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Commit | Line | Data |
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c0c050c5 MC |
1 | /* Broadcom NetXtreme-C/E network driver. |
2 | * | |
11f15ed3 | 3 | * Copyright (c) 2014-2016 Broadcom Corporation |
c6cc32a2 | 4 | * Copyright (c) 2016-2019 Broadcom Limited |
c0c050c5 MC |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | ||
13 | #include <linux/stringify.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/timer.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/vmalloc.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/etherdevice.h> | |
24 | #include <linux/skbuff.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/bitops.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/delay.h> | |
30 | #include <asm/byteorder.h> | |
31 | #include <asm/page.h> | |
32 | #include <linux/time.h> | |
33 | #include <linux/mii.h> | |
0ca12be9 | 34 | #include <linux/mdio.h> |
c0c050c5 MC |
35 | #include <linux/if.h> |
36 | #include <linux/if_vlan.h> | |
32e8239c | 37 | #include <linux/if_bridge.h> |
5ac67d8b | 38 | #include <linux/rtc.h> |
c6d30e83 | 39 | #include <linux/bpf.h> |
c0c050c5 MC |
40 | #include <net/ip.h> |
41 | #include <net/tcp.h> | |
42 | #include <net/udp.h> | |
43 | #include <net/checksum.h> | |
44 | #include <net/ip6_checksum.h> | |
ad51b8e9 | 45 | #include <net/udp_tunnel.h> |
c0c050c5 MC |
46 | #include <linux/workqueue.h> |
47 | #include <linux/prefetch.h> | |
48 | #include <linux/cache.h> | |
49 | #include <linux/log2.h> | |
50 | #include <linux/aer.h> | |
51 | #include <linux/bitmap.h> | |
52 | #include <linux/cpu_rmap.h> | |
56f0fd80 | 53 | #include <linux/cpumask.h> |
2ae7408f | 54 | #include <net/pkt_cls.h> |
cde49a42 VV |
55 | #include <linux/hwmon.h> |
56 | #include <linux/hwmon-sysfs.h> | |
322b87ca | 57 | #include <net/page_pool.h> |
c0c050c5 MC |
58 | |
59 | #include "bnxt_hsi.h" | |
60 | #include "bnxt.h" | |
a588e458 | 61 | #include "bnxt_ulp.h" |
c0c050c5 MC |
62 | #include "bnxt_sriov.h" |
63 | #include "bnxt_ethtool.h" | |
7df4ae9f | 64 | #include "bnxt_dcb.h" |
c6d30e83 | 65 | #include "bnxt_xdp.h" |
4ab0c6a8 | 66 | #include "bnxt_vfr.h" |
2ae7408f | 67 | #include "bnxt_tc.h" |
3c467bf3 | 68 | #include "bnxt_devlink.h" |
cabfb09d | 69 | #include "bnxt_debugfs.h" |
c0c050c5 MC |
70 | |
71 | #define BNXT_TX_TIMEOUT (5 * HZ) | |
72 | ||
73 | static const char version[] = | |
74 | "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; | |
75 | ||
76 | MODULE_LICENSE("GPL"); | |
77 | MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); | |
78 | MODULE_VERSION(DRV_MODULE_VERSION); | |
79 | ||
80 | #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) | |
81 | #define BNXT_RX_DMA_OFFSET NET_SKB_PAD | |
82 | #define BNXT_RX_COPY_THRESH 256 | |
83 | ||
4419dbe6 | 84 | #define BNXT_TX_PUSH_THRESH 164 |
c0c050c5 MC |
85 | |
86 | enum board_idx { | |
fbc9a523 | 87 | BCM57301, |
c0c050c5 MC |
88 | BCM57302, |
89 | BCM57304, | |
1f681688 | 90 | BCM57417_NPAR, |
fa853dda | 91 | BCM58700, |
b24eb6ae MC |
92 | BCM57311, |
93 | BCM57312, | |
fbc9a523 | 94 | BCM57402, |
c0c050c5 MC |
95 | BCM57404, |
96 | BCM57406, | |
1f681688 MC |
97 | BCM57402_NPAR, |
98 | BCM57407, | |
b24eb6ae MC |
99 | BCM57412, |
100 | BCM57414, | |
101 | BCM57416, | |
102 | BCM57417, | |
1f681688 | 103 | BCM57412_NPAR, |
5049e33b | 104 | BCM57314, |
1f681688 MC |
105 | BCM57417_SFP, |
106 | BCM57416_SFP, | |
107 | BCM57404_NPAR, | |
108 | BCM57406_NPAR, | |
109 | BCM57407_SFP, | |
adbc8305 | 110 | BCM57407_NPAR, |
1f681688 MC |
111 | BCM57414_NPAR, |
112 | BCM57416_NPAR, | |
32b40798 DK |
113 | BCM57452, |
114 | BCM57454, | |
92abef36 | 115 | BCM5745x_NPAR, |
1ab968d2 | 116 | BCM57508, |
c6cc32a2 | 117 | BCM57504, |
51fec80d | 118 | BCM57502, |
49c98421 MC |
119 | BCM57508_NPAR, |
120 | BCM57504_NPAR, | |
121 | BCM57502_NPAR, | |
4a58139b | 122 | BCM58802, |
8ed693b7 | 123 | BCM58804, |
4a58139b | 124 | BCM58808, |
adbc8305 MC |
125 | NETXTREME_E_VF, |
126 | NETXTREME_C_VF, | |
618784e3 | 127 | NETXTREME_S_VF, |
b16b6891 | 128 | NETXTREME_E_P5_VF, |
c0c050c5 MC |
129 | }; |
130 | ||
131 | /* indexed by enum above */ | |
132 | static const struct { | |
133 | char *name; | |
134 | } board_info[] = { | |
27573a7d SB |
135 | [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, |
136 | [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, | |
137 | [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
138 | [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, | |
139 | [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, | |
140 | [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, | |
141 | [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, | |
142 | [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, | |
143 | [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
144 | [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, | |
145 | [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, | |
146 | [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, | |
147 | [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, | |
148 | [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
149 | [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, | |
150 | [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, | |
151 | [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, | |
152 | [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
153 | [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, | |
154 | [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, | |
155 | [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, | |
156 | [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, | |
157 | [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, | |
158 | [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, | |
159 | [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, | |
160 | [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, | |
161 | [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
162 | [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, | |
92abef36 | 163 | [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, |
1ab968d2 | 164 | [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, |
c6cc32a2 | 165 | [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, |
51fec80d | 166 | [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, |
49c98421 MC |
167 | [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, |
168 | [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, | |
169 | [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, | |
27573a7d | 170 | [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, |
8ed693b7 | 171 | [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, |
27573a7d SB |
172 | [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, |
173 | [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, | |
174 | [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, | |
618784e3 | 175 | [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, |
b16b6891 | 176 | [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, |
c0c050c5 MC |
177 | }; |
178 | ||
179 | static const struct pci_device_id bnxt_pci_tbl[] = { | |
92abef36 VV |
180 | { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, |
181 | { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, | |
4a58139b | 182 | { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, |
adbc8305 | 183 | { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, |
fbc9a523 | 184 | { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, |
c0c050c5 MC |
185 | { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, |
186 | { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, | |
1f681688 | 187 | { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, |
fa853dda | 188 | { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, |
b24eb6ae MC |
189 | { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, |
190 | { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, | |
fbc9a523 | 191 | { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, |
c0c050c5 MC |
192 | { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, |
193 | { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, | |
1f681688 MC |
194 | { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, |
195 | { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, | |
b24eb6ae MC |
196 | { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, |
197 | { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, | |
198 | { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, | |
199 | { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, | |
1f681688 | 200 | { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, |
5049e33b | 201 | { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, |
1f681688 MC |
202 | { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, |
203 | { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, | |
204 | { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, | |
205 | { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, | |
206 | { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, | |
adbc8305 MC |
207 | { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, |
208 | { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, | |
1f681688 | 209 | { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, |
adbc8305 | 210 | { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, |
1f681688 | 211 | { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, |
adbc8305 | 212 | { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, |
4a58139b | 213 | { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, |
32b40798 | 214 | { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, |
1ab968d2 | 215 | { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, |
c6cc32a2 | 216 | { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, |
51fec80d | 217 | { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, |
49c98421 MC |
218 | { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR }, |
219 | { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, | |
220 | { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR }, | |
221 | { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR }, | |
222 | { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, | |
223 | { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR }, | |
4a58139b | 224 | { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, |
8ed693b7 | 225 | { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, |
c0c050c5 | 226 | #ifdef CONFIG_BNXT_SRIOV |
c7ef35eb DK |
227 | { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, |
228 | { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, | |
adbc8305 MC |
229 | { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, |
230 | { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, | |
231 | { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, | |
232 | { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, | |
233 | { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, | |
234 | { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, | |
51fec80d | 235 | { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, |
b16b6891 | 236 | { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, |
618784e3 | 237 | { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, |
c0c050c5 MC |
238 | #endif |
239 | { 0 } | |
240 | }; | |
241 | ||
242 | MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); | |
243 | ||
244 | static const u16 bnxt_vf_req_snif[] = { | |
245 | HWRM_FUNC_CFG, | |
91cdda40 | 246 | HWRM_FUNC_VF_CFG, |
c0c050c5 MC |
247 | HWRM_PORT_PHY_QCFG, |
248 | HWRM_CFA_L2_FILTER_ALLOC, | |
249 | }; | |
250 | ||
25be8623 | 251 | static const u16 bnxt_async_events_arr[] = { |
87c374de MC |
252 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, |
253 | ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, | |
254 | ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, | |
255 | ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, | |
256 | ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, | |
2151fe08 | 257 | ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, |
7e914027 | 258 | ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, |
25be8623 MC |
259 | }; |
260 | ||
c213eae8 MC |
261 | static struct workqueue_struct *bnxt_pf_wq; |
262 | ||
c0c050c5 MC |
263 | static bool bnxt_vf_pciid(enum board_idx idx) |
264 | { | |
618784e3 | 265 | return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || |
b16b6891 | 266 | idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); |
c0c050c5 MC |
267 | } |
268 | ||
269 | #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) | |
270 | #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) | |
271 | #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) | |
272 | ||
c0c050c5 MC |
273 | #define BNXT_CP_DB_IRQ_DIS(db) \ |
274 | writel(DB_CP_IRQ_DIS_FLAGS, db) | |
275 | ||
697197e5 MC |
276 | #define BNXT_DB_CQ(db, idx) \ |
277 | writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) | |
278 | ||
279 | #define BNXT_DB_NQ_P5(db, idx) \ | |
280 | writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) | |
281 | ||
282 | #define BNXT_DB_CQ_ARM(db, idx) \ | |
283 | writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) | |
284 | ||
285 | #define BNXT_DB_NQ_ARM_P5(db, idx) \ | |
286 | writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) | |
287 | ||
288 | static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
289 | { | |
290 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
291 | BNXT_DB_NQ_P5(db, idx); | |
292 | else | |
293 | BNXT_DB_CQ(db, idx); | |
294 | } | |
295 | ||
296 | static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
297 | { | |
298 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
299 | BNXT_DB_NQ_ARM_P5(db, idx); | |
300 | else | |
301 | BNXT_DB_CQ_ARM(db, idx); | |
302 | } | |
303 | ||
304 | static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) | |
305 | { | |
306 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
307 | writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), | |
308 | db->doorbell); | |
309 | else | |
310 | BNXT_DB_CQ(db, idx); | |
311 | } | |
312 | ||
38413406 | 313 | const u16 bnxt_lhint_arr[] = { |
c0c050c5 MC |
314 | TX_BD_FLAGS_LHINT_512_AND_SMALLER, |
315 | TX_BD_FLAGS_LHINT_512_TO_1023, | |
316 | TX_BD_FLAGS_LHINT_1024_TO_2047, | |
317 | TX_BD_FLAGS_LHINT_1024_TO_2047, | |
318 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
319 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
320 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
321 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
322 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
323 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
324 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
325 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
326 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
327 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
328 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
329 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
330 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
331 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
332 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, | |
333 | }; | |
334 | ||
ee5c7fb3 SP |
335 | static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) |
336 | { | |
337 | struct metadata_dst *md_dst = skb_metadata_dst(skb); | |
338 | ||
339 | if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) | |
340 | return 0; | |
341 | ||
342 | return md_dst->u.port_info.port_id; | |
343 | } | |
344 | ||
c0c050c5 MC |
345 | static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) |
346 | { | |
347 | struct bnxt *bp = netdev_priv(dev); | |
348 | struct tx_bd *txbd; | |
349 | struct tx_bd_ext *txbd1; | |
350 | struct netdev_queue *txq; | |
351 | int i; | |
352 | dma_addr_t mapping; | |
353 | unsigned int length, pad = 0; | |
354 | u32 len, free_size, vlan_tag_flags, cfa_action, flags; | |
355 | u16 prod, last_frag; | |
356 | struct pci_dev *pdev = bp->pdev; | |
c0c050c5 MC |
357 | struct bnxt_tx_ring_info *txr; |
358 | struct bnxt_sw_tx_bd *tx_buf; | |
359 | ||
360 | i = skb_get_queue_mapping(skb); | |
361 | if (unlikely(i >= bp->tx_nr_rings)) { | |
362 | dev_kfree_skb_any(skb); | |
363 | return NETDEV_TX_OK; | |
364 | } | |
365 | ||
c0c050c5 | 366 | txq = netdev_get_tx_queue(dev, i); |
a960dec9 | 367 | txr = &bp->tx_ring[bp->tx_ring_map[i]]; |
c0c050c5 MC |
368 | prod = txr->tx_prod; |
369 | ||
370 | free_size = bnxt_tx_avail(bp, txr); | |
371 | if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { | |
372 | netif_tx_stop_queue(txq); | |
373 | return NETDEV_TX_BUSY; | |
374 | } | |
375 | ||
376 | length = skb->len; | |
377 | len = skb_headlen(skb); | |
378 | last_frag = skb_shinfo(skb)->nr_frags; | |
379 | ||
380 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
381 | ||
382 | txbd->tx_bd_opaque = prod; | |
383 | ||
384 | tx_buf = &txr->tx_buf_ring[prod]; | |
385 | tx_buf->skb = skb; | |
386 | tx_buf->nr_frags = last_frag; | |
387 | ||
388 | vlan_tag_flags = 0; | |
ee5c7fb3 | 389 | cfa_action = bnxt_xmit_get_cfa_action(skb); |
c0c050c5 MC |
390 | if (skb_vlan_tag_present(skb)) { |
391 | vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | | |
392 | skb_vlan_tag_get(skb); | |
393 | /* Currently supports 8021Q, 8021AD vlan offloads | |
394 | * QINQ1, QINQ2, QINQ3 vlan headers are deprecated | |
395 | */ | |
396 | if (skb->vlan_proto == htons(ETH_P_8021Q)) | |
397 | vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; | |
398 | } | |
399 | ||
400 | if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { | |
4419dbe6 MC |
401 | struct tx_push_buffer *tx_push_buf = txr->tx_push; |
402 | struct tx_push_bd *tx_push = &tx_push_buf->push_bd; | |
403 | struct tx_bd_ext *tx_push1 = &tx_push->txbd2; | |
697197e5 | 404 | void __iomem *db = txr->tx_db.doorbell; |
4419dbe6 MC |
405 | void *pdata = tx_push_buf->data; |
406 | u64 *end; | |
407 | int j, push_len; | |
c0c050c5 MC |
408 | |
409 | /* Set COAL_NOW to be ready quickly for the next push */ | |
410 | tx_push->tx_bd_len_flags_type = | |
411 | cpu_to_le32((length << TX_BD_LEN_SHIFT) | | |
412 | TX_BD_TYPE_LONG_TX_BD | | |
413 | TX_BD_FLAGS_LHINT_512_AND_SMALLER | | |
414 | TX_BD_FLAGS_COAL_NOW | | |
415 | TX_BD_FLAGS_PACKET_END | | |
416 | (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); | |
417 | ||
418 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
419 | tx_push1->tx_bd_hsize_lflags = | |
420 | cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); | |
421 | else | |
422 | tx_push1->tx_bd_hsize_lflags = 0; | |
423 | ||
424 | tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); | |
ee5c7fb3 SP |
425 | tx_push1->tx_bd_cfa_action = |
426 | cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); | |
c0c050c5 | 427 | |
fbb0fa8b MC |
428 | end = pdata + length; |
429 | end = PTR_ALIGN(end, 8) - 1; | |
4419dbe6 MC |
430 | *end = 0; |
431 | ||
c0c050c5 MC |
432 | skb_copy_from_linear_data(skb, pdata, len); |
433 | pdata += len; | |
434 | for (j = 0; j < last_frag; j++) { | |
435 | skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; | |
436 | void *fptr; | |
437 | ||
438 | fptr = skb_frag_address_safe(frag); | |
439 | if (!fptr) | |
440 | goto normal_tx; | |
441 | ||
442 | memcpy(pdata, fptr, skb_frag_size(frag)); | |
443 | pdata += skb_frag_size(frag); | |
444 | } | |
445 | ||
4419dbe6 MC |
446 | txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; |
447 | txbd->tx_bd_haddr = txr->data_mapping; | |
c0c050c5 MC |
448 | prod = NEXT_TX(prod); |
449 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
450 | memcpy(txbd, tx_push1, sizeof(*txbd)); | |
451 | prod = NEXT_TX(prod); | |
4419dbe6 | 452 | tx_push->doorbell = |
c0c050c5 MC |
453 | cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); |
454 | txr->tx_prod = prod; | |
455 | ||
b9a8460a | 456 | tx_buf->is_push = 1; |
c0c050c5 | 457 | netdev_tx_sent_queue(txq, skb->len); |
b9a8460a | 458 | wmb(); /* Sync is_push and byte queue before pushing data */ |
c0c050c5 | 459 | |
4419dbe6 MC |
460 | push_len = (length + sizeof(*tx_push) + 7) / 8; |
461 | if (push_len > 16) { | |
697197e5 MC |
462 | __iowrite64_copy(db, tx_push_buf, 16); |
463 | __iowrite32_copy(db + 4, tx_push_buf + 1, | |
9d13744b | 464 | (push_len - 16) << 1); |
4419dbe6 | 465 | } else { |
697197e5 | 466 | __iowrite64_copy(db, tx_push_buf, push_len); |
4419dbe6 | 467 | } |
c0c050c5 | 468 | |
c0c050c5 MC |
469 | goto tx_done; |
470 | } | |
471 | ||
472 | normal_tx: | |
473 | if (length < BNXT_MIN_PKT_SIZE) { | |
474 | pad = BNXT_MIN_PKT_SIZE - length; | |
475 | if (skb_pad(skb, pad)) { | |
476 | /* SKB already freed. */ | |
477 | tx_buf->skb = NULL; | |
478 | return NETDEV_TX_OK; | |
479 | } | |
480 | length = BNXT_MIN_PKT_SIZE; | |
481 | } | |
482 | ||
483 | mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); | |
484 | ||
485 | if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { | |
486 | dev_kfree_skb_any(skb); | |
487 | tx_buf->skb = NULL; | |
488 | return NETDEV_TX_OK; | |
489 | } | |
490 | ||
491 | dma_unmap_addr_set(tx_buf, mapping, mapping); | |
492 | flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | | |
493 | ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); | |
494 | ||
495 | txbd->tx_bd_haddr = cpu_to_le64(mapping); | |
496 | ||
497 | prod = NEXT_TX(prod); | |
498 | txbd1 = (struct tx_bd_ext *) | |
499 | &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
500 | ||
501 | txbd1->tx_bd_hsize_lflags = 0; | |
502 | if (skb_is_gso(skb)) { | |
503 | u32 hdr_len; | |
504 | ||
505 | if (skb->encapsulation) | |
506 | hdr_len = skb_inner_network_offset(skb) + | |
507 | skb_inner_network_header_len(skb) + | |
508 | inner_tcp_hdrlen(skb); | |
509 | else | |
510 | hdr_len = skb_transport_offset(skb) + | |
511 | tcp_hdrlen(skb); | |
512 | ||
513 | txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | | |
514 | TX_BD_FLAGS_T_IPID | | |
515 | (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); | |
516 | length = skb_shinfo(skb)->gso_size; | |
517 | txbd1->tx_bd_mss = cpu_to_le32(length); | |
518 | length += hdr_len; | |
519 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
520 | txbd1->tx_bd_hsize_lflags = | |
521 | cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); | |
522 | txbd1->tx_bd_mss = 0; | |
523 | } | |
524 | ||
525 | length >>= 9; | |
2b3c6885 MC |
526 | if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { |
527 | dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", | |
528 | skb->len); | |
529 | i = 0; | |
530 | goto tx_dma_error; | |
531 | } | |
c0c050c5 MC |
532 | flags |= bnxt_lhint_arr[length]; |
533 | txbd->tx_bd_len_flags_type = cpu_to_le32(flags); | |
534 | ||
535 | txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); | |
ee5c7fb3 SP |
536 | txbd1->tx_bd_cfa_action = |
537 | cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); | |
c0c050c5 MC |
538 | for (i = 0; i < last_frag; i++) { |
539 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
540 | ||
541 | prod = NEXT_TX(prod); | |
542 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; | |
543 | ||
544 | len = skb_frag_size(frag); | |
545 | mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, | |
546 | DMA_TO_DEVICE); | |
547 | ||
548 | if (unlikely(dma_mapping_error(&pdev->dev, mapping))) | |
549 | goto tx_dma_error; | |
550 | ||
551 | tx_buf = &txr->tx_buf_ring[prod]; | |
552 | dma_unmap_addr_set(tx_buf, mapping, mapping); | |
553 | ||
554 | txbd->tx_bd_haddr = cpu_to_le64(mapping); | |
555 | ||
556 | flags = len << TX_BD_LEN_SHIFT; | |
557 | txbd->tx_bd_len_flags_type = cpu_to_le32(flags); | |
558 | } | |
559 | ||
560 | flags &= ~TX_BD_LEN; | |
561 | txbd->tx_bd_len_flags_type = | |
562 | cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | | |
563 | TX_BD_FLAGS_PACKET_END); | |
564 | ||
565 | netdev_tx_sent_queue(txq, skb->len); | |
566 | ||
567 | /* Sync BD data before updating doorbell */ | |
568 | wmb(); | |
569 | ||
570 | prod = NEXT_TX(prod); | |
571 | txr->tx_prod = prod; | |
572 | ||
6b16f9ee | 573 | if (!netdev_xmit_more() || netif_xmit_stopped(txq)) |
697197e5 | 574 | bnxt_db_write(bp, &txr->tx_db, prod); |
c0c050c5 MC |
575 | |
576 | tx_done: | |
577 | ||
c0c050c5 | 578 | if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { |
6b16f9ee | 579 | if (netdev_xmit_more() && !tx_buf->is_push) |
697197e5 | 580 | bnxt_db_write(bp, &txr->tx_db, prod); |
4d172f21 | 581 | |
c0c050c5 MC |
582 | netif_tx_stop_queue(txq); |
583 | ||
584 | /* netif_tx_stop_queue() must be done before checking | |
585 | * tx index in bnxt_tx_avail() below, because in | |
586 | * bnxt_tx_int(), we update tx index before checking for | |
587 | * netif_tx_queue_stopped(). | |
588 | */ | |
589 | smp_mb(); | |
590 | if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) | |
591 | netif_tx_wake_queue(txq); | |
592 | } | |
593 | return NETDEV_TX_OK; | |
594 | ||
595 | tx_dma_error: | |
596 | last_frag = i; | |
597 | ||
598 | /* start back at beginning and unmap skb */ | |
599 | prod = txr->tx_prod; | |
600 | tx_buf = &txr->tx_buf_ring[prod]; | |
601 | tx_buf->skb = NULL; | |
602 | dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
603 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
604 | prod = NEXT_TX(prod); | |
605 | ||
606 | /* unmap remaining mapped pages */ | |
607 | for (i = 0; i < last_frag; i++) { | |
608 | prod = NEXT_TX(prod); | |
609 | tx_buf = &txr->tx_buf_ring[prod]; | |
610 | dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
611 | skb_frag_size(&skb_shinfo(skb)->frags[i]), | |
612 | PCI_DMA_TODEVICE); | |
613 | } | |
614 | ||
615 | dev_kfree_skb_any(skb); | |
616 | return NETDEV_TX_OK; | |
617 | } | |
618 | ||
619 | static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) | |
620 | { | |
b6ab4b01 | 621 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; |
a960dec9 | 622 | struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); |
c0c050c5 MC |
623 | u16 cons = txr->tx_cons; |
624 | struct pci_dev *pdev = bp->pdev; | |
625 | int i; | |
626 | unsigned int tx_bytes = 0; | |
627 | ||
628 | for (i = 0; i < nr_pkts; i++) { | |
629 | struct bnxt_sw_tx_bd *tx_buf; | |
630 | struct sk_buff *skb; | |
631 | int j, last; | |
632 | ||
633 | tx_buf = &txr->tx_buf_ring[cons]; | |
634 | cons = NEXT_TX(cons); | |
635 | skb = tx_buf->skb; | |
636 | tx_buf->skb = NULL; | |
637 | ||
638 | if (tx_buf->is_push) { | |
639 | tx_buf->is_push = 0; | |
640 | goto next_tx_int; | |
641 | } | |
642 | ||
643 | dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), | |
644 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
645 | last = tx_buf->nr_frags; | |
646 | ||
647 | for (j = 0; j < last; j++) { | |
648 | cons = NEXT_TX(cons); | |
649 | tx_buf = &txr->tx_buf_ring[cons]; | |
650 | dma_unmap_page( | |
651 | &pdev->dev, | |
652 | dma_unmap_addr(tx_buf, mapping), | |
653 | skb_frag_size(&skb_shinfo(skb)->frags[j]), | |
654 | PCI_DMA_TODEVICE); | |
655 | } | |
656 | ||
657 | next_tx_int: | |
658 | cons = NEXT_TX(cons); | |
659 | ||
660 | tx_bytes += skb->len; | |
661 | dev_kfree_skb_any(skb); | |
662 | } | |
663 | ||
664 | netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); | |
665 | txr->tx_cons = cons; | |
666 | ||
667 | /* Need to make the tx_cons update visible to bnxt_start_xmit() | |
668 | * before checking for netif_tx_queue_stopped(). Without the | |
669 | * memory barrier, there is a small possibility that bnxt_start_xmit() | |
670 | * will miss it and cause the queue to be stopped forever. | |
671 | */ | |
672 | smp_mb(); | |
673 | ||
674 | if (unlikely(netif_tx_queue_stopped(txq)) && | |
675 | (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { | |
676 | __netif_tx_lock(txq, smp_processor_id()); | |
677 | if (netif_tx_queue_stopped(txq) && | |
678 | bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && | |
679 | txr->dev_state != BNXT_DEV_STATE_CLOSING) | |
680 | netif_tx_wake_queue(txq); | |
681 | __netif_tx_unlock(txq); | |
682 | } | |
683 | } | |
684 | ||
c61fb99c | 685 | static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, |
322b87ca | 686 | struct bnxt_rx_ring_info *rxr, |
c61fb99c MC |
687 | gfp_t gfp) |
688 | { | |
689 | struct device *dev = &bp->pdev->dev; | |
690 | struct page *page; | |
691 | ||
322b87ca | 692 | page = page_pool_dev_alloc_pages(rxr->page_pool); |
c61fb99c MC |
693 | if (!page) |
694 | return NULL; | |
695 | ||
c519fe9a SN |
696 | *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, |
697 | DMA_ATTR_WEAK_ORDERING); | |
c61fb99c | 698 | if (dma_mapping_error(dev, *mapping)) { |
322b87ca | 699 | page_pool_recycle_direct(rxr->page_pool, page); |
c61fb99c MC |
700 | return NULL; |
701 | } | |
702 | *mapping += bp->rx_dma_offset; | |
703 | return page; | |
704 | } | |
705 | ||
c0c050c5 MC |
706 | static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, |
707 | gfp_t gfp) | |
708 | { | |
709 | u8 *data; | |
710 | struct pci_dev *pdev = bp->pdev; | |
711 | ||
712 | data = kmalloc(bp->rx_buf_size, gfp); | |
713 | if (!data) | |
714 | return NULL; | |
715 | ||
c519fe9a SN |
716 | *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, |
717 | bp->rx_buf_use_size, bp->rx_dir, | |
718 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
719 | |
720 | if (dma_mapping_error(&pdev->dev, *mapping)) { | |
721 | kfree(data); | |
722 | data = NULL; | |
723 | } | |
724 | return data; | |
725 | } | |
726 | ||
38413406 MC |
727 | int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
728 | u16 prod, gfp_t gfp) | |
c0c050c5 MC |
729 | { |
730 | struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
731 | struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; | |
c0c050c5 MC |
732 | dma_addr_t mapping; |
733 | ||
c61fb99c | 734 | if (BNXT_RX_PAGE_MODE(bp)) { |
322b87ca AG |
735 | struct page *page = |
736 | __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); | |
c0c050c5 | 737 | |
c61fb99c MC |
738 | if (!page) |
739 | return -ENOMEM; | |
740 | ||
741 | rx_buf->data = page; | |
742 | rx_buf->data_ptr = page_address(page) + bp->rx_offset; | |
743 | } else { | |
744 | u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); | |
745 | ||
746 | if (!data) | |
747 | return -ENOMEM; | |
748 | ||
749 | rx_buf->data = data; | |
750 | rx_buf->data_ptr = data + bp->rx_offset; | |
751 | } | |
11cd119d | 752 | rx_buf->mapping = mapping; |
c0c050c5 MC |
753 | |
754 | rxbd->rx_bd_haddr = cpu_to_le64(mapping); | |
c0c050c5 MC |
755 | return 0; |
756 | } | |
757 | ||
c6d30e83 | 758 | void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) |
c0c050c5 MC |
759 | { |
760 | u16 prod = rxr->rx_prod; | |
761 | struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; | |
762 | struct rx_bd *cons_bd, *prod_bd; | |
763 | ||
764 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
765 | cons_rx_buf = &rxr->rx_buf_ring[cons]; | |
766 | ||
767 | prod_rx_buf->data = data; | |
6bb19474 | 768 | prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; |
c0c050c5 | 769 | |
11cd119d | 770 | prod_rx_buf->mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
771 | |
772 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
773 | cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; | |
774 | ||
775 | prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; | |
776 | } | |
777 | ||
778 | static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) | |
779 | { | |
780 | u16 next, max = rxr->rx_agg_bmap_size; | |
781 | ||
782 | next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); | |
783 | if (next >= max) | |
784 | next = find_first_zero_bit(rxr->rx_agg_bmap, max); | |
785 | return next; | |
786 | } | |
787 | ||
788 | static inline int bnxt_alloc_rx_page(struct bnxt *bp, | |
789 | struct bnxt_rx_ring_info *rxr, | |
790 | u16 prod, gfp_t gfp) | |
791 | { | |
792 | struct rx_bd *rxbd = | |
793 | &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
794 | struct bnxt_sw_rx_agg_bd *rx_agg_buf; | |
795 | struct pci_dev *pdev = bp->pdev; | |
796 | struct page *page; | |
797 | dma_addr_t mapping; | |
798 | u16 sw_prod = rxr->rx_sw_agg_prod; | |
89d0a06c | 799 | unsigned int offset = 0; |
c0c050c5 | 800 | |
89d0a06c MC |
801 | if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { |
802 | page = rxr->rx_page; | |
803 | if (!page) { | |
804 | page = alloc_page(gfp); | |
805 | if (!page) | |
806 | return -ENOMEM; | |
807 | rxr->rx_page = page; | |
808 | rxr->rx_page_offset = 0; | |
809 | } | |
810 | offset = rxr->rx_page_offset; | |
811 | rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; | |
812 | if (rxr->rx_page_offset == PAGE_SIZE) | |
813 | rxr->rx_page = NULL; | |
814 | else | |
815 | get_page(page); | |
816 | } else { | |
817 | page = alloc_page(gfp); | |
818 | if (!page) | |
819 | return -ENOMEM; | |
820 | } | |
c0c050c5 | 821 | |
c519fe9a SN |
822 | mapping = dma_map_page_attrs(&pdev->dev, page, offset, |
823 | BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, | |
824 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
825 | if (dma_mapping_error(&pdev->dev, mapping)) { |
826 | __free_page(page); | |
827 | return -EIO; | |
828 | } | |
829 | ||
830 | if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) | |
831 | sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); | |
832 | ||
833 | __set_bit(sw_prod, rxr->rx_agg_bmap); | |
834 | rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; | |
835 | rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); | |
836 | ||
837 | rx_agg_buf->page = page; | |
89d0a06c | 838 | rx_agg_buf->offset = offset; |
c0c050c5 MC |
839 | rx_agg_buf->mapping = mapping; |
840 | rxbd->rx_bd_haddr = cpu_to_le64(mapping); | |
841 | rxbd->rx_bd_opaque = sw_prod; | |
842 | return 0; | |
843 | } | |
844 | ||
4a228a3a MC |
845 | static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, |
846 | struct bnxt_cp_ring_info *cpr, | |
847 | u16 cp_cons, u16 curr) | |
848 | { | |
849 | struct rx_agg_cmp *agg; | |
850 | ||
851 | cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); | |
852 | agg = (struct rx_agg_cmp *) | |
853 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
854 | return agg; | |
855 | } | |
856 | ||
bfcd8d79 MC |
857 | static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, |
858 | struct bnxt_rx_ring_info *rxr, | |
859 | u16 agg_id, u16 curr) | |
860 | { | |
861 | struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; | |
862 | ||
863 | return &tpa_info->agg_arr[curr]; | |
864 | } | |
865 | ||
4a228a3a MC |
866 | static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, |
867 | u16 start, u32 agg_bufs, bool tpa) | |
c0c050c5 | 868 | { |
e44758b7 | 869 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 | 870 | struct bnxt *bp = bnapi->bp; |
b6ab4b01 | 871 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 MC |
872 | u16 prod = rxr->rx_agg_prod; |
873 | u16 sw_prod = rxr->rx_sw_agg_prod; | |
bfcd8d79 | 874 | bool p5_tpa = false; |
c0c050c5 MC |
875 | u32 i; |
876 | ||
bfcd8d79 MC |
877 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) |
878 | p5_tpa = true; | |
879 | ||
c0c050c5 MC |
880 | for (i = 0; i < agg_bufs; i++) { |
881 | u16 cons; | |
882 | struct rx_agg_cmp *agg; | |
883 | struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; | |
884 | struct rx_bd *prod_bd; | |
885 | struct page *page; | |
886 | ||
bfcd8d79 MC |
887 | if (p5_tpa) |
888 | agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); | |
889 | else | |
890 | agg = bnxt_get_agg(bp, cpr, idx, start + i); | |
c0c050c5 MC |
891 | cons = agg->rx_agg_cmp_opaque; |
892 | __clear_bit(cons, rxr->rx_agg_bmap); | |
893 | ||
894 | if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) | |
895 | sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); | |
896 | ||
897 | __set_bit(sw_prod, rxr->rx_agg_bmap); | |
898 | prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; | |
899 | cons_rx_buf = &rxr->rx_agg_ring[cons]; | |
900 | ||
901 | /* It is possible for sw_prod to be equal to cons, so | |
902 | * set cons_rx_buf->page to NULL first. | |
903 | */ | |
904 | page = cons_rx_buf->page; | |
905 | cons_rx_buf->page = NULL; | |
906 | prod_rx_buf->page = page; | |
89d0a06c | 907 | prod_rx_buf->offset = cons_rx_buf->offset; |
c0c050c5 MC |
908 | |
909 | prod_rx_buf->mapping = cons_rx_buf->mapping; | |
910 | ||
911 | prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
912 | ||
913 | prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); | |
914 | prod_bd->rx_bd_opaque = sw_prod; | |
915 | ||
916 | prod = NEXT_RX_AGG(prod); | |
917 | sw_prod = NEXT_RX_AGG(sw_prod); | |
c0c050c5 MC |
918 | } |
919 | rxr->rx_agg_prod = prod; | |
920 | rxr->rx_sw_agg_prod = sw_prod; | |
921 | } | |
922 | ||
c61fb99c MC |
923 | static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, |
924 | struct bnxt_rx_ring_info *rxr, | |
925 | u16 cons, void *data, u8 *data_ptr, | |
926 | dma_addr_t dma_addr, | |
927 | unsigned int offset_and_len) | |
928 | { | |
929 | unsigned int payload = offset_and_len >> 16; | |
930 | unsigned int len = offset_and_len & 0xffff; | |
d7840976 | 931 | skb_frag_t *frag; |
c61fb99c MC |
932 | struct page *page = data; |
933 | u16 prod = rxr->rx_prod; | |
934 | struct sk_buff *skb; | |
935 | int off, err; | |
936 | ||
937 | err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); | |
938 | if (unlikely(err)) { | |
939 | bnxt_reuse_rx_data(rxr, cons, data); | |
940 | return NULL; | |
941 | } | |
942 | dma_addr -= bp->rx_dma_offset; | |
c519fe9a SN |
943 | dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, |
944 | DMA_ATTR_WEAK_ORDERING); | |
c61fb99c MC |
945 | |
946 | if (unlikely(!payload)) | |
c43f1255 | 947 | payload = eth_get_headlen(bp->dev, data_ptr, len); |
c61fb99c MC |
948 | |
949 | skb = napi_alloc_skb(&rxr->bnapi->napi, payload); | |
950 | if (!skb) { | |
951 | __free_page(page); | |
952 | return NULL; | |
953 | } | |
954 | ||
955 | off = (void *)data_ptr - page_address(page); | |
956 | skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); | |
957 | memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, | |
958 | payload + NET_IP_ALIGN); | |
959 | ||
960 | frag = &skb_shinfo(skb)->frags[0]; | |
961 | skb_frag_size_sub(frag, payload); | |
b54c9d5b | 962 | skb_frag_off_add(frag, payload); |
c61fb99c MC |
963 | skb->data_len -= payload; |
964 | skb->tail += payload; | |
965 | ||
966 | return skb; | |
967 | } | |
968 | ||
c0c050c5 MC |
969 | static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, |
970 | struct bnxt_rx_ring_info *rxr, u16 cons, | |
6bb19474 MC |
971 | void *data, u8 *data_ptr, |
972 | dma_addr_t dma_addr, | |
973 | unsigned int offset_and_len) | |
c0c050c5 | 974 | { |
6bb19474 | 975 | u16 prod = rxr->rx_prod; |
c0c050c5 | 976 | struct sk_buff *skb; |
6bb19474 | 977 | int err; |
c0c050c5 MC |
978 | |
979 | err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); | |
980 | if (unlikely(err)) { | |
981 | bnxt_reuse_rx_data(rxr, cons, data); | |
982 | return NULL; | |
983 | } | |
984 | ||
985 | skb = build_skb(data, 0); | |
c519fe9a SN |
986 | dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, |
987 | bp->rx_dir, DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
988 | if (!skb) { |
989 | kfree(data); | |
990 | return NULL; | |
991 | } | |
992 | ||
b3dba77c | 993 | skb_reserve(skb, bp->rx_offset); |
6bb19474 | 994 | skb_put(skb, offset_and_len & 0xffff); |
c0c050c5 MC |
995 | return skb; |
996 | } | |
997 | ||
e44758b7 MC |
998 | static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, |
999 | struct bnxt_cp_ring_info *cpr, | |
4a228a3a MC |
1000 | struct sk_buff *skb, u16 idx, |
1001 | u32 agg_bufs, bool tpa) | |
c0c050c5 | 1002 | { |
e44758b7 | 1003 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 | 1004 | struct pci_dev *pdev = bp->pdev; |
b6ab4b01 | 1005 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 | 1006 | u16 prod = rxr->rx_agg_prod; |
bfcd8d79 | 1007 | bool p5_tpa = false; |
c0c050c5 MC |
1008 | u32 i; |
1009 | ||
bfcd8d79 MC |
1010 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) |
1011 | p5_tpa = true; | |
1012 | ||
c0c050c5 MC |
1013 | for (i = 0; i < agg_bufs; i++) { |
1014 | u16 cons, frag_len; | |
1015 | struct rx_agg_cmp *agg; | |
1016 | struct bnxt_sw_rx_agg_bd *cons_rx_buf; | |
1017 | struct page *page; | |
1018 | dma_addr_t mapping; | |
1019 | ||
bfcd8d79 MC |
1020 | if (p5_tpa) |
1021 | agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); | |
1022 | else | |
1023 | agg = bnxt_get_agg(bp, cpr, idx, i); | |
c0c050c5 MC |
1024 | cons = agg->rx_agg_cmp_opaque; |
1025 | frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & | |
1026 | RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; | |
1027 | ||
1028 | cons_rx_buf = &rxr->rx_agg_ring[cons]; | |
89d0a06c MC |
1029 | skb_fill_page_desc(skb, i, cons_rx_buf->page, |
1030 | cons_rx_buf->offset, frag_len); | |
c0c050c5 MC |
1031 | __clear_bit(cons, rxr->rx_agg_bmap); |
1032 | ||
1033 | /* It is possible for bnxt_alloc_rx_page() to allocate | |
1034 | * a sw_prod index that equals the cons index, so we | |
1035 | * need to clear the cons entry now. | |
1036 | */ | |
11cd119d | 1037 | mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
1038 | page = cons_rx_buf->page; |
1039 | cons_rx_buf->page = NULL; | |
1040 | ||
1041 | if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { | |
1042 | struct skb_shared_info *shinfo; | |
1043 | unsigned int nr_frags; | |
1044 | ||
1045 | shinfo = skb_shinfo(skb); | |
1046 | nr_frags = --shinfo->nr_frags; | |
1047 | __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); | |
1048 | ||
1049 | dev_kfree_skb(skb); | |
1050 | ||
1051 | cons_rx_buf->page = page; | |
1052 | ||
1053 | /* Update prod since possibly some pages have been | |
1054 | * allocated already. | |
1055 | */ | |
1056 | rxr->rx_agg_prod = prod; | |
4a228a3a | 1057 | bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); |
c0c050c5 MC |
1058 | return NULL; |
1059 | } | |
1060 | ||
c519fe9a SN |
1061 | dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, |
1062 | PCI_DMA_FROMDEVICE, | |
1063 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
1064 | |
1065 | skb->data_len += frag_len; | |
1066 | skb->len += frag_len; | |
1067 | skb->truesize += PAGE_SIZE; | |
1068 | ||
1069 | prod = NEXT_RX_AGG(prod); | |
c0c050c5 MC |
1070 | } |
1071 | rxr->rx_agg_prod = prod; | |
1072 | return skb; | |
1073 | } | |
1074 | ||
1075 | static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, | |
1076 | u8 agg_bufs, u32 *raw_cons) | |
1077 | { | |
1078 | u16 last; | |
1079 | struct rx_agg_cmp *agg; | |
1080 | ||
1081 | *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); | |
1082 | last = RING_CMP(*raw_cons); | |
1083 | agg = (struct rx_agg_cmp *) | |
1084 | &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; | |
1085 | return RX_AGG_CMP_VALID(agg, *raw_cons); | |
1086 | } | |
1087 | ||
1088 | static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, | |
1089 | unsigned int len, | |
1090 | dma_addr_t mapping) | |
1091 | { | |
1092 | struct bnxt *bp = bnapi->bp; | |
1093 | struct pci_dev *pdev = bp->pdev; | |
1094 | struct sk_buff *skb; | |
1095 | ||
1096 | skb = napi_alloc_skb(&bnapi->napi, len); | |
1097 | if (!skb) | |
1098 | return NULL; | |
1099 | ||
745fc05c MC |
1100 | dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, |
1101 | bp->rx_dir); | |
c0c050c5 | 1102 | |
6bb19474 MC |
1103 | memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, |
1104 | len + NET_IP_ALIGN); | |
c0c050c5 | 1105 | |
745fc05c MC |
1106 | dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, |
1107 | bp->rx_dir); | |
c0c050c5 MC |
1108 | |
1109 | skb_put(skb, len); | |
1110 | return skb; | |
1111 | } | |
1112 | ||
e44758b7 | 1113 | static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
fa7e2812 MC |
1114 | u32 *raw_cons, void *cmp) |
1115 | { | |
fa7e2812 MC |
1116 | struct rx_cmp *rxcmp = cmp; |
1117 | u32 tmp_raw_cons = *raw_cons; | |
1118 | u8 cmp_type, agg_bufs = 0; | |
1119 | ||
1120 | cmp_type = RX_CMP_TYPE(rxcmp); | |
1121 | ||
1122 | if (cmp_type == CMP_TYPE_RX_L2_CMP) { | |
1123 | agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & | |
1124 | RX_CMP_AGG_BUFS) >> | |
1125 | RX_CMP_AGG_BUFS_SHIFT; | |
1126 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
1127 | struct rx_tpa_end_cmp *tpa_end = cmp; | |
1128 | ||
bfcd8d79 MC |
1129 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
1130 | return 0; | |
1131 | ||
4a228a3a | 1132 | agg_bufs = TPA_END_AGG_BUFS(tpa_end); |
fa7e2812 MC |
1133 | } |
1134 | ||
1135 | if (agg_bufs) { | |
1136 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) | |
1137 | return -EBUSY; | |
1138 | } | |
1139 | *raw_cons = tmp_raw_cons; | |
1140 | return 0; | |
1141 | } | |
1142 | ||
230d1f0d MC |
1143 | static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) |
1144 | { | |
1145 | if (BNXT_PF(bp)) | |
1146 | queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); | |
1147 | else | |
1148 | schedule_delayed_work(&bp->fw_reset_task, delay); | |
1149 | } | |
1150 | ||
c213eae8 MC |
1151 | static void bnxt_queue_sp_work(struct bnxt *bp) |
1152 | { | |
1153 | if (BNXT_PF(bp)) | |
1154 | queue_work(bnxt_pf_wq, &bp->sp_task); | |
1155 | else | |
1156 | schedule_work(&bp->sp_task); | |
1157 | } | |
1158 | ||
1159 | static void bnxt_cancel_sp_work(struct bnxt *bp) | |
1160 | { | |
1161 | if (BNXT_PF(bp)) | |
1162 | flush_workqueue(bnxt_pf_wq); | |
1163 | else | |
1164 | cancel_work_sync(&bp->sp_task); | |
1165 | } | |
1166 | ||
fa7e2812 MC |
1167 | static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) |
1168 | { | |
1169 | if (!rxr->bnapi->in_reset) { | |
1170 | rxr->bnapi->in_reset = true; | |
1171 | set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 1172 | bnxt_queue_sp_work(bp); |
fa7e2812 MC |
1173 | } |
1174 | rxr->rx_next_cons = 0xffff; | |
1175 | } | |
1176 | ||
ec4d8e7c MC |
1177 | static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) |
1178 | { | |
1179 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1180 | u16 idx = agg_id & MAX_TPA_P5_MASK; | |
1181 | ||
1182 | if (test_bit(idx, map->agg_idx_bmap)) | |
1183 | idx = find_first_zero_bit(map->agg_idx_bmap, | |
1184 | BNXT_AGG_IDX_BMAP_SIZE); | |
1185 | __set_bit(idx, map->agg_idx_bmap); | |
1186 | map->agg_id_tbl[agg_id] = idx; | |
1187 | return idx; | |
1188 | } | |
1189 | ||
1190 | static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) | |
1191 | { | |
1192 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1193 | ||
1194 | __clear_bit(idx, map->agg_idx_bmap); | |
1195 | } | |
1196 | ||
1197 | static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) | |
1198 | { | |
1199 | struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; | |
1200 | ||
1201 | return map->agg_id_tbl[agg_id]; | |
1202 | } | |
1203 | ||
c0c050c5 MC |
1204 | static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
1205 | struct rx_tpa_start_cmp *tpa_start, | |
1206 | struct rx_tpa_start_cmp_ext *tpa_start1) | |
1207 | { | |
c0c050c5 | 1208 | struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; |
bfcd8d79 MC |
1209 | struct bnxt_tpa_info *tpa_info; |
1210 | u16 cons, prod, agg_id; | |
c0c050c5 MC |
1211 | struct rx_bd *prod_bd; |
1212 | dma_addr_t mapping; | |
1213 | ||
ec4d8e7c | 1214 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
bfcd8d79 | 1215 | agg_id = TPA_START_AGG_ID_P5(tpa_start); |
ec4d8e7c MC |
1216 | agg_id = bnxt_alloc_agg_idx(rxr, agg_id); |
1217 | } else { | |
bfcd8d79 | 1218 | agg_id = TPA_START_AGG_ID(tpa_start); |
ec4d8e7c | 1219 | } |
c0c050c5 MC |
1220 | cons = tpa_start->rx_tpa_start_cmp_opaque; |
1221 | prod = rxr->rx_prod; | |
1222 | cons_rx_buf = &rxr->rx_buf_ring[cons]; | |
1223 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
1224 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1225 | ||
bfcd8d79 MC |
1226 | if (unlikely(cons != rxr->rx_next_cons || |
1227 | TPA_START_ERROR(tpa_start))) { | |
1228 | netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", | |
1229 | cons, rxr->rx_next_cons, | |
1230 | TPA_START_ERROR_CODE(tpa_start1)); | |
fa7e2812 MC |
1231 | bnxt_sched_reset(bp, rxr); |
1232 | return; | |
1233 | } | |
ee5c7fb3 SP |
1234 | /* Store cfa_code in tpa_info to use in tpa_end |
1235 | * completion processing. | |
1236 | */ | |
1237 | tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); | |
c0c050c5 | 1238 | prod_rx_buf->data = tpa_info->data; |
6bb19474 | 1239 | prod_rx_buf->data_ptr = tpa_info->data_ptr; |
c0c050c5 MC |
1240 | |
1241 | mapping = tpa_info->mapping; | |
11cd119d | 1242 | prod_rx_buf->mapping = mapping; |
c0c050c5 MC |
1243 | |
1244 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
1245 | ||
1246 | prod_bd->rx_bd_haddr = cpu_to_le64(mapping); | |
1247 | ||
1248 | tpa_info->data = cons_rx_buf->data; | |
6bb19474 | 1249 | tpa_info->data_ptr = cons_rx_buf->data_ptr; |
c0c050c5 | 1250 | cons_rx_buf->data = NULL; |
11cd119d | 1251 | tpa_info->mapping = cons_rx_buf->mapping; |
c0c050c5 MC |
1252 | |
1253 | tpa_info->len = | |
1254 | le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> | |
1255 | RX_TPA_START_CMP_LEN_SHIFT; | |
1256 | if (likely(TPA_START_HASH_VALID(tpa_start))) { | |
1257 | u32 hash_type = TPA_START_HASH_TYPE(tpa_start); | |
1258 | ||
1259 | tpa_info->hash_type = PKT_HASH_TYPE_L4; | |
1260 | tpa_info->gso_type = SKB_GSO_TCPV4; | |
1261 | /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ | |
50f011b6 | 1262 | if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) |
c0c050c5 MC |
1263 | tpa_info->gso_type = SKB_GSO_TCPV6; |
1264 | tpa_info->rss_hash = | |
1265 | le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); | |
1266 | } else { | |
1267 | tpa_info->hash_type = PKT_HASH_TYPE_NONE; | |
1268 | tpa_info->gso_type = 0; | |
1269 | if (netif_msg_rx_err(bp)) | |
1270 | netdev_warn(bp->dev, "TPA packet without valid hash\n"); | |
1271 | } | |
1272 | tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); | |
1273 | tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); | |
94758f8d | 1274 | tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); |
bfcd8d79 | 1275 | tpa_info->agg_count = 0; |
c0c050c5 MC |
1276 | |
1277 | rxr->rx_prod = NEXT_RX(prod); | |
1278 | cons = NEXT_RX(cons); | |
376a5b86 | 1279 | rxr->rx_next_cons = NEXT_RX(cons); |
c0c050c5 MC |
1280 | cons_rx_buf = &rxr->rx_buf_ring[cons]; |
1281 | ||
1282 | bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); | |
1283 | rxr->rx_prod = NEXT_RX(rxr->rx_prod); | |
1284 | cons_rx_buf->data = NULL; | |
1285 | } | |
1286 | ||
4a228a3a | 1287 | static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) |
c0c050c5 MC |
1288 | { |
1289 | if (agg_bufs) | |
4a228a3a | 1290 | bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); |
c0c050c5 MC |
1291 | } |
1292 | ||
bee5a188 MC |
1293 | #ifdef CONFIG_INET |
1294 | static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) | |
1295 | { | |
1296 | struct udphdr *uh = NULL; | |
1297 | ||
1298 | if (ip_proto == htons(ETH_P_IP)) { | |
1299 | struct iphdr *iph = (struct iphdr *)skb->data; | |
1300 | ||
1301 | if (iph->protocol == IPPROTO_UDP) | |
1302 | uh = (struct udphdr *)(iph + 1); | |
1303 | } else { | |
1304 | struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; | |
1305 | ||
1306 | if (iph->nexthdr == IPPROTO_UDP) | |
1307 | uh = (struct udphdr *)(iph + 1); | |
1308 | } | |
1309 | if (uh) { | |
1310 | if (uh->check) | |
1311 | skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; | |
1312 | else | |
1313 | skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; | |
1314 | } | |
1315 | } | |
1316 | #endif | |
1317 | ||
94758f8d MC |
1318 | static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, |
1319 | int payload_off, int tcp_ts, | |
1320 | struct sk_buff *skb) | |
1321 | { | |
1322 | #ifdef CONFIG_INET | |
1323 | struct tcphdr *th; | |
1324 | int len, nw_off; | |
1325 | u16 outer_ip_off, inner_ip_off, inner_mac_off; | |
1326 | u32 hdr_info = tpa_info->hdr_info; | |
1327 | bool loopback = false; | |
1328 | ||
1329 | inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); | |
1330 | inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); | |
1331 | outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); | |
1332 | ||
1333 | /* If the packet is an internal loopback packet, the offsets will | |
1334 | * have an extra 4 bytes. | |
1335 | */ | |
1336 | if (inner_mac_off == 4) { | |
1337 | loopback = true; | |
1338 | } else if (inner_mac_off > 4) { | |
1339 | __be16 proto = *((__be16 *)(skb->data + inner_ip_off - | |
1340 | ETH_HLEN - 2)); | |
1341 | ||
1342 | /* We only support inner iPv4/ipv6. If we don't see the | |
1343 | * correct protocol ID, it must be a loopback packet where | |
1344 | * the offsets are off by 4. | |
1345 | */ | |
09a7636a | 1346 | if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) |
94758f8d MC |
1347 | loopback = true; |
1348 | } | |
1349 | if (loopback) { | |
1350 | /* internal loopback packet, subtract all offsets by 4 */ | |
1351 | inner_ip_off -= 4; | |
1352 | inner_mac_off -= 4; | |
1353 | outer_ip_off -= 4; | |
1354 | } | |
1355 | ||
1356 | nw_off = inner_ip_off - ETH_HLEN; | |
1357 | skb_set_network_header(skb, nw_off); | |
1358 | if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { | |
1359 | struct ipv6hdr *iph = ipv6_hdr(skb); | |
1360 | ||
1361 | skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); | |
1362 | len = skb->len - skb_transport_offset(skb); | |
1363 | th = tcp_hdr(skb); | |
1364 | th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); | |
1365 | } else { | |
1366 | struct iphdr *iph = ip_hdr(skb); | |
1367 | ||
1368 | skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); | |
1369 | len = skb->len - skb_transport_offset(skb); | |
1370 | th = tcp_hdr(skb); | |
1371 | th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); | |
1372 | } | |
1373 | ||
1374 | if (inner_mac_off) { /* tunnel */ | |
94758f8d MC |
1375 | __be16 proto = *((__be16 *)(skb->data + outer_ip_off - |
1376 | ETH_HLEN - 2)); | |
1377 | ||
bee5a188 | 1378 | bnxt_gro_tunnel(skb, proto); |
94758f8d MC |
1379 | } |
1380 | #endif | |
1381 | return skb; | |
1382 | } | |
1383 | ||
67912c36 MC |
1384 | static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, |
1385 | int payload_off, int tcp_ts, | |
1386 | struct sk_buff *skb) | |
1387 | { | |
1388 | #ifdef CONFIG_INET | |
1389 | u16 outer_ip_off, inner_ip_off, inner_mac_off; | |
1390 | u32 hdr_info = tpa_info->hdr_info; | |
1391 | int iphdr_len, nw_off; | |
1392 | ||
1393 | inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); | |
1394 | inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); | |
1395 | outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); | |
1396 | ||
1397 | nw_off = inner_ip_off - ETH_HLEN; | |
1398 | skb_set_network_header(skb, nw_off); | |
1399 | iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? | |
1400 | sizeof(struct ipv6hdr) : sizeof(struct iphdr); | |
1401 | skb_set_transport_header(skb, nw_off + iphdr_len); | |
1402 | ||
1403 | if (inner_mac_off) { /* tunnel */ | |
1404 | __be16 proto = *((__be16 *)(skb->data + outer_ip_off - | |
1405 | ETH_HLEN - 2)); | |
1406 | ||
1407 | bnxt_gro_tunnel(skb, proto); | |
1408 | } | |
1409 | #endif | |
1410 | return skb; | |
1411 | } | |
1412 | ||
c0c050c5 MC |
1413 | #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) |
1414 | #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) | |
1415 | ||
309369c9 MC |
1416 | static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, |
1417 | int payload_off, int tcp_ts, | |
c0c050c5 MC |
1418 | struct sk_buff *skb) |
1419 | { | |
d1611c3a | 1420 | #ifdef CONFIG_INET |
c0c050c5 | 1421 | struct tcphdr *th; |
719ca811 | 1422 | int len, nw_off, tcp_opt_len = 0; |
27e24189 | 1423 | |
309369c9 | 1424 | if (tcp_ts) |
c0c050c5 MC |
1425 | tcp_opt_len = 12; |
1426 | ||
c0c050c5 MC |
1427 | if (tpa_info->gso_type == SKB_GSO_TCPV4) { |
1428 | struct iphdr *iph; | |
1429 | ||
1430 | nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - | |
1431 | ETH_HLEN; | |
1432 | skb_set_network_header(skb, nw_off); | |
1433 | iph = ip_hdr(skb); | |
1434 | skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); | |
1435 | len = skb->len - skb_transport_offset(skb); | |
1436 | th = tcp_hdr(skb); | |
1437 | th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); | |
1438 | } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { | |
1439 | struct ipv6hdr *iph; | |
1440 | ||
1441 | nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - | |
1442 | ETH_HLEN; | |
1443 | skb_set_network_header(skb, nw_off); | |
1444 | iph = ipv6_hdr(skb); | |
1445 | skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); | |
1446 | len = skb->len - skb_transport_offset(skb); | |
1447 | th = tcp_hdr(skb); | |
1448 | th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); | |
1449 | } else { | |
1450 | dev_kfree_skb_any(skb); | |
1451 | return NULL; | |
1452 | } | |
c0c050c5 | 1453 | |
bee5a188 MC |
1454 | if (nw_off) /* tunnel */ |
1455 | bnxt_gro_tunnel(skb, skb->protocol); | |
c0c050c5 MC |
1456 | #endif |
1457 | return skb; | |
1458 | } | |
1459 | ||
309369c9 MC |
1460 | static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, |
1461 | struct bnxt_tpa_info *tpa_info, | |
1462 | struct rx_tpa_end_cmp *tpa_end, | |
1463 | struct rx_tpa_end_cmp_ext *tpa_end1, | |
1464 | struct sk_buff *skb) | |
1465 | { | |
1466 | #ifdef CONFIG_INET | |
1467 | int payload_off; | |
1468 | u16 segs; | |
1469 | ||
1470 | segs = TPA_END_TPA_SEGS(tpa_end); | |
1471 | if (segs == 1) | |
1472 | return skb; | |
1473 | ||
1474 | NAPI_GRO_CB(skb)->count = segs; | |
1475 | skb_shinfo(skb)->gso_size = | |
1476 | le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); | |
1477 | skb_shinfo(skb)->gso_type = tpa_info->gso_type; | |
bfcd8d79 MC |
1478 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
1479 | payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); | |
1480 | else | |
1481 | payload_off = TPA_END_PAYLOAD_OFF(tpa_end); | |
309369c9 | 1482 | skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); |
5910906c MC |
1483 | if (likely(skb)) |
1484 | tcp_gro_complete(skb); | |
309369c9 MC |
1485 | #endif |
1486 | return skb; | |
1487 | } | |
1488 | ||
ee5c7fb3 SP |
1489 | /* Given the cfa_code of a received packet determine which |
1490 | * netdev (vf-rep or PF) the packet is destined to. | |
1491 | */ | |
1492 | static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) | |
1493 | { | |
1494 | struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); | |
1495 | ||
1496 | /* if vf-rep dev is NULL, the must belongs to the PF */ | |
1497 | return dev ? dev : bp->dev; | |
1498 | } | |
1499 | ||
c0c050c5 | 1500 | static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, |
e44758b7 | 1501 | struct bnxt_cp_ring_info *cpr, |
c0c050c5 MC |
1502 | u32 *raw_cons, |
1503 | struct rx_tpa_end_cmp *tpa_end, | |
1504 | struct rx_tpa_end_cmp_ext *tpa_end1, | |
4e5dbbda | 1505 | u8 *event) |
c0c050c5 | 1506 | { |
e44758b7 | 1507 | struct bnxt_napi *bnapi = cpr->bnapi; |
b6ab4b01 | 1508 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
6bb19474 | 1509 | u8 *data_ptr, agg_bufs; |
c0c050c5 MC |
1510 | unsigned int len; |
1511 | struct bnxt_tpa_info *tpa_info; | |
1512 | dma_addr_t mapping; | |
1513 | struct sk_buff *skb; | |
bfcd8d79 | 1514 | u16 idx = 0, agg_id; |
6bb19474 | 1515 | void *data; |
bfcd8d79 | 1516 | bool gro; |
c0c050c5 | 1517 | |
fa7e2812 | 1518 | if (unlikely(bnapi->in_reset)) { |
e44758b7 | 1519 | int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); |
fa7e2812 MC |
1520 | |
1521 | if (rc < 0) | |
1522 | return ERR_PTR(-EBUSY); | |
1523 | return NULL; | |
1524 | } | |
1525 | ||
bfcd8d79 MC |
1526 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
1527 | agg_id = TPA_END_AGG_ID_P5(tpa_end); | |
ec4d8e7c | 1528 | agg_id = bnxt_lookup_agg_idx(rxr, agg_id); |
bfcd8d79 MC |
1529 | agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); |
1530 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1531 | if (unlikely(agg_bufs != tpa_info->agg_count)) { | |
1532 | netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", | |
1533 | agg_bufs, tpa_info->agg_count); | |
1534 | agg_bufs = tpa_info->agg_count; | |
1535 | } | |
1536 | tpa_info->agg_count = 0; | |
1537 | *event |= BNXT_AGG_EVENT; | |
ec4d8e7c | 1538 | bnxt_free_agg_idx(rxr, agg_id); |
bfcd8d79 MC |
1539 | idx = agg_id; |
1540 | gro = !!(bp->flags & BNXT_FLAG_GRO); | |
1541 | } else { | |
1542 | agg_id = TPA_END_AGG_ID(tpa_end); | |
1543 | agg_bufs = TPA_END_AGG_BUFS(tpa_end); | |
1544 | tpa_info = &rxr->rx_tpa[agg_id]; | |
1545 | idx = RING_CMP(*raw_cons); | |
1546 | if (agg_bufs) { | |
1547 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) | |
1548 | return ERR_PTR(-EBUSY); | |
1549 | ||
1550 | *event |= BNXT_AGG_EVENT; | |
1551 | idx = NEXT_CMP(idx); | |
1552 | } | |
1553 | gro = !!TPA_END_GRO(tpa_end); | |
1554 | } | |
c0c050c5 | 1555 | data = tpa_info->data; |
6bb19474 MC |
1556 | data_ptr = tpa_info->data_ptr; |
1557 | prefetch(data_ptr); | |
c0c050c5 MC |
1558 | len = tpa_info->len; |
1559 | mapping = tpa_info->mapping; | |
1560 | ||
69c149e2 | 1561 | if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { |
4a228a3a | 1562 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
69c149e2 MC |
1563 | if (agg_bufs > MAX_SKB_FRAGS) |
1564 | netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", | |
1565 | agg_bufs, (int)MAX_SKB_FRAGS); | |
c0c050c5 MC |
1566 | return NULL; |
1567 | } | |
1568 | ||
1569 | if (len <= bp->rx_copy_thresh) { | |
6bb19474 | 1570 | skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); |
c0c050c5 | 1571 | if (!skb) { |
4a228a3a | 1572 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1573 | return NULL; |
1574 | } | |
1575 | } else { | |
1576 | u8 *new_data; | |
1577 | dma_addr_t new_mapping; | |
1578 | ||
1579 | new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); | |
1580 | if (!new_data) { | |
4a228a3a | 1581 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1582 | return NULL; |
1583 | } | |
1584 | ||
1585 | tpa_info->data = new_data; | |
b3dba77c | 1586 | tpa_info->data_ptr = new_data + bp->rx_offset; |
c0c050c5 MC |
1587 | tpa_info->mapping = new_mapping; |
1588 | ||
1589 | skb = build_skb(data, 0); | |
c519fe9a SN |
1590 | dma_unmap_single_attrs(&bp->pdev->dev, mapping, |
1591 | bp->rx_buf_use_size, bp->rx_dir, | |
1592 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
1593 | |
1594 | if (!skb) { | |
1595 | kfree(data); | |
4a228a3a | 1596 | bnxt_abort_tpa(cpr, idx, agg_bufs); |
c0c050c5 MC |
1597 | return NULL; |
1598 | } | |
b3dba77c | 1599 | skb_reserve(skb, bp->rx_offset); |
c0c050c5 MC |
1600 | skb_put(skb, len); |
1601 | } | |
1602 | ||
1603 | if (agg_bufs) { | |
4a228a3a | 1604 | skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true); |
c0c050c5 MC |
1605 | if (!skb) { |
1606 | /* Page reuse already handled by bnxt_rx_pages(). */ | |
1607 | return NULL; | |
1608 | } | |
1609 | } | |
ee5c7fb3 SP |
1610 | |
1611 | skb->protocol = | |
1612 | eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); | |
c0c050c5 MC |
1613 | |
1614 | if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) | |
1615 | skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); | |
1616 | ||
8852ddb4 MC |
1617 | if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && |
1618 | (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
c0c050c5 MC |
1619 | u16 vlan_proto = tpa_info->metadata >> |
1620 | RX_CMP_FLAGS2_METADATA_TPID_SFT; | |
ed7bc602 | 1621 | u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; |
c0c050c5 | 1622 | |
8852ddb4 | 1623 | __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); |
c0c050c5 MC |
1624 | } |
1625 | ||
1626 | skb_checksum_none_assert(skb); | |
1627 | if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { | |
1628 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1629 | skb->csum_level = | |
1630 | (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; | |
1631 | } | |
1632 | ||
bfcd8d79 | 1633 | if (gro) |
309369c9 | 1634 | skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); |
c0c050c5 MC |
1635 | |
1636 | return skb; | |
1637 | } | |
1638 | ||
8fe88ce7 MC |
1639 | static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
1640 | struct rx_agg_cmp *rx_agg) | |
1641 | { | |
1642 | u16 agg_id = TPA_AGG_AGG_ID(rx_agg); | |
1643 | struct bnxt_tpa_info *tpa_info; | |
1644 | ||
ec4d8e7c | 1645 | agg_id = bnxt_lookup_agg_idx(rxr, agg_id); |
8fe88ce7 MC |
1646 | tpa_info = &rxr->rx_tpa[agg_id]; |
1647 | BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); | |
1648 | tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; | |
1649 | } | |
1650 | ||
ee5c7fb3 SP |
1651 | static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, |
1652 | struct sk_buff *skb) | |
1653 | { | |
1654 | if (skb->dev != bp->dev) { | |
1655 | /* this packet belongs to a vf-rep */ | |
1656 | bnxt_vf_rep_rx(bp, skb); | |
1657 | return; | |
1658 | } | |
1659 | skb_record_rx_queue(skb, bnapi->index); | |
1660 | napi_gro_receive(&bnapi->napi, skb); | |
1661 | } | |
1662 | ||
c0c050c5 MC |
1663 | /* returns the following: |
1664 | * 1 - 1 packet successfully received | |
1665 | * 0 - successful TPA_START, packet not completed yet | |
1666 | * -EBUSY - completion ring does not have all the agg buffers yet | |
1667 | * -ENOMEM - packet aborted due to out of memory | |
1668 | * -EIO - packet aborted due to hw error indicated in BD | |
1669 | */ | |
e44758b7 MC |
1670 | static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
1671 | u32 *raw_cons, u8 *event) | |
c0c050c5 | 1672 | { |
e44758b7 | 1673 | struct bnxt_napi *bnapi = cpr->bnapi; |
b6ab4b01 | 1674 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 MC |
1675 | struct net_device *dev = bp->dev; |
1676 | struct rx_cmp *rxcmp; | |
1677 | struct rx_cmp_ext *rxcmp1; | |
1678 | u32 tmp_raw_cons = *raw_cons; | |
ee5c7fb3 | 1679 | u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); |
c0c050c5 MC |
1680 | struct bnxt_sw_rx_bd *rx_buf; |
1681 | unsigned int len; | |
6bb19474 | 1682 | u8 *data_ptr, agg_bufs, cmp_type; |
c0c050c5 MC |
1683 | dma_addr_t dma_addr; |
1684 | struct sk_buff *skb; | |
6bb19474 | 1685 | void *data; |
c0c050c5 | 1686 | int rc = 0; |
c61fb99c | 1687 | u32 misc; |
c0c050c5 MC |
1688 | |
1689 | rxcmp = (struct rx_cmp *) | |
1690 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1691 | ||
8fe88ce7 MC |
1692 | cmp_type = RX_CMP_TYPE(rxcmp); |
1693 | ||
1694 | if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { | |
1695 | bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); | |
1696 | goto next_rx_no_prod_no_len; | |
1697 | } | |
1698 | ||
c0c050c5 MC |
1699 | tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); |
1700 | cp_cons = RING_CMP(tmp_raw_cons); | |
1701 | rxcmp1 = (struct rx_cmp_ext *) | |
1702 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1703 | ||
1704 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
1705 | return -EBUSY; | |
1706 | ||
c0c050c5 MC |
1707 | prod = rxr->rx_prod; |
1708 | ||
1709 | if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { | |
1710 | bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, | |
1711 | (struct rx_tpa_start_cmp_ext *)rxcmp1); | |
1712 | ||
4e5dbbda | 1713 | *event |= BNXT_RX_EVENT; |
e7e70fa6 | 1714 | goto next_rx_no_prod_no_len; |
c0c050c5 MC |
1715 | |
1716 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
e44758b7 | 1717 | skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, |
c0c050c5 | 1718 | (struct rx_tpa_end_cmp *)rxcmp, |
4e5dbbda | 1719 | (struct rx_tpa_end_cmp_ext *)rxcmp1, event); |
c0c050c5 | 1720 | |
1fac4b2f | 1721 | if (IS_ERR(skb)) |
c0c050c5 MC |
1722 | return -EBUSY; |
1723 | ||
1724 | rc = -ENOMEM; | |
1725 | if (likely(skb)) { | |
ee5c7fb3 | 1726 | bnxt_deliver_skb(bp, bnapi, skb); |
c0c050c5 MC |
1727 | rc = 1; |
1728 | } | |
4e5dbbda | 1729 | *event |= BNXT_RX_EVENT; |
e7e70fa6 | 1730 | goto next_rx_no_prod_no_len; |
c0c050c5 MC |
1731 | } |
1732 | ||
1733 | cons = rxcmp->rx_cmp_opaque; | |
fa7e2812 | 1734 | if (unlikely(cons != rxr->rx_next_cons)) { |
e44758b7 | 1735 | int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); |
fa7e2812 | 1736 | |
a1b0e4e6 MC |
1737 | netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", |
1738 | cons, rxr->rx_next_cons); | |
fa7e2812 MC |
1739 | bnxt_sched_reset(bp, rxr); |
1740 | return rc1; | |
1741 | } | |
a1b0e4e6 MC |
1742 | rx_buf = &rxr->rx_buf_ring[cons]; |
1743 | data = rx_buf->data; | |
1744 | data_ptr = rx_buf->data_ptr; | |
6bb19474 | 1745 | prefetch(data_ptr); |
c0c050c5 | 1746 | |
c61fb99c MC |
1747 | misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); |
1748 | agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; | |
c0c050c5 MC |
1749 | |
1750 | if (agg_bufs) { | |
1751 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) | |
1752 | return -EBUSY; | |
1753 | ||
1754 | cp_cons = NEXT_CMP(cp_cons); | |
4e5dbbda | 1755 | *event |= BNXT_AGG_EVENT; |
c0c050c5 | 1756 | } |
4e5dbbda | 1757 | *event |= BNXT_RX_EVENT; |
c0c050c5 MC |
1758 | |
1759 | rx_buf->data = NULL; | |
1760 | if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { | |
8e44e96c MC |
1761 | u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); |
1762 | ||
c0c050c5 MC |
1763 | bnxt_reuse_rx_data(rxr, cons, data); |
1764 | if (agg_bufs) | |
4a228a3a MC |
1765 | bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, |
1766 | false); | |
c0c050c5 MC |
1767 | |
1768 | rc = -EIO; | |
8e44e96c MC |
1769 | if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { |
1770 | netdev_warn(bp->dev, "RX buffer error %x\n", rx_err); | |
1771 | bnxt_sched_reset(bp, rxr); | |
1772 | } | |
0b397b17 | 1773 | goto next_rx_no_len; |
c0c050c5 MC |
1774 | } |
1775 | ||
1776 | len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; | |
11cd119d | 1777 | dma_addr = rx_buf->mapping; |
c0c050c5 | 1778 | |
c6d30e83 MC |
1779 | if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { |
1780 | rc = 1; | |
1781 | goto next_rx; | |
1782 | } | |
1783 | ||
c0c050c5 | 1784 | if (len <= bp->rx_copy_thresh) { |
6bb19474 | 1785 | skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); |
c0c050c5 MC |
1786 | bnxt_reuse_rx_data(rxr, cons, data); |
1787 | if (!skb) { | |
296d5b54 | 1788 | if (agg_bufs) |
4a228a3a MC |
1789 | bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, |
1790 | agg_bufs, false); | |
c0c050c5 MC |
1791 | rc = -ENOMEM; |
1792 | goto next_rx; | |
1793 | } | |
1794 | } else { | |
c61fb99c MC |
1795 | u32 payload; |
1796 | ||
c6d30e83 MC |
1797 | if (rx_buf->data_ptr == data_ptr) |
1798 | payload = misc & RX_CMP_PAYLOAD_OFFSET; | |
1799 | else | |
1800 | payload = 0; | |
6bb19474 | 1801 | skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, |
c61fb99c | 1802 | payload | len); |
c0c050c5 MC |
1803 | if (!skb) { |
1804 | rc = -ENOMEM; | |
1805 | goto next_rx; | |
1806 | } | |
1807 | } | |
1808 | ||
1809 | if (agg_bufs) { | |
4a228a3a | 1810 | skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false); |
c0c050c5 MC |
1811 | if (!skb) { |
1812 | rc = -ENOMEM; | |
1813 | goto next_rx; | |
1814 | } | |
1815 | } | |
1816 | ||
1817 | if (RX_CMP_HASH_VALID(rxcmp)) { | |
1818 | u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); | |
1819 | enum pkt_hash_types type = PKT_HASH_TYPE_L4; | |
1820 | ||
1821 | /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ | |
1822 | if (hash_type != 1 && hash_type != 3) | |
1823 | type = PKT_HASH_TYPE_L3; | |
1824 | skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); | |
1825 | } | |
1826 | ||
ee5c7fb3 SP |
1827 | cfa_code = RX_CMP_CFA_CODE(rxcmp1); |
1828 | skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); | |
c0c050c5 | 1829 | |
8852ddb4 MC |
1830 | if ((rxcmp1->rx_cmp_flags2 & |
1831 | cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && | |
1832 | (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
c0c050c5 | 1833 | u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); |
ed7bc602 | 1834 | u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; |
c0c050c5 MC |
1835 | u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; |
1836 | ||
8852ddb4 | 1837 | __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); |
c0c050c5 MC |
1838 | } |
1839 | ||
1840 | skb_checksum_none_assert(skb); | |
1841 | if (RX_CMP_L4_CS_OK(rxcmp1)) { | |
1842 | if (dev->features & NETIF_F_RXCSUM) { | |
1843 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1844 | skb->csum_level = RX_CMP_ENCAP(rxcmp1); | |
1845 | } | |
1846 | } else { | |
665e350d SB |
1847 | if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { |
1848 | if (dev->features & NETIF_F_RXCSUM) | |
d1981929 | 1849 | bnapi->cp_ring.rx_l4_csum_errors++; |
665e350d | 1850 | } |
c0c050c5 MC |
1851 | } |
1852 | ||
ee5c7fb3 | 1853 | bnxt_deliver_skb(bp, bnapi, skb); |
c0c050c5 MC |
1854 | rc = 1; |
1855 | ||
1856 | next_rx: | |
6a8788f2 AG |
1857 | cpr->rx_packets += 1; |
1858 | cpr->rx_bytes += len; | |
e7e70fa6 | 1859 | |
0b397b17 MC |
1860 | next_rx_no_len: |
1861 | rxr->rx_prod = NEXT_RX(prod); | |
1862 | rxr->rx_next_cons = NEXT_RX(cons); | |
1863 | ||
e7e70fa6 | 1864 | next_rx_no_prod_no_len: |
c0c050c5 MC |
1865 | *raw_cons = tmp_raw_cons; |
1866 | ||
1867 | return rc; | |
1868 | } | |
1869 | ||
2270bc5d MC |
1870 | /* In netpoll mode, if we are using a combined completion ring, we need to |
1871 | * discard the rx packets and recycle the buffers. | |
1872 | */ | |
e44758b7 MC |
1873 | static int bnxt_force_rx_discard(struct bnxt *bp, |
1874 | struct bnxt_cp_ring_info *cpr, | |
2270bc5d MC |
1875 | u32 *raw_cons, u8 *event) |
1876 | { | |
2270bc5d MC |
1877 | u32 tmp_raw_cons = *raw_cons; |
1878 | struct rx_cmp_ext *rxcmp1; | |
1879 | struct rx_cmp *rxcmp; | |
1880 | u16 cp_cons; | |
1881 | u8 cmp_type; | |
1882 | ||
1883 | cp_cons = RING_CMP(tmp_raw_cons); | |
1884 | rxcmp = (struct rx_cmp *) | |
1885 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1886 | ||
1887 | tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); | |
1888 | cp_cons = RING_CMP(tmp_raw_cons); | |
1889 | rxcmp1 = (struct rx_cmp_ext *) | |
1890 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
1891 | ||
1892 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
1893 | return -EBUSY; | |
1894 | ||
1895 | cmp_type = RX_CMP_TYPE(rxcmp); | |
1896 | if (cmp_type == CMP_TYPE_RX_L2_CMP) { | |
1897 | rxcmp1->rx_cmp_cfa_code_errors_v2 |= | |
1898 | cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); | |
1899 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { | |
1900 | struct rx_tpa_end_cmp_ext *tpa_end1; | |
1901 | ||
1902 | tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; | |
1903 | tpa_end1->rx_tpa_end_cmp_errors_v2 |= | |
1904 | cpu_to_le32(RX_TPA_END_CMP_ERRORS); | |
1905 | } | |
e44758b7 | 1906 | return bnxt_rx_pkt(bp, cpr, raw_cons, event); |
2270bc5d MC |
1907 | } |
1908 | ||
7e914027 MC |
1909 | u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) |
1910 | { | |
1911 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
1912 | u32 reg = fw_health->regs[reg_idx]; | |
1913 | u32 reg_type, reg_off, val = 0; | |
1914 | ||
1915 | reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); | |
1916 | reg_off = BNXT_FW_HEALTH_REG_OFF(reg); | |
1917 | switch (reg_type) { | |
1918 | case BNXT_FW_HEALTH_REG_TYPE_CFG: | |
1919 | pci_read_config_dword(bp->pdev, reg_off, &val); | |
1920 | break; | |
1921 | case BNXT_FW_HEALTH_REG_TYPE_GRC: | |
1922 | reg_off = fw_health->mapped_regs[reg_idx]; | |
1923 | /* fall through */ | |
1924 | case BNXT_FW_HEALTH_REG_TYPE_BAR0: | |
1925 | val = readl(bp->bar0 + reg_off); | |
1926 | break; | |
1927 | case BNXT_FW_HEALTH_REG_TYPE_BAR1: | |
1928 | val = readl(bp->bar1 + reg_off); | |
1929 | break; | |
1930 | } | |
1931 | if (reg_idx == BNXT_FW_RESET_INPROG_REG) | |
1932 | val &= fw_health->fw_reset_inprog_reg_mask; | |
1933 | return val; | |
1934 | } | |
1935 | ||
4bb13abf | 1936 | #define BNXT_GET_EVENT_PORT(data) \ |
87c374de MC |
1937 | ((data) & \ |
1938 | ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) | |
4bb13abf | 1939 | |
c0c050c5 MC |
1940 | static int bnxt_async_event_process(struct bnxt *bp, |
1941 | struct hwrm_async_event_cmpl *cmpl) | |
1942 | { | |
1943 | u16 event_id = le16_to_cpu(cmpl->event_id); | |
1944 | ||
1945 | /* TODO CHIMP_FW: Define event id's for link change, error etc */ | |
1946 | switch (event_id) { | |
87c374de | 1947 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { |
8cbde117 MC |
1948 | u32 data1 = le32_to_cpu(cmpl->event_data1); |
1949 | struct bnxt_link_info *link_info = &bp->link_info; | |
1950 | ||
1951 | if (BNXT_VF(bp)) | |
1952 | goto async_event_process_exit; | |
a8168b6c MC |
1953 | |
1954 | /* print unsupported speed warning in forced speed mode only */ | |
1955 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && | |
1956 | (data1 & 0x20000)) { | |
8cbde117 MC |
1957 | u16 fw_speed = link_info->force_link_speed; |
1958 | u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); | |
1959 | ||
a8168b6c MC |
1960 | if (speed != SPEED_UNKNOWN) |
1961 | netdev_warn(bp->dev, "Link speed %d no longer supported\n", | |
1962 | speed); | |
8cbde117 | 1963 | } |
286ef9d6 | 1964 | set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); |
8cbde117 | 1965 | } |
bc171e87 | 1966 | /* fall through */ |
87c374de | 1967 | case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: |
c0c050c5 | 1968 | set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); |
19241368 | 1969 | break; |
87c374de | 1970 | case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: |
19241368 | 1971 | set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); |
c0c050c5 | 1972 | break; |
87c374de | 1973 | case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { |
4bb13abf MC |
1974 | u32 data1 = le32_to_cpu(cmpl->event_data1); |
1975 | u16 port_id = BNXT_GET_EVENT_PORT(data1); | |
1976 | ||
1977 | if (BNXT_VF(bp)) | |
1978 | break; | |
1979 | ||
1980 | if (bp->pf.port_id != port_id) | |
1981 | break; | |
1982 | ||
4bb13abf MC |
1983 | set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); |
1984 | break; | |
1985 | } | |
87c374de | 1986 | case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: |
fc0f1929 MC |
1987 | if (BNXT_PF(bp)) |
1988 | goto async_event_process_exit; | |
1989 | set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); | |
1990 | break; | |
acfb50e4 VV |
1991 | case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { |
1992 | u32 data1 = le32_to_cpu(cmpl->event_data1); | |
1993 | ||
2151fe08 MC |
1994 | bp->fw_reset_timestamp = jiffies; |
1995 | bp->fw_reset_min_dsecs = cmpl->timestamp_lo; | |
1996 | if (!bp->fw_reset_min_dsecs) | |
1997 | bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; | |
1998 | bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); | |
1999 | if (!bp->fw_reset_max_dsecs) | |
2000 | bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; | |
acfb50e4 VV |
2001 | if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { |
2002 | netdev_warn(bp->dev, "Firmware fatal reset event received\n"); | |
2003 | set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); | |
2004 | } else { | |
2005 | netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n", | |
2006 | bp->fw_reset_max_dsecs * 100); | |
2007 | } | |
2151fe08 MC |
2008 | set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); |
2009 | break; | |
acfb50e4 | 2010 | } |
7e914027 MC |
2011 | case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { |
2012 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
2013 | u32 data1 = le32_to_cpu(cmpl->event_data1); | |
2014 | ||
2015 | if (!fw_health) | |
2016 | goto async_event_process_exit; | |
2017 | ||
2018 | fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1); | |
2019 | fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); | |
2020 | if (!fw_health->enabled) | |
2021 | break; | |
2022 | ||
2023 | if (netif_msg_drv(bp)) | |
2024 | netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n", | |
2025 | fw_health->enabled, fw_health->master, | |
2026 | bnxt_fw_health_readl(bp, | |
2027 | BNXT_FW_RESET_CNT_REG), | |
2028 | bnxt_fw_health_readl(bp, | |
2029 | BNXT_FW_HEALTH_REG)); | |
2030 | fw_health->tmr_multiplier = | |
2031 | DIV_ROUND_UP(fw_health->polling_dsecs * HZ, | |
2032 | bp->current_interval * 10); | |
2033 | fw_health->tmr_counter = fw_health->tmr_multiplier; | |
2034 | fw_health->last_fw_heartbeat = | |
2035 | bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
2036 | fw_health->last_fw_reset_cnt = | |
2037 | bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
2038 | goto async_event_process_exit; | |
2039 | } | |
c0c050c5 | 2040 | default: |
19241368 | 2041 | goto async_event_process_exit; |
c0c050c5 | 2042 | } |
c213eae8 | 2043 | bnxt_queue_sp_work(bp); |
19241368 | 2044 | async_event_process_exit: |
a588e458 | 2045 | bnxt_ulp_async_events(bp, cmpl); |
c0c050c5 MC |
2046 | return 0; |
2047 | } | |
2048 | ||
2049 | static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) | |
2050 | { | |
2051 | u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; | |
2052 | struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; | |
2053 | struct hwrm_fwd_req_cmpl *fwd_req_cmpl = | |
2054 | (struct hwrm_fwd_req_cmpl *)txcmp; | |
2055 | ||
2056 | switch (cmpl_type) { | |
2057 | case CMPL_BASE_TYPE_HWRM_DONE: | |
2058 | seq_id = le16_to_cpu(h_cmpl->sequence_id); | |
2059 | if (seq_id == bp->hwrm_intr_seq_id) | |
fc718bb2 | 2060 | bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; |
c0c050c5 MC |
2061 | else |
2062 | netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); | |
2063 | break; | |
2064 | ||
2065 | case CMPL_BASE_TYPE_HWRM_FWD_REQ: | |
2066 | vf_id = le16_to_cpu(fwd_req_cmpl->source_id); | |
2067 | ||
2068 | if ((vf_id < bp->pf.first_vf_id) || | |
2069 | (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { | |
2070 | netdev_err(bp->dev, "Msg contains invalid VF id %x\n", | |
2071 | vf_id); | |
2072 | return -EINVAL; | |
2073 | } | |
2074 | ||
2075 | set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); | |
2076 | set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); | |
c213eae8 | 2077 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
2078 | break; |
2079 | ||
2080 | case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: | |
2081 | bnxt_async_event_process(bp, | |
2082 | (struct hwrm_async_event_cmpl *)txcmp); | |
2083 | ||
2084 | default: | |
2085 | break; | |
2086 | } | |
2087 | ||
2088 | return 0; | |
2089 | } | |
2090 | ||
2091 | static irqreturn_t bnxt_msix(int irq, void *dev_instance) | |
2092 | { | |
2093 | struct bnxt_napi *bnapi = dev_instance; | |
2094 | struct bnxt *bp = bnapi->bp; | |
2095 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2096 | u32 cons = RING_CMP(cpr->cp_raw_cons); | |
2097 | ||
6a8788f2 | 2098 | cpr->event_ctr++; |
c0c050c5 MC |
2099 | prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); |
2100 | napi_schedule(&bnapi->napi); | |
2101 | return IRQ_HANDLED; | |
2102 | } | |
2103 | ||
2104 | static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) | |
2105 | { | |
2106 | u32 raw_cons = cpr->cp_raw_cons; | |
2107 | u16 cons = RING_CMP(raw_cons); | |
2108 | struct tx_cmp *txcmp; | |
2109 | ||
2110 | txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2111 | ||
2112 | return TX_CMP_VALID(txcmp, raw_cons); | |
2113 | } | |
2114 | ||
c0c050c5 MC |
2115 | static irqreturn_t bnxt_inta(int irq, void *dev_instance) |
2116 | { | |
2117 | struct bnxt_napi *bnapi = dev_instance; | |
2118 | struct bnxt *bp = bnapi->bp; | |
2119 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2120 | u32 cons = RING_CMP(cpr->cp_raw_cons); | |
2121 | u32 int_status; | |
2122 | ||
2123 | prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); | |
2124 | ||
2125 | if (!bnxt_has_work(bp, cpr)) { | |
11809490 | 2126 | int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); |
c0c050c5 MC |
2127 | /* return if erroneous interrupt */ |
2128 | if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) | |
2129 | return IRQ_NONE; | |
2130 | } | |
2131 | ||
2132 | /* disable ring IRQ */ | |
697197e5 | 2133 | BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); |
c0c050c5 MC |
2134 | |
2135 | /* Return here if interrupt is shared and is disabled. */ | |
2136 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | |
2137 | return IRQ_HANDLED; | |
2138 | ||
2139 | napi_schedule(&bnapi->napi); | |
2140 | return IRQ_HANDLED; | |
2141 | } | |
2142 | ||
3675b92f MC |
2143 | static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
2144 | int budget) | |
c0c050c5 | 2145 | { |
e44758b7 | 2146 | struct bnxt_napi *bnapi = cpr->bnapi; |
c0c050c5 MC |
2147 | u32 raw_cons = cpr->cp_raw_cons; |
2148 | u32 cons; | |
2149 | int tx_pkts = 0; | |
2150 | int rx_pkts = 0; | |
4e5dbbda | 2151 | u8 event = 0; |
c0c050c5 MC |
2152 | struct tx_cmp *txcmp; |
2153 | ||
0fcec985 | 2154 | cpr->has_more_work = 0; |
c0c050c5 MC |
2155 | while (1) { |
2156 | int rc; | |
2157 | ||
2158 | cons = RING_CMP(raw_cons); | |
2159 | txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2160 | ||
2161 | if (!TX_CMP_VALID(txcmp, raw_cons)) | |
2162 | break; | |
2163 | ||
67a95e20 MC |
2164 | /* The valid test of the entry must be done first before |
2165 | * reading any further. | |
2166 | */ | |
b67daab0 | 2167 | dma_rmb(); |
3675b92f | 2168 | cpr->had_work_done = 1; |
c0c050c5 MC |
2169 | if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { |
2170 | tx_pkts++; | |
2171 | /* return full budget so NAPI will complete. */ | |
73f21c65 | 2172 | if (unlikely(tx_pkts > bp->tx_wake_thresh)) { |
c0c050c5 | 2173 | rx_pkts = budget; |
73f21c65 | 2174 | raw_cons = NEXT_RAW_CMP(raw_cons); |
0fcec985 MC |
2175 | if (budget) |
2176 | cpr->has_more_work = 1; | |
73f21c65 MC |
2177 | break; |
2178 | } | |
c0c050c5 | 2179 | } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { |
2270bc5d | 2180 | if (likely(budget)) |
e44758b7 | 2181 | rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); |
2270bc5d | 2182 | else |
e44758b7 | 2183 | rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, |
2270bc5d | 2184 | &event); |
c0c050c5 MC |
2185 | if (likely(rc >= 0)) |
2186 | rx_pkts += rc; | |
903649e7 MC |
2187 | /* Increment rx_pkts when rc is -ENOMEM to count towards |
2188 | * the NAPI budget. Otherwise, we may potentially loop | |
2189 | * here forever if we consistently cannot allocate | |
2190 | * buffers. | |
2191 | */ | |
2edbdb31 | 2192 | else if (rc == -ENOMEM && budget) |
903649e7 | 2193 | rx_pkts++; |
c0c050c5 MC |
2194 | else if (rc == -EBUSY) /* partial completion */ |
2195 | break; | |
c0c050c5 MC |
2196 | } else if (unlikely((TX_CMP_TYPE(txcmp) == |
2197 | CMPL_BASE_TYPE_HWRM_DONE) || | |
2198 | (TX_CMP_TYPE(txcmp) == | |
2199 | CMPL_BASE_TYPE_HWRM_FWD_REQ) || | |
2200 | (TX_CMP_TYPE(txcmp) == | |
2201 | CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { | |
2202 | bnxt_hwrm_handler(bp, txcmp); | |
2203 | } | |
2204 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2205 | ||
0fcec985 MC |
2206 | if (rx_pkts && rx_pkts == budget) { |
2207 | cpr->has_more_work = 1; | |
c0c050c5 | 2208 | break; |
0fcec985 | 2209 | } |
c0c050c5 MC |
2210 | } |
2211 | ||
f18c2b77 AG |
2212 | if (event & BNXT_REDIRECT_EVENT) |
2213 | xdp_do_flush_map(); | |
2214 | ||
38413406 MC |
2215 | if (event & BNXT_TX_EVENT) { |
2216 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; | |
38413406 MC |
2217 | u16 prod = txr->tx_prod; |
2218 | ||
2219 | /* Sync BD data before updating doorbell */ | |
2220 | wmb(); | |
2221 | ||
697197e5 | 2222 | bnxt_db_write_relaxed(bp, &txr->tx_db, prod); |
38413406 MC |
2223 | } |
2224 | ||
c0c050c5 | 2225 | cpr->cp_raw_cons = raw_cons; |
3675b92f MC |
2226 | bnapi->tx_pkts += tx_pkts; |
2227 | bnapi->events |= event; | |
2228 | return rx_pkts; | |
2229 | } | |
c0c050c5 | 2230 | |
3675b92f MC |
2231 | static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) |
2232 | { | |
2233 | if (bnapi->tx_pkts) { | |
2234 | bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); | |
2235 | bnapi->tx_pkts = 0; | |
2236 | } | |
c0c050c5 | 2237 | |
3675b92f | 2238 | if (bnapi->events & BNXT_RX_EVENT) { |
b6ab4b01 | 2239 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
c0c050c5 | 2240 | |
3675b92f | 2241 | if (bnapi->events & BNXT_AGG_EVENT) |
697197e5 | 2242 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); |
e8f267b0 | 2243 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); |
c0c050c5 | 2244 | } |
3675b92f MC |
2245 | bnapi->events = 0; |
2246 | } | |
2247 | ||
2248 | static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, | |
2249 | int budget) | |
2250 | { | |
2251 | struct bnxt_napi *bnapi = cpr->bnapi; | |
2252 | int rx_pkts; | |
2253 | ||
2254 | rx_pkts = __bnxt_poll_work(bp, cpr, budget); | |
2255 | ||
2256 | /* ACK completion ring before freeing tx ring and producing new | |
2257 | * buffers in rx/agg rings to prevent overflowing the completion | |
2258 | * ring. | |
2259 | */ | |
2260 | bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); | |
2261 | ||
2262 | __bnxt_poll_work_done(bp, bnapi); | |
c0c050c5 MC |
2263 | return rx_pkts; |
2264 | } | |
2265 | ||
10bbdaf5 PS |
2266 | static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) |
2267 | { | |
2268 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2269 | struct bnxt *bp = bnapi->bp; | |
2270 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2271 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; | |
2272 | struct tx_cmp *txcmp; | |
2273 | struct rx_cmp_ext *rxcmp1; | |
2274 | u32 cp_cons, tmp_raw_cons; | |
2275 | u32 raw_cons = cpr->cp_raw_cons; | |
2276 | u32 rx_pkts = 0; | |
4e5dbbda | 2277 | u8 event = 0; |
10bbdaf5 PS |
2278 | |
2279 | while (1) { | |
2280 | int rc; | |
2281 | ||
2282 | cp_cons = RING_CMP(raw_cons); | |
2283 | txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
2284 | ||
2285 | if (!TX_CMP_VALID(txcmp, raw_cons)) | |
2286 | break; | |
2287 | ||
2288 | if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { | |
2289 | tmp_raw_cons = NEXT_RAW_CMP(raw_cons); | |
2290 | cp_cons = RING_CMP(tmp_raw_cons); | |
2291 | rxcmp1 = (struct rx_cmp_ext *) | |
2292 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; | |
2293 | ||
2294 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) | |
2295 | break; | |
2296 | ||
2297 | /* force an error to recycle the buffer */ | |
2298 | rxcmp1->rx_cmp_cfa_code_errors_v2 |= | |
2299 | cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); | |
2300 | ||
e44758b7 | 2301 | rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); |
2edbdb31 | 2302 | if (likely(rc == -EIO) && budget) |
10bbdaf5 PS |
2303 | rx_pkts++; |
2304 | else if (rc == -EBUSY) /* partial completion */ | |
2305 | break; | |
2306 | } else if (unlikely(TX_CMP_TYPE(txcmp) == | |
2307 | CMPL_BASE_TYPE_HWRM_DONE)) { | |
2308 | bnxt_hwrm_handler(bp, txcmp); | |
2309 | } else { | |
2310 | netdev_err(bp->dev, | |
2311 | "Invalid completion received on special ring\n"); | |
2312 | } | |
2313 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2314 | ||
2315 | if (rx_pkts == budget) | |
2316 | break; | |
2317 | } | |
2318 | ||
2319 | cpr->cp_raw_cons = raw_cons; | |
697197e5 MC |
2320 | BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); |
2321 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); | |
10bbdaf5 | 2322 | |
434c975a | 2323 | if (event & BNXT_AGG_EVENT) |
697197e5 | 2324 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); |
10bbdaf5 PS |
2325 | |
2326 | if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { | |
6ad20165 | 2327 | napi_complete_done(napi, rx_pkts); |
697197e5 | 2328 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
10bbdaf5 PS |
2329 | } |
2330 | return rx_pkts; | |
2331 | } | |
2332 | ||
c0c050c5 MC |
2333 | static int bnxt_poll(struct napi_struct *napi, int budget) |
2334 | { | |
2335 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2336 | struct bnxt *bp = bnapi->bp; | |
2337 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2338 | int work_done = 0; | |
2339 | ||
c0c050c5 | 2340 | while (1) { |
e44758b7 | 2341 | work_done += bnxt_poll_work(bp, cpr, budget - work_done); |
c0c050c5 | 2342 | |
73f21c65 MC |
2343 | if (work_done >= budget) { |
2344 | if (!budget) | |
697197e5 | 2345 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
c0c050c5 | 2346 | break; |
73f21c65 | 2347 | } |
c0c050c5 MC |
2348 | |
2349 | if (!bnxt_has_work(bp, cpr)) { | |
e7b95691 | 2350 | if (napi_complete_done(napi, work_done)) |
697197e5 | 2351 | BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); |
c0c050c5 MC |
2352 | break; |
2353 | } | |
2354 | } | |
6a8788f2 | 2355 | if (bp->flags & BNXT_FLAG_DIM) { |
f06d0ca4 | 2356 | struct dim_sample dim_sample = {}; |
6a8788f2 | 2357 | |
8960b389 TG |
2358 | dim_update_sample(cpr->event_ctr, |
2359 | cpr->rx_packets, | |
2360 | cpr->rx_bytes, | |
2361 | &dim_sample); | |
6a8788f2 AG |
2362 | net_dim(&cpr->dim, dim_sample); |
2363 | } | |
c0c050c5 MC |
2364 | return work_done; |
2365 | } | |
2366 | ||
0fcec985 MC |
2367 | static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) |
2368 | { | |
2369 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2370 | int i, work_done = 0; | |
2371 | ||
2372 | for (i = 0; i < 2; i++) { | |
2373 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; | |
2374 | ||
2375 | if (cpr2) { | |
2376 | work_done += __bnxt_poll_work(bp, cpr2, | |
2377 | budget - work_done); | |
2378 | cpr->has_more_work |= cpr2->has_more_work; | |
2379 | } | |
2380 | } | |
2381 | return work_done; | |
2382 | } | |
2383 | ||
2384 | static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, | |
2385 | u64 dbr_type, bool all) | |
2386 | { | |
2387 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2388 | int i; | |
2389 | ||
2390 | for (i = 0; i < 2; i++) { | |
2391 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; | |
2392 | struct bnxt_db_info *db; | |
2393 | ||
2394 | if (cpr2 && (all || cpr2->had_work_done)) { | |
2395 | db = &cpr2->cp_db; | |
2396 | writeq(db->db_key64 | dbr_type | | |
2397 | RING_CMP(cpr2->cp_raw_cons), db->doorbell); | |
2398 | cpr2->had_work_done = 0; | |
2399 | } | |
2400 | } | |
2401 | __bnxt_poll_work_done(bp, bnapi); | |
2402 | } | |
2403 | ||
2404 | static int bnxt_poll_p5(struct napi_struct *napi, int budget) | |
2405 | { | |
2406 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); | |
2407 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
2408 | u32 raw_cons = cpr->cp_raw_cons; | |
2409 | struct bnxt *bp = bnapi->bp; | |
2410 | struct nqe_cn *nqcmp; | |
2411 | int work_done = 0; | |
2412 | u32 cons; | |
2413 | ||
2414 | if (cpr->has_more_work) { | |
2415 | cpr->has_more_work = 0; | |
2416 | work_done = __bnxt_poll_cqs(bp, bnapi, budget); | |
2417 | if (cpr->has_more_work) { | |
2418 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false); | |
2419 | return work_done; | |
2420 | } | |
2421 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true); | |
2422 | if (napi_complete_done(napi, work_done)) | |
2423 | BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons); | |
2424 | return work_done; | |
2425 | } | |
2426 | while (1) { | |
2427 | cons = RING_CMP(raw_cons); | |
2428 | nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; | |
2429 | ||
2430 | if (!NQ_CMP_VALID(nqcmp, raw_cons)) { | |
2431 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, | |
2432 | false); | |
2433 | cpr->cp_raw_cons = raw_cons; | |
2434 | if (napi_complete_done(napi, work_done)) | |
2435 | BNXT_DB_NQ_ARM_P5(&cpr->cp_db, | |
2436 | cpr->cp_raw_cons); | |
2437 | return work_done; | |
2438 | } | |
2439 | ||
2440 | /* The valid test of the entry must be done first before | |
2441 | * reading any further. | |
2442 | */ | |
2443 | dma_rmb(); | |
2444 | ||
2445 | if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { | |
2446 | u32 idx = le32_to_cpu(nqcmp->cq_handle_low); | |
2447 | struct bnxt_cp_ring_info *cpr2; | |
2448 | ||
2449 | cpr2 = cpr->cp_ring_arr[idx]; | |
2450 | work_done += __bnxt_poll_work(bp, cpr2, | |
2451 | budget - work_done); | |
2452 | cpr->has_more_work = cpr2->has_more_work; | |
2453 | } else { | |
2454 | bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); | |
2455 | } | |
2456 | raw_cons = NEXT_RAW_CMP(raw_cons); | |
2457 | if (cpr->has_more_work) | |
2458 | break; | |
2459 | } | |
2460 | __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true); | |
2461 | cpr->cp_raw_cons = raw_cons; | |
2462 | return work_done; | |
2463 | } | |
2464 | ||
c0c050c5 MC |
2465 | static void bnxt_free_tx_skbs(struct bnxt *bp) |
2466 | { | |
2467 | int i, max_idx; | |
2468 | struct pci_dev *pdev = bp->pdev; | |
2469 | ||
b6ab4b01 | 2470 | if (!bp->tx_ring) |
c0c050c5 MC |
2471 | return; |
2472 | ||
2473 | max_idx = bp->tx_nr_pages * TX_DESC_CNT; | |
2474 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2475 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
2476 | int j; |
2477 | ||
c0c050c5 MC |
2478 | for (j = 0; j < max_idx;) { |
2479 | struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; | |
f18c2b77 | 2480 | struct sk_buff *skb; |
c0c050c5 MC |
2481 | int k, last; |
2482 | ||
f18c2b77 AG |
2483 | if (i < bp->tx_nr_rings_xdp && |
2484 | tx_buf->action == XDP_REDIRECT) { | |
2485 | dma_unmap_single(&pdev->dev, | |
2486 | dma_unmap_addr(tx_buf, mapping), | |
2487 | dma_unmap_len(tx_buf, len), | |
2488 | PCI_DMA_TODEVICE); | |
2489 | xdp_return_frame(tx_buf->xdpf); | |
2490 | tx_buf->action = 0; | |
2491 | tx_buf->xdpf = NULL; | |
2492 | j++; | |
2493 | continue; | |
2494 | } | |
2495 | ||
2496 | skb = tx_buf->skb; | |
c0c050c5 MC |
2497 | if (!skb) { |
2498 | j++; | |
2499 | continue; | |
2500 | } | |
2501 | ||
2502 | tx_buf->skb = NULL; | |
2503 | ||
2504 | if (tx_buf->is_push) { | |
2505 | dev_kfree_skb(skb); | |
2506 | j += 2; | |
2507 | continue; | |
2508 | } | |
2509 | ||
2510 | dma_unmap_single(&pdev->dev, | |
2511 | dma_unmap_addr(tx_buf, mapping), | |
2512 | skb_headlen(skb), | |
2513 | PCI_DMA_TODEVICE); | |
2514 | ||
2515 | last = tx_buf->nr_frags; | |
2516 | j += 2; | |
d612a579 MC |
2517 | for (k = 0; k < last; k++, j++) { |
2518 | int ring_idx = j & bp->tx_ring_mask; | |
c0c050c5 MC |
2519 | skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; |
2520 | ||
d612a579 | 2521 | tx_buf = &txr->tx_buf_ring[ring_idx]; |
c0c050c5 MC |
2522 | dma_unmap_page( |
2523 | &pdev->dev, | |
2524 | dma_unmap_addr(tx_buf, mapping), | |
2525 | skb_frag_size(frag), PCI_DMA_TODEVICE); | |
2526 | } | |
2527 | dev_kfree_skb(skb); | |
2528 | } | |
2529 | netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); | |
2530 | } | |
2531 | } | |
2532 | ||
2533 | static void bnxt_free_rx_skbs(struct bnxt *bp) | |
2534 | { | |
2535 | int i, max_idx, max_agg_idx; | |
2536 | struct pci_dev *pdev = bp->pdev; | |
2537 | ||
b6ab4b01 | 2538 | if (!bp->rx_ring) |
c0c050c5 MC |
2539 | return; |
2540 | ||
2541 | max_idx = bp->rx_nr_pages * RX_DESC_CNT; | |
2542 | max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; | |
2543 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
b6ab4b01 | 2544 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
ec4d8e7c | 2545 | struct bnxt_tpa_idx_map *map; |
c0c050c5 MC |
2546 | int j; |
2547 | ||
c0c050c5 | 2548 | if (rxr->rx_tpa) { |
79632e9b | 2549 | for (j = 0; j < bp->max_tpa; j++) { |
c0c050c5 MC |
2550 | struct bnxt_tpa_info *tpa_info = |
2551 | &rxr->rx_tpa[j]; | |
2552 | u8 *data = tpa_info->data; | |
2553 | ||
2554 | if (!data) | |
2555 | continue; | |
2556 | ||
c519fe9a SN |
2557 | dma_unmap_single_attrs(&pdev->dev, |
2558 | tpa_info->mapping, | |
2559 | bp->rx_buf_use_size, | |
2560 | bp->rx_dir, | |
2561 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
2562 | |
2563 | tpa_info->data = NULL; | |
2564 | ||
2565 | kfree(data); | |
2566 | } | |
2567 | } | |
2568 | ||
2569 | for (j = 0; j < max_idx; j++) { | |
2570 | struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; | |
3ed3a83e | 2571 | dma_addr_t mapping = rx_buf->mapping; |
6bb19474 | 2572 | void *data = rx_buf->data; |
c0c050c5 MC |
2573 | |
2574 | if (!data) | |
2575 | continue; | |
2576 | ||
c0c050c5 MC |
2577 | rx_buf->data = NULL; |
2578 | ||
3ed3a83e MC |
2579 | if (BNXT_RX_PAGE_MODE(bp)) { |
2580 | mapping -= bp->rx_dma_offset; | |
c519fe9a SN |
2581 | dma_unmap_page_attrs(&pdev->dev, mapping, |
2582 | PAGE_SIZE, bp->rx_dir, | |
2583 | DMA_ATTR_WEAK_ORDERING); | |
322b87ca | 2584 | page_pool_recycle_direct(rxr->page_pool, data); |
3ed3a83e | 2585 | } else { |
c519fe9a SN |
2586 | dma_unmap_single_attrs(&pdev->dev, mapping, |
2587 | bp->rx_buf_use_size, | |
2588 | bp->rx_dir, | |
2589 | DMA_ATTR_WEAK_ORDERING); | |
c61fb99c | 2590 | kfree(data); |
3ed3a83e | 2591 | } |
c0c050c5 MC |
2592 | } |
2593 | ||
2594 | for (j = 0; j < max_agg_idx; j++) { | |
2595 | struct bnxt_sw_rx_agg_bd *rx_agg_buf = | |
2596 | &rxr->rx_agg_ring[j]; | |
2597 | struct page *page = rx_agg_buf->page; | |
2598 | ||
2599 | if (!page) | |
2600 | continue; | |
2601 | ||
c519fe9a SN |
2602 | dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, |
2603 | BNXT_RX_PAGE_SIZE, | |
2604 | PCI_DMA_FROMDEVICE, | |
2605 | DMA_ATTR_WEAK_ORDERING); | |
c0c050c5 MC |
2606 | |
2607 | rx_agg_buf->page = NULL; | |
2608 | __clear_bit(j, rxr->rx_agg_bmap); | |
2609 | ||
2610 | __free_page(page); | |
2611 | } | |
89d0a06c MC |
2612 | if (rxr->rx_page) { |
2613 | __free_page(rxr->rx_page); | |
2614 | rxr->rx_page = NULL; | |
2615 | } | |
ec4d8e7c MC |
2616 | map = rxr->rx_tpa_idx_map; |
2617 | if (map) | |
2618 | memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); | |
c0c050c5 MC |
2619 | } |
2620 | } | |
2621 | ||
2622 | static void bnxt_free_skbs(struct bnxt *bp) | |
2623 | { | |
2624 | bnxt_free_tx_skbs(bp); | |
2625 | bnxt_free_rx_skbs(bp); | |
2626 | } | |
2627 | ||
6fe19886 | 2628 | static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) |
c0c050c5 MC |
2629 | { |
2630 | struct pci_dev *pdev = bp->pdev; | |
2631 | int i; | |
2632 | ||
6fe19886 MC |
2633 | for (i = 0; i < rmem->nr_pages; i++) { |
2634 | if (!rmem->pg_arr[i]) | |
c0c050c5 MC |
2635 | continue; |
2636 | ||
6fe19886 MC |
2637 | dma_free_coherent(&pdev->dev, rmem->page_size, |
2638 | rmem->pg_arr[i], rmem->dma_arr[i]); | |
c0c050c5 | 2639 | |
6fe19886 | 2640 | rmem->pg_arr[i] = NULL; |
c0c050c5 | 2641 | } |
6fe19886 | 2642 | if (rmem->pg_tbl) { |
4f49b2b8 MC |
2643 | size_t pg_tbl_size = rmem->nr_pages * 8; |
2644 | ||
2645 | if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) | |
2646 | pg_tbl_size = rmem->page_size; | |
2647 | dma_free_coherent(&pdev->dev, pg_tbl_size, | |
6fe19886 MC |
2648 | rmem->pg_tbl, rmem->pg_tbl_map); |
2649 | rmem->pg_tbl = NULL; | |
c0c050c5 | 2650 | } |
6fe19886 MC |
2651 | if (rmem->vmem_size && *rmem->vmem) { |
2652 | vfree(*rmem->vmem); | |
2653 | *rmem->vmem = NULL; | |
c0c050c5 MC |
2654 | } |
2655 | } | |
2656 | ||
6fe19886 | 2657 | static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) |
c0c050c5 | 2658 | { |
c0c050c5 | 2659 | struct pci_dev *pdev = bp->pdev; |
66cca20a | 2660 | u64 valid_bit = 0; |
6fe19886 | 2661 | int i; |
c0c050c5 | 2662 | |
66cca20a MC |
2663 | if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) |
2664 | valid_bit = PTU_PTE_VALID; | |
4f49b2b8 MC |
2665 | if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { |
2666 | size_t pg_tbl_size = rmem->nr_pages * 8; | |
2667 | ||
2668 | if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) | |
2669 | pg_tbl_size = rmem->page_size; | |
2670 | rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, | |
6fe19886 | 2671 | &rmem->pg_tbl_map, |
c0c050c5 | 2672 | GFP_KERNEL); |
6fe19886 | 2673 | if (!rmem->pg_tbl) |
c0c050c5 MC |
2674 | return -ENOMEM; |
2675 | } | |
2676 | ||
6fe19886 | 2677 | for (i = 0; i < rmem->nr_pages; i++) { |
66cca20a MC |
2678 | u64 extra_bits = valid_bit; |
2679 | ||
6fe19886 MC |
2680 | rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, |
2681 | rmem->page_size, | |
2682 | &rmem->dma_arr[i], | |
c0c050c5 | 2683 | GFP_KERNEL); |
6fe19886 | 2684 | if (!rmem->pg_arr[i]) |
c0c050c5 MC |
2685 | return -ENOMEM; |
2686 | ||
4f49b2b8 | 2687 | if (rmem->nr_pages > 1 || rmem->depth > 0) { |
66cca20a MC |
2688 | if (i == rmem->nr_pages - 2 && |
2689 | (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) | |
2690 | extra_bits |= PTU_PTE_NEXT_TO_LAST; | |
2691 | else if (i == rmem->nr_pages - 1 && | |
2692 | (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) | |
2693 | extra_bits |= PTU_PTE_LAST; | |
2694 | rmem->pg_tbl[i] = | |
2695 | cpu_to_le64(rmem->dma_arr[i] | extra_bits); | |
2696 | } | |
c0c050c5 MC |
2697 | } |
2698 | ||
6fe19886 MC |
2699 | if (rmem->vmem_size) { |
2700 | *rmem->vmem = vzalloc(rmem->vmem_size); | |
2701 | if (!(*rmem->vmem)) | |
c0c050c5 MC |
2702 | return -ENOMEM; |
2703 | } | |
2704 | return 0; | |
2705 | } | |
2706 | ||
4a228a3a MC |
2707 | static void bnxt_free_tpa_info(struct bnxt *bp) |
2708 | { | |
2709 | int i; | |
2710 | ||
2711 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
2712 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
2713 | ||
ec4d8e7c MC |
2714 | kfree(rxr->rx_tpa_idx_map); |
2715 | rxr->rx_tpa_idx_map = NULL; | |
79632e9b MC |
2716 | if (rxr->rx_tpa) { |
2717 | kfree(rxr->rx_tpa[0].agg_arr); | |
2718 | rxr->rx_tpa[0].agg_arr = NULL; | |
2719 | } | |
4a228a3a MC |
2720 | kfree(rxr->rx_tpa); |
2721 | rxr->rx_tpa = NULL; | |
2722 | } | |
2723 | } | |
2724 | ||
2725 | static int bnxt_alloc_tpa_info(struct bnxt *bp) | |
2726 | { | |
79632e9b MC |
2727 | int i, j, total_aggs = 0; |
2728 | ||
2729 | bp->max_tpa = MAX_TPA; | |
2730 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
2731 | if (!bp->max_tpa_v2) | |
2732 | return 0; | |
2733 | bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); | |
2734 | total_aggs = bp->max_tpa * MAX_SKB_FRAGS; | |
2735 | } | |
4a228a3a MC |
2736 | |
2737 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
2738 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
79632e9b | 2739 | struct rx_agg_cmp *agg; |
4a228a3a | 2740 | |
79632e9b | 2741 | rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), |
4a228a3a MC |
2742 | GFP_KERNEL); |
2743 | if (!rxr->rx_tpa) | |
2744 | return -ENOMEM; | |
79632e9b MC |
2745 | |
2746 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
2747 | continue; | |
2748 | agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL); | |
2749 | rxr->rx_tpa[0].agg_arr = agg; | |
2750 | if (!agg) | |
2751 | return -ENOMEM; | |
2752 | for (j = 1; j < bp->max_tpa; j++) | |
2753 | rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS; | |
ec4d8e7c MC |
2754 | rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), |
2755 | GFP_KERNEL); | |
2756 | if (!rxr->rx_tpa_idx_map) | |
2757 | return -ENOMEM; | |
4a228a3a MC |
2758 | } |
2759 | return 0; | |
2760 | } | |
2761 | ||
c0c050c5 MC |
2762 | static void bnxt_free_rx_rings(struct bnxt *bp) |
2763 | { | |
2764 | int i; | |
2765 | ||
b6ab4b01 | 2766 | if (!bp->rx_ring) |
c0c050c5 MC |
2767 | return; |
2768 | ||
4a228a3a | 2769 | bnxt_free_tpa_info(bp); |
c0c050c5 | 2770 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 2771 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
2772 | struct bnxt_ring_struct *ring; |
2773 | ||
c6d30e83 MC |
2774 | if (rxr->xdp_prog) |
2775 | bpf_prog_put(rxr->xdp_prog); | |
2776 | ||
96a8604f JDB |
2777 | if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) |
2778 | xdp_rxq_info_unreg(&rxr->xdp_rxq); | |
2779 | ||
12479f62 | 2780 | page_pool_destroy(rxr->page_pool); |
322b87ca AG |
2781 | rxr->page_pool = NULL; |
2782 | ||
c0c050c5 MC |
2783 | kfree(rxr->rx_agg_bmap); |
2784 | rxr->rx_agg_bmap = NULL; | |
2785 | ||
2786 | ring = &rxr->rx_ring_struct; | |
6fe19886 | 2787 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2788 | |
2789 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 | 2790 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2791 | } |
2792 | } | |
2793 | ||
322b87ca AG |
2794 | static int bnxt_alloc_rx_page_pool(struct bnxt *bp, |
2795 | struct bnxt_rx_ring_info *rxr) | |
2796 | { | |
2797 | struct page_pool_params pp = { 0 }; | |
2798 | ||
2799 | pp.pool_size = bp->rx_ring_size; | |
2800 | pp.nid = dev_to_node(&bp->pdev->dev); | |
2801 | pp.dev = &bp->pdev->dev; | |
2802 | pp.dma_dir = DMA_BIDIRECTIONAL; | |
2803 | ||
2804 | rxr->page_pool = page_pool_create(&pp); | |
2805 | if (IS_ERR(rxr->page_pool)) { | |
2806 | int err = PTR_ERR(rxr->page_pool); | |
2807 | ||
2808 | rxr->page_pool = NULL; | |
2809 | return err; | |
2810 | } | |
2811 | return 0; | |
2812 | } | |
2813 | ||
c0c050c5 MC |
2814 | static int bnxt_alloc_rx_rings(struct bnxt *bp) |
2815 | { | |
4a228a3a | 2816 | int i, rc = 0, agg_rings = 0; |
c0c050c5 | 2817 | |
b6ab4b01 MC |
2818 | if (!bp->rx_ring) |
2819 | return -ENOMEM; | |
2820 | ||
c0c050c5 MC |
2821 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
2822 | agg_rings = 1; | |
2823 | ||
c0c050c5 | 2824 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 2825 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
2826 | struct bnxt_ring_struct *ring; |
2827 | ||
c0c050c5 MC |
2828 | ring = &rxr->rx_ring_struct; |
2829 | ||
322b87ca AG |
2830 | rc = bnxt_alloc_rx_page_pool(bp, rxr); |
2831 | if (rc) | |
2832 | return rc; | |
2833 | ||
96a8604f | 2834 | rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); |
12479f62 | 2835 | if (rc < 0) |
96a8604f JDB |
2836 | return rc; |
2837 | ||
f18c2b77 | 2838 | rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, |
322b87ca AG |
2839 | MEM_TYPE_PAGE_POOL, |
2840 | rxr->page_pool); | |
f18c2b77 AG |
2841 | if (rc) { |
2842 | xdp_rxq_info_unreg(&rxr->xdp_rxq); | |
2843 | return rc; | |
2844 | } | |
2845 | ||
6fe19886 | 2846 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2847 | if (rc) |
2848 | return rc; | |
2849 | ||
2c61d211 | 2850 | ring->grp_idx = i; |
c0c050c5 MC |
2851 | if (agg_rings) { |
2852 | u16 mem_size; | |
2853 | ||
2854 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 | 2855 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2856 | if (rc) |
2857 | return rc; | |
2858 | ||
9899bb59 | 2859 | ring->grp_idx = i; |
c0c050c5 MC |
2860 | rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; |
2861 | mem_size = rxr->rx_agg_bmap_size / 8; | |
2862 | rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); | |
2863 | if (!rxr->rx_agg_bmap) | |
2864 | return -ENOMEM; | |
c0c050c5 MC |
2865 | } |
2866 | } | |
4a228a3a MC |
2867 | if (bp->flags & BNXT_FLAG_TPA) |
2868 | rc = bnxt_alloc_tpa_info(bp); | |
2869 | return rc; | |
c0c050c5 MC |
2870 | } |
2871 | ||
2872 | static void bnxt_free_tx_rings(struct bnxt *bp) | |
2873 | { | |
2874 | int i; | |
2875 | struct pci_dev *pdev = bp->pdev; | |
2876 | ||
b6ab4b01 | 2877 | if (!bp->tx_ring) |
c0c050c5 MC |
2878 | return; |
2879 | ||
2880 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2881 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
2882 | struct bnxt_ring_struct *ring; |
2883 | ||
c0c050c5 MC |
2884 | if (txr->tx_push) { |
2885 | dma_free_coherent(&pdev->dev, bp->tx_push_size, | |
2886 | txr->tx_push, txr->tx_push_mapping); | |
2887 | txr->tx_push = NULL; | |
2888 | } | |
2889 | ||
2890 | ring = &txr->tx_ring_struct; | |
2891 | ||
6fe19886 | 2892 | bnxt_free_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2893 | } |
2894 | } | |
2895 | ||
2896 | static int bnxt_alloc_tx_rings(struct bnxt *bp) | |
2897 | { | |
2898 | int i, j, rc; | |
2899 | struct pci_dev *pdev = bp->pdev; | |
2900 | ||
2901 | bp->tx_push_size = 0; | |
2902 | if (bp->tx_push_thresh) { | |
2903 | int push_size; | |
2904 | ||
2905 | push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + | |
2906 | bp->tx_push_thresh); | |
2907 | ||
4419dbe6 | 2908 | if (push_size > 256) { |
c0c050c5 MC |
2909 | push_size = 0; |
2910 | bp->tx_push_thresh = 0; | |
2911 | } | |
2912 | ||
2913 | bp->tx_push_size = push_size; | |
2914 | } | |
2915 | ||
2916 | for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 2917 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 | 2918 | struct bnxt_ring_struct *ring; |
2e8ef77e | 2919 | u8 qidx; |
c0c050c5 | 2920 | |
c0c050c5 MC |
2921 | ring = &txr->tx_ring_struct; |
2922 | ||
6fe19886 | 2923 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
2924 | if (rc) |
2925 | return rc; | |
2926 | ||
9899bb59 | 2927 | ring->grp_idx = txr->bnapi->index; |
c0c050c5 | 2928 | if (bp->tx_push_size) { |
c0c050c5 MC |
2929 | dma_addr_t mapping; |
2930 | ||
2931 | /* One pre-allocated DMA buffer to backup | |
2932 | * TX push operation | |
2933 | */ | |
2934 | txr->tx_push = dma_alloc_coherent(&pdev->dev, | |
2935 | bp->tx_push_size, | |
2936 | &txr->tx_push_mapping, | |
2937 | GFP_KERNEL); | |
2938 | ||
2939 | if (!txr->tx_push) | |
2940 | return -ENOMEM; | |
2941 | ||
c0c050c5 MC |
2942 | mapping = txr->tx_push_mapping + |
2943 | sizeof(struct tx_push_bd); | |
4419dbe6 | 2944 | txr->data_mapping = cpu_to_le64(mapping); |
c0c050c5 | 2945 | } |
2e8ef77e MC |
2946 | qidx = bp->tc_to_qidx[j]; |
2947 | ring->queue_id = bp->q_info[qidx].queue_id; | |
5f449249 MC |
2948 | if (i < bp->tx_nr_rings_xdp) |
2949 | continue; | |
c0c050c5 MC |
2950 | if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) |
2951 | j++; | |
2952 | } | |
2953 | return 0; | |
2954 | } | |
2955 | ||
2956 | static void bnxt_free_cp_rings(struct bnxt *bp) | |
2957 | { | |
2958 | int i; | |
2959 | ||
2960 | if (!bp->bnapi) | |
2961 | return; | |
2962 | ||
2963 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
2964 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
2965 | struct bnxt_cp_ring_info *cpr; | |
2966 | struct bnxt_ring_struct *ring; | |
50e3ab78 | 2967 | int j; |
c0c050c5 MC |
2968 | |
2969 | if (!bnapi) | |
2970 | continue; | |
2971 | ||
2972 | cpr = &bnapi->cp_ring; | |
2973 | ring = &cpr->cp_ring_struct; | |
2974 | ||
6fe19886 | 2975 | bnxt_free_ring(bp, &ring->ring_mem); |
50e3ab78 MC |
2976 | |
2977 | for (j = 0; j < 2; j++) { | |
2978 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
2979 | ||
2980 | if (cpr2) { | |
2981 | ring = &cpr2->cp_ring_struct; | |
2982 | bnxt_free_ring(bp, &ring->ring_mem); | |
2983 | kfree(cpr2); | |
2984 | cpr->cp_ring_arr[j] = NULL; | |
2985 | } | |
2986 | } | |
c0c050c5 MC |
2987 | } |
2988 | } | |
2989 | ||
50e3ab78 MC |
2990 | static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) |
2991 | { | |
2992 | struct bnxt_ring_mem_info *rmem; | |
2993 | struct bnxt_ring_struct *ring; | |
2994 | struct bnxt_cp_ring_info *cpr; | |
2995 | int rc; | |
2996 | ||
2997 | cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); | |
2998 | if (!cpr) | |
2999 | return NULL; | |
3000 | ||
3001 | ring = &cpr->cp_ring_struct; | |
3002 | rmem = &ring->ring_mem; | |
3003 | rmem->nr_pages = bp->cp_nr_pages; | |
3004 | rmem->page_size = HW_CMPD_RING_SIZE; | |
3005 | rmem->pg_arr = (void **)cpr->cp_desc_ring; | |
3006 | rmem->dma_arr = cpr->cp_desc_mapping; | |
3007 | rmem->flags = BNXT_RMEM_RING_PTE_FLAG; | |
3008 | rc = bnxt_alloc_ring(bp, rmem); | |
3009 | if (rc) { | |
3010 | bnxt_free_ring(bp, rmem); | |
3011 | kfree(cpr); | |
3012 | cpr = NULL; | |
3013 | } | |
3014 | return cpr; | |
3015 | } | |
3016 | ||
c0c050c5 MC |
3017 | static int bnxt_alloc_cp_rings(struct bnxt *bp) |
3018 | { | |
50e3ab78 | 3019 | bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); |
e5811b8c | 3020 | int i, rc, ulp_base_vec, ulp_msix; |
c0c050c5 | 3021 | |
e5811b8c MC |
3022 | ulp_msix = bnxt_get_ulp_msix_num(bp); |
3023 | ulp_base_vec = bnxt_get_ulp_msix_base(bp); | |
c0c050c5 MC |
3024 | for (i = 0; i < bp->cp_nr_rings; i++) { |
3025 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3026 | struct bnxt_cp_ring_info *cpr; | |
3027 | struct bnxt_ring_struct *ring; | |
3028 | ||
3029 | if (!bnapi) | |
3030 | continue; | |
3031 | ||
3032 | cpr = &bnapi->cp_ring; | |
50e3ab78 | 3033 | cpr->bnapi = bnapi; |
c0c050c5 MC |
3034 | ring = &cpr->cp_ring_struct; |
3035 | ||
6fe19886 | 3036 | rc = bnxt_alloc_ring(bp, &ring->ring_mem); |
c0c050c5 MC |
3037 | if (rc) |
3038 | return rc; | |
e5811b8c MC |
3039 | |
3040 | if (ulp_msix && i >= ulp_base_vec) | |
3041 | ring->map_idx = i + ulp_msix; | |
3042 | else | |
3043 | ring->map_idx = i; | |
50e3ab78 MC |
3044 | |
3045 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
3046 | continue; | |
3047 | ||
3048 | if (i < bp->rx_nr_rings) { | |
3049 | struct bnxt_cp_ring_info *cpr2 = | |
3050 | bnxt_alloc_cp_sub_ring(bp); | |
3051 | ||
3052 | cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; | |
3053 | if (!cpr2) | |
3054 | return -ENOMEM; | |
3055 | cpr2->bnapi = bnapi; | |
3056 | } | |
3057 | if ((sh && i < bp->tx_nr_rings) || | |
3058 | (!sh && i >= bp->rx_nr_rings)) { | |
3059 | struct bnxt_cp_ring_info *cpr2 = | |
3060 | bnxt_alloc_cp_sub_ring(bp); | |
3061 | ||
3062 | cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; | |
3063 | if (!cpr2) | |
3064 | return -ENOMEM; | |
3065 | cpr2->bnapi = bnapi; | |
3066 | } | |
c0c050c5 MC |
3067 | } |
3068 | return 0; | |
3069 | } | |
3070 | ||
3071 | static void bnxt_init_ring_struct(struct bnxt *bp) | |
3072 | { | |
3073 | int i; | |
3074 | ||
3075 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3076 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6fe19886 | 3077 | struct bnxt_ring_mem_info *rmem; |
c0c050c5 MC |
3078 | struct bnxt_cp_ring_info *cpr; |
3079 | struct bnxt_rx_ring_info *rxr; | |
3080 | struct bnxt_tx_ring_info *txr; | |
3081 | struct bnxt_ring_struct *ring; | |
3082 | ||
3083 | if (!bnapi) | |
3084 | continue; | |
3085 | ||
3086 | cpr = &bnapi->cp_ring; | |
3087 | ring = &cpr->cp_ring_struct; | |
6fe19886 MC |
3088 | rmem = &ring->ring_mem; |
3089 | rmem->nr_pages = bp->cp_nr_pages; | |
3090 | rmem->page_size = HW_CMPD_RING_SIZE; | |
3091 | rmem->pg_arr = (void **)cpr->cp_desc_ring; | |
3092 | rmem->dma_arr = cpr->cp_desc_mapping; | |
3093 | rmem->vmem_size = 0; | |
c0c050c5 | 3094 | |
b6ab4b01 | 3095 | rxr = bnapi->rx_ring; |
3b2b7d9d MC |
3096 | if (!rxr) |
3097 | goto skip_rx; | |
3098 | ||
c0c050c5 | 3099 | ring = &rxr->rx_ring_struct; |
6fe19886 MC |
3100 | rmem = &ring->ring_mem; |
3101 | rmem->nr_pages = bp->rx_nr_pages; | |
3102 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3103 | rmem->pg_arr = (void **)rxr->rx_desc_ring; | |
3104 | rmem->dma_arr = rxr->rx_desc_mapping; | |
3105 | rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; | |
3106 | rmem->vmem = (void **)&rxr->rx_buf_ring; | |
c0c050c5 MC |
3107 | |
3108 | ring = &rxr->rx_agg_ring_struct; | |
6fe19886 MC |
3109 | rmem = &ring->ring_mem; |
3110 | rmem->nr_pages = bp->rx_agg_nr_pages; | |
3111 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3112 | rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; | |
3113 | rmem->dma_arr = rxr->rx_agg_desc_mapping; | |
3114 | rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; | |
3115 | rmem->vmem = (void **)&rxr->rx_agg_ring; | |
c0c050c5 | 3116 | |
3b2b7d9d | 3117 | skip_rx: |
b6ab4b01 | 3118 | txr = bnapi->tx_ring; |
3b2b7d9d MC |
3119 | if (!txr) |
3120 | continue; | |
3121 | ||
c0c050c5 | 3122 | ring = &txr->tx_ring_struct; |
6fe19886 MC |
3123 | rmem = &ring->ring_mem; |
3124 | rmem->nr_pages = bp->tx_nr_pages; | |
3125 | rmem->page_size = HW_RXBD_RING_SIZE; | |
3126 | rmem->pg_arr = (void **)txr->tx_desc_ring; | |
3127 | rmem->dma_arr = txr->tx_desc_mapping; | |
3128 | rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; | |
3129 | rmem->vmem = (void **)&txr->tx_buf_ring; | |
c0c050c5 MC |
3130 | } |
3131 | } | |
3132 | ||
3133 | static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) | |
3134 | { | |
3135 | int i; | |
3136 | u32 prod; | |
3137 | struct rx_bd **rx_buf_ring; | |
3138 | ||
6fe19886 MC |
3139 | rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; |
3140 | for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { | |
c0c050c5 MC |
3141 | int j; |
3142 | struct rx_bd *rxbd; | |
3143 | ||
3144 | rxbd = rx_buf_ring[i]; | |
3145 | if (!rxbd) | |
3146 | continue; | |
3147 | ||
3148 | for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { | |
3149 | rxbd->rx_bd_len_flags_type = cpu_to_le32(type); | |
3150 | rxbd->rx_bd_opaque = prod; | |
3151 | } | |
3152 | } | |
3153 | } | |
3154 | ||
3155 | static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) | |
3156 | { | |
3157 | struct net_device *dev = bp->dev; | |
c0c050c5 MC |
3158 | struct bnxt_rx_ring_info *rxr; |
3159 | struct bnxt_ring_struct *ring; | |
3160 | u32 prod, type; | |
3161 | int i; | |
3162 | ||
c0c050c5 MC |
3163 | type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | |
3164 | RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; | |
3165 | ||
3166 | if (NET_IP_ALIGN == 2) | |
3167 | type |= RX_BD_FLAGS_SOP; | |
3168 | ||
b6ab4b01 | 3169 | rxr = &bp->rx_ring[ring_nr]; |
c0c050c5 MC |
3170 | ring = &rxr->rx_ring_struct; |
3171 | bnxt_init_rxbd_pages(ring, type); | |
3172 | ||
c6d30e83 MC |
3173 | if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { |
3174 | rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1); | |
3175 | if (IS_ERR(rxr->xdp_prog)) { | |
3176 | int rc = PTR_ERR(rxr->xdp_prog); | |
3177 | ||
3178 | rxr->xdp_prog = NULL; | |
3179 | return rc; | |
3180 | } | |
3181 | } | |
c0c050c5 MC |
3182 | prod = rxr->rx_prod; |
3183 | for (i = 0; i < bp->rx_ring_size; i++) { | |
3184 | if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { | |
3185 | netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", | |
3186 | ring_nr, i, bp->rx_ring_size); | |
3187 | break; | |
3188 | } | |
3189 | prod = NEXT_RX(prod); | |
3190 | } | |
3191 | rxr->rx_prod = prod; | |
3192 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3193 | ||
edd0c2cc MC |
3194 | ring = &rxr->rx_agg_ring_struct; |
3195 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3196 | ||
c0c050c5 MC |
3197 | if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) |
3198 | return 0; | |
3199 | ||
2839f28b | 3200 | type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | |
c0c050c5 MC |
3201 | RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; |
3202 | ||
3203 | bnxt_init_rxbd_pages(ring, type); | |
3204 | ||
3205 | prod = rxr->rx_agg_prod; | |
3206 | for (i = 0; i < bp->rx_agg_ring_size; i++) { | |
3207 | if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { | |
3208 | netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", | |
3209 | ring_nr, i, bp->rx_ring_size); | |
3210 | break; | |
3211 | } | |
3212 | prod = NEXT_RX_AGG(prod); | |
3213 | } | |
3214 | rxr->rx_agg_prod = prod; | |
c0c050c5 MC |
3215 | |
3216 | if (bp->flags & BNXT_FLAG_TPA) { | |
3217 | if (rxr->rx_tpa) { | |
3218 | u8 *data; | |
3219 | dma_addr_t mapping; | |
3220 | ||
79632e9b | 3221 | for (i = 0; i < bp->max_tpa; i++) { |
c0c050c5 MC |
3222 | data = __bnxt_alloc_rx_data(bp, &mapping, |
3223 | GFP_KERNEL); | |
3224 | if (!data) | |
3225 | return -ENOMEM; | |
3226 | ||
3227 | rxr->rx_tpa[i].data = data; | |
b3dba77c | 3228 | rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; |
c0c050c5 MC |
3229 | rxr->rx_tpa[i].mapping = mapping; |
3230 | } | |
3231 | } else { | |
3232 | netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); | |
3233 | return -ENOMEM; | |
3234 | } | |
3235 | } | |
3236 | ||
3237 | return 0; | |
3238 | } | |
3239 | ||
2247925f SP |
3240 | static void bnxt_init_cp_rings(struct bnxt *bp) |
3241 | { | |
3e08b184 | 3242 | int i, j; |
2247925f SP |
3243 | |
3244 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3245 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; | |
3246 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
3247 | ||
3248 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
6a8788f2 AG |
3249 | cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; |
3250 | cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; | |
3e08b184 MC |
3251 | for (j = 0; j < 2; j++) { |
3252 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
3253 | ||
3254 | if (!cpr2) | |
3255 | continue; | |
3256 | ||
3257 | ring = &cpr2->cp_ring_struct; | |
3258 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3259 | cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; | |
3260 | cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; | |
3261 | } | |
2247925f SP |
3262 | } |
3263 | } | |
3264 | ||
c0c050c5 MC |
3265 | static int bnxt_init_rx_rings(struct bnxt *bp) |
3266 | { | |
3267 | int i, rc = 0; | |
3268 | ||
c61fb99c | 3269 | if (BNXT_RX_PAGE_MODE(bp)) { |
c6d30e83 MC |
3270 | bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; |
3271 | bp->rx_dma_offset = XDP_PACKET_HEADROOM; | |
c61fb99c MC |
3272 | } else { |
3273 | bp->rx_offset = BNXT_RX_OFFSET; | |
3274 | bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; | |
3275 | } | |
b3dba77c | 3276 | |
c0c050c5 MC |
3277 | for (i = 0; i < bp->rx_nr_rings; i++) { |
3278 | rc = bnxt_init_one_rx_ring(bp, i); | |
3279 | if (rc) | |
3280 | break; | |
3281 | } | |
3282 | ||
3283 | return rc; | |
3284 | } | |
3285 | ||
3286 | static int bnxt_init_tx_rings(struct bnxt *bp) | |
3287 | { | |
3288 | u16 i; | |
3289 | ||
3290 | bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, | |
3291 | MAX_SKB_FRAGS + 1); | |
3292 | ||
3293 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 3294 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
c0c050c5 MC |
3295 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
3296 | ||
3297 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
3298 | } | |
3299 | ||
3300 | return 0; | |
3301 | } | |
3302 | ||
3303 | static void bnxt_free_ring_grps(struct bnxt *bp) | |
3304 | { | |
3305 | kfree(bp->grp_info); | |
3306 | bp->grp_info = NULL; | |
3307 | } | |
3308 | ||
3309 | static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) | |
3310 | { | |
3311 | int i; | |
3312 | ||
3313 | if (irq_re_init) { | |
3314 | bp->grp_info = kcalloc(bp->cp_nr_rings, | |
3315 | sizeof(struct bnxt_ring_grp_info), | |
3316 | GFP_KERNEL); | |
3317 | if (!bp->grp_info) | |
3318 | return -ENOMEM; | |
3319 | } | |
3320 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3321 | if (irq_re_init) | |
3322 | bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; | |
3323 | bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; | |
3324 | bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; | |
3325 | bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; | |
3326 | bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; | |
3327 | } | |
3328 | return 0; | |
3329 | } | |
3330 | ||
3331 | static void bnxt_free_vnics(struct bnxt *bp) | |
3332 | { | |
3333 | kfree(bp->vnic_info); | |
3334 | bp->vnic_info = NULL; | |
3335 | bp->nr_vnics = 0; | |
3336 | } | |
3337 | ||
3338 | static int bnxt_alloc_vnics(struct bnxt *bp) | |
3339 | { | |
3340 | int num_vnics = 1; | |
3341 | ||
3342 | #ifdef CONFIG_RFS_ACCEL | |
9b3d15e6 | 3343 | if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) |
c0c050c5 MC |
3344 | num_vnics += bp->rx_nr_rings; |
3345 | #endif | |
3346 | ||
dc52c6c7 PS |
3347 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
3348 | num_vnics++; | |
3349 | ||
c0c050c5 MC |
3350 | bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), |
3351 | GFP_KERNEL); | |
3352 | if (!bp->vnic_info) | |
3353 | return -ENOMEM; | |
3354 | ||
3355 | bp->nr_vnics = num_vnics; | |
3356 | return 0; | |
3357 | } | |
3358 | ||
3359 | static void bnxt_init_vnics(struct bnxt *bp) | |
3360 | { | |
3361 | int i; | |
3362 | ||
3363 | for (i = 0; i < bp->nr_vnics; i++) { | |
3364 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
44c6f72a | 3365 | int j; |
c0c050c5 MC |
3366 | |
3367 | vnic->fw_vnic_id = INVALID_HW_RING_ID; | |
44c6f72a MC |
3368 | for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) |
3369 | vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; | |
3370 | ||
c0c050c5 MC |
3371 | vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; |
3372 | ||
3373 | if (bp->vnic_info[i].rss_hash_key) { | |
3374 | if (i == 0) | |
3375 | prandom_bytes(vnic->rss_hash_key, | |
3376 | HW_HASH_KEY_SIZE); | |
3377 | else | |
3378 | memcpy(vnic->rss_hash_key, | |
3379 | bp->vnic_info[0].rss_hash_key, | |
3380 | HW_HASH_KEY_SIZE); | |
3381 | } | |
3382 | } | |
3383 | } | |
3384 | ||
3385 | static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) | |
3386 | { | |
3387 | int pages; | |
3388 | ||
3389 | pages = ring_size / desc_per_pg; | |
3390 | ||
3391 | if (!pages) | |
3392 | return 1; | |
3393 | ||
3394 | pages++; | |
3395 | ||
3396 | while (pages & (pages - 1)) | |
3397 | pages++; | |
3398 | ||
3399 | return pages; | |
3400 | } | |
3401 | ||
c6d30e83 | 3402 | void bnxt_set_tpa_flags(struct bnxt *bp) |
c0c050c5 MC |
3403 | { |
3404 | bp->flags &= ~BNXT_FLAG_TPA; | |
341138c3 MC |
3405 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
3406 | return; | |
c0c050c5 MC |
3407 | if (bp->dev->features & NETIF_F_LRO) |
3408 | bp->flags |= BNXT_FLAG_LRO; | |
1054aee8 | 3409 | else if (bp->dev->features & NETIF_F_GRO_HW) |
c0c050c5 MC |
3410 | bp->flags |= BNXT_FLAG_GRO; |
3411 | } | |
3412 | ||
3413 | /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must | |
3414 | * be set on entry. | |
3415 | */ | |
3416 | void bnxt_set_ring_params(struct bnxt *bp) | |
3417 | { | |
3418 | u32 ring_size, rx_size, rx_space; | |
3419 | u32 agg_factor = 0, agg_ring_size = 0; | |
3420 | ||
3421 | /* 8 for CRC and VLAN */ | |
3422 | rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); | |
3423 | ||
3424 | rx_space = rx_size + NET_SKB_PAD + | |
3425 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
3426 | ||
3427 | bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; | |
3428 | ring_size = bp->rx_ring_size; | |
3429 | bp->rx_agg_ring_size = 0; | |
3430 | bp->rx_agg_nr_pages = 0; | |
3431 | ||
3432 | if (bp->flags & BNXT_FLAG_TPA) | |
2839f28b | 3433 | agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); |
c0c050c5 MC |
3434 | |
3435 | bp->flags &= ~BNXT_FLAG_JUMBO; | |
bdbd1eb5 | 3436 | if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { |
c0c050c5 MC |
3437 | u32 jumbo_factor; |
3438 | ||
3439 | bp->flags |= BNXT_FLAG_JUMBO; | |
3440 | jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; | |
3441 | if (jumbo_factor > agg_factor) | |
3442 | agg_factor = jumbo_factor; | |
3443 | } | |
3444 | agg_ring_size = ring_size * agg_factor; | |
3445 | ||
3446 | if (agg_ring_size) { | |
3447 | bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, | |
3448 | RX_DESC_CNT); | |
3449 | if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { | |
3450 | u32 tmp = agg_ring_size; | |
3451 | ||
3452 | bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; | |
3453 | agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; | |
3454 | netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", | |
3455 | tmp, agg_ring_size); | |
3456 | } | |
3457 | bp->rx_agg_ring_size = agg_ring_size; | |
3458 | bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; | |
3459 | rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); | |
3460 | rx_space = rx_size + NET_SKB_PAD + | |
3461 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
3462 | } | |
3463 | ||
3464 | bp->rx_buf_use_size = rx_size; | |
3465 | bp->rx_buf_size = rx_space; | |
3466 | ||
3467 | bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); | |
3468 | bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; | |
3469 | ||
3470 | ring_size = bp->tx_ring_size; | |
3471 | bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); | |
3472 | bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; | |
3473 | ||
3474 | ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; | |
3475 | bp->cp_ring_size = ring_size; | |
3476 | ||
3477 | bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); | |
3478 | if (bp->cp_nr_pages > MAX_CP_PAGES) { | |
3479 | bp->cp_nr_pages = MAX_CP_PAGES; | |
3480 | bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; | |
3481 | netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", | |
3482 | ring_size, bp->cp_ring_size); | |
3483 | } | |
3484 | bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; | |
3485 | bp->cp_ring_mask = bp->cp_bit - 1; | |
3486 | } | |
3487 | ||
96a8604f JDB |
3488 | /* Changing allocation mode of RX rings. |
3489 | * TODO: Update when extending xdp_rxq_info to support allocation modes. | |
3490 | */ | |
c61fb99c | 3491 | int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) |
6bb19474 | 3492 | { |
c61fb99c MC |
3493 | if (page_mode) { |
3494 | if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) | |
3495 | return -EOPNOTSUPP; | |
7eb9bb3a MC |
3496 | bp->dev->max_mtu = |
3497 | min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); | |
c61fb99c MC |
3498 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; |
3499 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; | |
c61fb99c MC |
3500 | bp->rx_dir = DMA_BIDIRECTIONAL; |
3501 | bp->rx_skb_func = bnxt_rx_page_skb; | |
1054aee8 MC |
3502 | /* Disable LRO or GRO_HW */ |
3503 | netdev_update_features(bp->dev); | |
c61fb99c | 3504 | } else { |
7eb9bb3a | 3505 | bp->dev->max_mtu = bp->max_mtu; |
c61fb99c MC |
3506 | bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; |
3507 | bp->rx_dir = DMA_FROM_DEVICE; | |
3508 | bp->rx_skb_func = bnxt_rx_skb; | |
3509 | } | |
6bb19474 MC |
3510 | return 0; |
3511 | } | |
3512 | ||
c0c050c5 MC |
3513 | static void bnxt_free_vnic_attributes(struct bnxt *bp) |
3514 | { | |
3515 | int i; | |
3516 | struct bnxt_vnic_info *vnic; | |
3517 | struct pci_dev *pdev = bp->pdev; | |
3518 | ||
3519 | if (!bp->vnic_info) | |
3520 | return; | |
3521 | ||
3522 | for (i = 0; i < bp->nr_vnics; i++) { | |
3523 | vnic = &bp->vnic_info[i]; | |
3524 | ||
3525 | kfree(vnic->fw_grp_ids); | |
3526 | vnic->fw_grp_ids = NULL; | |
3527 | ||
3528 | kfree(vnic->uc_list); | |
3529 | vnic->uc_list = NULL; | |
3530 | ||
3531 | if (vnic->mc_list) { | |
3532 | dma_free_coherent(&pdev->dev, vnic->mc_list_size, | |
3533 | vnic->mc_list, vnic->mc_list_mapping); | |
3534 | vnic->mc_list = NULL; | |
3535 | } | |
3536 | ||
3537 | if (vnic->rss_table) { | |
3538 | dma_free_coherent(&pdev->dev, PAGE_SIZE, | |
3539 | vnic->rss_table, | |
3540 | vnic->rss_table_dma_addr); | |
3541 | vnic->rss_table = NULL; | |
3542 | } | |
3543 | ||
3544 | vnic->rss_hash_key = NULL; | |
3545 | vnic->flags = 0; | |
3546 | } | |
3547 | } | |
3548 | ||
3549 | static int bnxt_alloc_vnic_attributes(struct bnxt *bp) | |
3550 | { | |
3551 | int i, rc = 0, size; | |
3552 | struct bnxt_vnic_info *vnic; | |
3553 | struct pci_dev *pdev = bp->pdev; | |
3554 | int max_rings; | |
3555 | ||
3556 | for (i = 0; i < bp->nr_vnics; i++) { | |
3557 | vnic = &bp->vnic_info[i]; | |
3558 | ||
3559 | if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { | |
3560 | int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; | |
3561 | ||
3562 | if (mem_size > 0) { | |
3563 | vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); | |
3564 | if (!vnic->uc_list) { | |
3565 | rc = -ENOMEM; | |
3566 | goto out; | |
3567 | } | |
3568 | } | |
3569 | } | |
3570 | ||
3571 | if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { | |
3572 | vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; | |
3573 | vnic->mc_list = | |
3574 | dma_alloc_coherent(&pdev->dev, | |
3575 | vnic->mc_list_size, | |
3576 | &vnic->mc_list_mapping, | |
3577 | GFP_KERNEL); | |
3578 | if (!vnic->mc_list) { | |
3579 | rc = -ENOMEM; | |
3580 | goto out; | |
3581 | } | |
3582 | } | |
3583 | ||
44c6f72a MC |
3584 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
3585 | goto vnic_skip_grps; | |
3586 | ||
c0c050c5 MC |
3587 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
3588 | max_rings = bp->rx_nr_rings; | |
3589 | else | |
3590 | max_rings = 1; | |
3591 | ||
3592 | vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); | |
3593 | if (!vnic->fw_grp_ids) { | |
3594 | rc = -ENOMEM; | |
3595 | goto out; | |
3596 | } | |
44c6f72a | 3597 | vnic_skip_grps: |
ae10ae74 MC |
3598 | if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && |
3599 | !(vnic->flags & BNXT_VNIC_RSS_FLAG)) | |
3600 | continue; | |
3601 | ||
c0c050c5 MC |
3602 | /* Allocate rss table and hash key */ |
3603 | vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3604 | &vnic->rss_table_dma_addr, | |
3605 | GFP_KERNEL); | |
3606 | if (!vnic->rss_table) { | |
3607 | rc = -ENOMEM; | |
3608 | goto out; | |
3609 | } | |
3610 | ||
3611 | size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); | |
3612 | ||
3613 | vnic->rss_hash_key = ((void *)vnic->rss_table) + size; | |
3614 | vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; | |
3615 | } | |
3616 | return 0; | |
3617 | ||
3618 | out: | |
3619 | return rc; | |
3620 | } | |
3621 | ||
3622 | static void bnxt_free_hwrm_resources(struct bnxt *bp) | |
3623 | { | |
3624 | struct pci_dev *pdev = bp->pdev; | |
3625 | ||
a2bf74f4 VD |
3626 | if (bp->hwrm_cmd_resp_addr) { |
3627 | dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, | |
3628 | bp->hwrm_cmd_resp_dma_addr); | |
3629 | bp->hwrm_cmd_resp_addr = NULL; | |
3630 | } | |
760b6d33 VD |
3631 | |
3632 | if (bp->hwrm_cmd_kong_resp_addr) { | |
3633 | dma_free_coherent(&pdev->dev, PAGE_SIZE, | |
3634 | bp->hwrm_cmd_kong_resp_addr, | |
3635 | bp->hwrm_cmd_kong_resp_dma_addr); | |
3636 | bp->hwrm_cmd_kong_resp_addr = NULL; | |
3637 | } | |
3638 | } | |
3639 | ||
3640 | static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) | |
3641 | { | |
3642 | struct pci_dev *pdev = bp->pdev; | |
3643 | ||
ba642ab7 MC |
3644 | if (bp->hwrm_cmd_kong_resp_addr) |
3645 | return 0; | |
3646 | ||
760b6d33 VD |
3647 | bp->hwrm_cmd_kong_resp_addr = |
3648 | dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3649 | &bp->hwrm_cmd_kong_resp_dma_addr, | |
3650 | GFP_KERNEL); | |
3651 | if (!bp->hwrm_cmd_kong_resp_addr) | |
3652 | return -ENOMEM; | |
3653 | ||
3654 | return 0; | |
c0c050c5 MC |
3655 | } |
3656 | ||
3657 | static int bnxt_alloc_hwrm_resources(struct bnxt *bp) | |
3658 | { | |
3659 | struct pci_dev *pdev = bp->pdev; | |
3660 | ||
3661 | bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
3662 | &bp->hwrm_cmd_resp_dma_addr, | |
3663 | GFP_KERNEL); | |
3664 | if (!bp->hwrm_cmd_resp_addr) | |
3665 | return -ENOMEM; | |
c0c050c5 MC |
3666 | |
3667 | return 0; | |
3668 | } | |
3669 | ||
e605db80 DK |
3670 | static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) |
3671 | { | |
3672 | if (bp->hwrm_short_cmd_req_addr) { | |
3673 | struct pci_dev *pdev = bp->pdev; | |
3674 | ||
1dfddc41 | 3675 | dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, |
e605db80 DK |
3676 | bp->hwrm_short_cmd_req_addr, |
3677 | bp->hwrm_short_cmd_req_dma_addr); | |
3678 | bp->hwrm_short_cmd_req_addr = NULL; | |
3679 | } | |
3680 | } | |
3681 | ||
3682 | static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) | |
3683 | { | |
3684 | struct pci_dev *pdev = bp->pdev; | |
3685 | ||
ba642ab7 MC |
3686 | if (bp->hwrm_short_cmd_req_addr) |
3687 | return 0; | |
3688 | ||
e605db80 | 3689 | bp->hwrm_short_cmd_req_addr = |
1dfddc41 | 3690 | dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, |
e605db80 DK |
3691 | &bp->hwrm_short_cmd_req_dma_addr, |
3692 | GFP_KERNEL); | |
3693 | if (!bp->hwrm_short_cmd_req_addr) | |
3694 | return -ENOMEM; | |
3695 | ||
3696 | return 0; | |
3697 | } | |
3698 | ||
fd3ab1c7 | 3699 | static void bnxt_free_port_stats(struct bnxt *bp) |
c0c050c5 | 3700 | { |
c0c050c5 MC |
3701 | struct pci_dev *pdev = bp->pdev; |
3702 | ||
00db3cba VV |
3703 | bp->flags &= ~BNXT_FLAG_PORT_STATS; |
3704 | bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; | |
3705 | ||
3bdf56c4 MC |
3706 | if (bp->hw_rx_port_stats) { |
3707 | dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, | |
3708 | bp->hw_rx_port_stats, | |
3709 | bp->hw_rx_port_stats_map); | |
3710 | bp->hw_rx_port_stats = NULL; | |
00db3cba VV |
3711 | } |
3712 | ||
36e53349 MC |
3713 | if (bp->hw_tx_port_stats_ext) { |
3714 | dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext), | |
3715 | bp->hw_tx_port_stats_ext, | |
3716 | bp->hw_tx_port_stats_ext_map); | |
3717 | bp->hw_tx_port_stats_ext = NULL; | |
3718 | } | |
3719 | ||
00db3cba VV |
3720 | if (bp->hw_rx_port_stats_ext) { |
3721 | dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), | |
3722 | bp->hw_rx_port_stats_ext, | |
3723 | bp->hw_rx_port_stats_ext_map); | |
3724 | bp->hw_rx_port_stats_ext = NULL; | |
3bdf56c4 | 3725 | } |
55e4398d VV |
3726 | |
3727 | if (bp->hw_pcie_stats) { | |
3728 | dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), | |
3729 | bp->hw_pcie_stats, bp->hw_pcie_stats_map); | |
3730 | bp->hw_pcie_stats = NULL; | |
3731 | } | |
fd3ab1c7 MC |
3732 | } |
3733 | ||
3734 | static void bnxt_free_ring_stats(struct bnxt *bp) | |
3735 | { | |
3736 | struct pci_dev *pdev = bp->pdev; | |
3737 | int size, i; | |
3bdf56c4 | 3738 | |
c0c050c5 MC |
3739 | if (!bp->bnapi) |
3740 | return; | |
3741 | ||
4e748506 | 3742 | size = bp->hw_ring_stats_size; |
c0c050c5 MC |
3743 | |
3744 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3745 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3746 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3747 | ||
3748 | if (cpr->hw_stats) { | |
3749 | dma_free_coherent(&pdev->dev, size, cpr->hw_stats, | |
3750 | cpr->hw_stats_map); | |
3751 | cpr->hw_stats = NULL; | |
3752 | } | |
3753 | } | |
3754 | } | |
3755 | ||
3756 | static int bnxt_alloc_stats(struct bnxt *bp) | |
3757 | { | |
3758 | u32 size, i; | |
3759 | struct pci_dev *pdev = bp->pdev; | |
3760 | ||
4e748506 | 3761 | size = bp->hw_ring_stats_size; |
c0c050c5 MC |
3762 | |
3763 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3764 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3765 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3766 | ||
3767 | cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, | |
3768 | &cpr->hw_stats_map, | |
3769 | GFP_KERNEL); | |
3770 | if (!cpr->hw_stats) | |
3771 | return -ENOMEM; | |
3772 | ||
3773 | cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; | |
3774 | } | |
3bdf56c4 | 3775 | |
a220eabc VV |
3776 | if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) |
3777 | return 0; | |
fd3ab1c7 | 3778 | |
a220eabc VV |
3779 | if (bp->hw_rx_port_stats) |
3780 | goto alloc_ext_stats; | |
3bdf56c4 | 3781 | |
a220eabc VV |
3782 | bp->hw_port_stats_size = sizeof(struct rx_port_stats) + |
3783 | sizeof(struct tx_port_stats) + 1024; | |
3bdf56c4 | 3784 | |
a220eabc VV |
3785 | bp->hw_rx_port_stats = |
3786 | dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, | |
3787 | &bp->hw_rx_port_stats_map, | |
3788 | GFP_KERNEL); | |
3789 | if (!bp->hw_rx_port_stats) | |
3790 | return -ENOMEM; | |
3bdf56c4 | 3791 | |
a220eabc VV |
3792 | bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512; |
3793 | bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + | |
3794 | sizeof(struct rx_port_stats) + 512; | |
3795 | bp->flags |= BNXT_FLAG_PORT_STATS; | |
00db3cba | 3796 | |
fd3ab1c7 | 3797 | alloc_ext_stats: |
a220eabc VV |
3798 | /* Display extended statistics only if FW supports it */ |
3799 | if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) | |
6154532f | 3800 | if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) |
00db3cba VV |
3801 | return 0; |
3802 | ||
a220eabc VV |
3803 | if (bp->hw_rx_port_stats_ext) |
3804 | goto alloc_tx_ext_stats; | |
fd3ab1c7 | 3805 | |
a220eabc VV |
3806 | bp->hw_rx_port_stats_ext = |
3807 | dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), | |
3808 | &bp->hw_rx_port_stats_ext_map, GFP_KERNEL); | |
3809 | if (!bp->hw_rx_port_stats_ext) | |
3810 | return 0; | |
00db3cba | 3811 | |
fd3ab1c7 | 3812 | alloc_tx_ext_stats: |
a220eabc | 3813 | if (bp->hw_tx_port_stats_ext) |
55e4398d | 3814 | goto alloc_pcie_stats; |
fd3ab1c7 | 3815 | |
6154532f VV |
3816 | if (bp->hwrm_spec_code >= 0x10902 || |
3817 | (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { | |
a220eabc VV |
3818 | bp->hw_tx_port_stats_ext = |
3819 | dma_alloc_coherent(&pdev->dev, | |
3820 | sizeof(struct tx_port_stats_ext), | |
3821 | &bp->hw_tx_port_stats_ext_map, | |
3822 | GFP_KERNEL); | |
3bdf56c4 | 3823 | } |
a220eabc | 3824 | bp->flags |= BNXT_FLAG_PORT_STATS_EXT; |
55e4398d VV |
3825 | |
3826 | alloc_pcie_stats: | |
3827 | if (bp->hw_pcie_stats || | |
3828 | !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) | |
3829 | return 0; | |
3830 | ||
3831 | bp->hw_pcie_stats = | |
3832 | dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), | |
3833 | &bp->hw_pcie_stats_map, GFP_KERNEL); | |
3834 | if (!bp->hw_pcie_stats) | |
3835 | return 0; | |
3836 | ||
3837 | bp->flags |= BNXT_FLAG_PCIE_STATS; | |
c0c050c5 MC |
3838 | return 0; |
3839 | } | |
3840 | ||
3841 | static void bnxt_clear_ring_indices(struct bnxt *bp) | |
3842 | { | |
3843 | int i; | |
3844 | ||
3845 | if (!bp->bnapi) | |
3846 | return; | |
3847 | ||
3848 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
3849 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
3850 | struct bnxt_cp_ring_info *cpr; | |
3851 | struct bnxt_rx_ring_info *rxr; | |
3852 | struct bnxt_tx_ring_info *txr; | |
3853 | ||
3854 | if (!bnapi) | |
3855 | continue; | |
3856 | ||
3857 | cpr = &bnapi->cp_ring; | |
3858 | cpr->cp_raw_cons = 0; | |
3859 | ||
b6ab4b01 | 3860 | txr = bnapi->tx_ring; |
3b2b7d9d MC |
3861 | if (txr) { |
3862 | txr->tx_prod = 0; | |
3863 | txr->tx_cons = 0; | |
3864 | } | |
c0c050c5 | 3865 | |
b6ab4b01 | 3866 | rxr = bnapi->rx_ring; |
3b2b7d9d MC |
3867 | if (rxr) { |
3868 | rxr->rx_prod = 0; | |
3869 | rxr->rx_agg_prod = 0; | |
3870 | rxr->rx_sw_agg_prod = 0; | |
376a5b86 | 3871 | rxr->rx_next_cons = 0; |
3b2b7d9d | 3872 | } |
c0c050c5 MC |
3873 | } |
3874 | } | |
3875 | ||
3876 | static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) | |
3877 | { | |
3878 | #ifdef CONFIG_RFS_ACCEL | |
3879 | int i; | |
3880 | ||
3881 | /* Under rtnl_lock and all our NAPIs have been disabled. It's | |
3882 | * safe to delete the hash table. | |
3883 | */ | |
3884 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { | |
3885 | struct hlist_head *head; | |
3886 | struct hlist_node *tmp; | |
3887 | struct bnxt_ntuple_filter *fltr; | |
3888 | ||
3889 | head = &bp->ntp_fltr_hash_tbl[i]; | |
3890 | hlist_for_each_entry_safe(fltr, tmp, head, hash) { | |
3891 | hlist_del(&fltr->hash); | |
3892 | kfree(fltr); | |
3893 | } | |
3894 | } | |
3895 | if (irq_reinit) { | |
3896 | kfree(bp->ntp_fltr_bmap); | |
3897 | bp->ntp_fltr_bmap = NULL; | |
3898 | } | |
3899 | bp->ntp_fltr_count = 0; | |
3900 | #endif | |
3901 | } | |
3902 | ||
3903 | static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) | |
3904 | { | |
3905 | #ifdef CONFIG_RFS_ACCEL | |
3906 | int i, rc = 0; | |
3907 | ||
3908 | if (!(bp->flags & BNXT_FLAG_RFS)) | |
3909 | return 0; | |
3910 | ||
3911 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) | |
3912 | INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); | |
3913 | ||
3914 | bp->ntp_fltr_count = 0; | |
ac45bd93 DC |
3915 | bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), |
3916 | sizeof(long), | |
c0c050c5 MC |
3917 | GFP_KERNEL); |
3918 | ||
3919 | if (!bp->ntp_fltr_bmap) | |
3920 | rc = -ENOMEM; | |
3921 | ||
3922 | return rc; | |
3923 | #else | |
3924 | return 0; | |
3925 | #endif | |
3926 | } | |
3927 | ||
3928 | static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) | |
3929 | { | |
3930 | bnxt_free_vnic_attributes(bp); | |
3931 | bnxt_free_tx_rings(bp); | |
3932 | bnxt_free_rx_rings(bp); | |
3933 | bnxt_free_cp_rings(bp); | |
3934 | bnxt_free_ntp_fltrs(bp, irq_re_init); | |
3935 | if (irq_re_init) { | |
fd3ab1c7 | 3936 | bnxt_free_ring_stats(bp); |
c0c050c5 MC |
3937 | bnxt_free_ring_grps(bp); |
3938 | bnxt_free_vnics(bp); | |
a960dec9 MC |
3939 | kfree(bp->tx_ring_map); |
3940 | bp->tx_ring_map = NULL; | |
b6ab4b01 MC |
3941 | kfree(bp->tx_ring); |
3942 | bp->tx_ring = NULL; | |
3943 | kfree(bp->rx_ring); | |
3944 | bp->rx_ring = NULL; | |
c0c050c5 MC |
3945 | kfree(bp->bnapi); |
3946 | bp->bnapi = NULL; | |
3947 | } else { | |
3948 | bnxt_clear_ring_indices(bp); | |
3949 | } | |
3950 | } | |
3951 | ||
3952 | static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) | |
3953 | { | |
01657bcd | 3954 | int i, j, rc, size, arr_size; |
c0c050c5 MC |
3955 | void *bnapi; |
3956 | ||
3957 | if (irq_re_init) { | |
3958 | /* Allocate bnapi mem pointer array and mem block for | |
3959 | * all queues | |
3960 | */ | |
3961 | arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * | |
3962 | bp->cp_nr_rings); | |
3963 | size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); | |
3964 | bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); | |
3965 | if (!bnapi) | |
3966 | return -ENOMEM; | |
3967 | ||
3968 | bp->bnapi = bnapi; | |
3969 | bnapi += arr_size; | |
3970 | for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { | |
3971 | bp->bnapi[i] = bnapi; | |
3972 | bp->bnapi[i]->index = i; | |
3973 | bp->bnapi[i]->bp = bp; | |
e38287b7 MC |
3974 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
3975 | struct bnxt_cp_ring_info *cpr = | |
3976 | &bp->bnapi[i]->cp_ring; | |
3977 | ||
3978 | cpr->cp_ring_struct.ring_mem.flags = | |
3979 | BNXT_RMEM_RING_PTE_FLAG; | |
3980 | } | |
c0c050c5 MC |
3981 | } |
3982 | ||
b6ab4b01 MC |
3983 | bp->rx_ring = kcalloc(bp->rx_nr_rings, |
3984 | sizeof(struct bnxt_rx_ring_info), | |
3985 | GFP_KERNEL); | |
3986 | if (!bp->rx_ring) | |
3987 | return -ENOMEM; | |
3988 | ||
3989 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
e38287b7 MC |
3990 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
3991 | ||
3992 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
3993 | rxr->rx_ring_struct.ring_mem.flags = | |
3994 | BNXT_RMEM_RING_PTE_FLAG; | |
3995 | rxr->rx_agg_ring_struct.ring_mem.flags = | |
3996 | BNXT_RMEM_RING_PTE_FLAG; | |
3997 | } | |
3998 | rxr->bnapi = bp->bnapi[i]; | |
b6ab4b01 MC |
3999 | bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; |
4000 | } | |
4001 | ||
4002 | bp->tx_ring = kcalloc(bp->tx_nr_rings, | |
4003 | sizeof(struct bnxt_tx_ring_info), | |
4004 | GFP_KERNEL); | |
4005 | if (!bp->tx_ring) | |
4006 | return -ENOMEM; | |
4007 | ||
a960dec9 MC |
4008 | bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), |
4009 | GFP_KERNEL); | |
4010 | ||
4011 | if (!bp->tx_ring_map) | |
4012 | return -ENOMEM; | |
4013 | ||
01657bcd MC |
4014 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
4015 | j = 0; | |
4016 | else | |
4017 | j = bp->rx_nr_rings; | |
4018 | ||
4019 | for (i = 0; i < bp->tx_nr_rings; i++, j++) { | |
e38287b7 MC |
4020 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
4021 | ||
4022 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
4023 | txr->tx_ring_struct.ring_mem.flags = | |
4024 | BNXT_RMEM_RING_PTE_FLAG; | |
4025 | txr->bnapi = bp->bnapi[j]; | |
4026 | bp->bnapi[j]->tx_ring = txr; | |
5f449249 | 4027 | bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; |
38413406 | 4028 | if (i >= bp->tx_nr_rings_xdp) { |
e38287b7 | 4029 | txr->txq_index = i - bp->tx_nr_rings_xdp; |
38413406 MC |
4030 | bp->bnapi[j]->tx_int = bnxt_tx_int; |
4031 | } else { | |
fa3e93e8 | 4032 | bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; |
38413406 MC |
4033 | bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; |
4034 | } | |
b6ab4b01 MC |
4035 | } |
4036 | ||
c0c050c5 MC |
4037 | rc = bnxt_alloc_stats(bp); |
4038 | if (rc) | |
4039 | goto alloc_mem_err; | |
4040 | ||
4041 | rc = bnxt_alloc_ntp_fltrs(bp); | |
4042 | if (rc) | |
4043 | goto alloc_mem_err; | |
4044 | ||
4045 | rc = bnxt_alloc_vnics(bp); | |
4046 | if (rc) | |
4047 | goto alloc_mem_err; | |
4048 | } | |
4049 | ||
4050 | bnxt_init_ring_struct(bp); | |
4051 | ||
4052 | rc = bnxt_alloc_rx_rings(bp); | |
4053 | if (rc) | |
4054 | goto alloc_mem_err; | |
4055 | ||
4056 | rc = bnxt_alloc_tx_rings(bp); | |
4057 | if (rc) | |
4058 | goto alloc_mem_err; | |
4059 | ||
4060 | rc = bnxt_alloc_cp_rings(bp); | |
4061 | if (rc) | |
4062 | goto alloc_mem_err; | |
4063 | ||
4064 | bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | | |
4065 | BNXT_VNIC_UCAST_FLAG; | |
4066 | rc = bnxt_alloc_vnic_attributes(bp); | |
4067 | if (rc) | |
4068 | goto alloc_mem_err; | |
4069 | return 0; | |
4070 | ||
4071 | alloc_mem_err: | |
4072 | bnxt_free_mem(bp, true); | |
4073 | return rc; | |
4074 | } | |
4075 | ||
9d8bc097 MC |
4076 | static void bnxt_disable_int(struct bnxt *bp) |
4077 | { | |
4078 | int i; | |
4079 | ||
4080 | if (!bp->bnapi) | |
4081 | return; | |
4082 | ||
4083 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
4084 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
4085 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
daf1f1e7 | 4086 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; |
9d8bc097 | 4087 | |
daf1f1e7 | 4088 | if (ring->fw_ring_id != INVALID_HW_RING_ID) |
697197e5 | 4089 | bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); |
9d8bc097 MC |
4090 | } |
4091 | } | |
4092 | ||
e5811b8c MC |
4093 | static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) |
4094 | { | |
4095 | struct bnxt_napi *bnapi = bp->bnapi[n]; | |
4096 | struct bnxt_cp_ring_info *cpr; | |
4097 | ||
4098 | cpr = &bnapi->cp_ring; | |
4099 | return cpr->cp_ring_struct.map_idx; | |
4100 | } | |
4101 | ||
9d8bc097 MC |
4102 | static void bnxt_disable_int_sync(struct bnxt *bp) |
4103 | { | |
4104 | int i; | |
4105 | ||
4106 | atomic_inc(&bp->intr_sem); | |
4107 | ||
4108 | bnxt_disable_int(bp); | |
e5811b8c MC |
4109 | for (i = 0; i < bp->cp_nr_rings; i++) { |
4110 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); | |
4111 | ||
4112 | synchronize_irq(bp->irq_tbl[map_idx].vector); | |
4113 | } | |
9d8bc097 MC |
4114 | } |
4115 | ||
4116 | static void bnxt_enable_int(struct bnxt *bp) | |
4117 | { | |
4118 | int i; | |
4119 | ||
4120 | atomic_set(&bp->intr_sem, 0); | |
4121 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
4122 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
4123 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
4124 | ||
697197e5 | 4125 | bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); |
9d8bc097 MC |
4126 | } |
4127 | } | |
4128 | ||
c0c050c5 MC |
4129 | void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, |
4130 | u16 cmpl_ring, u16 target_id) | |
4131 | { | |
a8643e16 | 4132 | struct input *req = request; |
c0c050c5 | 4133 | |
a8643e16 MC |
4134 | req->req_type = cpu_to_le16(req_type); |
4135 | req->cmpl_ring = cpu_to_le16(cmpl_ring); | |
4136 | req->target_id = cpu_to_le16(target_id); | |
760b6d33 VD |
4137 | if (bnxt_kong_hwrm_message(bp, req)) |
4138 | req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); | |
4139 | else | |
4140 | req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); | |
c0c050c5 MC |
4141 | } |
4142 | ||
d4f1420d MC |
4143 | static int bnxt_hwrm_to_stderr(u32 hwrm_err) |
4144 | { | |
4145 | switch (hwrm_err) { | |
4146 | case HWRM_ERR_CODE_SUCCESS: | |
4147 | return 0; | |
4148 | case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: | |
4149 | return -EACCES; | |
4150 | case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: | |
4151 | return -ENOSPC; | |
4152 | case HWRM_ERR_CODE_INVALID_PARAMS: | |
4153 | case HWRM_ERR_CODE_INVALID_FLAGS: | |
4154 | case HWRM_ERR_CODE_INVALID_ENABLES: | |
4155 | case HWRM_ERR_CODE_UNSUPPORTED_TLV: | |
4156 | case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR: | |
4157 | return -EINVAL; | |
4158 | case HWRM_ERR_CODE_NO_BUFFER: | |
4159 | return -ENOMEM; | |
4160 | case HWRM_ERR_CODE_HOT_RESET_PROGRESS: | |
4161 | return -EAGAIN; | |
4162 | case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: | |
4163 | return -EOPNOTSUPP; | |
4164 | default: | |
4165 | return -EIO; | |
4166 | } | |
4167 | } | |
4168 | ||
fbfbc485 MC |
4169 | static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, |
4170 | int timeout, bool silent) | |
c0c050c5 | 4171 | { |
a11fa2be | 4172 | int i, intr_process, rc, tmo_count; |
a8643e16 | 4173 | struct input *req = msg; |
c0c050c5 | 4174 | u32 *data = msg; |
845adfe4 MC |
4175 | __le32 *resp_len; |
4176 | u8 *valid; | |
c0c050c5 MC |
4177 | u16 cp_ring_id, len = 0; |
4178 | struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; | |
e605db80 | 4179 | u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; |
ebd5818c | 4180 | struct hwrm_short_input short_input = {0}; |
2e9ee398 | 4181 | u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; |
89455017 | 4182 | u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr; |
2e9ee398 | 4183 | u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; |
760b6d33 | 4184 | u16 dst = BNXT_HWRM_CHNL_CHIMP; |
c0c050c5 | 4185 | |
b4fff207 MC |
4186 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
4187 | return -EBUSY; | |
4188 | ||
1dfddc41 MC |
4189 | if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { |
4190 | if (msg_len > bp->hwrm_max_ext_req_len || | |
4191 | !bp->hwrm_short_cmd_req_addr) | |
4192 | return -EINVAL; | |
4193 | } | |
4194 | ||
760b6d33 VD |
4195 | if (bnxt_hwrm_kong_chnl(bp, req)) { |
4196 | dst = BNXT_HWRM_CHNL_KONG; | |
4197 | bar_offset = BNXT_GRCPF_REG_KONG_COMM; | |
4198 | doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; | |
4199 | resp = bp->hwrm_cmd_kong_resp_addr; | |
4200 | resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr; | |
4201 | } | |
4202 | ||
4203 | memset(resp, 0, PAGE_SIZE); | |
4204 | cp_ring_id = le16_to_cpu(req->cmpl_ring); | |
4205 | intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; | |
4206 | ||
4207 | req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); | |
4208 | /* currently supports only one outstanding message */ | |
4209 | if (intr_process) | |
4210 | bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); | |
4211 | ||
1dfddc41 MC |
4212 | if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || |
4213 | msg_len > BNXT_HWRM_MAX_REQ_LEN) { | |
e605db80 | 4214 | void *short_cmd_req = bp->hwrm_short_cmd_req_addr; |
1dfddc41 MC |
4215 | u16 max_msg_len; |
4216 | ||
4217 | /* Set boundary for maximum extended request length for short | |
4218 | * cmd format. If passed up from device use the max supported | |
4219 | * internal req length. | |
4220 | */ | |
4221 | max_msg_len = bp->hwrm_max_ext_req_len; | |
e605db80 DK |
4222 | |
4223 | memcpy(short_cmd_req, req, msg_len); | |
1dfddc41 MC |
4224 | if (msg_len < max_msg_len) |
4225 | memset(short_cmd_req + msg_len, 0, | |
4226 | max_msg_len - msg_len); | |
e605db80 DK |
4227 | |
4228 | short_input.req_type = req->req_type; | |
4229 | short_input.signature = | |
4230 | cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); | |
4231 | short_input.size = cpu_to_le16(msg_len); | |
4232 | short_input.req_addr = | |
4233 | cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); | |
4234 | ||
4235 | data = (u32 *)&short_input; | |
4236 | msg_len = sizeof(short_input); | |
4237 | ||
4238 | /* Sync memory write before updating doorbell */ | |
4239 | wmb(); | |
4240 | ||
4241 | max_req_len = BNXT_HWRM_SHORT_REQ_LEN; | |
4242 | } | |
4243 | ||
c0c050c5 | 4244 | /* Write request msg to hwrm channel */ |
2e9ee398 | 4245 | __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); |
c0c050c5 | 4246 | |
e605db80 | 4247 | for (i = msg_len; i < max_req_len; i += 4) |
2e9ee398 | 4248 | writel(0, bp->bar0 + bar_offset + i); |
d79979a1 | 4249 | |
c0c050c5 | 4250 | /* Ring channel doorbell */ |
2e9ee398 | 4251 | writel(1, bp->bar0 + doorbell_offset); |
c0c050c5 | 4252 | |
5bedb529 MC |
4253 | if (!pci_is_enabled(bp->pdev)) |
4254 | return 0; | |
4255 | ||
ff4fe81d MC |
4256 | if (!timeout) |
4257 | timeout = DFLT_HWRM_CMD_TIMEOUT; | |
9751e8e7 AG |
4258 | /* convert timeout to usec */ |
4259 | timeout *= 1000; | |
ff4fe81d | 4260 | |
c0c050c5 | 4261 | i = 0; |
9751e8e7 AG |
4262 | /* Short timeout for the first few iterations: |
4263 | * number of loops = number of loops for short timeout + | |
4264 | * number of loops for standard timeout. | |
4265 | */ | |
4266 | tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; | |
4267 | timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; | |
4268 | tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); | |
89455017 VD |
4269 | resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET); |
4270 | ||
c0c050c5 | 4271 | if (intr_process) { |
fc718bb2 VD |
4272 | u16 seq_id = bp->hwrm_intr_seq_id; |
4273 | ||
c0c050c5 | 4274 | /* Wait until hwrm response cmpl interrupt is processed */ |
fc718bb2 | 4275 | while (bp->hwrm_intr_seq_id != (u16)~seq_id && |
a11fa2be | 4276 | i++ < tmo_count) { |
9751e8e7 AG |
4277 | /* on first few passes, just barely sleep */ |
4278 | if (i < HWRM_SHORT_TIMEOUT_COUNTER) | |
4279 | usleep_range(HWRM_SHORT_MIN_TIMEOUT, | |
4280 | HWRM_SHORT_MAX_TIMEOUT); | |
4281 | else | |
4282 | usleep_range(HWRM_MIN_TIMEOUT, | |
4283 | HWRM_MAX_TIMEOUT); | |
c0c050c5 MC |
4284 | } |
4285 | ||
fc718bb2 | 4286 | if (bp->hwrm_intr_seq_id != (u16)~seq_id) { |
5bedb529 MC |
4287 | if (!silent) |
4288 | netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", | |
4289 | le16_to_cpu(req->req_type)); | |
a935cb7e | 4290 | return -EBUSY; |
c0c050c5 | 4291 | } |
845adfe4 MC |
4292 | len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> |
4293 | HWRM_RESP_LEN_SFT; | |
89455017 | 4294 | valid = resp_addr + len - 1; |
c0c050c5 | 4295 | } else { |
cc559c1a MC |
4296 | int j; |
4297 | ||
c0c050c5 | 4298 | /* Check if response len is updated */ |
a11fa2be | 4299 | for (i = 0; i < tmo_count; i++) { |
c0c050c5 MC |
4300 | len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> |
4301 | HWRM_RESP_LEN_SFT; | |
4302 | if (len) | |
4303 | break; | |
9751e8e7 | 4304 | /* on first few passes, just barely sleep */ |
67681d02 | 4305 | if (i < HWRM_SHORT_TIMEOUT_COUNTER) |
9751e8e7 AG |
4306 | usleep_range(HWRM_SHORT_MIN_TIMEOUT, |
4307 | HWRM_SHORT_MAX_TIMEOUT); | |
4308 | else | |
4309 | usleep_range(HWRM_MIN_TIMEOUT, | |
4310 | HWRM_MAX_TIMEOUT); | |
c0c050c5 MC |
4311 | } |
4312 | ||
a11fa2be | 4313 | if (i >= tmo_count) { |
5bedb529 MC |
4314 | if (!silent) |
4315 | netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", | |
4316 | HWRM_TOTAL_TIMEOUT(i), | |
4317 | le16_to_cpu(req->req_type), | |
4318 | le16_to_cpu(req->seq_id), len); | |
a935cb7e | 4319 | return -EBUSY; |
c0c050c5 MC |
4320 | } |
4321 | ||
845adfe4 | 4322 | /* Last byte of resp contains valid bit */ |
89455017 | 4323 | valid = resp_addr + len - 1; |
cc559c1a | 4324 | for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { |
845adfe4 MC |
4325 | /* make sure we read from updated DMA memory */ |
4326 | dma_rmb(); | |
4327 | if (*valid) | |
c0c050c5 | 4328 | break; |
0000b81a | 4329 | usleep_range(1, 5); |
c0c050c5 MC |
4330 | } |
4331 | ||
cc559c1a | 4332 | if (j >= HWRM_VALID_BIT_DELAY_USEC) { |
5bedb529 MC |
4333 | if (!silent) |
4334 | netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", | |
4335 | HWRM_TOTAL_TIMEOUT(i), | |
4336 | le16_to_cpu(req->req_type), | |
4337 | le16_to_cpu(req->seq_id), len, | |
4338 | *valid); | |
a935cb7e | 4339 | return -EBUSY; |
c0c050c5 MC |
4340 | } |
4341 | } | |
4342 | ||
845adfe4 MC |
4343 | /* Zero valid bit for compatibility. Valid bit in an older spec |
4344 | * may become a new field in a newer spec. We must make sure that | |
4345 | * a new field not implemented by old spec will read zero. | |
4346 | */ | |
4347 | *valid = 0; | |
c0c050c5 | 4348 | rc = le16_to_cpu(resp->error_code); |
fbfbc485 | 4349 | if (rc && !silent) |
c0c050c5 MC |
4350 | netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", |
4351 | le16_to_cpu(resp->req_type), | |
4352 | le16_to_cpu(resp->seq_id), rc); | |
d4f1420d | 4353 | return bnxt_hwrm_to_stderr(rc); |
fbfbc485 MC |
4354 | } |
4355 | ||
4356 | int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) | |
4357 | { | |
4358 | return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); | |
c0c050c5 MC |
4359 | } |
4360 | ||
cc72f3b1 MC |
4361 | int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, |
4362 | int timeout) | |
4363 | { | |
4364 | return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); | |
4365 | } | |
4366 | ||
c0c050c5 MC |
4367 | int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) |
4368 | { | |
4369 | int rc; | |
4370 | ||
4371 | mutex_lock(&bp->hwrm_cmd_lock); | |
4372 | rc = _hwrm_send_message(bp, msg, msg_len, timeout); | |
4373 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4374 | return rc; | |
4375 | } | |
4376 | ||
90e20921 MC |
4377 | int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, |
4378 | int timeout) | |
4379 | { | |
4380 | int rc; | |
4381 | ||
4382 | mutex_lock(&bp->hwrm_cmd_lock); | |
4383 | rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); | |
4384 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4385 | return rc; | |
4386 | } | |
4387 | ||
a1653b13 MC |
4388 | int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, |
4389 | int bmap_size) | |
c0c050c5 MC |
4390 | { |
4391 | struct hwrm_func_drv_rgtr_input req = {0}; | |
25be8623 MC |
4392 | DECLARE_BITMAP(async_events_bmap, 256); |
4393 | u32 *events = (u32 *)async_events_bmap; | |
a1653b13 | 4394 | int i; |
c0c050c5 MC |
4395 | |
4396 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); | |
4397 | ||
4398 | req.enables = | |
a1653b13 | 4399 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); |
c0c050c5 | 4400 | |
25be8623 | 4401 | memset(async_events_bmap, 0, sizeof(async_events_bmap)); |
7e914027 MC |
4402 | for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { |
4403 | u16 event_id = bnxt_async_events_arr[i]; | |
25be8623 | 4404 | |
7e914027 MC |
4405 | if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && |
4406 | !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
4407 | continue; | |
4408 | __set_bit(bnxt_async_events_arr[i], async_events_bmap); | |
4409 | } | |
a1653b13 MC |
4410 | if (bmap && bmap_size) { |
4411 | for (i = 0; i < bmap_size; i++) { | |
4412 | if (test_bit(i, bmap)) | |
4413 | __set_bit(i, async_events_bmap); | |
4414 | } | |
4415 | } | |
4416 | ||
25be8623 MC |
4417 | for (i = 0; i < 8; i++) |
4418 | req.async_event_fwd[i] |= cpu_to_le32(events[i]); | |
4419 | ||
a1653b13 MC |
4420 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
4421 | } | |
4422 | ||
4423 | static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) | |
4424 | { | |
25e1acd6 | 4425 | struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; |
a1653b13 | 4426 | struct hwrm_func_drv_rgtr_input req = {0}; |
acfb50e4 | 4427 | u32 flags; |
25e1acd6 | 4428 | int rc; |
a1653b13 MC |
4429 | |
4430 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); | |
4431 | ||
4432 | req.enables = | |
4433 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | | |
4434 | FUNC_DRV_RGTR_REQ_ENABLES_VER); | |
4435 | ||
11f15ed3 | 4436 | req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); |
acfb50e4 VV |
4437 | flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE | |
4438 | FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; | |
4439 | if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) | |
4440 | flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT; | |
4441 | req.flags = cpu_to_le32(flags); | |
d4f52de0 MC |
4442 | req.ver_maj_8b = DRV_VER_MAJ; |
4443 | req.ver_min_8b = DRV_VER_MIN; | |
4444 | req.ver_upd_8b = DRV_VER_UPD; | |
4445 | req.ver_maj = cpu_to_le16(DRV_VER_MAJ); | |
4446 | req.ver_min = cpu_to_le16(DRV_VER_MIN); | |
4447 | req.ver_upd = cpu_to_le16(DRV_VER_UPD); | |
c0c050c5 MC |
4448 | |
4449 | if (BNXT_PF(bp)) { | |
9b0436c3 | 4450 | u32 data[8]; |
a1653b13 | 4451 | int i; |
c0c050c5 | 4452 | |
9b0436c3 MC |
4453 | memset(data, 0, sizeof(data)); |
4454 | for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { | |
4455 | u16 cmd = bnxt_vf_req_snif[i]; | |
4456 | unsigned int bit, idx; | |
4457 | ||
4458 | idx = cmd / 32; | |
4459 | bit = cmd % 32; | |
4460 | data[idx] |= 1 << bit; | |
4461 | } | |
c0c050c5 | 4462 | |
de68f5de MC |
4463 | for (i = 0; i < 8; i++) |
4464 | req.vf_req_fwd[i] = cpu_to_le32(data[i]); | |
4465 | ||
c0c050c5 MC |
4466 | req.enables |= |
4467 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); | |
4468 | } | |
4469 | ||
abd43a13 VD |
4470 | if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) |
4471 | req.flags |= cpu_to_le32( | |
4472 | FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); | |
4473 | ||
25e1acd6 MC |
4474 | mutex_lock(&bp->hwrm_cmd_lock); |
4475 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
d4f1420d MC |
4476 | if (!rc && (resp->flags & |
4477 | cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))) | |
25e1acd6 MC |
4478 | bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; |
4479 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4480 | return rc; | |
c0c050c5 MC |
4481 | } |
4482 | ||
be58a0da JH |
4483 | static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) |
4484 | { | |
4485 | struct hwrm_func_drv_unrgtr_input req = {0}; | |
4486 | ||
4487 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); | |
4488 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4489 | } | |
4490 | ||
c0c050c5 MC |
4491 | static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) |
4492 | { | |
4493 | u32 rc = 0; | |
4494 | struct hwrm_tunnel_dst_port_free_input req = {0}; | |
4495 | ||
4496 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); | |
4497 | req.tunnel_type = tunnel_type; | |
4498 | ||
4499 | switch (tunnel_type) { | |
4500 | case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: | |
4501 | req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; | |
4502 | break; | |
4503 | case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: | |
4504 | req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; | |
4505 | break; | |
4506 | default: | |
4507 | break; | |
4508 | } | |
4509 | ||
4510 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4511 | if (rc) | |
4512 | netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", | |
4513 | rc); | |
4514 | return rc; | |
4515 | } | |
4516 | ||
4517 | static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, | |
4518 | u8 tunnel_type) | |
4519 | { | |
4520 | u32 rc = 0; | |
4521 | struct hwrm_tunnel_dst_port_alloc_input req = {0}; | |
4522 | struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
4523 | ||
4524 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); | |
4525 | ||
4526 | req.tunnel_type = tunnel_type; | |
4527 | req.tunnel_dst_port_val = port; | |
4528 | ||
4529 | mutex_lock(&bp->hwrm_cmd_lock); | |
4530 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4531 | if (rc) { | |
4532 | netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", | |
4533 | rc); | |
4534 | goto err_out; | |
4535 | } | |
4536 | ||
57aac71b CJ |
4537 | switch (tunnel_type) { |
4538 | case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: | |
c0c050c5 | 4539 | bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; |
57aac71b CJ |
4540 | break; |
4541 | case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: | |
c0c050c5 | 4542 | bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; |
57aac71b CJ |
4543 | break; |
4544 | default: | |
4545 | break; | |
4546 | } | |
4547 | ||
c0c050c5 MC |
4548 | err_out: |
4549 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4550 | return rc; | |
4551 | } | |
4552 | ||
4553 | static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) | |
4554 | { | |
4555 | struct hwrm_cfa_l2_set_rx_mask_input req = {0}; | |
4556 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4557 | ||
4558 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); | |
c193554e | 4559 | req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); |
c0c050c5 MC |
4560 | |
4561 | req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); | |
4562 | req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); | |
4563 | req.mask = cpu_to_le32(vnic->rx_mask); | |
4564 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4565 | } | |
4566 | ||
4567 | #ifdef CONFIG_RFS_ACCEL | |
4568 | static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, | |
4569 | struct bnxt_ntuple_filter *fltr) | |
4570 | { | |
4571 | struct hwrm_cfa_ntuple_filter_free_input req = {0}; | |
4572 | ||
4573 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); | |
4574 | req.ntuple_filter_id = fltr->filter_id; | |
4575 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4576 | } | |
4577 | ||
4578 | #define BNXT_NTP_FLTR_FLAGS \ | |
4579 | (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ | |
4580 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ | |
4581 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ | |
4582 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ | |
4583 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ | |
4584 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ | |
4585 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ | |
4586 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ | |
4587 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ | |
4588 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ | |
4589 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ | |
4590 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ | |
4591 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ | |
c193554e | 4592 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) |
c0c050c5 | 4593 | |
61aad724 MC |
4594 | #define BNXT_NTP_TUNNEL_FLTR_FLAG \ |
4595 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE | |
4596 | ||
c0c050c5 MC |
4597 | static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, |
4598 | struct bnxt_ntuple_filter *fltr) | |
4599 | { | |
c0c050c5 | 4600 | struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; |
5c209fc8 | 4601 | struct hwrm_cfa_ntuple_filter_alloc_output *resp; |
c0c050c5 | 4602 | struct flow_keys *keys = &fltr->fkeys; |
ac33906c MC |
4603 | struct bnxt_vnic_info *vnic; |
4604 | u32 dst_ena = 0; | |
5c209fc8 | 4605 | int rc = 0; |
c0c050c5 MC |
4606 | |
4607 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); | |
a54c4d74 | 4608 | req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; |
c0c050c5 | 4609 | |
ac33906c MC |
4610 | if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) { |
4611 | dst_ena = CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX; | |
4612 | req.rfs_ring_tbl_idx = cpu_to_le16(fltr->rxq); | |
4613 | vnic = &bp->vnic_info[0]; | |
4614 | } else { | |
4615 | vnic = &bp->vnic_info[fltr->rxq + 1]; | |
4616 | } | |
4617 | req.dst_id = cpu_to_le16(vnic->fw_vnic_id); | |
4618 | req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS | dst_ena); | |
c0c050c5 MC |
4619 | |
4620 | req.ethertype = htons(ETH_P_IP); | |
4621 | memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); | |
c193554e | 4622 | req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; |
c0c050c5 MC |
4623 | req.ip_protocol = keys->basic.ip_proto; |
4624 | ||
dda0e746 MC |
4625 | if (keys->basic.n_proto == htons(ETH_P_IPV6)) { |
4626 | int i; | |
4627 | ||
4628 | req.ethertype = htons(ETH_P_IPV6); | |
4629 | req.ip_addr_type = | |
4630 | CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; | |
4631 | *(struct in6_addr *)&req.src_ipaddr[0] = | |
4632 | keys->addrs.v6addrs.src; | |
4633 | *(struct in6_addr *)&req.dst_ipaddr[0] = | |
4634 | keys->addrs.v6addrs.dst; | |
4635 | for (i = 0; i < 4; i++) { | |
4636 | req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); | |
4637 | req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); | |
4638 | } | |
4639 | } else { | |
4640 | req.src_ipaddr[0] = keys->addrs.v4addrs.src; | |
4641 | req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); | |
4642 | req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; | |
4643 | req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); | |
4644 | } | |
61aad724 MC |
4645 | if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { |
4646 | req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); | |
4647 | req.tunnel_type = | |
4648 | CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; | |
4649 | } | |
c0c050c5 MC |
4650 | |
4651 | req.src_port = keys->ports.src; | |
4652 | req.src_port_mask = cpu_to_be16(0xffff); | |
4653 | req.dst_port = keys->ports.dst; | |
4654 | req.dst_port_mask = cpu_to_be16(0xffff); | |
4655 | ||
c0c050c5 MC |
4656 | mutex_lock(&bp->hwrm_cmd_lock); |
4657 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5c209fc8 VD |
4658 | if (!rc) { |
4659 | resp = bnxt_get_hwrm_resp_addr(bp, &req); | |
c0c050c5 | 4660 | fltr->filter_id = resp->ntuple_filter_id; |
5c209fc8 | 4661 | } |
c0c050c5 MC |
4662 | mutex_unlock(&bp->hwrm_cmd_lock); |
4663 | return rc; | |
4664 | } | |
4665 | #endif | |
4666 | ||
4667 | static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, | |
4668 | u8 *mac_addr) | |
4669 | { | |
4670 | u32 rc = 0; | |
4671 | struct hwrm_cfa_l2_filter_alloc_input req = {0}; | |
4672 | struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
4673 | ||
4674 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); | |
dc52c6c7 PS |
4675 | req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); |
4676 | if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
4677 | req.flags |= | |
4678 | cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); | |
c193554e | 4679 | req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); |
c0c050c5 MC |
4680 | req.enables = |
4681 | cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | | |
c193554e | 4682 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | |
c0c050c5 MC |
4683 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); |
4684 | memcpy(req.l2_addr, mac_addr, ETH_ALEN); | |
4685 | req.l2_addr_mask[0] = 0xff; | |
4686 | req.l2_addr_mask[1] = 0xff; | |
4687 | req.l2_addr_mask[2] = 0xff; | |
4688 | req.l2_addr_mask[3] = 0xff; | |
4689 | req.l2_addr_mask[4] = 0xff; | |
4690 | req.l2_addr_mask[5] = 0xff; | |
4691 | ||
4692 | mutex_lock(&bp->hwrm_cmd_lock); | |
4693 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4694 | if (!rc) | |
4695 | bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = | |
4696 | resp->l2_filter_id; | |
4697 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4698 | return rc; | |
4699 | } | |
4700 | ||
4701 | static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) | |
4702 | { | |
4703 | u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ | |
4704 | int rc = 0; | |
4705 | ||
4706 | /* Any associated ntuple filters will also be cleared by firmware. */ | |
4707 | mutex_lock(&bp->hwrm_cmd_lock); | |
4708 | for (i = 0; i < num_of_vnics; i++) { | |
4709 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
4710 | ||
4711 | for (j = 0; j < vnic->uc_filter_count; j++) { | |
4712 | struct hwrm_cfa_l2_filter_free_input req = {0}; | |
4713 | ||
4714 | bnxt_hwrm_cmd_hdr_init(bp, &req, | |
4715 | HWRM_CFA_L2_FILTER_FREE, -1, -1); | |
4716 | ||
4717 | req.l2_filter_id = vnic->fw_l2_filter_id[j]; | |
4718 | ||
4719 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
4720 | HWRM_CMD_TIMEOUT); | |
4721 | } | |
4722 | vnic->uc_filter_count = 0; | |
4723 | } | |
4724 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4725 | ||
4726 | return rc; | |
4727 | } | |
4728 | ||
4729 | static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) | |
4730 | { | |
4731 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
79632e9b | 4732 | u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; |
c0c050c5 MC |
4733 | struct hwrm_vnic_tpa_cfg_input req = {0}; |
4734 | ||
3c4fe80b MC |
4735 | if (vnic->fw_vnic_id == INVALID_HW_RING_ID) |
4736 | return 0; | |
4737 | ||
c0c050c5 MC |
4738 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); |
4739 | ||
4740 | if (tpa_flags) { | |
4741 | u16 mss = bp->dev->mtu - 40; | |
4742 | u32 nsegs, n, segs = 0, flags; | |
4743 | ||
4744 | flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | | |
4745 | VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | | |
4746 | VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | | |
4747 | VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | | |
4748 | VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; | |
4749 | if (tpa_flags & BNXT_FLAG_GRO) | |
4750 | flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; | |
4751 | ||
4752 | req.flags = cpu_to_le32(flags); | |
4753 | ||
4754 | req.enables = | |
4755 | cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | | |
c193554e MC |
4756 | VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | |
4757 | VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); | |
c0c050c5 MC |
4758 | |
4759 | /* Number of segs are log2 units, and first packet is not | |
4760 | * included as part of this units. | |
4761 | */ | |
2839f28b MC |
4762 | if (mss <= BNXT_RX_PAGE_SIZE) { |
4763 | n = BNXT_RX_PAGE_SIZE / mss; | |
c0c050c5 MC |
4764 | nsegs = (MAX_SKB_FRAGS - 1) * n; |
4765 | } else { | |
2839f28b MC |
4766 | n = mss / BNXT_RX_PAGE_SIZE; |
4767 | if (mss & (BNXT_RX_PAGE_SIZE - 1)) | |
c0c050c5 MC |
4768 | n++; |
4769 | nsegs = (MAX_SKB_FRAGS - n) / n; | |
4770 | } | |
4771 | ||
79632e9b MC |
4772 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
4773 | segs = MAX_TPA_SEGS_P5; | |
4774 | max_aggs = bp->max_tpa; | |
4775 | } else { | |
4776 | segs = ilog2(nsegs); | |
4777 | } | |
c0c050c5 | 4778 | req.max_agg_segs = cpu_to_le16(segs); |
79632e9b | 4779 | req.max_aggs = cpu_to_le16(max_aggs); |
c193554e MC |
4780 | |
4781 | req.min_agg_len = cpu_to_le32(512); | |
c0c050c5 MC |
4782 | } |
4783 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); | |
4784 | ||
4785 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4786 | } | |
4787 | ||
2c61d211 MC |
4788 | static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) |
4789 | { | |
4790 | struct bnxt_ring_grp_info *grp_info; | |
4791 | ||
4792 | grp_info = &bp->grp_info[ring->grp_idx]; | |
4793 | return grp_info->cp_fw_ring_id; | |
4794 | } | |
4795 | ||
4796 | static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) | |
4797 | { | |
4798 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4799 | struct bnxt_napi *bnapi = rxr->bnapi; | |
4800 | struct bnxt_cp_ring_info *cpr; | |
4801 | ||
4802 | cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; | |
4803 | return cpr->cp_ring_struct.fw_ring_id; | |
4804 | } else { | |
4805 | return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); | |
4806 | } | |
4807 | } | |
4808 | ||
4809 | static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) | |
4810 | { | |
4811 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
4812 | struct bnxt_napi *bnapi = txr->bnapi; | |
4813 | struct bnxt_cp_ring_info *cpr; | |
4814 | ||
4815 | cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; | |
4816 | return cpr->cp_ring_struct.fw_ring_id; | |
4817 | } else { | |
4818 | return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); | |
4819 | } | |
4820 | } | |
4821 | ||
c0c050c5 MC |
4822 | static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) |
4823 | { | |
4824 | u32 i, j, max_rings; | |
4825 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4826 | struct hwrm_vnic_rss_cfg_input req = {0}; | |
4827 | ||
7b3af4f7 MC |
4828 | if ((bp->flags & BNXT_FLAG_CHIP_P5) || |
4829 | vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) | |
c0c050c5 MC |
4830 | return 0; |
4831 | ||
4832 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); | |
4833 | if (set_rss) { | |
87da7f79 | 4834 | req.hash_type = cpu_to_le32(bp->rss_hash_cfg); |
50f011b6 | 4835 | req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; |
dc52c6c7 PS |
4836 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) { |
4837 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
4838 | max_rings = bp->rx_nr_rings - 1; | |
4839 | else | |
4840 | max_rings = bp->rx_nr_rings; | |
4841 | } else { | |
c0c050c5 | 4842 | max_rings = 1; |
dc52c6c7 | 4843 | } |
c0c050c5 MC |
4844 | |
4845 | /* Fill the RSS indirection table with ring group ids */ | |
4846 | for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { | |
4847 | if (j == max_rings) | |
4848 | j = 0; | |
4849 | vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); | |
4850 | } | |
4851 | ||
4852 | req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); | |
4853 | req.hash_key_tbl_addr = | |
4854 | cpu_to_le64(vnic->rss_hash_key_dma_addr); | |
4855 | } | |
94ce9caa | 4856 | req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); |
c0c050c5 MC |
4857 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
4858 | } | |
4859 | ||
7b3af4f7 MC |
4860 | static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) |
4861 | { | |
4862 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4863 | u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings; | |
4864 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; | |
4865 | struct hwrm_vnic_rss_cfg_input req = {0}; | |
4866 | ||
4867 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); | |
4868 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); | |
4869 | if (!set_rss) { | |
4870 | hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4871 | return 0; | |
4872 | } | |
4873 | req.hash_type = cpu_to_le32(bp->rss_hash_cfg); | |
4874 | req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; | |
4875 | req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); | |
4876 | req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); | |
4877 | nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); | |
4878 | for (i = 0, k = 0; i < nr_ctxs; i++) { | |
4879 | __le16 *ring_tbl = vnic->rss_table; | |
4880 | int rc; | |
4881 | ||
4882 | req.ring_table_pair_index = i; | |
4883 | req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); | |
4884 | for (j = 0; j < 64; j++) { | |
4885 | u16 ring_id; | |
4886 | ||
4887 | ring_id = rxr->rx_ring_struct.fw_ring_id; | |
4888 | *ring_tbl++ = cpu_to_le16(ring_id); | |
4889 | ring_id = bnxt_cp_ring_for_rx(bp, rxr); | |
4890 | *ring_tbl++ = cpu_to_le16(ring_id); | |
4891 | rxr++; | |
4892 | k++; | |
4893 | if (k == max_rings) { | |
4894 | k = 0; | |
4895 | rxr = &bp->rx_ring[0]; | |
4896 | } | |
4897 | } | |
4898 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4899 | if (rc) | |
d4f1420d | 4900 | return rc; |
7b3af4f7 MC |
4901 | } |
4902 | return 0; | |
4903 | } | |
4904 | ||
c0c050c5 MC |
4905 | static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) |
4906 | { | |
4907 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; | |
4908 | struct hwrm_vnic_plcmodes_cfg_input req = {0}; | |
4909 | ||
4910 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); | |
4911 | req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | | |
4912 | VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | | |
4913 | VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); | |
4914 | req.enables = | |
4915 | cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | | |
4916 | VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); | |
4917 | /* thresholds not implemented in firmware yet */ | |
4918 | req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); | |
4919 | req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); | |
4920 | req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); | |
4921 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4922 | } | |
4923 | ||
94ce9caa PS |
4924 | static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, |
4925 | u16 ctx_idx) | |
c0c050c5 MC |
4926 | { |
4927 | struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; | |
4928 | ||
4929 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); | |
4930 | req.rss_cos_lb_ctx_id = | |
94ce9caa | 4931 | cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); |
c0c050c5 MC |
4932 | |
4933 | hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
94ce9caa | 4934 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; |
c0c050c5 MC |
4935 | } |
4936 | ||
4937 | static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) | |
4938 | { | |
94ce9caa | 4939 | int i, j; |
c0c050c5 MC |
4940 | |
4941 | for (i = 0; i < bp->nr_vnics; i++) { | |
4942 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; | |
4943 | ||
94ce9caa PS |
4944 | for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { |
4945 | if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) | |
4946 | bnxt_hwrm_vnic_ctx_free_one(bp, i, j); | |
4947 | } | |
c0c050c5 MC |
4948 | } |
4949 | bp->rsscos_nr_ctxs = 0; | |
4950 | } | |
4951 | ||
94ce9caa | 4952 | static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) |
c0c050c5 MC |
4953 | { |
4954 | int rc; | |
4955 | struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; | |
4956 | struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = | |
4957 | bp->hwrm_cmd_resp_addr; | |
4958 | ||
4959 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, | |
4960 | -1); | |
4961 | ||
4962 | mutex_lock(&bp->hwrm_cmd_lock); | |
4963 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
4964 | if (!rc) | |
94ce9caa | 4965 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = |
c0c050c5 MC |
4966 | le16_to_cpu(resp->rss_cos_lb_ctx_id); |
4967 | mutex_unlock(&bp->hwrm_cmd_lock); | |
4968 | ||
4969 | return rc; | |
4970 | } | |
4971 | ||
abe93ad2 MC |
4972 | static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) |
4973 | { | |
4974 | if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) | |
4975 | return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; | |
4976 | return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; | |
4977 | } | |
4978 | ||
a588e458 | 4979 | int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) |
c0c050c5 | 4980 | { |
b81a90d3 | 4981 | unsigned int ring = 0, grp_idx; |
c0c050c5 MC |
4982 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
4983 | struct hwrm_vnic_cfg_input req = {0}; | |
cf6645f8 | 4984 | u16 def_vlan = 0; |
c0c050c5 MC |
4985 | |
4986 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); | |
dc52c6c7 | 4987 | |
7b3af4f7 MC |
4988 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
4989 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; | |
4990 | ||
4991 | req.default_rx_ring_id = | |
4992 | cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); | |
4993 | req.default_cmpl_ring_id = | |
4994 | cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); | |
4995 | req.enables = | |
4996 | cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | | |
4997 | VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); | |
4998 | goto vnic_mru; | |
4999 | } | |
dc52c6c7 | 5000 | req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); |
c0c050c5 | 5001 | /* Only RSS support for now TBD: COS & LB */ |
dc52c6c7 PS |
5002 | if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { |
5003 | req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); | |
5004 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | | |
5005 | VNIC_CFG_REQ_ENABLES_MRU); | |
ae10ae74 MC |
5006 | } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { |
5007 | req.rss_rule = | |
5008 | cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); | |
5009 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | | |
5010 | VNIC_CFG_REQ_ENABLES_MRU); | |
5011 | req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); | |
dc52c6c7 PS |
5012 | } else { |
5013 | req.rss_rule = cpu_to_le16(0xffff); | |
5014 | } | |
94ce9caa | 5015 | |
dc52c6c7 PS |
5016 | if (BNXT_CHIP_TYPE_NITRO_A0(bp) && |
5017 | (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { | |
94ce9caa PS |
5018 | req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); |
5019 | req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); | |
5020 | } else { | |
5021 | req.cos_rule = cpu_to_le16(0xffff); | |
5022 | } | |
5023 | ||
c0c050c5 | 5024 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
b81a90d3 | 5025 | ring = 0; |
c0c050c5 | 5026 | else if (vnic->flags & BNXT_VNIC_RFS_FLAG) |
b81a90d3 | 5027 | ring = vnic_id - 1; |
76595193 PS |
5028 | else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) |
5029 | ring = bp->rx_nr_rings - 1; | |
c0c050c5 | 5030 | |
b81a90d3 | 5031 | grp_idx = bp->rx_ring[ring].bnapi->index; |
c0c050c5 | 5032 | req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); |
c0c050c5 | 5033 | req.lb_rule = cpu_to_le16(0xffff); |
7b3af4f7 | 5034 | vnic_mru: |
c0c050c5 MC |
5035 | req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + |
5036 | VLAN_HLEN); | |
5037 | ||
7b3af4f7 | 5038 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); |
cf6645f8 MC |
5039 | #ifdef CONFIG_BNXT_SRIOV |
5040 | if (BNXT_VF(bp)) | |
5041 | def_vlan = bp->vf.vlan; | |
5042 | #endif | |
5043 | if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) | |
c0c050c5 | 5044 | req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); |
a588e458 | 5045 | if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) |
abe93ad2 | 5046 | req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); |
c0c050c5 MC |
5047 | |
5048 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5049 | } | |
5050 | ||
5051 | static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) | |
5052 | { | |
5053 | u32 rc = 0; | |
5054 | ||
5055 | if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { | |
5056 | struct hwrm_vnic_free_input req = {0}; | |
5057 | ||
5058 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); | |
5059 | req.vnic_id = | |
5060 | cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); | |
5061 | ||
5062 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
c0c050c5 MC |
5063 | bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; |
5064 | } | |
5065 | return rc; | |
5066 | } | |
5067 | ||
5068 | static void bnxt_hwrm_vnic_free(struct bnxt *bp) | |
5069 | { | |
5070 | u16 i; | |
5071 | ||
5072 | for (i = 0; i < bp->nr_vnics; i++) | |
5073 | bnxt_hwrm_vnic_free_one(bp, i); | |
5074 | } | |
5075 | ||
b81a90d3 MC |
5076 | static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, |
5077 | unsigned int start_rx_ring_idx, | |
5078 | unsigned int nr_rings) | |
c0c050c5 | 5079 | { |
b81a90d3 MC |
5080 | int rc = 0; |
5081 | unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; | |
c0c050c5 MC |
5082 | struct hwrm_vnic_alloc_input req = {0}; |
5083 | struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
44c6f72a MC |
5084 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
5085 | ||
5086 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
5087 | goto vnic_no_ring_grps; | |
c0c050c5 MC |
5088 | |
5089 | /* map ring groups to this vnic */ | |
b81a90d3 MC |
5090 | for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { |
5091 | grp_idx = bp->rx_ring[i].bnapi->index; | |
5092 | if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { | |
c0c050c5 | 5093 | netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", |
b81a90d3 | 5094 | j, nr_rings); |
c0c050c5 MC |
5095 | break; |
5096 | } | |
44c6f72a | 5097 | vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; |
c0c050c5 MC |
5098 | } |
5099 | ||
44c6f72a MC |
5100 | vnic_no_ring_grps: |
5101 | for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) | |
5102 | vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5103 | if (vnic_id == 0) |
5104 | req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); | |
5105 | ||
5106 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); | |
5107 | ||
5108 | mutex_lock(&bp->hwrm_cmd_lock); | |
5109 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5110 | if (!rc) | |
44c6f72a | 5111 | vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); |
c0c050c5 MC |
5112 | mutex_unlock(&bp->hwrm_cmd_lock); |
5113 | return rc; | |
5114 | } | |
5115 | ||
8fdefd63 MC |
5116 | static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) |
5117 | { | |
5118 | struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
5119 | struct hwrm_vnic_qcaps_input req = {0}; | |
5120 | int rc; | |
5121 | ||
fbbdbc64 | 5122 | bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); |
ba642ab7 | 5123 | bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); |
8fdefd63 MC |
5124 | if (bp->hwrm_spec_code < 0x10600) |
5125 | return 0; | |
5126 | ||
5127 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); | |
5128 | mutex_lock(&bp->hwrm_cmd_lock); | |
5129 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5130 | if (!rc) { | |
abe93ad2 MC |
5131 | u32 flags = le32_to_cpu(resp->flags); |
5132 | ||
41e8d798 MC |
5133 | if (!(bp->flags & BNXT_FLAG_CHIP_P5) && |
5134 | (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) | |
8fdefd63 | 5135 | bp->flags |= BNXT_FLAG_NEW_RSS_CAP; |
abe93ad2 MC |
5136 | if (flags & |
5137 | VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) | |
5138 | bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; | |
79632e9b | 5139 | bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); |
4e748506 MC |
5140 | if (bp->max_tpa_v2) |
5141 | bp->hw_ring_stats_size = | |
5142 | sizeof(struct ctx_hw_stats_ext); | |
8fdefd63 MC |
5143 | } |
5144 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5145 | return rc; | |
5146 | } | |
5147 | ||
c0c050c5 MC |
5148 | static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) |
5149 | { | |
5150 | u16 i; | |
5151 | u32 rc = 0; | |
5152 | ||
44c6f72a MC |
5153 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5154 | return 0; | |
5155 | ||
c0c050c5 MC |
5156 | mutex_lock(&bp->hwrm_cmd_lock); |
5157 | for (i = 0; i < bp->rx_nr_rings; i++) { | |
5158 | struct hwrm_ring_grp_alloc_input req = {0}; | |
5159 | struct hwrm_ring_grp_alloc_output *resp = | |
5160 | bp->hwrm_cmd_resp_addr; | |
b81a90d3 | 5161 | unsigned int grp_idx = bp->rx_ring[i].bnapi->index; |
c0c050c5 MC |
5162 | |
5163 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); | |
5164 | ||
b81a90d3 MC |
5165 | req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); |
5166 | req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); | |
5167 | req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); | |
5168 | req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); | |
c0c050c5 MC |
5169 | |
5170 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
5171 | HWRM_CMD_TIMEOUT); | |
5172 | if (rc) | |
5173 | break; | |
5174 | ||
b81a90d3 MC |
5175 | bp->grp_info[grp_idx].fw_grp_id = |
5176 | le32_to_cpu(resp->ring_group_id); | |
c0c050c5 MC |
5177 | } |
5178 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5179 | return rc; | |
5180 | } | |
5181 | ||
5182 | static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) | |
5183 | { | |
5184 | u16 i; | |
5185 | u32 rc = 0; | |
5186 | struct hwrm_ring_grp_free_input req = {0}; | |
5187 | ||
44c6f72a | 5188 | if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) |
c0c050c5 MC |
5189 | return 0; |
5190 | ||
5191 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); | |
5192 | ||
5193 | mutex_lock(&bp->hwrm_cmd_lock); | |
5194 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
5195 | if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) | |
5196 | continue; | |
5197 | req.ring_group_id = | |
5198 | cpu_to_le32(bp->grp_info[i].fw_grp_id); | |
5199 | ||
5200 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
5201 | HWRM_CMD_TIMEOUT); | |
c0c050c5 MC |
5202 | bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; |
5203 | } | |
5204 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5205 | return rc; | |
5206 | } | |
5207 | ||
5208 | static int hwrm_ring_alloc_send_msg(struct bnxt *bp, | |
5209 | struct bnxt_ring_struct *ring, | |
9899bb59 | 5210 | u32 ring_type, u32 map_index) |
c0c050c5 MC |
5211 | { |
5212 | int rc = 0, err = 0; | |
5213 | struct hwrm_ring_alloc_input req = {0}; | |
5214 | struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
6fe19886 | 5215 | struct bnxt_ring_mem_info *rmem = &ring->ring_mem; |
9899bb59 | 5216 | struct bnxt_ring_grp_info *grp_info; |
c0c050c5 MC |
5217 | u16 ring_id; |
5218 | ||
5219 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); | |
5220 | ||
5221 | req.enables = 0; | |
6fe19886 MC |
5222 | if (rmem->nr_pages > 1) { |
5223 | req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); | |
c0c050c5 MC |
5224 | /* Page size is in log2 units */ |
5225 | req.page_size = BNXT_PAGE_SHIFT; | |
5226 | req.page_tbl_depth = 1; | |
5227 | } else { | |
6fe19886 | 5228 | req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); |
c0c050c5 MC |
5229 | } |
5230 | req.fbo = 0; | |
5231 | /* Association of ring index with doorbell index and MSIX number */ | |
5232 | req.logical_id = cpu_to_le16(map_index); | |
5233 | ||
5234 | switch (ring_type) { | |
2c61d211 MC |
5235 | case HWRM_RING_ALLOC_TX: { |
5236 | struct bnxt_tx_ring_info *txr; | |
5237 | ||
5238 | txr = container_of(ring, struct bnxt_tx_ring_info, | |
5239 | tx_ring_struct); | |
c0c050c5 MC |
5240 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; |
5241 | /* Association of transmit ring with completion ring */ | |
9899bb59 | 5242 | grp_info = &bp->grp_info[ring->grp_idx]; |
2c61d211 | 5243 | req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); |
c0c050c5 | 5244 | req.length = cpu_to_le32(bp->tx_ring_mask + 1); |
9899bb59 | 5245 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); |
c0c050c5 MC |
5246 | req.queue_id = cpu_to_le16(ring->queue_id); |
5247 | break; | |
2c61d211 | 5248 | } |
c0c050c5 MC |
5249 | case HWRM_RING_ALLOC_RX: |
5250 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; | |
5251 | req.length = cpu_to_le32(bp->rx_ring_mask + 1); | |
23aefdd7 MC |
5252 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5253 | u16 flags = 0; | |
5254 | ||
5255 | /* Association of rx ring with stats context */ | |
5256 | grp_info = &bp->grp_info[ring->grp_idx]; | |
5257 | req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); | |
5258 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); | |
5259 | req.enables |= cpu_to_le32( | |
5260 | RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); | |
5261 | if (NET_IP_ALIGN == 2) | |
5262 | flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; | |
5263 | req.flags = cpu_to_le16(flags); | |
5264 | } | |
c0c050c5 MC |
5265 | break; |
5266 | case HWRM_RING_ALLOC_AGG: | |
23aefdd7 MC |
5267 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5268 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; | |
5269 | /* Association of agg ring with rx ring */ | |
5270 | grp_info = &bp->grp_info[ring->grp_idx]; | |
5271 | req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); | |
5272 | req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); | |
5273 | req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); | |
5274 | req.enables |= cpu_to_le32( | |
5275 | RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | | |
5276 | RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); | |
5277 | } else { | |
5278 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; | |
5279 | } | |
c0c050c5 MC |
5280 | req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); |
5281 | break; | |
5282 | case HWRM_RING_ALLOC_CMPL: | |
bac9a7e0 | 5283 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; |
c0c050c5 | 5284 | req.length = cpu_to_le32(bp->cp_ring_mask + 1); |
23aefdd7 MC |
5285 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5286 | /* Association of cp ring with nq */ | |
5287 | grp_info = &bp->grp_info[map_index]; | |
5288 | req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); | |
5289 | req.cq_handle = cpu_to_le64(ring->handle); | |
5290 | req.enables |= cpu_to_le32( | |
5291 | RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); | |
5292 | } else if (bp->flags & BNXT_FLAG_USING_MSIX) { | |
5293 | req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; | |
5294 | } | |
5295 | break; | |
5296 | case HWRM_RING_ALLOC_NQ: | |
5297 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; | |
5298 | req.length = cpu_to_le32(bp->cp_ring_mask + 1); | |
c0c050c5 MC |
5299 | if (bp->flags & BNXT_FLAG_USING_MSIX) |
5300 | req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; | |
5301 | break; | |
5302 | default: | |
5303 | netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", | |
5304 | ring_type); | |
5305 | return -1; | |
5306 | } | |
5307 | ||
5308 | mutex_lock(&bp->hwrm_cmd_lock); | |
5309 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5310 | err = le16_to_cpu(resp->error_code); | |
5311 | ring_id = le16_to_cpu(resp->ring_id); | |
5312 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5313 | ||
5314 | if (rc || err) { | |
2727c888 MC |
5315 | netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", |
5316 | ring_type, rc, err); | |
5317 | return -EIO; | |
c0c050c5 MC |
5318 | } |
5319 | ring->fw_ring_id = ring_id; | |
5320 | return rc; | |
5321 | } | |
5322 | ||
486b5c22 MC |
5323 | static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) |
5324 | { | |
5325 | int rc; | |
5326 | ||
5327 | if (BNXT_PF(bp)) { | |
5328 | struct hwrm_func_cfg_input req = {0}; | |
5329 | ||
5330 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
5331 | req.fid = cpu_to_le16(0xffff); | |
5332 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); | |
5333 | req.async_event_cr = cpu_to_le16(idx); | |
5334 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5335 | } else { | |
5336 | struct hwrm_func_vf_cfg_input req = {0}; | |
5337 | ||
5338 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); | |
5339 | req.enables = | |
5340 | cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); | |
5341 | req.async_event_cr = cpu_to_le16(idx); | |
5342 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5343 | } | |
5344 | return rc; | |
5345 | } | |
5346 | ||
697197e5 MC |
5347 | static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, |
5348 | u32 map_idx, u32 xid) | |
5349 | { | |
5350 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
5351 | if (BNXT_PF(bp)) | |
5352 | db->doorbell = bp->bar1 + 0x10000; | |
5353 | else | |
5354 | db->doorbell = bp->bar1 + 0x4000; | |
5355 | switch (ring_type) { | |
5356 | case HWRM_RING_ALLOC_TX: | |
5357 | db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; | |
5358 | break; | |
5359 | case HWRM_RING_ALLOC_RX: | |
5360 | case HWRM_RING_ALLOC_AGG: | |
5361 | db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; | |
5362 | break; | |
5363 | case HWRM_RING_ALLOC_CMPL: | |
5364 | db->db_key64 = DBR_PATH_L2; | |
5365 | break; | |
5366 | case HWRM_RING_ALLOC_NQ: | |
5367 | db->db_key64 = DBR_PATH_L2; | |
5368 | break; | |
5369 | } | |
5370 | db->db_key64 |= (u64)xid << DBR_XID_SFT; | |
5371 | } else { | |
5372 | db->doorbell = bp->bar1 + map_idx * 0x80; | |
5373 | switch (ring_type) { | |
5374 | case HWRM_RING_ALLOC_TX: | |
5375 | db->db_key32 = DB_KEY_TX; | |
5376 | break; | |
5377 | case HWRM_RING_ALLOC_RX: | |
5378 | case HWRM_RING_ALLOC_AGG: | |
5379 | db->db_key32 = DB_KEY_RX; | |
5380 | break; | |
5381 | case HWRM_RING_ALLOC_CMPL: | |
5382 | db->db_key32 = DB_KEY_CP; | |
5383 | break; | |
5384 | } | |
5385 | } | |
5386 | } | |
5387 | ||
c0c050c5 MC |
5388 | static int bnxt_hwrm_ring_alloc(struct bnxt *bp) |
5389 | { | |
e8f267b0 | 5390 | bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); |
c0c050c5 | 5391 | int i, rc = 0; |
697197e5 | 5392 | u32 type; |
c0c050c5 | 5393 | |
23aefdd7 MC |
5394 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5395 | type = HWRM_RING_ALLOC_NQ; | |
5396 | else | |
5397 | type = HWRM_RING_ALLOC_CMPL; | |
edd0c2cc MC |
5398 | for (i = 0; i < bp->cp_nr_rings; i++) { |
5399 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
5400 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
5401 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
9899bb59 | 5402 | u32 map_idx = ring->map_idx; |
5e66e35a | 5403 | unsigned int vector; |
c0c050c5 | 5404 | |
5e66e35a MC |
5405 | vector = bp->irq_tbl[map_idx].vector; |
5406 | disable_irq_nosync(vector); | |
697197e5 | 5407 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
5e66e35a MC |
5408 | if (rc) { |
5409 | enable_irq(vector); | |
edd0c2cc | 5410 | goto err_out; |
5e66e35a | 5411 | } |
697197e5 MC |
5412 | bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); |
5413 | bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); | |
5e66e35a | 5414 | enable_irq(vector); |
edd0c2cc | 5415 | bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; |
486b5c22 MC |
5416 | |
5417 | if (!i) { | |
5418 | rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); | |
5419 | if (rc) | |
5420 | netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); | |
5421 | } | |
c0c050c5 MC |
5422 | } |
5423 | ||
697197e5 | 5424 | type = HWRM_RING_ALLOC_TX; |
edd0c2cc | 5425 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 5426 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
3e08b184 MC |
5427 | struct bnxt_ring_struct *ring; |
5428 | u32 map_idx; | |
c0c050c5 | 5429 | |
3e08b184 MC |
5430 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5431 | struct bnxt_napi *bnapi = txr->bnapi; | |
5432 | struct bnxt_cp_ring_info *cpr, *cpr2; | |
5433 | u32 type2 = HWRM_RING_ALLOC_CMPL; | |
5434 | ||
5435 | cpr = &bnapi->cp_ring; | |
5436 | cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; | |
5437 | ring = &cpr2->cp_ring_struct; | |
5438 | ring->handle = BNXT_TX_HDL; | |
5439 | map_idx = bnapi->index; | |
5440 | rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); | |
5441 | if (rc) | |
5442 | goto err_out; | |
5443 | bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, | |
5444 | ring->fw_ring_id); | |
5445 | bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); | |
5446 | } | |
5447 | ring = &txr->tx_ring_struct; | |
5448 | map_idx = i; | |
697197e5 | 5449 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
edd0c2cc MC |
5450 | if (rc) |
5451 | goto err_out; | |
697197e5 | 5452 | bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); |
c0c050c5 MC |
5453 | } |
5454 | ||
697197e5 | 5455 | type = HWRM_RING_ALLOC_RX; |
edd0c2cc | 5456 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5457 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5458 | struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; |
3e08b184 MC |
5459 | struct bnxt_napi *bnapi = rxr->bnapi; |
5460 | u32 map_idx = bnapi->index; | |
c0c050c5 | 5461 | |
697197e5 | 5462 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
edd0c2cc MC |
5463 | if (rc) |
5464 | goto err_out; | |
697197e5 | 5465 | bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); |
e8f267b0 MC |
5466 | /* If we have agg rings, post agg buffers first. */ |
5467 | if (!agg_rings) | |
5468 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); | |
b81a90d3 | 5469 | bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; |
3e08b184 MC |
5470 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5471 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
5472 | u32 type2 = HWRM_RING_ALLOC_CMPL; | |
5473 | struct bnxt_cp_ring_info *cpr2; | |
5474 | ||
5475 | cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; | |
5476 | ring = &cpr2->cp_ring_struct; | |
5477 | ring->handle = BNXT_RX_HDL; | |
5478 | rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); | |
5479 | if (rc) | |
5480 | goto err_out; | |
5481 | bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, | |
5482 | ring->fw_ring_id); | |
5483 | bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); | |
5484 | } | |
c0c050c5 MC |
5485 | } |
5486 | ||
e8f267b0 | 5487 | if (agg_rings) { |
697197e5 | 5488 | type = HWRM_RING_ALLOC_AGG; |
c0c050c5 | 5489 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5490 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
c0c050c5 MC |
5491 | struct bnxt_ring_struct *ring = |
5492 | &rxr->rx_agg_ring_struct; | |
9899bb59 | 5493 | u32 grp_idx = ring->grp_idx; |
b81a90d3 | 5494 | u32 map_idx = grp_idx + bp->rx_nr_rings; |
c0c050c5 | 5495 | |
697197e5 | 5496 | rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); |
c0c050c5 MC |
5497 | if (rc) |
5498 | goto err_out; | |
5499 | ||
697197e5 MC |
5500 | bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, |
5501 | ring->fw_ring_id); | |
5502 | bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); | |
e8f267b0 | 5503 | bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); |
b81a90d3 | 5504 | bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; |
c0c050c5 MC |
5505 | } |
5506 | } | |
5507 | err_out: | |
5508 | return rc; | |
5509 | } | |
5510 | ||
5511 | static int hwrm_ring_free_send_msg(struct bnxt *bp, | |
5512 | struct bnxt_ring_struct *ring, | |
5513 | u32 ring_type, int cmpl_ring_id) | |
5514 | { | |
5515 | int rc; | |
5516 | struct hwrm_ring_free_input req = {0}; | |
5517 | struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; | |
5518 | u16 error_code; | |
5519 | ||
b4fff207 MC |
5520 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
5521 | return 0; | |
5522 | ||
74608fc9 | 5523 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); |
c0c050c5 MC |
5524 | req.ring_type = ring_type; |
5525 | req.ring_id = cpu_to_le16(ring->fw_ring_id); | |
5526 | ||
5527 | mutex_lock(&bp->hwrm_cmd_lock); | |
5528 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5529 | error_code = le16_to_cpu(resp->error_code); | |
5530 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5531 | ||
5532 | if (rc || error_code) { | |
2727c888 MC |
5533 | netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", |
5534 | ring_type, rc, error_code); | |
5535 | return -EIO; | |
c0c050c5 MC |
5536 | } |
5537 | return 0; | |
5538 | } | |
5539 | ||
edd0c2cc | 5540 | static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) |
c0c050c5 | 5541 | { |
23aefdd7 | 5542 | u32 type; |
edd0c2cc | 5543 | int i; |
c0c050c5 MC |
5544 | |
5545 | if (!bp->bnapi) | |
edd0c2cc | 5546 | return; |
c0c050c5 | 5547 | |
edd0c2cc | 5548 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 5549 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
edd0c2cc | 5550 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
edd0c2cc MC |
5551 | |
5552 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5553 | u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); |
5554 | ||
edd0c2cc MC |
5555 | hwrm_ring_free_send_msg(bp, ring, |
5556 | RING_FREE_REQ_RING_TYPE_TX, | |
5557 | close_path ? cmpl_ring_id : | |
5558 | INVALID_HW_RING_ID); | |
5559 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5560 | } |
5561 | } | |
5562 | ||
edd0c2cc | 5563 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5564 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5565 | struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; |
b81a90d3 | 5566 | u32 grp_idx = rxr->bnapi->index; |
edd0c2cc MC |
5567 | |
5568 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5569 | u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); |
5570 | ||
edd0c2cc MC |
5571 | hwrm_ring_free_send_msg(bp, ring, |
5572 | RING_FREE_REQ_RING_TYPE_RX, | |
5573 | close_path ? cmpl_ring_id : | |
5574 | INVALID_HW_RING_ID); | |
5575 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
b81a90d3 MC |
5576 | bp->grp_info[grp_idx].rx_fw_ring_id = |
5577 | INVALID_HW_RING_ID; | |
c0c050c5 MC |
5578 | } |
5579 | } | |
5580 | ||
23aefdd7 MC |
5581 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5582 | type = RING_FREE_REQ_RING_TYPE_RX_AGG; | |
5583 | else | |
5584 | type = RING_FREE_REQ_RING_TYPE_RX; | |
edd0c2cc | 5585 | for (i = 0; i < bp->rx_nr_rings; i++) { |
b6ab4b01 | 5586 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
edd0c2cc | 5587 | struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; |
b81a90d3 | 5588 | u32 grp_idx = rxr->bnapi->index; |
edd0c2cc MC |
5589 | |
5590 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
1f83391b MC |
5591 | u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); |
5592 | ||
23aefdd7 | 5593 | hwrm_ring_free_send_msg(bp, ring, type, |
edd0c2cc MC |
5594 | close_path ? cmpl_ring_id : |
5595 | INVALID_HW_RING_ID); | |
5596 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
b81a90d3 MC |
5597 | bp->grp_info[grp_idx].agg_fw_ring_id = |
5598 | INVALID_HW_RING_ID; | |
c0c050c5 MC |
5599 | } |
5600 | } | |
5601 | ||
9d8bc097 MC |
5602 | /* The completion rings are about to be freed. After that the |
5603 | * IRQ doorbell will not work anymore. So we need to disable | |
5604 | * IRQ here. | |
5605 | */ | |
5606 | bnxt_disable_int_sync(bp); | |
5607 | ||
23aefdd7 MC |
5608 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
5609 | type = RING_FREE_REQ_RING_TYPE_NQ; | |
5610 | else | |
5611 | type = RING_FREE_REQ_RING_TYPE_L2_CMPL; | |
edd0c2cc MC |
5612 | for (i = 0; i < bp->cp_nr_rings; i++) { |
5613 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
5614 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
3e08b184 MC |
5615 | struct bnxt_ring_struct *ring; |
5616 | int j; | |
edd0c2cc | 5617 | |
3e08b184 MC |
5618 | for (j = 0; j < 2; j++) { |
5619 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
5620 | ||
5621 | if (cpr2) { | |
5622 | ring = &cpr2->cp_ring_struct; | |
5623 | if (ring->fw_ring_id == INVALID_HW_RING_ID) | |
5624 | continue; | |
5625 | hwrm_ring_free_send_msg(bp, ring, | |
5626 | RING_FREE_REQ_RING_TYPE_L2_CMPL, | |
5627 | INVALID_HW_RING_ID); | |
5628 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
5629 | } | |
5630 | } | |
5631 | ring = &cpr->cp_ring_struct; | |
edd0c2cc | 5632 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { |
23aefdd7 | 5633 | hwrm_ring_free_send_msg(bp, ring, type, |
edd0c2cc MC |
5634 | INVALID_HW_RING_ID); |
5635 | ring->fw_ring_id = INVALID_HW_RING_ID; | |
5636 | bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; | |
c0c050c5 MC |
5637 | } |
5638 | } | |
c0c050c5 MC |
5639 | } |
5640 | ||
41e8d798 MC |
5641 | static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, |
5642 | bool shared); | |
5643 | ||
674f50a5 MC |
5644 | static int bnxt_hwrm_get_rings(struct bnxt *bp) |
5645 | { | |
5646 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
5647 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
5648 | struct hwrm_func_qcfg_input req = {0}; | |
5649 | int rc; | |
5650 | ||
5651 | if (bp->hwrm_spec_code < 0x10601) | |
5652 | return 0; | |
5653 | ||
5654 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
5655 | req.fid = cpu_to_le16(0xffff); | |
5656 | mutex_lock(&bp->hwrm_cmd_lock); | |
5657 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5658 | if (rc) { | |
5659 | mutex_unlock(&bp->hwrm_cmd_lock); | |
d4f1420d | 5660 | return rc; |
674f50a5 MC |
5661 | } |
5662 | ||
5663 | hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); | |
f1ca94de | 5664 | if (BNXT_NEW_RM(bp)) { |
674f50a5 MC |
5665 | u16 cp, stats; |
5666 | ||
5667 | hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); | |
5668 | hw_resc->resv_hw_ring_grps = | |
5669 | le32_to_cpu(resp->alloc_hw_ring_grps); | |
5670 | hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); | |
5671 | cp = le16_to_cpu(resp->alloc_cmpl_rings); | |
5672 | stats = le16_to_cpu(resp->alloc_stat_ctx); | |
75720e63 | 5673 | hw_resc->resv_irqs = cp; |
41e8d798 MC |
5674 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5675 | int rx = hw_resc->resv_rx_rings; | |
5676 | int tx = hw_resc->resv_tx_rings; | |
5677 | ||
5678 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5679 | rx >>= 1; | |
5680 | if (cp < (rx + tx)) { | |
5681 | bnxt_trim_rings(bp, &rx, &tx, cp, false); | |
5682 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5683 | rx <<= 1; | |
5684 | hw_resc->resv_rx_rings = rx; | |
5685 | hw_resc->resv_tx_rings = tx; | |
5686 | } | |
75720e63 | 5687 | hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); |
41e8d798 MC |
5688 | hw_resc->resv_hw_ring_grps = rx; |
5689 | } | |
674f50a5 | 5690 | hw_resc->resv_cp_rings = cp; |
780baad4 | 5691 | hw_resc->resv_stat_ctxs = stats; |
674f50a5 MC |
5692 | } |
5693 | mutex_unlock(&bp->hwrm_cmd_lock); | |
5694 | return 0; | |
5695 | } | |
5696 | ||
391be5c2 MC |
5697 | /* Caller must hold bp->hwrm_cmd_lock */ |
5698 | int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) | |
5699 | { | |
5700 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
5701 | struct hwrm_func_qcfg_input req = {0}; | |
5702 | int rc; | |
5703 | ||
5704 | if (bp->hwrm_spec_code < 0x10601) | |
5705 | return 0; | |
5706 | ||
5707 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
5708 | req.fid = cpu_to_le16(fid); | |
5709 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
5710 | if (!rc) | |
5711 | *tx_rings = le16_to_cpu(resp->alloc_tx_rings); | |
5712 | ||
5713 | return rc; | |
5714 | } | |
5715 | ||
41e8d798 MC |
5716 | static bool bnxt_rfs_supported(struct bnxt *bp); |
5717 | ||
4ed50ef4 MC |
5718 | static void |
5719 | __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, | |
5720 | int tx_rings, int rx_rings, int ring_grps, | |
780baad4 | 5721 | int cp_rings, int stats, int vnics) |
391be5c2 | 5722 | { |
674f50a5 | 5723 | u32 enables = 0; |
391be5c2 | 5724 | |
4ed50ef4 MC |
5725 | bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); |
5726 | req->fid = cpu_to_le16(0xffff); | |
674f50a5 | 5727 | enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; |
4ed50ef4 | 5728 | req->num_tx_rings = cpu_to_le16(tx_rings); |
f1ca94de | 5729 | if (BNXT_NEW_RM(bp)) { |
674f50a5 | 5730 | enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; |
3f93cd3f | 5731 | enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; |
41e8d798 MC |
5732 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5733 | enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; | |
5734 | enables |= tx_rings + ring_grps ? | |
3f93cd3f | 5735 | FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5736 | enables |= rx_rings ? |
5737 | FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
5738 | } else { | |
5739 | enables |= cp_rings ? | |
3f93cd3f | 5740 | FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5741 | enables |= ring_grps ? |
5742 | FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | | |
5743 | FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
5744 | } | |
dbe80d44 | 5745 | enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; |
674f50a5 | 5746 | |
4ed50ef4 | 5747 | req->num_rx_rings = cpu_to_le16(rx_rings); |
41e8d798 MC |
5748 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5749 | req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); | |
5750 | req->num_msix = cpu_to_le16(cp_rings); | |
5751 | req->num_rsscos_ctxs = | |
5752 | cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); | |
5753 | } else { | |
5754 | req->num_cmpl_rings = cpu_to_le16(cp_rings); | |
5755 | req->num_hw_ring_grps = cpu_to_le16(ring_grps); | |
5756 | req->num_rsscos_ctxs = cpu_to_le16(1); | |
5757 | if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && | |
5758 | bnxt_rfs_supported(bp)) | |
5759 | req->num_rsscos_ctxs = | |
5760 | cpu_to_le16(ring_grps + 1); | |
5761 | } | |
780baad4 | 5762 | req->num_stat_ctxs = cpu_to_le16(stats); |
4ed50ef4 | 5763 | req->num_vnics = cpu_to_le16(vnics); |
674f50a5 | 5764 | } |
4ed50ef4 MC |
5765 | req->enables = cpu_to_le32(enables); |
5766 | } | |
5767 | ||
5768 | static void | |
5769 | __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, | |
5770 | struct hwrm_func_vf_cfg_input *req, int tx_rings, | |
5771 | int rx_rings, int ring_grps, int cp_rings, | |
780baad4 | 5772 | int stats, int vnics) |
4ed50ef4 MC |
5773 | { |
5774 | u32 enables = 0; | |
5775 | ||
5776 | bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); | |
5777 | enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; | |
41e8d798 MC |
5778 | enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | |
5779 | FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; | |
3f93cd3f | 5780 | enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; |
41e8d798 MC |
5781 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5782 | enables |= tx_rings + ring_grps ? | |
3f93cd3f | 5783 | FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5784 | } else { |
5785 | enables |= cp_rings ? | |
3f93cd3f | 5786 | FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; |
41e8d798 MC |
5787 | enables |= ring_grps ? |
5788 | FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; | |
5789 | } | |
4ed50ef4 | 5790 | enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; |
41e8d798 | 5791 | enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; |
4ed50ef4 | 5792 | |
41e8d798 | 5793 | req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); |
4ed50ef4 MC |
5794 | req->num_tx_rings = cpu_to_le16(tx_rings); |
5795 | req->num_rx_rings = cpu_to_le16(rx_rings); | |
41e8d798 MC |
5796 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
5797 | req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); | |
5798 | req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); | |
5799 | } else { | |
5800 | req->num_cmpl_rings = cpu_to_le16(cp_rings); | |
5801 | req->num_hw_ring_grps = cpu_to_le16(ring_grps); | |
5802 | req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); | |
5803 | } | |
780baad4 | 5804 | req->num_stat_ctxs = cpu_to_le16(stats); |
4ed50ef4 MC |
5805 | req->num_vnics = cpu_to_le16(vnics); |
5806 | ||
5807 | req->enables = cpu_to_le32(enables); | |
5808 | } | |
5809 | ||
5810 | static int | |
5811 | bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 | 5812 | int ring_grps, int cp_rings, int stats, int vnics) |
4ed50ef4 MC |
5813 | { |
5814 | struct hwrm_func_cfg_input req = {0}; | |
5815 | int rc; | |
5816 | ||
5817 | __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, | |
780baad4 | 5818 | cp_rings, stats, vnics); |
4ed50ef4 | 5819 | if (!req.enables) |
391be5c2 MC |
5820 | return 0; |
5821 | ||
674f50a5 MC |
5822 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
5823 | if (rc) | |
d4f1420d | 5824 | return rc; |
674f50a5 MC |
5825 | |
5826 | if (bp->hwrm_spec_code < 0x10601) | |
5827 | bp->hw_resc.resv_tx_rings = tx_rings; | |
5828 | ||
5829 | rc = bnxt_hwrm_get_rings(bp); | |
5830 | return rc; | |
5831 | } | |
5832 | ||
5833 | static int | |
5834 | bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 | 5835 | int ring_grps, int cp_rings, int stats, int vnics) |
674f50a5 MC |
5836 | { |
5837 | struct hwrm_func_vf_cfg_input req = {0}; | |
674f50a5 MC |
5838 | int rc; |
5839 | ||
f1ca94de | 5840 | if (!BNXT_NEW_RM(bp)) { |
674f50a5 | 5841 | bp->hw_resc.resv_tx_rings = tx_rings; |
391be5c2 | 5842 | return 0; |
674f50a5 | 5843 | } |
391be5c2 | 5844 | |
4ed50ef4 | 5845 | __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 5846 | cp_rings, stats, vnics); |
391be5c2 | 5847 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
674f50a5 | 5848 | if (rc) |
d4f1420d | 5849 | return rc; |
674f50a5 MC |
5850 | |
5851 | rc = bnxt_hwrm_get_rings(bp); | |
5852 | return rc; | |
5853 | } | |
5854 | ||
5855 | static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, | |
780baad4 | 5856 | int cp, int stat, int vnic) |
674f50a5 MC |
5857 | { |
5858 | if (BNXT_PF(bp)) | |
780baad4 VV |
5859 | return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, |
5860 | vnic); | |
674f50a5 | 5861 | else |
780baad4 VV |
5862 | return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, |
5863 | vnic); | |
674f50a5 MC |
5864 | } |
5865 | ||
b16b6891 | 5866 | int bnxt_nq_rings_in_use(struct bnxt *bp) |
08654eb2 MC |
5867 | { |
5868 | int cp = bp->cp_nr_rings; | |
5869 | int ulp_msix, ulp_base; | |
5870 | ||
5871 | ulp_msix = bnxt_get_ulp_msix_num(bp); | |
5872 | if (ulp_msix) { | |
5873 | ulp_base = bnxt_get_ulp_msix_base(bp); | |
5874 | cp += ulp_msix; | |
5875 | if ((ulp_base + ulp_msix) > cp) | |
5876 | cp = ulp_base + ulp_msix; | |
5877 | } | |
5878 | return cp; | |
5879 | } | |
5880 | ||
c0b8cda0 MC |
5881 | static int bnxt_cp_rings_in_use(struct bnxt *bp) |
5882 | { | |
5883 | int cp; | |
5884 | ||
5885 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
5886 | return bnxt_nq_rings_in_use(bp); | |
5887 | ||
5888 | cp = bp->tx_nr_rings + bp->rx_nr_rings; | |
5889 | return cp; | |
5890 | } | |
5891 | ||
780baad4 VV |
5892 | static int bnxt_get_func_stat_ctxs(struct bnxt *bp) |
5893 | { | |
d77b1ad8 MC |
5894 | int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); |
5895 | int cp = bp->cp_nr_rings; | |
5896 | ||
5897 | if (!ulp_stat) | |
5898 | return cp; | |
5899 | ||
5900 | if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) | |
5901 | return bnxt_get_ulp_msix_base(bp) + ulp_stat; | |
5902 | ||
5903 | return cp + ulp_stat; | |
780baad4 VV |
5904 | } |
5905 | ||
4e41dc5d MC |
5906 | static bool bnxt_need_reserve_rings(struct bnxt *bp) |
5907 | { | |
5908 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
fbcfc8e4 | 5909 | int cp = bnxt_cp_rings_in_use(bp); |
c0b8cda0 | 5910 | int nq = bnxt_nq_rings_in_use(bp); |
780baad4 | 5911 | int rx = bp->rx_nr_rings, stat; |
4e41dc5d MC |
5912 | int vnic = 1, grp = rx; |
5913 | ||
5914 | if (bp->hwrm_spec_code < 0x10601) | |
5915 | return false; | |
5916 | ||
5917 | if (hw_resc->resv_tx_rings != bp->tx_nr_rings) | |
5918 | return true; | |
5919 | ||
41e8d798 | 5920 | if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) |
4e41dc5d MC |
5921 | vnic = rx + 1; |
5922 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5923 | rx <<= 1; | |
780baad4 | 5924 | stat = bnxt_get_func_stat_ctxs(bp); |
f1ca94de | 5925 | if (BNXT_NEW_RM(bp) && |
4e41dc5d | 5926 | (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || |
01989c6b | 5927 | hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || |
41e8d798 MC |
5928 | (hw_resc->resv_hw_ring_grps != grp && |
5929 | !(bp->flags & BNXT_FLAG_CHIP_P5)))) | |
4e41dc5d | 5930 | return true; |
01989c6b MC |
5931 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && |
5932 | hw_resc->resv_irqs != nq) | |
5933 | return true; | |
4e41dc5d MC |
5934 | return false; |
5935 | } | |
5936 | ||
674f50a5 MC |
5937 | static int __bnxt_reserve_rings(struct bnxt *bp) |
5938 | { | |
5939 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
c0b8cda0 | 5940 | int cp = bnxt_nq_rings_in_use(bp); |
674f50a5 MC |
5941 | int tx = bp->tx_nr_rings; |
5942 | int rx = bp->rx_nr_rings; | |
674f50a5 | 5943 | int grp, rx_rings, rc; |
780baad4 | 5944 | int vnic = 1, stat; |
674f50a5 | 5945 | bool sh = false; |
674f50a5 | 5946 | |
4e41dc5d | 5947 | if (!bnxt_need_reserve_rings(bp)) |
674f50a5 MC |
5948 | return 0; |
5949 | ||
5950 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
5951 | sh = true; | |
41e8d798 | 5952 | if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) |
674f50a5 MC |
5953 | vnic = rx + 1; |
5954 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5955 | rx <<= 1; | |
674f50a5 | 5956 | grp = bp->rx_nr_rings; |
780baad4 | 5957 | stat = bnxt_get_func_stat_ctxs(bp); |
674f50a5 | 5958 | |
780baad4 | 5959 | rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); |
391be5c2 MC |
5960 | if (rc) |
5961 | return rc; | |
5962 | ||
674f50a5 | 5963 | tx = hw_resc->resv_tx_rings; |
f1ca94de | 5964 | if (BNXT_NEW_RM(bp)) { |
674f50a5 | 5965 | rx = hw_resc->resv_rx_rings; |
c0b8cda0 | 5966 | cp = hw_resc->resv_irqs; |
674f50a5 MC |
5967 | grp = hw_resc->resv_hw_ring_grps; |
5968 | vnic = hw_resc->resv_vnics; | |
780baad4 | 5969 | stat = hw_resc->resv_stat_ctxs; |
674f50a5 MC |
5970 | } |
5971 | ||
5972 | rx_rings = rx; | |
5973 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
5974 | if (rx >= 2) { | |
5975 | rx_rings = rx >> 1; | |
5976 | } else { | |
5977 | if (netif_running(bp->dev)) | |
5978 | return -ENOMEM; | |
5979 | ||
5980 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; | |
5981 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS; | |
5982 | bp->dev->hw_features &= ~NETIF_F_LRO; | |
5983 | bp->dev->features &= ~NETIF_F_LRO; | |
5984 | bnxt_set_ring_params(bp); | |
5985 | } | |
5986 | } | |
5987 | rx_rings = min_t(int, rx_rings, grp); | |
780baad4 VV |
5988 | cp = min_t(int, cp, bp->cp_nr_rings); |
5989 | if (stat > bnxt_get_ulp_stat_ctxs(bp)) | |
5990 | stat -= bnxt_get_ulp_stat_ctxs(bp); | |
5991 | cp = min_t(int, cp, stat); | |
674f50a5 MC |
5992 | rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); |
5993 | if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
5994 | rx = rx_rings << 1; | |
5995 | cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; | |
5996 | bp->tx_nr_rings = tx; | |
5997 | bp->rx_nr_rings = rx_rings; | |
5998 | bp->cp_nr_rings = cp; | |
5999 | ||
780baad4 | 6000 | if (!tx || !rx || !cp || !grp || !vnic || !stat) |
674f50a5 MC |
6001 | return -ENOMEM; |
6002 | ||
391be5c2 MC |
6003 | return rc; |
6004 | } | |
6005 | ||
8f23d638 | 6006 | static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, |
780baad4 VV |
6007 | int ring_grps, int cp_rings, int stats, |
6008 | int vnics) | |
98fdbe73 | 6009 | { |
8f23d638 | 6010 | struct hwrm_func_vf_cfg_input req = {0}; |
6fc2ffdf | 6011 | u32 flags; |
98fdbe73 MC |
6012 | int rc; |
6013 | ||
f1ca94de | 6014 | if (!BNXT_NEW_RM(bp)) |
98fdbe73 MC |
6015 | return 0; |
6016 | ||
6fc2ffdf | 6017 | __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 6018 | cp_rings, stats, vnics); |
8f23d638 MC |
6019 | flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | |
6020 | FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | | |
6021 | FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | | |
8f23d638 | 6022 | FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | |
41e8d798 MC |
6023 | FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | |
6024 | FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; | |
6025 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
6026 | flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; | |
8f23d638 MC |
6027 | |
6028 | req.flags = cpu_to_le32(flags); | |
8f23d638 | 6029 | rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
d4f1420d | 6030 | return rc; |
8f23d638 MC |
6031 | } |
6032 | ||
6033 | static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, | |
780baad4 VV |
6034 | int ring_grps, int cp_rings, int stats, |
6035 | int vnics) | |
8f23d638 MC |
6036 | { |
6037 | struct hwrm_func_cfg_input req = {0}; | |
6fc2ffdf | 6038 | u32 flags; |
8f23d638 | 6039 | int rc; |
98fdbe73 | 6040 | |
6fc2ffdf | 6041 | __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, |
780baad4 | 6042 | cp_rings, stats, vnics); |
8f23d638 | 6043 | flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; |
41e8d798 | 6044 | if (BNXT_NEW_RM(bp)) { |
8f23d638 MC |
6045 | flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | |
6046 | FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | | |
8f23d638 MC |
6047 | FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | |
6048 | FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; | |
41e8d798 | 6049 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
0b815023 MC |
6050 | flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | |
6051 | FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; | |
41e8d798 MC |
6052 | else |
6053 | flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; | |
6054 | } | |
6fc2ffdf | 6055 | |
8f23d638 | 6056 | req.flags = cpu_to_le32(flags); |
98fdbe73 | 6057 | rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
d4f1420d | 6058 | return rc; |
98fdbe73 MC |
6059 | } |
6060 | ||
8f23d638 | 6061 | static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, |
780baad4 VV |
6062 | int ring_grps, int cp_rings, int stats, |
6063 | int vnics) | |
8f23d638 MC |
6064 | { |
6065 | if (bp->hwrm_spec_code < 0x10801) | |
6066 | return 0; | |
6067 | ||
6068 | if (BNXT_PF(bp)) | |
6069 | return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, | |
780baad4 VV |
6070 | ring_grps, cp_rings, stats, |
6071 | vnics); | |
8f23d638 MC |
6072 | |
6073 | return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, | |
780baad4 | 6074 | cp_rings, stats, vnics); |
8f23d638 MC |
6075 | } |
6076 | ||
74706afa MC |
6077 | static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) |
6078 | { | |
6079 | struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6080 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6081 | struct hwrm_ring_aggint_qcaps_input req = {0}; | |
6082 | int rc; | |
6083 | ||
6084 | coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; | |
6085 | coal_cap->num_cmpl_dma_aggr_max = 63; | |
6086 | coal_cap->num_cmpl_dma_aggr_during_int_max = 63; | |
6087 | coal_cap->cmpl_aggr_dma_tmr_max = 65535; | |
6088 | coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; | |
6089 | coal_cap->int_lat_tmr_min_max = 65535; | |
6090 | coal_cap->int_lat_tmr_max_max = 65535; | |
6091 | coal_cap->num_cmpl_aggr_int_max = 65535; | |
6092 | coal_cap->timer_units = 80; | |
6093 | ||
6094 | if (bp->hwrm_spec_code < 0x10902) | |
6095 | return; | |
6096 | ||
6097 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); | |
6098 | mutex_lock(&bp->hwrm_cmd_lock); | |
6099 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6100 | if (!rc) { | |
6101 | coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); | |
58590c8d | 6102 | coal_cap->nq_params = le32_to_cpu(resp->nq_params); |
74706afa MC |
6103 | coal_cap->num_cmpl_dma_aggr_max = |
6104 | le16_to_cpu(resp->num_cmpl_dma_aggr_max); | |
6105 | coal_cap->num_cmpl_dma_aggr_during_int_max = | |
6106 | le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); | |
6107 | coal_cap->cmpl_aggr_dma_tmr_max = | |
6108 | le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); | |
6109 | coal_cap->cmpl_aggr_dma_tmr_during_int_max = | |
6110 | le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); | |
6111 | coal_cap->int_lat_tmr_min_max = | |
6112 | le16_to_cpu(resp->int_lat_tmr_min_max); | |
6113 | coal_cap->int_lat_tmr_max_max = | |
6114 | le16_to_cpu(resp->int_lat_tmr_max_max); | |
6115 | coal_cap->num_cmpl_aggr_int_max = | |
6116 | le16_to_cpu(resp->num_cmpl_aggr_int_max); | |
6117 | coal_cap->timer_units = le16_to_cpu(resp->timer_units); | |
6118 | } | |
6119 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6120 | } | |
6121 | ||
6122 | static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) | |
6123 | { | |
6124 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6125 | ||
6126 | return usec * 1000 / coal_cap->timer_units; | |
6127 | } | |
6128 | ||
6129 | static void bnxt_hwrm_set_coal_params(struct bnxt *bp, | |
6130 | struct bnxt_coal *hw_coal, | |
bb053f52 MC |
6131 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) |
6132 | { | |
74706afa MC |
6133 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; |
6134 | u32 cmpl_params = coal_cap->cmpl_params; | |
6135 | u16 val, tmr, max, flags = 0; | |
f8503969 MC |
6136 | |
6137 | max = hw_coal->bufs_per_record * 128; | |
6138 | if (hw_coal->budget) | |
6139 | max = hw_coal->bufs_per_record * hw_coal->budget; | |
74706afa | 6140 | max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); |
f8503969 MC |
6141 | |
6142 | val = clamp_t(u16, hw_coal->coal_bufs, 1, max); | |
6143 | req->num_cmpl_aggr_int = cpu_to_le16(val); | |
b153cbc5 | 6144 | |
74706afa | 6145 | val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); |
f8503969 MC |
6146 | req->num_cmpl_dma_aggr = cpu_to_le16(val); |
6147 | ||
74706afa MC |
6148 | val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, |
6149 | coal_cap->num_cmpl_dma_aggr_during_int_max); | |
f8503969 MC |
6150 | req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); |
6151 | ||
74706afa MC |
6152 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); |
6153 | tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); | |
f8503969 MC |
6154 | req->int_lat_tmr_max = cpu_to_le16(tmr); |
6155 | ||
6156 | /* min timer set to 1/2 of interrupt timer */ | |
74706afa MC |
6157 | if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { |
6158 | val = tmr / 2; | |
6159 | val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); | |
6160 | req->int_lat_tmr_min = cpu_to_le16(val); | |
6161 | req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); | |
6162 | } | |
f8503969 MC |
6163 | |
6164 | /* buf timer set to 1/4 of interrupt timer */ | |
74706afa | 6165 | val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); |
f8503969 MC |
6166 | req->cmpl_aggr_dma_tmr = cpu_to_le16(val); |
6167 | ||
74706afa MC |
6168 | if (cmpl_params & |
6169 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { | |
6170 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); | |
6171 | val = clamp_t(u16, tmr, 1, | |
6172 | coal_cap->cmpl_aggr_dma_tmr_during_int_max); | |
6173 | req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr); | |
6174 | req->enables |= | |
6175 | cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); | |
6176 | } | |
f8503969 | 6177 | |
74706afa MC |
6178 | if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) |
6179 | flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; | |
6180 | if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && | |
6181 | hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) | |
f8503969 | 6182 | flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; |
bb053f52 | 6183 | req->flags = cpu_to_le16(flags); |
74706afa | 6184 | req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); |
bb053f52 MC |
6185 | } |
6186 | ||
58590c8d MC |
6187 | /* Caller holds bp->hwrm_cmd_lock */ |
6188 | static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, | |
6189 | struct bnxt_coal *hw_coal) | |
6190 | { | |
6191 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; | |
6192 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6193 | struct bnxt_coal_cap *coal_cap = &bp->coal_cap; | |
6194 | u32 nq_params = coal_cap->nq_params; | |
6195 | u16 tmr; | |
6196 | ||
6197 | if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) | |
6198 | return 0; | |
6199 | ||
6200 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, | |
6201 | -1, -1); | |
6202 | req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); | |
6203 | req.flags = | |
6204 | cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); | |
6205 | ||
6206 | tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; | |
6207 | tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); | |
6208 | req.int_lat_tmr_min = cpu_to_le16(tmr); | |
6209 | req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); | |
6210 | return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6211 | } | |
6212 | ||
6a8788f2 AG |
6213 | int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) |
6214 | { | |
6215 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; | |
6216 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6217 | struct bnxt_coal coal; | |
6a8788f2 AG |
6218 | |
6219 | /* Tick values in micro seconds. | |
6220 | * 1 coal_buf x bufs_per_record = 1 completion record. | |
6221 | */ | |
6222 | memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); | |
6223 | ||
6224 | coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; | |
6225 | coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; | |
6226 | ||
6227 | if (!bnapi->rx_ring) | |
6228 | return -ENODEV; | |
6229 | ||
6230 | bnxt_hwrm_cmd_hdr_init(bp, &req_rx, | |
6231 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
6232 | ||
74706afa | 6233 | bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); |
6a8788f2 | 6234 | |
2c61d211 | 6235 | req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); |
6a8788f2 AG |
6236 | |
6237 | return hwrm_send_message(bp, &req_rx, sizeof(req_rx), | |
6238 | HWRM_CMD_TIMEOUT); | |
6239 | } | |
6240 | ||
c0c050c5 MC |
6241 | int bnxt_hwrm_set_coal(struct bnxt *bp) |
6242 | { | |
6243 | int i, rc = 0; | |
dfc9c94a MC |
6244 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, |
6245 | req_tx = {0}, *req; | |
c0c050c5 | 6246 | |
dfc9c94a MC |
6247 | bnxt_hwrm_cmd_hdr_init(bp, &req_rx, |
6248 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
6249 | bnxt_hwrm_cmd_hdr_init(bp, &req_tx, | |
6250 | HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); | |
c0c050c5 | 6251 | |
74706afa MC |
6252 | bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); |
6253 | bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); | |
c0c050c5 MC |
6254 | |
6255 | mutex_lock(&bp->hwrm_cmd_lock); | |
6256 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
dfc9c94a | 6257 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
58590c8d | 6258 | struct bnxt_coal *hw_coal; |
2c61d211 | 6259 | u16 ring_id; |
c0c050c5 | 6260 | |
dfc9c94a | 6261 | req = &req_rx; |
2c61d211 MC |
6262 | if (!bnapi->rx_ring) { |
6263 | ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); | |
dfc9c94a | 6264 | req = &req_tx; |
2c61d211 MC |
6265 | } else { |
6266 | ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); | |
6267 | } | |
6268 | req->ring_id = cpu_to_le16(ring_id); | |
dfc9c94a MC |
6269 | |
6270 | rc = _hwrm_send_message(bp, req, sizeof(*req), | |
c0c050c5 MC |
6271 | HWRM_CMD_TIMEOUT); |
6272 | if (rc) | |
6273 | break; | |
58590c8d MC |
6274 | |
6275 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
6276 | continue; | |
6277 | ||
6278 | if (bnapi->rx_ring && bnapi->tx_ring) { | |
6279 | req = &req_tx; | |
6280 | ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); | |
6281 | req->ring_id = cpu_to_le16(ring_id); | |
6282 | rc = _hwrm_send_message(bp, req, sizeof(*req), | |
6283 | HWRM_CMD_TIMEOUT); | |
6284 | if (rc) | |
6285 | break; | |
6286 | } | |
6287 | if (bnapi->rx_ring) | |
6288 | hw_coal = &bp->rx_coal; | |
6289 | else | |
6290 | hw_coal = &bp->tx_coal; | |
6291 | __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); | |
c0c050c5 MC |
6292 | } |
6293 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6294 | return rc; | |
6295 | } | |
6296 | ||
6297 | static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) | |
6298 | { | |
6299 | int rc = 0, i; | |
6300 | struct hwrm_stat_ctx_free_input req = {0}; | |
6301 | ||
6302 | if (!bp->bnapi) | |
6303 | return 0; | |
6304 | ||
3e8060fa PS |
6305 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
6306 | return 0; | |
6307 | ||
c0c050c5 MC |
6308 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); |
6309 | ||
6310 | mutex_lock(&bp->hwrm_cmd_lock); | |
6311 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6312 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6313 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6314 | ||
6315 | if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { | |
6316 | req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); | |
6317 | ||
6318 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
6319 | HWRM_CMD_TIMEOUT); | |
c0c050c5 MC |
6320 | |
6321 | cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; | |
6322 | } | |
6323 | } | |
6324 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6325 | return rc; | |
6326 | } | |
6327 | ||
6328 | static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) | |
6329 | { | |
6330 | int rc = 0, i; | |
6331 | struct hwrm_stat_ctx_alloc_input req = {0}; | |
6332 | struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
6333 | ||
3e8060fa PS |
6334 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
6335 | return 0; | |
6336 | ||
c0c050c5 MC |
6337 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); |
6338 | ||
4e748506 | 6339 | req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); |
51f30785 | 6340 | req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); |
c0c050c5 MC |
6341 | |
6342 | mutex_lock(&bp->hwrm_cmd_lock); | |
6343 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6344 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
6345 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
6346 | ||
6347 | req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); | |
6348 | ||
6349 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
6350 | HWRM_CMD_TIMEOUT); | |
6351 | if (rc) | |
6352 | break; | |
6353 | ||
6354 | cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); | |
6355 | ||
6356 | bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; | |
6357 | } | |
6358 | mutex_unlock(&bp->hwrm_cmd_lock); | |
89aa8445 | 6359 | return rc; |
c0c050c5 MC |
6360 | } |
6361 | ||
cf6645f8 MC |
6362 | static int bnxt_hwrm_func_qcfg(struct bnxt *bp) |
6363 | { | |
6364 | struct hwrm_func_qcfg_input req = {0}; | |
567b2abe | 6365 | struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; |
9315edca | 6366 | u16 flags; |
cf6645f8 MC |
6367 | int rc; |
6368 | ||
6369 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); | |
6370 | req.fid = cpu_to_le16(0xffff); | |
6371 | mutex_lock(&bp->hwrm_cmd_lock); | |
6372 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6373 | if (rc) | |
6374 | goto func_qcfg_exit; | |
6375 | ||
6376 | #ifdef CONFIG_BNXT_SRIOV | |
6377 | if (BNXT_VF(bp)) { | |
cf6645f8 MC |
6378 | struct bnxt_vf_info *vf = &bp->vf; |
6379 | ||
6380 | vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; | |
230d1f0d MC |
6381 | } else { |
6382 | bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); | |
cf6645f8 MC |
6383 | } |
6384 | #endif | |
9315edca MC |
6385 | flags = le16_to_cpu(resp->flags); |
6386 | if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | | |
6387 | FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { | |
97381a18 | 6388 | bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; |
9315edca | 6389 | if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) |
97381a18 | 6390 | bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; |
9315edca MC |
6391 | } |
6392 | if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) | |
6393 | bp->flags |= BNXT_FLAG_MULTI_HOST; | |
bc39f885 | 6394 | |
567b2abe SB |
6395 | switch (resp->port_partition_type) { |
6396 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: | |
6397 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: | |
6398 | case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: | |
6399 | bp->port_partition_type = resp->port_partition_type; | |
6400 | break; | |
6401 | } | |
32e8239c MC |
6402 | if (bp->hwrm_spec_code < 0x10707 || |
6403 | resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) | |
6404 | bp->br_mode = BRIDGE_MODE_VEB; | |
6405 | else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) | |
6406 | bp->br_mode = BRIDGE_MODE_VEPA; | |
6407 | else | |
6408 | bp->br_mode = BRIDGE_MODE_UNDEF; | |
cf6645f8 | 6409 | |
7eb9bb3a MC |
6410 | bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); |
6411 | if (!bp->max_mtu) | |
6412 | bp->max_mtu = BNXT_MAX_MTU; | |
6413 | ||
cf6645f8 MC |
6414 | func_qcfg_exit: |
6415 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6416 | return rc; | |
6417 | } | |
6418 | ||
98f04cf0 MC |
6419 | static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) |
6420 | { | |
6421 | struct hwrm_func_backing_store_qcaps_input req = {0}; | |
6422 | struct hwrm_func_backing_store_qcaps_output *resp = | |
6423 | bp->hwrm_cmd_resp_addr; | |
6424 | int rc; | |
6425 | ||
6426 | if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) | |
6427 | return 0; | |
6428 | ||
6429 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); | |
6430 | mutex_lock(&bp->hwrm_cmd_lock); | |
6431 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6432 | if (!rc) { | |
6433 | struct bnxt_ctx_pg_info *ctx_pg; | |
6434 | struct bnxt_ctx_mem_info *ctx; | |
6435 | int i; | |
6436 | ||
6437 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
6438 | if (!ctx) { | |
6439 | rc = -ENOMEM; | |
6440 | goto ctx_err; | |
6441 | } | |
6442 | ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL); | |
6443 | if (!ctx_pg) { | |
6444 | kfree(ctx); | |
6445 | rc = -ENOMEM; | |
6446 | goto ctx_err; | |
6447 | } | |
6448 | for (i = 0; i < bp->max_q + 1; i++, ctx_pg++) | |
6449 | ctx->tqm_mem[i] = ctx_pg; | |
6450 | ||
6451 | bp->ctx = ctx; | |
6452 | ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); | |
6453 | ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); | |
6454 | ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); | |
6455 | ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); | |
6456 | ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); | |
6457 | ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); | |
6458 | ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); | |
6459 | ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); | |
6460 | ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); | |
6461 | ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); | |
6462 | ctx->vnic_max_vnic_entries = | |
6463 | le16_to_cpu(resp->vnic_max_vnic_entries); | |
6464 | ctx->vnic_max_ring_table_entries = | |
6465 | le16_to_cpu(resp->vnic_max_ring_table_entries); | |
6466 | ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); | |
6467 | ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); | |
6468 | ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); | |
6469 | ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); | |
6470 | ctx->tqm_min_entries_per_ring = | |
6471 | le32_to_cpu(resp->tqm_min_entries_per_ring); | |
6472 | ctx->tqm_max_entries_per_ring = | |
6473 | le32_to_cpu(resp->tqm_max_entries_per_ring); | |
6474 | ctx->tqm_entries_multiple = resp->tqm_entries_multiple; | |
6475 | if (!ctx->tqm_entries_multiple) | |
6476 | ctx->tqm_entries_multiple = 1; | |
6477 | ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); | |
6478 | ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); | |
53579e37 DS |
6479 | ctx->mrav_num_entries_units = |
6480 | le16_to_cpu(resp->mrav_num_entries_units); | |
98f04cf0 MC |
6481 | ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); |
6482 | ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); | |
6483 | } else { | |
6484 | rc = 0; | |
6485 | } | |
6486 | ctx_err: | |
6487 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6488 | return rc; | |
6489 | } | |
6490 | ||
1b9394e5 MC |
6491 | static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, |
6492 | __le64 *pg_dir) | |
6493 | { | |
6494 | u8 pg_size = 0; | |
6495 | ||
6496 | if (BNXT_PAGE_SHIFT == 13) | |
6497 | pg_size = 1 << 4; | |
6498 | else if (BNXT_PAGE_SIZE == 16) | |
6499 | pg_size = 2 << 4; | |
6500 | ||
6501 | *pg_attr = pg_size; | |
08fe9d18 MC |
6502 | if (rmem->depth >= 1) { |
6503 | if (rmem->depth == 2) | |
6504 | *pg_attr |= 2; | |
6505 | else | |
6506 | *pg_attr |= 1; | |
1b9394e5 MC |
6507 | *pg_dir = cpu_to_le64(rmem->pg_tbl_map); |
6508 | } else { | |
6509 | *pg_dir = cpu_to_le64(rmem->dma_arr[0]); | |
6510 | } | |
6511 | } | |
6512 | ||
6513 | #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ | |
6514 | (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ | |
6515 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ | |
6516 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ | |
6517 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ | |
6518 | FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) | |
6519 | ||
6520 | static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) | |
6521 | { | |
6522 | struct hwrm_func_backing_store_cfg_input req = {0}; | |
6523 | struct bnxt_ctx_mem_info *ctx = bp->ctx; | |
6524 | struct bnxt_ctx_pg_info *ctx_pg; | |
6525 | __le32 *num_entries; | |
6526 | __le64 *pg_dir; | |
53579e37 | 6527 | u32 flags = 0; |
1b9394e5 MC |
6528 | u8 *pg_attr; |
6529 | int i, rc; | |
6530 | u32 ena; | |
6531 | ||
6532 | if (!ctx) | |
6533 | return 0; | |
6534 | ||
6535 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); | |
6536 | req.enables = cpu_to_le32(enables); | |
6537 | ||
6538 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { | |
6539 | ctx_pg = &ctx->qp_mem; | |
6540 | req.qp_num_entries = cpu_to_le32(ctx_pg->entries); | |
6541 | req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); | |
6542 | req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); | |
6543 | req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); | |
6544 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6545 | &req.qpc_pg_size_qpc_lvl, | |
6546 | &req.qpc_page_dir); | |
6547 | } | |
6548 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { | |
6549 | ctx_pg = &ctx->srq_mem; | |
6550 | req.srq_num_entries = cpu_to_le32(ctx_pg->entries); | |
6551 | req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); | |
6552 | req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); | |
6553 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6554 | &req.srq_pg_size_srq_lvl, | |
6555 | &req.srq_page_dir); | |
6556 | } | |
6557 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { | |
6558 | ctx_pg = &ctx->cq_mem; | |
6559 | req.cq_num_entries = cpu_to_le32(ctx_pg->entries); | |
6560 | req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); | |
6561 | req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); | |
6562 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, | |
6563 | &req.cq_page_dir); | |
6564 | } | |
6565 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { | |
6566 | ctx_pg = &ctx->vnic_mem; | |
6567 | req.vnic_num_vnic_entries = | |
6568 | cpu_to_le16(ctx->vnic_max_vnic_entries); | |
6569 | req.vnic_num_ring_table_entries = | |
6570 | cpu_to_le16(ctx->vnic_max_ring_table_entries); | |
6571 | req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); | |
6572 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6573 | &req.vnic_pg_size_vnic_lvl, | |
6574 | &req.vnic_page_dir); | |
6575 | } | |
6576 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { | |
6577 | ctx_pg = &ctx->stat_mem; | |
6578 | req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); | |
6579 | req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); | |
6580 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6581 | &req.stat_pg_size_stat_lvl, | |
6582 | &req.stat_page_dir); | |
6583 | } | |
cf6daed0 MC |
6584 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { |
6585 | ctx_pg = &ctx->mrav_mem; | |
6586 | req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); | |
53579e37 DS |
6587 | if (ctx->mrav_num_entries_units) |
6588 | flags |= | |
6589 | FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; | |
cf6daed0 MC |
6590 | req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); |
6591 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6592 | &req.mrav_pg_size_mrav_lvl, | |
6593 | &req.mrav_page_dir); | |
6594 | } | |
6595 | if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { | |
6596 | ctx_pg = &ctx->tim_mem; | |
6597 | req.tim_num_entries = cpu_to_le32(ctx_pg->entries); | |
6598 | req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); | |
6599 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, | |
6600 | &req.tim_pg_size_tim_lvl, | |
6601 | &req.tim_page_dir); | |
6602 | } | |
1b9394e5 MC |
6603 | for (i = 0, num_entries = &req.tqm_sp_num_entries, |
6604 | pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, | |
6605 | pg_dir = &req.tqm_sp_page_dir, | |
6606 | ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; | |
6607 | i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { | |
6608 | if (!(enables & ena)) | |
6609 | continue; | |
6610 | ||
6611 | req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); | |
6612 | ctx_pg = ctx->tqm_mem[i]; | |
6613 | *num_entries = cpu_to_le32(ctx_pg->entries); | |
6614 | bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); | |
6615 | } | |
53579e37 | 6616 | req.flags = cpu_to_le32(flags); |
1b9394e5 | 6617 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
1b9394e5 MC |
6618 | return rc; |
6619 | } | |
6620 | ||
98f04cf0 | 6621 | static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, |
08fe9d18 | 6622 | struct bnxt_ctx_pg_info *ctx_pg) |
98f04cf0 MC |
6623 | { |
6624 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6625 | ||
98f04cf0 MC |
6626 | rmem->page_size = BNXT_PAGE_SIZE; |
6627 | rmem->pg_arr = ctx_pg->ctx_pg_arr; | |
6628 | rmem->dma_arr = ctx_pg->ctx_dma_arr; | |
1b9394e5 | 6629 | rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; |
08fe9d18 MC |
6630 | if (rmem->depth >= 1) |
6631 | rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; | |
98f04cf0 MC |
6632 | return bnxt_alloc_ring(bp, rmem); |
6633 | } | |
6634 | ||
08fe9d18 MC |
6635 | static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, |
6636 | struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, | |
6637 | u8 depth) | |
6638 | { | |
6639 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6640 | int rc; | |
6641 | ||
6642 | if (!mem_size) | |
6643 | return 0; | |
6644 | ||
6645 | ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); | |
6646 | if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { | |
6647 | ctx_pg->nr_pages = 0; | |
6648 | return -EINVAL; | |
6649 | } | |
6650 | if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { | |
6651 | int nr_tbls, i; | |
6652 | ||
6653 | rmem->depth = 2; | |
6654 | ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), | |
6655 | GFP_KERNEL); | |
6656 | if (!ctx_pg->ctx_pg_tbl) | |
6657 | return -ENOMEM; | |
6658 | nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); | |
6659 | rmem->nr_pages = nr_tbls; | |
6660 | rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); | |
6661 | if (rc) | |
6662 | return rc; | |
6663 | for (i = 0; i < nr_tbls; i++) { | |
6664 | struct bnxt_ctx_pg_info *pg_tbl; | |
6665 | ||
6666 | pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); | |
6667 | if (!pg_tbl) | |
6668 | return -ENOMEM; | |
6669 | ctx_pg->ctx_pg_tbl[i] = pg_tbl; | |
6670 | rmem = &pg_tbl->ring_mem; | |
6671 | rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; | |
6672 | rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; | |
6673 | rmem->depth = 1; | |
6674 | rmem->nr_pages = MAX_CTX_PAGES; | |
6ef982de MC |
6675 | if (i == (nr_tbls - 1)) { |
6676 | int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; | |
6677 | ||
6678 | if (rem) | |
6679 | rmem->nr_pages = rem; | |
6680 | } | |
08fe9d18 MC |
6681 | rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); |
6682 | if (rc) | |
6683 | break; | |
6684 | } | |
6685 | } else { | |
6686 | rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); | |
6687 | if (rmem->nr_pages > 1 || depth) | |
6688 | rmem->depth = 1; | |
6689 | rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); | |
6690 | } | |
6691 | return rc; | |
6692 | } | |
6693 | ||
6694 | static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, | |
6695 | struct bnxt_ctx_pg_info *ctx_pg) | |
6696 | { | |
6697 | struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; | |
6698 | ||
6699 | if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || | |
6700 | ctx_pg->ctx_pg_tbl) { | |
6701 | int i, nr_tbls = rmem->nr_pages; | |
6702 | ||
6703 | for (i = 0; i < nr_tbls; i++) { | |
6704 | struct bnxt_ctx_pg_info *pg_tbl; | |
6705 | struct bnxt_ring_mem_info *rmem2; | |
6706 | ||
6707 | pg_tbl = ctx_pg->ctx_pg_tbl[i]; | |
6708 | if (!pg_tbl) | |
6709 | continue; | |
6710 | rmem2 = &pg_tbl->ring_mem; | |
6711 | bnxt_free_ring(bp, rmem2); | |
6712 | ctx_pg->ctx_pg_arr[i] = NULL; | |
6713 | kfree(pg_tbl); | |
6714 | ctx_pg->ctx_pg_tbl[i] = NULL; | |
6715 | } | |
6716 | kfree(ctx_pg->ctx_pg_tbl); | |
6717 | ctx_pg->ctx_pg_tbl = NULL; | |
6718 | } | |
6719 | bnxt_free_ring(bp, rmem); | |
6720 | ctx_pg->nr_pages = 0; | |
6721 | } | |
6722 | ||
98f04cf0 MC |
6723 | static void bnxt_free_ctx_mem(struct bnxt *bp) |
6724 | { | |
6725 | struct bnxt_ctx_mem_info *ctx = bp->ctx; | |
6726 | int i; | |
6727 | ||
6728 | if (!ctx) | |
6729 | return; | |
6730 | ||
6731 | if (ctx->tqm_mem[0]) { | |
6732 | for (i = 0; i < bp->max_q + 1; i++) | |
08fe9d18 | 6733 | bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); |
98f04cf0 MC |
6734 | kfree(ctx->tqm_mem[0]); |
6735 | ctx->tqm_mem[0] = NULL; | |
6736 | } | |
6737 | ||
cf6daed0 MC |
6738 | bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); |
6739 | bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); | |
08fe9d18 MC |
6740 | bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); |
6741 | bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); | |
6742 | bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); | |
6743 | bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); | |
6744 | bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); | |
98f04cf0 MC |
6745 | ctx->flags &= ~BNXT_CTX_FLAG_INITED; |
6746 | } | |
6747 | ||
6748 | static int bnxt_alloc_ctx_mem(struct bnxt *bp) | |
6749 | { | |
6750 | struct bnxt_ctx_pg_info *ctx_pg; | |
6751 | struct bnxt_ctx_mem_info *ctx; | |
1b9394e5 | 6752 | u32 mem_size, ena, entries; |
53579e37 | 6753 | u32 num_mr, num_ah; |
cf6daed0 MC |
6754 | u32 extra_srqs = 0; |
6755 | u32 extra_qps = 0; | |
6756 | u8 pg_lvl = 1; | |
98f04cf0 MC |
6757 | int i, rc; |
6758 | ||
6759 | rc = bnxt_hwrm_func_backing_store_qcaps(bp); | |
6760 | if (rc) { | |
6761 | netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", | |
6762 | rc); | |
6763 | return rc; | |
6764 | } | |
6765 | ctx = bp->ctx; | |
6766 | if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) | |
6767 | return 0; | |
6768 | ||
d629522e | 6769 | if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { |
cf6daed0 MC |
6770 | pg_lvl = 2; |
6771 | extra_qps = 65536; | |
6772 | extra_srqs = 8192; | |
6773 | } | |
6774 | ||
98f04cf0 | 6775 | ctx_pg = &ctx->qp_mem; |
cf6daed0 MC |
6776 | ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + |
6777 | extra_qps; | |
98f04cf0 | 6778 | mem_size = ctx->qp_entry_size * ctx_pg->entries; |
cf6daed0 | 6779 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl); |
98f04cf0 MC |
6780 | if (rc) |
6781 | return rc; | |
6782 | ||
6783 | ctx_pg = &ctx->srq_mem; | |
cf6daed0 | 6784 | ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; |
98f04cf0 | 6785 | mem_size = ctx->srq_entry_size * ctx_pg->entries; |
cf6daed0 | 6786 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl); |
98f04cf0 MC |
6787 | if (rc) |
6788 | return rc; | |
6789 | ||
6790 | ctx_pg = &ctx->cq_mem; | |
cf6daed0 | 6791 | ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; |
98f04cf0 | 6792 | mem_size = ctx->cq_entry_size * ctx_pg->entries; |
cf6daed0 | 6793 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl); |
98f04cf0 MC |
6794 | if (rc) |
6795 | return rc; | |
6796 | ||
6797 | ctx_pg = &ctx->vnic_mem; | |
6798 | ctx_pg->entries = ctx->vnic_max_vnic_entries + | |
6799 | ctx->vnic_max_ring_table_entries; | |
6800 | mem_size = ctx->vnic_entry_size * ctx_pg->entries; | |
08fe9d18 | 6801 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); |
98f04cf0 MC |
6802 | if (rc) |
6803 | return rc; | |
6804 | ||
6805 | ctx_pg = &ctx->stat_mem; | |
6806 | ctx_pg->entries = ctx->stat_max_entries; | |
6807 | mem_size = ctx->stat_entry_size * ctx_pg->entries; | |
08fe9d18 | 6808 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); |
98f04cf0 MC |
6809 | if (rc) |
6810 | return rc; | |
6811 | ||
cf6daed0 MC |
6812 | ena = 0; |
6813 | if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) | |
6814 | goto skip_rdma; | |
6815 | ||
6816 | ctx_pg = &ctx->mrav_mem; | |
53579e37 DS |
6817 | /* 128K extra is needed to accommodate static AH context |
6818 | * allocation by f/w. | |
6819 | */ | |
6820 | num_mr = 1024 * 256; | |
6821 | num_ah = 1024 * 128; | |
6822 | ctx_pg->entries = num_mr + num_ah; | |
cf6daed0 MC |
6823 | mem_size = ctx->mrav_entry_size * ctx_pg->entries; |
6824 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2); | |
6825 | if (rc) | |
6826 | return rc; | |
6827 | ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; | |
53579e37 DS |
6828 | if (ctx->mrav_num_entries_units) |
6829 | ctx_pg->entries = | |
6830 | ((num_mr / ctx->mrav_num_entries_units) << 16) | | |
6831 | (num_ah / ctx->mrav_num_entries_units); | |
cf6daed0 MC |
6832 | |
6833 | ctx_pg = &ctx->tim_mem; | |
6834 | ctx_pg->entries = ctx->qp_mem.entries; | |
6835 | mem_size = ctx->tim_entry_size * ctx_pg->entries; | |
6836 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); | |
6837 | if (rc) | |
6838 | return rc; | |
6839 | ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; | |
6840 | ||
6841 | skip_rdma: | |
6842 | entries = ctx->qp_max_l2_entries + extra_qps; | |
98f04cf0 MC |
6843 | entries = roundup(entries, ctx->tqm_entries_multiple); |
6844 | entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring, | |
6845 | ctx->tqm_max_entries_per_ring); | |
cf6daed0 | 6846 | for (i = 0; i < bp->max_q + 1; i++) { |
98f04cf0 MC |
6847 | ctx_pg = ctx->tqm_mem[i]; |
6848 | ctx_pg->entries = entries; | |
6849 | mem_size = ctx->tqm_entry_size * entries; | |
08fe9d18 | 6850 | rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); |
98f04cf0 MC |
6851 | if (rc) |
6852 | return rc; | |
1b9394e5 | 6853 | ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; |
98f04cf0 | 6854 | } |
1b9394e5 MC |
6855 | ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; |
6856 | rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); | |
6857 | if (rc) | |
6858 | netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", | |
6859 | rc); | |
6860 | else | |
6861 | ctx->flags |= BNXT_CTX_FLAG_INITED; | |
6862 | ||
98f04cf0 MC |
6863 | return 0; |
6864 | } | |
6865 | ||
db4723b3 | 6866 | int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) |
be0dd9c4 MC |
6867 | { |
6868 | struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6869 | struct hwrm_func_resource_qcaps_input req = {0}; | |
6870 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
6871 | int rc; | |
6872 | ||
6873 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); | |
6874 | req.fid = cpu_to_le16(0xffff); | |
6875 | ||
6876 | mutex_lock(&bp->hwrm_cmd_lock); | |
351cbde9 JT |
6877 | rc = _hwrm_send_message_silent(bp, &req, sizeof(req), |
6878 | HWRM_CMD_TIMEOUT); | |
d4f1420d | 6879 | if (rc) |
be0dd9c4 | 6880 | goto hwrm_func_resc_qcaps_exit; |
be0dd9c4 | 6881 | |
db4723b3 MC |
6882 | hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); |
6883 | if (!all) | |
6884 | goto hwrm_func_resc_qcaps_exit; | |
6885 | ||
be0dd9c4 MC |
6886 | hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); |
6887 | hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); | |
6888 | hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); | |
6889 | hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); | |
6890 | hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); | |
6891 | hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); | |
6892 | hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); | |
6893 | hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); | |
6894 | hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); | |
6895 | hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); | |
6896 | hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); | |
6897 | hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); | |
6898 | hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); | |
6899 | hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); | |
6900 | hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); | |
6901 | hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); | |
6902 | ||
9c1fabdf MC |
6903 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
6904 | u16 max_msix = le16_to_cpu(resp->max_msix); | |
6905 | ||
f7588cd8 | 6906 | hw_resc->max_nqs = max_msix; |
9c1fabdf MC |
6907 | hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; |
6908 | } | |
6909 | ||
4673d664 MC |
6910 | if (BNXT_PF(bp)) { |
6911 | struct bnxt_pf_info *pf = &bp->pf; | |
6912 | ||
6913 | pf->vf_resv_strategy = | |
6914 | le16_to_cpu(resp->vf_reservation_strategy); | |
bf82736d | 6915 | if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) |
4673d664 MC |
6916 | pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; |
6917 | } | |
be0dd9c4 MC |
6918 | hwrm_func_resc_qcaps_exit: |
6919 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6920 | return rc; | |
6921 | } | |
6922 | ||
6923 | static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) | |
c0c050c5 MC |
6924 | { |
6925 | int rc = 0; | |
6926 | struct hwrm_func_qcaps_input req = {0}; | |
6927 | struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
6a4f2947 MC |
6928 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
6929 | u32 flags; | |
c0c050c5 MC |
6930 | |
6931 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); | |
6932 | req.fid = cpu_to_le16(0xffff); | |
6933 | ||
6934 | mutex_lock(&bp->hwrm_cmd_lock); | |
6935 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
6936 | if (rc) | |
6937 | goto hwrm_func_qcaps_exit; | |
6938 | ||
6a4f2947 MC |
6939 | flags = le32_to_cpu(resp->flags); |
6940 | if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) | |
e4060d30 | 6941 | bp->flags |= BNXT_FLAG_ROCEV1_CAP; |
6a4f2947 | 6942 | if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) |
e4060d30 | 6943 | bp->flags |= BNXT_FLAG_ROCEV2_CAP; |
55e4398d VV |
6944 | if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) |
6945 | bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; | |
6154532f VV |
6946 | if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) |
6947 | bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; | |
07f83d72 MC |
6948 | if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) |
6949 | bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; | |
4037eb71 VV |
6950 | if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) |
6951 | bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; | |
e4060d30 | 6952 | |
7cc5a20e | 6953 | bp->tx_push_thresh = 0; |
6a4f2947 | 6954 | if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) |
7cc5a20e MC |
6955 | bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; |
6956 | ||
6a4f2947 MC |
6957 | hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); |
6958 | hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); | |
6959 | hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); | |
6960 | hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); | |
6961 | hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); | |
6962 | if (!hw_resc->max_hw_ring_grps) | |
6963 | hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; | |
6964 | hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); | |
6965 | hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); | |
6966 | hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); | |
6967 | ||
c0c050c5 MC |
6968 | if (BNXT_PF(bp)) { |
6969 | struct bnxt_pf_info *pf = &bp->pf; | |
6970 | ||
6971 | pf->fw_fid = le16_to_cpu(resp->fid); | |
6972 | pf->port_id = le16_to_cpu(resp->port_id); | |
87027db1 | 6973 | bp->dev->dev_port = pf->port_id; |
11f15ed3 | 6974 | memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); |
c0c050c5 MC |
6975 | pf->first_vf_id = le16_to_cpu(resp->first_vf_id); |
6976 | pf->max_vfs = le16_to_cpu(resp->max_vfs); | |
6977 | pf->max_encap_records = le32_to_cpu(resp->max_encap_records); | |
6978 | pf->max_decap_records = le32_to_cpu(resp->max_decap_records); | |
6979 | pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); | |
6980 | pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); | |
6981 | pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); | |
6982 | pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); | |
ba642ab7 | 6983 | bp->flags &= ~BNXT_FLAG_WOL_CAP; |
6a4f2947 | 6984 | if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) |
c1ef146a | 6985 | bp->flags |= BNXT_FLAG_WOL_CAP; |
c0c050c5 | 6986 | } else { |
379a80a1 | 6987 | #ifdef CONFIG_BNXT_SRIOV |
c0c050c5 MC |
6988 | struct bnxt_vf_info *vf = &bp->vf; |
6989 | ||
6990 | vf->fw_fid = le16_to_cpu(resp->fid); | |
7cc5a20e | 6991 | memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); |
379a80a1 | 6992 | #endif |
c0c050c5 MC |
6993 | } |
6994 | ||
c0c050c5 MC |
6995 | hwrm_func_qcaps_exit: |
6996 | mutex_unlock(&bp->hwrm_cmd_lock); | |
6997 | return rc; | |
6998 | } | |
6999 | ||
804fba4e MC |
7000 | static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); |
7001 | ||
be0dd9c4 MC |
7002 | static int bnxt_hwrm_func_qcaps(struct bnxt *bp) |
7003 | { | |
7004 | int rc; | |
7005 | ||
7006 | rc = __bnxt_hwrm_func_qcaps(bp); | |
7007 | if (rc) | |
7008 | return rc; | |
804fba4e MC |
7009 | rc = bnxt_hwrm_queue_qportcfg(bp); |
7010 | if (rc) { | |
7011 | netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); | |
7012 | return rc; | |
7013 | } | |
be0dd9c4 | 7014 | if (bp->hwrm_spec_code >= 0x10803) { |
98f04cf0 MC |
7015 | rc = bnxt_alloc_ctx_mem(bp); |
7016 | if (rc) | |
7017 | return rc; | |
db4723b3 | 7018 | rc = bnxt_hwrm_func_resc_qcaps(bp, true); |
be0dd9c4 | 7019 | if (!rc) |
97381a18 | 7020 | bp->fw_cap |= BNXT_FW_CAP_NEW_RM; |
be0dd9c4 MC |
7021 | } |
7022 | return 0; | |
7023 | } | |
7024 | ||
e969ae5b MC |
7025 | static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) |
7026 | { | |
7027 | struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; | |
7028 | struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; | |
7029 | int rc = 0; | |
7030 | u32 flags; | |
7031 | ||
7032 | if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) | |
7033 | return 0; | |
7034 | ||
7035 | resp = bp->hwrm_cmd_resp_addr; | |
7036 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); | |
7037 | ||
7038 | mutex_lock(&bp->hwrm_cmd_lock); | |
7039 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7040 | if (rc) | |
7041 | goto hwrm_cfa_adv_qcaps_exit; | |
7042 | ||
7043 | flags = le32_to_cpu(resp->flags); | |
7044 | if (flags & | |
7045 | CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED) | |
7046 | bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX; | |
7047 | ||
7048 | hwrm_cfa_adv_qcaps_exit: | |
7049 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7050 | return rc; | |
7051 | } | |
7052 | ||
9ffbd677 MC |
7053 | static int bnxt_map_fw_health_regs(struct bnxt *bp) |
7054 | { | |
7055 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
7056 | u32 reg_base = 0xffffffff; | |
7057 | int i; | |
7058 | ||
7059 | /* Only pre-map the monitoring GRC registers using window 3 */ | |
7060 | for (i = 0; i < 4; i++) { | |
7061 | u32 reg = fw_health->regs[i]; | |
7062 | ||
7063 | if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) | |
7064 | continue; | |
7065 | if (reg_base == 0xffffffff) | |
7066 | reg_base = reg & BNXT_GRC_BASE_MASK; | |
7067 | if ((reg & BNXT_GRC_BASE_MASK) != reg_base) | |
7068 | return -ERANGE; | |
7069 | fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_BASE + | |
7070 | (reg & BNXT_GRC_OFFSET_MASK); | |
7071 | } | |
7072 | if (reg_base == 0xffffffff) | |
7073 | return 0; | |
7074 | ||
7075 | writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + | |
7076 | BNXT_FW_HEALTH_WIN_MAP_OFF); | |
7077 | return 0; | |
7078 | } | |
7079 | ||
07f83d72 MC |
7080 | static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) |
7081 | { | |
7082 | struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
7083 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
7084 | struct hwrm_error_recovery_qcfg_input req = {0}; | |
7085 | int rc, i; | |
7086 | ||
7087 | if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) | |
7088 | return 0; | |
7089 | ||
7090 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1); | |
7091 | mutex_lock(&bp->hwrm_cmd_lock); | |
7092 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7093 | if (rc) | |
7094 | goto err_recovery_out; | |
7095 | if (!fw_health) { | |
7096 | fw_health = kzalloc(sizeof(*fw_health), GFP_KERNEL); | |
7097 | bp->fw_health = fw_health; | |
7098 | if (!fw_health) { | |
7099 | rc = -ENOMEM; | |
7100 | goto err_recovery_out; | |
7101 | } | |
7102 | } | |
7103 | fw_health->flags = le32_to_cpu(resp->flags); | |
7104 | if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && | |
7105 | !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { | |
7106 | rc = -EINVAL; | |
7107 | goto err_recovery_out; | |
7108 | } | |
7109 | fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); | |
7110 | fw_health->master_func_wait_dsecs = | |
7111 | le32_to_cpu(resp->master_func_wait_period); | |
7112 | fw_health->normal_func_wait_dsecs = | |
7113 | le32_to_cpu(resp->normal_func_wait_period); | |
7114 | fw_health->post_reset_wait_dsecs = | |
7115 | le32_to_cpu(resp->master_func_wait_period_after_reset); | |
7116 | fw_health->post_reset_max_wait_dsecs = | |
7117 | le32_to_cpu(resp->max_bailout_time_after_reset); | |
7118 | fw_health->regs[BNXT_FW_HEALTH_REG] = | |
7119 | le32_to_cpu(resp->fw_health_status_reg); | |
7120 | fw_health->regs[BNXT_FW_HEARTBEAT_REG] = | |
7121 | le32_to_cpu(resp->fw_heartbeat_reg); | |
7122 | fw_health->regs[BNXT_FW_RESET_CNT_REG] = | |
7123 | le32_to_cpu(resp->fw_reset_cnt_reg); | |
7124 | fw_health->regs[BNXT_FW_RESET_INPROG_REG] = | |
7125 | le32_to_cpu(resp->reset_inprogress_reg); | |
7126 | fw_health->fw_reset_inprog_reg_mask = | |
7127 | le32_to_cpu(resp->reset_inprogress_reg_mask); | |
7128 | fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; | |
7129 | if (fw_health->fw_reset_seq_cnt >= 16) { | |
7130 | rc = -EINVAL; | |
7131 | goto err_recovery_out; | |
7132 | } | |
7133 | for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { | |
7134 | fw_health->fw_reset_seq_regs[i] = | |
7135 | le32_to_cpu(resp->reset_reg[i]); | |
7136 | fw_health->fw_reset_seq_vals[i] = | |
7137 | le32_to_cpu(resp->reset_reg_val[i]); | |
7138 | fw_health->fw_reset_seq_delay_msec[i] = | |
7139 | resp->delay_after_reset[i]; | |
7140 | } | |
7141 | err_recovery_out: | |
7142 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9ffbd677 MC |
7143 | if (!rc) |
7144 | rc = bnxt_map_fw_health_regs(bp); | |
07f83d72 MC |
7145 | if (rc) |
7146 | bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; | |
7147 | return rc; | |
7148 | } | |
7149 | ||
c0c050c5 MC |
7150 | static int bnxt_hwrm_func_reset(struct bnxt *bp) |
7151 | { | |
7152 | struct hwrm_func_reset_input req = {0}; | |
7153 | ||
7154 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); | |
7155 | req.enables = 0; | |
7156 | ||
7157 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); | |
7158 | } | |
7159 | ||
7160 | static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) | |
7161 | { | |
7162 | int rc = 0; | |
7163 | struct hwrm_queue_qportcfg_input req = {0}; | |
7164 | struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
aabfc016 MC |
7165 | u8 i, j, *qptr; |
7166 | bool no_rdma; | |
c0c050c5 MC |
7167 | |
7168 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); | |
7169 | ||
7170 | mutex_lock(&bp->hwrm_cmd_lock); | |
7171 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7172 | if (rc) | |
7173 | goto qportcfg_exit; | |
7174 | ||
7175 | if (!resp->max_configurable_queues) { | |
7176 | rc = -EINVAL; | |
7177 | goto qportcfg_exit; | |
7178 | } | |
7179 | bp->max_tc = resp->max_configurable_queues; | |
87c374de | 7180 | bp->max_lltc = resp->max_configurable_lossless_queues; |
c0c050c5 MC |
7181 | if (bp->max_tc > BNXT_MAX_QUEUE) |
7182 | bp->max_tc = BNXT_MAX_QUEUE; | |
7183 | ||
aabfc016 MC |
7184 | no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); |
7185 | qptr = &resp->queue_id0; | |
7186 | for (i = 0, j = 0; i < bp->max_tc; i++) { | |
98f04cf0 MC |
7187 | bp->q_info[j].queue_id = *qptr; |
7188 | bp->q_ids[i] = *qptr++; | |
aabfc016 MC |
7189 | bp->q_info[j].queue_profile = *qptr++; |
7190 | bp->tc_to_qidx[j] = j; | |
7191 | if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || | |
7192 | (no_rdma && BNXT_PF(bp))) | |
7193 | j++; | |
7194 | } | |
98f04cf0 | 7195 | bp->max_q = bp->max_tc; |
aabfc016 MC |
7196 | bp->max_tc = max_t(u8, j, 1); |
7197 | ||
441cabbb MC |
7198 | if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) |
7199 | bp->max_tc = 1; | |
7200 | ||
87c374de MC |
7201 | if (bp->max_lltc > bp->max_tc) |
7202 | bp->max_lltc = bp->max_tc; | |
7203 | ||
c0c050c5 MC |
7204 | qportcfg_exit: |
7205 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7206 | return rc; | |
7207 | } | |
7208 | ||
ba642ab7 | 7209 | static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent) |
c0c050c5 | 7210 | { |
c0c050c5 | 7211 | struct hwrm_ver_get_input req = {0}; |
ba642ab7 | 7212 | int rc; |
c0c050c5 MC |
7213 | |
7214 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); | |
7215 | req.hwrm_intf_maj = HWRM_VERSION_MAJOR; | |
7216 | req.hwrm_intf_min = HWRM_VERSION_MINOR; | |
7217 | req.hwrm_intf_upd = HWRM_VERSION_UPDATE; | |
ba642ab7 MC |
7218 | |
7219 | rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT, | |
7220 | silent); | |
7221 | return rc; | |
7222 | } | |
7223 | ||
7224 | static int bnxt_hwrm_ver_get(struct bnxt *bp) | |
7225 | { | |
7226 | struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; | |
7227 | u32 dev_caps_cfg; | |
7228 | int rc; | |
7229 | ||
7230 | bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; | |
c0c050c5 | 7231 | mutex_lock(&bp->hwrm_cmd_lock); |
ba642ab7 | 7232 | rc = __bnxt_hwrm_ver_get(bp, false); |
c0c050c5 MC |
7233 | if (rc) |
7234 | goto hwrm_ver_get_exit; | |
7235 | ||
7236 | memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); | |
7237 | ||
894aa69a MC |
7238 | bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | |
7239 | resp->hwrm_intf_min_8b << 8 | | |
7240 | resp->hwrm_intf_upd_8b; | |
7241 | if (resp->hwrm_intf_maj_8b < 1) { | |
c193554e | 7242 | netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", |
894aa69a MC |
7243 | resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, |
7244 | resp->hwrm_intf_upd_8b); | |
c193554e | 7245 | netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); |
c0c050c5 | 7246 | } |
431aa1eb | 7247 | snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", |
894aa69a MC |
7248 | resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, |
7249 | resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); | |
c0c050c5 | 7250 | |
691aa620 VV |
7251 | if (strlen(resp->active_pkg_name)) { |
7252 | int fw_ver_len = strlen(bp->fw_ver_str); | |
7253 | ||
7254 | snprintf(bp->fw_ver_str + fw_ver_len, | |
7255 | FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", | |
7256 | resp->active_pkg_name); | |
7257 | bp->fw_cap |= BNXT_FW_CAP_PKG_VER; | |
7258 | } | |
7259 | ||
ff4fe81d MC |
7260 | bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); |
7261 | if (!bp->hwrm_cmd_timeout) | |
7262 | bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; | |
7263 | ||
1dfddc41 | 7264 | if (resp->hwrm_intf_maj_8b >= 1) { |
e6ef2699 | 7265 | bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); |
1dfddc41 MC |
7266 | bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); |
7267 | } | |
7268 | if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) | |
7269 | bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; | |
e6ef2699 | 7270 | |
659c805c | 7271 | bp->chip_num = le16_to_cpu(resp->chip_num); |
3e8060fa PS |
7272 | if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && |
7273 | !resp->chip_metal) | |
7274 | bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; | |
659c805c | 7275 | |
e605db80 DK |
7276 | dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); |
7277 | if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && | |
7278 | (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) | |
97381a18 | 7279 | bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; |
e605db80 | 7280 | |
760b6d33 VD |
7281 | if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) |
7282 | bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; | |
7283 | ||
abd43a13 VD |
7284 | if (dev_caps_cfg & |
7285 | VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) | |
7286 | bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; | |
7287 | ||
2a516444 MC |
7288 | if (dev_caps_cfg & |
7289 | VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) | |
7290 | bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; | |
7291 | ||
e969ae5b MC |
7292 | if (dev_caps_cfg & |
7293 | VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) | |
7294 | bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; | |
7295 | ||
c0c050c5 MC |
7296 | hwrm_ver_get_exit: |
7297 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7298 | return rc; | |
7299 | } | |
7300 | ||
5ac67d8b RS |
7301 | int bnxt_hwrm_fw_set_time(struct bnxt *bp) |
7302 | { | |
7303 | struct hwrm_fw_set_time_input req = {0}; | |
7dfaa7bc AB |
7304 | struct tm tm; |
7305 | time64_t now = ktime_get_real_seconds(); | |
5ac67d8b | 7306 | |
ca2c39e2 MC |
7307 | if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || |
7308 | bp->hwrm_spec_code < 0x10400) | |
5ac67d8b RS |
7309 | return -EOPNOTSUPP; |
7310 | ||
7dfaa7bc | 7311 | time64_to_tm(now, 0, &tm); |
5ac67d8b RS |
7312 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); |
7313 | req.year = cpu_to_le16(1900 + tm.tm_year); | |
7314 | req.month = 1 + tm.tm_mon; | |
7315 | req.day = tm.tm_mday; | |
7316 | req.hour = tm.tm_hour; | |
7317 | req.minute = tm.tm_min; | |
7318 | req.second = tm.tm_sec; | |
7319 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7320 | } | |
7321 | ||
3bdf56c4 MC |
7322 | static int bnxt_hwrm_port_qstats(struct bnxt *bp) |
7323 | { | |
7324 | int rc; | |
7325 | struct bnxt_pf_info *pf = &bp->pf; | |
7326 | struct hwrm_port_qstats_input req = {0}; | |
7327 | ||
7328 | if (!(bp->flags & BNXT_FLAG_PORT_STATS)) | |
7329 | return 0; | |
7330 | ||
7331 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); | |
7332 | req.port_id = cpu_to_le16(pf->port_id); | |
7333 | req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); | |
7334 | req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); | |
7335 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7336 | return rc; | |
7337 | } | |
7338 | ||
00db3cba VV |
7339 | static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) |
7340 | { | |
36e53349 | 7341 | struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; |
e37fed79 | 7342 | struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; |
00db3cba VV |
7343 | struct hwrm_port_qstats_ext_input req = {0}; |
7344 | struct bnxt_pf_info *pf = &bp->pf; | |
ad361adf | 7345 | u32 tx_stat_size; |
36e53349 | 7346 | int rc; |
00db3cba VV |
7347 | |
7348 | if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) | |
7349 | return 0; | |
7350 | ||
7351 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); | |
7352 | req.port_id = cpu_to_le16(pf->port_id); | |
7353 | req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); | |
7354 | req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); | |
ad361adf MC |
7355 | tx_stat_size = bp->hw_tx_port_stats_ext ? |
7356 | sizeof(*bp->hw_tx_port_stats_ext) : 0; | |
7357 | req.tx_stat_size = cpu_to_le16(tx_stat_size); | |
36e53349 MC |
7358 | req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map); |
7359 | mutex_lock(&bp->hwrm_cmd_lock); | |
7360 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7361 | if (!rc) { | |
7362 | bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; | |
ad361adf MC |
7363 | bp->fw_tx_stats_ext_size = tx_stat_size ? |
7364 | le16_to_cpu(resp->tx_stat_size) / 8 : 0; | |
36e53349 MC |
7365 | } else { |
7366 | bp->fw_rx_stats_ext_size = 0; | |
7367 | bp->fw_tx_stats_ext_size = 0; | |
7368 | } | |
e37fed79 MC |
7369 | if (bp->fw_tx_stats_ext_size <= |
7370 | offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { | |
7371 | mutex_unlock(&bp->hwrm_cmd_lock); | |
7372 | bp->pri2cos_valid = 0; | |
7373 | return rc; | |
7374 | } | |
7375 | ||
7376 | bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); | |
7377 | req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); | |
7378 | ||
7379 | rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); | |
7380 | if (!rc) { | |
7381 | struct hwrm_queue_pri2cos_qcfg_output *resp2; | |
7382 | u8 *pri2cos; | |
7383 | int i, j; | |
7384 | ||
7385 | resp2 = bp->hwrm_cmd_resp_addr; | |
7386 | pri2cos = &resp2->pri0_cos_queue_id; | |
7387 | for (i = 0; i < 8; i++) { | |
7388 | u8 queue_id = pri2cos[i]; | |
7389 | ||
7390 | for (j = 0; j < bp->max_q; j++) { | |
7391 | if (bp->q_ids[j] == queue_id) | |
7392 | bp->pri2cos[i] = j; | |
7393 | } | |
7394 | } | |
7395 | bp->pri2cos_valid = 1; | |
7396 | } | |
36e53349 MC |
7397 | mutex_unlock(&bp->hwrm_cmd_lock); |
7398 | return rc; | |
00db3cba VV |
7399 | } |
7400 | ||
55e4398d VV |
7401 | static int bnxt_hwrm_pcie_qstats(struct bnxt *bp) |
7402 | { | |
7403 | struct hwrm_pcie_qstats_input req = {0}; | |
7404 | ||
7405 | if (!(bp->flags & BNXT_FLAG_PCIE_STATS)) | |
7406 | return 0; | |
7407 | ||
7408 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); | |
7409 | req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats)); | |
7410 | req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map); | |
7411 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
7412 | } | |
7413 | ||
c0c050c5 MC |
7414 | static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) |
7415 | { | |
7416 | if (bp->vxlan_port_cnt) { | |
7417 | bnxt_hwrm_tunnel_dst_port_free( | |
7418 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); | |
7419 | } | |
7420 | bp->vxlan_port_cnt = 0; | |
7421 | if (bp->nge_port_cnt) { | |
7422 | bnxt_hwrm_tunnel_dst_port_free( | |
7423 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); | |
7424 | } | |
7425 | bp->nge_port_cnt = 0; | |
7426 | } | |
7427 | ||
7428 | static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) | |
7429 | { | |
7430 | int rc, i; | |
7431 | u32 tpa_flags = 0; | |
7432 | ||
7433 | if (set_tpa) | |
7434 | tpa_flags = bp->flags & BNXT_FLAG_TPA; | |
b4fff207 MC |
7435 | else if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) |
7436 | return 0; | |
c0c050c5 MC |
7437 | for (i = 0; i < bp->nr_vnics; i++) { |
7438 | rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); | |
7439 | if (rc) { | |
7440 | netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", | |
23e12c89 | 7441 | i, rc); |
c0c050c5 MC |
7442 | return rc; |
7443 | } | |
7444 | } | |
7445 | return 0; | |
7446 | } | |
7447 | ||
7448 | static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) | |
7449 | { | |
7450 | int i; | |
7451 | ||
7452 | for (i = 0; i < bp->nr_vnics; i++) | |
7453 | bnxt_hwrm_vnic_set_rss(bp, i, false); | |
7454 | } | |
7455 | ||
a46ecb11 | 7456 | static void bnxt_clear_vnic(struct bnxt *bp) |
c0c050c5 | 7457 | { |
a46ecb11 MC |
7458 | if (!bp->vnic_info) |
7459 | return; | |
7460 | ||
7461 | bnxt_hwrm_clear_vnic_filter(bp); | |
7462 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { | |
c0c050c5 MC |
7463 | /* clear all RSS setting before free vnic ctx */ |
7464 | bnxt_hwrm_clear_vnic_rss(bp); | |
7465 | bnxt_hwrm_vnic_ctx_free(bp); | |
c0c050c5 | 7466 | } |
a46ecb11 MC |
7467 | /* before free the vnic, undo the vnic tpa settings */ |
7468 | if (bp->flags & BNXT_FLAG_TPA) | |
7469 | bnxt_set_tpa(bp, false); | |
7470 | bnxt_hwrm_vnic_free(bp); | |
7471 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7472 | bnxt_hwrm_vnic_ctx_free(bp); | |
7473 | } | |
7474 | ||
7475 | static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, | |
7476 | bool irq_re_init) | |
7477 | { | |
7478 | bnxt_clear_vnic(bp); | |
c0c050c5 MC |
7479 | bnxt_hwrm_ring_free(bp, close_path); |
7480 | bnxt_hwrm_ring_grp_free(bp); | |
7481 | if (irq_re_init) { | |
7482 | bnxt_hwrm_stat_ctx_free(bp); | |
7483 | bnxt_hwrm_free_tunnel_ports(bp); | |
7484 | } | |
7485 | } | |
7486 | ||
39d8ba2e MC |
7487 | static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) |
7488 | { | |
7489 | struct hwrm_func_cfg_input req = {0}; | |
7490 | int rc; | |
7491 | ||
7492 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
7493 | req.fid = cpu_to_le16(0xffff); | |
7494 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); | |
7495 | if (br_mode == BRIDGE_MODE_VEB) | |
7496 | req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; | |
7497 | else if (br_mode == BRIDGE_MODE_VEPA) | |
7498 | req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; | |
7499 | else | |
7500 | return -EINVAL; | |
7501 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
39d8ba2e MC |
7502 | return rc; |
7503 | } | |
7504 | ||
c3480a60 MC |
7505 | static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) |
7506 | { | |
7507 | struct hwrm_func_cfg_input req = {0}; | |
7508 | int rc; | |
7509 | ||
7510 | if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) | |
7511 | return 0; | |
7512 | ||
7513 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); | |
7514 | req.fid = cpu_to_le16(0xffff); | |
7515 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); | |
d4f52de0 | 7516 | req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; |
c3480a60 | 7517 | if (size == 128) |
d4f52de0 | 7518 | req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; |
c3480a60 MC |
7519 | |
7520 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
c3480a60 MC |
7521 | return rc; |
7522 | } | |
7523 | ||
7b3af4f7 | 7524 | static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) |
c0c050c5 | 7525 | { |
ae10ae74 | 7526 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
c0c050c5 MC |
7527 | int rc; |
7528 | ||
ae10ae74 MC |
7529 | if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) |
7530 | goto skip_rss_ctx; | |
7531 | ||
c0c050c5 | 7532 | /* allocate context for vnic */ |
94ce9caa | 7533 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); |
c0c050c5 MC |
7534 | if (rc) { |
7535 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", | |
7536 | vnic_id, rc); | |
7537 | goto vnic_setup_err; | |
7538 | } | |
7539 | bp->rsscos_nr_ctxs++; | |
7540 | ||
94ce9caa PS |
7541 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
7542 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); | |
7543 | if (rc) { | |
7544 | netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", | |
7545 | vnic_id, rc); | |
7546 | goto vnic_setup_err; | |
7547 | } | |
7548 | bp->rsscos_nr_ctxs++; | |
7549 | } | |
7550 | ||
ae10ae74 | 7551 | skip_rss_ctx: |
c0c050c5 MC |
7552 | /* configure default vnic, ring grp */ |
7553 | rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); | |
7554 | if (rc) { | |
7555 | netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", | |
7556 | vnic_id, rc); | |
7557 | goto vnic_setup_err; | |
7558 | } | |
7559 | ||
7560 | /* Enable RSS hashing on vnic */ | |
7561 | rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); | |
7562 | if (rc) { | |
7563 | netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", | |
7564 | vnic_id, rc); | |
7565 | goto vnic_setup_err; | |
7566 | } | |
7567 | ||
7568 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
7569 | rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); | |
7570 | if (rc) { | |
7571 | netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", | |
7572 | vnic_id, rc); | |
7573 | } | |
7574 | } | |
7575 | ||
7576 | vnic_setup_err: | |
7577 | return rc; | |
7578 | } | |
7579 | ||
7b3af4f7 MC |
7580 | static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) |
7581 | { | |
7582 | int rc, i, nr_ctxs; | |
7583 | ||
7584 | nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); | |
7585 | for (i = 0; i < nr_ctxs; i++) { | |
7586 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); | |
7587 | if (rc) { | |
7588 | netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", | |
7589 | vnic_id, i, rc); | |
7590 | break; | |
7591 | } | |
7592 | bp->rsscos_nr_ctxs++; | |
7593 | } | |
7594 | if (i < nr_ctxs) | |
7595 | return -ENOMEM; | |
7596 | ||
7597 | rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); | |
7598 | if (rc) { | |
7599 | netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", | |
7600 | vnic_id, rc); | |
7601 | return rc; | |
7602 | } | |
7603 | rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); | |
7604 | if (rc) { | |
7605 | netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", | |
7606 | vnic_id, rc); | |
7607 | return rc; | |
7608 | } | |
7609 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { | |
7610 | rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); | |
7611 | if (rc) { | |
7612 | netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", | |
7613 | vnic_id, rc); | |
7614 | } | |
7615 | } | |
7616 | return rc; | |
7617 | } | |
7618 | ||
7619 | static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) | |
7620 | { | |
7621 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7622 | return __bnxt_setup_vnic_p5(bp, vnic_id); | |
7623 | else | |
7624 | return __bnxt_setup_vnic(bp, vnic_id); | |
7625 | } | |
7626 | ||
c0c050c5 MC |
7627 | static int bnxt_alloc_rfs_vnics(struct bnxt *bp) |
7628 | { | |
7629 | #ifdef CONFIG_RFS_ACCEL | |
7630 | int i, rc = 0; | |
7631 | ||
9b3d15e6 MC |
7632 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
7633 | return 0; | |
7634 | ||
c0c050c5 | 7635 | for (i = 0; i < bp->rx_nr_rings; i++) { |
ae10ae74 | 7636 | struct bnxt_vnic_info *vnic; |
c0c050c5 MC |
7637 | u16 vnic_id = i + 1; |
7638 | u16 ring_id = i; | |
7639 | ||
7640 | if (vnic_id >= bp->nr_vnics) | |
7641 | break; | |
7642 | ||
ae10ae74 MC |
7643 | vnic = &bp->vnic_info[vnic_id]; |
7644 | vnic->flags |= BNXT_VNIC_RFS_FLAG; | |
7645 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) | |
7646 | vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; | |
b81a90d3 | 7647 | rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); |
c0c050c5 MC |
7648 | if (rc) { |
7649 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", | |
7650 | vnic_id, rc); | |
7651 | break; | |
7652 | } | |
7653 | rc = bnxt_setup_vnic(bp, vnic_id); | |
7654 | if (rc) | |
7655 | break; | |
7656 | } | |
7657 | return rc; | |
7658 | #else | |
7659 | return 0; | |
7660 | #endif | |
7661 | } | |
7662 | ||
17c71ac3 MC |
7663 | /* Allow PF and VF with default VLAN to be in promiscuous mode */ |
7664 | static bool bnxt_promisc_ok(struct bnxt *bp) | |
7665 | { | |
7666 | #ifdef CONFIG_BNXT_SRIOV | |
7667 | if (BNXT_VF(bp) && !bp->vf.vlan) | |
7668 | return false; | |
7669 | #endif | |
7670 | return true; | |
7671 | } | |
7672 | ||
dc52c6c7 PS |
7673 | static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) |
7674 | { | |
7675 | unsigned int rc = 0; | |
7676 | ||
7677 | rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); | |
7678 | if (rc) { | |
7679 | netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", | |
7680 | rc); | |
7681 | return rc; | |
7682 | } | |
7683 | ||
7684 | rc = bnxt_hwrm_vnic_cfg(bp, 1); | |
7685 | if (rc) { | |
7686 | netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", | |
7687 | rc); | |
7688 | return rc; | |
7689 | } | |
7690 | return rc; | |
7691 | } | |
7692 | ||
b664f008 | 7693 | static int bnxt_cfg_rx_mode(struct bnxt *); |
7d2837dd | 7694 | static bool bnxt_mc_list_updated(struct bnxt *, u32 *); |
b664f008 | 7695 | |
c0c050c5 MC |
7696 | static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) |
7697 | { | |
7d2837dd | 7698 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; |
c0c050c5 | 7699 | int rc = 0; |
76595193 | 7700 | unsigned int rx_nr_rings = bp->rx_nr_rings; |
c0c050c5 MC |
7701 | |
7702 | if (irq_re_init) { | |
7703 | rc = bnxt_hwrm_stat_ctx_alloc(bp); | |
7704 | if (rc) { | |
7705 | netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", | |
7706 | rc); | |
7707 | goto err_out; | |
7708 | } | |
7709 | } | |
7710 | ||
7711 | rc = bnxt_hwrm_ring_alloc(bp); | |
7712 | if (rc) { | |
7713 | netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); | |
7714 | goto err_out; | |
7715 | } | |
7716 | ||
7717 | rc = bnxt_hwrm_ring_grp_alloc(bp); | |
7718 | if (rc) { | |
7719 | netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); | |
7720 | goto err_out; | |
7721 | } | |
7722 | ||
76595193 PS |
7723 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) |
7724 | rx_nr_rings--; | |
7725 | ||
c0c050c5 | 7726 | /* default vnic 0 */ |
76595193 | 7727 | rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); |
c0c050c5 MC |
7728 | if (rc) { |
7729 | netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); | |
7730 | goto err_out; | |
7731 | } | |
7732 | ||
7733 | rc = bnxt_setup_vnic(bp, 0); | |
7734 | if (rc) | |
7735 | goto err_out; | |
7736 | ||
7737 | if (bp->flags & BNXT_FLAG_RFS) { | |
7738 | rc = bnxt_alloc_rfs_vnics(bp); | |
7739 | if (rc) | |
7740 | goto err_out; | |
7741 | } | |
7742 | ||
7743 | if (bp->flags & BNXT_FLAG_TPA) { | |
7744 | rc = bnxt_set_tpa(bp, true); | |
7745 | if (rc) | |
7746 | goto err_out; | |
7747 | } | |
7748 | ||
7749 | if (BNXT_VF(bp)) | |
7750 | bnxt_update_vf_mac(bp); | |
7751 | ||
7752 | /* Filter for default vnic 0 */ | |
7753 | rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); | |
7754 | if (rc) { | |
7755 | netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); | |
7756 | goto err_out; | |
7757 | } | |
7d2837dd | 7758 | vnic->uc_filter_count = 1; |
c0c050c5 | 7759 | |
30e33848 MC |
7760 | vnic->rx_mask = 0; |
7761 | if (bp->dev->flags & IFF_BROADCAST) | |
7762 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; | |
c0c050c5 | 7763 | |
17c71ac3 | 7764 | if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) |
7d2837dd MC |
7765 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
7766 | ||
7767 | if (bp->dev->flags & IFF_ALLMULTI) { | |
7768 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
7769 | vnic->mc_list_count = 0; | |
7770 | } else { | |
7771 | u32 mask = 0; | |
7772 | ||
7773 | bnxt_mc_list_updated(bp, &mask); | |
7774 | vnic->rx_mask |= mask; | |
7775 | } | |
c0c050c5 | 7776 | |
b664f008 MC |
7777 | rc = bnxt_cfg_rx_mode(bp); |
7778 | if (rc) | |
c0c050c5 | 7779 | goto err_out; |
c0c050c5 MC |
7780 | |
7781 | rc = bnxt_hwrm_set_coal(bp); | |
7782 | if (rc) | |
7783 | netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", | |
dc52c6c7 PS |
7784 | rc); |
7785 | ||
7786 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { | |
7787 | rc = bnxt_setup_nitroa0_vnic(bp); | |
7788 | if (rc) | |
7789 | netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", | |
7790 | rc); | |
7791 | } | |
c0c050c5 | 7792 | |
cf6645f8 MC |
7793 | if (BNXT_VF(bp)) { |
7794 | bnxt_hwrm_func_qcfg(bp); | |
7795 | netdev_update_features(bp->dev); | |
7796 | } | |
7797 | ||
c0c050c5 MC |
7798 | return 0; |
7799 | ||
7800 | err_out: | |
7801 | bnxt_hwrm_resource_free(bp, 0, true); | |
7802 | ||
7803 | return rc; | |
7804 | } | |
7805 | ||
7806 | static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) | |
7807 | { | |
7808 | bnxt_hwrm_resource_free(bp, 1, irq_re_init); | |
7809 | return 0; | |
7810 | } | |
7811 | ||
7812 | static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) | |
7813 | { | |
2247925f | 7814 | bnxt_init_cp_rings(bp); |
c0c050c5 MC |
7815 | bnxt_init_rx_rings(bp); |
7816 | bnxt_init_tx_rings(bp); | |
7817 | bnxt_init_ring_grps(bp, irq_re_init); | |
7818 | bnxt_init_vnics(bp); | |
7819 | ||
7820 | return bnxt_init_chip(bp, irq_re_init); | |
7821 | } | |
7822 | ||
c0c050c5 MC |
7823 | static int bnxt_set_real_num_queues(struct bnxt *bp) |
7824 | { | |
7825 | int rc; | |
7826 | struct net_device *dev = bp->dev; | |
7827 | ||
5f449249 MC |
7828 | rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - |
7829 | bp->tx_nr_rings_xdp); | |
c0c050c5 MC |
7830 | if (rc) |
7831 | return rc; | |
7832 | ||
7833 | rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); | |
7834 | if (rc) | |
7835 | return rc; | |
7836 | ||
7837 | #ifdef CONFIG_RFS_ACCEL | |
45019a18 | 7838 | if (bp->flags & BNXT_FLAG_RFS) |
c0c050c5 | 7839 | dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); |
c0c050c5 MC |
7840 | #endif |
7841 | ||
7842 | return rc; | |
7843 | } | |
7844 | ||
6e6c5a57 MC |
7845 | static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, |
7846 | bool shared) | |
7847 | { | |
7848 | int _rx = *rx, _tx = *tx; | |
7849 | ||
7850 | if (shared) { | |
7851 | *rx = min_t(int, _rx, max); | |
7852 | *tx = min_t(int, _tx, max); | |
7853 | } else { | |
7854 | if (max < 2) | |
7855 | return -ENOMEM; | |
7856 | ||
7857 | while (_rx + _tx > max) { | |
7858 | if (_rx > _tx && _rx > 1) | |
7859 | _rx--; | |
7860 | else if (_tx > 1) | |
7861 | _tx--; | |
7862 | } | |
7863 | *rx = _rx; | |
7864 | *tx = _tx; | |
7865 | } | |
7866 | return 0; | |
7867 | } | |
7868 | ||
7809592d MC |
7869 | static void bnxt_setup_msix(struct bnxt *bp) |
7870 | { | |
7871 | const int len = sizeof(bp->irq_tbl[0].name); | |
7872 | struct net_device *dev = bp->dev; | |
7873 | int tcs, i; | |
7874 | ||
7875 | tcs = netdev_get_num_tc(dev); | |
7876 | if (tcs > 1) { | |
d1e7925e | 7877 | int i, off, count; |
7809592d | 7878 | |
d1e7925e MC |
7879 | for (i = 0; i < tcs; i++) { |
7880 | count = bp->tx_nr_rings_per_tc; | |
7881 | off = i * count; | |
7882 | netdev_set_tc_queue(dev, i, count, off); | |
7809592d MC |
7883 | } |
7884 | } | |
7885 | ||
7886 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
e5811b8c | 7887 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
7809592d MC |
7888 | char *attr; |
7889 | ||
7890 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
7891 | attr = "TxRx"; | |
7892 | else if (i < bp->rx_nr_rings) | |
7893 | attr = "rx"; | |
7894 | else | |
7895 | attr = "tx"; | |
7896 | ||
e5811b8c MC |
7897 | snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, |
7898 | attr, i); | |
7899 | bp->irq_tbl[map_idx].handler = bnxt_msix; | |
7809592d MC |
7900 | } |
7901 | } | |
7902 | ||
7903 | static void bnxt_setup_inta(struct bnxt *bp) | |
7904 | { | |
7905 | const int len = sizeof(bp->irq_tbl[0].name); | |
7906 | ||
7907 | if (netdev_get_num_tc(bp->dev)) | |
7908 | netdev_reset_tc(bp->dev); | |
7909 | ||
7910 | snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", | |
7911 | 0); | |
7912 | bp->irq_tbl[0].handler = bnxt_inta; | |
7913 | } | |
7914 | ||
7915 | static int bnxt_setup_int_mode(struct bnxt *bp) | |
7916 | { | |
7917 | int rc; | |
7918 | ||
7919 | if (bp->flags & BNXT_FLAG_USING_MSIX) | |
7920 | bnxt_setup_msix(bp); | |
7921 | else | |
7922 | bnxt_setup_inta(bp); | |
7923 | ||
7924 | rc = bnxt_set_real_num_queues(bp); | |
7925 | return rc; | |
7926 | } | |
7927 | ||
b7429954 | 7928 | #ifdef CONFIG_RFS_ACCEL |
8079e8f1 MC |
7929 | static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) |
7930 | { | |
6a4f2947 | 7931 | return bp->hw_resc.max_rsscos_ctxs; |
8079e8f1 MC |
7932 | } |
7933 | ||
7934 | static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) | |
7935 | { | |
6a4f2947 | 7936 | return bp->hw_resc.max_vnics; |
8079e8f1 | 7937 | } |
b7429954 | 7938 | #endif |
8079e8f1 | 7939 | |
e4060d30 MC |
7940 | unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) |
7941 | { | |
6a4f2947 | 7942 | return bp->hw_resc.max_stat_ctxs; |
e4060d30 MC |
7943 | } |
7944 | ||
7945 | unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) | |
7946 | { | |
6a4f2947 | 7947 | return bp->hw_resc.max_cp_rings; |
e4060d30 MC |
7948 | } |
7949 | ||
e916b081 | 7950 | static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) |
a588e458 | 7951 | { |
c0b8cda0 MC |
7952 | unsigned int cp = bp->hw_resc.max_cp_rings; |
7953 | ||
7954 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
7955 | cp -= bnxt_get_ulp_msix_num(bp); | |
7956 | ||
7957 | return cp; | |
a588e458 MC |
7958 | } |
7959 | ||
ad95c27b | 7960 | static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) |
7809592d | 7961 | { |
6a4f2947 MC |
7962 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
7963 | ||
f7588cd8 MC |
7964 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
7965 | return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); | |
7966 | ||
6a4f2947 | 7967 | return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); |
7809592d MC |
7968 | } |
7969 | ||
30f52947 | 7970 | static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) |
33c2657e | 7971 | { |
6a4f2947 | 7972 | bp->hw_resc.max_irqs = max_irqs; |
33c2657e MC |
7973 | } |
7974 | ||
e916b081 MC |
7975 | unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) |
7976 | { | |
7977 | unsigned int cp; | |
7978 | ||
7979 | cp = bnxt_get_max_func_cp_rings_for_en(bp); | |
7980 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
7981 | return cp - bp->rx_nr_rings - bp->tx_nr_rings; | |
7982 | else | |
7983 | return cp - bp->cp_nr_rings; | |
7984 | } | |
7985 | ||
c027c6b4 VV |
7986 | unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) |
7987 | { | |
d77b1ad8 | 7988 | return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); |
c027c6b4 VV |
7989 | } |
7990 | ||
fbcfc8e4 MC |
7991 | int bnxt_get_avail_msix(struct bnxt *bp, int num) |
7992 | { | |
7993 | int max_cp = bnxt_get_max_func_cp_rings(bp); | |
7994 | int max_irq = bnxt_get_max_func_irqs(bp); | |
7995 | int total_req = bp->cp_nr_rings + num; | |
7996 | int max_idx, avail_msix; | |
7997 | ||
75720e63 MC |
7998 | max_idx = bp->total_irqs; |
7999 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
8000 | max_idx = min_t(int, bp->total_irqs, max_cp); | |
fbcfc8e4 | 8001 | avail_msix = max_idx - bp->cp_nr_rings; |
f1ca94de | 8002 | if (!BNXT_NEW_RM(bp) || avail_msix >= num) |
fbcfc8e4 MC |
8003 | return avail_msix; |
8004 | ||
8005 | if (max_irq < total_req) { | |
8006 | num = max_irq - bp->cp_nr_rings; | |
8007 | if (num <= 0) | |
8008 | return 0; | |
8009 | } | |
8010 | return num; | |
8011 | } | |
8012 | ||
08654eb2 MC |
8013 | static int bnxt_get_num_msix(struct bnxt *bp) |
8014 | { | |
f1ca94de | 8015 | if (!BNXT_NEW_RM(bp)) |
08654eb2 MC |
8016 | return bnxt_get_max_func_irqs(bp); |
8017 | ||
c0b8cda0 | 8018 | return bnxt_nq_rings_in_use(bp); |
08654eb2 MC |
8019 | } |
8020 | ||
7809592d | 8021 | static int bnxt_init_msix(struct bnxt *bp) |
c0c050c5 | 8022 | { |
fbcfc8e4 | 8023 | int i, total_vecs, max, rc = 0, min = 1, ulp_msix; |
7809592d | 8024 | struct msix_entry *msix_ent; |
c0c050c5 | 8025 | |
08654eb2 MC |
8026 | total_vecs = bnxt_get_num_msix(bp); |
8027 | max = bnxt_get_max_func_irqs(bp); | |
8028 | if (total_vecs > max) | |
8029 | total_vecs = max; | |
8030 | ||
2773dfb2 MC |
8031 | if (!total_vecs) |
8032 | return 0; | |
8033 | ||
c0c050c5 MC |
8034 | msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); |
8035 | if (!msix_ent) | |
8036 | return -ENOMEM; | |
8037 | ||
8038 | for (i = 0; i < total_vecs; i++) { | |
8039 | msix_ent[i].entry = i; | |
8040 | msix_ent[i].vector = 0; | |
8041 | } | |
8042 | ||
01657bcd MC |
8043 | if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) |
8044 | min = 2; | |
8045 | ||
8046 | total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); | |
fbcfc8e4 MC |
8047 | ulp_msix = bnxt_get_ulp_msix_num(bp); |
8048 | if (total_vecs < 0 || total_vecs < ulp_msix) { | |
c0c050c5 MC |
8049 | rc = -ENODEV; |
8050 | goto msix_setup_exit; | |
8051 | } | |
8052 | ||
8053 | bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); | |
8054 | if (bp->irq_tbl) { | |
7809592d MC |
8055 | for (i = 0; i < total_vecs; i++) |
8056 | bp->irq_tbl[i].vector = msix_ent[i].vector; | |
c0c050c5 | 8057 | |
7809592d | 8058 | bp->total_irqs = total_vecs; |
c0c050c5 | 8059 | /* Trim rings based upon num of vectors allocated */ |
6e6c5a57 | 8060 | rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, |
fbcfc8e4 | 8061 | total_vecs - ulp_msix, min == 1); |
6e6c5a57 MC |
8062 | if (rc) |
8063 | goto msix_setup_exit; | |
8064 | ||
7809592d MC |
8065 | bp->cp_nr_rings = (min == 1) ? |
8066 | max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : | |
8067 | bp->tx_nr_rings + bp->rx_nr_rings; | |
c0c050c5 | 8068 | |
c0c050c5 MC |
8069 | } else { |
8070 | rc = -ENOMEM; | |
8071 | goto msix_setup_exit; | |
8072 | } | |
8073 | bp->flags |= BNXT_FLAG_USING_MSIX; | |
8074 | kfree(msix_ent); | |
8075 | return 0; | |
8076 | ||
8077 | msix_setup_exit: | |
7809592d MC |
8078 | netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); |
8079 | kfree(bp->irq_tbl); | |
8080 | bp->irq_tbl = NULL; | |
c0c050c5 MC |
8081 | pci_disable_msix(bp->pdev); |
8082 | kfree(msix_ent); | |
8083 | return rc; | |
8084 | } | |
8085 | ||
7809592d | 8086 | static int bnxt_init_inta(struct bnxt *bp) |
c0c050c5 | 8087 | { |
c0c050c5 | 8088 | bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); |
7809592d MC |
8089 | if (!bp->irq_tbl) |
8090 | return -ENOMEM; | |
8091 | ||
8092 | bp->total_irqs = 1; | |
c0c050c5 MC |
8093 | bp->rx_nr_rings = 1; |
8094 | bp->tx_nr_rings = 1; | |
8095 | bp->cp_nr_rings = 1; | |
01657bcd | 8096 | bp->flags |= BNXT_FLAG_SHARED_RINGS; |
c0c050c5 | 8097 | bp->irq_tbl[0].vector = bp->pdev->irq; |
7809592d | 8098 | return 0; |
c0c050c5 MC |
8099 | } |
8100 | ||
7809592d | 8101 | static int bnxt_init_int_mode(struct bnxt *bp) |
c0c050c5 MC |
8102 | { |
8103 | int rc = 0; | |
8104 | ||
8105 | if (bp->flags & BNXT_FLAG_MSIX_CAP) | |
7809592d | 8106 | rc = bnxt_init_msix(bp); |
c0c050c5 | 8107 | |
1fa72e29 | 8108 | if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { |
c0c050c5 | 8109 | /* fallback to INTA */ |
7809592d | 8110 | rc = bnxt_init_inta(bp); |
c0c050c5 MC |
8111 | } |
8112 | return rc; | |
8113 | } | |
8114 | ||
7809592d MC |
8115 | static void bnxt_clear_int_mode(struct bnxt *bp) |
8116 | { | |
8117 | if (bp->flags & BNXT_FLAG_USING_MSIX) | |
8118 | pci_disable_msix(bp->pdev); | |
8119 | ||
8120 | kfree(bp->irq_tbl); | |
8121 | bp->irq_tbl = NULL; | |
8122 | bp->flags &= ~BNXT_FLAG_USING_MSIX; | |
8123 | } | |
8124 | ||
1b3f0b75 | 8125 | int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) |
674f50a5 | 8126 | { |
674f50a5 | 8127 | int tcs = netdev_get_num_tc(bp->dev); |
1b3f0b75 | 8128 | bool irq_cleared = false; |
674f50a5 MC |
8129 | int rc; |
8130 | ||
8131 | if (!bnxt_need_reserve_rings(bp)) | |
8132 | return 0; | |
8133 | ||
1b3f0b75 MC |
8134 | if (irq_re_init && BNXT_NEW_RM(bp) && |
8135 | bnxt_get_num_msix(bp) != bp->total_irqs) { | |
ec86f14e | 8136 | bnxt_ulp_irq_stop(bp); |
674f50a5 | 8137 | bnxt_clear_int_mode(bp); |
1b3f0b75 | 8138 | irq_cleared = true; |
36d65be9 MC |
8139 | } |
8140 | rc = __bnxt_reserve_rings(bp); | |
1b3f0b75 | 8141 | if (irq_cleared) { |
36d65be9 MC |
8142 | if (!rc) |
8143 | rc = bnxt_init_int_mode(bp); | |
ec86f14e | 8144 | bnxt_ulp_irq_restart(bp, rc); |
36d65be9 MC |
8145 | } |
8146 | if (rc) { | |
8147 | netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); | |
8148 | return rc; | |
674f50a5 MC |
8149 | } |
8150 | if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { | |
8151 | netdev_err(bp->dev, "tx ring reservation failure\n"); | |
8152 | netdev_reset_tc(bp->dev); | |
8153 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
8154 | return -ENOMEM; | |
8155 | } | |
674f50a5 MC |
8156 | return 0; |
8157 | } | |
8158 | ||
c0c050c5 MC |
8159 | static void bnxt_free_irq(struct bnxt *bp) |
8160 | { | |
8161 | struct bnxt_irq *irq; | |
8162 | int i; | |
8163 | ||
8164 | #ifdef CONFIG_RFS_ACCEL | |
8165 | free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); | |
8166 | bp->dev->rx_cpu_rmap = NULL; | |
8167 | #endif | |
cb98526b | 8168 | if (!bp->irq_tbl || !bp->bnapi) |
c0c050c5 MC |
8169 | return; |
8170 | ||
8171 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
e5811b8c MC |
8172 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
8173 | ||
8174 | irq = &bp->irq_tbl[map_idx]; | |
56f0fd80 VV |
8175 | if (irq->requested) { |
8176 | if (irq->have_cpumask) { | |
8177 | irq_set_affinity_hint(irq->vector, NULL); | |
8178 | free_cpumask_var(irq->cpu_mask); | |
8179 | irq->have_cpumask = 0; | |
8180 | } | |
c0c050c5 | 8181 | free_irq(irq->vector, bp->bnapi[i]); |
56f0fd80 VV |
8182 | } |
8183 | ||
c0c050c5 MC |
8184 | irq->requested = 0; |
8185 | } | |
c0c050c5 MC |
8186 | } |
8187 | ||
8188 | static int bnxt_request_irq(struct bnxt *bp) | |
8189 | { | |
b81a90d3 | 8190 | int i, j, rc = 0; |
c0c050c5 MC |
8191 | unsigned long flags = 0; |
8192 | #ifdef CONFIG_RFS_ACCEL | |
e5811b8c | 8193 | struct cpu_rmap *rmap; |
c0c050c5 MC |
8194 | #endif |
8195 | ||
e5811b8c MC |
8196 | rc = bnxt_setup_int_mode(bp); |
8197 | if (rc) { | |
8198 | netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", | |
8199 | rc); | |
8200 | return rc; | |
8201 | } | |
8202 | #ifdef CONFIG_RFS_ACCEL | |
8203 | rmap = bp->dev->rx_cpu_rmap; | |
8204 | #endif | |
c0c050c5 MC |
8205 | if (!(bp->flags & BNXT_FLAG_USING_MSIX)) |
8206 | flags = IRQF_SHARED; | |
8207 | ||
b81a90d3 | 8208 | for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { |
e5811b8c MC |
8209 | int map_idx = bnxt_cp_num_to_irq_num(bp, i); |
8210 | struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; | |
8211 | ||
c0c050c5 | 8212 | #ifdef CONFIG_RFS_ACCEL |
b81a90d3 | 8213 | if (rmap && bp->bnapi[i]->rx_ring) { |
c0c050c5 MC |
8214 | rc = irq_cpu_rmap_add(rmap, irq->vector); |
8215 | if (rc) | |
8216 | netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", | |
b81a90d3 MC |
8217 | j); |
8218 | j++; | |
c0c050c5 MC |
8219 | } |
8220 | #endif | |
8221 | rc = request_irq(irq->vector, irq->handler, flags, irq->name, | |
8222 | bp->bnapi[i]); | |
8223 | if (rc) | |
8224 | break; | |
8225 | ||
8226 | irq->requested = 1; | |
56f0fd80 VV |
8227 | |
8228 | if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { | |
8229 | int numa_node = dev_to_node(&bp->pdev->dev); | |
8230 | ||
8231 | irq->have_cpumask = 1; | |
8232 | cpumask_set_cpu(cpumask_local_spread(i, numa_node), | |
8233 | irq->cpu_mask); | |
8234 | rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); | |
8235 | if (rc) { | |
8236 | netdev_warn(bp->dev, | |
8237 | "Set affinity failed, IRQ = %d\n", | |
8238 | irq->vector); | |
8239 | break; | |
8240 | } | |
8241 | } | |
c0c050c5 MC |
8242 | } |
8243 | return rc; | |
8244 | } | |
8245 | ||
8246 | static void bnxt_del_napi(struct bnxt *bp) | |
8247 | { | |
8248 | int i; | |
8249 | ||
8250 | if (!bp->bnapi) | |
8251 | return; | |
8252 | ||
8253 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
8254 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
8255 | ||
8256 | napi_hash_del(&bnapi->napi); | |
8257 | netif_napi_del(&bnapi->napi); | |
8258 | } | |
e5f6f564 ED |
8259 | /* We called napi_hash_del() before netif_napi_del(), we need |
8260 | * to respect an RCU grace period before freeing napi structures. | |
8261 | */ | |
8262 | synchronize_net(); | |
c0c050c5 MC |
8263 | } |
8264 | ||
8265 | static void bnxt_init_napi(struct bnxt *bp) | |
8266 | { | |
8267 | int i; | |
10bbdaf5 | 8268 | unsigned int cp_nr_rings = bp->cp_nr_rings; |
c0c050c5 MC |
8269 | struct bnxt_napi *bnapi; |
8270 | ||
8271 | if (bp->flags & BNXT_FLAG_USING_MSIX) { | |
0fcec985 MC |
8272 | int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; |
8273 | ||
8274 | if (bp->flags & BNXT_FLAG_CHIP_P5) | |
8275 | poll_fn = bnxt_poll_p5; | |
8276 | else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) | |
10bbdaf5 PS |
8277 | cp_nr_rings--; |
8278 | for (i = 0; i < cp_nr_rings; i++) { | |
c0c050c5 | 8279 | bnapi = bp->bnapi[i]; |
0fcec985 | 8280 | netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); |
c0c050c5 | 8281 | } |
10bbdaf5 PS |
8282 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
8283 | bnapi = bp->bnapi[cp_nr_rings]; | |
8284 | netif_napi_add(bp->dev, &bnapi->napi, | |
8285 | bnxt_poll_nitroa0, 64); | |
10bbdaf5 | 8286 | } |
c0c050c5 MC |
8287 | } else { |
8288 | bnapi = bp->bnapi[0]; | |
8289 | netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); | |
c0c050c5 MC |
8290 | } |
8291 | } | |
8292 | ||
8293 | static void bnxt_disable_napi(struct bnxt *bp) | |
8294 | { | |
8295 | int i; | |
8296 | ||
8297 | if (!bp->bnapi) | |
8298 | return; | |
8299 | ||
0bc0b97f AG |
8300 | for (i = 0; i < bp->cp_nr_rings; i++) { |
8301 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; | |
8302 | ||
8303 | if (bp->bnapi[i]->rx_ring) | |
8304 | cancel_work_sync(&cpr->dim.work); | |
8305 | ||
c0c050c5 | 8306 | napi_disable(&bp->bnapi[i]->napi); |
0bc0b97f | 8307 | } |
c0c050c5 MC |
8308 | } |
8309 | ||
8310 | static void bnxt_enable_napi(struct bnxt *bp) | |
8311 | { | |
8312 | int i; | |
8313 | ||
8314 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
6a8788f2 | 8315 | struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; |
fa7e2812 | 8316 | bp->bnapi[i]->in_reset = false; |
6a8788f2 AG |
8317 | |
8318 | if (bp->bnapi[i]->rx_ring) { | |
8319 | INIT_WORK(&cpr->dim.work, bnxt_dim_work); | |
c002bd52 | 8320 | cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
6a8788f2 | 8321 | } |
c0c050c5 MC |
8322 | napi_enable(&bp->bnapi[i]->napi); |
8323 | } | |
8324 | } | |
8325 | ||
7df4ae9f | 8326 | void bnxt_tx_disable(struct bnxt *bp) |
c0c050c5 MC |
8327 | { |
8328 | int i; | |
c0c050c5 | 8329 | struct bnxt_tx_ring_info *txr; |
c0c050c5 | 8330 | |
b6ab4b01 | 8331 | if (bp->tx_ring) { |
c0c050c5 | 8332 | for (i = 0; i < bp->tx_nr_rings; i++) { |
b6ab4b01 | 8333 | txr = &bp->tx_ring[i]; |
c0c050c5 | 8334 | txr->dev_state = BNXT_DEV_STATE_CLOSING; |
c0c050c5 MC |
8335 | } |
8336 | } | |
8337 | /* Stop all TX queues */ | |
8338 | netif_tx_disable(bp->dev); | |
8339 | netif_carrier_off(bp->dev); | |
8340 | } | |
8341 | ||
7df4ae9f | 8342 | void bnxt_tx_enable(struct bnxt *bp) |
c0c050c5 MC |
8343 | { |
8344 | int i; | |
c0c050c5 | 8345 | struct bnxt_tx_ring_info *txr; |
c0c050c5 MC |
8346 | |
8347 | for (i = 0; i < bp->tx_nr_rings; i++) { | |
b6ab4b01 | 8348 | txr = &bp->tx_ring[i]; |
c0c050c5 MC |
8349 | txr->dev_state = 0; |
8350 | } | |
8351 | netif_tx_wake_all_queues(bp->dev); | |
8352 | if (bp->link_info.link_up) | |
8353 | netif_carrier_on(bp->dev); | |
8354 | } | |
8355 | ||
8356 | static void bnxt_report_link(struct bnxt *bp) | |
8357 | { | |
8358 | if (bp->link_info.link_up) { | |
8359 | const char *duplex; | |
8360 | const char *flow_ctrl; | |
38a21b34 DK |
8361 | u32 speed; |
8362 | u16 fec; | |
c0c050c5 MC |
8363 | |
8364 | netif_carrier_on(bp->dev); | |
8365 | if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) | |
8366 | duplex = "full"; | |
8367 | else | |
8368 | duplex = "half"; | |
8369 | if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) | |
8370 | flow_ctrl = "ON - receive & transmit"; | |
8371 | else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) | |
8372 | flow_ctrl = "ON - transmit"; | |
8373 | else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) | |
8374 | flow_ctrl = "ON - receive"; | |
8375 | else | |
8376 | flow_ctrl = "none"; | |
8377 | speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); | |
38a21b34 | 8378 | netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", |
c0c050c5 | 8379 | speed, duplex, flow_ctrl); |
170ce013 MC |
8380 | if (bp->flags & BNXT_FLAG_EEE_CAP) |
8381 | netdev_info(bp->dev, "EEE is %s\n", | |
8382 | bp->eee.eee_active ? "active" : | |
8383 | "not active"); | |
e70c752f MC |
8384 | fec = bp->link_info.fec_cfg; |
8385 | if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) | |
8386 | netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", | |
8387 | (fec & BNXT_FEC_AUTONEG) ? "on" : "off", | |
8388 | (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : | |
8389 | (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); | |
c0c050c5 MC |
8390 | } else { |
8391 | netif_carrier_off(bp->dev); | |
8392 | netdev_err(bp->dev, "NIC Link is Down\n"); | |
8393 | } | |
8394 | } | |
8395 | ||
170ce013 MC |
8396 | static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) |
8397 | { | |
8398 | int rc = 0; | |
8399 | struct hwrm_port_phy_qcaps_input req = {0}; | |
8400 | struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
93ed8117 | 8401 | struct bnxt_link_info *link_info = &bp->link_info; |
170ce013 | 8402 | |
ba642ab7 MC |
8403 | bp->flags &= ~BNXT_FLAG_EEE_CAP; |
8404 | if (bp->test_info) | |
8405 | bp->test_info->flags &= ~BNXT_TEST_FL_EXT_LPBK; | |
170ce013 MC |
8406 | if (bp->hwrm_spec_code < 0x10201) |
8407 | return 0; | |
8408 | ||
8409 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); | |
8410 | ||
8411 | mutex_lock(&bp->hwrm_cmd_lock); | |
8412 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8413 | if (rc) | |
8414 | goto hwrm_phy_qcaps_exit; | |
8415 | ||
acb20054 | 8416 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { |
170ce013 MC |
8417 | struct ethtool_eee *eee = &bp->eee; |
8418 | u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); | |
8419 | ||
8420 | bp->flags |= BNXT_FLAG_EEE_CAP; | |
8421 | eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8422 | bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & | |
8423 | PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; | |
8424 | bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & | |
8425 | PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; | |
8426 | } | |
55fd0cf3 MC |
8427 | if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { |
8428 | if (bp->test_info) | |
8429 | bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; | |
8430 | } | |
520ad89a MC |
8431 | if (resp->supported_speeds_auto_mode) |
8432 | link_info->support_auto_speeds = | |
8433 | le16_to_cpu(resp->supported_speeds_auto_mode); | |
170ce013 | 8434 | |
d5430d31 MC |
8435 | bp->port_count = resp->port_cnt; |
8436 | ||
170ce013 MC |
8437 | hwrm_phy_qcaps_exit: |
8438 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8439 | return rc; | |
8440 | } | |
8441 | ||
c0c050c5 MC |
8442 | static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) |
8443 | { | |
8444 | int rc = 0; | |
8445 | struct bnxt_link_info *link_info = &bp->link_info; | |
8446 | struct hwrm_port_phy_qcfg_input req = {0}; | |
8447 | struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
8448 | u8 link_up = link_info->link_up; | |
286ef9d6 | 8449 | u16 diff; |
c0c050c5 MC |
8450 | |
8451 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); | |
8452 | ||
8453 | mutex_lock(&bp->hwrm_cmd_lock); | |
8454 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8455 | if (rc) { | |
8456 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8457 | return rc; | |
8458 | } | |
8459 | ||
8460 | memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); | |
8461 | link_info->phy_link_status = resp->link; | |
acb20054 MC |
8462 | link_info->duplex = resp->duplex_cfg; |
8463 | if (bp->hwrm_spec_code >= 0x10800) | |
8464 | link_info->duplex = resp->duplex_state; | |
c0c050c5 MC |
8465 | link_info->pause = resp->pause; |
8466 | link_info->auto_mode = resp->auto_mode; | |
8467 | link_info->auto_pause_setting = resp->auto_pause; | |
3277360e | 8468 | link_info->lp_pause = resp->link_partner_adv_pause; |
c0c050c5 | 8469 | link_info->force_pause_setting = resp->force_pause; |
acb20054 | 8470 | link_info->duplex_setting = resp->duplex_cfg; |
c0c050c5 MC |
8471 | if (link_info->phy_link_status == BNXT_LINK_LINK) |
8472 | link_info->link_speed = le16_to_cpu(resp->link_speed); | |
8473 | else | |
8474 | link_info->link_speed = 0; | |
8475 | link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); | |
c0c050c5 MC |
8476 | link_info->support_speeds = le16_to_cpu(resp->support_speeds); |
8477 | link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); | |
3277360e MC |
8478 | link_info->lp_auto_link_speeds = |
8479 | le16_to_cpu(resp->link_partner_adv_speeds); | |
c0c050c5 MC |
8480 | link_info->preemphasis = le32_to_cpu(resp->preemphasis); |
8481 | link_info->phy_ver[0] = resp->phy_maj; | |
8482 | link_info->phy_ver[1] = resp->phy_min; | |
8483 | link_info->phy_ver[2] = resp->phy_bld; | |
8484 | link_info->media_type = resp->media_type; | |
03efbec0 | 8485 | link_info->phy_type = resp->phy_type; |
11f15ed3 | 8486 | link_info->transceiver = resp->xcvr_pkg_type; |
170ce013 MC |
8487 | link_info->phy_addr = resp->eee_config_phy_addr & |
8488 | PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; | |
42ee18fe | 8489 | link_info->module_status = resp->module_status; |
170ce013 MC |
8490 | |
8491 | if (bp->flags & BNXT_FLAG_EEE_CAP) { | |
8492 | struct ethtool_eee *eee = &bp->eee; | |
8493 | u16 fw_speeds; | |
8494 | ||
8495 | eee->eee_active = 0; | |
8496 | if (resp->eee_config_phy_addr & | |
8497 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { | |
8498 | eee->eee_active = 1; | |
8499 | fw_speeds = le16_to_cpu( | |
8500 | resp->link_partner_adv_eee_link_speed_mask); | |
8501 | eee->lp_advertised = | |
8502 | _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8503 | } | |
8504 | ||
8505 | /* Pull initial EEE config */ | |
8506 | if (!chng_link_state) { | |
8507 | if (resp->eee_config_phy_addr & | |
8508 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) | |
8509 | eee->eee_enabled = 1; | |
c0c050c5 | 8510 | |
170ce013 MC |
8511 | fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); |
8512 | eee->advertised = | |
8513 | _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); | |
8514 | ||
8515 | if (resp->eee_config_phy_addr & | |
8516 | PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { | |
8517 | __le32 tmr; | |
8518 | ||
8519 | eee->tx_lpi_enabled = 1; | |
8520 | tmr = resp->xcvr_identifier_type_tx_lpi_timer; | |
8521 | eee->tx_lpi_timer = le32_to_cpu(tmr) & | |
8522 | PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; | |
8523 | } | |
8524 | } | |
8525 | } | |
e70c752f MC |
8526 | |
8527 | link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; | |
8528 | if (bp->hwrm_spec_code >= 0x10504) | |
8529 | link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); | |
8530 | ||
c0c050c5 MC |
8531 | /* TODO: need to add more logic to report VF link */ |
8532 | if (chng_link_state) { | |
8533 | if (link_info->phy_link_status == BNXT_LINK_LINK) | |
8534 | link_info->link_up = 1; | |
8535 | else | |
8536 | link_info->link_up = 0; | |
8537 | if (link_up != link_info->link_up) | |
8538 | bnxt_report_link(bp); | |
8539 | } else { | |
8540 | /* alwasy link down if not require to update link state */ | |
8541 | link_info->link_up = 0; | |
8542 | } | |
8543 | mutex_unlock(&bp->hwrm_cmd_lock); | |
286ef9d6 | 8544 | |
dac04907 MC |
8545 | if (!BNXT_SINGLE_PF(bp)) |
8546 | return 0; | |
8547 | ||
286ef9d6 MC |
8548 | diff = link_info->support_auto_speeds ^ link_info->advertising; |
8549 | if ((link_info->support_auto_speeds | diff) != | |
8550 | link_info->support_auto_speeds) { | |
8551 | /* An advertised speed is no longer supported, so we need to | |
0eaa24b9 MC |
8552 | * update the advertisement settings. Caller holds RTNL |
8553 | * so we can modify link settings. | |
286ef9d6 | 8554 | */ |
286ef9d6 | 8555 | link_info->advertising = link_info->support_auto_speeds; |
0eaa24b9 | 8556 | if (link_info->autoneg & BNXT_AUTONEG_SPEED) |
286ef9d6 | 8557 | bnxt_hwrm_set_link_setting(bp, true, false); |
286ef9d6 | 8558 | } |
c0c050c5 MC |
8559 | return 0; |
8560 | } | |
8561 | ||
10289bec MC |
8562 | static void bnxt_get_port_module_status(struct bnxt *bp) |
8563 | { | |
8564 | struct bnxt_link_info *link_info = &bp->link_info; | |
8565 | struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; | |
8566 | u8 module_status; | |
8567 | ||
8568 | if (bnxt_update_link(bp, true)) | |
8569 | return; | |
8570 | ||
8571 | module_status = link_info->module_status; | |
8572 | switch (module_status) { | |
8573 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: | |
8574 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: | |
8575 | case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: | |
8576 | netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", | |
8577 | bp->pf.port_id); | |
8578 | if (bp->hwrm_spec_code >= 0x10201) { | |
8579 | netdev_warn(bp->dev, "Module part number %s\n", | |
8580 | resp->phy_vendor_partnumber); | |
8581 | } | |
8582 | if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) | |
8583 | netdev_warn(bp->dev, "TX is disabled\n"); | |
8584 | if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) | |
8585 | netdev_warn(bp->dev, "SFP+ module is shutdown\n"); | |
8586 | } | |
8587 | } | |
8588 | ||
c0c050c5 MC |
8589 | static void |
8590 | bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) | |
8591 | { | |
8592 | if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { | |
c9ee9516 MC |
8593 | if (bp->hwrm_spec_code >= 0x10201) |
8594 | req->auto_pause = | |
8595 | PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; | |
c0c050c5 MC |
8596 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) |
8597 | req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; | |
8598 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) | |
49b5c7a1 | 8599 | req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; |
c0c050c5 MC |
8600 | req->enables |= |
8601 | cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); | |
8602 | } else { | |
8603 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) | |
8604 | req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; | |
8605 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) | |
8606 | req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; | |
8607 | req->enables |= | |
8608 | cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); | |
c9ee9516 MC |
8609 | if (bp->hwrm_spec_code >= 0x10201) { |
8610 | req->auto_pause = req->force_pause; | |
8611 | req->enables |= cpu_to_le32( | |
8612 | PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); | |
8613 | } | |
c0c050c5 MC |
8614 | } |
8615 | } | |
8616 | ||
8617 | static void bnxt_hwrm_set_link_common(struct bnxt *bp, | |
8618 | struct hwrm_port_phy_cfg_input *req) | |
8619 | { | |
8620 | u8 autoneg = bp->link_info.autoneg; | |
8621 | u16 fw_link_speed = bp->link_info.req_link_speed; | |
68515a18 | 8622 | u16 advertising = bp->link_info.advertising; |
c0c050c5 MC |
8623 | |
8624 | if (autoneg & BNXT_AUTONEG_SPEED) { | |
8625 | req->auto_mode |= | |
11f15ed3 | 8626 | PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; |
c0c050c5 MC |
8627 | |
8628 | req->enables |= cpu_to_le32( | |
8629 | PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); | |
8630 | req->auto_link_speed_mask = cpu_to_le16(advertising); | |
8631 | ||
8632 | req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); | |
8633 | req->flags |= | |
8634 | cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); | |
8635 | } else { | |
8636 | req->force_link_speed = cpu_to_le16(fw_link_speed); | |
8637 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); | |
8638 | } | |
8639 | ||
c0c050c5 MC |
8640 | /* tell chimp that the setting takes effect immediately */ |
8641 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); | |
8642 | } | |
8643 | ||
8644 | int bnxt_hwrm_set_pause(struct bnxt *bp) | |
8645 | { | |
8646 | struct hwrm_port_phy_cfg_input req = {0}; | |
8647 | int rc; | |
8648 | ||
8649 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
8650 | bnxt_hwrm_set_pause_common(bp, &req); | |
8651 | ||
8652 | if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || | |
8653 | bp->link_info.force_link_chng) | |
8654 | bnxt_hwrm_set_link_common(bp, &req); | |
8655 | ||
8656 | mutex_lock(&bp->hwrm_cmd_lock); | |
8657 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8658 | if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { | |
8659 | /* since changing of pause setting doesn't trigger any link | |
8660 | * change event, the driver needs to update the current pause | |
8661 | * result upon successfully return of the phy_cfg command | |
8662 | */ | |
8663 | bp->link_info.pause = | |
8664 | bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; | |
8665 | bp->link_info.auto_pause_setting = 0; | |
8666 | if (!bp->link_info.force_link_chng) | |
8667 | bnxt_report_link(bp); | |
8668 | } | |
8669 | bp->link_info.force_link_chng = false; | |
8670 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8671 | return rc; | |
8672 | } | |
8673 | ||
939f7f0c MC |
8674 | static void bnxt_hwrm_set_eee(struct bnxt *bp, |
8675 | struct hwrm_port_phy_cfg_input *req) | |
8676 | { | |
8677 | struct ethtool_eee *eee = &bp->eee; | |
8678 | ||
8679 | if (eee->eee_enabled) { | |
8680 | u16 eee_speeds; | |
8681 | u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; | |
8682 | ||
8683 | if (eee->tx_lpi_enabled) | |
8684 | flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; | |
8685 | else | |
8686 | flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; | |
8687 | ||
8688 | req->flags |= cpu_to_le32(flags); | |
8689 | eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); | |
8690 | req->eee_link_speed_mask = cpu_to_le16(eee_speeds); | |
8691 | req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); | |
8692 | } else { | |
8693 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); | |
8694 | } | |
8695 | } | |
8696 | ||
8697 | int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) | |
c0c050c5 MC |
8698 | { |
8699 | struct hwrm_port_phy_cfg_input req = {0}; | |
8700 | ||
8701 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
8702 | if (set_pause) | |
8703 | bnxt_hwrm_set_pause_common(bp, &req); | |
8704 | ||
8705 | bnxt_hwrm_set_link_common(bp, &req); | |
939f7f0c MC |
8706 | |
8707 | if (set_eee) | |
8708 | bnxt_hwrm_set_eee(bp, &req); | |
c0c050c5 MC |
8709 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
8710 | } | |
8711 | ||
33f7d55f MC |
8712 | static int bnxt_hwrm_shutdown_link(struct bnxt *bp) |
8713 | { | |
8714 | struct hwrm_port_phy_cfg_input req = {0}; | |
8715 | ||
567b2abe | 8716 | if (!BNXT_SINGLE_PF(bp)) |
33f7d55f MC |
8717 | return 0; |
8718 | ||
8719 | if (pci_num_vf(bp->pdev)) | |
8720 | return 0; | |
8721 | ||
8722 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); | |
16d663a6 | 8723 | req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); |
33f7d55f MC |
8724 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
8725 | } | |
8726 | ||
ec5d31e3 MC |
8727 | static int bnxt_fw_init_one(struct bnxt *bp); |
8728 | ||
25e1acd6 MC |
8729 | static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) |
8730 | { | |
8731 | struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; | |
8732 | struct hwrm_func_drv_if_change_input req = {0}; | |
ec5d31e3 MC |
8733 | bool resc_reinit = false, fw_reset = false; |
8734 | u32 flags = 0; | |
25e1acd6 MC |
8735 | int rc; |
8736 | ||
8737 | if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) | |
8738 | return 0; | |
8739 | ||
8740 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); | |
8741 | if (up) | |
8742 | req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); | |
8743 | mutex_lock(&bp->hwrm_cmd_lock); | |
8744 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
ec5d31e3 MC |
8745 | if (!rc) |
8746 | flags = le32_to_cpu(resp->flags); | |
25e1acd6 | 8747 | mutex_unlock(&bp->hwrm_cmd_lock); |
ec5d31e3 MC |
8748 | if (rc) |
8749 | return rc; | |
25e1acd6 | 8750 | |
ec5d31e3 MC |
8751 | if (!up) |
8752 | return 0; | |
25e1acd6 | 8753 | |
ec5d31e3 MC |
8754 | if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) |
8755 | resc_reinit = true; | |
8756 | if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE) | |
8757 | fw_reset = true; | |
8758 | ||
3bc7d4a3 MC |
8759 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { |
8760 | netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); | |
8761 | return -ENODEV; | |
8762 | } | |
ec5d31e3 MC |
8763 | if (resc_reinit || fw_reset) { |
8764 | if (fw_reset) { | |
f3a6d206 VV |
8765 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) |
8766 | bnxt_ulp_stop(bp); | |
ec5d31e3 MC |
8767 | rc = bnxt_fw_init_one(bp); |
8768 | if (rc) { | |
8769 | set_bit(BNXT_STATE_ABORT_ERR, &bp->state); | |
8770 | return rc; | |
8771 | } | |
8772 | bnxt_clear_int_mode(bp); | |
8773 | rc = bnxt_init_int_mode(bp); | |
8774 | if (rc) { | |
8775 | netdev_err(bp->dev, "init int mode failed\n"); | |
8776 | return rc; | |
8777 | } | |
8778 | set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); | |
8779 | } | |
8780 | if (BNXT_NEW_RM(bp)) { | |
8781 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; | |
8782 | ||
8783 | rc = bnxt_hwrm_func_resc_qcaps(bp, true); | |
8784 | hw_resc->resv_cp_rings = 0; | |
8785 | hw_resc->resv_stat_ctxs = 0; | |
8786 | hw_resc->resv_irqs = 0; | |
8787 | hw_resc->resv_tx_rings = 0; | |
8788 | hw_resc->resv_rx_rings = 0; | |
8789 | hw_resc->resv_hw_ring_grps = 0; | |
8790 | hw_resc->resv_vnics = 0; | |
8791 | if (!fw_reset) { | |
8792 | bp->tx_nr_rings = 0; | |
8793 | bp->rx_nr_rings = 0; | |
8794 | } | |
8795 | } | |
25e1acd6 | 8796 | } |
ec5d31e3 | 8797 | return 0; |
25e1acd6 MC |
8798 | } |
8799 | ||
5ad2cbee MC |
8800 | static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) |
8801 | { | |
8802 | struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; | |
8803 | struct hwrm_port_led_qcaps_input req = {0}; | |
8804 | struct bnxt_pf_info *pf = &bp->pf; | |
8805 | int rc; | |
8806 | ||
ba642ab7 | 8807 | bp->num_leds = 0; |
5ad2cbee MC |
8808 | if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) |
8809 | return 0; | |
8810 | ||
8811 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); | |
8812 | req.port_id = cpu_to_le16(pf->port_id); | |
8813 | mutex_lock(&bp->hwrm_cmd_lock); | |
8814 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8815 | if (rc) { | |
8816 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8817 | return rc; | |
8818 | } | |
8819 | if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { | |
8820 | int i; | |
8821 | ||
8822 | bp->num_leds = resp->num_leds; | |
8823 | memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * | |
8824 | bp->num_leds); | |
8825 | for (i = 0; i < bp->num_leds; i++) { | |
8826 | struct bnxt_led_info *led = &bp->leds[i]; | |
8827 | __le16 caps = led->led_state_caps; | |
8828 | ||
8829 | if (!led->led_group_id || | |
8830 | !BNXT_LED_ALT_BLINK_CAP(caps)) { | |
8831 | bp->num_leds = 0; | |
8832 | break; | |
8833 | } | |
8834 | } | |
8835 | } | |
8836 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8837 | return 0; | |
8838 | } | |
8839 | ||
5282db6c MC |
8840 | int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) |
8841 | { | |
8842 | struct hwrm_wol_filter_alloc_input req = {0}; | |
8843 | struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; | |
8844 | int rc; | |
8845 | ||
8846 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); | |
8847 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
8848 | req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; | |
8849 | req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); | |
8850 | memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); | |
8851 | mutex_lock(&bp->hwrm_cmd_lock); | |
8852 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8853 | if (!rc) | |
8854 | bp->wol_filter_id = resp->wol_filter_id; | |
8855 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8856 | return rc; | |
8857 | } | |
8858 | ||
8859 | int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) | |
8860 | { | |
8861 | struct hwrm_wol_filter_free_input req = {0}; | |
8862 | int rc; | |
8863 | ||
8864 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); | |
8865 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
8866 | req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); | |
8867 | req.wol_filter_id = bp->wol_filter_id; | |
8868 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8869 | return rc; | |
8870 | } | |
8871 | ||
c1ef146a MC |
8872 | static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) |
8873 | { | |
8874 | struct hwrm_wol_filter_qcfg_input req = {0}; | |
8875 | struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
8876 | u16 next_handle = 0; | |
8877 | int rc; | |
8878 | ||
8879 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); | |
8880 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
8881 | req.handle = cpu_to_le16(handle); | |
8882 | mutex_lock(&bp->hwrm_cmd_lock); | |
8883 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
8884 | if (!rc) { | |
8885 | next_handle = le16_to_cpu(resp->next_handle); | |
8886 | if (next_handle != 0) { | |
8887 | if (resp->wol_type == | |
8888 | WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { | |
8889 | bp->wol = 1; | |
8890 | bp->wol_filter_id = resp->wol_filter_id; | |
8891 | } | |
8892 | } | |
8893 | } | |
8894 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8895 | return next_handle; | |
8896 | } | |
8897 | ||
8898 | static void bnxt_get_wol_settings(struct bnxt *bp) | |
8899 | { | |
8900 | u16 handle = 0; | |
8901 | ||
ba642ab7 | 8902 | bp->wol = 0; |
c1ef146a MC |
8903 | if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) |
8904 | return; | |
8905 | ||
8906 | do { | |
8907 | handle = bnxt_hwrm_get_wol_fltrs(bp, handle); | |
8908 | } while (handle && handle != 0xffff); | |
8909 | } | |
8910 | ||
cde49a42 VV |
8911 | #ifdef CONFIG_BNXT_HWMON |
8912 | static ssize_t bnxt_show_temp(struct device *dev, | |
8913 | struct device_attribute *devattr, char *buf) | |
8914 | { | |
8915 | struct hwrm_temp_monitor_query_input req = {0}; | |
8916 | struct hwrm_temp_monitor_query_output *resp; | |
8917 | struct bnxt *bp = dev_get_drvdata(dev); | |
8918 | u32 temp = 0; | |
8919 | ||
8920 | resp = bp->hwrm_cmd_resp_addr; | |
8921 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); | |
8922 | mutex_lock(&bp->hwrm_cmd_lock); | |
8923 | if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) | |
8924 | temp = resp->temp * 1000; /* display millidegree */ | |
8925 | mutex_unlock(&bp->hwrm_cmd_lock); | |
8926 | ||
8927 | return sprintf(buf, "%u\n", temp); | |
8928 | } | |
8929 | static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); | |
8930 | ||
8931 | static struct attribute *bnxt_attrs[] = { | |
8932 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
8933 | NULL | |
8934 | }; | |
8935 | ATTRIBUTE_GROUPS(bnxt); | |
8936 | ||
8937 | static void bnxt_hwmon_close(struct bnxt *bp) | |
8938 | { | |
8939 | if (bp->hwmon_dev) { | |
8940 | hwmon_device_unregister(bp->hwmon_dev); | |
8941 | bp->hwmon_dev = NULL; | |
8942 | } | |
8943 | } | |
8944 | ||
8945 | static void bnxt_hwmon_open(struct bnxt *bp) | |
8946 | { | |
8947 | struct pci_dev *pdev = bp->pdev; | |
8948 | ||
ba642ab7 MC |
8949 | if (bp->hwmon_dev) |
8950 | return; | |
8951 | ||
cde49a42 VV |
8952 | bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, |
8953 | DRV_MODULE_NAME, bp, | |
8954 | bnxt_groups); | |
8955 | if (IS_ERR(bp->hwmon_dev)) { | |
8956 | bp->hwmon_dev = NULL; | |
8957 | dev_warn(&pdev->dev, "Cannot register hwmon device\n"); | |
8958 | } | |
8959 | } | |
8960 | #else | |
8961 | static void bnxt_hwmon_close(struct bnxt *bp) | |
8962 | { | |
8963 | } | |
8964 | ||
8965 | static void bnxt_hwmon_open(struct bnxt *bp) | |
8966 | { | |
8967 | } | |
8968 | #endif | |
8969 | ||
939f7f0c MC |
8970 | static bool bnxt_eee_config_ok(struct bnxt *bp) |
8971 | { | |
8972 | struct ethtool_eee *eee = &bp->eee; | |
8973 | struct bnxt_link_info *link_info = &bp->link_info; | |
8974 | ||
8975 | if (!(bp->flags & BNXT_FLAG_EEE_CAP)) | |
8976 | return true; | |
8977 | ||
8978 | if (eee->eee_enabled) { | |
8979 | u32 advertising = | |
8980 | _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); | |
8981 | ||
8982 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { | |
8983 | eee->eee_enabled = 0; | |
8984 | return false; | |
8985 | } | |
8986 | if (eee->advertised & ~advertising) { | |
8987 | eee->advertised = advertising & eee->supported; | |
8988 | return false; | |
8989 | } | |
8990 | } | |
8991 | return true; | |
8992 | } | |
8993 | ||
c0c050c5 MC |
8994 | static int bnxt_update_phy_setting(struct bnxt *bp) |
8995 | { | |
8996 | int rc; | |
8997 | bool update_link = false; | |
8998 | bool update_pause = false; | |
939f7f0c | 8999 | bool update_eee = false; |
c0c050c5 MC |
9000 | struct bnxt_link_info *link_info = &bp->link_info; |
9001 | ||
9002 | rc = bnxt_update_link(bp, true); | |
9003 | if (rc) { | |
9004 | netdev_err(bp->dev, "failed to update link (rc: %x)\n", | |
9005 | rc); | |
9006 | return rc; | |
9007 | } | |
33dac24a MC |
9008 | if (!BNXT_SINGLE_PF(bp)) |
9009 | return 0; | |
9010 | ||
c0c050c5 | 9011 | if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && |
c9ee9516 MC |
9012 | (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != |
9013 | link_info->req_flow_ctrl) | |
c0c050c5 MC |
9014 | update_pause = true; |
9015 | if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && | |
9016 | link_info->force_pause_setting != link_info->req_flow_ctrl) | |
9017 | update_pause = true; | |
c0c050c5 MC |
9018 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { |
9019 | if (BNXT_AUTO_MODE(link_info->auto_mode)) | |
9020 | update_link = true; | |
9021 | if (link_info->req_link_speed != link_info->force_link_speed) | |
9022 | update_link = true; | |
de73018f MC |
9023 | if (link_info->req_duplex != link_info->duplex_setting) |
9024 | update_link = true; | |
c0c050c5 MC |
9025 | } else { |
9026 | if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) | |
9027 | update_link = true; | |
9028 | if (link_info->advertising != link_info->auto_link_speeds) | |
9029 | update_link = true; | |
c0c050c5 MC |
9030 | } |
9031 | ||
16d663a6 MC |
9032 | /* The last close may have shutdown the link, so need to call |
9033 | * PHY_CFG to bring it back up. | |
9034 | */ | |
9035 | if (!netif_carrier_ok(bp->dev)) | |
9036 | update_link = true; | |
9037 | ||
939f7f0c MC |
9038 | if (!bnxt_eee_config_ok(bp)) |
9039 | update_eee = true; | |
9040 | ||
c0c050c5 | 9041 | if (update_link) |
939f7f0c | 9042 | rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); |
c0c050c5 MC |
9043 | else if (update_pause) |
9044 | rc = bnxt_hwrm_set_pause(bp); | |
9045 | if (rc) { | |
9046 | netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", | |
9047 | rc); | |
9048 | return rc; | |
9049 | } | |
9050 | ||
9051 | return rc; | |
9052 | } | |
9053 | ||
11809490 JH |
9054 | /* Common routine to pre-map certain register block to different GRC window. |
9055 | * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows | |
9056 | * in PF and 3 windows in VF that can be customized to map in different | |
9057 | * register blocks. | |
9058 | */ | |
9059 | static void bnxt_preset_reg_win(struct bnxt *bp) | |
9060 | { | |
9061 | if (BNXT_PF(bp)) { | |
9062 | /* CAG registers map to GRC window #4 */ | |
9063 | writel(BNXT_CAG_REG_BASE, | |
9064 | bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); | |
9065 | } | |
9066 | } | |
9067 | ||
47558acd MC |
9068 | static int bnxt_init_dflt_ring_mode(struct bnxt *bp); |
9069 | ||
c0c050c5 MC |
9070 | static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) |
9071 | { | |
9072 | int rc = 0; | |
9073 | ||
11809490 | 9074 | bnxt_preset_reg_win(bp); |
c0c050c5 MC |
9075 | netif_carrier_off(bp->dev); |
9076 | if (irq_re_init) { | |
47558acd MC |
9077 | /* Reserve rings now if none were reserved at driver probe. */ |
9078 | rc = bnxt_init_dflt_ring_mode(bp); | |
9079 | if (rc) { | |
9080 | netdev_err(bp->dev, "Failed to reserve default rings at open\n"); | |
9081 | return rc; | |
9082 | } | |
c0c050c5 | 9083 | } |
1b3f0b75 | 9084 | rc = bnxt_reserve_rings(bp, irq_re_init); |
41e8d798 MC |
9085 | if (rc) |
9086 | return rc; | |
c0c050c5 MC |
9087 | if ((bp->flags & BNXT_FLAG_RFS) && |
9088 | !(bp->flags & BNXT_FLAG_USING_MSIX)) { | |
9089 | /* disable RFS if falling back to INTA */ | |
9090 | bp->dev->hw_features &= ~NETIF_F_NTUPLE; | |
9091 | bp->flags &= ~BNXT_FLAG_RFS; | |
9092 | } | |
9093 | ||
9094 | rc = bnxt_alloc_mem(bp, irq_re_init); | |
9095 | if (rc) { | |
9096 | netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); | |
9097 | goto open_err_free_mem; | |
9098 | } | |
9099 | ||
9100 | if (irq_re_init) { | |
9101 | bnxt_init_napi(bp); | |
9102 | rc = bnxt_request_irq(bp); | |
9103 | if (rc) { | |
9104 | netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); | |
c58387ab | 9105 | goto open_err_irq; |
c0c050c5 MC |
9106 | } |
9107 | } | |
9108 | ||
9109 | bnxt_enable_napi(bp); | |
cabfb09d | 9110 | bnxt_debug_dev_init(bp); |
c0c050c5 MC |
9111 | |
9112 | rc = bnxt_init_nic(bp, irq_re_init); | |
9113 | if (rc) { | |
9114 | netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); | |
9115 | goto open_err; | |
9116 | } | |
9117 | ||
9118 | if (link_re_init) { | |
e2dc9b6e | 9119 | mutex_lock(&bp->link_lock); |
c0c050c5 | 9120 | rc = bnxt_update_phy_setting(bp); |
e2dc9b6e | 9121 | mutex_unlock(&bp->link_lock); |
a1ef4a79 | 9122 | if (rc) { |
ba41d46f | 9123 | netdev_warn(bp->dev, "failed to update phy settings\n"); |
a1ef4a79 MC |
9124 | if (BNXT_SINGLE_PF(bp)) { |
9125 | bp->link_info.phy_retry = true; | |
9126 | bp->link_info.phy_retry_expires = | |
9127 | jiffies + 5 * HZ; | |
9128 | } | |
9129 | } | |
c0c050c5 MC |
9130 | } |
9131 | ||
7cdd5fc3 | 9132 | if (irq_re_init) |
ad51b8e9 | 9133 | udp_tunnel_get_rx_info(bp->dev); |
c0c050c5 | 9134 | |
caefe526 | 9135 | set_bit(BNXT_STATE_OPEN, &bp->state); |
c0c050c5 MC |
9136 | bnxt_enable_int(bp); |
9137 | /* Enable TX queues */ | |
9138 | bnxt_tx_enable(bp); | |
9139 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
10289bec MC |
9140 | /* Poll link status and check for SFP+ module status */ |
9141 | bnxt_get_port_module_status(bp); | |
c0c050c5 | 9142 | |
ee5c7fb3 SP |
9143 | /* VF-reps may need to be re-opened after the PF is re-opened */ |
9144 | if (BNXT_PF(bp)) | |
9145 | bnxt_vf_reps_open(bp); | |
c0c050c5 MC |
9146 | return 0; |
9147 | ||
9148 | open_err: | |
cabfb09d | 9149 | bnxt_debug_dev_exit(bp); |
c0c050c5 | 9150 | bnxt_disable_napi(bp); |
c58387ab VG |
9151 | |
9152 | open_err_irq: | |
c0c050c5 MC |
9153 | bnxt_del_napi(bp); |
9154 | ||
9155 | open_err_free_mem: | |
9156 | bnxt_free_skbs(bp); | |
9157 | bnxt_free_irq(bp); | |
9158 | bnxt_free_mem(bp, true); | |
9159 | return rc; | |
9160 | } | |
9161 | ||
9162 | /* rtnl_lock held */ | |
9163 | int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) | |
9164 | { | |
9165 | int rc = 0; | |
9166 | ||
9167 | rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); | |
9168 | if (rc) { | |
9169 | netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); | |
9170 | dev_close(bp->dev); | |
9171 | } | |
9172 | return rc; | |
9173 | } | |
9174 | ||
f7dc1ea6 MC |
9175 | /* rtnl_lock held, open the NIC half way by allocating all resources, but |
9176 | * NAPI, IRQ, and TX are not enabled. This is mainly used for offline | |
9177 | * self tests. | |
9178 | */ | |
9179 | int bnxt_half_open_nic(struct bnxt *bp) | |
9180 | { | |
9181 | int rc = 0; | |
9182 | ||
9183 | rc = bnxt_alloc_mem(bp, false); | |
9184 | if (rc) { | |
9185 | netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); | |
9186 | goto half_open_err; | |
9187 | } | |
9188 | rc = bnxt_init_nic(bp, false); | |
9189 | if (rc) { | |
9190 | netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); | |
9191 | goto half_open_err; | |
9192 | } | |
9193 | return 0; | |
9194 | ||
9195 | half_open_err: | |
9196 | bnxt_free_skbs(bp); | |
9197 | bnxt_free_mem(bp, false); | |
9198 | dev_close(bp->dev); | |
9199 | return rc; | |
9200 | } | |
9201 | ||
9202 | /* rtnl_lock held, this call can only be made after a previous successful | |
9203 | * call to bnxt_half_open_nic(). | |
9204 | */ | |
9205 | void bnxt_half_close_nic(struct bnxt *bp) | |
9206 | { | |
9207 | bnxt_hwrm_resource_free(bp, false, false); | |
9208 | bnxt_free_skbs(bp); | |
9209 | bnxt_free_mem(bp, false); | |
9210 | } | |
9211 | ||
c0c050c5 MC |
9212 | static int bnxt_open(struct net_device *dev) |
9213 | { | |
9214 | struct bnxt *bp = netdev_priv(dev); | |
25e1acd6 | 9215 | int rc; |
c0c050c5 | 9216 | |
ec5d31e3 MC |
9217 | if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { |
9218 | netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n"); | |
9219 | return -ENODEV; | |
9220 | } | |
9221 | ||
9222 | rc = bnxt_hwrm_if_change(bp, true); | |
25e1acd6 | 9223 | if (rc) |
ec5d31e3 MC |
9224 | return rc; |
9225 | rc = __bnxt_open_nic(bp, true, true); | |
9226 | if (rc) { | |
25e1acd6 | 9227 | bnxt_hwrm_if_change(bp, false); |
ec5d31e3 | 9228 | } else { |
f3a6d206 VV |
9229 | if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { |
9230 | if (BNXT_PF(bp)) { | |
9231 | struct bnxt_pf_info *pf = &bp->pf; | |
9232 | int n = pf->active_vfs; | |
cde49a42 | 9233 | |
f3a6d206 VV |
9234 | if (n) |
9235 | bnxt_cfg_hw_sriov(bp, &n, true); | |
9236 | } | |
9237 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) | |
9238 | bnxt_ulp_start(bp, 0); | |
ec5d31e3 MC |
9239 | } |
9240 | bnxt_hwmon_open(bp); | |
9241 | } | |
cde49a42 | 9242 | |
25e1acd6 | 9243 | return rc; |
c0c050c5 MC |
9244 | } |
9245 | ||
f9b76ebd MC |
9246 | static bool bnxt_drv_busy(struct bnxt *bp) |
9247 | { | |
9248 | return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || | |
9249 | test_bit(BNXT_STATE_READ_STATS, &bp->state)); | |
9250 | } | |
9251 | ||
b8875ca3 MC |
9252 | static void bnxt_get_ring_stats(struct bnxt *bp, |
9253 | struct rtnl_link_stats64 *stats); | |
9254 | ||
86e953db MC |
9255 | static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, |
9256 | bool link_re_init) | |
c0c050c5 | 9257 | { |
ee5c7fb3 SP |
9258 | /* Close the VF-reps before closing PF */ |
9259 | if (BNXT_PF(bp)) | |
9260 | bnxt_vf_reps_close(bp); | |
86e953db | 9261 | |
c0c050c5 MC |
9262 | /* Change device state to avoid TX queue wake up's */ |
9263 | bnxt_tx_disable(bp); | |
9264 | ||
caefe526 | 9265 | clear_bit(BNXT_STATE_OPEN, &bp->state); |
4cebdcec | 9266 | smp_mb__after_atomic(); |
f9b76ebd | 9267 | while (bnxt_drv_busy(bp)) |
4cebdcec | 9268 | msleep(20); |
c0c050c5 | 9269 | |
9d8bc097 | 9270 | /* Flush rings and and disable interrupts */ |
c0c050c5 MC |
9271 | bnxt_shutdown_nic(bp, irq_re_init); |
9272 | ||
9273 | /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ | |
9274 | ||
cabfb09d | 9275 | bnxt_debug_dev_exit(bp); |
c0c050c5 | 9276 | bnxt_disable_napi(bp); |
c0c050c5 | 9277 | del_timer_sync(&bp->timer); |
3bc7d4a3 MC |
9278 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && |
9279 | pci_is_enabled(bp->pdev)) | |
9280 | pci_disable_device(bp->pdev); | |
9281 | ||
c0c050c5 MC |
9282 | bnxt_free_skbs(bp); |
9283 | ||
b8875ca3 MC |
9284 | /* Save ring stats before shutdown */ |
9285 | if (bp->bnapi) | |
9286 | bnxt_get_ring_stats(bp, &bp->net_stats_prev); | |
c0c050c5 MC |
9287 | if (irq_re_init) { |
9288 | bnxt_free_irq(bp); | |
9289 | bnxt_del_napi(bp); | |
9290 | } | |
9291 | bnxt_free_mem(bp, irq_re_init); | |
86e953db MC |
9292 | } |
9293 | ||
9294 | int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) | |
9295 | { | |
9296 | int rc = 0; | |
9297 | ||
3bc7d4a3 MC |
9298 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { |
9299 | /* If we get here, it means firmware reset is in progress | |
9300 | * while we are trying to close. We can safely proceed with | |
9301 | * the close because we are holding rtnl_lock(). Some firmware | |
9302 | * messages may fail as we proceed to close. We set the | |
9303 | * ABORT_ERR flag here so that the FW reset thread will later | |
9304 | * abort when it gets the rtnl_lock() and sees the flag. | |
9305 | */ | |
9306 | netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); | |
9307 | set_bit(BNXT_STATE_ABORT_ERR, &bp->state); | |
9308 | } | |
9309 | ||
86e953db MC |
9310 | #ifdef CONFIG_BNXT_SRIOV |
9311 | if (bp->sriov_cfg) { | |
9312 | rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, | |
9313 | !bp->sriov_cfg, | |
9314 | BNXT_SRIOV_CFG_WAIT_TMO); | |
9315 | if (rc) | |
9316 | netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); | |
9317 | } | |
9318 | #endif | |
9319 | __bnxt_close_nic(bp, irq_re_init, link_re_init); | |
c0c050c5 MC |
9320 | return rc; |
9321 | } | |
9322 | ||
9323 | static int bnxt_close(struct net_device *dev) | |
9324 | { | |
9325 | struct bnxt *bp = netdev_priv(dev); | |
9326 | ||
cde49a42 | 9327 | bnxt_hwmon_close(bp); |
c0c050c5 | 9328 | bnxt_close_nic(bp, true, true); |
33f7d55f | 9329 | bnxt_hwrm_shutdown_link(bp); |
25e1acd6 | 9330 | bnxt_hwrm_if_change(bp, false); |
c0c050c5 MC |
9331 | return 0; |
9332 | } | |
9333 | ||
0ca12be9 VV |
9334 | static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, |
9335 | u16 *val) | |
9336 | { | |
9337 | struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; | |
9338 | struct hwrm_port_phy_mdio_read_input req = {0}; | |
9339 | int rc; | |
9340 | ||
9341 | if (bp->hwrm_spec_code < 0x10a00) | |
9342 | return -EOPNOTSUPP; | |
9343 | ||
9344 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); | |
9345 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9346 | req.phy_addr = phy_addr; | |
9347 | req.reg_addr = cpu_to_le16(reg & 0x1f); | |
2730214d | 9348 | if (mdio_phy_id_is_c45(phy_addr)) { |
0ca12be9 VV |
9349 | req.cl45_mdio = 1; |
9350 | req.phy_addr = mdio_phy_id_prtad(phy_addr); | |
9351 | req.dev_addr = mdio_phy_id_devad(phy_addr); | |
9352 | req.reg_addr = cpu_to_le16(reg); | |
9353 | } | |
9354 | ||
9355 | mutex_lock(&bp->hwrm_cmd_lock); | |
9356 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9357 | if (!rc) | |
9358 | *val = le16_to_cpu(resp->reg_data); | |
9359 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9360 | return rc; | |
9361 | } | |
9362 | ||
9363 | static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, | |
9364 | u16 val) | |
9365 | { | |
9366 | struct hwrm_port_phy_mdio_write_input req = {0}; | |
9367 | ||
9368 | if (bp->hwrm_spec_code < 0x10a00) | |
9369 | return -EOPNOTSUPP; | |
9370 | ||
9371 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); | |
9372 | req.port_id = cpu_to_le16(bp->pf.port_id); | |
9373 | req.phy_addr = phy_addr; | |
9374 | req.reg_addr = cpu_to_le16(reg & 0x1f); | |
2730214d | 9375 | if (mdio_phy_id_is_c45(phy_addr)) { |
0ca12be9 VV |
9376 | req.cl45_mdio = 1; |
9377 | req.phy_addr = mdio_phy_id_prtad(phy_addr); | |
9378 | req.dev_addr = mdio_phy_id_devad(phy_addr); | |
9379 | req.reg_addr = cpu_to_le16(reg); | |
9380 | } | |
9381 | req.reg_data = cpu_to_le16(val); | |
9382 | ||
9383 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9384 | } | |
9385 | ||
c0c050c5 MC |
9386 | /* rtnl_lock held */ |
9387 | static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
9388 | { | |
0ca12be9 VV |
9389 | struct mii_ioctl_data *mdio = if_mii(ifr); |
9390 | struct bnxt *bp = netdev_priv(dev); | |
9391 | int rc; | |
9392 | ||
c0c050c5 MC |
9393 | switch (cmd) { |
9394 | case SIOCGMIIPHY: | |
0ca12be9 VV |
9395 | mdio->phy_id = bp->link_info.phy_addr; |
9396 | ||
c0c050c5 MC |
9397 | /* fallthru */ |
9398 | case SIOCGMIIREG: { | |
0ca12be9 VV |
9399 | u16 mii_regval = 0; |
9400 | ||
c0c050c5 MC |
9401 | if (!netif_running(dev)) |
9402 | return -EAGAIN; | |
9403 | ||
0ca12be9 VV |
9404 | rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, |
9405 | &mii_regval); | |
9406 | mdio->val_out = mii_regval; | |
9407 | return rc; | |
c0c050c5 MC |
9408 | } |
9409 | ||
9410 | case SIOCSMIIREG: | |
9411 | if (!netif_running(dev)) | |
9412 | return -EAGAIN; | |
9413 | ||
0ca12be9 VV |
9414 | return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, |
9415 | mdio->val_in); | |
c0c050c5 MC |
9416 | |
9417 | default: | |
9418 | /* do nothing */ | |
9419 | break; | |
9420 | } | |
9421 | return -EOPNOTSUPP; | |
9422 | } | |
9423 | ||
b8875ca3 MC |
9424 | static void bnxt_get_ring_stats(struct bnxt *bp, |
9425 | struct rtnl_link_stats64 *stats) | |
c0c050c5 | 9426 | { |
b8875ca3 | 9427 | int i; |
c0c050c5 | 9428 | |
c0c050c5 | 9429 | |
c0c050c5 MC |
9430 | for (i = 0; i < bp->cp_nr_rings; i++) { |
9431 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
9432 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
9433 | struct ctx_hw_stats *hw_stats = cpr->hw_stats; | |
9434 | ||
9435 | stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); | |
9436 | stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); | |
9437 | stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); | |
9438 | ||
9439 | stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); | |
9440 | stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); | |
9441 | stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); | |
9442 | ||
9443 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); | |
9444 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); | |
9445 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); | |
9446 | ||
9447 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); | |
9448 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); | |
9449 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); | |
9450 | ||
9451 | stats->rx_missed_errors += | |
9452 | le64_to_cpu(hw_stats->rx_discard_pkts); | |
9453 | ||
9454 | stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); | |
9455 | ||
c0c050c5 MC |
9456 | stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); |
9457 | } | |
b8875ca3 MC |
9458 | } |
9459 | ||
9460 | static void bnxt_add_prev_stats(struct bnxt *bp, | |
9461 | struct rtnl_link_stats64 *stats) | |
9462 | { | |
9463 | struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; | |
9464 | ||
9465 | stats->rx_packets += prev_stats->rx_packets; | |
9466 | stats->tx_packets += prev_stats->tx_packets; | |
9467 | stats->rx_bytes += prev_stats->rx_bytes; | |
9468 | stats->tx_bytes += prev_stats->tx_bytes; | |
9469 | stats->rx_missed_errors += prev_stats->rx_missed_errors; | |
9470 | stats->multicast += prev_stats->multicast; | |
9471 | stats->tx_dropped += prev_stats->tx_dropped; | |
9472 | } | |
9473 | ||
9474 | static void | |
9475 | bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
9476 | { | |
9477 | struct bnxt *bp = netdev_priv(dev); | |
9478 | ||
9479 | set_bit(BNXT_STATE_READ_STATS, &bp->state); | |
9480 | /* Make sure bnxt_close_nic() sees that we are reading stats before | |
9481 | * we check the BNXT_STATE_OPEN flag. | |
9482 | */ | |
9483 | smp_mb__after_atomic(); | |
9484 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { | |
9485 | clear_bit(BNXT_STATE_READ_STATS, &bp->state); | |
9486 | *stats = bp->net_stats_prev; | |
9487 | return; | |
9488 | } | |
9489 | ||
9490 | bnxt_get_ring_stats(bp, stats); | |
9491 | bnxt_add_prev_stats(bp, stats); | |
c0c050c5 | 9492 | |
9947f83f MC |
9493 | if (bp->flags & BNXT_FLAG_PORT_STATS) { |
9494 | struct rx_port_stats *rx = bp->hw_rx_port_stats; | |
9495 | struct tx_port_stats *tx = bp->hw_tx_port_stats; | |
9496 | ||
9497 | stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); | |
9498 | stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); | |
9499 | stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + | |
9500 | le64_to_cpu(rx->rx_ovrsz_frames) + | |
9501 | le64_to_cpu(rx->rx_runt_frames); | |
9502 | stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + | |
9503 | le64_to_cpu(rx->rx_jbr_frames); | |
9504 | stats->collisions = le64_to_cpu(tx->tx_total_collisions); | |
9505 | stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); | |
9506 | stats->tx_errors = le64_to_cpu(tx->tx_err); | |
9507 | } | |
f9b76ebd | 9508 | clear_bit(BNXT_STATE_READ_STATS, &bp->state); |
c0c050c5 MC |
9509 | } |
9510 | ||
9511 | static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) | |
9512 | { | |
9513 | struct net_device *dev = bp->dev; | |
9514 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9515 | struct netdev_hw_addr *ha; | |
9516 | u8 *haddr; | |
9517 | int mc_count = 0; | |
9518 | bool update = false; | |
9519 | int off = 0; | |
9520 | ||
9521 | netdev_for_each_mc_addr(ha, dev) { | |
9522 | if (mc_count >= BNXT_MAX_MC_ADDRS) { | |
9523 | *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9524 | vnic->mc_list_count = 0; | |
9525 | return false; | |
9526 | } | |
9527 | haddr = ha->addr; | |
9528 | if (!ether_addr_equal(haddr, vnic->mc_list + off)) { | |
9529 | memcpy(vnic->mc_list + off, haddr, ETH_ALEN); | |
9530 | update = true; | |
9531 | } | |
9532 | off += ETH_ALEN; | |
9533 | mc_count++; | |
9534 | } | |
9535 | if (mc_count) | |
9536 | *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; | |
9537 | ||
9538 | if (mc_count != vnic->mc_list_count) { | |
9539 | vnic->mc_list_count = mc_count; | |
9540 | update = true; | |
9541 | } | |
9542 | return update; | |
9543 | } | |
9544 | ||
9545 | static bool bnxt_uc_list_updated(struct bnxt *bp) | |
9546 | { | |
9547 | struct net_device *dev = bp->dev; | |
9548 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9549 | struct netdev_hw_addr *ha; | |
9550 | int off = 0; | |
9551 | ||
9552 | if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) | |
9553 | return true; | |
9554 | ||
9555 | netdev_for_each_uc_addr(ha, dev) { | |
9556 | if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) | |
9557 | return true; | |
9558 | ||
9559 | off += ETH_ALEN; | |
9560 | } | |
9561 | return false; | |
9562 | } | |
9563 | ||
9564 | static void bnxt_set_rx_mode(struct net_device *dev) | |
9565 | { | |
9566 | struct bnxt *bp = netdev_priv(dev); | |
268d0895 | 9567 | struct bnxt_vnic_info *vnic; |
c0c050c5 MC |
9568 | bool mc_update = false; |
9569 | bool uc_update; | |
268d0895 | 9570 | u32 mask; |
c0c050c5 | 9571 | |
268d0895 | 9572 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) |
c0c050c5 MC |
9573 | return; |
9574 | ||
268d0895 MC |
9575 | vnic = &bp->vnic_info[0]; |
9576 | mask = vnic->rx_mask; | |
c0c050c5 MC |
9577 | mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | |
9578 | CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | | |
30e33848 MC |
9579 | CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | |
9580 | CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); | |
c0c050c5 | 9581 | |
17c71ac3 | 9582 | if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) |
c0c050c5 MC |
9583 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
9584 | ||
9585 | uc_update = bnxt_uc_list_updated(bp); | |
9586 | ||
30e33848 MC |
9587 | if (dev->flags & IFF_BROADCAST) |
9588 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; | |
c0c050c5 MC |
9589 | if (dev->flags & IFF_ALLMULTI) { |
9590 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9591 | vnic->mc_list_count = 0; | |
9592 | } else { | |
9593 | mc_update = bnxt_mc_list_updated(bp, &mask); | |
9594 | } | |
9595 | ||
9596 | if (mask != vnic->rx_mask || uc_update || mc_update) { | |
9597 | vnic->rx_mask = mask; | |
9598 | ||
9599 | set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 9600 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
9601 | } |
9602 | } | |
9603 | ||
b664f008 | 9604 | static int bnxt_cfg_rx_mode(struct bnxt *bp) |
c0c050c5 MC |
9605 | { |
9606 | struct net_device *dev = bp->dev; | |
9607 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
9608 | struct netdev_hw_addr *ha; | |
9609 | int i, off = 0, rc; | |
9610 | bool uc_update; | |
9611 | ||
9612 | netif_addr_lock_bh(dev); | |
9613 | uc_update = bnxt_uc_list_updated(bp); | |
9614 | netif_addr_unlock_bh(dev); | |
9615 | ||
9616 | if (!uc_update) | |
9617 | goto skip_uc; | |
9618 | ||
9619 | mutex_lock(&bp->hwrm_cmd_lock); | |
9620 | for (i = 1; i < vnic->uc_filter_count; i++) { | |
9621 | struct hwrm_cfa_l2_filter_free_input req = {0}; | |
9622 | ||
9623 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, | |
9624 | -1); | |
9625 | ||
9626 | req.l2_filter_id = vnic->fw_l2_filter_id[i]; | |
9627 | ||
9628 | rc = _hwrm_send_message(bp, &req, sizeof(req), | |
9629 | HWRM_CMD_TIMEOUT); | |
9630 | } | |
9631 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9632 | ||
9633 | vnic->uc_filter_count = 1; | |
9634 | ||
9635 | netif_addr_lock_bh(dev); | |
9636 | if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { | |
9637 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; | |
9638 | } else { | |
9639 | netdev_for_each_uc_addr(ha, dev) { | |
9640 | memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); | |
9641 | off += ETH_ALEN; | |
9642 | vnic->uc_filter_count++; | |
9643 | } | |
9644 | } | |
9645 | netif_addr_unlock_bh(dev); | |
9646 | ||
9647 | for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { | |
9648 | rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); | |
9649 | if (rc) { | |
9650 | netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", | |
9651 | rc); | |
9652 | vnic->uc_filter_count = i; | |
b664f008 | 9653 | return rc; |
c0c050c5 MC |
9654 | } |
9655 | } | |
9656 | ||
9657 | skip_uc: | |
9658 | rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); | |
b4e30e8e MC |
9659 | if (rc && vnic->mc_list_count) { |
9660 | netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", | |
9661 | rc); | |
9662 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; | |
9663 | vnic->mc_list_count = 0; | |
9664 | rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); | |
9665 | } | |
c0c050c5 | 9666 | if (rc) |
b4e30e8e | 9667 | netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", |
c0c050c5 | 9668 | rc); |
b664f008 MC |
9669 | |
9670 | return rc; | |
c0c050c5 MC |
9671 | } |
9672 | ||
2773dfb2 MC |
9673 | static bool bnxt_can_reserve_rings(struct bnxt *bp) |
9674 | { | |
9675 | #ifdef CONFIG_BNXT_SRIOV | |
f1ca94de | 9676 | if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { |
2773dfb2 MC |
9677 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
9678 | ||
9679 | /* No minimum rings were provisioned by the PF. Don't | |
9680 | * reserve rings by default when device is down. | |
9681 | */ | |
9682 | if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) | |
9683 | return true; | |
9684 | ||
9685 | if (!netif_running(bp->dev)) | |
9686 | return false; | |
9687 | } | |
9688 | #endif | |
9689 | return true; | |
9690 | } | |
9691 | ||
8079e8f1 MC |
9692 | /* If the chip and firmware supports RFS */ |
9693 | static bool bnxt_rfs_supported(struct bnxt *bp) | |
9694 | { | |
e969ae5b MC |
9695 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
9696 | if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) | |
9697 | return true; | |
41e8d798 | 9698 | return false; |
e969ae5b | 9699 | } |
8079e8f1 MC |
9700 | if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) |
9701 | return true; | |
ae10ae74 MC |
9702 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) |
9703 | return true; | |
8079e8f1 MC |
9704 | return false; |
9705 | } | |
9706 | ||
9707 | /* If runtime conditions support RFS */ | |
2bcfa6f6 MC |
9708 | static bool bnxt_rfs_capable(struct bnxt *bp) |
9709 | { | |
9710 | #ifdef CONFIG_RFS_ACCEL | |
8079e8f1 | 9711 | int vnics, max_vnics, max_rss_ctxs; |
2bcfa6f6 | 9712 | |
41e8d798 | 9713 | if (bp->flags & BNXT_FLAG_CHIP_P5) |
ac33906c | 9714 | return bnxt_rfs_supported(bp); |
2773dfb2 | 9715 | if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) |
2bcfa6f6 MC |
9716 | return false; |
9717 | ||
9718 | vnics = 1 + bp->rx_nr_rings; | |
8079e8f1 MC |
9719 | max_vnics = bnxt_get_max_func_vnics(bp); |
9720 | max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); | |
ae10ae74 MC |
9721 | |
9722 | /* RSS contexts not a limiting factor */ | |
9723 | if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) | |
9724 | max_rss_ctxs = max_vnics; | |
8079e8f1 | 9725 | if (vnics > max_vnics || vnics > max_rss_ctxs) { |
6a1eef5b MC |
9726 | if (bp->rx_nr_rings > 1) |
9727 | netdev_warn(bp->dev, | |
9728 | "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", | |
9729 | min(max_rss_ctxs - 1, max_vnics - 1)); | |
2bcfa6f6 | 9730 | return false; |
a2304909 | 9731 | } |
2bcfa6f6 | 9732 | |
f1ca94de | 9733 | if (!BNXT_NEW_RM(bp)) |
6a1eef5b MC |
9734 | return true; |
9735 | ||
9736 | if (vnics == bp->hw_resc.resv_vnics) | |
9737 | return true; | |
9738 | ||
780baad4 | 9739 | bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); |
6a1eef5b MC |
9740 | if (vnics <= bp->hw_resc.resv_vnics) |
9741 | return true; | |
9742 | ||
9743 | netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); | |
780baad4 | 9744 | bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); |
6a1eef5b | 9745 | return false; |
2bcfa6f6 MC |
9746 | #else |
9747 | return false; | |
9748 | #endif | |
9749 | } | |
9750 | ||
c0c050c5 MC |
9751 | static netdev_features_t bnxt_fix_features(struct net_device *dev, |
9752 | netdev_features_t features) | |
9753 | { | |
2bcfa6f6 MC |
9754 | struct bnxt *bp = netdev_priv(dev); |
9755 | ||
a2304909 | 9756 | if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) |
2bcfa6f6 | 9757 | features &= ~NETIF_F_NTUPLE; |
5a9f6b23 | 9758 | |
1054aee8 MC |
9759 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
9760 | features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); | |
9761 | ||
9762 | if (!(features & NETIF_F_GRO)) | |
9763 | features &= ~NETIF_F_GRO_HW; | |
9764 | ||
9765 | if (features & NETIF_F_GRO_HW) | |
9766 | features &= ~NETIF_F_LRO; | |
9767 | ||
5a9f6b23 MC |
9768 | /* Both CTAG and STAG VLAN accelaration on the RX side have to be |
9769 | * turned on or off together. | |
9770 | */ | |
9771 | if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != | |
9772 | (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { | |
9773 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) | |
9774 | features &= ~(NETIF_F_HW_VLAN_CTAG_RX | | |
9775 | NETIF_F_HW_VLAN_STAG_RX); | |
9776 | else | |
9777 | features |= NETIF_F_HW_VLAN_CTAG_RX | | |
9778 | NETIF_F_HW_VLAN_STAG_RX; | |
9779 | } | |
cf6645f8 MC |
9780 | #ifdef CONFIG_BNXT_SRIOV |
9781 | if (BNXT_VF(bp)) { | |
9782 | if (bp->vf.vlan) { | |
9783 | features &= ~(NETIF_F_HW_VLAN_CTAG_RX | | |
9784 | NETIF_F_HW_VLAN_STAG_RX); | |
9785 | } | |
9786 | } | |
9787 | #endif | |
c0c050c5 MC |
9788 | return features; |
9789 | } | |
9790 | ||
9791 | static int bnxt_set_features(struct net_device *dev, netdev_features_t features) | |
9792 | { | |
9793 | struct bnxt *bp = netdev_priv(dev); | |
9794 | u32 flags = bp->flags; | |
9795 | u32 changes; | |
9796 | int rc = 0; | |
9797 | bool re_init = false; | |
9798 | bool update_tpa = false; | |
9799 | ||
9800 | flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; | |
1054aee8 | 9801 | if (features & NETIF_F_GRO_HW) |
c0c050c5 | 9802 | flags |= BNXT_FLAG_GRO; |
1054aee8 | 9803 | else if (features & NETIF_F_LRO) |
c0c050c5 MC |
9804 | flags |= BNXT_FLAG_LRO; |
9805 | ||
bdbd1eb5 MC |
9806 | if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) |
9807 | flags &= ~BNXT_FLAG_TPA; | |
9808 | ||
c0c050c5 MC |
9809 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
9810 | flags |= BNXT_FLAG_STRIP_VLAN; | |
9811 | ||
9812 | if (features & NETIF_F_NTUPLE) | |
9813 | flags |= BNXT_FLAG_RFS; | |
9814 | ||
9815 | changes = flags ^ bp->flags; | |
9816 | if (changes & BNXT_FLAG_TPA) { | |
9817 | update_tpa = true; | |
9818 | if ((bp->flags & BNXT_FLAG_TPA) == 0 || | |
f45b7b78 MC |
9819 | (flags & BNXT_FLAG_TPA) == 0 || |
9820 | (bp->flags & BNXT_FLAG_CHIP_P5)) | |
c0c050c5 MC |
9821 | re_init = true; |
9822 | } | |
9823 | ||
9824 | if (changes & ~BNXT_FLAG_TPA) | |
9825 | re_init = true; | |
9826 | ||
9827 | if (flags != bp->flags) { | |
9828 | u32 old_flags = bp->flags; | |
9829 | ||
2bcfa6f6 | 9830 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { |
f45b7b78 | 9831 | bp->flags = flags; |
c0c050c5 MC |
9832 | if (update_tpa) |
9833 | bnxt_set_ring_params(bp); | |
9834 | return rc; | |
9835 | } | |
9836 | ||
9837 | if (re_init) { | |
9838 | bnxt_close_nic(bp, false, false); | |
f45b7b78 | 9839 | bp->flags = flags; |
c0c050c5 MC |
9840 | if (update_tpa) |
9841 | bnxt_set_ring_params(bp); | |
9842 | ||
9843 | return bnxt_open_nic(bp, false, false); | |
9844 | } | |
9845 | if (update_tpa) { | |
f45b7b78 | 9846 | bp->flags = flags; |
c0c050c5 MC |
9847 | rc = bnxt_set_tpa(bp, |
9848 | (flags & BNXT_FLAG_TPA) ? | |
9849 | true : false); | |
9850 | if (rc) | |
9851 | bp->flags = old_flags; | |
9852 | } | |
9853 | } | |
9854 | return rc; | |
9855 | } | |
9856 | ||
ffd77621 MC |
9857 | static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, |
9858 | u32 ring_id, u32 *prod, u32 *cons) | |
9859 | { | |
9860 | struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; | |
9861 | struct hwrm_dbg_ring_info_get_input req = {0}; | |
9862 | int rc; | |
9863 | ||
9864 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); | |
9865 | req.ring_type = ring_type; | |
9866 | req.fw_ring_id = cpu_to_le32(ring_id); | |
9867 | mutex_lock(&bp->hwrm_cmd_lock); | |
9868 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
9869 | if (!rc) { | |
9870 | *prod = le32_to_cpu(resp->producer_index); | |
9871 | *cons = le32_to_cpu(resp->consumer_index); | |
9872 | } | |
9873 | mutex_unlock(&bp->hwrm_cmd_lock); | |
9874 | return rc; | |
9875 | } | |
9876 | ||
9f554590 MC |
9877 | static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) |
9878 | { | |
b6ab4b01 | 9879 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; |
9f554590 MC |
9880 | int i = bnapi->index; |
9881 | ||
3b2b7d9d MC |
9882 | if (!txr) |
9883 | return; | |
9884 | ||
9f554590 MC |
9885 | netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", |
9886 | i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, | |
9887 | txr->tx_cons); | |
9888 | } | |
9889 | ||
9890 | static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) | |
9891 | { | |
b6ab4b01 | 9892 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
9f554590 MC |
9893 | int i = bnapi->index; |
9894 | ||
3b2b7d9d MC |
9895 | if (!rxr) |
9896 | return; | |
9897 | ||
9f554590 MC |
9898 | netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", |
9899 | i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, | |
9900 | rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, | |
9901 | rxr->rx_sw_agg_prod); | |
9902 | } | |
9903 | ||
9904 | static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) | |
9905 | { | |
9906 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
9907 | int i = bnapi->index; | |
9908 | ||
9909 | netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", | |
9910 | i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); | |
9911 | } | |
9912 | ||
c0c050c5 MC |
9913 | static void bnxt_dbg_dump_states(struct bnxt *bp) |
9914 | { | |
9915 | int i; | |
9916 | struct bnxt_napi *bnapi; | |
c0c050c5 MC |
9917 | |
9918 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
9919 | bnapi = bp->bnapi[i]; | |
c0c050c5 | 9920 | if (netif_msg_drv(bp)) { |
9f554590 MC |
9921 | bnxt_dump_tx_sw_state(bnapi); |
9922 | bnxt_dump_rx_sw_state(bnapi); | |
9923 | bnxt_dump_cp_sw_state(bnapi); | |
c0c050c5 MC |
9924 | } |
9925 | } | |
9926 | } | |
9927 | ||
6988bd92 | 9928 | static void bnxt_reset_task(struct bnxt *bp, bool silent) |
c0c050c5 | 9929 | { |
6988bd92 MC |
9930 | if (!silent) |
9931 | bnxt_dbg_dump_states(bp); | |
028de140 | 9932 | if (netif_running(bp->dev)) { |
b386cd36 MC |
9933 | int rc; |
9934 | ||
aa46dfff VV |
9935 | if (silent) { |
9936 | bnxt_close_nic(bp, false, false); | |
9937 | bnxt_open_nic(bp, false, false); | |
9938 | } else { | |
b386cd36 | 9939 | bnxt_ulp_stop(bp); |
aa46dfff VV |
9940 | bnxt_close_nic(bp, true, false); |
9941 | rc = bnxt_open_nic(bp, true, false); | |
9942 | bnxt_ulp_start(bp, rc); | |
9943 | } | |
028de140 | 9944 | } |
c0c050c5 MC |
9945 | } |
9946 | ||
9947 | static void bnxt_tx_timeout(struct net_device *dev) | |
9948 | { | |
9949 | struct bnxt *bp = netdev_priv(dev); | |
9950 | ||
9951 | netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); | |
9952 | set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); | |
c213eae8 | 9953 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
9954 | } |
9955 | ||
acfb50e4 VV |
9956 | static void bnxt_fw_health_check(struct bnxt *bp) |
9957 | { | |
9958 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
9959 | u32 val; | |
9960 | ||
9961 | if (!fw_health || !fw_health->enabled || | |
9962 | test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) | |
9963 | return; | |
9964 | ||
9965 | if (fw_health->tmr_counter) { | |
9966 | fw_health->tmr_counter--; | |
9967 | return; | |
9968 | } | |
9969 | ||
9970 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
9971 | if (val == fw_health->last_fw_heartbeat) | |
9972 | goto fw_reset; | |
9973 | ||
9974 | fw_health->last_fw_heartbeat = val; | |
9975 | ||
9976 | val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
9977 | if (val != fw_health->last_fw_reset_cnt) | |
9978 | goto fw_reset; | |
9979 | ||
9980 | fw_health->tmr_counter = fw_health->tmr_multiplier; | |
9981 | return; | |
9982 | ||
9983 | fw_reset: | |
9984 | set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event); | |
9985 | bnxt_queue_sp_work(bp); | |
9986 | } | |
9987 | ||
e99e88a9 | 9988 | static void bnxt_timer(struct timer_list *t) |
c0c050c5 | 9989 | { |
e99e88a9 | 9990 | struct bnxt *bp = from_timer(bp, t, timer); |
c0c050c5 MC |
9991 | struct net_device *dev = bp->dev; |
9992 | ||
9993 | if (!netif_running(dev)) | |
9994 | return; | |
9995 | ||
9996 | if (atomic_read(&bp->intr_sem) != 0) | |
9997 | goto bnxt_restart_timer; | |
9998 | ||
acfb50e4 VV |
9999 | if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) |
10000 | bnxt_fw_health_check(bp); | |
10001 | ||
adcc331e MC |
10002 | if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && |
10003 | bp->stats_coal_ticks) { | |
3bdf56c4 | 10004 | set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); |
c213eae8 | 10005 | bnxt_queue_sp_work(bp); |
3bdf56c4 | 10006 | } |
5a84acbe SP |
10007 | |
10008 | if (bnxt_tc_flower_enabled(bp)) { | |
10009 | set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); | |
10010 | bnxt_queue_sp_work(bp); | |
10011 | } | |
a1ef4a79 MC |
10012 | |
10013 | if (bp->link_info.phy_retry) { | |
10014 | if (time_after(jiffies, bp->link_info.phy_retry_expires)) { | |
acda6180 | 10015 | bp->link_info.phy_retry = false; |
a1ef4a79 MC |
10016 | netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); |
10017 | } else { | |
10018 | set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); | |
10019 | bnxt_queue_sp_work(bp); | |
10020 | } | |
10021 | } | |
ffd77621 MC |
10022 | |
10023 | if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) { | |
10024 | set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); | |
10025 | bnxt_queue_sp_work(bp); | |
10026 | } | |
c0c050c5 MC |
10027 | bnxt_restart_timer: |
10028 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
10029 | } | |
10030 | ||
a551ee94 | 10031 | static void bnxt_rtnl_lock_sp(struct bnxt *bp) |
6988bd92 | 10032 | { |
a551ee94 MC |
10033 | /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK |
10034 | * set. If the device is being closed, bnxt_close() may be holding | |
6988bd92 MC |
10035 | * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we |
10036 | * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). | |
10037 | */ | |
10038 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
10039 | rtnl_lock(); | |
a551ee94 MC |
10040 | } |
10041 | ||
10042 | static void bnxt_rtnl_unlock_sp(struct bnxt *bp) | |
10043 | { | |
6988bd92 MC |
10044 | set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
10045 | rtnl_unlock(); | |
10046 | } | |
10047 | ||
a551ee94 MC |
10048 | /* Only called from bnxt_sp_task() */ |
10049 | static void bnxt_reset(struct bnxt *bp, bool silent) | |
10050 | { | |
10051 | bnxt_rtnl_lock_sp(bp); | |
10052 | if (test_bit(BNXT_STATE_OPEN, &bp->state)) | |
10053 | bnxt_reset_task(bp, silent); | |
10054 | bnxt_rtnl_unlock_sp(bp); | |
10055 | } | |
10056 | ||
230d1f0d MC |
10057 | static void bnxt_fw_reset_close(struct bnxt *bp) |
10058 | { | |
f3a6d206 | 10059 | bnxt_ulp_stop(bp); |
230d1f0d | 10060 | __bnxt_close_nic(bp, true, false); |
230d1f0d MC |
10061 | bnxt_clear_int_mode(bp); |
10062 | bnxt_hwrm_func_drv_unrgtr(bp); | |
10063 | bnxt_free_ctx_mem(bp); | |
10064 | kfree(bp->ctx); | |
10065 | bp->ctx = NULL; | |
10066 | } | |
10067 | ||
acfb50e4 VV |
10068 | static bool is_bnxt_fw_ok(struct bnxt *bp) |
10069 | { | |
10070 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10071 | bool no_heartbeat = false, has_reset = false; | |
10072 | u32 val; | |
10073 | ||
10074 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); | |
10075 | if (val == fw_health->last_fw_heartbeat) | |
10076 | no_heartbeat = true; | |
10077 | ||
10078 | val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); | |
10079 | if (val != fw_health->last_fw_reset_cnt) | |
10080 | has_reset = true; | |
10081 | ||
10082 | if (!no_heartbeat && has_reset) | |
10083 | return true; | |
10084 | ||
10085 | return false; | |
10086 | } | |
10087 | ||
d1db9e16 MC |
10088 | /* rtnl_lock is acquired before calling this function */ |
10089 | static void bnxt_force_fw_reset(struct bnxt *bp) | |
10090 | { | |
10091 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10092 | u32 wait_dsecs; | |
10093 | ||
10094 | if (!test_bit(BNXT_STATE_OPEN, &bp->state) || | |
10095 | test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) | |
10096 | return; | |
10097 | ||
10098 | set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10099 | bnxt_fw_reset_close(bp); | |
10100 | wait_dsecs = fw_health->master_func_wait_dsecs; | |
10101 | if (fw_health->master) { | |
10102 | if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) | |
10103 | wait_dsecs = 0; | |
10104 | bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; | |
10105 | } else { | |
10106 | bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; | |
10107 | wait_dsecs = fw_health->normal_func_wait_dsecs; | |
10108 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10109 | } | |
4037eb71 VV |
10110 | |
10111 | bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; | |
d1db9e16 MC |
10112 | bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; |
10113 | bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); | |
10114 | } | |
10115 | ||
10116 | void bnxt_fw_exception(struct bnxt *bp) | |
10117 | { | |
10118 | set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); | |
10119 | bnxt_rtnl_lock_sp(bp); | |
10120 | bnxt_force_fw_reset(bp); | |
10121 | bnxt_rtnl_unlock_sp(bp); | |
10122 | } | |
10123 | ||
e72cb7d6 MC |
10124 | /* Returns the number of registered VFs, or 1 if VF configuration is pending, or |
10125 | * < 0 on error. | |
10126 | */ | |
10127 | static int bnxt_get_registered_vfs(struct bnxt *bp) | |
230d1f0d | 10128 | { |
e72cb7d6 | 10129 | #ifdef CONFIG_BNXT_SRIOV |
230d1f0d MC |
10130 | int rc; |
10131 | ||
e72cb7d6 MC |
10132 | if (!BNXT_PF(bp)) |
10133 | return 0; | |
10134 | ||
10135 | rc = bnxt_hwrm_func_qcfg(bp); | |
10136 | if (rc) { | |
10137 | netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); | |
10138 | return rc; | |
10139 | } | |
10140 | if (bp->pf.registered_vfs) | |
10141 | return bp->pf.registered_vfs; | |
10142 | if (bp->sriov_cfg) | |
10143 | return 1; | |
10144 | #endif | |
10145 | return 0; | |
10146 | } | |
10147 | ||
10148 | void bnxt_fw_reset(struct bnxt *bp) | |
10149 | { | |
230d1f0d MC |
10150 | bnxt_rtnl_lock_sp(bp); |
10151 | if (test_bit(BNXT_STATE_OPEN, &bp->state) && | |
10152 | !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { | |
4037eb71 | 10153 | int n = 0, tmo; |
e72cb7d6 | 10154 | |
230d1f0d | 10155 | set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); |
e72cb7d6 MC |
10156 | if (bp->pf.active_vfs && |
10157 | !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) | |
10158 | n = bnxt_get_registered_vfs(bp); | |
10159 | if (n < 0) { | |
10160 | netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", | |
10161 | n); | |
10162 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10163 | dev_close(bp->dev); | |
10164 | goto fw_reset_exit; | |
10165 | } else if (n > 0) { | |
10166 | u16 vf_tmo_dsecs = n * 10; | |
10167 | ||
10168 | if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) | |
10169 | bp->fw_reset_max_dsecs = vf_tmo_dsecs; | |
10170 | bp->fw_reset_state = | |
10171 | BNXT_FW_RESET_STATE_POLL_VF; | |
10172 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
10173 | goto fw_reset_exit; | |
230d1f0d MC |
10174 | } |
10175 | bnxt_fw_reset_close(bp); | |
4037eb71 VV |
10176 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { |
10177 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; | |
10178 | tmo = HZ / 10; | |
10179 | } else { | |
10180 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10181 | tmo = bp->fw_reset_min_dsecs * HZ / 10; | |
10182 | } | |
10183 | bnxt_queue_fw_reset_work(bp, tmo); | |
230d1f0d MC |
10184 | } |
10185 | fw_reset_exit: | |
10186 | bnxt_rtnl_unlock_sp(bp); | |
10187 | } | |
10188 | ||
ffd77621 MC |
10189 | static void bnxt_chk_missed_irq(struct bnxt *bp) |
10190 | { | |
10191 | int i; | |
10192 | ||
10193 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) | |
10194 | return; | |
10195 | ||
10196 | for (i = 0; i < bp->cp_nr_rings; i++) { | |
10197 | struct bnxt_napi *bnapi = bp->bnapi[i]; | |
10198 | struct bnxt_cp_ring_info *cpr; | |
10199 | u32 fw_ring_id; | |
10200 | int j; | |
10201 | ||
10202 | if (!bnapi) | |
10203 | continue; | |
10204 | ||
10205 | cpr = &bnapi->cp_ring; | |
10206 | for (j = 0; j < 2; j++) { | |
10207 | struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; | |
10208 | u32 val[2]; | |
10209 | ||
10210 | if (!cpr2 || cpr2->has_more_work || | |
10211 | !bnxt_has_work(bp, cpr2)) | |
10212 | continue; | |
10213 | ||
10214 | if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { | |
10215 | cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; | |
10216 | continue; | |
10217 | } | |
10218 | fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; | |
10219 | bnxt_dbg_hwrm_ring_info_get(bp, | |
10220 | DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, | |
10221 | fw_ring_id, &val[0], &val[1]); | |
83eb5c5c | 10222 | cpr->missed_irqs++; |
ffd77621 MC |
10223 | } |
10224 | } | |
10225 | } | |
10226 | ||
c0c050c5 MC |
10227 | static void bnxt_cfg_ntp_filters(struct bnxt *); |
10228 | ||
10229 | static void bnxt_sp_task(struct work_struct *work) | |
10230 | { | |
10231 | struct bnxt *bp = container_of(work, struct bnxt, sp_task); | |
c0c050c5 | 10232 | |
4cebdcec MC |
10233 | set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
10234 | smp_mb__after_atomic(); | |
10235 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { | |
10236 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
c0c050c5 | 10237 | return; |
4cebdcec | 10238 | } |
c0c050c5 MC |
10239 | |
10240 | if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) | |
10241 | bnxt_cfg_rx_mode(bp); | |
10242 | ||
10243 | if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) | |
10244 | bnxt_cfg_ntp_filters(bp); | |
c0c050c5 MC |
10245 | if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) |
10246 | bnxt_hwrm_exec_fwd_req(bp); | |
10247 | if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { | |
10248 | bnxt_hwrm_tunnel_dst_port_alloc( | |
10249 | bp, bp->vxlan_port, | |
10250 | TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); | |
10251 | } | |
10252 | if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { | |
10253 | bnxt_hwrm_tunnel_dst_port_free( | |
10254 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); | |
10255 | } | |
7cdd5fc3 AD |
10256 | if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { |
10257 | bnxt_hwrm_tunnel_dst_port_alloc( | |
10258 | bp, bp->nge_port, | |
10259 | TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); | |
10260 | } | |
10261 | if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { | |
10262 | bnxt_hwrm_tunnel_dst_port_free( | |
10263 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); | |
10264 | } | |
00db3cba | 10265 | if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { |
3bdf56c4 | 10266 | bnxt_hwrm_port_qstats(bp); |
00db3cba | 10267 | bnxt_hwrm_port_qstats_ext(bp); |
55e4398d | 10268 | bnxt_hwrm_pcie_qstats(bp); |
00db3cba | 10269 | } |
3bdf56c4 | 10270 | |
0eaa24b9 | 10271 | if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { |
e2dc9b6e | 10272 | int rc; |
0eaa24b9 | 10273 | |
e2dc9b6e | 10274 | mutex_lock(&bp->link_lock); |
0eaa24b9 MC |
10275 | if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, |
10276 | &bp->sp_event)) | |
10277 | bnxt_hwrm_phy_qcaps(bp); | |
10278 | ||
e2dc9b6e MC |
10279 | rc = bnxt_update_link(bp, true); |
10280 | mutex_unlock(&bp->link_lock); | |
0eaa24b9 MC |
10281 | if (rc) |
10282 | netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", | |
10283 | rc); | |
10284 | } | |
a1ef4a79 MC |
10285 | if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { |
10286 | int rc; | |
10287 | ||
10288 | mutex_lock(&bp->link_lock); | |
10289 | rc = bnxt_update_phy_setting(bp); | |
10290 | mutex_unlock(&bp->link_lock); | |
10291 | if (rc) { | |
10292 | netdev_warn(bp->dev, "update phy settings retry failed\n"); | |
10293 | } else { | |
10294 | bp->link_info.phy_retry = false; | |
10295 | netdev_info(bp->dev, "update phy settings retry succeeded\n"); | |
10296 | } | |
10297 | } | |
90c694bb | 10298 | if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { |
e2dc9b6e MC |
10299 | mutex_lock(&bp->link_lock); |
10300 | bnxt_get_port_module_status(bp); | |
10301 | mutex_unlock(&bp->link_lock); | |
90c694bb | 10302 | } |
5a84acbe SP |
10303 | |
10304 | if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) | |
10305 | bnxt_tc_flow_stats_work(bp); | |
10306 | ||
ffd77621 MC |
10307 | if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) |
10308 | bnxt_chk_missed_irq(bp); | |
10309 | ||
e2dc9b6e MC |
10310 | /* These functions below will clear BNXT_STATE_IN_SP_TASK. They |
10311 | * must be the last functions to be called before exiting. | |
10312 | */ | |
6988bd92 MC |
10313 | if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) |
10314 | bnxt_reset(bp, false); | |
4cebdcec | 10315 | |
fc0f1929 MC |
10316 | if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) |
10317 | bnxt_reset(bp, true); | |
10318 | ||
657a33c8 VV |
10319 | if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) |
10320 | bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT); | |
10321 | ||
acfb50e4 VV |
10322 | if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { |
10323 | if (!is_bnxt_fw_ok(bp)) | |
10324 | bnxt_devlink_health_report(bp, | |
10325 | BNXT_FW_EXCEPTION_SP_EVENT); | |
10326 | } | |
10327 | ||
4cebdcec MC |
10328 | smp_mb__before_atomic(); |
10329 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); | |
c0c050c5 MC |
10330 | } |
10331 | ||
d1e7925e | 10332 | /* Under rtnl_lock */ |
98fdbe73 MC |
10333 | int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, |
10334 | int tx_xdp) | |
d1e7925e MC |
10335 | { |
10336 | int max_rx, max_tx, tx_sets = 1; | |
780baad4 | 10337 | int tx_rings_needed, stats; |
8f23d638 | 10338 | int rx_rings = rx; |
6fc2ffdf | 10339 | int cp, vnics, rc; |
d1e7925e | 10340 | |
d1e7925e MC |
10341 | if (tcs) |
10342 | tx_sets = tcs; | |
10343 | ||
10344 | rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); | |
10345 | if (rc) | |
10346 | return rc; | |
10347 | ||
10348 | if (max_rx < rx) | |
10349 | return -ENOMEM; | |
10350 | ||
5f449249 | 10351 | tx_rings_needed = tx * tx_sets + tx_xdp; |
d1e7925e MC |
10352 | if (max_tx < tx_rings_needed) |
10353 | return -ENOMEM; | |
10354 | ||
6fc2ffdf | 10355 | vnics = 1; |
9b3d15e6 | 10356 | if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) |
6fc2ffdf EW |
10357 | vnics += rx_rings; |
10358 | ||
8f23d638 MC |
10359 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
10360 | rx_rings <<= 1; | |
10361 | cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; | |
780baad4 VV |
10362 | stats = cp; |
10363 | if (BNXT_NEW_RM(bp)) { | |
11c3ec7b | 10364 | cp += bnxt_get_ulp_msix_num(bp); |
780baad4 VV |
10365 | stats += bnxt_get_ulp_stat_ctxs(bp); |
10366 | } | |
6fc2ffdf | 10367 | return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, |
780baad4 | 10368 | stats, vnics); |
d1e7925e MC |
10369 | } |
10370 | ||
17086399 SP |
10371 | static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) |
10372 | { | |
10373 | if (bp->bar2) { | |
10374 | pci_iounmap(pdev, bp->bar2); | |
10375 | bp->bar2 = NULL; | |
10376 | } | |
10377 | ||
10378 | if (bp->bar1) { | |
10379 | pci_iounmap(pdev, bp->bar1); | |
10380 | bp->bar1 = NULL; | |
10381 | } | |
10382 | ||
10383 | if (bp->bar0) { | |
10384 | pci_iounmap(pdev, bp->bar0); | |
10385 | bp->bar0 = NULL; | |
10386 | } | |
10387 | } | |
10388 | ||
10389 | static void bnxt_cleanup_pci(struct bnxt *bp) | |
10390 | { | |
10391 | bnxt_unmap_bars(bp, bp->pdev); | |
10392 | pci_release_regions(bp->pdev); | |
f6824308 VV |
10393 | if (pci_is_enabled(bp->pdev)) |
10394 | pci_disable_device(bp->pdev); | |
17086399 SP |
10395 | } |
10396 | ||
18775aa8 MC |
10397 | static void bnxt_init_dflt_coal(struct bnxt *bp) |
10398 | { | |
10399 | struct bnxt_coal *coal; | |
10400 | ||
10401 | /* Tick values in micro seconds. | |
10402 | * 1 coal_buf x bufs_per_record = 1 completion record. | |
10403 | */ | |
10404 | coal = &bp->rx_coal; | |
0c2ff8d7 | 10405 | coal->coal_ticks = 10; |
18775aa8 MC |
10406 | coal->coal_bufs = 30; |
10407 | coal->coal_ticks_irq = 1; | |
10408 | coal->coal_bufs_irq = 2; | |
05abe4dd | 10409 | coal->idle_thresh = 50; |
18775aa8 MC |
10410 | coal->bufs_per_record = 2; |
10411 | coal->budget = 64; /* NAPI budget */ | |
10412 | ||
10413 | coal = &bp->tx_coal; | |
10414 | coal->coal_ticks = 28; | |
10415 | coal->coal_bufs = 30; | |
10416 | coal->coal_ticks_irq = 2; | |
10417 | coal->coal_bufs_irq = 2; | |
10418 | coal->bufs_per_record = 1; | |
10419 | ||
10420 | bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; | |
10421 | } | |
10422 | ||
7c380918 MC |
10423 | static int bnxt_fw_init_one_p1(struct bnxt *bp) |
10424 | { | |
10425 | int rc; | |
10426 | ||
10427 | bp->fw_cap = 0; | |
10428 | rc = bnxt_hwrm_ver_get(bp); | |
10429 | if (rc) | |
10430 | return rc; | |
10431 | ||
10432 | if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { | |
10433 | rc = bnxt_alloc_kong_hwrm_resources(bp); | |
10434 | if (rc) | |
10435 | bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; | |
10436 | } | |
10437 | ||
10438 | if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || | |
10439 | bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { | |
10440 | rc = bnxt_alloc_hwrm_short_cmd_req(bp); | |
10441 | if (rc) | |
10442 | return rc; | |
10443 | } | |
10444 | rc = bnxt_hwrm_func_reset(bp); | |
10445 | if (rc) | |
10446 | return -ENODEV; | |
10447 | ||
10448 | bnxt_hwrm_fw_set_time(bp); | |
10449 | return 0; | |
10450 | } | |
10451 | ||
10452 | static int bnxt_fw_init_one_p2(struct bnxt *bp) | |
10453 | { | |
10454 | int rc; | |
10455 | ||
10456 | /* Get the MAX capabilities for this function */ | |
10457 | rc = bnxt_hwrm_func_qcaps(bp); | |
10458 | if (rc) { | |
10459 | netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", | |
10460 | rc); | |
10461 | return -ENODEV; | |
10462 | } | |
10463 | ||
10464 | rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); | |
10465 | if (rc) | |
10466 | netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", | |
10467 | rc); | |
10468 | ||
07f83d72 MC |
10469 | rc = bnxt_hwrm_error_recovery_qcfg(bp); |
10470 | if (rc) | |
10471 | netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", | |
10472 | rc); | |
10473 | ||
7c380918 MC |
10474 | rc = bnxt_hwrm_func_drv_rgtr(bp); |
10475 | if (rc) | |
10476 | return -ENODEV; | |
10477 | ||
10478 | rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0); | |
10479 | if (rc) | |
10480 | return -ENODEV; | |
10481 | ||
10482 | bnxt_hwrm_func_qcfg(bp); | |
10483 | bnxt_hwrm_vnic_qcaps(bp); | |
10484 | bnxt_hwrm_port_led_qcaps(bp); | |
10485 | bnxt_ethtool_init(bp); | |
10486 | bnxt_dcb_init(bp); | |
10487 | return 0; | |
10488 | } | |
10489 | ||
ba642ab7 MC |
10490 | static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) |
10491 | { | |
10492 | bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; | |
10493 | bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | | |
10494 | VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | | |
10495 | VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | | |
10496 | VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; | |
10497 | if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) { | |
10498 | bp->flags |= BNXT_FLAG_UDP_RSS_CAP; | |
10499 | bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | | |
10500 | VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; | |
10501 | } | |
10502 | } | |
10503 | ||
10504 | static void bnxt_set_dflt_rfs(struct bnxt *bp) | |
10505 | { | |
10506 | struct net_device *dev = bp->dev; | |
10507 | ||
10508 | dev->hw_features &= ~NETIF_F_NTUPLE; | |
10509 | dev->features &= ~NETIF_F_NTUPLE; | |
10510 | bp->flags &= ~BNXT_FLAG_RFS; | |
10511 | if (bnxt_rfs_supported(bp)) { | |
10512 | dev->hw_features |= NETIF_F_NTUPLE; | |
10513 | if (bnxt_rfs_capable(bp)) { | |
10514 | bp->flags |= BNXT_FLAG_RFS; | |
10515 | dev->features |= NETIF_F_NTUPLE; | |
10516 | } | |
10517 | } | |
10518 | } | |
10519 | ||
10520 | static void bnxt_fw_init_one_p3(struct bnxt *bp) | |
10521 | { | |
10522 | struct pci_dev *pdev = bp->pdev; | |
10523 | ||
10524 | bnxt_set_dflt_rss_hash_type(bp); | |
10525 | bnxt_set_dflt_rfs(bp); | |
10526 | ||
10527 | bnxt_get_wol_settings(bp); | |
10528 | if (bp->flags & BNXT_FLAG_WOL_CAP) | |
10529 | device_set_wakeup_enable(&pdev->dev, bp->wol); | |
10530 | else | |
10531 | device_set_wakeup_capable(&pdev->dev, false); | |
10532 | ||
10533 | bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); | |
10534 | bnxt_hwrm_coal_params_qcaps(bp); | |
10535 | } | |
10536 | ||
ec5d31e3 MC |
10537 | static int bnxt_fw_init_one(struct bnxt *bp) |
10538 | { | |
10539 | int rc; | |
10540 | ||
10541 | rc = bnxt_fw_init_one_p1(bp); | |
10542 | if (rc) { | |
10543 | netdev_err(bp->dev, "Firmware init phase 1 failed\n"); | |
10544 | return rc; | |
10545 | } | |
10546 | rc = bnxt_fw_init_one_p2(bp); | |
10547 | if (rc) { | |
10548 | netdev_err(bp->dev, "Firmware init phase 2 failed\n"); | |
10549 | return rc; | |
10550 | } | |
10551 | rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); | |
10552 | if (rc) | |
10553 | return rc; | |
10554 | bnxt_fw_init_one_p3(bp); | |
10555 | return 0; | |
10556 | } | |
10557 | ||
cbb51067 MC |
10558 | static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) |
10559 | { | |
10560 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
10561 | u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; | |
10562 | u32 val = fw_health->fw_reset_seq_vals[reg_idx]; | |
10563 | u32 reg_type, reg_off, delay_msecs; | |
10564 | ||
10565 | delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; | |
10566 | reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); | |
10567 | reg_off = BNXT_FW_HEALTH_REG_OFF(reg); | |
10568 | switch (reg_type) { | |
10569 | case BNXT_FW_HEALTH_REG_TYPE_CFG: | |
10570 | pci_write_config_dword(bp->pdev, reg_off, val); | |
10571 | break; | |
10572 | case BNXT_FW_HEALTH_REG_TYPE_GRC: | |
10573 | writel(reg_off & BNXT_GRC_BASE_MASK, | |
10574 | bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); | |
10575 | reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; | |
10576 | /* fall through */ | |
10577 | case BNXT_FW_HEALTH_REG_TYPE_BAR0: | |
10578 | writel(val, bp->bar0 + reg_off); | |
10579 | break; | |
10580 | case BNXT_FW_HEALTH_REG_TYPE_BAR1: | |
10581 | writel(val, bp->bar1 + reg_off); | |
10582 | break; | |
10583 | } | |
10584 | if (delay_msecs) { | |
10585 | pci_read_config_dword(bp->pdev, 0, &val); | |
10586 | msleep(delay_msecs); | |
10587 | } | |
10588 | } | |
10589 | ||
10590 | static void bnxt_reset_all(struct bnxt *bp) | |
10591 | { | |
10592 | struct bnxt_fw_health *fw_health = bp->fw_health; | |
e07ab202 VV |
10593 | int i, rc; |
10594 | ||
10595 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { | |
10596 | #ifdef CONFIG_TEE_BNXT_FW | |
10597 | rc = tee_bnxt_fw_load(); | |
10598 | if (rc) | |
10599 | netdev_err(bp->dev, "Unable to reset FW rc=%d\n", rc); | |
10600 | bp->fw_reset_timestamp = jiffies; | |
10601 | #endif | |
10602 | return; | |
10603 | } | |
cbb51067 MC |
10604 | |
10605 | if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { | |
10606 | for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) | |
10607 | bnxt_fw_reset_writel(bp, i); | |
10608 | } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { | |
10609 | struct hwrm_fw_reset_input req = {0}; | |
cbb51067 MC |
10610 | |
10611 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); | |
10612 | req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); | |
10613 | req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; | |
10614 | req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; | |
10615 | req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; | |
10616 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
10617 | if (rc) | |
10618 | netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); | |
10619 | } | |
10620 | bp->fw_reset_timestamp = jiffies; | |
10621 | } | |
10622 | ||
230d1f0d MC |
10623 | static void bnxt_fw_reset_task(struct work_struct *work) |
10624 | { | |
10625 | struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); | |
10626 | int rc; | |
10627 | ||
10628 | if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { | |
10629 | netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); | |
10630 | return; | |
10631 | } | |
10632 | ||
10633 | switch (bp->fw_reset_state) { | |
e72cb7d6 MC |
10634 | case BNXT_FW_RESET_STATE_POLL_VF: { |
10635 | int n = bnxt_get_registered_vfs(bp); | |
4037eb71 | 10636 | int tmo; |
e72cb7d6 MC |
10637 | |
10638 | if (n < 0) { | |
230d1f0d | 10639 | netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", |
e72cb7d6 | 10640 | n, jiffies_to_msecs(jiffies - |
230d1f0d MC |
10641 | bp->fw_reset_timestamp)); |
10642 | goto fw_reset_abort; | |
e72cb7d6 | 10643 | } else if (n > 0) { |
230d1f0d MC |
10644 | if (time_after(jiffies, bp->fw_reset_timestamp + |
10645 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
10646 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10647 | bp->fw_reset_state = 0; | |
e72cb7d6 MC |
10648 | netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", |
10649 | n); | |
230d1f0d MC |
10650 | return; |
10651 | } | |
10652 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
10653 | return; | |
10654 | } | |
10655 | bp->fw_reset_timestamp = jiffies; | |
10656 | rtnl_lock(); | |
10657 | bnxt_fw_reset_close(bp); | |
4037eb71 VV |
10658 | if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { |
10659 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; | |
10660 | tmo = HZ / 10; | |
10661 | } else { | |
10662 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10663 | tmo = bp->fw_reset_min_dsecs * HZ / 10; | |
10664 | } | |
230d1f0d | 10665 | rtnl_unlock(); |
4037eb71 | 10666 | bnxt_queue_fw_reset_work(bp, tmo); |
230d1f0d | 10667 | return; |
e72cb7d6 | 10668 | } |
4037eb71 VV |
10669 | case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { |
10670 | u32 val; | |
10671 | ||
10672 | val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); | |
10673 | if (!(val & BNXT_FW_STATUS_SHUTDOWN) && | |
10674 | !time_after(jiffies, bp->fw_reset_timestamp + | |
10675 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
10676 | bnxt_queue_fw_reset_work(bp, HZ / 5); | |
10677 | return; | |
10678 | } | |
10679 | ||
10680 | if (!bp->fw_health->master) { | |
10681 | u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; | |
10682 | ||
10683 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
10684 | bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); | |
10685 | return; | |
10686 | } | |
10687 | bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; | |
10688 | } | |
10689 | /* fall through */ | |
c6a9e7aa | 10690 | case BNXT_FW_RESET_STATE_RESET_FW: |
cbb51067 MC |
10691 | bnxt_reset_all(bp); |
10692 | bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; | |
c6a9e7aa | 10693 | bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); |
cbb51067 | 10694 | return; |
230d1f0d | 10695 | case BNXT_FW_RESET_STATE_ENABLE_DEV: |
d1db9e16 MC |
10696 | if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) && |
10697 | bp->fw_health) { | |
10698 | u32 val; | |
10699 | ||
10700 | val = bnxt_fw_health_readl(bp, | |
10701 | BNXT_FW_RESET_INPROG_REG); | |
10702 | if (val) | |
10703 | netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n", | |
10704 | val); | |
10705 | } | |
b4fff207 | 10706 | clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); |
230d1f0d MC |
10707 | if (pci_enable_device(bp->pdev)) { |
10708 | netdev_err(bp->dev, "Cannot re-enable PCI device\n"); | |
10709 | goto fw_reset_abort; | |
10710 | } | |
10711 | pci_set_master(bp->pdev); | |
10712 | bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; | |
10713 | /* fall through */ | |
10714 | case BNXT_FW_RESET_STATE_POLL_FW: | |
10715 | bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; | |
10716 | rc = __bnxt_hwrm_ver_get(bp, true); | |
10717 | if (rc) { | |
10718 | if (time_after(jiffies, bp->fw_reset_timestamp + | |
10719 | (bp->fw_reset_max_dsecs * HZ / 10))) { | |
10720 | netdev_err(bp->dev, "Firmware reset aborted\n"); | |
10721 | goto fw_reset_abort; | |
10722 | } | |
10723 | bnxt_queue_fw_reset_work(bp, HZ / 5); | |
10724 | return; | |
10725 | } | |
10726 | bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; | |
10727 | bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; | |
10728 | /* fall through */ | |
10729 | case BNXT_FW_RESET_STATE_OPENING: | |
10730 | while (!rtnl_trylock()) { | |
10731 | bnxt_queue_fw_reset_work(bp, HZ / 10); | |
10732 | return; | |
10733 | } | |
10734 | rc = bnxt_open(bp->dev); | |
10735 | if (rc) { | |
10736 | netdev_err(bp->dev, "bnxt_open_nic() failed\n"); | |
10737 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10738 | dev_close(bp->dev); | |
10739 | } | |
230d1f0d MC |
10740 | |
10741 | bp->fw_reset_state = 0; | |
10742 | /* Make sure fw_reset_state is 0 before clearing the flag */ | |
10743 | smp_mb__before_atomic(); | |
10744 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
f3a6d206 VV |
10745 | bnxt_ulp_start(bp, rc); |
10746 | rtnl_unlock(); | |
230d1f0d MC |
10747 | break; |
10748 | } | |
10749 | return; | |
10750 | ||
10751 | fw_reset_abort: | |
10752 | clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); | |
10753 | bp->fw_reset_state = 0; | |
10754 | rtnl_lock(); | |
10755 | dev_close(bp->dev); | |
10756 | rtnl_unlock(); | |
10757 | } | |
10758 | ||
c0c050c5 MC |
10759 | static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) |
10760 | { | |
10761 | int rc; | |
10762 | struct bnxt *bp = netdev_priv(dev); | |
10763 | ||
10764 | SET_NETDEV_DEV(dev, &pdev->dev); | |
10765 | ||
10766 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ | |
10767 | rc = pci_enable_device(pdev); | |
10768 | if (rc) { | |
10769 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); | |
10770 | goto init_err; | |
10771 | } | |
10772 | ||
10773 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
10774 | dev_err(&pdev->dev, | |
10775 | "Cannot find PCI device base address, aborting\n"); | |
10776 | rc = -ENODEV; | |
10777 | goto init_err_disable; | |
10778 | } | |
10779 | ||
10780 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
10781 | if (rc) { | |
10782 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); | |
10783 | goto init_err_disable; | |
10784 | } | |
10785 | ||
10786 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && | |
10787 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { | |
10788 | dev_err(&pdev->dev, "System does not support DMA, aborting\n"); | |
10789 | goto init_err_disable; | |
10790 | } | |
10791 | ||
10792 | pci_set_master(pdev); | |
10793 | ||
10794 | bp->dev = dev; | |
10795 | bp->pdev = pdev; | |
10796 | ||
10797 | bp->bar0 = pci_ioremap_bar(pdev, 0); | |
10798 | if (!bp->bar0) { | |
10799 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); | |
10800 | rc = -ENOMEM; | |
10801 | goto init_err_release; | |
10802 | } | |
10803 | ||
10804 | bp->bar1 = pci_ioremap_bar(pdev, 2); | |
10805 | if (!bp->bar1) { | |
10806 | dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); | |
10807 | rc = -ENOMEM; | |
10808 | goto init_err_release; | |
10809 | } | |
10810 | ||
10811 | bp->bar2 = pci_ioremap_bar(pdev, 4); | |
10812 | if (!bp->bar2) { | |
10813 | dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); | |
10814 | rc = -ENOMEM; | |
10815 | goto init_err_release; | |
10816 | } | |
10817 | ||
6316ea6d SB |
10818 | pci_enable_pcie_error_reporting(pdev); |
10819 | ||
c0c050c5 | 10820 | INIT_WORK(&bp->sp_task, bnxt_sp_task); |
230d1f0d | 10821 | INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); |
c0c050c5 MC |
10822 | |
10823 | spin_lock_init(&bp->ntp_fltr_lock); | |
697197e5 MC |
10824 | #if BITS_PER_LONG == 32 |
10825 | spin_lock_init(&bp->db_lock); | |
10826 | #endif | |
c0c050c5 MC |
10827 | |
10828 | bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; | |
10829 | bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; | |
10830 | ||
18775aa8 | 10831 | bnxt_init_dflt_coal(bp); |
51f30785 | 10832 | |
e99e88a9 | 10833 | timer_setup(&bp->timer, bnxt_timer, 0); |
c0c050c5 MC |
10834 | bp->current_interval = BNXT_TIMER_INTERVAL; |
10835 | ||
caefe526 | 10836 | clear_bit(BNXT_STATE_OPEN, &bp->state); |
c0c050c5 MC |
10837 | return 0; |
10838 | ||
10839 | init_err_release: | |
17086399 | 10840 | bnxt_unmap_bars(bp, pdev); |
c0c050c5 MC |
10841 | pci_release_regions(pdev); |
10842 | ||
10843 | init_err_disable: | |
10844 | pci_disable_device(pdev); | |
10845 | ||
10846 | init_err: | |
10847 | return rc; | |
10848 | } | |
10849 | ||
10850 | /* rtnl_lock held */ | |
10851 | static int bnxt_change_mac_addr(struct net_device *dev, void *p) | |
10852 | { | |
10853 | struct sockaddr *addr = p; | |
1fc2cfd0 JH |
10854 | struct bnxt *bp = netdev_priv(dev); |
10855 | int rc = 0; | |
c0c050c5 MC |
10856 | |
10857 | if (!is_valid_ether_addr(addr->sa_data)) | |
10858 | return -EADDRNOTAVAIL; | |
10859 | ||
c1a7bdff MC |
10860 | if (ether_addr_equal(addr->sa_data, dev->dev_addr)) |
10861 | return 0; | |
10862 | ||
28ea334b | 10863 | rc = bnxt_approve_mac(bp, addr->sa_data, true); |
84c33dd3 MC |
10864 | if (rc) |
10865 | return rc; | |
bdd4347b | 10866 | |
c0c050c5 | 10867 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
1fc2cfd0 JH |
10868 | if (netif_running(dev)) { |
10869 | bnxt_close_nic(bp, false, false); | |
10870 | rc = bnxt_open_nic(bp, false, false); | |
10871 | } | |
c0c050c5 | 10872 | |
1fc2cfd0 | 10873 | return rc; |
c0c050c5 MC |
10874 | } |
10875 | ||
10876 | /* rtnl_lock held */ | |
10877 | static int bnxt_change_mtu(struct net_device *dev, int new_mtu) | |
10878 | { | |
10879 | struct bnxt *bp = netdev_priv(dev); | |
10880 | ||
c0c050c5 MC |
10881 | if (netif_running(dev)) |
10882 | bnxt_close_nic(bp, false, false); | |
10883 | ||
10884 | dev->mtu = new_mtu; | |
10885 | bnxt_set_ring_params(bp); | |
10886 | ||
10887 | if (netif_running(dev)) | |
10888 | return bnxt_open_nic(bp, false, false); | |
10889 | ||
10890 | return 0; | |
10891 | } | |
10892 | ||
c5e3deb8 | 10893 | int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) |
c0c050c5 MC |
10894 | { |
10895 | struct bnxt *bp = netdev_priv(dev); | |
3ffb6a39 | 10896 | bool sh = false; |
d1e7925e | 10897 | int rc; |
16e5cc64 | 10898 | |
c0c050c5 | 10899 | if (tc > bp->max_tc) { |
b451c8b6 | 10900 | netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", |
c0c050c5 MC |
10901 | tc, bp->max_tc); |
10902 | return -EINVAL; | |
10903 | } | |
10904 | ||
10905 | if (netdev_get_num_tc(dev) == tc) | |
10906 | return 0; | |
10907 | ||
3ffb6a39 MC |
10908 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
10909 | sh = true; | |
10910 | ||
98fdbe73 MC |
10911 | rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, |
10912 | sh, tc, bp->tx_nr_rings_xdp); | |
d1e7925e MC |
10913 | if (rc) |
10914 | return rc; | |
c0c050c5 MC |
10915 | |
10916 | /* Needs to close the device and do hw resource re-allocations */ | |
10917 | if (netif_running(bp->dev)) | |
10918 | bnxt_close_nic(bp, true, false); | |
10919 | ||
10920 | if (tc) { | |
10921 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; | |
10922 | netdev_set_num_tc(dev, tc); | |
10923 | } else { | |
10924 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
10925 | netdev_reset_tc(dev); | |
10926 | } | |
87e9b377 | 10927 | bp->tx_nr_rings += bp->tx_nr_rings_xdp; |
3ffb6a39 MC |
10928 | bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : |
10929 | bp->tx_nr_rings + bp->rx_nr_rings; | |
c0c050c5 MC |
10930 | |
10931 | if (netif_running(bp->dev)) | |
10932 | return bnxt_open_nic(bp, true, false); | |
10933 | ||
10934 | return 0; | |
10935 | } | |
10936 | ||
9e0fd15d JP |
10937 | static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
10938 | void *cb_priv) | |
c5e3deb8 | 10939 | { |
9e0fd15d | 10940 | struct bnxt *bp = cb_priv; |
de4784ca | 10941 | |
312324f1 JK |
10942 | if (!bnxt_tc_flower_enabled(bp) || |
10943 | !tc_cls_can_offload_and_chain0(bp->dev, type_data)) | |
38cf0426 | 10944 | return -EOPNOTSUPP; |
c5e3deb8 | 10945 | |
9e0fd15d JP |
10946 | switch (type) { |
10947 | case TC_SETUP_CLSFLOWER: | |
10948 | return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); | |
10949 | default: | |
10950 | return -EOPNOTSUPP; | |
10951 | } | |
10952 | } | |
10953 | ||
627c89d0 | 10954 | LIST_HEAD(bnxt_block_cb_list); |
955bcb6e | 10955 | |
2ae7408f SP |
10956 | static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, |
10957 | void *type_data) | |
10958 | { | |
4e95bc26 PNA |
10959 | struct bnxt *bp = netdev_priv(dev); |
10960 | ||
2ae7408f | 10961 | switch (type) { |
9e0fd15d | 10962 | case TC_SETUP_BLOCK: |
955bcb6e PNA |
10963 | return flow_block_cb_setup_simple(type_data, |
10964 | &bnxt_block_cb_list, | |
4e95bc26 PNA |
10965 | bnxt_setup_tc_block_cb, |
10966 | bp, bp, true); | |
575ed7d3 | 10967 | case TC_SETUP_QDISC_MQPRIO: { |
2ae7408f SP |
10968 | struct tc_mqprio_qopt *mqprio = type_data; |
10969 | ||
10970 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; | |
56f36acd | 10971 | |
2ae7408f SP |
10972 | return bnxt_setup_mq_tc(dev, mqprio->num_tc); |
10973 | } | |
10974 | default: | |
10975 | return -EOPNOTSUPP; | |
10976 | } | |
c5e3deb8 MC |
10977 | } |
10978 | ||
c0c050c5 MC |
10979 | #ifdef CONFIG_RFS_ACCEL |
10980 | static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, | |
10981 | struct bnxt_ntuple_filter *f2) | |
10982 | { | |
10983 | struct flow_keys *keys1 = &f1->fkeys; | |
10984 | struct flow_keys *keys2 = &f2->fkeys; | |
10985 | ||
10986 | if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src && | |
10987 | keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst && | |
10988 | keys1->ports.ports == keys2->ports.ports && | |
10989 | keys1->basic.ip_proto == keys2->basic.ip_proto && | |
10990 | keys1->basic.n_proto == keys2->basic.n_proto && | |
61aad724 | 10991 | keys1->control.flags == keys2->control.flags && |
a54c4d74 MC |
10992 | ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && |
10993 | ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) | |
c0c050c5 MC |
10994 | return true; |
10995 | ||
10996 | return false; | |
10997 | } | |
10998 | ||
10999 | static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, | |
11000 | u16 rxq_index, u32 flow_id) | |
11001 | { | |
11002 | struct bnxt *bp = netdev_priv(dev); | |
11003 | struct bnxt_ntuple_filter *fltr, *new_fltr; | |
11004 | struct flow_keys *fkeys; | |
11005 | struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); | |
a54c4d74 | 11006 | int rc = 0, idx, bit_id, l2_idx = 0; |
c0c050c5 MC |
11007 | struct hlist_head *head; |
11008 | ||
a54c4d74 MC |
11009 | if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { |
11010 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; | |
11011 | int off = 0, j; | |
11012 | ||
11013 | netif_addr_lock_bh(dev); | |
11014 | for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { | |
11015 | if (ether_addr_equal(eth->h_dest, | |
11016 | vnic->uc_list + off)) { | |
11017 | l2_idx = j + 1; | |
11018 | break; | |
11019 | } | |
11020 | } | |
11021 | netif_addr_unlock_bh(dev); | |
11022 | if (!l2_idx) | |
11023 | return -EINVAL; | |
11024 | } | |
c0c050c5 MC |
11025 | new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); |
11026 | if (!new_fltr) | |
11027 | return -ENOMEM; | |
11028 | ||
11029 | fkeys = &new_fltr->fkeys; | |
11030 | if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { | |
11031 | rc = -EPROTONOSUPPORT; | |
11032 | goto err_free; | |
11033 | } | |
11034 | ||
dda0e746 MC |
11035 | if ((fkeys->basic.n_proto != htons(ETH_P_IP) && |
11036 | fkeys->basic.n_proto != htons(ETH_P_IPV6)) || | |
c0c050c5 MC |
11037 | ((fkeys->basic.ip_proto != IPPROTO_TCP) && |
11038 | (fkeys->basic.ip_proto != IPPROTO_UDP))) { | |
11039 | rc = -EPROTONOSUPPORT; | |
11040 | goto err_free; | |
11041 | } | |
dda0e746 MC |
11042 | if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && |
11043 | bp->hwrm_spec_code < 0x10601) { | |
11044 | rc = -EPROTONOSUPPORT; | |
11045 | goto err_free; | |
11046 | } | |
61aad724 MC |
11047 | if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) && |
11048 | bp->hwrm_spec_code < 0x10601) { | |
11049 | rc = -EPROTONOSUPPORT; | |
11050 | goto err_free; | |
11051 | } | |
c0c050c5 | 11052 | |
a54c4d74 | 11053 | memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); |
c0c050c5 MC |
11054 | memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); |
11055 | ||
11056 | idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; | |
11057 | head = &bp->ntp_fltr_hash_tbl[idx]; | |
11058 | rcu_read_lock(); | |
11059 | hlist_for_each_entry_rcu(fltr, head, hash) { | |
11060 | if (bnxt_fltr_match(fltr, new_fltr)) { | |
11061 | rcu_read_unlock(); | |
11062 | rc = 0; | |
11063 | goto err_free; | |
11064 | } | |
11065 | } | |
11066 | rcu_read_unlock(); | |
11067 | ||
11068 | spin_lock_bh(&bp->ntp_fltr_lock); | |
84e86b98 MC |
11069 | bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, |
11070 | BNXT_NTP_FLTR_MAX_FLTR, 0); | |
11071 | if (bit_id < 0) { | |
c0c050c5 MC |
11072 | spin_unlock_bh(&bp->ntp_fltr_lock); |
11073 | rc = -ENOMEM; | |
11074 | goto err_free; | |
11075 | } | |
11076 | ||
84e86b98 | 11077 | new_fltr->sw_id = (u16)bit_id; |
c0c050c5 | 11078 | new_fltr->flow_id = flow_id; |
a54c4d74 | 11079 | new_fltr->l2_fltr_idx = l2_idx; |
c0c050c5 MC |
11080 | new_fltr->rxq = rxq_index; |
11081 | hlist_add_head_rcu(&new_fltr->hash, head); | |
11082 | bp->ntp_fltr_count++; | |
11083 | spin_unlock_bh(&bp->ntp_fltr_lock); | |
11084 | ||
11085 | set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); | |
c213eae8 | 11086 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
11087 | |
11088 | return new_fltr->sw_id; | |
11089 | ||
11090 | err_free: | |
11091 | kfree(new_fltr); | |
11092 | return rc; | |
11093 | } | |
11094 | ||
11095 | static void bnxt_cfg_ntp_filters(struct bnxt *bp) | |
11096 | { | |
11097 | int i; | |
11098 | ||
11099 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { | |
11100 | struct hlist_head *head; | |
11101 | struct hlist_node *tmp; | |
11102 | struct bnxt_ntuple_filter *fltr; | |
11103 | int rc; | |
11104 | ||
11105 | head = &bp->ntp_fltr_hash_tbl[i]; | |
11106 | hlist_for_each_entry_safe(fltr, tmp, head, hash) { | |
11107 | bool del = false; | |
11108 | ||
11109 | if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { | |
11110 | if (rps_may_expire_flow(bp->dev, fltr->rxq, | |
11111 | fltr->flow_id, | |
11112 | fltr->sw_id)) { | |
11113 | bnxt_hwrm_cfa_ntuple_filter_free(bp, | |
11114 | fltr); | |
11115 | del = true; | |
11116 | } | |
11117 | } else { | |
11118 | rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, | |
11119 | fltr); | |
11120 | if (rc) | |
11121 | del = true; | |
11122 | else | |
11123 | set_bit(BNXT_FLTR_VALID, &fltr->state); | |
11124 | } | |
11125 | ||
11126 | if (del) { | |
11127 | spin_lock_bh(&bp->ntp_fltr_lock); | |
11128 | hlist_del_rcu(&fltr->hash); | |
11129 | bp->ntp_fltr_count--; | |
11130 | spin_unlock_bh(&bp->ntp_fltr_lock); | |
11131 | synchronize_rcu(); | |
11132 | clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); | |
11133 | kfree(fltr); | |
11134 | } | |
11135 | } | |
11136 | } | |
19241368 JH |
11137 | if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) |
11138 | netdev_info(bp->dev, "Receive PF driver unload event!"); | |
c0c050c5 MC |
11139 | } |
11140 | ||
11141 | #else | |
11142 | ||
11143 | static void bnxt_cfg_ntp_filters(struct bnxt *bp) | |
11144 | { | |
11145 | } | |
11146 | ||
11147 | #endif /* CONFIG_RFS_ACCEL */ | |
11148 | ||
ad51b8e9 AD |
11149 | static void bnxt_udp_tunnel_add(struct net_device *dev, |
11150 | struct udp_tunnel_info *ti) | |
c0c050c5 MC |
11151 | { |
11152 | struct bnxt *bp = netdev_priv(dev); | |
11153 | ||
ad51b8e9 | 11154 | if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) |
c0c050c5 MC |
11155 | return; |
11156 | ||
ad51b8e9 | 11157 | if (!netif_running(dev)) |
c0c050c5 MC |
11158 | return; |
11159 | ||
ad51b8e9 AD |
11160 | switch (ti->type) { |
11161 | case UDP_TUNNEL_TYPE_VXLAN: | |
11162 | if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) | |
11163 | return; | |
c0c050c5 | 11164 | |
ad51b8e9 AD |
11165 | bp->vxlan_port_cnt++; |
11166 | if (bp->vxlan_port_cnt == 1) { | |
11167 | bp->vxlan_port = ti->port; | |
11168 | set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); | |
c213eae8 | 11169 | bnxt_queue_sp_work(bp); |
ad51b8e9 AD |
11170 | } |
11171 | break; | |
7cdd5fc3 AD |
11172 | case UDP_TUNNEL_TYPE_GENEVE: |
11173 | if (bp->nge_port_cnt && bp->nge_port != ti->port) | |
11174 | return; | |
11175 | ||
11176 | bp->nge_port_cnt++; | |
11177 | if (bp->nge_port_cnt == 1) { | |
11178 | bp->nge_port = ti->port; | |
11179 | set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); | |
11180 | } | |
11181 | break; | |
ad51b8e9 AD |
11182 | default: |
11183 | return; | |
c0c050c5 | 11184 | } |
ad51b8e9 | 11185 | |
c213eae8 | 11186 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
11187 | } |
11188 | ||
ad51b8e9 AD |
11189 | static void bnxt_udp_tunnel_del(struct net_device *dev, |
11190 | struct udp_tunnel_info *ti) | |
c0c050c5 MC |
11191 | { |
11192 | struct bnxt *bp = netdev_priv(dev); | |
11193 | ||
ad51b8e9 | 11194 | if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) |
c0c050c5 MC |
11195 | return; |
11196 | ||
ad51b8e9 | 11197 | if (!netif_running(dev)) |
c0c050c5 MC |
11198 | return; |
11199 | ||
ad51b8e9 AD |
11200 | switch (ti->type) { |
11201 | case UDP_TUNNEL_TYPE_VXLAN: | |
11202 | if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) | |
11203 | return; | |
c0c050c5 MC |
11204 | bp->vxlan_port_cnt--; |
11205 | ||
ad51b8e9 AD |
11206 | if (bp->vxlan_port_cnt != 0) |
11207 | return; | |
11208 | ||
11209 | set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); | |
11210 | break; | |
7cdd5fc3 AD |
11211 | case UDP_TUNNEL_TYPE_GENEVE: |
11212 | if (!bp->nge_port_cnt || bp->nge_port != ti->port) | |
11213 | return; | |
11214 | bp->nge_port_cnt--; | |
11215 | ||
11216 | if (bp->nge_port_cnt != 0) | |
11217 | return; | |
11218 | ||
11219 | set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); | |
11220 | break; | |
ad51b8e9 AD |
11221 | default: |
11222 | return; | |
c0c050c5 | 11223 | } |
ad51b8e9 | 11224 | |
c213eae8 | 11225 | bnxt_queue_sp_work(bp); |
c0c050c5 MC |
11226 | } |
11227 | ||
39d8ba2e MC |
11228 | static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, |
11229 | struct net_device *dev, u32 filter_mask, | |
11230 | int nlflags) | |
11231 | { | |
11232 | struct bnxt *bp = netdev_priv(dev); | |
11233 | ||
11234 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, | |
11235 | nlflags, filter_mask, NULL); | |
11236 | } | |
11237 | ||
11238 | static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, | |
2fd527b7 | 11239 | u16 flags, struct netlink_ext_ack *extack) |
39d8ba2e MC |
11240 | { |
11241 | struct bnxt *bp = netdev_priv(dev); | |
11242 | struct nlattr *attr, *br_spec; | |
11243 | int rem, rc = 0; | |
11244 | ||
11245 | if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) | |
11246 | return -EOPNOTSUPP; | |
11247 | ||
11248 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
11249 | if (!br_spec) | |
11250 | return -EINVAL; | |
11251 | ||
11252 | nla_for_each_nested(attr, br_spec, rem) { | |
11253 | u16 mode; | |
11254 | ||
11255 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
11256 | continue; | |
11257 | ||
11258 | if (nla_len(attr) < sizeof(mode)) | |
11259 | return -EINVAL; | |
11260 | ||
11261 | mode = nla_get_u16(attr); | |
11262 | if (mode == bp->br_mode) | |
11263 | break; | |
11264 | ||
11265 | rc = bnxt_hwrm_set_br_mode(bp, mode); | |
11266 | if (!rc) | |
11267 | bp->br_mode = mode; | |
11268 | break; | |
11269 | } | |
11270 | return rc; | |
11271 | } | |
11272 | ||
52d5254a FF |
11273 | int bnxt_get_port_parent_id(struct net_device *dev, |
11274 | struct netdev_phys_item_id *ppid) | |
c124a62f | 11275 | { |
52d5254a FF |
11276 | struct bnxt *bp = netdev_priv(dev); |
11277 | ||
c124a62f SP |
11278 | if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) |
11279 | return -EOPNOTSUPP; | |
11280 | ||
11281 | /* The PF and it's VF-reps only support the switchdev framework */ | |
11282 | if (!BNXT_PF(bp)) | |
11283 | return -EOPNOTSUPP; | |
11284 | ||
52d5254a FF |
11285 | ppid->id_len = sizeof(bp->switch_id); |
11286 | memcpy(ppid->id, bp->switch_id, ppid->id_len); | |
c124a62f | 11287 | |
52d5254a | 11288 | return 0; |
c124a62f SP |
11289 | } |
11290 | ||
c9c49a65 JP |
11291 | static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) |
11292 | { | |
11293 | struct bnxt *bp = netdev_priv(dev); | |
11294 | ||
11295 | return &bp->dl_port; | |
11296 | } | |
11297 | ||
c0c050c5 MC |
11298 | static const struct net_device_ops bnxt_netdev_ops = { |
11299 | .ndo_open = bnxt_open, | |
11300 | .ndo_start_xmit = bnxt_start_xmit, | |
11301 | .ndo_stop = bnxt_close, | |
11302 | .ndo_get_stats64 = bnxt_get_stats64, | |
11303 | .ndo_set_rx_mode = bnxt_set_rx_mode, | |
11304 | .ndo_do_ioctl = bnxt_ioctl, | |
11305 | .ndo_validate_addr = eth_validate_addr, | |
11306 | .ndo_set_mac_address = bnxt_change_mac_addr, | |
11307 | .ndo_change_mtu = bnxt_change_mtu, | |
11308 | .ndo_fix_features = bnxt_fix_features, | |
11309 | .ndo_set_features = bnxt_set_features, | |
11310 | .ndo_tx_timeout = bnxt_tx_timeout, | |
11311 | #ifdef CONFIG_BNXT_SRIOV | |
11312 | .ndo_get_vf_config = bnxt_get_vf_config, | |
11313 | .ndo_set_vf_mac = bnxt_set_vf_mac, | |
11314 | .ndo_set_vf_vlan = bnxt_set_vf_vlan, | |
11315 | .ndo_set_vf_rate = bnxt_set_vf_bw, | |
11316 | .ndo_set_vf_link_state = bnxt_set_vf_link_state, | |
11317 | .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, | |
746df139 | 11318 | .ndo_set_vf_trust = bnxt_set_vf_trust, |
c0c050c5 MC |
11319 | #endif |
11320 | .ndo_setup_tc = bnxt_setup_tc, | |
11321 | #ifdef CONFIG_RFS_ACCEL | |
11322 | .ndo_rx_flow_steer = bnxt_rx_flow_steer, | |
11323 | #endif | |
ad51b8e9 AD |
11324 | .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, |
11325 | .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, | |
f4e63525 | 11326 | .ndo_bpf = bnxt_xdp, |
f18c2b77 | 11327 | .ndo_xdp_xmit = bnxt_xdp_xmit, |
39d8ba2e MC |
11328 | .ndo_bridge_getlink = bnxt_bridge_getlink, |
11329 | .ndo_bridge_setlink = bnxt_bridge_setlink, | |
c9c49a65 | 11330 | .ndo_get_devlink_port = bnxt_get_devlink_port, |
c0c050c5 MC |
11331 | }; |
11332 | ||
11333 | static void bnxt_remove_one(struct pci_dev *pdev) | |
11334 | { | |
11335 | struct net_device *dev = pci_get_drvdata(pdev); | |
11336 | struct bnxt *bp = netdev_priv(dev); | |
11337 | ||
4ab0c6a8 | 11338 | if (BNXT_PF(bp)) { |
c0c050c5 | 11339 | bnxt_sriov_disable(bp); |
4ab0c6a8 SP |
11340 | bnxt_dl_unregister(bp); |
11341 | } | |
c0c050c5 | 11342 | |
6316ea6d | 11343 | pci_disable_pcie_error_reporting(pdev); |
c0c050c5 | 11344 | unregister_netdev(dev); |
2ae7408f | 11345 | bnxt_shutdown_tc(bp); |
c213eae8 | 11346 | bnxt_cancel_sp_work(bp); |
c0c050c5 MC |
11347 | bp->sp_event = 0; |
11348 | ||
7809592d | 11349 | bnxt_clear_int_mode(bp); |
be58a0da | 11350 | bnxt_hwrm_func_drv_unrgtr(bp); |
c0c050c5 | 11351 | bnxt_free_hwrm_resources(bp); |
e605db80 | 11352 | bnxt_free_hwrm_short_cmd_req(bp); |
eb513658 | 11353 | bnxt_ethtool_free(bp); |
7df4ae9f | 11354 | bnxt_dcb_free(bp); |
a588e458 MC |
11355 | kfree(bp->edev); |
11356 | bp->edev = NULL; | |
c20dc142 | 11357 | bnxt_cleanup_pci(bp); |
98f04cf0 MC |
11358 | bnxt_free_ctx_mem(bp); |
11359 | kfree(bp->ctx); | |
11360 | bp->ctx = NULL; | |
fd3ab1c7 | 11361 | bnxt_free_port_stats(bp); |
c0c050c5 | 11362 | free_netdev(dev); |
c0c050c5 MC |
11363 | } |
11364 | ||
ba642ab7 | 11365 | static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) |
c0c050c5 MC |
11366 | { |
11367 | int rc = 0; | |
11368 | struct bnxt_link_info *link_info = &bp->link_info; | |
c0c050c5 | 11369 | |
170ce013 MC |
11370 | rc = bnxt_hwrm_phy_qcaps(bp); |
11371 | if (rc) { | |
11372 | netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", | |
11373 | rc); | |
11374 | return rc; | |
11375 | } | |
c0c050c5 MC |
11376 | rc = bnxt_update_link(bp, false); |
11377 | if (rc) { | |
11378 | netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", | |
11379 | rc); | |
11380 | return rc; | |
11381 | } | |
11382 | ||
93ed8117 MC |
11383 | /* Older firmware does not have supported_auto_speeds, so assume |
11384 | * that all supported speeds can be autonegotiated. | |
11385 | */ | |
11386 | if (link_info->auto_link_speeds && !link_info->support_auto_speeds) | |
11387 | link_info->support_auto_speeds = link_info->support_speeds; | |
11388 | ||
ba642ab7 MC |
11389 | if (!fw_dflt) |
11390 | return 0; | |
11391 | ||
c0c050c5 | 11392 | /*initialize the ethool setting copy with NVM settings */ |
0d8abf02 | 11393 | if (BNXT_AUTO_MODE(link_info->auto_mode)) { |
c9ee9516 MC |
11394 | link_info->autoneg = BNXT_AUTONEG_SPEED; |
11395 | if (bp->hwrm_spec_code >= 0x10201) { | |
11396 | if (link_info->auto_pause_setting & | |
11397 | PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) | |
11398 | link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; | |
11399 | } else { | |
11400 | link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; | |
11401 | } | |
0d8abf02 | 11402 | link_info->advertising = link_info->auto_link_speeds; |
0d8abf02 MC |
11403 | } else { |
11404 | link_info->req_link_speed = link_info->force_link_speed; | |
11405 | link_info->req_duplex = link_info->duplex_setting; | |
c0c050c5 | 11406 | } |
c9ee9516 MC |
11407 | if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) |
11408 | link_info->req_flow_ctrl = | |
11409 | link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; | |
11410 | else | |
11411 | link_info->req_flow_ctrl = link_info->force_pause_setting; | |
ba642ab7 | 11412 | return 0; |
c0c050c5 MC |
11413 | } |
11414 | ||
11415 | static int bnxt_get_max_irq(struct pci_dev *pdev) | |
11416 | { | |
11417 | u16 ctrl; | |
11418 | ||
11419 | if (!pdev->msix_cap) | |
11420 | return 1; | |
11421 | ||
11422 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
11423 | return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; | |
11424 | } | |
11425 | ||
6e6c5a57 MC |
11426 | static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, |
11427 | int *max_cp) | |
c0c050c5 | 11428 | { |
6a4f2947 | 11429 | struct bnxt_hw_resc *hw_resc = &bp->hw_resc; |
e30fbc33 | 11430 | int max_ring_grps = 0, max_irq; |
c0c050c5 | 11431 | |
6a4f2947 MC |
11432 | *max_tx = hw_resc->max_tx_rings; |
11433 | *max_rx = hw_resc->max_rx_rings; | |
e30fbc33 MC |
11434 | *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); |
11435 | max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - | |
11436 | bnxt_get_ulp_msix_num(bp), | |
c027c6b4 | 11437 | hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); |
e30fbc33 MC |
11438 | if (!(bp->flags & BNXT_FLAG_CHIP_P5)) |
11439 | *max_cp = min_t(int, *max_cp, max_irq); | |
6a4f2947 | 11440 | max_ring_grps = hw_resc->max_hw_ring_grps; |
76595193 PS |
11441 | if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { |
11442 | *max_cp -= 1; | |
11443 | *max_rx -= 2; | |
11444 | } | |
c0c050c5 MC |
11445 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
11446 | *max_rx >>= 1; | |
e30fbc33 MC |
11447 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
11448 | bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); | |
11449 | /* On P5 chips, max_cp output param should be available NQs */ | |
11450 | *max_cp = max_irq; | |
11451 | } | |
b72d4a68 | 11452 | *max_rx = min_t(int, *max_rx, max_ring_grps); |
6e6c5a57 MC |
11453 | } |
11454 | ||
11455 | int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) | |
11456 | { | |
11457 | int rx, tx, cp; | |
11458 | ||
11459 | _bnxt_get_max_rings(bp, &rx, &tx, &cp); | |
78f058a4 MC |
11460 | *max_rx = rx; |
11461 | *max_tx = tx; | |
6e6c5a57 MC |
11462 | if (!rx || !tx || !cp) |
11463 | return -ENOMEM; | |
11464 | ||
6e6c5a57 MC |
11465 | return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); |
11466 | } | |
11467 | ||
e4060d30 MC |
11468 | static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, |
11469 | bool shared) | |
11470 | { | |
11471 | int rc; | |
11472 | ||
11473 | rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); | |
bdbd1eb5 MC |
11474 | if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { |
11475 | /* Not enough rings, try disabling agg rings. */ | |
11476 | bp->flags &= ~BNXT_FLAG_AGG_RINGS; | |
11477 | rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); | |
07f4fde5 MC |
11478 | if (rc) { |
11479 | /* set BNXT_FLAG_AGG_RINGS back for consistency */ | |
11480 | bp->flags |= BNXT_FLAG_AGG_RINGS; | |
bdbd1eb5 | 11481 | return rc; |
07f4fde5 | 11482 | } |
bdbd1eb5 | 11483 | bp->flags |= BNXT_FLAG_NO_AGG_RINGS; |
1054aee8 MC |
11484 | bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); |
11485 | bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); | |
bdbd1eb5 MC |
11486 | bnxt_set_ring_params(bp); |
11487 | } | |
e4060d30 MC |
11488 | |
11489 | if (bp->flags & BNXT_FLAG_ROCE_CAP) { | |
11490 | int max_cp, max_stat, max_irq; | |
11491 | ||
11492 | /* Reserve minimum resources for RoCE */ | |
11493 | max_cp = bnxt_get_max_func_cp_rings(bp); | |
11494 | max_stat = bnxt_get_max_func_stat_ctxs(bp); | |
11495 | max_irq = bnxt_get_max_func_irqs(bp); | |
11496 | if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || | |
11497 | max_irq <= BNXT_MIN_ROCE_CP_RINGS || | |
11498 | max_stat <= BNXT_MIN_ROCE_STAT_CTXS) | |
11499 | return 0; | |
11500 | ||
11501 | max_cp -= BNXT_MIN_ROCE_CP_RINGS; | |
11502 | max_irq -= BNXT_MIN_ROCE_CP_RINGS; | |
11503 | max_stat -= BNXT_MIN_ROCE_STAT_CTXS; | |
11504 | max_cp = min_t(int, max_cp, max_irq); | |
11505 | max_cp = min_t(int, max_cp, max_stat); | |
11506 | rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); | |
11507 | if (rc) | |
11508 | rc = 0; | |
11509 | } | |
11510 | return rc; | |
11511 | } | |
11512 | ||
58ea801a MC |
11513 | /* In initial default shared ring setting, each shared ring must have a |
11514 | * RX/TX ring pair. | |
11515 | */ | |
11516 | static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) | |
11517 | { | |
11518 | bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); | |
11519 | bp->rx_nr_rings = bp->cp_nr_rings; | |
11520 | bp->tx_nr_rings_per_tc = bp->cp_nr_rings; | |
11521 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
11522 | } | |
11523 | ||
702c221c | 11524 | static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) |
6e6c5a57 MC |
11525 | { |
11526 | int dflt_rings, max_rx_rings, max_tx_rings, rc; | |
6e6c5a57 | 11527 | |
2773dfb2 MC |
11528 | if (!bnxt_can_reserve_rings(bp)) |
11529 | return 0; | |
11530 | ||
6e6c5a57 MC |
11531 | if (sh) |
11532 | bp->flags |= BNXT_FLAG_SHARED_RINGS; | |
d629522e | 11533 | dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); |
1d3ef13d MC |
11534 | /* Reduce default rings on multi-port cards so that total default |
11535 | * rings do not exceed CPU count. | |
11536 | */ | |
11537 | if (bp->port_count > 1) { | |
11538 | int max_rings = | |
11539 | max_t(int, num_online_cpus() / bp->port_count, 1); | |
11540 | ||
11541 | dflt_rings = min_t(int, dflt_rings, max_rings); | |
11542 | } | |
e4060d30 | 11543 | rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); |
6e6c5a57 MC |
11544 | if (rc) |
11545 | return rc; | |
11546 | bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); | |
11547 | bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); | |
58ea801a MC |
11548 | if (sh) |
11549 | bnxt_trim_dflt_sh_rings(bp); | |
11550 | else | |
11551 | bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; | |
11552 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
391be5c2 | 11553 | |
674f50a5 | 11554 | rc = __bnxt_reserve_rings(bp); |
391be5c2 MC |
11555 | if (rc) |
11556 | netdev_warn(bp->dev, "Unable to reserve tx rings\n"); | |
58ea801a MC |
11557 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
11558 | if (sh) | |
11559 | bnxt_trim_dflt_sh_rings(bp); | |
391be5c2 | 11560 | |
674f50a5 MC |
11561 | /* Rings may have been trimmed, re-reserve the trimmed rings. */ |
11562 | if (bnxt_need_reserve_rings(bp)) { | |
11563 | rc = __bnxt_reserve_rings(bp); | |
11564 | if (rc) | |
11565 | netdev_warn(bp->dev, "2nd rings reservation failed.\n"); | |
11566 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
11567 | } | |
76595193 PS |
11568 | if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { |
11569 | bp->rx_nr_rings++; | |
11570 | bp->cp_nr_rings++; | |
11571 | } | |
6e6c5a57 | 11572 | return rc; |
c0c050c5 MC |
11573 | } |
11574 | ||
47558acd MC |
11575 | static int bnxt_init_dflt_ring_mode(struct bnxt *bp) |
11576 | { | |
11577 | int rc; | |
11578 | ||
11579 | if (bp->tx_nr_rings) | |
11580 | return 0; | |
11581 | ||
6b95c3e9 MC |
11582 | bnxt_ulp_irq_stop(bp); |
11583 | bnxt_clear_int_mode(bp); | |
47558acd MC |
11584 | rc = bnxt_set_dflt_rings(bp, true); |
11585 | if (rc) { | |
11586 | netdev_err(bp->dev, "Not enough rings available.\n"); | |
6b95c3e9 | 11587 | goto init_dflt_ring_err; |
47558acd MC |
11588 | } |
11589 | rc = bnxt_init_int_mode(bp); | |
11590 | if (rc) | |
6b95c3e9 MC |
11591 | goto init_dflt_ring_err; |
11592 | ||
47558acd MC |
11593 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
11594 | if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { | |
11595 | bp->flags |= BNXT_FLAG_RFS; | |
11596 | bp->dev->features |= NETIF_F_NTUPLE; | |
11597 | } | |
6b95c3e9 MC |
11598 | init_dflt_ring_err: |
11599 | bnxt_ulp_irq_restart(bp, rc); | |
11600 | return rc; | |
47558acd MC |
11601 | } |
11602 | ||
80fcaf46 | 11603 | int bnxt_restore_pf_fw_resources(struct bnxt *bp) |
7b08f661 | 11604 | { |
80fcaf46 MC |
11605 | int rc; |
11606 | ||
7b08f661 MC |
11607 | ASSERT_RTNL(); |
11608 | bnxt_hwrm_func_qcaps(bp); | |
1a037782 VD |
11609 | |
11610 | if (netif_running(bp->dev)) | |
11611 | __bnxt_close_nic(bp, true, false); | |
11612 | ||
ec86f14e | 11613 | bnxt_ulp_irq_stop(bp); |
80fcaf46 MC |
11614 | bnxt_clear_int_mode(bp); |
11615 | rc = bnxt_init_int_mode(bp); | |
ec86f14e | 11616 | bnxt_ulp_irq_restart(bp, rc); |
1a037782 VD |
11617 | |
11618 | if (netif_running(bp->dev)) { | |
11619 | if (rc) | |
11620 | dev_close(bp->dev); | |
11621 | else | |
11622 | rc = bnxt_open_nic(bp, true, false); | |
11623 | } | |
11624 | ||
80fcaf46 | 11625 | return rc; |
7b08f661 MC |
11626 | } |
11627 | ||
a22a6ac2 MC |
11628 | static int bnxt_init_mac_addr(struct bnxt *bp) |
11629 | { | |
11630 | int rc = 0; | |
11631 | ||
11632 | if (BNXT_PF(bp)) { | |
11633 | memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); | |
11634 | } else { | |
11635 | #ifdef CONFIG_BNXT_SRIOV | |
11636 | struct bnxt_vf_info *vf = &bp->vf; | |
28ea334b | 11637 | bool strict_approval = true; |
a22a6ac2 MC |
11638 | |
11639 | if (is_valid_ether_addr(vf->mac_addr)) { | |
91cdda40 | 11640 | /* overwrite netdev dev_addr with admin VF MAC */ |
a22a6ac2 | 11641 | memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); |
28ea334b MC |
11642 | /* Older PF driver or firmware may not approve this |
11643 | * correctly. | |
11644 | */ | |
11645 | strict_approval = false; | |
a22a6ac2 MC |
11646 | } else { |
11647 | eth_hw_addr_random(bp->dev); | |
a22a6ac2 | 11648 | } |
28ea334b | 11649 | rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); |
a22a6ac2 MC |
11650 | #endif |
11651 | } | |
11652 | return rc; | |
11653 | } | |
11654 | ||
03213a99 JP |
11655 | static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) |
11656 | { | |
11657 | struct pci_dev *pdev = bp->pdev; | |
11658 | int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN); | |
11659 | u32 dw; | |
11660 | ||
11661 | if (!pos) { | |
11662 | netdev_info(bp->dev, "Unable do read adapter's DSN"); | |
11663 | return -EOPNOTSUPP; | |
11664 | } | |
11665 | ||
11666 | /* DSN (two dw) is at an offset of 4 from the cap pos */ | |
11667 | pos += 4; | |
11668 | pci_read_config_dword(pdev, pos, &dw); | |
11669 | put_unaligned_le32(dw, &dsn[0]); | |
11670 | pci_read_config_dword(pdev, pos + 4, &dw); | |
11671 | put_unaligned_le32(dw, &dsn[4]); | |
11672 | return 0; | |
11673 | } | |
11674 | ||
c0c050c5 MC |
11675 | static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
11676 | { | |
11677 | static int version_printed; | |
11678 | struct net_device *dev; | |
11679 | struct bnxt *bp; | |
6e6c5a57 | 11680 | int rc, max_irqs; |
c0c050c5 | 11681 | |
4e00338a | 11682 | if (pci_is_bridge(pdev)) |
fa853dda PS |
11683 | return -ENODEV; |
11684 | ||
c0c050c5 MC |
11685 | if (version_printed++ == 0) |
11686 | pr_info("%s", version); | |
11687 | ||
11688 | max_irqs = bnxt_get_max_irq(pdev); | |
11689 | dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); | |
11690 | if (!dev) | |
11691 | return -ENOMEM; | |
11692 | ||
11693 | bp = netdev_priv(dev); | |
9c1fabdf | 11694 | bnxt_set_max_func_irqs(bp, max_irqs); |
c0c050c5 MC |
11695 | |
11696 | if (bnxt_vf_pciid(ent->driver_data)) | |
11697 | bp->flags |= BNXT_FLAG_VF; | |
11698 | ||
2bcfa6f6 | 11699 | if (pdev->msix_cap) |
c0c050c5 | 11700 | bp->flags |= BNXT_FLAG_MSIX_CAP; |
c0c050c5 MC |
11701 | |
11702 | rc = bnxt_init_board(pdev, dev); | |
11703 | if (rc < 0) | |
11704 | goto init_err_free; | |
11705 | ||
11706 | dev->netdev_ops = &bnxt_netdev_ops; | |
11707 | dev->watchdog_timeo = BNXT_TX_TIMEOUT; | |
11708 | dev->ethtool_ops = &bnxt_ethtool_ops; | |
c0c050c5 MC |
11709 | pci_set_drvdata(pdev, dev); |
11710 | ||
3e8060fa PS |
11711 | rc = bnxt_alloc_hwrm_resources(bp); |
11712 | if (rc) | |
17086399 | 11713 | goto init_err_pci_clean; |
3e8060fa PS |
11714 | |
11715 | mutex_init(&bp->hwrm_cmd_lock); | |
ba642ab7 | 11716 | mutex_init(&bp->link_lock); |
7c380918 MC |
11717 | |
11718 | rc = bnxt_fw_init_one_p1(bp); | |
3e8060fa | 11719 | if (rc) |
17086399 | 11720 | goto init_err_pci_clean; |
3e8060fa | 11721 | |
e38287b7 MC |
11722 | if (BNXT_CHIP_P5(bp)) |
11723 | bp->flags |= BNXT_FLAG_CHIP_P5; | |
11724 | ||
7c380918 | 11725 | rc = bnxt_fw_init_one_p2(bp); |
3c2217a6 MC |
11726 | if (rc) |
11727 | goto init_err_pci_clean; | |
11728 | ||
c0c050c5 MC |
11729 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | |
11730 | NETIF_F_TSO | NETIF_F_TSO6 | | |
11731 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | | |
7e13318d | 11732 | NETIF_F_GSO_IPXIP4 | |
152971ee AD |
11733 | NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | |
11734 | NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | | |
3e8060fa PS |
11735 | NETIF_F_RXCSUM | NETIF_F_GRO; |
11736 | ||
e38287b7 | 11737 | if (BNXT_SUPPORTS_TPA(bp)) |
3e8060fa | 11738 | dev->hw_features |= NETIF_F_LRO; |
c0c050c5 | 11739 | |
c0c050c5 MC |
11740 | dev->hw_enc_features = |
11741 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | |
11742 | NETIF_F_TSO | NETIF_F_TSO6 | | |
11743 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | | |
152971ee | 11744 | NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | |
7e13318d | 11745 | NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; |
152971ee AD |
11746 | dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | |
11747 | NETIF_F_GSO_GRE_CSUM; | |
c0c050c5 MC |
11748 | dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; |
11749 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | | |
11750 | NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; | |
e38287b7 | 11751 | if (BNXT_SUPPORTS_TPA(bp)) |
1054aee8 | 11752 | dev->hw_features |= NETIF_F_GRO_HW; |
c0c050c5 | 11753 | dev->features |= dev->hw_features | NETIF_F_HIGHDMA; |
1054aee8 MC |
11754 | if (dev->features & NETIF_F_GRO_HW) |
11755 | dev->features &= ~NETIF_F_LRO; | |
c0c050c5 MC |
11756 | dev->priv_flags |= IFF_UNICAST_FLT; |
11757 | ||
11758 | #ifdef CONFIG_BNXT_SRIOV | |
11759 | init_waitqueue_head(&bp->sriov_cfg_wait); | |
4ab0c6a8 | 11760 | mutex_init(&bp->sriov_lock); |
c0c050c5 | 11761 | #endif |
e38287b7 MC |
11762 | if (BNXT_SUPPORTS_TPA(bp)) { |
11763 | bp->gro_func = bnxt_gro_func_5730x; | |
67912c36 | 11764 | if (BNXT_CHIP_P4(bp)) |
e38287b7 | 11765 | bp->gro_func = bnxt_gro_func_5731x; |
67912c36 MC |
11766 | else if (BNXT_CHIP_P5(bp)) |
11767 | bp->gro_func = bnxt_gro_func_5750x; | |
e38287b7 MC |
11768 | } |
11769 | if (!BNXT_CHIP_P4_PLUS(bp)) | |
434c975a | 11770 | bp->flags |= BNXT_FLAG_DOUBLE_DB; |
309369c9 | 11771 | |
a588e458 MC |
11772 | bp->ulp_probe = bnxt_ulp_probe; |
11773 | ||
a22a6ac2 MC |
11774 | rc = bnxt_init_mac_addr(bp); |
11775 | if (rc) { | |
11776 | dev_err(&pdev->dev, "Unable to initialize mac address.\n"); | |
11777 | rc = -EADDRNOTAVAIL; | |
11778 | goto init_err_pci_clean; | |
11779 | } | |
c0c050c5 | 11780 | |
2e9217d1 VV |
11781 | if (BNXT_PF(bp)) { |
11782 | /* Read the adapter's DSN to use as the eswitch switch_id */ | |
11783 | rc = bnxt_pcie_dsn_get(bp, bp->switch_id); | |
11784 | if (rc) | |
11785 | goto init_err_pci_clean; | |
11786 | } | |
567b2abe | 11787 | |
7eb9bb3a MC |
11788 | /* MTU range: 60 - FW defined max */ |
11789 | dev->min_mtu = ETH_ZLEN; | |
11790 | dev->max_mtu = bp->max_mtu; | |
11791 | ||
ba642ab7 | 11792 | rc = bnxt_probe_phy(bp, true); |
d5430d31 MC |
11793 | if (rc) |
11794 | goto init_err_pci_clean; | |
11795 | ||
c61fb99c | 11796 | bnxt_set_rx_skb_mode(bp, false); |
c0c050c5 MC |
11797 | bnxt_set_tpa_flags(bp); |
11798 | bnxt_set_ring_params(bp); | |
702c221c | 11799 | rc = bnxt_set_dflt_rings(bp, true); |
bdbd1eb5 MC |
11800 | if (rc) { |
11801 | netdev_err(bp->dev, "Not enough rings available.\n"); | |
11802 | rc = -ENOMEM; | |
17086399 | 11803 | goto init_err_pci_clean; |
bdbd1eb5 | 11804 | } |
c0c050c5 | 11805 | |
ba642ab7 | 11806 | bnxt_fw_init_one_p3(bp); |
2bcfa6f6 | 11807 | |
c0c050c5 MC |
11808 | if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) |
11809 | bp->flags |= BNXT_FLAG_STRIP_VLAN; | |
11810 | ||
7809592d | 11811 | rc = bnxt_init_int_mode(bp); |
c0c050c5 | 11812 | if (rc) |
17086399 | 11813 | goto init_err_pci_clean; |
c0c050c5 | 11814 | |
832aed16 MC |
11815 | /* No TC has been set yet and rings may have been trimmed due to |
11816 | * limited MSIX, so we re-initialize the TX rings per TC. | |
11817 | */ | |
11818 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; | |
11819 | ||
c213eae8 MC |
11820 | if (BNXT_PF(bp)) { |
11821 | if (!bnxt_pf_wq) { | |
11822 | bnxt_pf_wq = | |
11823 | create_singlethread_workqueue("bnxt_pf_wq"); | |
11824 | if (!bnxt_pf_wq) { | |
11825 | dev_err(&pdev->dev, "Unable to create workqueue.\n"); | |
11826 | goto init_err_pci_clean; | |
11827 | } | |
11828 | } | |
2ae7408f | 11829 | bnxt_init_tc(bp); |
c213eae8 | 11830 | } |
2ae7408f | 11831 | |
7809592d MC |
11832 | rc = register_netdev(dev); |
11833 | if (rc) | |
2ae7408f | 11834 | goto init_err_cleanup_tc; |
7809592d | 11835 | |
4ab0c6a8 SP |
11836 | if (BNXT_PF(bp)) |
11837 | bnxt_dl_register(bp); | |
11838 | ||
c0c050c5 MC |
11839 | netdev_info(dev, "%s found at mem %lx, node addr %pM\n", |
11840 | board_info[ent->driver_data].name, | |
11841 | (long)pci_resource_start(pdev, 0), dev->dev_addr); | |
af125b75 | 11842 | pcie_print_link_status(pdev); |
90c4f788 | 11843 | |
c0c050c5 MC |
11844 | return 0; |
11845 | ||
2ae7408f SP |
11846 | init_err_cleanup_tc: |
11847 | bnxt_shutdown_tc(bp); | |
7809592d MC |
11848 | bnxt_clear_int_mode(bp); |
11849 | ||
17086399 | 11850 | init_err_pci_clean: |
f9099d61 | 11851 | bnxt_free_hwrm_short_cmd_req(bp); |
a2bf74f4 | 11852 | bnxt_free_hwrm_resources(bp); |
98f04cf0 MC |
11853 | bnxt_free_ctx_mem(bp); |
11854 | kfree(bp->ctx); | |
11855 | bp->ctx = NULL; | |
07f83d72 MC |
11856 | kfree(bp->fw_health); |
11857 | bp->fw_health = NULL; | |
17086399 | 11858 | bnxt_cleanup_pci(bp); |
c0c050c5 MC |
11859 | |
11860 | init_err_free: | |
11861 | free_netdev(dev); | |
11862 | return rc; | |
11863 | } | |
11864 | ||
d196ece7 MC |
11865 | static void bnxt_shutdown(struct pci_dev *pdev) |
11866 | { | |
11867 | struct net_device *dev = pci_get_drvdata(pdev); | |
11868 | struct bnxt *bp; | |
11869 | ||
11870 | if (!dev) | |
11871 | return; | |
11872 | ||
11873 | rtnl_lock(); | |
11874 | bp = netdev_priv(dev); | |
11875 | if (!bp) | |
11876 | goto shutdown_exit; | |
11877 | ||
11878 | if (netif_running(dev)) | |
11879 | dev_close(dev); | |
11880 | ||
a7f3f939 RJ |
11881 | bnxt_ulp_shutdown(bp); |
11882 | ||
d196ece7 MC |
11883 | if (system_state == SYSTEM_POWER_OFF) { |
11884 | bnxt_clear_int_mode(bp); | |
c20dc142 | 11885 | pci_disable_device(pdev); |
d196ece7 MC |
11886 | pci_wake_from_d3(pdev, bp->wol); |
11887 | pci_set_power_state(pdev, PCI_D3hot); | |
11888 | } | |
11889 | ||
11890 | shutdown_exit: | |
11891 | rtnl_unlock(); | |
11892 | } | |
11893 | ||
f65a2044 MC |
11894 | #ifdef CONFIG_PM_SLEEP |
11895 | static int bnxt_suspend(struct device *device) | |
11896 | { | |
f521eaa9 | 11897 | struct net_device *dev = dev_get_drvdata(device); |
f65a2044 MC |
11898 | struct bnxt *bp = netdev_priv(dev); |
11899 | int rc = 0; | |
11900 | ||
11901 | rtnl_lock(); | |
6a68749d | 11902 | bnxt_ulp_stop(bp); |
f65a2044 MC |
11903 | if (netif_running(dev)) { |
11904 | netif_device_detach(dev); | |
11905 | rc = bnxt_close(dev); | |
11906 | } | |
11907 | bnxt_hwrm_func_drv_unrgtr(bp); | |
11908 | rtnl_unlock(); | |
11909 | return rc; | |
11910 | } | |
11911 | ||
11912 | static int bnxt_resume(struct device *device) | |
11913 | { | |
f521eaa9 | 11914 | struct net_device *dev = dev_get_drvdata(device); |
f65a2044 MC |
11915 | struct bnxt *bp = netdev_priv(dev); |
11916 | int rc = 0; | |
11917 | ||
11918 | rtnl_lock(); | |
11919 | if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) { | |
11920 | rc = -ENODEV; | |
11921 | goto resume_exit; | |
11922 | } | |
11923 | rc = bnxt_hwrm_func_reset(bp); | |
11924 | if (rc) { | |
11925 | rc = -EBUSY; | |
11926 | goto resume_exit; | |
11927 | } | |
11928 | bnxt_get_wol_settings(bp); | |
11929 | if (netif_running(dev)) { | |
11930 | rc = bnxt_open(dev); | |
11931 | if (!rc) | |
11932 | netif_device_attach(dev); | |
11933 | } | |
11934 | ||
11935 | resume_exit: | |
6a68749d | 11936 | bnxt_ulp_start(bp, rc); |
f65a2044 MC |
11937 | rtnl_unlock(); |
11938 | return rc; | |
11939 | } | |
11940 | ||
11941 | static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); | |
11942 | #define BNXT_PM_OPS (&bnxt_pm_ops) | |
11943 | ||
11944 | #else | |
11945 | ||
11946 | #define BNXT_PM_OPS NULL | |
11947 | ||
11948 | #endif /* CONFIG_PM_SLEEP */ | |
11949 | ||
6316ea6d SB |
11950 | /** |
11951 | * bnxt_io_error_detected - called when PCI error is detected | |
11952 | * @pdev: Pointer to PCI device | |
11953 | * @state: The current pci connection state | |
11954 | * | |
11955 | * This function is called after a PCI bus error affecting | |
11956 | * this device has been detected. | |
11957 | */ | |
11958 | static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, | |
11959 | pci_channel_state_t state) | |
11960 | { | |
11961 | struct net_device *netdev = pci_get_drvdata(pdev); | |
a588e458 | 11962 | struct bnxt *bp = netdev_priv(netdev); |
6316ea6d SB |
11963 | |
11964 | netdev_info(netdev, "PCI I/O error detected\n"); | |
11965 | ||
11966 | rtnl_lock(); | |
11967 | netif_device_detach(netdev); | |
11968 | ||
a588e458 MC |
11969 | bnxt_ulp_stop(bp); |
11970 | ||
6316ea6d SB |
11971 | if (state == pci_channel_io_perm_failure) { |
11972 | rtnl_unlock(); | |
11973 | return PCI_ERS_RESULT_DISCONNECT; | |
11974 | } | |
11975 | ||
11976 | if (netif_running(netdev)) | |
11977 | bnxt_close(netdev); | |
11978 | ||
11979 | pci_disable_device(pdev); | |
11980 | rtnl_unlock(); | |
11981 | ||
11982 | /* Request a slot slot reset. */ | |
11983 | return PCI_ERS_RESULT_NEED_RESET; | |
11984 | } | |
11985 | ||
11986 | /** | |
11987 | * bnxt_io_slot_reset - called after the pci bus has been reset. | |
11988 | * @pdev: Pointer to PCI device | |
11989 | * | |
11990 | * Restart the card from scratch, as if from a cold-boot. | |
11991 | * At this point, the card has exprienced a hard reset, | |
11992 | * followed by fixups by BIOS, and has its config space | |
11993 | * set up identically to what it was at cold boot. | |
11994 | */ | |
11995 | static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) | |
11996 | { | |
11997 | struct net_device *netdev = pci_get_drvdata(pdev); | |
11998 | struct bnxt *bp = netdev_priv(netdev); | |
11999 | int err = 0; | |
12000 | pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; | |
12001 | ||
12002 | netdev_info(bp->dev, "PCI Slot Reset\n"); | |
12003 | ||
12004 | rtnl_lock(); | |
12005 | ||
12006 | if (pci_enable_device(pdev)) { | |
12007 | dev_err(&pdev->dev, | |
12008 | "Cannot re-enable PCI device after reset.\n"); | |
12009 | } else { | |
12010 | pci_set_master(pdev); | |
12011 | ||
aa8ed021 MC |
12012 | err = bnxt_hwrm_func_reset(bp); |
12013 | if (!err && netif_running(netdev)) | |
6316ea6d SB |
12014 | err = bnxt_open(netdev); |
12015 | ||
aa46dfff | 12016 | if (!err) |
6316ea6d | 12017 | result = PCI_ERS_RESULT_RECOVERED; |
aa46dfff | 12018 | bnxt_ulp_start(bp, err); |
6316ea6d SB |
12019 | } |
12020 | ||
12021 | if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) | |
12022 | dev_close(netdev); | |
12023 | ||
12024 | rtnl_unlock(); | |
12025 | ||
6316ea6d SB |
12026 | return PCI_ERS_RESULT_RECOVERED; |
12027 | } | |
12028 | ||
12029 | /** | |
12030 | * bnxt_io_resume - called when traffic can start flowing again. | |
12031 | * @pdev: Pointer to PCI device | |
12032 | * | |
12033 | * This callback is called when the error recovery driver tells | |
12034 | * us that its OK to resume normal operation. | |
12035 | */ | |
12036 | static void bnxt_io_resume(struct pci_dev *pdev) | |
12037 | { | |
12038 | struct net_device *netdev = pci_get_drvdata(pdev); | |
12039 | ||
12040 | rtnl_lock(); | |
12041 | ||
12042 | netif_device_attach(netdev); | |
12043 | ||
12044 | rtnl_unlock(); | |
12045 | } | |
12046 | ||
12047 | static const struct pci_error_handlers bnxt_err_handler = { | |
12048 | .error_detected = bnxt_io_error_detected, | |
12049 | .slot_reset = bnxt_io_slot_reset, | |
12050 | .resume = bnxt_io_resume | |
12051 | }; | |
12052 | ||
c0c050c5 MC |
12053 | static struct pci_driver bnxt_pci_driver = { |
12054 | .name = DRV_MODULE_NAME, | |
12055 | .id_table = bnxt_pci_tbl, | |
12056 | .probe = bnxt_init_one, | |
12057 | .remove = bnxt_remove_one, | |
d196ece7 | 12058 | .shutdown = bnxt_shutdown, |
f65a2044 | 12059 | .driver.pm = BNXT_PM_OPS, |
6316ea6d | 12060 | .err_handler = &bnxt_err_handler, |
c0c050c5 MC |
12061 | #if defined(CONFIG_BNXT_SRIOV) |
12062 | .sriov_configure = bnxt_sriov_configure, | |
12063 | #endif | |
12064 | }; | |
12065 | ||
c213eae8 MC |
12066 | static int __init bnxt_init(void) |
12067 | { | |
cabfb09d | 12068 | bnxt_debug_init(); |
c213eae8 MC |
12069 | return pci_register_driver(&bnxt_pci_driver); |
12070 | } | |
12071 | ||
12072 | static void __exit bnxt_exit(void) | |
12073 | { | |
12074 | pci_unregister_driver(&bnxt_pci_driver); | |
12075 | if (bnxt_pf_wq) | |
12076 | destroy_workqueue(bnxt_pf_wq); | |
cabfb09d | 12077 | bnxt_debug_exit(); |
c213eae8 MC |
12078 | } |
12079 | ||
12080 | module_init(bnxt_init); | |
12081 | module_exit(bnxt_exit); |