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bnxt_en: Refactor bnxt_fw_to_ethtool_advertised_spds().
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2015 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11
12#include <linux/stringify.h>
13#include <linux/kernel.h>
14#include <linux/timer.h>
15#include <linux/errno.h>
16#include <linux/ioport.h>
17#include <linux/slab.h>
18#include <linux/vmalloc.h>
19#include <linux/interrupt.h>
20#include <linux/pci.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/dma-mapping.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/delay.h>
29#include <asm/byteorder.h>
30#include <asm/page.h>
31#include <linux/time.h>
32#include <linux/mii.h>
33#include <linux/if.h>
34#include <linux/if_vlan.h>
35#include <net/ip.h>
36#include <net/tcp.h>
37#include <net/udp.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41#include <net/vxlan.h>
42#endif
43#ifdef CONFIG_NET_RX_BUSY_POLL
44#include <net/busy_poll.h>
45#endif
46#include <linux/workqueue.h>
47#include <linux/prefetch.h>
48#include <linux/cache.h>
49#include <linux/log2.h>
50#include <linux/aer.h>
51#include <linux/bitmap.h>
52#include <linux/cpu_rmap.h>
53
54#include "bnxt_hsi.h"
55#include "bnxt.h"
56#include "bnxt_sriov.h"
57#include "bnxt_ethtool.h"
58
59#define BNXT_TX_TIMEOUT (5 * HZ)
60
61static const char version[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63
64MODULE_LICENSE("GPL");
65MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66MODULE_VERSION(DRV_MODULE_VERSION);
67
68#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70#define BNXT_RX_COPY_THRESH 256
71
4419dbe6 72#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 73
74enum board_idx {
fbc9a523 75 BCM57301,
c0c050c5
MC		 76 BCM57302,
77 BCM57304,
fbc9a523 78 BCM57402,
c0c050c5
MC		 79 BCM57404,
80 BCM57406,
81 BCM57304_VF,
82 BCM57404_VF,
83};
84
85/* indexed by enum above */
86static const struct {
87 char *name;
88} board_info[] = {
fbc9a523
DC		 89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
c0c050c5 91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
fbc9a523 92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
c0c050c5 93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
fbc9a523 94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
c0c050c5
MC		 95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
97};
98
99static const struct pci_device_id bnxt_pci_tbl[] = {
fbc9a523 100 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 101 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
102 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
fbc9a523 103 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 104 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
105 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
106#ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
108 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
109#endif
110 { 0 }
111};
112
113MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
114
115static const u16 bnxt_vf_req_snif[] = {
116 HWRM_FUNC_CFG,
117 HWRM_PORT_PHY_QCFG,
118 HWRM_CFA_L2_FILTER_ALLOC,
119};
120
121static bool bnxt_vf_pciid(enum board_idx idx)
122{
123 return (idx == BCM57304_VF || idx == BCM57404_VF);
124}
125
126#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
127#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
128#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
129
130#define BNXT_CP_DB_REARM(db, raw_cons) \
131 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
132
133#define BNXT_CP_DB(db, raw_cons) \
134 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
135
136#define BNXT_CP_DB_IRQ_DIS(db) \
137 writel(DB_CP_IRQ_DIS_FLAGS, db)
138
139static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
140{
141 /* Tell compiler to fetch tx indices from memory. */
142 barrier();
143
144 return bp->tx_ring_size -
145 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
146}
147
148static const u16 bnxt_lhint_arr[] = {
149 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
150 TX_BD_FLAGS_LHINT_512_TO_1023,
151 TX_BD_FLAGS_LHINT_1024_TO_2047,
152 TX_BD_FLAGS_LHINT_1024_TO_2047,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
168};
169
170static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
171{
172 struct bnxt *bp = netdev_priv(dev);
173 struct tx_bd *txbd;
174 struct tx_bd_ext *txbd1;
175 struct netdev_queue *txq;
176 int i;
177 dma_addr_t mapping;
178 unsigned int length, pad = 0;
179 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
180 u16 prod, last_frag;
181 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 182 struct bnxt_tx_ring_info *txr;
183 struct bnxt_sw_tx_bd *tx_buf;
184
185 i = skb_get_queue_mapping(skb);
186 if (unlikely(i >= bp->tx_nr_rings)) {
187 dev_kfree_skb_any(skb);
188 return NETDEV_TX_OK;
189 }
190
b6ab4b01 191 txr = &bp->tx_ring[i];
c0c050c5
MC		 192 txq = netdev_get_tx_queue(dev, i);
193 prod = txr->tx_prod;
194
195 free_size = bnxt_tx_avail(bp, txr);
196 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
197 netif_tx_stop_queue(txq);
198 return NETDEV_TX_BUSY;
199 }
200
201 length = skb->len;
202 len = skb_headlen(skb);
203 last_frag = skb_shinfo(skb)->nr_frags;
204
205 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
206
207 txbd->tx_bd_opaque = prod;
208
209 tx_buf = &txr->tx_buf_ring[prod];
210 tx_buf->skb = skb;
211 tx_buf->nr_frags = last_frag;
212
213 vlan_tag_flags = 0;
214 cfa_action = 0;
215 if (skb_vlan_tag_present(skb)) {
216 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
217 skb_vlan_tag_get(skb);
218 /* Currently supports 8021Q, 8021AD vlan offloads
219 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
220 */
221 if (skb->vlan_proto == htons(ETH_P_8021Q))
222 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
223 }
224
225 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 226 struct tx_push_buffer *tx_push_buf = txr->tx_push;
227 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
228 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
229 void *pdata = tx_push_buf->data;
230 u64 *end;
231 int j, push_len;
c0c050c5
MC		 232
233 /* Set COAL_NOW to be ready quickly for the next push */
234 tx_push->tx_bd_len_flags_type =
235 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
236 TX_BD_TYPE_LONG_TX_BD |
237 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
238 TX_BD_FLAGS_COAL_NOW |
239 TX_BD_FLAGS_PACKET_END |
240 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
241
242 if (skb->ip_summed == CHECKSUM_PARTIAL)
243 tx_push1->tx_bd_hsize_lflags =
244 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
245 else
246 tx_push1->tx_bd_hsize_lflags = 0;
247
248 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
249 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
250
fbb0fa8b
MC		 251 end = pdata + length;
252 end = PTR_ALIGN(end, 8) - 1;
4419dbe6
MC		 253 *end = 0;
254
c0c050c5
MC		 255 skb_copy_from_linear_data(skb, pdata, len);
256 pdata += len;
257 for (j = 0; j < last_frag; j++) {
258 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
259 void *fptr;
260
261 fptr = skb_frag_address_safe(frag);
262 if (!fptr)
263 goto normal_tx;
264
265 memcpy(pdata, fptr, skb_frag_size(frag));
266 pdata += skb_frag_size(frag);
267 }
268
4419dbe6
MC		 269 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
270 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 271 prod = NEXT_TX(prod);
272 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
273 memcpy(txbd, tx_push1, sizeof(*txbd));
274 prod = NEXT_TX(prod);
4419dbe6 275 tx_push->doorbell =
c0c050c5
MC		 276 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
277 txr->tx_prod = prod;
278
279 netdev_tx_sent_queue(txq, skb->len);
280
4419dbe6
MC		 281 push_len = (length + sizeof(*tx_push) + 7) / 8;
282 if (push_len > 16) {
283 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
284 __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
285 push_len - 16);
286 } else {
287 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
288 push_len);
289 }
c0c050c5
MC		 290
291 tx_buf->is_push = 1;
c0c050c5
MC		 292 goto tx_done;
293 }
294
295normal_tx:
296 if (length < BNXT_MIN_PKT_SIZE) {
297 pad = BNXT_MIN_PKT_SIZE - length;
298 if (skb_pad(skb, pad)) {
299 /* SKB already freed. */
300 tx_buf->skb = NULL;
301 return NETDEV_TX_OK;
302 }
303 length = BNXT_MIN_PKT_SIZE;
304 }
305
306 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
307
308 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
309 dev_kfree_skb_any(skb);
310 tx_buf->skb = NULL;
311 return NETDEV_TX_OK;
312 }
313
314 dma_unmap_addr_set(tx_buf, mapping, mapping);
315 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
316 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
317
318 txbd->tx_bd_haddr = cpu_to_le64(mapping);
319
320 prod = NEXT_TX(prod);
321 txbd1 = (struct tx_bd_ext *)
322 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
323
324 txbd1->tx_bd_hsize_lflags = 0;
325 if (skb_is_gso(skb)) {
326 u32 hdr_len;
327
328 if (skb->encapsulation)
329 hdr_len = skb_inner_network_offset(skb) +
330 skb_inner_network_header_len(skb) +
331 inner_tcp_hdrlen(skb);
332 else
333 hdr_len = skb_transport_offset(skb) +
334 tcp_hdrlen(skb);
335
336 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
337 TX_BD_FLAGS_T_IPID |
338 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
339 length = skb_shinfo(skb)->gso_size;
340 txbd1->tx_bd_mss = cpu_to_le32(length);
341 length += hdr_len;
342 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
343 txbd1->tx_bd_hsize_lflags =
344 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
345 txbd1->tx_bd_mss = 0;
346 }
347
348 length >>= 9;
349 flags |= bnxt_lhint_arr[length];
350 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
351
352 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
353 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
354 for (i = 0; i < last_frag; i++) {
355 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
356
357 prod = NEXT_TX(prod);
358 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
359
360 len = skb_frag_size(frag);
361 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
362 DMA_TO_DEVICE);
363
364 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
365 goto tx_dma_error;
366
367 tx_buf = &txr->tx_buf_ring[prod];
368 dma_unmap_addr_set(tx_buf, mapping, mapping);
369
370 txbd->tx_bd_haddr = cpu_to_le64(mapping);
371
372 flags = len << TX_BD_LEN_SHIFT;
373 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
374 }
375
376 flags &= ~TX_BD_LEN;
377 txbd->tx_bd_len_flags_type =
378 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
379 TX_BD_FLAGS_PACKET_END);
380
381 netdev_tx_sent_queue(txq, skb->len);
382
383 /* Sync BD data before updating doorbell */
384 wmb();
385
386 prod = NEXT_TX(prod);
387 txr->tx_prod = prod;
388
389 writel(DB_KEY_TX | prod, txr->tx_doorbell);
390 writel(DB_KEY_TX | prod, txr->tx_doorbell);
391
392tx_done:
393
394 mmiowb();
395
396 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
397 netif_tx_stop_queue(txq);
398
399 /* netif_tx_stop_queue() must be done before checking
400 * tx index in bnxt_tx_avail() below, because in
401 * bnxt_tx_int(), we update tx index before checking for
402 * netif_tx_queue_stopped().
403 */
404 smp_mb();
405 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
406 netif_tx_wake_queue(txq);
407 }
408 return NETDEV_TX_OK;
409
410tx_dma_error:
411 last_frag = i;
412
413 /* start back at beginning and unmap skb */
414 prod = txr->tx_prod;
415 tx_buf = &txr->tx_buf_ring[prod];
416 tx_buf->skb = NULL;
417 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
418 skb_headlen(skb), PCI_DMA_TODEVICE);
419 prod = NEXT_TX(prod);
420
421 /* unmap remaining mapped pages */
422 for (i = 0; i < last_frag; i++) {
423 prod = NEXT_TX(prod);
424 tx_buf = &txr->tx_buf_ring[prod];
425 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
426 skb_frag_size(&skb_shinfo(skb)->frags[i]),
427 PCI_DMA_TODEVICE);
428 }
429
430 dev_kfree_skb_any(skb);
431 return NETDEV_TX_OK;
432}
433
434static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
435{
b6ab4b01 436 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
b81a90d3 437 int index = txr - &bp->tx_ring[0];
c0c050c5
MC		 438 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
439 u16 cons = txr->tx_cons;
440 struct pci_dev *pdev = bp->pdev;
441 int i;
442 unsigned int tx_bytes = 0;
443
444 for (i = 0; i < nr_pkts; i++) {
445 struct bnxt_sw_tx_bd *tx_buf;
446 struct sk_buff *skb;
447 int j, last;
448
449 tx_buf = &txr->tx_buf_ring[cons];
450 cons = NEXT_TX(cons);
451 skb = tx_buf->skb;
452 tx_buf->skb = NULL;
453
454 if (tx_buf->is_push) {
455 tx_buf->is_push = 0;
456 goto next_tx_int;
457 }
458
459 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
460 skb_headlen(skb), PCI_DMA_TODEVICE);
461 last = tx_buf->nr_frags;
462
463 for (j = 0; j < last; j++) {
464 cons = NEXT_TX(cons);
465 tx_buf = &txr->tx_buf_ring[cons];
466 dma_unmap_page(
467 &pdev->dev,
468 dma_unmap_addr(tx_buf, mapping),
469 skb_frag_size(&skb_shinfo(skb)->frags[j]),
470 PCI_DMA_TODEVICE);
471 }
472
473next_tx_int:
474 cons = NEXT_TX(cons);
475
476 tx_bytes += skb->len;
477 dev_kfree_skb_any(skb);
478 }
479
480 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
481 txr->tx_cons = cons;
482
483 /* Need to make the tx_cons update visible to bnxt_start_xmit()
484 * before checking for netif_tx_queue_stopped(). Without the
485 * memory barrier, there is a small possibility that bnxt_start_xmit()
486 * will miss it and cause the queue to be stopped forever.
487 */
488 smp_mb();
489
490 if (unlikely(netif_tx_queue_stopped(txq)) &&
491 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
492 __netif_tx_lock(txq, smp_processor_id());
493 if (netif_tx_queue_stopped(txq) &&
494 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
495 txr->dev_state != BNXT_DEV_STATE_CLOSING)
496 netif_tx_wake_queue(txq);
497 __netif_tx_unlock(txq);
498 }
499}
500
501static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
502 gfp_t gfp)
503{
504 u8 *data;
505 struct pci_dev *pdev = bp->pdev;
506
507 data = kmalloc(bp->rx_buf_size, gfp);
508 if (!data)
509 return NULL;
510
511 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
512 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
513
514 if (dma_mapping_error(&pdev->dev, *mapping)) {
515 kfree(data);
516 data = NULL;
517 }
518 return data;
519}
520
521static inline int bnxt_alloc_rx_data(struct bnxt *bp,
522 struct bnxt_rx_ring_info *rxr,
523 u16 prod, gfp_t gfp)
524{
525 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
526 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
527 u8 *data;
528 dma_addr_t mapping;
529
530 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
531 if (!data)
532 return -ENOMEM;
533
534 rx_buf->data = data;
535 dma_unmap_addr_set(rx_buf, mapping, mapping);
536
537 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
538
539 return 0;
540}
541
542static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
543 u8 *data)
544{
545 u16 prod = rxr->rx_prod;
546 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
547 struct rx_bd *cons_bd, *prod_bd;
548
549 prod_rx_buf = &rxr->rx_buf_ring[prod];
550 cons_rx_buf = &rxr->rx_buf_ring[cons];
551
552 prod_rx_buf->data = data;
553
554 dma_unmap_addr_set(prod_rx_buf, mapping,
555 dma_unmap_addr(cons_rx_buf, mapping));
556
557 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
558 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
559
560 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
561}
562
563static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
564{
565 u16 next, max = rxr->rx_agg_bmap_size;
566
567 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
568 if (next >= max)
569 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
570 return next;
571}
572
573static inline int bnxt_alloc_rx_page(struct bnxt *bp,
574 struct bnxt_rx_ring_info *rxr,
575 u16 prod, gfp_t gfp)
576{
577 struct rx_bd *rxbd =
578 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
579 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
580 struct pci_dev *pdev = bp->pdev;
581 struct page *page;
582 dma_addr_t mapping;
583 u16 sw_prod = rxr->rx_sw_agg_prod;
584
585 page = alloc_page(gfp);
586 if (!page)
587 return -ENOMEM;
588
589 mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
590 PCI_DMA_FROMDEVICE);
591 if (dma_mapping_error(&pdev->dev, mapping)) {
592 __free_page(page);
593 return -EIO;
594 }
595
596 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
597 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
598
599 __set_bit(sw_prod, rxr->rx_agg_bmap);
600 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
601 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
602
603 rx_agg_buf->page = page;
604 rx_agg_buf->mapping = mapping;
605 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
606 rxbd->rx_bd_opaque = sw_prod;
607 return 0;
608}
609
610static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
611 u32 agg_bufs)
612{
613 struct bnxt *bp = bnapi->bp;
614 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 615 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 616 u16 prod = rxr->rx_agg_prod;
617 u16 sw_prod = rxr->rx_sw_agg_prod;
618 u32 i;
619
620 for (i = 0; i < agg_bufs; i++) {
621 u16 cons;
622 struct rx_agg_cmp *agg;
623 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
624 struct rx_bd *prod_bd;
625 struct page *page;
626
627 agg = (struct rx_agg_cmp *)
628 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
629 cons = agg->rx_agg_cmp_opaque;
630 __clear_bit(cons, rxr->rx_agg_bmap);
631
632 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
633 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
634
635 __set_bit(sw_prod, rxr->rx_agg_bmap);
636 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
637 cons_rx_buf = &rxr->rx_agg_ring[cons];
638
639 /* It is possible for sw_prod to be equal to cons, so
640 * set cons_rx_buf->page to NULL first.
641 */
642 page = cons_rx_buf->page;
643 cons_rx_buf->page = NULL;
644 prod_rx_buf->page = page;
645
646 prod_rx_buf->mapping = cons_rx_buf->mapping;
647
648 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
649
650 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
651 prod_bd->rx_bd_opaque = sw_prod;
652
653 prod = NEXT_RX_AGG(prod);
654 sw_prod = NEXT_RX_AGG(sw_prod);
655 cp_cons = NEXT_CMP(cp_cons);
656 }
657 rxr->rx_agg_prod = prod;
658 rxr->rx_sw_agg_prod = sw_prod;
659}
660
661static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
662 struct bnxt_rx_ring_info *rxr, u16 cons,
663 u16 prod, u8 *data, dma_addr_t dma_addr,
664 unsigned int len)
665{
666 int err;
667 struct sk_buff *skb;
668
669 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
670 if (unlikely(err)) {
671 bnxt_reuse_rx_data(rxr, cons, data);
672 return NULL;
673 }
674
675 skb = build_skb(data, 0);
676 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
677 PCI_DMA_FROMDEVICE);
678 if (!skb) {
679 kfree(data);
680 return NULL;
681 }
682
683 skb_reserve(skb, BNXT_RX_OFFSET);
684 skb_put(skb, len);
685 return skb;
686}
687
688static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
689 struct sk_buff *skb, u16 cp_cons,
690 u32 agg_bufs)
691{
692 struct pci_dev *pdev = bp->pdev;
693 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 694 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 695 u16 prod = rxr->rx_agg_prod;
696 u32 i;
697
698 for (i = 0; i < agg_bufs; i++) {
699 u16 cons, frag_len;
700 struct rx_agg_cmp *agg;
701 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
702 struct page *page;
703 dma_addr_t mapping;
704
705 agg = (struct rx_agg_cmp *)
706 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
707 cons = agg->rx_agg_cmp_opaque;
708 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
709 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
710
711 cons_rx_buf = &rxr->rx_agg_ring[cons];
712 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
713 __clear_bit(cons, rxr->rx_agg_bmap);
714
715 /* It is possible for bnxt_alloc_rx_page() to allocate
716 * a sw_prod index that equals the cons index, so we
717 * need to clear the cons entry now.
718 */
719 mapping = dma_unmap_addr(cons_rx_buf, mapping);
720 page = cons_rx_buf->page;
721 cons_rx_buf->page = NULL;
722
723 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
724 struct skb_shared_info *shinfo;
725 unsigned int nr_frags;
726
727 shinfo = skb_shinfo(skb);
728 nr_frags = --shinfo->nr_frags;
729 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
730
731 dev_kfree_skb(skb);
732
733 cons_rx_buf->page = page;
734
735 /* Update prod since possibly some pages have been
736 * allocated already.
737 */
738 rxr->rx_agg_prod = prod;
739 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
740 return NULL;
741 }
742
743 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
744 PCI_DMA_FROMDEVICE);
745
746 skb->data_len += frag_len;
747 skb->len += frag_len;
748 skb->truesize += PAGE_SIZE;
749
750 prod = NEXT_RX_AGG(prod);
751 cp_cons = NEXT_CMP(cp_cons);
752 }
753 rxr->rx_agg_prod = prod;
754 return skb;
755}
756
757static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
758 u8 agg_bufs, u32 *raw_cons)
759{
760 u16 last;
761 struct rx_agg_cmp *agg;
762
763 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
764 last = RING_CMP(*raw_cons);
765 agg = (struct rx_agg_cmp *)
766 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
767 return RX_AGG_CMP_VALID(agg, *raw_cons);
768}
769
770static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
771 unsigned int len,
772 dma_addr_t mapping)
773{
774 struct bnxt *bp = bnapi->bp;
775 struct pci_dev *pdev = bp->pdev;
776 struct sk_buff *skb;
777
778 skb = napi_alloc_skb(&bnapi->napi, len);
779 if (!skb)
780 return NULL;
781
782 dma_sync_single_for_cpu(&pdev->dev, mapping,
783 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
784
785 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
786
787 dma_sync_single_for_device(&pdev->dev, mapping,
788 bp->rx_copy_thresh,
789 PCI_DMA_FROMDEVICE);
790
791 skb_put(skb, len);
792 return skb;
793}
794
795static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
796 struct rx_tpa_start_cmp *tpa_start,
797 struct rx_tpa_start_cmp_ext *tpa_start1)
798{
799 u8 agg_id = TPA_START_AGG_ID(tpa_start);
800 u16 cons, prod;
801 struct bnxt_tpa_info *tpa_info;
802 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
803 struct rx_bd *prod_bd;
804 dma_addr_t mapping;
805
806 cons = tpa_start->rx_tpa_start_cmp_opaque;
807 prod = rxr->rx_prod;
808 cons_rx_buf = &rxr->rx_buf_ring[cons];
809 prod_rx_buf = &rxr->rx_buf_ring[prod];
810 tpa_info = &rxr->rx_tpa[agg_id];
811
812 prod_rx_buf->data = tpa_info->data;
813
814 mapping = tpa_info->mapping;
815 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
816
817 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
818
819 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
820
821 tpa_info->data = cons_rx_buf->data;
822 cons_rx_buf->data = NULL;
823 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
824
825 tpa_info->len =
826 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
827 RX_TPA_START_CMP_LEN_SHIFT;
828 if (likely(TPA_START_HASH_VALID(tpa_start))) {
829 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
830
831 tpa_info->hash_type = PKT_HASH_TYPE_L4;
832 tpa_info->gso_type = SKB_GSO_TCPV4;
833 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
834 if (hash_type == 3)
835 tpa_info->gso_type = SKB_GSO_TCPV6;
836 tpa_info->rss_hash =
837 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
838 } else {
839 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
840 tpa_info->gso_type = 0;
841 if (netif_msg_rx_err(bp))
842 netdev_warn(bp->dev, "TPA packet without valid hash\n");
843 }
844 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
845 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
846
847 rxr->rx_prod = NEXT_RX(prod);
848 cons = NEXT_RX(cons);
849 cons_rx_buf = &rxr->rx_buf_ring[cons];
850
851 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
852 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
853 cons_rx_buf->data = NULL;
854}
855
856static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
857 u16 cp_cons, u32 agg_bufs)
858{
859 if (agg_bufs)
860 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
861}
862
863#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
864#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
865
866static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
867 struct rx_tpa_end_cmp *tpa_end,
868 struct rx_tpa_end_cmp_ext *tpa_end1,
869 struct sk_buff *skb)
870{
d1611c3a 871#ifdef CONFIG_INET
c0c050c5
MC		 872 struct tcphdr *th;
873 int payload_off, tcp_opt_len = 0;
874 int len, nw_off;
27e24189 875 u16 segs;
c0c050c5 876
27e24189
MC		 877 segs = TPA_END_TPA_SEGS(tpa_end);
878 if (segs == 1)
879 return skb;
880
881 NAPI_GRO_CB(skb)->count = segs;
c0c050c5
MC		 882 skb_shinfo(skb)->gso_size =
883 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
884 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
885 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
886 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
887 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
888 if (TPA_END_GRO_TS(tpa_end))
889 tcp_opt_len = 12;
890
c0c050c5
MC		 891 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
892 struct iphdr *iph;
893
894 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
895 ETH_HLEN;
896 skb_set_network_header(skb, nw_off);
897 iph = ip_hdr(skb);
898 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
899 len = skb->len - skb_transport_offset(skb);
900 th = tcp_hdr(skb);
901 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
902 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
903 struct ipv6hdr *iph;
904
905 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
906 ETH_HLEN;
907 skb_set_network_header(skb, nw_off);
908 iph = ipv6_hdr(skb);
909 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
910 len = skb->len - skb_transport_offset(skb);
911 th = tcp_hdr(skb);
912 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
913 } else {
914 dev_kfree_skb_any(skb);
915 return NULL;
916 }
917 tcp_gro_complete(skb);
918
919 if (nw_off) { /* tunnel */
920 struct udphdr *uh = NULL;
921
922 if (skb->protocol == htons(ETH_P_IP)) {
923 struct iphdr *iph = (struct iphdr *)skb->data;
924
925 if (iph->protocol == IPPROTO_UDP)
926 uh = (struct udphdr *)(iph + 1);
927 } else {
928 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
929
930 if (iph->nexthdr == IPPROTO_UDP)
931 uh = (struct udphdr *)(iph + 1);
932 }
933 if (uh) {
934 if (uh->check)
935 skb_shinfo(skb)->gso_type |=
936 SKB_GSO_UDP_TUNNEL_CSUM;
937 else
938 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
939 }
940 }
941#endif
942 return skb;
943}
944
945static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
946 struct bnxt_napi *bnapi,
947 u32 *raw_cons,
948 struct rx_tpa_end_cmp *tpa_end,
949 struct rx_tpa_end_cmp_ext *tpa_end1,
950 bool *agg_event)
951{
952 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 953 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 954 u8 agg_id = TPA_END_AGG_ID(tpa_end);
955 u8 *data, agg_bufs;
956 u16 cp_cons = RING_CMP(*raw_cons);
957 unsigned int len;
958 struct bnxt_tpa_info *tpa_info;
959 dma_addr_t mapping;
960 struct sk_buff *skb;
961
962 tpa_info = &rxr->rx_tpa[agg_id];
963 data = tpa_info->data;
964 prefetch(data);
965 len = tpa_info->len;
966 mapping = tpa_info->mapping;
967
968 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
969 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
970
971 if (agg_bufs) {
972 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
973 return ERR_PTR(-EBUSY);
974
975 *agg_event = true;
976 cp_cons = NEXT_CMP(cp_cons);
977 }
978
979 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
980 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
981 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
982 agg_bufs, (int)MAX_SKB_FRAGS);
983 return NULL;
984 }
985
986 if (len <= bp->rx_copy_thresh) {
987 skb = bnxt_copy_skb(bnapi, data, len, mapping);
988 if (!skb) {
989 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
990 return NULL;
991 }
992 } else {
993 u8 *new_data;
994 dma_addr_t new_mapping;
995
996 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
997 if (!new_data) {
998 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
999 return NULL;
1000 }
1001
1002 tpa_info->data = new_data;
1003 tpa_info->mapping = new_mapping;
1004
1005 skb = build_skb(data, 0);
1006 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1007 PCI_DMA_FROMDEVICE);
1008
1009 if (!skb) {
1010 kfree(data);
1011 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1012 return NULL;
1013 }
1014 skb_reserve(skb, BNXT_RX_OFFSET);
1015 skb_put(skb, len);
1016 }
1017
1018 if (agg_bufs) {
1019 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1020 if (!skb) {
1021 /* Page reuse already handled by bnxt_rx_pages(). */
1022 return NULL;
1023 }
1024 }
1025 skb->protocol = eth_type_trans(skb, bp->dev);
1026
1027 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1028 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1029
1030 if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1031 netdev_features_t features = skb->dev->features;
1032 u16 vlan_proto = tpa_info->metadata >>
1033 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1034
1035 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1036 vlan_proto == ETH_P_8021Q) ||
1037 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1038 vlan_proto == ETH_P_8021AD)) {
1039 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1040 tpa_info->metadata &
1041 RX_CMP_FLAGS2_METADATA_VID_MASK);
1042 }
1043 }
1044
1045 skb_checksum_none_assert(skb);
1046 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1047 skb->ip_summed = CHECKSUM_UNNECESSARY;
1048 skb->csum_level =
1049 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1050 }
1051
1052 if (TPA_END_GRO(tpa_end))
1053 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1054
1055 return skb;
1056}
1057
1058/* returns the following:
1059 * 1 - 1 packet successfully received
1060 * 0 - successful TPA_START, packet not completed yet
1061 * -EBUSY - completion ring does not have all the agg buffers yet
1062 * -ENOMEM - packet aborted due to out of memory
1063 * -EIO - packet aborted due to hw error indicated in BD
1064 */
1065static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1066 bool *agg_event)
1067{
1068 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1069 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1070 struct net_device *dev = bp->dev;
1071 struct rx_cmp *rxcmp;
1072 struct rx_cmp_ext *rxcmp1;
1073 u32 tmp_raw_cons = *raw_cons;
1074 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1075 struct bnxt_sw_rx_bd *rx_buf;
1076 unsigned int len;
1077 u8 *data, agg_bufs, cmp_type;
1078 dma_addr_t dma_addr;
1079 struct sk_buff *skb;
1080 int rc = 0;
1081
1082 rxcmp = (struct rx_cmp *)
1083 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1084
1085 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1086 cp_cons = RING_CMP(tmp_raw_cons);
1087 rxcmp1 = (struct rx_cmp_ext *)
1088 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1089
1090 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1091 return -EBUSY;
1092
1093 cmp_type = RX_CMP_TYPE(rxcmp);
1094
1095 prod = rxr->rx_prod;
1096
1097 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1098 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1099 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1100
1101 goto next_rx_no_prod;
1102
1103 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1104 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1105 (struct rx_tpa_end_cmp *)rxcmp,
1106 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1107 agg_event);
1108
1109 if (unlikely(IS_ERR(skb)))
1110 return -EBUSY;
1111
1112 rc = -ENOMEM;
1113 if (likely(skb)) {
1114 skb_record_rx_queue(skb, bnapi->index);
1115 skb_mark_napi_id(skb, &bnapi->napi);
1116 if (bnxt_busy_polling(bnapi))
1117 netif_receive_skb(skb);
1118 else
1119 napi_gro_receive(&bnapi->napi, skb);
1120 rc = 1;
1121 }
1122 goto next_rx_no_prod;
1123 }
1124
1125 cons = rxcmp->rx_cmp_opaque;
1126 rx_buf = &rxr->rx_buf_ring[cons];
1127 data = rx_buf->data;
1128 prefetch(data);
1129
1130 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1131 RX_CMP_AGG_BUFS_SHIFT;
1132
1133 if (agg_bufs) {
1134 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1135 return -EBUSY;
1136
1137 cp_cons = NEXT_CMP(cp_cons);
1138 *agg_event = true;
1139 }
1140
1141 rx_buf->data = NULL;
1142 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1143 bnxt_reuse_rx_data(rxr, cons, data);
1144 if (agg_bufs)
1145 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1146
1147 rc = -EIO;
1148 goto next_rx;
1149 }
1150
1151 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1152 dma_addr = dma_unmap_addr(rx_buf, mapping);
1153
1154 if (len <= bp->rx_copy_thresh) {
1155 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1156 bnxt_reuse_rx_data(rxr, cons, data);
1157 if (!skb) {
1158 rc = -ENOMEM;
1159 goto next_rx;
1160 }
1161 } else {
1162 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1163 if (!skb) {
1164 rc = -ENOMEM;
1165 goto next_rx;
1166 }
1167 }
1168
1169 if (agg_bufs) {
1170 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1171 if (!skb) {
1172 rc = -ENOMEM;
1173 goto next_rx;
1174 }
1175 }
1176
1177 if (RX_CMP_HASH_VALID(rxcmp)) {
1178 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1179 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1180
1181 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1182 if (hash_type != 1 && hash_type != 3)
1183 type = PKT_HASH_TYPE_L3;
1184 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1185 }
1186
1187 skb->protocol = eth_type_trans(skb, dev);
1188
1189 if (rxcmp1->rx_cmp_flags2 &
1190 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1191 netdev_features_t features = skb->dev->features;
1192 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1193 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1194
1195 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1196 vlan_proto == ETH_P_8021Q) ||
1197 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1198 vlan_proto == ETH_P_8021AD))
1199 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1200 meta_data &
1201 RX_CMP_FLAGS2_METADATA_VID_MASK);
1202 }
1203
1204 skb_checksum_none_assert(skb);
1205 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1206 if (dev->features & NETIF_F_RXCSUM) {
1207 skb->ip_summed = CHECKSUM_UNNECESSARY;
1208 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1209 }
1210 } else {
665e350d
SB		 1211 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1212 if (dev->features & NETIF_F_RXCSUM)
1213 cpr->rx_l4_csum_errors++;
1214 }
c0c050c5
MC		 1215 }
1216
1217 skb_record_rx_queue(skb, bnapi->index);
1218 skb_mark_napi_id(skb, &bnapi->napi);
1219 if (bnxt_busy_polling(bnapi))
1220 netif_receive_skb(skb);
1221 else
1222 napi_gro_receive(&bnapi->napi, skb);
1223 rc = 1;
1224
1225next_rx:
1226 rxr->rx_prod = NEXT_RX(prod);
1227
1228next_rx_no_prod:
1229 *raw_cons = tmp_raw_cons;
1230
1231 return rc;
1232}
1233
1234static int bnxt_async_event_process(struct bnxt *bp,
1235 struct hwrm_async_event_cmpl *cmpl)
1236{
1237 u16 event_id = le16_to_cpu(cmpl->event_id);
1238
1239 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1240 switch (event_id) {
1241 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1242 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368
JH		 1243 break;
1244 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1245 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5
MC		 1246 break;
1247 default:
1248 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1249 event_id);
19241368 1250 goto async_event_process_exit;
c0c050c5 1251 }
19241368
JH		 1252 schedule_work(&bp->sp_task);
1253async_event_process_exit:
c0c050c5
MC		 1254 return 0;
1255}
1256
1257static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1258{
1259 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1260 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1261 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1262 (struct hwrm_fwd_req_cmpl *)txcmp;
1263
1264 switch (cmpl_type) {
1265 case CMPL_BASE_TYPE_HWRM_DONE:
1266 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1267 if (seq_id == bp->hwrm_intr_seq_id)
1268 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1269 else
1270 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1271 break;
1272
1273 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1274 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1275
1276 if ((vf_id < bp->pf.first_vf_id) ||
1277 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1278 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1279 vf_id);
1280 return -EINVAL;
1281 }
1282
1283 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1284 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1285 schedule_work(&bp->sp_task);
1286 break;
1287
1288 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1289 bnxt_async_event_process(bp,
1290 (struct hwrm_async_event_cmpl *)txcmp);
1291
1292 default:
1293 break;
1294 }
1295
1296 return 0;
1297}
1298
1299static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1300{
1301 struct bnxt_napi *bnapi = dev_instance;
1302 struct bnxt *bp = bnapi->bp;
1303 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1304 u32 cons = RING_CMP(cpr->cp_raw_cons);
1305
1306 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1307 napi_schedule(&bnapi->napi);
1308 return IRQ_HANDLED;
1309}
1310
1311static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1312{
1313 u32 raw_cons = cpr->cp_raw_cons;
1314 u16 cons = RING_CMP(raw_cons);
1315 struct tx_cmp *txcmp;
1316
1317 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1318
1319 return TX_CMP_VALID(txcmp, raw_cons);
1320}
1321
c0c050c5
MC		 1322static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1323{
1324 struct bnxt_napi *bnapi = dev_instance;
1325 struct bnxt *bp = bnapi->bp;
1326 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1327 u32 cons = RING_CMP(cpr->cp_raw_cons);
1328 u32 int_status;
1329
1330 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1331
1332 if (!bnxt_has_work(bp, cpr)) {
11809490 1333 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1334 /* return if erroneous interrupt */
1335 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1336 return IRQ_NONE;
1337 }
1338
1339 /* disable ring IRQ */
1340 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1341
1342 /* Return here if interrupt is shared and is disabled. */
1343 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1344 return IRQ_HANDLED;
1345
1346 napi_schedule(&bnapi->napi);
1347 return IRQ_HANDLED;
1348}
1349
1350static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1351{
1352 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1353 u32 raw_cons = cpr->cp_raw_cons;
1354 u32 cons;
1355 int tx_pkts = 0;
1356 int rx_pkts = 0;
1357 bool rx_event = false;
1358 bool agg_event = false;
1359 struct tx_cmp *txcmp;
1360
1361 while (1) {
1362 int rc;
1363
1364 cons = RING_CMP(raw_cons);
1365 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1366
1367 if (!TX_CMP_VALID(txcmp, raw_cons))
1368 break;
1369
1370 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1371 tx_pkts++;
1372 /* return full budget so NAPI will complete. */
1373 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1374 rx_pkts = budget;
1375 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1376 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1377 if (likely(rc >= 0))
1378 rx_pkts += rc;
1379 else if (rc == -EBUSY) /* partial completion */
1380 break;
1381 rx_event = true;
1382 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1383 CMPL_BASE_TYPE_HWRM_DONE) ||
1384 (TX_CMP_TYPE(txcmp) ==
1385 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1386 (TX_CMP_TYPE(txcmp) ==
1387 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1388 bnxt_hwrm_handler(bp, txcmp);
1389 }
1390 raw_cons = NEXT_RAW_CMP(raw_cons);
1391
1392 if (rx_pkts == budget)
1393 break;
1394 }
1395
1396 cpr->cp_raw_cons = raw_cons;
1397 /* ACK completion ring before freeing tx ring and producing new
1398 * buffers in rx/agg rings to prevent overflowing the completion
1399 * ring.
1400 */
1401 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1402
1403 if (tx_pkts)
1404 bnxt_tx_int(bp, bnapi, tx_pkts);
1405
1406 if (rx_event) {
b6ab4b01 1407 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1408
1409 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1410 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1411 if (agg_event) {
1412 writel(DB_KEY_RX | rxr->rx_agg_prod,
1413 rxr->rx_agg_doorbell);
1414 writel(DB_KEY_RX | rxr->rx_agg_prod,
1415 rxr->rx_agg_doorbell);
1416 }
1417 }
1418 return rx_pkts;
1419}
1420
1421static int bnxt_poll(struct napi_struct *napi, int budget)
1422{
1423 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1424 struct bnxt *bp = bnapi->bp;
1425 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1426 int work_done = 0;
1427
1428 if (!bnxt_lock_napi(bnapi))
1429 return budget;
1430
1431 while (1) {
1432 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1433
1434 if (work_done >= budget)
1435 break;
1436
1437 if (!bnxt_has_work(bp, cpr)) {
1438 napi_complete(napi);
1439 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1440 break;
1441 }
1442 }
1443 mmiowb();
1444 bnxt_unlock_napi(bnapi);
1445 return work_done;
1446}
1447
1448#ifdef CONFIG_NET_RX_BUSY_POLL
1449static int bnxt_busy_poll(struct napi_struct *napi)
1450{
1451 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1452 struct bnxt *bp = bnapi->bp;
1453 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1454 int rx_work, budget = 4;
1455
1456 if (atomic_read(&bp->intr_sem) != 0)
1457 return LL_FLUSH_FAILED;
1458
1459 if (!bnxt_lock_poll(bnapi))
1460 return LL_FLUSH_BUSY;
1461
1462 rx_work = bnxt_poll_work(bp, bnapi, budget);
1463
1464 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1465
1466 bnxt_unlock_poll(bnapi);
1467 return rx_work;
1468}
1469#endif
1470
1471static void bnxt_free_tx_skbs(struct bnxt *bp)
1472{
1473 int i, max_idx;
1474 struct pci_dev *pdev = bp->pdev;
1475
b6ab4b01 1476 if (!bp->tx_ring)
c0c050c5
MC		 1477 return;
1478
1479 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1480 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1481 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1482 int j;
1483
c0c050c5
MC		 1484 for (j = 0; j < max_idx;) {
1485 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1486 struct sk_buff *skb = tx_buf->skb;
1487 int k, last;
1488
1489 if (!skb) {
1490 j++;
1491 continue;
1492 }
1493
1494 tx_buf->skb = NULL;
1495
1496 if (tx_buf->is_push) {
1497 dev_kfree_skb(skb);
1498 j += 2;
1499 continue;
1500 }
1501
1502 dma_unmap_single(&pdev->dev,
1503 dma_unmap_addr(tx_buf, mapping),
1504 skb_headlen(skb),
1505 PCI_DMA_TODEVICE);
1506
1507 last = tx_buf->nr_frags;
1508 j += 2;
d612a579
MC		 1509 for (k = 0; k < last; k++, j++) {
1510 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 1511 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1512
d612a579 1513 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 1514 dma_unmap_page(
1515 &pdev->dev,
1516 dma_unmap_addr(tx_buf, mapping),
1517 skb_frag_size(frag), PCI_DMA_TODEVICE);
1518 }
1519 dev_kfree_skb(skb);
1520 }
1521 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1522 }
1523}
1524
1525static void bnxt_free_rx_skbs(struct bnxt *bp)
1526{
1527 int i, max_idx, max_agg_idx;
1528 struct pci_dev *pdev = bp->pdev;
1529
b6ab4b01 1530 if (!bp->rx_ring)
c0c050c5
MC		 1531 return;
1532
1533 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1534 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1535 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1536 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1537 int j;
1538
c0c050c5
MC		 1539 if (rxr->rx_tpa) {
1540 for (j = 0; j < MAX_TPA; j++) {
1541 struct bnxt_tpa_info *tpa_info =
1542 &rxr->rx_tpa[j];
1543 u8 *data = tpa_info->data;
1544
1545 if (!data)
1546 continue;
1547
1548 dma_unmap_single(
1549 &pdev->dev,
1550 dma_unmap_addr(tpa_info, mapping),
1551 bp->rx_buf_use_size,
1552 PCI_DMA_FROMDEVICE);
1553
1554 tpa_info->data = NULL;
1555
1556 kfree(data);
1557 }
1558 }
1559
1560 for (j = 0; j < max_idx; j++) {
1561 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1562 u8 *data = rx_buf->data;
1563
1564 if (!data)
1565 continue;
1566
1567 dma_unmap_single(&pdev->dev,
1568 dma_unmap_addr(rx_buf, mapping),
1569 bp->rx_buf_use_size,
1570 PCI_DMA_FROMDEVICE);
1571
1572 rx_buf->data = NULL;
1573
1574 kfree(data);
1575 }
1576
1577 for (j = 0; j < max_agg_idx; j++) {
1578 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1579 &rxr->rx_agg_ring[j];
1580 struct page *page = rx_agg_buf->page;
1581
1582 if (!page)
1583 continue;
1584
1585 dma_unmap_page(&pdev->dev,
1586 dma_unmap_addr(rx_agg_buf, mapping),
1587 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1588
1589 rx_agg_buf->page = NULL;
1590 __clear_bit(j, rxr->rx_agg_bmap);
1591
1592 __free_page(page);
1593 }
1594 }
1595}
1596
1597static void bnxt_free_skbs(struct bnxt *bp)
1598{
1599 bnxt_free_tx_skbs(bp);
1600 bnxt_free_rx_skbs(bp);
1601}
1602
1603static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1604{
1605 struct pci_dev *pdev = bp->pdev;
1606 int i;
1607
1608 for (i = 0; i < ring->nr_pages; i++) {
1609 if (!ring->pg_arr[i])
1610 continue;
1611
1612 dma_free_coherent(&pdev->dev, ring->page_size,
1613 ring->pg_arr[i], ring->dma_arr[i]);
1614
1615 ring->pg_arr[i] = NULL;
1616 }
1617 if (ring->pg_tbl) {
1618 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1619 ring->pg_tbl, ring->pg_tbl_map);
1620 ring->pg_tbl = NULL;
1621 }
1622 if (ring->vmem_size && *ring->vmem) {
1623 vfree(*ring->vmem);
1624 *ring->vmem = NULL;
1625 }
1626}
1627
1628static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1629{
1630 int i;
1631 struct pci_dev *pdev = bp->pdev;
1632
1633 if (ring->nr_pages > 1) {
1634 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1635 ring->nr_pages * 8,
1636 &ring->pg_tbl_map,
1637 GFP_KERNEL);
1638 if (!ring->pg_tbl)
1639 return -ENOMEM;
1640 }
1641
1642 for (i = 0; i < ring->nr_pages; i++) {
1643 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1644 ring->page_size,
1645 &ring->dma_arr[i],
1646 GFP_KERNEL);
1647 if (!ring->pg_arr[i])
1648 return -ENOMEM;
1649
1650 if (ring->nr_pages > 1)
1651 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1652 }
1653
1654 if (ring->vmem_size) {
1655 *ring->vmem = vzalloc(ring->vmem_size);
1656 if (!(*ring->vmem))
1657 return -ENOMEM;
1658 }
1659 return 0;
1660}
1661
1662static void bnxt_free_rx_rings(struct bnxt *bp)
1663{
1664 int i;
1665
b6ab4b01 1666 if (!bp->rx_ring)
c0c050c5
MC		 1667 return;
1668
1669 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1670 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1671 struct bnxt_ring_struct *ring;
1672
c0c050c5
MC		 1673 kfree(rxr->rx_tpa);
1674 rxr->rx_tpa = NULL;
1675
1676 kfree(rxr->rx_agg_bmap);
1677 rxr->rx_agg_bmap = NULL;
1678
1679 ring = &rxr->rx_ring_struct;
1680 bnxt_free_ring(bp, ring);
1681
1682 ring = &rxr->rx_agg_ring_struct;
1683 bnxt_free_ring(bp, ring);
1684 }
1685}
1686
1687static int bnxt_alloc_rx_rings(struct bnxt *bp)
1688{
1689 int i, rc, agg_rings = 0, tpa_rings = 0;
1690
b6ab4b01
MC		 1691 if (!bp->rx_ring)
1692 return -ENOMEM;
1693
c0c050c5
MC		 1694 if (bp->flags & BNXT_FLAG_AGG_RINGS)
1695 agg_rings = 1;
1696
1697 if (bp->flags & BNXT_FLAG_TPA)
1698 tpa_rings = 1;
1699
1700 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1701 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1702 struct bnxt_ring_struct *ring;
1703
c0c050c5
MC		 1704 ring = &rxr->rx_ring_struct;
1705
1706 rc = bnxt_alloc_ring(bp, ring);
1707 if (rc)
1708 return rc;
1709
1710 if (agg_rings) {
1711 u16 mem_size;
1712
1713 ring = &rxr->rx_agg_ring_struct;
1714 rc = bnxt_alloc_ring(bp, ring);
1715 if (rc)
1716 return rc;
1717
1718 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1719 mem_size = rxr->rx_agg_bmap_size / 8;
1720 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1721 if (!rxr->rx_agg_bmap)
1722 return -ENOMEM;
1723
1724 if (tpa_rings) {
1725 rxr->rx_tpa = kcalloc(MAX_TPA,
1726 sizeof(struct bnxt_tpa_info),
1727 GFP_KERNEL);
1728 if (!rxr->rx_tpa)
1729 return -ENOMEM;
1730 }
1731 }
1732 }
1733 return 0;
1734}
1735
1736static void bnxt_free_tx_rings(struct bnxt *bp)
1737{
1738 int i;
1739 struct pci_dev *pdev = bp->pdev;
1740
b6ab4b01 1741 if (!bp->tx_ring)
c0c050c5
MC		 1742 return;
1743
1744 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1745 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1746 struct bnxt_ring_struct *ring;
1747
c0c050c5
MC		 1748 if (txr->tx_push) {
1749 dma_free_coherent(&pdev->dev, bp->tx_push_size,
1750 txr->tx_push, txr->tx_push_mapping);
1751 txr->tx_push = NULL;
1752 }
1753
1754 ring = &txr->tx_ring_struct;
1755
1756 bnxt_free_ring(bp, ring);
1757 }
1758}
1759
1760static int bnxt_alloc_tx_rings(struct bnxt *bp)
1761{
1762 int i, j, rc;
1763 struct pci_dev *pdev = bp->pdev;
1764
1765 bp->tx_push_size = 0;
1766 if (bp->tx_push_thresh) {
1767 int push_size;
1768
1769 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1770 bp->tx_push_thresh);
1771
4419dbe6 1772 if (push_size > 256) {
c0c050c5
MC		 1773 push_size = 0;
1774 bp->tx_push_thresh = 0;
1775 }
1776
1777 bp->tx_push_size = push_size;
1778 }
1779
1780 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1781 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1782 struct bnxt_ring_struct *ring;
1783
c0c050c5
MC		 1784 ring = &txr->tx_ring_struct;
1785
1786 rc = bnxt_alloc_ring(bp, ring);
1787 if (rc)
1788 return rc;
1789
1790 if (bp->tx_push_size) {
c0c050c5
MC		 1791 dma_addr_t mapping;
1792
1793 /* One pre-allocated DMA buffer to backup
1794 * TX push operation
1795 */
1796 txr->tx_push = dma_alloc_coherent(&pdev->dev,
1797 bp->tx_push_size,
1798 &txr->tx_push_mapping,
1799 GFP_KERNEL);
1800
1801 if (!txr->tx_push)
1802 return -ENOMEM;
1803
c0c050c5
MC		 1804 mapping = txr->tx_push_mapping +
1805 sizeof(struct tx_push_bd);
4419dbe6 1806 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 1807
4419dbe6 1808 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5
MC		 1809 }
1810 ring->queue_id = bp->q_info[j].queue_id;
1811 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1812 j++;
1813 }
1814 return 0;
1815}
1816
1817static void bnxt_free_cp_rings(struct bnxt *bp)
1818{
1819 int i;
1820
1821 if (!bp->bnapi)
1822 return;
1823
1824 for (i = 0; i < bp->cp_nr_rings; i++) {
1825 struct bnxt_napi *bnapi = bp->bnapi[i];
1826 struct bnxt_cp_ring_info *cpr;
1827 struct bnxt_ring_struct *ring;
1828
1829 if (!bnapi)
1830 continue;
1831
1832 cpr = &bnapi->cp_ring;
1833 ring = &cpr->cp_ring_struct;
1834
1835 bnxt_free_ring(bp, ring);
1836 }
1837}
1838
1839static int bnxt_alloc_cp_rings(struct bnxt *bp)
1840{
1841 int i, rc;
1842
1843 for (i = 0; i < bp->cp_nr_rings; i++) {
1844 struct bnxt_napi *bnapi = bp->bnapi[i];
1845 struct bnxt_cp_ring_info *cpr;
1846 struct bnxt_ring_struct *ring;
1847
1848 if (!bnapi)
1849 continue;
1850
1851 cpr = &bnapi->cp_ring;
1852 ring = &cpr->cp_ring_struct;
1853
1854 rc = bnxt_alloc_ring(bp, ring);
1855 if (rc)
1856 return rc;
1857 }
1858 return 0;
1859}
1860
1861static void bnxt_init_ring_struct(struct bnxt *bp)
1862{
1863 int i;
1864
1865 for (i = 0; i < bp->cp_nr_rings; i++) {
1866 struct bnxt_napi *bnapi = bp->bnapi[i];
1867 struct bnxt_cp_ring_info *cpr;
1868 struct bnxt_rx_ring_info *rxr;
1869 struct bnxt_tx_ring_info *txr;
1870 struct bnxt_ring_struct *ring;
1871
1872 if (!bnapi)
1873 continue;
1874
1875 cpr = &bnapi->cp_ring;
1876 ring = &cpr->cp_ring_struct;
1877 ring->nr_pages = bp->cp_nr_pages;
1878 ring->page_size = HW_CMPD_RING_SIZE;
1879 ring->pg_arr = (void **)cpr->cp_desc_ring;
1880 ring->dma_arr = cpr->cp_desc_mapping;
1881 ring->vmem_size = 0;
1882
b6ab4b01 1883 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 1884 if (!rxr)
1885 goto skip_rx;
1886
c0c050c5
MC		 1887 ring = &rxr->rx_ring_struct;
1888 ring->nr_pages = bp->rx_nr_pages;
1889 ring->page_size = HW_RXBD_RING_SIZE;
1890 ring->pg_arr = (void **)rxr->rx_desc_ring;
1891 ring->dma_arr = rxr->rx_desc_mapping;
1892 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1893 ring->vmem = (void **)&rxr->rx_buf_ring;
1894
1895 ring = &rxr->rx_agg_ring_struct;
1896 ring->nr_pages = bp->rx_agg_nr_pages;
1897 ring->page_size = HW_RXBD_RING_SIZE;
1898 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1899 ring->dma_arr = rxr->rx_agg_desc_mapping;
1900 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1901 ring->vmem = (void **)&rxr->rx_agg_ring;
1902
3b2b7d9d 1903skip_rx:
b6ab4b01 1904 txr = bnapi->tx_ring;
3b2b7d9d
MC		 1905 if (!txr)
1906 continue;
1907
c0c050c5
MC		 1908 ring = &txr->tx_ring_struct;
1909 ring->nr_pages = bp->tx_nr_pages;
1910 ring->page_size = HW_RXBD_RING_SIZE;
1911 ring->pg_arr = (void **)txr->tx_desc_ring;
1912 ring->dma_arr = txr->tx_desc_mapping;
1913 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1914 ring->vmem = (void **)&txr->tx_buf_ring;
1915 }
1916}
1917
1918static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1919{
1920 int i;
1921 u32 prod;
1922 struct rx_bd **rx_buf_ring;
1923
1924 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1925 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1926 int j;
1927 struct rx_bd *rxbd;
1928
1929 rxbd = rx_buf_ring[i];
1930 if (!rxbd)
1931 continue;
1932
1933 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1934 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1935 rxbd->rx_bd_opaque = prod;
1936 }
1937 }
1938}
1939
1940static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1941{
1942 struct net_device *dev = bp->dev;
c0c050c5
MC		 1943 struct bnxt_rx_ring_info *rxr;
1944 struct bnxt_ring_struct *ring;
1945 u32 prod, type;
1946 int i;
1947
c0c050c5
MC		 1948 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1949 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1950
1951 if (NET_IP_ALIGN == 2)
1952 type |= RX_BD_FLAGS_SOP;
1953
b6ab4b01 1954 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 1955 ring = &rxr->rx_ring_struct;
1956 bnxt_init_rxbd_pages(ring, type);
1957
1958 prod = rxr->rx_prod;
1959 for (i = 0; i < bp->rx_ring_size; i++) {
1960 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1961 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1962 ring_nr, i, bp->rx_ring_size);
1963 break;
1964 }
1965 prod = NEXT_RX(prod);
1966 }
1967 rxr->rx_prod = prod;
1968 ring->fw_ring_id = INVALID_HW_RING_ID;
1969
edd0c2cc
MC		 1970 ring = &rxr->rx_agg_ring_struct;
1971 ring->fw_ring_id = INVALID_HW_RING_ID;
1972
c0c050c5
MC		 1973 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1974 return 0;
1975
c0c050c5
MC		 1976 type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
1977 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
1978
1979 bnxt_init_rxbd_pages(ring, type);
1980
1981 prod = rxr->rx_agg_prod;
1982 for (i = 0; i < bp->rx_agg_ring_size; i++) {
1983 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
1984 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
1985 ring_nr, i, bp->rx_ring_size);
1986 break;
1987 }
1988 prod = NEXT_RX_AGG(prod);
1989 }
1990 rxr->rx_agg_prod = prod;
c0c050c5
MC		 1991
1992 if (bp->flags & BNXT_FLAG_TPA) {
1993 if (rxr->rx_tpa) {
1994 u8 *data;
1995 dma_addr_t mapping;
1996
1997 for (i = 0; i < MAX_TPA; i++) {
1998 data = __bnxt_alloc_rx_data(bp, &mapping,
1999 GFP_KERNEL);
2000 if (!data)
2001 return -ENOMEM;
2002
2003 rxr->rx_tpa[i].data = data;
2004 rxr->rx_tpa[i].mapping = mapping;
2005 }
2006 } else {
2007 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2008 return -ENOMEM;
2009 }
2010 }
2011
2012 return 0;
2013}
2014
2015static int bnxt_init_rx_rings(struct bnxt *bp)
2016{
2017 int i, rc = 0;
2018
2019 for (i = 0; i < bp->rx_nr_rings; i++) {
2020 rc = bnxt_init_one_rx_ring(bp, i);
2021 if (rc)
2022 break;
2023 }
2024
2025 return rc;
2026}
2027
2028static int bnxt_init_tx_rings(struct bnxt *bp)
2029{
2030 u16 i;
2031
2032 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2033 MAX_SKB_FRAGS + 1);
2034
2035 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2036 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2037 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2038
2039 ring->fw_ring_id = INVALID_HW_RING_ID;
2040 }
2041
2042 return 0;
2043}
2044
2045static void bnxt_free_ring_grps(struct bnxt *bp)
2046{
2047 kfree(bp->grp_info);
2048 bp->grp_info = NULL;
2049}
2050
2051static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2052{
2053 int i;
2054
2055 if (irq_re_init) {
2056 bp->grp_info = kcalloc(bp->cp_nr_rings,
2057 sizeof(struct bnxt_ring_grp_info),
2058 GFP_KERNEL);
2059 if (!bp->grp_info)
2060 return -ENOMEM;
2061 }
2062 for (i = 0; i < bp->cp_nr_rings; i++) {
2063 if (irq_re_init)
2064 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2065 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2066 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2067 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2068 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2069 }
2070 return 0;
2071}
2072
2073static void bnxt_free_vnics(struct bnxt *bp)
2074{
2075 kfree(bp->vnic_info);
2076 bp->vnic_info = NULL;
2077 bp->nr_vnics = 0;
2078}
2079
2080static int bnxt_alloc_vnics(struct bnxt *bp)
2081{
2082 int num_vnics = 1;
2083
2084#ifdef CONFIG_RFS_ACCEL
2085 if (bp->flags & BNXT_FLAG_RFS)
2086 num_vnics += bp->rx_nr_rings;
2087#endif
2088
2089 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2090 GFP_KERNEL);
2091 if (!bp->vnic_info)
2092 return -ENOMEM;
2093
2094 bp->nr_vnics = num_vnics;
2095 return 0;
2096}
2097
2098static void bnxt_init_vnics(struct bnxt *bp)
2099{
2100 int i;
2101
2102 for (i = 0; i < bp->nr_vnics; i++) {
2103 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2104
2105 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2106 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2107 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2108
2109 if (bp->vnic_info[i].rss_hash_key) {
2110 if (i == 0)
2111 prandom_bytes(vnic->rss_hash_key,
2112 HW_HASH_KEY_SIZE);
2113 else
2114 memcpy(vnic->rss_hash_key,
2115 bp->vnic_info[0].rss_hash_key,
2116 HW_HASH_KEY_SIZE);
2117 }
2118 }
2119}
2120
2121static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2122{
2123 int pages;
2124
2125 pages = ring_size / desc_per_pg;
2126
2127 if (!pages)
2128 return 1;
2129
2130 pages++;
2131
2132 while (pages & (pages - 1))
2133 pages++;
2134
2135 return pages;
2136}
2137
2138static void bnxt_set_tpa_flags(struct bnxt *bp)
2139{
2140 bp->flags &= ~BNXT_FLAG_TPA;
2141 if (bp->dev->features & NETIF_F_LRO)
2142 bp->flags |= BNXT_FLAG_LRO;
2143 if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2144 bp->flags |= BNXT_FLAG_GRO;
2145}
2146
2147/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2148 * be set on entry.
2149 */
2150void bnxt_set_ring_params(struct bnxt *bp)
2151{
2152 u32 ring_size, rx_size, rx_space;
2153 u32 agg_factor = 0, agg_ring_size = 0;
2154
2155 /* 8 for CRC and VLAN */
2156 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2157
2158 rx_space = rx_size + NET_SKB_PAD +
2159 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2160
2161 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2162 ring_size = bp->rx_ring_size;
2163 bp->rx_agg_ring_size = 0;
2164 bp->rx_agg_nr_pages = 0;
2165
2166 if (bp->flags & BNXT_FLAG_TPA)
2167 agg_factor = 4;
2168
2169 bp->flags &= ~BNXT_FLAG_JUMBO;
2170 if (rx_space > PAGE_SIZE) {
2171 u32 jumbo_factor;
2172
2173 bp->flags |= BNXT_FLAG_JUMBO;
2174 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2175 if (jumbo_factor > agg_factor)
2176 agg_factor = jumbo_factor;
2177 }
2178 agg_ring_size = ring_size * agg_factor;
2179
2180 if (agg_ring_size) {
2181 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2182 RX_DESC_CNT);
2183 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2184 u32 tmp = agg_ring_size;
2185
2186 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2187 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2188 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2189 tmp, agg_ring_size);
2190 }
2191 bp->rx_agg_ring_size = agg_ring_size;
2192 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2193 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2194 rx_space = rx_size + NET_SKB_PAD +
2195 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2196 }
2197
2198 bp->rx_buf_use_size = rx_size;
2199 bp->rx_buf_size = rx_space;
2200
2201 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2202 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2203
2204 ring_size = bp->tx_ring_size;
2205 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2206 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2207
2208 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2209 bp->cp_ring_size = ring_size;
2210
2211 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2212 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2213 bp->cp_nr_pages = MAX_CP_PAGES;
2214 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2215 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2216 ring_size, bp->cp_ring_size);
2217 }
2218 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2219 bp->cp_ring_mask = bp->cp_bit - 1;
2220}
2221
2222static void bnxt_free_vnic_attributes(struct bnxt *bp)
2223{
2224 int i;
2225 struct bnxt_vnic_info *vnic;
2226 struct pci_dev *pdev = bp->pdev;
2227
2228 if (!bp->vnic_info)
2229 return;
2230
2231 for (i = 0; i < bp->nr_vnics; i++) {
2232 vnic = &bp->vnic_info[i];
2233
2234 kfree(vnic->fw_grp_ids);
2235 vnic->fw_grp_ids = NULL;
2236
2237 kfree(vnic->uc_list);
2238 vnic->uc_list = NULL;
2239
2240 if (vnic->mc_list) {
2241 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2242 vnic->mc_list, vnic->mc_list_mapping);
2243 vnic->mc_list = NULL;
2244 }
2245
2246 if (vnic->rss_table) {
2247 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2248 vnic->rss_table,
2249 vnic->rss_table_dma_addr);
2250 vnic->rss_table = NULL;
2251 }
2252
2253 vnic->rss_hash_key = NULL;
2254 vnic->flags = 0;
2255 }
2256}
2257
2258static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2259{
2260 int i, rc = 0, size;
2261 struct bnxt_vnic_info *vnic;
2262 struct pci_dev *pdev = bp->pdev;
2263 int max_rings;
2264
2265 for (i = 0; i < bp->nr_vnics; i++) {
2266 vnic = &bp->vnic_info[i];
2267
2268 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2269 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2270
2271 if (mem_size > 0) {
2272 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2273 if (!vnic->uc_list) {
2274 rc = -ENOMEM;
2275 goto out;
2276 }
2277 }
2278 }
2279
2280 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2281 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2282 vnic->mc_list =
2283 dma_alloc_coherent(&pdev->dev,
2284 vnic->mc_list_size,
2285 &vnic->mc_list_mapping,
2286 GFP_KERNEL);
2287 if (!vnic->mc_list) {
2288 rc = -ENOMEM;
2289 goto out;
2290 }
2291 }
2292
2293 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2294 max_rings = bp->rx_nr_rings;
2295 else
2296 max_rings = 1;
2297
2298 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2299 if (!vnic->fw_grp_ids) {
2300 rc = -ENOMEM;
2301 goto out;
2302 }
2303
2304 /* Allocate rss table and hash key */
2305 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2306 &vnic->rss_table_dma_addr,
2307 GFP_KERNEL);
2308 if (!vnic->rss_table) {
2309 rc = -ENOMEM;
2310 goto out;
2311 }
2312
2313 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2314
2315 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2316 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2317 }
2318 return 0;
2319
2320out:
2321 return rc;
2322}
2323
2324static void bnxt_free_hwrm_resources(struct bnxt *bp)
2325{
2326 struct pci_dev *pdev = bp->pdev;
2327
2328 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2329 bp->hwrm_cmd_resp_dma_addr);
2330
2331 bp->hwrm_cmd_resp_addr = NULL;
2332 if (bp->hwrm_dbg_resp_addr) {
2333 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2334 bp->hwrm_dbg_resp_addr,
2335 bp->hwrm_dbg_resp_dma_addr);
2336
2337 bp->hwrm_dbg_resp_addr = NULL;
2338 }
2339}
2340
2341static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2342{
2343 struct pci_dev *pdev = bp->pdev;
2344
2345 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2346 &bp->hwrm_cmd_resp_dma_addr,
2347 GFP_KERNEL);
2348 if (!bp->hwrm_cmd_resp_addr)
2349 return -ENOMEM;
2350 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2351 HWRM_DBG_REG_BUF_SIZE,
2352 &bp->hwrm_dbg_resp_dma_addr,
2353 GFP_KERNEL);
2354 if (!bp->hwrm_dbg_resp_addr)
2355 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2356
2357 return 0;
2358}
2359
2360static void bnxt_free_stats(struct bnxt *bp)
2361{
2362 u32 size, i;
2363 struct pci_dev *pdev = bp->pdev;
2364
2365 if (!bp->bnapi)
2366 return;
2367
2368 size = sizeof(struct ctx_hw_stats);
2369
2370 for (i = 0; i < bp->cp_nr_rings; i++) {
2371 struct bnxt_napi *bnapi = bp->bnapi[i];
2372 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2373
2374 if (cpr->hw_stats) {
2375 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2376 cpr->hw_stats_map);
2377 cpr->hw_stats = NULL;
2378 }
2379 }
2380}
2381
2382static int bnxt_alloc_stats(struct bnxt *bp)
2383{
2384 u32 size, i;
2385 struct pci_dev *pdev = bp->pdev;
2386
2387 size = sizeof(struct ctx_hw_stats);
2388
2389 for (i = 0; i < bp->cp_nr_rings; i++) {
2390 struct bnxt_napi *bnapi = bp->bnapi[i];
2391 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2392
2393 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2394 &cpr->hw_stats_map,
2395 GFP_KERNEL);
2396 if (!cpr->hw_stats)
2397 return -ENOMEM;
2398
2399 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2400 }
2401 return 0;
2402}
2403
2404static void bnxt_clear_ring_indices(struct bnxt *bp)
2405{
2406 int i;
2407
2408 if (!bp->bnapi)
2409 return;
2410
2411 for (i = 0; i < bp->cp_nr_rings; i++) {
2412 struct bnxt_napi *bnapi = bp->bnapi[i];
2413 struct bnxt_cp_ring_info *cpr;
2414 struct bnxt_rx_ring_info *rxr;
2415 struct bnxt_tx_ring_info *txr;
2416
2417 if (!bnapi)
2418 continue;
2419
2420 cpr = &bnapi->cp_ring;
2421 cpr->cp_raw_cons = 0;
2422
b6ab4b01 2423 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2424 if (txr) {
2425 txr->tx_prod = 0;
2426 txr->tx_cons = 0;
2427 }
c0c050c5 2428
b6ab4b01 2429 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2430 if (rxr) {
2431 rxr->rx_prod = 0;
2432 rxr->rx_agg_prod = 0;
2433 rxr->rx_sw_agg_prod = 0;
2434 }
c0c050c5
MC		 2435 }
2436}
2437
2438static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2439{
2440#ifdef CONFIG_RFS_ACCEL
2441 int i;
2442
2443 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2444 * safe to delete the hash table.
2445 */
2446 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2447 struct hlist_head *head;
2448 struct hlist_node *tmp;
2449 struct bnxt_ntuple_filter *fltr;
2450
2451 head = &bp->ntp_fltr_hash_tbl[i];
2452 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2453 hlist_del(&fltr->hash);
2454 kfree(fltr);
2455 }
2456 }
2457 if (irq_reinit) {
2458 kfree(bp->ntp_fltr_bmap);
2459 bp->ntp_fltr_bmap = NULL;
2460 }
2461 bp->ntp_fltr_count = 0;
2462#endif
2463}
2464
2465static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2466{
2467#ifdef CONFIG_RFS_ACCEL
2468 int i, rc = 0;
2469
2470 if (!(bp->flags & BNXT_FLAG_RFS))
2471 return 0;
2472
2473 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2474 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2475
2476 bp->ntp_fltr_count = 0;
2477 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2478 GFP_KERNEL);
2479
2480 if (!bp->ntp_fltr_bmap)
2481 rc = -ENOMEM;
2482
2483 return rc;
2484#else
2485 return 0;
2486#endif
2487}
2488
2489static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2490{
2491 bnxt_free_vnic_attributes(bp);
2492 bnxt_free_tx_rings(bp);
2493 bnxt_free_rx_rings(bp);
2494 bnxt_free_cp_rings(bp);
2495 bnxt_free_ntp_fltrs(bp, irq_re_init);
2496 if (irq_re_init) {
2497 bnxt_free_stats(bp);
2498 bnxt_free_ring_grps(bp);
2499 bnxt_free_vnics(bp);
b6ab4b01
MC		 2500 kfree(bp->tx_ring);
2501 bp->tx_ring = NULL;
2502 kfree(bp->rx_ring);
2503 bp->rx_ring = NULL;
c0c050c5
MC		 2504 kfree(bp->bnapi);
2505 bp->bnapi = NULL;
2506 } else {
2507 bnxt_clear_ring_indices(bp);
2508 }
2509}
2510
2511static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2512{
01657bcd 2513 int i, j, rc, size, arr_size;
c0c050c5
MC		 2514 void *bnapi;
2515
2516 if (irq_re_init) {
2517 /* Allocate bnapi mem pointer array and mem block for
2518 * all queues
2519 */
2520 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2521 bp->cp_nr_rings);
2522 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2523 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2524 if (!bnapi)
2525 return -ENOMEM;
2526
2527 bp->bnapi = bnapi;
2528 bnapi += arr_size;
2529 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2530 bp->bnapi[i] = bnapi;
2531 bp->bnapi[i]->index = i;
2532 bp->bnapi[i]->bp = bp;
2533 }
2534
b6ab4b01
MC		 2535 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2536 sizeof(struct bnxt_rx_ring_info),
2537 GFP_KERNEL);
2538 if (!bp->rx_ring)
2539 return -ENOMEM;
2540
2541 for (i = 0; i < bp->rx_nr_rings; i++) {
2542 bp->rx_ring[i].bnapi = bp->bnapi[i];
2543 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2544 }
2545
2546 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2547 sizeof(struct bnxt_tx_ring_info),
2548 GFP_KERNEL);
2549 if (!bp->tx_ring)
2550 return -ENOMEM;
2551
01657bcd
MC		 2552 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2553 j = 0;
2554 else
2555 j = bp->rx_nr_rings;
2556
2557 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2558 bp->tx_ring[i].bnapi = bp->bnapi[j];
2559 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
b6ab4b01
MC		 2560 }
2561
c0c050c5
MC		 2562 rc = bnxt_alloc_stats(bp);
2563 if (rc)
2564 goto alloc_mem_err;
2565
2566 rc = bnxt_alloc_ntp_fltrs(bp);
2567 if (rc)
2568 goto alloc_mem_err;
2569
2570 rc = bnxt_alloc_vnics(bp);
2571 if (rc)
2572 goto alloc_mem_err;
2573 }
2574
2575 bnxt_init_ring_struct(bp);
2576
2577 rc = bnxt_alloc_rx_rings(bp);
2578 if (rc)
2579 goto alloc_mem_err;
2580
2581 rc = bnxt_alloc_tx_rings(bp);
2582 if (rc)
2583 goto alloc_mem_err;
2584
2585 rc = bnxt_alloc_cp_rings(bp);
2586 if (rc)
2587 goto alloc_mem_err;
2588
2589 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2590 BNXT_VNIC_UCAST_FLAG;
2591 rc = bnxt_alloc_vnic_attributes(bp);
2592 if (rc)
2593 goto alloc_mem_err;
2594 return 0;
2595
2596alloc_mem_err:
2597 bnxt_free_mem(bp, true);
2598 return rc;
2599}
2600
2601void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2602 u16 cmpl_ring, u16 target_id)
2603{
a8643e16 2604 struct input *req = request;
c0c050c5 2605
a8643e16
MC		 2606 req->req_type = cpu_to_le16(req_type);
2607 req->cmpl_ring = cpu_to_le16(cmpl_ring);
2608 req->target_id = cpu_to_le16(target_id);
c0c050c5
MC		 2609 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2610}
2611
fbfbc485
MC		 2612static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
2613 int timeout, bool silent)
c0c050c5
MC		 2614{
2615 int i, intr_process, rc;
a8643e16 2616 struct input *req = msg;
c0c050c5
MC		 2617 u32 *data = msg;
2618 __le32 *resp_len, *valid;
2619 u16 cp_ring_id, len = 0;
2620 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2621
a8643e16 2622 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
c0c050c5 2623 memset(resp, 0, PAGE_SIZE);
a8643e16 2624 cp_ring_id = le16_to_cpu(req->cmpl_ring);
c0c050c5
MC		 2625 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2626
2627 /* Write request msg to hwrm channel */
2628 __iowrite32_copy(bp->bar0, data, msg_len / 4);
2629
d79979a1
MC		 2630 for (i = msg_len; i < HWRM_MAX_REQ_LEN; i += 4)
2631 writel(0, bp->bar0 + i);
2632
c0c050c5
MC		 2633 /* currently supports only one outstanding message */
2634 if (intr_process)
a8643e16 2635 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
c0c050c5
MC		 2636
2637 /* Ring channel doorbell */
2638 writel(1, bp->bar0 + 0x100);
2639
ff4fe81d
MC		 2640 if (!timeout)
2641 timeout = DFLT_HWRM_CMD_TIMEOUT;
2642
c0c050c5
MC		 2643 i = 0;
2644 if (intr_process) {
2645 /* Wait until hwrm response cmpl interrupt is processed */
2646 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2647 i++ < timeout) {
2648 usleep_range(600, 800);
2649 }
2650
2651 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2652 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
a8643e16 2653 le16_to_cpu(req->req_type));
c0c050c5
MC		 2654 return -1;
2655 }
2656 } else {
2657 /* Check if response len is updated */
2658 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2659 for (i = 0; i < timeout; i++) {
2660 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2661 HWRM_RESP_LEN_SFT;
2662 if (len)
2663 break;
2664 usleep_range(600, 800);
2665 }
2666
2667 if (i >= timeout) {
2668 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
a8643e16
MC		 2669 timeout, le16_to_cpu(req->req_type),
2670 le16_to_cpu(req->seq_id), *resp_len);
c0c050c5
MC		 2671 return -1;
2672 }
2673
2674 /* Last word of resp contains valid bit */
2675 valid = bp->hwrm_cmd_resp_addr + len - 4;
2676 for (i = 0; i < timeout; i++) {
2677 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2678 break;
2679 usleep_range(600, 800);
2680 }
2681
2682 if (i >= timeout) {
2683 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
a8643e16
MC		 2684 timeout, le16_to_cpu(req->req_type),
2685 le16_to_cpu(req->seq_id), len, *valid);
c0c050c5
MC		 2686 return -1;
2687 }
2688 }
2689
2690 rc = le16_to_cpu(resp->error_code);
fbfbc485 2691 if (rc && !silent)
c0c050c5
MC		 2692 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2693 le16_to_cpu(resp->req_type),
2694 le16_to_cpu(resp->seq_id), rc);
fbfbc485
MC		 2695 return rc;
2696}
2697
2698int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2699{
2700 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
c0c050c5
MC		 2701}
2702
2703int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2704{
2705 int rc;
2706
2707 mutex_lock(&bp->hwrm_cmd_lock);
2708 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2709 mutex_unlock(&bp->hwrm_cmd_lock);
2710 return rc;
2711}
2712
90e20921
MC		 2713int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
2714 int timeout)
2715{
2716 int rc;
2717
2718 mutex_lock(&bp->hwrm_cmd_lock);
2719 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
2720 mutex_unlock(&bp->hwrm_cmd_lock);
2721 return rc;
2722}
2723
c0c050c5
MC		 2724static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2725{
2726 struct hwrm_func_drv_rgtr_input req = {0};
2727 int i;
2728
2729 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2730
2731 req.enables =
2732 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2733 FUNC_DRV_RGTR_REQ_ENABLES_VER |
2734 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2735
2736 /* TODO: current async event fwd bits are not defined and the firmware
2737 * only checks if it is non-zero to enable async event forwarding
2738 */
2739 req.async_event_fwd[0] |= cpu_to_le32(1);
2740 req.os_type = cpu_to_le16(1);
2741 req.ver_maj = DRV_VER_MAJ;
2742 req.ver_min = DRV_VER_MIN;
2743 req.ver_upd = DRV_VER_UPD;
2744
2745 if (BNXT_PF(bp)) {
de68f5de 2746 DECLARE_BITMAP(vf_req_snif_bmap, 256);
c0c050c5
MC		 2747 u32 *data = (u32 *)vf_req_snif_bmap;
2748
de68f5de 2749 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
c0c050c5
MC		 2750 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2751 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2752
de68f5de
MC		 2753 for (i = 0; i < 8; i++)
2754 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2755
c0c050c5
MC		 2756 req.enables |=
2757 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2758 }
2759
2760 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2761}
2762
be58a0da
JH		 2763static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2764{
2765 struct hwrm_func_drv_unrgtr_input req = {0};
2766
2767 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2768 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2769}
2770
c0c050c5
MC		 2771static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2772{
2773 u32 rc = 0;
2774 struct hwrm_tunnel_dst_port_free_input req = {0};
2775
2776 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2777 req.tunnel_type = tunnel_type;
2778
2779 switch (tunnel_type) {
2780 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2781 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2782 break;
2783 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2784 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2785 break;
2786 default:
2787 break;
2788 }
2789
2790 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2791 if (rc)
2792 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2793 rc);
2794 return rc;
2795}
2796
2797static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2798 u8 tunnel_type)
2799{
2800 u32 rc = 0;
2801 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2802 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2803
2804 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2805
2806 req.tunnel_type = tunnel_type;
2807 req.tunnel_dst_port_val = port;
2808
2809 mutex_lock(&bp->hwrm_cmd_lock);
2810 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2811 if (rc) {
2812 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2813 rc);
2814 goto err_out;
2815 }
2816
2817 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2818 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2819
2820 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2821 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2822err_out:
2823 mutex_unlock(&bp->hwrm_cmd_lock);
2824 return rc;
2825}
2826
2827static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2828{
2829 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2830 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2831
2832 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 2833 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 2834
2835 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2836 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2837 req.mask = cpu_to_le32(vnic->rx_mask);
2838 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2839}
2840
2841#ifdef CONFIG_RFS_ACCEL
2842static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2843 struct bnxt_ntuple_filter *fltr)
2844{
2845 struct hwrm_cfa_ntuple_filter_free_input req = {0};
2846
2847 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2848 req.ntuple_filter_id = fltr->filter_id;
2849 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2850}
2851
2852#define BNXT_NTP_FLTR_FLAGS \
2853 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2854 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2855 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2856 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2857 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2858 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2859 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2860 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2861 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2862 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2863 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2864 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2865 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 2866 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5
MC		 2867
2868static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2869 struct bnxt_ntuple_filter *fltr)
2870{
2871 int rc = 0;
2872 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2873 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2874 bp->hwrm_cmd_resp_addr;
2875 struct flow_keys *keys = &fltr->fkeys;
2876 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2877
2878 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2879 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2880
2881 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2882
2883 req.ethertype = htons(ETH_P_IP);
2884 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 2885 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 2886 req.ip_protocol = keys->basic.ip_proto;
2887
2888 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2889 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2890 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2891 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2892
2893 req.src_port = keys->ports.src;
2894 req.src_port_mask = cpu_to_be16(0xffff);
2895 req.dst_port = keys->ports.dst;
2896 req.dst_port_mask = cpu_to_be16(0xffff);
2897
c193554e 2898 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 2899 mutex_lock(&bp->hwrm_cmd_lock);
2900 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2901 if (!rc)
2902 fltr->filter_id = resp->ntuple_filter_id;
2903 mutex_unlock(&bp->hwrm_cmd_lock);
2904 return rc;
2905}
2906#endif
2907
2908static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2909 u8 *mac_addr)
2910{
2911 u32 rc = 0;
2912 struct hwrm_cfa_l2_filter_alloc_input req = {0};
2913 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2914
2915 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2916 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2917 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 2918 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 2919 req.enables =
2920 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 2921 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 2922 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2923 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2924 req.l2_addr_mask[0] = 0xff;
2925 req.l2_addr_mask[1] = 0xff;
2926 req.l2_addr_mask[2] = 0xff;
2927 req.l2_addr_mask[3] = 0xff;
2928 req.l2_addr_mask[4] = 0xff;
2929 req.l2_addr_mask[5] = 0xff;
2930
2931 mutex_lock(&bp->hwrm_cmd_lock);
2932 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2933 if (!rc)
2934 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2935 resp->l2_filter_id;
2936 mutex_unlock(&bp->hwrm_cmd_lock);
2937 return rc;
2938}
2939
2940static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2941{
2942 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2943 int rc = 0;
2944
2945 /* Any associated ntuple filters will also be cleared by firmware. */
2946 mutex_lock(&bp->hwrm_cmd_lock);
2947 for (i = 0; i < num_of_vnics; i++) {
2948 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2949
2950 for (j = 0; j < vnic->uc_filter_count; j++) {
2951 struct hwrm_cfa_l2_filter_free_input req = {0};
2952
2953 bnxt_hwrm_cmd_hdr_init(bp, &req,
2954 HWRM_CFA_L2_FILTER_FREE, -1, -1);
2955
2956 req.l2_filter_id = vnic->fw_l2_filter_id[j];
2957
2958 rc = _hwrm_send_message(bp, &req, sizeof(req),
2959 HWRM_CMD_TIMEOUT);
2960 }
2961 vnic->uc_filter_count = 0;
2962 }
2963 mutex_unlock(&bp->hwrm_cmd_lock);
2964
2965 return rc;
2966}
2967
2968static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
2969{
2970 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2971 struct hwrm_vnic_tpa_cfg_input req = {0};
2972
2973 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
2974
2975 if (tpa_flags) {
2976 u16 mss = bp->dev->mtu - 40;
2977 u32 nsegs, n, segs = 0, flags;
2978
2979 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
2980 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
2981 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
2982 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
2983 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
2984 if (tpa_flags & BNXT_FLAG_GRO)
2985 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
2986
2987 req.flags = cpu_to_le32(flags);
2988
2989 req.enables =
2990 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 2991 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
2992 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 2993
2994 /* Number of segs are log2 units, and first packet is not
2995 * included as part of this units.
2996 */
2997 if (mss <= PAGE_SIZE) {
2998 n = PAGE_SIZE / mss;
2999 nsegs = (MAX_SKB_FRAGS - 1) * n;
3000 } else {
3001 n = mss / PAGE_SIZE;
3002 if (mss & (PAGE_SIZE - 1))
3003 n++;
3004 nsegs = (MAX_SKB_FRAGS - n) / n;
3005 }
3006
3007 segs = ilog2(nsegs);
3008 req.max_agg_segs = cpu_to_le16(segs);
3009 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 3010
3011 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 3012 }
3013 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3014
3015 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3016}
3017
3018static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3019{
3020 u32 i, j, max_rings;
3021 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3022 struct hwrm_vnic_rss_cfg_input req = {0};
3023
3024 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
3025 return 0;
3026
3027 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3028 if (set_rss) {
3029 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3030 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3031 BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3032 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3033
3034 req.hash_type = cpu_to_le32(vnic->hash_type);
3035
3036 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3037 max_rings = bp->rx_nr_rings;
3038 else
3039 max_rings = 1;
3040
3041 /* Fill the RSS indirection table with ring group ids */
3042 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3043 if (j == max_rings)
3044 j = 0;
3045 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3046 }
3047
3048 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3049 req.hash_key_tbl_addr =
3050 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3051 }
3052 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3053 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3054}
3055
3056static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3057{
3058 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3059 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3060
3061 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3062 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3063 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3064 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3065 req.enables =
3066 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3067 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3068 /* thresholds not implemented in firmware yet */
3069 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3070 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3071 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3072 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3073}
3074
3075static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3076{
3077 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3078
3079 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3080 req.rss_cos_lb_ctx_id =
3081 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3082
3083 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3084 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3085}
3086
3087static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3088{
3089 int i;
3090
3091 for (i = 0; i < bp->nr_vnics; i++) {
3092 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3093
3094 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3095 bnxt_hwrm_vnic_ctx_free_one(bp, i);
3096 }
3097 bp->rsscos_nr_ctxs = 0;
3098}
3099
3100static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3101{
3102 int rc;
3103 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3104 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3105 bp->hwrm_cmd_resp_addr;
3106
3107 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3108 -1);
3109
3110 mutex_lock(&bp->hwrm_cmd_lock);
3111 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3112 if (!rc)
3113 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3114 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3115 mutex_unlock(&bp->hwrm_cmd_lock);
3116
3117 return rc;
3118}
3119
3120static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3121{
b81a90d3 3122 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 3123 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3124 struct hwrm_vnic_cfg_input req = {0};
3125
3126 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3127 /* Only RSS support for now TBD: COS & LB */
3128 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3129 VNIC_CFG_REQ_ENABLES_RSS_RULE);
3130 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3131 req.cos_rule = cpu_to_le16(0xffff);
3132 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 3133 ring = 0;
c0c050c5 3134 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 3135 ring = vnic_id - 1;
c0c050c5 3136
b81a90d3 3137 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5
MC		 3138 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3139 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3140
3141 req.lb_rule = cpu_to_le16(0xffff);
3142 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3143 VLAN_HLEN);
3144
3145 if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3146 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3147
3148 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3149}
3150
3151static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3152{
3153 u32 rc = 0;
3154
3155 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3156 struct hwrm_vnic_free_input req = {0};
3157
3158 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3159 req.vnic_id =
3160 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3161
3162 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3163 if (rc)
3164 return rc;
3165 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3166 }
3167 return rc;
3168}
3169
3170static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3171{
3172 u16 i;
3173
3174 for (i = 0; i < bp->nr_vnics; i++)
3175 bnxt_hwrm_vnic_free_one(bp, i);
3176}
3177
b81a90d3
MC		 3178static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3179 unsigned int start_rx_ring_idx,
3180 unsigned int nr_rings)
c0c050c5 3181{
b81a90d3
MC		 3182 int rc = 0;
3183 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 3184 struct hwrm_vnic_alloc_input req = {0};
3185 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3186
3187 /* map ring groups to this vnic */
b81a90d3
MC		 3188 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3189 grp_idx = bp->rx_ring[i].bnapi->index;
3190 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 3191 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 3192 j, nr_rings);
c0c050c5
MC		 3193 break;
3194 }
3195 bp->vnic_info[vnic_id].fw_grp_ids[j] =
b81a90d3 3196 bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 3197 }
3198
3199 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3200 if (vnic_id == 0)
3201 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3202
3203 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3204
3205 mutex_lock(&bp->hwrm_cmd_lock);
3206 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3207 if (!rc)
3208 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3209 mutex_unlock(&bp->hwrm_cmd_lock);
3210 return rc;
3211}
3212
3213static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3214{
3215 u16 i;
3216 u32 rc = 0;
3217
3218 mutex_lock(&bp->hwrm_cmd_lock);
3219 for (i = 0; i < bp->rx_nr_rings; i++) {
3220 struct hwrm_ring_grp_alloc_input req = {0};
3221 struct hwrm_ring_grp_alloc_output *resp =
3222 bp->hwrm_cmd_resp_addr;
b81a90d3 3223 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 3224
3225 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3226
b81a90d3
MC		 3227 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3228 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3229 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3230 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 3231
3232 rc = _hwrm_send_message(bp, &req, sizeof(req),
3233 HWRM_CMD_TIMEOUT);
3234 if (rc)
3235 break;
3236
b81a90d3
MC		 3237 bp->grp_info[grp_idx].fw_grp_id =
3238 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 3239 }
3240 mutex_unlock(&bp->hwrm_cmd_lock);
3241 return rc;
3242}
3243
3244static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3245{
3246 u16 i;
3247 u32 rc = 0;
3248 struct hwrm_ring_grp_free_input req = {0};
3249
3250 if (!bp->grp_info)
3251 return 0;
3252
3253 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3254
3255 mutex_lock(&bp->hwrm_cmd_lock);
3256 for (i = 0; i < bp->cp_nr_rings; i++) {
3257 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3258 continue;
3259 req.ring_group_id =
3260 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3261
3262 rc = _hwrm_send_message(bp, &req, sizeof(req),
3263 HWRM_CMD_TIMEOUT);
3264 if (rc)
3265 break;
3266 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3267 }
3268 mutex_unlock(&bp->hwrm_cmd_lock);
3269 return rc;
3270}
3271
3272static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3273 struct bnxt_ring_struct *ring,
3274 u32 ring_type, u32 map_index,
3275 u32 stats_ctx_id)
3276{
3277 int rc = 0, err = 0;
3278 struct hwrm_ring_alloc_input req = {0};
3279 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3280 u16 ring_id;
3281
3282 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3283
3284 req.enables = 0;
3285 if (ring->nr_pages > 1) {
3286 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3287 /* Page size is in log2 units */
3288 req.page_size = BNXT_PAGE_SHIFT;
3289 req.page_tbl_depth = 1;
3290 } else {
3291 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3292 }
3293 req.fbo = 0;
3294 /* Association of ring index with doorbell index and MSIX number */
3295 req.logical_id = cpu_to_le16(map_index);
3296
3297 switch (ring_type) {
3298 case HWRM_RING_ALLOC_TX:
3299 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3300 /* Association of transmit ring with completion ring */
3301 req.cmpl_ring_id =
3302 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3303 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3304 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3305 req.queue_id = cpu_to_le16(ring->queue_id);
3306 break;
3307 case HWRM_RING_ALLOC_RX:
3308 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3309 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3310 break;
3311 case HWRM_RING_ALLOC_AGG:
3312 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3313 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3314 break;
3315 case HWRM_RING_ALLOC_CMPL:
3316 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3317 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3318 if (bp->flags & BNXT_FLAG_USING_MSIX)
3319 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3320 break;
3321 default:
3322 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3323 ring_type);
3324 return -1;
3325 }
3326
3327 mutex_lock(&bp->hwrm_cmd_lock);
3328 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3329 err = le16_to_cpu(resp->error_code);
3330 ring_id = le16_to_cpu(resp->ring_id);
3331 mutex_unlock(&bp->hwrm_cmd_lock);
3332
3333 if (rc || err) {
3334 switch (ring_type) {
3335 case RING_FREE_REQ_RING_TYPE_CMPL:
3336 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3337 rc, err);
3338 return -1;
3339
3340 case RING_FREE_REQ_RING_TYPE_RX:
3341 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3342 rc, err);
3343 return -1;
3344
3345 case RING_FREE_REQ_RING_TYPE_TX:
3346 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3347 rc, err);
3348 return -1;
3349
3350 default:
3351 netdev_err(bp->dev, "Invalid ring\n");
3352 return -1;
3353 }
3354 }
3355 ring->fw_ring_id = ring_id;
3356 return rc;
3357}
3358
3359static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3360{
3361 int i, rc = 0;
3362
edd0c2cc
MC		 3363 for (i = 0; i < bp->cp_nr_rings; i++) {
3364 struct bnxt_napi *bnapi = bp->bnapi[i];
3365 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3366 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
c0c050c5 3367
edd0c2cc
MC		 3368 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3369 INVALID_STATS_CTX_ID);
3370 if (rc)
3371 goto err_out;
3372 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3373 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3374 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3375 }
3376
edd0c2cc 3377 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3378 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3379 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3380 u32 map_idx = txr->bnapi->index;
3381 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
c0c050c5 3382
b81a90d3
MC		 3383 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3384 map_idx, fw_stats_ctx);
edd0c2cc
MC		 3385 if (rc)
3386 goto err_out;
b81a90d3 3387 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3388 }
3389
edd0c2cc 3390 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3391 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3392 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 3393 u32 map_idx = rxr->bnapi->index;
c0c050c5 3394
b81a90d3
MC		 3395 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3396 map_idx, INVALID_STATS_CTX_ID);
edd0c2cc
MC		 3397 if (rc)
3398 goto err_out;
b81a90d3 3399 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
edd0c2cc 3400 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
b81a90d3 3401 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3402 }
3403
3404 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3405 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3406 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 3407 struct bnxt_ring_struct *ring =
3408 &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3409 u32 grp_idx = rxr->bnapi->index;
3410 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5
MC		 3411
3412 rc = hwrm_ring_alloc_send_msg(bp, ring,
3413 HWRM_RING_ALLOC_AGG,
b81a90d3 3414 map_idx,
c0c050c5
MC		 3415 INVALID_STATS_CTX_ID);
3416 if (rc)
3417 goto err_out;
3418
b81a90d3 3419 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3420 writel(DB_KEY_RX | rxr->rx_agg_prod,
3421 rxr->rx_agg_doorbell);
b81a90d3 3422 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3423 }
3424 }
3425err_out:
3426 return rc;
3427}
3428
3429static int hwrm_ring_free_send_msg(struct bnxt *bp,
3430 struct bnxt_ring_struct *ring,
3431 u32 ring_type, int cmpl_ring_id)
3432{
3433 int rc;
3434 struct hwrm_ring_free_input req = {0};
3435 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3436 u16 error_code;
3437
74608fc9 3438 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 3439 req.ring_type = ring_type;
3440 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3441
3442 mutex_lock(&bp->hwrm_cmd_lock);
3443 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3444 error_code = le16_to_cpu(resp->error_code);
3445 mutex_unlock(&bp->hwrm_cmd_lock);
3446
3447 if (rc || error_code) {
3448 switch (ring_type) {
3449 case RING_FREE_REQ_RING_TYPE_CMPL:
3450 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3451 rc);
3452 return rc;
3453 case RING_FREE_REQ_RING_TYPE_RX:
3454 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3455 rc);
3456 return rc;
3457 case RING_FREE_REQ_RING_TYPE_TX:
3458 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3459 rc);
3460 return rc;
3461 default:
3462 netdev_err(bp->dev, "Invalid ring\n");
3463 return -1;
3464 }
3465 }
3466 return 0;
3467}
3468
edd0c2cc 3469static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 3470{
edd0c2cc 3471 int i;
c0c050c5
MC		 3472
3473 if (!bp->bnapi)
edd0c2cc 3474 return;
c0c050c5 3475
edd0c2cc 3476 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3477 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3478 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3479 u32 grp_idx = txr->bnapi->index;
3480 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3481
3482 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3483 hwrm_ring_free_send_msg(bp, ring,
3484 RING_FREE_REQ_RING_TYPE_TX,
3485 close_path ? cmpl_ring_id :
3486 INVALID_HW_RING_ID);
3487 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 3488 }
3489 }
3490
edd0c2cc 3491 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3492 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3493 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3
MC		 3494 u32 grp_idx = rxr->bnapi->index;
3495 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3496
3497 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3498 hwrm_ring_free_send_msg(bp, ring,
3499 RING_FREE_REQ_RING_TYPE_RX,
3500 close_path ? cmpl_ring_id :
3501 INVALID_HW_RING_ID);
3502 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 3503 bp->grp_info[grp_idx].rx_fw_ring_id =
3504 INVALID_HW_RING_ID;
c0c050c5
MC		 3505 }
3506 }
3507
edd0c2cc 3508 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3509 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3510 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3511 u32 grp_idx = rxr->bnapi->index;
3512 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3513
3514 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3515 hwrm_ring_free_send_msg(bp, ring,
3516 RING_FREE_REQ_RING_TYPE_RX,
3517 close_path ? cmpl_ring_id :
3518 INVALID_HW_RING_ID);
3519 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 3520 bp->grp_info[grp_idx].agg_fw_ring_id =
3521 INVALID_HW_RING_ID;
c0c050c5
MC		 3522 }
3523 }
3524
edd0c2cc
MC		 3525 for (i = 0; i < bp->cp_nr_rings; i++) {
3526 struct bnxt_napi *bnapi = bp->bnapi[i];
3527 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3528 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3529
3530 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3531 hwrm_ring_free_send_msg(bp, ring,
3532 RING_FREE_REQ_RING_TYPE_CMPL,
3533 INVALID_HW_RING_ID);
3534 ring->fw_ring_id = INVALID_HW_RING_ID;
3535 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 3536 }
3537 }
c0c050c5
MC		 3538}
3539
bb053f52
MC		 3540static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3541 u32 buf_tmrs, u16 flags,
3542 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3543{
3544 req->flags = cpu_to_le16(flags);
3545 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3546 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3547 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3548 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3549 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3550 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3551 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3552 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3553}
3554
c0c050c5
MC		 3555int bnxt_hwrm_set_coal(struct bnxt *bp)
3556{
3557 int i, rc = 0;
dfc9c94a
MC		 3558 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3559 req_tx = {0}, *req;
c0c050c5
MC		 3560 u16 max_buf, max_buf_irq;
3561 u16 buf_tmr, buf_tmr_irq;
3562 u32 flags;
3563
dfc9c94a
MC		 3564 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3565 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3566 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3567 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
c0c050c5 3568
dfb5b894
MC		 3569 /* Each rx completion (2 records) should be DMAed immediately.
3570 * DMA 1/4 of the completion buffers at a time.
3571 */
3572 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
c0c050c5
MC		 3573 /* max_buf must not be zero */
3574 max_buf = clamp_t(u16, max_buf, 1, 63);
dfb5b894
MC		 3575 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
3576 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
3577 /* buf timer set to 1/4 of interrupt timer */
3578 buf_tmr = max_t(u16, buf_tmr / 4, 1);
3579 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
3580 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
c0c050c5
MC		 3581
3582 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3583
3584 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3585 * if coal_ticks is less than 25 us.
3586 */
dfb5b894 3587 if (bp->rx_coal_ticks < 25)
c0c050c5
MC		 3588 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3589
bb053f52 3590 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
dfc9c94a
MC		 3591 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
3592
3593 /* max_buf must not be zero */
3594 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
3595 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
3596 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
3597 /* buf timer set to 1/4 of interrupt timer */
3598 buf_tmr = max_t(u16, buf_tmr / 4, 1);
3599 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
3600 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3601
3602 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3603 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3604 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
c0c050c5
MC		 3605
3606 mutex_lock(&bp->hwrm_cmd_lock);
3607 for (i = 0; i < bp->cp_nr_rings; i++) {
dfc9c94a 3608 struct bnxt_napi *bnapi = bp->bnapi[i];
c0c050c5 3609
dfc9c94a
MC		 3610 req = &req_rx;
3611 if (!bnapi->rx_ring)
3612 req = &req_tx;
3613 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3614
3615 rc = _hwrm_send_message(bp, req, sizeof(*req),
c0c050c5
MC		 3616 HWRM_CMD_TIMEOUT);
3617 if (rc)
3618 break;
3619 }
3620 mutex_unlock(&bp->hwrm_cmd_lock);
3621 return rc;
3622}
3623
3624static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3625{
3626 int rc = 0, i;
3627 struct hwrm_stat_ctx_free_input req = {0};
3628
3629 if (!bp->bnapi)
3630 return 0;
3631
3632 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3633
3634 mutex_lock(&bp->hwrm_cmd_lock);
3635 for (i = 0; i < bp->cp_nr_rings; i++) {
3636 struct bnxt_napi *bnapi = bp->bnapi[i];
3637 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3638
3639 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3640 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3641
3642 rc = _hwrm_send_message(bp, &req, sizeof(req),
3643 HWRM_CMD_TIMEOUT);
3644 if (rc)
3645 break;
3646
3647 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3648 }
3649 }
3650 mutex_unlock(&bp->hwrm_cmd_lock);
3651 return rc;
3652}
3653
3654static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3655{
3656 int rc = 0, i;
3657 struct hwrm_stat_ctx_alloc_input req = {0};
3658 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3659
3660 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3661
3662 req.update_period_ms = cpu_to_le32(1000);
3663
3664 mutex_lock(&bp->hwrm_cmd_lock);
3665 for (i = 0; i < bp->cp_nr_rings; i++) {
3666 struct bnxt_napi *bnapi = bp->bnapi[i];
3667 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3668
3669 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3670
3671 rc = _hwrm_send_message(bp, &req, sizeof(req),
3672 HWRM_CMD_TIMEOUT);
3673 if (rc)
3674 break;
3675
3676 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3677
3678 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3679 }
3680 mutex_unlock(&bp->hwrm_cmd_lock);
3681 return 0;
3682}
3683
4a21b49b 3684int bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 3685{
3686 int rc = 0;
3687 struct hwrm_func_qcaps_input req = {0};
3688 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3689
3690 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3691 req.fid = cpu_to_le16(0xffff);
3692
3693 mutex_lock(&bp->hwrm_cmd_lock);
3694 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3695 if (rc)
3696 goto hwrm_func_qcaps_exit;
3697
3698 if (BNXT_PF(bp)) {
3699 struct bnxt_pf_info *pf = &bp->pf;
3700
3701 pf->fw_fid = le16_to_cpu(resp->fid);
3702 pf->port_id = le16_to_cpu(resp->port_id);
3703 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
bdd4347b 3704 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
c0c050c5
MC		 3705 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3706 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3707 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
c0c050c5 3708 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 3709 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3710 if (!pf->max_hw_ring_grps)
3711 pf->max_hw_ring_grps = pf->max_tx_rings;
c0c050c5
MC		 3712 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3713 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3714 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3715 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3716 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3717 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3718 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3719 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3720 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3721 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3722 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3723 } else {
379a80a1 3724#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 3725 struct bnxt_vf_info *vf = &bp->vf;
3726
3727 vf->fw_fid = le16_to_cpu(resp->fid);
3728 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
bdd4347b
JH		 3729 if (is_valid_ether_addr(vf->mac_addr))
3730 /* overwrite netdev dev_adr with admin VF MAC */
3731 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3732 else
3733 random_ether_addr(bp->dev->dev_addr);
c0c050c5
MC		 3734
3735 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3736 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3737 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3738 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 3739 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3740 if (!vf->max_hw_ring_grps)
3741 vf->max_hw_ring_grps = vf->max_tx_rings;
c0c050c5
MC		 3742 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3743 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3744 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
379a80a1 3745#endif
c0c050c5
MC		 3746 }
3747
3748 bp->tx_push_thresh = 0;
3749 if (resp->flags &
3750 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3751 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3752
3753hwrm_func_qcaps_exit:
3754 mutex_unlock(&bp->hwrm_cmd_lock);
3755 return rc;
3756}
3757
3758static int bnxt_hwrm_func_reset(struct bnxt *bp)
3759{
3760 struct hwrm_func_reset_input req = {0};
3761
3762 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3763 req.enables = 0;
3764
3765 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3766}
3767
3768static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3769{
3770 int rc = 0;
3771 struct hwrm_queue_qportcfg_input req = {0};
3772 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3773 u8 i, *qptr;
3774
3775 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3776
3777 mutex_lock(&bp->hwrm_cmd_lock);
3778 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3779 if (rc)
3780 goto qportcfg_exit;
3781
3782 if (!resp->max_configurable_queues) {
3783 rc = -EINVAL;
3784 goto qportcfg_exit;
3785 }
3786 bp->max_tc = resp->max_configurable_queues;
3787 if (bp->max_tc > BNXT_MAX_QUEUE)
3788 bp->max_tc = BNXT_MAX_QUEUE;
3789
3790 qptr = &resp->queue_id0;
3791 for (i = 0; i < bp->max_tc; i++) {
3792 bp->q_info[i].queue_id = *qptr++;
3793 bp->q_info[i].queue_profile = *qptr++;
3794 }
3795
3796qportcfg_exit:
3797 mutex_unlock(&bp->hwrm_cmd_lock);
3798 return rc;
3799}
3800
3801static int bnxt_hwrm_ver_get(struct bnxt *bp)
3802{
3803 int rc;
3804 struct hwrm_ver_get_input req = {0};
3805 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3806
3807 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3808 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3809 req.hwrm_intf_min = HWRM_VERSION_MINOR;
3810 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3811 mutex_lock(&bp->hwrm_cmd_lock);
3812 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3813 if (rc)
3814 goto hwrm_ver_get_exit;
3815
3816 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3817
c193554e
MC		 3818 if (resp->hwrm_intf_maj < 1) {
3819 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
c0c050c5 3820 resp->hwrm_intf_maj, resp->hwrm_intf_min,
c193554e
MC		 3821 resp->hwrm_intf_upd);
3822 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5 3823 }
3ebf6f0a 3824 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
c0c050c5
MC		 3825 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3826 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3827
ff4fe81d
MC		 3828 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
3829 if (!bp->hwrm_cmd_timeout)
3830 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
3831
c0c050c5
MC		 3832hwrm_ver_get_exit:
3833 mutex_unlock(&bp->hwrm_cmd_lock);
3834 return rc;
3835}
3836
3837static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3838{
3839 if (bp->vxlan_port_cnt) {
3840 bnxt_hwrm_tunnel_dst_port_free(
3841 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3842 }
3843 bp->vxlan_port_cnt = 0;
3844 if (bp->nge_port_cnt) {
3845 bnxt_hwrm_tunnel_dst_port_free(
3846 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3847 }
3848 bp->nge_port_cnt = 0;
3849}
3850
3851static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3852{
3853 int rc, i;
3854 u32 tpa_flags = 0;
3855
3856 if (set_tpa)
3857 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3858 for (i = 0; i < bp->nr_vnics; i++) {
3859 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3860 if (rc) {
3861 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3862 rc, i);
3863 return rc;
3864 }
3865 }
3866 return 0;
3867}
3868
3869static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3870{
3871 int i;
3872
3873 for (i = 0; i < bp->nr_vnics; i++)
3874 bnxt_hwrm_vnic_set_rss(bp, i, false);
3875}
3876
3877static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3878 bool irq_re_init)
3879{
3880 if (bp->vnic_info) {
3881 bnxt_hwrm_clear_vnic_filter(bp);
3882 /* clear all RSS setting before free vnic ctx */
3883 bnxt_hwrm_clear_vnic_rss(bp);
3884 bnxt_hwrm_vnic_ctx_free(bp);
3885 /* before free the vnic, undo the vnic tpa settings */
3886 if (bp->flags & BNXT_FLAG_TPA)
3887 bnxt_set_tpa(bp, false);
3888 bnxt_hwrm_vnic_free(bp);
3889 }
3890 bnxt_hwrm_ring_free(bp, close_path);
3891 bnxt_hwrm_ring_grp_free(bp);
3892 if (irq_re_init) {
3893 bnxt_hwrm_stat_ctx_free(bp);
3894 bnxt_hwrm_free_tunnel_ports(bp);
3895 }
3896}
3897
3898static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3899{
3900 int rc;
3901
3902 /* allocate context for vnic */
3903 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3904 if (rc) {
3905 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3906 vnic_id, rc);
3907 goto vnic_setup_err;
3908 }
3909 bp->rsscos_nr_ctxs++;
3910
3911 /* configure default vnic, ring grp */
3912 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3913 if (rc) {
3914 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3915 vnic_id, rc);
3916 goto vnic_setup_err;
3917 }
3918
3919 /* Enable RSS hashing on vnic */
3920 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3921 if (rc) {
3922 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3923 vnic_id, rc);
3924 goto vnic_setup_err;
3925 }
3926
3927 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3928 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
3929 if (rc) {
3930 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
3931 vnic_id, rc);
3932 }
3933 }
3934
3935vnic_setup_err:
3936 return rc;
3937}
3938
3939static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
3940{
3941#ifdef CONFIG_RFS_ACCEL
3942 int i, rc = 0;
3943
3944 for (i = 0; i < bp->rx_nr_rings; i++) {
3945 u16 vnic_id = i + 1;
3946 u16 ring_id = i;
3947
3948 if (vnic_id >= bp->nr_vnics)
3949 break;
3950
3951 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
b81a90d3 3952 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 3953 if (rc) {
3954 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3955 vnic_id, rc);
3956 break;
3957 }
3958 rc = bnxt_setup_vnic(bp, vnic_id);
3959 if (rc)
3960 break;
3961 }
3962 return rc;
3963#else
3964 return 0;
3965#endif
3966}
3967
b664f008
MC		 3968static int bnxt_cfg_rx_mode(struct bnxt *);
3969
c0c050c5
MC		 3970static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
3971{
3972 int rc = 0;
3973
3974 if (irq_re_init) {
3975 rc = bnxt_hwrm_stat_ctx_alloc(bp);
3976 if (rc) {
3977 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
3978 rc);
3979 goto err_out;
3980 }
3981 }
3982
3983 rc = bnxt_hwrm_ring_alloc(bp);
3984 if (rc) {
3985 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
3986 goto err_out;
3987 }
3988
3989 rc = bnxt_hwrm_ring_grp_alloc(bp);
3990 if (rc) {
3991 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
3992 goto err_out;
3993 }
3994
3995 /* default vnic 0 */
3996 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
3997 if (rc) {
3998 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
3999 goto err_out;
4000 }
4001
4002 rc = bnxt_setup_vnic(bp, 0);
4003 if (rc)
4004 goto err_out;
4005
4006 if (bp->flags & BNXT_FLAG_RFS) {
4007 rc = bnxt_alloc_rfs_vnics(bp);
4008 if (rc)
4009 goto err_out;
4010 }
4011
4012 if (bp->flags & BNXT_FLAG_TPA) {
4013 rc = bnxt_set_tpa(bp, true);
4014 if (rc)
4015 goto err_out;
4016 }
4017
4018 if (BNXT_VF(bp))
4019 bnxt_update_vf_mac(bp);
4020
4021 /* Filter for default vnic 0 */
4022 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4023 if (rc) {
4024 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4025 goto err_out;
4026 }
4027 bp->vnic_info[0].uc_filter_count = 1;
4028
c193554e 4029 bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5
MC		 4030
4031 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4032 bp->vnic_info[0].rx_mask |=
4033 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4034
b664f008
MC		 4035 rc = bnxt_cfg_rx_mode(bp);
4036 if (rc)
c0c050c5 4037 goto err_out;
c0c050c5
MC		 4038
4039 rc = bnxt_hwrm_set_coal(bp);
4040 if (rc)
4041 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4042 rc);
4043
4044 return 0;
4045
4046err_out:
4047 bnxt_hwrm_resource_free(bp, 0, true);
4048
4049 return rc;
4050}
4051
4052static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4053{
4054 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4055 return 0;
4056}
4057
4058static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4059{
4060 bnxt_init_rx_rings(bp);
4061 bnxt_init_tx_rings(bp);
4062 bnxt_init_ring_grps(bp, irq_re_init);
4063 bnxt_init_vnics(bp);
4064
4065 return bnxt_init_chip(bp, irq_re_init);
4066}
4067
4068static void bnxt_disable_int(struct bnxt *bp)
4069{
4070 int i;
4071
4072 if (!bp->bnapi)
4073 return;
4074
4075 for (i = 0; i < bp->cp_nr_rings; i++) {
4076 struct bnxt_napi *bnapi = bp->bnapi[i];
4077 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4078
4079 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4080 }
4081}
4082
4083static void bnxt_enable_int(struct bnxt *bp)
4084{
4085 int i;
4086
4087 atomic_set(&bp->intr_sem, 0);
4088 for (i = 0; i < bp->cp_nr_rings; i++) {
4089 struct bnxt_napi *bnapi = bp->bnapi[i];
4090 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4091
4092 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4093 }
4094}
4095
4096static int bnxt_set_real_num_queues(struct bnxt *bp)
4097{
4098 int rc;
4099 struct net_device *dev = bp->dev;
4100
4101 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4102 if (rc)
4103 return rc;
4104
4105 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4106 if (rc)
4107 return rc;
4108
4109#ifdef CONFIG_RFS_ACCEL
45019a18 4110 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 4111 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 4112#endif
4113
4114 return rc;
4115}
4116
6e6c5a57
MC		 4117static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4118 bool shared)
4119{
4120 int _rx = *rx, _tx = *tx;
4121
4122 if (shared) {
4123 *rx = min_t(int, _rx, max);
4124 *tx = min_t(int, _tx, max);
4125 } else {
4126 if (max < 2)
4127 return -ENOMEM;
4128
4129 while (_rx + _tx > max) {
4130 if (_rx > _tx && _rx > 1)
4131 _rx--;
4132 else if (_tx > 1)
4133 _tx--;
4134 }
4135 *rx = _rx;
4136 *tx = _tx;
4137 }
4138 return 0;
4139}
4140
c0c050c5
MC		 4141static int bnxt_setup_msix(struct bnxt *bp)
4142{
4143 struct msix_entry *msix_ent;
4144 struct net_device *dev = bp->dev;
01657bcd 4145 int i, total_vecs, rc = 0, min = 1;
c0c050c5
MC		 4146 const int len = sizeof(bp->irq_tbl[0].name);
4147
4148 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4149 total_vecs = bp->cp_nr_rings;
4150
4151 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4152 if (!msix_ent)
4153 return -ENOMEM;
4154
4155 for (i = 0; i < total_vecs; i++) {
4156 msix_ent[i].entry = i;
4157 msix_ent[i].vector = 0;
4158 }
4159
01657bcd
MC		 4160 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4161 min = 2;
4162
4163 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
c0c050c5
MC		 4164 if (total_vecs < 0) {
4165 rc = -ENODEV;
4166 goto msix_setup_exit;
4167 }
4168
4169 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4170 if (bp->irq_tbl) {
4171 int tcs;
4172
4173 /* Trim rings based upon num of vectors allocated */
6e6c5a57 4174 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
01657bcd 4175 total_vecs, min == 1);
6e6c5a57
MC		 4176 if (rc)
4177 goto msix_setup_exit;
4178
c0c050c5
MC		 4179 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4180 tcs = netdev_get_num_tc(dev);
4181 if (tcs > 1) {
4182 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4183 if (bp->tx_nr_rings_per_tc == 0) {
4184 netdev_reset_tc(dev);
4185 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4186 } else {
4187 int i, off, count;
4188
4189 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4190 for (i = 0; i < tcs; i++) {
4191 count = bp->tx_nr_rings_per_tc;
4192 off = i * count;
4193 netdev_set_tc_queue(dev, i, count, off);
4194 }
4195 }
4196 }
01657bcd 4197 bp->cp_nr_rings = total_vecs;
c0c050c5
MC		 4198
4199 for (i = 0; i < bp->cp_nr_rings; i++) {
01657bcd
MC		 4200 char *attr;
4201
c0c050c5 4202 bp->irq_tbl[i].vector = msix_ent[i].vector;
01657bcd
MC		 4203 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4204 attr = "TxRx";
4205 else if (i < bp->rx_nr_rings)
4206 attr = "rx";
4207 else
4208 attr = "tx";
4209
c0c050c5 4210 snprintf(bp->irq_tbl[i].name, len,
01657bcd 4211 "%s-%s-%d", dev->name, attr, i);
c0c050c5
MC		 4212 bp->irq_tbl[i].handler = bnxt_msix;
4213 }
4214 rc = bnxt_set_real_num_queues(bp);
4215 if (rc)
4216 goto msix_setup_exit;
4217 } else {
4218 rc = -ENOMEM;
4219 goto msix_setup_exit;
4220 }
4221 bp->flags |= BNXT_FLAG_USING_MSIX;
4222 kfree(msix_ent);
4223 return 0;
4224
4225msix_setup_exit:
4226 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4227 pci_disable_msix(bp->pdev);
4228 kfree(msix_ent);
4229 return rc;
4230}
4231
4232static int bnxt_setup_inta(struct bnxt *bp)
4233{
4234 int rc;
4235 const int len = sizeof(bp->irq_tbl[0].name);
4236
4237 if (netdev_get_num_tc(bp->dev))
4238 netdev_reset_tc(bp->dev);
4239
4240 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4241 if (!bp->irq_tbl) {
4242 rc = -ENOMEM;
4243 return rc;
4244 }
4245 bp->rx_nr_rings = 1;
4246 bp->tx_nr_rings = 1;
4247 bp->cp_nr_rings = 1;
4248 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
01657bcd 4249 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5
MC		 4250 bp->irq_tbl[0].vector = bp->pdev->irq;
4251 snprintf(bp->irq_tbl[0].name, len,
4252 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4253 bp->irq_tbl[0].handler = bnxt_inta;
4254 rc = bnxt_set_real_num_queues(bp);
4255 return rc;
4256}
4257
4258static int bnxt_setup_int_mode(struct bnxt *bp)
4259{
4260 int rc = 0;
4261
4262 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4263 rc = bnxt_setup_msix(bp);
4264
4265 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4266 /* fallback to INTA */
4267 rc = bnxt_setup_inta(bp);
4268 }
4269 return rc;
4270}
4271
4272static void bnxt_free_irq(struct bnxt *bp)
4273{
4274 struct bnxt_irq *irq;
4275 int i;
4276
4277#ifdef CONFIG_RFS_ACCEL
4278 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4279 bp->dev->rx_cpu_rmap = NULL;
4280#endif
4281 if (!bp->irq_tbl)
4282 return;
4283
4284 for (i = 0; i < bp->cp_nr_rings; i++) {
4285 irq = &bp->irq_tbl[i];
4286 if (irq->requested)
4287 free_irq(irq->vector, bp->bnapi[i]);
4288 irq->requested = 0;
4289 }
4290 if (bp->flags & BNXT_FLAG_USING_MSIX)
4291 pci_disable_msix(bp->pdev);
4292 kfree(bp->irq_tbl);
4293 bp->irq_tbl = NULL;
4294}
4295
4296static int bnxt_request_irq(struct bnxt *bp)
4297{
b81a90d3 4298 int i, j, rc = 0;
c0c050c5
MC		 4299 unsigned long flags = 0;
4300#ifdef CONFIG_RFS_ACCEL
4301 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4302#endif
4303
4304 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4305 flags = IRQF_SHARED;
4306
b81a90d3 4307 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
c0c050c5
MC		 4308 struct bnxt_irq *irq = &bp->irq_tbl[i];
4309#ifdef CONFIG_RFS_ACCEL
b81a90d3 4310 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 4311 rc = irq_cpu_rmap_add(rmap, irq->vector);
4312 if (rc)
4313 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 4314 j);
4315 j++;
c0c050c5
MC		 4316 }
4317#endif
4318 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4319 bp->bnapi[i]);
4320 if (rc)
4321 break;
4322
4323 irq->requested = 1;
4324 }
4325 return rc;
4326}
4327
4328static void bnxt_del_napi(struct bnxt *bp)
4329{
4330 int i;
4331
4332 if (!bp->bnapi)
4333 return;
4334
4335 for (i = 0; i < bp->cp_nr_rings; i++) {
4336 struct bnxt_napi *bnapi = bp->bnapi[i];
4337
4338 napi_hash_del(&bnapi->napi);
4339 netif_napi_del(&bnapi->napi);
4340 }
4341}
4342
4343static void bnxt_init_napi(struct bnxt *bp)
4344{
4345 int i;
4346 struct bnxt_napi *bnapi;
4347
4348 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4349 for (i = 0; i < bp->cp_nr_rings; i++) {
4350 bnapi = bp->bnapi[i];
4351 netif_napi_add(bp->dev, &bnapi->napi,
4352 bnxt_poll, 64);
c0c050c5
MC		 4353 }
4354 } else {
4355 bnapi = bp->bnapi[0];
4356 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 4357 }
4358}
4359
4360static void bnxt_disable_napi(struct bnxt *bp)
4361{
4362 int i;
4363
4364 if (!bp->bnapi)
4365 return;
4366
4367 for (i = 0; i < bp->cp_nr_rings; i++) {
4368 napi_disable(&bp->bnapi[i]->napi);
4369 bnxt_disable_poll(bp->bnapi[i]);
4370 }
4371}
4372
4373static void bnxt_enable_napi(struct bnxt *bp)
4374{
4375 int i;
4376
4377 for (i = 0; i < bp->cp_nr_rings; i++) {
4378 bnxt_enable_poll(bp->bnapi[i]);
4379 napi_enable(&bp->bnapi[i]->napi);
4380 }
4381}
4382
4383static void bnxt_tx_disable(struct bnxt *bp)
4384{
4385 int i;
c0c050c5
MC		 4386 struct bnxt_tx_ring_info *txr;
4387 struct netdev_queue *txq;
4388
b6ab4b01 4389 if (bp->tx_ring) {
c0c050c5 4390 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4391 txr = &bp->tx_ring[i];
c0c050c5
MC		 4392 txq = netdev_get_tx_queue(bp->dev, i);
4393 __netif_tx_lock(txq, smp_processor_id());
4394 txr->dev_state = BNXT_DEV_STATE_CLOSING;
4395 __netif_tx_unlock(txq);
4396 }
4397 }
4398 /* Stop all TX queues */
4399 netif_tx_disable(bp->dev);
4400 netif_carrier_off(bp->dev);
4401}
4402
4403static void bnxt_tx_enable(struct bnxt *bp)
4404{
4405 int i;
c0c050c5
MC		 4406 struct bnxt_tx_ring_info *txr;
4407 struct netdev_queue *txq;
4408
4409 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4410 txr = &bp->tx_ring[i];
c0c050c5
MC		 4411 txq = netdev_get_tx_queue(bp->dev, i);
4412 txr->dev_state = 0;
4413 }
4414 netif_tx_wake_all_queues(bp->dev);
4415 if (bp->link_info.link_up)
4416 netif_carrier_on(bp->dev);
4417}
4418
4419static void bnxt_report_link(struct bnxt *bp)
4420{
4421 if (bp->link_info.link_up) {
4422 const char *duplex;
4423 const char *flow_ctrl;
4424 u16 speed;
4425
4426 netif_carrier_on(bp->dev);
4427 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4428 duplex = "full";
4429 else
4430 duplex = "half";
4431 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4432 flow_ctrl = "ON - receive & transmit";
4433 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4434 flow_ctrl = "ON - transmit";
4435 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4436 flow_ctrl = "ON - receive";
4437 else
4438 flow_ctrl = "none";
4439 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4440 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4441 speed, duplex, flow_ctrl);
4442 } else {
4443 netif_carrier_off(bp->dev);
4444 netdev_err(bp->dev, "NIC Link is Down\n");
4445 }
4446}
4447
4448static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4449{
4450 int rc = 0;
4451 struct bnxt_link_info *link_info = &bp->link_info;
4452 struct hwrm_port_phy_qcfg_input req = {0};
4453 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4454 u8 link_up = link_info->link_up;
4455
4456 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4457
4458 mutex_lock(&bp->hwrm_cmd_lock);
4459 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4460 if (rc) {
4461 mutex_unlock(&bp->hwrm_cmd_lock);
4462 return rc;
4463 }
4464
4465 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4466 link_info->phy_link_status = resp->link;
4467 link_info->duplex = resp->duplex;
4468 link_info->pause = resp->pause;
4469 link_info->auto_mode = resp->auto_mode;
4470 link_info->auto_pause_setting = resp->auto_pause;
4471 link_info->force_pause_setting = resp->force_pause;
c193554e 4472 link_info->duplex_setting = resp->duplex;
c0c050c5
MC		 4473 if (link_info->phy_link_status == BNXT_LINK_LINK)
4474 link_info->link_speed = le16_to_cpu(resp->link_speed);
4475 else
4476 link_info->link_speed = 0;
4477 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4478 link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4479 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4480 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4481 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4482 link_info->phy_ver[0] = resp->phy_maj;
4483 link_info->phy_ver[1] = resp->phy_min;
4484 link_info->phy_ver[2] = resp->phy_bld;
4485 link_info->media_type = resp->media_type;
4486 link_info->transceiver = resp->transceiver_type;
4487 link_info->phy_addr = resp->phy_addr;
4488
4489 /* TODO: need to add more logic to report VF link */
4490 if (chng_link_state) {
4491 if (link_info->phy_link_status == BNXT_LINK_LINK)
4492 link_info->link_up = 1;
4493 else
4494 link_info->link_up = 0;
4495 if (link_up != link_info->link_up)
4496 bnxt_report_link(bp);
4497 } else {
4498 /* alwasy link down if not require to update link state */
4499 link_info->link_up = 0;
4500 }
4501 mutex_unlock(&bp->hwrm_cmd_lock);
4502 return 0;
4503}
4504
4505static void
4506bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4507{
4508 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4509 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4510 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4511 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4512 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4513 req->enables |=
4514 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4515 } else {
4516 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4517 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4518 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4519 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4520 req->enables |=
4521 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4522 }
4523}
4524
4525static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4526 struct hwrm_port_phy_cfg_input *req)
4527{
4528 u8 autoneg = bp->link_info.autoneg;
4529 u16 fw_link_speed = bp->link_info.req_link_speed;
4530 u32 advertising = bp->link_info.advertising;
4531
4532 if (autoneg & BNXT_AUTONEG_SPEED) {
4533 req->auto_mode |=
4534 PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4535
4536 req->enables |= cpu_to_le32(
4537 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4538 req->auto_link_speed_mask = cpu_to_le16(advertising);
4539
4540 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4541 req->flags |=
4542 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4543 } else {
4544 req->force_link_speed = cpu_to_le16(fw_link_speed);
4545 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4546 }
4547
4548 /* currently don't support half duplex */
4549 req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4550 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4551 /* tell chimp that the setting takes effect immediately */
4552 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4553}
4554
4555int bnxt_hwrm_set_pause(struct bnxt *bp)
4556{
4557 struct hwrm_port_phy_cfg_input req = {0};
4558 int rc;
4559
4560 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4561 bnxt_hwrm_set_pause_common(bp, &req);
4562
4563 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4564 bp->link_info.force_link_chng)
4565 bnxt_hwrm_set_link_common(bp, &req);
4566
4567 mutex_lock(&bp->hwrm_cmd_lock);
4568 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4569 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4570 /* since changing of pause setting doesn't trigger any link
4571 * change event, the driver needs to update the current pause
4572 * result upon successfully return of the phy_cfg command
4573 */
4574 bp->link_info.pause =
4575 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4576 bp->link_info.auto_pause_setting = 0;
4577 if (!bp->link_info.force_link_chng)
4578 bnxt_report_link(bp);
4579 }
4580 bp->link_info.force_link_chng = false;
4581 mutex_unlock(&bp->hwrm_cmd_lock);
4582 return rc;
4583}
4584
4585int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4586{
4587 struct hwrm_port_phy_cfg_input req = {0};
4588
4589 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4590 if (set_pause)
4591 bnxt_hwrm_set_pause_common(bp, &req);
4592
4593 bnxt_hwrm_set_link_common(bp, &req);
4594 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4595}
4596
4597static int bnxt_update_phy_setting(struct bnxt *bp)
4598{
4599 int rc;
4600 bool update_link = false;
4601 bool update_pause = false;
4602 struct bnxt_link_info *link_info = &bp->link_info;
4603
4604 rc = bnxt_update_link(bp, true);
4605 if (rc) {
4606 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4607 rc);
4608 return rc;
4609 }
4610 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4611 link_info->auto_pause_setting != link_info->req_flow_ctrl)
4612 update_pause = true;
4613 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4614 link_info->force_pause_setting != link_info->req_flow_ctrl)
4615 update_pause = true;
c0c050c5
MC		 4616 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4617 if (BNXT_AUTO_MODE(link_info->auto_mode))
4618 update_link = true;
4619 if (link_info->req_link_speed != link_info->force_link_speed)
4620 update_link = true;
de73018f
MC		 4621 if (link_info->req_duplex != link_info->duplex_setting)
4622 update_link = true;
c0c050c5
MC		 4623 } else {
4624 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4625 update_link = true;
4626 if (link_info->advertising != link_info->auto_link_speeds)
4627 update_link = true;
c0c050c5
MC		 4628 }
4629
4630 if (update_link)
4631 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4632 else if (update_pause)
4633 rc = bnxt_hwrm_set_pause(bp);
4634 if (rc) {
4635 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4636 rc);
4637 return rc;
4638 }
4639
4640 return rc;
4641}
4642
11809490
JH		 4643/* Common routine to pre-map certain register block to different GRC window.
4644 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4645 * in PF and 3 windows in VF that can be customized to map in different
4646 * register blocks.
4647 */
4648static void bnxt_preset_reg_win(struct bnxt *bp)
4649{
4650 if (BNXT_PF(bp)) {
4651 /* CAG registers map to GRC window #4 */
4652 writel(BNXT_CAG_REG_BASE,
4653 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4654 }
4655}
4656
c0c050c5
MC		 4657static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4658{
4659 int rc = 0;
4660
11809490 4661 bnxt_preset_reg_win(bp);
c0c050c5
MC		 4662 netif_carrier_off(bp->dev);
4663 if (irq_re_init) {
4664 rc = bnxt_setup_int_mode(bp);
4665 if (rc) {
4666 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4667 rc);
4668 return rc;
4669 }
4670 }
4671 if ((bp->flags & BNXT_FLAG_RFS) &&
4672 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4673 /* disable RFS if falling back to INTA */
4674 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4675 bp->flags &= ~BNXT_FLAG_RFS;
4676 }
4677
4678 rc = bnxt_alloc_mem(bp, irq_re_init);
4679 if (rc) {
4680 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4681 goto open_err_free_mem;
4682 }
4683
4684 if (irq_re_init) {
4685 bnxt_init_napi(bp);
4686 rc = bnxt_request_irq(bp);
4687 if (rc) {
4688 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4689 goto open_err;
4690 }
4691 }
4692
4693 bnxt_enable_napi(bp);
4694
4695 rc = bnxt_init_nic(bp, irq_re_init);
4696 if (rc) {
4697 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4698 goto open_err;
4699 }
4700
4701 if (link_re_init) {
4702 rc = bnxt_update_phy_setting(bp);
4703 if (rc)
ba41d46f 4704 netdev_warn(bp->dev, "failed to update phy settings\n");
c0c050c5
MC		 4705 }
4706
4707 if (irq_re_init) {
4708#if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4709 vxlan_get_rx_port(bp->dev);
4710#endif
4711 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4712 bp, htons(0x17c1),
4713 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4714 bp->nge_port_cnt = 1;
4715 }
4716
caefe526 4717 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 4718 bnxt_enable_int(bp);
4719 /* Enable TX queues */
4720 bnxt_tx_enable(bp);
4721 mod_timer(&bp->timer, jiffies + bp->current_interval);
035a1539 4722 bnxt_update_link(bp, true);
c0c050c5
MC		 4723
4724 return 0;
4725
4726open_err:
4727 bnxt_disable_napi(bp);
4728 bnxt_del_napi(bp);
4729
4730open_err_free_mem:
4731 bnxt_free_skbs(bp);
4732 bnxt_free_irq(bp);
4733 bnxt_free_mem(bp, true);
4734 return rc;
4735}
4736
4737/* rtnl_lock held */
4738int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4739{
4740 int rc = 0;
4741
4742 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4743 if (rc) {
4744 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4745 dev_close(bp->dev);
4746 }
4747 return rc;
4748}
4749
4750static int bnxt_open(struct net_device *dev)
4751{
4752 struct bnxt *bp = netdev_priv(dev);
4753 int rc = 0;
4754
4755 rc = bnxt_hwrm_func_reset(bp);
4756 if (rc) {
4757 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4758 rc);
4759 rc = -1;
4760 return rc;
4761 }
4762 return __bnxt_open_nic(bp, true, true);
4763}
4764
4765static void bnxt_disable_int_sync(struct bnxt *bp)
4766{
4767 int i;
4768
4769 atomic_inc(&bp->intr_sem);
4770 if (!netif_running(bp->dev))
4771 return;
4772
4773 bnxt_disable_int(bp);
4774 for (i = 0; i < bp->cp_nr_rings; i++)
4775 synchronize_irq(bp->irq_tbl[i].vector);
4776}
4777
4778int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4779{
4780 int rc = 0;
4781
4782#ifdef CONFIG_BNXT_SRIOV
4783 if (bp->sriov_cfg) {
4784 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4785 !bp->sriov_cfg,
4786 BNXT_SRIOV_CFG_WAIT_TMO);
4787 if (rc)
4788 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4789 }
4790#endif
4791 /* Change device state to avoid TX queue wake up's */
4792 bnxt_tx_disable(bp);
4793
caefe526 4794 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec
MC		 4795 smp_mb__after_atomic();
4796 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
4797 msleep(20);
c0c050c5
MC		 4798
4799 /* Flush rings before disabling interrupts */
4800 bnxt_shutdown_nic(bp, irq_re_init);
4801
4802 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4803
4804 bnxt_disable_napi(bp);
4805 bnxt_disable_int_sync(bp);
4806 del_timer_sync(&bp->timer);
4807 bnxt_free_skbs(bp);
4808
4809 if (irq_re_init) {
4810 bnxt_free_irq(bp);
4811 bnxt_del_napi(bp);
4812 }
4813 bnxt_free_mem(bp, irq_re_init);
4814 return rc;
4815}
4816
4817static int bnxt_close(struct net_device *dev)
4818{
4819 struct bnxt *bp = netdev_priv(dev);
4820
4821 bnxt_close_nic(bp, true, true);
4822 return 0;
4823}
4824
4825/* rtnl_lock held */
4826static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4827{
4828 switch (cmd) {
4829 case SIOCGMIIPHY:
4830 /* fallthru */
4831 case SIOCGMIIREG: {
4832 if (!netif_running(dev))
4833 return -EAGAIN;
4834
4835 return 0;
4836 }
4837
4838 case SIOCSMIIREG:
4839 if (!netif_running(dev))
4840 return -EAGAIN;
4841
4842 return 0;
4843
4844 default:
4845 /* do nothing */
4846 break;
4847 }
4848 return -EOPNOTSUPP;
4849}
4850
4851static struct rtnl_link_stats64 *
4852bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4853{
4854 u32 i;
4855 struct bnxt *bp = netdev_priv(dev);
4856
4857 memset(stats, 0, sizeof(struct rtnl_link_stats64));
4858
4859 if (!bp->bnapi)
4860 return stats;
4861
4862 /* TODO check if we need to synchronize with bnxt_close path */
4863 for (i = 0; i < bp->cp_nr_rings; i++) {
4864 struct bnxt_napi *bnapi = bp->bnapi[i];
4865 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4866 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4867
4868 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4869 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4870 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4871
4872 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4873 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4874 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4875
4876 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4877 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4878 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4879
4880 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4881 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4882 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4883
4884 stats->rx_missed_errors +=
4885 le64_to_cpu(hw_stats->rx_discard_pkts);
4886
4887 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4888
c0c050c5
MC		 4889 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4890 }
4891
4892 return stats;
4893}
4894
4895static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4896{
4897 struct net_device *dev = bp->dev;
4898 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4899 struct netdev_hw_addr *ha;
4900 u8 *haddr;
4901 int mc_count = 0;
4902 bool update = false;
4903 int off = 0;
4904
4905 netdev_for_each_mc_addr(ha, dev) {
4906 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4907 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4908 vnic->mc_list_count = 0;
4909 return false;
4910 }
4911 haddr = ha->addr;
4912 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
4913 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
4914 update = true;
4915 }
4916 off += ETH_ALEN;
4917 mc_count++;
4918 }
4919 if (mc_count)
4920 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
4921
4922 if (mc_count != vnic->mc_list_count) {
4923 vnic->mc_list_count = mc_count;
4924 update = true;
4925 }
4926 return update;
4927}
4928
4929static bool bnxt_uc_list_updated(struct bnxt *bp)
4930{
4931 struct net_device *dev = bp->dev;
4932 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4933 struct netdev_hw_addr *ha;
4934 int off = 0;
4935
4936 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
4937 return true;
4938
4939 netdev_for_each_uc_addr(ha, dev) {
4940 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
4941 return true;
4942
4943 off += ETH_ALEN;
4944 }
4945 return false;
4946}
4947
4948static void bnxt_set_rx_mode(struct net_device *dev)
4949{
4950 struct bnxt *bp = netdev_priv(dev);
4951 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4952 u32 mask = vnic->rx_mask;
4953 bool mc_update = false;
4954 bool uc_update;
4955
4956 if (!netif_running(dev))
4957 return;
4958
4959 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
4960 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
4961 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
4962
4963 /* Only allow PF to be in promiscuous mode */
4964 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4965 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4966
4967 uc_update = bnxt_uc_list_updated(bp);
4968
4969 if (dev->flags & IFF_ALLMULTI) {
4970 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4971 vnic->mc_list_count = 0;
4972 } else {
4973 mc_update = bnxt_mc_list_updated(bp, &mask);
4974 }
4975
4976 if (mask != vnic->rx_mask || uc_update || mc_update) {
4977 vnic->rx_mask = mask;
4978
4979 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
4980 schedule_work(&bp->sp_task);
4981 }
4982}
4983
b664f008 4984static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 4985{
4986 struct net_device *dev = bp->dev;
4987 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4988 struct netdev_hw_addr *ha;
4989 int i, off = 0, rc;
4990 bool uc_update;
4991
4992 netif_addr_lock_bh(dev);
4993 uc_update = bnxt_uc_list_updated(bp);
4994 netif_addr_unlock_bh(dev);
4995
4996 if (!uc_update)
4997 goto skip_uc;
4998
4999 mutex_lock(&bp->hwrm_cmd_lock);
5000 for (i = 1; i < vnic->uc_filter_count; i++) {
5001 struct hwrm_cfa_l2_filter_free_input req = {0};
5002
5003 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5004 -1);
5005
5006 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5007
5008 rc = _hwrm_send_message(bp, &req, sizeof(req),
5009 HWRM_CMD_TIMEOUT);
5010 }
5011 mutex_unlock(&bp->hwrm_cmd_lock);
5012
5013 vnic->uc_filter_count = 1;
5014
5015 netif_addr_lock_bh(dev);
5016 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5017 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5018 } else {
5019 netdev_for_each_uc_addr(ha, dev) {
5020 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5021 off += ETH_ALEN;
5022 vnic->uc_filter_count++;
5023 }
5024 }
5025 netif_addr_unlock_bh(dev);
5026
5027 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5028 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5029 if (rc) {
5030 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5031 rc);
5032 vnic->uc_filter_count = i;
b664f008 5033 return rc;
c0c050c5
MC		 5034 }
5035 }
5036
5037skip_uc:
5038 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5039 if (rc)
5040 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5041 rc);
b664f008
MC		 5042
5043 return rc;
c0c050c5
MC		 5044}
5045
2bcfa6f6
MC		 5046static bool bnxt_rfs_capable(struct bnxt *bp)
5047{
5048#ifdef CONFIG_RFS_ACCEL
5049 struct bnxt_pf_info *pf = &bp->pf;
5050 int vnics;
5051
5052 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5053 return false;
5054
5055 vnics = 1 + bp->rx_nr_rings;
5056 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
5057 return false;
5058
5059 return true;
5060#else
5061 return false;
5062#endif
5063}
5064
c0c050c5
MC		 5065static netdev_features_t bnxt_fix_features(struct net_device *dev,
5066 netdev_features_t features)
5067{
2bcfa6f6
MC		 5068 struct bnxt *bp = netdev_priv(dev);
5069
5070 if (!bnxt_rfs_capable(bp))
5071 features &= ~NETIF_F_NTUPLE;
c0c050c5
MC		 5072 return features;
5073}
5074
5075static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5076{
5077 struct bnxt *bp = netdev_priv(dev);
5078 u32 flags = bp->flags;
5079 u32 changes;
5080 int rc = 0;
5081 bool re_init = false;
5082 bool update_tpa = false;
5083
5084 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5085 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5086 flags |= BNXT_FLAG_GRO;
5087 if (features & NETIF_F_LRO)
5088 flags |= BNXT_FLAG_LRO;
5089
5090 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5091 flags |= BNXT_FLAG_STRIP_VLAN;
5092
5093 if (features & NETIF_F_NTUPLE)
5094 flags |= BNXT_FLAG_RFS;
5095
5096 changes = flags ^ bp->flags;
5097 if (changes & BNXT_FLAG_TPA) {
5098 update_tpa = true;
5099 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5100 (flags & BNXT_FLAG_TPA) == 0)
5101 re_init = true;
5102 }
5103
5104 if (changes & ~BNXT_FLAG_TPA)
5105 re_init = true;
5106
5107 if (flags != bp->flags) {
5108 u32 old_flags = bp->flags;
5109
5110 bp->flags = flags;
5111
2bcfa6f6 5112 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 5113 if (update_tpa)
5114 bnxt_set_ring_params(bp);
5115 return rc;
5116 }
5117
5118 if (re_init) {
5119 bnxt_close_nic(bp, false, false);
5120 if (update_tpa)
5121 bnxt_set_ring_params(bp);
5122
5123 return bnxt_open_nic(bp, false, false);
5124 }
5125 if (update_tpa) {
5126 rc = bnxt_set_tpa(bp,
5127 (flags & BNXT_FLAG_TPA) ?
5128 true : false);
5129 if (rc)
5130 bp->flags = old_flags;
5131 }
5132 }
5133 return rc;
5134}
5135
9f554590
MC		 5136static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5137{
b6ab4b01 5138 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 5139 int i = bnapi->index;
5140
3b2b7d9d
MC		 5141 if (!txr)
5142 return;
5143
9f554590
MC		 5144 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5145 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5146 txr->tx_cons);
5147}
5148
5149static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5150{
b6ab4b01 5151 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 5152 int i = bnapi->index;
5153
3b2b7d9d
MC		 5154 if (!rxr)
5155 return;
5156
9f554590
MC		 5157 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5158 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5159 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5160 rxr->rx_sw_agg_prod);
5161}
5162
5163static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5164{
5165 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5166 int i = bnapi->index;
5167
5168 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5169 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5170}
5171
c0c050c5
MC		 5172static void bnxt_dbg_dump_states(struct bnxt *bp)
5173{
5174 int i;
5175 struct bnxt_napi *bnapi;
c0c050c5
MC		 5176
5177 for (i = 0; i < bp->cp_nr_rings; i++) {
5178 bnapi = bp->bnapi[i];
c0c050c5 5179 if (netif_msg_drv(bp)) {
9f554590
MC		 5180 bnxt_dump_tx_sw_state(bnapi);
5181 bnxt_dump_rx_sw_state(bnapi);
5182 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 5183 }
5184 }
5185}
5186
5187static void bnxt_reset_task(struct bnxt *bp)
5188{
5189 bnxt_dbg_dump_states(bp);
028de140
MC		 5190 if (netif_running(bp->dev)) {
5191 bnxt_close_nic(bp, false, false);
5192 bnxt_open_nic(bp, false, false);
5193 }
c0c050c5
MC		 5194}
5195
5196static void bnxt_tx_timeout(struct net_device *dev)
5197{
5198 struct bnxt *bp = netdev_priv(dev);
5199
5200 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
5201 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5202 schedule_work(&bp->sp_task);
5203}
5204
5205#ifdef CONFIG_NET_POLL_CONTROLLER
5206static void bnxt_poll_controller(struct net_device *dev)
5207{
5208 struct bnxt *bp = netdev_priv(dev);
5209 int i;
5210
5211 for (i = 0; i < bp->cp_nr_rings; i++) {
5212 struct bnxt_irq *irq = &bp->irq_tbl[i];
5213
5214 disable_irq(irq->vector);
5215 irq->handler(irq->vector, bp->bnapi[i]);
5216 enable_irq(irq->vector);
5217 }
5218}
5219#endif
5220
5221static void bnxt_timer(unsigned long data)
5222{
5223 struct bnxt *bp = (struct bnxt *)data;
5224 struct net_device *dev = bp->dev;
5225
5226 if (!netif_running(dev))
5227 return;
5228
5229 if (atomic_read(&bp->intr_sem) != 0)
5230 goto bnxt_restart_timer;
5231
5232bnxt_restart_timer:
5233 mod_timer(&bp->timer, jiffies + bp->current_interval);
5234}
5235
5236static void bnxt_cfg_ntp_filters(struct bnxt *);
5237
5238static void bnxt_sp_task(struct work_struct *work)
5239{
5240 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5241 int rc;
5242
4cebdcec
MC		 5243 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5244 smp_mb__after_atomic();
5245 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5246 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 5247 return;
4cebdcec 5248 }
c0c050c5
MC		 5249
5250 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5251 bnxt_cfg_rx_mode(bp);
5252
5253 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5254 bnxt_cfg_ntp_filters(bp);
5255 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5256 rc = bnxt_update_link(bp, true);
5257 if (rc)
5258 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5259 rc);
5260 }
5261 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5262 bnxt_hwrm_exec_fwd_req(bp);
5263 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5264 bnxt_hwrm_tunnel_dst_port_alloc(
5265 bp, bp->vxlan_port,
5266 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5267 }
5268 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5269 bnxt_hwrm_tunnel_dst_port_free(
5270 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5271 }
028de140
MC		 5272 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5273 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5274 * for BNXT_STATE_IN_SP_TASK to clear.
5275 */
5276 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5277 rtnl_lock();
c0c050c5 5278 bnxt_reset_task(bp);
028de140
MC		 5279 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5280 rtnl_unlock();
5281 }
4cebdcec
MC		 5282
5283 smp_mb__before_atomic();
5284 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 5285}
5286
5287static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5288{
5289 int rc;
5290 struct bnxt *bp = netdev_priv(dev);
5291
5292 SET_NETDEV_DEV(dev, &pdev->dev);
5293
5294 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5295 rc = pci_enable_device(pdev);
5296 if (rc) {
5297 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5298 goto init_err;
5299 }
5300
5301 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5302 dev_err(&pdev->dev,
5303 "Cannot find PCI device base address, aborting\n");
5304 rc = -ENODEV;
5305 goto init_err_disable;
5306 }
5307
5308 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5309 if (rc) {
5310 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5311 goto init_err_disable;
5312 }
5313
5314 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5315 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5316 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5317 goto init_err_disable;
5318 }
5319
5320 pci_set_master(pdev);
5321
5322 bp->dev = dev;
5323 bp->pdev = pdev;
5324
5325 bp->bar0 = pci_ioremap_bar(pdev, 0);
5326 if (!bp->bar0) {
5327 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5328 rc = -ENOMEM;
5329 goto init_err_release;
5330 }
5331
5332 bp->bar1 = pci_ioremap_bar(pdev, 2);
5333 if (!bp->bar1) {
5334 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5335 rc = -ENOMEM;
5336 goto init_err_release;
5337 }
5338
5339 bp->bar2 = pci_ioremap_bar(pdev, 4);
5340 if (!bp->bar2) {
5341 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5342 rc = -ENOMEM;
5343 goto init_err_release;
5344 }
5345
5346 INIT_WORK(&bp->sp_task, bnxt_sp_task);
5347
5348 spin_lock_init(&bp->ntp_fltr_lock);
5349
5350 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5351 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5352
dfb5b894 5353 /* tick values in micro seconds */
dfc9c94a
MC		 5354 bp->rx_coal_ticks = 12;
5355 bp->rx_coal_bufs = 30;
dfb5b894
MC		 5356 bp->rx_coal_ticks_irq = 1;
5357 bp->rx_coal_bufs_irq = 2;
c0c050c5 5358
dfc9c94a
MC		 5359 bp->tx_coal_ticks = 25;
5360 bp->tx_coal_bufs = 30;
5361 bp->tx_coal_ticks_irq = 2;
5362 bp->tx_coal_bufs_irq = 2;
5363
c0c050c5
MC		 5364 init_timer(&bp->timer);
5365 bp->timer.data = (unsigned long)bp;
5366 bp->timer.function = bnxt_timer;
5367 bp->current_interval = BNXT_TIMER_INTERVAL;
5368
caefe526 5369 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 5370
5371 return 0;
5372
5373init_err_release:
5374 if (bp->bar2) {
5375 pci_iounmap(pdev, bp->bar2);
5376 bp->bar2 = NULL;
5377 }
5378
5379 if (bp->bar1) {
5380 pci_iounmap(pdev, bp->bar1);
5381 bp->bar1 = NULL;
5382 }
5383
5384 if (bp->bar0) {
5385 pci_iounmap(pdev, bp->bar0);
5386 bp->bar0 = NULL;
5387 }
5388
5389 pci_release_regions(pdev);
5390
5391init_err_disable:
5392 pci_disable_device(pdev);
5393
5394init_err:
5395 return rc;
5396}
5397
5398/* rtnl_lock held */
5399static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5400{
5401 struct sockaddr *addr = p;
1fc2cfd0
JH		 5402 struct bnxt *bp = netdev_priv(dev);
5403 int rc = 0;
c0c050c5
MC		 5404
5405 if (!is_valid_ether_addr(addr->sa_data))
5406 return -EADDRNOTAVAIL;
5407
bdd4347b
JH		 5408#ifdef CONFIG_BNXT_SRIOV
5409 if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr))
5410 return -EADDRNOTAVAIL;
5411#endif
5412
1fc2cfd0
JH		 5413 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5414 return 0;
5415
c0c050c5 5416 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 5417 if (netif_running(dev)) {
5418 bnxt_close_nic(bp, false, false);
5419 rc = bnxt_open_nic(bp, false, false);
5420 }
c0c050c5 5421
1fc2cfd0 5422 return rc;
c0c050c5
MC		 5423}
5424
5425/* rtnl_lock held */
5426static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5427{
5428 struct bnxt *bp = netdev_priv(dev);
5429
5430 if (new_mtu < 60 || new_mtu > 9000)
5431 return -EINVAL;
5432
5433 if (netif_running(dev))
5434 bnxt_close_nic(bp, false, false);
5435
5436 dev->mtu = new_mtu;
5437 bnxt_set_ring_params(bp);
5438
5439 if (netif_running(dev))
5440 return bnxt_open_nic(bp, false, false);
5441
5442 return 0;
5443}
5444
16e5cc64
JF		 5445static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
5446 struct tc_to_netdev *ntc)
c0c050c5
MC		 5447{
5448 struct bnxt *bp = netdev_priv(dev);
16e5cc64 5449 u8 tc;
c0c050c5 5450
5eb4dce3 5451 if (ntc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 5452 return -EINVAL;
5453
16e5cc64
JF		 5454 tc = ntc->tc;
5455
c0c050c5
MC		 5456 if (tc > bp->max_tc) {
5457 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5458 tc, bp->max_tc);
5459 return -EINVAL;
5460 }
5461
5462 if (netdev_get_num_tc(dev) == tc)
5463 return 0;
5464
5465 if (tc) {
6e6c5a57 5466 int max_rx_rings, max_tx_rings, rc;
01657bcd
MC		 5467 bool sh = false;
5468
5469 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5470 sh = true;
c0c050c5 5471
01657bcd 5472 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57 5473 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
c0c050c5
MC		 5474 return -ENOMEM;
5475 }
5476
5477 /* Needs to close the device and do hw resource re-allocations */
5478 if (netif_running(bp->dev))
5479 bnxt_close_nic(bp, true, false);
5480
5481 if (tc) {
5482 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5483 netdev_set_num_tc(dev, tc);
5484 } else {
5485 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5486 netdev_reset_tc(dev);
5487 }
5488 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5489 bp->num_stat_ctxs = bp->cp_nr_rings;
5490
5491 if (netif_running(bp->dev))
5492 return bnxt_open_nic(bp, true, false);
5493
5494 return 0;
5495}
5496
5497#ifdef CONFIG_RFS_ACCEL
5498static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5499 struct bnxt_ntuple_filter *f2)
5500{
5501 struct flow_keys *keys1 = &f1->fkeys;
5502 struct flow_keys *keys2 = &f2->fkeys;
5503
5504 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5505 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5506 keys1->ports.ports == keys2->ports.ports &&
5507 keys1->basic.ip_proto == keys2->basic.ip_proto &&
5508 keys1->basic.n_proto == keys2->basic.n_proto &&
5509 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5510 return true;
5511
5512 return false;
5513}
5514
5515static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5516 u16 rxq_index, u32 flow_id)
5517{
5518 struct bnxt *bp = netdev_priv(dev);
5519 struct bnxt_ntuple_filter *fltr, *new_fltr;
5520 struct flow_keys *fkeys;
5521 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
84e86b98 5522 int rc = 0, idx, bit_id;
c0c050c5
MC		 5523 struct hlist_head *head;
5524
5525 if (skb->encapsulation)
5526 return -EPROTONOSUPPORT;
5527
5528 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5529 if (!new_fltr)
5530 return -ENOMEM;
5531
5532 fkeys = &new_fltr->fkeys;
5533 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5534 rc = -EPROTONOSUPPORT;
5535 goto err_free;
5536 }
5537
5538 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5539 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5540 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5541 rc = -EPROTONOSUPPORT;
5542 goto err_free;
5543 }
5544
5545 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5546
5547 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5548 head = &bp->ntp_fltr_hash_tbl[idx];
5549 rcu_read_lock();
5550 hlist_for_each_entry_rcu(fltr, head, hash) {
5551 if (bnxt_fltr_match(fltr, new_fltr)) {
5552 rcu_read_unlock();
5553 rc = 0;
5554 goto err_free;
5555 }
5556 }
5557 rcu_read_unlock();
5558
5559 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 5560 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5561 BNXT_NTP_FLTR_MAX_FLTR, 0);
5562 if (bit_id < 0) {
c0c050c5
MC		 5563 spin_unlock_bh(&bp->ntp_fltr_lock);
5564 rc = -ENOMEM;
5565 goto err_free;
5566 }
5567
84e86b98 5568 new_fltr->sw_id = (u16)bit_id;
c0c050c5
MC		 5569 new_fltr->flow_id = flow_id;
5570 new_fltr->rxq = rxq_index;
5571 hlist_add_head_rcu(&new_fltr->hash, head);
5572 bp->ntp_fltr_count++;
5573 spin_unlock_bh(&bp->ntp_fltr_lock);
5574
5575 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5576 schedule_work(&bp->sp_task);
5577
5578 return new_fltr->sw_id;
5579
5580err_free:
5581 kfree(new_fltr);
5582 return rc;
5583}
5584
5585static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5586{
5587 int i;
5588
5589 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5590 struct hlist_head *head;
5591 struct hlist_node *tmp;
5592 struct bnxt_ntuple_filter *fltr;
5593 int rc;
5594
5595 head = &bp->ntp_fltr_hash_tbl[i];
5596 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5597 bool del = false;
5598
5599 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5600 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5601 fltr->flow_id,
5602 fltr->sw_id)) {
5603 bnxt_hwrm_cfa_ntuple_filter_free(bp,
5604 fltr);
5605 del = true;
5606 }
5607 } else {
5608 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5609 fltr);
5610 if (rc)
5611 del = true;
5612 else
5613 set_bit(BNXT_FLTR_VALID, &fltr->state);
5614 }
5615
5616 if (del) {
5617 spin_lock_bh(&bp->ntp_fltr_lock);
5618 hlist_del_rcu(&fltr->hash);
5619 bp->ntp_fltr_count--;
5620 spin_unlock_bh(&bp->ntp_fltr_lock);
5621 synchronize_rcu();
5622 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5623 kfree(fltr);
5624 }
5625 }
5626 }
19241368
JH		 5627 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
5628 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 5629}
5630
5631#else
5632
5633static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5634{
5635}
5636
5637#endif /* CONFIG_RFS_ACCEL */
5638
5639static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5640 __be16 port)
5641{
5642 struct bnxt *bp = netdev_priv(dev);
5643
5644 if (!netif_running(dev))
5645 return;
5646
5647 if (sa_family != AF_INET6 && sa_family != AF_INET)
5648 return;
5649
5650 if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5651 return;
5652
5653 bp->vxlan_port_cnt++;
5654 if (bp->vxlan_port_cnt == 1) {
5655 bp->vxlan_port = port;
5656 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5657 schedule_work(&bp->sp_task);
5658 }
5659}
5660
5661static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5662 __be16 port)
5663{
5664 struct bnxt *bp = netdev_priv(dev);
5665
5666 if (!netif_running(dev))
5667 return;
5668
5669 if (sa_family != AF_INET6 && sa_family != AF_INET)
5670 return;
5671
5672 if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5673 bp->vxlan_port_cnt--;
5674
5675 if (bp->vxlan_port_cnt == 0) {
5676 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5677 schedule_work(&bp->sp_task);
5678 }
5679 }
5680}
5681
5682static const struct net_device_ops bnxt_netdev_ops = {
5683 .ndo_open = bnxt_open,
5684 .ndo_start_xmit = bnxt_start_xmit,
5685 .ndo_stop = bnxt_close,
5686 .ndo_get_stats64 = bnxt_get_stats64,
5687 .ndo_set_rx_mode = bnxt_set_rx_mode,
5688 .ndo_do_ioctl = bnxt_ioctl,
5689 .ndo_validate_addr = eth_validate_addr,
5690 .ndo_set_mac_address = bnxt_change_mac_addr,
5691 .ndo_change_mtu = bnxt_change_mtu,
5692 .ndo_fix_features = bnxt_fix_features,
5693 .ndo_set_features = bnxt_set_features,
5694 .ndo_tx_timeout = bnxt_tx_timeout,
5695#ifdef CONFIG_BNXT_SRIOV
5696 .ndo_get_vf_config = bnxt_get_vf_config,
5697 .ndo_set_vf_mac = bnxt_set_vf_mac,
5698 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
5699 .ndo_set_vf_rate = bnxt_set_vf_bw,
5700 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
5701 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
5702#endif
5703#ifdef CONFIG_NET_POLL_CONTROLLER
5704 .ndo_poll_controller = bnxt_poll_controller,
5705#endif
5706 .ndo_setup_tc = bnxt_setup_tc,
5707#ifdef CONFIG_RFS_ACCEL
5708 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
5709#endif
5710 .ndo_add_vxlan_port = bnxt_add_vxlan_port,
5711 .ndo_del_vxlan_port = bnxt_del_vxlan_port,
5712#ifdef CONFIG_NET_RX_BUSY_POLL
5713 .ndo_busy_poll = bnxt_busy_poll,
5714#endif
5715};
5716
5717static void bnxt_remove_one(struct pci_dev *pdev)
5718{
5719 struct net_device *dev = pci_get_drvdata(pdev);
5720 struct bnxt *bp = netdev_priv(dev);
5721
5722 if (BNXT_PF(bp))
5723 bnxt_sriov_disable(bp);
5724
5725 unregister_netdev(dev);
5726 cancel_work_sync(&bp->sp_task);
5727 bp->sp_event = 0;
5728
be58a0da 5729 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5
MC		 5730 bnxt_free_hwrm_resources(bp);
5731 pci_iounmap(pdev, bp->bar2);
5732 pci_iounmap(pdev, bp->bar1);
5733 pci_iounmap(pdev, bp->bar0);
5734 free_netdev(dev);
5735
5736 pci_release_regions(pdev);
5737 pci_disable_device(pdev);
5738}
5739
5740static int bnxt_probe_phy(struct bnxt *bp)
5741{
5742 int rc = 0;
5743 struct bnxt_link_info *link_info = &bp->link_info;
c0c050c5
MC		 5744
5745 rc = bnxt_update_link(bp, false);
5746 if (rc) {
5747 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5748 rc);
5749 return rc;
5750 }
5751
5752 /*initialize the ethool setting copy with NVM settings */
0d8abf02
MC		 5753 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
5754 link_info->autoneg = BNXT_AUTONEG_SPEED |
5755 BNXT_AUTONEG_FLOW_CTRL;
5756 link_info->advertising = link_info->auto_link_speeds;
c0c050c5 5757 link_info->req_flow_ctrl = link_info->auto_pause_setting;
0d8abf02
MC		 5758 } else {
5759 link_info->req_link_speed = link_info->force_link_speed;
5760 link_info->req_duplex = link_info->duplex_setting;
c0c050c5
MC		 5761 link_info->req_flow_ctrl = link_info->force_pause_setting;
5762 }
c0c050c5
MC		 5763 return rc;
5764}
5765
5766static int bnxt_get_max_irq(struct pci_dev *pdev)
5767{
5768 u16 ctrl;
5769
5770 if (!pdev->msix_cap)
5771 return 1;
5772
5773 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5774 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5775}
5776
6e6c5a57
MC		 5777static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
5778 int *max_cp)
c0c050c5 5779{
6e6c5a57 5780 int max_ring_grps = 0;
c0c050c5 5781
379a80a1 5782#ifdef CONFIG_BNXT_SRIOV
415b6f19 5783 if (!BNXT_PF(bp)) {
c0c050c5
MC		 5784 *max_tx = bp->vf.max_tx_rings;
5785 *max_rx = bp->vf.max_rx_rings;
6e6c5a57
MC		 5786 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5787 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
b72d4a68 5788 max_ring_grps = bp->vf.max_hw_ring_grps;
415b6f19 5789 } else
379a80a1 5790#endif
415b6f19
AB		 5791 {
5792 *max_tx = bp->pf.max_tx_rings;
5793 *max_rx = bp->pf.max_rx_rings;
5794 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5795 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
5796 max_ring_grps = bp->pf.max_hw_ring_grps;
c0c050c5 5797 }
415b6f19 5798
c0c050c5
MC		 5799 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5800 *max_rx >>= 1;
b72d4a68 5801 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 5802}
5803
5804int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
5805{
5806 int rx, tx, cp;
5807
5808 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
5809 if (!rx || !tx || !cp)
5810 return -ENOMEM;
5811
5812 *max_rx = rx;
5813 *max_tx = tx;
5814 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
5815}
5816
5817static int bnxt_set_dflt_rings(struct bnxt *bp)
5818{
5819 int dflt_rings, max_rx_rings, max_tx_rings, rc;
5820 bool sh = true;
5821
5822 if (sh)
5823 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5824 dflt_rings = netif_get_num_default_rss_queues();
5825 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5826 if (rc)
5827 return rc;
5828 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5829 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5830 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5831 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5832 bp->tx_nr_rings + bp->rx_nr_rings;
5833 bp->num_stat_ctxs = bp->cp_nr_rings;
5834 return rc;
c0c050c5
MC		 5835}
5836
5837static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5838{
5839 static int version_printed;
5840 struct net_device *dev;
5841 struct bnxt *bp;
6e6c5a57 5842 int rc, max_irqs;
c0c050c5
MC		 5843
5844 if (version_printed++ == 0)
5845 pr_info("%s", version);
5846
5847 max_irqs = bnxt_get_max_irq(pdev);
5848 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5849 if (!dev)
5850 return -ENOMEM;
5851
5852 bp = netdev_priv(dev);
5853
5854 if (bnxt_vf_pciid(ent->driver_data))
5855 bp->flags |= BNXT_FLAG_VF;
5856
2bcfa6f6 5857 if (pdev->msix_cap)
c0c050c5 5858 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 5859
5860 rc = bnxt_init_board(pdev, dev);
5861 if (rc < 0)
5862 goto init_err_free;
5863
5864 dev->netdev_ops = &bnxt_netdev_ops;
5865 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5866 dev->ethtool_ops = &bnxt_ethtool_ops;
5867
5868 pci_set_drvdata(pdev, dev);
5869
5870 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5871 NETIF_F_TSO | NETIF_F_TSO6 |
5872 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5873 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5874 NETIF_F_RXHASH |
5875 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5876
c0c050c5
MC		 5877 dev->hw_enc_features =
5878 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5879 NETIF_F_TSO | NETIF_F_TSO6 |
5880 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5881 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5882 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5883 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5884 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5885 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5886 dev->priv_flags |= IFF_UNICAST_FLT;
5887
5888#ifdef CONFIG_BNXT_SRIOV
5889 init_waitqueue_head(&bp->sriov_cfg_wait);
5890#endif
5891 rc = bnxt_alloc_hwrm_resources(bp);
5892 if (rc)
5893 goto init_err;
5894
5895 mutex_init(&bp->hwrm_cmd_lock);
5896 bnxt_hwrm_ver_get(bp);
5897
5898 rc = bnxt_hwrm_func_drv_rgtr(bp);
5899 if (rc)
5900 goto init_err;
5901
5902 /* Get the MAX capabilities for this function */
5903 rc = bnxt_hwrm_func_qcaps(bp);
5904 if (rc) {
5905 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
5906 rc);
5907 rc = -1;
5908 goto init_err;
5909 }
5910
5911 rc = bnxt_hwrm_queue_qportcfg(bp);
5912 if (rc) {
5913 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
5914 rc);
5915 rc = -1;
5916 goto init_err;
5917 }
5918
5919 bnxt_set_tpa_flags(bp);
5920 bnxt_set_ring_params(bp);
bdd4347b 5921 if (BNXT_PF(bp))
c0c050c5 5922 bp->pf.max_irqs = max_irqs;
379a80a1 5923#if defined(CONFIG_BNXT_SRIOV)
bdd4347b 5924 else
c0c050c5 5925 bp->vf.max_irqs = max_irqs;
379a80a1 5926#endif
6e6c5a57 5927 bnxt_set_dflt_rings(bp);
c0c050c5 5928
2bcfa6f6
MC		 5929 if (BNXT_PF(bp)) {
5930 dev->hw_features |= NETIF_F_NTUPLE;
5931 if (bnxt_rfs_capable(bp)) {
5932 bp->flags |= BNXT_FLAG_RFS;
5933 dev->features |= NETIF_F_NTUPLE;
5934 }
5935 }
5936
c0c050c5
MC		 5937 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
5938 bp->flags |= BNXT_FLAG_STRIP_VLAN;
5939
5940 rc = bnxt_probe_phy(bp);
5941 if (rc)
5942 goto init_err;
5943
5944 rc = register_netdev(dev);
5945 if (rc)
5946 goto init_err;
5947
5948 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
5949 board_info[ent->driver_data].name,
5950 (long)pci_resource_start(pdev, 0), dev->dev_addr);
5951
5952 return 0;
5953
5954init_err:
5955 pci_iounmap(pdev, bp->bar0);
5956 pci_release_regions(pdev);
5957 pci_disable_device(pdev);
5958
5959init_err_free:
5960 free_netdev(dev);
5961 return rc;
5962}
5963
5964static struct pci_driver bnxt_pci_driver = {
5965 .name = DRV_MODULE_NAME,
5966 .id_table = bnxt_pci_tbl,
5967 .probe = bnxt_init_one,
5968 .remove = bnxt_remove_one,
5969#if defined(CONFIG_BNXT_SRIOV)
5970 .sriov_configure = bnxt_sriov_configure,
5971#endif
5972};
5973
5974module_pci_driver(bnxt_pci_driver);
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