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bnxt_en: Enable MRU enables bit when configuring VNIC MRU.
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
11f15ed3 3 * Copyright (c) 2014-2016 Broadcom Corporation
c0c050c5
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11
12#include <linux/stringify.h>
13#include <linux/kernel.h>
14#include <linux/timer.h>
15#include <linux/errno.h>
16#include <linux/ioport.h>
17#include <linux/slab.h>
18#include <linux/vmalloc.h>
19#include <linux/interrupt.h>
20#include <linux/pci.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/dma-mapping.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/delay.h>
29#include <asm/byteorder.h>
30#include <asm/page.h>
31#include <linux/time.h>
32#include <linux/mii.h>
33#include <linux/if.h>
34#include <linux/if_vlan.h>
35#include <net/ip.h>
36#include <net/tcp.h>
37#include <net/udp.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
ad51b8e9 40#include <net/udp_tunnel.h>
c0c050c5
MC		 41#ifdef CONFIG_NET_RX_BUSY_POLL
42#include <net/busy_poll.h>
43#endif
44#include <linux/workqueue.h>
45#include <linux/prefetch.h>
46#include <linux/cache.h>
47#include <linux/log2.h>
48#include <linux/aer.h>
49#include <linux/bitmap.h>
50#include <linux/cpu_rmap.h>
51
52#include "bnxt_hsi.h"
53#include "bnxt.h"
54#include "bnxt_sriov.h"
55#include "bnxt_ethtool.h"
56
57#define BNXT_TX_TIMEOUT (5 * HZ)
58
59static const char version[] =
60 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
61
62MODULE_LICENSE("GPL");
63MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
64MODULE_VERSION(DRV_MODULE_VERSION);
65
66#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
67#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
68#define BNXT_RX_COPY_THRESH 256
69
4419dbe6 70#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 71
72enum board_idx {
fbc9a523 73 BCM57301,
c0c050c5
MC		 74 BCM57302,
75 BCM57304,
b24eb6ae
MC		 76 BCM57311,
77 BCM57312,
fbc9a523 78 BCM57402,
c0c050c5
MC		 79 BCM57404,
80 BCM57406,
ebcd4eeb 81 BCM57404_NPAR,
b24eb6ae
MC		 82 BCM57412,
83 BCM57414,
84 BCM57416,
85 BCM57417,
86 BCM57414_NPAR,
5049e33b 87 BCM57314,
c0c050c5
MC		 88 BCM57304_VF,
89 BCM57404_VF,
b24eb6ae
MC		 90 BCM57414_VF,
91 BCM57314_VF,
c0c050c5
MC		 92};
93
94/* indexed by enum above */
95static const struct {
96 char *name;
97} board_info[] = {
fbc9a523
DC		 98 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
99 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
c0c050c5 100 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
b24eb6ae
MC		 101 { "Broadcom BCM57311 NetXtreme-C Single-port 10Gb Ethernet" },
102 { "Broadcom BCM57312 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
fbc9a523 103 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
c0c050c5 104 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
fbc9a523 105 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
ebcd4eeb 106 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
b24eb6ae
MC		 107 { "Broadcom BCM57412 NetXtreme-E Dual-port 10Gb Ethernet" },
108 { "Broadcom BCM57414 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
109 { "Broadcom BCM57416 NetXtreme-E Dual-port 10GBase-T Ethernet" },
110 { "Broadcom BCM57417 NetXtreme-E Dual-port 10GBase-T Ethernet" },
111 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
5049e33b 112 { "Broadcom BCM57314 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
c0c050c5
MC		 113 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
114 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
b24eb6ae
MC		 115 { "Broadcom BCM57414 NetXtreme-E Ethernet Virtual Function" },
116 { "Broadcom BCM57314 NetXtreme-E Ethernet Virtual Function" },
c0c050c5
MC		 117};
118
119static const struct pci_device_id bnxt_pci_tbl[] = {
fbc9a523 120 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 121 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
122 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
b24eb6ae
MC		 123 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
124 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
fbc9a523 125 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 126 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
127 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
ebcd4eeb 128 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57404_NPAR },
b24eb6ae
MC		 129 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
130 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
131 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
132 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
133 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57414_NPAR },
5049e33b 134 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
c0c050c5
MC		 135#ifdef CONFIG_BNXT_SRIOV
136 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
137 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
b24eb6ae
MC		 138 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = BCM57414_VF },
139 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = BCM57314_VF },
c0c050c5
MC		 140#endif
141 { 0 }
142};
143
144MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
145
146static const u16 bnxt_vf_req_snif[] = {
147 HWRM_FUNC_CFG,
148 HWRM_PORT_PHY_QCFG,
149 HWRM_CFA_L2_FILTER_ALLOC,
150};
151
25be8623
MC		 152static const u16 bnxt_async_events_arr[] = {
153 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
154 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
4bb13abf 155 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
fc0f1929 156 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
8cbde117 157 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
25be8623
MC		 158};
159
c0c050c5
MC		 160static bool bnxt_vf_pciid(enum board_idx idx)
161{
b24eb6ae
MC		 162 return (idx == BCM57304_VF || idx == BCM57404_VF ||
163 idx == BCM57314_VF || idx == BCM57414_VF);
c0c050c5
MC		 164}
165
166#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
167#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
168#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
169
170#define BNXT_CP_DB_REARM(db, raw_cons) \
171 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
172
173#define BNXT_CP_DB(db, raw_cons) \
174 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
175
176#define BNXT_CP_DB_IRQ_DIS(db) \
177 writel(DB_CP_IRQ_DIS_FLAGS, db)
178
179static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
180{
181 /* Tell compiler to fetch tx indices from memory. */
182 barrier();
183
184 return bp->tx_ring_size -
185 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
186}
187
188static const u16 bnxt_lhint_arr[] = {
189 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
190 TX_BD_FLAGS_LHINT_512_TO_1023,
191 TX_BD_FLAGS_LHINT_1024_TO_2047,
192 TX_BD_FLAGS_LHINT_1024_TO_2047,
193 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
194 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
195 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
196 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
197 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
198 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
199 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
200 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
201 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
202 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
203 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
204 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
205 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
206 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
207 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
208};
209
210static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
211{
212 struct bnxt *bp = netdev_priv(dev);
213 struct tx_bd *txbd;
214 struct tx_bd_ext *txbd1;
215 struct netdev_queue *txq;
216 int i;
217 dma_addr_t mapping;
218 unsigned int length, pad = 0;
219 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
220 u16 prod, last_frag;
221 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 222 struct bnxt_tx_ring_info *txr;
223 struct bnxt_sw_tx_bd *tx_buf;
224
225 i = skb_get_queue_mapping(skb);
226 if (unlikely(i >= bp->tx_nr_rings)) {
227 dev_kfree_skb_any(skb);
228 return NETDEV_TX_OK;
229 }
230
b6ab4b01 231 txr = &bp->tx_ring[i];
c0c050c5
MC		 232 txq = netdev_get_tx_queue(dev, i);
233 prod = txr->tx_prod;
234
235 free_size = bnxt_tx_avail(bp, txr);
236 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
237 netif_tx_stop_queue(txq);
238 return NETDEV_TX_BUSY;
239 }
240
241 length = skb->len;
242 len = skb_headlen(skb);
243 last_frag = skb_shinfo(skb)->nr_frags;
244
245 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
246
247 txbd->tx_bd_opaque = prod;
248
249 tx_buf = &txr->tx_buf_ring[prod];
250 tx_buf->skb = skb;
251 tx_buf->nr_frags = last_frag;
252
253 vlan_tag_flags = 0;
254 cfa_action = 0;
255 if (skb_vlan_tag_present(skb)) {
256 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
257 skb_vlan_tag_get(skb);
258 /* Currently supports 8021Q, 8021AD vlan offloads
259 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
260 */
261 if (skb->vlan_proto == htons(ETH_P_8021Q))
262 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
263 }
264
265 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 266 struct tx_push_buffer *tx_push_buf = txr->tx_push;
267 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
268 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
269 void *pdata = tx_push_buf->data;
270 u64 *end;
271 int j, push_len;
c0c050c5
MC		 272
273 /* Set COAL_NOW to be ready quickly for the next push */
274 tx_push->tx_bd_len_flags_type =
275 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
276 TX_BD_TYPE_LONG_TX_BD |
277 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
278 TX_BD_FLAGS_COAL_NOW |
279 TX_BD_FLAGS_PACKET_END |
280 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
281
282 if (skb->ip_summed == CHECKSUM_PARTIAL)
283 tx_push1->tx_bd_hsize_lflags =
284 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
285 else
286 tx_push1->tx_bd_hsize_lflags = 0;
287
288 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
289 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
290
fbb0fa8b
MC		 291 end = pdata + length;
292 end = PTR_ALIGN(end, 8) - 1;
4419dbe6
MC		 293 *end = 0;
294
c0c050c5
MC		 295 skb_copy_from_linear_data(skb, pdata, len);
296 pdata += len;
297 for (j = 0; j < last_frag; j++) {
298 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
299 void *fptr;
300
301 fptr = skb_frag_address_safe(frag);
302 if (!fptr)
303 goto normal_tx;
304
305 memcpy(pdata, fptr, skb_frag_size(frag));
306 pdata += skb_frag_size(frag);
307 }
308
4419dbe6
MC		 309 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
310 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 311 prod = NEXT_TX(prod);
312 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
313 memcpy(txbd, tx_push1, sizeof(*txbd));
314 prod = NEXT_TX(prod);
4419dbe6 315 tx_push->doorbell =
c0c050c5
MC		 316 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
317 txr->tx_prod = prod;
318
b9a8460a 319 tx_buf->is_push = 1;
c0c050c5 320 netdev_tx_sent_queue(txq, skb->len);
b9a8460a 321 wmb(); /* Sync is_push and byte queue before pushing data */
c0c050c5 322
4419dbe6
MC		 323 push_len = (length + sizeof(*tx_push) + 7) / 8;
324 if (push_len > 16) {
325 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
326 __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
327 push_len - 16);
328 } else {
329 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
330 push_len);
331 }
c0c050c5 332
c0c050c5
MC		 333 goto tx_done;
334 }
335
336normal_tx:
337 if (length < BNXT_MIN_PKT_SIZE) {
338 pad = BNXT_MIN_PKT_SIZE - length;
339 if (skb_pad(skb, pad)) {
340 /* SKB already freed. */
341 tx_buf->skb = NULL;
342 return NETDEV_TX_OK;
343 }
344 length = BNXT_MIN_PKT_SIZE;
345 }
346
347 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
348
349 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
350 dev_kfree_skb_any(skb);
351 tx_buf->skb = NULL;
352 return NETDEV_TX_OK;
353 }
354
355 dma_unmap_addr_set(tx_buf, mapping, mapping);
356 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
357 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
358
359 txbd->tx_bd_haddr = cpu_to_le64(mapping);
360
361 prod = NEXT_TX(prod);
362 txbd1 = (struct tx_bd_ext *)
363 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
364
365 txbd1->tx_bd_hsize_lflags = 0;
366 if (skb_is_gso(skb)) {
367 u32 hdr_len;
368
369 if (skb->encapsulation)
370 hdr_len = skb_inner_network_offset(skb) +
371 skb_inner_network_header_len(skb) +
372 inner_tcp_hdrlen(skb);
373 else
374 hdr_len = skb_transport_offset(skb) +
375 tcp_hdrlen(skb);
376
377 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
378 TX_BD_FLAGS_T_IPID |
379 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
380 length = skb_shinfo(skb)->gso_size;
381 txbd1->tx_bd_mss = cpu_to_le32(length);
382 length += hdr_len;
383 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
384 txbd1->tx_bd_hsize_lflags =
385 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
386 txbd1->tx_bd_mss = 0;
387 }
388
389 length >>= 9;
390 flags |= bnxt_lhint_arr[length];
391 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
392
393 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
394 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
395 for (i = 0; i < last_frag; i++) {
396 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
397
398 prod = NEXT_TX(prod);
399 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
400
401 len = skb_frag_size(frag);
402 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
403 DMA_TO_DEVICE);
404
405 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
406 goto tx_dma_error;
407
408 tx_buf = &txr->tx_buf_ring[prod];
409 dma_unmap_addr_set(tx_buf, mapping, mapping);
410
411 txbd->tx_bd_haddr = cpu_to_le64(mapping);
412
413 flags = len << TX_BD_LEN_SHIFT;
414 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
415 }
416
417 flags &= ~TX_BD_LEN;
418 txbd->tx_bd_len_flags_type =
419 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
420 TX_BD_FLAGS_PACKET_END);
421
422 netdev_tx_sent_queue(txq, skb->len);
423
424 /* Sync BD data before updating doorbell */
425 wmb();
426
427 prod = NEXT_TX(prod);
428 txr->tx_prod = prod;
429
430 writel(DB_KEY_TX | prod, txr->tx_doorbell);
431 writel(DB_KEY_TX | prod, txr->tx_doorbell);
432
433tx_done:
434
435 mmiowb();
436
437 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
438 netif_tx_stop_queue(txq);
439
440 /* netif_tx_stop_queue() must be done before checking
441 * tx index in bnxt_tx_avail() below, because in
442 * bnxt_tx_int(), we update tx index before checking for
443 * netif_tx_queue_stopped().
444 */
445 smp_mb();
446 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
447 netif_tx_wake_queue(txq);
448 }
449 return NETDEV_TX_OK;
450
451tx_dma_error:
452 last_frag = i;
453
454 /* start back at beginning and unmap skb */
455 prod = txr->tx_prod;
456 tx_buf = &txr->tx_buf_ring[prod];
457 tx_buf->skb = NULL;
458 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
459 skb_headlen(skb), PCI_DMA_TODEVICE);
460 prod = NEXT_TX(prod);
461
462 /* unmap remaining mapped pages */
463 for (i = 0; i < last_frag; i++) {
464 prod = NEXT_TX(prod);
465 tx_buf = &txr->tx_buf_ring[prod];
466 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
467 skb_frag_size(&skb_shinfo(skb)->frags[i]),
468 PCI_DMA_TODEVICE);
469 }
470
471 dev_kfree_skb_any(skb);
472 return NETDEV_TX_OK;
473}
474
475static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
476{
b6ab4b01 477 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
b81a90d3 478 int index = txr - &bp->tx_ring[0];
c0c050c5
MC		 479 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
480 u16 cons = txr->tx_cons;
481 struct pci_dev *pdev = bp->pdev;
482 int i;
483 unsigned int tx_bytes = 0;
484
485 for (i = 0; i < nr_pkts; i++) {
486 struct bnxt_sw_tx_bd *tx_buf;
487 struct sk_buff *skb;
488 int j, last;
489
490 tx_buf = &txr->tx_buf_ring[cons];
491 cons = NEXT_TX(cons);
492 skb = tx_buf->skb;
493 tx_buf->skb = NULL;
494
495 if (tx_buf->is_push) {
496 tx_buf->is_push = 0;
497 goto next_tx_int;
498 }
499
500 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
501 skb_headlen(skb), PCI_DMA_TODEVICE);
502 last = tx_buf->nr_frags;
503
504 for (j = 0; j < last; j++) {
505 cons = NEXT_TX(cons);
506 tx_buf = &txr->tx_buf_ring[cons];
507 dma_unmap_page(
508 &pdev->dev,
509 dma_unmap_addr(tx_buf, mapping),
510 skb_frag_size(&skb_shinfo(skb)->frags[j]),
511 PCI_DMA_TODEVICE);
512 }
513
514next_tx_int:
515 cons = NEXT_TX(cons);
516
517 tx_bytes += skb->len;
518 dev_kfree_skb_any(skb);
519 }
520
521 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
522 txr->tx_cons = cons;
523
524 /* Need to make the tx_cons update visible to bnxt_start_xmit()
525 * before checking for netif_tx_queue_stopped(). Without the
526 * memory barrier, there is a small possibility that bnxt_start_xmit()
527 * will miss it and cause the queue to be stopped forever.
528 */
529 smp_mb();
530
531 if (unlikely(netif_tx_queue_stopped(txq)) &&
532 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
533 __netif_tx_lock(txq, smp_processor_id());
534 if (netif_tx_queue_stopped(txq) &&
535 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
536 txr->dev_state != BNXT_DEV_STATE_CLOSING)
537 netif_tx_wake_queue(txq);
538 __netif_tx_unlock(txq);
539 }
540}
541
542static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
543 gfp_t gfp)
544{
545 u8 *data;
546 struct pci_dev *pdev = bp->pdev;
547
548 data = kmalloc(bp->rx_buf_size, gfp);
549 if (!data)
550 return NULL;
551
552 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
553 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
554
555 if (dma_mapping_error(&pdev->dev, *mapping)) {
556 kfree(data);
557 data = NULL;
558 }
559 return data;
560}
561
562static inline int bnxt_alloc_rx_data(struct bnxt *bp,
563 struct bnxt_rx_ring_info *rxr,
564 u16 prod, gfp_t gfp)
565{
566 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
567 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
568 u8 *data;
569 dma_addr_t mapping;
570
571 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
572 if (!data)
573 return -ENOMEM;
574
575 rx_buf->data = data;
576 dma_unmap_addr_set(rx_buf, mapping, mapping);
577
578 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
579
580 return 0;
581}
582
583static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
584 u8 *data)
585{
586 u16 prod = rxr->rx_prod;
587 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
588 struct rx_bd *cons_bd, *prod_bd;
589
590 prod_rx_buf = &rxr->rx_buf_ring[prod];
591 cons_rx_buf = &rxr->rx_buf_ring[cons];
592
593 prod_rx_buf->data = data;
594
595 dma_unmap_addr_set(prod_rx_buf, mapping,
596 dma_unmap_addr(cons_rx_buf, mapping));
597
598 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
599 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
600
601 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
602}
603
604static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
605{
606 u16 next, max = rxr->rx_agg_bmap_size;
607
608 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
609 if (next >= max)
610 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
611 return next;
612}
613
614static inline int bnxt_alloc_rx_page(struct bnxt *bp,
615 struct bnxt_rx_ring_info *rxr,
616 u16 prod, gfp_t gfp)
617{
618 struct rx_bd *rxbd =
619 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
620 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
621 struct pci_dev *pdev = bp->pdev;
622 struct page *page;
623 dma_addr_t mapping;
624 u16 sw_prod = rxr->rx_sw_agg_prod;
89d0a06c 625 unsigned int offset = 0;
c0c050c5 626
89d0a06c
MC		 627 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
628 page = rxr->rx_page;
629 if (!page) {
630 page = alloc_page(gfp);
631 if (!page)
632 return -ENOMEM;
633 rxr->rx_page = page;
634 rxr->rx_page_offset = 0;
635 }
636 offset = rxr->rx_page_offset;
637 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
638 if (rxr->rx_page_offset == PAGE_SIZE)
639 rxr->rx_page = NULL;
640 else
641 get_page(page);
642 } else {
643 page = alloc_page(gfp);
644 if (!page)
645 return -ENOMEM;
646 }
c0c050c5 647
89d0a06c 648 mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
c0c050c5
MC		 649 PCI_DMA_FROMDEVICE);
650 if (dma_mapping_error(&pdev->dev, mapping)) {
651 __free_page(page);
652 return -EIO;
653 }
654
655 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
656 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
657
658 __set_bit(sw_prod, rxr->rx_agg_bmap);
659 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
660 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
661
662 rx_agg_buf->page = page;
89d0a06c 663 rx_agg_buf->offset = offset;
c0c050c5
MC		 664 rx_agg_buf->mapping = mapping;
665 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
666 rxbd->rx_bd_opaque = sw_prod;
667 return 0;
668}
669
670static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
671 u32 agg_bufs)
672{
673 struct bnxt *bp = bnapi->bp;
674 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 675 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 676 u16 prod = rxr->rx_agg_prod;
677 u16 sw_prod = rxr->rx_sw_agg_prod;
678 u32 i;
679
680 for (i = 0; i < agg_bufs; i++) {
681 u16 cons;
682 struct rx_agg_cmp *agg;
683 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
684 struct rx_bd *prod_bd;
685 struct page *page;
686
687 agg = (struct rx_agg_cmp *)
688 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
689 cons = agg->rx_agg_cmp_opaque;
690 __clear_bit(cons, rxr->rx_agg_bmap);
691
692 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
693 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
694
695 __set_bit(sw_prod, rxr->rx_agg_bmap);
696 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
697 cons_rx_buf = &rxr->rx_agg_ring[cons];
698
699 /* It is possible for sw_prod to be equal to cons, so
700 * set cons_rx_buf->page to NULL first.
701 */
702 page = cons_rx_buf->page;
703 cons_rx_buf->page = NULL;
704 prod_rx_buf->page = page;
89d0a06c 705 prod_rx_buf->offset = cons_rx_buf->offset;
c0c050c5
MC		 706
707 prod_rx_buf->mapping = cons_rx_buf->mapping;
708
709 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
710
711 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
712 prod_bd->rx_bd_opaque = sw_prod;
713
714 prod = NEXT_RX_AGG(prod);
715 sw_prod = NEXT_RX_AGG(sw_prod);
716 cp_cons = NEXT_CMP(cp_cons);
717 }
718 rxr->rx_agg_prod = prod;
719 rxr->rx_sw_agg_prod = sw_prod;
720}
721
722static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
723 struct bnxt_rx_ring_info *rxr, u16 cons,
724 u16 prod, u8 *data, dma_addr_t dma_addr,
725 unsigned int len)
726{
727 int err;
728 struct sk_buff *skb;
729
730 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
731 if (unlikely(err)) {
732 bnxt_reuse_rx_data(rxr, cons, data);
733 return NULL;
734 }
735
736 skb = build_skb(data, 0);
737 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
738 PCI_DMA_FROMDEVICE);
739 if (!skb) {
740 kfree(data);
741 return NULL;
742 }
743
744 skb_reserve(skb, BNXT_RX_OFFSET);
745 skb_put(skb, len);
746 return skb;
747}
748
749static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
750 struct sk_buff *skb, u16 cp_cons,
751 u32 agg_bufs)
752{
753 struct pci_dev *pdev = bp->pdev;
754 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 755 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 756 u16 prod = rxr->rx_agg_prod;
757 u32 i;
758
759 for (i = 0; i < agg_bufs; i++) {
760 u16 cons, frag_len;
761 struct rx_agg_cmp *agg;
762 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
763 struct page *page;
764 dma_addr_t mapping;
765
766 agg = (struct rx_agg_cmp *)
767 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
768 cons = agg->rx_agg_cmp_opaque;
769 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
770 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
771
772 cons_rx_buf = &rxr->rx_agg_ring[cons];
89d0a06c
MC		 773 skb_fill_page_desc(skb, i, cons_rx_buf->page,
774 cons_rx_buf->offset, frag_len);
c0c050c5
MC		 775 __clear_bit(cons, rxr->rx_agg_bmap);
776
777 /* It is possible for bnxt_alloc_rx_page() to allocate
778 * a sw_prod index that equals the cons index, so we
779 * need to clear the cons entry now.
780 */
781 mapping = dma_unmap_addr(cons_rx_buf, mapping);
782 page = cons_rx_buf->page;
783 cons_rx_buf->page = NULL;
784
785 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
786 struct skb_shared_info *shinfo;
787 unsigned int nr_frags;
788
789 shinfo = skb_shinfo(skb);
790 nr_frags = --shinfo->nr_frags;
791 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
792
793 dev_kfree_skb(skb);
794
795 cons_rx_buf->page = page;
796
797 /* Update prod since possibly some pages have been
798 * allocated already.
799 */
800 rxr->rx_agg_prod = prod;
801 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
802 return NULL;
803 }
804
2839f28b 805 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
c0c050c5
MC		 806 PCI_DMA_FROMDEVICE);
807
808 skb->data_len += frag_len;
809 skb->len += frag_len;
810 skb->truesize += PAGE_SIZE;
811
812 prod = NEXT_RX_AGG(prod);
813 cp_cons = NEXT_CMP(cp_cons);
814 }
815 rxr->rx_agg_prod = prod;
816 return skb;
817}
818
819static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
820 u8 agg_bufs, u32 *raw_cons)
821{
822 u16 last;
823 struct rx_agg_cmp *agg;
824
825 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
826 last = RING_CMP(*raw_cons);
827 agg = (struct rx_agg_cmp *)
828 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
829 return RX_AGG_CMP_VALID(agg, *raw_cons);
830}
831
832static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
833 unsigned int len,
834 dma_addr_t mapping)
835{
836 struct bnxt *bp = bnapi->bp;
837 struct pci_dev *pdev = bp->pdev;
838 struct sk_buff *skb;
839
840 skb = napi_alloc_skb(&bnapi->napi, len);
841 if (!skb)
842 return NULL;
843
844 dma_sync_single_for_cpu(&pdev->dev, mapping,
845 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
846
847 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
848
849 dma_sync_single_for_device(&pdev->dev, mapping,
850 bp->rx_copy_thresh,
851 PCI_DMA_FROMDEVICE);
852
853 skb_put(skb, len);
854 return skb;
855}
856
fa7e2812
MC		 857static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
858 u32 *raw_cons, void *cmp)
859{
860 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
861 struct rx_cmp *rxcmp = cmp;
862 u32 tmp_raw_cons = *raw_cons;
863 u8 cmp_type, agg_bufs = 0;
864
865 cmp_type = RX_CMP_TYPE(rxcmp);
866
867 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
868 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
869 RX_CMP_AGG_BUFS) >>
870 RX_CMP_AGG_BUFS_SHIFT;
871 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
872 struct rx_tpa_end_cmp *tpa_end = cmp;
873
874 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
875 RX_TPA_END_CMP_AGG_BUFS) >>
876 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
877 }
878
879 if (agg_bufs) {
880 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
881 return -EBUSY;
882 }
883 *raw_cons = tmp_raw_cons;
884 return 0;
885}
886
887static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
888{
889 if (!rxr->bnapi->in_reset) {
890 rxr->bnapi->in_reset = true;
891 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
892 schedule_work(&bp->sp_task);
893 }
894 rxr->rx_next_cons = 0xffff;
895}
896
c0c050c5
MC		 897static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
898 struct rx_tpa_start_cmp *tpa_start,
899 struct rx_tpa_start_cmp_ext *tpa_start1)
900{
901 u8 agg_id = TPA_START_AGG_ID(tpa_start);
902 u16 cons, prod;
903 struct bnxt_tpa_info *tpa_info;
904 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
905 struct rx_bd *prod_bd;
906 dma_addr_t mapping;
907
908 cons = tpa_start->rx_tpa_start_cmp_opaque;
909 prod = rxr->rx_prod;
910 cons_rx_buf = &rxr->rx_buf_ring[cons];
911 prod_rx_buf = &rxr->rx_buf_ring[prod];
912 tpa_info = &rxr->rx_tpa[agg_id];
913
fa7e2812
MC		 914 if (unlikely(cons != rxr->rx_next_cons)) {
915 bnxt_sched_reset(bp, rxr);
916 return;
917 }
918
c0c050c5
MC		 919 prod_rx_buf->data = tpa_info->data;
920
921 mapping = tpa_info->mapping;
922 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
923
924 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
925
926 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
927
928 tpa_info->data = cons_rx_buf->data;
929 cons_rx_buf->data = NULL;
930 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
931
932 tpa_info->len =
933 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
934 RX_TPA_START_CMP_LEN_SHIFT;
935 if (likely(TPA_START_HASH_VALID(tpa_start))) {
936 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
937
938 tpa_info->hash_type = PKT_HASH_TYPE_L4;
939 tpa_info->gso_type = SKB_GSO_TCPV4;
940 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
941 if (hash_type == 3)
942 tpa_info->gso_type = SKB_GSO_TCPV6;
943 tpa_info->rss_hash =
944 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
945 } else {
946 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
947 tpa_info->gso_type = 0;
948 if (netif_msg_rx_err(bp))
949 netdev_warn(bp->dev, "TPA packet without valid hash\n");
950 }
951 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
952 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
94758f8d 953 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
c0c050c5
MC		 954
955 rxr->rx_prod = NEXT_RX(prod);
956 cons = NEXT_RX(cons);
376a5b86 957 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 958 cons_rx_buf = &rxr->rx_buf_ring[cons];
959
960 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
961 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
962 cons_rx_buf->data = NULL;
963}
964
965static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
966 u16 cp_cons, u32 agg_bufs)
967{
968 if (agg_bufs)
969 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
970}
971
94758f8d
MC		 972static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
973 int payload_off, int tcp_ts,
974 struct sk_buff *skb)
975{
976#ifdef CONFIG_INET
977 struct tcphdr *th;
978 int len, nw_off;
979 u16 outer_ip_off, inner_ip_off, inner_mac_off;
980 u32 hdr_info = tpa_info->hdr_info;
981 bool loopback = false;
982
983 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
984 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
985 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
986
987 /* If the packet is an internal loopback packet, the offsets will
988 * have an extra 4 bytes.
989 */
990 if (inner_mac_off == 4) {
991 loopback = true;
992 } else if (inner_mac_off > 4) {
993 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
994 ETH_HLEN - 2));
995
996 /* We only support inner iPv4/ipv6. If we don't see the
997 * correct protocol ID, it must be a loopback packet where
998 * the offsets are off by 4.
999 */
1000 if (proto != htons(ETH_P_IP) && proto && htons(ETH_P_IPV6))
1001 loopback = true;
1002 }
1003 if (loopback) {
1004 /* internal loopback packet, subtract all offsets by 4 */
1005 inner_ip_off -= 4;
1006 inner_mac_off -= 4;
1007 outer_ip_off -= 4;
1008 }
1009
1010 nw_off = inner_ip_off - ETH_HLEN;
1011 skb_set_network_header(skb, nw_off);
1012 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1013 struct ipv6hdr *iph = ipv6_hdr(skb);
1014
1015 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1016 len = skb->len - skb_transport_offset(skb);
1017 th = tcp_hdr(skb);
1018 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1019 } else {
1020 struct iphdr *iph = ip_hdr(skb);
1021
1022 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1023 len = skb->len - skb_transport_offset(skb);
1024 th = tcp_hdr(skb);
1025 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1026 }
1027
1028 if (inner_mac_off) { /* tunnel */
1029 struct udphdr *uh = NULL;
1030 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1031 ETH_HLEN - 2));
1032
1033 if (proto == htons(ETH_P_IP)) {
1034 struct iphdr *iph = (struct iphdr *)skb->data;
1035
1036 if (iph->protocol == IPPROTO_UDP)
1037 uh = (struct udphdr *)(iph + 1);
1038 } else {
1039 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1040
1041 if (iph->nexthdr == IPPROTO_UDP)
1042 uh = (struct udphdr *)(iph + 1);
1043 }
1044 if (uh) {
1045 if (uh->check)
1046 skb_shinfo(skb)->gso_type |=
1047 SKB_GSO_UDP_TUNNEL_CSUM;
1048 else
1049 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1050 }
1051 }
1052#endif
1053 return skb;
1054}
1055
c0c050c5
MC		 1056#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1057#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1058
309369c9
MC		 1059static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1060 int payload_off, int tcp_ts,
c0c050c5
MC		 1061 struct sk_buff *skb)
1062{
d1611c3a 1063#ifdef CONFIG_INET
c0c050c5 1064 struct tcphdr *th;
309369c9 1065 int len, nw_off, tcp_opt_len;
27e24189 1066
309369c9 1067 if (tcp_ts)
c0c050c5
MC		 1068 tcp_opt_len = 12;
1069
c0c050c5
MC		 1070 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1071 struct iphdr *iph;
1072
1073 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1074 ETH_HLEN;
1075 skb_set_network_header(skb, nw_off);
1076 iph = ip_hdr(skb);
1077 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1078 len = skb->len - skb_transport_offset(skb);
1079 th = tcp_hdr(skb);
1080 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1081 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1082 struct ipv6hdr *iph;
1083
1084 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1085 ETH_HLEN;
1086 skb_set_network_header(skb, nw_off);
1087 iph = ipv6_hdr(skb);
1088 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1089 len = skb->len - skb_transport_offset(skb);
1090 th = tcp_hdr(skb);
1091 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1092 } else {
1093 dev_kfree_skb_any(skb);
1094 return NULL;
1095 }
1096 tcp_gro_complete(skb);
1097
1098 if (nw_off) { /* tunnel */
1099 struct udphdr *uh = NULL;
1100
1101 if (skb->protocol == htons(ETH_P_IP)) {
1102 struct iphdr *iph = (struct iphdr *)skb->data;
1103
1104 if (iph->protocol == IPPROTO_UDP)
1105 uh = (struct udphdr *)(iph + 1);
1106 } else {
1107 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1108
1109 if (iph->nexthdr == IPPROTO_UDP)
1110 uh = (struct udphdr *)(iph + 1);
1111 }
1112 if (uh) {
1113 if (uh->check)
1114 skb_shinfo(skb)->gso_type |=
1115 SKB_GSO_UDP_TUNNEL_CSUM;
1116 else
1117 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1118 }
1119 }
1120#endif
1121 return skb;
1122}
1123
309369c9
MC		 1124static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1125 struct bnxt_tpa_info *tpa_info,
1126 struct rx_tpa_end_cmp *tpa_end,
1127 struct rx_tpa_end_cmp_ext *tpa_end1,
1128 struct sk_buff *skb)
1129{
1130#ifdef CONFIG_INET
1131 int payload_off;
1132 u16 segs;
1133
1134 segs = TPA_END_TPA_SEGS(tpa_end);
1135 if (segs == 1)
1136 return skb;
1137
1138 NAPI_GRO_CB(skb)->count = segs;
1139 skb_shinfo(skb)->gso_size =
1140 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1141 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1142 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1143 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1144 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1145 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1146#endif
1147 return skb;
1148}
1149
c0c050c5
MC		 1150static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1151 struct bnxt_napi *bnapi,
1152 u32 *raw_cons,
1153 struct rx_tpa_end_cmp *tpa_end,
1154 struct rx_tpa_end_cmp_ext *tpa_end1,
1155 bool *agg_event)
1156{
1157 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1158 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1159 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1160 u8 *data, agg_bufs;
1161 u16 cp_cons = RING_CMP(*raw_cons);
1162 unsigned int len;
1163 struct bnxt_tpa_info *tpa_info;
1164 dma_addr_t mapping;
1165 struct sk_buff *skb;
1166
fa7e2812
MC		 1167 if (unlikely(bnapi->in_reset)) {
1168 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1169
1170 if (rc < 0)
1171 return ERR_PTR(-EBUSY);
1172 return NULL;
1173 }
1174
c0c050c5
MC		 1175 tpa_info = &rxr->rx_tpa[agg_id];
1176 data = tpa_info->data;
1177 prefetch(data);
1178 len = tpa_info->len;
1179 mapping = tpa_info->mapping;
1180
1181 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1182 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1183
1184 if (agg_bufs) {
1185 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1186 return ERR_PTR(-EBUSY);
1187
1188 *agg_event = true;
1189 cp_cons = NEXT_CMP(cp_cons);
1190 }
1191
1192 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1193 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1194 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1195 agg_bufs, (int)MAX_SKB_FRAGS);
1196 return NULL;
1197 }
1198
1199 if (len <= bp->rx_copy_thresh) {
1200 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1201 if (!skb) {
1202 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1203 return NULL;
1204 }
1205 } else {
1206 u8 *new_data;
1207 dma_addr_t new_mapping;
1208
1209 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1210 if (!new_data) {
1211 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1212 return NULL;
1213 }
1214
1215 tpa_info->data = new_data;
1216 tpa_info->mapping = new_mapping;
1217
1218 skb = build_skb(data, 0);
1219 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1220 PCI_DMA_FROMDEVICE);
1221
1222 if (!skb) {
1223 kfree(data);
1224 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1225 return NULL;
1226 }
1227 skb_reserve(skb, BNXT_RX_OFFSET);
1228 skb_put(skb, len);
1229 }
1230
1231 if (agg_bufs) {
1232 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1233 if (!skb) {
1234 /* Page reuse already handled by bnxt_rx_pages(). */
1235 return NULL;
1236 }
1237 }
1238 skb->protocol = eth_type_trans(skb, bp->dev);
1239
1240 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1241 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1242
8852ddb4
MC		 1243 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1244 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5
MC		 1245 u16 vlan_proto = tpa_info->metadata >>
1246 RX_CMP_FLAGS2_METADATA_TPID_SFT;
8852ddb4 1247 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5 1248
8852ddb4 1249 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1250 }
1251
1252 skb_checksum_none_assert(skb);
1253 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1254 skb->ip_summed = CHECKSUM_UNNECESSARY;
1255 skb->csum_level =
1256 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1257 }
1258
1259 if (TPA_END_GRO(tpa_end))
309369c9 1260 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
c0c050c5
MC		 1261
1262 return skb;
1263}
1264
1265/* returns the following:
1266 * 1 - 1 packet successfully received
1267 * 0 - successful TPA_START, packet not completed yet
1268 * -EBUSY - completion ring does not have all the agg buffers yet
1269 * -ENOMEM - packet aborted due to out of memory
1270 * -EIO - packet aborted due to hw error indicated in BD
1271 */
1272static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1273 bool *agg_event)
1274{
1275 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1276 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1277 struct net_device *dev = bp->dev;
1278 struct rx_cmp *rxcmp;
1279 struct rx_cmp_ext *rxcmp1;
1280 u32 tmp_raw_cons = *raw_cons;
1281 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1282 struct bnxt_sw_rx_bd *rx_buf;
1283 unsigned int len;
1284 u8 *data, agg_bufs, cmp_type;
1285 dma_addr_t dma_addr;
1286 struct sk_buff *skb;
1287 int rc = 0;
1288
1289 rxcmp = (struct rx_cmp *)
1290 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1291
1292 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1293 cp_cons = RING_CMP(tmp_raw_cons);
1294 rxcmp1 = (struct rx_cmp_ext *)
1295 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1296
1297 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1298 return -EBUSY;
1299
1300 cmp_type = RX_CMP_TYPE(rxcmp);
1301
1302 prod = rxr->rx_prod;
1303
1304 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1305 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1306 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1307
1308 goto next_rx_no_prod;
1309
1310 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1311 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1312 (struct rx_tpa_end_cmp *)rxcmp,
1313 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1314 agg_event);
1315
1316 if (unlikely(IS_ERR(skb)))
1317 return -EBUSY;
1318
1319 rc = -ENOMEM;
1320 if (likely(skb)) {
1321 skb_record_rx_queue(skb, bnapi->index);
1322 skb_mark_napi_id(skb, &bnapi->napi);
1323 if (bnxt_busy_polling(bnapi))
1324 netif_receive_skb(skb);
1325 else
1326 napi_gro_receive(&bnapi->napi, skb);
1327 rc = 1;
1328 }
1329 goto next_rx_no_prod;
1330 }
1331
1332 cons = rxcmp->rx_cmp_opaque;
1333 rx_buf = &rxr->rx_buf_ring[cons];
1334 data = rx_buf->data;
fa7e2812
MC		 1335 if (unlikely(cons != rxr->rx_next_cons)) {
1336 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1337
1338 bnxt_sched_reset(bp, rxr);
1339 return rc1;
1340 }
c0c050c5
MC		 1341 prefetch(data);
1342
1343 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1344 RX_CMP_AGG_BUFS_SHIFT;
1345
1346 if (agg_bufs) {
1347 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1348 return -EBUSY;
1349
1350 cp_cons = NEXT_CMP(cp_cons);
1351 *agg_event = true;
1352 }
1353
1354 rx_buf->data = NULL;
1355 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1356 bnxt_reuse_rx_data(rxr, cons, data);
1357 if (agg_bufs)
1358 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1359
1360 rc = -EIO;
1361 goto next_rx;
1362 }
1363
1364 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1365 dma_addr = dma_unmap_addr(rx_buf, mapping);
1366
1367 if (len <= bp->rx_copy_thresh) {
1368 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1369 bnxt_reuse_rx_data(rxr, cons, data);
1370 if (!skb) {
1371 rc = -ENOMEM;
1372 goto next_rx;
1373 }
1374 } else {
1375 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1376 if (!skb) {
1377 rc = -ENOMEM;
1378 goto next_rx;
1379 }
1380 }
1381
1382 if (agg_bufs) {
1383 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1384 if (!skb) {
1385 rc = -ENOMEM;
1386 goto next_rx;
1387 }
1388 }
1389
1390 if (RX_CMP_HASH_VALID(rxcmp)) {
1391 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1392 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1393
1394 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1395 if (hash_type != 1 && hash_type != 3)
1396 type = PKT_HASH_TYPE_L3;
1397 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1398 }
1399
1400 skb->protocol = eth_type_trans(skb, dev);
1401
8852ddb4
MC		 1402 if ((rxcmp1->rx_cmp_flags2 &
1403 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1404 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5 1405 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
8852ddb4 1406 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5
MC		 1407 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1408
8852ddb4 1409 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1410 }
1411
1412 skb_checksum_none_assert(skb);
1413 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1414 if (dev->features & NETIF_F_RXCSUM) {
1415 skb->ip_summed = CHECKSUM_UNNECESSARY;
1416 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1417 }
1418 } else {
665e350d
SB		 1419 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1420 if (dev->features & NETIF_F_RXCSUM)
1421 cpr->rx_l4_csum_errors++;
1422 }
c0c050c5
MC		 1423 }
1424
1425 skb_record_rx_queue(skb, bnapi->index);
1426 skb_mark_napi_id(skb, &bnapi->napi);
1427 if (bnxt_busy_polling(bnapi))
1428 netif_receive_skb(skb);
1429 else
1430 napi_gro_receive(&bnapi->napi, skb);
1431 rc = 1;
1432
1433next_rx:
1434 rxr->rx_prod = NEXT_RX(prod);
376a5b86 1435 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1436
1437next_rx_no_prod:
1438 *raw_cons = tmp_raw_cons;
1439
1440 return rc;
1441}
1442
4bb13abf
MC		 1443#define BNXT_GET_EVENT_PORT(data) \
1444 ((data) & \
1445 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1446
c0c050c5
MC		 1447static int bnxt_async_event_process(struct bnxt *bp,
1448 struct hwrm_async_event_cmpl *cmpl)
1449{
1450 u16 event_id = le16_to_cpu(cmpl->event_id);
1451
1452 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1453 switch (event_id) {
8cbde117
MC		 1454 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1455 u32 data1 = le32_to_cpu(cmpl->event_data1);
1456 struct bnxt_link_info *link_info = &bp->link_info;
1457
1458 if (BNXT_VF(bp))
1459 goto async_event_process_exit;
1460 if (data1 & 0x20000) {
1461 u16 fw_speed = link_info->force_link_speed;
1462 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1463
1464 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1465 speed);
1466 }
1467 /* fall thru */
1468 }
c0c050c5
MC		 1469 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1470 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368
JH		 1471 break;
1472 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1473 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5 1474 break;
4bb13abf
MC		 1475 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1476 u32 data1 = le32_to_cpu(cmpl->event_data1);
1477 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1478
1479 if (BNXT_VF(bp))
1480 break;
1481
1482 if (bp->pf.port_id != port_id)
1483 break;
1484
4bb13abf
MC		 1485 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1486 break;
1487 }
fc0f1929
MC		 1488 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1489 if (BNXT_PF(bp))
1490 goto async_event_process_exit;
1491 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1492 break;
c0c050c5
MC		 1493 default:
1494 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1495 event_id);
19241368 1496 goto async_event_process_exit;
c0c050c5 1497 }
19241368
JH		 1498 schedule_work(&bp->sp_task);
1499async_event_process_exit:
c0c050c5
MC		 1500 return 0;
1501}
1502
1503static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1504{
1505 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1506 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1507 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1508 (struct hwrm_fwd_req_cmpl *)txcmp;
1509
1510 switch (cmpl_type) {
1511 case CMPL_BASE_TYPE_HWRM_DONE:
1512 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1513 if (seq_id == bp->hwrm_intr_seq_id)
1514 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1515 else
1516 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1517 break;
1518
1519 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1520 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1521
1522 if ((vf_id < bp->pf.first_vf_id) ||
1523 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1524 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1525 vf_id);
1526 return -EINVAL;
1527 }
1528
1529 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1530 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1531 schedule_work(&bp->sp_task);
1532 break;
1533
1534 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1535 bnxt_async_event_process(bp,
1536 (struct hwrm_async_event_cmpl *)txcmp);
1537
1538 default:
1539 break;
1540 }
1541
1542 return 0;
1543}
1544
1545static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1546{
1547 struct bnxt_napi *bnapi = dev_instance;
1548 struct bnxt *bp = bnapi->bp;
1549 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1550 u32 cons = RING_CMP(cpr->cp_raw_cons);
1551
1552 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1553 napi_schedule(&bnapi->napi);
1554 return IRQ_HANDLED;
1555}
1556
1557static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1558{
1559 u32 raw_cons = cpr->cp_raw_cons;
1560 u16 cons = RING_CMP(raw_cons);
1561 struct tx_cmp *txcmp;
1562
1563 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1564
1565 return TX_CMP_VALID(txcmp, raw_cons);
1566}
1567
c0c050c5
MC		 1568static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1569{
1570 struct bnxt_napi *bnapi = dev_instance;
1571 struct bnxt *bp = bnapi->bp;
1572 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1573 u32 cons = RING_CMP(cpr->cp_raw_cons);
1574 u32 int_status;
1575
1576 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1577
1578 if (!bnxt_has_work(bp, cpr)) {
11809490 1579 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1580 /* return if erroneous interrupt */
1581 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1582 return IRQ_NONE;
1583 }
1584
1585 /* disable ring IRQ */
1586 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1587
1588 /* Return here if interrupt is shared and is disabled. */
1589 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1590 return IRQ_HANDLED;
1591
1592 napi_schedule(&bnapi->napi);
1593 return IRQ_HANDLED;
1594}
1595
1596static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1597{
1598 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1599 u32 raw_cons = cpr->cp_raw_cons;
1600 u32 cons;
1601 int tx_pkts = 0;
1602 int rx_pkts = 0;
1603 bool rx_event = false;
1604 bool agg_event = false;
1605 struct tx_cmp *txcmp;
1606
1607 while (1) {
1608 int rc;
1609
1610 cons = RING_CMP(raw_cons);
1611 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1612
1613 if (!TX_CMP_VALID(txcmp, raw_cons))
1614 break;
1615
67a95e20
MC		 1616 /* The valid test of the entry must be done first before
1617 * reading any further.
1618 */
b67daab0 1619 dma_rmb();
c0c050c5
MC		 1620 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1621 tx_pkts++;
1622 /* return full budget so NAPI will complete. */
1623 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1624 rx_pkts = budget;
1625 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1626 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1627 if (likely(rc >= 0))
1628 rx_pkts += rc;
1629 else if (rc == -EBUSY) /* partial completion */
1630 break;
1631 rx_event = true;
1632 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1633 CMPL_BASE_TYPE_HWRM_DONE) ||
1634 (TX_CMP_TYPE(txcmp) ==
1635 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1636 (TX_CMP_TYPE(txcmp) ==
1637 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1638 bnxt_hwrm_handler(bp, txcmp);
1639 }
1640 raw_cons = NEXT_RAW_CMP(raw_cons);
1641
1642 if (rx_pkts == budget)
1643 break;
1644 }
1645
1646 cpr->cp_raw_cons = raw_cons;
1647 /* ACK completion ring before freeing tx ring and producing new
1648 * buffers in rx/agg rings to prevent overflowing the completion
1649 * ring.
1650 */
1651 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1652
1653 if (tx_pkts)
1654 bnxt_tx_int(bp, bnapi, tx_pkts);
1655
1656 if (rx_event) {
b6ab4b01 1657 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1658
1659 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1660 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1661 if (agg_event) {
1662 writel(DB_KEY_RX | rxr->rx_agg_prod,
1663 rxr->rx_agg_doorbell);
1664 writel(DB_KEY_RX | rxr->rx_agg_prod,
1665 rxr->rx_agg_doorbell);
1666 }
1667 }
1668 return rx_pkts;
1669}
1670
1671static int bnxt_poll(struct napi_struct *napi, int budget)
1672{
1673 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1674 struct bnxt *bp = bnapi->bp;
1675 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1676 int work_done = 0;
1677
1678 if (!bnxt_lock_napi(bnapi))
1679 return budget;
1680
1681 while (1) {
1682 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1683
1684 if (work_done >= budget)
1685 break;
1686
1687 if (!bnxt_has_work(bp, cpr)) {
1688 napi_complete(napi);
1689 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1690 break;
1691 }
1692 }
1693 mmiowb();
1694 bnxt_unlock_napi(bnapi);
1695 return work_done;
1696}
1697
1698#ifdef CONFIG_NET_RX_BUSY_POLL
1699static int bnxt_busy_poll(struct napi_struct *napi)
1700{
1701 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1702 struct bnxt *bp = bnapi->bp;
1703 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1704 int rx_work, budget = 4;
1705
1706 if (atomic_read(&bp->intr_sem) != 0)
1707 return LL_FLUSH_FAILED;
1708
1709 if (!bnxt_lock_poll(bnapi))
1710 return LL_FLUSH_BUSY;
1711
1712 rx_work = bnxt_poll_work(bp, bnapi, budget);
1713
1714 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1715
1716 bnxt_unlock_poll(bnapi);
1717 return rx_work;
1718}
1719#endif
1720
1721static void bnxt_free_tx_skbs(struct bnxt *bp)
1722{
1723 int i, max_idx;
1724 struct pci_dev *pdev = bp->pdev;
1725
b6ab4b01 1726 if (!bp->tx_ring)
c0c050c5
MC		 1727 return;
1728
1729 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1730 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1731 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1732 int j;
1733
c0c050c5
MC		 1734 for (j = 0; j < max_idx;) {
1735 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1736 struct sk_buff *skb = tx_buf->skb;
1737 int k, last;
1738
1739 if (!skb) {
1740 j++;
1741 continue;
1742 }
1743
1744 tx_buf->skb = NULL;
1745
1746 if (tx_buf->is_push) {
1747 dev_kfree_skb(skb);
1748 j += 2;
1749 continue;
1750 }
1751
1752 dma_unmap_single(&pdev->dev,
1753 dma_unmap_addr(tx_buf, mapping),
1754 skb_headlen(skb),
1755 PCI_DMA_TODEVICE);
1756
1757 last = tx_buf->nr_frags;
1758 j += 2;
d612a579
MC		 1759 for (k = 0; k < last; k++, j++) {
1760 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 1761 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1762
d612a579 1763 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 1764 dma_unmap_page(
1765 &pdev->dev,
1766 dma_unmap_addr(tx_buf, mapping),
1767 skb_frag_size(frag), PCI_DMA_TODEVICE);
1768 }
1769 dev_kfree_skb(skb);
1770 }
1771 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1772 }
1773}
1774
1775static void bnxt_free_rx_skbs(struct bnxt *bp)
1776{
1777 int i, max_idx, max_agg_idx;
1778 struct pci_dev *pdev = bp->pdev;
1779
b6ab4b01 1780 if (!bp->rx_ring)
c0c050c5
MC		 1781 return;
1782
1783 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1784 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1785 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1786 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1787 int j;
1788
c0c050c5
MC		 1789 if (rxr->rx_tpa) {
1790 for (j = 0; j < MAX_TPA; j++) {
1791 struct bnxt_tpa_info *tpa_info =
1792 &rxr->rx_tpa[j];
1793 u8 *data = tpa_info->data;
1794
1795 if (!data)
1796 continue;
1797
1798 dma_unmap_single(
1799 &pdev->dev,
1800 dma_unmap_addr(tpa_info, mapping),
1801 bp->rx_buf_use_size,
1802 PCI_DMA_FROMDEVICE);
1803
1804 tpa_info->data = NULL;
1805
1806 kfree(data);
1807 }
1808 }
1809
1810 for (j = 0; j < max_idx; j++) {
1811 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1812 u8 *data = rx_buf->data;
1813
1814 if (!data)
1815 continue;
1816
1817 dma_unmap_single(&pdev->dev,
1818 dma_unmap_addr(rx_buf, mapping),
1819 bp->rx_buf_use_size,
1820 PCI_DMA_FROMDEVICE);
1821
1822 rx_buf->data = NULL;
1823
1824 kfree(data);
1825 }
1826
1827 for (j = 0; j < max_agg_idx; j++) {
1828 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1829 &rxr->rx_agg_ring[j];
1830 struct page *page = rx_agg_buf->page;
1831
1832 if (!page)
1833 continue;
1834
1835 dma_unmap_page(&pdev->dev,
1836 dma_unmap_addr(rx_agg_buf, mapping),
2839f28b 1837 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
c0c050c5
MC		 1838
1839 rx_agg_buf->page = NULL;
1840 __clear_bit(j, rxr->rx_agg_bmap);
1841
1842 __free_page(page);
1843 }
89d0a06c
MC		 1844 if (rxr->rx_page) {
1845 __free_page(rxr->rx_page);
1846 rxr->rx_page = NULL;
1847 }
c0c050c5
MC		 1848 }
1849}
1850
1851static void bnxt_free_skbs(struct bnxt *bp)
1852{
1853 bnxt_free_tx_skbs(bp);
1854 bnxt_free_rx_skbs(bp);
1855}
1856
1857static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1858{
1859 struct pci_dev *pdev = bp->pdev;
1860 int i;
1861
1862 for (i = 0; i < ring->nr_pages; i++) {
1863 if (!ring->pg_arr[i])
1864 continue;
1865
1866 dma_free_coherent(&pdev->dev, ring->page_size,
1867 ring->pg_arr[i], ring->dma_arr[i]);
1868
1869 ring->pg_arr[i] = NULL;
1870 }
1871 if (ring->pg_tbl) {
1872 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1873 ring->pg_tbl, ring->pg_tbl_map);
1874 ring->pg_tbl = NULL;
1875 }
1876 if (ring->vmem_size && *ring->vmem) {
1877 vfree(*ring->vmem);
1878 *ring->vmem = NULL;
1879 }
1880}
1881
1882static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1883{
1884 int i;
1885 struct pci_dev *pdev = bp->pdev;
1886
1887 if (ring->nr_pages > 1) {
1888 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1889 ring->nr_pages * 8,
1890 &ring->pg_tbl_map,
1891 GFP_KERNEL);
1892 if (!ring->pg_tbl)
1893 return -ENOMEM;
1894 }
1895
1896 for (i = 0; i < ring->nr_pages; i++) {
1897 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1898 ring->page_size,
1899 &ring->dma_arr[i],
1900 GFP_KERNEL);
1901 if (!ring->pg_arr[i])
1902 return -ENOMEM;
1903
1904 if (ring->nr_pages > 1)
1905 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1906 }
1907
1908 if (ring->vmem_size) {
1909 *ring->vmem = vzalloc(ring->vmem_size);
1910 if (!(*ring->vmem))
1911 return -ENOMEM;
1912 }
1913 return 0;
1914}
1915
1916static void bnxt_free_rx_rings(struct bnxt *bp)
1917{
1918 int i;
1919
b6ab4b01 1920 if (!bp->rx_ring)
c0c050c5
MC		 1921 return;
1922
1923 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1924 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1925 struct bnxt_ring_struct *ring;
1926
c0c050c5
MC		 1927 kfree(rxr->rx_tpa);
1928 rxr->rx_tpa = NULL;
1929
1930 kfree(rxr->rx_agg_bmap);
1931 rxr->rx_agg_bmap = NULL;
1932
1933 ring = &rxr->rx_ring_struct;
1934 bnxt_free_ring(bp, ring);
1935
1936 ring = &rxr->rx_agg_ring_struct;
1937 bnxt_free_ring(bp, ring);
1938 }
1939}
1940
1941static int bnxt_alloc_rx_rings(struct bnxt *bp)
1942{
1943 int i, rc, agg_rings = 0, tpa_rings = 0;
1944
b6ab4b01
MC		 1945 if (!bp->rx_ring)
1946 return -ENOMEM;
1947
c0c050c5
MC		 1948 if (bp->flags & BNXT_FLAG_AGG_RINGS)
1949 agg_rings = 1;
1950
1951 if (bp->flags & BNXT_FLAG_TPA)
1952 tpa_rings = 1;
1953
1954 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1955 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1956 struct bnxt_ring_struct *ring;
1957
c0c050c5
MC		 1958 ring = &rxr->rx_ring_struct;
1959
1960 rc = bnxt_alloc_ring(bp, ring);
1961 if (rc)
1962 return rc;
1963
1964 if (agg_rings) {
1965 u16 mem_size;
1966
1967 ring = &rxr->rx_agg_ring_struct;
1968 rc = bnxt_alloc_ring(bp, ring);
1969 if (rc)
1970 return rc;
1971
1972 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1973 mem_size = rxr->rx_agg_bmap_size / 8;
1974 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1975 if (!rxr->rx_agg_bmap)
1976 return -ENOMEM;
1977
1978 if (tpa_rings) {
1979 rxr->rx_tpa = kcalloc(MAX_TPA,
1980 sizeof(struct bnxt_tpa_info),
1981 GFP_KERNEL);
1982 if (!rxr->rx_tpa)
1983 return -ENOMEM;
1984 }
1985 }
1986 }
1987 return 0;
1988}
1989
1990static void bnxt_free_tx_rings(struct bnxt *bp)
1991{
1992 int i;
1993 struct pci_dev *pdev = bp->pdev;
1994
b6ab4b01 1995 if (!bp->tx_ring)
c0c050c5
MC		 1996 return;
1997
1998 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1999 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2000 struct bnxt_ring_struct *ring;
2001
c0c050c5
MC		 2002 if (txr->tx_push) {
2003 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2004 txr->tx_push, txr->tx_push_mapping);
2005 txr->tx_push = NULL;
2006 }
2007
2008 ring = &txr->tx_ring_struct;
2009
2010 bnxt_free_ring(bp, ring);
2011 }
2012}
2013
2014static int bnxt_alloc_tx_rings(struct bnxt *bp)
2015{
2016 int i, j, rc;
2017 struct pci_dev *pdev = bp->pdev;
2018
2019 bp->tx_push_size = 0;
2020 if (bp->tx_push_thresh) {
2021 int push_size;
2022
2023 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2024 bp->tx_push_thresh);
2025
4419dbe6 2026 if (push_size > 256) {
c0c050c5
MC		 2027 push_size = 0;
2028 bp->tx_push_thresh = 0;
2029 }
2030
2031 bp->tx_push_size = push_size;
2032 }
2033
2034 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2035 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2036 struct bnxt_ring_struct *ring;
2037
c0c050c5
MC		 2038 ring = &txr->tx_ring_struct;
2039
2040 rc = bnxt_alloc_ring(bp, ring);
2041 if (rc)
2042 return rc;
2043
2044 if (bp->tx_push_size) {
c0c050c5
MC		 2045 dma_addr_t mapping;
2046
2047 /* One pre-allocated DMA buffer to backup
2048 * TX push operation
2049 */
2050 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2051 bp->tx_push_size,
2052 &txr->tx_push_mapping,
2053 GFP_KERNEL);
2054
2055 if (!txr->tx_push)
2056 return -ENOMEM;
2057
c0c050c5
MC		 2058 mapping = txr->tx_push_mapping +
2059 sizeof(struct tx_push_bd);
4419dbe6 2060 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 2061
4419dbe6 2062 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5
MC		 2063 }
2064 ring->queue_id = bp->q_info[j].queue_id;
2065 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2066 j++;
2067 }
2068 return 0;
2069}
2070
2071static void bnxt_free_cp_rings(struct bnxt *bp)
2072{
2073 int i;
2074
2075 if (!bp->bnapi)
2076 return;
2077
2078 for (i = 0; i < bp->cp_nr_rings; i++) {
2079 struct bnxt_napi *bnapi = bp->bnapi[i];
2080 struct bnxt_cp_ring_info *cpr;
2081 struct bnxt_ring_struct *ring;
2082
2083 if (!bnapi)
2084 continue;
2085
2086 cpr = &bnapi->cp_ring;
2087 ring = &cpr->cp_ring_struct;
2088
2089 bnxt_free_ring(bp, ring);
2090 }
2091}
2092
2093static int bnxt_alloc_cp_rings(struct bnxt *bp)
2094{
2095 int i, rc;
2096
2097 for (i = 0; i < bp->cp_nr_rings; i++) {
2098 struct bnxt_napi *bnapi = bp->bnapi[i];
2099 struct bnxt_cp_ring_info *cpr;
2100 struct bnxt_ring_struct *ring;
2101
2102 if (!bnapi)
2103 continue;
2104
2105 cpr = &bnapi->cp_ring;
2106 ring = &cpr->cp_ring_struct;
2107
2108 rc = bnxt_alloc_ring(bp, ring);
2109 if (rc)
2110 return rc;
2111 }
2112 return 0;
2113}
2114
2115static void bnxt_init_ring_struct(struct bnxt *bp)
2116{
2117 int i;
2118
2119 for (i = 0; i < bp->cp_nr_rings; i++) {
2120 struct bnxt_napi *bnapi = bp->bnapi[i];
2121 struct bnxt_cp_ring_info *cpr;
2122 struct bnxt_rx_ring_info *rxr;
2123 struct bnxt_tx_ring_info *txr;
2124 struct bnxt_ring_struct *ring;
2125
2126 if (!bnapi)
2127 continue;
2128
2129 cpr = &bnapi->cp_ring;
2130 ring = &cpr->cp_ring_struct;
2131 ring->nr_pages = bp->cp_nr_pages;
2132 ring->page_size = HW_CMPD_RING_SIZE;
2133 ring->pg_arr = (void **)cpr->cp_desc_ring;
2134 ring->dma_arr = cpr->cp_desc_mapping;
2135 ring->vmem_size = 0;
2136
b6ab4b01 2137 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2138 if (!rxr)
2139 goto skip_rx;
2140
c0c050c5
MC		 2141 ring = &rxr->rx_ring_struct;
2142 ring->nr_pages = bp->rx_nr_pages;
2143 ring->page_size = HW_RXBD_RING_SIZE;
2144 ring->pg_arr = (void **)rxr->rx_desc_ring;
2145 ring->dma_arr = rxr->rx_desc_mapping;
2146 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2147 ring->vmem = (void **)&rxr->rx_buf_ring;
2148
2149 ring = &rxr->rx_agg_ring_struct;
2150 ring->nr_pages = bp->rx_agg_nr_pages;
2151 ring->page_size = HW_RXBD_RING_SIZE;
2152 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2153 ring->dma_arr = rxr->rx_agg_desc_mapping;
2154 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2155 ring->vmem = (void **)&rxr->rx_agg_ring;
2156
3b2b7d9d 2157skip_rx:
b6ab4b01 2158 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2159 if (!txr)
2160 continue;
2161
c0c050c5
MC		 2162 ring = &txr->tx_ring_struct;
2163 ring->nr_pages = bp->tx_nr_pages;
2164 ring->page_size = HW_RXBD_RING_SIZE;
2165 ring->pg_arr = (void **)txr->tx_desc_ring;
2166 ring->dma_arr = txr->tx_desc_mapping;
2167 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2168 ring->vmem = (void **)&txr->tx_buf_ring;
2169 }
2170}
2171
2172static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2173{
2174 int i;
2175 u32 prod;
2176 struct rx_bd **rx_buf_ring;
2177
2178 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2179 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2180 int j;
2181 struct rx_bd *rxbd;
2182
2183 rxbd = rx_buf_ring[i];
2184 if (!rxbd)
2185 continue;
2186
2187 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2188 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2189 rxbd->rx_bd_opaque = prod;
2190 }
2191 }
2192}
2193
2194static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2195{
2196 struct net_device *dev = bp->dev;
c0c050c5
MC		 2197 struct bnxt_rx_ring_info *rxr;
2198 struct bnxt_ring_struct *ring;
2199 u32 prod, type;
2200 int i;
2201
c0c050c5
MC		 2202 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2203 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2204
2205 if (NET_IP_ALIGN == 2)
2206 type |= RX_BD_FLAGS_SOP;
2207
b6ab4b01 2208 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 2209 ring = &rxr->rx_ring_struct;
2210 bnxt_init_rxbd_pages(ring, type);
2211
2212 prod = rxr->rx_prod;
2213 for (i = 0; i < bp->rx_ring_size; i++) {
2214 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2215 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2216 ring_nr, i, bp->rx_ring_size);
2217 break;
2218 }
2219 prod = NEXT_RX(prod);
2220 }
2221 rxr->rx_prod = prod;
2222 ring->fw_ring_id = INVALID_HW_RING_ID;
2223
edd0c2cc
MC		 2224 ring = &rxr->rx_agg_ring_struct;
2225 ring->fw_ring_id = INVALID_HW_RING_ID;
2226
c0c050c5
MC		 2227 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2228 return 0;
2229
2839f28b 2230 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
c0c050c5
MC		 2231 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2232
2233 bnxt_init_rxbd_pages(ring, type);
2234
2235 prod = rxr->rx_agg_prod;
2236 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2237 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2238 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2239 ring_nr, i, bp->rx_ring_size);
2240 break;
2241 }
2242 prod = NEXT_RX_AGG(prod);
2243 }
2244 rxr->rx_agg_prod = prod;
c0c050c5
MC		 2245
2246 if (bp->flags & BNXT_FLAG_TPA) {
2247 if (rxr->rx_tpa) {
2248 u8 *data;
2249 dma_addr_t mapping;
2250
2251 for (i = 0; i < MAX_TPA; i++) {
2252 data = __bnxt_alloc_rx_data(bp, &mapping,
2253 GFP_KERNEL);
2254 if (!data)
2255 return -ENOMEM;
2256
2257 rxr->rx_tpa[i].data = data;
2258 rxr->rx_tpa[i].mapping = mapping;
2259 }
2260 } else {
2261 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2262 return -ENOMEM;
2263 }
2264 }
2265
2266 return 0;
2267}
2268
2269static int bnxt_init_rx_rings(struct bnxt *bp)
2270{
2271 int i, rc = 0;
2272
2273 for (i = 0; i < bp->rx_nr_rings; i++) {
2274 rc = bnxt_init_one_rx_ring(bp, i);
2275 if (rc)
2276 break;
2277 }
2278
2279 return rc;
2280}
2281
2282static int bnxt_init_tx_rings(struct bnxt *bp)
2283{
2284 u16 i;
2285
2286 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2287 MAX_SKB_FRAGS + 1);
2288
2289 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2290 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2291 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2292
2293 ring->fw_ring_id = INVALID_HW_RING_ID;
2294 }
2295
2296 return 0;
2297}
2298
2299static void bnxt_free_ring_grps(struct bnxt *bp)
2300{
2301 kfree(bp->grp_info);
2302 bp->grp_info = NULL;
2303}
2304
2305static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2306{
2307 int i;
2308
2309 if (irq_re_init) {
2310 bp->grp_info = kcalloc(bp->cp_nr_rings,
2311 sizeof(struct bnxt_ring_grp_info),
2312 GFP_KERNEL);
2313 if (!bp->grp_info)
2314 return -ENOMEM;
2315 }
2316 for (i = 0; i < bp->cp_nr_rings; i++) {
2317 if (irq_re_init)
2318 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2319 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2320 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2321 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2322 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2323 }
2324 return 0;
2325}
2326
2327static void bnxt_free_vnics(struct bnxt *bp)
2328{
2329 kfree(bp->vnic_info);
2330 bp->vnic_info = NULL;
2331 bp->nr_vnics = 0;
2332}
2333
2334static int bnxt_alloc_vnics(struct bnxt *bp)
2335{
2336 int num_vnics = 1;
2337
2338#ifdef CONFIG_RFS_ACCEL
2339 if (bp->flags & BNXT_FLAG_RFS)
2340 num_vnics += bp->rx_nr_rings;
2341#endif
2342
2343 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2344 GFP_KERNEL);
2345 if (!bp->vnic_info)
2346 return -ENOMEM;
2347
2348 bp->nr_vnics = num_vnics;
2349 return 0;
2350}
2351
2352static void bnxt_init_vnics(struct bnxt *bp)
2353{
2354 int i;
2355
2356 for (i = 0; i < bp->nr_vnics; i++) {
2357 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2358
2359 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2360 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2361 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2362
2363 if (bp->vnic_info[i].rss_hash_key) {
2364 if (i == 0)
2365 prandom_bytes(vnic->rss_hash_key,
2366 HW_HASH_KEY_SIZE);
2367 else
2368 memcpy(vnic->rss_hash_key,
2369 bp->vnic_info[0].rss_hash_key,
2370 HW_HASH_KEY_SIZE);
2371 }
2372 }
2373}
2374
2375static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2376{
2377 int pages;
2378
2379 pages = ring_size / desc_per_pg;
2380
2381 if (!pages)
2382 return 1;
2383
2384 pages++;
2385
2386 while (pages & (pages - 1))
2387 pages++;
2388
2389 return pages;
2390}
2391
2392static void bnxt_set_tpa_flags(struct bnxt *bp)
2393{
2394 bp->flags &= ~BNXT_FLAG_TPA;
2395 if (bp->dev->features & NETIF_F_LRO)
2396 bp->flags |= BNXT_FLAG_LRO;
94758f8d 2397 if (bp->dev->features & NETIF_F_GRO)
c0c050c5
MC		 2398 bp->flags |= BNXT_FLAG_GRO;
2399}
2400
2401/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2402 * be set on entry.
2403 */
2404void bnxt_set_ring_params(struct bnxt *bp)
2405{
2406 u32 ring_size, rx_size, rx_space;
2407 u32 agg_factor = 0, agg_ring_size = 0;
2408
2409 /* 8 for CRC and VLAN */
2410 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2411
2412 rx_space = rx_size + NET_SKB_PAD +
2413 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2414
2415 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2416 ring_size = bp->rx_ring_size;
2417 bp->rx_agg_ring_size = 0;
2418 bp->rx_agg_nr_pages = 0;
2419
2420 if (bp->flags & BNXT_FLAG_TPA)
2839f28b 2421 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
c0c050c5
MC		 2422
2423 bp->flags &= ~BNXT_FLAG_JUMBO;
2424 if (rx_space > PAGE_SIZE) {
2425 u32 jumbo_factor;
2426
2427 bp->flags |= BNXT_FLAG_JUMBO;
2428 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2429 if (jumbo_factor > agg_factor)
2430 agg_factor = jumbo_factor;
2431 }
2432 agg_ring_size = ring_size * agg_factor;
2433
2434 if (agg_ring_size) {
2435 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2436 RX_DESC_CNT);
2437 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2438 u32 tmp = agg_ring_size;
2439
2440 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2441 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2442 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2443 tmp, agg_ring_size);
2444 }
2445 bp->rx_agg_ring_size = agg_ring_size;
2446 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2447 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2448 rx_space = rx_size + NET_SKB_PAD +
2449 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2450 }
2451
2452 bp->rx_buf_use_size = rx_size;
2453 bp->rx_buf_size = rx_space;
2454
2455 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2456 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2457
2458 ring_size = bp->tx_ring_size;
2459 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2460 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2461
2462 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2463 bp->cp_ring_size = ring_size;
2464
2465 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2466 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2467 bp->cp_nr_pages = MAX_CP_PAGES;
2468 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2469 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2470 ring_size, bp->cp_ring_size);
2471 }
2472 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2473 bp->cp_ring_mask = bp->cp_bit - 1;
2474}
2475
2476static void bnxt_free_vnic_attributes(struct bnxt *bp)
2477{
2478 int i;
2479 struct bnxt_vnic_info *vnic;
2480 struct pci_dev *pdev = bp->pdev;
2481
2482 if (!bp->vnic_info)
2483 return;
2484
2485 for (i = 0; i < bp->nr_vnics; i++) {
2486 vnic = &bp->vnic_info[i];
2487
2488 kfree(vnic->fw_grp_ids);
2489 vnic->fw_grp_ids = NULL;
2490
2491 kfree(vnic->uc_list);
2492 vnic->uc_list = NULL;
2493
2494 if (vnic->mc_list) {
2495 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2496 vnic->mc_list, vnic->mc_list_mapping);
2497 vnic->mc_list = NULL;
2498 }
2499
2500 if (vnic->rss_table) {
2501 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2502 vnic->rss_table,
2503 vnic->rss_table_dma_addr);
2504 vnic->rss_table = NULL;
2505 }
2506
2507 vnic->rss_hash_key = NULL;
2508 vnic->flags = 0;
2509 }
2510}
2511
2512static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2513{
2514 int i, rc = 0, size;
2515 struct bnxt_vnic_info *vnic;
2516 struct pci_dev *pdev = bp->pdev;
2517 int max_rings;
2518
2519 for (i = 0; i < bp->nr_vnics; i++) {
2520 vnic = &bp->vnic_info[i];
2521
2522 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2523 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2524
2525 if (mem_size > 0) {
2526 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2527 if (!vnic->uc_list) {
2528 rc = -ENOMEM;
2529 goto out;
2530 }
2531 }
2532 }
2533
2534 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2535 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2536 vnic->mc_list =
2537 dma_alloc_coherent(&pdev->dev,
2538 vnic->mc_list_size,
2539 &vnic->mc_list_mapping,
2540 GFP_KERNEL);
2541 if (!vnic->mc_list) {
2542 rc = -ENOMEM;
2543 goto out;
2544 }
2545 }
2546
2547 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2548 max_rings = bp->rx_nr_rings;
2549 else
2550 max_rings = 1;
2551
2552 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2553 if (!vnic->fw_grp_ids) {
2554 rc = -ENOMEM;
2555 goto out;
2556 }
2557
2558 /* Allocate rss table and hash key */
2559 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2560 &vnic->rss_table_dma_addr,
2561 GFP_KERNEL);
2562 if (!vnic->rss_table) {
2563 rc = -ENOMEM;
2564 goto out;
2565 }
2566
2567 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2568
2569 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2570 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2571 }
2572 return 0;
2573
2574out:
2575 return rc;
2576}
2577
2578static void bnxt_free_hwrm_resources(struct bnxt *bp)
2579{
2580 struct pci_dev *pdev = bp->pdev;
2581
2582 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2583 bp->hwrm_cmd_resp_dma_addr);
2584
2585 bp->hwrm_cmd_resp_addr = NULL;
2586 if (bp->hwrm_dbg_resp_addr) {
2587 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2588 bp->hwrm_dbg_resp_addr,
2589 bp->hwrm_dbg_resp_dma_addr);
2590
2591 bp->hwrm_dbg_resp_addr = NULL;
2592 }
2593}
2594
2595static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2596{
2597 struct pci_dev *pdev = bp->pdev;
2598
2599 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2600 &bp->hwrm_cmd_resp_dma_addr,
2601 GFP_KERNEL);
2602 if (!bp->hwrm_cmd_resp_addr)
2603 return -ENOMEM;
2604 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2605 HWRM_DBG_REG_BUF_SIZE,
2606 &bp->hwrm_dbg_resp_dma_addr,
2607 GFP_KERNEL);
2608 if (!bp->hwrm_dbg_resp_addr)
2609 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2610
2611 return 0;
2612}
2613
2614static void bnxt_free_stats(struct bnxt *bp)
2615{
2616 u32 size, i;
2617 struct pci_dev *pdev = bp->pdev;
2618
3bdf56c4
MC		 2619 if (bp->hw_rx_port_stats) {
2620 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2621 bp->hw_rx_port_stats,
2622 bp->hw_rx_port_stats_map);
2623 bp->hw_rx_port_stats = NULL;
2624 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2625 }
2626
c0c050c5
MC		 2627 if (!bp->bnapi)
2628 return;
2629
2630 size = sizeof(struct ctx_hw_stats);
2631
2632 for (i = 0; i < bp->cp_nr_rings; i++) {
2633 struct bnxt_napi *bnapi = bp->bnapi[i];
2634 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2635
2636 if (cpr->hw_stats) {
2637 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2638 cpr->hw_stats_map);
2639 cpr->hw_stats = NULL;
2640 }
2641 }
2642}
2643
2644static int bnxt_alloc_stats(struct bnxt *bp)
2645{
2646 u32 size, i;
2647 struct pci_dev *pdev = bp->pdev;
2648
2649 size = sizeof(struct ctx_hw_stats);
2650
2651 for (i = 0; i < bp->cp_nr_rings; i++) {
2652 struct bnxt_napi *bnapi = bp->bnapi[i];
2653 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2654
2655 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2656 &cpr->hw_stats_map,
2657 GFP_KERNEL);
2658 if (!cpr->hw_stats)
2659 return -ENOMEM;
2660
2661 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2662 }
3bdf56c4
MC		 2663
2664 if (BNXT_PF(bp)) {
2665 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2666 sizeof(struct tx_port_stats) + 1024;
2667
2668 bp->hw_rx_port_stats =
2669 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2670 &bp->hw_rx_port_stats_map,
2671 GFP_KERNEL);
2672 if (!bp->hw_rx_port_stats)
2673 return -ENOMEM;
2674
2675 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2676 512;
2677 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2678 sizeof(struct rx_port_stats) + 512;
2679 bp->flags |= BNXT_FLAG_PORT_STATS;
2680 }
c0c050c5
MC		 2681 return 0;
2682}
2683
2684static void bnxt_clear_ring_indices(struct bnxt *bp)
2685{
2686 int i;
2687
2688 if (!bp->bnapi)
2689 return;
2690
2691 for (i = 0; i < bp->cp_nr_rings; i++) {
2692 struct bnxt_napi *bnapi = bp->bnapi[i];
2693 struct bnxt_cp_ring_info *cpr;
2694 struct bnxt_rx_ring_info *rxr;
2695 struct bnxt_tx_ring_info *txr;
2696
2697 if (!bnapi)
2698 continue;
2699
2700 cpr = &bnapi->cp_ring;
2701 cpr->cp_raw_cons = 0;
2702
b6ab4b01 2703 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2704 if (txr) {
2705 txr->tx_prod = 0;
2706 txr->tx_cons = 0;
2707 }
c0c050c5 2708
b6ab4b01 2709 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2710 if (rxr) {
2711 rxr->rx_prod = 0;
2712 rxr->rx_agg_prod = 0;
2713 rxr->rx_sw_agg_prod = 0;
376a5b86 2714 rxr->rx_next_cons = 0;
3b2b7d9d 2715 }
c0c050c5
MC		 2716 }
2717}
2718
2719static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2720{
2721#ifdef CONFIG_RFS_ACCEL
2722 int i;
2723
2724 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2725 * safe to delete the hash table.
2726 */
2727 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2728 struct hlist_head *head;
2729 struct hlist_node *tmp;
2730 struct bnxt_ntuple_filter *fltr;
2731
2732 head = &bp->ntp_fltr_hash_tbl[i];
2733 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2734 hlist_del(&fltr->hash);
2735 kfree(fltr);
2736 }
2737 }
2738 if (irq_reinit) {
2739 kfree(bp->ntp_fltr_bmap);
2740 bp->ntp_fltr_bmap = NULL;
2741 }
2742 bp->ntp_fltr_count = 0;
2743#endif
2744}
2745
2746static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2747{
2748#ifdef CONFIG_RFS_ACCEL
2749 int i, rc = 0;
2750
2751 if (!(bp->flags & BNXT_FLAG_RFS))
2752 return 0;
2753
2754 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2755 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2756
2757 bp->ntp_fltr_count = 0;
2758 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2759 GFP_KERNEL);
2760
2761 if (!bp->ntp_fltr_bmap)
2762 rc = -ENOMEM;
2763
2764 return rc;
2765#else
2766 return 0;
2767#endif
2768}
2769
2770static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2771{
2772 bnxt_free_vnic_attributes(bp);
2773 bnxt_free_tx_rings(bp);
2774 bnxt_free_rx_rings(bp);
2775 bnxt_free_cp_rings(bp);
2776 bnxt_free_ntp_fltrs(bp, irq_re_init);
2777 if (irq_re_init) {
2778 bnxt_free_stats(bp);
2779 bnxt_free_ring_grps(bp);
2780 bnxt_free_vnics(bp);
b6ab4b01
MC		 2781 kfree(bp->tx_ring);
2782 bp->tx_ring = NULL;
2783 kfree(bp->rx_ring);
2784 bp->rx_ring = NULL;
c0c050c5
MC		 2785 kfree(bp->bnapi);
2786 bp->bnapi = NULL;
2787 } else {
2788 bnxt_clear_ring_indices(bp);
2789 }
2790}
2791
2792static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2793{
01657bcd 2794 int i, j, rc, size, arr_size;
c0c050c5
MC		 2795 void *bnapi;
2796
2797 if (irq_re_init) {
2798 /* Allocate bnapi mem pointer array and mem block for
2799 * all queues
2800 */
2801 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2802 bp->cp_nr_rings);
2803 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2804 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2805 if (!bnapi)
2806 return -ENOMEM;
2807
2808 bp->bnapi = bnapi;
2809 bnapi += arr_size;
2810 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2811 bp->bnapi[i] = bnapi;
2812 bp->bnapi[i]->index = i;
2813 bp->bnapi[i]->bp = bp;
2814 }
2815
b6ab4b01
MC		 2816 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2817 sizeof(struct bnxt_rx_ring_info),
2818 GFP_KERNEL);
2819 if (!bp->rx_ring)
2820 return -ENOMEM;
2821
2822 for (i = 0; i < bp->rx_nr_rings; i++) {
2823 bp->rx_ring[i].bnapi = bp->bnapi[i];
2824 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2825 }
2826
2827 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2828 sizeof(struct bnxt_tx_ring_info),
2829 GFP_KERNEL);
2830 if (!bp->tx_ring)
2831 return -ENOMEM;
2832
01657bcd
MC		 2833 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2834 j = 0;
2835 else
2836 j = bp->rx_nr_rings;
2837
2838 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2839 bp->tx_ring[i].bnapi = bp->bnapi[j];
2840 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
b6ab4b01
MC		 2841 }
2842
c0c050c5
MC		 2843 rc = bnxt_alloc_stats(bp);
2844 if (rc)
2845 goto alloc_mem_err;
2846
2847 rc = bnxt_alloc_ntp_fltrs(bp);
2848 if (rc)
2849 goto alloc_mem_err;
2850
2851 rc = bnxt_alloc_vnics(bp);
2852 if (rc)
2853 goto alloc_mem_err;
2854 }
2855
2856 bnxt_init_ring_struct(bp);
2857
2858 rc = bnxt_alloc_rx_rings(bp);
2859 if (rc)
2860 goto alloc_mem_err;
2861
2862 rc = bnxt_alloc_tx_rings(bp);
2863 if (rc)
2864 goto alloc_mem_err;
2865
2866 rc = bnxt_alloc_cp_rings(bp);
2867 if (rc)
2868 goto alloc_mem_err;
2869
2870 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2871 BNXT_VNIC_UCAST_FLAG;
2872 rc = bnxt_alloc_vnic_attributes(bp);
2873 if (rc)
2874 goto alloc_mem_err;
2875 return 0;
2876
2877alloc_mem_err:
2878 bnxt_free_mem(bp, true);
2879 return rc;
2880}
2881
2882void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2883 u16 cmpl_ring, u16 target_id)
2884{
a8643e16 2885 struct input *req = request;
c0c050c5 2886
a8643e16
MC		 2887 req->req_type = cpu_to_le16(req_type);
2888 req->cmpl_ring = cpu_to_le16(cmpl_ring);
2889 req->target_id = cpu_to_le16(target_id);
c0c050c5
MC		 2890 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2891}
2892
fbfbc485
MC		 2893static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
2894 int timeout, bool silent)
c0c050c5 2895{
a11fa2be 2896 int i, intr_process, rc, tmo_count;
a8643e16 2897 struct input *req = msg;
c0c050c5
MC		 2898 u32 *data = msg;
2899 __le32 *resp_len, *valid;
2900 u16 cp_ring_id, len = 0;
2901 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2902
a8643e16 2903 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
c0c050c5 2904 memset(resp, 0, PAGE_SIZE);
a8643e16 2905 cp_ring_id = le16_to_cpu(req->cmpl_ring);
c0c050c5
MC		 2906 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2907
2908 /* Write request msg to hwrm channel */
2909 __iowrite32_copy(bp->bar0, data, msg_len / 4);
2910
e6ef2699 2911 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
d79979a1
MC		 2912 writel(0, bp->bar0 + i);
2913
c0c050c5
MC		 2914 /* currently supports only one outstanding message */
2915 if (intr_process)
a8643e16 2916 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
c0c050c5
MC		 2917
2918 /* Ring channel doorbell */
2919 writel(1, bp->bar0 + 0x100);
2920
ff4fe81d
MC		 2921 if (!timeout)
2922 timeout = DFLT_HWRM_CMD_TIMEOUT;
2923
c0c050c5 2924 i = 0;
a11fa2be 2925 tmo_count = timeout * 40;
c0c050c5
MC		 2926 if (intr_process) {
2927 /* Wait until hwrm response cmpl interrupt is processed */
2928 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
a11fa2be
MC		 2929 i++ < tmo_count) {
2930 usleep_range(25, 40);
c0c050c5
MC		 2931 }
2932
2933 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2934 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
a8643e16 2935 le16_to_cpu(req->req_type));
c0c050c5
MC		 2936 return -1;
2937 }
2938 } else {
2939 /* Check if response len is updated */
2940 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
a11fa2be 2941 for (i = 0; i < tmo_count; i++) {
c0c050c5
MC		 2942 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2943 HWRM_RESP_LEN_SFT;
2944 if (len)
2945 break;
a11fa2be 2946 usleep_range(25, 40);
c0c050c5
MC		 2947 }
2948
a11fa2be 2949 if (i >= tmo_count) {
c0c050c5 2950 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
a8643e16 2951 timeout, le16_to_cpu(req->req_type),
8578d6c1 2952 le16_to_cpu(req->seq_id), len);
c0c050c5
MC		 2953 return -1;
2954 }
2955
2956 /* Last word of resp contains valid bit */
2957 valid = bp->hwrm_cmd_resp_addr + len - 4;
a11fa2be 2958 for (i = 0; i < 5; i++) {
c0c050c5
MC		 2959 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2960 break;
a11fa2be 2961 udelay(1);
c0c050c5
MC		 2962 }
2963
a11fa2be 2964 if (i >= 5) {
c0c050c5 2965 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
a8643e16
MC		 2966 timeout, le16_to_cpu(req->req_type),
2967 le16_to_cpu(req->seq_id), len, *valid);
c0c050c5
MC		 2968 return -1;
2969 }
2970 }
2971
2972 rc = le16_to_cpu(resp->error_code);
fbfbc485 2973 if (rc && !silent)
c0c050c5
MC		 2974 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2975 le16_to_cpu(resp->req_type),
2976 le16_to_cpu(resp->seq_id), rc);
fbfbc485
MC		 2977 return rc;
2978}
2979
2980int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2981{
2982 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
c0c050c5
MC		 2983}
2984
2985int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2986{
2987 int rc;
2988
2989 mutex_lock(&bp->hwrm_cmd_lock);
2990 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2991 mutex_unlock(&bp->hwrm_cmd_lock);
2992 return rc;
2993}
2994
90e20921
MC		 2995int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
2996 int timeout)
2997{
2998 int rc;
2999
3000 mutex_lock(&bp->hwrm_cmd_lock);
3001 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3002 mutex_unlock(&bp->hwrm_cmd_lock);
3003 return rc;
3004}
3005
c0c050c5
MC		 3006static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3007{
3008 struct hwrm_func_drv_rgtr_input req = {0};
3009 int i;
25be8623
MC		 3010 DECLARE_BITMAP(async_events_bmap, 256);
3011 u32 *events = (u32 *)async_events_bmap;
c0c050c5
MC		 3012
3013 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3014
3015 req.enables =
3016 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3017 FUNC_DRV_RGTR_REQ_ENABLES_VER |
3018 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3019
25be8623
MC		 3020 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3021 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3022 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3023
3024 for (i = 0; i < 8; i++)
3025 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3026
11f15ed3 3027 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
c0c050c5
MC		 3028 req.ver_maj = DRV_VER_MAJ;
3029 req.ver_min = DRV_VER_MIN;
3030 req.ver_upd = DRV_VER_UPD;
3031
3032 if (BNXT_PF(bp)) {
de68f5de 3033 DECLARE_BITMAP(vf_req_snif_bmap, 256);
c0c050c5
MC		 3034 u32 *data = (u32 *)vf_req_snif_bmap;
3035
de68f5de 3036 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
c0c050c5
MC		 3037 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3038 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3039
de68f5de
MC		 3040 for (i = 0; i < 8; i++)
3041 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3042
c0c050c5
MC		 3043 req.enables |=
3044 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3045 }
3046
3047 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3048}
3049
be58a0da
JH		 3050static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3051{
3052 struct hwrm_func_drv_unrgtr_input req = {0};
3053
3054 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3055 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3056}
3057
c0c050c5
MC		 3058static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3059{
3060 u32 rc = 0;
3061 struct hwrm_tunnel_dst_port_free_input req = {0};
3062
3063 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3064 req.tunnel_type = tunnel_type;
3065
3066 switch (tunnel_type) {
3067 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3068 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3069 break;
3070 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3071 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3072 break;
3073 default:
3074 break;
3075 }
3076
3077 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3078 if (rc)
3079 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3080 rc);
3081 return rc;
3082}
3083
3084static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3085 u8 tunnel_type)
3086{
3087 u32 rc = 0;
3088 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3089 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3090
3091 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3092
3093 req.tunnel_type = tunnel_type;
3094 req.tunnel_dst_port_val = port;
3095
3096 mutex_lock(&bp->hwrm_cmd_lock);
3097 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3098 if (rc) {
3099 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3100 rc);
3101 goto err_out;
3102 }
3103
3104 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
3105 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3106
3107 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
3108 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3109err_out:
3110 mutex_unlock(&bp->hwrm_cmd_lock);
3111 return rc;
3112}
3113
3114static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3115{
3116 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3117 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3118
3119 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 3120 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 3121
3122 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3123 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3124 req.mask = cpu_to_le32(vnic->rx_mask);
3125 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3126}
3127
3128#ifdef CONFIG_RFS_ACCEL
3129static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3130 struct bnxt_ntuple_filter *fltr)
3131{
3132 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3133
3134 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3135 req.ntuple_filter_id = fltr->filter_id;
3136 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3137}
3138
3139#define BNXT_NTP_FLTR_FLAGS \
3140 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3141 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3142 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3143 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3144 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3145 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3146 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3147 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3148 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3149 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3150 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3151 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3152 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 3153 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5
MC		 3154
3155static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3156 struct bnxt_ntuple_filter *fltr)
3157{
3158 int rc = 0;
3159 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3160 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3161 bp->hwrm_cmd_resp_addr;
3162 struct flow_keys *keys = &fltr->fkeys;
3163 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3164
3165 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3166 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
3167
3168 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3169
3170 req.ethertype = htons(ETH_P_IP);
3171 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 3172 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 3173 req.ip_protocol = keys->basic.ip_proto;
3174
3175 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3176 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3177 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3178 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3179
3180 req.src_port = keys->ports.src;
3181 req.src_port_mask = cpu_to_be16(0xffff);
3182 req.dst_port = keys->ports.dst;
3183 req.dst_port_mask = cpu_to_be16(0xffff);
3184
c193554e 3185 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 3186 mutex_lock(&bp->hwrm_cmd_lock);
3187 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3188 if (!rc)
3189 fltr->filter_id = resp->ntuple_filter_id;
3190 mutex_unlock(&bp->hwrm_cmd_lock);
3191 return rc;
3192}
3193#endif
3194
3195static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3196 u8 *mac_addr)
3197{
3198 u32 rc = 0;
3199 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3200 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3201
3202 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3203 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
3204 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 3205 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 3206 req.enables =
3207 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 3208 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 3209 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3210 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3211 req.l2_addr_mask[0] = 0xff;
3212 req.l2_addr_mask[1] = 0xff;
3213 req.l2_addr_mask[2] = 0xff;
3214 req.l2_addr_mask[3] = 0xff;
3215 req.l2_addr_mask[4] = 0xff;
3216 req.l2_addr_mask[5] = 0xff;
3217
3218 mutex_lock(&bp->hwrm_cmd_lock);
3219 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3220 if (!rc)
3221 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3222 resp->l2_filter_id;
3223 mutex_unlock(&bp->hwrm_cmd_lock);
3224 return rc;
3225}
3226
3227static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3228{
3229 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3230 int rc = 0;
3231
3232 /* Any associated ntuple filters will also be cleared by firmware. */
3233 mutex_lock(&bp->hwrm_cmd_lock);
3234 for (i = 0; i < num_of_vnics; i++) {
3235 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3236
3237 for (j = 0; j < vnic->uc_filter_count; j++) {
3238 struct hwrm_cfa_l2_filter_free_input req = {0};
3239
3240 bnxt_hwrm_cmd_hdr_init(bp, &req,
3241 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3242
3243 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3244
3245 rc = _hwrm_send_message(bp, &req, sizeof(req),
3246 HWRM_CMD_TIMEOUT);
3247 }
3248 vnic->uc_filter_count = 0;
3249 }
3250 mutex_unlock(&bp->hwrm_cmd_lock);
3251
3252 return rc;
3253}
3254
3255static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3256{
3257 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3258 struct hwrm_vnic_tpa_cfg_input req = {0};
3259
3260 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3261
3262 if (tpa_flags) {
3263 u16 mss = bp->dev->mtu - 40;
3264 u32 nsegs, n, segs = 0, flags;
3265
3266 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3267 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3268 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3269 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3270 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3271 if (tpa_flags & BNXT_FLAG_GRO)
3272 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3273
3274 req.flags = cpu_to_le32(flags);
3275
3276 req.enables =
3277 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 3278 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3279 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 3280
3281 /* Number of segs are log2 units, and first packet is not
3282 * included as part of this units.
3283 */
2839f28b
MC		 3284 if (mss <= BNXT_RX_PAGE_SIZE) {
3285 n = BNXT_RX_PAGE_SIZE / mss;
c0c050c5
MC		 3286 nsegs = (MAX_SKB_FRAGS - 1) * n;
3287 } else {
2839f28b
MC		 3288 n = mss / BNXT_RX_PAGE_SIZE;
3289 if (mss & (BNXT_RX_PAGE_SIZE - 1))
c0c050c5
MC		 3290 n++;
3291 nsegs = (MAX_SKB_FRAGS - n) / n;
3292 }
3293
3294 segs = ilog2(nsegs);
3295 req.max_agg_segs = cpu_to_le16(segs);
3296 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 3297
3298 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 3299 }
3300 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3301
3302 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3303}
3304
3305static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3306{
3307 u32 i, j, max_rings;
3308 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3309 struct hwrm_vnic_rss_cfg_input req = {0};
3310
3311 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
3312 return 0;
3313
3314 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3315 if (set_rss) {
3316 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3317 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3318 BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3319 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3320
3321 req.hash_type = cpu_to_le32(vnic->hash_type);
3322
3323 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3324 max_rings = bp->rx_nr_rings;
3325 else
3326 max_rings = 1;
3327
3328 /* Fill the RSS indirection table with ring group ids */
3329 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3330 if (j == max_rings)
3331 j = 0;
3332 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3333 }
3334
3335 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3336 req.hash_key_tbl_addr =
3337 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3338 }
3339 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3340 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3341}
3342
3343static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3344{
3345 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3346 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3347
3348 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3349 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3350 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3351 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3352 req.enables =
3353 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3354 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3355 /* thresholds not implemented in firmware yet */
3356 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3357 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3358 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3359 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3360}
3361
3362static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3363{
3364 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3365
3366 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3367 req.rss_cos_lb_ctx_id =
3368 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3369
3370 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3371 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3372}
3373
3374static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3375{
3376 int i;
3377
3378 for (i = 0; i < bp->nr_vnics; i++) {
3379 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3380
3381 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3382 bnxt_hwrm_vnic_ctx_free_one(bp, i);
3383 }
3384 bp->rsscos_nr_ctxs = 0;
3385}
3386
3387static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3388{
3389 int rc;
3390 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3391 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3392 bp->hwrm_cmd_resp_addr;
3393
3394 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3395 -1);
3396
3397 mutex_lock(&bp->hwrm_cmd_lock);
3398 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3399 if (!rc)
3400 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3401 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3402 mutex_unlock(&bp->hwrm_cmd_lock);
3403
3404 return rc;
3405}
3406
3407static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3408{
b81a90d3 3409 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 3410 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3411 struct hwrm_vnic_cfg_input req = {0};
cf6645f8 3412 u16 def_vlan = 0;
c0c050c5
MC		 3413
3414 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3415 /* Only RSS support for now TBD: COS & LB */
3416 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
550feebf
MC		 3417 VNIC_CFG_REQ_ENABLES_RSS_RULE |
3418 VNIC_CFG_REQ_ENABLES_MRU);
c0c050c5
MC		 3419 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3420 req.cos_rule = cpu_to_le16(0xffff);
3421 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 3422 ring = 0;
c0c050c5 3423 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 3424 ring = vnic_id - 1;
c0c050c5 3425
b81a90d3 3426 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5
MC		 3427 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3428 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3429
3430 req.lb_rule = cpu_to_le16(0xffff);
3431 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3432 VLAN_HLEN);
3433
cf6645f8
MC		 3434#ifdef CONFIG_BNXT_SRIOV
3435 if (BNXT_VF(bp))
3436 def_vlan = bp->vf.vlan;
3437#endif
3438 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
c0c050c5
MC		 3439 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3440
3441 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3442}
3443
3444static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3445{
3446 u32 rc = 0;
3447
3448 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3449 struct hwrm_vnic_free_input req = {0};
3450
3451 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3452 req.vnic_id =
3453 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3454
3455 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3456 if (rc)
3457 return rc;
3458 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3459 }
3460 return rc;
3461}
3462
3463static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3464{
3465 u16 i;
3466
3467 for (i = 0; i < bp->nr_vnics; i++)
3468 bnxt_hwrm_vnic_free_one(bp, i);
3469}
3470
b81a90d3
MC		 3471static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3472 unsigned int start_rx_ring_idx,
3473 unsigned int nr_rings)
c0c050c5 3474{
b81a90d3
MC		 3475 int rc = 0;
3476 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 3477 struct hwrm_vnic_alloc_input req = {0};
3478 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3479
3480 /* map ring groups to this vnic */
b81a90d3
MC		 3481 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3482 grp_idx = bp->rx_ring[i].bnapi->index;
3483 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 3484 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 3485 j, nr_rings);
c0c050c5
MC		 3486 break;
3487 }
3488 bp->vnic_info[vnic_id].fw_grp_ids[j] =
b81a90d3 3489 bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 3490 }
3491
3492 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3493 if (vnic_id == 0)
3494 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3495
3496 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3497
3498 mutex_lock(&bp->hwrm_cmd_lock);
3499 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3500 if (!rc)
3501 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3502 mutex_unlock(&bp->hwrm_cmd_lock);
3503 return rc;
3504}
3505
3506static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3507{
3508 u16 i;
3509 u32 rc = 0;
3510
3511 mutex_lock(&bp->hwrm_cmd_lock);
3512 for (i = 0; i < bp->rx_nr_rings; i++) {
3513 struct hwrm_ring_grp_alloc_input req = {0};
3514 struct hwrm_ring_grp_alloc_output *resp =
3515 bp->hwrm_cmd_resp_addr;
b81a90d3 3516 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 3517
3518 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3519
b81a90d3
MC		 3520 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3521 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3522 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3523 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 3524
3525 rc = _hwrm_send_message(bp, &req, sizeof(req),
3526 HWRM_CMD_TIMEOUT);
3527 if (rc)
3528 break;
3529
b81a90d3
MC		 3530 bp->grp_info[grp_idx].fw_grp_id =
3531 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 3532 }
3533 mutex_unlock(&bp->hwrm_cmd_lock);
3534 return rc;
3535}
3536
3537static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3538{
3539 u16 i;
3540 u32 rc = 0;
3541 struct hwrm_ring_grp_free_input req = {0};
3542
3543 if (!bp->grp_info)
3544 return 0;
3545
3546 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3547
3548 mutex_lock(&bp->hwrm_cmd_lock);
3549 for (i = 0; i < bp->cp_nr_rings; i++) {
3550 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3551 continue;
3552 req.ring_group_id =
3553 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3554
3555 rc = _hwrm_send_message(bp, &req, sizeof(req),
3556 HWRM_CMD_TIMEOUT);
3557 if (rc)
3558 break;
3559 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3560 }
3561 mutex_unlock(&bp->hwrm_cmd_lock);
3562 return rc;
3563}
3564
3565static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3566 struct bnxt_ring_struct *ring,
3567 u32 ring_type, u32 map_index,
3568 u32 stats_ctx_id)
3569{
3570 int rc = 0, err = 0;
3571 struct hwrm_ring_alloc_input req = {0};
3572 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3573 u16 ring_id;
3574
3575 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3576
3577 req.enables = 0;
3578 if (ring->nr_pages > 1) {
3579 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3580 /* Page size is in log2 units */
3581 req.page_size = BNXT_PAGE_SHIFT;
3582 req.page_tbl_depth = 1;
3583 } else {
3584 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3585 }
3586 req.fbo = 0;
3587 /* Association of ring index with doorbell index and MSIX number */
3588 req.logical_id = cpu_to_le16(map_index);
3589
3590 switch (ring_type) {
3591 case HWRM_RING_ALLOC_TX:
3592 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3593 /* Association of transmit ring with completion ring */
3594 req.cmpl_ring_id =
3595 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3596 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3597 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3598 req.queue_id = cpu_to_le16(ring->queue_id);
3599 break;
3600 case HWRM_RING_ALLOC_RX:
3601 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3602 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3603 break;
3604 case HWRM_RING_ALLOC_AGG:
3605 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3606 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3607 break;
3608 case HWRM_RING_ALLOC_CMPL:
3609 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3610 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3611 if (bp->flags & BNXT_FLAG_USING_MSIX)
3612 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3613 break;
3614 default:
3615 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3616 ring_type);
3617 return -1;
3618 }
3619
3620 mutex_lock(&bp->hwrm_cmd_lock);
3621 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3622 err = le16_to_cpu(resp->error_code);
3623 ring_id = le16_to_cpu(resp->ring_id);
3624 mutex_unlock(&bp->hwrm_cmd_lock);
3625
3626 if (rc || err) {
3627 switch (ring_type) {
3628 case RING_FREE_REQ_RING_TYPE_CMPL:
3629 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3630 rc, err);
3631 return -1;
3632
3633 case RING_FREE_REQ_RING_TYPE_RX:
3634 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3635 rc, err);
3636 return -1;
3637
3638 case RING_FREE_REQ_RING_TYPE_TX:
3639 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3640 rc, err);
3641 return -1;
3642
3643 default:
3644 netdev_err(bp->dev, "Invalid ring\n");
3645 return -1;
3646 }
3647 }
3648 ring->fw_ring_id = ring_id;
3649 return rc;
3650}
3651
3652static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3653{
3654 int i, rc = 0;
3655
edd0c2cc
MC		 3656 for (i = 0; i < bp->cp_nr_rings; i++) {
3657 struct bnxt_napi *bnapi = bp->bnapi[i];
3658 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3659 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
c0c050c5 3660
33e52d88 3661 cpr->cp_doorbell = bp->bar1 + i * 0x80;
edd0c2cc
MC		 3662 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3663 INVALID_STATS_CTX_ID);
3664 if (rc)
3665 goto err_out;
edd0c2cc
MC		 3666 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3667 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3668 }
3669
edd0c2cc 3670 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3671 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3672 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3673 u32 map_idx = txr->bnapi->index;
3674 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
c0c050c5 3675
b81a90d3
MC		 3676 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3677 map_idx, fw_stats_ctx);
edd0c2cc
MC		 3678 if (rc)
3679 goto err_out;
b81a90d3 3680 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3681 }
3682
edd0c2cc 3683 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3684 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3685 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 3686 u32 map_idx = rxr->bnapi->index;
c0c050c5 3687
b81a90d3
MC		 3688 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3689 map_idx, INVALID_STATS_CTX_ID);
edd0c2cc
MC		 3690 if (rc)
3691 goto err_out;
b81a90d3 3692 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
edd0c2cc 3693 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
b81a90d3 3694 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3695 }
3696
3697 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3698 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3699 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 3700 struct bnxt_ring_struct *ring =
3701 &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3702 u32 grp_idx = rxr->bnapi->index;
3703 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5
MC		 3704
3705 rc = hwrm_ring_alloc_send_msg(bp, ring,
3706 HWRM_RING_ALLOC_AGG,
b81a90d3 3707 map_idx,
c0c050c5
MC		 3708 INVALID_STATS_CTX_ID);
3709 if (rc)
3710 goto err_out;
3711
b81a90d3 3712 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3713 writel(DB_KEY_RX | rxr->rx_agg_prod,
3714 rxr->rx_agg_doorbell);
b81a90d3 3715 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3716 }
3717 }
3718err_out:
3719 return rc;
3720}
3721
3722static int hwrm_ring_free_send_msg(struct bnxt *bp,
3723 struct bnxt_ring_struct *ring,
3724 u32 ring_type, int cmpl_ring_id)
3725{
3726 int rc;
3727 struct hwrm_ring_free_input req = {0};
3728 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3729 u16 error_code;
3730
74608fc9 3731 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 3732 req.ring_type = ring_type;
3733 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3734
3735 mutex_lock(&bp->hwrm_cmd_lock);
3736 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3737 error_code = le16_to_cpu(resp->error_code);
3738 mutex_unlock(&bp->hwrm_cmd_lock);
3739
3740 if (rc || error_code) {
3741 switch (ring_type) {
3742 case RING_FREE_REQ_RING_TYPE_CMPL:
3743 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3744 rc);
3745 return rc;
3746 case RING_FREE_REQ_RING_TYPE_RX:
3747 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3748 rc);
3749 return rc;
3750 case RING_FREE_REQ_RING_TYPE_TX:
3751 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3752 rc);
3753 return rc;
3754 default:
3755 netdev_err(bp->dev, "Invalid ring\n");
3756 return -1;
3757 }
3758 }
3759 return 0;
3760}
3761
edd0c2cc 3762static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 3763{
edd0c2cc 3764 int i;
c0c050c5
MC		 3765
3766 if (!bp->bnapi)
edd0c2cc 3767 return;
c0c050c5 3768
edd0c2cc 3769 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3770 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3771 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3772 u32 grp_idx = txr->bnapi->index;
3773 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3774
3775 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3776 hwrm_ring_free_send_msg(bp, ring,
3777 RING_FREE_REQ_RING_TYPE_TX,
3778 close_path ? cmpl_ring_id :
3779 INVALID_HW_RING_ID);
3780 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 3781 }
3782 }
3783
edd0c2cc 3784 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3785 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3786 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3
MC		 3787 u32 grp_idx = rxr->bnapi->index;
3788 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3789
3790 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3791 hwrm_ring_free_send_msg(bp, ring,
3792 RING_FREE_REQ_RING_TYPE_RX,
3793 close_path ? cmpl_ring_id :
3794 INVALID_HW_RING_ID);
3795 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 3796 bp->grp_info[grp_idx].rx_fw_ring_id =
3797 INVALID_HW_RING_ID;
c0c050c5
MC		 3798 }
3799 }
3800
edd0c2cc 3801 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3802 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3803 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3804 u32 grp_idx = rxr->bnapi->index;
3805 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3806
3807 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3808 hwrm_ring_free_send_msg(bp, ring,
3809 RING_FREE_REQ_RING_TYPE_RX,
3810 close_path ? cmpl_ring_id :
3811 INVALID_HW_RING_ID);
3812 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 3813 bp->grp_info[grp_idx].agg_fw_ring_id =
3814 INVALID_HW_RING_ID;
c0c050c5
MC		 3815 }
3816 }
3817
edd0c2cc
MC		 3818 for (i = 0; i < bp->cp_nr_rings; i++) {
3819 struct bnxt_napi *bnapi = bp->bnapi[i];
3820 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3821 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3822
3823 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3824 hwrm_ring_free_send_msg(bp, ring,
3825 RING_FREE_REQ_RING_TYPE_CMPL,
3826 INVALID_HW_RING_ID);
3827 ring->fw_ring_id = INVALID_HW_RING_ID;
3828 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 3829 }
3830 }
c0c050c5
MC		 3831}
3832
bb053f52
MC		 3833static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3834 u32 buf_tmrs, u16 flags,
3835 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3836{
3837 req->flags = cpu_to_le16(flags);
3838 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3839 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3840 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3841 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3842 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3843 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3844 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3845 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3846}
3847
c0c050c5
MC		 3848int bnxt_hwrm_set_coal(struct bnxt *bp)
3849{
3850 int i, rc = 0;
dfc9c94a
MC		 3851 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3852 req_tx = {0}, *req;
c0c050c5
MC		 3853 u16 max_buf, max_buf_irq;
3854 u16 buf_tmr, buf_tmr_irq;
3855 u32 flags;
3856
dfc9c94a
MC		 3857 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3858 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3859 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3860 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
c0c050c5 3861
dfb5b894
MC		 3862 /* Each rx completion (2 records) should be DMAed immediately.
3863 * DMA 1/4 of the completion buffers at a time.
3864 */
3865 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
c0c050c5
MC		 3866 /* max_buf must not be zero */
3867 max_buf = clamp_t(u16, max_buf, 1, 63);
dfb5b894
MC		 3868 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
3869 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
3870 /* buf timer set to 1/4 of interrupt timer */
3871 buf_tmr = max_t(u16, buf_tmr / 4, 1);
3872 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
3873 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
c0c050c5
MC		 3874
3875 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3876
3877 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3878 * if coal_ticks is less than 25 us.
3879 */
dfb5b894 3880 if (bp->rx_coal_ticks < 25)
c0c050c5
MC		 3881 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3882
bb053f52 3883 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
dfc9c94a
MC		 3884 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
3885
3886 /* max_buf must not be zero */
3887 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
3888 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
3889 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
3890 /* buf timer set to 1/4 of interrupt timer */
3891 buf_tmr = max_t(u16, buf_tmr / 4, 1);
3892 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
3893 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3894
3895 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3896 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3897 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
c0c050c5
MC		 3898
3899 mutex_lock(&bp->hwrm_cmd_lock);
3900 for (i = 0; i < bp->cp_nr_rings; i++) {
dfc9c94a 3901 struct bnxt_napi *bnapi = bp->bnapi[i];
c0c050c5 3902
dfc9c94a
MC		 3903 req = &req_rx;
3904 if (!bnapi->rx_ring)
3905 req = &req_tx;
3906 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3907
3908 rc = _hwrm_send_message(bp, req, sizeof(*req),
c0c050c5
MC		 3909 HWRM_CMD_TIMEOUT);
3910 if (rc)
3911 break;
3912 }
3913 mutex_unlock(&bp->hwrm_cmd_lock);
3914 return rc;
3915}
3916
3917static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3918{
3919 int rc = 0, i;
3920 struct hwrm_stat_ctx_free_input req = {0};
3921
3922 if (!bp->bnapi)
3923 return 0;
3924
3925 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3926
3927 mutex_lock(&bp->hwrm_cmd_lock);
3928 for (i = 0; i < bp->cp_nr_rings; i++) {
3929 struct bnxt_napi *bnapi = bp->bnapi[i];
3930 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3931
3932 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3933 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3934
3935 rc = _hwrm_send_message(bp, &req, sizeof(req),
3936 HWRM_CMD_TIMEOUT);
3937 if (rc)
3938 break;
3939
3940 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3941 }
3942 }
3943 mutex_unlock(&bp->hwrm_cmd_lock);
3944 return rc;
3945}
3946
3947static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3948{
3949 int rc = 0, i;
3950 struct hwrm_stat_ctx_alloc_input req = {0};
3951 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3952
3953 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3954
3955 req.update_period_ms = cpu_to_le32(1000);
3956
3957 mutex_lock(&bp->hwrm_cmd_lock);
3958 for (i = 0; i < bp->cp_nr_rings; i++) {
3959 struct bnxt_napi *bnapi = bp->bnapi[i];
3960 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3961
3962 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3963
3964 rc = _hwrm_send_message(bp, &req, sizeof(req),
3965 HWRM_CMD_TIMEOUT);
3966 if (rc)
3967 break;
3968
3969 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3970
3971 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3972 }
3973 mutex_unlock(&bp->hwrm_cmd_lock);
3974 return 0;
3975}
3976
cf6645f8
MC		 3977static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
3978{
3979 struct hwrm_func_qcfg_input req = {0};
567b2abe 3980 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
cf6645f8
MC		 3981 int rc;
3982
3983 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
3984 req.fid = cpu_to_le16(0xffff);
3985 mutex_lock(&bp->hwrm_cmd_lock);
3986 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3987 if (rc)
3988 goto func_qcfg_exit;
3989
3990#ifdef CONFIG_BNXT_SRIOV
3991 if (BNXT_VF(bp)) {
cf6645f8
MC		 3992 struct bnxt_vf_info *vf = &bp->vf;
3993
3994 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
3995 }
3996#endif
567b2abe
SB		 3997 switch (resp->port_partition_type) {
3998 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
3999 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4000 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4001 bp->port_partition_type = resp->port_partition_type;
4002 break;
4003 }
cf6645f8
MC		 4004
4005func_qcfg_exit:
4006 mutex_unlock(&bp->hwrm_cmd_lock);
4007 return rc;
4008}
4009
4a21b49b 4010int bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 4011{
4012 int rc = 0;
4013 struct hwrm_func_qcaps_input req = {0};
4014 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4015
4016 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4017 req.fid = cpu_to_le16(0xffff);
4018
4019 mutex_lock(&bp->hwrm_cmd_lock);
4020 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4021 if (rc)
4022 goto hwrm_func_qcaps_exit;
4023
4024 if (BNXT_PF(bp)) {
4025 struct bnxt_pf_info *pf = &bp->pf;
4026
4027 pf->fw_fid = le16_to_cpu(resp->fid);
4028 pf->port_id = le16_to_cpu(resp->port_id);
11f15ed3 4029 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
bdd4347b 4030 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
c0c050c5
MC		 4031 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4032 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4033 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
c0c050c5 4034 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4035 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4036 if (!pf->max_hw_ring_grps)
4037 pf->max_hw_ring_grps = pf->max_tx_rings;
c0c050c5
MC		 4038 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4039 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4040 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4041 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4042 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4043 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4044 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4045 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4046 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4047 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4048 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4049 } else {
379a80a1 4050#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 4051 struct bnxt_vf_info *vf = &bp->vf;
4052
4053 vf->fw_fid = le16_to_cpu(resp->fid);
11f15ed3 4054 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
bdd4347b
JH		 4055 if (is_valid_ether_addr(vf->mac_addr))
4056 /* overwrite netdev dev_adr with admin VF MAC */
4057 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4058 else
4059 random_ether_addr(bp->dev->dev_addr);
c0c050c5
MC		 4060
4061 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4062 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4063 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4064 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4065 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4066 if (!vf->max_hw_ring_grps)
4067 vf->max_hw_ring_grps = vf->max_tx_rings;
c0c050c5
MC		 4068 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4069 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4070 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
379a80a1 4071#endif
c0c050c5
MC		 4072 }
4073
4074 bp->tx_push_thresh = 0;
4075 if (resp->flags &
4076 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4077 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4078
4079hwrm_func_qcaps_exit:
4080 mutex_unlock(&bp->hwrm_cmd_lock);
4081 return rc;
4082}
4083
4084static int bnxt_hwrm_func_reset(struct bnxt *bp)
4085{
4086 struct hwrm_func_reset_input req = {0};
4087
4088 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4089 req.enables = 0;
4090
4091 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4092}
4093
4094static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4095{
4096 int rc = 0;
4097 struct hwrm_queue_qportcfg_input req = {0};
4098 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4099 u8 i, *qptr;
4100
4101 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4102
4103 mutex_lock(&bp->hwrm_cmd_lock);
4104 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4105 if (rc)
4106 goto qportcfg_exit;
4107
4108 if (!resp->max_configurable_queues) {
4109 rc = -EINVAL;
4110 goto qportcfg_exit;
4111 }
4112 bp->max_tc = resp->max_configurable_queues;
4113 if (bp->max_tc > BNXT_MAX_QUEUE)
4114 bp->max_tc = BNXT_MAX_QUEUE;
4115
4116 qptr = &resp->queue_id0;
4117 for (i = 0; i < bp->max_tc; i++) {
4118 bp->q_info[i].queue_id = *qptr++;
4119 bp->q_info[i].queue_profile = *qptr++;
4120 }
4121
4122qportcfg_exit:
4123 mutex_unlock(&bp->hwrm_cmd_lock);
4124 return rc;
4125}
4126
4127static int bnxt_hwrm_ver_get(struct bnxt *bp)
4128{
4129 int rc;
4130 struct hwrm_ver_get_input req = {0};
4131 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4132
e6ef2699 4133 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
c0c050c5
MC		 4134 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4135 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4136 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4137 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4138 mutex_lock(&bp->hwrm_cmd_lock);
4139 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4140 if (rc)
4141 goto hwrm_ver_get_exit;
4142
4143 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4144
11f15ed3
MC		 4145 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4146 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
c193554e
MC		 4147 if (resp->hwrm_intf_maj < 1) {
4148 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
c0c050c5 4149 resp->hwrm_intf_maj, resp->hwrm_intf_min,
c193554e
MC		 4150 resp->hwrm_intf_upd);
4151 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5 4152 }
3ebf6f0a 4153 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
c0c050c5
MC		 4154 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4155 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4156
ff4fe81d
MC		 4157 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4158 if (!bp->hwrm_cmd_timeout)
4159 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4160
e6ef2699
MC		 4161 if (resp->hwrm_intf_maj >= 1)
4162 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4163
659c805c
MC		 4164 bp->chip_num = le16_to_cpu(resp->chip_num);
4165
c0c050c5
MC		 4166hwrm_ver_get_exit:
4167 mutex_unlock(&bp->hwrm_cmd_lock);
4168 return rc;
4169}
4170
3bdf56c4
MC		 4171static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4172{
4173 int rc;
4174 struct bnxt_pf_info *pf = &bp->pf;
4175 struct hwrm_port_qstats_input req = {0};
4176
4177 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4178 return 0;
4179
4180 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4181 req.port_id = cpu_to_le16(pf->port_id);
4182 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4183 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4184 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4185 return rc;
4186}
4187
c0c050c5
MC		 4188static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4189{
4190 if (bp->vxlan_port_cnt) {
4191 bnxt_hwrm_tunnel_dst_port_free(
4192 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4193 }
4194 bp->vxlan_port_cnt = 0;
4195 if (bp->nge_port_cnt) {
4196 bnxt_hwrm_tunnel_dst_port_free(
4197 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4198 }
4199 bp->nge_port_cnt = 0;
4200}
4201
4202static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4203{
4204 int rc, i;
4205 u32 tpa_flags = 0;
4206
4207 if (set_tpa)
4208 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4209 for (i = 0; i < bp->nr_vnics; i++) {
4210 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4211 if (rc) {
4212 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4213 rc, i);
4214 return rc;
4215 }
4216 }
4217 return 0;
4218}
4219
4220static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4221{
4222 int i;
4223
4224 for (i = 0; i < bp->nr_vnics; i++)
4225 bnxt_hwrm_vnic_set_rss(bp, i, false);
4226}
4227
4228static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4229 bool irq_re_init)
4230{
4231 if (bp->vnic_info) {
4232 bnxt_hwrm_clear_vnic_filter(bp);
4233 /* clear all RSS setting before free vnic ctx */
4234 bnxt_hwrm_clear_vnic_rss(bp);
4235 bnxt_hwrm_vnic_ctx_free(bp);
4236 /* before free the vnic, undo the vnic tpa settings */
4237 if (bp->flags & BNXT_FLAG_TPA)
4238 bnxt_set_tpa(bp, false);
4239 bnxt_hwrm_vnic_free(bp);
4240 }
4241 bnxt_hwrm_ring_free(bp, close_path);
4242 bnxt_hwrm_ring_grp_free(bp);
4243 if (irq_re_init) {
4244 bnxt_hwrm_stat_ctx_free(bp);
4245 bnxt_hwrm_free_tunnel_ports(bp);
4246 }
4247}
4248
4249static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4250{
4251 int rc;
4252
4253 /* allocate context for vnic */
4254 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
4255 if (rc) {
4256 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4257 vnic_id, rc);
4258 goto vnic_setup_err;
4259 }
4260 bp->rsscos_nr_ctxs++;
4261
4262 /* configure default vnic, ring grp */
4263 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4264 if (rc) {
4265 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4266 vnic_id, rc);
4267 goto vnic_setup_err;
4268 }
4269
4270 /* Enable RSS hashing on vnic */
4271 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4272 if (rc) {
4273 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4274 vnic_id, rc);
4275 goto vnic_setup_err;
4276 }
4277
4278 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4279 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4280 if (rc) {
4281 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4282 vnic_id, rc);
4283 }
4284 }
4285
4286vnic_setup_err:
4287 return rc;
4288}
4289
4290static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4291{
4292#ifdef CONFIG_RFS_ACCEL
4293 int i, rc = 0;
4294
4295 for (i = 0; i < bp->rx_nr_rings; i++) {
4296 u16 vnic_id = i + 1;
4297 u16 ring_id = i;
4298
4299 if (vnic_id >= bp->nr_vnics)
4300 break;
4301
4302 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
b81a90d3 4303 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 4304 if (rc) {
4305 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4306 vnic_id, rc);
4307 break;
4308 }
4309 rc = bnxt_setup_vnic(bp, vnic_id);
4310 if (rc)
4311 break;
4312 }
4313 return rc;
4314#else
4315 return 0;
4316#endif
4317}
4318
b664f008 4319static int bnxt_cfg_rx_mode(struct bnxt *);
7d2837dd 4320static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
b664f008 4321
c0c050c5
MC		 4322static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4323{
7d2837dd 4324 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
c0c050c5
MC		 4325 int rc = 0;
4326
4327 if (irq_re_init) {
4328 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4329 if (rc) {
4330 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4331 rc);
4332 goto err_out;
4333 }
4334 }
4335
4336 rc = bnxt_hwrm_ring_alloc(bp);
4337 if (rc) {
4338 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4339 goto err_out;
4340 }
4341
4342 rc = bnxt_hwrm_ring_grp_alloc(bp);
4343 if (rc) {
4344 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4345 goto err_out;
4346 }
4347
4348 /* default vnic 0 */
4349 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
4350 if (rc) {
4351 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4352 goto err_out;
4353 }
4354
4355 rc = bnxt_setup_vnic(bp, 0);
4356 if (rc)
4357 goto err_out;
4358
4359 if (bp->flags & BNXT_FLAG_RFS) {
4360 rc = bnxt_alloc_rfs_vnics(bp);
4361 if (rc)
4362 goto err_out;
4363 }
4364
4365 if (bp->flags & BNXT_FLAG_TPA) {
4366 rc = bnxt_set_tpa(bp, true);
4367 if (rc)
4368 goto err_out;
4369 }
4370
4371 if (BNXT_VF(bp))
4372 bnxt_update_vf_mac(bp);
4373
4374 /* Filter for default vnic 0 */
4375 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4376 if (rc) {
4377 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4378 goto err_out;
4379 }
7d2837dd 4380 vnic->uc_filter_count = 1;
c0c050c5 4381
7d2837dd 4382 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5
MC		 4383
4384 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
7d2837dd
MC		 4385 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4386
4387 if (bp->dev->flags & IFF_ALLMULTI) {
4388 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4389 vnic->mc_list_count = 0;
4390 } else {
4391 u32 mask = 0;
4392
4393 bnxt_mc_list_updated(bp, &mask);
4394 vnic->rx_mask |= mask;
4395 }
c0c050c5 4396
b664f008
MC		 4397 rc = bnxt_cfg_rx_mode(bp);
4398 if (rc)
c0c050c5 4399 goto err_out;
c0c050c5
MC		 4400
4401 rc = bnxt_hwrm_set_coal(bp);
4402 if (rc)
4403 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4404 rc);
4405
cf6645f8
MC		 4406 if (BNXT_VF(bp)) {
4407 bnxt_hwrm_func_qcfg(bp);
4408 netdev_update_features(bp->dev);
4409 }
4410
c0c050c5
MC		 4411 return 0;
4412
4413err_out:
4414 bnxt_hwrm_resource_free(bp, 0, true);
4415
4416 return rc;
4417}
4418
4419static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4420{
4421 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4422 return 0;
4423}
4424
4425static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4426{
4427 bnxt_init_rx_rings(bp);
4428 bnxt_init_tx_rings(bp);
4429 bnxt_init_ring_grps(bp, irq_re_init);
4430 bnxt_init_vnics(bp);
4431
4432 return bnxt_init_chip(bp, irq_re_init);
4433}
4434
4435static void bnxt_disable_int(struct bnxt *bp)
4436{
4437 int i;
4438
4439 if (!bp->bnapi)
4440 return;
4441
4442 for (i = 0; i < bp->cp_nr_rings; i++) {
4443 struct bnxt_napi *bnapi = bp->bnapi[i];
4444 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4445
4446 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4447 }
4448}
4449
4450static void bnxt_enable_int(struct bnxt *bp)
4451{
4452 int i;
4453
4454 atomic_set(&bp->intr_sem, 0);
4455 for (i = 0; i < bp->cp_nr_rings; i++) {
4456 struct bnxt_napi *bnapi = bp->bnapi[i];
4457 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4458
4459 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4460 }
4461}
4462
4463static int bnxt_set_real_num_queues(struct bnxt *bp)
4464{
4465 int rc;
4466 struct net_device *dev = bp->dev;
4467
4468 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4469 if (rc)
4470 return rc;
4471
4472 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4473 if (rc)
4474 return rc;
4475
4476#ifdef CONFIG_RFS_ACCEL
45019a18 4477 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 4478 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 4479#endif
4480
4481 return rc;
4482}
4483
6e6c5a57
MC		 4484static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4485 bool shared)
4486{
4487 int _rx = *rx, _tx = *tx;
4488
4489 if (shared) {
4490 *rx = min_t(int, _rx, max);
4491 *tx = min_t(int, _tx, max);
4492 } else {
4493 if (max < 2)
4494 return -ENOMEM;
4495
4496 while (_rx + _tx > max) {
4497 if (_rx > _tx && _rx > 1)
4498 _rx--;
4499 else if (_tx > 1)
4500 _tx--;
4501 }
4502 *rx = _rx;
4503 *tx = _tx;
4504 }
4505 return 0;
4506}
4507
c0c050c5
MC		 4508static int bnxt_setup_msix(struct bnxt *bp)
4509{
4510 struct msix_entry *msix_ent;
4511 struct net_device *dev = bp->dev;
01657bcd 4512 int i, total_vecs, rc = 0, min = 1;
c0c050c5
MC		 4513 const int len = sizeof(bp->irq_tbl[0].name);
4514
4515 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4516 total_vecs = bp->cp_nr_rings;
4517
4518 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4519 if (!msix_ent)
4520 return -ENOMEM;
4521
4522 for (i = 0; i < total_vecs; i++) {
4523 msix_ent[i].entry = i;
4524 msix_ent[i].vector = 0;
4525 }
4526
01657bcd
MC		 4527 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4528 min = 2;
4529
4530 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
c0c050c5
MC		 4531 if (total_vecs < 0) {
4532 rc = -ENODEV;
4533 goto msix_setup_exit;
4534 }
4535
4536 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4537 if (bp->irq_tbl) {
4538 int tcs;
4539
4540 /* Trim rings based upon num of vectors allocated */
6e6c5a57 4541 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
01657bcd 4542 total_vecs, min == 1);
6e6c5a57
MC		 4543 if (rc)
4544 goto msix_setup_exit;
4545
c0c050c5
MC		 4546 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4547 tcs = netdev_get_num_tc(dev);
4548 if (tcs > 1) {
4549 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4550 if (bp->tx_nr_rings_per_tc == 0) {
4551 netdev_reset_tc(dev);
4552 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4553 } else {
4554 int i, off, count;
4555
4556 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4557 for (i = 0; i < tcs; i++) {
4558 count = bp->tx_nr_rings_per_tc;
4559 off = i * count;
4560 netdev_set_tc_queue(dev, i, count, off);
4561 }
4562 }
4563 }
01657bcd 4564 bp->cp_nr_rings = total_vecs;
c0c050c5
MC		 4565
4566 for (i = 0; i < bp->cp_nr_rings; i++) {
01657bcd
MC		 4567 char *attr;
4568
c0c050c5 4569 bp->irq_tbl[i].vector = msix_ent[i].vector;
01657bcd
MC		 4570 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4571 attr = "TxRx";
4572 else if (i < bp->rx_nr_rings)
4573 attr = "rx";
4574 else
4575 attr = "tx";
4576
c0c050c5 4577 snprintf(bp->irq_tbl[i].name, len,
01657bcd 4578 "%s-%s-%d", dev->name, attr, i);
c0c050c5
MC		 4579 bp->irq_tbl[i].handler = bnxt_msix;
4580 }
4581 rc = bnxt_set_real_num_queues(bp);
4582 if (rc)
4583 goto msix_setup_exit;
4584 } else {
4585 rc = -ENOMEM;
4586 goto msix_setup_exit;
4587 }
4588 bp->flags |= BNXT_FLAG_USING_MSIX;
4589 kfree(msix_ent);
4590 return 0;
4591
4592msix_setup_exit:
4593 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4594 pci_disable_msix(bp->pdev);
4595 kfree(msix_ent);
4596 return rc;
4597}
4598
4599static int bnxt_setup_inta(struct bnxt *bp)
4600{
4601 int rc;
4602 const int len = sizeof(bp->irq_tbl[0].name);
4603
4604 if (netdev_get_num_tc(bp->dev))
4605 netdev_reset_tc(bp->dev);
4606
4607 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4608 if (!bp->irq_tbl) {
4609 rc = -ENOMEM;
4610 return rc;
4611 }
4612 bp->rx_nr_rings = 1;
4613 bp->tx_nr_rings = 1;
4614 bp->cp_nr_rings = 1;
4615 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
01657bcd 4616 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5
MC		 4617 bp->irq_tbl[0].vector = bp->pdev->irq;
4618 snprintf(bp->irq_tbl[0].name, len,
4619 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4620 bp->irq_tbl[0].handler = bnxt_inta;
4621 rc = bnxt_set_real_num_queues(bp);
4622 return rc;
4623}
4624
4625static int bnxt_setup_int_mode(struct bnxt *bp)
4626{
4627 int rc = 0;
4628
4629 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4630 rc = bnxt_setup_msix(bp);
4631
1fa72e29 4632 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
c0c050c5
MC		 4633 /* fallback to INTA */
4634 rc = bnxt_setup_inta(bp);
4635 }
4636 return rc;
4637}
4638
4639static void bnxt_free_irq(struct bnxt *bp)
4640{
4641 struct bnxt_irq *irq;
4642 int i;
4643
4644#ifdef CONFIG_RFS_ACCEL
4645 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4646 bp->dev->rx_cpu_rmap = NULL;
4647#endif
4648 if (!bp->irq_tbl)
4649 return;
4650
4651 for (i = 0; i < bp->cp_nr_rings; i++) {
4652 irq = &bp->irq_tbl[i];
4653 if (irq->requested)
4654 free_irq(irq->vector, bp->bnapi[i]);
4655 irq->requested = 0;
4656 }
4657 if (bp->flags & BNXT_FLAG_USING_MSIX)
4658 pci_disable_msix(bp->pdev);
4659 kfree(bp->irq_tbl);
4660 bp->irq_tbl = NULL;
4661}
4662
4663static int bnxt_request_irq(struct bnxt *bp)
4664{
b81a90d3 4665 int i, j, rc = 0;
c0c050c5
MC		 4666 unsigned long flags = 0;
4667#ifdef CONFIG_RFS_ACCEL
4668 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4669#endif
4670
4671 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4672 flags = IRQF_SHARED;
4673
b81a90d3 4674 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
c0c050c5
MC		 4675 struct bnxt_irq *irq = &bp->irq_tbl[i];
4676#ifdef CONFIG_RFS_ACCEL
b81a90d3 4677 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 4678 rc = irq_cpu_rmap_add(rmap, irq->vector);
4679 if (rc)
4680 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 4681 j);
4682 j++;
c0c050c5
MC		 4683 }
4684#endif
4685 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4686 bp->bnapi[i]);
4687 if (rc)
4688 break;
4689
4690 irq->requested = 1;
4691 }
4692 return rc;
4693}
4694
4695static void bnxt_del_napi(struct bnxt *bp)
4696{
4697 int i;
4698
4699 if (!bp->bnapi)
4700 return;
4701
4702 for (i = 0; i < bp->cp_nr_rings; i++) {
4703 struct bnxt_napi *bnapi = bp->bnapi[i];
4704
4705 napi_hash_del(&bnapi->napi);
4706 netif_napi_del(&bnapi->napi);
4707 }
4708}
4709
4710static void bnxt_init_napi(struct bnxt *bp)
4711{
4712 int i;
4713 struct bnxt_napi *bnapi;
4714
4715 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4716 for (i = 0; i < bp->cp_nr_rings; i++) {
4717 bnapi = bp->bnapi[i];
4718 netif_napi_add(bp->dev, &bnapi->napi,
4719 bnxt_poll, 64);
c0c050c5
MC		 4720 }
4721 } else {
4722 bnapi = bp->bnapi[0];
4723 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 4724 }
4725}
4726
4727static void bnxt_disable_napi(struct bnxt *bp)
4728{
4729 int i;
4730
4731 if (!bp->bnapi)
4732 return;
4733
4734 for (i = 0; i < bp->cp_nr_rings; i++) {
4735 napi_disable(&bp->bnapi[i]->napi);
4736 bnxt_disable_poll(bp->bnapi[i]);
4737 }
4738}
4739
4740static void bnxt_enable_napi(struct bnxt *bp)
4741{
4742 int i;
4743
4744 for (i = 0; i < bp->cp_nr_rings; i++) {
fa7e2812 4745 bp->bnapi[i]->in_reset = false;
c0c050c5
MC		 4746 bnxt_enable_poll(bp->bnapi[i]);
4747 napi_enable(&bp->bnapi[i]->napi);
4748 }
4749}
4750
4751static void bnxt_tx_disable(struct bnxt *bp)
4752{
4753 int i;
c0c050c5
MC		 4754 struct bnxt_tx_ring_info *txr;
4755 struct netdev_queue *txq;
4756
b6ab4b01 4757 if (bp->tx_ring) {
c0c050c5 4758 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4759 txr = &bp->tx_ring[i];
c0c050c5
MC		 4760 txq = netdev_get_tx_queue(bp->dev, i);
4761 __netif_tx_lock(txq, smp_processor_id());
4762 txr->dev_state = BNXT_DEV_STATE_CLOSING;
4763 __netif_tx_unlock(txq);
4764 }
4765 }
4766 /* Stop all TX queues */
4767 netif_tx_disable(bp->dev);
4768 netif_carrier_off(bp->dev);
4769}
4770
4771static void bnxt_tx_enable(struct bnxt *bp)
4772{
4773 int i;
c0c050c5
MC		 4774 struct bnxt_tx_ring_info *txr;
4775 struct netdev_queue *txq;
4776
4777 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4778 txr = &bp->tx_ring[i];
c0c050c5
MC		 4779 txq = netdev_get_tx_queue(bp->dev, i);
4780 txr->dev_state = 0;
4781 }
4782 netif_tx_wake_all_queues(bp->dev);
4783 if (bp->link_info.link_up)
4784 netif_carrier_on(bp->dev);
4785}
4786
4787static void bnxt_report_link(struct bnxt *bp)
4788{
4789 if (bp->link_info.link_up) {
4790 const char *duplex;
4791 const char *flow_ctrl;
4792 u16 speed;
4793
4794 netif_carrier_on(bp->dev);
4795 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4796 duplex = "full";
4797 else
4798 duplex = "half";
4799 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4800 flow_ctrl = "ON - receive & transmit";
4801 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4802 flow_ctrl = "ON - transmit";
4803 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4804 flow_ctrl = "ON - receive";
4805 else
4806 flow_ctrl = "none";
4807 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4808 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4809 speed, duplex, flow_ctrl);
170ce013
MC		 4810 if (bp->flags & BNXT_FLAG_EEE_CAP)
4811 netdev_info(bp->dev, "EEE is %s\n",
4812 bp->eee.eee_active ? "active" :
4813 "not active");
c0c050c5
MC		 4814 } else {
4815 netif_carrier_off(bp->dev);
4816 netdev_err(bp->dev, "NIC Link is Down\n");
4817 }
4818}
4819
170ce013
MC		 4820static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
4821{
4822 int rc = 0;
4823 struct hwrm_port_phy_qcaps_input req = {0};
4824 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
93ed8117 4825 struct bnxt_link_info *link_info = &bp->link_info;
170ce013
MC		 4826
4827 if (bp->hwrm_spec_code < 0x10201)
4828 return 0;
4829
4830 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
4831
4832 mutex_lock(&bp->hwrm_cmd_lock);
4833 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4834 if (rc)
4835 goto hwrm_phy_qcaps_exit;
4836
4837 if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
4838 struct ethtool_eee *eee = &bp->eee;
4839 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
4840
4841 bp->flags |= BNXT_FLAG_EEE_CAP;
4842 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4843 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
4844 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
4845 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
4846 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
4847 }
93ed8117
MC		 4848 link_info->support_auto_speeds =
4849 le16_to_cpu(resp->supported_speeds_auto_mode);
170ce013
MC		 4850
4851hwrm_phy_qcaps_exit:
4852 mutex_unlock(&bp->hwrm_cmd_lock);
4853 return rc;
4854}
4855
c0c050c5
MC		 4856static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4857{
4858 int rc = 0;
4859 struct bnxt_link_info *link_info = &bp->link_info;
4860 struct hwrm_port_phy_qcfg_input req = {0};
4861 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4862 u8 link_up = link_info->link_up;
4863
4864 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4865
4866 mutex_lock(&bp->hwrm_cmd_lock);
4867 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4868 if (rc) {
4869 mutex_unlock(&bp->hwrm_cmd_lock);
4870 return rc;
4871 }
4872
4873 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4874 link_info->phy_link_status = resp->link;
4875 link_info->duplex = resp->duplex;
4876 link_info->pause = resp->pause;
4877 link_info->auto_mode = resp->auto_mode;
4878 link_info->auto_pause_setting = resp->auto_pause;
3277360e 4879 link_info->lp_pause = resp->link_partner_adv_pause;
c0c050c5 4880 link_info->force_pause_setting = resp->force_pause;
c193554e 4881 link_info->duplex_setting = resp->duplex;
c0c050c5
MC		 4882 if (link_info->phy_link_status == BNXT_LINK_LINK)
4883 link_info->link_speed = le16_to_cpu(resp->link_speed);
4884 else
4885 link_info->link_speed = 0;
4886 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
c0c050c5
MC		 4887 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4888 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
3277360e
MC		 4889 link_info->lp_auto_link_speeds =
4890 le16_to_cpu(resp->link_partner_adv_speeds);
c0c050c5
MC		 4891 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4892 link_info->phy_ver[0] = resp->phy_maj;
4893 link_info->phy_ver[1] = resp->phy_min;
4894 link_info->phy_ver[2] = resp->phy_bld;
4895 link_info->media_type = resp->media_type;
03efbec0 4896 link_info->phy_type = resp->phy_type;
11f15ed3 4897 link_info->transceiver = resp->xcvr_pkg_type;
170ce013
MC		 4898 link_info->phy_addr = resp->eee_config_phy_addr &
4899 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
42ee18fe 4900 link_info->module_status = resp->module_status;
170ce013
MC		 4901
4902 if (bp->flags & BNXT_FLAG_EEE_CAP) {
4903 struct ethtool_eee *eee = &bp->eee;
4904 u16 fw_speeds;
4905
4906 eee->eee_active = 0;
4907 if (resp->eee_config_phy_addr &
4908 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
4909 eee->eee_active = 1;
4910 fw_speeds = le16_to_cpu(
4911 resp->link_partner_adv_eee_link_speed_mask);
4912 eee->lp_advertised =
4913 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4914 }
4915
4916 /* Pull initial EEE config */
4917 if (!chng_link_state) {
4918 if (resp->eee_config_phy_addr &
4919 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
4920 eee->eee_enabled = 1;
c0c050c5 4921
170ce013
MC		 4922 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
4923 eee->advertised =
4924 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4925
4926 if (resp->eee_config_phy_addr &
4927 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
4928 __le32 tmr;
4929
4930 eee->tx_lpi_enabled = 1;
4931 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
4932 eee->tx_lpi_timer = le32_to_cpu(tmr) &
4933 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
4934 }
4935 }
4936 }
c0c050c5
MC		 4937 /* TODO: need to add more logic to report VF link */
4938 if (chng_link_state) {
4939 if (link_info->phy_link_status == BNXT_LINK_LINK)
4940 link_info->link_up = 1;
4941 else
4942 link_info->link_up = 0;
4943 if (link_up != link_info->link_up)
4944 bnxt_report_link(bp);
4945 } else {
4946 /* alwasy link down if not require to update link state */
4947 link_info->link_up = 0;
4948 }
4949 mutex_unlock(&bp->hwrm_cmd_lock);
4950 return 0;
4951}
4952
10289bec
MC		 4953static void bnxt_get_port_module_status(struct bnxt *bp)
4954{
4955 struct bnxt_link_info *link_info = &bp->link_info;
4956 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
4957 u8 module_status;
4958
4959 if (bnxt_update_link(bp, true))
4960 return;
4961
4962 module_status = link_info->module_status;
4963 switch (module_status) {
4964 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
4965 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
4966 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
4967 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
4968 bp->pf.port_id);
4969 if (bp->hwrm_spec_code >= 0x10201) {
4970 netdev_warn(bp->dev, "Module part number %s\n",
4971 resp->phy_vendor_partnumber);
4972 }
4973 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
4974 netdev_warn(bp->dev, "TX is disabled\n");
4975 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
4976 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
4977 }
4978}
4979
c0c050c5
MC		 4980static void
4981bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4982{
4983 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
c9ee9516
MC		 4984 if (bp->hwrm_spec_code >= 0x10201)
4985 req->auto_pause =
4986 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
c0c050c5
MC		 4987 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4988 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4989 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
49b5c7a1 4990 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
c0c050c5
MC		 4991 req->enables |=
4992 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4993 } else {
4994 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4995 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4996 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4997 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4998 req->enables |=
4999 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
c9ee9516
MC		 5000 if (bp->hwrm_spec_code >= 0x10201) {
5001 req->auto_pause = req->force_pause;
5002 req->enables |= cpu_to_le32(
5003 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5004 }
c0c050c5
MC		 5005 }
5006}
5007
5008static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5009 struct hwrm_port_phy_cfg_input *req)
5010{
5011 u8 autoneg = bp->link_info.autoneg;
5012 u16 fw_link_speed = bp->link_info.req_link_speed;
5013 u32 advertising = bp->link_info.advertising;
5014
5015 if (autoneg & BNXT_AUTONEG_SPEED) {
5016 req->auto_mode |=
11f15ed3 5017 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
c0c050c5
MC		 5018
5019 req->enables |= cpu_to_le32(
5020 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5021 req->auto_link_speed_mask = cpu_to_le16(advertising);
5022
5023 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5024 req->flags |=
5025 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5026 } else {
5027 req->force_link_speed = cpu_to_le16(fw_link_speed);
5028 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5029 }
5030
c0c050c5
MC		 5031 /* tell chimp that the setting takes effect immediately */
5032 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5033}
5034
5035int bnxt_hwrm_set_pause(struct bnxt *bp)
5036{
5037 struct hwrm_port_phy_cfg_input req = {0};
5038 int rc;
5039
5040 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5041 bnxt_hwrm_set_pause_common(bp, &req);
5042
5043 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5044 bp->link_info.force_link_chng)
5045 bnxt_hwrm_set_link_common(bp, &req);
5046
5047 mutex_lock(&bp->hwrm_cmd_lock);
5048 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5049 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5050 /* since changing of pause setting doesn't trigger any link
5051 * change event, the driver needs to update the current pause
5052 * result upon successfully return of the phy_cfg command
5053 */
5054 bp->link_info.pause =
5055 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5056 bp->link_info.auto_pause_setting = 0;
5057 if (!bp->link_info.force_link_chng)
5058 bnxt_report_link(bp);
5059 }
5060 bp->link_info.force_link_chng = false;
5061 mutex_unlock(&bp->hwrm_cmd_lock);
5062 return rc;
5063}
5064
939f7f0c
MC		 5065static void bnxt_hwrm_set_eee(struct bnxt *bp,
5066 struct hwrm_port_phy_cfg_input *req)
5067{
5068 struct ethtool_eee *eee = &bp->eee;
5069
5070 if (eee->eee_enabled) {
5071 u16 eee_speeds;
5072 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5073
5074 if (eee->tx_lpi_enabled)
5075 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5076 else
5077 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5078
5079 req->flags |= cpu_to_le32(flags);
5080 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5081 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5082 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5083 } else {
5084 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5085 }
5086}
5087
5088int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
c0c050c5
MC		 5089{
5090 struct hwrm_port_phy_cfg_input req = {0};
5091
5092 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5093 if (set_pause)
5094 bnxt_hwrm_set_pause_common(bp, &req);
5095
5096 bnxt_hwrm_set_link_common(bp, &req);
939f7f0c
MC		 5097
5098 if (set_eee)
5099 bnxt_hwrm_set_eee(bp, &req);
c0c050c5
MC		 5100 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5101}
5102
33f7d55f
MC		 5103static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5104{
5105 struct hwrm_port_phy_cfg_input req = {0};
5106
567b2abe 5107 if (!BNXT_SINGLE_PF(bp))
33f7d55f
MC		 5108 return 0;
5109
5110 if (pci_num_vf(bp->pdev))
5111 return 0;
5112
5113 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5114 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN);
5115 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5116}
5117
939f7f0c
MC		 5118static bool bnxt_eee_config_ok(struct bnxt *bp)
5119{
5120 struct ethtool_eee *eee = &bp->eee;
5121 struct bnxt_link_info *link_info = &bp->link_info;
5122
5123 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5124 return true;
5125
5126 if (eee->eee_enabled) {
5127 u32 advertising =
5128 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5129
5130 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5131 eee->eee_enabled = 0;
5132 return false;
5133 }
5134 if (eee->advertised & ~advertising) {
5135 eee->advertised = advertising & eee->supported;
5136 return false;
5137 }
5138 }
5139 return true;
5140}
5141
c0c050c5
MC		 5142static int bnxt_update_phy_setting(struct bnxt *bp)
5143{
5144 int rc;
5145 bool update_link = false;
5146 bool update_pause = false;
939f7f0c 5147 bool update_eee = false;
c0c050c5
MC		 5148 struct bnxt_link_info *link_info = &bp->link_info;
5149
5150 rc = bnxt_update_link(bp, true);
5151 if (rc) {
5152 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5153 rc);
5154 return rc;
5155 }
5156 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
c9ee9516
MC		 5157 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5158 link_info->req_flow_ctrl)
c0c050c5
MC		 5159 update_pause = true;
5160 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5161 link_info->force_pause_setting != link_info->req_flow_ctrl)
5162 update_pause = true;
c0c050c5
MC		 5163 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5164 if (BNXT_AUTO_MODE(link_info->auto_mode))
5165 update_link = true;
5166 if (link_info->req_link_speed != link_info->force_link_speed)
5167 update_link = true;
de73018f
MC		 5168 if (link_info->req_duplex != link_info->duplex_setting)
5169 update_link = true;
c0c050c5
MC		 5170 } else {
5171 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5172 update_link = true;
5173 if (link_info->advertising != link_info->auto_link_speeds)
5174 update_link = true;
c0c050c5
MC		 5175 }
5176
939f7f0c
MC		 5177 if (!bnxt_eee_config_ok(bp))
5178 update_eee = true;
5179
c0c050c5 5180 if (update_link)
939f7f0c 5181 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
c0c050c5
MC		 5182 else if (update_pause)
5183 rc = bnxt_hwrm_set_pause(bp);
5184 if (rc) {
5185 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5186 rc);
5187 return rc;
5188 }
5189
5190 return rc;
5191}
5192
11809490
JH		 5193/* Common routine to pre-map certain register block to different GRC window.
5194 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5195 * in PF and 3 windows in VF that can be customized to map in different
5196 * register blocks.
5197 */
5198static void bnxt_preset_reg_win(struct bnxt *bp)
5199{
5200 if (BNXT_PF(bp)) {
5201 /* CAG registers map to GRC window #4 */
5202 writel(BNXT_CAG_REG_BASE,
5203 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5204 }
5205}
5206
c0c050c5
MC		 5207static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5208{
5209 int rc = 0;
5210
11809490 5211 bnxt_preset_reg_win(bp);
c0c050c5
MC		 5212 netif_carrier_off(bp->dev);
5213 if (irq_re_init) {
5214 rc = bnxt_setup_int_mode(bp);
5215 if (rc) {
5216 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5217 rc);
5218 return rc;
5219 }
5220 }
5221 if ((bp->flags & BNXT_FLAG_RFS) &&
5222 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5223 /* disable RFS if falling back to INTA */
5224 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5225 bp->flags &= ~BNXT_FLAG_RFS;
5226 }
5227
5228 rc = bnxt_alloc_mem(bp, irq_re_init);
5229 if (rc) {
5230 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5231 goto open_err_free_mem;
5232 }
5233
5234 if (irq_re_init) {
5235 bnxt_init_napi(bp);
5236 rc = bnxt_request_irq(bp);
5237 if (rc) {
5238 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5239 goto open_err;
5240 }
5241 }
5242
5243 bnxt_enable_napi(bp);
5244
5245 rc = bnxt_init_nic(bp, irq_re_init);
5246 if (rc) {
5247 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5248 goto open_err;
5249 }
5250
5251 if (link_re_init) {
5252 rc = bnxt_update_phy_setting(bp);
5253 if (rc)
ba41d46f 5254 netdev_warn(bp->dev, "failed to update phy settings\n");
c0c050c5
MC		 5255 }
5256
7cdd5fc3 5257 if (irq_re_init)
ad51b8e9 5258 udp_tunnel_get_rx_info(bp->dev);
c0c050c5 5259
caefe526 5260 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 5261 bnxt_enable_int(bp);
5262 /* Enable TX queues */
5263 bnxt_tx_enable(bp);
5264 mod_timer(&bp->timer, jiffies + bp->current_interval);
10289bec
MC		 5265 /* Poll link status and check for SFP+ module status */
5266 bnxt_get_port_module_status(bp);
c0c050c5
MC		 5267
5268 return 0;
5269
5270open_err:
5271 bnxt_disable_napi(bp);
5272 bnxt_del_napi(bp);
5273
5274open_err_free_mem:
5275 bnxt_free_skbs(bp);
5276 bnxt_free_irq(bp);
5277 bnxt_free_mem(bp, true);
5278 return rc;
5279}
5280
5281/* rtnl_lock held */
5282int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5283{
5284 int rc = 0;
5285
5286 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5287 if (rc) {
5288 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5289 dev_close(bp->dev);
5290 }
5291 return rc;
5292}
5293
5294static int bnxt_open(struct net_device *dev)
5295{
5296 struct bnxt *bp = netdev_priv(dev);
5297 int rc = 0;
5298
2a5bedfa
MC		 5299 if (!test_bit(BNXT_STATE_FN_RST_DONE, &bp->state)) {
5300 rc = bnxt_hwrm_func_reset(bp);
5301 if (rc) {
5302 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
5303 rc);
5304 rc = -EBUSY;
5305 return rc;
5306 }
5307 /* Do func_reset during the 1st PF open only to prevent killing
5308 * the VFs when the PF is brought down and up.
5309 */
5310 if (BNXT_PF(bp))
5311 set_bit(BNXT_STATE_FN_RST_DONE, &bp->state);
c0c050c5
MC		 5312 }
5313 return __bnxt_open_nic(bp, true, true);
5314}
5315
5316static void bnxt_disable_int_sync(struct bnxt *bp)
5317{
5318 int i;
5319
5320 atomic_inc(&bp->intr_sem);
5321 if (!netif_running(bp->dev))
5322 return;
5323
5324 bnxt_disable_int(bp);
5325 for (i = 0; i < bp->cp_nr_rings; i++)
5326 synchronize_irq(bp->irq_tbl[i].vector);
5327}
5328
5329int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5330{
5331 int rc = 0;
5332
5333#ifdef CONFIG_BNXT_SRIOV
5334 if (bp->sriov_cfg) {
5335 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5336 !bp->sriov_cfg,
5337 BNXT_SRIOV_CFG_WAIT_TMO);
5338 if (rc)
5339 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5340 }
5341#endif
5342 /* Change device state to avoid TX queue wake up's */
5343 bnxt_tx_disable(bp);
5344
caefe526 5345 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec
MC		 5346 smp_mb__after_atomic();
5347 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5348 msleep(20);
c0c050c5
MC		 5349
5350 /* Flush rings before disabling interrupts */
5351 bnxt_shutdown_nic(bp, irq_re_init);
5352
5353 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5354
5355 bnxt_disable_napi(bp);
5356 bnxt_disable_int_sync(bp);
5357 del_timer_sync(&bp->timer);
5358 bnxt_free_skbs(bp);
5359
5360 if (irq_re_init) {
5361 bnxt_free_irq(bp);
5362 bnxt_del_napi(bp);
5363 }
5364 bnxt_free_mem(bp, irq_re_init);
5365 return rc;
5366}
5367
5368static int bnxt_close(struct net_device *dev)
5369{
5370 struct bnxt *bp = netdev_priv(dev);
5371
5372 bnxt_close_nic(bp, true, true);
33f7d55f 5373 bnxt_hwrm_shutdown_link(bp);
c0c050c5
MC		 5374 return 0;
5375}
5376
5377/* rtnl_lock held */
5378static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5379{
5380 switch (cmd) {
5381 case SIOCGMIIPHY:
5382 /* fallthru */
5383 case SIOCGMIIREG: {
5384 if (!netif_running(dev))
5385 return -EAGAIN;
5386
5387 return 0;
5388 }
5389
5390 case SIOCSMIIREG:
5391 if (!netif_running(dev))
5392 return -EAGAIN;
5393
5394 return 0;
5395
5396 default:
5397 /* do nothing */
5398 break;
5399 }
5400 return -EOPNOTSUPP;
5401}
5402
5403static struct rtnl_link_stats64 *
5404bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5405{
5406 u32 i;
5407 struct bnxt *bp = netdev_priv(dev);
5408
5409 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5410
5411 if (!bp->bnapi)
5412 return stats;
5413
5414 /* TODO check if we need to synchronize with bnxt_close path */
5415 for (i = 0; i < bp->cp_nr_rings; i++) {
5416 struct bnxt_napi *bnapi = bp->bnapi[i];
5417 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5418 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
5419
5420 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
5421 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
5422 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
5423
5424 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
5425 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
5426 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
5427
5428 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
5429 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
5430 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
5431
5432 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
5433 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
5434 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
5435
5436 stats->rx_missed_errors +=
5437 le64_to_cpu(hw_stats->rx_discard_pkts);
5438
5439 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
5440
c0c050c5
MC		 5441 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
5442 }
5443
9947f83f
MC		 5444 if (bp->flags & BNXT_FLAG_PORT_STATS) {
5445 struct rx_port_stats *rx = bp->hw_rx_port_stats;
5446 struct tx_port_stats *tx = bp->hw_tx_port_stats;
5447
5448 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
5449 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
5450 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
5451 le64_to_cpu(rx->rx_ovrsz_frames) +
5452 le64_to_cpu(rx->rx_runt_frames);
5453 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
5454 le64_to_cpu(rx->rx_jbr_frames);
5455 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
5456 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
5457 stats->tx_errors = le64_to_cpu(tx->tx_err);
5458 }
5459
c0c050c5
MC		 5460 return stats;
5461}
5462
5463static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
5464{
5465 struct net_device *dev = bp->dev;
5466 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5467 struct netdev_hw_addr *ha;
5468 u8 *haddr;
5469 int mc_count = 0;
5470 bool update = false;
5471 int off = 0;
5472
5473 netdev_for_each_mc_addr(ha, dev) {
5474 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5475 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5476 vnic->mc_list_count = 0;
5477 return false;
5478 }
5479 haddr = ha->addr;
5480 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5481 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5482 update = true;
5483 }
5484 off += ETH_ALEN;
5485 mc_count++;
5486 }
5487 if (mc_count)
5488 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5489
5490 if (mc_count != vnic->mc_list_count) {
5491 vnic->mc_list_count = mc_count;
5492 update = true;
5493 }
5494 return update;
5495}
5496
5497static bool bnxt_uc_list_updated(struct bnxt *bp)
5498{
5499 struct net_device *dev = bp->dev;
5500 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5501 struct netdev_hw_addr *ha;
5502 int off = 0;
5503
5504 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5505 return true;
5506
5507 netdev_for_each_uc_addr(ha, dev) {
5508 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5509 return true;
5510
5511 off += ETH_ALEN;
5512 }
5513 return false;
5514}
5515
5516static void bnxt_set_rx_mode(struct net_device *dev)
5517{
5518 struct bnxt *bp = netdev_priv(dev);
5519 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5520 u32 mask = vnic->rx_mask;
5521 bool mc_update = false;
5522 bool uc_update;
5523
5524 if (!netif_running(dev))
5525 return;
5526
5527 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5528 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5529 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5530
5531 /* Only allow PF to be in promiscuous mode */
5532 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
5533 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5534
5535 uc_update = bnxt_uc_list_updated(bp);
5536
5537 if (dev->flags & IFF_ALLMULTI) {
5538 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5539 vnic->mc_list_count = 0;
5540 } else {
5541 mc_update = bnxt_mc_list_updated(bp, &mask);
5542 }
5543
5544 if (mask != vnic->rx_mask || uc_update || mc_update) {
5545 vnic->rx_mask = mask;
5546
5547 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5548 schedule_work(&bp->sp_task);
5549 }
5550}
5551
b664f008 5552static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 5553{
5554 struct net_device *dev = bp->dev;
5555 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5556 struct netdev_hw_addr *ha;
5557 int i, off = 0, rc;
5558 bool uc_update;
5559
5560 netif_addr_lock_bh(dev);
5561 uc_update = bnxt_uc_list_updated(bp);
5562 netif_addr_unlock_bh(dev);
5563
5564 if (!uc_update)
5565 goto skip_uc;
5566
5567 mutex_lock(&bp->hwrm_cmd_lock);
5568 for (i = 1; i < vnic->uc_filter_count; i++) {
5569 struct hwrm_cfa_l2_filter_free_input req = {0};
5570
5571 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5572 -1);
5573
5574 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5575
5576 rc = _hwrm_send_message(bp, &req, sizeof(req),
5577 HWRM_CMD_TIMEOUT);
5578 }
5579 mutex_unlock(&bp->hwrm_cmd_lock);
5580
5581 vnic->uc_filter_count = 1;
5582
5583 netif_addr_lock_bh(dev);
5584 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5585 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5586 } else {
5587 netdev_for_each_uc_addr(ha, dev) {
5588 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5589 off += ETH_ALEN;
5590 vnic->uc_filter_count++;
5591 }
5592 }
5593 netif_addr_unlock_bh(dev);
5594
5595 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5596 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5597 if (rc) {
5598 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5599 rc);
5600 vnic->uc_filter_count = i;
b664f008 5601 return rc;
c0c050c5
MC		 5602 }
5603 }
5604
5605skip_uc:
5606 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5607 if (rc)
5608 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5609 rc);
b664f008
MC		 5610
5611 return rc;
c0c050c5
MC		 5612}
5613
2bcfa6f6
MC		 5614static bool bnxt_rfs_capable(struct bnxt *bp)
5615{
5616#ifdef CONFIG_RFS_ACCEL
5617 struct bnxt_pf_info *pf = &bp->pf;
5618 int vnics;
5619
5620 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5621 return false;
5622
5623 vnics = 1 + bp->rx_nr_rings;
5624 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
5625 return false;
5626
5627 return true;
5628#else
5629 return false;
5630#endif
5631}
5632
c0c050c5
MC		 5633static netdev_features_t bnxt_fix_features(struct net_device *dev,
5634 netdev_features_t features)
5635{
2bcfa6f6
MC		 5636 struct bnxt *bp = netdev_priv(dev);
5637
5638 if (!bnxt_rfs_capable(bp))
5639 features &= ~NETIF_F_NTUPLE;
5a9f6b23
MC		 5640
5641 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
5642 * turned on or off together.
5643 */
5644 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
5645 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
5646 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
5647 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5648 NETIF_F_HW_VLAN_STAG_RX);
5649 else
5650 features |= NETIF_F_HW_VLAN_CTAG_RX |
5651 NETIF_F_HW_VLAN_STAG_RX;
5652 }
cf6645f8
MC		 5653#ifdef CONFIG_BNXT_SRIOV
5654 if (BNXT_VF(bp)) {
5655 if (bp->vf.vlan) {
5656 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5657 NETIF_F_HW_VLAN_STAG_RX);
5658 }
5659 }
5660#endif
c0c050c5
MC		 5661 return features;
5662}
5663
5664static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5665{
5666 struct bnxt *bp = netdev_priv(dev);
5667 u32 flags = bp->flags;
5668 u32 changes;
5669 int rc = 0;
5670 bool re_init = false;
5671 bool update_tpa = false;
5672
5673 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5674 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5675 flags |= BNXT_FLAG_GRO;
5676 if (features & NETIF_F_LRO)
5677 flags |= BNXT_FLAG_LRO;
5678
5679 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5680 flags |= BNXT_FLAG_STRIP_VLAN;
5681
5682 if (features & NETIF_F_NTUPLE)
5683 flags |= BNXT_FLAG_RFS;
5684
5685 changes = flags ^ bp->flags;
5686 if (changes & BNXT_FLAG_TPA) {
5687 update_tpa = true;
5688 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5689 (flags & BNXT_FLAG_TPA) == 0)
5690 re_init = true;
5691 }
5692
5693 if (changes & ~BNXT_FLAG_TPA)
5694 re_init = true;
5695
5696 if (flags != bp->flags) {
5697 u32 old_flags = bp->flags;
5698
5699 bp->flags = flags;
5700
2bcfa6f6 5701 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 5702 if (update_tpa)
5703 bnxt_set_ring_params(bp);
5704 return rc;
5705 }
5706
5707 if (re_init) {
5708 bnxt_close_nic(bp, false, false);
5709 if (update_tpa)
5710 bnxt_set_ring_params(bp);
5711
5712 return bnxt_open_nic(bp, false, false);
5713 }
5714 if (update_tpa) {
5715 rc = bnxt_set_tpa(bp,
5716 (flags & BNXT_FLAG_TPA) ?
5717 true : false);
5718 if (rc)
5719 bp->flags = old_flags;
5720 }
5721 }
5722 return rc;
5723}
5724
9f554590
MC		 5725static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5726{
b6ab4b01 5727 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 5728 int i = bnapi->index;
5729
3b2b7d9d
MC		 5730 if (!txr)
5731 return;
5732
9f554590
MC		 5733 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5734 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5735 txr->tx_cons);
5736}
5737
5738static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5739{
b6ab4b01 5740 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 5741 int i = bnapi->index;
5742
3b2b7d9d
MC		 5743 if (!rxr)
5744 return;
5745
9f554590
MC		 5746 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5747 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5748 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5749 rxr->rx_sw_agg_prod);
5750}
5751
5752static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5753{
5754 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5755 int i = bnapi->index;
5756
5757 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5758 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5759}
5760
c0c050c5
MC		 5761static void bnxt_dbg_dump_states(struct bnxt *bp)
5762{
5763 int i;
5764 struct bnxt_napi *bnapi;
c0c050c5
MC		 5765
5766 for (i = 0; i < bp->cp_nr_rings; i++) {
5767 bnapi = bp->bnapi[i];
c0c050c5 5768 if (netif_msg_drv(bp)) {
9f554590
MC		 5769 bnxt_dump_tx_sw_state(bnapi);
5770 bnxt_dump_rx_sw_state(bnapi);
5771 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 5772 }
5773 }
5774}
5775
6988bd92 5776static void bnxt_reset_task(struct bnxt *bp, bool silent)
c0c050c5 5777{
6988bd92
MC		 5778 if (!silent)
5779 bnxt_dbg_dump_states(bp);
028de140
MC		 5780 if (netif_running(bp->dev)) {
5781 bnxt_close_nic(bp, false, false);
5782 bnxt_open_nic(bp, false, false);
5783 }
c0c050c5
MC		 5784}
5785
5786static void bnxt_tx_timeout(struct net_device *dev)
5787{
5788 struct bnxt *bp = netdev_priv(dev);
5789
5790 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
5791 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5792 schedule_work(&bp->sp_task);
5793}
5794
5795#ifdef CONFIG_NET_POLL_CONTROLLER
5796static void bnxt_poll_controller(struct net_device *dev)
5797{
5798 struct bnxt *bp = netdev_priv(dev);
5799 int i;
5800
5801 for (i = 0; i < bp->cp_nr_rings; i++) {
5802 struct bnxt_irq *irq = &bp->irq_tbl[i];
5803
5804 disable_irq(irq->vector);
5805 irq->handler(irq->vector, bp->bnapi[i]);
5806 enable_irq(irq->vector);
5807 }
5808}
5809#endif
5810
5811static void bnxt_timer(unsigned long data)
5812{
5813 struct bnxt *bp = (struct bnxt *)data;
5814 struct net_device *dev = bp->dev;
5815
5816 if (!netif_running(dev))
5817 return;
5818
5819 if (atomic_read(&bp->intr_sem) != 0)
5820 goto bnxt_restart_timer;
5821
3bdf56c4
MC		 5822 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
5823 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
5824 schedule_work(&bp->sp_task);
5825 }
c0c050c5
MC		 5826bnxt_restart_timer:
5827 mod_timer(&bp->timer, jiffies + bp->current_interval);
5828}
5829
6988bd92
MC		 5830/* Only called from bnxt_sp_task() */
5831static void bnxt_reset(struct bnxt *bp, bool silent)
5832{
5833 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5834 * for BNXT_STATE_IN_SP_TASK to clear.
5835 * If there is a parallel dev_close(), bnxt_close() may be holding
5836 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
5837 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
5838 */
5839 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5840 rtnl_lock();
5841 if (test_bit(BNXT_STATE_OPEN, &bp->state))
5842 bnxt_reset_task(bp, silent);
5843 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5844 rtnl_unlock();
5845}
5846
c0c050c5
MC		 5847static void bnxt_cfg_ntp_filters(struct bnxt *);
5848
5849static void bnxt_sp_task(struct work_struct *work)
5850{
5851 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5852 int rc;
5853
4cebdcec
MC		 5854 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5855 smp_mb__after_atomic();
5856 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5857 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 5858 return;
4cebdcec 5859 }
c0c050c5
MC		 5860
5861 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5862 bnxt_cfg_rx_mode(bp);
5863
5864 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5865 bnxt_cfg_ntp_filters(bp);
5866 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5867 rc = bnxt_update_link(bp, true);
5868 if (rc)
5869 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5870 rc);
5871 }
5872 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5873 bnxt_hwrm_exec_fwd_req(bp);
5874 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5875 bnxt_hwrm_tunnel_dst_port_alloc(
5876 bp, bp->vxlan_port,
5877 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5878 }
5879 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5880 bnxt_hwrm_tunnel_dst_port_free(
5881 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5882 }
7cdd5fc3
AD		 5883 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5884 bnxt_hwrm_tunnel_dst_port_alloc(
5885 bp, bp->nge_port,
5886 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5887 }
5888 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5889 bnxt_hwrm_tunnel_dst_port_free(
5890 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5891 }
6988bd92
MC		 5892 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
5893 bnxt_reset(bp, false);
4cebdcec 5894
fc0f1929
MC		 5895 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
5896 bnxt_reset(bp, true);
5897
4bb13abf 5898 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event))
10289bec 5899 bnxt_get_port_module_status(bp);
4bb13abf 5900
3bdf56c4
MC		 5901 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
5902 bnxt_hwrm_port_qstats(bp);
5903
4cebdcec
MC		 5904 smp_mb__before_atomic();
5905 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 5906}
5907
5908static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5909{
5910 int rc;
5911 struct bnxt *bp = netdev_priv(dev);
5912
5913 SET_NETDEV_DEV(dev, &pdev->dev);
5914
5915 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5916 rc = pci_enable_device(pdev);
5917 if (rc) {
5918 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5919 goto init_err;
5920 }
5921
5922 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5923 dev_err(&pdev->dev,
5924 "Cannot find PCI device base address, aborting\n");
5925 rc = -ENODEV;
5926 goto init_err_disable;
5927 }
5928
5929 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5930 if (rc) {
5931 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5932 goto init_err_disable;
5933 }
5934
5935 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5936 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5937 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5938 goto init_err_disable;
5939 }
5940
5941 pci_set_master(pdev);
5942
5943 bp->dev = dev;
5944 bp->pdev = pdev;
5945
5946 bp->bar0 = pci_ioremap_bar(pdev, 0);
5947 if (!bp->bar0) {
5948 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5949 rc = -ENOMEM;
5950 goto init_err_release;
5951 }
5952
5953 bp->bar1 = pci_ioremap_bar(pdev, 2);
5954 if (!bp->bar1) {
5955 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5956 rc = -ENOMEM;
5957 goto init_err_release;
5958 }
5959
5960 bp->bar2 = pci_ioremap_bar(pdev, 4);
5961 if (!bp->bar2) {
5962 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5963 rc = -ENOMEM;
5964 goto init_err_release;
5965 }
5966
6316ea6d
SB		 5967 pci_enable_pcie_error_reporting(pdev);
5968
c0c050c5
MC		 5969 INIT_WORK(&bp->sp_task, bnxt_sp_task);
5970
5971 spin_lock_init(&bp->ntp_fltr_lock);
5972
5973 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5974 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5975
dfb5b894 5976 /* tick values in micro seconds */
dfc9c94a
MC		 5977 bp->rx_coal_ticks = 12;
5978 bp->rx_coal_bufs = 30;
dfb5b894
MC		 5979 bp->rx_coal_ticks_irq = 1;
5980 bp->rx_coal_bufs_irq = 2;
c0c050c5 5981
dfc9c94a
MC		 5982 bp->tx_coal_ticks = 25;
5983 bp->tx_coal_bufs = 30;
5984 bp->tx_coal_ticks_irq = 2;
5985 bp->tx_coal_bufs_irq = 2;
5986
c0c050c5
MC		 5987 init_timer(&bp->timer);
5988 bp->timer.data = (unsigned long)bp;
5989 bp->timer.function = bnxt_timer;
5990 bp->current_interval = BNXT_TIMER_INTERVAL;
5991
caefe526 5992 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 5993
5994 return 0;
5995
5996init_err_release:
5997 if (bp->bar2) {
5998 pci_iounmap(pdev, bp->bar2);
5999 bp->bar2 = NULL;
6000 }
6001
6002 if (bp->bar1) {
6003 pci_iounmap(pdev, bp->bar1);
6004 bp->bar1 = NULL;
6005 }
6006
6007 if (bp->bar0) {
6008 pci_iounmap(pdev, bp->bar0);
6009 bp->bar0 = NULL;
6010 }
6011
6012 pci_release_regions(pdev);
6013
6014init_err_disable:
6015 pci_disable_device(pdev);
6016
6017init_err:
6018 return rc;
6019}
6020
6021/* rtnl_lock held */
6022static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6023{
6024 struct sockaddr *addr = p;
1fc2cfd0
JH		 6025 struct bnxt *bp = netdev_priv(dev);
6026 int rc = 0;
c0c050c5
MC		 6027
6028 if (!is_valid_ether_addr(addr->sa_data))
6029 return -EADDRNOTAVAIL;
6030
84c33dd3
MC		 6031 rc = bnxt_approve_mac(bp, addr->sa_data);
6032 if (rc)
6033 return rc;
bdd4347b 6034
1fc2cfd0
JH		 6035 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6036 return 0;
6037
c0c050c5 6038 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 6039 if (netif_running(dev)) {
6040 bnxt_close_nic(bp, false, false);
6041 rc = bnxt_open_nic(bp, false, false);
6042 }
c0c050c5 6043
1fc2cfd0 6044 return rc;
c0c050c5
MC		 6045}
6046
6047/* rtnl_lock held */
6048static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6049{
6050 struct bnxt *bp = netdev_priv(dev);
6051
6052 if (new_mtu < 60 || new_mtu > 9000)
6053 return -EINVAL;
6054
6055 if (netif_running(dev))
6056 bnxt_close_nic(bp, false, false);
6057
6058 dev->mtu = new_mtu;
6059 bnxt_set_ring_params(bp);
6060
6061 if (netif_running(dev))
6062 return bnxt_open_nic(bp, false, false);
6063
6064 return 0;
6065}
6066
16e5cc64
JF		 6067static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6068 struct tc_to_netdev *ntc)
c0c050c5
MC		 6069{
6070 struct bnxt *bp = netdev_priv(dev);
16e5cc64 6071 u8 tc;
c0c050c5 6072
5eb4dce3 6073 if (ntc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 6074 return -EINVAL;
6075
16e5cc64
JF		 6076 tc = ntc->tc;
6077
c0c050c5
MC		 6078 if (tc > bp->max_tc) {
6079 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
6080 tc, bp->max_tc);
6081 return -EINVAL;
6082 }
6083
6084 if (netdev_get_num_tc(dev) == tc)
6085 return 0;
6086
6087 if (tc) {
6e6c5a57 6088 int max_rx_rings, max_tx_rings, rc;
01657bcd
MC		 6089 bool sh = false;
6090
6091 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6092 sh = true;
c0c050c5 6093
01657bcd 6094 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57 6095 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
c0c050c5
MC		 6096 return -ENOMEM;
6097 }
6098
6099 /* Needs to close the device and do hw resource re-allocations */
6100 if (netif_running(bp->dev))
6101 bnxt_close_nic(bp, true, false);
6102
6103 if (tc) {
6104 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6105 netdev_set_num_tc(dev, tc);
6106 } else {
6107 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6108 netdev_reset_tc(dev);
6109 }
6110 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
6111 bp->num_stat_ctxs = bp->cp_nr_rings;
6112
6113 if (netif_running(bp->dev))
6114 return bnxt_open_nic(bp, true, false);
6115
6116 return 0;
6117}
6118
6119#ifdef CONFIG_RFS_ACCEL
6120static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6121 struct bnxt_ntuple_filter *f2)
6122{
6123 struct flow_keys *keys1 = &f1->fkeys;
6124 struct flow_keys *keys2 = &f2->fkeys;
6125
6126 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6127 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6128 keys1->ports.ports == keys2->ports.ports &&
6129 keys1->basic.ip_proto == keys2->basic.ip_proto &&
6130 keys1->basic.n_proto == keys2->basic.n_proto &&
6131 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
6132 return true;
6133
6134 return false;
6135}
6136
6137static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6138 u16 rxq_index, u32 flow_id)
6139{
6140 struct bnxt *bp = netdev_priv(dev);
6141 struct bnxt_ntuple_filter *fltr, *new_fltr;
6142 struct flow_keys *fkeys;
6143 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
84e86b98 6144 int rc = 0, idx, bit_id;
c0c050c5
MC		 6145 struct hlist_head *head;
6146
6147 if (skb->encapsulation)
6148 return -EPROTONOSUPPORT;
6149
6150 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6151 if (!new_fltr)
6152 return -ENOMEM;
6153
6154 fkeys = &new_fltr->fkeys;
6155 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6156 rc = -EPROTONOSUPPORT;
6157 goto err_free;
6158 }
6159
6160 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
6161 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6162 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6163 rc = -EPROTONOSUPPORT;
6164 goto err_free;
6165 }
6166
6167 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6168
6169 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6170 head = &bp->ntp_fltr_hash_tbl[idx];
6171 rcu_read_lock();
6172 hlist_for_each_entry_rcu(fltr, head, hash) {
6173 if (bnxt_fltr_match(fltr, new_fltr)) {
6174 rcu_read_unlock();
6175 rc = 0;
6176 goto err_free;
6177 }
6178 }
6179 rcu_read_unlock();
6180
6181 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 6182 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6183 BNXT_NTP_FLTR_MAX_FLTR, 0);
6184 if (bit_id < 0) {
c0c050c5
MC		 6185 spin_unlock_bh(&bp->ntp_fltr_lock);
6186 rc = -ENOMEM;
6187 goto err_free;
6188 }
6189
84e86b98 6190 new_fltr->sw_id = (u16)bit_id;
c0c050c5
MC		 6191 new_fltr->flow_id = flow_id;
6192 new_fltr->rxq = rxq_index;
6193 hlist_add_head_rcu(&new_fltr->hash, head);
6194 bp->ntp_fltr_count++;
6195 spin_unlock_bh(&bp->ntp_fltr_lock);
6196
6197 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6198 schedule_work(&bp->sp_task);
6199
6200 return new_fltr->sw_id;
6201
6202err_free:
6203 kfree(new_fltr);
6204 return rc;
6205}
6206
6207static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6208{
6209 int i;
6210
6211 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6212 struct hlist_head *head;
6213 struct hlist_node *tmp;
6214 struct bnxt_ntuple_filter *fltr;
6215 int rc;
6216
6217 head = &bp->ntp_fltr_hash_tbl[i];
6218 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6219 bool del = false;
6220
6221 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6222 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6223 fltr->flow_id,
6224 fltr->sw_id)) {
6225 bnxt_hwrm_cfa_ntuple_filter_free(bp,
6226 fltr);
6227 del = true;
6228 }
6229 } else {
6230 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6231 fltr);
6232 if (rc)
6233 del = true;
6234 else
6235 set_bit(BNXT_FLTR_VALID, &fltr->state);
6236 }
6237
6238 if (del) {
6239 spin_lock_bh(&bp->ntp_fltr_lock);
6240 hlist_del_rcu(&fltr->hash);
6241 bp->ntp_fltr_count--;
6242 spin_unlock_bh(&bp->ntp_fltr_lock);
6243 synchronize_rcu();
6244 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6245 kfree(fltr);
6246 }
6247 }
6248 }
19241368
JH		 6249 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6250 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 6251}
6252
6253#else
6254
6255static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6256{
6257}
6258
6259#endif /* CONFIG_RFS_ACCEL */
6260
ad51b8e9
AD		 6261static void bnxt_udp_tunnel_add(struct net_device *dev,
6262 struct udp_tunnel_info *ti)
c0c050c5
MC		 6263{
6264 struct bnxt *bp = netdev_priv(dev);
6265
ad51b8e9 6266 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 6267 return;
6268
ad51b8e9 6269 if (!netif_running(dev))
c0c050c5
MC		 6270 return;
6271
ad51b8e9
AD		 6272 switch (ti->type) {
6273 case UDP_TUNNEL_TYPE_VXLAN:
6274 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
6275 return;
c0c050c5 6276
ad51b8e9
AD		 6277 bp->vxlan_port_cnt++;
6278 if (bp->vxlan_port_cnt == 1) {
6279 bp->vxlan_port = ti->port;
6280 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
6281 schedule_work(&bp->sp_task);
6282 }
6283 break;
7cdd5fc3
AD		 6284 case UDP_TUNNEL_TYPE_GENEVE:
6285 if (bp->nge_port_cnt && bp->nge_port != ti->port)
6286 return;
6287
6288 bp->nge_port_cnt++;
6289 if (bp->nge_port_cnt == 1) {
6290 bp->nge_port = ti->port;
6291 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
6292 }
6293 break;
ad51b8e9
AD		 6294 default:
6295 return;
c0c050c5 6296 }
ad51b8e9
AD		 6297
6298 schedule_work(&bp->sp_task);
c0c050c5
MC		 6299}
6300
ad51b8e9
AD		 6301static void bnxt_udp_tunnel_del(struct net_device *dev,
6302 struct udp_tunnel_info *ti)
c0c050c5
MC		 6303{
6304 struct bnxt *bp = netdev_priv(dev);
6305
ad51b8e9 6306 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 6307 return;
6308
ad51b8e9 6309 if (!netif_running(dev))
c0c050c5
MC		 6310 return;
6311
ad51b8e9
AD		 6312 switch (ti->type) {
6313 case UDP_TUNNEL_TYPE_VXLAN:
6314 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
6315 return;
c0c050c5
MC		 6316 bp->vxlan_port_cnt--;
6317
ad51b8e9
AD		 6318 if (bp->vxlan_port_cnt != 0)
6319 return;
6320
6321 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
6322 break;
7cdd5fc3
AD		 6323 case UDP_TUNNEL_TYPE_GENEVE:
6324 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
6325 return;
6326 bp->nge_port_cnt--;
6327
6328 if (bp->nge_port_cnt != 0)
6329 return;
6330
6331 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
6332 break;
ad51b8e9
AD		 6333 default:
6334 return;
c0c050c5 6335 }
ad51b8e9
AD		 6336
6337 schedule_work(&bp->sp_task);
c0c050c5
MC		 6338}
6339
6340static const struct net_device_ops bnxt_netdev_ops = {
6341 .ndo_open = bnxt_open,
6342 .ndo_start_xmit = bnxt_start_xmit,
6343 .ndo_stop = bnxt_close,
6344 .ndo_get_stats64 = bnxt_get_stats64,
6345 .ndo_set_rx_mode = bnxt_set_rx_mode,
6346 .ndo_do_ioctl = bnxt_ioctl,
6347 .ndo_validate_addr = eth_validate_addr,
6348 .ndo_set_mac_address = bnxt_change_mac_addr,
6349 .ndo_change_mtu = bnxt_change_mtu,
6350 .ndo_fix_features = bnxt_fix_features,
6351 .ndo_set_features = bnxt_set_features,
6352 .ndo_tx_timeout = bnxt_tx_timeout,
6353#ifdef CONFIG_BNXT_SRIOV
6354 .ndo_get_vf_config = bnxt_get_vf_config,
6355 .ndo_set_vf_mac = bnxt_set_vf_mac,
6356 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
6357 .ndo_set_vf_rate = bnxt_set_vf_bw,
6358 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
6359 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
6360#endif
6361#ifdef CONFIG_NET_POLL_CONTROLLER
6362 .ndo_poll_controller = bnxt_poll_controller,
6363#endif
6364 .ndo_setup_tc = bnxt_setup_tc,
6365#ifdef CONFIG_RFS_ACCEL
6366 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
6367#endif
ad51b8e9
AD		 6368 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
6369 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
c0c050c5
MC		 6370#ifdef CONFIG_NET_RX_BUSY_POLL
6371 .ndo_busy_poll = bnxt_busy_poll,
6372#endif
6373};
6374
6375static void bnxt_remove_one(struct pci_dev *pdev)
6376{
6377 struct net_device *dev = pci_get_drvdata(pdev);
6378 struct bnxt *bp = netdev_priv(dev);
6379
6380 if (BNXT_PF(bp))
6381 bnxt_sriov_disable(bp);
6382
6316ea6d 6383 pci_disable_pcie_error_reporting(pdev);
c0c050c5
MC		 6384 unregister_netdev(dev);
6385 cancel_work_sync(&bp->sp_task);
6386 bp->sp_event = 0;
6387
be58a0da 6388 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5
MC		 6389 bnxt_free_hwrm_resources(bp);
6390 pci_iounmap(pdev, bp->bar2);
6391 pci_iounmap(pdev, bp->bar1);
6392 pci_iounmap(pdev, bp->bar0);
6393 free_netdev(dev);
6394
6395 pci_release_regions(pdev);
6396 pci_disable_device(pdev);
6397}
6398
6399static int bnxt_probe_phy(struct bnxt *bp)
6400{
6401 int rc = 0;
6402 struct bnxt_link_info *link_info = &bp->link_info;
c0c050c5 6403
170ce013
MC		 6404 rc = bnxt_hwrm_phy_qcaps(bp);
6405 if (rc) {
6406 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
6407 rc);
6408 return rc;
6409 }
6410
c0c050c5
MC		 6411 rc = bnxt_update_link(bp, false);
6412 if (rc) {
6413 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
6414 rc);
6415 return rc;
6416 }
6417
93ed8117
MC		 6418 /* Older firmware does not have supported_auto_speeds, so assume
6419 * that all supported speeds can be autonegotiated.
6420 */
6421 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
6422 link_info->support_auto_speeds = link_info->support_speeds;
6423
c0c050c5 6424 /*initialize the ethool setting copy with NVM settings */
0d8abf02 6425 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
c9ee9516
MC		 6426 link_info->autoneg = BNXT_AUTONEG_SPEED;
6427 if (bp->hwrm_spec_code >= 0x10201) {
6428 if (link_info->auto_pause_setting &
6429 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
6430 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6431 } else {
6432 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6433 }
0d8abf02 6434 link_info->advertising = link_info->auto_link_speeds;
0d8abf02
MC		 6435 } else {
6436 link_info->req_link_speed = link_info->force_link_speed;
6437 link_info->req_duplex = link_info->duplex_setting;
c0c050c5 6438 }
c9ee9516
MC		 6439 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
6440 link_info->req_flow_ctrl =
6441 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
6442 else
6443 link_info->req_flow_ctrl = link_info->force_pause_setting;
c0c050c5
MC		 6444 return rc;
6445}
6446
6447static int bnxt_get_max_irq(struct pci_dev *pdev)
6448{
6449 u16 ctrl;
6450
6451 if (!pdev->msix_cap)
6452 return 1;
6453
6454 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
6455 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
6456}
6457
6e6c5a57
MC		 6458static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
6459 int *max_cp)
c0c050c5 6460{
6e6c5a57 6461 int max_ring_grps = 0;
c0c050c5 6462
379a80a1 6463#ifdef CONFIG_BNXT_SRIOV
415b6f19 6464 if (!BNXT_PF(bp)) {
c0c050c5
MC		 6465 *max_tx = bp->vf.max_tx_rings;
6466 *max_rx = bp->vf.max_rx_rings;
6e6c5a57
MC		 6467 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
6468 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
b72d4a68 6469 max_ring_grps = bp->vf.max_hw_ring_grps;
415b6f19 6470 } else
379a80a1 6471#endif
415b6f19
AB		 6472 {
6473 *max_tx = bp->pf.max_tx_rings;
6474 *max_rx = bp->pf.max_rx_rings;
6475 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
6476 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
6477 max_ring_grps = bp->pf.max_hw_ring_grps;
c0c050c5 6478 }
415b6f19 6479
c0c050c5
MC		 6480 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6481 *max_rx >>= 1;
b72d4a68 6482 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 6483}
6484
6485int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
6486{
6487 int rx, tx, cp;
6488
6489 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
6490 if (!rx || !tx || !cp)
6491 return -ENOMEM;
6492
6493 *max_rx = rx;
6494 *max_tx = tx;
6495 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
6496}
6497
6498static int bnxt_set_dflt_rings(struct bnxt *bp)
6499{
6500 int dflt_rings, max_rx_rings, max_tx_rings, rc;
6501 bool sh = true;
6502
6503 if (sh)
6504 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6505 dflt_rings = netif_get_num_default_rss_queues();
6506 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6507 if (rc)
6508 return rc;
6509 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
6510 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
6511 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6512 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6513 bp->tx_nr_rings + bp->rx_nr_rings;
6514 bp->num_stat_ctxs = bp->cp_nr_rings;
6515 return rc;
c0c050c5
MC		 6516}
6517
90c4f788
AK		 6518static void bnxt_parse_log_pcie_link(struct bnxt *bp)
6519{
6520 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
6521 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
6522
6523 if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
6524 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
6525 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
6526 else
6527 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
6528 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
6529 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
6530 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
6531 "Unknown", width);
6532}
6533
c0c050c5
MC		 6534static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6535{
6536 static int version_printed;
6537 struct net_device *dev;
6538 struct bnxt *bp;
6e6c5a57 6539 int rc, max_irqs;
c0c050c5
MC		 6540
6541 if (version_printed++ == 0)
6542 pr_info("%s", version);
6543
6544 max_irqs = bnxt_get_max_irq(pdev);
6545 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
6546 if (!dev)
6547 return -ENOMEM;
6548
6549 bp = netdev_priv(dev);
6550
6551 if (bnxt_vf_pciid(ent->driver_data))
6552 bp->flags |= BNXT_FLAG_VF;
6553
2bcfa6f6 6554 if (pdev->msix_cap)
c0c050c5 6555 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 6556
6557 rc = bnxt_init_board(pdev, dev);
6558 if (rc < 0)
6559 goto init_err_free;
6560
6561 dev->netdev_ops = &bnxt_netdev_ops;
6562 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
6563 dev->ethtool_ops = &bnxt_ethtool_ops;
6564
6565 pci_set_drvdata(pdev, dev);
6566
6567 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6568 NETIF_F_TSO | NETIF_F_TSO6 |
6569 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7e13318d 6570 NETIF_F_GSO_IPXIP4 |
152971ee
AD		 6571 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6572 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
c0c050c5
MC		 6573 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
6574
c0c050c5
MC		 6575 dev->hw_enc_features =
6576 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6577 NETIF_F_TSO | NETIF_F_TSO6 |
6578 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
152971ee 6579 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7e13318d 6580 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
152971ee
AD		 6581 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
6582 NETIF_F_GSO_GRE_CSUM;
c0c050c5
MC		 6583 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
6584 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6585 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
6586 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
6587 dev->priv_flags |= IFF_UNICAST_FLT;
6588
6589#ifdef CONFIG_BNXT_SRIOV
6590 init_waitqueue_head(&bp->sriov_cfg_wait);
6591#endif
6592 rc = bnxt_alloc_hwrm_resources(bp);
6593 if (rc)
6594 goto init_err;
6595
6596 mutex_init(&bp->hwrm_cmd_lock);
659c805c
MC		 6597 rc = bnxt_hwrm_ver_get(bp);
6598 if (rc)
6599 goto init_err;
c0c050c5 6600
309369c9 6601 bp->gro_func = bnxt_gro_func_5730x;
94758f8d
MC		 6602 if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
6603 bp->gro_func = bnxt_gro_func_5731x;
309369c9 6604
c0c050c5
MC		 6605 rc = bnxt_hwrm_func_drv_rgtr(bp);
6606 if (rc)
6607 goto init_err;
6608
6609 /* Get the MAX capabilities for this function */
6610 rc = bnxt_hwrm_func_qcaps(bp);
6611 if (rc) {
6612 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
6613 rc);
6614 rc = -1;
6615 goto init_err;
6616 }
6617
6618 rc = bnxt_hwrm_queue_qportcfg(bp);
6619 if (rc) {
6620 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
6621 rc);
6622 rc = -1;
6623 goto init_err;
6624 }
6625
567b2abe
SB		 6626 bnxt_hwrm_func_qcfg(bp);
6627
c0c050c5
MC		 6628 bnxt_set_tpa_flags(bp);
6629 bnxt_set_ring_params(bp);
bdd4347b 6630 if (BNXT_PF(bp))
c0c050c5 6631 bp->pf.max_irqs = max_irqs;
379a80a1 6632#if defined(CONFIG_BNXT_SRIOV)
bdd4347b 6633 else
c0c050c5 6634 bp->vf.max_irqs = max_irqs;
379a80a1 6635#endif
6e6c5a57 6636 bnxt_set_dflt_rings(bp);
c0c050c5 6637
2bcfa6f6
MC		 6638 if (BNXT_PF(bp)) {
6639 dev->hw_features |= NETIF_F_NTUPLE;
6640 if (bnxt_rfs_capable(bp)) {
6641 bp->flags |= BNXT_FLAG_RFS;
6642 dev->features |= NETIF_F_NTUPLE;
6643 }
6644 }
6645
c0c050c5
MC		 6646 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
6647 bp->flags |= BNXT_FLAG_STRIP_VLAN;
6648
6649 rc = bnxt_probe_phy(bp);
6650 if (rc)
6651 goto init_err;
6652
6653 rc = register_netdev(dev);
6654 if (rc)
6655 goto init_err;
6656
6657 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
6658 board_info[ent->driver_data].name,
6659 (long)pci_resource_start(pdev, 0), dev->dev_addr);
6660
90c4f788
AK		 6661 bnxt_parse_log_pcie_link(bp);
6662
c0c050c5
MC		 6663 return 0;
6664
6665init_err:
6666 pci_iounmap(pdev, bp->bar0);
6667 pci_release_regions(pdev);
6668 pci_disable_device(pdev);
6669
6670init_err_free:
6671 free_netdev(dev);
6672 return rc;
6673}
6674
6316ea6d
SB		 6675/**
6676 * bnxt_io_error_detected - called when PCI error is detected
6677 * @pdev: Pointer to PCI device
6678 * @state: The current pci connection state
6679 *
6680 * This function is called after a PCI bus error affecting
6681 * this device has been detected.
6682 */
6683static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
6684 pci_channel_state_t state)
6685{
6686 struct net_device *netdev = pci_get_drvdata(pdev);
2a5bedfa 6687 struct bnxt *bp = netdev_priv(netdev);
6316ea6d
SB		 6688
6689 netdev_info(netdev, "PCI I/O error detected\n");
6690
6691 rtnl_lock();
6692 netif_device_detach(netdev);
6693
6694 if (state == pci_channel_io_perm_failure) {
6695 rtnl_unlock();
6696 return PCI_ERS_RESULT_DISCONNECT;
6697 }
6698
6699 if (netif_running(netdev))
6700 bnxt_close(netdev);
6701
2a5bedfa
MC		 6702 /* So that func_reset will be done during slot_reset */
6703 clear_bit(BNXT_STATE_FN_RST_DONE, &bp->state);
6316ea6d
SB		 6704 pci_disable_device(pdev);
6705 rtnl_unlock();
6706
6707 /* Request a slot slot reset. */
6708 return PCI_ERS_RESULT_NEED_RESET;
6709}
6710
6711/**
6712 * bnxt_io_slot_reset - called after the pci bus has been reset.
6713 * @pdev: Pointer to PCI device
6714 *
6715 * Restart the card from scratch, as if from a cold-boot.
6716 * At this point, the card has exprienced a hard reset,
6717 * followed by fixups by BIOS, and has its config space
6718 * set up identically to what it was at cold boot.
6719 */
6720static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
6721{
6722 struct net_device *netdev = pci_get_drvdata(pdev);
6723 struct bnxt *bp = netdev_priv(netdev);
6724 int err = 0;
6725 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
6726
6727 netdev_info(bp->dev, "PCI Slot Reset\n");
6728
6729 rtnl_lock();
6730
6731 if (pci_enable_device(pdev)) {
6732 dev_err(&pdev->dev,
6733 "Cannot re-enable PCI device after reset.\n");
6734 } else {
6735 pci_set_master(pdev);
6736
6737 if (netif_running(netdev))
6738 err = bnxt_open(netdev);
6739
6740 if (!err)
6741 result = PCI_ERS_RESULT_RECOVERED;
6742 }
6743
6744 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
6745 dev_close(netdev);
6746
6747 rtnl_unlock();
6748
6749 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6750 if (err) {
6751 dev_err(&pdev->dev,
6752 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6753 err); /* non-fatal, continue */
6754 }
6755
6756 return PCI_ERS_RESULT_RECOVERED;
6757}
6758
6759/**
6760 * bnxt_io_resume - called when traffic can start flowing again.
6761 * @pdev: Pointer to PCI device
6762 *
6763 * This callback is called when the error recovery driver tells
6764 * us that its OK to resume normal operation.
6765 */
6766static void bnxt_io_resume(struct pci_dev *pdev)
6767{
6768 struct net_device *netdev = pci_get_drvdata(pdev);
6769
6770 rtnl_lock();
6771
6772 netif_device_attach(netdev);
6773
6774 rtnl_unlock();
6775}
6776
6777static const struct pci_error_handlers bnxt_err_handler = {
6778 .error_detected = bnxt_io_error_detected,
6779 .slot_reset = bnxt_io_slot_reset,
6780 .resume = bnxt_io_resume
6781};
6782
c0c050c5
MC		 6783static struct pci_driver bnxt_pci_driver = {
6784 .name = DRV_MODULE_NAME,
6785 .id_table = bnxt_pci_tbl,
6786 .probe = bnxt_init_one,
6787 .remove = bnxt_remove_one,
6316ea6d 6788 .err_handler = &bnxt_err_handler,
c0c050c5
MC		 6789#if defined(CONFIG_BNXT_SRIOV)
6790 .sriov_configure = bnxt_sriov_configure,
6791#endif
6792};
6793
6794module_pci_driver(bnxt_pci_driver);
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