]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/ethernet/broadcom/bnxt/bnxt.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
bnxt_en: assign CPU affinity hints to bnxt_en IRQs
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
11f15ed3 3 * Copyright (c) 2014-2016 Broadcom Corporation
bac9a7e0 4 * Copyright (c) 2016-2017 Broadcom Limited
c0c050c5
MC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12
13#include <linux/stringify.h>
14#include <linux/kernel.h>
15#include <linux/timer.h>
16#include <linux/errno.h>
17#include <linux/ioport.h>
18#include <linux/slab.h>
19#include <linux/vmalloc.h>
20#include <linux/interrupt.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/dma-mapping.h>
26#include <linux/bitops.h>
27#include <linux/io.h>
28#include <linux/irq.h>
29#include <linux/delay.h>
30#include <asm/byteorder.h>
31#include <asm/page.h>
32#include <linux/time.h>
33#include <linux/mii.h>
34#include <linux/if.h>
35#include <linux/if_vlan.h>
32e8239c 36#include <linux/if_bridge.h>
5ac67d8b 37#include <linux/rtc.h>
c6d30e83 38#include <linux/bpf.h>
c0c050c5
MC		 39#include <net/ip.h>
40#include <net/tcp.h>
41#include <net/udp.h>
42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
ad51b8e9 44#include <net/udp_tunnel.h>
c0c050c5
MC		 45#include <linux/workqueue.h>
46#include <linux/prefetch.h>
47#include <linux/cache.h>
48#include <linux/log2.h>
49#include <linux/aer.h>
50#include <linux/bitmap.h>
51#include <linux/cpu_rmap.h>
56f0fd80 52#include <linux/cpumask.h>
c0c050c5
MC		 53
54#include "bnxt_hsi.h"
55#include "bnxt.h"
a588e458 56#include "bnxt_ulp.h"
c0c050c5
MC		 57#include "bnxt_sriov.h"
58#include "bnxt_ethtool.h"
7df4ae9f 59#include "bnxt_dcb.h"
c6d30e83 60#include "bnxt_xdp.h"
4ab0c6a8 61#include "bnxt_vfr.h"
c0c050c5
MC		 62
63#define BNXT_TX_TIMEOUT (5 * HZ)
64
65static const char version[] =
66 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
67
68MODULE_LICENSE("GPL");
69MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
70MODULE_VERSION(DRV_MODULE_VERSION);
71
72#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
73#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
74#define BNXT_RX_COPY_THRESH 256
75
4419dbe6 76#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 77
78enum board_idx {
fbc9a523 79 BCM57301,
c0c050c5
MC		 80 BCM57302,
81 BCM57304,
1f681688 82 BCM57417_NPAR,
fa853dda 83 BCM58700,
b24eb6ae
MC		 84 BCM57311,
85 BCM57312,
fbc9a523 86 BCM57402,
c0c050c5
MC		 87 BCM57404,
88 BCM57406,
1f681688
MC		 89 BCM57402_NPAR,
90 BCM57407,
b24eb6ae
MC		 91 BCM57412,
92 BCM57414,
93 BCM57416,
94 BCM57417,
1f681688 95 BCM57412_NPAR,
5049e33b 96 BCM57314,
1f681688
MC		 97 BCM57417_SFP,
98 BCM57416_SFP,
99 BCM57404_NPAR,
100 BCM57406_NPAR,
101 BCM57407_SFP,
adbc8305 102 BCM57407_NPAR,
1f681688
MC		 103 BCM57414_NPAR,
104 BCM57416_NPAR,
32b40798
DK		 105 BCM57452,
106 BCM57454,
adbc8305
MC		 107 NETXTREME_E_VF,
108 NETXTREME_C_VF,
c0c050c5
MC		 109};
110
111/* indexed by enum above */
112static const struct {
113 char *name;
114} board_info[] = {
adbc8305
MC		 115 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
116 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
117 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
1f681688 118 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 119 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
120 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
121 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
122 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
123 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
124 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
1f681688 125 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 126 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
127 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
128 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
129 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
130 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
1f681688 131 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 132 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
133 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
134 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
1f681688
MC		 135 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
136 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 137 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
138 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
1f681688
MC		 139 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
140 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
32b40798
DK		 141 { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
142 { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
adbc8305
MC		 143 { "Broadcom NetXtreme-E Ethernet Virtual Function" },
144 { "Broadcom NetXtreme-C Ethernet Virtual Function" },
c0c050c5
MC		 145};
146
147static const struct pci_device_id bnxt_pci_tbl[] = {
adbc8305 148 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
fbc9a523 149 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 150 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
151 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
1f681688 152 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
fa853dda 153 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
b24eb6ae
MC		 154 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
155 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
fbc9a523 156 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 157 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
158 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
1f681688
MC		 159 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
160 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
b24eb6ae
MC		 161 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
162 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
163 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
164 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
1f681688 165 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
5049e33b 166 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
1f681688
MC		 167 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
168 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
169 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
170 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
171 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
adbc8305
MC		 172 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
173 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
1f681688 174 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
adbc8305 175 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
1f681688 176 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
adbc8305 177 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
32b40798
DK		 178 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
179 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
c0c050c5 180#ifdef CONFIG_BNXT_SRIOV
c7ef35eb
DK		 181 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
182 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
adbc8305
MC		 183 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
184 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
185 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
186 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
187 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
188 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
c0c050c5
MC		 189#endif
190 { 0 }
191};
192
193MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
194
195static const u16 bnxt_vf_req_snif[] = {
196 HWRM_FUNC_CFG,
197 HWRM_PORT_PHY_QCFG,
198 HWRM_CFA_L2_FILTER_ALLOC,
199};
200
25be8623 201static const u16 bnxt_async_events_arr[] = {
87c374de
MC		 202 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
203 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
204 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
205 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
206 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
25be8623
MC		 207};
208
c0c050c5
MC		 209static bool bnxt_vf_pciid(enum board_idx idx)
210{
adbc8305 211 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
c0c050c5
MC		 212}
213
214#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
215#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
216#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
217
218#define BNXT_CP_DB_REARM(db, raw_cons) \
219 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
220
221#define BNXT_CP_DB(db, raw_cons) \
222 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
223
224#define BNXT_CP_DB_IRQ_DIS(db) \
225 writel(DB_CP_IRQ_DIS_FLAGS, db)
226
38413406 227const u16 bnxt_lhint_arr[] = {
c0c050c5
MC		 228 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
229 TX_BD_FLAGS_LHINT_512_TO_1023,
230 TX_BD_FLAGS_LHINT_1024_TO_2047,
231 TX_BD_FLAGS_LHINT_1024_TO_2047,
232 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
233 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
234 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
235 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
236 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
237 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
238 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
239 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
240 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
241 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
242 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
243 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
244 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
245 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
246 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
247};
248
ee5c7fb3
SP		 249static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
250{
251 struct metadata_dst *md_dst = skb_metadata_dst(skb);
252
253 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
254 return 0;
255
256 return md_dst->u.port_info.port_id;
257}
258
c0c050c5
MC		 259static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
260{
261 struct bnxt *bp = netdev_priv(dev);
262 struct tx_bd *txbd;
263 struct tx_bd_ext *txbd1;
264 struct netdev_queue *txq;
265 int i;
266 dma_addr_t mapping;
267 unsigned int length, pad = 0;
268 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
269 u16 prod, last_frag;
270 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 271 struct bnxt_tx_ring_info *txr;
272 struct bnxt_sw_tx_bd *tx_buf;
273
274 i = skb_get_queue_mapping(skb);
275 if (unlikely(i >= bp->tx_nr_rings)) {
276 dev_kfree_skb_any(skb);
277 return NETDEV_TX_OK;
278 }
279
c0c050c5 280 txq = netdev_get_tx_queue(dev, i);
a960dec9 281 txr = &bp->tx_ring[bp->tx_ring_map[i]];
c0c050c5
MC		 282 prod = txr->tx_prod;
283
284 free_size = bnxt_tx_avail(bp, txr);
285 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
286 netif_tx_stop_queue(txq);
287 return NETDEV_TX_BUSY;
288 }
289
290 length = skb->len;
291 len = skb_headlen(skb);
292 last_frag = skb_shinfo(skb)->nr_frags;
293
294 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
295
296 txbd->tx_bd_opaque = prod;
297
298 tx_buf = &txr->tx_buf_ring[prod];
299 tx_buf->skb = skb;
300 tx_buf->nr_frags = last_frag;
301
302 vlan_tag_flags = 0;
ee5c7fb3 303 cfa_action = bnxt_xmit_get_cfa_action(skb);
c0c050c5
MC		 304 if (skb_vlan_tag_present(skb)) {
305 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
306 skb_vlan_tag_get(skb);
307 /* Currently supports 8021Q, 8021AD vlan offloads
308 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
309 */
310 if (skb->vlan_proto == htons(ETH_P_8021Q))
311 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
312 }
313
314 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 315 struct tx_push_buffer *tx_push_buf = txr->tx_push;
316 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
317 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
318 void *pdata = tx_push_buf->data;
319 u64 *end;
320 int j, push_len;
c0c050c5
MC		 321
322 /* Set COAL_NOW to be ready quickly for the next push */
323 tx_push->tx_bd_len_flags_type =
324 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
325 TX_BD_TYPE_LONG_TX_BD |
326 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
327 TX_BD_FLAGS_COAL_NOW |
328 TX_BD_FLAGS_PACKET_END |
329 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
330
331 if (skb->ip_summed == CHECKSUM_PARTIAL)
332 tx_push1->tx_bd_hsize_lflags =
333 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
334 else
335 tx_push1->tx_bd_hsize_lflags = 0;
336
337 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
ee5c7fb3
SP		 338 tx_push1->tx_bd_cfa_action =
339 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
c0c050c5 340
fbb0fa8b
MC		 341 end = pdata + length;
342 end = PTR_ALIGN(end, 8) - 1;
4419dbe6
MC		 343 *end = 0;
344
c0c050c5
MC		 345 skb_copy_from_linear_data(skb, pdata, len);
346 pdata += len;
347 for (j = 0; j < last_frag; j++) {
348 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
349 void *fptr;
350
351 fptr = skb_frag_address_safe(frag);
352 if (!fptr)
353 goto normal_tx;
354
355 memcpy(pdata, fptr, skb_frag_size(frag));
356 pdata += skb_frag_size(frag);
357 }
358
4419dbe6
MC		 359 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
360 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 361 prod = NEXT_TX(prod);
362 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
363 memcpy(txbd, tx_push1, sizeof(*txbd));
364 prod = NEXT_TX(prod);
4419dbe6 365 tx_push->doorbell =
c0c050c5
MC		 366 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
367 txr->tx_prod = prod;
368
b9a8460a 369 tx_buf->is_push = 1;
c0c050c5 370 netdev_tx_sent_queue(txq, skb->len);
b9a8460a 371 wmb(); /* Sync is_push and byte queue before pushing data */
c0c050c5 372
4419dbe6
MC		 373 push_len = (length + sizeof(*tx_push) + 7) / 8;
374 if (push_len > 16) {
375 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
9d13744b
MC		 376 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
377 (push_len - 16) << 1);
4419dbe6
MC		 378 } else {
379 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
380 push_len);
381 }
c0c050c5 382
c0c050c5
MC		 383 goto tx_done;
384 }
385
386normal_tx:
387 if (length < BNXT_MIN_PKT_SIZE) {
388 pad = BNXT_MIN_PKT_SIZE - length;
389 if (skb_pad(skb, pad)) {
390 /* SKB already freed. */
391 tx_buf->skb = NULL;
392 return NETDEV_TX_OK;
393 }
394 length = BNXT_MIN_PKT_SIZE;
395 }
396
397 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
398
399 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
400 dev_kfree_skb_any(skb);
401 tx_buf->skb = NULL;
402 return NETDEV_TX_OK;
403 }
404
405 dma_unmap_addr_set(tx_buf, mapping, mapping);
406 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
407 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
408
409 txbd->tx_bd_haddr = cpu_to_le64(mapping);
410
411 prod = NEXT_TX(prod);
412 txbd1 = (struct tx_bd_ext *)
413 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
414
415 txbd1->tx_bd_hsize_lflags = 0;
416 if (skb_is_gso(skb)) {
417 u32 hdr_len;
418
419 if (skb->encapsulation)
420 hdr_len = skb_inner_network_offset(skb) +
421 skb_inner_network_header_len(skb) +
422 inner_tcp_hdrlen(skb);
423 else
424 hdr_len = skb_transport_offset(skb) +
425 tcp_hdrlen(skb);
426
427 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
428 TX_BD_FLAGS_T_IPID |
429 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
430 length = skb_shinfo(skb)->gso_size;
431 txbd1->tx_bd_mss = cpu_to_le32(length);
432 length += hdr_len;
433 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
434 txbd1->tx_bd_hsize_lflags =
435 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
436 txbd1->tx_bd_mss = 0;
437 }
438
439 length >>= 9;
440 flags |= bnxt_lhint_arr[length];
441 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
442
443 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
ee5c7fb3
SP		 444 txbd1->tx_bd_cfa_action =
445 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
c0c050c5
MC		 446 for (i = 0; i < last_frag; i++) {
447 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
448
449 prod = NEXT_TX(prod);
450 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
451
452 len = skb_frag_size(frag);
453 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
454 DMA_TO_DEVICE);
455
456 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
457 goto tx_dma_error;
458
459 tx_buf = &txr->tx_buf_ring[prod];
460 dma_unmap_addr_set(tx_buf, mapping, mapping);
461
462 txbd->tx_bd_haddr = cpu_to_le64(mapping);
463
464 flags = len << TX_BD_LEN_SHIFT;
465 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
466 }
467
468 flags &= ~TX_BD_LEN;
469 txbd->tx_bd_len_flags_type =
470 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
471 TX_BD_FLAGS_PACKET_END);
472
473 netdev_tx_sent_queue(txq, skb->len);
474
475 /* Sync BD data before updating doorbell */
476 wmb();
477
478 prod = NEXT_TX(prod);
479 txr->tx_prod = prod;
480
ffe40645 481 if (!skb->xmit_more || netif_xmit_stopped(txq))
4d172f21 482 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
c0c050c5
MC		 483
484tx_done:
485
486 mmiowb();
487
488 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
4d172f21
MC		 489 if (skb->xmit_more && !tx_buf->is_push)
490 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
491
c0c050c5
MC		 492 netif_tx_stop_queue(txq);
493
494 /* netif_tx_stop_queue() must be done before checking
495 * tx index in bnxt_tx_avail() below, because in
496 * bnxt_tx_int(), we update tx index before checking for
497 * netif_tx_queue_stopped().
498 */
499 smp_mb();
500 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
501 netif_tx_wake_queue(txq);
502 }
503 return NETDEV_TX_OK;
504
505tx_dma_error:
506 last_frag = i;
507
508 /* start back at beginning and unmap skb */
509 prod = txr->tx_prod;
510 tx_buf = &txr->tx_buf_ring[prod];
511 tx_buf->skb = NULL;
512 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
513 skb_headlen(skb), PCI_DMA_TODEVICE);
514 prod = NEXT_TX(prod);
515
516 /* unmap remaining mapped pages */
517 for (i = 0; i < last_frag; i++) {
518 prod = NEXT_TX(prod);
519 tx_buf = &txr->tx_buf_ring[prod];
520 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
521 skb_frag_size(&skb_shinfo(skb)->frags[i]),
522 PCI_DMA_TODEVICE);
523 }
524
525 dev_kfree_skb_any(skb);
526 return NETDEV_TX_OK;
527}
528
529static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
530{
b6ab4b01 531 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
a960dec9 532 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
c0c050c5
MC		 533 u16 cons = txr->tx_cons;
534 struct pci_dev *pdev = bp->pdev;
535 int i;
536 unsigned int tx_bytes = 0;
537
538 for (i = 0; i < nr_pkts; i++) {
539 struct bnxt_sw_tx_bd *tx_buf;
540 struct sk_buff *skb;
541 int j, last;
542
543 tx_buf = &txr->tx_buf_ring[cons];
544 cons = NEXT_TX(cons);
545 skb = tx_buf->skb;
546 tx_buf->skb = NULL;
547
548 if (tx_buf->is_push) {
549 tx_buf->is_push = 0;
550 goto next_tx_int;
551 }
552
553 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
554 skb_headlen(skb), PCI_DMA_TODEVICE);
555 last = tx_buf->nr_frags;
556
557 for (j = 0; j < last; j++) {
558 cons = NEXT_TX(cons);
559 tx_buf = &txr->tx_buf_ring[cons];
560 dma_unmap_page(
561 &pdev->dev,
562 dma_unmap_addr(tx_buf, mapping),
563 skb_frag_size(&skb_shinfo(skb)->frags[j]),
564 PCI_DMA_TODEVICE);
565 }
566
567next_tx_int:
568 cons = NEXT_TX(cons);
569
570 tx_bytes += skb->len;
571 dev_kfree_skb_any(skb);
572 }
573
574 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
575 txr->tx_cons = cons;
576
577 /* Need to make the tx_cons update visible to bnxt_start_xmit()
578 * before checking for netif_tx_queue_stopped(). Without the
579 * memory barrier, there is a small possibility that bnxt_start_xmit()
580 * will miss it and cause the queue to be stopped forever.
581 */
582 smp_mb();
583
584 if (unlikely(netif_tx_queue_stopped(txq)) &&
585 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
586 __netif_tx_lock(txq, smp_processor_id());
587 if (netif_tx_queue_stopped(txq) &&
588 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
589 txr->dev_state != BNXT_DEV_STATE_CLOSING)
590 netif_tx_wake_queue(txq);
591 __netif_tx_unlock(txq);
592 }
593}
594
c61fb99c
MC		 595static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
596 gfp_t gfp)
597{
598 struct device *dev = &bp->pdev->dev;
599 struct page *page;
600
601 page = alloc_page(gfp);
602 if (!page)
603 return NULL;
604
c519fe9a
SN		 605 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
606 DMA_ATTR_WEAK_ORDERING);
c61fb99c
MC		 607 if (dma_mapping_error(dev, *mapping)) {
608 __free_page(page);
609 return NULL;
610 }
611 *mapping += bp->rx_dma_offset;
612 return page;
613}
614
c0c050c5
MC		 615static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
616 gfp_t gfp)
617{
618 u8 *data;
619 struct pci_dev *pdev = bp->pdev;
620
621 data = kmalloc(bp->rx_buf_size, gfp);
622 if (!data)
623 return NULL;
624
c519fe9a
SN		 625 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
626 bp->rx_buf_use_size, bp->rx_dir,
627 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 628
629 if (dma_mapping_error(&pdev->dev, *mapping)) {
630 kfree(data);
631 data = NULL;
632 }
633 return data;
634}
635
38413406
MC		 636int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
637 u16 prod, gfp_t gfp)
c0c050c5
MC		 638{
639 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
640 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
c0c050c5
MC		 641 dma_addr_t mapping;
642
c61fb99c
MC		 643 if (BNXT_RX_PAGE_MODE(bp)) {
644 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
c0c050c5 645
c61fb99c
MC		 646 if (!page)
647 return -ENOMEM;
648
649 rx_buf->data = page;
650 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
651 } else {
652 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
653
654 if (!data)
655 return -ENOMEM;
656
657 rx_buf->data = data;
658 rx_buf->data_ptr = data + bp->rx_offset;
659 }
11cd119d 660 rx_buf->mapping = mapping;
c0c050c5
MC		 661
662 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
c0c050c5
MC		 663 return 0;
664}
665
c6d30e83 666void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
c0c050c5
MC		 667{
668 u16 prod = rxr->rx_prod;
669 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
670 struct rx_bd *cons_bd, *prod_bd;
671
672 prod_rx_buf = &rxr->rx_buf_ring[prod];
673 cons_rx_buf = &rxr->rx_buf_ring[cons];
674
675 prod_rx_buf->data = data;
6bb19474 676 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
c0c050c5 677
11cd119d 678 prod_rx_buf->mapping = cons_rx_buf->mapping;
c0c050c5
MC		 679
680 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
681 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
682
683 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
684}
685
686static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
687{
688 u16 next, max = rxr->rx_agg_bmap_size;
689
690 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
691 if (next >= max)
692 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
693 return next;
694}
695
696static inline int bnxt_alloc_rx_page(struct bnxt *bp,
697 struct bnxt_rx_ring_info *rxr,
698 u16 prod, gfp_t gfp)
699{
700 struct rx_bd *rxbd =
701 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
702 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
703 struct pci_dev *pdev = bp->pdev;
704 struct page *page;
705 dma_addr_t mapping;
706 u16 sw_prod = rxr->rx_sw_agg_prod;
89d0a06c 707 unsigned int offset = 0;
c0c050c5 708
89d0a06c
MC		 709 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
710 page = rxr->rx_page;
711 if (!page) {
712 page = alloc_page(gfp);
713 if (!page)
714 return -ENOMEM;
715 rxr->rx_page = page;
716 rxr->rx_page_offset = 0;
717 }
718 offset = rxr->rx_page_offset;
719 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
720 if (rxr->rx_page_offset == PAGE_SIZE)
721 rxr->rx_page = NULL;
722 else
723 get_page(page);
724 } else {
725 page = alloc_page(gfp);
726 if (!page)
727 return -ENOMEM;
728 }
c0c050c5 729
c519fe9a
SN		 730 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
731 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
732 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 733 if (dma_mapping_error(&pdev->dev, mapping)) {
734 __free_page(page);
735 return -EIO;
736 }
737
738 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
739 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
740
741 __set_bit(sw_prod, rxr->rx_agg_bmap);
742 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
743 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
744
745 rx_agg_buf->page = page;
89d0a06c 746 rx_agg_buf->offset = offset;
c0c050c5
MC		 747 rx_agg_buf->mapping = mapping;
748 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
749 rxbd->rx_bd_opaque = sw_prod;
750 return 0;
751}
752
753static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
754 u32 agg_bufs)
755{
756 struct bnxt *bp = bnapi->bp;
757 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 758 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 759 u16 prod = rxr->rx_agg_prod;
760 u16 sw_prod = rxr->rx_sw_agg_prod;
761 u32 i;
762
763 for (i = 0; i < agg_bufs; i++) {
764 u16 cons;
765 struct rx_agg_cmp *agg;
766 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
767 struct rx_bd *prod_bd;
768 struct page *page;
769
770 agg = (struct rx_agg_cmp *)
771 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
772 cons = agg->rx_agg_cmp_opaque;
773 __clear_bit(cons, rxr->rx_agg_bmap);
774
775 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
776 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
777
778 __set_bit(sw_prod, rxr->rx_agg_bmap);
779 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
780 cons_rx_buf = &rxr->rx_agg_ring[cons];
781
782 /* It is possible for sw_prod to be equal to cons, so
783 * set cons_rx_buf->page to NULL first.
784 */
785 page = cons_rx_buf->page;
786 cons_rx_buf->page = NULL;
787 prod_rx_buf->page = page;
89d0a06c 788 prod_rx_buf->offset = cons_rx_buf->offset;
c0c050c5
MC		 789
790 prod_rx_buf->mapping = cons_rx_buf->mapping;
791
792 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
793
794 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
795 prod_bd->rx_bd_opaque = sw_prod;
796
797 prod = NEXT_RX_AGG(prod);
798 sw_prod = NEXT_RX_AGG(sw_prod);
799 cp_cons = NEXT_CMP(cp_cons);
800 }
801 rxr->rx_agg_prod = prod;
802 rxr->rx_sw_agg_prod = sw_prod;
803}
804
c61fb99c
MC		 805static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
806 struct bnxt_rx_ring_info *rxr,
807 u16 cons, void *data, u8 *data_ptr,
808 dma_addr_t dma_addr,
809 unsigned int offset_and_len)
810{
811 unsigned int payload = offset_and_len >> 16;
812 unsigned int len = offset_and_len & 0xffff;
813 struct skb_frag_struct *frag;
814 struct page *page = data;
815 u16 prod = rxr->rx_prod;
816 struct sk_buff *skb;
817 int off, err;
818
819 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
820 if (unlikely(err)) {
821 bnxt_reuse_rx_data(rxr, cons, data);
822 return NULL;
823 }
824 dma_addr -= bp->rx_dma_offset;
c519fe9a
SN		 825 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
826 DMA_ATTR_WEAK_ORDERING);
c61fb99c
MC		 827
828 if (unlikely(!payload))
829 payload = eth_get_headlen(data_ptr, len);
830
831 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
832 if (!skb) {
833 __free_page(page);
834 return NULL;
835 }
836
837 off = (void *)data_ptr - page_address(page);
838 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
839 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
840 payload + NET_IP_ALIGN);
841
842 frag = &skb_shinfo(skb)->frags[0];
843 skb_frag_size_sub(frag, payload);
844 frag->page_offset += payload;
845 skb->data_len -= payload;
846 skb->tail += payload;
847
848 return skb;
849}
850
c0c050c5
MC		 851static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
852 struct bnxt_rx_ring_info *rxr, u16 cons,
6bb19474
MC		 853 void *data, u8 *data_ptr,
854 dma_addr_t dma_addr,
855 unsigned int offset_and_len)
c0c050c5 856{
6bb19474 857 u16 prod = rxr->rx_prod;
c0c050c5 858 struct sk_buff *skb;
6bb19474 859 int err;
c0c050c5
MC		 860
861 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
862 if (unlikely(err)) {
863 bnxt_reuse_rx_data(rxr, cons, data);
864 return NULL;
865 }
866
867 skb = build_skb(data, 0);
c519fe9a
SN		 868 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
869 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 870 if (!skb) {
871 kfree(data);
872 return NULL;
873 }
874
b3dba77c 875 skb_reserve(skb, bp->rx_offset);
6bb19474 876 skb_put(skb, offset_and_len & 0xffff);
c0c050c5
MC		 877 return skb;
878}
879
880static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
881 struct sk_buff *skb, u16 cp_cons,
882 u32 agg_bufs)
883{
884 struct pci_dev *pdev = bp->pdev;
885 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 886 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 887 u16 prod = rxr->rx_agg_prod;
888 u32 i;
889
890 for (i = 0; i < agg_bufs; i++) {
891 u16 cons, frag_len;
892 struct rx_agg_cmp *agg;
893 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
894 struct page *page;
895 dma_addr_t mapping;
896
897 agg = (struct rx_agg_cmp *)
898 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
899 cons = agg->rx_agg_cmp_opaque;
900 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
901 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
902
903 cons_rx_buf = &rxr->rx_agg_ring[cons];
89d0a06c
MC		 904 skb_fill_page_desc(skb, i, cons_rx_buf->page,
905 cons_rx_buf->offset, frag_len);
c0c050c5
MC		 906 __clear_bit(cons, rxr->rx_agg_bmap);
907
908 /* It is possible for bnxt_alloc_rx_page() to allocate
909 * a sw_prod index that equals the cons index, so we
910 * need to clear the cons entry now.
911 */
11cd119d 912 mapping = cons_rx_buf->mapping;
c0c050c5
MC		 913 page = cons_rx_buf->page;
914 cons_rx_buf->page = NULL;
915
916 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
917 struct skb_shared_info *shinfo;
918 unsigned int nr_frags;
919
920 shinfo = skb_shinfo(skb);
921 nr_frags = --shinfo->nr_frags;
922 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
923
924 dev_kfree_skb(skb);
925
926 cons_rx_buf->page = page;
927
928 /* Update prod since possibly some pages have been
929 * allocated already.
930 */
931 rxr->rx_agg_prod = prod;
932 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
933 return NULL;
934 }
935
c519fe9a
SN		 936 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
937 PCI_DMA_FROMDEVICE,
938 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 939
940 skb->data_len += frag_len;
941 skb->len += frag_len;
942 skb->truesize += PAGE_SIZE;
943
944 prod = NEXT_RX_AGG(prod);
945 cp_cons = NEXT_CMP(cp_cons);
946 }
947 rxr->rx_agg_prod = prod;
948 return skb;
949}
950
951static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
952 u8 agg_bufs, u32 *raw_cons)
953{
954 u16 last;
955 struct rx_agg_cmp *agg;
956
957 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
958 last = RING_CMP(*raw_cons);
959 agg = (struct rx_agg_cmp *)
960 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
961 return RX_AGG_CMP_VALID(agg, *raw_cons);
962}
963
964static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
965 unsigned int len,
966 dma_addr_t mapping)
967{
968 struct bnxt *bp = bnapi->bp;
969 struct pci_dev *pdev = bp->pdev;
970 struct sk_buff *skb;
971
972 skb = napi_alloc_skb(&bnapi->napi, len);
973 if (!skb)
974 return NULL;
975
745fc05c
MC		 976 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
977 bp->rx_dir);
c0c050c5 978
6bb19474
MC		 979 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
980 len + NET_IP_ALIGN);
c0c050c5 981
745fc05c
MC		 982 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
983 bp->rx_dir);
c0c050c5
MC		 984
985 skb_put(skb, len);
986 return skb;
987}
988
fa7e2812
MC		 989static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
990 u32 *raw_cons, void *cmp)
991{
992 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
993 struct rx_cmp *rxcmp = cmp;
994 u32 tmp_raw_cons = *raw_cons;
995 u8 cmp_type, agg_bufs = 0;
996
997 cmp_type = RX_CMP_TYPE(rxcmp);
998
999 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1000 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1001 RX_CMP_AGG_BUFS) >>
1002 RX_CMP_AGG_BUFS_SHIFT;
1003 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1004 struct rx_tpa_end_cmp *tpa_end = cmp;
1005
1006 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1007 RX_TPA_END_CMP_AGG_BUFS) >>
1008 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1009 }
1010
1011 if (agg_bufs) {
1012 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1013 return -EBUSY;
1014 }
1015 *raw_cons = tmp_raw_cons;
1016 return 0;
1017}
1018
1019static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1020{
1021 if (!rxr->bnapi->in_reset) {
1022 rxr->bnapi->in_reset = true;
1023 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1024 schedule_work(&bp->sp_task);
1025 }
1026 rxr->rx_next_cons = 0xffff;
1027}
1028
c0c050c5
MC		 1029static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1030 struct rx_tpa_start_cmp *tpa_start,
1031 struct rx_tpa_start_cmp_ext *tpa_start1)
1032{
1033 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1034 u16 cons, prod;
1035 struct bnxt_tpa_info *tpa_info;
1036 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1037 struct rx_bd *prod_bd;
1038 dma_addr_t mapping;
1039
1040 cons = tpa_start->rx_tpa_start_cmp_opaque;
1041 prod = rxr->rx_prod;
1042 cons_rx_buf = &rxr->rx_buf_ring[cons];
1043 prod_rx_buf = &rxr->rx_buf_ring[prod];
1044 tpa_info = &rxr->rx_tpa[agg_id];
1045
fa7e2812
MC		 1046 if (unlikely(cons != rxr->rx_next_cons)) {
1047 bnxt_sched_reset(bp, rxr);
1048 return;
1049 }
ee5c7fb3
SP		 1050 /* Store cfa_code in tpa_info to use in tpa_end
1051 * completion processing.
1052 */
1053 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
c0c050c5 1054 prod_rx_buf->data = tpa_info->data;
6bb19474 1055 prod_rx_buf->data_ptr = tpa_info->data_ptr;
c0c050c5
MC		 1056
1057 mapping = tpa_info->mapping;
11cd119d 1058 prod_rx_buf->mapping = mapping;
c0c050c5
MC		 1059
1060 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1061
1062 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1063
1064 tpa_info->data = cons_rx_buf->data;
6bb19474 1065 tpa_info->data_ptr = cons_rx_buf->data_ptr;
c0c050c5 1066 cons_rx_buf->data = NULL;
11cd119d 1067 tpa_info->mapping = cons_rx_buf->mapping;
c0c050c5
MC		 1068
1069 tpa_info->len =
1070 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1071 RX_TPA_START_CMP_LEN_SHIFT;
1072 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1073 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1074
1075 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1076 tpa_info->gso_type = SKB_GSO_TCPV4;
1077 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1078 if (hash_type == 3)
1079 tpa_info->gso_type = SKB_GSO_TCPV6;
1080 tpa_info->rss_hash =
1081 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1082 } else {
1083 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1084 tpa_info->gso_type = 0;
1085 if (netif_msg_rx_err(bp))
1086 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1087 }
1088 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1089 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
94758f8d 1090 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
c0c050c5
MC		 1091
1092 rxr->rx_prod = NEXT_RX(prod);
1093 cons = NEXT_RX(cons);
376a5b86 1094 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1095 cons_rx_buf = &rxr->rx_buf_ring[cons];
1096
1097 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1098 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1099 cons_rx_buf->data = NULL;
1100}
1101
1102static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1103 u16 cp_cons, u32 agg_bufs)
1104{
1105 if (agg_bufs)
1106 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1107}
1108
94758f8d
MC		 1109static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1110 int payload_off, int tcp_ts,
1111 struct sk_buff *skb)
1112{
1113#ifdef CONFIG_INET
1114 struct tcphdr *th;
1115 int len, nw_off;
1116 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1117 u32 hdr_info = tpa_info->hdr_info;
1118 bool loopback = false;
1119
1120 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1121 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1122 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1123
1124 /* If the packet is an internal loopback packet, the offsets will
1125 * have an extra 4 bytes.
1126 */
1127 if (inner_mac_off == 4) {
1128 loopback = true;
1129 } else if (inner_mac_off > 4) {
1130 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1131 ETH_HLEN - 2));
1132
1133 /* We only support inner iPv4/ipv6. If we don't see the
1134 * correct protocol ID, it must be a loopback packet where
1135 * the offsets are off by 4.
1136 */
09a7636a 1137 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
94758f8d
MC		 1138 loopback = true;
1139 }
1140 if (loopback) {
1141 /* internal loopback packet, subtract all offsets by 4 */
1142 inner_ip_off -= 4;
1143 inner_mac_off -= 4;
1144 outer_ip_off -= 4;
1145 }
1146
1147 nw_off = inner_ip_off - ETH_HLEN;
1148 skb_set_network_header(skb, nw_off);
1149 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1150 struct ipv6hdr *iph = ipv6_hdr(skb);
1151
1152 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1153 len = skb->len - skb_transport_offset(skb);
1154 th = tcp_hdr(skb);
1155 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1156 } else {
1157 struct iphdr *iph = ip_hdr(skb);
1158
1159 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1160 len = skb->len - skb_transport_offset(skb);
1161 th = tcp_hdr(skb);
1162 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1163 }
1164
1165 if (inner_mac_off) { /* tunnel */
1166 struct udphdr *uh = NULL;
1167 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1168 ETH_HLEN - 2));
1169
1170 if (proto == htons(ETH_P_IP)) {
1171 struct iphdr *iph = (struct iphdr *)skb->data;
1172
1173 if (iph->protocol == IPPROTO_UDP)
1174 uh = (struct udphdr *)(iph + 1);
1175 } else {
1176 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1177
1178 if (iph->nexthdr == IPPROTO_UDP)
1179 uh = (struct udphdr *)(iph + 1);
1180 }
1181 if (uh) {
1182 if (uh->check)
1183 skb_shinfo(skb)->gso_type |=
1184 SKB_GSO_UDP_TUNNEL_CSUM;
1185 else
1186 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1187 }
1188 }
1189#endif
1190 return skb;
1191}
1192
c0c050c5
MC		 1193#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1194#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1195
309369c9
MC		 1196static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1197 int payload_off, int tcp_ts,
c0c050c5
MC		 1198 struct sk_buff *skb)
1199{
d1611c3a 1200#ifdef CONFIG_INET
c0c050c5 1201 struct tcphdr *th;
719ca811 1202 int len, nw_off, tcp_opt_len = 0;
27e24189 1203
309369c9 1204 if (tcp_ts)
c0c050c5
MC		 1205 tcp_opt_len = 12;
1206
c0c050c5
MC		 1207 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1208 struct iphdr *iph;
1209
1210 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1211 ETH_HLEN;
1212 skb_set_network_header(skb, nw_off);
1213 iph = ip_hdr(skb);
1214 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1215 len = skb->len - skb_transport_offset(skb);
1216 th = tcp_hdr(skb);
1217 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1218 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1219 struct ipv6hdr *iph;
1220
1221 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1222 ETH_HLEN;
1223 skb_set_network_header(skb, nw_off);
1224 iph = ipv6_hdr(skb);
1225 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1226 len = skb->len - skb_transport_offset(skb);
1227 th = tcp_hdr(skb);
1228 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1229 } else {
1230 dev_kfree_skb_any(skb);
1231 return NULL;
1232 }
c0c050c5
MC		 1233
1234 if (nw_off) { /* tunnel */
1235 struct udphdr *uh = NULL;
1236
1237 if (skb->protocol == htons(ETH_P_IP)) {
1238 struct iphdr *iph = (struct iphdr *)skb->data;
1239
1240 if (iph->protocol == IPPROTO_UDP)
1241 uh = (struct udphdr *)(iph + 1);
1242 } else {
1243 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1244
1245 if (iph->nexthdr == IPPROTO_UDP)
1246 uh = (struct udphdr *)(iph + 1);
1247 }
1248 if (uh) {
1249 if (uh->check)
1250 skb_shinfo(skb)->gso_type |=
1251 SKB_GSO_UDP_TUNNEL_CSUM;
1252 else
1253 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1254 }
1255 }
1256#endif
1257 return skb;
1258}
1259
309369c9
MC		 1260static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1261 struct bnxt_tpa_info *tpa_info,
1262 struct rx_tpa_end_cmp *tpa_end,
1263 struct rx_tpa_end_cmp_ext *tpa_end1,
1264 struct sk_buff *skb)
1265{
1266#ifdef CONFIG_INET
1267 int payload_off;
1268 u16 segs;
1269
1270 segs = TPA_END_TPA_SEGS(tpa_end);
1271 if (segs == 1)
1272 return skb;
1273
1274 NAPI_GRO_CB(skb)->count = segs;
1275 skb_shinfo(skb)->gso_size =
1276 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1277 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1278 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1279 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1280 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1281 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
5910906c
MC		 1282 if (likely(skb))
1283 tcp_gro_complete(skb);
309369c9
MC		 1284#endif
1285 return skb;
1286}
1287
ee5c7fb3
SP		 1288/* Given the cfa_code of a received packet determine which
1289 * netdev (vf-rep or PF) the packet is destined to.
1290 */
1291static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1292{
1293 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1294
1295 /* if vf-rep dev is NULL, the must belongs to the PF */
1296 return dev ? dev : bp->dev;
1297}
1298
c0c050c5
MC		 1299static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1300 struct bnxt_napi *bnapi,
1301 u32 *raw_cons,
1302 struct rx_tpa_end_cmp *tpa_end,
1303 struct rx_tpa_end_cmp_ext *tpa_end1,
4e5dbbda 1304 u8 *event)
c0c050c5
MC		 1305{
1306 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1307 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5 1308 u8 agg_id = TPA_END_AGG_ID(tpa_end);
6bb19474 1309 u8 *data_ptr, agg_bufs;
c0c050c5
MC		 1310 u16 cp_cons = RING_CMP(*raw_cons);
1311 unsigned int len;
1312 struct bnxt_tpa_info *tpa_info;
1313 dma_addr_t mapping;
1314 struct sk_buff *skb;
6bb19474 1315 void *data;
c0c050c5 1316
fa7e2812
MC		 1317 if (unlikely(bnapi->in_reset)) {
1318 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1319
1320 if (rc < 0)
1321 return ERR_PTR(-EBUSY);
1322 return NULL;
1323 }
1324
c0c050c5
MC		 1325 tpa_info = &rxr->rx_tpa[agg_id];
1326 data = tpa_info->data;
6bb19474
MC		 1327 data_ptr = tpa_info->data_ptr;
1328 prefetch(data_ptr);
c0c050c5
MC		 1329 len = tpa_info->len;
1330 mapping = tpa_info->mapping;
1331
1332 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1333 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1334
1335 if (agg_bufs) {
1336 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1337 return ERR_PTR(-EBUSY);
1338
4e5dbbda 1339 *event |= BNXT_AGG_EVENT;
c0c050c5
MC		 1340 cp_cons = NEXT_CMP(cp_cons);
1341 }
1342
69c149e2 1343 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
c0c050c5 1344 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
69c149e2
MC		 1345 if (agg_bufs > MAX_SKB_FRAGS)
1346 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1347 agg_bufs, (int)MAX_SKB_FRAGS);
c0c050c5
MC		 1348 return NULL;
1349 }
1350
1351 if (len <= bp->rx_copy_thresh) {
6bb19474 1352 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
c0c050c5
MC		 1353 if (!skb) {
1354 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1355 return NULL;
1356 }
1357 } else {
1358 u8 *new_data;
1359 dma_addr_t new_mapping;
1360
1361 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1362 if (!new_data) {
1363 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1364 return NULL;
1365 }
1366
1367 tpa_info->data = new_data;
b3dba77c 1368 tpa_info->data_ptr = new_data + bp->rx_offset;
c0c050c5
MC		 1369 tpa_info->mapping = new_mapping;
1370
1371 skb = build_skb(data, 0);
c519fe9a
SN		 1372 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1373 bp->rx_buf_use_size, bp->rx_dir,
1374 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 1375
1376 if (!skb) {
1377 kfree(data);
1378 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1379 return NULL;
1380 }
b3dba77c 1381 skb_reserve(skb, bp->rx_offset);
c0c050c5
MC		 1382 skb_put(skb, len);
1383 }
1384
1385 if (agg_bufs) {
1386 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1387 if (!skb) {
1388 /* Page reuse already handled by bnxt_rx_pages(). */
1389 return NULL;
1390 }
1391 }
ee5c7fb3
SP		 1392
1393 skb->protocol =
1394 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
c0c050c5
MC		 1395
1396 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1397 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1398
8852ddb4
MC		 1399 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1400 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5
MC		 1401 u16 vlan_proto = tpa_info->metadata >>
1402 RX_CMP_FLAGS2_METADATA_TPID_SFT;
8852ddb4 1403 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5 1404
8852ddb4 1405 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1406 }
1407
1408 skb_checksum_none_assert(skb);
1409 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1410 skb->ip_summed = CHECKSUM_UNNECESSARY;
1411 skb->csum_level =
1412 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1413 }
1414
1415 if (TPA_END_GRO(tpa_end))
309369c9 1416 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
c0c050c5
MC		 1417
1418 return skb;
1419}
1420
ee5c7fb3
SP		 1421static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1422 struct sk_buff *skb)
1423{
1424 if (skb->dev != bp->dev) {
1425 /* this packet belongs to a vf-rep */
1426 bnxt_vf_rep_rx(bp, skb);
1427 return;
1428 }
1429 skb_record_rx_queue(skb, bnapi->index);
1430 napi_gro_receive(&bnapi->napi, skb);
1431}
1432
c0c050c5
MC		 1433/* returns the following:
1434 * 1 - 1 packet successfully received
1435 * 0 - successful TPA_START, packet not completed yet
1436 * -EBUSY - completion ring does not have all the agg buffers yet
1437 * -ENOMEM - packet aborted due to out of memory
1438 * -EIO - packet aborted due to hw error indicated in BD
1439 */
1440static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
4e5dbbda 1441 u8 *event)
c0c050c5
MC		 1442{
1443 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1444 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1445 struct net_device *dev = bp->dev;
1446 struct rx_cmp *rxcmp;
1447 struct rx_cmp_ext *rxcmp1;
1448 u32 tmp_raw_cons = *raw_cons;
ee5c7fb3 1449 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
c0c050c5
MC		 1450 struct bnxt_sw_rx_bd *rx_buf;
1451 unsigned int len;
6bb19474 1452 u8 *data_ptr, agg_bufs, cmp_type;
c0c050c5
MC		 1453 dma_addr_t dma_addr;
1454 struct sk_buff *skb;
6bb19474 1455 void *data;
c0c050c5 1456 int rc = 0;
c61fb99c 1457 u32 misc;
c0c050c5
MC		 1458
1459 rxcmp = (struct rx_cmp *)
1460 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1461
1462 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1463 cp_cons = RING_CMP(tmp_raw_cons);
1464 rxcmp1 = (struct rx_cmp_ext *)
1465 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1466
1467 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1468 return -EBUSY;
1469
1470 cmp_type = RX_CMP_TYPE(rxcmp);
1471
1472 prod = rxr->rx_prod;
1473
1474 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1475 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1476 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1477
4e5dbbda 1478 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1479 goto next_rx_no_prod;
1480
1481 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1482 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1483 (struct rx_tpa_end_cmp *)rxcmp,
4e5dbbda 1484 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
c0c050c5
MC		 1485
1486 if (unlikely(IS_ERR(skb)))
1487 return -EBUSY;
1488
1489 rc = -ENOMEM;
1490 if (likely(skb)) {
ee5c7fb3 1491 bnxt_deliver_skb(bp, bnapi, skb);
c0c050c5
MC		 1492 rc = 1;
1493 }
4e5dbbda 1494 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1495 goto next_rx_no_prod;
1496 }
1497
1498 cons = rxcmp->rx_cmp_opaque;
1499 rx_buf = &rxr->rx_buf_ring[cons];
1500 data = rx_buf->data;
6bb19474 1501 data_ptr = rx_buf->data_ptr;
fa7e2812
MC		 1502 if (unlikely(cons != rxr->rx_next_cons)) {
1503 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1504
1505 bnxt_sched_reset(bp, rxr);
1506 return rc1;
1507 }
6bb19474 1508 prefetch(data_ptr);
c0c050c5 1509
c61fb99c
MC		 1510 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1511 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
c0c050c5
MC		 1512
1513 if (agg_bufs) {
1514 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1515 return -EBUSY;
1516
1517 cp_cons = NEXT_CMP(cp_cons);
4e5dbbda 1518 *event |= BNXT_AGG_EVENT;
c0c050c5 1519 }
4e5dbbda 1520 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1521
1522 rx_buf->data = NULL;
1523 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1524 bnxt_reuse_rx_data(rxr, cons, data);
1525 if (agg_bufs)
1526 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1527
1528 rc = -EIO;
1529 goto next_rx;
1530 }
1531
1532 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
11cd119d 1533 dma_addr = rx_buf->mapping;
c0c050c5 1534
c6d30e83
MC		 1535 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1536 rc = 1;
1537 goto next_rx;
1538 }
1539
c0c050c5 1540 if (len <= bp->rx_copy_thresh) {
6bb19474 1541 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
c0c050c5
MC		 1542 bnxt_reuse_rx_data(rxr, cons, data);
1543 if (!skb) {
1544 rc = -ENOMEM;
1545 goto next_rx;
1546 }
1547 } else {
c61fb99c
MC		 1548 u32 payload;
1549
c6d30e83
MC		 1550 if (rx_buf->data_ptr == data_ptr)
1551 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1552 else
1553 payload = 0;
6bb19474 1554 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
c61fb99c 1555 payload | len);
c0c050c5
MC		 1556 if (!skb) {
1557 rc = -ENOMEM;
1558 goto next_rx;
1559 }
1560 }
1561
1562 if (agg_bufs) {
1563 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1564 if (!skb) {
1565 rc = -ENOMEM;
1566 goto next_rx;
1567 }
1568 }
1569
1570 if (RX_CMP_HASH_VALID(rxcmp)) {
1571 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1572 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1573
1574 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1575 if (hash_type != 1 && hash_type != 3)
1576 type = PKT_HASH_TYPE_L3;
1577 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1578 }
1579
ee5c7fb3
SP		 1580 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1581 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
c0c050c5 1582
8852ddb4
MC		 1583 if ((rxcmp1->rx_cmp_flags2 &
1584 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1585 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5 1586 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
8852ddb4 1587 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5
MC		 1588 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1589
8852ddb4 1590 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1591 }
1592
1593 skb_checksum_none_assert(skb);
1594 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1595 if (dev->features & NETIF_F_RXCSUM) {
1596 skb->ip_summed = CHECKSUM_UNNECESSARY;
1597 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1598 }
1599 } else {
665e350d
SB		 1600 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1601 if (dev->features & NETIF_F_RXCSUM)
1602 cpr->rx_l4_csum_errors++;
1603 }
c0c050c5
MC		 1604 }
1605
ee5c7fb3 1606 bnxt_deliver_skb(bp, bnapi, skb);
c0c050c5
MC		 1607 rc = 1;
1608
1609next_rx:
1610 rxr->rx_prod = NEXT_RX(prod);
376a5b86 1611 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1612
1613next_rx_no_prod:
1614 *raw_cons = tmp_raw_cons;
1615
1616 return rc;
1617}
1618
2270bc5d
MC		 1619/* In netpoll mode, if we are using a combined completion ring, we need to
1620 * discard the rx packets and recycle the buffers.
1621 */
1622static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1623 u32 *raw_cons, u8 *event)
1624{
1625 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1626 u32 tmp_raw_cons = *raw_cons;
1627 struct rx_cmp_ext *rxcmp1;
1628 struct rx_cmp *rxcmp;
1629 u16 cp_cons;
1630 u8 cmp_type;
1631
1632 cp_cons = RING_CMP(tmp_raw_cons);
1633 rxcmp = (struct rx_cmp *)
1634 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1635
1636 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1637 cp_cons = RING_CMP(tmp_raw_cons);
1638 rxcmp1 = (struct rx_cmp_ext *)
1639 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1640
1641 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1642 return -EBUSY;
1643
1644 cmp_type = RX_CMP_TYPE(rxcmp);
1645 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1646 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1647 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1648 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1649 struct rx_tpa_end_cmp_ext *tpa_end1;
1650
1651 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1652 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1653 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1654 }
1655 return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1656}
1657
4bb13abf 1658#define BNXT_GET_EVENT_PORT(data) \
87c374de
MC		 1659 ((data) & \
1660 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
4bb13abf 1661
c0c050c5
MC		 1662static int bnxt_async_event_process(struct bnxt *bp,
1663 struct hwrm_async_event_cmpl *cmpl)
1664{
1665 u16 event_id = le16_to_cpu(cmpl->event_id);
1666
1667 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1668 switch (event_id) {
87c374de 1669 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
8cbde117
MC		 1670 u32 data1 = le32_to_cpu(cmpl->event_data1);
1671 struct bnxt_link_info *link_info = &bp->link_info;
1672
1673 if (BNXT_VF(bp))
1674 goto async_event_process_exit;
1675 if (data1 & 0x20000) {
1676 u16 fw_speed = link_info->force_link_speed;
1677 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1678
1679 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1680 speed);
1681 }
286ef9d6 1682 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
8cbde117
MC		 1683 /* fall thru */
1684 }
87c374de 1685 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
c0c050c5 1686 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368 1687 break;
87c374de 1688 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
19241368 1689 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5 1690 break;
87c374de 1691 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
4bb13abf
MC		 1692 u32 data1 = le32_to_cpu(cmpl->event_data1);
1693 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1694
1695 if (BNXT_VF(bp))
1696 break;
1697
1698 if (bp->pf.port_id != port_id)
1699 break;
1700
4bb13abf
MC		 1701 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1702 break;
1703 }
87c374de 1704 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
fc0f1929
MC		 1705 if (BNXT_PF(bp))
1706 goto async_event_process_exit;
1707 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1708 break;
c0c050c5 1709 default:
19241368 1710 goto async_event_process_exit;
c0c050c5 1711 }
19241368
JH		 1712 schedule_work(&bp->sp_task);
1713async_event_process_exit:
a588e458 1714 bnxt_ulp_async_events(bp, cmpl);
c0c050c5
MC		 1715 return 0;
1716}
1717
1718static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1719{
1720 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1721 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1722 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1723 (struct hwrm_fwd_req_cmpl *)txcmp;
1724
1725 switch (cmpl_type) {
1726 case CMPL_BASE_TYPE_HWRM_DONE:
1727 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1728 if (seq_id == bp->hwrm_intr_seq_id)
1729 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1730 else
1731 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1732 break;
1733
1734 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1735 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1736
1737 if ((vf_id < bp->pf.first_vf_id) ||
1738 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1739 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1740 vf_id);
1741 return -EINVAL;
1742 }
1743
1744 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1745 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1746 schedule_work(&bp->sp_task);
1747 break;
1748
1749 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1750 bnxt_async_event_process(bp,
1751 (struct hwrm_async_event_cmpl *)txcmp);
1752
1753 default:
1754 break;
1755 }
1756
1757 return 0;
1758}
1759
1760static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1761{
1762 struct bnxt_napi *bnapi = dev_instance;
1763 struct bnxt *bp = bnapi->bp;
1764 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1765 u32 cons = RING_CMP(cpr->cp_raw_cons);
1766
1767 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1768 napi_schedule(&bnapi->napi);
1769 return IRQ_HANDLED;
1770}
1771
1772static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1773{
1774 u32 raw_cons = cpr->cp_raw_cons;
1775 u16 cons = RING_CMP(raw_cons);
1776 struct tx_cmp *txcmp;
1777
1778 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1779
1780 return TX_CMP_VALID(txcmp, raw_cons);
1781}
1782
c0c050c5
MC		 1783static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1784{
1785 struct bnxt_napi *bnapi = dev_instance;
1786 struct bnxt *bp = bnapi->bp;
1787 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1788 u32 cons = RING_CMP(cpr->cp_raw_cons);
1789 u32 int_status;
1790
1791 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1792
1793 if (!bnxt_has_work(bp, cpr)) {
11809490 1794 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1795 /* return if erroneous interrupt */
1796 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1797 return IRQ_NONE;
1798 }
1799
1800 /* disable ring IRQ */
1801 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1802
1803 /* Return here if interrupt is shared and is disabled. */
1804 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1805 return IRQ_HANDLED;
1806
1807 napi_schedule(&bnapi->napi);
1808 return IRQ_HANDLED;
1809}
1810
1811static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1812{
1813 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1814 u32 raw_cons = cpr->cp_raw_cons;
1815 u32 cons;
1816 int tx_pkts = 0;
1817 int rx_pkts = 0;
4e5dbbda 1818 u8 event = 0;
c0c050c5
MC		 1819 struct tx_cmp *txcmp;
1820
1821 while (1) {
1822 int rc;
1823
1824 cons = RING_CMP(raw_cons);
1825 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1826
1827 if (!TX_CMP_VALID(txcmp, raw_cons))
1828 break;
1829
67a95e20
MC		 1830 /* The valid test of the entry must be done first before
1831 * reading any further.
1832 */
b67daab0 1833 dma_rmb();
c0c050c5
MC		 1834 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1835 tx_pkts++;
1836 /* return full budget so NAPI will complete. */
1837 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1838 rx_pkts = budget;
1839 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2270bc5d
MC		 1840 if (likely(budget))
1841 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1842 else
1843 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1844 &event);
c0c050c5
MC		 1845 if (likely(rc >= 0))
1846 rx_pkts += rc;
1847 else if (rc == -EBUSY) /* partial completion */
1848 break;
c0c050c5
MC		 1849 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1850 CMPL_BASE_TYPE_HWRM_DONE) ||
1851 (TX_CMP_TYPE(txcmp) ==
1852 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1853 (TX_CMP_TYPE(txcmp) ==
1854 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1855 bnxt_hwrm_handler(bp, txcmp);
1856 }
1857 raw_cons = NEXT_RAW_CMP(raw_cons);
1858
1859 if (rx_pkts == budget)
1860 break;
1861 }
1862
38413406
MC		 1863 if (event & BNXT_TX_EVENT) {
1864 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1865 void __iomem *db = txr->tx_doorbell;
1866 u16 prod = txr->tx_prod;
1867
1868 /* Sync BD data before updating doorbell */
1869 wmb();
1870
434c975a 1871 bnxt_db_write(bp, db, DB_KEY_TX | prod);
38413406
MC		 1872 }
1873
c0c050c5
MC		 1874 cpr->cp_raw_cons = raw_cons;
1875 /* ACK completion ring before freeing tx ring and producing new
1876 * buffers in rx/agg rings to prevent overflowing the completion
1877 * ring.
1878 */
1879 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1880
1881 if (tx_pkts)
fa3e93e8 1882 bnapi->tx_int(bp, bnapi, tx_pkts);
c0c050c5 1883
4e5dbbda 1884 if (event & BNXT_RX_EVENT) {
b6ab4b01 1885 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5 1886
434c975a
MC		 1887 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1888 if (event & BNXT_AGG_EVENT)
1889 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1890 DB_KEY_RX | rxr->rx_agg_prod);
c0c050c5
MC		 1891 }
1892 return rx_pkts;
1893}
1894
10bbdaf5
PS		 1895static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1896{
1897 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1898 struct bnxt *bp = bnapi->bp;
1899 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1900 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1901 struct tx_cmp *txcmp;
1902 struct rx_cmp_ext *rxcmp1;
1903 u32 cp_cons, tmp_raw_cons;
1904 u32 raw_cons = cpr->cp_raw_cons;
1905 u32 rx_pkts = 0;
4e5dbbda 1906 u8 event = 0;
10bbdaf5
PS		 1907
1908 while (1) {
1909 int rc;
1910
1911 cp_cons = RING_CMP(raw_cons);
1912 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1913
1914 if (!TX_CMP_VALID(txcmp, raw_cons))
1915 break;
1916
1917 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1918 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1919 cp_cons = RING_CMP(tmp_raw_cons);
1920 rxcmp1 = (struct rx_cmp_ext *)
1921 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1922
1923 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1924 break;
1925
1926 /* force an error to recycle the buffer */
1927 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1928 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1929
4e5dbbda 1930 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
10bbdaf5
PS		 1931 if (likely(rc == -EIO))
1932 rx_pkts++;
1933 else if (rc == -EBUSY) /* partial completion */
1934 break;
1935 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1936 CMPL_BASE_TYPE_HWRM_DONE)) {
1937 bnxt_hwrm_handler(bp, txcmp);
1938 } else {
1939 netdev_err(bp->dev,
1940 "Invalid completion received on special ring\n");
1941 }
1942 raw_cons = NEXT_RAW_CMP(raw_cons);
1943
1944 if (rx_pkts == budget)
1945 break;
1946 }
1947
1948 cpr->cp_raw_cons = raw_cons;
1949 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
434c975a 1950 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
10bbdaf5 1951
434c975a
MC		 1952 if (event & BNXT_AGG_EVENT)
1953 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1954 DB_KEY_RX | rxr->rx_agg_prod);
10bbdaf5
PS		 1955
1956 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
6ad20165 1957 napi_complete_done(napi, rx_pkts);
10bbdaf5
PS		 1958 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1959 }
1960 return rx_pkts;
1961}
1962
c0c050c5
MC		 1963static int bnxt_poll(struct napi_struct *napi, int budget)
1964{
1965 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1966 struct bnxt *bp = bnapi->bp;
1967 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1968 int work_done = 0;
1969
c0c050c5
MC		 1970 while (1) {
1971 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1972
1973 if (work_done >= budget)
1974 break;
1975
1976 if (!bnxt_has_work(bp, cpr)) {
e7b95691
MC		 1977 if (napi_complete_done(napi, work_done))
1978 BNXT_CP_DB_REARM(cpr->cp_doorbell,
1979 cpr->cp_raw_cons);
c0c050c5
MC		 1980 break;
1981 }
1982 }
1983 mmiowb();
c0c050c5
MC		 1984 return work_done;
1985}
1986
c0c050c5
MC		 1987static void bnxt_free_tx_skbs(struct bnxt *bp)
1988{
1989 int i, max_idx;
1990 struct pci_dev *pdev = bp->pdev;
1991
b6ab4b01 1992 if (!bp->tx_ring)
c0c050c5
MC		 1993 return;
1994
1995 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1996 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1997 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1998 int j;
1999
c0c050c5
MC		 2000 for (j = 0; j < max_idx;) {
2001 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2002 struct sk_buff *skb = tx_buf->skb;
2003 int k, last;
2004
2005 if (!skb) {
2006 j++;
2007 continue;
2008 }
2009
2010 tx_buf->skb = NULL;
2011
2012 if (tx_buf->is_push) {
2013 dev_kfree_skb(skb);
2014 j += 2;
2015 continue;
2016 }
2017
2018 dma_unmap_single(&pdev->dev,
2019 dma_unmap_addr(tx_buf, mapping),
2020 skb_headlen(skb),
2021 PCI_DMA_TODEVICE);
2022
2023 last = tx_buf->nr_frags;
2024 j += 2;
d612a579
MC		 2025 for (k = 0; k < last; k++, j++) {
2026 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 2027 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2028
d612a579 2029 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 2030 dma_unmap_page(
2031 &pdev->dev,
2032 dma_unmap_addr(tx_buf, mapping),
2033 skb_frag_size(frag), PCI_DMA_TODEVICE);
2034 }
2035 dev_kfree_skb(skb);
2036 }
2037 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2038 }
2039}
2040
2041static void bnxt_free_rx_skbs(struct bnxt *bp)
2042{
2043 int i, max_idx, max_agg_idx;
2044 struct pci_dev *pdev = bp->pdev;
2045
b6ab4b01 2046 if (!bp->rx_ring)
c0c050c5
MC		 2047 return;
2048
2049 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2050 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2051 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2052 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2053 int j;
2054
c0c050c5
MC		 2055 if (rxr->rx_tpa) {
2056 for (j = 0; j < MAX_TPA; j++) {
2057 struct bnxt_tpa_info *tpa_info =
2058 &rxr->rx_tpa[j];
2059 u8 *data = tpa_info->data;
2060
2061 if (!data)
2062 continue;
2063
c519fe9a
SN		 2064 dma_unmap_single_attrs(&pdev->dev,
2065 tpa_info->mapping,
2066 bp->rx_buf_use_size,
2067 bp->rx_dir,
2068 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 2069
2070 tpa_info->data = NULL;
2071
2072 kfree(data);
2073 }
2074 }
2075
2076 for (j = 0; j < max_idx; j++) {
2077 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
3ed3a83e 2078 dma_addr_t mapping = rx_buf->mapping;
6bb19474 2079 void *data = rx_buf->data;
c0c050c5
MC		 2080
2081 if (!data)
2082 continue;
2083
c0c050c5
MC		 2084 rx_buf->data = NULL;
2085
3ed3a83e
MC		 2086 if (BNXT_RX_PAGE_MODE(bp)) {
2087 mapping -= bp->rx_dma_offset;
c519fe9a
SN		 2088 dma_unmap_page_attrs(&pdev->dev, mapping,
2089 PAGE_SIZE, bp->rx_dir,
2090 DMA_ATTR_WEAK_ORDERING);
c61fb99c 2091 __free_page(data);
3ed3a83e 2092 } else {
c519fe9a
SN		 2093 dma_unmap_single_attrs(&pdev->dev, mapping,
2094 bp->rx_buf_use_size,
2095 bp->rx_dir,
2096 DMA_ATTR_WEAK_ORDERING);
c61fb99c 2097 kfree(data);
3ed3a83e 2098 }
c0c050c5
MC		 2099 }
2100
2101 for (j = 0; j < max_agg_idx; j++) {
2102 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2103 &rxr->rx_agg_ring[j];
2104 struct page *page = rx_agg_buf->page;
2105
2106 if (!page)
2107 continue;
2108
c519fe9a
SN		 2109 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2110 BNXT_RX_PAGE_SIZE,
2111 PCI_DMA_FROMDEVICE,
2112 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 2113
2114 rx_agg_buf->page = NULL;
2115 __clear_bit(j, rxr->rx_agg_bmap);
2116
2117 __free_page(page);
2118 }
89d0a06c
MC		 2119 if (rxr->rx_page) {
2120 __free_page(rxr->rx_page);
2121 rxr->rx_page = NULL;
2122 }
c0c050c5
MC		 2123 }
2124}
2125
2126static void bnxt_free_skbs(struct bnxt *bp)
2127{
2128 bnxt_free_tx_skbs(bp);
2129 bnxt_free_rx_skbs(bp);
2130}
2131
2132static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2133{
2134 struct pci_dev *pdev = bp->pdev;
2135 int i;
2136
2137 for (i = 0; i < ring->nr_pages; i++) {
2138 if (!ring->pg_arr[i])
2139 continue;
2140
2141 dma_free_coherent(&pdev->dev, ring->page_size,
2142 ring->pg_arr[i], ring->dma_arr[i]);
2143
2144 ring->pg_arr[i] = NULL;
2145 }
2146 if (ring->pg_tbl) {
2147 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2148 ring->pg_tbl, ring->pg_tbl_map);
2149 ring->pg_tbl = NULL;
2150 }
2151 if (ring->vmem_size && *ring->vmem) {
2152 vfree(*ring->vmem);
2153 *ring->vmem = NULL;
2154 }
2155}
2156
2157static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2158{
2159 int i;
2160 struct pci_dev *pdev = bp->pdev;
2161
2162 if (ring->nr_pages > 1) {
2163 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2164 ring->nr_pages * 8,
2165 &ring->pg_tbl_map,
2166 GFP_KERNEL);
2167 if (!ring->pg_tbl)
2168 return -ENOMEM;
2169 }
2170
2171 for (i = 0; i < ring->nr_pages; i++) {
2172 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2173 ring->page_size,
2174 &ring->dma_arr[i],
2175 GFP_KERNEL);
2176 if (!ring->pg_arr[i])
2177 return -ENOMEM;
2178
2179 if (ring->nr_pages > 1)
2180 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2181 }
2182
2183 if (ring->vmem_size) {
2184 *ring->vmem = vzalloc(ring->vmem_size);
2185 if (!(*ring->vmem))
2186 return -ENOMEM;
2187 }
2188 return 0;
2189}
2190
2191static void bnxt_free_rx_rings(struct bnxt *bp)
2192{
2193 int i;
2194
b6ab4b01 2195 if (!bp->rx_ring)
c0c050c5
MC		 2196 return;
2197
2198 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2199 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2200 struct bnxt_ring_struct *ring;
2201
c6d30e83
MC		 2202 if (rxr->xdp_prog)
2203 bpf_prog_put(rxr->xdp_prog);
2204
c0c050c5
MC		 2205 kfree(rxr->rx_tpa);
2206 rxr->rx_tpa = NULL;
2207
2208 kfree(rxr->rx_agg_bmap);
2209 rxr->rx_agg_bmap = NULL;
2210
2211 ring = &rxr->rx_ring_struct;
2212 bnxt_free_ring(bp, ring);
2213
2214 ring = &rxr->rx_agg_ring_struct;
2215 bnxt_free_ring(bp, ring);
2216 }
2217}
2218
2219static int bnxt_alloc_rx_rings(struct bnxt *bp)
2220{
2221 int i, rc, agg_rings = 0, tpa_rings = 0;
2222
b6ab4b01
MC		 2223 if (!bp->rx_ring)
2224 return -ENOMEM;
2225
c0c050c5
MC		 2226 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2227 agg_rings = 1;
2228
2229 if (bp->flags & BNXT_FLAG_TPA)
2230 tpa_rings = 1;
2231
2232 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2233 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2234 struct bnxt_ring_struct *ring;
2235
c0c050c5
MC		 2236 ring = &rxr->rx_ring_struct;
2237
2238 rc = bnxt_alloc_ring(bp, ring);
2239 if (rc)
2240 return rc;
2241
2242 if (agg_rings) {
2243 u16 mem_size;
2244
2245 ring = &rxr->rx_agg_ring_struct;
2246 rc = bnxt_alloc_ring(bp, ring);
2247 if (rc)
2248 return rc;
2249
2250 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2251 mem_size = rxr->rx_agg_bmap_size / 8;
2252 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2253 if (!rxr->rx_agg_bmap)
2254 return -ENOMEM;
2255
2256 if (tpa_rings) {
2257 rxr->rx_tpa = kcalloc(MAX_TPA,
2258 sizeof(struct bnxt_tpa_info),
2259 GFP_KERNEL);
2260 if (!rxr->rx_tpa)
2261 return -ENOMEM;
2262 }
2263 }
2264 }
2265 return 0;
2266}
2267
2268static void bnxt_free_tx_rings(struct bnxt *bp)
2269{
2270 int i;
2271 struct pci_dev *pdev = bp->pdev;
2272
b6ab4b01 2273 if (!bp->tx_ring)
c0c050c5
MC		 2274 return;
2275
2276 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2277 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2278 struct bnxt_ring_struct *ring;
2279
c0c050c5
MC		 2280 if (txr->tx_push) {
2281 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2282 txr->tx_push, txr->tx_push_mapping);
2283 txr->tx_push = NULL;
2284 }
2285
2286 ring = &txr->tx_ring_struct;
2287
2288 bnxt_free_ring(bp, ring);
2289 }
2290}
2291
2292static int bnxt_alloc_tx_rings(struct bnxt *bp)
2293{
2294 int i, j, rc;
2295 struct pci_dev *pdev = bp->pdev;
2296
2297 bp->tx_push_size = 0;
2298 if (bp->tx_push_thresh) {
2299 int push_size;
2300
2301 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2302 bp->tx_push_thresh);
2303
4419dbe6 2304 if (push_size > 256) {
c0c050c5
MC		 2305 push_size = 0;
2306 bp->tx_push_thresh = 0;
2307 }
2308
2309 bp->tx_push_size = push_size;
2310 }
2311
2312 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2313 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2314 struct bnxt_ring_struct *ring;
2315
c0c050c5
MC		 2316 ring = &txr->tx_ring_struct;
2317
2318 rc = bnxt_alloc_ring(bp, ring);
2319 if (rc)
2320 return rc;
2321
2322 if (bp->tx_push_size) {
c0c050c5
MC		 2323 dma_addr_t mapping;
2324
2325 /* One pre-allocated DMA buffer to backup
2326 * TX push operation
2327 */
2328 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2329 bp->tx_push_size,
2330 &txr->tx_push_mapping,
2331 GFP_KERNEL);
2332
2333 if (!txr->tx_push)
2334 return -ENOMEM;
2335
c0c050c5
MC		 2336 mapping = txr->tx_push_mapping +
2337 sizeof(struct tx_push_bd);
4419dbe6 2338 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 2339
4419dbe6 2340 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5
MC		 2341 }
2342 ring->queue_id = bp->q_info[j].queue_id;
5f449249
MC		 2343 if (i < bp->tx_nr_rings_xdp)
2344 continue;
c0c050c5
MC		 2345 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2346 j++;
2347 }
2348 return 0;
2349}
2350
2351static void bnxt_free_cp_rings(struct bnxt *bp)
2352{
2353 int i;
2354
2355 if (!bp->bnapi)
2356 return;
2357
2358 for (i = 0; i < bp->cp_nr_rings; i++) {
2359 struct bnxt_napi *bnapi = bp->bnapi[i];
2360 struct bnxt_cp_ring_info *cpr;
2361 struct bnxt_ring_struct *ring;
2362
2363 if (!bnapi)
2364 continue;
2365
2366 cpr = &bnapi->cp_ring;
2367 ring = &cpr->cp_ring_struct;
2368
2369 bnxt_free_ring(bp, ring);
2370 }
2371}
2372
2373static int bnxt_alloc_cp_rings(struct bnxt *bp)
2374{
2375 int i, rc;
2376
2377 for (i = 0; i < bp->cp_nr_rings; i++) {
2378 struct bnxt_napi *bnapi = bp->bnapi[i];
2379 struct bnxt_cp_ring_info *cpr;
2380 struct bnxt_ring_struct *ring;
2381
2382 if (!bnapi)
2383 continue;
2384
2385 cpr = &bnapi->cp_ring;
2386 ring = &cpr->cp_ring_struct;
2387
2388 rc = bnxt_alloc_ring(bp, ring);
2389 if (rc)
2390 return rc;
2391 }
2392 return 0;
2393}
2394
2395static void bnxt_init_ring_struct(struct bnxt *bp)
2396{
2397 int i;
2398
2399 for (i = 0; i < bp->cp_nr_rings; i++) {
2400 struct bnxt_napi *bnapi = bp->bnapi[i];
2401 struct bnxt_cp_ring_info *cpr;
2402 struct bnxt_rx_ring_info *rxr;
2403 struct bnxt_tx_ring_info *txr;
2404 struct bnxt_ring_struct *ring;
2405
2406 if (!bnapi)
2407 continue;
2408
2409 cpr = &bnapi->cp_ring;
2410 ring = &cpr->cp_ring_struct;
2411 ring->nr_pages = bp->cp_nr_pages;
2412 ring->page_size = HW_CMPD_RING_SIZE;
2413 ring->pg_arr = (void **)cpr->cp_desc_ring;
2414 ring->dma_arr = cpr->cp_desc_mapping;
2415 ring->vmem_size = 0;
2416
b6ab4b01 2417 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2418 if (!rxr)
2419 goto skip_rx;
2420
c0c050c5
MC		 2421 ring = &rxr->rx_ring_struct;
2422 ring->nr_pages = bp->rx_nr_pages;
2423 ring->page_size = HW_RXBD_RING_SIZE;
2424 ring->pg_arr = (void **)rxr->rx_desc_ring;
2425 ring->dma_arr = rxr->rx_desc_mapping;
2426 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2427 ring->vmem = (void **)&rxr->rx_buf_ring;
2428
2429 ring = &rxr->rx_agg_ring_struct;
2430 ring->nr_pages = bp->rx_agg_nr_pages;
2431 ring->page_size = HW_RXBD_RING_SIZE;
2432 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2433 ring->dma_arr = rxr->rx_agg_desc_mapping;
2434 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2435 ring->vmem = (void **)&rxr->rx_agg_ring;
2436
3b2b7d9d 2437skip_rx:
b6ab4b01 2438 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2439 if (!txr)
2440 continue;
2441
c0c050c5
MC		 2442 ring = &txr->tx_ring_struct;
2443 ring->nr_pages = bp->tx_nr_pages;
2444 ring->page_size = HW_RXBD_RING_SIZE;
2445 ring->pg_arr = (void **)txr->tx_desc_ring;
2446 ring->dma_arr = txr->tx_desc_mapping;
2447 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2448 ring->vmem = (void **)&txr->tx_buf_ring;
2449 }
2450}
2451
2452static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2453{
2454 int i;
2455 u32 prod;
2456 struct rx_bd **rx_buf_ring;
2457
2458 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2459 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2460 int j;
2461 struct rx_bd *rxbd;
2462
2463 rxbd = rx_buf_ring[i];
2464 if (!rxbd)
2465 continue;
2466
2467 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2468 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2469 rxbd->rx_bd_opaque = prod;
2470 }
2471 }
2472}
2473
2474static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2475{
2476 struct net_device *dev = bp->dev;
c0c050c5
MC		 2477 struct bnxt_rx_ring_info *rxr;
2478 struct bnxt_ring_struct *ring;
2479 u32 prod, type;
2480 int i;
2481
c0c050c5
MC		 2482 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2483 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2484
2485 if (NET_IP_ALIGN == 2)
2486 type |= RX_BD_FLAGS_SOP;
2487
b6ab4b01 2488 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 2489 ring = &rxr->rx_ring_struct;
2490 bnxt_init_rxbd_pages(ring, type);
2491
c6d30e83
MC		 2492 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2493 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2494 if (IS_ERR(rxr->xdp_prog)) {
2495 int rc = PTR_ERR(rxr->xdp_prog);
2496
2497 rxr->xdp_prog = NULL;
2498 return rc;
2499 }
2500 }
c0c050c5
MC		 2501 prod = rxr->rx_prod;
2502 for (i = 0; i < bp->rx_ring_size; i++) {
2503 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2504 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2505 ring_nr, i, bp->rx_ring_size);
2506 break;
2507 }
2508 prod = NEXT_RX(prod);
2509 }
2510 rxr->rx_prod = prod;
2511 ring->fw_ring_id = INVALID_HW_RING_ID;
2512
edd0c2cc
MC		 2513 ring = &rxr->rx_agg_ring_struct;
2514 ring->fw_ring_id = INVALID_HW_RING_ID;
2515
c0c050c5
MC		 2516 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2517 return 0;
2518
2839f28b 2519 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
c0c050c5
MC		 2520 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2521
2522 bnxt_init_rxbd_pages(ring, type);
2523
2524 prod = rxr->rx_agg_prod;
2525 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2526 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2527 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2528 ring_nr, i, bp->rx_ring_size);
2529 break;
2530 }
2531 prod = NEXT_RX_AGG(prod);
2532 }
2533 rxr->rx_agg_prod = prod;
c0c050c5
MC		 2534
2535 if (bp->flags & BNXT_FLAG_TPA) {
2536 if (rxr->rx_tpa) {
2537 u8 *data;
2538 dma_addr_t mapping;
2539
2540 for (i = 0; i < MAX_TPA; i++) {
2541 data = __bnxt_alloc_rx_data(bp, &mapping,
2542 GFP_KERNEL);
2543 if (!data)
2544 return -ENOMEM;
2545
2546 rxr->rx_tpa[i].data = data;
b3dba77c 2547 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
c0c050c5
MC		 2548 rxr->rx_tpa[i].mapping = mapping;
2549 }
2550 } else {
2551 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2552 return -ENOMEM;
2553 }
2554 }
2555
2556 return 0;
2557}
2558
2247925f
SP		 2559static void bnxt_init_cp_rings(struct bnxt *bp)
2560{
2561 int i;
2562
2563 for (i = 0; i < bp->cp_nr_rings; i++) {
2564 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2565 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2566
2567 ring->fw_ring_id = INVALID_HW_RING_ID;
2568 }
2569}
2570
c0c050c5
MC		 2571static int bnxt_init_rx_rings(struct bnxt *bp)
2572{
2573 int i, rc = 0;
2574
c61fb99c 2575 if (BNXT_RX_PAGE_MODE(bp)) {
c6d30e83
MC		 2576 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2577 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
c61fb99c
MC		 2578 } else {
2579 bp->rx_offset = BNXT_RX_OFFSET;
2580 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2581 }
b3dba77c 2582
c0c050c5
MC		 2583 for (i = 0; i < bp->rx_nr_rings; i++) {
2584 rc = bnxt_init_one_rx_ring(bp, i);
2585 if (rc)
2586 break;
2587 }
2588
2589 return rc;
2590}
2591
2592static int bnxt_init_tx_rings(struct bnxt *bp)
2593{
2594 u16 i;
2595
2596 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2597 MAX_SKB_FRAGS + 1);
2598
2599 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2600 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2601 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2602
2603 ring->fw_ring_id = INVALID_HW_RING_ID;
2604 }
2605
2606 return 0;
2607}
2608
2609static void bnxt_free_ring_grps(struct bnxt *bp)
2610{
2611 kfree(bp->grp_info);
2612 bp->grp_info = NULL;
2613}
2614
2615static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2616{
2617 int i;
2618
2619 if (irq_re_init) {
2620 bp->grp_info = kcalloc(bp->cp_nr_rings,
2621 sizeof(struct bnxt_ring_grp_info),
2622 GFP_KERNEL);
2623 if (!bp->grp_info)
2624 return -ENOMEM;
2625 }
2626 for (i = 0; i < bp->cp_nr_rings; i++) {
2627 if (irq_re_init)
2628 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2629 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2630 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2631 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2632 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2633 }
2634 return 0;
2635}
2636
2637static void bnxt_free_vnics(struct bnxt *bp)
2638{
2639 kfree(bp->vnic_info);
2640 bp->vnic_info = NULL;
2641 bp->nr_vnics = 0;
2642}
2643
2644static int bnxt_alloc_vnics(struct bnxt *bp)
2645{
2646 int num_vnics = 1;
2647
2648#ifdef CONFIG_RFS_ACCEL
2649 if (bp->flags & BNXT_FLAG_RFS)
2650 num_vnics += bp->rx_nr_rings;
2651#endif
2652
dc52c6c7
PS		 2653 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2654 num_vnics++;
2655
c0c050c5
MC		 2656 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2657 GFP_KERNEL);
2658 if (!bp->vnic_info)
2659 return -ENOMEM;
2660
2661 bp->nr_vnics = num_vnics;
2662 return 0;
2663}
2664
2665static void bnxt_init_vnics(struct bnxt *bp)
2666{
2667 int i;
2668
2669 for (i = 0; i < bp->nr_vnics; i++) {
2670 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2671
2672 vnic->fw_vnic_id = INVALID_HW_RING_ID;
94ce9caa
PS		 2673 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2674 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 2675 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2676
2677 if (bp->vnic_info[i].rss_hash_key) {
2678 if (i == 0)
2679 prandom_bytes(vnic->rss_hash_key,
2680 HW_HASH_KEY_SIZE);
2681 else
2682 memcpy(vnic->rss_hash_key,
2683 bp->vnic_info[0].rss_hash_key,
2684 HW_HASH_KEY_SIZE);
2685 }
2686 }
2687}
2688
2689static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2690{
2691 int pages;
2692
2693 pages = ring_size / desc_per_pg;
2694
2695 if (!pages)
2696 return 1;
2697
2698 pages++;
2699
2700 while (pages & (pages - 1))
2701 pages++;
2702
2703 return pages;
2704}
2705
c6d30e83 2706void bnxt_set_tpa_flags(struct bnxt *bp)
c0c050c5
MC		 2707{
2708 bp->flags &= ~BNXT_FLAG_TPA;
341138c3
MC		 2709 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2710 return;
c0c050c5
MC		 2711 if (bp->dev->features & NETIF_F_LRO)
2712 bp->flags |= BNXT_FLAG_LRO;
94758f8d 2713 if (bp->dev->features & NETIF_F_GRO)
c0c050c5
MC		 2714 bp->flags |= BNXT_FLAG_GRO;
2715}
2716
2717/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2718 * be set on entry.
2719 */
2720void bnxt_set_ring_params(struct bnxt *bp)
2721{
2722 u32 ring_size, rx_size, rx_space;
2723 u32 agg_factor = 0, agg_ring_size = 0;
2724
2725 /* 8 for CRC and VLAN */
2726 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2727
2728 rx_space = rx_size + NET_SKB_PAD +
2729 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2730
2731 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2732 ring_size = bp->rx_ring_size;
2733 bp->rx_agg_ring_size = 0;
2734 bp->rx_agg_nr_pages = 0;
2735
2736 if (bp->flags & BNXT_FLAG_TPA)
2839f28b 2737 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
c0c050c5
MC		 2738
2739 bp->flags &= ~BNXT_FLAG_JUMBO;
bdbd1eb5 2740 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
c0c050c5
MC		 2741 u32 jumbo_factor;
2742
2743 bp->flags |= BNXT_FLAG_JUMBO;
2744 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2745 if (jumbo_factor > agg_factor)
2746 agg_factor = jumbo_factor;
2747 }
2748 agg_ring_size = ring_size * agg_factor;
2749
2750 if (agg_ring_size) {
2751 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2752 RX_DESC_CNT);
2753 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2754 u32 tmp = agg_ring_size;
2755
2756 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2757 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2758 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2759 tmp, agg_ring_size);
2760 }
2761 bp->rx_agg_ring_size = agg_ring_size;
2762 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2763 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2764 rx_space = rx_size + NET_SKB_PAD +
2765 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2766 }
2767
2768 bp->rx_buf_use_size = rx_size;
2769 bp->rx_buf_size = rx_space;
2770
2771 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2772 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2773
2774 ring_size = bp->tx_ring_size;
2775 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2776 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2777
2778 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2779 bp->cp_ring_size = ring_size;
2780
2781 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2782 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2783 bp->cp_nr_pages = MAX_CP_PAGES;
2784 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2785 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2786 ring_size, bp->cp_ring_size);
2787 }
2788 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2789 bp->cp_ring_mask = bp->cp_bit - 1;
2790}
2791
c61fb99c 2792int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
6bb19474 2793{
c61fb99c
MC		 2794 if (page_mode) {
2795 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2796 return -EOPNOTSUPP;
2797 bp->dev->max_mtu = BNXT_MAX_PAGE_MODE_MTU;
2798 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2799 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2800 bp->dev->hw_features &= ~NETIF_F_LRO;
2801 bp->dev->features &= ~NETIF_F_LRO;
2802 bp->rx_dir = DMA_BIDIRECTIONAL;
2803 bp->rx_skb_func = bnxt_rx_page_skb;
2804 } else {
2805 bp->dev->max_mtu = BNXT_MAX_MTU;
2806 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2807 bp->rx_dir = DMA_FROM_DEVICE;
2808 bp->rx_skb_func = bnxt_rx_skb;
2809 }
6bb19474
MC		 2810 return 0;
2811}
2812
c0c050c5
MC		 2813static void bnxt_free_vnic_attributes(struct bnxt *bp)
2814{
2815 int i;
2816 struct bnxt_vnic_info *vnic;
2817 struct pci_dev *pdev = bp->pdev;
2818
2819 if (!bp->vnic_info)
2820 return;
2821
2822 for (i = 0; i < bp->nr_vnics; i++) {
2823 vnic = &bp->vnic_info[i];
2824
2825 kfree(vnic->fw_grp_ids);
2826 vnic->fw_grp_ids = NULL;
2827
2828 kfree(vnic->uc_list);
2829 vnic->uc_list = NULL;
2830
2831 if (vnic->mc_list) {
2832 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2833 vnic->mc_list, vnic->mc_list_mapping);
2834 vnic->mc_list = NULL;
2835 }
2836
2837 if (vnic->rss_table) {
2838 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2839 vnic->rss_table,
2840 vnic->rss_table_dma_addr);
2841 vnic->rss_table = NULL;
2842 }
2843
2844 vnic->rss_hash_key = NULL;
2845 vnic->flags = 0;
2846 }
2847}
2848
2849static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2850{
2851 int i, rc = 0, size;
2852 struct bnxt_vnic_info *vnic;
2853 struct pci_dev *pdev = bp->pdev;
2854 int max_rings;
2855
2856 for (i = 0; i < bp->nr_vnics; i++) {
2857 vnic = &bp->vnic_info[i];
2858
2859 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2860 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2861
2862 if (mem_size > 0) {
2863 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2864 if (!vnic->uc_list) {
2865 rc = -ENOMEM;
2866 goto out;
2867 }
2868 }
2869 }
2870
2871 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2872 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2873 vnic->mc_list =
2874 dma_alloc_coherent(&pdev->dev,
2875 vnic->mc_list_size,
2876 &vnic->mc_list_mapping,
2877 GFP_KERNEL);
2878 if (!vnic->mc_list) {
2879 rc = -ENOMEM;
2880 goto out;
2881 }
2882 }
2883
2884 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2885 max_rings = bp->rx_nr_rings;
2886 else
2887 max_rings = 1;
2888
2889 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2890 if (!vnic->fw_grp_ids) {
2891 rc = -ENOMEM;
2892 goto out;
2893 }
2894
ae10ae74
MC		 2895 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2896 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2897 continue;
2898
c0c050c5
MC		 2899 /* Allocate rss table and hash key */
2900 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2901 &vnic->rss_table_dma_addr,
2902 GFP_KERNEL);
2903 if (!vnic->rss_table) {
2904 rc = -ENOMEM;
2905 goto out;
2906 }
2907
2908 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2909
2910 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2911 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2912 }
2913 return 0;
2914
2915out:
2916 return rc;
2917}
2918
2919static void bnxt_free_hwrm_resources(struct bnxt *bp)
2920{
2921 struct pci_dev *pdev = bp->pdev;
2922
2923 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2924 bp->hwrm_cmd_resp_dma_addr);
2925
2926 bp->hwrm_cmd_resp_addr = NULL;
2927 if (bp->hwrm_dbg_resp_addr) {
2928 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2929 bp->hwrm_dbg_resp_addr,
2930 bp->hwrm_dbg_resp_dma_addr);
2931
2932 bp->hwrm_dbg_resp_addr = NULL;
2933 }
2934}
2935
2936static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2937{
2938 struct pci_dev *pdev = bp->pdev;
2939
2940 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2941 &bp->hwrm_cmd_resp_dma_addr,
2942 GFP_KERNEL);
2943 if (!bp->hwrm_cmd_resp_addr)
2944 return -ENOMEM;
2945 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2946 HWRM_DBG_REG_BUF_SIZE,
2947 &bp->hwrm_dbg_resp_dma_addr,
2948 GFP_KERNEL);
2949 if (!bp->hwrm_dbg_resp_addr)
2950 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2951
2952 return 0;
2953}
2954
e605db80
DK		 2955static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
2956{
2957 if (bp->hwrm_short_cmd_req_addr) {
2958 struct pci_dev *pdev = bp->pdev;
2959
2960 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
2961 bp->hwrm_short_cmd_req_addr,
2962 bp->hwrm_short_cmd_req_dma_addr);
2963 bp->hwrm_short_cmd_req_addr = NULL;
2964 }
2965}
2966
2967static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
2968{
2969 struct pci_dev *pdev = bp->pdev;
2970
2971 bp->hwrm_short_cmd_req_addr =
2972 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
2973 &bp->hwrm_short_cmd_req_dma_addr,
2974 GFP_KERNEL);
2975 if (!bp->hwrm_short_cmd_req_addr)
2976 return -ENOMEM;
2977
2978 return 0;
2979}
2980
c0c050c5
MC		 2981static void bnxt_free_stats(struct bnxt *bp)
2982{
2983 u32 size, i;
2984 struct pci_dev *pdev = bp->pdev;
2985
3bdf56c4
MC		 2986 if (bp->hw_rx_port_stats) {
2987 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2988 bp->hw_rx_port_stats,
2989 bp->hw_rx_port_stats_map);
2990 bp->hw_rx_port_stats = NULL;
2991 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2992 }
2993
c0c050c5
MC		 2994 if (!bp->bnapi)
2995 return;
2996
2997 size = sizeof(struct ctx_hw_stats);
2998
2999 for (i = 0; i < bp->cp_nr_rings; i++) {
3000 struct bnxt_napi *bnapi = bp->bnapi[i];
3001 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3002
3003 if (cpr->hw_stats) {
3004 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3005 cpr->hw_stats_map);
3006 cpr->hw_stats = NULL;
3007 }
3008 }
3009}
3010
3011static int bnxt_alloc_stats(struct bnxt *bp)
3012{
3013 u32 size, i;
3014 struct pci_dev *pdev = bp->pdev;
3015
3016 size = sizeof(struct ctx_hw_stats);
3017
3018 for (i = 0; i < bp->cp_nr_rings; i++) {
3019 struct bnxt_napi *bnapi = bp->bnapi[i];
3020 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3021
3022 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3023 &cpr->hw_stats_map,
3024 GFP_KERNEL);
3025 if (!cpr->hw_stats)
3026 return -ENOMEM;
3027
3028 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3029 }
3bdf56c4 3030
3e8060fa 3031 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3bdf56c4
MC		 3032 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3033 sizeof(struct tx_port_stats) + 1024;
3034
3035 bp->hw_rx_port_stats =
3036 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3037 &bp->hw_rx_port_stats_map,
3038 GFP_KERNEL);
3039 if (!bp->hw_rx_port_stats)
3040 return -ENOMEM;
3041
3042 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3043 512;
3044 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3045 sizeof(struct rx_port_stats) + 512;
3046 bp->flags |= BNXT_FLAG_PORT_STATS;
3047 }
c0c050c5
MC		 3048 return 0;
3049}
3050
3051static void bnxt_clear_ring_indices(struct bnxt *bp)
3052{
3053 int i;
3054
3055 if (!bp->bnapi)
3056 return;
3057
3058 for (i = 0; i < bp->cp_nr_rings; i++) {
3059 struct bnxt_napi *bnapi = bp->bnapi[i];
3060 struct bnxt_cp_ring_info *cpr;
3061 struct bnxt_rx_ring_info *rxr;
3062 struct bnxt_tx_ring_info *txr;
3063
3064 if (!bnapi)
3065 continue;
3066
3067 cpr = &bnapi->cp_ring;
3068 cpr->cp_raw_cons = 0;
3069
b6ab4b01 3070 txr = bnapi->tx_ring;
3b2b7d9d
MC		 3071 if (txr) {
3072 txr->tx_prod = 0;
3073 txr->tx_cons = 0;
3074 }
c0c050c5 3075
b6ab4b01 3076 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 3077 if (rxr) {
3078 rxr->rx_prod = 0;
3079 rxr->rx_agg_prod = 0;
3080 rxr->rx_sw_agg_prod = 0;
376a5b86 3081 rxr->rx_next_cons = 0;
3b2b7d9d 3082 }
c0c050c5
MC		 3083 }
3084}
3085
3086static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3087{
3088#ifdef CONFIG_RFS_ACCEL
3089 int i;
3090
3091 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3092 * safe to delete the hash table.
3093 */
3094 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3095 struct hlist_head *head;
3096 struct hlist_node *tmp;
3097 struct bnxt_ntuple_filter *fltr;
3098
3099 head = &bp->ntp_fltr_hash_tbl[i];
3100 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3101 hlist_del(&fltr->hash);
3102 kfree(fltr);
3103 }
3104 }
3105 if (irq_reinit) {
3106 kfree(bp->ntp_fltr_bmap);
3107 bp->ntp_fltr_bmap = NULL;
3108 }
3109 bp->ntp_fltr_count = 0;
3110#endif
3111}
3112
3113static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3114{
3115#ifdef CONFIG_RFS_ACCEL
3116 int i, rc = 0;
3117
3118 if (!(bp->flags & BNXT_FLAG_RFS))
3119 return 0;
3120
3121 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3122 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3123
3124 bp->ntp_fltr_count = 0;
ac45bd93
DC		 3125 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3126 sizeof(long),
c0c050c5
MC		 3127 GFP_KERNEL);
3128
3129 if (!bp->ntp_fltr_bmap)
3130 rc = -ENOMEM;
3131
3132 return rc;
3133#else
3134 return 0;
3135#endif
3136}
3137
3138static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3139{
3140 bnxt_free_vnic_attributes(bp);
3141 bnxt_free_tx_rings(bp);
3142 bnxt_free_rx_rings(bp);
3143 bnxt_free_cp_rings(bp);
3144 bnxt_free_ntp_fltrs(bp, irq_re_init);
3145 if (irq_re_init) {
3146 bnxt_free_stats(bp);
3147 bnxt_free_ring_grps(bp);
3148 bnxt_free_vnics(bp);
a960dec9
MC		 3149 kfree(bp->tx_ring_map);
3150 bp->tx_ring_map = NULL;
b6ab4b01
MC		 3151 kfree(bp->tx_ring);
3152 bp->tx_ring = NULL;
3153 kfree(bp->rx_ring);
3154 bp->rx_ring = NULL;
c0c050c5
MC		 3155 kfree(bp->bnapi);
3156 bp->bnapi = NULL;
3157 } else {
3158 bnxt_clear_ring_indices(bp);
3159 }
3160}
3161
3162static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3163{
01657bcd 3164 int i, j, rc, size, arr_size;
c0c050c5
MC		 3165 void *bnapi;
3166
3167 if (irq_re_init) {
3168 /* Allocate bnapi mem pointer array and mem block for
3169 * all queues
3170 */
3171 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3172 bp->cp_nr_rings);
3173 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3174 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3175 if (!bnapi)
3176 return -ENOMEM;
3177
3178 bp->bnapi = bnapi;
3179 bnapi += arr_size;
3180 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3181 bp->bnapi[i] = bnapi;
3182 bp->bnapi[i]->index = i;
3183 bp->bnapi[i]->bp = bp;
3184 }
3185
b6ab4b01
MC		 3186 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3187 sizeof(struct bnxt_rx_ring_info),
3188 GFP_KERNEL);
3189 if (!bp->rx_ring)
3190 return -ENOMEM;
3191
3192 for (i = 0; i < bp->rx_nr_rings; i++) {
3193 bp->rx_ring[i].bnapi = bp->bnapi[i];
3194 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3195 }
3196
3197 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3198 sizeof(struct bnxt_tx_ring_info),
3199 GFP_KERNEL);
3200 if (!bp->tx_ring)
3201 return -ENOMEM;
3202
a960dec9
MC		 3203 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3204 GFP_KERNEL);
3205
3206 if (!bp->tx_ring_map)
3207 return -ENOMEM;
3208
01657bcd
MC		 3209 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3210 j = 0;
3211 else
3212 j = bp->rx_nr_rings;
3213
3214 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3215 bp->tx_ring[i].bnapi = bp->bnapi[j];
3216 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
5f449249 3217 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
38413406 3218 if (i >= bp->tx_nr_rings_xdp) {
5f449249
MC		 3219 bp->tx_ring[i].txq_index = i -
3220 bp->tx_nr_rings_xdp;
38413406
MC		 3221 bp->bnapi[j]->tx_int = bnxt_tx_int;
3222 } else {
fa3e93e8 3223 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
38413406
MC		 3224 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3225 }
b6ab4b01
MC		 3226 }
3227
c0c050c5
MC		 3228 rc = bnxt_alloc_stats(bp);
3229 if (rc)
3230 goto alloc_mem_err;
3231
3232 rc = bnxt_alloc_ntp_fltrs(bp);
3233 if (rc)
3234 goto alloc_mem_err;
3235
3236 rc = bnxt_alloc_vnics(bp);
3237 if (rc)
3238 goto alloc_mem_err;
3239 }
3240
3241 bnxt_init_ring_struct(bp);
3242
3243 rc = bnxt_alloc_rx_rings(bp);
3244 if (rc)
3245 goto alloc_mem_err;
3246
3247 rc = bnxt_alloc_tx_rings(bp);
3248 if (rc)
3249 goto alloc_mem_err;
3250
3251 rc = bnxt_alloc_cp_rings(bp);
3252 if (rc)
3253 goto alloc_mem_err;
3254
3255 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3256 BNXT_VNIC_UCAST_FLAG;
3257 rc = bnxt_alloc_vnic_attributes(bp);
3258 if (rc)
3259 goto alloc_mem_err;
3260 return 0;
3261
3262alloc_mem_err:
3263 bnxt_free_mem(bp, true);
3264 return rc;
3265}
3266
9d8bc097
MC		 3267static void bnxt_disable_int(struct bnxt *bp)
3268{
3269 int i;
3270
3271 if (!bp->bnapi)
3272 return;
3273
3274 for (i = 0; i < bp->cp_nr_rings; i++) {
3275 struct bnxt_napi *bnapi = bp->bnapi[i];
3276 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
daf1f1e7 3277 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
9d8bc097 3278
daf1f1e7
MC		 3279 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3280 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
9d8bc097
MC		 3281 }
3282}
3283
3284static void bnxt_disable_int_sync(struct bnxt *bp)
3285{
3286 int i;
3287
3288 atomic_inc(&bp->intr_sem);
3289
3290 bnxt_disable_int(bp);
3291 for (i = 0; i < bp->cp_nr_rings; i++)
3292 synchronize_irq(bp->irq_tbl[i].vector);
3293}
3294
3295static void bnxt_enable_int(struct bnxt *bp)
3296{
3297 int i;
3298
3299 atomic_set(&bp->intr_sem, 0);
3300 for (i = 0; i < bp->cp_nr_rings; i++) {
3301 struct bnxt_napi *bnapi = bp->bnapi[i];
3302 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3303
3304 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3305 }
3306}
3307
c0c050c5
MC		 3308void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3309 u16 cmpl_ring, u16 target_id)
3310{
a8643e16 3311 struct input *req = request;
c0c050c5 3312
a8643e16
MC		 3313 req->req_type = cpu_to_le16(req_type);
3314 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3315 req->target_id = cpu_to_le16(target_id);
c0c050c5
MC		 3316 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3317}
3318
fbfbc485
MC		 3319static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3320 int timeout, bool silent)
c0c050c5 3321{
a11fa2be 3322 int i, intr_process, rc, tmo_count;
a8643e16 3323 struct input *req = msg;
c0c050c5
MC		 3324 u32 *data = msg;
3325 __le32 *resp_len, *valid;
3326 u16 cp_ring_id, len = 0;
3327 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
e605db80 3328 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
c0c050c5 3329
a8643e16 3330 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
c0c050c5 3331 memset(resp, 0, PAGE_SIZE);
a8643e16 3332 cp_ring_id = le16_to_cpu(req->cmpl_ring);
c0c050c5
MC		 3333 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3334
e605db80
DK		 3335 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
3336 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3337 struct hwrm_short_input short_input = {0};
3338
3339 memcpy(short_cmd_req, req, msg_len);
3340 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3341 msg_len);
3342
3343 short_input.req_type = req->req_type;
3344 short_input.signature =
3345 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3346 short_input.size = cpu_to_le16(msg_len);
3347 short_input.req_addr =
3348 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3349
3350 data = (u32 *)&short_input;
3351 msg_len = sizeof(short_input);
3352
3353 /* Sync memory write before updating doorbell */
3354 wmb();
3355
3356 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3357 }
3358
c0c050c5
MC		 3359 /* Write request msg to hwrm channel */
3360 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3361
e605db80 3362 for (i = msg_len; i < max_req_len; i += 4)
d79979a1
MC		 3363 writel(0, bp->bar0 + i);
3364
c0c050c5
MC		 3365 /* currently supports only one outstanding message */
3366 if (intr_process)
a8643e16 3367 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
c0c050c5
MC		 3368
3369 /* Ring channel doorbell */
3370 writel(1, bp->bar0 + 0x100);
3371
ff4fe81d
MC		 3372 if (!timeout)
3373 timeout = DFLT_HWRM_CMD_TIMEOUT;
3374
c0c050c5 3375 i = 0;
a11fa2be 3376 tmo_count = timeout * 40;
c0c050c5
MC		 3377 if (intr_process) {
3378 /* Wait until hwrm response cmpl interrupt is processed */
3379 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
a11fa2be
MC		 3380 i++ < tmo_count) {
3381 usleep_range(25, 40);
c0c050c5
MC		 3382 }
3383
3384 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3385 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
a8643e16 3386 le16_to_cpu(req->req_type));
c0c050c5
MC		 3387 return -1;
3388 }
3389 } else {
3390 /* Check if response len is updated */
3391 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
a11fa2be 3392 for (i = 0; i < tmo_count; i++) {
c0c050c5
MC		 3393 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3394 HWRM_RESP_LEN_SFT;
3395 if (len)
3396 break;
a11fa2be 3397 usleep_range(25, 40);
c0c050c5
MC		 3398 }
3399
a11fa2be 3400 if (i >= tmo_count) {
c0c050c5 3401 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
a8643e16 3402 timeout, le16_to_cpu(req->req_type),
8578d6c1 3403 le16_to_cpu(req->seq_id), len);
c0c050c5
MC		 3404 return -1;
3405 }
3406
3407 /* Last word of resp contains valid bit */
3408 valid = bp->hwrm_cmd_resp_addr + len - 4;
a11fa2be 3409 for (i = 0; i < 5; i++) {
c0c050c5
MC		 3410 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3411 break;
a11fa2be 3412 udelay(1);
c0c050c5
MC		 3413 }
3414
a11fa2be 3415 if (i >= 5) {
c0c050c5 3416 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
a8643e16
MC		 3417 timeout, le16_to_cpu(req->req_type),
3418 le16_to_cpu(req->seq_id), len, *valid);
c0c050c5
MC		 3419 return -1;
3420 }
3421 }
3422
3423 rc = le16_to_cpu(resp->error_code);
fbfbc485 3424 if (rc && !silent)
c0c050c5
MC		 3425 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3426 le16_to_cpu(resp->req_type),
3427 le16_to_cpu(resp->seq_id), rc);
fbfbc485
MC		 3428 return rc;
3429}
3430
3431int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3432{
3433 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
c0c050c5
MC		 3434}
3435
3436int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3437{
3438 int rc;
3439
3440 mutex_lock(&bp->hwrm_cmd_lock);
3441 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3442 mutex_unlock(&bp->hwrm_cmd_lock);
3443 return rc;
3444}
3445
90e20921
MC		 3446int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3447 int timeout)
3448{
3449 int rc;
3450
3451 mutex_lock(&bp->hwrm_cmd_lock);
3452 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3453 mutex_unlock(&bp->hwrm_cmd_lock);
3454 return rc;
3455}
3456
a1653b13
MC		 3457int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3458 int bmap_size)
c0c050c5
MC		 3459{
3460 struct hwrm_func_drv_rgtr_input req = {0};
25be8623
MC		 3461 DECLARE_BITMAP(async_events_bmap, 256);
3462 u32 *events = (u32 *)async_events_bmap;
a1653b13 3463 int i;
c0c050c5
MC		 3464
3465 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3466
3467 req.enables =
a1653b13 3468 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
c0c050c5 3469
25be8623
MC		 3470 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3471 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3472 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3473
a1653b13
MC		 3474 if (bmap && bmap_size) {
3475 for (i = 0; i < bmap_size; i++) {
3476 if (test_bit(i, bmap))
3477 __set_bit(i, async_events_bmap);
3478 }
3479 }
3480
25be8623
MC		 3481 for (i = 0; i < 8; i++)
3482 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3483
a1653b13
MC		 3484 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3485}
3486
3487static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3488{
3489 struct hwrm_func_drv_rgtr_input req = {0};
3490
3491 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3492
3493 req.enables =
3494 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3495 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3496
11f15ed3 3497 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
c0c050c5
MC		 3498 req.ver_maj = DRV_VER_MAJ;
3499 req.ver_min = DRV_VER_MIN;
3500 req.ver_upd = DRV_VER_UPD;
3501
3502 if (BNXT_PF(bp)) {
9b0436c3 3503 u32 data[8];
a1653b13 3504 int i;
c0c050c5 3505
9b0436c3
MC		 3506 memset(data, 0, sizeof(data));
3507 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3508 u16 cmd = bnxt_vf_req_snif[i];
3509 unsigned int bit, idx;
3510
3511 idx = cmd / 32;
3512 bit = cmd % 32;
3513 data[idx] |= 1 << bit;
3514 }
c0c050c5 3515
de68f5de
MC		 3516 for (i = 0; i < 8; i++)
3517 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3518
c0c050c5
MC		 3519 req.enables |=
3520 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3521 }
3522
3523 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3524}
3525
be58a0da
JH		 3526static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3527{
3528 struct hwrm_func_drv_unrgtr_input req = {0};
3529
3530 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3531 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3532}
3533
c0c050c5
MC		 3534static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3535{
3536 u32 rc = 0;
3537 struct hwrm_tunnel_dst_port_free_input req = {0};
3538
3539 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3540 req.tunnel_type = tunnel_type;
3541
3542 switch (tunnel_type) {
3543 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3544 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3545 break;
3546 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3547 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3548 break;
3549 default:
3550 break;
3551 }
3552
3553 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3554 if (rc)
3555 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3556 rc);
3557 return rc;
3558}
3559
3560static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3561 u8 tunnel_type)
3562{
3563 u32 rc = 0;
3564 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3565 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3566
3567 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3568
3569 req.tunnel_type = tunnel_type;
3570 req.tunnel_dst_port_val = port;
3571
3572 mutex_lock(&bp->hwrm_cmd_lock);
3573 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3574 if (rc) {
3575 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3576 rc);
3577 goto err_out;
3578 }
3579
57aac71b
CJ		 3580 switch (tunnel_type) {
3581 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
c0c050c5 3582 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3583 break;
3584 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
c0c050c5 3585 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3586 break;
3587 default:
3588 break;
3589 }
3590
c0c050c5
MC		 3591err_out:
3592 mutex_unlock(&bp->hwrm_cmd_lock);
3593 return rc;
3594}
3595
3596static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3597{
3598 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3599 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3600
3601 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 3602 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 3603
3604 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3605 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3606 req.mask = cpu_to_le32(vnic->rx_mask);
3607 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3608}
3609
3610#ifdef CONFIG_RFS_ACCEL
3611static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3612 struct bnxt_ntuple_filter *fltr)
3613{
3614 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3615
3616 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3617 req.ntuple_filter_id = fltr->filter_id;
3618 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3619}
3620
3621#define BNXT_NTP_FLTR_FLAGS \
3622 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3623 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3624 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3625 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3626 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3627 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3628 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3629 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3630 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3631 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3632 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3633 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3634 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 3635 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5 3636
61aad724
MC		 3637#define BNXT_NTP_TUNNEL_FLTR_FLAG \
3638 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3639
c0c050c5
MC		 3640static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3641 struct bnxt_ntuple_filter *fltr)
3642{
3643 int rc = 0;
3644 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3645 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3646 bp->hwrm_cmd_resp_addr;
3647 struct flow_keys *keys = &fltr->fkeys;
3648 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3649
3650 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
a54c4d74 3651 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
c0c050c5
MC		 3652
3653 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3654
3655 req.ethertype = htons(ETH_P_IP);
3656 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 3657 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 3658 req.ip_protocol = keys->basic.ip_proto;
3659
dda0e746
MC		 3660 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3661 int i;
3662
3663 req.ethertype = htons(ETH_P_IPV6);
3664 req.ip_addr_type =
3665 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3666 *(struct in6_addr *)&req.src_ipaddr[0] =
3667 keys->addrs.v6addrs.src;
3668 *(struct in6_addr *)&req.dst_ipaddr[0] =
3669 keys->addrs.v6addrs.dst;
3670 for (i = 0; i < 4; i++) {
3671 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3672 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3673 }
3674 } else {
3675 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3676 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3677 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3678 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3679 }
61aad724
MC		 3680 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3681 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3682 req.tunnel_type =
3683 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3684 }
c0c050c5
MC		 3685
3686 req.src_port = keys->ports.src;
3687 req.src_port_mask = cpu_to_be16(0xffff);
3688 req.dst_port = keys->ports.dst;
3689 req.dst_port_mask = cpu_to_be16(0xffff);
3690
c193554e 3691 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 3692 mutex_lock(&bp->hwrm_cmd_lock);
3693 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3694 if (!rc)
3695 fltr->filter_id = resp->ntuple_filter_id;
3696 mutex_unlock(&bp->hwrm_cmd_lock);
3697 return rc;
3698}
3699#endif
3700
3701static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3702 u8 *mac_addr)
3703{
3704 u32 rc = 0;
3705 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3706 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3707
3708 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
dc52c6c7
PS		 3709 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3710 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3711 req.flags |=
3712 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 3713 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 3714 req.enables =
3715 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 3716 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 3717 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3718 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3719 req.l2_addr_mask[0] = 0xff;
3720 req.l2_addr_mask[1] = 0xff;
3721 req.l2_addr_mask[2] = 0xff;
3722 req.l2_addr_mask[3] = 0xff;
3723 req.l2_addr_mask[4] = 0xff;
3724 req.l2_addr_mask[5] = 0xff;
3725
3726 mutex_lock(&bp->hwrm_cmd_lock);
3727 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3728 if (!rc)
3729 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3730 resp->l2_filter_id;
3731 mutex_unlock(&bp->hwrm_cmd_lock);
3732 return rc;
3733}
3734
3735static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3736{
3737 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3738 int rc = 0;
3739
3740 /* Any associated ntuple filters will also be cleared by firmware. */
3741 mutex_lock(&bp->hwrm_cmd_lock);
3742 for (i = 0; i < num_of_vnics; i++) {
3743 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3744
3745 for (j = 0; j < vnic->uc_filter_count; j++) {
3746 struct hwrm_cfa_l2_filter_free_input req = {0};
3747
3748 bnxt_hwrm_cmd_hdr_init(bp, &req,
3749 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3750
3751 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3752
3753 rc = _hwrm_send_message(bp, &req, sizeof(req),
3754 HWRM_CMD_TIMEOUT);
3755 }
3756 vnic->uc_filter_count = 0;
3757 }
3758 mutex_unlock(&bp->hwrm_cmd_lock);
3759
3760 return rc;
3761}
3762
3763static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3764{
3765 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3766 struct hwrm_vnic_tpa_cfg_input req = {0};
3767
3768 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3769
3770 if (tpa_flags) {
3771 u16 mss = bp->dev->mtu - 40;
3772 u32 nsegs, n, segs = 0, flags;
3773
3774 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3775 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3776 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3777 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3778 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3779 if (tpa_flags & BNXT_FLAG_GRO)
3780 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3781
3782 req.flags = cpu_to_le32(flags);
3783
3784 req.enables =
3785 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 3786 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3787 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 3788
3789 /* Number of segs are log2 units, and first packet is not
3790 * included as part of this units.
3791 */
2839f28b
MC		 3792 if (mss <= BNXT_RX_PAGE_SIZE) {
3793 n = BNXT_RX_PAGE_SIZE / mss;
c0c050c5
MC		 3794 nsegs = (MAX_SKB_FRAGS - 1) * n;
3795 } else {
2839f28b
MC		 3796 n = mss / BNXT_RX_PAGE_SIZE;
3797 if (mss & (BNXT_RX_PAGE_SIZE - 1))
c0c050c5
MC		 3798 n++;
3799 nsegs = (MAX_SKB_FRAGS - n) / n;
3800 }
3801
3802 segs = ilog2(nsegs);
3803 req.max_agg_segs = cpu_to_le16(segs);
3804 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 3805
3806 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 3807 }
3808 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3809
3810 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3811}
3812
3813static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3814{
3815 u32 i, j, max_rings;
3816 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3817 struct hwrm_vnic_rss_cfg_input req = {0};
3818
94ce9caa 3819 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
c0c050c5
MC		 3820 return 0;
3821
3822 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3823 if (set_rss) {
87da7f79 3824 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
dc52c6c7
PS		 3825 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3826 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3827 max_rings = bp->rx_nr_rings - 1;
3828 else
3829 max_rings = bp->rx_nr_rings;
3830 } else {
c0c050c5 3831 max_rings = 1;
dc52c6c7 3832 }
c0c050c5
MC		 3833
3834 /* Fill the RSS indirection table with ring group ids */
3835 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3836 if (j == max_rings)
3837 j = 0;
3838 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3839 }
3840
3841 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3842 req.hash_key_tbl_addr =
3843 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3844 }
94ce9caa 3845 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
c0c050c5
MC		 3846 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3847}
3848
3849static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3850{
3851 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3852 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3853
3854 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3855 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3856 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3857 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3858 req.enables =
3859 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3860 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3861 /* thresholds not implemented in firmware yet */
3862 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3863 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3864 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3865 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3866}
3867
94ce9caa
PS		 3868static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3869 u16 ctx_idx)
c0c050c5
MC		 3870{
3871 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3872
3873 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3874 req.rss_cos_lb_ctx_id =
94ce9caa 3875 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
c0c050c5
MC		 3876
3877 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
94ce9caa 3878 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
c0c050c5
MC		 3879}
3880
3881static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3882{
94ce9caa 3883 int i, j;
c0c050c5
MC		 3884
3885 for (i = 0; i < bp->nr_vnics; i++) {
3886 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3887
94ce9caa
PS		 3888 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3889 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3890 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3891 }
c0c050c5
MC		 3892 }
3893 bp->rsscos_nr_ctxs = 0;
3894}
3895
94ce9caa 3896static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
c0c050c5
MC		 3897{
3898 int rc;
3899 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3900 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3901 bp->hwrm_cmd_resp_addr;
3902
3903 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3904 -1);
3905
3906 mutex_lock(&bp->hwrm_cmd_lock);
3907 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3908 if (!rc)
94ce9caa 3909 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
c0c050c5
MC		 3910 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3911 mutex_unlock(&bp->hwrm_cmd_lock);
3912
3913 return rc;
3914}
3915
a588e458 3916int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
c0c050c5 3917{
b81a90d3 3918 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 3919 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3920 struct hwrm_vnic_cfg_input req = {0};
cf6645f8 3921 u16 def_vlan = 0;
c0c050c5
MC		 3922
3923 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
dc52c6c7
PS		 3924
3925 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
c0c050c5 3926 /* Only RSS support for now TBD: COS & LB */
dc52c6c7
PS		 3927 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3928 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3929 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3930 VNIC_CFG_REQ_ENABLES_MRU);
ae10ae74
MC		 3931 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
3932 req.rss_rule =
3933 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
3934 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3935 VNIC_CFG_REQ_ENABLES_MRU);
3936 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
dc52c6c7
PS		 3937 } else {
3938 req.rss_rule = cpu_to_le16(0xffff);
3939 }
94ce9caa 3940
dc52c6c7
PS		 3941 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3942 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
94ce9caa
PS		 3943 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3944 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3945 } else {
3946 req.cos_rule = cpu_to_le16(0xffff);
3947 }
3948
c0c050c5 3949 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 3950 ring = 0;
c0c050c5 3951 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 3952 ring = vnic_id - 1;
76595193
PS		 3953 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3954 ring = bp->rx_nr_rings - 1;
c0c050c5 3955
b81a90d3 3956 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5
MC		 3957 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3958 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3959
3960 req.lb_rule = cpu_to_le16(0xffff);
3961 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3962 VLAN_HLEN);
3963
cf6645f8
MC		 3964#ifdef CONFIG_BNXT_SRIOV
3965 if (BNXT_VF(bp))
3966 def_vlan = bp->vf.vlan;
3967#endif
3968 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
c0c050c5 3969 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
a588e458
MC		 3970 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
3971 req.flags |=
3972 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
c0c050c5
MC		 3973
3974 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3975}
3976
3977static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3978{
3979 u32 rc = 0;
3980
3981 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3982 struct hwrm_vnic_free_input req = {0};
3983
3984 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3985 req.vnic_id =
3986 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3987
3988 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3989 if (rc)
3990 return rc;
3991 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3992 }
3993 return rc;
3994}
3995
3996static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3997{
3998 u16 i;
3999
4000 for (i = 0; i < bp->nr_vnics; i++)
4001 bnxt_hwrm_vnic_free_one(bp, i);
4002}
4003
b81a90d3
MC		 4004static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4005 unsigned int start_rx_ring_idx,
4006 unsigned int nr_rings)
c0c050c5 4007{
b81a90d3
MC		 4008 int rc = 0;
4009 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 4010 struct hwrm_vnic_alloc_input req = {0};
4011 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4012
4013 /* map ring groups to this vnic */
b81a90d3
MC		 4014 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4015 grp_idx = bp->rx_ring[i].bnapi->index;
4016 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 4017 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 4018 j, nr_rings);
c0c050c5
MC		 4019 break;
4020 }
4021 bp->vnic_info[vnic_id].fw_grp_ids[j] =
b81a90d3 4022 bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 4023 }
4024
94ce9caa
PS		 4025 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4026 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 4027 if (vnic_id == 0)
4028 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4029
4030 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4031
4032 mutex_lock(&bp->hwrm_cmd_lock);
4033 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4034 if (!rc)
4035 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4036 mutex_unlock(&bp->hwrm_cmd_lock);
4037 return rc;
4038}
4039
8fdefd63
MC		 4040static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4041{
4042 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4043 struct hwrm_vnic_qcaps_input req = {0};
4044 int rc;
4045
4046 if (bp->hwrm_spec_code < 0x10600)
4047 return 0;
4048
4049 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4050 mutex_lock(&bp->hwrm_cmd_lock);
4051 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4052 if (!rc) {
4053 if (resp->flags &
4054 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4055 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4056 }
4057 mutex_unlock(&bp->hwrm_cmd_lock);
4058 return rc;
4059}
4060
c0c050c5
MC		 4061static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4062{
4063 u16 i;
4064 u32 rc = 0;
4065
4066 mutex_lock(&bp->hwrm_cmd_lock);
4067 for (i = 0; i < bp->rx_nr_rings; i++) {
4068 struct hwrm_ring_grp_alloc_input req = {0};
4069 struct hwrm_ring_grp_alloc_output *resp =
4070 bp->hwrm_cmd_resp_addr;
b81a90d3 4071 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 4072
4073 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4074
b81a90d3
MC		 4075 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4076 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4077 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4078 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 4079
4080 rc = _hwrm_send_message(bp, &req, sizeof(req),
4081 HWRM_CMD_TIMEOUT);
4082 if (rc)
4083 break;
4084
b81a90d3
MC		 4085 bp->grp_info[grp_idx].fw_grp_id =
4086 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 4087 }
4088 mutex_unlock(&bp->hwrm_cmd_lock);
4089 return rc;
4090}
4091
4092static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4093{
4094 u16 i;
4095 u32 rc = 0;
4096 struct hwrm_ring_grp_free_input req = {0};
4097
4098 if (!bp->grp_info)
4099 return 0;
4100
4101 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4102
4103 mutex_lock(&bp->hwrm_cmd_lock);
4104 for (i = 0; i < bp->cp_nr_rings; i++) {
4105 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4106 continue;
4107 req.ring_group_id =
4108 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4109
4110 rc = _hwrm_send_message(bp, &req, sizeof(req),
4111 HWRM_CMD_TIMEOUT);
4112 if (rc)
4113 break;
4114 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4115 }
4116 mutex_unlock(&bp->hwrm_cmd_lock);
4117 return rc;
4118}
4119
4120static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4121 struct bnxt_ring_struct *ring,
4122 u32 ring_type, u32 map_index,
4123 u32 stats_ctx_id)
4124{
4125 int rc = 0, err = 0;
4126 struct hwrm_ring_alloc_input req = {0};
4127 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4128 u16 ring_id;
4129
4130 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4131
4132 req.enables = 0;
4133 if (ring->nr_pages > 1) {
4134 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4135 /* Page size is in log2 units */
4136 req.page_size = BNXT_PAGE_SHIFT;
4137 req.page_tbl_depth = 1;
4138 } else {
4139 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
4140 }
4141 req.fbo = 0;
4142 /* Association of ring index with doorbell index and MSIX number */
4143 req.logical_id = cpu_to_le16(map_index);
4144
4145 switch (ring_type) {
4146 case HWRM_RING_ALLOC_TX:
4147 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4148 /* Association of transmit ring with completion ring */
4149 req.cmpl_ring_id =
4150 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
4151 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4152 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
4153 req.queue_id = cpu_to_le16(ring->queue_id);
4154 break;
4155 case HWRM_RING_ALLOC_RX:
4156 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4157 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4158 break;
4159 case HWRM_RING_ALLOC_AGG:
4160 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4161 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4162 break;
4163 case HWRM_RING_ALLOC_CMPL:
bac9a7e0 4164 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
c0c050c5
MC		 4165 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4166 if (bp->flags & BNXT_FLAG_USING_MSIX)
4167 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4168 break;
4169 default:
4170 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4171 ring_type);
4172 return -1;
4173 }
4174
4175 mutex_lock(&bp->hwrm_cmd_lock);
4176 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4177 err = le16_to_cpu(resp->error_code);
4178 ring_id = le16_to_cpu(resp->ring_id);
4179 mutex_unlock(&bp->hwrm_cmd_lock);
4180
4181 if (rc || err) {
4182 switch (ring_type) {
bac9a7e0 4183 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
c0c050c5
MC		 4184 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4185 rc, err);
4186 return -1;
4187
4188 case RING_FREE_REQ_RING_TYPE_RX:
4189 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4190 rc, err);
4191 return -1;
4192
4193 case RING_FREE_REQ_RING_TYPE_TX:
4194 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4195 rc, err);
4196 return -1;
4197
4198 default:
4199 netdev_err(bp->dev, "Invalid ring\n");
4200 return -1;
4201 }
4202 }
4203 ring->fw_ring_id = ring_id;
4204 return rc;
4205}
4206
486b5c22
MC		 4207static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4208{
4209 int rc;
4210
4211 if (BNXT_PF(bp)) {
4212 struct hwrm_func_cfg_input req = {0};
4213
4214 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4215 req.fid = cpu_to_le16(0xffff);
4216 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4217 req.async_event_cr = cpu_to_le16(idx);
4218 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4219 } else {
4220 struct hwrm_func_vf_cfg_input req = {0};
4221
4222 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4223 req.enables =
4224 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4225 req.async_event_cr = cpu_to_le16(idx);
4226 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4227 }
4228 return rc;
4229}
4230
c0c050c5
MC		 4231static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4232{
4233 int i, rc = 0;
4234
edd0c2cc
MC		 4235 for (i = 0; i < bp->cp_nr_rings; i++) {
4236 struct bnxt_napi *bnapi = bp->bnapi[i];
4237 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4238 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
c0c050c5 4239
33e52d88 4240 cpr->cp_doorbell = bp->bar1 + i * 0x80;
edd0c2cc
MC		 4241 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4242 INVALID_STATS_CTX_ID);
4243 if (rc)
4244 goto err_out;
edd0c2cc
MC		 4245 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4246 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
486b5c22
MC		 4247
4248 if (!i) {
4249 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4250 if (rc)
4251 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4252 }
c0c050c5
MC		 4253 }
4254
edd0c2cc 4255 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4256 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 4257 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 4258 u32 map_idx = txr->bnapi->index;
4259 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
c0c050c5 4260
b81a90d3
MC		 4261 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4262 map_idx, fw_stats_ctx);
edd0c2cc
MC		 4263 if (rc)
4264 goto err_out;
b81a90d3 4265 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 4266 }
4267
edd0c2cc 4268 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4269 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4270 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 4271 u32 map_idx = rxr->bnapi->index;
c0c050c5 4272
b81a90d3
MC		 4273 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4274 map_idx, INVALID_STATS_CTX_ID);
edd0c2cc
MC		 4275 if (rc)
4276 goto err_out;
b81a90d3 4277 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
edd0c2cc 4278 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
b81a90d3 4279 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 4280 }
4281
4282 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4283 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4284 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 4285 struct bnxt_ring_struct *ring =
4286 &rxr->rx_agg_ring_struct;
b81a90d3
MC		 4287 u32 grp_idx = rxr->bnapi->index;
4288 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5
MC		 4289
4290 rc = hwrm_ring_alloc_send_msg(bp, ring,
4291 HWRM_RING_ALLOC_AGG,
b81a90d3 4292 map_idx,
c0c050c5
MC		 4293 INVALID_STATS_CTX_ID);
4294 if (rc)
4295 goto err_out;
4296
b81a90d3 4297 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 4298 writel(DB_KEY_RX | rxr->rx_agg_prod,
4299 rxr->rx_agg_doorbell);
b81a90d3 4300 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 4301 }
4302 }
4303err_out:
4304 return rc;
4305}
4306
4307static int hwrm_ring_free_send_msg(struct bnxt *bp,
4308 struct bnxt_ring_struct *ring,
4309 u32 ring_type, int cmpl_ring_id)
4310{
4311 int rc;
4312 struct hwrm_ring_free_input req = {0};
4313 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4314 u16 error_code;
4315
74608fc9 4316 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 4317 req.ring_type = ring_type;
4318 req.ring_id = cpu_to_le16(ring->fw_ring_id);
4319
4320 mutex_lock(&bp->hwrm_cmd_lock);
4321 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4322 error_code = le16_to_cpu(resp->error_code);
4323 mutex_unlock(&bp->hwrm_cmd_lock);
4324
4325 if (rc || error_code) {
4326 switch (ring_type) {
bac9a7e0 4327 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
c0c050c5
MC		 4328 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4329 rc);
4330 return rc;
4331 case RING_FREE_REQ_RING_TYPE_RX:
4332 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4333 rc);
4334 return rc;
4335 case RING_FREE_REQ_RING_TYPE_TX:
4336 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4337 rc);
4338 return rc;
4339 default:
4340 netdev_err(bp->dev, "Invalid ring\n");
4341 return -1;
4342 }
4343 }
4344 return 0;
4345}
4346
edd0c2cc 4347static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 4348{
edd0c2cc 4349 int i;
c0c050c5
MC		 4350
4351 if (!bp->bnapi)
edd0c2cc 4352 return;
c0c050c5 4353
edd0c2cc 4354 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4355 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 4356 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 4357 u32 grp_idx = txr->bnapi->index;
4358 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4359
4360 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4361 hwrm_ring_free_send_msg(bp, ring,
4362 RING_FREE_REQ_RING_TYPE_TX,
4363 close_path ? cmpl_ring_id :
4364 INVALID_HW_RING_ID);
4365 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4366 }
4367 }
4368
edd0c2cc 4369 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4370 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4371 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3
MC		 4372 u32 grp_idx = rxr->bnapi->index;
4373 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4374
4375 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4376 hwrm_ring_free_send_msg(bp, ring,
4377 RING_FREE_REQ_RING_TYPE_RX,
4378 close_path ? cmpl_ring_id :
4379 INVALID_HW_RING_ID);
4380 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4381 bp->grp_info[grp_idx].rx_fw_ring_id =
4382 INVALID_HW_RING_ID;
c0c050c5
MC		 4383 }
4384 }
4385
edd0c2cc 4386 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4387 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4388 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3
MC		 4389 u32 grp_idx = rxr->bnapi->index;
4390 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4391
4392 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4393 hwrm_ring_free_send_msg(bp, ring,
4394 RING_FREE_REQ_RING_TYPE_RX,
4395 close_path ? cmpl_ring_id :
4396 INVALID_HW_RING_ID);
4397 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4398 bp->grp_info[grp_idx].agg_fw_ring_id =
4399 INVALID_HW_RING_ID;
c0c050c5
MC		 4400 }
4401 }
4402
9d8bc097
MC		 4403 /* The completion rings are about to be freed. After that the
4404 * IRQ doorbell will not work anymore. So we need to disable
4405 * IRQ here.
4406 */
4407 bnxt_disable_int_sync(bp);
4408
edd0c2cc
MC		 4409 for (i = 0; i < bp->cp_nr_rings; i++) {
4410 struct bnxt_napi *bnapi = bp->bnapi[i];
4411 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4412 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4413
4414 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4415 hwrm_ring_free_send_msg(bp, ring,
bac9a7e0 4416 RING_FREE_REQ_RING_TYPE_L2_CMPL,
edd0c2cc
MC		 4417 INVALID_HW_RING_ID);
4418 ring->fw_ring_id = INVALID_HW_RING_ID;
4419 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4420 }
4421 }
c0c050c5
MC		 4422}
4423
391be5c2
MC		 4424/* Caller must hold bp->hwrm_cmd_lock */
4425int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4426{
4427 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4428 struct hwrm_func_qcfg_input req = {0};
4429 int rc;
4430
4431 if (bp->hwrm_spec_code < 0x10601)
4432 return 0;
4433
4434 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4435 req.fid = cpu_to_le16(fid);
4436 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4437 if (!rc)
4438 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4439
4440 return rc;
4441}
4442
d1e7925e 4443static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
391be5c2
MC		 4444{
4445 struct hwrm_func_cfg_input req = {0};
4446 int rc;
4447
4448 if (bp->hwrm_spec_code < 0x10601)
4449 return 0;
4450
4451 if (BNXT_VF(bp))
4452 return 0;
4453
4454 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4455 req.fid = cpu_to_le16(0xffff);
4456 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4457 req.num_tx_rings = cpu_to_le16(*tx_rings);
4458 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4459 if (rc)
4460 return rc;
4461
4462 mutex_lock(&bp->hwrm_cmd_lock);
4463 rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4464 mutex_unlock(&bp->hwrm_cmd_lock);
98fdbe73
MC		 4465 if (!rc)
4466 bp->tx_reserved_rings = *tx_rings;
391be5c2
MC		 4467 return rc;
4468}
4469
98fdbe73
MC		 4470static int bnxt_hwrm_check_tx_rings(struct bnxt *bp, int tx_rings)
4471{
4472 struct hwrm_func_cfg_input req = {0};
4473 int rc;
4474
4475 if (bp->hwrm_spec_code < 0x10801)
4476 return 0;
4477
4478 if (BNXT_VF(bp))
4479 return 0;
4480
4481 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4482 req.fid = cpu_to_le16(0xffff);
4483 req.flags = cpu_to_le32(FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST);
4484 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4485 req.num_tx_rings = cpu_to_le16(tx_rings);
4486 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4487 if (rc)
4488 return -ENOMEM;
4489 return 0;
4490}
4491
bb053f52
MC		 4492static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
4493 u32 buf_tmrs, u16 flags,
4494 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4495{
4496 req->flags = cpu_to_le16(flags);
4497 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
4498 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
4499 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
4500 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
4501 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4502 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
4503 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
4504 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
4505}
4506
c0c050c5
MC		 4507int bnxt_hwrm_set_coal(struct bnxt *bp)
4508{
4509 int i, rc = 0;
dfc9c94a
MC		 4510 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4511 req_tx = {0}, *req;
c0c050c5
MC		 4512 u16 max_buf, max_buf_irq;
4513 u16 buf_tmr, buf_tmr_irq;
4514 u32 flags;
4515
dfc9c94a
MC		 4516 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4517 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4518 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4519 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
c0c050c5 4520
dfb5b894
MC		 4521 /* Each rx completion (2 records) should be DMAed immediately.
4522 * DMA 1/4 of the completion buffers at a time.
4523 */
4524 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
c0c050c5
MC		 4525 /* max_buf must not be zero */
4526 max_buf = clamp_t(u16, max_buf, 1, 63);
dfb5b894
MC		 4527 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4528 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4529 /* buf timer set to 1/4 of interrupt timer */
4530 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4531 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4532 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
c0c050c5
MC		 4533
4534 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4535
4536 /* RING_IDLE generates more IRQs for lower latency. Enable it only
4537 * if coal_ticks is less than 25 us.
4538 */
dfb5b894 4539 if (bp->rx_coal_ticks < 25)
c0c050c5
MC		 4540 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4541
bb053f52 4542 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
dfc9c94a
MC		 4543 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4544
4545 /* max_buf must not be zero */
4546 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4547 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4548 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4549 /* buf timer set to 1/4 of interrupt timer */
4550 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4551 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4552 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4553
4554 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4555 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4556 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
c0c050c5
MC		 4557
4558 mutex_lock(&bp->hwrm_cmd_lock);
4559 for (i = 0; i < bp->cp_nr_rings; i++) {
dfc9c94a 4560 struct bnxt_napi *bnapi = bp->bnapi[i];
c0c050c5 4561
dfc9c94a
MC		 4562 req = &req_rx;
4563 if (!bnapi->rx_ring)
4564 req = &req_tx;
4565 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4566
4567 rc = _hwrm_send_message(bp, req, sizeof(*req),
c0c050c5
MC		 4568 HWRM_CMD_TIMEOUT);
4569 if (rc)
4570 break;
4571 }
4572 mutex_unlock(&bp->hwrm_cmd_lock);
4573 return rc;
4574}
4575
4576static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4577{
4578 int rc = 0, i;
4579 struct hwrm_stat_ctx_free_input req = {0};
4580
4581 if (!bp->bnapi)
4582 return 0;
4583
3e8060fa
PS		 4584 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4585 return 0;
4586
c0c050c5
MC		 4587 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4588
4589 mutex_lock(&bp->hwrm_cmd_lock);
4590 for (i = 0; i < bp->cp_nr_rings; i++) {
4591 struct bnxt_napi *bnapi = bp->bnapi[i];
4592 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4593
4594 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4595 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4596
4597 rc = _hwrm_send_message(bp, &req, sizeof(req),
4598 HWRM_CMD_TIMEOUT);
4599 if (rc)
4600 break;
4601
4602 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4603 }
4604 }
4605 mutex_unlock(&bp->hwrm_cmd_lock);
4606 return rc;
4607}
4608
4609static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4610{
4611 int rc = 0, i;
4612 struct hwrm_stat_ctx_alloc_input req = {0};
4613 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4614
3e8060fa
PS		 4615 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4616 return 0;
4617
c0c050c5
MC		 4618 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4619
51f30785 4620 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
c0c050c5
MC		 4621
4622 mutex_lock(&bp->hwrm_cmd_lock);
4623 for (i = 0; i < bp->cp_nr_rings; i++) {
4624 struct bnxt_napi *bnapi = bp->bnapi[i];
4625 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4626
4627 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4628
4629 rc = _hwrm_send_message(bp, &req, sizeof(req),
4630 HWRM_CMD_TIMEOUT);
4631 if (rc)
4632 break;
4633
4634 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4635
4636 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4637 }
4638 mutex_unlock(&bp->hwrm_cmd_lock);
89aa8445 4639 return rc;
c0c050c5
MC		 4640}
4641
cf6645f8
MC		 4642static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4643{
4644 struct hwrm_func_qcfg_input req = {0};
567b2abe 4645 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9315edca 4646 u16 flags;
cf6645f8
MC		 4647 int rc;
4648
4649 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4650 req.fid = cpu_to_le16(0xffff);
4651 mutex_lock(&bp->hwrm_cmd_lock);
4652 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4653 if (rc)
4654 goto func_qcfg_exit;
4655
4656#ifdef CONFIG_BNXT_SRIOV
4657 if (BNXT_VF(bp)) {
cf6645f8
MC		 4658 struct bnxt_vf_info *vf = &bp->vf;
4659
4660 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4661 }
4662#endif
9315edca
MC		 4663 flags = le16_to_cpu(resp->flags);
4664 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
4665 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
4666 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
4667 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
4668 bp->flags |= BNXT_FLAG_FW_DCBX_AGENT;
4669 }
4670 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
4671 bp->flags |= BNXT_FLAG_MULTI_HOST;
bc39f885 4672
567b2abe
SB		 4673 switch (resp->port_partition_type) {
4674 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4675 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4676 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4677 bp->port_partition_type = resp->port_partition_type;
4678 break;
4679 }
32e8239c
MC		 4680 if (bp->hwrm_spec_code < 0x10707 ||
4681 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
4682 bp->br_mode = BRIDGE_MODE_VEB;
4683 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
4684 bp->br_mode = BRIDGE_MODE_VEPA;
4685 else
4686 bp->br_mode = BRIDGE_MODE_UNDEF;
cf6645f8
MC		 4687
4688func_qcfg_exit:
4689 mutex_unlock(&bp->hwrm_cmd_lock);
4690 return rc;
4691}
4692
7b08f661 4693static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 4694{
4695 int rc = 0;
4696 struct hwrm_func_qcaps_input req = {0};
4697 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4698
4699 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4700 req.fid = cpu_to_le16(0xffff);
4701
4702 mutex_lock(&bp->hwrm_cmd_lock);
4703 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4704 if (rc)
4705 goto hwrm_func_qcaps_exit;
4706
e4060d30
MC		 4707 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4708 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4709 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4710 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4711
7cc5a20e
MC		 4712 bp->tx_push_thresh = 0;
4713 if (resp->flags &
4714 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4715 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4716
c0c050c5
MC		 4717 if (BNXT_PF(bp)) {
4718 struct bnxt_pf_info *pf = &bp->pf;
4719
4720 pf->fw_fid = le16_to_cpu(resp->fid);
4721 pf->port_id = le16_to_cpu(resp->port_id);
87027db1 4722 bp->dev->dev_port = pf->port_id;
11f15ed3 4723 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
bdd4347b 4724 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
c0c050c5
MC		 4725 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4726 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4727 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
c0c050c5 4728 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4729 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4730 if (!pf->max_hw_ring_grps)
4731 pf->max_hw_ring_grps = pf->max_tx_rings;
c0c050c5
MC		 4732 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4733 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4734 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4735 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4736 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4737 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4738 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4739 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4740 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4741 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4742 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
c1ef146a
MC		 4743 if (resp->flags &
4744 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED))
4745 bp->flags |= BNXT_FLAG_WOL_CAP;
c0c050c5 4746 } else {
379a80a1 4747#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 4748 struct bnxt_vf_info *vf = &bp->vf;
4749
4750 vf->fw_fid = le16_to_cpu(resp->fid);
c0c050c5
MC		 4751
4752 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4753 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4754 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4755 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4756 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4757 if (!vf->max_hw_ring_grps)
4758 vf->max_hw_ring_grps = vf->max_tx_rings;
c0c050c5
MC		 4759 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4760 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4761 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7cc5a20e
MC		 4762
4763 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
001154eb
MC		 4764 mutex_unlock(&bp->hwrm_cmd_lock);
4765
4766 if (is_valid_ether_addr(vf->mac_addr)) {
7cc5a20e
MC		 4767 /* overwrite netdev dev_adr with admin VF MAC */
4768 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
001154eb 4769 } else {
1faaa78f 4770 eth_hw_addr_random(bp->dev);
001154eb
MC		 4771 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4772 }
4773 return rc;
379a80a1 4774#endif
c0c050c5
MC		 4775 }
4776
c0c050c5
MC		 4777hwrm_func_qcaps_exit:
4778 mutex_unlock(&bp->hwrm_cmd_lock);
4779 return rc;
4780}
4781
4782static int bnxt_hwrm_func_reset(struct bnxt *bp)
4783{
4784 struct hwrm_func_reset_input req = {0};
4785
4786 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4787 req.enables = 0;
4788
4789 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4790}
4791
4792static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4793{
4794 int rc = 0;
4795 struct hwrm_queue_qportcfg_input req = {0};
4796 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4797 u8 i, *qptr;
4798
4799 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4800
4801 mutex_lock(&bp->hwrm_cmd_lock);
4802 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4803 if (rc)
4804 goto qportcfg_exit;
4805
4806 if (!resp->max_configurable_queues) {
4807 rc = -EINVAL;
4808 goto qportcfg_exit;
4809 }
4810 bp->max_tc = resp->max_configurable_queues;
87c374de 4811 bp->max_lltc = resp->max_configurable_lossless_queues;
c0c050c5
MC		 4812 if (bp->max_tc > BNXT_MAX_QUEUE)
4813 bp->max_tc = BNXT_MAX_QUEUE;
4814
441cabbb
MC		 4815 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4816 bp->max_tc = 1;
4817
87c374de
MC		 4818 if (bp->max_lltc > bp->max_tc)
4819 bp->max_lltc = bp->max_tc;
4820
c0c050c5
MC		 4821 qptr = &resp->queue_id0;
4822 for (i = 0; i < bp->max_tc; i++) {
4823 bp->q_info[i].queue_id = *qptr++;
4824 bp->q_info[i].queue_profile = *qptr++;
4825 }
4826
4827qportcfg_exit:
4828 mutex_unlock(&bp->hwrm_cmd_lock);
4829 return rc;
4830}
4831
4832static int bnxt_hwrm_ver_get(struct bnxt *bp)
4833{
4834 int rc;
4835 struct hwrm_ver_get_input req = {0};
4836 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
e605db80 4837 u32 dev_caps_cfg;
c0c050c5 4838
e6ef2699 4839 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
c0c050c5
MC		 4840 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4841 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4842 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4843 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4844 mutex_lock(&bp->hwrm_cmd_lock);
4845 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4846 if (rc)
4847 goto hwrm_ver_get_exit;
4848
4849 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4850
11f15ed3
MC		 4851 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4852 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
c193554e
MC		 4853 if (resp->hwrm_intf_maj < 1) {
4854 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
c0c050c5 4855 resp->hwrm_intf_maj, resp->hwrm_intf_min,
c193554e
MC		 4856 resp->hwrm_intf_upd);
4857 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5 4858 }
3ebf6f0a 4859 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
c0c050c5
MC		 4860 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4861 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4862
ff4fe81d
MC		 4863 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4864 if (!bp->hwrm_cmd_timeout)
4865 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4866
e6ef2699
MC		 4867 if (resp->hwrm_intf_maj >= 1)
4868 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4869
659c805c 4870 bp->chip_num = le16_to_cpu(resp->chip_num);
3e8060fa
PS		 4871 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4872 !resp->chip_metal)
4873 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
659c805c 4874
e605db80
DK		 4875 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
4876 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
4877 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
4878 bp->flags |= BNXT_FLAG_SHORT_CMD;
4879
c0c050c5
MC		 4880hwrm_ver_get_exit:
4881 mutex_unlock(&bp->hwrm_cmd_lock);
4882 return rc;
4883}
4884
5ac67d8b
RS		 4885int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4886{
878786d9 4887#if IS_ENABLED(CONFIG_RTC_LIB)
5ac67d8b
RS		 4888 struct hwrm_fw_set_time_input req = {0};
4889 struct rtc_time tm;
4890 struct timeval tv;
4891
4892 if (bp->hwrm_spec_code < 0x10400)
4893 return -EOPNOTSUPP;
4894
4895 do_gettimeofday(&tv);
4896 rtc_time_to_tm(tv.tv_sec, &tm);
4897 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4898 req.year = cpu_to_le16(1900 + tm.tm_year);
4899 req.month = 1 + tm.tm_mon;
4900 req.day = tm.tm_mday;
4901 req.hour = tm.tm_hour;
4902 req.minute = tm.tm_min;
4903 req.second = tm.tm_sec;
4904 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
878786d9
RS		 4905#else
4906 return -EOPNOTSUPP;
4907#endif
5ac67d8b
RS		 4908}
4909
3bdf56c4
MC		 4910static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4911{
4912 int rc;
4913 struct bnxt_pf_info *pf = &bp->pf;
4914 struct hwrm_port_qstats_input req = {0};
4915
4916 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4917 return 0;
4918
4919 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4920 req.port_id = cpu_to_le16(pf->port_id);
4921 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4922 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4923 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4924 return rc;
4925}
4926
c0c050c5
MC		 4927static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4928{
4929 if (bp->vxlan_port_cnt) {
4930 bnxt_hwrm_tunnel_dst_port_free(
4931 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4932 }
4933 bp->vxlan_port_cnt = 0;
4934 if (bp->nge_port_cnt) {
4935 bnxt_hwrm_tunnel_dst_port_free(
4936 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4937 }
4938 bp->nge_port_cnt = 0;
4939}
4940
4941static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4942{
4943 int rc, i;
4944 u32 tpa_flags = 0;
4945
4946 if (set_tpa)
4947 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4948 for (i = 0; i < bp->nr_vnics; i++) {
4949 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4950 if (rc) {
4951 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
23e12c89 4952 i, rc);
c0c050c5
MC		 4953 return rc;
4954 }
4955 }
4956 return 0;
4957}
4958
4959static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4960{
4961 int i;
4962
4963 for (i = 0; i < bp->nr_vnics; i++)
4964 bnxt_hwrm_vnic_set_rss(bp, i, false);
4965}
4966
4967static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4968 bool irq_re_init)
4969{
4970 if (bp->vnic_info) {
4971 bnxt_hwrm_clear_vnic_filter(bp);
4972 /* clear all RSS setting before free vnic ctx */
4973 bnxt_hwrm_clear_vnic_rss(bp);
4974 bnxt_hwrm_vnic_ctx_free(bp);
4975 /* before free the vnic, undo the vnic tpa settings */
4976 if (bp->flags & BNXT_FLAG_TPA)
4977 bnxt_set_tpa(bp, false);
4978 bnxt_hwrm_vnic_free(bp);
4979 }
4980 bnxt_hwrm_ring_free(bp, close_path);
4981 bnxt_hwrm_ring_grp_free(bp);
4982 if (irq_re_init) {
4983 bnxt_hwrm_stat_ctx_free(bp);
4984 bnxt_hwrm_free_tunnel_ports(bp);
4985 }
4986}
4987
39d8ba2e
MC		 4988static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
4989{
4990 struct hwrm_func_cfg_input req = {0};
4991 int rc;
4992
4993 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4994 req.fid = cpu_to_le16(0xffff);
4995 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
4996 if (br_mode == BRIDGE_MODE_VEB)
4997 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
4998 else if (br_mode == BRIDGE_MODE_VEPA)
4999 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5000 else
5001 return -EINVAL;
5002 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5003 if (rc)
5004 rc = -EIO;
5005 return rc;
5006}
5007
c0c050c5
MC		 5008static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5009{
ae10ae74 5010 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
c0c050c5
MC		 5011 int rc;
5012
ae10ae74
MC		 5013 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5014 goto skip_rss_ctx;
5015
c0c050c5 5016 /* allocate context for vnic */
94ce9caa 5017 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
c0c050c5
MC		 5018 if (rc) {
5019 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5020 vnic_id, rc);
5021 goto vnic_setup_err;
5022 }
5023 bp->rsscos_nr_ctxs++;
5024
94ce9caa
PS		 5025 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5026 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5027 if (rc) {
5028 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5029 vnic_id, rc);
5030 goto vnic_setup_err;
5031 }
5032 bp->rsscos_nr_ctxs++;
5033 }
5034
ae10ae74 5035skip_rss_ctx:
c0c050c5
MC		 5036 /* configure default vnic, ring grp */
5037 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5038 if (rc) {
5039 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5040 vnic_id, rc);
5041 goto vnic_setup_err;
5042 }
5043
5044 /* Enable RSS hashing on vnic */
5045 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5046 if (rc) {
5047 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5048 vnic_id, rc);
5049 goto vnic_setup_err;
5050 }
5051
5052 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5053 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5054 if (rc) {
5055 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5056 vnic_id, rc);
5057 }
5058 }
5059
5060vnic_setup_err:
5061 return rc;
5062}
5063
5064static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5065{
5066#ifdef CONFIG_RFS_ACCEL
5067 int i, rc = 0;
5068
5069 for (i = 0; i < bp->rx_nr_rings; i++) {
ae10ae74 5070 struct bnxt_vnic_info *vnic;
c0c050c5
MC		 5071 u16 vnic_id = i + 1;
5072 u16 ring_id = i;
5073
5074 if (vnic_id >= bp->nr_vnics)
5075 break;
5076
ae10ae74
MC		 5077 vnic = &bp->vnic_info[vnic_id];
5078 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5079 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5080 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
b81a90d3 5081 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 5082 if (rc) {
5083 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5084 vnic_id, rc);
5085 break;
5086 }
5087 rc = bnxt_setup_vnic(bp, vnic_id);
5088 if (rc)
5089 break;
5090 }
5091 return rc;
5092#else
5093 return 0;
5094#endif
5095}
5096
17c71ac3
MC		 5097/* Allow PF and VF with default VLAN to be in promiscuous mode */
5098static bool bnxt_promisc_ok(struct bnxt *bp)
5099{
5100#ifdef CONFIG_BNXT_SRIOV
5101 if (BNXT_VF(bp) && !bp->vf.vlan)
5102 return false;
5103#endif
5104 return true;
5105}
5106
dc52c6c7
PS		 5107static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5108{
5109 unsigned int rc = 0;
5110
5111 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5112 if (rc) {
5113 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5114 rc);
5115 return rc;
5116 }
5117
5118 rc = bnxt_hwrm_vnic_cfg(bp, 1);
5119 if (rc) {
5120 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5121 rc);
5122 return rc;
5123 }
5124 return rc;
5125}
5126
b664f008 5127static int bnxt_cfg_rx_mode(struct bnxt *);
7d2837dd 5128static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
b664f008 5129
c0c050c5
MC		 5130static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5131{
7d2837dd 5132 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
c0c050c5 5133 int rc = 0;
76595193 5134 unsigned int rx_nr_rings = bp->rx_nr_rings;
c0c050c5
MC		 5135
5136 if (irq_re_init) {
5137 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5138 if (rc) {
5139 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5140 rc);
5141 goto err_out;
5142 }
98fdbe73
MC		 5143 if (bp->tx_reserved_rings != bp->tx_nr_rings) {
5144 int tx = bp->tx_nr_rings;
5145
5146 if (bnxt_hwrm_reserve_tx_rings(bp, &tx) ||
5147 tx < bp->tx_nr_rings) {
5148 rc = -ENOMEM;
5149 goto err_out;
5150 }
5151 }
c0c050c5
MC		 5152 }
5153
5154 rc = bnxt_hwrm_ring_alloc(bp);
5155 if (rc) {
5156 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5157 goto err_out;
5158 }
5159
5160 rc = bnxt_hwrm_ring_grp_alloc(bp);
5161 if (rc) {
5162 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5163 goto err_out;
5164 }
5165
76595193
PS		 5166 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5167 rx_nr_rings--;
5168
c0c050c5 5169 /* default vnic 0 */
76595193 5170 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
c0c050c5
MC		 5171 if (rc) {
5172 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5173 goto err_out;
5174 }
5175
5176 rc = bnxt_setup_vnic(bp, 0);
5177 if (rc)
5178 goto err_out;
5179
5180 if (bp->flags & BNXT_FLAG_RFS) {
5181 rc = bnxt_alloc_rfs_vnics(bp);
5182 if (rc)
5183 goto err_out;
5184 }
5185
5186 if (bp->flags & BNXT_FLAG_TPA) {
5187 rc = bnxt_set_tpa(bp, true);
5188 if (rc)
5189 goto err_out;
5190 }
5191
5192 if (BNXT_VF(bp))
5193 bnxt_update_vf_mac(bp);
5194
5195 /* Filter for default vnic 0 */
5196 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5197 if (rc) {
5198 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5199 goto err_out;
5200 }
7d2837dd 5201 vnic->uc_filter_count = 1;
c0c050c5 5202
7d2837dd 5203 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5 5204
17c71ac3 5205 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7d2837dd
MC		 5206 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5207
5208 if (bp->dev->flags & IFF_ALLMULTI) {
5209 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5210 vnic->mc_list_count = 0;
5211 } else {
5212 u32 mask = 0;
5213
5214 bnxt_mc_list_updated(bp, &mask);
5215 vnic->rx_mask |= mask;
5216 }
c0c050c5 5217
b664f008
MC		 5218 rc = bnxt_cfg_rx_mode(bp);
5219 if (rc)
c0c050c5 5220 goto err_out;
c0c050c5
MC		 5221
5222 rc = bnxt_hwrm_set_coal(bp);
5223 if (rc)
5224 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
dc52c6c7
PS		 5225 rc);
5226
5227 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5228 rc = bnxt_setup_nitroa0_vnic(bp);
5229 if (rc)
5230 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5231 rc);
5232 }
c0c050c5 5233
cf6645f8
MC		 5234 if (BNXT_VF(bp)) {
5235 bnxt_hwrm_func_qcfg(bp);
5236 netdev_update_features(bp->dev);
5237 }
5238
c0c050c5
MC		 5239 return 0;
5240
5241err_out:
5242 bnxt_hwrm_resource_free(bp, 0, true);
5243
5244 return rc;
5245}
5246
5247static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5248{
5249 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5250 return 0;
5251}
5252
5253static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5254{
2247925f 5255 bnxt_init_cp_rings(bp);
c0c050c5
MC		 5256 bnxt_init_rx_rings(bp);
5257 bnxt_init_tx_rings(bp);
5258 bnxt_init_ring_grps(bp, irq_re_init);
5259 bnxt_init_vnics(bp);
5260
5261 return bnxt_init_chip(bp, irq_re_init);
5262}
5263
c0c050c5
MC		 5264static int bnxt_set_real_num_queues(struct bnxt *bp)
5265{
5266 int rc;
5267 struct net_device *dev = bp->dev;
5268
5f449249
MC		 5269 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5270 bp->tx_nr_rings_xdp);
c0c050c5
MC		 5271 if (rc)
5272 return rc;
5273
5274 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5275 if (rc)
5276 return rc;
5277
5278#ifdef CONFIG_RFS_ACCEL
45019a18 5279 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 5280 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 5281#endif
5282
5283 return rc;
5284}
5285
6e6c5a57
MC		 5286static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5287 bool shared)
5288{
5289 int _rx = *rx, _tx = *tx;
5290
5291 if (shared) {
5292 *rx = min_t(int, _rx, max);
5293 *tx = min_t(int, _tx, max);
5294 } else {
5295 if (max < 2)
5296 return -ENOMEM;
5297
5298 while (_rx + _tx > max) {
5299 if (_rx > _tx && _rx > 1)
5300 _rx--;
5301 else if (_tx > 1)
5302 _tx--;
5303 }
5304 *rx = _rx;
5305 *tx = _tx;
5306 }
5307 return 0;
5308}
5309
7809592d
MC		 5310static void bnxt_setup_msix(struct bnxt *bp)
5311{
5312 const int len = sizeof(bp->irq_tbl[0].name);
5313 struct net_device *dev = bp->dev;
5314 int tcs, i;
5315
5316 tcs = netdev_get_num_tc(dev);
5317 if (tcs > 1) {
d1e7925e 5318 int i, off, count;
7809592d 5319
d1e7925e
MC		 5320 for (i = 0; i < tcs; i++) {
5321 count = bp->tx_nr_rings_per_tc;
5322 off = i * count;
5323 netdev_set_tc_queue(dev, i, count, off);
7809592d
MC		 5324 }
5325 }
5326
5327 for (i = 0; i < bp->cp_nr_rings; i++) {
5328 char *attr;
5329
5330 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5331 attr = "TxRx";
5332 else if (i < bp->rx_nr_rings)
5333 attr = "rx";
5334 else
5335 attr = "tx";
5336
5337 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5338 i);
5339 bp->irq_tbl[i].handler = bnxt_msix;
5340 }
5341}
5342
5343static void bnxt_setup_inta(struct bnxt *bp)
5344{
5345 const int len = sizeof(bp->irq_tbl[0].name);
5346
5347 if (netdev_get_num_tc(bp->dev))
5348 netdev_reset_tc(bp->dev);
5349
5350 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5351 0);
5352 bp->irq_tbl[0].handler = bnxt_inta;
5353}
5354
5355static int bnxt_setup_int_mode(struct bnxt *bp)
5356{
5357 int rc;
5358
5359 if (bp->flags & BNXT_FLAG_USING_MSIX)
5360 bnxt_setup_msix(bp);
5361 else
5362 bnxt_setup_inta(bp);
5363
5364 rc = bnxt_set_real_num_queues(bp);
5365 return rc;
5366}
5367
b7429954 5368#ifdef CONFIG_RFS_ACCEL
8079e8f1
MC		 5369static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5370{
5371#if defined(CONFIG_BNXT_SRIOV)
5372 if (BNXT_VF(bp))
5373 return bp->vf.max_rsscos_ctxs;
5374#endif
5375 return bp->pf.max_rsscos_ctxs;
5376}
5377
5378static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5379{
5380#if defined(CONFIG_BNXT_SRIOV)
5381 if (BNXT_VF(bp))
5382 return bp->vf.max_vnics;
5383#endif
5384 return bp->pf.max_vnics;
5385}
b7429954 5386#endif
8079e8f1 5387
e4060d30
MC		 5388unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5389{
5390#if defined(CONFIG_BNXT_SRIOV)
5391 if (BNXT_VF(bp))
5392 return bp->vf.max_stat_ctxs;
5393#endif
5394 return bp->pf.max_stat_ctxs;
5395}
5396
a588e458
MC		 5397void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5398{
5399#if defined(CONFIG_BNXT_SRIOV)
5400 if (BNXT_VF(bp))
5401 bp->vf.max_stat_ctxs = max;
5402 else
5403#endif
5404 bp->pf.max_stat_ctxs = max;
5405}
5406
e4060d30
MC		 5407unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5408{
5409#if defined(CONFIG_BNXT_SRIOV)
5410 if (BNXT_VF(bp))
5411 return bp->vf.max_cp_rings;
5412#endif
5413 return bp->pf.max_cp_rings;
5414}
5415
a588e458
MC		 5416void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5417{
5418#if defined(CONFIG_BNXT_SRIOV)
5419 if (BNXT_VF(bp))
5420 bp->vf.max_cp_rings = max;
5421 else
5422#endif
5423 bp->pf.max_cp_rings = max;
5424}
5425
7809592d
MC		 5426static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5427{
5428#if defined(CONFIG_BNXT_SRIOV)
5429 if (BNXT_VF(bp))
68a946bb
MC		 5430 return min_t(unsigned int, bp->vf.max_irqs,
5431 bp->vf.max_cp_rings);
7809592d 5432#endif
68a946bb 5433 return min_t(unsigned int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7809592d
MC		 5434}
5435
33c2657e
MC		 5436void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5437{
5438#if defined(CONFIG_BNXT_SRIOV)
5439 if (BNXT_VF(bp))
5440 bp->vf.max_irqs = max_irqs;
5441 else
5442#endif
5443 bp->pf.max_irqs = max_irqs;
5444}
5445
7809592d 5446static int bnxt_init_msix(struct bnxt *bp)
c0c050c5 5447{
01657bcd 5448 int i, total_vecs, rc = 0, min = 1;
7809592d 5449 struct msix_entry *msix_ent;
c0c050c5 5450
7809592d 5451 total_vecs = bnxt_get_max_func_irqs(bp);
c0c050c5
MC		 5452 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5453 if (!msix_ent)
5454 return -ENOMEM;
5455
5456 for (i = 0; i < total_vecs; i++) {
5457 msix_ent[i].entry = i;
5458 msix_ent[i].vector = 0;
5459 }
5460
01657bcd
MC		 5461 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5462 min = 2;
5463
5464 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
c0c050c5
MC		 5465 if (total_vecs < 0) {
5466 rc = -ENODEV;
5467 goto msix_setup_exit;
5468 }
5469
5470 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5471 if (bp->irq_tbl) {
7809592d
MC		 5472 for (i = 0; i < total_vecs; i++)
5473 bp->irq_tbl[i].vector = msix_ent[i].vector;
c0c050c5 5474
7809592d 5475 bp->total_irqs = total_vecs;
c0c050c5 5476 /* Trim rings based upon num of vectors allocated */
6e6c5a57 5477 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
01657bcd 5478 total_vecs, min == 1);
6e6c5a57
MC		 5479 if (rc)
5480 goto msix_setup_exit;
5481
c0c050c5 5482 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7809592d
MC		 5483 bp->cp_nr_rings = (min == 1) ?
5484 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5485 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5 5486
c0c050c5
MC		 5487 } else {
5488 rc = -ENOMEM;
5489 goto msix_setup_exit;
5490 }
5491 bp->flags |= BNXT_FLAG_USING_MSIX;
5492 kfree(msix_ent);
5493 return 0;
5494
5495msix_setup_exit:
7809592d
MC		 5496 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5497 kfree(bp->irq_tbl);
5498 bp->irq_tbl = NULL;
c0c050c5
MC		 5499 pci_disable_msix(bp->pdev);
5500 kfree(msix_ent);
5501 return rc;
5502}
5503
7809592d 5504static int bnxt_init_inta(struct bnxt *bp)
c0c050c5 5505{
c0c050c5 5506 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7809592d
MC		 5507 if (!bp->irq_tbl)
5508 return -ENOMEM;
5509
5510 bp->total_irqs = 1;
c0c050c5
MC		 5511 bp->rx_nr_rings = 1;
5512 bp->tx_nr_rings = 1;
5513 bp->cp_nr_rings = 1;
5514 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
01657bcd 5515 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5 5516 bp->irq_tbl[0].vector = bp->pdev->irq;
7809592d 5517 return 0;
c0c050c5
MC		 5518}
5519
7809592d 5520static int bnxt_init_int_mode(struct bnxt *bp)
c0c050c5
MC		 5521{
5522 int rc = 0;
5523
5524 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7809592d 5525 rc = bnxt_init_msix(bp);
c0c050c5 5526
1fa72e29 5527 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
c0c050c5 5528 /* fallback to INTA */
7809592d 5529 rc = bnxt_init_inta(bp);
c0c050c5
MC		 5530 }
5531 return rc;
5532}
5533
7809592d
MC		 5534static void bnxt_clear_int_mode(struct bnxt *bp)
5535{
5536 if (bp->flags & BNXT_FLAG_USING_MSIX)
5537 pci_disable_msix(bp->pdev);
5538
5539 kfree(bp->irq_tbl);
5540 bp->irq_tbl = NULL;
5541 bp->flags &= ~BNXT_FLAG_USING_MSIX;
5542}
5543
c0c050c5
MC		 5544static void bnxt_free_irq(struct bnxt *bp)
5545{
5546 struct bnxt_irq *irq;
5547 int i;
5548
5549#ifdef CONFIG_RFS_ACCEL
5550 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5551 bp->dev->rx_cpu_rmap = NULL;
5552#endif
5553 if (!bp->irq_tbl)
5554 return;
5555
5556 for (i = 0; i < bp->cp_nr_rings; i++) {
5557 irq = &bp->irq_tbl[i];
56f0fd80
VV		 5558 if (irq->requested) {
5559 if (irq->have_cpumask) {
5560 irq_set_affinity_hint(irq->vector, NULL);
5561 free_cpumask_var(irq->cpu_mask);
5562 irq->have_cpumask = 0;
5563 }
c0c050c5 5564 free_irq(irq->vector, bp->bnapi[i]);
56f0fd80
VV		 5565 }
5566
c0c050c5
MC		 5567 irq->requested = 0;
5568 }
c0c050c5
MC		 5569}
5570
5571static int bnxt_request_irq(struct bnxt *bp)
5572{
b81a90d3 5573 int i, j, rc = 0;
c0c050c5
MC		 5574 unsigned long flags = 0;
5575#ifdef CONFIG_RFS_ACCEL
5576 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5577#endif
5578
5579 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5580 flags = IRQF_SHARED;
5581
b81a90d3 5582 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
c0c050c5
MC		 5583 struct bnxt_irq *irq = &bp->irq_tbl[i];
5584#ifdef CONFIG_RFS_ACCEL
b81a90d3 5585 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 5586 rc = irq_cpu_rmap_add(rmap, irq->vector);
5587 if (rc)
5588 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 5589 j);
5590 j++;
c0c050c5
MC		 5591 }
5592#endif
5593 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5594 bp->bnapi[i]);
5595 if (rc)
5596 break;
5597
5598 irq->requested = 1;
56f0fd80
VV		 5599
5600 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
5601 int numa_node = dev_to_node(&bp->pdev->dev);
5602
5603 irq->have_cpumask = 1;
5604 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
5605 irq->cpu_mask);
5606 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
5607 if (rc) {
5608 netdev_warn(bp->dev,
5609 "Set affinity failed, IRQ = %d\n",
5610 irq->vector);
5611 break;
5612 }
5613 }
c0c050c5
MC		 5614 }
5615 return rc;
5616}
5617
5618static void bnxt_del_napi(struct bnxt *bp)
5619{
5620 int i;
5621
5622 if (!bp->bnapi)
5623 return;
5624
5625 for (i = 0; i < bp->cp_nr_rings; i++) {
5626 struct bnxt_napi *bnapi = bp->bnapi[i];
5627
5628 napi_hash_del(&bnapi->napi);
5629 netif_napi_del(&bnapi->napi);
5630 }
e5f6f564
ED		 5631 /* We called napi_hash_del() before netif_napi_del(), we need
5632 * to respect an RCU grace period before freeing napi structures.
5633 */
5634 synchronize_net();
c0c050c5
MC		 5635}
5636
5637static void bnxt_init_napi(struct bnxt *bp)
5638{
5639 int i;
10bbdaf5 5640 unsigned int cp_nr_rings = bp->cp_nr_rings;
c0c050c5
MC		 5641 struct bnxt_napi *bnapi;
5642
5643 if (bp->flags & BNXT_FLAG_USING_MSIX) {
10bbdaf5
PS		 5644 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5645 cp_nr_rings--;
5646 for (i = 0; i < cp_nr_rings; i++) {
c0c050c5
MC		 5647 bnapi = bp->bnapi[i];
5648 netif_napi_add(bp->dev, &bnapi->napi,
5649 bnxt_poll, 64);
c0c050c5 5650 }
10bbdaf5
PS		 5651 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5652 bnapi = bp->bnapi[cp_nr_rings];
5653 netif_napi_add(bp->dev, &bnapi->napi,
5654 bnxt_poll_nitroa0, 64);
10bbdaf5 5655 }
c0c050c5
MC		 5656 } else {
5657 bnapi = bp->bnapi[0];
5658 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 5659 }
5660}
5661
5662static void bnxt_disable_napi(struct bnxt *bp)
5663{
5664 int i;
5665
5666 if (!bp->bnapi)
5667 return;
5668
b356a2e7 5669 for (i = 0; i < bp->cp_nr_rings; i++)
c0c050c5 5670 napi_disable(&bp->bnapi[i]->napi);
c0c050c5
MC		 5671}
5672
5673static void bnxt_enable_napi(struct bnxt *bp)
5674{
5675 int i;
5676
5677 for (i = 0; i < bp->cp_nr_rings; i++) {
fa7e2812 5678 bp->bnapi[i]->in_reset = false;
c0c050c5
MC		 5679 napi_enable(&bp->bnapi[i]->napi);
5680 }
5681}
5682
7df4ae9f 5683void bnxt_tx_disable(struct bnxt *bp)
c0c050c5
MC		 5684{
5685 int i;
c0c050c5 5686 struct bnxt_tx_ring_info *txr;
c0c050c5 5687
b6ab4b01 5688 if (bp->tx_ring) {
c0c050c5 5689 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 5690 txr = &bp->tx_ring[i];
c0c050c5 5691 txr->dev_state = BNXT_DEV_STATE_CLOSING;
c0c050c5
MC		 5692 }
5693 }
5694 /* Stop all TX queues */
5695 netif_tx_disable(bp->dev);
5696 netif_carrier_off(bp->dev);
5697}
5698
7df4ae9f 5699void bnxt_tx_enable(struct bnxt *bp)
c0c050c5
MC		 5700{
5701 int i;
c0c050c5 5702 struct bnxt_tx_ring_info *txr;
c0c050c5
MC		 5703
5704 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 5705 txr = &bp->tx_ring[i];
c0c050c5
MC		 5706 txr->dev_state = 0;
5707 }
5708 netif_tx_wake_all_queues(bp->dev);
5709 if (bp->link_info.link_up)
5710 netif_carrier_on(bp->dev);
5711}
5712
5713static void bnxt_report_link(struct bnxt *bp)
5714{
5715 if (bp->link_info.link_up) {
5716 const char *duplex;
5717 const char *flow_ctrl;
38a21b34
DK		 5718 u32 speed;
5719 u16 fec;
c0c050c5
MC		 5720
5721 netif_carrier_on(bp->dev);
5722 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5723 duplex = "full";
5724 else
5725 duplex = "half";
5726 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5727 flow_ctrl = "ON - receive & transmit";
5728 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5729 flow_ctrl = "ON - transmit";
5730 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5731 flow_ctrl = "ON - receive";
5732 else
5733 flow_ctrl = "none";
5734 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
38a21b34 5735 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
c0c050c5 5736 speed, duplex, flow_ctrl);
170ce013
MC		 5737 if (bp->flags & BNXT_FLAG_EEE_CAP)
5738 netdev_info(bp->dev, "EEE is %s\n",
5739 bp->eee.eee_active ? "active" :
5740 "not active");
e70c752f
MC		 5741 fec = bp->link_info.fec_cfg;
5742 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
5743 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
5744 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
5745 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
5746 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
c0c050c5
MC		 5747 } else {
5748 netif_carrier_off(bp->dev);
5749 netdev_err(bp->dev, "NIC Link is Down\n");
5750 }
5751}
5752
170ce013
MC		 5753static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5754{
5755 int rc = 0;
5756 struct hwrm_port_phy_qcaps_input req = {0};
5757 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
93ed8117 5758 struct bnxt_link_info *link_info = &bp->link_info;
170ce013
MC		 5759
5760 if (bp->hwrm_spec_code < 0x10201)
5761 return 0;
5762
5763 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5764
5765 mutex_lock(&bp->hwrm_cmd_lock);
5766 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5767 if (rc)
5768 goto hwrm_phy_qcaps_exit;
5769
acb20054 5770 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
170ce013
MC		 5771 struct ethtool_eee *eee = &bp->eee;
5772 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5773
5774 bp->flags |= BNXT_FLAG_EEE_CAP;
5775 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5776 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5777 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5778 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5779 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5780 }
520ad89a
MC		 5781 if (resp->supported_speeds_auto_mode)
5782 link_info->support_auto_speeds =
5783 le16_to_cpu(resp->supported_speeds_auto_mode);
170ce013
MC		 5784
5785hwrm_phy_qcaps_exit:
5786 mutex_unlock(&bp->hwrm_cmd_lock);
5787 return rc;
5788}
5789
c0c050c5
MC		 5790static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5791{
5792 int rc = 0;
5793 struct bnxt_link_info *link_info = &bp->link_info;
5794 struct hwrm_port_phy_qcfg_input req = {0};
5795 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5796 u8 link_up = link_info->link_up;
286ef9d6 5797 u16 diff;
c0c050c5
MC		 5798
5799 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5800
5801 mutex_lock(&bp->hwrm_cmd_lock);
5802 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5803 if (rc) {
5804 mutex_unlock(&bp->hwrm_cmd_lock);
5805 return rc;
5806 }
5807
5808 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5809 link_info->phy_link_status = resp->link;
acb20054
MC		 5810 link_info->duplex = resp->duplex_cfg;
5811 if (bp->hwrm_spec_code >= 0x10800)
5812 link_info->duplex = resp->duplex_state;
c0c050c5
MC		 5813 link_info->pause = resp->pause;
5814 link_info->auto_mode = resp->auto_mode;
5815 link_info->auto_pause_setting = resp->auto_pause;
3277360e 5816 link_info->lp_pause = resp->link_partner_adv_pause;
c0c050c5 5817 link_info->force_pause_setting = resp->force_pause;
acb20054 5818 link_info->duplex_setting = resp->duplex_cfg;
c0c050c5
MC		 5819 if (link_info->phy_link_status == BNXT_LINK_LINK)
5820 link_info->link_speed = le16_to_cpu(resp->link_speed);
5821 else
5822 link_info->link_speed = 0;
5823 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
c0c050c5
MC		 5824 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5825 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
3277360e
MC		 5826 link_info->lp_auto_link_speeds =
5827 le16_to_cpu(resp->link_partner_adv_speeds);
c0c050c5
MC		 5828 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5829 link_info->phy_ver[0] = resp->phy_maj;
5830 link_info->phy_ver[1] = resp->phy_min;
5831 link_info->phy_ver[2] = resp->phy_bld;
5832 link_info->media_type = resp->media_type;
03efbec0 5833 link_info->phy_type = resp->phy_type;
11f15ed3 5834 link_info->transceiver = resp->xcvr_pkg_type;
170ce013
MC		 5835 link_info->phy_addr = resp->eee_config_phy_addr &
5836 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
42ee18fe 5837 link_info->module_status = resp->module_status;
170ce013
MC		 5838
5839 if (bp->flags & BNXT_FLAG_EEE_CAP) {
5840 struct ethtool_eee *eee = &bp->eee;
5841 u16 fw_speeds;
5842
5843 eee->eee_active = 0;
5844 if (resp->eee_config_phy_addr &
5845 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5846 eee->eee_active = 1;
5847 fw_speeds = le16_to_cpu(
5848 resp->link_partner_adv_eee_link_speed_mask);
5849 eee->lp_advertised =
5850 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5851 }
5852
5853 /* Pull initial EEE config */
5854 if (!chng_link_state) {
5855 if (resp->eee_config_phy_addr &
5856 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5857 eee->eee_enabled = 1;
c0c050c5 5858
170ce013
MC		 5859 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5860 eee->advertised =
5861 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5862
5863 if (resp->eee_config_phy_addr &
5864 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5865 __le32 tmr;
5866
5867 eee->tx_lpi_enabled = 1;
5868 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5869 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5870 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5871 }
5872 }
5873 }
e70c752f
MC		 5874
5875 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
5876 if (bp->hwrm_spec_code >= 0x10504)
5877 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
5878
c0c050c5
MC		 5879 /* TODO: need to add more logic to report VF link */
5880 if (chng_link_state) {
5881 if (link_info->phy_link_status == BNXT_LINK_LINK)
5882 link_info->link_up = 1;
5883 else
5884 link_info->link_up = 0;
5885 if (link_up != link_info->link_up)
5886 bnxt_report_link(bp);
5887 } else {
5888 /* alwasy link down if not require to update link state */
5889 link_info->link_up = 0;
5890 }
5891 mutex_unlock(&bp->hwrm_cmd_lock);
286ef9d6
MC		 5892
5893 diff = link_info->support_auto_speeds ^ link_info->advertising;
5894 if ((link_info->support_auto_speeds | diff) !=
5895 link_info->support_auto_speeds) {
5896 /* An advertised speed is no longer supported, so we need to
0eaa24b9
MC		 5897 * update the advertisement settings. Caller holds RTNL
5898 * so we can modify link settings.
286ef9d6 5899 */
286ef9d6 5900 link_info->advertising = link_info->support_auto_speeds;
0eaa24b9 5901 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
286ef9d6 5902 bnxt_hwrm_set_link_setting(bp, true, false);
286ef9d6 5903 }
c0c050c5
MC		 5904 return 0;
5905}
5906
10289bec
MC		 5907static void bnxt_get_port_module_status(struct bnxt *bp)
5908{
5909 struct bnxt_link_info *link_info = &bp->link_info;
5910 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5911 u8 module_status;
5912
5913 if (bnxt_update_link(bp, true))
5914 return;
5915
5916 module_status = link_info->module_status;
5917 switch (module_status) {
5918 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5919 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5920 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5921 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5922 bp->pf.port_id);
5923 if (bp->hwrm_spec_code >= 0x10201) {
5924 netdev_warn(bp->dev, "Module part number %s\n",
5925 resp->phy_vendor_partnumber);
5926 }
5927 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5928 netdev_warn(bp->dev, "TX is disabled\n");
5929 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5930 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5931 }
5932}
5933
c0c050c5
MC		 5934static void
5935bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5936{
5937 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
c9ee9516
MC		 5938 if (bp->hwrm_spec_code >= 0x10201)
5939 req->auto_pause =
5940 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
c0c050c5
MC		 5941 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5942 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5943 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
49b5c7a1 5944 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
c0c050c5
MC		 5945 req->enables |=
5946 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5947 } else {
5948 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5949 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5950 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5951 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5952 req->enables |=
5953 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
c9ee9516
MC		 5954 if (bp->hwrm_spec_code >= 0x10201) {
5955 req->auto_pause = req->force_pause;
5956 req->enables |= cpu_to_le32(
5957 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5958 }
c0c050c5
MC		 5959 }
5960}
5961
5962static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5963 struct hwrm_port_phy_cfg_input *req)
5964{
5965 u8 autoneg = bp->link_info.autoneg;
5966 u16 fw_link_speed = bp->link_info.req_link_speed;
68515a18 5967 u16 advertising = bp->link_info.advertising;
c0c050c5
MC		 5968
5969 if (autoneg & BNXT_AUTONEG_SPEED) {
5970 req->auto_mode |=
11f15ed3 5971 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
c0c050c5
MC		 5972
5973 req->enables |= cpu_to_le32(
5974 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5975 req->auto_link_speed_mask = cpu_to_le16(advertising);
5976
5977 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5978 req->flags |=
5979 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5980 } else {
5981 req->force_link_speed = cpu_to_le16(fw_link_speed);
5982 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5983 }
5984
c0c050c5
MC		 5985 /* tell chimp that the setting takes effect immediately */
5986 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5987}
5988
5989int bnxt_hwrm_set_pause(struct bnxt *bp)
5990{
5991 struct hwrm_port_phy_cfg_input req = {0};
5992 int rc;
5993
5994 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5995 bnxt_hwrm_set_pause_common(bp, &req);
5996
5997 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5998 bp->link_info.force_link_chng)
5999 bnxt_hwrm_set_link_common(bp, &req);
6000
6001 mutex_lock(&bp->hwrm_cmd_lock);
6002 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6003 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6004 /* since changing of pause setting doesn't trigger any link
6005 * change event, the driver needs to update the current pause
6006 * result upon successfully return of the phy_cfg command
6007 */
6008 bp->link_info.pause =
6009 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6010 bp->link_info.auto_pause_setting = 0;
6011 if (!bp->link_info.force_link_chng)
6012 bnxt_report_link(bp);
6013 }
6014 bp->link_info.force_link_chng = false;
6015 mutex_unlock(&bp->hwrm_cmd_lock);
6016 return rc;
6017}
6018
939f7f0c
MC		 6019static void bnxt_hwrm_set_eee(struct bnxt *bp,
6020 struct hwrm_port_phy_cfg_input *req)
6021{
6022 struct ethtool_eee *eee = &bp->eee;
6023
6024 if (eee->eee_enabled) {
6025 u16 eee_speeds;
6026 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6027
6028 if (eee->tx_lpi_enabled)
6029 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6030 else
6031 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6032
6033 req->flags |= cpu_to_le32(flags);
6034 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6035 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6036 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6037 } else {
6038 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6039 }
6040}
6041
6042int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
c0c050c5
MC		 6043{
6044 struct hwrm_port_phy_cfg_input req = {0};
6045
6046 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6047 if (set_pause)
6048 bnxt_hwrm_set_pause_common(bp, &req);
6049
6050 bnxt_hwrm_set_link_common(bp, &req);
939f7f0c
MC		 6051
6052 if (set_eee)
6053 bnxt_hwrm_set_eee(bp, &req);
c0c050c5
MC		 6054 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6055}
6056
33f7d55f
MC		 6057static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6058{
6059 struct hwrm_port_phy_cfg_input req = {0};
6060
567b2abe 6061 if (!BNXT_SINGLE_PF(bp))
33f7d55f
MC		 6062 return 0;
6063
6064 if (pci_num_vf(bp->pdev))
6065 return 0;
6066
6067 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
16d663a6 6068 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
33f7d55f
MC		 6069 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6070}
6071
5ad2cbee
MC		 6072static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6073{
6074 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6075 struct hwrm_port_led_qcaps_input req = {0};
6076 struct bnxt_pf_info *pf = &bp->pf;
6077 int rc;
6078
6079 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6080 return 0;
6081
6082 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6083 req.port_id = cpu_to_le16(pf->port_id);
6084 mutex_lock(&bp->hwrm_cmd_lock);
6085 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6086 if (rc) {
6087 mutex_unlock(&bp->hwrm_cmd_lock);
6088 return rc;
6089 }
6090 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6091 int i;
6092
6093 bp->num_leds = resp->num_leds;
6094 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6095 bp->num_leds);
6096 for (i = 0; i < bp->num_leds; i++) {
6097 struct bnxt_led_info *led = &bp->leds[i];
6098 __le16 caps = led->led_state_caps;
6099
6100 if (!led->led_group_id ||
6101 !BNXT_LED_ALT_BLINK_CAP(caps)) {
6102 bp->num_leds = 0;
6103 break;
6104 }
6105 }
6106 }
6107 mutex_unlock(&bp->hwrm_cmd_lock);
6108 return 0;
6109}
6110
5282db6c
MC		 6111int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6112{
6113 struct hwrm_wol_filter_alloc_input req = {0};
6114 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6115 int rc;
6116
6117 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6118 req.port_id = cpu_to_le16(bp->pf.port_id);
6119 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6120 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6121 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6122 mutex_lock(&bp->hwrm_cmd_lock);
6123 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6124 if (!rc)
6125 bp->wol_filter_id = resp->wol_filter_id;
6126 mutex_unlock(&bp->hwrm_cmd_lock);
6127 return rc;
6128}
6129
6130int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6131{
6132 struct hwrm_wol_filter_free_input req = {0};
6133 int rc;
6134
6135 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6136 req.port_id = cpu_to_le16(bp->pf.port_id);
6137 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6138 req.wol_filter_id = bp->wol_filter_id;
6139 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6140 return rc;
6141}
6142
c1ef146a
MC		 6143static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6144{
6145 struct hwrm_wol_filter_qcfg_input req = {0};
6146 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6147 u16 next_handle = 0;
6148 int rc;
6149
6150 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6151 req.port_id = cpu_to_le16(bp->pf.port_id);
6152 req.handle = cpu_to_le16(handle);
6153 mutex_lock(&bp->hwrm_cmd_lock);
6154 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6155 if (!rc) {
6156 next_handle = le16_to_cpu(resp->next_handle);
6157 if (next_handle != 0) {
6158 if (resp->wol_type ==
6159 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6160 bp->wol = 1;
6161 bp->wol_filter_id = resp->wol_filter_id;
6162 }
6163 }
6164 }
6165 mutex_unlock(&bp->hwrm_cmd_lock);
6166 return next_handle;
6167}
6168
6169static void bnxt_get_wol_settings(struct bnxt *bp)
6170{
6171 u16 handle = 0;
6172
6173 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6174 return;
6175
6176 do {
6177 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6178 } while (handle && handle != 0xffff);
6179}
6180
939f7f0c
MC		 6181static bool bnxt_eee_config_ok(struct bnxt *bp)
6182{
6183 struct ethtool_eee *eee = &bp->eee;
6184 struct bnxt_link_info *link_info = &bp->link_info;
6185
6186 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6187 return true;
6188
6189 if (eee->eee_enabled) {
6190 u32 advertising =
6191 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6192
6193 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6194 eee->eee_enabled = 0;
6195 return false;
6196 }
6197 if (eee->advertised & ~advertising) {
6198 eee->advertised = advertising & eee->supported;
6199 return false;
6200 }
6201 }
6202 return true;
6203}
6204
c0c050c5
MC		 6205static int bnxt_update_phy_setting(struct bnxt *bp)
6206{
6207 int rc;
6208 bool update_link = false;
6209 bool update_pause = false;
939f7f0c 6210 bool update_eee = false;
c0c050c5
MC		 6211 struct bnxt_link_info *link_info = &bp->link_info;
6212
6213 rc = bnxt_update_link(bp, true);
6214 if (rc) {
6215 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6216 rc);
6217 return rc;
6218 }
33dac24a
MC		 6219 if (!BNXT_SINGLE_PF(bp))
6220 return 0;
6221
c0c050c5 6222 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
c9ee9516
MC		 6223 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6224 link_info->req_flow_ctrl)
c0c050c5
MC		 6225 update_pause = true;
6226 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6227 link_info->force_pause_setting != link_info->req_flow_ctrl)
6228 update_pause = true;
c0c050c5
MC		 6229 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6230 if (BNXT_AUTO_MODE(link_info->auto_mode))
6231 update_link = true;
6232 if (link_info->req_link_speed != link_info->force_link_speed)
6233 update_link = true;
de73018f
MC		 6234 if (link_info->req_duplex != link_info->duplex_setting)
6235 update_link = true;
c0c050c5
MC		 6236 } else {
6237 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6238 update_link = true;
6239 if (link_info->advertising != link_info->auto_link_speeds)
6240 update_link = true;
c0c050c5
MC		 6241 }
6242
16d663a6
MC		 6243 /* The last close may have shutdown the link, so need to call
6244 * PHY_CFG to bring it back up.
6245 */
6246 if (!netif_carrier_ok(bp->dev))
6247 update_link = true;
6248
939f7f0c
MC		 6249 if (!bnxt_eee_config_ok(bp))
6250 update_eee = true;
6251
c0c050c5 6252 if (update_link)
939f7f0c 6253 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
c0c050c5
MC		 6254 else if (update_pause)
6255 rc = bnxt_hwrm_set_pause(bp);
6256 if (rc) {
6257 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6258 rc);
6259 return rc;
6260 }
6261
6262 return rc;
6263}
6264
11809490
JH		 6265/* Common routine to pre-map certain register block to different GRC window.
6266 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6267 * in PF and 3 windows in VF that can be customized to map in different
6268 * register blocks.
6269 */
6270static void bnxt_preset_reg_win(struct bnxt *bp)
6271{
6272 if (BNXT_PF(bp)) {
6273 /* CAG registers map to GRC window #4 */
6274 writel(BNXT_CAG_REG_BASE,
6275 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6276 }
6277}
6278
c0c050c5
MC		 6279static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6280{
6281 int rc = 0;
6282
11809490 6283 bnxt_preset_reg_win(bp);
c0c050c5
MC		 6284 netif_carrier_off(bp->dev);
6285 if (irq_re_init) {
6286 rc = bnxt_setup_int_mode(bp);
6287 if (rc) {
6288 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6289 rc);
6290 return rc;
6291 }
6292 }
6293 if ((bp->flags & BNXT_FLAG_RFS) &&
6294 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6295 /* disable RFS if falling back to INTA */
6296 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6297 bp->flags &= ~BNXT_FLAG_RFS;
6298 }
6299
6300 rc = bnxt_alloc_mem(bp, irq_re_init);
6301 if (rc) {
6302 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6303 goto open_err_free_mem;
6304 }
6305
6306 if (irq_re_init) {
6307 bnxt_init_napi(bp);
6308 rc = bnxt_request_irq(bp);
6309 if (rc) {
6310 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6311 goto open_err;
6312 }
6313 }
6314
6315 bnxt_enable_napi(bp);
6316
6317 rc = bnxt_init_nic(bp, irq_re_init);
6318 if (rc) {
6319 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6320 goto open_err;
6321 }
6322
6323 if (link_re_init) {
6324 rc = bnxt_update_phy_setting(bp);
6325 if (rc)
ba41d46f 6326 netdev_warn(bp->dev, "failed to update phy settings\n");
c0c050c5
MC		 6327 }
6328
7cdd5fc3 6329 if (irq_re_init)
ad51b8e9 6330 udp_tunnel_get_rx_info(bp->dev);
c0c050c5 6331
caefe526 6332 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 6333 bnxt_enable_int(bp);
6334 /* Enable TX queues */
6335 bnxt_tx_enable(bp);
6336 mod_timer(&bp->timer, jiffies + bp->current_interval);
10289bec
MC		 6337 /* Poll link status and check for SFP+ module status */
6338 bnxt_get_port_module_status(bp);
c0c050c5 6339
ee5c7fb3
SP		 6340 /* VF-reps may need to be re-opened after the PF is re-opened */
6341 if (BNXT_PF(bp))
6342 bnxt_vf_reps_open(bp);
c0c050c5
MC		 6343 return 0;
6344
6345open_err:
6346 bnxt_disable_napi(bp);
6347 bnxt_del_napi(bp);
6348
6349open_err_free_mem:
6350 bnxt_free_skbs(bp);
6351 bnxt_free_irq(bp);
6352 bnxt_free_mem(bp, true);
6353 return rc;
6354}
6355
6356/* rtnl_lock held */
6357int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6358{
6359 int rc = 0;
6360
6361 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6362 if (rc) {
6363 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6364 dev_close(bp->dev);
6365 }
6366 return rc;
6367}
6368
f7dc1ea6
MC		 6369/* rtnl_lock held, open the NIC half way by allocating all resources, but
6370 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
6371 * self tests.
6372 */
6373int bnxt_half_open_nic(struct bnxt *bp)
6374{
6375 int rc = 0;
6376
6377 rc = bnxt_alloc_mem(bp, false);
6378 if (rc) {
6379 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6380 goto half_open_err;
6381 }
6382 rc = bnxt_init_nic(bp, false);
6383 if (rc) {
6384 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6385 goto half_open_err;
6386 }
6387 return 0;
6388
6389half_open_err:
6390 bnxt_free_skbs(bp);
6391 bnxt_free_mem(bp, false);
6392 dev_close(bp->dev);
6393 return rc;
6394}
6395
6396/* rtnl_lock held, this call can only be made after a previous successful
6397 * call to bnxt_half_open_nic().
6398 */
6399void bnxt_half_close_nic(struct bnxt *bp)
6400{
6401 bnxt_hwrm_resource_free(bp, false, false);
6402 bnxt_free_skbs(bp);
6403 bnxt_free_mem(bp, false);
6404}
6405
c0c050c5
MC		 6406static int bnxt_open(struct net_device *dev)
6407{
6408 struct bnxt *bp = netdev_priv(dev);
c0c050c5 6409
c0c050c5
MC		 6410 return __bnxt_open_nic(bp, true, true);
6411}
6412
f9b76ebd
MC		 6413static bool bnxt_drv_busy(struct bnxt *bp)
6414{
6415 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
6416 test_bit(BNXT_STATE_READ_STATS, &bp->state));
6417}
6418
c0c050c5
MC		 6419int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6420{
6421 int rc = 0;
6422
6423#ifdef CONFIG_BNXT_SRIOV
6424 if (bp->sriov_cfg) {
6425 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6426 !bp->sriov_cfg,
6427 BNXT_SRIOV_CFG_WAIT_TMO);
6428 if (rc)
6429 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6430 }
ee5c7fb3
SP		 6431
6432 /* Close the VF-reps before closing PF */
6433 if (BNXT_PF(bp))
6434 bnxt_vf_reps_close(bp);
c0c050c5
MC		 6435#endif
6436 /* Change device state to avoid TX queue wake up's */
6437 bnxt_tx_disable(bp);
6438
caefe526 6439 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec 6440 smp_mb__after_atomic();
f9b76ebd 6441 while (bnxt_drv_busy(bp))
4cebdcec 6442 msleep(20);
c0c050c5 6443
9d8bc097 6444 /* Flush rings and and disable interrupts */
c0c050c5
MC		 6445 bnxt_shutdown_nic(bp, irq_re_init);
6446
6447 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6448
6449 bnxt_disable_napi(bp);
c0c050c5
MC		 6450 del_timer_sync(&bp->timer);
6451 bnxt_free_skbs(bp);
6452
6453 if (irq_re_init) {
6454 bnxt_free_irq(bp);
6455 bnxt_del_napi(bp);
6456 }
6457 bnxt_free_mem(bp, irq_re_init);
6458 return rc;
6459}
6460
6461static int bnxt_close(struct net_device *dev)
6462{
6463 struct bnxt *bp = netdev_priv(dev);
6464
6465 bnxt_close_nic(bp, true, true);
33f7d55f 6466 bnxt_hwrm_shutdown_link(bp);
c0c050c5
MC		 6467 return 0;
6468}
6469
6470/* rtnl_lock held */
6471static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6472{
6473 switch (cmd) {
6474 case SIOCGMIIPHY:
6475 /* fallthru */
6476 case SIOCGMIIREG: {
6477 if (!netif_running(dev))
6478 return -EAGAIN;
6479
6480 return 0;
6481 }
6482
6483 case SIOCSMIIREG:
6484 if (!netif_running(dev))
6485 return -EAGAIN;
6486
6487 return 0;
6488
6489 default:
6490 /* do nothing */
6491 break;
6492 }
6493 return -EOPNOTSUPP;
6494}
6495
bc1f4470 6496static void
c0c050c5
MC		 6497bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6498{
6499 u32 i;
6500 struct bnxt *bp = netdev_priv(dev);
6501
f9b76ebd
MC		 6502 set_bit(BNXT_STATE_READ_STATS, &bp->state);
6503 /* Make sure bnxt_close_nic() sees that we are reading stats before
6504 * we check the BNXT_STATE_OPEN flag.
6505 */
6506 smp_mb__after_atomic();
6507 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6508 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
bc1f4470 6509 return;
f9b76ebd 6510 }
c0c050c5
MC		 6511
6512 /* TODO check if we need to synchronize with bnxt_close path */
6513 for (i = 0; i < bp->cp_nr_rings; i++) {
6514 struct bnxt_napi *bnapi = bp->bnapi[i];
6515 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6516 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6517
6518 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6519 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6520 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6521
6522 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6523 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6524 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6525
6526 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6527 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6528 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6529
6530 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6531 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6532 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6533
6534 stats->rx_missed_errors +=
6535 le64_to_cpu(hw_stats->rx_discard_pkts);
6536
6537 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6538
c0c050c5
MC		 6539 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6540 }
6541
9947f83f
MC		 6542 if (bp->flags & BNXT_FLAG_PORT_STATS) {
6543 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6544 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6545
6546 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6547 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6548 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6549 le64_to_cpu(rx->rx_ovrsz_frames) +
6550 le64_to_cpu(rx->rx_runt_frames);
6551 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6552 le64_to_cpu(rx->rx_jbr_frames);
6553 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6554 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6555 stats->tx_errors = le64_to_cpu(tx->tx_err);
6556 }
f9b76ebd 6557 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
c0c050c5
MC		 6558}
6559
6560static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6561{
6562 struct net_device *dev = bp->dev;
6563 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6564 struct netdev_hw_addr *ha;
6565 u8 *haddr;
6566 int mc_count = 0;
6567 bool update = false;
6568 int off = 0;
6569
6570 netdev_for_each_mc_addr(ha, dev) {
6571 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6572 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6573 vnic->mc_list_count = 0;
6574 return false;
6575 }
6576 haddr = ha->addr;
6577 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6578 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6579 update = true;
6580 }
6581 off += ETH_ALEN;
6582 mc_count++;
6583 }
6584 if (mc_count)
6585 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6586
6587 if (mc_count != vnic->mc_list_count) {
6588 vnic->mc_list_count = mc_count;
6589 update = true;
6590 }
6591 return update;
6592}
6593
6594static bool bnxt_uc_list_updated(struct bnxt *bp)
6595{
6596 struct net_device *dev = bp->dev;
6597 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6598 struct netdev_hw_addr *ha;
6599 int off = 0;
6600
6601 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6602 return true;
6603
6604 netdev_for_each_uc_addr(ha, dev) {
6605 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6606 return true;
6607
6608 off += ETH_ALEN;
6609 }
6610 return false;
6611}
6612
6613static void bnxt_set_rx_mode(struct net_device *dev)
6614{
6615 struct bnxt *bp = netdev_priv(dev);
6616 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6617 u32 mask = vnic->rx_mask;
6618 bool mc_update = false;
6619 bool uc_update;
6620
6621 if (!netif_running(dev))
6622 return;
6623
6624 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6625 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6626 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6627
17c71ac3 6628 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
c0c050c5
MC		 6629 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6630
6631 uc_update = bnxt_uc_list_updated(bp);
6632
6633 if (dev->flags & IFF_ALLMULTI) {
6634 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6635 vnic->mc_list_count = 0;
6636 } else {
6637 mc_update = bnxt_mc_list_updated(bp, &mask);
6638 }
6639
6640 if (mask != vnic->rx_mask || uc_update || mc_update) {
6641 vnic->rx_mask = mask;
6642
6643 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6644 schedule_work(&bp->sp_task);
6645 }
6646}
6647
b664f008 6648static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 6649{
6650 struct net_device *dev = bp->dev;
6651 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6652 struct netdev_hw_addr *ha;
6653 int i, off = 0, rc;
6654 bool uc_update;
6655
6656 netif_addr_lock_bh(dev);
6657 uc_update = bnxt_uc_list_updated(bp);
6658 netif_addr_unlock_bh(dev);
6659
6660 if (!uc_update)
6661 goto skip_uc;
6662
6663 mutex_lock(&bp->hwrm_cmd_lock);
6664 for (i = 1; i < vnic->uc_filter_count; i++) {
6665 struct hwrm_cfa_l2_filter_free_input req = {0};
6666
6667 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6668 -1);
6669
6670 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6671
6672 rc = _hwrm_send_message(bp, &req, sizeof(req),
6673 HWRM_CMD_TIMEOUT);
6674 }
6675 mutex_unlock(&bp->hwrm_cmd_lock);
6676
6677 vnic->uc_filter_count = 1;
6678
6679 netif_addr_lock_bh(dev);
6680 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6681 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6682 } else {
6683 netdev_for_each_uc_addr(ha, dev) {
6684 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6685 off += ETH_ALEN;
6686 vnic->uc_filter_count++;
6687 }
6688 }
6689 netif_addr_unlock_bh(dev);
6690
6691 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6692 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6693 if (rc) {
6694 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6695 rc);
6696 vnic->uc_filter_count = i;
b664f008 6697 return rc;
c0c050c5
MC		 6698 }
6699 }
6700
6701skip_uc:
6702 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6703 if (rc)
6704 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6705 rc);
b664f008
MC		 6706
6707 return rc;
c0c050c5
MC		 6708}
6709
8079e8f1
MC		 6710/* If the chip and firmware supports RFS */
6711static bool bnxt_rfs_supported(struct bnxt *bp)
6712{
6713 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6714 return true;
ae10ae74
MC		 6715 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6716 return true;
8079e8f1
MC		 6717 return false;
6718}
6719
6720/* If runtime conditions support RFS */
2bcfa6f6
MC		 6721static bool bnxt_rfs_capable(struct bnxt *bp)
6722{
6723#ifdef CONFIG_RFS_ACCEL
8079e8f1 6724 int vnics, max_vnics, max_rss_ctxs;
2bcfa6f6 6725
964fd480 6726 if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
2bcfa6f6
MC		 6727 return false;
6728
6729 vnics = 1 + bp->rx_nr_rings;
8079e8f1
MC		 6730 max_vnics = bnxt_get_max_func_vnics(bp);
6731 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
ae10ae74
MC		 6732
6733 /* RSS contexts not a limiting factor */
6734 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6735 max_rss_ctxs = max_vnics;
8079e8f1 6736 if (vnics > max_vnics || vnics > max_rss_ctxs) {
a2304909
VV		 6737 netdev_warn(bp->dev,
6738 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
8079e8f1 6739 min(max_rss_ctxs - 1, max_vnics - 1));
2bcfa6f6 6740 return false;
a2304909 6741 }
2bcfa6f6
MC		 6742
6743 return true;
6744#else
6745 return false;
6746#endif
6747}
6748
c0c050c5
MC		 6749static netdev_features_t bnxt_fix_features(struct net_device *dev,
6750 netdev_features_t features)
6751{
2bcfa6f6
MC		 6752 struct bnxt *bp = netdev_priv(dev);
6753
a2304909 6754 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
2bcfa6f6 6755 features &= ~NETIF_F_NTUPLE;
5a9f6b23
MC		 6756
6757 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6758 * turned on or off together.
6759 */
6760 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6761 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6762 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6763 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6764 NETIF_F_HW_VLAN_STAG_RX);
6765 else
6766 features |= NETIF_F_HW_VLAN_CTAG_RX |
6767 NETIF_F_HW_VLAN_STAG_RX;
6768 }
cf6645f8
MC		 6769#ifdef CONFIG_BNXT_SRIOV
6770 if (BNXT_VF(bp)) {
6771 if (bp->vf.vlan) {
6772 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6773 NETIF_F_HW_VLAN_STAG_RX);
6774 }
6775 }
6776#endif
c0c050c5
MC		 6777 return features;
6778}
6779
6780static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6781{
6782 struct bnxt *bp = netdev_priv(dev);
6783 u32 flags = bp->flags;
6784 u32 changes;
6785 int rc = 0;
6786 bool re_init = false;
6787 bool update_tpa = false;
6788
6789 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
3e8060fa 6790 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
c0c050c5
MC		 6791 flags |= BNXT_FLAG_GRO;
6792 if (features & NETIF_F_LRO)
6793 flags |= BNXT_FLAG_LRO;
6794
bdbd1eb5
MC		 6795 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6796 flags &= ~BNXT_FLAG_TPA;
6797
c0c050c5
MC		 6798 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6799 flags |= BNXT_FLAG_STRIP_VLAN;
6800
6801 if (features & NETIF_F_NTUPLE)
6802 flags |= BNXT_FLAG_RFS;
6803
6804 changes = flags ^ bp->flags;
6805 if (changes & BNXT_FLAG_TPA) {
6806 update_tpa = true;
6807 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6808 (flags & BNXT_FLAG_TPA) == 0)
6809 re_init = true;
6810 }
6811
6812 if (changes & ~BNXT_FLAG_TPA)
6813 re_init = true;
6814
6815 if (flags != bp->flags) {
6816 u32 old_flags = bp->flags;
6817
6818 bp->flags = flags;
6819
2bcfa6f6 6820 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 6821 if (update_tpa)
6822 bnxt_set_ring_params(bp);
6823 return rc;
6824 }
6825
6826 if (re_init) {
6827 bnxt_close_nic(bp, false, false);
6828 if (update_tpa)
6829 bnxt_set_ring_params(bp);
6830
6831 return bnxt_open_nic(bp, false, false);
6832 }
6833 if (update_tpa) {
6834 rc = bnxt_set_tpa(bp,
6835 (flags & BNXT_FLAG_TPA) ?
6836 true : false);
6837 if (rc)
6838 bp->flags = old_flags;
6839 }
6840 }
6841 return rc;
6842}
6843
9f554590
MC		 6844static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6845{
b6ab4b01 6846 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 6847 int i = bnapi->index;
6848
3b2b7d9d
MC		 6849 if (!txr)
6850 return;
6851
9f554590
MC		 6852 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6853 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6854 txr->tx_cons);
6855}
6856
6857static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6858{
b6ab4b01 6859 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 6860 int i = bnapi->index;
6861
3b2b7d9d
MC		 6862 if (!rxr)
6863 return;
6864
9f554590
MC		 6865 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6866 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6867 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6868 rxr->rx_sw_agg_prod);
6869}
6870
6871static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6872{
6873 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6874 int i = bnapi->index;
6875
6876 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6877 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6878}
6879
c0c050c5
MC		 6880static void bnxt_dbg_dump_states(struct bnxt *bp)
6881{
6882 int i;
6883 struct bnxt_napi *bnapi;
c0c050c5
MC		 6884
6885 for (i = 0; i < bp->cp_nr_rings; i++) {
6886 bnapi = bp->bnapi[i];
c0c050c5 6887 if (netif_msg_drv(bp)) {
9f554590
MC		 6888 bnxt_dump_tx_sw_state(bnapi);
6889 bnxt_dump_rx_sw_state(bnapi);
6890 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 6891 }
6892 }
6893}
6894
6988bd92 6895static void bnxt_reset_task(struct bnxt *bp, bool silent)
c0c050c5 6896{
6988bd92
MC		 6897 if (!silent)
6898 bnxt_dbg_dump_states(bp);
028de140 6899 if (netif_running(bp->dev)) {
b386cd36
MC		 6900 int rc;
6901
6902 if (!silent)
6903 bnxt_ulp_stop(bp);
028de140 6904 bnxt_close_nic(bp, false, false);
b386cd36
MC		 6905 rc = bnxt_open_nic(bp, false, false);
6906 if (!silent && !rc)
6907 bnxt_ulp_start(bp);
028de140 6908 }
c0c050c5
MC		 6909}
6910
6911static void bnxt_tx_timeout(struct net_device *dev)
6912{
6913 struct bnxt *bp = netdev_priv(dev);
6914
6915 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
6916 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6917 schedule_work(&bp->sp_task);
6918}
6919
6920#ifdef CONFIG_NET_POLL_CONTROLLER
6921static void bnxt_poll_controller(struct net_device *dev)
6922{
6923 struct bnxt *bp = netdev_priv(dev);
6924 int i;
6925
2270bc5d
MC		 6926 /* Only process tx rings/combined rings in netpoll mode. */
6927 for (i = 0; i < bp->tx_nr_rings; i++) {
6928 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5 6929
2270bc5d 6930 napi_schedule(&txr->bnapi->napi);
c0c050c5
MC		 6931 }
6932}
6933#endif
6934
6935static void bnxt_timer(unsigned long data)
6936{
6937 struct bnxt *bp = (struct bnxt *)data;
6938 struct net_device *dev = bp->dev;
6939
6940 if (!netif_running(dev))
6941 return;
6942
6943 if (atomic_read(&bp->intr_sem) != 0)
6944 goto bnxt_restart_timer;
6945
adcc331e
MC		 6946 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
6947 bp->stats_coal_ticks) {
3bdf56c4
MC		 6948 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6949 schedule_work(&bp->sp_task);
6950 }
c0c050c5
MC		 6951bnxt_restart_timer:
6952 mod_timer(&bp->timer, jiffies + bp->current_interval);
6953}
6954
a551ee94 6955static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6988bd92 6956{
a551ee94
MC		 6957 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6958 * set. If the device is being closed, bnxt_close() may be holding
6988bd92
MC		 6959 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
6960 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6961 */
6962 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6963 rtnl_lock();
a551ee94
MC		 6964}
6965
6966static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
6967{
6988bd92
MC		 6968 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6969 rtnl_unlock();
6970}
6971
a551ee94
MC		 6972/* Only called from bnxt_sp_task() */
6973static void bnxt_reset(struct bnxt *bp, bool silent)
6974{
6975 bnxt_rtnl_lock_sp(bp);
6976 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6977 bnxt_reset_task(bp, silent);
6978 bnxt_rtnl_unlock_sp(bp);
6979}
6980
c0c050c5
MC		 6981static void bnxt_cfg_ntp_filters(struct bnxt *);
6982
6983static void bnxt_sp_task(struct work_struct *work)
6984{
6985 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
c0c050c5 6986
4cebdcec
MC		 6987 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6988 smp_mb__after_atomic();
6989 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6990 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 6991 return;
4cebdcec 6992 }
c0c050c5
MC		 6993
6994 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6995 bnxt_cfg_rx_mode(bp);
6996
6997 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6998 bnxt_cfg_ntp_filters(bp);
c0c050c5
MC		 6999 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7000 bnxt_hwrm_exec_fwd_req(bp);
7001 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7002 bnxt_hwrm_tunnel_dst_port_alloc(
7003 bp, bp->vxlan_port,
7004 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7005 }
7006 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7007 bnxt_hwrm_tunnel_dst_port_free(
7008 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7009 }
7cdd5fc3
AD		 7010 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7011 bnxt_hwrm_tunnel_dst_port_alloc(
7012 bp, bp->nge_port,
7013 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7014 }
7015 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7016 bnxt_hwrm_tunnel_dst_port_free(
7017 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7018 }
3bdf56c4
MC		 7019 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
7020 bnxt_hwrm_port_qstats(bp);
7021
a551ee94
MC		 7022 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
7023 * must be the last functions to be called before exiting.
7024 */
0eaa24b9
MC		 7025 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
7026 int rc = 0;
7027
7028 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7029 &bp->sp_event))
7030 bnxt_hwrm_phy_qcaps(bp);
7031
7032 bnxt_rtnl_lock_sp(bp);
7033 if (test_bit(BNXT_STATE_OPEN, &bp->state))
7034 rc = bnxt_update_link(bp, true);
7035 bnxt_rtnl_unlock_sp(bp);
7036 if (rc)
7037 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7038 rc);
7039 }
90c694bb
MC		 7040 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7041 bnxt_rtnl_lock_sp(bp);
7042 if (test_bit(BNXT_STATE_OPEN, &bp->state))
7043 bnxt_get_port_module_status(bp);
7044 bnxt_rtnl_unlock_sp(bp);
7045 }
6988bd92
MC		 7046 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7047 bnxt_reset(bp, false);
4cebdcec 7048
fc0f1929
MC		 7049 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7050 bnxt_reset(bp, true);
7051
4cebdcec
MC		 7052 smp_mb__before_atomic();
7053 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 7054}
7055
d1e7925e 7056/* Under rtnl_lock */
98fdbe73
MC		 7057int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7058 int tx_xdp)
d1e7925e
MC		 7059{
7060 int max_rx, max_tx, tx_sets = 1;
7061 int tx_rings_needed;
d1e7925e
MC		 7062 int rc;
7063
d1e7925e
MC		 7064 if (tcs)
7065 tx_sets = tcs;
7066
7067 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7068 if (rc)
7069 return rc;
7070
7071 if (max_rx < rx)
7072 return -ENOMEM;
7073
5f449249 7074 tx_rings_needed = tx * tx_sets + tx_xdp;
d1e7925e
MC		 7075 if (max_tx < tx_rings_needed)
7076 return -ENOMEM;
7077
98fdbe73 7078 return bnxt_hwrm_check_tx_rings(bp, tx_rings_needed);
d1e7925e
MC		 7079}
7080
17086399
SP		 7081static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7082{
7083 if (bp->bar2) {
7084 pci_iounmap(pdev, bp->bar2);
7085 bp->bar2 = NULL;
7086 }
7087
7088 if (bp->bar1) {
7089 pci_iounmap(pdev, bp->bar1);
7090 bp->bar1 = NULL;
7091 }
7092
7093 if (bp->bar0) {
7094 pci_iounmap(pdev, bp->bar0);
7095 bp->bar0 = NULL;
7096 }
7097}
7098
7099static void bnxt_cleanup_pci(struct bnxt *bp)
7100{
7101 bnxt_unmap_bars(bp, bp->pdev);
7102 pci_release_regions(bp->pdev);
7103 pci_disable_device(bp->pdev);
7104}
7105
c0c050c5
MC		 7106static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7107{
7108 int rc;
7109 struct bnxt *bp = netdev_priv(dev);
7110
7111 SET_NETDEV_DEV(dev, &pdev->dev);
7112
7113 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7114 rc = pci_enable_device(pdev);
7115 if (rc) {
7116 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7117 goto init_err;
7118 }
7119
7120 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7121 dev_err(&pdev->dev,
7122 "Cannot find PCI device base address, aborting\n");
7123 rc = -ENODEV;
7124 goto init_err_disable;
7125 }
7126
7127 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7128 if (rc) {
7129 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7130 goto init_err_disable;
7131 }
7132
7133 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
7134 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
7135 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7136 goto init_err_disable;
7137 }
7138
7139 pci_set_master(pdev);
7140
7141 bp->dev = dev;
7142 bp->pdev = pdev;
7143
7144 bp->bar0 = pci_ioremap_bar(pdev, 0);
7145 if (!bp->bar0) {
7146 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
7147 rc = -ENOMEM;
7148 goto init_err_release;
7149 }
7150
7151 bp->bar1 = pci_ioremap_bar(pdev, 2);
7152 if (!bp->bar1) {
7153 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
7154 rc = -ENOMEM;
7155 goto init_err_release;
7156 }
7157
7158 bp->bar2 = pci_ioremap_bar(pdev, 4);
7159 if (!bp->bar2) {
7160 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
7161 rc = -ENOMEM;
7162 goto init_err_release;
7163 }
7164
6316ea6d
SB		 7165 pci_enable_pcie_error_reporting(pdev);
7166
c0c050c5
MC		 7167 INIT_WORK(&bp->sp_task, bnxt_sp_task);
7168
7169 spin_lock_init(&bp->ntp_fltr_lock);
7170
7171 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
7172 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
7173
dfb5b894 7174 /* tick values in micro seconds */
dfc9c94a
MC		 7175 bp->rx_coal_ticks = 12;
7176 bp->rx_coal_bufs = 30;
dfb5b894
MC		 7177 bp->rx_coal_ticks_irq = 1;
7178 bp->rx_coal_bufs_irq = 2;
c0c050c5 7179
dfc9c94a
MC		 7180 bp->tx_coal_ticks = 25;
7181 bp->tx_coal_bufs = 30;
7182 bp->tx_coal_ticks_irq = 2;
7183 bp->tx_coal_bufs_irq = 2;
7184
51f30785
MC		 7185 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7186
c0c050c5
MC		 7187 init_timer(&bp->timer);
7188 bp->timer.data = (unsigned long)bp;
7189 bp->timer.function = bnxt_timer;
7190 bp->current_interval = BNXT_TIMER_INTERVAL;
7191
caefe526 7192 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 7193 return 0;
7194
7195init_err_release:
17086399 7196 bnxt_unmap_bars(bp, pdev);
c0c050c5
MC		 7197 pci_release_regions(pdev);
7198
7199init_err_disable:
7200 pci_disable_device(pdev);
7201
7202init_err:
7203 return rc;
7204}
7205
7206/* rtnl_lock held */
7207static int bnxt_change_mac_addr(struct net_device *dev, void *p)
7208{
7209 struct sockaddr *addr = p;
1fc2cfd0
JH		 7210 struct bnxt *bp = netdev_priv(dev);
7211 int rc = 0;
c0c050c5
MC		 7212
7213 if (!is_valid_ether_addr(addr->sa_data))
7214 return -EADDRNOTAVAIL;
7215
84c33dd3
MC		 7216 rc = bnxt_approve_mac(bp, addr->sa_data);
7217 if (rc)
7218 return rc;
bdd4347b 7219
1fc2cfd0
JH		 7220 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
7221 return 0;
7222
c0c050c5 7223 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 7224 if (netif_running(dev)) {
7225 bnxt_close_nic(bp, false, false);
7226 rc = bnxt_open_nic(bp, false, false);
7227 }
c0c050c5 7228
1fc2cfd0 7229 return rc;
c0c050c5
MC		 7230}
7231
7232/* rtnl_lock held */
7233static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
7234{
7235 struct bnxt *bp = netdev_priv(dev);
7236
c0c050c5
MC		 7237 if (netif_running(dev))
7238 bnxt_close_nic(bp, false, false);
7239
7240 dev->mtu = new_mtu;
7241 bnxt_set_ring_params(bp);
7242
7243 if (netif_running(dev))
7244 return bnxt_open_nic(bp, false, false);
7245
7246 return 0;
7247}
7248
c5e3deb8 7249int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
c0c050c5
MC		 7250{
7251 struct bnxt *bp = netdev_priv(dev);
3ffb6a39 7252 bool sh = false;
d1e7925e 7253 int rc;
16e5cc64 7254
c0c050c5 7255 if (tc > bp->max_tc) {
b451c8b6 7256 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
c0c050c5
MC		 7257 tc, bp->max_tc);
7258 return -EINVAL;
7259 }
7260
7261 if (netdev_get_num_tc(dev) == tc)
7262 return 0;
7263
3ffb6a39
MC		 7264 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7265 sh = true;
7266
98fdbe73
MC		 7267 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7268 sh, tc, bp->tx_nr_rings_xdp);
d1e7925e
MC		 7269 if (rc)
7270 return rc;
c0c050c5
MC		 7271
7272 /* Needs to close the device and do hw resource re-allocations */
7273 if (netif_running(bp->dev))
7274 bnxt_close_nic(bp, true, false);
7275
7276 if (tc) {
7277 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7278 netdev_set_num_tc(dev, tc);
7279 } else {
7280 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7281 netdev_reset_tc(dev);
7282 }
3ffb6a39
MC		 7283 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7284 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5
MC		 7285 bp->num_stat_ctxs = bp->cp_nr_rings;
7286
7287 if (netif_running(bp->dev))
7288 return bnxt_open_nic(bp, true, false);
7289
7290 return 0;
7291}
7292
2572ac53 7293static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 7294 void *type_data)
c5e3deb8 7295{
de4784ca
JP		 7296 struct tc_mqprio_qopt *mqprio = type_data;
7297
2572ac53 7298 if (type != TC_SETUP_MQPRIO)
38cf0426 7299 return -EOPNOTSUPP;
c5e3deb8 7300
de4784ca 7301 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
56f36acd 7302
de4784ca 7303 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
c5e3deb8
MC		 7304}
7305
c0c050c5
MC		 7306#ifdef CONFIG_RFS_ACCEL
7307static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7308 struct bnxt_ntuple_filter *f2)
7309{
7310 struct flow_keys *keys1 = &f1->fkeys;
7311 struct flow_keys *keys2 = &f2->fkeys;
7312
7313 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
7314 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
7315 keys1->ports.ports == keys2->ports.ports &&
7316 keys1->basic.ip_proto == keys2->basic.ip_proto &&
7317 keys1->basic.n_proto == keys2->basic.n_proto &&
61aad724 7318 keys1->control.flags == keys2->control.flags &&
a54c4d74
MC		 7319 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7320 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
c0c050c5
MC		 7321 return true;
7322
7323 return false;
7324}
7325
7326static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7327 u16 rxq_index, u32 flow_id)
7328{
7329 struct bnxt *bp = netdev_priv(dev);
7330 struct bnxt_ntuple_filter *fltr, *new_fltr;
7331 struct flow_keys *fkeys;
7332 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
a54c4d74 7333 int rc = 0, idx, bit_id, l2_idx = 0;
c0c050c5
MC		 7334 struct hlist_head *head;
7335
a54c4d74
MC		 7336 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
7337 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7338 int off = 0, j;
7339
7340 netif_addr_lock_bh(dev);
7341 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
7342 if (ether_addr_equal(eth->h_dest,
7343 vnic->uc_list + off)) {
7344 l2_idx = j + 1;
7345 break;
7346 }
7347 }
7348 netif_addr_unlock_bh(dev);
7349 if (!l2_idx)
7350 return -EINVAL;
7351 }
c0c050c5
MC		 7352 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
7353 if (!new_fltr)
7354 return -ENOMEM;
7355
7356 fkeys = &new_fltr->fkeys;
7357 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
7358 rc = -EPROTONOSUPPORT;
7359 goto err_free;
7360 }
7361
dda0e746
MC		 7362 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
7363 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
c0c050c5
MC		 7364 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
7365 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
7366 rc = -EPROTONOSUPPORT;
7367 goto err_free;
7368 }
dda0e746
MC		 7369 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
7370 bp->hwrm_spec_code < 0x10601) {
7371 rc = -EPROTONOSUPPORT;
7372 goto err_free;
7373 }
61aad724
MC		 7374 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
7375 bp->hwrm_spec_code < 0x10601) {
7376 rc = -EPROTONOSUPPORT;
7377 goto err_free;
7378 }
c0c050c5 7379
a54c4d74 7380 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
c0c050c5
MC		 7381 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
7382
7383 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
7384 head = &bp->ntp_fltr_hash_tbl[idx];
7385 rcu_read_lock();
7386 hlist_for_each_entry_rcu(fltr, head, hash) {
7387 if (bnxt_fltr_match(fltr, new_fltr)) {
7388 rcu_read_unlock();
7389 rc = 0;
7390 goto err_free;
7391 }
7392 }
7393 rcu_read_unlock();
7394
7395 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 7396 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
7397 BNXT_NTP_FLTR_MAX_FLTR, 0);
7398 if (bit_id < 0) {
c0c050c5
MC		 7399 spin_unlock_bh(&bp->ntp_fltr_lock);
7400 rc = -ENOMEM;
7401 goto err_free;
7402 }
7403
84e86b98 7404 new_fltr->sw_id = (u16)bit_id;
c0c050c5 7405 new_fltr->flow_id = flow_id;
a54c4d74 7406 new_fltr->l2_fltr_idx = l2_idx;
c0c050c5
MC		 7407 new_fltr->rxq = rxq_index;
7408 hlist_add_head_rcu(&new_fltr->hash, head);
7409 bp->ntp_fltr_count++;
7410 spin_unlock_bh(&bp->ntp_fltr_lock);
7411
7412 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
7413 schedule_work(&bp->sp_task);
7414
7415 return new_fltr->sw_id;
7416
7417err_free:
7418 kfree(new_fltr);
7419 return rc;
7420}
7421
7422static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7423{
7424 int i;
7425
7426 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7427 struct hlist_head *head;
7428 struct hlist_node *tmp;
7429 struct bnxt_ntuple_filter *fltr;
7430 int rc;
7431
7432 head = &bp->ntp_fltr_hash_tbl[i];
7433 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7434 bool del = false;
7435
7436 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7437 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7438 fltr->flow_id,
7439 fltr->sw_id)) {
7440 bnxt_hwrm_cfa_ntuple_filter_free(bp,
7441 fltr);
7442 del = true;
7443 }
7444 } else {
7445 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7446 fltr);
7447 if (rc)
7448 del = true;
7449 else
7450 set_bit(BNXT_FLTR_VALID, &fltr->state);
7451 }
7452
7453 if (del) {
7454 spin_lock_bh(&bp->ntp_fltr_lock);
7455 hlist_del_rcu(&fltr->hash);
7456 bp->ntp_fltr_count--;
7457 spin_unlock_bh(&bp->ntp_fltr_lock);
7458 synchronize_rcu();
7459 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7460 kfree(fltr);
7461 }
7462 }
7463 }
19241368
JH		 7464 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7465 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 7466}
7467
7468#else
7469
7470static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7471{
7472}
7473
7474#endif /* CONFIG_RFS_ACCEL */
7475
ad51b8e9
AD		 7476static void bnxt_udp_tunnel_add(struct net_device *dev,
7477 struct udp_tunnel_info *ti)
c0c050c5
MC		 7478{
7479 struct bnxt *bp = netdev_priv(dev);
7480
ad51b8e9 7481 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 7482 return;
7483
ad51b8e9 7484 if (!netif_running(dev))
c0c050c5
MC		 7485 return;
7486
ad51b8e9
AD		 7487 switch (ti->type) {
7488 case UDP_TUNNEL_TYPE_VXLAN:
7489 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7490 return;
c0c050c5 7491
ad51b8e9
AD		 7492 bp->vxlan_port_cnt++;
7493 if (bp->vxlan_port_cnt == 1) {
7494 bp->vxlan_port = ti->port;
7495 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
7496 schedule_work(&bp->sp_task);
7497 }
7498 break;
7cdd5fc3
AD		 7499 case UDP_TUNNEL_TYPE_GENEVE:
7500 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7501 return;
7502
7503 bp->nge_port_cnt++;
7504 if (bp->nge_port_cnt == 1) {
7505 bp->nge_port = ti->port;
7506 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7507 }
7508 break;
ad51b8e9
AD		 7509 default:
7510 return;
c0c050c5 7511 }
ad51b8e9
AD		 7512
7513 schedule_work(&bp->sp_task);
c0c050c5
MC		 7514}
7515
ad51b8e9
AD		 7516static void bnxt_udp_tunnel_del(struct net_device *dev,
7517 struct udp_tunnel_info *ti)
c0c050c5
MC		 7518{
7519 struct bnxt *bp = netdev_priv(dev);
7520
ad51b8e9 7521 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 7522 return;
7523
ad51b8e9 7524 if (!netif_running(dev))
c0c050c5
MC		 7525 return;
7526
ad51b8e9
AD		 7527 switch (ti->type) {
7528 case UDP_TUNNEL_TYPE_VXLAN:
7529 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7530 return;
c0c050c5
MC		 7531 bp->vxlan_port_cnt--;
7532
ad51b8e9
AD		 7533 if (bp->vxlan_port_cnt != 0)
7534 return;
7535
7536 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7537 break;
7cdd5fc3
AD		 7538 case UDP_TUNNEL_TYPE_GENEVE:
7539 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7540 return;
7541 bp->nge_port_cnt--;
7542
7543 if (bp->nge_port_cnt != 0)
7544 return;
7545
7546 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7547 break;
ad51b8e9
AD		 7548 default:
7549 return;
c0c050c5 7550 }
ad51b8e9
AD		 7551
7552 schedule_work(&bp->sp_task);
c0c050c5
MC		 7553}
7554
39d8ba2e
MC		 7555static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7556 struct net_device *dev, u32 filter_mask,
7557 int nlflags)
7558{
7559 struct bnxt *bp = netdev_priv(dev);
7560
7561 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
7562 nlflags, filter_mask, NULL);
7563}
7564
7565static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
7566 u16 flags)
7567{
7568 struct bnxt *bp = netdev_priv(dev);
7569 struct nlattr *attr, *br_spec;
7570 int rem, rc = 0;
7571
7572 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
7573 return -EOPNOTSUPP;
7574
7575 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7576 if (!br_spec)
7577 return -EINVAL;
7578
7579 nla_for_each_nested(attr, br_spec, rem) {
7580 u16 mode;
7581
7582 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7583 continue;
7584
7585 if (nla_len(attr) < sizeof(mode))
7586 return -EINVAL;
7587
7588 mode = nla_get_u16(attr);
7589 if (mode == bp->br_mode)
7590 break;
7591
7592 rc = bnxt_hwrm_set_br_mode(bp, mode);
7593 if (!rc)
7594 bp->br_mode = mode;
7595 break;
7596 }
7597 return rc;
7598}
7599
c124a62f
SP		 7600static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
7601 size_t len)
7602{
7603 struct bnxt *bp = netdev_priv(dev);
7604 int rc;
7605
7606 /* The PF and it's VF-reps only support the switchdev framework */
7607 if (!BNXT_PF(bp))
7608 return -EOPNOTSUPP;
7609
53f70b8b 7610 rc = snprintf(buf, len, "p%d", bp->pf.port_id);
c124a62f
SP		 7611
7612 if (rc >= len)
7613 return -EOPNOTSUPP;
7614 return 0;
7615}
7616
7617int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
7618{
7619 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
7620 return -EOPNOTSUPP;
7621
7622 /* The PF and it's VF-reps only support the switchdev framework */
7623 if (!BNXT_PF(bp))
7624 return -EOPNOTSUPP;
7625
7626 switch (attr->id) {
7627 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
7628 /* In SRIOV each PF-pool (PF + child VFs) serves as a
7629 * switching domain, the PF's perm mac-addr can be used
7630 * as the unique parent-id
7631 */
7632 attr->u.ppid.id_len = ETH_ALEN;
7633 ether_addr_copy(attr->u.ppid.id, bp->pf.mac_addr);
7634 break;
7635 default:
7636 return -EOPNOTSUPP;
7637 }
7638 return 0;
7639}
7640
7641static int bnxt_swdev_port_attr_get(struct net_device *dev,
7642 struct switchdev_attr *attr)
7643{
7644 return bnxt_port_attr_get(netdev_priv(dev), attr);
7645}
7646
7647static const struct switchdev_ops bnxt_switchdev_ops = {
7648 .switchdev_port_attr_get = bnxt_swdev_port_attr_get
7649};
7650
c0c050c5
MC		 7651static const struct net_device_ops bnxt_netdev_ops = {
7652 .ndo_open = bnxt_open,
7653 .ndo_start_xmit = bnxt_start_xmit,
7654 .ndo_stop = bnxt_close,
7655 .ndo_get_stats64 = bnxt_get_stats64,
7656 .ndo_set_rx_mode = bnxt_set_rx_mode,
7657 .ndo_do_ioctl = bnxt_ioctl,
7658 .ndo_validate_addr = eth_validate_addr,
7659 .ndo_set_mac_address = bnxt_change_mac_addr,
7660 .ndo_change_mtu = bnxt_change_mtu,
7661 .ndo_fix_features = bnxt_fix_features,
7662 .ndo_set_features = bnxt_set_features,
7663 .ndo_tx_timeout = bnxt_tx_timeout,
7664#ifdef CONFIG_BNXT_SRIOV
7665 .ndo_get_vf_config = bnxt_get_vf_config,
7666 .ndo_set_vf_mac = bnxt_set_vf_mac,
7667 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
7668 .ndo_set_vf_rate = bnxt_set_vf_bw,
7669 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
7670 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
7671#endif
7672#ifdef CONFIG_NET_POLL_CONTROLLER
7673 .ndo_poll_controller = bnxt_poll_controller,
7674#endif
7675 .ndo_setup_tc = bnxt_setup_tc,
7676#ifdef CONFIG_RFS_ACCEL
7677 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
7678#endif
ad51b8e9
AD		 7679 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
7680 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
c6d30e83 7681 .ndo_xdp = bnxt_xdp,
39d8ba2e
MC		 7682 .ndo_bridge_getlink = bnxt_bridge_getlink,
7683 .ndo_bridge_setlink = bnxt_bridge_setlink,
c124a62f 7684 .ndo_get_phys_port_name = bnxt_get_phys_port_name
c0c050c5
MC		 7685};
7686
7687static void bnxt_remove_one(struct pci_dev *pdev)
7688{
7689 struct net_device *dev = pci_get_drvdata(pdev);
7690 struct bnxt *bp = netdev_priv(dev);
7691
4ab0c6a8 7692 if (BNXT_PF(bp)) {
c0c050c5 7693 bnxt_sriov_disable(bp);
4ab0c6a8
SP		 7694 bnxt_dl_unregister(bp);
7695 }
c0c050c5 7696
6316ea6d 7697 pci_disable_pcie_error_reporting(pdev);
c0c050c5
MC		 7698 unregister_netdev(dev);
7699 cancel_work_sync(&bp->sp_task);
7700 bp->sp_event = 0;
7701
7809592d 7702 bnxt_clear_int_mode(bp);
be58a0da 7703 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5 7704 bnxt_free_hwrm_resources(bp);
e605db80 7705 bnxt_free_hwrm_short_cmd_req(bp);
eb513658 7706 bnxt_ethtool_free(bp);
7df4ae9f 7707 bnxt_dcb_free(bp);
a588e458
MC		 7708 kfree(bp->edev);
7709 bp->edev = NULL;
c6d30e83
MC		 7710 if (bp->xdp_prog)
7711 bpf_prog_put(bp->xdp_prog);
17086399 7712 bnxt_cleanup_pci(bp);
c0c050c5 7713 free_netdev(dev);
c0c050c5
MC		 7714}
7715
7716static int bnxt_probe_phy(struct bnxt *bp)
7717{
7718 int rc = 0;
7719 struct bnxt_link_info *link_info = &bp->link_info;
c0c050c5 7720
170ce013
MC		 7721 rc = bnxt_hwrm_phy_qcaps(bp);
7722 if (rc) {
7723 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7724 rc);
7725 return rc;
7726 }
7727
c0c050c5
MC		 7728 rc = bnxt_update_link(bp, false);
7729 if (rc) {
7730 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7731 rc);
7732 return rc;
7733 }
7734
93ed8117
MC		 7735 /* Older firmware does not have supported_auto_speeds, so assume
7736 * that all supported speeds can be autonegotiated.
7737 */
7738 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7739 link_info->support_auto_speeds = link_info->support_speeds;
7740
c0c050c5 7741 /*initialize the ethool setting copy with NVM settings */
0d8abf02 7742 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
c9ee9516
MC		 7743 link_info->autoneg = BNXT_AUTONEG_SPEED;
7744 if (bp->hwrm_spec_code >= 0x10201) {
7745 if (link_info->auto_pause_setting &
7746 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7747 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7748 } else {
7749 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7750 }
0d8abf02 7751 link_info->advertising = link_info->auto_link_speeds;
0d8abf02
MC		 7752 } else {
7753 link_info->req_link_speed = link_info->force_link_speed;
7754 link_info->req_duplex = link_info->duplex_setting;
c0c050c5 7755 }
c9ee9516
MC		 7756 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7757 link_info->req_flow_ctrl =
7758 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7759 else
7760 link_info->req_flow_ctrl = link_info->force_pause_setting;
c0c050c5
MC		 7761 return rc;
7762}
7763
7764static int bnxt_get_max_irq(struct pci_dev *pdev)
7765{
7766 u16 ctrl;
7767
7768 if (!pdev->msix_cap)
7769 return 1;
7770
7771 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7772 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7773}
7774
6e6c5a57
MC		 7775static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7776 int *max_cp)
c0c050c5 7777{
6e6c5a57 7778 int max_ring_grps = 0;
c0c050c5 7779
379a80a1 7780#ifdef CONFIG_BNXT_SRIOV
415b6f19 7781 if (!BNXT_PF(bp)) {
c0c050c5
MC		 7782 *max_tx = bp->vf.max_tx_rings;
7783 *max_rx = bp->vf.max_rx_rings;
6e6c5a57
MC		 7784 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7785 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
b72d4a68 7786 max_ring_grps = bp->vf.max_hw_ring_grps;
415b6f19 7787 } else
379a80a1 7788#endif
415b6f19
AB		 7789 {
7790 *max_tx = bp->pf.max_tx_rings;
7791 *max_rx = bp->pf.max_rx_rings;
7792 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7793 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7794 max_ring_grps = bp->pf.max_hw_ring_grps;
c0c050c5 7795 }
76595193
PS		 7796 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7797 *max_cp -= 1;
7798 *max_rx -= 2;
7799 }
c0c050c5
MC		 7800 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7801 *max_rx >>= 1;
b72d4a68 7802 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 7803}
7804
7805int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7806{
7807 int rx, tx, cp;
7808
7809 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7810 if (!rx || !tx || !cp)
7811 return -ENOMEM;
7812
7813 *max_rx = rx;
7814 *max_tx = tx;
7815 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7816}
7817
e4060d30
MC		 7818static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7819 bool shared)
7820{
7821 int rc;
7822
7823 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
bdbd1eb5
MC		 7824 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7825 /* Not enough rings, try disabling agg rings. */
7826 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7827 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7828 if (rc)
7829 return rc;
7830 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7831 bp->dev->hw_features &= ~NETIF_F_LRO;
7832 bp->dev->features &= ~NETIF_F_LRO;
7833 bnxt_set_ring_params(bp);
7834 }
e4060d30
MC		 7835
7836 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7837 int max_cp, max_stat, max_irq;
7838
7839 /* Reserve minimum resources for RoCE */
7840 max_cp = bnxt_get_max_func_cp_rings(bp);
7841 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7842 max_irq = bnxt_get_max_func_irqs(bp);
7843 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7844 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7845 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7846 return 0;
7847
7848 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7849 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7850 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7851 max_cp = min_t(int, max_cp, max_irq);
7852 max_cp = min_t(int, max_cp, max_stat);
7853 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7854 if (rc)
7855 rc = 0;
7856 }
7857 return rc;
7858}
7859
702c221c 7860static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
6e6c5a57
MC		 7861{
7862 int dflt_rings, max_rx_rings, max_tx_rings, rc;
6e6c5a57
MC		 7863
7864 if (sh)
7865 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7866 dflt_rings = netif_get_num_default_rss_queues();
e4060d30 7867 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57
MC		 7868 if (rc)
7869 return rc;
7870 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7871 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
391be5c2
MC		 7872
7873 rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
7874 if (rc)
7875 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
7876
6e6c5a57
MC		 7877 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7878 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7879 bp->tx_nr_rings + bp->rx_nr_rings;
7880 bp->num_stat_ctxs = bp->cp_nr_rings;
76595193
PS		 7881 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7882 bp->rx_nr_rings++;
7883 bp->cp_nr_rings++;
7884 }
6e6c5a57 7885 return rc;
c0c050c5
MC		 7886}
7887
7b08f661
MC		 7888void bnxt_restore_pf_fw_resources(struct bnxt *bp)
7889{
7890 ASSERT_RTNL();
7891 bnxt_hwrm_func_qcaps(bp);
a588e458 7892 bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
7b08f661
MC		 7893}
7894
90c4f788
AK		 7895static void bnxt_parse_log_pcie_link(struct bnxt *bp)
7896{
7897 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
7898 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
7899
7900 if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
7901 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
7902 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
7903 else
7904 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
7905 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
7906 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
7907 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
7908 "Unknown", width);
7909}
7910
c0c050c5
MC		 7911static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7912{
7913 static int version_printed;
7914 struct net_device *dev;
7915 struct bnxt *bp;
6e6c5a57 7916 int rc, max_irqs;
c0c050c5 7917
4e00338a 7918 if (pci_is_bridge(pdev))
fa853dda
PS		 7919 return -ENODEV;
7920
c0c050c5
MC		 7921 if (version_printed++ == 0)
7922 pr_info("%s", version);
7923
7924 max_irqs = bnxt_get_max_irq(pdev);
7925 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
7926 if (!dev)
7927 return -ENOMEM;
7928
7929 bp = netdev_priv(dev);
7930
7931 if (bnxt_vf_pciid(ent->driver_data))
7932 bp->flags |= BNXT_FLAG_VF;
7933
2bcfa6f6 7934 if (pdev->msix_cap)
c0c050c5 7935 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 7936
7937 rc = bnxt_init_board(pdev, dev);
7938 if (rc < 0)
7939 goto init_err_free;
7940
7941 dev->netdev_ops = &bnxt_netdev_ops;
7942 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
7943 dev->ethtool_ops = &bnxt_ethtool_ops;
bc88055a 7944 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
c0c050c5
MC		 7945 pci_set_drvdata(pdev, dev);
7946
3e8060fa
PS		 7947 rc = bnxt_alloc_hwrm_resources(bp);
7948 if (rc)
17086399 7949 goto init_err_pci_clean;
3e8060fa
PS		 7950
7951 mutex_init(&bp->hwrm_cmd_lock);
7952 rc = bnxt_hwrm_ver_get(bp);
7953 if (rc)
17086399 7954 goto init_err_pci_clean;
3e8060fa 7955
e605db80
DK		 7956 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
7957 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
7958 if (rc)
7959 goto init_err_pci_clean;
7960 }
7961
3c2217a6
MC		 7962 rc = bnxt_hwrm_func_reset(bp);
7963 if (rc)
7964 goto init_err_pci_clean;
7965
5ac67d8b
RS		 7966 bnxt_hwrm_fw_set_time(bp);
7967
c0c050c5
MC		 7968 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7969 NETIF_F_TSO | NETIF_F_TSO6 |
7970 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7e13318d 7971 NETIF_F_GSO_IPXIP4 |
152971ee
AD		 7972 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7973 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
3e8060fa
PS		 7974 NETIF_F_RXCSUM | NETIF_F_GRO;
7975
7976 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
7977 dev->hw_features |= NETIF_F_LRO;
c0c050c5 7978
c0c050c5
MC		 7979 dev->hw_enc_features =
7980 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7981 NETIF_F_TSO | NETIF_F_TSO6 |
7982 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
152971ee 7983 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7e13318d 7984 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
152971ee
AD		 7985 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
7986 NETIF_F_GSO_GRE_CSUM;
c0c050c5
MC		 7987 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
7988 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7989 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
7990 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
7991 dev->priv_flags |= IFF_UNICAST_FLT;
7992
e1c6dcca
JW		 7993 /* MTU range: 60 - 9500 */
7994 dev->min_mtu = ETH_ZLEN;
c61fb99c 7995 dev->max_mtu = BNXT_MAX_MTU;
e1c6dcca 7996
c0c050c5
MC		 7997#ifdef CONFIG_BNXT_SRIOV
7998 init_waitqueue_head(&bp->sriov_cfg_wait);
4ab0c6a8 7999 mutex_init(&bp->sriov_lock);
c0c050c5 8000#endif
309369c9 8001 bp->gro_func = bnxt_gro_func_5730x;
3284f9e1 8002 if (BNXT_CHIP_P4_PLUS(bp))
94758f8d 8003 bp->gro_func = bnxt_gro_func_5731x;
434c975a
MC		 8004 else
8005 bp->flags |= BNXT_FLAG_DOUBLE_DB;
309369c9 8006
c0c050c5
MC		 8007 rc = bnxt_hwrm_func_drv_rgtr(bp);
8008 if (rc)
17086399 8009 goto init_err_pci_clean;
c0c050c5 8010
a1653b13
MC		 8011 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
8012 if (rc)
17086399 8013 goto init_err_pci_clean;
a1653b13 8014
a588e458
MC		 8015 bp->ulp_probe = bnxt_ulp_probe;
8016
c0c050c5
MC		 8017 /* Get the MAX capabilities for this function */
8018 rc = bnxt_hwrm_func_qcaps(bp);
8019 if (rc) {
8020 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
8021 rc);
8022 rc = -1;
17086399 8023 goto init_err_pci_clean;
c0c050c5
MC		 8024 }
8025
8026 rc = bnxt_hwrm_queue_qportcfg(bp);
8027 if (rc) {
8028 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
8029 rc);
8030 rc = -1;
17086399 8031 goto init_err_pci_clean;
c0c050c5
MC		 8032 }
8033
567b2abe 8034 bnxt_hwrm_func_qcfg(bp);
5ad2cbee 8035 bnxt_hwrm_port_led_qcaps(bp);
eb513658 8036 bnxt_ethtool_init(bp);
87fe6032 8037 bnxt_dcb_init(bp);
567b2abe 8038
c61fb99c 8039 bnxt_set_rx_skb_mode(bp, false);
c0c050c5
MC		 8040 bnxt_set_tpa_flags(bp);
8041 bnxt_set_ring_params(bp);
33c2657e 8042 bnxt_set_max_func_irqs(bp, max_irqs);
702c221c 8043 rc = bnxt_set_dflt_rings(bp, true);
bdbd1eb5
MC		 8044 if (rc) {
8045 netdev_err(bp->dev, "Not enough rings available.\n");
8046 rc = -ENOMEM;
17086399 8047 goto init_err_pci_clean;
bdbd1eb5 8048 }
c0c050c5 8049
87da7f79
MC		 8050 /* Default RSS hash cfg. */
8051 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
8052 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
8053 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
8054 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
3284f9e1 8055 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
87da7f79
MC		 8056 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
8057 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
8058 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
8059 }
8060
8fdefd63 8061 bnxt_hwrm_vnic_qcaps(bp);
8079e8f1 8062 if (bnxt_rfs_supported(bp)) {
2bcfa6f6
MC		 8063 dev->hw_features |= NETIF_F_NTUPLE;
8064 if (bnxt_rfs_capable(bp)) {
8065 bp->flags |= BNXT_FLAG_RFS;
8066 dev->features |= NETIF_F_NTUPLE;
8067 }
8068 }
8069
c0c050c5
MC		 8070 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
8071 bp->flags |= BNXT_FLAG_STRIP_VLAN;
8072
8073 rc = bnxt_probe_phy(bp);
8074 if (rc)
17086399 8075 goto init_err_pci_clean;
c0c050c5 8076
7809592d 8077 rc = bnxt_init_int_mode(bp);
c0c050c5 8078 if (rc)
17086399 8079 goto init_err_pci_clean;
c0c050c5 8080
c1ef146a 8081 bnxt_get_wol_settings(bp);
d196ece7
MC		 8082 if (bp->flags & BNXT_FLAG_WOL_CAP)
8083 device_set_wakeup_enable(&pdev->dev, bp->wol);
8084 else
8085 device_set_wakeup_capable(&pdev->dev, false);
c1ef146a 8086
7809592d
MC		 8087 rc = register_netdev(dev);
8088 if (rc)
8089 goto init_err_clr_int;
8090
4ab0c6a8
SP		 8091 if (BNXT_PF(bp))
8092 bnxt_dl_register(bp);
8093
c0c050c5
MC		 8094 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
8095 board_info[ent->driver_data].name,
8096 (long)pci_resource_start(pdev, 0), dev->dev_addr);
8097
90c4f788
AK		 8098 bnxt_parse_log_pcie_link(bp);
8099
c0c050c5
MC		 8100 return 0;
8101
7809592d
MC		 8102init_err_clr_int:
8103 bnxt_clear_int_mode(bp);
8104
17086399
SP		 8105init_err_pci_clean:
8106 bnxt_cleanup_pci(bp);
c0c050c5
MC		 8107
8108init_err_free:
8109 free_netdev(dev);
8110 return rc;
8111}
8112
d196ece7
MC		 8113static void bnxt_shutdown(struct pci_dev *pdev)
8114{
8115 struct net_device *dev = pci_get_drvdata(pdev);
8116 struct bnxt *bp;
8117
8118 if (!dev)
8119 return;
8120
8121 rtnl_lock();
8122 bp = netdev_priv(dev);
8123 if (!bp)
8124 goto shutdown_exit;
8125
8126 if (netif_running(dev))
8127 dev_close(dev);
8128
8129 if (system_state == SYSTEM_POWER_OFF) {
0efd2fc6 8130 bnxt_ulp_shutdown(bp);
d196ece7
MC		 8131 bnxt_clear_int_mode(bp);
8132 pci_wake_from_d3(pdev, bp->wol);
8133 pci_set_power_state(pdev, PCI_D3hot);
8134 }
8135
8136shutdown_exit:
8137 rtnl_unlock();
8138}
8139
f65a2044
MC		 8140#ifdef CONFIG_PM_SLEEP
8141static int bnxt_suspend(struct device *device)
8142{
8143 struct pci_dev *pdev = to_pci_dev(device);
8144 struct net_device *dev = pci_get_drvdata(pdev);
8145 struct bnxt *bp = netdev_priv(dev);
8146 int rc = 0;
8147
8148 rtnl_lock();
8149 if (netif_running(dev)) {
8150 netif_device_detach(dev);
8151 rc = bnxt_close(dev);
8152 }
8153 bnxt_hwrm_func_drv_unrgtr(bp);
8154 rtnl_unlock();
8155 return rc;
8156}
8157
8158static int bnxt_resume(struct device *device)
8159{
8160 struct pci_dev *pdev = to_pci_dev(device);
8161 struct net_device *dev = pci_get_drvdata(pdev);
8162 struct bnxt *bp = netdev_priv(dev);
8163 int rc = 0;
8164
8165 rtnl_lock();
8166 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
8167 rc = -ENODEV;
8168 goto resume_exit;
8169 }
8170 rc = bnxt_hwrm_func_reset(bp);
8171 if (rc) {
8172 rc = -EBUSY;
8173 goto resume_exit;
8174 }
8175 bnxt_get_wol_settings(bp);
8176 if (netif_running(dev)) {
8177 rc = bnxt_open(dev);
8178 if (!rc)
8179 netif_device_attach(dev);
8180 }
8181
8182resume_exit:
8183 rtnl_unlock();
8184 return rc;
8185}
8186
8187static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
8188#define BNXT_PM_OPS (&bnxt_pm_ops)
8189
8190#else
8191
8192#define BNXT_PM_OPS NULL
8193
8194#endif /* CONFIG_PM_SLEEP */
8195
6316ea6d
SB		 8196/**
8197 * bnxt_io_error_detected - called when PCI error is detected
8198 * @pdev: Pointer to PCI device
8199 * @state: The current pci connection state
8200 *
8201 * This function is called after a PCI bus error affecting
8202 * this device has been detected.
8203 */
8204static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
8205 pci_channel_state_t state)
8206{
8207 struct net_device *netdev = pci_get_drvdata(pdev);
a588e458 8208 struct bnxt *bp = netdev_priv(netdev);
6316ea6d
SB		 8209
8210 netdev_info(netdev, "PCI I/O error detected\n");
8211
8212 rtnl_lock();
8213 netif_device_detach(netdev);
8214
a588e458
MC		 8215 bnxt_ulp_stop(bp);
8216
6316ea6d
SB		 8217 if (state == pci_channel_io_perm_failure) {
8218 rtnl_unlock();
8219 return PCI_ERS_RESULT_DISCONNECT;
8220 }
8221
8222 if (netif_running(netdev))
8223 bnxt_close(netdev);
8224
8225 pci_disable_device(pdev);
8226 rtnl_unlock();
8227
8228 /* Request a slot slot reset. */
8229 return PCI_ERS_RESULT_NEED_RESET;
8230}
8231
8232/**
8233 * bnxt_io_slot_reset - called after the pci bus has been reset.
8234 * @pdev: Pointer to PCI device
8235 *
8236 * Restart the card from scratch, as if from a cold-boot.
8237 * At this point, the card has exprienced a hard reset,
8238 * followed by fixups by BIOS, and has its config space
8239 * set up identically to what it was at cold boot.
8240 */
8241static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
8242{
8243 struct net_device *netdev = pci_get_drvdata(pdev);
8244 struct bnxt *bp = netdev_priv(netdev);
8245 int err = 0;
8246 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8247
8248 netdev_info(bp->dev, "PCI Slot Reset\n");
8249
8250 rtnl_lock();
8251
8252 if (pci_enable_device(pdev)) {
8253 dev_err(&pdev->dev,
8254 "Cannot re-enable PCI device after reset.\n");
8255 } else {
8256 pci_set_master(pdev);
8257
aa8ed021
MC		 8258 err = bnxt_hwrm_func_reset(bp);
8259 if (!err && netif_running(netdev))
6316ea6d
SB		 8260 err = bnxt_open(netdev);
8261
a588e458 8262 if (!err) {
6316ea6d 8263 result = PCI_ERS_RESULT_RECOVERED;
a588e458
MC		 8264 bnxt_ulp_start(bp);
8265 }
6316ea6d
SB		 8266 }
8267
8268 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
8269 dev_close(netdev);
8270
8271 rtnl_unlock();
8272
8273 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8274 if (err) {
8275 dev_err(&pdev->dev,
8276 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8277 err); /* non-fatal, continue */
8278 }
8279
8280 return PCI_ERS_RESULT_RECOVERED;
8281}
8282
8283/**
8284 * bnxt_io_resume - called when traffic can start flowing again.
8285 * @pdev: Pointer to PCI device
8286 *
8287 * This callback is called when the error recovery driver tells
8288 * us that its OK to resume normal operation.
8289 */
8290static void bnxt_io_resume(struct pci_dev *pdev)
8291{
8292 struct net_device *netdev = pci_get_drvdata(pdev);
8293
8294 rtnl_lock();
8295
8296 netif_device_attach(netdev);
8297
8298 rtnl_unlock();
8299}
8300
8301static const struct pci_error_handlers bnxt_err_handler = {
8302 .error_detected = bnxt_io_error_detected,
8303 .slot_reset = bnxt_io_slot_reset,
8304 .resume = bnxt_io_resume
8305};
8306
c0c050c5
MC		 8307static struct pci_driver bnxt_pci_driver = {
8308 .name = DRV_MODULE_NAME,
8309 .id_table = bnxt_pci_tbl,
8310 .probe = bnxt_init_one,
8311 .remove = bnxt_remove_one,
d196ece7 8312 .shutdown = bnxt_shutdown,
f65a2044 8313 .driver.pm = BNXT_PM_OPS,
6316ea6d 8314 .err_handler = &bnxt_err_handler,
c0c050c5
MC		 8315#if defined(CONFIG_BNXT_SRIOV)
8316 .sriov_configure = bnxt_sriov_configure,
8317#endif
8318};
8319
8320module_pci_driver(bnxt_pci_driver);
Ubuntu Jammy Linux kernel mirror