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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
11f15ed3 3 * Copyright (c) 2014-2016 Broadcom Corporation
bac9a7e0 4 * Copyright (c) 2016-2017 Broadcom Limited
c0c050c5
MC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12
13#include <linux/stringify.h>
14#include <linux/kernel.h>
15#include <linux/timer.h>
16#include <linux/errno.h>
17#include <linux/ioport.h>
18#include <linux/slab.h>
19#include <linux/vmalloc.h>
20#include <linux/interrupt.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/dma-mapping.h>
26#include <linux/bitops.h>
27#include <linux/io.h>
28#include <linux/irq.h>
29#include <linux/delay.h>
30#include <asm/byteorder.h>
31#include <asm/page.h>
32#include <linux/time.h>
33#include <linux/mii.h>
34#include <linux/if.h>
35#include <linux/if_vlan.h>
32e8239c 36#include <linux/if_bridge.h>
5ac67d8b 37#include <linux/rtc.h>
c6d30e83 38#include <linux/bpf.h>
c0c050c5
MC		 39#include <net/ip.h>
40#include <net/tcp.h>
41#include <net/udp.h>
42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
ad51b8e9 44#include <net/udp_tunnel.h>
c0c050c5
MC		 45#include <linux/workqueue.h>
46#include <linux/prefetch.h>
47#include <linux/cache.h>
48#include <linux/log2.h>
49#include <linux/aer.h>
50#include <linux/bitmap.h>
51#include <linux/cpu_rmap.h>
56f0fd80 52#include <linux/cpumask.h>
2ae7408f 53#include <net/pkt_cls.h>
c0c050c5
MC		 54
55#include "bnxt_hsi.h"
56#include "bnxt.h"
a588e458 57#include "bnxt_ulp.h"
c0c050c5
MC		 58#include "bnxt_sriov.h"
59#include "bnxt_ethtool.h"
7df4ae9f 60#include "bnxt_dcb.h"
c6d30e83 61#include "bnxt_xdp.h"
4ab0c6a8 62#include "bnxt_vfr.h"
2ae7408f 63#include "bnxt_tc.h"
3c467bf3 64#include "bnxt_devlink.h"
c0c050c5
MC		 65
66#define BNXT_TX_TIMEOUT (5 * HZ)
67
68static const char version[] =
69 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
70
71MODULE_LICENSE("GPL");
72MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
73MODULE_VERSION(DRV_MODULE_VERSION);
74
75#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
76#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
77#define BNXT_RX_COPY_THRESH 256
78
4419dbe6 79#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 80
81enum board_idx {
fbc9a523 82 BCM57301,
c0c050c5
MC		 83 BCM57302,
84 BCM57304,
1f681688 85 BCM57417_NPAR,
fa853dda 86 BCM58700,
b24eb6ae
MC		 87 BCM57311,
88 BCM57312,
fbc9a523 89 BCM57402,
c0c050c5
MC		 90 BCM57404,
91 BCM57406,
1f681688
MC		 92 BCM57402_NPAR,
93 BCM57407,
b24eb6ae
MC		 94 BCM57412,
95 BCM57414,
96 BCM57416,
97 BCM57417,
1f681688 98 BCM57412_NPAR,
5049e33b 99 BCM57314,
1f681688
MC		 100 BCM57417_SFP,
101 BCM57416_SFP,
102 BCM57404_NPAR,
103 BCM57406_NPAR,
104 BCM57407_SFP,
adbc8305 105 BCM57407_NPAR,
1f681688
MC		 106 BCM57414_NPAR,
107 BCM57416_NPAR,
32b40798
DK		 108 BCM57452,
109 BCM57454,
4a58139b 110 BCM58802,
8ed693b7 111 BCM58804,
4a58139b 112 BCM58808,
adbc8305
MC		 113 NETXTREME_E_VF,
114 NETXTREME_C_VF,
618784e3 115 NETXTREME_S_VF,
c0c050c5
MC		 116};
117
118/* indexed by enum above */
119static const struct {
120 char *name;
121} board_info[] = {
27573a7d
SB		 122 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
123 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
124 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
125 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
126 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
127 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
128 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
129 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
130 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
131 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
132 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
133 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
134 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
135 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
136 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
137 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
138 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
139 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
140 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
141 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
142 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
143 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
144 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
145 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
146 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
147 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
148 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
149 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
150 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
8ed693b7 151 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
27573a7d
SB		 152 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
153 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
154 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
618784e3 155 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
c0c050c5
MC		 156};
157
158static const struct pci_device_id bnxt_pci_tbl[] = {
4a58139b 159 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
adbc8305 160 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
fbc9a523 161 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 162 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
163 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
1f681688 164 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
fa853dda 165 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
b24eb6ae
MC		 166 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
167 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
fbc9a523 168 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 169 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
170 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
1f681688
MC		 171 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
172 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
b24eb6ae
MC		 173 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
174 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
175 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
176 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
1f681688 177 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
5049e33b 178 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
1f681688
MC		 179 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
180 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
181 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
182 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
183 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
adbc8305
MC		 184 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
185 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
1f681688 186 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
adbc8305 187 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
1f681688 188 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
adbc8305 189 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
4a58139b 190 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
32b40798 191 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
4a58139b 192 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
8ed693b7 193 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
c0c050c5 194#ifdef CONFIG_BNXT_SRIOV
c7ef35eb
DK		 195 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
196 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
adbc8305
MC		 197 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
198 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
199 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
200 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
201 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
202 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
618784e3 203 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
c0c050c5
MC		 204#endif
205 { 0 }
206};
207
208MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
209
210static const u16 bnxt_vf_req_snif[] = {
211 HWRM_FUNC_CFG,
212 HWRM_PORT_PHY_QCFG,
213 HWRM_CFA_L2_FILTER_ALLOC,
214};
215
25be8623 216static const u16 bnxt_async_events_arr[] = {
87c374de
MC		 217 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
218 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
219 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
220 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
221 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
25be8623
MC		 222};
223
c213eae8
MC		 224static struct workqueue_struct *bnxt_pf_wq;
225
c0c050c5
MC		 226static bool bnxt_vf_pciid(enum board_idx idx)
227{
618784e3
RM		 228 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
229 idx == NETXTREME_S_VF);
c0c050c5
MC		 230}
231
232#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
233#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
234#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
235
236#define BNXT_CP_DB_REARM(db, raw_cons) \
237 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
238
239#define BNXT_CP_DB(db, raw_cons) \
240 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
241
242#define BNXT_CP_DB_IRQ_DIS(db) \
243 writel(DB_CP_IRQ_DIS_FLAGS, db)
244
38413406 245const u16 bnxt_lhint_arr[] = {
c0c050c5
MC		 246 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
247 TX_BD_FLAGS_LHINT_512_TO_1023,
248 TX_BD_FLAGS_LHINT_1024_TO_2047,
249 TX_BD_FLAGS_LHINT_1024_TO_2047,
250 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
251 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
252 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
253 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
254 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
255 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
256 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
257 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
258 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
259 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
260 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
261 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
262 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
263 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
264 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
265};
266
ee5c7fb3
SP		 267static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
268{
269 struct metadata_dst *md_dst = skb_metadata_dst(skb);
270
271 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
272 return 0;
273
274 return md_dst->u.port_info.port_id;
275}
276
c0c050c5
MC		 277static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
278{
279 struct bnxt *bp = netdev_priv(dev);
280 struct tx_bd *txbd;
281 struct tx_bd_ext *txbd1;
282 struct netdev_queue *txq;
283 int i;
284 dma_addr_t mapping;
285 unsigned int length, pad = 0;
286 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
287 u16 prod, last_frag;
288 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 289 struct bnxt_tx_ring_info *txr;
290 struct bnxt_sw_tx_bd *tx_buf;
291
292 i = skb_get_queue_mapping(skb);
293 if (unlikely(i >= bp->tx_nr_rings)) {
294 dev_kfree_skb_any(skb);
295 return NETDEV_TX_OK;
296 }
297
c0c050c5 298 txq = netdev_get_tx_queue(dev, i);
a960dec9 299 txr = &bp->tx_ring[bp->tx_ring_map[i]];
c0c050c5
MC		 300 prod = txr->tx_prod;
301
302 free_size = bnxt_tx_avail(bp, txr);
303 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
304 netif_tx_stop_queue(txq);
305 return NETDEV_TX_BUSY;
306 }
307
308 length = skb->len;
309 len = skb_headlen(skb);
310 last_frag = skb_shinfo(skb)->nr_frags;
311
312 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
313
314 txbd->tx_bd_opaque = prod;
315
316 tx_buf = &txr->tx_buf_ring[prod];
317 tx_buf->skb = skb;
318 tx_buf->nr_frags = last_frag;
319
320 vlan_tag_flags = 0;
ee5c7fb3 321 cfa_action = bnxt_xmit_get_cfa_action(skb);
c0c050c5
MC		 322 if (skb_vlan_tag_present(skb)) {
323 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
324 skb_vlan_tag_get(skb);
325 /* Currently supports 8021Q, 8021AD vlan offloads
326 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
327 */
328 if (skb->vlan_proto == htons(ETH_P_8021Q))
329 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
330 }
331
332 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 333 struct tx_push_buffer *tx_push_buf = txr->tx_push;
334 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
335 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
336 void *pdata = tx_push_buf->data;
337 u64 *end;
338 int j, push_len;
c0c050c5
MC		 339
340 /* Set COAL_NOW to be ready quickly for the next push */
341 tx_push->tx_bd_len_flags_type =
342 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
343 TX_BD_TYPE_LONG_TX_BD |
344 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
345 TX_BD_FLAGS_COAL_NOW |
346 TX_BD_FLAGS_PACKET_END |
347 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
348
349 if (skb->ip_summed == CHECKSUM_PARTIAL)
350 tx_push1->tx_bd_hsize_lflags =
351 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
352 else
353 tx_push1->tx_bd_hsize_lflags = 0;
354
355 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
ee5c7fb3
SP		 356 tx_push1->tx_bd_cfa_action =
357 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
c0c050c5 358
fbb0fa8b
MC		 359 end = pdata + length;
360 end = PTR_ALIGN(end, 8) - 1;
4419dbe6
MC		 361 *end = 0;
362
c0c050c5
MC		 363 skb_copy_from_linear_data(skb, pdata, len);
364 pdata += len;
365 for (j = 0; j < last_frag; j++) {
366 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
367 void *fptr;
368
369 fptr = skb_frag_address_safe(frag);
370 if (!fptr)
371 goto normal_tx;
372
373 memcpy(pdata, fptr, skb_frag_size(frag));
374 pdata += skb_frag_size(frag);
375 }
376
4419dbe6
MC		 377 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
378 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 379 prod = NEXT_TX(prod);
380 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
381 memcpy(txbd, tx_push1, sizeof(*txbd));
382 prod = NEXT_TX(prod);
4419dbe6 383 tx_push->doorbell =
c0c050c5
MC		 384 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
385 txr->tx_prod = prod;
386
b9a8460a 387 tx_buf->is_push = 1;
c0c050c5 388 netdev_tx_sent_queue(txq, skb->len);
b9a8460a 389 wmb(); /* Sync is_push and byte queue before pushing data */
c0c050c5 390
4419dbe6
MC		 391 push_len = (length + sizeof(*tx_push) + 7) / 8;
392 if (push_len > 16) {
393 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
9d13744b
MC		 394 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
395 (push_len - 16) << 1);
4419dbe6
MC		 396 } else {
397 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
398 push_len);
399 }
c0c050c5 400
c0c050c5
MC		 401 goto tx_done;
402 }
403
404normal_tx:
405 if (length < BNXT_MIN_PKT_SIZE) {
406 pad = BNXT_MIN_PKT_SIZE - length;
407 if (skb_pad(skb, pad)) {
408 /* SKB already freed. */
409 tx_buf->skb = NULL;
410 return NETDEV_TX_OK;
411 }
412 length = BNXT_MIN_PKT_SIZE;
413 }
414
415 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
416
417 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
418 dev_kfree_skb_any(skb);
419 tx_buf->skb = NULL;
420 return NETDEV_TX_OK;
421 }
422
423 dma_unmap_addr_set(tx_buf, mapping, mapping);
424 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
425 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
426
427 txbd->tx_bd_haddr = cpu_to_le64(mapping);
428
429 prod = NEXT_TX(prod);
430 txbd1 = (struct tx_bd_ext *)
431 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
432
433 txbd1->tx_bd_hsize_lflags = 0;
434 if (skb_is_gso(skb)) {
435 u32 hdr_len;
436
437 if (skb->encapsulation)
438 hdr_len = skb_inner_network_offset(skb) +
439 skb_inner_network_header_len(skb) +
440 inner_tcp_hdrlen(skb);
441 else
442 hdr_len = skb_transport_offset(skb) +
443 tcp_hdrlen(skb);
444
445 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
446 TX_BD_FLAGS_T_IPID |
447 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
448 length = skb_shinfo(skb)->gso_size;
449 txbd1->tx_bd_mss = cpu_to_le32(length);
450 length += hdr_len;
451 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
452 txbd1->tx_bd_hsize_lflags =
453 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
454 txbd1->tx_bd_mss = 0;
455 }
456
457 length >>= 9;
458 flags |= bnxt_lhint_arr[length];
459 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
460
461 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
ee5c7fb3
SP		 462 txbd1->tx_bd_cfa_action =
463 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
c0c050c5
MC		 464 for (i = 0; i < last_frag; i++) {
465 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
466
467 prod = NEXT_TX(prod);
468 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
469
470 len = skb_frag_size(frag);
471 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
472 DMA_TO_DEVICE);
473
474 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
475 goto tx_dma_error;
476
477 tx_buf = &txr->tx_buf_ring[prod];
478 dma_unmap_addr_set(tx_buf, mapping, mapping);
479
480 txbd->tx_bd_haddr = cpu_to_le64(mapping);
481
482 flags = len << TX_BD_LEN_SHIFT;
483 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
484 }
485
486 flags &= ~TX_BD_LEN;
487 txbd->tx_bd_len_flags_type =
488 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
489 TX_BD_FLAGS_PACKET_END);
490
491 netdev_tx_sent_queue(txq, skb->len);
492
493 /* Sync BD data before updating doorbell */
494 wmb();
495
496 prod = NEXT_TX(prod);
497 txr->tx_prod = prod;
498
ffe40645 499 if (!skb->xmit_more || netif_xmit_stopped(txq))
4d172f21 500 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
c0c050c5
MC		 501
502tx_done:
503
504 mmiowb();
505
506 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
4d172f21
MC		 507 if (skb->xmit_more && !tx_buf->is_push)
508 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
509
c0c050c5
MC		 510 netif_tx_stop_queue(txq);
511
512 /* netif_tx_stop_queue() must be done before checking
513 * tx index in bnxt_tx_avail() below, because in
514 * bnxt_tx_int(), we update tx index before checking for
515 * netif_tx_queue_stopped().
516 */
517 smp_mb();
518 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
519 netif_tx_wake_queue(txq);
520 }
521 return NETDEV_TX_OK;
522
523tx_dma_error:
524 last_frag = i;
525
526 /* start back at beginning and unmap skb */
527 prod = txr->tx_prod;
528 tx_buf = &txr->tx_buf_ring[prod];
529 tx_buf->skb = NULL;
530 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
531 skb_headlen(skb), PCI_DMA_TODEVICE);
532 prod = NEXT_TX(prod);
533
534 /* unmap remaining mapped pages */
535 for (i = 0; i < last_frag; i++) {
536 prod = NEXT_TX(prod);
537 tx_buf = &txr->tx_buf_ring[prod];
538 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
539 skb_frag_size(&skb_shinfo(skb)->frags[i]),
540 PCI_DMA_TODEVICE);
541 }
542
543 dev_kfree_skb_any(skb);
544 return NETDEV_TX_OK;
545}
546
547static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
548{
b6ab4b01 549 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
a960dec9 550 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
c0c050c5
MC		 551 u16 cons = txr->tx_cons;
552 struct pci_dev *pdev = bp->pdev;
553 int i;
554 unsigned int tx_bytes = 0;
555
556 for (i = 0; i < nr_pkts; i++) {
557 struct bnxt_sw_tx_bd *tx_buf;
558 struct sk_buff *skb;
559 int j, last;
560
561 tx_buf = &txr->tx_buf_ring[cons];
562 cons = NEXT_TX(cons);
563 skb = tx_buf->skb;
564 tx_buf->skb = NULL;
565
566 if (tx_buf->is_push) {
567 tx_buf->is_push = 0;
568 goto next_tx_int;
569 }
570
571 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
572 skb_headlen(skb), PCI_DMA_TODEVICE);
573 last = tx_buf->nr_frags;
574
575 for (j = 0; j < last; j++) {
576 cons = NEXT_TX(cons);
577 tx_buf = &txr->tx_buf_ring[cons];
578 dma_unmap_page(
579 &pdev->dev,
580 dma_unmap_addr(tx_buf, mapping),
581 skb_frag_size(&skb_shinfo(skb)->frags[j]),
582 PCI_DMA_TODEVICE);
583 }
584
585next_tx_int:
586 cons = NEXT_TX(cons);
587
588 tx_bytes += skb->len;
589 dev_kfree_skb_any(skb);
590 }
591
592 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
593 txr->tx_cons = cons;
594
595 /* Need to make the tx_cons update visible to bnxt_start_xmit()
596 * before checking for netif_tx_queue_stopped(). Without the
597 * memory barrier, there is a small possibility that bnxt_start_xmit()
598 * will miss it and cause the queue to be stopped forever.
599 */
600 smp_mb();
601
602 if (unlikely(netif_tx_queue_stopped(txq)) &&
603 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
604 __netif_tx_lock(txq, smp_processor_id());
605 if (netif_tx_queue_stopped(txq) &&
606 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
607 txr->dev_state != BNXT_DEV_STATE_CLOSING)
608 netif_tx_wake_queue(txq);
609 __netif_tx_unlock(txq);
610 }
611}
612
c61fb99c
MC		 613static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
614 gfp_t gfp)
615{
616 struct device *dev = &bp->pdev->dev;
617 struct page *page;
618
619 page = alloc_page(gfp);
620 if (!page)
621 return NULL;
622
c519fe9a
SN		 623 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
624 DMA_ATTR_WEAK_ORDERING);
c61fb99c
MC		 625 if (dma_mapping_error(dev, *mapping)) {
626 __free_page(page);
627 return NULL;
628 }
629 *mapping += bp->rx_dma_offset;
630 return page;
631}
632
c0c050c5
MC		 633static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
634 gfp_t gfp)
635{
636 u8 *data;
637 struct pci_dev *pdev = bp->pdev;
638
639 data = kmalloc(bp->rx_buf_size, gfp);
640 if (!data)
641 return NULL;
642
c519fe9a
SN		 643 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
644 bp->rx_buf_use_size, bp->rx_dir,
645 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 646
647 if (dma_mapping_error(&pdev->dev, *mapping)) {
648 kfree(data);
649 data = NULL;
650 }
651 return data;
652}
653
38413406
MC		 654int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
655 u16 prod, gfp_t gfp)
c0c050c5
MC		 656{
657 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
658 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
c0c050c5
MC		 659 dma_addr_t mapping;
660
c61fb99c
MC		 661 if (BNXT_RX_PAGE_MODE(bp)) {
662 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
c0c050c5 663
c61fb99c
MC		 664 if (!page)
665 return -ENOMEM;
666
667 rx_buf->data = page;
668 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
669 } else {
670 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
671
672 if (!data)
673 return -ENOMEM;
674
675 rx_buf->data = data;
676 rx_buf->data_ptr = data + bp->rx_offset;
677 }
11cd119d 678 rx_buf->mapping = mapping;
c0c050c5
MC		 679
680 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
c0c050c5
MC		 681 return 0;
682}
683
c6d30e83 684void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
c0c050c5
MC		 685{
686 u16 prod = rxr->rx_prod;
687 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
688 struct rx_bd *cons_bd, *prod_bd;
689
690 prod_rx_buf = &rxr->rx_buf_ring[prod];
691 cons_rx_buf = &rxr->rx_buf_ring[cons];
692
693 prod_rx_buf->data = data;
6bb19474 694 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
c0c050c5 695
11cd119d 696 prod_rx_buf->mapping = cons_rx_buf->mapping;
c0c050c5
MC		 697
698 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
699 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
700
701 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
702}
703
704static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
705{
706 u16 next, max = rxr->rx_agg_bmap_size;
707
708 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
709 if (next >= max)
710 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
711 return next;
712}
713
714static inline int bnxt_alloc_rx_page(struct bnxt *bp,
715 struct bnxt_rx_ring_info *rxr,
716 u16 prod, gfp_t gfp)
717{
718 struct rx_bd *rxbd =
719 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
720 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
721 struct pci_dev *pdev = bp->pdev;
722 struct page *page;
723 dma_addr_t mapping;
724 u16 sw_prod = rxr->rx_sw_agg_prod;
89d0a06c 725 unsigned int offset = 0;
c0c050c5 726
89d0a06c
MC		 727 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
728 page = rxr->rx_page;
729 if (!page) {
730 page = alloc_page(gfp);
731 if (!page)
732 return -ENOMEM;
733 rxr->rx_page = page;
734 rxr->rx_page_offset = 0;
735 }
736 offset = rxr->rx_page_offset;
737 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
738 if (rxr->rx_page_offset == PAGE_SIZE)
739 rxr->rx_page = NULL;
740 else
741 get_page(page);
742 } else {
743 page = alloc_page(gfp);
744 if (!page)
745 return -ENOMEM;
746 }
c0c050c5 747
c519fe9a
SN		 748 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
749 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
750 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 751 if (dma_mapping_error(&pdev->dev, mapping)) {
752 __free_page(page);
753 return -EIO;
754 }
755
756 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
757 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
758
759 __set_bit(sw_prod, rxr->rx_agg_bmap);
760 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
761 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
762
763 rx_agg_buf->page = page;
89d0a06c 764 rx_agg_buf->offset = offset;
c0c050c5
MC		 765 rx_agg_buf->mapping = mapping;
766 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
767 rxbd->rx_bd_opaque = sw_prod;
768 return 0;
769}
770
771static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
772 u32 agg_bufs)
773{
774 struct bnxt *bp = bnapi->bp;
775 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 776 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 777 u16 prod = rxr->rx_agg_prod;
778 u16 sw_prod = rxr->rx_sw_agg_prod;
779 u32 i;
780
781 for (i = 0; i < agg_bufs; i++) {
782 u16 cons;
783 struct rx_agg_cmp *agg;
784 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
785 struct rx_bd *prod_bd;
786 struct page *page;
787
788 agg = (struct rx_agg_cmp *)
789 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
790 cons = agg->rx_agg_cmp_opaque;
791 __clear_bit(cons, rxr->rx_agg_bmap);
792
793 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
794 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
795
796 __set_bit(sw_prod, rxr->rx_agg_bmap);
797 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
798 cons_rx_buf = &rxr->rx_agg_ring[cons];
799
800 /* It is possible for sw_prod to be equal to cons, so
801 * set cons_rx_buf->page to NULL first.
802 */
803 page = cons_rx_buf->page;
804 cons_rx_buf->page = NULL;
805 prod_rx_buf->page = page;
89d0a06c 806 prod_rx_buf->offset = cons_rx_buf->offset;
c0c050c5
MC		 807
808 prod_rx_buf->mapping = cons_rx_buf->mapping;
809
810 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
811
812 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
813 prod_bd->rx_bd_opaque = sw_prod;
814
815 prod = NEXT_RX_AGG(prod);
816 sw_prod = NEXT_RX_AGG(sw_prod);
817 cp_cons = NEXT_CMP(cp_cons);
818 }
819 rxr->rx_agg_prod = prod;
820 rxr->rx_sw_agg_prod = sw_prod;
821}
822
c61fb99c
MC		 823static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
824 struct bnxt_rx_ring_info *rxr,
825 u16 cons, void *data, u8 *data_ptr,
826 dma_addr_t dma_addr,
827 unsigned int offset_and_len)
828{
829 unsigned int payload = offset_and_len >> 16;
830 unsigned int len = offset_and_len & 0xffff;
831 struct skb_frag_struct *frag;
832 struct page *page = data;
833 u16 prod = rxr->rx_prod;
834 struct sk_buff *skb;
835 int off, err;
836
837 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
838 if (unlikely(err)) {
839 bnxt_reuse_rx_data(rxr, cons, data);
840 return NULL;
841 }
842 dma_addr -= bp->rx_dma_offset;
c519fe9a
SN		 843 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
844 DMA_ATTR_WEAK_ORDERING);
c61fb99c
MC		 845
846 if (unlikely(!payload))
847 payload = eth_get_headlen(data_ptr, len);
848
849 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
850 if (!skb) {
851 __free_page(page);
852 return NULL;
853 }
854
855 off = (void *)data_ptr - page_address(page);
856 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
857 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
858 payload + NET_IP_ALIGN);
859
860 frag = &skb_shinfo(skb)->frags[0];
861 skb_frag_size_sub(frag, payload);
862 frag->page_offset += payload;
863 skb->data_len -= payload;
864 skb->tail += payload;
865
866 return skb;
867}
868
c0c050c5
MC		 869static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
870 struct bnxt_rx_ring_info *rxr, u16 cons,
6bb19474
MC		 871 void *data, u8 *data_ptr,
872 dma_addr_t dma_addr,
873 unsigned int offset_and_len)
c0c050c5 874{
6bb19474 875 u16 prod = rxr->rx_prod;
c0c050c5 876 struct sk_buff *skb;
6bb19474 877 int err;
c0c050c5
MC		 878
879 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
880 if (unlikely(err)) {
881 bnxt_reuse_rx_data(rxr, cons, data);
882 return NULL;
883 }
884
885 skb = build_skb(data, 0);
c519fe9a
SN		 886 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
887 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 888 if (!skb) {
889 kfree(data);
890 return NULL;
891 }
892
b3dba77c 893 skb_reserve(skb, bp->rx_offset);
6bb19474 894 skb_put(skb, offset_and_len & 0xffff);
c0c050c5
MC		 895 return skb;
896}
897
898static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
899 struct sk_buff *skb, u16 cp_cons,
900 u32 agg_bufs)
901{
902 struct pci_dev *pdev = bp->pdev;
903 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 904 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 905 u16 prod = rxr->rx_agg_prod;
906 u32 i;
907
908 for (i = 0; i < agg_bufs; i++) {
909 u16 cons, frag_len;
910 struct rx_agg_cmp *agg;
911 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
912 struct page *page;
913 dma_addr_t mapping;
914
915 agg = (struct rx_agg_cmp *)
916 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
917 cons = agg->rx_agg_cmp_opaque;
918 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
919 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
920
921 cons_rx_buf = &rxr->rx_agg_ring[cons];
89d0a06c
MC		 922 skb_fill_page_desc(skb, i, cons_rx_buf->page,
923 cons_rx_buf->offset, frag_len);
c0c050c5
MC		 924 __clear_bit(cons, rxr->rx_agg_bmap);
925
926 /* It is possible for bnxt_alloc_rx_page() to allocate
927 * a sw_prod index that equals the cons index, so we
928 * need to clear the cons entry now.
929 */
11cd119d 930 mapping = cons_rx_buf->mapping;
c0c050c5
MC		 931 page = cons_rx_buf->page;
932 cons_rx_buf->page = NULL;
933
934 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
935 struct skb_shared_info *shinfo;
936 unsigned int nr_frags;
937
938 shinfo = skb_shinfo(skb);
939 nr_frags = --shinfo->nr_frags;
940 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
941
942 dev_kfree_skb(skb);
943
944 cons_rx_buf->page = page;
945
946 /* Update prod since possibly some pages have been
947 * allocated already.
948 */
949 rxr->rx_agg_prod = prod;
950 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
951 return NULL;
952 }
953
c519fe9a
SN		 954 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
955 PCI_DMA_FROMDEVICE,
956 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 957
958 skb->data_len += frag_len;
959 skb->len += frag_len;
960 skb->truesize += PAGE_SIZE;
961
962 prod = NEXT_RX_AGG(prod);
963 cp_cons = NEXT_CMP(cp_cons);
964 }
965 rxr->rx_agg_prod = prod;
966 return skb;
967}
968
969static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
970 u8 agg_bufs, u32 *raw_cons)
971{
972 u16 last;
973 struct rx_agg_cmp *agg;
974
975 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
976 last = RING_CMP(*raw_cons);
977 agg = (struct rx_agg_cmp *)
978 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
979 return RX_AGG_CMP_VALID(agg, *raw_cons);
980}
981
982static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
983 unsigned int len,
984 dma_addr_t mapping)
985{
986 struct bnxt *bp = bnapi->bp;
987 struct pci_dev *pdev = bp->pdev;
988 struct sk_buff *skb;
989
990 skb = napi_alloc_skb(&bnapi->napi, len);
991 if (!skb)
992 return NULL;
993
745fc05c
MC		 994 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
995 bp->rx_dir);
c0c050c5 996
6bb19474
MC		 997 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
998 len + NET_IP_ALIGN);
c0c050c5 999
745fc05c
MC		 1000 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1001 bp->rx_dir);
c0c050c5
MC		 1002
1003 skb_put(skb, len);
1004 return skb;
1005}
1006
fa7e2812
MC		 1007static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1008 u32 *raw_cons, void *cmp)
1009{
1010 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1011 struct rx_cmp *rxcmp = cmp;
1012 u32 tmp_raw_cons = *raw_cons;
1013 u8 cmp_type, agg_bufs = 0;
1014
1015 cmp_type = RX_CMP_TYPE(rxcmp);
1016
1017 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1018 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1019 RX_CMP_AGG_BUFS) >>
1020 RX_CMP_AGG_BUFS_SHIFT;
1021 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1022 struct rx_tpa_end_cmp *tpa_end = cmp;
1023
1024 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1025 RX_TPA_END_CMP_AGG_BUFS) >>
1026 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1027 }
1028
1029 if (agg_bufs) {
1030 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1031 return -EBUSY;
1032 }
1033 *raw_cons = tmp_raw_cons;
1034 return 0;
1035}
1036
c213eae8
MC		 1037static void bnxt_queue_sp_work(struct bnxt *bp)
1038{
1039 if (BNXT_PF(bp))
1040 queue_work(bnxt_pf_wq, &bp->sp_task);
1041 else
1042 schedule_work(&bp->sp_task);
1043}
1044
1045static void bnxt_cancel_sp_work(struct bnxt *bp)
1046{
1047 if (BNXT_PF(bp))
1048 flush_workqueue(bnxt_pf_wq);
1049 else
1050 cancel_work_sync(&bp->sp_task);
1051}
1052
fa7e2812
MC		 1053static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1054{
1055 if (!rxr->bnapi->in_reset) {
1056 rxr->bnapi->in_reset = true;
1057 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
c213eae8 1058 bnxt_queue_sp_work(bp);
fa7e2812
MC		 1059 }
1060 rxr->rx_next_cons = 0xffff;
1061}
1062
c0c050c5
MC		 1063static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1064 struct rx_tpa_start_cmp *tpa_start,
1065 struct rx_tpa_start_cmp_ext *tpa_start1)
1066{
1067 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1068 u16 cons, prod;
1069 struct bnxt_tpa_info *tpa_info;
1070 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1071 struct rx_bd *prod_bd;
1072 dma_addr_t mapping;
1073
1074 cons = tpa_start->rx_tpa_start_cmp_opaque;
1075 prod = rxr->rx_prod;
1076 cons_rx_buf = &rxr->rx_buf_ring[cons];
1077 prod_rx_buf = &rxr->rx_buf_ring[prod];
1078 tpa_info = &rxr->rx_tpa[agg_id];
1079
fa7e2812
MC		 1080 if (unlikely(cons != rxr->rx_next_cons)) {
1081 bnxt_sched_reset(bp, rxr);
1082 return;
1083 }
ee5c7fb3
SP		 1084 /* Store cfa_code in tpa_info to use in tpa_end
1085 * completion processing.
1086 */
1087 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
c0c050c5 1088 prod_rx_buf->data = tpa_info->data;
6bb19474 1089 prod_rx_buf->data_ptr = tpa_info->data_ptr;
c0c050c5
MC		 1090
1091 mapping = tpa_info->mapping;
11cd119d 1092 prod_rx_buf->mapping = mapping;
c0c050c5
MC		 1093
1094 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1095
1096 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1097
1098 tpa_info->data = cons_rx_buf->data;
6bb19474 1099 tpa_info->data_ptr = cons_rx_buf->data_ptr;
c0c050c5 1100 cons_rx_buf->data = NULL;
11cd119d 1101 tpa_info->mapping = cons_rx_buf->mapping;
c0c050c5
MC		 1102
1103 tpa_info->len =
1104 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1105 RX_TPA_START_CMP_LEN_SHIFT;
1106 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1107 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1108
1109 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1110 tpa_info->gso_type = SKB_GSO_TCPV4;
1111 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1112 if (hash_type == 3)
1113 tpa_info->gso_type = SKB_GSO_TCPV6;
1114 tpa_info->rss_hash =
1115 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1116 } else {
1117 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1118 tpa_info->gso_type = 0;
1119 if (netif_msg_rx_err(bp))
1120 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1121 }
1122 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1123 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
94758f8d 1124 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
c0c050c5
MC		 1125
1126 rxr->rx_prod = NEXT_RX(prod);
1127 cons = NEXT_RX(cons);
376a5b86 1128 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1129 cons_rx_buf = &rxr->rx_buf_ring[cons];
1130
1131 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1132 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1133 cons_rx_buf->data = NULL;
1134}
1135
1136static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1137 u16 cp_cons, u32 agg_bufs)
1138{
1139 if (agg_bufs)
1140 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1141}
1142
94758f8d
MC		 1143static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1144 int payload_off, int tcp_ts,
1145 struct sk_buff *skb)
1146{
1147#ifdef CONFIG_INET
1148 struct tcphdr *th;
1149 int len, nw_off;
1150 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1151 u32 hdr_info = tpa_info->hdr_info;
1152 bool loopback = false;
1153
1154 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1155 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1156 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1157
1158 /* If the packet is an internal loopback packet, the offsets will
1159 * have an extra 4 bytes.
1160 */
1161 if (inner_mac_off == 4) {
1162 loopback = true;
1163 } else if (inner_mac_off > 4) {
1164 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1165 ETH_HLEN - 2));
1166
1167 /* We only support inner iPv4/ipv6. If we don't see the
1168 * correct protocol ID, it must be a loopback packet where
1169 * the offsets are off by 4.
1170 */
09a7636a 1171 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
94758f8d
MC		 1172 loopback = true;
1173 }
1174 if (loopback) {
1175 /* internal loopback packet, subtract all offsets by 4 */
1176 inner_ip_off -= 4;
1177 inner_mac_off -= 4;
1178 outer_ip_off -= 4;
1179 }
1180
1181 nw_off = inner_ip_off - ETH_HLEN;
1182 skb_set_network_header(skb, nw_off);
1183 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1184 struct ipv6hdr *iph = ipv6_hdr(skb);
1185
1186 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1187 len = skb->len - skb_transport_offset(skb);
1188 th = tcp_hdr(skb);
1189 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1190 } else {
1191 struct iphdr *iph = ip_hdr(skb);
1192
1193 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1194 len = skb->len - skb_transport_offset(skb);
1195 th = tcp_hdr(skb);
1196 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1197 }
1198
1199 if (inner_mac_off) { /* tunnel */
1200 struct udphdr *uh = NULL;
1201 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1202 ETH_HLEN - 2));
1203
1204 if (proto == htons(ETH_P_IP)) {
1205 struct iphdr *iph = (struct iphdr *)skb->data;
1206
1207 if (iph->protocol == IPPROTO_UDP)
1208 uh = (struct udphdr *)(iph + 1);
1209 } else {
1210 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1211
1212 if (iph->nexthdr == IPPROTO_UDP)
1213 uh = (struct udphdr *)(iph + 1);
1214 }
1215 if (uh) {
1216 if (uh->check)
1217 skb_shinfo(skb)->gso_type |=
1218 SKB_GSO_UDP_TUNNEL_CSUM;
1219 else
1220 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1221 }
1222 }
1223#endif
1224 return skb;
1225}
1226
c0c050c5
MC		 1227#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1228#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1229
309369c9
MC		 1230static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1231 int payload_off, int tcp_ts,
c0c050c5
MC		 1232 struct sk_buff *skb)
1233{
d1611c3a 1234#ifdef CONFIG_INET
c0c050c5 1235 struct tcphdr *th;
719ca811 1236 int len, nw_off, tcp_opt_len = 0;
27e24189 1237
309369c9 1238 if (tcp_ts)
c0c050c5
MC		 1239 tcp_opt_len = 12;
1240
c0c050c5
MC		 1241 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1242 struct iphdr *iph;
1243
1244 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1245 ETH_HLEN;
1246 skb_set_network_header(skb, nw_off);
1247 iph = ip_hdr(skb);
1248 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1249 len = skb->len - skb_transport_offset(skb);
1250 th = tcp_hdr(skb);
1251 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1252 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1253 struct ipv6hdr *iph;
1254
1255 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1256 ETH_HLEN;
1257 skb_set_network_header(skb, nw_off);
1258 iph = ipv6_hdr(skb);
1259 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1260 len = skb->len - skb_transport_offset(skb);
1261 th = tcp_hdr(skb);
1262 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1263 } else {
1264 dev_kfree_skb_any(skb);
1265 return NULL;
1266 }
c0c050c5
MC		 1267
1268 if (nw_off) { /* tunnel */
1269 struct udphdr *uh = NULL;
1270
1271 if (skb->protocol == htons(ETH_P_IP)) {
1272 struct iphdr *iph = (struct iphdr *)skb->data;
1273
1274 if (iph->protocol == IPPROTO_UDP)
1275 uh = (struct udphdr *)(iph + 1);
1276 } else {
1277 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1278
1279 if (iph->nexthdr == IPPROTO_UDP)
1280 uh = (struct udphdr *)(iph + 1);
1281 }
1282 if (uh) {
1283 if (uh->check)
1284 skb_shinfo(skb)->gso_type |=
1285 SKB_GSO_UDP_TUNNEL_CSUM;
1286 else
1287 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1288 }
1289 }
1290#endif
1291 return skb;
1292}
1293
309369c9
MC		 1294static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1295 struct bnxt_tpa_info *tpa_info,
1296 struct rx_tpa_end_cmp *tpa_end,
1297 struct rx_tpa_end_cmp_ext *tpa_end1,
1298 struct sk_buff *skb)
1299{
1300#ifdef CONFIG_INET
1301 int payload_off;
1302 u16 segs;
1303
1304 segs = TPA_END_TPA_SEGS(tpa_end);
1305 if (segs == 1)
1306 return skb;
1307
1308 NAPI_GRO_CB(skb)->count = segs;
1309 skb_shinfo(skb)->gso_size =
1310 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1311 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1312 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1313 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1314 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1315 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
5910906c
MC		 1316 if (likely(skb))
1317 tcp_gro_complete(skb);
309369c9
MC		 1318#endif
1319 return skb;
1320}
1321
ee5c7fb3
SP		 1322/* Given the cfa_code of a received packet determine which
1323 * netdev (vf-rep or PF) the packet is destined to.
1324 */
1325static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1326{
1327 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1328
1329 /* if vf-rep dev is NULL, the must belongs to the PF */
1330 return dev ? dev : bp->dev;
1331}
1332
c0c050c5
MC		 1333static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1334 struct bnxt_napi *bnapi,
1335 u32 *raw_cons,
1336 struct rx_tpa_end_cmp *tpa_end,
1337 struct rx_tpa_end_cmp_ext *tpa_end1,
4e5dbbda 1338 u8 *event)
c0c050c5
MC		 1339{
1340 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1341 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5 1342 u8 agg_id = TPA_END_AGG_ID(tpa_end);
6bb19474 1343 u8 *data_ptr, agg_bufs;
c0c050c5
MC		 1344 u16 cp_cons = RING_CMP(*raw_cons);
1345 unsigned int len;
1346 struct bnxt_tpa_info *tpa_info;
1347 dma_addr_t mapping;
1348 struct sk_buff *skb;
6bb19474 1349 void *data;
c0c050c5 1350
fa7e2812
MC		 1351 if (unlikely(bnapi->in_reset)) {
1352 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1353
1354 if (rc < 0)
1355 return ERR_PTR(-EBUSY);
1356 return NULL;
1357 }
1358
c0c050c5
MC		 1359 tpa_info = &rxr->rx_tpa[agg_id];
1360 data = tpa_info->data;
6bb19474
MC		 1361 data_ptr = tpa_info->data_ptr;
1362 prefetch(data_ptr);
c0c050c5
MC		 1363 len = tpa_info->len;
1364 mapping = tpa_info->mapping;
1365
1366 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1367 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1368
1369 if (agg_bufs) {
1370 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1371 return ERR_PTR(-EBUSY);
1372
4e5dbbda 1373 *event |= BNXT_AGG_EVENT;
c0c050c5
MC		 1374 cp_cons = NEXT_CMP(cp_cons);
1375 }
1376
69c149e2 1377 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
c0c050c5 1378 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
69c149e2
MC		 1379 if (agg_bufs > MAX_SKB_FRAGS)
1380 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1381 agg_bufs, (int)MAX_SKB_FRAGS);
c0c050c5
MC		 1382 return NULL;
1383 }
1384
1385 if (len <= bp->rx_copy_thresh) {
6bb19474 1386 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
c0c050c5
MC		 1387 if (!skb) {
1388 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1389 return NULL;
1390 }
1391 } else {
1392 u8 *new_data;
1393 dma_addr_t new_mapping;
1394
1395 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1396 if (!new_data) {
1397 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1398 return NULL;
1399 }
1400
1401 tpa_info->data = new_data;
b3dba77c 1402 tpa_info->data_ptr = new_data + bp->rx_offset;
c0c050c5
MC		 1403 tpa_info->mapping = new_mapping;
1404
1405 skb = build_skb(data, 0);
c519fe9a
SN		 1406 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1407 bp->rx_buf_use_size, bp->rx_dir,
1408 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 1409
1410 if (!skb) {
1411 kfree(data);
1412 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1413 return NULL;
1414 }
b3dba77c 1415 skb_reserve(skb, bp->rx_offset);
c0c050c5
MC		 1416 skb_put(skb, len);
1417 }
1418
1419 if (agg_bufs) {
1420 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1421 if (!skb) {
1422 /* Page reuse already handled by bnxt_rx_pages(). */
1423 return NULL;
1424 }
1425 }
ee5c7fb3
SP		 1426
1427 skb->protocol =
1428 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
c0c050c5
MC		 1429
1430 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1431 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1432
8852ddb4
MC		 1433 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1434 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5
MC		 1435 u16 vlan_proto = tpa_info->metadata >>
1436 RX_CMP_FLAGS2_METADATA_TPID_SFT;
8852ddb4 1437 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5 1438
8852ddb4 1439 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1440 }
1441
1442 skb_checksum_none_assert(skb);
1443 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1444 skb->ip_summed = CHECKSUM_UNNECESSARY;
1445 skb->csum_level =
1446 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1447 }
1448
1449 if (TPA_END_GRO(tpa_end))
309369c9 1450 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
c0c050c5
MC		 1451
1452 return skb;
1453}
1454
ee5c7fb3
SP		 1455static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1456 struct sk_buff *skb)
1457{
1458 if (skb->dev != bp->dev) {
1459 /* this packet belongs to a vf-rep */
1460 bnxt_vf_rep_rx(bp, skb);
1461 return;
1462 }
1463 skb_record_rx_queue(skb, bnapi->index);
1464 napi_gro_receive(&bnapi->napi, skb);
1465}
1466
c0c050c5
MC		 1467/* returns the following:
1468 * 1 - 1 packet successfully received
1469 * 0 - successful TPA_START, packet not completed yet
1470 * -EBUSY - completion ring does not have all the agg buffers yet
1471 * -ENOMEM - packet aborted due to out of memory
1472 * -EIO - packet aborted due to hw error indicated in BD
1473 */
1474static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
4e5dbbda 1475 u8 *event)
c0c050c5
MC		 1476{
1477 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1478 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1479 struct net_device *dev = bp->dev;
1480 struct rx_cmp *rxcmp;
1481 struct rx_cmp_ext *rxcmp1;
1482 u32 tmp_raw_cons = *raw_cons;
ee5c7fb3 1483 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
c0c050c5
MC		 1484 struct bnxt_sw_rx_bd *rx_buf;
1485 unsigned int len;
6bb19474 1486 u8 *data_ptr, agg_bufs, cmp_type;
c0c050c5
MC		 1487 dma_addr_t dma_addr;
1488 struct sk_buff *skb;
6bb19474 1489 void *data;
c0c050c5 1490 int rc = 0;
c61fb99c 1491 u32 misc;
c0c050c5
MC		 1492
1493 rxcmp = (struct rx_cmp *)
1494 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1495
1496 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1497 cp_cons = RING_CMP(tmp_raw_cons);
1498 rxcmp1 = (struct rx_cmp_ext *)
1499 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1500
1501 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1502 return -EBUSY;
1503
1504 cmp_type = RX_CMP_TYPE(rxcmp);
1505
1506 prod = rxr->rx_prod;
1507
1508 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1509 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1510 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1511
4e5dbbda 1512 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1513 goto next_rx_no_prod;
1514
1515 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1516 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1517 (struct rx_tpa_end_cmp *)rxcmp,
4e5dbbda 1518 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
c0c050c5 1519
1fac4b2f 1520 if (IS_ERR(skb))
c0c050c5
MC		 1521 return -EBUSY;
1522
1523 rc = -ENOMEM;
1524 if (likely(skb)) {
ee5c7fb3 1525 bnxt_deliver_skb(bp, bnapi, skb);
c0c050c5
MC		 1526 rc = 1;
1527 }
4e5dbbda 1528 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1529 goto next_rx_no_prod;
1530 }
1531
1532 cons = rxcmp->rx_cmp_opaque;
1533 rx_buf = &rxr->rx_buf_ring[cons];
1534 data = rx_buf->data;
6bb19474 1535 data_ptr = rx_buf->data_ptr;
fa7e2812
MC		 1536 if (unlikely(cons != rxr->rx_next_cons)) {
1537 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1538
1539 bnxt_sched_reset(bp, rxr);
1540 return rc1;
1541 }
6bb19474 1542 prefetch(data_ptr);
c0c050c5 1543
c61fb99c
MC		 1544 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1545 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
c0c050c5
MC		 1546
1547 if (agg_bufs) {
1548 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1549 return -EBUSY;
1550
1551 cp_cons = NEXT_CMP(cp_cons);
4e5dbbda 1552 *event |= BNXT_AGG_EVENT;
c0c050c5 1553 }
4e5dbbda 1554 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1555
1556 rx_buf->data = NULL;
1557 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1558 bnxt_reuse_rx_data(rxr, cons, data);
1559 if (agg_bufs)
1560 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1561
1562 rc = -EIO;
1563 goto next_rx;
1564 }
1565
1566 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
11cd119d 1567 dma_addr = rx_buf->mapping;
c0c050c5 1568
c6d30e83
MC		 1569 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1570 rc = 1;
1571 goto next_rx;
1572 }
1573
c0c050c5 1574 if (len <= bp->rx_copy_thresh) {
6bb19474 1575 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
c0c050c5
MC		 1576 bnxt_reuse_rx_data(rxr, cons, data);
1577 if (!skb) {
1578 rc = -ENOMEM;
1579 goto next_rx;
1580 }
1581 } else {
c61fb99c
MC		 1582 u32 payload;
1583
c6d30e83
MC		 1584 if (rx_buf->data_ptr == data_ptr)
1585 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1586 else
1587 payload = 0;
6bb19474 1588 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
c61fb99c 1589 payload | len);
c0c050c5
MC		 1590 if (!skb) {
1591 rc = -ENOMEM;
1592 goto next_rx;
1593 }
1594 }
1595
1596 if (agg_bufs) {
1597 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1598 if (!skb) {
1599 rc = -ENOMEM;
1600 goto next_rx;
1601 }
1602 }
1603
1604 if (RX_CMP_HASH_VALID(rxcmp)) {
1605 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1606 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1607
1608 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1609 if (hash_type != 1 && hash_type != 3)
1610 type = PKT_HASH_TYPE_L3;
1611 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1612 }
1613
ee5c7fb3
SP		 1614 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1615 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
c0c050c5 1616
8852ddb4
MC		 1617 if ((rxcmp1->rx_cmp_flags2 &
1618 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1619 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5 1620 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
8852ddb4 1621 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5
MC		 1622 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1623
8852ddb4 1624 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1625 }
1626
1627 skb_checksum_none_assert(skb);
1628 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1629 if (dev->features & NETIF_F_RXCSUM) {
1630 skb->ip_summed = CHECKSUM_UNNECESSARY;
1631 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1632 }
1633 } else {
665e350d
SB		 1634 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1635 if (dev->features & NETIF_F_RXCSUM)
1636 cpr->rx_l4_csum_errors++;
1637 }
c0c050c5
MC		 1638 }
1639
ee5c7fb3 1640 bnxt_deliver_skb(bp, bnapi, skb);
c0c050c5
MC		 1641 rc = 1;
1642
1643next_rx:
1644 rxr->rx_prod = NEXT_RX(prod);
376a5b86 1645 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1646
1647next_rx_no_prod:
1648 *raw_cons = tmp_raw_cons;
1649
1650 return rc;
1651}
1652
2270bc5d
MC		 1653/* In netpoll mode, if we are using a combined completion ring, we need to
1654 * discard the rx packets and recycle the buffers.
1655 */
1656static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1657 u32 *raw_cons, u8 *event)
1658{
1659 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1660 u32 tmp_raw_cons = *raw_cons;
1661 struct rx_cmp_ext *rxcmp1;
1662 struct rx_cmp *rxcmp;
1663 u16 cp_cons;
1664 u8 cmp_type;
1665
1666 cp_cons = RING_CMP(tmp_raw_cons);
1667 rxcmp = (struct rx_cmp *)
1668 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1669
1670 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1671 cp_cons = RING_CMP(tmp_raw_cons);
1672 rxcmp1 = (struct rx_cmp_ext *)
1673 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1674
1675 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1676 return -EBUSY;
1677
1678 cmp_type = RX_CMP_TYPE(rxcmp);
1679 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1680 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1681 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1682 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1683 struct rx_tpa_end_cmp_ext *tpa_end1;
1684
1685 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1686 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1687 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1688 }
1689 return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1690}
1691
4bb13abf 1692#define BNXT_GET_EVENT_PORT(data) \
87c374de
MC		 1693 ((data) & \
1694 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
4bb13abf 1695
c0c050c5
MC		 1696static int bnxt_async_event_process(struct bnxt *bp,
1697 struct hwrm_async_event_cmpl *cmpl)
1698{
1699 u16 event_id = le16_to_cpu(cmpl->event_id);
1700
1701 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1702 switch (event_id) {
87c374de 1703 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
8cbde117
MC		 1704 u32 data1 = le32_to_cpu(cmpl->event_data1);
1705 struct bnxt_link_info *link_info = &bp->link_info;
1706
1707 if (BNXT_VF(bp))
1708 goto async_event_process_exit;
1709 if (data1 & 0x20000) {
1710 u16 fw_speed = link_info->force_link_speed;
1711 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1712
1713 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1714 speed);
1715 }
286ef9d6 1716 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
8cbde117
MC		 1717 /* fall thru */
1718 }
87c374de 1719 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
c0c050c5 1720 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368 1721 break;
87c374de 1722 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
19241368 1723 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5 1724 break;
87c374de 1725 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
4bb13abf
MC		 1726 u32 data1 = le32_to_cpu(cmpl->event_data1);
1727 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1728
1729 if (BNXT_VF(bp))
1730 break;
1731
1732 if (bp->pf.port_id != port_id)
1733 break;
1734
4bb13abf
MC		 1735 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1736 break;
1737 }
87c374de 1738 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
fc0f1929
MC		 1739 if (BNXT_PF(bp))
1740 goto async_event_process_exit;
1741 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1742 break;
c0c050c5 1743 default:
19241368 1744 goto async_event_process_exit;
c0c050c5 1745 }
c213eae8 1746 bnxt_queue_sp_work(bp);
19241368 1747async_event_process_exit:
a588e458 1748 bnxt_ulp_async_events(bp, cmpl);
c0c050c5
MC		 1749 return 0;
1750}
1751
1752static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1753{
1754 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1755 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1756 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1757 (struct hwrm_fwd_req_cmpl *)txcmp;
1758
1759 switch (cmpl_type) {
1760 case CMPL_BASE_TYPE_HWRM_DONE:
1761 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1762 if (seq_id == bp->hwrm_intr_seq_id)
1763 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1764 else
1765 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1766 break;
1767
1768 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1769 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1770
1771 if ((vf_id < bp->pf.first_vf_id) ||
1772 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1773 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1774 vf_id);
1775 return -EINVAL;
1776 }
1777
1778 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1779 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
c213eae8 1780 bnxt_queue_sp_work(bp);
c0c050c5
MC		 1781 break;
1782
1783 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1784 bnxt_async_event_process(bp,
1785 (struct hwrm_async_event_cmpl *)txcmp);
1786
1787 default:
1788 break;
1789 }
1790
1791 return 0;
1792}
1793
1794static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1795{
1796 struct bnxt_napi *bnapi = dev_instance;
1797 struct bnxt *bp = bnapi->bp;
1798 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1799 u32 cons = RING_CMP(cpr->cp_raw_cons);
1800
1801 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1802 napi_schedule(&bnapi->napi);
1803 return IRQ_HANDLED;
1804}
1805
1806static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1807{
1808 u32 raw_cons = cpr->cp_raw_cons;
1809 u16 cons = RING_CMP(raw_cons);
1810 struct tx_cmp *txcmp;
1811
1812 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1813
1814 return TX_CMP_VALID(txcmp, raw_cons);
1815}
1816
c0c050c5
MC		 1817static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1818{
1819 struct bnxt_napi *bnapi = dev_instance;
1820 struct bnxt *bp = bnapi->bp;
1821 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1822 u32 cons = RING_CMP(cpr->cp_raw_cons);
1823 u32 int_status;
1824
1825 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1826
1827 if (!bnxt_has_work(bp, cpr)) {
11809490 1828 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1829 /* return if erroneous interrupt */
1830 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1831 return IRQ_NONE;
1832 }
1833
1834 /* disable ring IRQ */
1835 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1836
1837 /* Return here if interrupt is shared and is disabled. */
1838 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1839 return IRQ_HANDLED;
1840
1841 napi_schedule(&bnapi->napi);
1842 return IRQ_HANDLED;
1843}
1844
1845static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1846{
1847 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1848 u32 raw_cons = cpr->cp_raw_cons;
1849 u32 cons;
1850 int tx_pkts = 0;
1851 int rx_pkts = 0;
4e5dbbda 1852 u8 event = 0;
c0c050c5
MC		 1853 struct tx_cmp *txcmp;
1854
1855 while (1) {
1856 int rc;
1857
1858 cons = RING_CMP(raw_cons);
1859 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1860
1861 if (!TX_CMP_VALID(txcmp, raw_cons))
1862 break;
1863
67a95e20
MC		 1864 /* The valid test of the entry must be done first before
1865 * reading any further.
1866 */
b67daab0 1867 dma_rmb();
c0c050c5
MC		 1868 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1869 tx_pkts++;
1870 /* return full budget so NAPI will complete. */
1871 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1872 rx_pkts = budget;
1873 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2270bc5d
MC		 1874 if (likely(budget))
1875 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1876 else
1877 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1878 &event);
c0c050c5
MC		 1879 if (likely(rc >= 0))
1880 rx_pkts += rc;
903649e7
MC		 1881 /* Increment rx_pkts when rc is -ENOMEM to count towards
1882 * the NAPI budget. Otherwise, we may potentially loop
1883 * here forever if we consistently cannot allocate
1884 * buffers.
1885 */
1886 else if (rc == -ENOMEM)
1887 rx_pkts++;
c0c050c5
MC		 1888 else if (rc == -EBUSY) /* partial completion */
1889 break;
c0c050c5
MC		 1890 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1891 CMPL_BASE_TYPE_HWRM_DONE) ||
1892 (TX_CMP_TYPE(txcmp) ==
1893 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1894 (TX_CMP_TYPE(txcmp) ==
1895 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1896 bnxt_hwrm_handler(bp, txcmp);
1897 }
1898 raw_cons = NEXT_RAW_CMP(raw_cons);
1899
1900 if (rx_pkts == budget)
1901 break;
1902 }
1903
38413406
MC		 1904 if (event & BNXT_TX_EVENT) {
1905 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1906 void __iomem *db = txr->tx_doorbell;
1907 u16 prod = txr->tx_prod;
1908
1909 /* Sync BD data before updating doorbell */
1910 wmb();
1911
434c975a 1912 bnxt_db_write(bp, db, DB_KEY_TX | prod);
38413406
MC		 1913 }
1914
c0c050c5
MC		 1915 cpr->cp_raw_cons = raw_cons;
1916 /* ACK completion ring before freeing tx ring and producing new
1917 * buffers in rx/agg rings to prevent overflowing the completion
1918 * ring.
1919 */
1920 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1921
1922 if (tx_pkts)
fa3e93e8 1923 bnapi->tx_int(bp, bnapi, tx_pkts);
c0c050c5 1924
4e5dbbda 1925 if (event & BNXT_RX_EVENT) {
b6ab4b01 1926 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5 1927
434c975a
MC		 1928 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1929 if (event & BNXT_AGG_EVENT)
1930 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1931 DB_KEY_RX | rxr->rx_agg_prod);
c0c050c5
MC		 1932 }
1933 return rx_pkts;
1934}
1935
10bbdaf5
PS		 1936static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1937{
1938 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1939 struct bnxt *bp = bnapi->bp;
1940 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1941 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1942 struct tx_cmp *txcmp;
1943 struct rx_cmp_ext *rxcmp1;
1944 u32 cp_cons, tmp_raw_cons;
1945 u32 raw_cons = cpr->cp_raw_cons;
1946 u32 rx_pkts = 0;
4e5dbbda 1947 u8 event = 0;
10bbdaf5
PS		 1948
1949 while (1) {
1950 int rc;
1951
1952 cp_cons = RING_CMP(raw_cons);
1953 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1954
1955 if (!TX_CMP_VALID(txcmp, raw_cons))
1956 break;
1957
1958 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1959 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1960 cp_cons = RING_CMP(tmp_raw_cons);
1961 rxcmp1 = (struct rx_cmp_ext *)
1962 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1963
1964 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1965 break;
1966
1967 /* force an error to recycle the buffer */
1968 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1969 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1970
4e5dbbda 1971 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
10bbdaf5
PS		 1972 if (likely(rc == -EIO))
1973 rx_pkts++;
1974 else if (rc == -EBUSY) /* partial completion */
1975 break;
1976 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1977 CMPL_BASE_TYPE_HWRM_DONE)) {
1978 bnxt_hwrm_handler(bp, txcmp);
1979 } else {
1980 netdev_err(bp->dev,
1981 "Invalid completion received on special ring\n");
1982 }
1983 raw_cons = NEXT_RAW_CMP(raw_cons);
1984
1985 if (rx_pkts == budget)
1986 break;
1987 }
1988
1989 cpr->cp_raw_cons = raw_cons;
1990 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
434c975a 1991 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
10bbdaf5 1992
434c975a
MC		 1993 if (event & BNXT_AGG_EVENT)
1994 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1995 DB_KEY_RX | rxr->rx_agg_prod);
10bbdaf5
PS		 1996
1997 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
6ad20165 1998 napi_complete_done(napi, rx_pkts);
10bbdaf5
PS		 1999 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2000 }
2001 return rx_pkts;
2002}
2003
c0c050c5
MC		 2004static int bnxt_poll(struct napi_struct *napi, int budget)
2005{
2006 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2007 struct bnxt *bp = bnapi->bp;
2008 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2009 int work_done = 0;
2010
c0c050c5
MC		 2011 while (1) {
2012 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2013
2014 if (work_done >= budget)
2015 break;
2016
2017 if (!bnxt_has_work(bp, cpr)) {
e7b95691
MC		 2018 if (napi_complete_done(napi, work_done))
2019 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2020 cpr->cp_raw_cons);
c0c050c5
MC		 2021 break;
2022 }
2023 }
2024 mmiowb();
c0c050c5
MC		 2025 return work_done;
2026}
2027
c0c050c5
MC		 2028static void bnxt_free_tx_skbs(struct bnxt *bp)
2029{
2030 int i, max_idx;
2031 struct pci_dev *pdev = bp->pdev;
2032
b6ab4b01 2033 if (!bp->tx_ring)
c0c050c5
MC		 2034 return;
2035
2036 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2037 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2038 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2039 int j;
2040
c0c050c5
MC		 2041 for (j = 0; j < max_idx;) {
2042 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2043 struct sk_buff *skb = tx_buf->skb;
2044 int k, last;
2045
2046 if (!skb) {
2047 j++;
2048 continue;
2049 }
2050
2051 tx_buf->skb = NULL;
2052
2053 if (tx_buf->is_push) {
2054 dev_kfree_skb(skb);
2055 j += 2;
2056 continue;
2057 }
2058
2059 dma_unmap_single(&pdev->dev,
2060 dma_unmap_addr(tx_buf, mapping),
2061 skb_headlen(skb),
2062 PCI_DMA_TODEVICE);
2063
2064 last = tx_buf->nr_frags;
2065 j += 2;
d612a579
MC		 2066 for (k = 0; k < last; k++, j++) {
2067 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 2068 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2069
d612a579 2070 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 2071 dma_unmap_page(
2072 &pdev->dev,
2073 dma_unmap_addr(tx_buf, mapping),
2074 skb_frag_size(frag), PCI_DMA_TODEVICE);
2075 }
2076 dev_kfree_skb(skb);
2077 }
2078 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2079 }
2080}
2081
2082static void bnxt_free_rx_skbs(struct bnxt *bp)
2083{
2084 int i, max_idx, max_agg_idx;
2085 struct pci_dev *pdev = bp->pdev;
2086
b6ab4b01 2087 if (!bp->rx_ring)
c0c050c5
MC		 2088 return;
2089
2090 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2091 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2092 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2093 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2094 int j;
2095
c0c050c5
MC		 2096 if (rxr->rx_tpa) {
2097 for (j = 0; j < MAX_TPA; j++) {
2098 struct bnxt_tpa_info *tpa_info =
2099 &rxr->rx_tpa[j];
2100 u8 *data = tpa_info->data;
2101
2102 if (!data)
2103 continue;
2104
c519fe9a
SN		 2105 dma_unmap_single_attrs(&pdev->dev,
2106 tpa_info->mapping,
2107 bp->rx_buf_use_size,
2108 bp->rx_dir,
2109 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 2110
2111 tpa_info->data = NULL;
2112
2113 kfree(data);
2114 }
2115 }
2116
2117 for (j = 0; j < max_idx; j++) {
2118 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
3ed3a83e 2119 dma_addr_t mapping = rx_buf->mapping;
6bb19474 2120 void *data = rx_buf->data;
c0c050c5
MC		 2121
2122 if (!data)
2123 continue;
2124
c0c050c5
MC		 2125 rx_buf->data = NULL;
2126
3ed3a83e
MC		 2127 if (BNXT_RX_PAGE_MODE(bp)) {
2128 mapping -= bp->rx_dma_offset;
c519fe9a
SN		 2129 dma_unmap_page_attrs(&pdev->dev, mapping,
2130 PAGE_SIZE, bp->rx_dir,
2131 DMA_ATTR_WEAK_ORDERING);
c61fb99c 2132 __free_page(data);
3ed3a83e 2133 } else {
c519fe9a
SN		 2134 dma_unmap_single_attrs(&pdev->dev, mapping,
2135 bp->rx_buf_use_size,
2136 bp->rx_dir,
2137 DMA_ATTR_WEAK_ORDERING);
c61fb99c 2138 kfree(data);
3ed3a83e 2139 }
c0c050c5
MC		 2140 }
2141
2142 for (j = 0; j < max_agg_idx; j++) {
2143 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2144 &rxr->rx_agg_ring[j];
2145 struct page *page = rx_agg_buf->page;
2146
2147 if (!page)
2148 continue;
2149
c519fe9a
SN		 2150 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2151 BNXT_RX_PAGE_SIZE,
2152 PCI_DMA_FROMDEVICE,
2153 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 2154
2155 rx_agg_buf->page = NULL;
2156 __clear_bit(j, rxr->rx_agg_bmap);
2157
2158 __free_page(page);
2159 }
89d0a06c
MC		 2160 if (rxr->rx_page) {
2161 __free_page(rxr->rx_page);
2162 rxr->rx_page = NULL;
2163 }
c0c050c5
MC		 2164 }
2165}
2166
2167static void bnxt_free_skbs(struct bnxt *bp)
2168{
2169 bnxt_free_tx_skbs(bp);
2170 bnxt_free_rx_skbs(bp);
2171}
2172
2173static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2174{
2175 struct pci_dev *pdev = bp->pdev;
2176 int i;
2177
2178 for (i = 0; i < ring->nr_pages; i++) {
2179 if (!ring->pg_arr[i])
2180 continue;
2181
2182 dma_free_coherent(&pdev->dev, ring->page_size,
2183 ring->pg_arr[i], ring->dma_arr[i]);
2184
2185 ring->pg_arr[i] = NULL;
2186 }
2187 if (ring->pg_tbl) {
2188 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2189 ring->pg_tbl, ring->pg_tbl_map);
2190 ring->pg_tbl = NULL;
2191 }
2192 if (ring->vmem_size && *ring->vmem) {
2193 vfree(*ring->vmem);
2194 *ring->vmem = NULL;
2195 }
2196}
2197
2198static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2199{
2200 int i;
2201 struct pci_dev *pdev = bp->pdev;
2202
2203 if (ring->nr_pages > 1) {
2204 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2205 ring->nr_pages * 8,
2206 &ring->pg_tbl_map,
2207 GFP_KERNEL);
2208 if (!ring->pg_tbl)
2209 return -ENOMEM;
2210 }
2211
2212 for (i = 0; i < ring->nr_pages; i++) {
2213 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2214 ring->page_size,
2215 &ring->dma_arr[i],
2216 GFP_KERNEL);
2217 if (!ring->pg_arr[i])
2218 return -ENOMEM;
2219
2220 if (ring->nr_pages > 1)
2221 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2222 }
2223
2224 if (ring->vmem_size) {
2225 *ring->vmem = vzalloc(ring->vmem_size);
2226 if (!(*ring->vmem))
2227 return -ENOMEM;
2228 }
2229 return 0;
2230}
2231
2232static void bnxt_free_rx_rings(struct bnxt *bp)
2233{
2234 int i;
2235
b6ab4b01 2236 if (!bp->rx_ring)
c0c050c5
MC		 2237 return;
2238
2239 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2240 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2241 struct bnxt_ring_struct *ring;
2242
c6d30e83
MC		 2243 if (rxr->xdp_prog)
2244 bpf_prog_put(rxr->xdp_prog);
2245
c0c050c5
MC		 2246 kfree(rxr->rx_tpa);
2247 rxr->rx_tpa = NULL;
2248
2249 kfree(rxr->rx_agg_bmap);
2250 rxr->rx_agg_bmap = NULL;
2251
2252 ring = &rxr->rx_ring_struct;
2253 bnxt_free_ring(bp, ring);
2254
2255 ring = &rxr->rx_agg_ring_struct;
2256 bnxt_free_ring(bp, ring);
2257 }
2258}
2259
2260static int bnxt_alloc_rx_rings(struct bnxt *bp)
2261{
2262 int i, rc, agg_rings = 0, tpa_rings = 0;
2263
b6ab4b01
MC		 2264 if (!bp->rx_ring)
2265 return -ENOMEM;
2266
c0c050c5
MC		 2267 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2268 agg_rings = 1;
2269
2270 if (bp->flags & BNXT_FLAG_TPA)
2271 tpa_rings = 1;
2272
2273 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2274 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2275 struct bnxt_ring_struct *ring;
2276
c0c050c5
MC		 2277 ring = &rxr->rx_ring_struct;
2278
2279 rc = bnxt_alloc_ring(bp, ring);
2280 if (rc)
2281 return rc;
2282
2283 if (agg_rings) {
2284 u16 mem_size;
2285
2286 ring = &rxr->rx_agg_ring_struct;
2287 rc = bnxt_alloc_ring(bp, ring);
2288 if (rc)
2289 return rc;
2290
2291 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2292 mem_size = rxr->rx_agg_bmap_size / 8;
2293 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2294 if (!rxr->rx_agg_bmap)
2295 return -ENOMEM;
2296
2297 if (tpa_rings) {
2298 rxr->rx_tpa = kcalloc(MAX_TPA,
2299 sizeof(struct bnxt_tpa_info),
2300 GFP_KERNEL);
2301 if (!rxr->rx_tpa)
2302 return -ENOMEM;
2303 }
2304 }
2305 }
2306 return 0;
2307}
2308
2309static void bnxt_free_tx_rings(struct bnxt *bp)
2310{
2311 int i;
2312 struct pci_dev *pdev = bp->pdev;
2313
b6ab4b01 2314 if (!bp->tx_ring)
c0c050c5
MC		 2315 return;
2316
2317 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2318 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2319 struct bnxt_ring_struct *ring;
2320
c0c050c5
MC		 2321 if (txr->tx_push) {
2322 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2323 txr->tx_push, txr->tx_push_mapping);
2324 txr->tx_push = NULL;
2325 }
2326
2327 ring = &txr->tx_ring_struct;
2328
2329 bnxt_free_ring(bp, ring);
2330 }
2331}
2332
2333static int bnxt_alloc_tx_rings(struct bnxt *bp)
2334{
2335 int i, j, rc;
2336 struct pci_dev *pdev = bp->pdev;
2337
2338 bp->tx_push_size = 0;
2339 if (bp->tx_push_thresh) {
2340 int push_size;
2341
2342 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2343 bp->tx_push_thresh);
2344
4419dbe6 2345 if (push_size > 256) {
c0c050c5
MC		 2346 push_size = 0;
2347 bp->tx_push_thresh = 0;
2348 }
2349
2350 bp->tx_push_size = push_size;
2351 }
2352
2353 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2354 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2355 struct bnxt_ring_struct *ring;
2356
c0c050c5
MC		 2357 ring = &txr->tx_ring_struct;
2358
2359 rc = bnxt_alloc_ring(bp, ring);
2360 if (rc)
2361 return rc;
2362
2363 if (bp->tx_push_size) {
c0c050c5
MC		 2364 dma_addr_t mapping;
2365
2366 /* One pre-allocated DMA buffer to backup
2367 * TX push operation
2368 */
2369 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2370 bp->tx_push_size,
2371 &txr->tx_push_mapping,
2372 GFP_KERNEL);
2373
2374 if (!txr->tx_push)
2375 return -ENOMEM;
2376
c0c050c5
MC		 2377 mapping = txr->tx_push_mapping +
2378 sizeof(struct tx_push_bd);
4419dbe6 2379 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 2380
4419dbe6 2381 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5
MC		 2382 }
2383 ring->queue_id = bp->q_info[j].queue_id;
5f449249
MC		 2384 if (i < bp->tx_nr_rings_xdp)
2385 continue;
c0c050c5
MC		 2386 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2387 j++;
2388 }
2389 return 0;
2390}
2391
2392static void bnxt_free_cp_rings(struct bnxt *bp)
2393{
2394 int i;
2395
2396 if (!bp->bnapi)
2397 return;
2398
2399 for (i = 0; i < bp->cp_nr_rings; i++) {
2400 struct bnxt_napi *bnapi = bp->bnapi[i];
2401 struct bnxt_cp_ring_info *cpr;
2402 struct bnxt_ring_struct *ring;
2403
2404 if (!bnapi)
2405 continue;
2406
2407 cpr = &bnapi->cp_ring;
2408 ring = &cpr->cp_ring_struct;
2409
2410 bnxt_free_ring(bp, ring);
2411 }
2412}
2413
2414static int bnxt_alloc_cp_rings(struct bnxt *bp)
2415{
2416 int i, rc;
2417
2418 for (i = 0; i < bp->cp_nr_rings; i++) {
2419 struct bnxt_napi *bnapi = bp->bnapi[i];
2420 struct bnxt_cp_ring_info *cpr;
2421 struct bnxt_ring_struct *ring;
2422
2423 if (!bnapi)
2424 continue;
2425
2426 cpr = &bnapi->cp_ring;
2427 ring = &cpr->cp_ring_struct;
2428
2429 rc = bnxt_alloc_ring(bp, ring);
2430 if (rc)
2431 return rc;
2432 }
2433 return 0;
2434}
2435
2436static void bnxt_init_ring_struct(struct bnxt *bp)
2437{
2438 int i;
2439
2440 for (i = 0; i < bp->cp_nr_rings; i++) {
2441 struct bnxt_napi *bnapi = bp->bnapi[i];
2442 struct bnxt_cp_ring_info *cpr;
2443 struct bnxt_rx_ring_info *rxr;
2444 struct bnxt_tx_ring_info *txr;
2445 struct bnxt_ring_struct *ring;
2446
2447 if (!bnapi)
2448 continue;
2449
2450 cpr = &bnapi->cp_ring;
2451 ring = &cpr->cp_ring_struct;
2452 ring->nr_pages = bp->cp_nr_pages;
2453 ring->page_size = HW_CMPD_RING_SIZE;
2454 ring->pg_arr = (void **)cpr->cp_desc_ring;
2455 ring->dma_arr = cpr->cp_desc_mapping;
2456 ring->vmem_size = 0;
2457
b6ab4b01 2458 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2459 if (!rxr)
2460 goto skip_rx;
2461
c0c050c5
MC		 2462 ring = &rxr->rx_ring_struct;
2463 ring->nr_pages = bp->rx_nr_pages;
2464 ring->page_size = HW_RXBD_RING_SIZE;
2465 ring->pg_arr = (void **)rxr->rx_desc_ring;
2466 ring->dma_arr = rxr->rx_desc_mapping;
2467 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2468 ring->vmem = (void **)&rxr->rx_buf_ring;
2469
2470 ring = &rxr->rx_agg_ring_struct;
2471 ring->nr_pages = bp->rx_agg_nr_pages;
2472 ring->page_size = HW_RXBD_RING_SIZE;
2473 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2474 ring->dma_arr = rxr->rx_agg_desc_mapping;
2475 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2476 ring->vmem = (void **)&rxr->rx_agg_ring;
2477
3b2b7d9d 2478skip_rx:
b6ab4b01 2479 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2480 if (!txr)
2481 continue;
2482
c0c050c5
MC		 2483 ring = &txr->tx_ring_struct;
2484 ring->nr_pages = bp->tx_nr_pages;
2485 ring->page_size = HW_RXBD_RING_SIZE;
2486 ring->pg_arr = (void **)txr->tx_desc_ring;
2487 ring->dma_arr = txr->tx_desc_mapping;
2488 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2489 ring->vmem = (void **)&txr->tx_buf_ring;
2490 }
2491}
2492
2493static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2494{
2495 int i;
2496 u32 prod;
2497 struct rx_bd **rx_buf_ring;
2498
2499 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2500 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2501 int j;
2502 struct rx_bd *rxbd;
2503
2504 rxbd = rx_buf_ring[i];
2505 if (!rxbd)
2506 continue;
2507
2508 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2509 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2510 rxbd->rx_bd_opaque = prod;
2511 }
2512 }
2513}
2514
2515static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2516{
2517 struct net_device *dev = bp->dev;
c0c050c5
MC		 2518 struct bnxt_rx_ring_info *rxr;
2519 struct bnxt_ring_struct *ring;
2520 u32 prod, type;
2521 int i;
2522
c0c050c5
MC		 2523 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2524 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2525
2526 if (NET_IP_ALIGN == 2)
2527 type |= RX_BD_FLAGS_SOP;
2528
b6ab4b01 2529 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 2530 ring = &rxr->rx_ring_struct;
2531 bnxt_init_rxbd_pages(ring, type);
2532
c6d30e83
MC		 2533 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2534 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2535 if (IS_ERR(rxr->xdp_prog)) {
2536 int rc = PTR_ERR(rxr->xdp_prog);
2537
2538 rxr->xdp_prog = NULL;
2539 return rc;
2540 }
2541 }
c0c050c5
MC		 2542 prod = rxr->rx_prod;
2543 for (i = 0; i < bp->rx_ring_size; i++) {
2544 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2545 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2546 ring_nr, i, bp->rx_ring_size);
2547 break;
2548 }
2549 prod = NEXT_RX(prod);
2550 }
2551 rxr->rx_prod = prod;
2552 ring->fw_ring_id = INVALID_HW_RING_ID;
2553
edd0c2cc
MC		 2554 ring = &rxr->rx_agg_ring_struct;
2555 ring->fw_ring_id = INVALID_HW_RING_ID;
2556
c0c050c5
MC		 2557 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2558 return 0;
2559
2839f28b 2560 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
c0c050c5
MC		 2561 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2562
2563 bnxt_init_rxbd_pages(ring, type);
2564
2565 prod = rxr->rx_agg_prod;
2566 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2567 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2568 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2569 ring_nr, i, bp->rx_ring_size);
2570 break;
2571 }
2572 prod = NEXT_RX_AGG(prod);
2573 }
2574 rxr->rx_agg_prod = prod;
c0c050c5
MC		 2575
2576 if (bp->flags & BNXT_FLAG_TPA) {
2577 if (rxr->rx_tpa) {
2578 u8 *data;
2579 dma_addr_t mapping;
2580
2581 for (i = 0; i < MAX_TPA; i++) {
2582 data = __bnxt_alloc_rx_data(bp, &mapping,
2583 GFP_KERNEL);
2584 if (!data)
2585 return -ENOMEM;
2586
2587 rxr->rx_tpa[i].data = data;
b3dba77c 2588 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
c0c050c5
MC		 2589 rxr->rx_tpa[i].mapping = mapping;
2590 }
2591 } else {
2592 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2593 return -ENOMEM;
2594 }
2595 }
2596
2597 return 0;
2598}
2599
2247925f
SP		 2600static void bnxt_init_cp_rings(struct bnxt *bp)
2601{
2602 int i;
2603
2604 for (i = 0; i < bp->cp_nr_rings; i++) {
2605 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2606 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2607
2608 ring->fw_ring_id = INVALID_HW_RING_ID;
2609 }
2610}
2611
c0c050c5
MC		 2612static int bnxt_init_rx_rings(struct bnxt *bp)
2613{
2614 int i, rc = 0;
2615
c61fb99c 2616 if (BNXT_RX_PAGE_MODE(bp)) {
c6d30e83
MC		 2617 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2618 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
c61fb99c
MC		 2619 } else {
2620 bp->rx_offset = BNXT_RX_OFFSET;
2621 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2622 }
b3dba77c 2623
c0c050c5
MC		 2624 for (i = 0; i < bp->rx_nr_rings; i++) {
2625 rc = bnxt_init_one_rx_ring(bp, i);
2626 if (rc)
2627 break;
2628 }
2629
2630 return rc;
2631}
2632
2633static int bnxt_init_tx_rings(struct bnxt *bp)
2634{
2635 u16 i;
2636
2637 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2638 MAX_SKB_FRAGS + 1);
2639
2640 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2641 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2642 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2643
2644 ring->fw_ring_id = INVALID_HW_RING_ID;
2645 }
2646
2647 return 0;
2648}
2649
2650static void bnxt_free_ring_grps(struct bnxt *bp)
2651{
2652 kfree(bp->grp_info);
2653 bp->grp_info = NULL;
2654}
2655
2656static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2657{
2658 int i;
2659
2660 if (irq_re_init) {
2661 bp->grp_info = kcalloc(bp->cp_nr_rings,
2662 sizeof(struct bnxt_ring_grp_info),
2663 GFP_KERNEL);
2664 if (!bp->grp_info)
2665 return -ENOMEM;
2666 }
2667 for (i = 0; i < bp->cp_nr_rings; i++) {
2668 if (irq_re_init)
2669 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2670 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2671 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2672 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2673 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2674 }
2675 return 0;
2676}
2677
2678static void bnxt_free_vnics(struct bnxt *bp)
2679{
2680 kfree(bp->vnic_info);
2681 bp->vnic_info = NULL;
2682 bp->nr_vnics = 0;
2683}
2684
2685static int bnxt_alloc_vnics(struct bnxt *bp)
2686{
2687 int num_vnics = 1;
2688
2689#ifdef CONFIG_RFS_ACCEL
2690 if (bp->flags & BNXT_FLAG_RFS)
2691 num_vnics += bp->rx_nr_rings;
2692#endif
2693
dc52c6c7
PS		 2694 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2695 num_vnics++;
2696
c0c050c5
MC		 2697 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2698 GFP_KERNEL);
2699 if (!bp->vnic_info)
2700 return -ENOMEM;
2701
2702 bp->nr_vnics = num_vnics;
2703 return 0;
2704}
2705
2706static void bnxt_init_vnics(struct bnxt *bp)
2707{
2708 int i;
2709
2710 for (i = 0; i < bp->nr_vnics; i++) {
2711 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2712
2713 vnic->fw_vnic_id = INVALID_HW_RING_ID;
94ce9caa
PS		 2714 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2715 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 2716 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2717
2718 if (bp->vnic_info[i].rss_hash_key) {
2719 if (i == 0)
2720 prandom_bytes(vnic->rss_hash_key,
2721 HW_HASH_KEY_SIZE);
2722 else
2723 memcpy(vnic->rss_hash_key,
2724 bp->vnic_info[0].rss_hash_key,
2725 HW_HASH_KEY_SIZE);
2726 }
2727 }
2728}
2729
2730static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2731{
2732 int pages;
2733
2734 pages = ring_size / desc_per_pg;
2735
2736 if (!pages)
2737 return 1;
2738
2739 pages++;
2740
2741 while (pages & (pages - 1))
2742 pages++;
2743
2744 return pages;
2745}
2746
c6d30e83 2747void bnxt_set_tpa_flags(struct bnxt *bp)
c0c050c5
MC		 2748{
2749 bp->flags &= ~BNXT_FLAG_TPA;
341138c3
MC		 2750 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2751 return;
c0c050c5
MC		 2752 if (bp->dev->features & NETIF_F_LRO)
2753 bp->flags |= BNXT_FLAG_LRO;
94758f8d 2754 if (bp->dev->features & NETIF_F_GRO)
c0c050c5
MC		 2755 bp->flags |= BNXT_FLAG_GRO;
2756}
2757
2758/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2759 * be set on entry.
2760 */
2761void bnxt_set_ring_params(struct bnxt *bp)
2762{
2763 u32 ring_size, rx_size, rx_space;
2764 u32 agg_factor = 0, agg_ring_size = 0;
2765
2766 /* 8 for CRC and VLAN */
2767 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2768
2769 rx_space = rx_size + NET_SKB_PAD +
2770 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2771
2772 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2773 ring_size = bp->rx_ring_size;
2774 bp->rx_agg_ring_size = 0;
2775 bp->rx_agg_nr_pages = 0;
2776
2777 if (bp->flags & BNXT_FLAG_TPA)
2839f28b 2778 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
c0c050c5
MC		 2779
2780 bp->flags &= ~BNXT_FLAG_JUMBO;
bdbd1eb5 2781 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
c0c050c5
MC		 2782 u32 jumbo_factor;
2783
2784 bp->flags |= BNXT_FLAG_JUMBO;
2785 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2786 if (jumbo_factor > agg_factor)
2787 agg_factor = jumbo_factor;
2788 }
2789 agg_ring_size = ring_size * agg_factor;
2790
2791 if (agg_ring_size) {
2792 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2793 RX_DESC_CNT);
2794 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2795 u32 tmp = agg_ring_size;
2796
2797 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2798 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2799 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2800 tmp, agg_ring_size);
2801 }
2802 bp->rx_agg_ring_size = agg_ring_size;
2803 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2804 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2805 rx_space = rx_size + NET_SKB_PAD +
2806 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2807 }
2808
2809 bp->rx_buf_use_size = rx_size;
2810 bp->rx_buf_size = rx_space;
2811
2812 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2813 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2814
2815 ring_size = bp->tx_ring_size;
2816 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2817 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2818
2819 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2820 bp->cp_ring_size = ring_size;
2821
2822 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2823 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2824 bp->cp_nr_pages = MAX_CP_PAGES;
2825 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2826 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2827 ring_size, bp->cp_ring_size);
2828 }
2829 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2830 bp->cp_ring_mask = bp->cp_bit - 1;
2831}
2832
c61fb99c 2833int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
6bb19474 2834{
c61fb99c
MC		 2835 if (page_mode) {
2836 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2837 return -EOPNOTSUPP;
7eb9bb3a
MC		 2838 bp->dev->max_mtu =
2839 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
c61fb99c
MC		 2840 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2841 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2842 bp->dev->hw_features &= ~NETIF_F_LRO;
2843 bp->dev->features &= ~NETIF_F_LRO;
2844 bp->rx_dir = DMA_BIDIRECTIONAL;
2845 bp->rx_skb_func = bnxt_rx_page_skb;
2846 } else {
7eb9bb3a 2847 bp->dev->max_mtu = bp->max_mtu;
c61fb99c
MC		 2848 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2849 bp->rx_dir = DMA_FROM_DEVICE;
2850 bp->rx_skb_func = bnxt_rx_skb;
2851 }
6bb19474
MC		 2852 return 0;
2853}
2854
c0c050c5
MC		 2855static void bnxt_free_vnic_attributes(struct bnxt *bp)
2856{
2857 int i;
2858 struct bnxt_vnic_info *vnic;
2859 struct pci_dev *pdev = bp->pdev;
2860
2861 if (!bp->vnic_info)
2862 return;
2863
2864 for (i = 0; i < bp->nr_vnics; i++) {
2865 vnic = &bp->vnic_info[i];
2866
2867 kfree(vnic->fw_grp_ids);
2868 vnic->fw_grp_ids = NULL;
2869
2870 kfree(vnic->uc_list);
2871 vnic->uc_list = NULL;
2872
2873 if (vnic->mc_list) {
2874 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2875 vnic->mc_list, vnic->mc_list_mapping);
2876 vnic->mc_list = NULL;
2877 }
2878
2879 if (vnic->rss_table) {
2880 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2881 vnic->rss_table,
2882 vnic->rss_table_dma_addr);
2883 vnic->rss_table = NULL;
2884 }
2885
2886 vnic->rss_hash_key = NULL;
2887 vnic->flags = 0;
2888 }
2889}
2890
2891static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2892{
2893 int i, rc = 0, size;
2894 struct bnxt_vnic_info *vnic;
2895 struct pci_dev *pdev = bp->pdev;
2896 int max_rings;
2897
2898 for (i = 0; i < bp->nr_vnics; i++) {
2899 vnic = &bp->vnic_info[i];
2900
2901 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2902 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2903
2904 if (mem_size > 0) {
2905 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2906 if (!vnic->uc_list) {
2907 rc = -ENOMEM;
2908 goto out;
2909 }
2910 }
2911 }
2912
2913 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2914 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2915 vnic->mc_list =
2916 dma_alloc_coherent(&pdev->dev,
2917 vnic->mc_list_size,
2918 &vnic->mc_list_mapping,
2919 GFP_KERNEL);
2920 if (!vnic->mc_list) {
2921 rc = -ENOMEM;
2922 goto out;
2923 }
2924 }
2925
2926 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2927 max_rings = bp->rx_nr_rings;
2928 else
2929 max_rings = 1;
2930
2931 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2932 if (!vnic->fw_grp_ids) {
2933 rc = -ENOMEM;
2934 goto out;
2935 }
2936
ae10ae74
MC		 2937 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2938 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2939 continue;
2940
c0c050c5
MC		 2941 /* Allocate rss table and hash key */
2942 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2943 &vnic->rss_table_dma_addr,
2944 GFP_KERNEL);
2945 if (!vnic->rss_table) {
2946 rc = -ENOMEM;
2947 goto out;
2948 }
2949
2950 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2951
2952 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2953 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2954 }
2955 return 0;
2956
2957out:
2958 return rc;
2959}
2960
2961static void bnxt_free_hwrm_resources(struct bnxt *bp)
2962{
2963 struct pci_dev *pdev = bp->pdev;
2964
2965 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2966 bp->hwrm_cmd_resp_dma_addr);
2967
2968 bp->hwrm_cmd_resp_addr = NULL;
2969 if (bp->hwrm_dbg_resp_addr) {
2970 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2971 bp->hwrm_dbg_resp_addr,
2972 bp->hwrm_dbg_resp_dma_addr);
2973
2974 bp->hwrm_dbg_resp_addr = NULL;
2975 }
2976}
2977
2978static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2979{
2980 struct pci_dev *pdev = bp->pdev;
2981
2982 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2983 &bp->hwrm_cmd_resp_dma_addr,
2984 GFP_KERNEL);
2985 if (!bp->hwrm_cmd_resp_addr)
2986 return -ENOMEM;
2987 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2988 HWRM_DBG_REG_BUF_SIZE,
2989 &bp->hwrm_dbg_resp_dma_addr,
2990 GFP_KERNEL);
2991 if (!bp->hwrm_dbg_resp_addr)
2992 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2993
2994 return 0;
2995}
2996
e605db80
DK		 2997static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
2998{
2999 if (bp->hwrm_short_cmd_req_addr) {
3000 struct pci_dev *pdev = bp->pdev;
3001
3002 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3003 bp->hwrm_short_cmd_req_addr,
3004 bp->hwrm_short_cmd_req_dma_addr);
3005 bp->hwrm_short_cmd_req_addr = NULL;
3006 }
3007}
3008
3009static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3010{
3011 struct pci_dev *pdev = bp->pdev;
3012
3013 bp->hwrm_short_cmd_req_addr =
3014 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3015 &bp->hwrm_short_cmd_req_dma_addr,
3016 GFP_KERNEL);
3017 if (!bp->hwrm_short_cmd_req_addr)
3018 return -ENOMEM;
3019
3020 return 0;
3021}
3022
c0c050c5
MC		 3023static void bnxt_free_stats(struct bnxt *bp)
3024{
3025 u32 size, i;
3026 struct pci_dev *pdev = bp->pdev;
3027
3bdf56c4
MC		 3028 if (bp->hw_rx_port_stats) {
3029 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3030 bp->hw_rx_port_stats,
3031 bp->hw_rx_port_stats_map);
3032 bp->hw_rx_port_stats = NULL;
3033 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3034 }
3035
c0c050c5
MC		 3036 if (!bp->bnapi)
3037 return;
3038
3039 size = sizeof(struct ctx_hw_stats);
3040
3041 for (i = 0; i < bp->cp_nr_rings; i++) {
3042 struct bnxt_napi *bnapi = bp->bnapi[i];
3043 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3044
3045 if (cpr->hw_stats) {
3046 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3047 cpr->hw_stats_map);
3048 cpr->hw_stats = NULL;
3049 }
3050 }
3051}
3052
3053static int bnxt_alloc_stats(struct bnxt *bp)
3054{
3055 u32 size, i;
3056 struct pci_dev *pdev = bp->pdev;
3057
3058 size = sizeof(struct ctx_hw_stats);
3059
3060 for (i = 0; i < bp->cp_nr_rings; i++) {
3061 struct bnxt_napi *bnapi = bp->bnapi[i];
3062 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3063
3064 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3065 &cpr->hw_stats_map,
3066 GFP_KERNEL);
3067 if (!cpr->hw_stats)
3068 return -ENOMEM;
3069
3070 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3071 }
3bdf56c4 3072
3e8060fa 3073 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3bdf56c4
MC		 3074 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3075 sizeof(struct tx_port_stats) + 1024;
3076
3077 bp->hw_rx_port_stats =
3078 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3079 &bp->hw_rx_port_stats_map,
3080 GFP_KERNEL);
3081 if (!bp->hw_rx_port_stats)
3082 return -ENOMEM;
3083
3084 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3085 512;
3086 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3087 sizeof(struct rx_port_stats) + 512;
3088 bp->flags |= BNXT_FLAG_PORT_STATS;
3089 }
c0c050c5
MC		 3090 return 0;
3091}
3092
3093static void bnxt_clear_ring_indices(struct bnxt *bp)
3094{
3095 int i;
3096
3097 if (!bp->bnapi)
3098 return;
3099
3100 for (i = 0; i < bp->cp_nr_rings; i++) {
3101 struct bnxt_napi *bnapi = bp->bnapi[i];
3102 struct bnxt_cp_ring_info *cpr;
3103 struct bnxt_rx_ring_info *rxr;
3104 struct bnxt_tx_ring_info *txr;
3105
3106 if (!bnapi)
3107 continue;
3108
3109 cpr = &bnapi->cp_ring;
3110 cpr->cp_raw_cons = 0;
3111
b6ab4b01 3112 txr = bnapi->tx_ring;
3b2b7d9d
MC		 3113 if (txr) {
3114 txr->tx_prod = 0;
3115 txr->tx_cons = 0;
3116 }
c0c050c5 3117
b6ab4b01 3118 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 3119 if (rxr) {
3120 rxr->rx_prod = 0;
3121 rxr->rx_agg_prod = 0;
3122 rxr->rx_sw_agg_prod = 0;
376a5b86 3123 rxr->rx_next_cons = 0;
3b2b7d9d 3124 }
c0c050c5
MC		 3125 }
3126}
3127
3128static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3129{
3130#ifdef CONFIG_RFS_ACCEL
3131 int i;
3132
3133 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3134 * safe to delete the hash table.
3135 */
3136 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3137 struct hlist_head *head;
3138 struct hlist_node *tmp;
3139 struct bnxt_ntuple_filter *fltr;
3140
3141 head = &bp->ntp_fltr_hash_tbl[i];
3142 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3143 hlist_del(&fltr->hash);
3144 kfree(fltr);
3145 }
3146 }
3147 if (irq_reinit) {
3148 kfree(bp->ntp_fltr_bmap);
3149 bp->ntp_fltr_bmap = NULL;
3150 }
3151 bp->ntp_fltr_count = 0;
3152#endif
3153}
3154
3155static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3156{
3157#ifdef CONFIG_RFS_ACCEL
3158 int i, rc = 0;
3159
3160 if (!(bp->flags & BNXT_FLAG_RFS))
3161 return 0;
3162
3163 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3164 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3165
3166 bp->ntp_fltr_count = 0;
ac45bd93
DC		 3167 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3168 sizeof(long),
c0c050c5
MC		 3169 GFP_KERNEL);
3170
3171 if (!bp->ntp_fltr_bmap)
3172 rc = -ENOMEM;
3173
3174 return rc;
3175#else
3176 return 0;
3177#endif
3178}
3179
3180static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3181{
3182 bnxt_free_vnic_attributes(bp);
3183 bnxt_free_tx_rings(bp);
3184 bnxt_free_rx_rings(bp);
3185 bnxt_free_cp_rings(bp);
3186 bnxt_free_ntp_fltrs(bp, irq_re_init);
3187 if (irq_re_init) {
3188 bnxt_free_stats(bp);
3189 bnxt_free_ring_grps(bp);
3190 bnxt_free_vnics(bp);
a960dec9
MC		 3191 kfree(bp->tx_ring_map);
3192 bp->tx_ring_map = NULL;
b6ab4b01
MC		 3193 kfree(bp->tx_ring);
3194 bp->tx_ring = NULL;
3195 kfree(bp->rx_ring);
3196 bp->rx_ring = NULL;
c0c050c5
MC		 3197 kfree(bp->bnapi);
3198 bp->bnapi = NULL;
3199 } else {
3200 bnxt_clear_ring_indices(bp);
3201 }
3202}
3203
3204static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3205{
01657bcd 3206 int i, j, rc, size, arr_size;
c0c050c5
MC		 3207 void *bnapi;
3208
3209 if (irq_re_init) {
3210 /* Allocate bnapi mem pointer array and mem block for
3211 * all queues
3212 */
3213 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3214 bp->cp_nr_rings);
3215 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3216 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3217 if (!bnapi)
3218 return -ENOMEM;
3219
3220 bp->bnapi = bnapi;
3221 bnapi += arr_size;
3222 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3223 bp->bnapi[i] = bnapi;
3224 bp->bnapi[i]->index = i;
3225 bp->bnapi[i]->bp = bp;
3226 }
3227
b6ab4b01
MC		 3228 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3229 sizeof(struct bnxt_rx_ring_info),
3230 GFP_KERNEL);
3231 if (!bp->rx_ring)
3232 return -ENOMEM;
3233
3234 for (i = 0; i < bp->rx_nr_rings; i++) {
3235 bp->rx_ring[i].bnapi = bp->bnapi[i];
3236 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3237 }
3238
3239 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3240 sizeof(struct bnxt_tx_ring_info),
3241 GFP_KERNEL);
3242 if (!bp->tx_ring)
3243 return -ENOMEM;
3244
a960dec9
MC		 3245 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3246 GFP_KERNEL);
3247
3248 if (!bp->tx_ring_map)
3249 return -ENOMEM;
3250
01657bcd
MC		 3251 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3252 j = 0;
3253 else
3254 j = bp->rx_nr_rings;
3255
3256 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3257 bp->tx_ring[i].bnapi = bp->bnapi[j];
3258 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
5f449249 3259 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
38413406 3260 if (i >= bp->tx_nr_rings_xdp) {
5f449249
MC		 3261 bp->tx_ring[i].txq_index = i -
3262 bp->tx_nr_rings_xdp;
38413406
MC		 3263 bp->bnapi[j]->tx_int = bnxt_tx_int;
3264 } else {
fa3e93e8 3265 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
38413406
MC		 3266 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3267 }
b6ab4b01
MC		 3268 }
3269
c0c050c5
MC		 3270 rc = bnxt_alloc_stats(bp);
3271 if (rc)
3272 goto alloc_mem_err;
3273
3274 rc = bnxt_alloc_ntp_fltrs(bp);
3275 if (rc)
3276 goto alloc_mem_err;
3277
3278 rc = bnxt_alloc_vnics(bp);
3279 if (rc)
3280 goto alloc_mem_err;
3281 }
3282
3283 bnxt_init_ring_struct(bp);
3284
3285 rc = bnxt_alloc_rx_rings(bp);
3286 if (rc)
3287 goto alloc_mem_err;
3288
3289 rc = bnxt_alloc_tx_rings(bp);
3290 if (rc)
3291 goto alloc_mem_err;
3292
3293 rc = bnxt_alloc_cp_rings(bp);
3294 if (rc)
3295 goto alloc_mem_err;
3296
3297 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3298 BNXT_VNIC_UCAST_FLAG;
3299 rc = bnxt_alloc_vnic_attributes(bp);
3300 if (rc)
3301 goto alloc_mem_err;
3302 return 0;
3303
3304alloc_mem_err:
3305 bnxt_free_mem(bp, true);
3306 return rc;
3307}
3308
9d8bc097
MC		 3309static void bnxt_disable_int(struct bnxt *bp)
3310{
3311 int i;
3312
3313 if (!bp->bnapi)
3314 return;
3315
3316 for (i = 0; i < bp->cp_nr_rings; i++) {
3317 struct bnxt_napi *bnapi = bp->bnapi[i];
3318 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
daf1f1e7 3319 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
9d8bc097 3320
daf1f1e7
MC		 3321 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3322 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
9d8bc097
MC		 3323 }
3324}
3325
3326static void bnxt_disable_int_sync(struct bnxt *bp)
3327{
3328 int i;
3329
3330 atomic_inc(&bp->intr_sem);
3331
3332 bnxt_disable_int(bp);
3333 for (i = 0; i < bp->cp_nr_rings; i++)
3334 synchronize_irq(bp->irq_tbl[i].vector);
3335}
3336
3337static void bnxt_enable_int(struct bnxt *bp)
3338{
3339 int i;
3340
3341 atomic_set(&bp->intr_sem, 0);
3342 for (i = 0; i < bp->cp_nr_rings; i++) {
3343 struct bnxt_napi *bnapi = bp->bnapi[i];
3344 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3345
3346 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3347 }
3348}
3349
c0c050c5
MC		 3350void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3351 u16 cmpl_ring, u16 target_id)
3352{
a8643e16 3353 struct input *req = request;
c0c050c5 3354
a8643e16
MC		 3355 req->req_type = cpu_to_le16(req_type);
3356 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3357 req->target_id = cpu_to_le16(target_id);
c0c050c5
MC		 3358 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3359}
3360
fbfbc485
MC		 3361static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3362 int timeout, bool silent)
c0c050c5 3363{
a11fa2be 3364 int i, intr_process, rc, tmo_count;
a8643e16 3365 struct input *req = msg;
c0c050c5
MC		 3366 u32 *data = msg;
3367 __le32 *resp_len, *valid;
3368 u16 cp_ring_id, len = 0;
3369 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
e605db80 3370 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
c0c050c5 3371
a8643e16 3372 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
c0c050c5 3373 memset(resp, 0, PAGE_SIZE);
a8643e16 3374 cp_ring_id = le16_to_cpu(req->cmpl_ring);
c0c050c5
MC		 3375 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3376
e605db80
DK		 3377 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
3378 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3379 struct hwrm_short_input short_input = {0};
3380
3381 memcpy(short_cmd_req, req, msg_len);
3382 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3383 msg_len);
3384
3385 short_input.req_type = req->req_type;
3386 short_input.signature =
3387 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3388 short_input.size = cpu_to_le16(msg_len);
3389 short_input.req_addr =
3390 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3391
3392 data = (u32 *)&short_input;
3393 msg_len = sizeof(short_input);
3394
3395 /* Sync memory write before updating doorbell */
3396 wmb();
3397
3398 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3399 }
3400
c0c050c5
MC		 3401 /* Write request msg to hwrm channel */
3402 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3403
e605db80 3404 for (i = msg_len; i < max_req_len; i += 4)
d79979a1
MC		 3405 writel(0, bp->bar0 + i);
3406
c0c050c5
MC		 3407 /* currently supports only one outstanding message */
3408 if (intr_process)
a8643e16 3409 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
c0c050c5
MC		 3410
3411 /* Ring channel doorbell */
3412 writel(1, bp->bar0 + 0x100);
3413
ff4fe81d
MC		 3414 if (!timeout)
3415 timeout = DFLT_HWRM_CMD_TIMEOUT;
3416
c0c050c5 3417 i = 0;
a11fa2be 3418 tmo_count = timeout * 40;
c0c050c5
MC		 3419 if (intr_process) {
3420 /* Wait until hwrm response cmpl interrupt is processed */
3421 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
a11fa2be
MC		 3422 i++ < tmo_count) {
3423 usleep_range(25, 40);
c0c050c5
MC		 3424 }
3425
3426 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3427 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
a8643e16 3428 le16_to_cpu(req->req_type));
c0c050c5
MC		 3429 return -1;
3430 }
3431 } else {
3432 /* Check if response len is updated */
3433 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
a11fa2be 3434 for (i = 0; i < tmo_count; i++) {
c0c050c5
MC		 3435 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3436 HWRM_RESP_LEN_SFT;
3437 if (len)
3438 break;
a11fa2be 3439 usleep_range(25, 40);
c0c050c5
MC		 3440 }
3441
a11fa2be 3442 if (i >= tmo_count) {
c0c050c5 3443 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
a8643e16 3444 timeout, le16_to_cpu(req->req_type),
8578d6c1 3445 le16_to_cpu(req->seq_id), len);
c0c050c5
MC		 3446 return -1;
3447 }
3448
3449 /* Last word of resp contains valid bit */
3450 valid = bp->hwrm_cmd_resp_addr + len - 4;
a11fa2be 3451 for (i = 0; i < 5; i++) {
c0c050c5
MC		 3452 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3453 break;
a11fa2be 3454 udelay(1);
c0c050c5
MC		 3455 }
3456
a11fa2be 3457 if (i >= 5) {
c0c050c5 3458 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
a8643e16
MC		 3459 timeout, le16_to_cpu(req->req_type),
3460 le16_to_cpu(req->seq_id), len, *valid);
c0c050c5
MC		 3461 return -1;
3462 }
3463 }
3464
3465 rc = le16_to_cpu(resp->error_code);
fbfbc485 3466 if (rc && !silent)
c0c050c5
MC		 3467 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3468 le16_to_cpu(resp->req_type),
3469 le16_to_cpu(resp->seq_id), rc);
fbfbc485
MC		 3470 return rc;
3471}
3472
3473int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3474{
3475 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
c0c050c5
MC		 3476}
3477
cc72f3b1
MC		 3478int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3479 int timeout)
3480{
3481 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3482}
3483
c0c050c5
MC		 3484int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3485{
3486 int rc;
3487
3488 mutex_lock(&bp->hwrm_cmd_lock);
3489 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3490 mutex_unlock(&bp->hwrm_cmd_lock);
3491 return rc;
3492}
3493
90e20921
MC		 3494int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3495 int timeout)
3496{
3497 int rc;
3498
3499 mutex_lock(&bp->hwrm_cmd_lock);
3500 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3501 mutex_unlock(&bp->hwrm_cmd_lock);
3502 return rc;
3503}
3504
a1653b13
MC		 3505int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3506 int bmap_size)
c0c050c5
MC		 3507{
3508 struct hwrm_func_drv_rgtr_input req = {0};
25be8623
MC		 3509 DECLARE_BITMAP(async_events_bmap, 256);
3510 u32 *events = (u32 *)async_events_bmap;
a1653b13 3511 int i;
c0c050c5
MC		 3512
3513 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3514
3515 req.enables =
a1653b13 3516 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
c0c050c5 3517
25be8623
MC		 3518 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3519 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3520 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3521
a1653b13
MC		 3522 if (bmap && bmap_size) {
3523 for (i = 0; i < bmap_size; i++) {
3524 if (test_bit(i, bmap))
3525 __set_bit(i, async_events_bmap);
3526 }
3527 }
3528
25be8623
MC		 3529 for (i = 0; i < 8; i++)
3530 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3531
a1653b13
MC		 3532 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3533}
3534
3535static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3536{
3537 struct hwrm_func_drv_rgtr_input req = {0};
3538
3539 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3540
3541 req.enables =
3542 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3543 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3544
11f15ed3 3545 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
c0c050c5
MC		 3546 req.ver_maj = DRV_VER_MAJ;
3547 req.ver_min = DRV_VER_MIN;
3548 req.ver_upd = DRV_VER_UPD;
3549
3550 if (BNXT_PF(bp)) {
9b0436c3 3551 u32 data[8];
a1653b13 3552 int i;
c0c050c5 3553
9b0436c3
MC		 3554 memset(data, 0, sizeof(data));
3555 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3556 u16 cmd = bnxt_vf_req_snif[i];
3557 unsigned int bit, idx;
3558
3559 idx = cmd / 32;
3560 bit = cmd % 32;
3561 data[idx] |= 1 << bit;
3562 }
c0c050c5 3563
de68f5de
MC		 3564 for (i = 0; i < 8; i++)
3565 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3566
c0c050c5
MC		 3567 req.enables |=
3568 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3569 }
3570
3571 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3572}
3573
be58a0da
JH		 3574static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3575{
3576 struct hwrm_func_drv_unrgtr_input req = {0};
3577
3578 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3579 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3580}
3581
c0c050c5
MC		 3582static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3583{
3584 u32 rc = 0;
3585 struct hwrm_tunnel_dst_port_free_input req = {0};
3586
3587 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3588 req.tunnel_type = tunnel_type;
3589
3590 switch (tunnel_type) {
3591 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3592 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3593 break;
3594 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3595 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3596 break;
3597 default:
3598 break;
3599 }
3600
3601 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3602 if (rc)
3603 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3604 rc);
3605 return rc;
3606}
3607
3608static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3609 u8 tunnel_type)
3610{
3611 u32 rc = 0;
3612 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3613 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3614
3615 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3616
3617 req.tunnel_type = tunnel_type;
3618 req.tunnel_dst_port_val = port;
3619
3620 mutex_lock(&bp->hwrm_cmd_lock);
3621 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3622 if (rc) {
3623 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3624 rc);
3625 goto err_out;
3626 }
3627
57aac71b
CJ		 3628 switch (tunnel_type) {
3629 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
c0c050c5 3630 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3631 break;
3632 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
c0c050c5 3633 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3634 break;
3635 default:
3636 break;
3637 }
3638
c0c050c5
MC		 3639err_out:
3640 mutex_unlock(&bp->hwrm_cmd_lock);
3641 return rc;
3642}
3643
3644static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3645{
3646 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3647 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3648
3649 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 3650 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 3651
3652 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3653 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3654 req.mask = cpu_to_le32(vnic->rx_mask);
3655 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3656}
3657
3658#ifdef CONFIG_RFS_ACCEL
3659static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3660 struct bnxt_ntuple_filter *fltr)
3661{
3662 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3663
3664 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3665 req.ntuple_filter_id = fltr->filter_id;
3666 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3667}
3668
3669#define BNXT_NTP_FLTR_FLAGS \
3670 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3671 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3672 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3673 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3674 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3675 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3676 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3677 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3678 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3679 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3680 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3681 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3682 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 3683 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5 3684
61aad724
MC		 3685#define BNXT_NTP_TUNNEL_FLTR_FLAG \
3686 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3687
c0c050c5
MC		 3688static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3689 struct bnxt_ntuple_filter *fltr)
3690{
3691 int rc = 0;
3692 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3693 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3694 bp->hwrm_cmd_resp_addr;
3695 struct flow_keys *keys = &fltr->fkeys;
3696 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3697
3698 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
a54c4d74 3699 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
c0c050c5
MC		 3700
3701 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3702
3703 req.ethertype = htons(ETH_P_IP);
3704 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 3705 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 3706 req.ip_protocol = keys->basic.ip_proto;
3707
dda0e746
MC		 3708 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3709 int i;
3710
3711 req.ethertype = htons(ETH_P_IPV6);
3712 req.ip_addr_type =
3713 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3714 *(struct in6_addr *)&req.src_ipaddr[0] =
3715 keys->addrs.v6addrs.src;
3716 *(struct in6_addr *)&req.dst_ipaddr[0] =
3717 keys->addrs.v6addrs.dst;
3718 for (i = 0; i < 4; i++) {
3719 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3720 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3721 }
3722 } else {
3723 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3724 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3725 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3726 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3727 }
61aad724
MC		 3728 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3729 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3730 req.tunnel_type =
3731 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3732 }
c0c050c5
MC		 3733
3734 req.src_port = keys->ports.src;
3735 req.src_port_mask = cpu_to_be16(0xffff);
3736 req.dst_port = keys->ports.dst;
3737 req.dst_port_mask = cpu_to_be16(0xffff);
3738
c193554e 3739 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 3740 mutex_lock(&bp->hwrm_cmd_lock);
3741 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3742 if (!rc)
3743 fltr->filter_id = resp->ntuple_filter_id;
3744 mutex_unlock(&bp->hwrm_cmd_lock);
3745 return rc;
3746}
3747#endif
3748
3749static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3750 u8 *mac_addr)
3751{
3752 u32 rc = 0;
3753 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3754 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3755
3756 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
dc52c6c7
PS		 3757 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3758 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3759 req.flags |=
3760 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 3761 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 3762 req.enables =
3763 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 3764 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 3765 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3766 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3767 req.l2_addr_mask[0] = 0xff;
3768 req.l2_addr_mask[1] = 0xff;
3769 req.l2_addr_mask[2] = 0xff;
3770 req.l2_addr_mask[3] = 0xff;
3771 req.l2_addr_mask[4] = 0xff;
3772 req.l2_addr_mask[5] = 0xff;
3773
3774 mutex_lock(&bp->hwrm_cmd_lock);
3775 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3776 if (!rc)
3777 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3778 resp->l2_filter_id;
3779 mutex_unlock(&bp->hwrm_cmd_lock);
3780 return rc;
3781}
3782
3783static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3784{
3785 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3786 int rc = 0;
3787
3788 /* Any associated ntuple filters will also be cleared by firmware. */
3789 mutex_lock(&bp->hwrm_cmd_lock);
3790 for (i = 0; i < num_of_vnics; i++) {
3791 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3792
3793 for (j = 0; j < vnic->uc_filter_count; j++) {
3794 struct hwrm_cfa_l2_filter_free_input req = {0};
3795
3796 bnxt_hwrm_cmd_hdr_init(bp, &req,
3797 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3798
3799 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3800
3801 rc = _hwrm_send_message(bp, &req, sizeof(req),
3802 HWRM_CMD_TIMEOUT);
3803 }
3804 vnic->uc_filter_count = 0;
3805 }
3806 mutex_unlock(&bp->hwrm_cmd_lock);
3807
3808 return rc;
3809}
3810
3811static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3812{
3813 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3814 struct hwrm_vnic_tpa_cfg_input req = {0};
3815
3816 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3817
3818 if (tpa_flags) {
3819 u16 mss = bp->dev->mtu - 40;
3820 u32 nsegs, n, segs = 0, flags;
3821
3822 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3823 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3824 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3825 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3826 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3827 if (tpa_flags & BNXT_FLAG_GRO)
3828 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3829
3830 req.flags = cpu_to_le32(flags);
3831
3832 req.enables =
3833 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 3834 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3835 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 3836
3837 /* Number of segs are log2 units, and first packet is not
3838 * included as part of this units.
3839 */
2839f28b
MC		 3840 if (mss <= BNXT_RX_PAGE_SIZE) {
3841 n = BNXT_RX_PAGE_SIZE / mss;
c0c050c5
MC		 3842 nsegs = (MAX_SKB_FRAGS - 1) * n;
3843 } else {
2839f28b
MC		 3844 n = mss / BNXT_RX_PAGE_SIZE;
3845 if (mss & (BNXT_RX_PAGE_SIZE - 1))
c0c050c5
MC		 3846 n++;
3847 nsegs = (MAX_SKB_FRAGS - n) / n;
3848 }
3849
3850 segs = ilog2(nsegs);
3851 req.max_agg_segs = cpu_to_le16(segs);
3852 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 3853
3854 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 3855 }
3856 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3857
3858 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3859}
3860
3861static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3862{
3863 u32 i, j, max_rings;
3864 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3865 struct hwrm_vnic_rss_cfg_input req = {0};
3866
94ce9caa 3867 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
c0c050c5
MC		 3868 return 0;
3869
3870 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3871 if (set_rss) {
87da7f79 3872 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
dc52c6c7
PS		 3873 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3874 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3875 max_rings = bp->rx_nr_rings - 1;
3876 else
3877 max_rings = bp->rx_nr_rings;
3878 } else {
c0c050c5 3879 max_rings = 1;
dc52c6c7 3880 }
c0c050c5
MC		 3881
3882 /* Fill the RSS indirection table with ring group ids */
3883 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3884 if (j == max_rings)
3885 j = 0;
3886 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3887 }
3888
3889 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3890 req.hash_key_tbl_addr =
3891 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3892 }
94ce9caa 3893 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
c0c050c5
MC		 3894 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3895}
3896
3897static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3898{
3899 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3900 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3901
3902 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3903 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3904 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3905 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3906 req.enables =
3907 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3908 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3909 /* thresholds not implemented in firmware yet */
3910 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3911 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3912 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3913 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3914}
3915
94ce9caa
PS		 3916static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3917 u16 ctx_idx)
c0c050c5
MC		 3918{
3919 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3920
3921 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3922 req.rss_cos_lb_ctx_id =
94ce9caa 3923 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
c0c050c5
MC		 3924
3925 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
94ce9caa 3926 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
c0c050c5
MC		 3927}
3928
3929static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3930{
94ce9caa 3931 int i, j;
c0c050c5
MC		 3932
3933 for (i = 0; i < bp->nr_vnics; i++) {
3934 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3935
94ce9caa
PS		 3936 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3937 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3938 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3939 }
c0c050c5
MC		 3940 }
3941 bp->rsscos_nr_ctxs = 0;
3942}
3943
94ce9caa 3944static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
c0c050c5
MC		 3945{
3946 int rc;
3947 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3948 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3949 bp->hwrm_cmd_resp_addr;
3950
3951 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3952 -1);
3953
3954 mutex_lock(&bp->hwrm_cmd_lock);
3955 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3956 if (!rc)
94ce9caa 3957 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
c0c050c5
MC		 3958 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3959 mutex_unlock(&bp->hwrm_cmd_lock);
3960
3961 return rc;
3962}
3963
a588e458 3964int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
c0c050c5 3965{
b81a90d3 3966 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 3967 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3968 struct hwrm_vnic_cfg_input req = {0};
cf6645f8 3969 u16 def_vlan = 0;
c0c050c5
MC		 3970
3971 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
dc52c6c7
PS		 3972
3973 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
c0c050c5 3974 /* Only RSS support for now TBD: COS & LB */
dc52c6c7
PS		 3975 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3976 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3977 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3978 VNIC_CFG_REQ_ENABLES_MRU);
ae10ae74
MC		 3979 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
3980 req.rss_rule =
3981 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
3982 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3983 VNIC_CFG_REQ_ENABLES_MRU);
3984 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
dc52c6c7
PS		 3985 } else {
3986 req.rss_rule = cpu_to_le16(0xffff);
3987 }
94ce9caa 3988
dc52c6c7
PS		 3989 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3990 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
94ce9caa
PS		 3991 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3992 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3993 } else {
3994 req.cos_rule = cpu_to_le16(0xffff);
3995 }
3996
c0c050c5 3997 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 3998 ring = 0;
c0c050c5 3999 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 4000 ring = vnic_id - 1;
76595193
PS		 4001 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4002 ring = bp->rx_nr_rings - 1;
c0c050c5 4003
b81a90d3 4004 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5
MC		 4005 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4006 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4007
4008 req.lb_rule = cpu_to_le16(0xffff);
4009 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4010 VLAN_HLEN);
4011
cf6645f8
MC		 4012#ifdef CONFIG_BNXT_SRIOV
4013 if (BNXT_VF(bp))
4014 def_vlan = bp->vf.vlan;
4015#endif
4016 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
c0c050c5 4017 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
a588e458
MC		 4018 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4019 req.flags |=
4020 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
c0c050c5
MC		 4021
4022 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4023}
4024
4025static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4026{
4027 u32 rc = 0;
4028
4029 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4030 struct hwrm_vnic_free_input req = {0};
4031
4032 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4033 req.vnic_id =
4034 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4035
4036 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4037 if (rc)
4038 return rc;
4039 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4040 }
4041 return rc;
4042}
4043
4044static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4045{
4046 u16 i;
4047
4048 for (i = 0; i < bp->nr_vnics; i++)
4049 bnxt_hwrm_vnic_free_one(bp, i);
4050}
4051
b81a90d3
MC		 4052static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4053 unsigned int start_rx_ring_idx,
4054 unsigned int nr_rings)
c0c050c5 4055{
b81a90d3
MC		 4056 int rc = 0;
4057 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 4058 struct hwrm_vnic_alloc_input req = {0};
4059 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4060
4061 /* map ring groups to this vnic */
b81a90d3
MC		 4062 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4063 grp_idx = bp->rx_ring[i].bnapi->index;
4064 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 4065 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 4066 j, nr_rings);
c0c050c5
MC		 4067 break;
4068 }
4069 bp->vnic_info[vnic_id].fw_grp_ids[j] =
b81a90d3 4070 bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 4071 }
4072
94ce9caa
PS		 4073 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4074 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 4075 if (vnic_id == 0)
4076 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4077
4078 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4079
4080 mutex_lock(&bp->hwrm_cmd_lock);
4081 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4082 if (!rc)
4083 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4084 mutex_unlock(&bp->hwrm_cmd_lock);
4085 return rc;
4086}
4087
8fdefd63
MC		 4088static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4089{
4090 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4091 struct hwrm_vnic_qcaps_input req = {0};
4092 int rc;
4093
4094 if (bp->hwrm_spec_code < 0x10600)
4095 return 0;
4096
4097 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4098 mutex_lock(&bp->hwrm_cmd_lock);
4099 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4100 if (!rc) {
4101 if (resp->flags &
4102 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4103 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4104 }
4105 mutex_unlock(&bp->hwrm_cmd_lock);
4106 return rc;
4107}
4108
c0c050c5
MC		 4109static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4110{
4111 u16 i;
4112 u32 rc = 0;
4113
4114 mutex_lock(&bp->hwrm_cmd_lock);
4115 for (i = 0; i < bp->rx_nr_rings; i++) {
4116 struct hwrm_ring_grp_alloc_input req = {0};
4117 struct hwrm_ring_grp_alloc_output *resp =
4118 bp->hwrm_cmd_resp_addr;
b81a90d3 4119 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 4120
4121 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4122
b81a90d3
MC		 4123 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4124 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4125 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4126 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 4127
4128 rc = _hwrm_send_message(bp, &req, sizeof(req),
4129 HWRM_CMD_TIMEOUT);
4130 if (rc)
4131 break;
4132
b81a90d3
MC		 4133 bp->grp_info[grp_idx].fw_grp_id =
4134 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 4135 }
4136 mutex_unlock(&bp->hwrm_cmd_lock);
4137 return rc;
4138}
4139
4140static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4141{
4142 u16 i;
4143 u32 rc = 0;
4144 struct hwrm_ring_grp_free_input req = {0};
4145
4146 if (!bp->grp_info)
4147 return 0;
4148
4149 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4150
4151 mutex_lock(&bp->hwrm_cmd_lock);
4152 for (i = 0; i < bp->cp_nr_rings; i++) {
4153 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4154 continue;
4155 req.ring_group_id =
4156 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4157
4158 rc = _hwrm_send_message(bp, &req, sizeof(req),
4159 HWRM_CMD_TIMEOUT);
4160 if (rc)
4161 break;
4162 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4163 }
4164 mutex_unlock(&bp->hwrm_cmd_lock);
4165 return rc;
4166}
4167
4168static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4169 struct bnxt_ring_struct *ring,
4170 u32 ring_type, u32 map_index,
4171 u32 stats_ctx_id)
4172{
4173 int rc = 0, err = 0;
4174 struct hwrm_ring_alloc_input req = {0};
4175 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4176 u16 ring_id;
4177
4178 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4179
4180 req.enables = 0;
4181 if (ring->nr_pages > 1) {
4182 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4183 /* Page size is in log2 units */
4184 req.page_size = BNXT_PAGE_SHIFT;
4185 req.page_tbl_depth = 1;
4186 } else {
4187 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
4188 }
4189 req.fbo = 0;
4190 /* Association of ring index with doorbell index and MSIX number */
4191 req.logical_id = cpu_to_le16(map_index);
4192
4193 switch (ring_type) {
4194 case HWRM_RING_ALLOC_TX:
4195 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4196 /* Association of transmit ring with completion ring */
4197 req.cmpl_ring_id =
4198 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
4199 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4200 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
4201 req.queue_id = cpu_to_le16(ring->queue_id);
4202 break;
4203 case HWRM_RING_ALLOC_RX:
4204 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4205 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4206 break;
4207 case HWRM_RING_ALLOC_AGG:
4208 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4209 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4210 break;
4211 case HWRM_RING_ALLOC_CMPL:
bac9a7e0 4212 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
c0c050c5
MC		 4213 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4214 if (bp->flags & BNXT_FLAG_USING_MSIX)
4215 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4216 break;
4217 default:
4218 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4219 ring_type);
4220 return -1;
4221 }
4222
4223 mutex_lock(&bp->hwrm_cmd_lock);
4224 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4225 err = le16_to_cpu(resp->error_code);
4226 ring_id = le16_to_cpu(resp->ring_id);
4227 mutex_unlock(&bp->hwrm_cmd_lock);
4228
4229 if (rc || err) {
4230 switch (ring_type) {
bac9a7e0 4231 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
c0c050c5
MC		 4232 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4233 rc, err);
4234 return -1;
4235
4236 case RING_FREE_REQ_RING_TYPE_RX:
4237 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4238 rc, err);
4239 return -1;
4240
4241 case RING_FREE_REQ_RING_TYPE_TX:
4242 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4243 rc, err);
4244 return -1;
4245
4246 default:
4247 netdev_err(bp->dev, "Invalid ring\n");
4248 return -1;
4249 }
4250 }
4251 ring->fw_ring_id = ring_id;
4252 return rc;
4253}
4254
486b5c22
MC		 4255static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4256{
4257 int rc;
4258
4259 if (BNXT_PF(bp)) {
4260 struct hwrm_func_cfg_input req = {0};
4261
4262 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4263 req.fid = cpu_to_le16(0xffff);
4264 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4265 req.async_event_cr = cpu_to_le16(idx);
4266 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4267 } else {
4268 struct hwrm_func_vf_cfg_input req = {0};
4269
4270 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4271 req.enables =
4272 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4273 req.async_event_cr = cpu_to_le16(idx);
4274 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4275 }
4276 return rc;
4277}
4278
c0c050c5
MC		 4279static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4280{
4281 int i, rc = 0;
4282
edd0c2cc
MC		 4283 for (i = 0; i < bp->cp_nr_rings; i++) {
4284 struct bnxt_napi *bnapi = bp->bnapi[i];
4285 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4286 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
c0c050c5 4287
33e52d88 4288 cpr->cp_doorbell = bp->bar1 + i * 0x80;
edd0c2cc
MC		 4289 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4290 INVALID_STATS_CTX_ID);
4291 if (rc)
4292 goto err_out;
edd0c2cc
MC		 4293 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4294 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
486b5c22
MC		 4295
4296 if (!i) {
4297 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4298 if (rc)
4299 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4300 }
c0c050c5
MC		 4301 }
4302
edd0c2cc 4303 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4304 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 4305 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 4306 u32 map_idx = txr->bnapi->index;
4307 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
c0c050c5 4308
b81a90d3
MC		 4309 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4310 map_idx, fw_stats_ctx);
edd0c2cc
MC		 4311 if (rc)
4312 goto err_out;
b81a90d3 4313 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 4314 }
4315
edd0c2cc 4316 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4317 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4318 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 4319 u32 map_idx = rxr->bnapi->index;
c0c050c5 4320
b81a90d3
MC		 4321 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4322 map_idx, INVALID_STATS_CTX_ID);
edd0c2cc
MC		 4323 if (rc)
4324 goto err_out;
b81a90d3 4325 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
edd0c2cc 4326 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
b81a90d3 4327 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 4328 }
4329
4330 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4331 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4332 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 4333 struct bnxt_ring_struct *ring =
4334 &rxr->rx_agg_ring_struct;
b81a90d3
MC		 4335 u32 grp_idx = rxr->bnapi->index;
4336 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5
MC		 4337
4338 rc = hwrm_ring_alloc_send_msg(bp, ring,
4339 HWRM_RING_ALLOC_AGG,
b81a90d3 4340 map_idx,
c0c050c5
MC		 4341 INVALID_STATS_CTX_ID);
4342 if (rc)
4343 goto err_out;
4344
b81a90d3 4345 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 4346 writel(DB_KEY_RX | rxr->rx_agg_prod,
4347 rxr->rx_agg_doorbell);
b81a90d3 4348 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 4349 }
4350 }
4351err_out:
4352 return rc;
4353}
4354
4355static int hwrm_ring_free_send_msg(struct bnxt *bp,
4356 struct bnxt_ring_struct *ring,
4357 u32 ring_type, int cmpl_ring_id)
4358{
4359 int rc;
4360 struct hwrm_ring_free_input req = {0};
4361 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4362 u16 error_code;
4363
74608fc9 4364 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 4365 req.ring_type = ring_type;
4366 req.ring_id = cpu_to_le16(ring->fw_ring_id);
4367
4368 mutex_lock(&bp->hwrm_cmd_lock);
4369 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4370 error_code = le16_to_cpu(resp->error_code);
4371 mutex_unlock(&bp->hwrm_cmd_lock);
4372
4373 if (rc || error_code) {
4374 switch (ring_type) {
bac9a7e0 4375 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
c0c050c5
MC		 4376 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4377 rc);
4378 return rc;
4379 case RING_FREE_REQ_RING_TYPE_RX:
4380 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4381 rc);
4382 return rc;
4383 case RING_FREE_REQ_RING_TYPE_TX:
4384 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4385 rc);
4386 return rc;
4387 default:
4388 netdev_err(bp->dev, "Invalid ring\n");
4389 return -1;
4390 }
4391 }
4392 return 0;
4393}
4394
edd0c2cc 4395static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 4396{
edd0c2cc 4397 int i;
c0c050c5
MC		 4398
4399 if (!bp->bnapi)
edd0c2cc 4400 return;
c0c050c5 4401
edd0c2cc 4402 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4403 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 4404 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 4405 u32 grp_idx = txr->bnapi->index;
4406 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4407
4408 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4409 hwrm_ring_free_send_msg(bp, ring,
4410 RING_FREE_REQ_RING_TYPE_TX,
4411 close_path ? cmpl_ring_id :
4412 INVALID_HW_RING_ID);
4413 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4414 }
4415 }
4416
edd0c2cc 4417 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4418 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4419 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3
MC		 4420 u32 grp_idx = rxr->bnapi->index;
4421 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4422
4423 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4424 hwrm_ring_free_send_msg(bp, ring,
4425 RING_FREE_REQ_RING_TYPE_RX,
4426 close_path ? cmpl_ring_id :
4427 INVALID_HW_RING_ID);
4428 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4429 bp->grp_info[grp_idx].rx_fw_ring_id =
4430 INVALID_HW_RING_ID;
c0c050c5
MC		 4431 }
4432 }
4433
edd0c2cc 4434 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4435 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4436 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3
MC		 4437 u32 grp_idx = rxr->bnapi->index;
4438 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4439
4440 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4441 hwrm_ring_free_send_msg(bp, ring,
4442 RING_FREE_REQ_RING_TYPE_RX,
4443 close_path ? cmpl_ring_id :
4444 INVALID_HW_RING_ID);
4445 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4446 bp->grp_info[grp_idx].agg_fw_ring_id =
4447 INVALID_HW_RING_ID;
c0c050c5
MC		 4448 }
4449 }
4450
9d8bc097
MC		 4451 /* The completion rings are about to be freed. After that the
4452 * IRQ doorbell will not work anymore. So we need to disable
4453 * IRQ here.
4454 */
4455 bnxt_disable_int_sync(bp);
4456
edd0c2cc
MC		 4457 for (i = 0; i < bp->cp_nr_rings; i++) {
4458 struct bnxt_napi *bnapi = bp->bnapi[i];
4459 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4460 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4461
4462 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4463 hwrm_ring_free_send_msg(bp, ring,
bac9a7e0 4464 RING_FREE_REQ_RING_TYPE_L2_CMPL,
edd0c2cc
MC		 4465 INVALID_HW_RING_ID);
4466 ring->fw_ring_id = INVALID_HW_RING_ID;
4467 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4468 }
4469 }
c0c050c5
MC		 4470}
4471
391be5c2
MC		 4472/* Caller must hold bp->hwrm_cmd_lock */
4473int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4474{
4475 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4476 struct hwrm_func_qcfg_input req = {0};
4477 int rc;
4478
4479 if (bp->hwrm_spec_code < 0x10601)
4480 return 0;
4481
4482 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4483 req.fid = cpu_to_le16(fid);
4484 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4485 if (!rc)
4486 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4487
4488 return rc;
4489}
4490
d1e7925e 4491static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
391be5c2
MC		 4492{
4493 struct hwrm_func_cfg_input req = {0};
4494 int rc;
4495
4496 if (bp->hwrm_spec_code < 0x10601)
4497 return 0;
4498
4499 if (BNXT_VF(bp))
4500 return 0;
4501
4502 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4503 req.fid = cpu_to_le16(0xffff);
4504 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4505 req.num_tx_rings = cpu_to_le16(*tx_rings);
4506 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4507 if (rc)
4508 return rc;
4509
4510 mutex_lock(&bp->hwrm_cmd_lock);
4511 rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4512 mutex_unlock(&bp->hwrm_cmd_lock);
98fdbe73
MC		 4513 if (!rc)
4514 bp->tx_reserved_rings = *tx_rings;
391be5c2
MC		 4515 return rc;
4516}
4517
98fdbe73
MC		 4518static int bnxt_hwrm_check_tx_rings(struct bnxt *bp, int tx_rings)
4519{
4520 struct hwrm_func_cfg_input req = {0};
4521 int rc;
4522
4523 if (bp->hwrm_spec_code < 0x10801)
4524 return 0;
4525
4526 if (BNXT_VF(bp))
4527 return 0;
4528
4529 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4530 req.fid = cpu_to_le16(0xffff);
4531 req.flags = cpu_to_le32(FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST);
4532 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4533 req.num_tx_rings = cpu_to_le16(tx_rings);
4534 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4535 if (rc)
4536 return -ENOMEM;
4537 return 0;
4538}
4539
f8503969 4540static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
bb053f52
MC		 4541 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4542{
f8503969
MC		 4543 u16 val, tmr, max, flags;
4544
4545 max = hw_coal->bufs_per_record * 128;
4546 if (hw_coal->budget)
4547 max = hw_coal->bufs_per_record * hw_coal->budget;
4548
4549 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4550 req->num_cmpl_aggr_int = cpu_to_le16(val);
b153cbc5
MC		 4551
4552 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4553 val = min_t(u16, val, 63);
f8503969
MC		 4554 req->num_cmpl_dma_aggr = cpu_to_le16(val);
4555
b153cbc5
MC		 4556 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4557 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
f8503969
MC		 4558 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4559
4560 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4561 tmr = max_t(u16, tmr, 1);
4562 req->int_lat_tmr_max = cpu_to_le16(tmr);
4563
4564 /* min timer set to 1/2 of interrupt timer */
4565 val = tmr / 2;
4566 req->int_lat_tmr_min = cpu_to_le16(val);
4567
4568 /* buf timer set to 1/4 of interrupt timer */
4569 val = max_t(u16, tmr / 4, 1);
4570 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4571
4572 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4573 tmr = max_t(u16, tmr, 1);
4574 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
4575
4576 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4577 if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4578 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
bb053f52 4579 req->flags = cpu_to_le16(flags);
bb053f52
MC		 4580}
4581
c0c050c5
MC		 4582int bnxt_hwrm_set_coal(struct bnxt *bp)
4583{
4584 int i, rc = 0;
dfc9c94a
MC		 4585 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4586 req_tx = {0}, *req;
c0c050c5 4587
dfc9c94a
MC		 4588 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4589 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4590 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4591 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
c0c050c5 4592
f8503969
MC		 4593 bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
4594 bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
c0c050c5
MC		 4595
4596 mutex_lock(&bp->hwrm_cmd_lock);
4597 for (i = 0; i < bp->cp_nr_rings; i++) {
dfc9c94a 4598 struct bnxt_napi *bnapi = bp->bnapi[i];
c0c050c5 4599
dfc9c94a
MC		 4600 req = &req_rx;
4601 if (!bnapi->rx_ring)
4602 req = &req_tx;
4603 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4604
4605 rc = _hwrm_send_message(bp, req, sizeof(*req),
c0c050c5
MC		 4606 HWRM_CMD_TIMEOUT);
4607 if (rc)
4608 break;
4609 }
4610 mutex_unlock(&bp->hwrm_cmd_lock);
4611 return rc;
4612}
4613
4614static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4615{
4616 int rc = 0, i;
4617 struct hwrm_stat_ctx_free_input req = {0};
4618
4619 if (!bp->bnapi)
4620 return 0;
4621
3e8060fa
PS		 4622 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4623 return 0;
4624
c0c050c5
MC		 4625 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4626
4627 mutex_lock(&bp->hwrm_cmd_lock);
4628 for (i = 0; i < bp->cp_nr_rings; i++) {
4629 struct bnxt_napi *bnapi = bp->bnapi[i];
4630 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4631
4632 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4633 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4634
4635 rc = _hwrm_send_message(bp, &req, sizeof(req),
4636 HWRM_CMD_TIMEOUT);
4637 if (rc)
4638 break;
4639
4640 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4641 }
4642 }
4643 mutex_unlock(&bp->hwrm_cmd_lock);
4644 return rc;
4645}
4646
4647static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4648{
4649 int rc = 0, i;
4650 struct hwrm_stat_ctx_alloc_input req = {0};
4651 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4652
3e8060fa
PS		 4653 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4654 return 0;
4655
c0c050c5
MC		 4656 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4657
51f30785 4658 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
c0c050c5
MC		 4659
4660 mutex_lock(&bp->hwrm_cmd_lock);
4661 for (i = 0; i < bp->cp_nr_rings; i++) {
4662 struct bnxt_napi *bnapi = bp->bnapi[i];
4663 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4664
4665 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4666
4667 rc = _hwrm_send_message(bp, &req, sizeof(req),
4668 HWRM_CMD_TIMEOUT);
4669 if (rc)
4670 break;
4671
4672 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4673
4674 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4675 }
4676 mutex_unlock(&bp->hwrm_cmd_lock);
89aa8445 4677 return rc;
c0c050c5
MC		 4678}
4679
cf6645f8
MC		 4680static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4681{
4682 struct hwrm_func_qcfg_input req = {0};
567b2abe 4683 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9315edca 4684 u16 flags;
cf6645f8
MC		 4685 int rc;
4686
4687 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4688 req.fid = cpu_to_le16(0xffff);
4689 mutex_lock(&bp->hwrm_cmd_lock);
4690 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4691 if (rc)
4692 goto func_qcfg_exit;
4693
4694#ifdef CONFIG_BNXT_SRIOV
4695 if (BNXT_VF(bp)) {
cf6645f8
MC		 4696 struct bnxt_vf_info *vf = &bp->vf;
4697
4698 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4699 }
4700#endif
9315edca
MC		 4701 flags = le16_to_cpu(resp->flags);
4702 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
4703 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
4704 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
4705 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
4706 bp->flags |= BNXT_FLAG_FW_DCBX_AGENT;
4707 }
4708 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
4709 bp->flags |= BNXT_FLAG_MULTI_HOST;
bc39f885 4710
567b2abe
SB		 4711 switch (resp->port_partition_type) {
4712 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4713 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4714 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4715 bp->port_partition_type = resp->port_partition_type;
4716 break;
4717 }
32e8239c
MC		 4718 if (bp->hwrm_spec_code < 0x10707 ||
4719 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
4720 bp->br_mode = BRIDGE_MODE_VEB;
4721 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
4722 bp->br_mode = BRIDGE_MODE_VEPA;
4723 else
4724 bp->br_mode = BRIDGE_MODE_UNDEF;
cf6645f8 4725
7eb9bb3a
MC		 4726 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
4727 if (!bp->max_mtu)
4728 bp->max_mtu = BNXT_MAX_MTU;
4729
cf6645f8
MC		 4730func_qcfg_exit:
4731 mutex_unlock(&bp->hwrm_cmd_lock);
4732 return rc;
4733}
4734
7b08f661 4735static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 4736{
4737 int rc = 0;
4738 struct hwrm_func_qcaps_input req = {0};
4739 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4740
4741 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4742 req.fid = cpu_to_le16(0xffff);
4743
4744 mutex_lock(&bp->hwrm_cmd_lock);
4745 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4746 if (rc)
4747 goto hwrm_func_qcaps_exit;
4748
e4060d30
MC		 4749 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4750 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4751 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4752 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4753
7cc5a20e
MC		 4754 bp->tx_push_thresh = 0;
4755 if (resp->flags &
4756 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4757 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4758
c0c050c5
MC		 4759 if (BNXT_PF(bp)) {
4760 struct bnxt_pf_info *pf = &bp->pf;
4761
4762 pf->fw_fid = le16_to_cpu(resp->fid);
4763 pf->port_id = le16_to_cpu(resp->port_id);
87027db1 4764 bp->dev->dev_port = pf->port_id;
11f15ed3 4765 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
c0c050c5
MC		 4766 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4767 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4768 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
c0c050c5 4769 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4770 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4771 if (!pf->max_hw_ring_grps)
4772 pf->max_hw_ring_grps = pf->max_tx_rings;
c0c050c5
MC		 4773 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4774 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4775 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4776 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4777 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4778 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4779 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4780 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4781 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4782 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4783 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
c1ef146a
MC		 4784 if (resp->flags &
4785 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED))
4786 bp->flags |= BNXT_FLAG_WOL_CAP;
c0c050c5 4787 } else {
379a80a1 4788#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 4789 struct bnxt_vf_info *vf = &bp->vf;
4790
4791 vf->fw_fid = le16_to_cpu(resp->fid);
c0c050c5
MC		 4792
4793 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4794 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4795 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4796 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4797 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4798 if (!vf->max_hw_ring_grps)
4799 vf->max_hw_ring_grps = vf->max_tx_rings;
c0c050c5
MC		 4800 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4801 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4802 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7cc5a20e
MC		 4803
4804 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
379a80a1 4805#endif
c0c050c5
MC		 4806 }
4807
c0c050c5
MC		 4808hwrm_func_qcaps_exit:
4809 mutex_unlock(&bp->hwrm_cmd_lock);
4810 return rc;
4811}
4812
4813static int bnxt_hwrm_func_reset(struct bnxt *bp)
4814{
4815 struct hwrm_func_reset_input req = {0};
4816
4817 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4818 req.enables = 0;
4819
4820 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4821}
4822
4823static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4824{
4825 int rc = 0;
4826 struct hwrm_queue_qportcfg_input req = {0};
4827 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4828 u8 i, *qptr;
4829
4830 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4831
4832 mutex_lock(&bp->hwrm_cmd_lock);
4833 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4834 if (rc)
4835 goto qportcfg_exit;
4836
4837 if (!resp->max_configurable_queues) {
4838 rc = -EINVAL;
4839 goto qportcfg_exit;
4840 }
4841 bp->max_tc = resp->max_configurable_queues;
87c374de 4842 bp->max_lltc = resp->max_configurable_lossless_queues;
c0c050c5
MC		 4843 if (bp->max_tc > BNXT_MAX_QUEUE)
4844 bp->max_tc = BNXT_MAX_QUEUE;
4845
441cabbb
MC		 4846 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4847 bp->max_tc = 1;
4848
87c374de
MC		 4849 if (bp->max_lltc > bp->max_tc)
4850 bp->max_lltc = bp->max_tc;
4851
c0c050c5
MC		 4852 qptr = &resp->queue_id0;
4853 for (i = 0; i < bp->max_tc; i++) {
4854 bp->q_info[i].queue_id = *qptr++;
4855 bp->q_info[i].queue_profile = *qptr++;
4856 }
4857
4858qportcfg_exit:
4859 mutex_unlock(&bp->hwrm_cmd_lock);
4860 return rc;
4861}
4862
4863static int bnxt_hwrm_ver_get(struct bnxt *bp)
4864{
4865 int rc;
4866 struct hwrm_ver_get_input req = {0};
4867 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
e605db80 4868 u32 dev_caps_cfg;
c0c050c5 4869
e6ef2699 4870 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
c0c050c5
MC		 4871 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4872 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4873 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4874 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4875 mutex_lock(&bp->hwrm_cmd_lock);
4876 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4877 if (rc)
4878 goto hwrm_ver_get_exit;
4879
4880 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4881
11f15ed3
MC		 4882 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4883 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
c193554e
MC		 4884 if (resp->hwrm_intf_maj < 1) {
4885 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
c0c050c5 4886 resp->hwrm_intf_maj, resp->hwrm_intf_min,
c193554e
MC		 4887 resp->hwrm_intf_upd);
4888 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5 4889 }
431aa1eb 4890 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
c0c050c5 4891 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
431aa1eb 4892 resp->hwrm_fw_rsvd);
c0c050c5 4893
ff4fe81d
MC		 4894 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4895 if (!bp->hwrm_cmd_timeout)
4896 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4897
e6ef2699
MC		 4898 if (resp->hwrm_intf_maj >= 1)
4899 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4900
659c805c 4901 bp->chip_num = le16_to_cpu(resp->chip_num);
3e8060fa
PS		 4902 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4903 !resp->chip_metal)
4904 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
659c805c 4905
e605db80
DK		 4906 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
4907 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
4908 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
4909 bp->flags |= BNXT_FLAG_SHORT_CMD;
4910
c0c050c5
MC		 4911hwrm_ver_get_exit:
4912 mutex_unlock(&bp->hwrm_cmd_lock);
4913 return rc;
4914}
4915
5ac67d8b
RS		 4916int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4917{
878786d9 4918#if IS_ENABLED(CONFIG_RTC_LIB)
5ac67d8b
RS		 4919 struct hwrm_fw_set_time_input req = {0};
4920 struct rtc_time tm;
4921 struct timeval tv;
4922
4923 if (bp->hwrm_spec_code < 0x10400)
4924 return -EOPNOTSUPP;
4925
4926 do_gettimeofday(&tv);
4927 rtc_time_to_tm(tv.tv_sec, &tm);
4928 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4929 req.year = cpu_to_le16(1900 + tm.tm_year);
4930 req.month = 1 + tm.tm_mon;
4931 req.day = tm.tm_mday;
4932 req.hour = tm.tm_hour;
4933 req.minute = tm.tm_min;
4934 req.second = tm.tm_sec;
4935 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
878786d9
RS		 4936#else
4937 return -EOPNOTSUPP;
4938#endif
5ac67d8b
RS		 4939}
4940
3bdf56c4
MC		 4941static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4942{
4943 int rc;
4944 struct bnxt_pf_info *pf = &bp->pf;
4945 struct hwrm_port_qstats_input req = {0};
4946
4947 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4948 return 0;
4949
4950 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4951 req.port_id = cpu_to_le16(pf->port_id);
4952 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4953 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4954 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4955 return rc;
4956}
4957
c0c050c5
MC		 4958static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4959{
4960 if (bp->vxlan_port_cnt) {
4961 bnxt_hwrm_tunnel_dst_port_free(
4962 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4963 }
4964 bp->vxlan_port_cnt = 0;
4965 if (bp->nge_port_cnt) {
4966 bnxt_hwrm_tunnel_dst_port_free(
4967 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4968 }
4969 bp->nge_port_cnt = 0;
4970}
4971
4972static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4973{
4974 int rc, i;
4975 u32 tpa_flags = 0;
4976
4977 if (set_tpa)
4978 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4979 for (i = 0; i < bp->nr_vnics; i++) {
4980 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4981 if (rc) {
4982 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
23e12c89 4983 i, rc);
c0c050c5
MC		 4984 return rc;
4985 }
4986 }
4987 return 0;
4988}
4989
4990static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4991{
4992 int i;
4993
4994 for (i = 0; i < bp->nr_vnics; i++)
4995 bnxt_hwrm_vnic_set_rss(bp, i, false);
4996}
4997
4998static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4999 bool irq_re_init)
5000{
5001 if (bp->vnic_info) {
5002 bnxt_hwrm_clear_vnic_filter(bp);
5003 /* clear all RSS setting before free vnic ctx */
5004 bnxt_hwrm_clear_vnic_rss(bp);
5005 bnxt_hwrm_vnic_ctx_free(bp);
5006 /* before free the vnic, undo the vnic tpa settings */
5007 if (bp->flags & BNXT_FLAG_TPA)
5008 bnxt_set_tpa(bp, false);
5009 bnxt_hwrm_vnic_free(bp);
5010 }
5011 bnxt_hwrm_ring_free(bp, close_path);
5012 bnxt_hwrm_ring_grp_free(bp);
5013 if (irq_re_init) {
5014 bnxt_hwrm_stat_ctx_free(bp);
5015 bnxt_hwrm_free_tunnel_ports(bp);
5016 }
5017}
5018
39d8ba2e
MC		 5019static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5020{
5021 struct hwrm_func_cfg_input req = {0};
5022 int rc;
5023
5024 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5025 req.fid = cpu_to_le16(0xffff);
5026 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5027 if (br_mode == BRIDGE_MODE_VEB)
5028 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5029 else if (br_mode == BRIDGE_MODE_VEPA)
5030 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5031 else
5032 return -EINVAL;
5033 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5034 if (rc)
5035 rc = -EIO;
5036 return rc;
5037}
5038
c0c050c5
MC		 5039static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5040{
ae10ae74 5041 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
c0c050c5
MC		 5042 int rc;
5043
ae10ae74
MC		 5044 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5045 goto skip_rss_ctx;
5046
c0c050c5 5047 /* allocate context for vnic */
94ce9caa 5048 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
c0c050c5
MC		 5049 if (rc) {
5050 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5051 vnic_id, rc);
5052 goto vnic_setup_err;
5053 }
5054 bp->rsscos_nr_ctxs++;
5055
94ce9caa
PS		 5056 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5057 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5058 if (rc) {
5059 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5060 vnic_id, rc);
5061 goto vnic_setup_err;
5062 }
5063 bp->rsscos_nr_ctxs++;
5064 }
5065
ae10ae74 5066skip_rss_ctx:
c0c050c5
MC		 5067 /* configure default vnic, ring grp */
5068 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5069 if (rc) {
5070 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5071 vnic_id, rc);
5072 goto vnic_setup_err;
5073 }
5074
5075 /* Enable RSS hashing on vnic */
5076 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5077 if (rc) {
5078 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5079 vnic_id, rc);
5080 goto vnic_setup_err;
5081 }
5082
5083 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5084 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5085 if (rc) {
5086 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5087 vnic_id, rc);
5088 }
5089 }
5090
5091vnic_setup_err:
5092 return rc;
5093}
5094
5095static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5096{
5097#ifdef CONFIG_RFS_ACCEL
5098 int i, rc = 0;
5099
5100 for (i = 0; i < bp->rx_nr_rings; i++) {
ae10ae74 5101 struct bnxt_vnic_info *vnic;
c0c050c5
MC		 5102 u16 vnic_id = i + 1;
5103 u16 ring_id = i;
5104
5105 if (vnic_id >= bp->nr_vnics)
5106 break;
5107
ae10ae74
MC		 5108 vnic = &bp->vnic_info[vnic_id];
5109 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5110 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5111 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
b81a90d3 5112 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 5113 if (rc) {
5114 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5115 vnic_id, rc);
5116 break;
5117 }
5118 rc = bnxt_setup_vnic(bp, vnic_id);
5119 if (rc)
5120 break;
5121 }
5122 return rc;
5123#else
5124 return 0;
5125#endif
5126}
5127
17c71ac3
MC		 5128/* Allow PF and VF with default VLAN to be in promiscuous mode */
5129static bool bnxt_promisc_ok(struct bnxt *bp)
5130{
5131#ifdef CONFIG_BNXT_SRIOV
5132 if (BNXT_VF(bp) && !bp->vf.vlan)
5133 return false;
5134#endif
5135 return true;
5136}
5137
dc52c6c7
PS		 5138static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5139{
5140 unsigned int rc = 0;
5141
5142 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5143 if (rc) {
5144 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5145 rc);
5146 return rc;
5147 }
5148
5149 rc = bnxt_hwrm_vnic_cfg(bp, 1);
5150 if (rc) {
5151 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5152 rc);
5153 return rc;
5154 }
5155 return rc;
5156}
5157
b664f008 5158static int bnxt_cfg_rx_mode(struct bnxt *);
7d2837dd 5159static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
b664f008 5160
c0c050c5
MC		 5161static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5162{
7d2837dd 5163 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
c0c050c5 5164 int rc = 0;
76595193 5165 unsigned int rx_nr_rings = bp->rx_nr_rings;
c0c050c5
MC		 5166
5167 if (irq_re_init) {
5168 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5169 if (rc) {
5170 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5171 rc);
5172 goto err_out;
5173 }
98fdbe73
MC		 5174 if (bp->tx_reserved_rings != bp->tx_nr_rings) {
5175 int tx = bp->tx_nr_rings;
5176
5177 if (bnxt_hwrm_reserve_tx_rings(bp, &tx) ||
5178 tx < bp->tx_nr_rings) {
5179 rc = -ENOMEM;
5180 goto err_out;
5181 }
5182 }
c0c050c5
MC		 5183 }
5184
5185 rc = bnxt_hwrm_ring_alloc(bp);
5186 if (rc) {
5187 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5188 goto err_out;
5189 }
5190
5191 rc = bnxt_hwrm_ring_grp_alloc(bp);
5192 if (rc) {
5193 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5194 goto err_out;
5195 }
5196
76595193
PS		 5197 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5198 rx_nr_rings--;
5199
c0c050c5 5200 /* default vnic 0 */
76595193 5201 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
c0c050c5
MC		 5202 if (rc) {
5203 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5204 goto err_out;
5205 }
5206
5207 rc = bnxt_setup_vnic(bp, 0);
5208 if (rc)
5209 goto err_out;
5210
5211 if (bp->flags & BNXT_FLAG_RFS) {
5212 rc = bnxt_alloc_rfs_vnics(bp);
5213 if (rc)
5214 goto err_out;
5215 }
5216
5217 if (bp->flags & BNXT_FLAG_TPA) {
5218 rc = bnxt_set_tpa(bp, true);
5219 if (rc)
5220 goto err_out;
5221 }
5222
5223 if (BNXT_VF(bp))
5224 bnxt_update_vf_mac(bp);
5225
5226 /* Filter for default vnic 0 */
5227 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5228 if (rc) {
5229 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5230 goto err_out;
5231 }
7d2837dd 5232 vnic->uc_filter_count = 1;
c0c050c5 5233
7d2837dd 5234 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5 5235
17c71ac3 5236 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7d2837dd
MC		 5237 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5238
5239 if (bp->dev->flags & IFF_ALLMULTI) {
5240 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5241 vnic->mc_list_count = 0;
5242 } else {
5243 u32 mask = 0;
5244
5245 bnxt_mc_list_updated(bp, &mask);
5246 vnic->rx_mask |= mask;
5247 }
c0c050c5 5248
b664f008
MC		 5249 rc = bnxt_cfg_rx_mode(bp);
5250 if (rc)
c0c050c5 5251 goto err_out;
c0c050c5
MC		 5252
5253 rc = bnxt_hwrm_set_coal(bp);
5254 if (rc)
5255 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
dc52c6c7
PS		 5256 rc);
5257
5258 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5259 rc = bnxt_setup_nitroa0_vnic(bp);
5260 if (rc)
5261 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5262 rc);
5263 }
c0c050c5 5264
cf6645f8
MC		 5265 if (BNXT_VF(bp)) {
5266 bnxt_hwrm_func_qcfg(bp);
5267 netdev_update_features(bp->dev);
5268 }
5269
c0c050c5
MC		 5270 return 0;
5271
5272err_out:
5273 bnxt_hwrm_resource_free(bp, 0, true);
5274
5275 return rc;
5276}
5277
5278static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5279{
5280 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5281 return 0;
5282}
5283
5284static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5285{
2247925f 5286 bnxt_init_cp_rings(bp);
c0c050c5
MC		 5287 bnxt_init_rx_rings(bp);
5288 bnxt_init_tx_rings(bp);
5289 bnxt_init_ring_grps(bp, irq_re_init);
5290 bnxt_init_vnics(bp);
5291
5292 return bnxt_init_chip(bp, irq_re_init);
5293}
5294
c0c050c5
MC		 5295static int bnxt_set_real_num_queues(struct bnxt *bp)
5296{
5297 int rc;
5298 struct net_device *dev = bp->dev;
5299
5f449249
MC		 5300 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5301 bp->tx_nr_rings_xdp);
c0c050c5
MC		 5302 if (rc)
5303 return rc;
5304
5305 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5306 if (rc)
5307 return rc;
5308
5309#ifdef CONFIG_RFS_ACCEL
45019a18 5310 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 5311 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 5312#endif
5313
5314 return rc;
5315}
5316
6e6c5a57
MC		 5317static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5318 bool shared)
5319{
5320 int _rx = *rx, _tx = *tx;
5321
5322 if (shared) {
5323 *rx = min_t(int, _rx, max);
5324 *tx = min_t(int, _tx, max);
5325 } else {
5326 if (max < 2)
5327 return -ENOMEM;
5328
5329 while (_rx + _tx > max) {
5330 if (_rx > _tx && _rx > 1)
5331 _rx--;
5332 else if (_tx > 1)
5333 _tx--;
5334 }
5335 *rx = _rx;
5336 *tx = _tx;
5337 }
5338 return 0;
5339}
5340
7809592d
MC		 5341static void bnxt_setup_msix(struct bnxt *bp)
5342{
5343 const int len = sizeof(bp->irq_tbl[0].name);
5344 struct net_device *dev = bp->dev;
5345 int tcs, i;
5346
5347 tcs = netdev_get_num_tc(dev);
5348 if (tcs > 1) {
d1e7925e 5349 int i, off, count;
7809592d 5350
d1e7925e
MC		 5351 for (i = 0; i < tcs; i++) {
5352 count = bp->tx_nr_rings_per_tc;
5353 off = i * count;
5354 netdev_set_tc_queue(dev, i, count, off);
7809592d
MC		 5355 }
5356 }
5357
5358 for (i = 0; i < bp->cp_nr_rings; i++) {
5359 char *attr;
5360
5361 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5362 attr = "TxRx";
5363 else if (i < bp->rx_nr_rings)
5364 attr = "rx";
5365 else
5366 attr = "tx";
5367
5368 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5369 i);
5370 bp->irq_tbl[i].handler = bnxt_msix;
5371 }
5372}
5373
5374static void bnxt_setup_inta(struct bnxt *bp)
5375{
5376 const int len = sizeof(bp->irq_tbl[0].name);
5377
5378 if (netdev_get_num_tc(bp->dev))
5379 netdev_reset_tc(bp->dev);
5380
5381 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5382 0);
5383 bp->irq_tbl[0].handler = bnxt_inta;
5384}
5385
5386static int bnxt_setup_int_mode(struct bnxt *bp)
5387{
5388 int rc;
5389
5390 if (bp->flags & BNXT_FLAG_USING_MSIX)
5391 bnxt_setup_msix(bp);
5392 else
5393 bnxt_setup_inta(bp);
5394
5395 rc = bnxt_set_real_num_queues(bp);
5396 return rc;
5397}
5398
b7429954 5399#ifdef CONFIG_RFS_ACCEL
8079e8f1
MC		 5400static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5401{
5402#if defined(CONFIG_BNXT_SRIOV)
5403 if (BNXT_VF(bp))
5404 return bp->vf.max_rsscos_ctxs;
5405#endif
5406 return bp->pf.max_rsscos_ctxs;
5407}
5408
5409static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5410{
5411#if defined(CONFIG_BNXT_SRIOV)
5412 if (BNXT_VF(bp))
5413 return bp->vf.max_vnics;
5414#endif
5415 return bp->pf.max_vnics;
5416}
b7429954 5417#endif
8079e8f1 5418
e4060d30
MC		 5419unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5420{
5421#if defined(CONFIG_BNXT_SRIOV)
5422 if (BNXT_VF(bp))
5423 return bp->vf.max_stat_ctxs;
5424#endif
5425 return bp->pf.max_stat_ctxs;
5426}
5427
a588e458
MC		 5428void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5429{
5430#if defined(CONFIG_BNXT_SRIOV)
5431 if (BNXT_VF(bp))
5432 bp->vf.max_stat_ctxs = max;
5433 else
5434#endif
5435 bp->pf.max_stat_ctxs = max;
5436}
5437
e4060d30
MC		 5438unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5439{
5440#if defined(CONFIG_BNXT_SRIOV)
5441 if (BNXT_VF(bp))
5442 return bp->vf.max_cp_rings;
5443#endif
5444 return bp->pf.max_cp_rings;
5445}
5446
a588e458
MC		 5447void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5448{
5449#if defined(CONFIG_BNXT_SRIOV)
5450 if (BNXT_VF(bp))
5451 bp->vf.max_cp_rings = max;
5452 else
5453#endif
5454 bp->pf.max_cp_rings = max;
5455}
5456
7809592d
MC		 5457static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5458{
5459#if defined(CONFIG_BNXT_SRIOV)
5460 if (BNXT_VF(bp))
68a946bb
MC		 5461 return min_t(unsigned int, bp->vf.max_irqs,
5462 bp->vf.max_cp_rings);
7809592d 5463#endif
68a946bb 5464 return min_t(unsigned int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7809592d
MC		 5465}
5466
33c2657e
MC		 5467void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5468{
5469#if defined(CONFIG_BNXT_SRIOV)
5470 if (BNXT_VF(bp))
5471 bp->vf.max_irqs = max_irqs;
5472 else
5473#endif
5474 bp->pf.max_irqs = max_irqs;
5475}
5476
7809592d 5477static int bnxt_init_msix(struct bnxt *bp)
c0c050c5 5478{
01657bcd 5479 int i, total_vecs, rc = 0, min = 1;
7809592d 5480 struct msix_entry *msix_ent;
c0c050c5 5481
7809592d 5482 total_vecs = bnxt_get_max_func_irqs(bp);
c0c050c5
MC		 5483 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5484 if (!msix_ent)
5485 return -ENOMEM;
5486
5487 for (i = 0; i < total_vecs; i++) {
5488 msix_ent[i].entry = i;
5489 msix_ent[i].vector = 0;
5490 }
5491
01657bcd
MC		 5492 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5493 min = 2;
5494
5495 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
c0c050c5
MC		 5496 if (total_vecs < 0) {
5497 rc = -ENODEV;
5498 goto msix_setup_exit;
5499 }
5500
5501 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5502 if (bp->irq_tbl) {
7809592d
MC		 5503 for (i = 0; i < total_vecs; i++)
5504 bp->irq_tbl[i].vector = msix_ent[i].vector;
c0c050c5 5505
7809592d 5506 bp->total_irqs = total_vecs;
c0c050c5 5507 /* Trim rings based upon num of vectors allocated */
6e6c5a57 5508 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
01657bcd 5509 total_vecs, min == 1);
6e6c5a57
MC		 5510 if (rc)
5511 goto msix_setup_exit;
5512
c0c050c5 5513 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7809592d
MC		 5514 bp->cp_nr_rings = (min == 1) ?
5515 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5516 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5 5517
c0c050c5
MC		 5518 } else {
5519 rc = -ENOMEM;
5520 goto msix_setup_exit;
5521 }
5522 bp->flags |= BNXT_FLAG_USING_MSIX;
5523 kfree(msix_ent);
5524 return 0;
5525
5526msix_setup_exit:
7809592d
MC		 5527 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5528 kfree(bp->irq_tbl);
5529 bp->irq_tbl = NULL;
c0c050c5
MC		 5530 pci_disable_msix(bp->pdev);
5531 kfree(msix_ent);
5532 return rc;
5533}
5534
7809592d 5535static int bnxt_init_inta(struct bnxt *bp)
c0c050c5 5536{
c0c050c5 5537 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7809592d
MC		 5538 if (!bp->irq_tbl)
5539 return -ENOMEM;
5540
5541 bp->total_irqs = 1;
c0c050c5
MC		 5542 bp->rx_nr_rings = 1;
5543 bp->tx_nr_rings = 1;
5544 bp->cp_nr_rings = 1;
5545 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
01657bcd 5546 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5 5547 bp->irq_tbl[0].vector = bp->pdev->irq;
7809592d 5548 return 0;
c0c050c5
MC		 5549}
5550
7809592d 5551static int bnxt_init_int_mode(struct bnxt *bp)
c0c050c5
MC		 5552{
5553 int rc = 0;
5554
5555 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7809592d 5556 rc = bnxt_init_msix(bp);
c0c050c5 5557
1fa72e29 5558 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
c0c050c5 5559 /* fallback to INTA */
7809592d 5560 rc = bnxt_init_inta(bp);
c0c050c5
MC		 5561 }
5562 return rc;
5563}
5564
7809592d
MC		 5565static void bnxt_clear_int_mode(struct bnxt *bp)
5566{
5567 if (bp->flags & BNXT_FLAG_USING_MSIX)
5568 pci_disable_msix(bp->pdev);
5569
5570 kfree(bp->irq_tbl);
5571 bp->irq_tbl = NULL;
5572 bp->flags &= ~BNXT_FLAG_USING_MSIX;
5573}
5574
c0c050c5
MC		 5575static void bnxt_free_irq(struct bnxt *bp)
5576{
5577 struct bnxt_irq *irq;
5578 int i;
5579
5580#ifdef CONFIG_RFS_ACCEL
5581 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5582 bp->dev->rx_cpu_rmap = NULL;
5583#endif
5584 if (!bp->irq_tbl)
5585 return;
5586
5587 for (i = 0; i < bp->cp_nr_rings; i++) {
5588 irq = &bp->irq_tbl[i];
56f0fd80
VV		 5589 if (irq->requested) {
5590 if (irq->have_cpumask) {
5591 irq_set_affinity_hint(irq->vector, NULL);
5592 free_cpumask_var(irq->cpu_mask);
5593 irq->have_cpumask = 0;
5594 }
c0c050c5 5595 free_irq(irq->vector, bp->bnapi[i]);
56f0fd80
VV		 5596 }
5597
c0c050c5
MC		 5598 irq->requested = 0;
5599 }
c0c050c5
MC		 5600}
5601
5602static int bnxt_request_irq(struct bnxt *bp)
5603{
b81a90d3 5604 int i, j, rc = 0;
c0c050c5
MC		 5605 unsigned long flags = 0;
5606#ifdef CONFIG_RFS_ACCEL
5607 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5608#endif
5609
5610 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5611 flags = IRQF_SHARED;
5612
b81a90d3 5613 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
c0c050c5
MC		 5614 struct bnxt_irq *irq = &bp->irq_tbl[i];
5615#ifdef CONFIG_RFS_ACCEL
b81a90d3 5616 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 5617 rc = irq_cpu_rmap_add(rmap, irq->vector);
5618 if (rc)
5619 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 5620 j);
5621 j++;
c0c050c5
MC		 5622 }
5623#endif
5624 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5625 bp->bnapi[i]);
5626 if (rc)
5627 break;
5628
5629 irq->requested = 1;
56f0fd80
VV		 5630
5631 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
5632 int numa_node = dev_to_node(&bp->pdev->dev);
5633
5634 irq->have_cpumask = 1;
5635 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
5636 irq->cpu_mask);
5637 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
5638 if (rc) {
5639 netdev_warn(bp->dev,
5640 "Set affinity failed, IRQ = %d\n",
5641 irq->vector);
5642 break;
5643 }
5644 }
c0c050c5
MC		 5645 }
5646 return rc;
5647}
5648
5649static void bnxt_del_napi(struct bnxt *bp)
5650{
5651 int i;
5652
5653 if (!bp->bnapi)
5654 return;
5655
5656 for (i = 0; i < bp->cp_nr_rings; i++) {
5657 struct bnxt_napi *bnapi = bp->bnapi[i];
5658
5659 napi_hash_del(&bnapi->napi);
5660 netif_napi_del(&bnapi->napi);
5661 }
e5f6f564
ED		 5662 /* We called napi_hash_del() before netif_napi_del(), we need
5663 * to respect an RCU grace period before freeing napi structures.
5664 */
5665 synchronize_net();
c0c050c5
MC		 5666}
5667
5668static void bnxt_init_napi(struct bnxt *bp)
5669{
5670 int i;
10bbdaf5 5671 unsigned int cp_nr_rings = bp->cp_nr_rings;
c0c050c5
MC		 5672 struct bnxt_napi *bnapi;
5673
5674 if (bp->flags & BNXT_FLAG_USING_MSIX) {
10bbdaf5
PS		 5675 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5676 cp_nr_rings--;
5677 for (i = 0; i < cp_nr_rings; i++) {
c0c050c5
MC		 5678 bnapi = bp->bnapi[i];
5679 netif_napi_add(bp->dev, &bnapi->napi,
5680 bnxt_poll, 64);
c0c050c5 5681 }
10bbdaf5
PS		 5682 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5683 bnapi = bp->bnapi[cp_nr_rings];
5684 netif_napi_add(bp->dev, &bnapi->napi,
5685 bnxt_poll_nitroa0, 64);
10bbdaf5 5686 }
c0c050c5
MC		 5687 } else {
5688 bnapi = bp->bnapi[0];
5689 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 5690 }
5691}
5692
5693static void bnxt_disable_napi(struct bnxt *bp)
5694{
5695 int i;
5696
5697 if (!bp->bnapi)
5698 return;
5699
b356a2e7 5700 for (i = 0; i < bp->cp_nr_rings; i++)
c0c050c5 5701 napi_disable(&bp->bnapi[i]->napi);
c0c050c5
MC		 5702}
5703
5704static void bnxt_enable_napi(struct bnxt *bp)
5705{
5706 int i;
5707
5708 for (i = 0; i < bp->cp_nr_rings; i++) {
fa7e2812 5709 bp->bnapi[i]->in_reset = false;
c0c050c5
MC		 5710 napi_enable(&bp->bnapi[i]->napi);
5711 }
5712}
5713
7df4ae9f 5714void bnxt_tx_disable(struct bnxt *bp)
c0c050c5
MC		 5715{
5716 int i;
c0c050c5 5717 struct bnxt_tx_ring_info *txr;
c0c050c5 5718
b6ab4b01 5719 if (bp->tx_ring) {
c0c050c5 5720 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 5721 txr = &bp->tx_ring[i];
c0c050c5 5722 txr->dev_state = BNXT_DEV_STATE_CLOSING;
c0c050c5
MC		 5723 }
5724 }
5725 /* Stop all TX queues */
5726 netif_tx_disable(bp->dev);
5727 netif_carrier_off(bp->dev);
5728}
5729
7df4ae9f 5730void bnxt_tx_enable(struct bnxt *bp)
c0c050c5
MC		 5731{
5732 int i;
c0c050c5 5733 struct bnxt_tx_ring_info *txr;
c0c050c5
MC		 5734
5735 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 5736 txr = &bp->tx_ring[i];
c0c050c5
MC		 5737 txr->dev_state = 0;
5738 }
5739 netif_tx_wake_all_queues(bp->dev);
5740 if (bp->link_info.link_up)
5741 netif_carrier_on(bp->dev);
5742}
5743
5744static void bnxt_report_link(struct bnxt *bp)
5745{
5746 if (bp->link_info.link_up) {
5747 const char *duplex;
5748 const char *flow_ctrl;
38a21b34
DK		 5749 u32 speed;
5750 u16 fec;
c0c050c5
MC		 5751
5752 netif_carrier_on(bp->dev);
5753 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5754 duplex = "full";
5755 else
5756 duplex = "half";
5757 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5758 flow_ctrl = "ON - receive & transmit";
5759 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5760 flow_ctrl = "ON - transmit";
5761 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5762 flow_ctrl = "ON - receive";
5763 else
5764 flow_ctrl = "none";
5765 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
38a21b34 5766 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
c0c050c5 5767 speed, duplex, flow_ctrl);
170ce013
MC		 5768 if (bp->flags & BNXT_FLAG_EEE_CAP)
5769 netdev_info(bp->dev, "EEE is %s\n",
5770 bp->eee.eee_active ? "active" :
5771 "not active");
e70c752f
MC		 5772 fec = bp->link_info.fec_cfg;
5773 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
5774 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
5775 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
5776 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
5777 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
c0c050c5
MC		 5778 } else {
5779 netif_carrier_off(bp->dev);
5780 netdev_err(bp->dev, "NIC Link is Down\n");
5781 }
5782}
5783
170ce013
MC		 5784static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5785{
5786 int rc = 0;
5787 struct hwrm_port_phy_qcaps_input req = {0};
5788 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
93ed8117 5789 struct bnxt_link_info *link_info = &bp->link_info;
170ce013
MC		 5790
5791 if (bp->hwrm_spec_code < 0x10201)
5792 return 0;
5793
5794 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5795
5796 mutex_lock(&bp->hwrm_cmd_lock);
5797 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5798 if (rc)
5799 goto hwrm_phy_qcaps_exit;
5800
acb20054 5801 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
170ce013
MC		 5802 struct ethtool_eee *eee = &bp->eee;
5803 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5804
5805 bp->flags |= BNXT_FLAG_EEE_CAP;
5806 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5807 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5808 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5809 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5810 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5811 }
520ad89a
MC		 5812 if (resp->supported_speeds_auto_mode)
5813 link_info->support_auto_speeds =
5814 le16_to_cpu(resp->supported_speeds_auto_mode);
170ce013 5815
d5430d31
MC		 5816 bp->port_count = resp->port_cnt;
5817
170ce013
MC		 5818hwrm_phy_qcaps_exit:
5819 mutex_unlock(&bp->hwrm_cmd_lock);
5820 return rc;
5821}
5822
c0c050c5
MC		 5823static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5824{
5825 int rc = 0;
5826 struct bnxt_link_info *link_info = &bp->link_info;
5827 struct hwrm_port_phy_qcfg_input req = {0};
5828 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5829 u8 link_up = link_info->link_up;
286ef9d6 5830 u16 diff;
c0c050c5
MC		 5831
5832 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5833
5834 mutex_lock(&bp->hwrm_cmd_lock);
5835 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5836 if (rc) {
5837 mutex_unlock(&bp->hwrm_cmd_lock);
5838 return rc;
5839 }
5840
5841 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5842 link_info->phy_link_status = resp->link;
acb20054
MC		 5843 link_info->duplex = resp->duplex_cfg;
5844 if (bp->hwrm_spec_code >= 0x10800)
5845 link_info->duplex = resp->duplex_state;
c0c050c5
MC		 5846 link_info->pause = resp->pause;
5847 link_info->auto_mode = resp->auto_mode;
5848 link_info->auto_pause_setting = resp->auto_pause;
3277360e 5849 link_info->lp_pause = resp->link_partner_adv_pause;
c0c050c5 5850 link_info->force_pause_setting = resp->force_pause;
acb20054 5851 link_info->duplex_setting = resp->duplex_cfg;
c0c050c5
MC		 5852 if (link_info->phy_link_status == BNXT_LINK_LINK)
5853 link_info->link_speed = le16_to_cpu(resp->link_speed);
5854 else
5855 link_info->link_speed = 0;
5856 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
c0c050c5
MC		 5857 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5858 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
3277360e
MC		 5859 link_info->lp_auto_link_speeds =
5860 le16_to_cpu(resp->link_partner_adv_speeds);
c0c050c5
MC		 5861 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5862 link_info->phy_ver[0] = resp->phy_maj;
5863 link_info->phy_ver[1] = resp->phy_min;
5864 link_info->phy_ver[2] = resp->phy_bld;
5865 link_info->media_type = resp->media_type;
03efbec0 5866 link_info->phy_type = resp->phy_type;
11f15ed3 5867 link_info->transceiver = resp->xcvr_pkg_type;
170ce013
MC		 5868 link_info->phy_addr = resp->eee_config_phy_addr &
5869 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
42ee18fe 5870 link_info->module_status = resp->module_status;
170ce013
MC		 5871
5872 if (bp->flags & BNXT_FLAG_EEE_CAP) {
5873 struct ethtool_eee *eee = &bp->eee;
5874 u16 fw_speeds;
5875
5876 eee->eee_active = 0;
5877 if (resp->eee_config_phy_addr &
5878 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5879 eee->eee_active = 1;
5880 fw_speeds = le16_to_cpu(
5881 resp->link_partner_adv_eee_link_speed_mask);
5882 eee->lp_advertised =
5883 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5884 }
5885
5886 /* Pull initial EEE config */
5887 if (!chng_link_state) {
5888 if (resp->eee_config_phy_addr &
5889 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5890 eee->eee_enabled = 1;
c0c050c5 5891
170ce013
MC		 5892 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5893 eee->advertised =
5894 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5895
5896 if (resp->eee_config_phy_addr &
5897 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5898 __le32 tmr;
5899
5900 eee->tx_lpi_enabled = 1;
5901 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5902 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5903 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5904 }
5905 }
5906 }
e70c752f
MC		 5907
5908 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
5909 if (bp->hwrm_spec_code >= 0x10504)
5910 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
5911
c0c050c5
MC		 5912 /* TODO: need to add more logic to report VF link */
5913 if (chng_link_state) {
5914 if (link_info->phy_link_status == BNXT_LINK_LINK)
5915 link_info->link_up = 1;
5916 else
5917 link_info->link_up = 0;
5918 if (link_up != link_info->link_up)
5919 bnxt_report_link(bp);
5920 } else {
5921 /* alwasy link down if not require to update link state */
5922 link_info->link_up = 0;
5923 }
5924 mutex_unlock(&bp->hwrm_cmd_lock);
286ef9d6
MC		 5925
5926 diff = link_info->support_auto_speeds ^ link_info->advertising;
5927 if ((link_info->support_auto_speeds | diff) !=
5928 link_info->support_auto_speeds) {
5929 /* An advertised speed is no longer supported, so we need to
0eaa24b9
MC		 5930 * update the advertisement settings. Caller holds RTNL
5931 * so we can modify link settings.
286ef9d6 5932 */
286ef9d6 5933 link_info->advertising = link_info->support_auto_speeds;
0eaa24b9 5934 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
286ef9d6 5935 bnxt_hwrm_set_link_setting(bp, true, false);
286ef9d6 5936 }
c0c050c5
MC		 5937 return 0;
5938}
5939
10289bec
MC		 5940static void bnxt_get_port_module_status(struct bnxt *bp)
5941{
5942 struct bnxt_link_info *link_info = &bp->link_info;
5943 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5944 u8 module_status;
5945
5946 if (bnxt_update_link(bp, true))
5947 return;
5948
5949 module_status = link_info->module_status;
5950 switch (module_status) {
5951 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5952 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5953 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5954 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5955 bp->pf.port_id);
5956 if (bp->hwrm_spec_code >= 0x10201) {
5957 netdev_warn(bp->dev, "Module part number %s\n",
5958 resp->phy_vendor_partnumber);
5959 }
5960 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5961 netdev_warn(bp->dev, "TX is disabled\n");
5962 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5963 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5964 }
5965}
5966
c0c050c5
MC		 5967static void
5968bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5969{
5970 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
c9ee9516
MC		 5971 if (bp->hwrm_spec_code >= 0x10201)
5972 req->auto_pause =
5973 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
c0c050c5
MC		 5974 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5975 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5976 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
49b5c7a1 5977 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
c0c050c5
MC		 5978 req->enables |=
5979 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5980 } else {
5981 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5982 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5983 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5984 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5985 req->enables |=
5986 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
c9ee9516
MC		 5987 if (bp->hwrm_spec_code >= 0x10201) {
5988 req->auto_pause = req->force_pause;
5989 req->enables |= cpu_to_le32(
5990 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5991 }
c0c050c5
MC		 5992 }
5993}
5994
5995static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5996 struct hwrm_port_phy_cfg_input *req)
5997{
5998 u8 autoneg = bp->link_info.autoneg;
5999 u16 fw_link_speed = bp->link_info.req_link_speed;
68515a18 6000 u16 advertising = bp->link_info.advertising;
c0c050c5
MC		 6001
6002 if (autoneg & BNXT_AUTONEG_SPEED) {
6003 req->auto_mode |=
11f15ed3 6004 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
c0c050c5
MC		 6005
6006 req->enables |= cpu_to_le32(
6007 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6008 req->auto_link_speed_mask = cpu_to_le16(advertising);
6009
6010 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6011 req->flags |=
6012 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6013 } else {
6014 req->force_link_speed = cpu_to_le16(fw_link_speed);
6015 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6016 }
6017
c0c050c5
MC		 6018 /* tell chimp that the setting takes effect immediately */
6019 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6020}
6021
6022int bnxt_hwrm_set_pause(struct bnxt *bp)
6023{
6024 struct hwrm_port_phy_cfg_input req = {0};
6025 int rc;
6026
6027 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6028 bnxt_hwrm_set_pause_common(bp, &req);
6029
6030 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6031 bp->link_info.force_link_chng)
6032 bnxt_hwrm_set_link_common(bp, &req);
6033
6034 mutex_lock(&bp->hwrm_cmd_lock);
6035 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6036 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6037 /* since changing of pause setting doesn't trigger any link
6038 * change event, the driver needs to update the current pause
6039 * result upon successfully return of the phy_cfg command
6040 */
6041 bp->link_info.pause =
6042 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6043 bp->link_info.auto_pause_setting = 0;
6044 if (!bp->link_info.force_link_chng)
6045 bnxt_report_link(bp);
6046 }
6047 bp->link_info.force_link_chng = false;
6048 mutex_unlock(&bp->hwrm_cmd_lock);
6049 return rc;
6050}
6051
939f7f0c
MC		 6052static void bnxt_hwrm_set_eee(struct bnxt *bp,
6053 struct hwrm_port_phy_cfg_input *req)
6054{
6055 struct ethtool_eee *eee = &bp->eee;
6056
6057 if (eee->eee_enabled) {
6058 u16 eee_speeds;
6059 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6060
6061 if (eee->tx_lpi_enabled)
6062 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6063 else
6064 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6065
6066 req->flags |= cpu_to_le32(flags);
6067 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6068 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6069 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6070 } else {
6071 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6072 }
6073}
6074
6075int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
c0c050c5
MC		 6076{
6077 struct hwrm_port_phy_cfg_input req = {0};
6078
6079 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6080 if (set_pause)
6081 bnxt_hwrm_set_pause_common(bp, &req);
6082
6083 bnxt_hwrm_set_link_common(bp, &req);
939f7f0c
MC		 6084
6085 if (set_eee)
6086 bnxt_hwrm_set_eee(bp, &req);
c0c050c5
MC		 6087 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6088}
6089
33f7d55f
MC		 6090static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6091{
6092 struct hwrm_port_phy_cfg_input req = {0};
6093
567b2abe 6094 if (!BNXT_SINGLE_PF(bp))
33f7d55f
MC		 6095 return 0;
6096
6097 if (pci_num_vf(bp->pdev))
6098 return 0;
6099
6100 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
16d663a6 6101 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
33f7d55f
MC		 6102 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6103}
6104
5ad2cbee
MC		 6105static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6106{
6107 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6108 struct hwrm_port_led_qcaps_input req = {0};
6109 struct bnxt_pf_info *pf = &bp->pf;
6110 int rc;
6111
6112 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6113 return 0;
6114
6115 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6116 req.port_id = cpu_to_le16(pf->port_id);
6117 mutex_lock(&bp->hwrm_cmd_lock);
6118 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6119 if (rc) {
6120 mutex_unlock(&bp->hwrm_cmd_lock);
6121 return rc;
6122 }
6123 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6124 int i;
6125
6126 bp->num_leds = resp->num_leds;
6127 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6128 bp->num_leds);
6129 for (i = 0; i < bp->num_leds; i++) {
6130 struct bnxt_led_info *led = &bp->leds[i];
6131 __le16 caps = led->led_state_caps;
6132
6133 if (!led->led_group_id ||
6134 !BNXT_LED_ALT_BLINK_CAP(caps)) {
6135 bp->num_leds = 0;
6136 break;
6137 }
6138 }
6139 }
6140 mutex_unlock(&bp->hwrm_cmd_lock);
6141 return 0;
6142}
6143
5282db6c
MC		 6144int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6145{
6146 struct hwrm_wol_filter_alloc_input req = {0};
6147 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6148 int rc;
6149
6150 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6151 req.port_id = cpu_to_le16(bp->pf.port_id);
6152 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6153 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6154 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6155 mutex_lock(&bp->hwrm_cmd_lock);
6156 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6157 if (!rc)
6158 bp->wol_filter_id = resp->wol_filter_id;
6159 mutex_unlock(&bp->hwrm_cmd_lock);
6160 return rc;
6161}
6162
6163int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6164{
6165 struct hwrm_wol_filter_free_input req = {0};
6166 int rc;
6167
6168 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6169 req.port_id = cpu_to_le16(bp->pf.port_id);
6170 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6171 req.wol_filter_id = bp->wol_filter_id;
6172 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6173 return rc;
6174}
6175
c1ef146a
MC		 6176static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6177{
6178 struct hwrm_wol_filter_qcfg_input req = {0};
6179 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6180 u16 next_handle = 0;
6181 int rc;
6182
6183 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6184 req.port_id = cpu_to_le16(bp->pf.port_id);
6185 req.handle = cpu_to_le16(handle);
6186 mutex_lock(&bp->hwrm_cmd_lock);
6187 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6188 if (!rc) {
6189 next_handle = le16_to_cpu(resp->next_handle);
6190 if (next_handle != 0) {
6191 if (resp->wol_type ==
6192 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6193 bp->wol = 1;
6194 bp->wol_filter_id = resp->wol_filter_id;
6195 }
6196 }
6197 }
6198 mutex_unlock(&bp->hwrm_cmd_lock);
6199 return next_handle;
6200}
6201
6202static void bnxt_get_wol_settings(struct bnxt *bp)
6203{
6204 u16 handle = 0;
6205
6206 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6207 return;
6208
6209 do {
6210 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6211 } while (handle && handle != 0xffff);
6212}
6213
939f7f0c
MC		 6214static bool bnxt_eee_config_ok(struct bnxt *bp)
6215{
6216 struct ethtool_eee *eee = &bp->eee;
6217 struct bnxt_link_info *link_info = &bp->link_info;
6218
6219 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6220 return true;
6221
6222 if (eee->eee_enabled) {
6223 u32 advertising =
6224 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6225
6226 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6227 eee->eee_enabled = 0;
6228 return false;
6229 }
6230 if (eee->advertised & ~advertising) {
6231 eee->advertised = advertising & eee->supported;
6232 return false;
6233 }
6234 }
6235 return true;
6236}
6237
c0c050c5
MC		 6238static int bnxt_update_phy_setting(struct bnxt *bp)
6239{
6240 int rc;
6241 bool update_link = false;
6242 bool update_pause = false;
939f7f0c 6243 bool update_eee = false;
c0c050c5
MC		 6244 struct bnxt_link_info *link_info = &bp->link_info;
6245
6246 rc = bnxt_update_link(bp, true);
6247 if (rc) {
6248 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6249 rc);
6250 return rc;
6251 }
33dac24a
MC		 6252 if (!BNXT_SINGLE_PF(bp))
6253 return 0;
6254
c0c050c5 6255 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
c9ee9516
MC		 6256 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6257 link_info->req_flow_ctrl)
c0c050c5
MC		 6258 update_pause = true;
6259 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6260 link_info->force_pause_setting != link_info->req_flow_ctrl)
6261 update_pause = true;
c0c050c5
MC		 6262 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6263 if (BNXT_AUTO_MODE(link_info->auto_mode))
6264 update_link = true;
6265 if (link_info->req_link_speed != link_info->force_link_speed)
6266 update_link = true;
de73018f
MC		 6267 if (link_info->req_duplex != link_info->duplex_setting)
6268 update_link = true;
c0c050c5
MC		 6269 } else {
6270 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6271 update_link = true;
6272 if (link_info->advertising != link_info->auto_link_speeds)
6273 update_link = true;
c0c050c5
MC		 6274 }
6275
16d663a6
MC		 6276 /* The last close may have shutdown the link, so need to call
6277 * PHY_CFG to bring it back up.
6278 */
6279 if (!netif_carrier_ok(bp->dev))
6280 update_link = true;
6281
939f7f0c
MC		 6282 if (!bnxt_eee_config_ok(bp))
6283 update_eee = true;
6284
c0c050c5 6285 if (update_link)
939f7f0c 6286 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
c0c050c5
MC		 6287 else if (update_pause)
6288 rc = bnxt_hwrm_set_pause(bp);
6289 if (rc) {
6290 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6291 rc);
6292 return rc;
6293 }
6294
6295 return rc;
6296}
6297
11809490
JH		 6298/* Common routine to pre-map certain register block to different GRC window.
6299 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6300 * in PF and 3 windows in VF that can be customized to map in different
6301 * register blocks.
6302 */
6303static void bnxt_preset_reg_win(struct bnxt *bp)
6304{
6305 if (BNXT_PF(bp)) {
6306 /* CAG registers map to GRC window #4 */
6307 writel(BNXT_CAG_REG_BASE,
6308 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6309 }
6310}
6311
c0c050c5
MC		 6312static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6313{
6314 int rc = 0;
6315
11809490 6316 bnxt_preset_reg_win(bp);
c0c050c5
MC		 6317 netif_carrier_off(bp->dev);
6318 if (irq_re_init) {
6319 rc = bnxt_setup_int_mode(bp);
6320 if (rc) {
6321 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6322 rc);
6323 return rc;
6324 }
6325 }
6326 if ((bp->flags & BNXT_FLAG_RFS) &&
6327 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6328 /* disable RFS if falling back to INTA */
6329 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6330 bp->flags &= ~BNXT_FLAG_RFS;
6331 }
6332
6333 rc = bnxt_alloc_mem(bp, irq_re_init);
6334 if (rc) {
6335 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6336 goto open_err_free_mem;
6337 }
6338
6339 if (irq_re_init) {
6340 bnxt_init_napi(bp);
6341 rc = bnxt_request_irq(bp);
6342 if (rc) {
6343 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6344 goto open_err;
6345 }
6346 }
6347
6348 bnxt_enable_napi(bp);
6349
6350 rc = bnxt_init_nic(bp, irq_re_init);
6351 if (rc) {
6352 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6353 goto open_err;
6354 }
6355
6356 if (link_re_init) {
e2dc9b6e 6357 mutex_lock(&bp->link_lock);
c0c050c5 6358 rc = bnxt_update_phy_setting(bp);
e2dc9b6e 6359 mutex_unlock(&bp->link_lock);
c0c050c5 6360 if (rc)
ba41d46f 6361 netdev_warn(bp->dev, "failed to update phy settings\n");
c0c050c5
MC		 6362 }
6363
7cdd5fc3 6364 if (irq_re_init)
ad51b8e9 6365 udp_tunnel_get_rx_info(bp->dev);
c0c050c5 6366
caefe526 6367 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 6368 bnxt_enable_int(bp);
6369 /* Enable TX queues */
6370 bnxt_tx_enable(bp);
6371 mod_timer(&bp->timer, jiffies + bp->current_interval);
10289bec
MC		 6372 /* Poll link status and check for SFP+ module status */
6373 bnxt_get_port_module_status(bp);
c0c050c5 6374
ee5c7fb3
SP		 6375 /* VF-reps may need to be re-opened after the PF is re-opened */
6376 if (BNXT_PF(bp))
6377 bnxt_vf_reps_open(bp);
c0c050c5
MC		 6378 return 0;
6379
6380open_err:
6381 bnxt_disable_napi(bp);
6382 bnxt_del_napi(bp);
6383
6384open_err_free_mem:
6385 bnxt_free_skbs(bp);
6386 bnxt_free_irq(bp);
6387 bnxt_free_mem(bp, true);
6388 return rc;
6389}
6390
6391/* rtnl_lock held */
6392int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6393{
6394 int rc = 0;
6395
6396 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6397 if (rc) {
6398 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6399 dev_close(bp->dev);
6400 }
6401 return rc;
6402}
6403
f7dc1ea6
MC		 6404/* rtnl_lock held, open the NIC half way by allocating all resources, but
6405 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
6406 * self tests.
6407 */
6408int bnxt_half_open_nic(struct bnxt *bp)
6409{
6410 int rc = 0;
6411
6412 rc = bnxt_alloc_mem(bp, false);
6413 if (rc) {
6414 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6415 goto half_open_err;
6416 }
6417 rc = bnxt_init_nic(bp, false);
6418 if (rc) {
6419 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6420 goto half_open_err;
6421 }
6422 return 0;
6423
6424half_open_err:
6425 bnxt_free_skbs(bp);
6426 bnxt_free_mem(bp, false);
6427 dev_close(bp->dev);
6428 return rc;
6429}
6430
6431/* rtnl_lock held, this call can only be made after a previous successful
6432 * call to bnxt_half_open_nic().
6433 */
6434void bnxt_half_close_nic(struct bnxt *bp)
6435{
6436 bnxt_hwrm_resource_free(bp, false, false);
6437 bnxt_free_skbs(bp);
6438 bnxt_free_mem(bp, false);
6439}
6440
c0c050c5
MC		 6441static int bnxt_open(struct net_device *dev)
6442{
6443 struct bnxt *bp = netdev_priv(dev);
c0c050c5 6444
c0c050c5
MC		 6445 return __bnxt_open_nic(bp, true, true);
6446}
6447
f9b76ebd
MC		 6448static bool bnxt_drv_busy(struct bnxt *bp)
6449{
6450 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
6451 test_bit(BNXT_STATE_READ_STATS, &bp->state));
6452}
6453
c0c050c5
MC		 6454int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6455{
6456 int rc = 0;
6457
6458#ifdef CONFIG_BNXT_SRIOV
6459 if (bp->sriov_cfg) {
6460 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6461 !bp->sriov_cfg,
6462 BNXT_SRIOV_CFG_WAIT_TMO);
6463 if (rc)
6464 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6465 }
ee5c7fb3
SP		 6466
6467 /* Close the VF-reps before closing PF */
6468 if (BNXT_PF(bp))
6469 bnxt_vf_reps_close(bp);
c0c050c5
MC		 6470#endif
6471 /* Change device state to avoid TX queue wake up's */
6472 bnxt_tx_disable(bp);
6473
caefe526 6474 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec 6475 smp_mb__after_atomic();
f9b76ebd 6476 while (bnxt_drv_busy(bp))
4cebdcec 6477 msleep(20);
c0c050c5 6478
9d8bc097 6479 /* Flush rings and and disable interrupts */
c0c050c5
MC		 6480 bnxt_shutdown_nic(bp, irq_re_init);
6481
6482 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6483
6484 bnxt_disable_napi(bp);
c0c050c5
MC		 6485 del_timer_sync(&bp->timer);
6486 bnxt_free_skbs(bp);
6487
6488 if (irq_re_init) {
6489 bnxt_free_irq(bp);
6490 bnxt_del_napi(bp);
6491 }
6492 bnxt_free_mem(bp, irq_re_init);
6493 return rc;
6494}
6495
6496static int bnxt_close(struct net_device *dev)
6497{
6498 struct bnxt *bp = netdev_priv(dev);
6499
6500 bnxt_close_nic(bp, true, true);
33f7d55f 6501 bnxt_hwrm_shutdown_link(bp);
c0c050c5
MC		 6502 return 0;
6503}
6504
6505/* rtnl_lock held */
6506static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6507{
6508 switch (cmd) {
6509 case SIOCGMIIPHY:
6510 /* fallthru */
6511 case SIOCGMIIREG: {
6512 if (!netif_running(dev))
6513 return -EAGAIN;
6514
6515 return 0;
6516 }
6517
6518 case SIOCSMIIREG:
6519 if (!netif_running(dev))
6520 return -EAGAIN;
6521
6522 return 0;
6523
6524 default:
6525 /* do nothing */
6526 break;
6527 }
6528 return -EOPNOTSUPP;
6529}
6530
bc1f4470 6531static void
c0c050c5
MC		 6532bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6533{
6534 u32 i;
6535 struct bnxt *bp = netdev_priv(dev);
6536
f9b76ebd
MC		 6537 set_bit(BNXT_STATE_READ_STATS, &bp->state);
6538 /* Make sure bnxt_close_nic() sees that we are reading stats before
6539 * we check the BNXT_STATE_OPEN flag.
6540 */
6541 smp_mb__after_atomic();
6542 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6543 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
bc1f4470 6544 return;
f9b76ebd 6545 }
c0c050c5
MC		 6546
6547 /* TODO check if we need to synchronize with bnxt_close path */
6548 for (i = 0; i < bp->cp_nr_rings; i++) {
6549 struct bnxt_napi *bnapi = bp->bnapi[i];
6550 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6551 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6552
6553 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6554 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6555 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6556
6557 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6558 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6559 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6560
6561 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6562 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6563 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6564
6565 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6566 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6567 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6568
6569 stats->rx_missed_errors +=
6570 le64_to_cpu(hw_stats->rx_discard_pkts);
6571
6572 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6573
c0c050c5
MC		 6574 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6575 }
6576
9947f83f
MC		 6577 if (bp->flags & BNXT_FLAG_PORT_STATS) {
6578 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6579 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6580
6581 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6582 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6583 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6584 le64_to_cpu(rx->rx_ovrsz_frames) +
6585 le64_to_cpu(rx->rx_runt_frames);
6586 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6587 le64_to_cpu(rx->rx_jbr_frames);
6588 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6589 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6590 stats->tx_errors = le64_to_cpu(tx->tx_err);
6591 }
f9b76ebd 6592 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
c0c050c5
MC		 6593}
6594
6595static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6596{
6597 struct net_device *dev = bp->dev;
6598 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6599 struct netdev_hw_addr *ha;
6600 u8 *haddr;
6601 int mc_count = 0;
6602 bool update = false;
6603 int off = 0;
6604
6605 netdev_for_each_mc_addr(ha, dev) {
6606 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6607 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6608 vnic->mc_list_count = 0;
6609 return false;
6610 }
6611 haddr = ha->addr;
6612 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6613 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6614 update = true;
6615 }
6616 off += ETH_ALEN;
6617 mc_count++;
6618 }
6619 if (mc_count)
6620 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6621
6622 if (mc_count != vnic->mc_list_count) {
6623 vnic->mc_list_count = mc_count;
6624 update = true;
6625 }
6626 return update;
6627}
6628
6629static bool bnxt_uc_list_updated(struct bnxt *bp)
6630{
6631 struct net_device *dev = bp->dev;
6632 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6633 struct netdev_hw_addr *ha;
6634 int off = 0;
6635
6636 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6637 return true;
6638
6639 netdev_for_each_uc_addr(ha, dev) {
6640 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6641 return true;
6642
6643 off += ETH_ALEN;
6644 }
6645 return false;
6646}
6647
6648static void bnxt_set_rx_mode(struct net_device *dev)
6649{
6650 struct bnxt *bp = netdev_priv(dev);
6651 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6652 u32 mask = vnic->rx_mask;
6653 bool mc_update = false;
6654 bool uc_update;
6655
6656 if (!netif_running(dev))
6657 return;
6658
6659 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6660 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6661 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6662
17c71ac3 6663 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
c0c050c5
MC		 6664 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6665
6666 uc_update = bnxt_uc_list_updated(bp);
6667
6668 if (dev->flags & IFF_ALLMULTI) {
6669 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6670 vnic->mc_list_count = 0;
6671 } else {
6672 mc_update = bnxt_mc_list_updated(bp, &mask);
6673 }
6674
6675 if (mask != vnic->rx_mask || uc_update || mc_update) {
6676 vnic->rx_mask = mask;
6677
6678 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
c213eae8 6679 bnxt_queue_sp_work(bp);
c0c050c5
MC		 6680 }
6681}
6682
b664f008 6683static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 6684{
6685 struct net_device *dev = bp->dev;
6686 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6687 struct netdev_hw_addr *ha;
6688 int i, off = 0, rc;
6689 bool uc_update;
6690
6691 netif_addr_lock_bh(dev);
6692 uc_update = bnxt_uc_list_updated(bp);
6693 netif_addr_unlock_bh(dev);
6694
6695 if (!uc_update)
6696 goto skip_uc;
6697
6698 mutex_lock(&bp->hwrm_cmd_lock);
6699 for (i = 1; i < vnic->uc_filter_count; i++) {
6700 struct hwrm_cfa_l2_filter_free_input req = {0};
6701
6702 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6703 -1);
6704
6705 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6706
6707 rc = _hwrm_send_message(bp, &req, sizeof(req),
6708 HWRM_CMD_TIMEOUT);
6709 }
6710 mutex_unlock(&bp->hwrm_cmd_lock);
6711
6712 vnic->uc_filter_count = 1;
6713
6714 netif_addr_lock_bh(dev);
6715 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6716 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6717 } else {
6718 netdev_for_each_uc_addr(ha, dev) {
6719 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6720 off += ETH_ALEN;
6721 vnic->uc_filter_count++;
6722 }
6723 }
6724 netif_addr_unlock_bh(dev);
6725
6726 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6727 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6728 if (rc) {
6729 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6730 rc);
6731 vnic->uc_filter_count = i;
b664f008 6732 return rc;
c0c050c5
MC		 6733 }
6734 }
6735
6736skip_uc:
6737 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6738 if (rc)
6739 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6740 rc);
b664f008
MC		 6741
6742 return rc;
c0c050c5
MC		 6743}
6744
8079e8f1
MC		 6745/* If the chip and firmware supports RFS */
6746static bool bnxt_rfs_supported(struct bnxt *bp)
6747{
6748 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6749 return true;
ae10ae74
MC		 6750 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6751 return true;
8079e8f1
MC		 6752 return false;
6753}
6754
6755/* If runtime conditions support RFS */
2bcfa6f6
MC		 6756static bool bnxt_rfs_capable(struct bnxt *bp)
6757{
6758#ifdef CONFIG_RFS_ACCEL
8079e8f1 6759 int vnics, max_vnics, max_rss_ctxs;
2bcfa6f6 6760
964fd480 6761 if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
2bcfa6f6
MC		 6762 return false;
6763
6764 vnics = 1 + bp->rx_nr_rings;
8079e8f1
MC		 6765 max_vnics = bnxt_get_max_func_vnics(bp);
6766 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
ae10ae74
MC		 6767
6768 /* RSS contexts not a limiting factor */
6769 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6770 max_rss_ctxs = max_vnics;
8079e8f1 6771 if (vnics > max_vnics || vnics > max_rss_ctxs) {
a2304909
VV		 6772 netdev_warn(bp->dev,
6773 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
8079e8f1 6774 min(max_rss_ctxs - 1, max_vnics - 1));
2bcfa6f6 6775 return false;
a2304909 6776 }
2bcfa6f6
MC		 6777
6778 return true;
6779#else
6780 return false;
6781#endif
6782}
6783
c0c050c5
MC		 6784static netdev_features_t bnxt_fix_features(struct net_device *dev,
6785 netdev_features_t features)
6786{
2bcfa6f6
MC		 6787 struct bnxt *bp = netdev_priv(dev);
6788
a2304909 6789 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
2bcfa6f6 6790 features &= ~NETIF_F_NTUPLE;
5a9f6b23
MC		 6791
6792 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6793 * turned on or off together.
6794 */
6795 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6796 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6797 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6798 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6799 NETIF_F_HW_VLAN_STAG_RX);
6800 else
6801 features |= NETIF_F_HW_VLAN_CTAG_RX |
6802 NETIF_F_HW_VLAN_STAG_RX;
6803 }
cf6645f8
MC		 6804#ifdef CONFIG_BNXT_SRIOV
6805 if (BNXT_VF(bp)) {
6806 if (bp->vf.vlan) {
6807 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6808 NETIF_F_HW_VLAN_STAG_RX);
6809 }
6810 }
6811#endif
c0c050c5
MC		 6812 return features;
6813}
6814
6815static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6816{
6817 struct bnxt *bp = netdev_priv(dev);
6818 u32 flags = bp->flags;
6819 u32 changes;
6820 int rc = 0;
6821 bool re_init = false;
6822 bool update_tpa = false;
6823
6824 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
3e8060fa 6825 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
c0c050c5
MC		 6826 flags |= BNXT_FLAG_GRO;
6827 if (features & NETIF_F_LRO)
6828 flags |= BNXT_FLAG_LRO;
6829
bdbd1eb5
MC		 6830 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6831 flags &= ~BNXT_FLAG_TPA;
6832
c0c050c5
MC		 6833 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6834 flags |= BNXT_FLAG_STRIP_VLAN;
6835
6836 if (features & NETIF_F_NTUPLE)
6837 flags |= BNXT_FLAG_RFS;
6838
6839 changes = flags ^ bp->flags;
6840 if (changes & BNXT_FLAG_TPA) {
6841 update_tpa = true;
6842 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6843 (flags & BNXT_FLAG_TPA) == 0)
6844 re_init = true;
6845 }
6846
6847 if (changes & ~BNXT_FLAG_TPA)
6848 re_init = true;
6849
6850 if (flags != bp->flags) {
6851 u32 old_flags = bp->flags;
6852
6853 bp->flags = flags;
6854
2bcfa6f6 6855 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 6856 if (update_tpa)
6857 bnxt_set_ring_params(bp);
6858 return rc;
6859 }
6860
6861 if (re_init) {
6862 bnxt_close_nic(bp, false, false);
6863 if (update_tpa)
6864 bnxt_set_ring_params(bp);
6865
6866 return bnxt_open_nic(bp, false, false);
6867 }
6868 if (update_tpa) {
6869 rc = bnxt_set_tpa(bp,
6870 (flags & BNXT_FLAG_TPA) ?
6871 true : false);
6872 if (rc)
6873 bp->flags = old_flags;
6874 }
6875 }
6876 return rc;
6877}
6878
9f554590
MC		 6879static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6880{
b6ab4b01 6881 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 6882 int i = bnapi->index;
6883
3b2b7d9d
MC		 6884 if (!txr)
6885 return;
6886
9f554590
MC		 6887 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6888 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6889 txr->tx_cons);
6890}
6891
6892static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6893{
b6ab4b01 6894 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 6895 int i = bnapi->index;
6896
3b2b7d9d
MC		 6897 if (!rxr)
6898 return;
6899
9f554590
MC		 6900 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6901 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6902 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6903 rxr->rx_sw_agg_prod);
6904}
6905
6906static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6907{
6908 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6909 int i = bnapi->index;
6910
6911 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6912 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6913}
6914
c0c050c5
MC		 6915static void bnxt_dbg_dump_states(struct bnxt *bp)
6916{
6917 int i;
6918 struct bnxt_napi *bnapi;
c0c050c5
MC		 6919
6920 for (i = 0; i < bp->cp_nr_rings; i++) {
6921 bnapi = bp->bnapi[i];
c0c050c5 6922 if (netif_msg_drv(bp)) {
9f554590
MC		 6923 bnxt_dump_tx_sw_state(bnapi);
6924 bnxt_dump_rx_sw_state(bnapi);
6925 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 6926 }
6927 }
6928}
6929
6988bd92 6930static void bnxt_reset_task(struct bnxt *bp, bool silent)
c0c050c5 6931{
6988bd92
MC		 6932 if (!silent)
6933 bnxt_dbg_dump_states(bp);
028de140 6934 if (netif_running(bp->dev)) {
b386cd36
MC		 6935 int rc;
6936
6937 if (!silent)
6938 bnxt_ulp_stop(bp);
028de140 6939 bnxt_close_nic(bp, false, false);
b386cd36
MC		 6940 rc = bnxt_open_nic(bp, false, false);
6941 if (!silent && !rc)
6942 bnxt_ulp_start(bp);
028de140 6943 }
c0c050c5
MC		 6944}
6945
6946static void bnxt_tx_timeout(struct net_device *dev)
6947{
6948 struct bnxt *bp = netdev_priv(dev);
6949
6950 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
6951 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
c213eae8 6952 bnxt_queue_sp_work(bp);
c0c050c5
MC		 6953}
6954
6955#ifdef CONFIG_NET_POLL_CONTROLLER
6956static void bnxt_poll_controller(struct net_device *dev)
6957{
6958 struct bnxt *bp = netdev_priv(dev);
6959 int i;
6960
2270bc5d
MC		 6961 /* Only process tx rings/combined rings in netpoll mode. */
6962 for (i = 0; i < bp->tx_nr_rings; i++) {
6963 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5 6964
2270bc5d 6965 napi_schedule(&txr->bnapi->napi);
c0c050c5
MC		 6966 }
6967}
6968#endif
6969
6970static void bnxt_timer(unsigned long data)
6971{
6972 struct bnxt *bp = (struct bnxt *)data;
6973 struct net_device *dev = bp->dev;
6974
6975 if (!netif_running(dev))
6976 return;
6977
6978 if (atomic_read(&bp->intr_sem) != 0)
6979 goto bnxt_restart_timer;
6980
adcc331e
MC		 6981 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
6982 bp->stats_coal_ticks) {
3bdf56c4 6983 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
c213eae8 6984 bnxt_queue_sp_work(bp);
3bdf56c4 6985 }
5a84acbe
SP		 6986
6987 if (bnxt_tc_flower_enabled(bp)) {
6988 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
6989 bnxt_queue_sp_work(bp);
6990 }
c0c050c5
MC		 6991bnxt_restart_timer:
6992 mod_timer(&bp->timer, jiffies + bp->current_interval);
6993}
6994
a551ee94 6995static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6988bd92 6996{
a551ee94
MC		 6997 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6998 * set. If the device is being closed, bnxt_close() may be holding
6988bd92
MC		 6999 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
7000 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7001 */
7002 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7003 rtnl_lock();
a551ee94
MC		 7004}
7005
7006static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7007{
6988bd92
MC		 7008 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7009 rtnl_unlock();
7010}
7011
a551ee94
MC		 7012/* Only called from bnxt_sp_task() */
7013static void bnxt_reset(struct bnxt *bp, bool silent)
7014{
7015 bnxt_rtnl_lock_sp(bp);
7016 if (test_bit(BNXT_STATE_OPEN, &bp->state))
7017 bnxt_reset_task(bp, silent);
7018 bnxt_rtnl_unlock_sp(bp);
7019}
7020
c0c050c5
MC		 7021static void bnxt_cfg_ntp_filters(struct bnxt *);
7022
7023static void bnxt_sp_task(struct work_struct *work)
7024{
7025 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
c0c050c5 7026
4cebdcec
MC		 7027 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7028 smp_mb__after_atomic();
7029 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7030 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 7031 return;
4cebdcec 7032 }
c0c050c5
MC		 7033
7034 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7035 bnxt_cfg_rx_mode(bp);
7036
7037 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7038 bnxt_cfg_ntp_filters(bp);
c0c050c5
MC		 7039 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7040 bnxt_hwrm_exec_fwd_req(bp);
7041 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7042 bnxt_hwrm_tunnel_dst_port_alloc(
7043 bp, bp->vxlan_port,
7044 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7045 }
7046 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7047 bnxt_hwrm_tunnel_dst_port_free(
7048 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7049 }
7cdd5fc3
AD		 7050 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7051 bnxt_hwrm_tunnel_dst_port_alloc(
7052 bp, bp->nge_port,
7053 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7054 }
7055 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7056 bnxt_hwrm_tunnel_dst_port_free(
7057 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7058 }
3bdf56c4
MC		 7059 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
7060 bnxt_hwrm_port_qstats(bp);
7061
0eaa24b9 7062 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
e2dc9b6e 7063 int rc;
0eaa24b9 7064
e2dc9b6e 7065 mutex_lock(&bp->link_lock);
0eaa24b9
MC		 7066 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7067 &bp->sp_event))
7068 bnxt_hwrm_phy_qcaps(bp);
7069
e2dc9b6e
MC		 7070 rc = bnxt_update_link(bp, true);
7071 mutex_unlock(&bp->link_lock);
0eaa24b9
MC		 7072 if (rc)
7073 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7074 rc);
7075 }
90c694bb 7076 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
e2dc9b6e
MC		 7077 mutex_lock(&bp->link_lock);
7078 bnxt_get_port_module_status(bp);
7079 mutex_unlock(&bp->link_lock);
90c694bb 7080 }
5a84acbe
SP		 7081
7082 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7083 bnxt_tc_flow_stats_work(bp);
7084
e2dc9b6e
MC		 7085 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
7086 * must be the last functions to be called before exiting.
7087 */
6988bd92
MC		 7088 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7089 bnxt_reset(bp, false);
4cebdcec 7090
fc0f1929
MC		 7091 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7092 bnxt_reset(bp, true);
7093
4cebdcec
MC		 7094 smp_mb__before_atomic();
7095 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 7096}
7097
d1e7925e 7098/* Under rtnl_lock */
98fdbe73
MC		 7099int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7100 int tx_xdp)
d1e7925e
MC		 7101{
7102 int max_rx, max_tx, tx_sets = 1;
7103 int tx_rings_needed;
d1e7925e
MC		 7104 int rc;
7105
d1e7925e
MC		 7106 if (tcs)
7107 tx_sets = tcs;
7108
7109 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7110 if (rc)
7111 return rc;
7112
7113 if (max_rx < rx)
7114 return -ENOMEM;
7115
5f449249 7116 tx_rings_needed = tx * tx_sets + tx_xdp;
d1e7925e
MC		 7117 if (max_tx < tx_rings_needed)
7118 return -ENOMEM;
7119
98fdbe73 7120 return bnxt_hwrm_check_tx_rings(bp, tx_rings_needed);
d1e7925e
MC		 7121}
7122
17086399
SP		 7123static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7124{
7125 if (bp->bar2) {
7126 pci_iounmap(pdev, bp->bar2);
7127 bp->bar2 = NULL;
7128 }
7129
7130 if (bp->bar1) {
7131 pci_iounmap(pdev, bp->bar1);
7132 bp->bar1 = NULL;
7133 }
7134
7135 if (bp->bar0) {
7136 pci_iounmap(pdev, bp->bar0);
7137 bp->bar0 = NULL;
7138 }
7139}
7140
7141static void bnxt_cleanup_pci(struct bnxt *bp)
7142{
7143 bnxt_unmap_bars(bp, bp->pdev);
7144 pci_release_regions(bp->pdev);
7145 pci_disable_device(bp->pdev);
7146}
7147
18775aa8
MC		 7148static void bnxt_init_dflt_coal(struct bnxt *bp)
7149{
7150 struct bnxt_coal *coal;
7151
7152 /* Tick values in micro seconds.
7153 * 1 coal_buf x bufs_per_record = 1 completion record.
7154 */
7155 coal = &bp->rx_coal;
7156 coal->coal_ticks = 14;
7157 coal->coal_bufs = 30;
7158 coal->coal_ticks_irq = 1;
7159 coal->coal_bufs_irq = 2;
7160 coal->idle_thresh = 25;
7161 coal->bufs_per_record = 2;
7162 coal->budget = 64; /* NAPI budget */
7163
7164 coal = &bp->tx_coal;
7165 coal->coal_ticks = 28;
7166 coal->coal_bufs = 30;
7167 coal->coal_ticks_irq = 2;
7168 coal->coal_bufs_irq = 2;
7169 coal->bufs_per_record = 1;
7170
7171 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7172}
7173
c0c050c5
MC		 7174static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7175{
7176 int rc;
7177 struct bnxt *bp = netdev_priv(dev);
7178
7179 SET_NETDEV_DEV(dev, &pdev->dev);
7180
7181 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7182 rc = pci_enable_device(pdev);
7183 if (rc) {
7184 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7185 goto init_err;
7186 }
7187
7188 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7189 dev_err(&pdev->dev,
7190 "Cannot find PCI device base address, aborting\n");
7191 rc = -ENODEV;
7192 goto init_err_disable;
7193 }
7194
7195 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7196 if (rc) {
7197 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7198 goto init_err_disable;
7199 }
7200
7201 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
7202 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
7203 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7204 goto init_err_disable;
7205 }
7206
7207 pci_set_master(pdev);
7208
7209 bp->dev = dev;
7210 bp->pdev = pdev;
7211
7212 bp->bar0 = pci_ioremap_bar(pdev, 0);
7213 if (!bp->bar0) {
7214 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
7215 rc = -ENOMEM;
7216 goto init_err_release;
7217 }
7218
7219 bp->bar1 = pci_ioremap_bar(pdev, 2);
7220 if (!bp->bar1) {
7221 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
7222 rc = -ENOMEM;
7223 goto init_err_release;
7224 }
7225
7226 bp->bar2 = pci_ioremap_bar(pdev, 4);
7227 if (!bp->bar2) {
7228 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
7229 rc = -ENOMEM;
7230 goto init_err_release;
7231 }
7232
6316ea6d
SB		 7233 pci_enable_pcie_error_reporting(pdev);
7234
c0c050c5
MC		 7235 INIT_WORK(&bp->sp_task, bnxt_sp_task);
7236
7237 spin_lock_init(&bp->ntp_fltr_lock);
7238
7239 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
7240 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
7241
18775aa8 7242 bnxt_init_dflt_coal(bp);
51f30785 7243
6c438244 7244 setup_timer(&bp->timer, bnxt_timer, (unsigned long)bp);
c0c050c5
MC		 7245 bp->current_interval = BNXT_TIMER_INTERVAL;
7246
caefe526 7247 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 7248 return 0;
7249
7250init_err_release:
17086399 7251 bnxt_unmap_bars(bp, pdev);
c0c050c5
MC		 7252 pci_release_regions(pdev);
7253
7254init_err_disable:
7255 pci_disable_device(pdev);
7256
7257init_err:
7258 return rc;
7259}
7260
7261/* rtnl_lock held */
7262static int bnxt_change_mac_addr(struct net_device *dev, void *p)
7263{
7264 struct sockaddr *addr = p;
1fc2cfd0
JH		 7265 struct bnxt *bp = netdev_priv(dev);
7266 int rc = 0;
c0c050c5
MC		 7267
7268 if (!is_valid_ether_addr(addr->sa_data))
7269 return -EADDRNOTAVAIL;
7270
c1a7bdff
MC		 7271 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
7272 return 0;
7273
84c33dd3
MC		 7274 rc = bnxt_approve_mac(bp, addr->sa_data);
7275 if (rc)
7276 return rc;
bdd4347b 7277
c0c050c5 7278 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 7279 if (netif_running(dev)) {
7280 bnxt_close_nic(bp, false, false);
7281 rc = bnxt_open_nic(bp, false, false);
7282 }
c0c050c5 7283
1fc2cfd0 7284 return rc;
c0c050c5
MC		 7285}
7286
7287/* rtnl_lock held */
7288static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
7289{
7290 struct bnxt *bp = netdev_priv(dev);
7291
c0c050c5
MC		 7292 if (netif_running(dev))
7293 bnxt_close_nic(bp, false, false);
7294
7295 dev->mtu = new_mtu;
7296 bnxt_set_ring_params(bp);
7297
7298 if (netif_running(dev))
7299 return bnxt_open_nic(bp, false, false);
7300
7301 return 0;
7302}
7303
c5e3deb8 7304int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
c0c050c5
MC		 7305{
7306 struct bnxt *bp = netdev_priv(dev);
3ffb6a39 7307 bool sh = false;
d1e7925e 7308 int rc;
16e5cc64 7309
c0c050c5 7310 if (tc > bp->max_tc) {
b451c8b6 7311 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
c0c050c5
MC		 7312 tc, bp->max_tc);
7313 return -EINVAL;
7314 }
7315
7316 if (netdev_get_num_tc(dev) == tc)
7317 return 0;
7318
3ffb6a39
MC		 7319 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7320 sh = true;
7321
98fdbe73
MC		 7322 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7323 sh, tc, bp->tx_nr_rings_xdp);
d1e7925e
MC		 7324 if (rc)
7325 return rc;
c0c050c5
MC		 7326
7327 /* Needs to close the device and do hw resource re-allocations */
7328 if (netif_running(bp->dev))
7329 bnxt_close_nic(bp, true, false);
7330
7331 if (tc) {
7332 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7333 netdev_set_num_tc(dev, tc);
7334 } else {
7335 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7336 netdev_reset_tc(dev);
7337 }
87e9b377 7338 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
3ffb6a39
MC		 7339 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7340 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5
MC		 7341 bp->num_stat_ctxs = bp->cp_nr_rings;
7342
7343 if (netif_running(bp->dev))
7344 return bnxt_open_nic(bp, true, false);
7345
7346 return 0;
7347}
7348
9e0fd15d
JP		 7349static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
7350 void *cb_priv)
c5e3deb8 7351{
9e0fd15d 7352 struct bnxt *bp = cb_priv;
de4784ca 7353
44ae12a7 7354 if (!bnxt_tc_flower_enabled(bp) || !tc_can_offload(bp->dev))
38cf0426 7355 return -EOPNOTSUPP;
c5e3deb8 7356
9e0fd15d
JP		 7357 switch (type) {
7358 case TC_SETUP_CLSFLOWER:
7359 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
7360 default:
7361 return -EOPNOTSUPP;
7362 }
7363}
7364
7365static int bnxt_setup_tc_block(struct net_device *dev,
7366 struct tc_block_offload *f)
7367{
7368 struct bnxt *bp = netdev_priv(dev);
7369
7370 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
7371 return -EOPNOTSUPP;
7372
7373 switch (f->command) {
7374 case TC_BLOCK_BIND:
7375 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
7376 bp, bp);
7377 case TC_BLOCK_UNBIND:
7378 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
7379 return 0;
7380 default:
7381 return -EOPNOTSUPP;
7382 }
2ae7408f
SP		 7383}
7384
7385static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
7386 void *type_data)
7387{
7388 switch (type) {
9e0fd15d
JP		 7389 case TC_SETUP_BLOCK:
7390 return bnxt_setup_tc_block(dev, type_data);
575ed7d3 7391 case TC_SETUP_QDISC_MQPRIO: {
2ae7408f
SP		 7392 struct tc_mqprio_qopt *mqprio = type_data;
7393
7394 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
56f36acd 7395
2ae7408f
SP		 7396 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
7397 }
7398 default:
7399 return -EOPNOTSUPP;
7400 }
c5e3deb8
MC		 7401}
7402
c0c050c5
MC		 7403#ifdef CONFIG_RFS_ACCEL
7404static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7405 struct bnxt_ntuple_filter *f2)
7406{
7407 struct flow_keys *keys1 = &f1->fkeys;
7408 struct flow_keys *keys2 = &f2->fkeys;
7409
7410 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
7411 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
7412 keys1->ports.ports == keys2->ports.ports &&
7413 keys1->basic.ip_proto == keys2->basic.ip_proto &&
7414 keys1->basic.n_proto == keys2->basic.n_proto &&
61aad724 7415 keys1->control.flags == keys2->control.flags &&
a54c4d74
MC		 7416 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7417 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
c0c050c5
MC		 7418 return true;
7419
7420 return false;
7421}
7422
7423static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7424 u16 rxq_index, u32 flow_id)
7425{
7426 struct bnxt *bp = netdev_priv(dev);
7427 struct bnxt_ntuple_filter *fltr, *new_fltr;
7428 struct flow_keys *fkeys;
7429 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
a54c4d74 7430 int rc = 0, idx, bit_id, l2_idx = 0;
c0c050c5
MC		 7431 struct hlist_head *head;
7432
a54c4d74
MC		 7433 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
7434 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7435 int off = 0, j;
7436
7437 netif_addr_lock_bh(dev);
7438 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
7439 if (ether_addr_equal(eth->h_dest,
7440 vnic->uc_list + off)) {
7441 l2_idx = j + 1;
7442 break;
7443 }
7444 }
7445 netif_addr_unlock_bh(dev);
7446 if (!l2_idx)
7447 return -EINVAL;
7448 }
c0c050c5
MC		 7449 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
7450 if (!new_fltr)
7451 return -ENOMEM;
7452
7453 fkeys = &new_fltr->fkeys;
7454 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
7455 rc = -EPROTONOSUPPORT;
7456 goto err_free;
7457 }
7458
dda0e746
MC		 7459 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
7460 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
c0c050c5
MC		 7461 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
7462 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
7463 rc = -EPROTONOSUPPORT;
7464 goto err_free;
7465 }
dda0e746
MC		 7466 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
7467 bp->hwrm_spec_code < 0x10601) {
7468 rc = -EPROTONOSUPPORT;
7469 goto err_free;
7470 }
61aad724
MC		 7471 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
7472 bp->hwrm_spec_code < 0x10601) {
7473 rc = -EPROTONOSUPPORT;
7474 goto err_free;
7475 }
c0c050c5 7476
a54c4d74 7477 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
c0c050c5
MC		 7478 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
7479
7480 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
7481 head = &bp->ntp_fltr_hash_tbl[idx];
7482 rcu_read_lock();
7483 hlist_for_each_entry_rcu(fltr, head, hash) {
7484 if (bnxt_fltr_match(fltr, new_fltr)) {
7485 rcu_read_unlock();
7486 rc = 0;
7487 goto err_free;
7488 }
7489 }
7490 rcu_read_unlock();
7491
7492 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 7493 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
7494 BNXT_NTP_FLTR_MAX_FLTR, 0);
7495 if (bit_id < 0) {
c0c050c5
MC		 7496 spin_unlock_bh(&bp->ntp_fltr_lock);
7497 rc = -ENOMEM;
7498 goto err_free;
7499 }
7500
84e86b98 7501 new_fltr->sw_id = (u16)bit_id;
c0c050c5 7502 new_fltr->flow_id = flow_id;
a54c4d74 7503 new_fltr->l2_fltr_idx = l2_idx;
c0c050c5
MC		 7504 new_fltr->rxq = rxq_index;
7505 hlist_add_head_rcu(&new_fltr->hash, head);
7506 bp->ntp_fltr_count++;
7507 spin_unlock_bh(&bp->ntp_fltr_lock);
7508
7509 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
c213eae8 7510 bnxt_queue_sp_work(bp);
c0c050c5
MC		 7511
7512 return new_fltr->sw_id;
7513
7514err_free:
7515 kfree(new_fltr);
7516 return rc;
7517}
7518
7519static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7520{
7521 int i;
7522
7523 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7524 struct hlist_head *head;
7525 struct hlist_node *tmp;
7526 struct bnxt_ntuple_filter *fltr;
7527 int rc;
7528
7529 head = &bp->ntp_fltr_hash_tbl[i];
7530 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7531 bool del = false;
7532
7533 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7534 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7535 fltr->flow_id,
7536 fltr->sw_id)) {
7537 bnxt_hwrm_cfa_ntuple_filter_free(bp,
7538 fltr);
7539 del = true;
7540 }
7541 } else {
7542 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7543 fltr);
7544 if (rc)
7545 del = true;
7546 else
7547 set_bit(BNXT_FLTR_VALID, &fltr->state);
7548 }
7549
7550 if (del) {
7551 spin_lock_bh(&bp->ntp_fltr_lock);
7552 hlist_del_rcu(&fltr->hash);
7553 bp->ntp_fltr_count--;
7554 spin_unlock_bh(&bp->ntp_fltr_lock);
7555 synchronize_rcu();
7556 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7557 kfree(fltr);
7558 }
7559 }
7560 }
19241368
JH		 7561 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7562 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 7563}
7564
7565#else
7566
7567static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7568{
7569}
7570
7571#endif /* CONFIG_RFS_ACCEL */
7572
ad51b8e9
AD		 7573static void bnxt_udp_tunnel_add(struct net_device *dev,
7574 struct udp_tunnel_info *ti)
c0c050c5
MC		 7575{
7576 struct bnxt *bp = netdev_priv(dev);
7577
ad51b8e9 7578 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 7579 return;
7580
ad51b8e9 7581 if (!netif_running(dev))
c0c050c5
MC		 7582 return;
7583
ad51b8e9
AD		 7584 switch (ti->type) {
7585 case UDP_TUNNEL_TYPE_VXLAN:
7586 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7587 return;
c0c050c5 7588
ad51b8e9
AD		 7589 bp->vxlan_port_cnt++;
7590 if (bp->vxlan_port_cnt == 1) {
7591 bp->vxlan_port = ti->port;
7592 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
c213eae8 7593 bnxt_queue_sp_work(bp);
ad51b8e9
AD		 7594 }
7595 break;
7cdd5fc3
AD		 7596 case UDP_TUNNEL_TYPE_GENEVE:
7597 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7598 return;
7599
7600 bp->nge_port_cnt++;
7601 if (bp->nge_port_cnt == 1) {
7602 bp->nge_port = ti->port;
7603 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7604 }
7605 break;
ad51b8e9
AD		 7606 default:
7607 return;
c0c050c5 7608 }
ad51b8e9 7609
c213eae8 7610 bnxt_queue_sp_work(bp);
c0c050c5
MC		 7611}
7612
ad51b8e9
AD		 7613static void bnxt_udp_tunnel_del(struct net_device *dev,
7614 struct udp_tunnel_info *ti)
c0c050c5
MC		 7615{
7616 struct bnxt *bp = netdev_priv(dev);
7617
ad51b8e9 7618 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 7619 return;
7620
ad51b8e9 7621 if (!netif_running(dev))
c0c050c5
MC		 7622 return;
7623
ad51b8e9
AD		 7624 switch (ti->type) {
7625 case UDP_TUNNEL_TYPE_VXLAN:
7626 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7627 return;
c0c050c5
MC		 7628 bp->vxlan_port_cnt--;
7629
ad51b8e9
AD		 7630 if (bp->vxlan_port_cnt != 0)
7631 return;
7632
7633 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7634 break;
7cdd5fc3
AD		 7635 case UDP_TUNNEL_TYPE_GENEVE:
7636 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7637 return;
7638 bp->nge_port_cnt--;
7639
7640 if (bp->nge_port_cnt != 0)
7641 return;
7642
7643 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7644 break;
ad51b8e9
AD		 7645 default:
7646 return;
c0c050c5 7647 }
ad51b8e9 7648
c213eae8 7649 bnxt_queue_sp_work(bp);
c0c050c5
MC		 7650}
7651
39d8ba2e
MC		 7652static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7653 struct net_device *dev, u32 filter_mask,
7654 int nlflags)
7655{
7656 struct bnxt *bp = netdev_priv(dev);
7657
7658 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
7659 nlflags, filter_mask, NULL);
7660}
7661
7662static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
7663 u16 flags)
7664{
7665 struct bnxt *bp = netdev_priv(dev);
7666 struct nlattr *attr, *br_spec;
7667 int rem, rc = 0;
7668
7669 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
7670 return -EOPNOTSUPP;
7671
7672 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7673 if (!br_spec)
7674 return -EINVAL;
7675
7676 nla_for_each_nested(attr, br_spec, rem) {
7677 u16 mode;
7678
7679 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7680 continue;
7681
7682 if (nla_len(attr) < sizeof(mode))
7683 return -EINVAL;
7684
7685 mode = nla_get_u16(attr);
7686 if (mode == bp->br_mode)
7687 break;
7688
7689 rc = bnxt_hwrm_set_br_mode(bp, mode);
7690 if (!rc)
7691 bp->br_mode = mode;
7692 break;
7693 }
7694 return rc;
7695}
7696
c124a62f
SP		 7697static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
7698 size_t len)
7699{
7700 struct bnxt *bp = netdev_priv(dev);
7701 int rc;
7702
7703 /* The PF and it's VF-reps only support the switchdev framework */
7704 if (!BNXT_PF(bp))
7705 return -EOPNOTSUPP;
7706
53f70b8b 7707 rc = snprintf(buf, len, "p%d", bp->pf.port_id);
c124a62f
SP		 7708
7709 if (rc >= len)
7710 return -EOPNOTSUPP;
7711 return 0;
7712}
7713
7714int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
7715{
7716 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
7717 return -EOPNOTSUPP;
7718
7719 /* The PF and it's VF-reps only support the switchdev framework */
7720 if (!BNXT_PF(bp))
7721 return -EOPNOTSUPP;
7722
7723 switch (attr->id) {
7724 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
7725 /* In SRIOV each PF-pool (PF + child VFs) serves as a
7726 * switching domain, the PF's perm mac-addr can be used
7727 * as the unique parent-id
7728 */
7729 attr->u.ppid.id_len = ETH_ALEN;
7730 ether_addr_copy(attr->u.ppid.id, bp->pf.mac_addr);
7731 break;
7732 default:
7733 return -EOPNOTSUPP;
7734 }
7735 return 0;
7736}
7737
7738static int bnxt_swdev_port_attr_get(struct net_device *dev,
7739 struct switchdev_attr *attr)
7740{
7741 return bnxt_port_attr_get(netdev_priv(dev), attr);
7742}
7743
7744static const struct switchdev_ops bnxt_switchdev_ops = {
7745 .switchdev_port_attr_get = bnxt_swdev_port_attr_get
7746};
7747
c0c050c5
MC		 7748static const struct net_device_ops bnxt_netdev_ops = {
7749 .ndo_open = bnxt_open,
7750 .ndo_start_xmit = bnxt_start_xmit,
7751 .ndo_stop = bnxt_close,
7752 .ndo_get_stats64 = bnxt_get_stats64,
7753 .ndo_set_rx_mode = bnxt_set_rx_mode,
7754 .ndo_do_ioctl = bnxt_ioctl,
7755 .ndo_validate_addr = eth_validate_addr,
7756 .ndo_set_mac_address = bnxt_change_mac_addr,
7757 .ndo_change_mtu = bnxt_change_mtu,
7758 .ndo_fix_features = bnxt_fix_features,
7759 .ndo_set_features = bnxt_set_features,
7760 .ndo_tx_timeout = bnxt_tx_timeout,
7761#ifdef CONFIG_BNXT_SRIOV
7762 .ndo_get_vf_config = bnxt_get_vf_config,
7763 .ndo_set_vf_mac = bnxt_set_vf_mac,
7764 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
7765 .ndo_set_vf_rate = bnxt_set_vf_bw,
7766 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
7767 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
7768#endif
7769#ifdef CONFIG_NET_POLL_CONTROLLER
7770 .ndo_poll_controller = bnxt_poll_controller,
7771#endif
7772 .ndo_setup_tc = bnxt_setup_tc,
7773#ifdef CONFIG_RFS_ACCEL
7774 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
7775#endif
ad51b8e9
AD		 7776 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
7777 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
f4e63525 7778 .ndo_bpf = bnxt_xdp,
39d8ba2e
MC		 7779 .ndo_bridge_getlink = bnxt_bridge_getlink,
7780 .ndo_bridge_setlink = bnxt_bridge_setlink,
c124a62f 7781 .ndo_get_phys_port_name = bnxt_get_phys_port_name
c0c050c5
MC		 7782};
7783
7784static void bnxt_remove_one(struct pci_dev *pdev)
7785{
7786 struct net_device *dev = pci_get_drvdata(pdev);
7787 struct bnxt *bp = netdev_priv(dev);
7788
4ab0c6a8 7789 if (BNXT_PF(bp)) {
c0c050c5 7790 bnxt_sriov_disable(bp);
4ab0c6a8
SP		 7791 bnxt_dl_unregister(bp);
7792 }
c0c050c5 7793
6316ea6d 7794 pci_disable_pcie_error_reporting(pdev);
c0c050c5 7795 unregister_netdev(dev);
2ae7408f 7796 bnxt_shutdown_tc(bp);
c213eae8 7797 bnxt_cancel_sp_work(bp);
c0c050c5
MC		 7798 bp->sp_event = 0;
7799
7809592d 7800 bnxt_clear_int_mode(bp);
be58a0da 7801 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5 7802 bnxt_free_hwrm_resources(bp);
e605db80 7803 bnxt_free_hwrm_short_cmd_req(bp);
eb513658 7804 bnxt_ethtool_free(bp);
7df4ae9f 7805 bnxt_dcb_free(bp);
a588e458
MC		 7806 kfree(bp->edev);
7807 bp->edev = NULL;
c6d30e83
MC		 7808 if (bp->xdp_prog)
7809 bpf_prog_put(bp->xdp_prog);
17086399 7810 bnxt_cleanup_pci(bp);
c0c050c5 7811 free_netdev(dev);
c0c050c5
MC		 7812}
7813
7814static int bnxt_probe_phy(struct bnxt *bp)
7815{
7816 int rc = 0;
7817 struct bnxt_link_info *link_info = &bp->link_info;
c0c050c5 7818
170ce013
MC		 7819 rc = bnxt_hwrm_phy_qcaps(bp);
7820 if (rc) {
7821 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7822 rc);
7823 return rc;
7824 }
e2dc9b6e 7825 mutex_init(&bp->link_lock);
170ce013 7826
c0c050c5
MC		 7827 rc = bnxt_update_link(bp, false);
7828 if (rc) {
7829 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7830 rc);
7831 return rc;
7832 }
7833
93ed8117
MC		 7834 /* Older firmware does not have supported_auto_speeds, so assume
7835 * that all supported speeds can be autonegotiated.
7836 */
7837 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7838 link_info->support_auto_speeds = link_info->support_speeds;
7839
c0c050c5 7840 /*initialize the ethool setting copy with NVM settings */
0d8abf02 7841 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
c9ee9516
MC		 7842 link_info->autoneg = BNXT_AUTONEG_SPEED;
7843 if (bp->hwrm_spec_code >= 0x10201) {
7844 if (link_info->auto_pause_setting &
7845 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7846 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7847 } else {
7848 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7849 }
0d8abf02 7850 link_info->advertising = link_info->auto_link_speeds;
0d8abf02
MC		 7851 } else {
7852 link_info->req_link_speed = link_info->force_link_speed;
7853 link_info->req_duplex = link_info->duplex_setting;
c0c050c5 7854 }
c9ee9516
MC		 7855 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7856 link_info->req_flow_ctrl =
7857 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7858 else
7859 link_info->req_flow_ctrl = link_info->force_pause_setting;
c0c050c5
MC		 7860 return rc;
7861}
7862
7863static int bnxt_get_max_irq(struct pci_dev *pdev)
7864{
7865 u16 ctrl;
7866
7867 if (!pdev->msix_cap)
7868 return 1;
7869
7870 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7871 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7872}
7873
6e6c5a57
MC		 7874static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7875 int *max_cp)
c0c050c5 7876{
6e6c5a57 7877 int max_ring_grps = 0;
c0c050c5 7878
379a80a1 7879#ifdef CONFIG_BNXT_SRIOV
415b6f19 7880 if (!BNXT_PF(bp)) {
c0c050c5
MC		 7881 *max_tx = bp->vf.max_tx_rings;
7882 *max_rx = bp->vf.max_rx_rings;
6e6c5a57
MC		 7883 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7884 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
b72d4a68 7885 max_ring_grps = bp->vf.max_hw_ring_grps;
415b6f19 7886 } else
379a80a1 7887#endif
415b6f19
AB		 7888 {
7889 *max_tx = bp->pf.max_tx_rings;
7890 *max_rx = bp->pf.max_rx_rings;
7891 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7892 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7893 max_ring_grps = bp->pf.max_hw_ring_grps;
c0c050c5 7894 }
76595193
PS		 7895 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7896 *max_cp -= 1;
7897 *max_rx -= 2;
7898 }
c0c050c5
MC		 7899 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7900 *max_rx >>= 1;
b72d4a68 7901 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 7902}
7903
7904int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7905{
7906 int rx, tx, cp;
7907
7908 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7909 if (!rx || !tx || !cp)
7910 return -ENOMEM;
7911
7912 *max_rx = rx;
7913 *max_tx = tx;
7914 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7915}
7916
e4060d30
MC		 7917static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7918 bool shared)
7919{
7920 int rc;
7921
7922 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
bdbd1eb5
MC		 7923 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7924 /* Not enough rings, try disabling agg rings. */
7925 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7926 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7927 if (rc)
7928 return rc;
7929 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7930 bp->dev->hw_features &= ~NETIF_F_LRO;
7931 bp->dev->features &= ~NETIF_F_LRO;
7932 bnxt_set_ring_params(bp);
7933 }
e4060d30
MC		 7934
7935 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7936 int max_cp, max_stat, max_irq;
7937
7938 /* Reserve minimum resources for RoCE */
7939 max_cp = bnxt_get_max_func_cp_rings(bp);
7940 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7941 max_irq = bnxt_get_max_func_irqs(bp);
7942 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7943 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7944 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7945 return 0;
7946
7947 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7948 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7949 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7950 max_cp = min_t(int, max_cp, max_irq);
7951 max_cp = min_t(int, max_cp, max_stat);
7952 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7953 if (rc)
7954 rc = 0;
7955 }
7956 return rc;
7957}
7958
702c221c 7959static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
6e6c5a57
MC		 7960{
7961 int dflt_rings, max_rx_rings, max_tx_rings, rc;
6e6c5a57
MC		 7962
7963 if (sh)
7964 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7965 dflt_rings = netif_get_num_default_rss_queues();
d5430d31
MC		 7966 /* Reduce default rings to reduce memory usage on multi-port cards */
7967 if (bp->port_count > 1)
7968 dflt_rings = min_t(int, dflt_rings, 4);
e4060d30 7969 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57
MC		 7970 if (rc)
7971 return rc;
7972 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7973 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
391be5c2
MC		 7974
7975 rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
7976 if (rc)
7977 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
7978
6e6c5a57
MC		 7979 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7980 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7981 bp->tx_nr_rings + bp->rx_nr_rings;
7982 bp->num_stat_ctxs = bp->cp_nr_rings;
76595193
PS		 7983 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7984 bp->rx_nr_rings++;
7985 bp->cp_nr_rings++;
7986 }
6e6c5a57 7987 return rc;
c0c050c5
MC		 7988}
7989
7b08f661
MC		 7990void bnxt_restore_pf_fw_resources(struct bnxt *bp)
7991{
7992 ASSERT_RTNL();
7993 bnxt_hwrm_func_qcaps(bp);
a588e458 7994 bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
7b08f661
MC		 7995}
7996
a22a6ac2
MC		 7997static int bnxt_init_mac_addr(struct bnxt *bp)
7998{
7999 int rc = 0;
8000
8001 if (BNXT_PF(bp)) {
8002 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
8003 } else {
8004#ifdef CONFIG_BNXT_SRIOV
8005 struct bnxt_vf_info *vf = &bp->vf;
8006
8007 if (is_valid_ether_addr(vf->mac_addr)) {
8008 /* overwrite netdev dev_adr with admin VF MAC */
8009 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8010 } else {
8011 eth_hw_addr_random(bp->dev);
8012 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
8013 }
8014#endif
8015 }
8016 return rc;
8017}
8018
90c4f788
AK		 8019static void bnxt_parse_log_pcie_link(struct bnxt *bp)
8020{
8021 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
8022 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
8023
7ab0760f 8024 if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) ||
90c4f788
AK		 8025 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
8026 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
8027 else
8028 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
8029 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
8030 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
8031 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
8032 "Unknown", width);
8033}
8034
c0c050c5
MC		 8035static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8036{
8037 static int version_printed;
8038 struct net_device *dev;
8039 struct bnxt *bp;
6e6c5a57 8040 int rc, max_irqs;
c0c050c5 8041
4e00338a 8042 if (pci_is_bridge(pdev))
fa853dda
PS		 8043 return -ENODEV;
8044
c0c050c5
MC		 8045 if (version_printed++ == 0)
8046 pr_info("%s", version);
8047
8048 max_irqs = bnxt_get_max_irq(pdev);
8049 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8050 if (!dev)
8051 return -ENOMEM;
8052
8053 bp = netdev_priv(dev);
8054
8055 if (bnxt_vf_pciid(ent->driver_data))
8056 bp->flags |= BNXT_FLAG_VF;
8057
2bcfa6f6 8058 if (pdev->msix_cap)
c0c050c5 8059 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 8060
8061 rc = bnxt_init_board(pdev, dev);
8062 if (rc < 0)
8063 goto init_err_free;
8064
8065 dev->netdev_ops = &bnxt_netdev_ops;
8066 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8067 dev->ethtool_ops = &bnxt_ethtool_ops;
bc88055a 8068 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
c0c050c5
MC		 8069 pci_set_drvdata(pdev, dev);
8070
3e8060fa
PS		 8071 rc = bnxt_alloc_hwrm_resources(bp);
8072 if (rc)
17086399 8073 goto init_err_pci_clean;
3e8060fa
PS		 8074
8075 mutex_init(&bp->hwrm_cmd_lock);
8076 rc = bnxt_hwrm_ver_get(bp);
8077 if (rc)
17086399 8078 goto init_err_pci_clean;
3e8060fa 8079
e605db80
DK		 8080 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
8081 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8082 if (rc)
8083 goto init_err_pci_clean;
8084 }
8085
3c2217a6
MC		 8086 rc = bnxt_hwrm_func_reset(bp);
8087 if (rc)
8088 goto init_err_pci_clean;
8089
5ac67d8b
RS		 8090 bnxt_hwrm_fw_set_time(bp);
8091
c0c050c5
MC		 8092 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8093 NETIF_F_TSO | NETIF_F_TSO6 |
8094 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7e13318d 8095 NETIF_F_GSO_IPXIP4 |
152971ee
AD		 8096 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8097 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
3e8060fa
PS		 8098 NETIF_F_RXCSUM | NETIF_F_GRO;
8099
8100 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8101 dev->hw_features |= NETIF_F_LRO;
c0c050c5 8102
c0c050c5
MC		 8103 dev->hw_enc_features =
8104 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8105 NETIF_F_TSO | NETIF_F_TSO6 |
8106 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
152971ee 8107 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7e13318d 8108 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
152971ee
AD		 8109 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
8110 NETIF_F_GSO_GRE_CSUM;
c0c050c5
MC		 8111 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
8112 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
8113 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
8114 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
8115 dev->priv_flags |= IFF_UNICAST_FLT;
8116
8117#ifdef CONFIG_BNXT_SRIOV
8118 init_waitqueue_head(&bp->sriov_cfg_wait);
4ab0c6a8 8119 mutex_init(&bp->sriov_lock);
c0c050c5 8120#endif
309369c9 8121 bp->gro_func = bnxt_gro_func_5730x;
3284f9e1 8122 if (BNXT_CHIP_P4_PLUS(bp))
94758f8d 8123 bp->gro_func = bnxt_gro_func_5731x;
434c975a
MC		 8124 else
8125 bp->flags |= BNXT_FLAG_DOUBLE_DB;
309369c9 8126
c0c050c5
MC		 8127 rc = bnxt_hwrm_func_drv_rgtr(bp);
8128 if (rc)
17086399 8129 goto init_err_pci_clean;
c0c050c5 8130
a1653b13
MC		 8131 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
8132 if (rc)
17086399 8133 goto init_err_pci_clean;
a1653b13 8134
a588e458
MC		 8135 bp->ulp_probe = bnxt_ulp_probe;
8136
c0c050c5
MC		 8137 /* Get the MAX capabilities for this function */
8138 rc = bnxt_hwrm_func_qcaps(bp);
8139 if (rc) {
8140 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
8141 rc);
8142 rc = -1;
17086399 8143 goto init_err_pci_clean;
c0c050c5 8144 }
a22a6ac2
MC		 8145 rc = bnxt_init_mac_addr(bp);
8146 if (rc) {
8147 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
8148 rc = -EADDRNOTAVAIL;
8149 goto init_err_pci_clean;
8150 }
c0c050c5
MC		 8151 rc = bnxt_hwrm_queue_qportcfg(bp);
8152 if (rc) {
8153 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
8154 rc);
8155 rc = -1;
17086399 8156 goto init_err_pci_clean;
c0c050c5
MC		 8157 }
8158
567b2abe 8159 bnxt_hwrm_func_qcfg(bp);
5ad2cbee 8160 bnxt_hwrm_port_led_qcaps(bp);
eb513658 8161 bnxt_ethtool_init(bp);
87fe6032 8162 bnxt_dcb_init(bp);
567b2abe 8163
7eb9bb3a
MC		 8164 /* MTU range: 60 - FW defined max */
8165 dev->min_mtu = ETH_ZLEN;
8166 dev->max_mtu = bp->max_mtu;
8167
d5430d31
MC		 8168 rc = bnxt_probe_phy(bp);
8169 if (rc)
8170 goto init_err_pci_clean;
8171
c61fb99c 8172 bnxt_set_rx_skb_mode(bp, false);
c0c050c5
MC		 8173 bnxt_set_tpa_flags(bp);
8174 bnxt_set_ring_params(bp);
33c2657e 8175 bnxt_set_max_func_irqs(bp, max_irqs);
702c221c 8176 rc = bnxt_set_dflt_rings(bp, true);
bdbd1eb5
MC		 8177 if (rc) {
8178 netdev_err(bp->dev, "Not enough rings available.\n");
8179 rc = -ENOMEM;
17086399 8180 goto init_err_pci_clean;
bdbd1eb5 8181 }
c0c050c5 8182
87da7f79
MC		 8183 /* Default RSS hash cfg. */
8184 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
8185 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
8186 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
8187 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
3284f9e1 8188 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
87da7f79
MC		 8189 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
8190 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
8191 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
8192 }
8193
8fdefd63 8194 bnxt_hwrm_vnic_qcaps(bp);
8079e8f1 8195 if (bnxt_rfs_supported(bp)) {
2bcfa6f6
MC		 8196 dev->hw_features |= NETIF_F_NTUPLE;
8197 if (bnxt_rfs_capable(bp)) {
8198 bp->flags |= BNXT_FLAG_RFS;
8199 dev->features |= NETIF_F_NTUPLE;
8200 }
8201 }
8202
c0c050c5
MC		 8203 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
8204 bp->flags |= BNXT_FLAG_STRIP_VLAN;
8205
7809592d 8206 rc = bnxt_init_int_mode(bp);
c0c050c5 8207 if (rc)
17086399 8208 goto init_err_pci_clean;
c0c050c5 8209
c1ef146a 8210 bnxt_get_wol_settings(bp);
d196ece7
MC		 8211 if (bp->flags & BNXT_FLAG_WOL_CAP)
8212 device_set_wakeup_enable(&pdev->dev, bp->wol);
8213 else
8214 device_set_wakeup_capable(&pdev->dev, false);
c1ef146a 8215
c213eae8
MC		 8216 if (BNXT_PF(bp)) {
8217 if (!bnxt_pf_wq) {
8218 bnxt_pf_wq =
8219 create_singlethread_workqueue("bnxt_pf_wq");
8220 if (!bnxt_pf_wq) {
8221 dev_err(&pdev->dev, "Unable to create workqueue.\n");
8222 goto init_err_pci_clean;
8223 }
8224 }
2ae7408f 8225 bnxt_init_tc(bp);
c213eae8 8226 }
2ae7408f 8227
7809592d
MC		 8228 rc = register_netdev(dev);
8229 if (rc)
2ae7408f 8230 goto init_err_cleanup_tc;
7809592d 8231
4ab0c6a8
SP		 8232 if (BNXT_PF(bp))
8233 bnxt_dl_register(bp);
8234
c0c050c5
MC		 8235 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
8236 board_info[ent->driver_data].name,
8237 (long)pci_resource_start(pdev, 0), dev->dev_addr);
8238
90c4f788
AK		 8239 bnxt_parse_log_pcie_link(bp);
8240
c0c050c5
MC		 8241 return 0;
8242
2ae7408f
SP		 8243init_err_cleanup_tc:
8244 bnxt_shutdown_tc(bp);
7809592d
MC		 8245 bnxt_clear_int_mode(bp);
8246
17086399
SP		 8247init_err_pci_clean:
8248 bnxt_cleanup_pci(bp);
c0c050c5
MC		 8249
8250init_err_free:
8251 free_netdev(dev);
8252 return rc;
8253}
8254
d196ece7
MC		 8255static void bnxt_shutdown(struct pci_dev *pdev)
8256{
8257 struct net_device *dev = pci_get_drvdata(pdev);
8258 struct bnxt *bp;
8259
8260 if (!dev)
8261 return;
8262
8263 rtnl_lock();
8264 bp = netdev_priv(dev);
8265 if (!bp)
8266 goto shutdown_exit;
8267
8268 if (netif_running(dev))
8269 dev_close(dev);
8270
8271 if (system_state == SYSTEM_POWER_OFF) {
0efd2fc6 8272 bnxt_ulp_shutdown(bp);
d196ece7
MC		 8273 bnxt_clear_int_mode(bp);
8274 pci_wake_from_d3(pdev, bp->wol);
8275 pci_set_power_state(pdev, PCI_D3hot);
8276 }
8277
8278shutdown_exit:
8279 rtnl_unlock();
8280}
8281
f65a2044
MC		 8282#ifdef CONFIG_PM_SLEEP
8283static int bnxt_suspend(struct device *device)
8284{
8285 struct pci_dev *pdev = to_pci_dev(device);
8286 struct net_device *dev = pci_get_drvdata(pdev);
8287 struct bnxt *bp = netdev_priv(dev);
8288 int rc = 0;
8289
8290 rtnl_lock();
8291 if (netif_running(dev)) {
8292 netif_device_detach(dev);
8293 rc = bnxt_close(dev);
8294 }
8295 bnxt_hwrm_func_drv_unrgtr(bp);
8296 rtnl_unlock();
8297 return rc;
8298}
8299
8300static int bnxt_resume(struct device *device)
8301{
8302 struct pci_dev *pdev = to_pci_dev(device);
8303 struct net_device *dev = pci_get_drvdata(pdev);
8304 struct bnxt *bp = netdev_priv(dev);
8305 int rc = 0;
8306
8307 rtnl_lock();
8308 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
8309 rc = -ENODEV;
8310 goto resume_exit;
8311 }
8312 rc = bnxt_hwrm_func_reset(bp);
8313 if (rc) {
8314 rc = -EBUSY;
8315 goto resume_exit;
8316 }
8317 bnxt_get_wol_settings(bp);
8318 if (netif_running(dev)) {
8319 rc = bnxt_open(dev);
8320 if (!rc)
8321 netif_device_attach(dev);
8322 }
8323
8324resume_exit:
8325 rtnl_unlock();
8326 return rc;
8327}
8328
8329static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
8330#define BNXT_PM_OPS (&bnxt_pm_ops)
8331
8332#else
8333
8334#define BNXT_PM_OPS NULL
8335
8336#endif /* CONFIG_PM_SLEEP */
8337
6316ea6d
SB		 8338/**
8339 * bnxt_io_error_detected - called when PCI error is detected
8340 * @pdev: Pointer to PCI device
8341 * @state: The current pci connection state
8342 *
8343 * This function is called after a PCI bus error affecting
8344 * this device has been detected.
8345 */
8346static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
8347 pci_channel_state_t state)
8348{
8349 struct net_device *netdev = pci_get_drvdata(pdev);
a588e458 8350 struct bnxt *bp = netdev_priv(netdev);
6316ea6d
SB		 8351
8352 netdev_info(netdev, "PCI I/O error detected\n");
8353
8354 rtnl_lock();
8355 netif_device_detach(netdev);
8356
a588e458
MC		 8357 bnxt_ulp_stop(bp);
8358
6316ea6d
SB		 8359 if (state == pci_channel_io_perm_failure) {
8360 rtnl_unlock();
8361 return PCI_ERS_RESULT_DISCONNECT;
8362 }
8363
8364 if (netif_running(netdev))
8365 bnxt_close(netdev);
8366
8367 pci_disable_device(pdev);
8368 rtnl_unlock();
8369
8370 /* Request a slot slot reset. */
8371 return PCI_ERS_RESULT_NEED_RESET;
8372}
8373
8374/**
8375 * bnxt_io_slot_reset - called after the pci bus has been reset.
8376 * @pdev: Pointer to PCI device
8377 *
8378 * Restart the card from scratch, as if from a cold-boot.
8379 * At this point, the card has exprienced a hard reset,
8380 * followed by fixups by BIOS, and has its config space
8381 * set up identically to what it was at cold boot.
8382 */
8383static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
8384{
8385 struct net_device *netdev = pci_get_drvdata(pdev);
8386 struct bnxt *bp = netdev_priv(netdev);
8387 int err = 0;
8388 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8389
8390 netdev_info(bp->dev, "PCI Slot Reset\n");
8391
8392 rtnl_lock();
8393
8394 if (pci_enable_device(pdev)) {
8395 dev_err(&pdev->dev,
8396 "Cannot re-enable PCI device after reset.\n");
8397 } else {
8398 pci_set_master(pdev);
8399
aa8ed021
MC		 8400 err = bnxt_hwrm_func_reset(bp);
8401 if (!err && netif_running(netdev))
6316ea6d
SB		 8402 err = bnxt_open(netdev);
8403
a588e458 8404 if (!err) {
6316ea6d 8405 result = PCI_ERS_RESULT_RECOVERED;
a588e458
MC		 8406 bnxt_ulp_start(bp);
8407 }
6316ea6d
SB		 8408 }
8409
8410 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
8411 dev_close(netdev);
8412
8413 rtnl_unlock();
8414
8415 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8416 if (err) {
8417 dev_err(&pdev->dev,
8418 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8419 err); /* non-fatal, continue */
8420 }
8421
8422 return PCI_ERS_RESULT_RECOVERED;
8423}
8424
8425/**
8426 * bnxt_io_resume - called when traffic can start flowing again.
8427 * @pdev: Pointer to PCI device
8428 *
8429 * This callback is called when the error recovery driver tells
8430 * us that its OK to resume normal operation.
8431 */
8432static void bnxt_io_resume(struct pci_dev *pdev)
8433{
8434 struct net_device *netdev = pci_get_drvdata(pdev);
8435
8436 rtnl_lock();
8437
8438 netif_device_attach(netdev);
8439
8440 rtnl_unlock();
8441}
8442
8443static const struct pci_error_handlers bnxt_err_handler = {
8444 .error_detected = bnxt_io_error_detected,
8445 .slot_reset = bnxt_io_slot_reset,
8446 .resume = bnxt_io_resume
8447};
8448
c0c050c5
MC		 8449static struct pci_driver bnxt_pci_driver = {
8450 .name = DRV_MODULE_NAME,
8451 .id_table = bnxt_pci_tbl,
8452 .probe = bnxt_init_one,
8453 .remove = bnxt_remove_one,
d196ece7 8454 .shutdown = bnxt_shutdown,
f65a2044 8455 .driver.pm = BNXT_PM_OPS,
6316ea6d 8456 .err_handler = &bnxt_err_handler,
c0c050c5
MC		 8457#if defined(CONFIG_BNXT_SRIOV)
8458 .sriov_configure = bnxt_sriov_configure,
8459#endif
8460};
8461
c213eae8
MC		 8462static int __init bnxt_init(void)
8463{
8464 return pci_register_driver(&bnxt_pci_driver);
8465}
8466
8467static void __exit bnxt_exit(void)
8468{
8469 pci_unregister_driver(&bnxt_pci_driver);
8470 if (bnxt_pf_wq)
8471 destroy_workqueue(bnxt_pf_wq);
8472}
8473
8474module_init(bnxt_init);
8475module_exit(bnxt_exit);
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