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bnxt_en: Add cache line size setting to optimize performance.
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
11f15ed3 3 * Copyright (c) 2014-2016 Broadcom Corporation
894aa69a 4 * Copyright (c) 2016-2018 Broadcom Limited
c0c050c5
MC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12
13#include <linux/stringify.h>
14#include <linux/kernel.h>
15#include <linux/timer.h>
16#include <linux/errno.h>
17#include <linux/ioport.h>
18#include <linux/slab.h>
19#include <linux/vmalloc.h>
20#include <linux/interrupt.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/dma-mapping.h>
26#include <linux/bitops.h>
27#include <linux/io.h>
28#include <linux/irq.h>
29#include <linux/delay.h>
30#include <asm/byteorder.h>
31#include <asm/page.h>
32#include <linux/time.h>
33#include <linux/mii.h>
34#include <linux/if.h>
35#include <linux/if_vlan.h>
32e8239c 36#include <linux/if_bridge.h>
5ac67d8b 37#include <linux/rtc.h>
c6d30e83 38#include <linux/bpf.h>
c0c050c5
MC		 39#include <net/ip.h>
40#include <net/tcp.h>
41#include <net/udp.h>
42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
ad51b8e9 44#include <net/udp_tunnel.h>
c0c050c5
MC		 45#include <linux/workqueue.h>
46#include <linux/prefetch.h>
47#include <linux/cache.h>
48#include <linux/log2.h>
49#include <linux/aer.h>
50#include <linux/bitmap.h>
51#include <linux/cpu_rmap.h>
56f0fd80 52#include <linux/cpumask.h>
2ae7408f 53#include <net/pkt_cls.h>
c0c050c5
MC		 54
55#include "bnxt_hsi.h"
56#include "bnxt.h"
a588e458 57#include "bnxt_ulp.h"
c0c050c5
MC		 58#include "bnxt_sriov.h"
59#include "bnxt_ethtool.h"
7df4ae9f 60#include "bnxt_dcb.h"
c6d30e83 61#include "bnxt_xdp.h"
4ab0c6a8 62#include "bnxt_vfr.h"
2ae7408f 63#include "bnxt_tc.h"
3c467bf3 64#include "bnxt_devlink.h"
c0c050c5
MC		 65
66#define BNXT_TX_TIMEOUT (5 * HZ)
67
68static const char version[] =
69 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
70
71MODULE_LICENSE("GPL");
72MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
73MODULE_VERSION(DRV_MODULE_VERSION);
74
75#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
76#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
77#define BNXT_RX_COPY_THRESH 256
78
4419dbe6 79#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 80
81enum board_idx {
fbc9a523 82 BCM57301,
c0c050c5
MC		 83 BCM57302,
84 BCM57304,
1f681688 85 BCM57417_NPAR,
fa853dda 86 BCM58700,
b24eb6ae
MC		 87 BCM57311,
88 BCM57312,
fbc9a523 89 BCM57402,
c0c050c5
MC		 90 BCM57404,
91 BCM57406,
1f681688
MC		 92 BCM57402_NPAR,
93 BCM57407,
b24eb6ae
MC		 94 BCM57412,
95 BCM57414,
96 BCM57416,
97 BCM57417,
1f681688 98 BCM57412_NPAR,
5049e33b 99 BCM57314,
1f681688
MC		 100 BCM57417_SFP,
101 BCM57416_SFP,
102 BCM57404_NPAR,
103 BCM57406_NPAR,
104 BCM57407_SFP,
adbc8305 105 BCM57407_NPAR,
1f681688
MC		 106 BCM57414_NPAR,
107 BCM57416_NPAR,
32b40798
DK		 108 BCM57452,
109 BCM57454,
92abef36 110 BCM5745x_NPAR,
4a58139b 111 BCM58802,
8ed693b7 112 BCM58804,
4a58139b 113 BCM58808,
adbc8305
MC		 114 NETXTREME_E_VF,
115 NETXTREME_C_VF,
618784e3 116 NETXTREME_S_VF,
c0c050c5
MC		 117};
118
119/* indexed by enum above */
120static const struct {
121 char *name;
122} board_info[] = {
27573a7d
SB		 123 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
124 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
125 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
126 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
127 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
128 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
129 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
130 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
131 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
132 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
133 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
134 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
135 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
136 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
137 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
138 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
139 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
140 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
141 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
142 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
143 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
144 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
145 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
146 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
147 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
148 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
149 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
150 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
92abef36 151 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
27573a7d 152 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
8ed693b7 153 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
27573a7d
SB		 154 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
155 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
156 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
618784e3 157 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
c0c050c5
MC		 158};
159
160static const struct pci_device_id bnxt_pci_tbl[] = {
92abef36
VV		 161 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
162 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
4a58139b 163 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
adbc8305 164 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
fbc9a523 165 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 166 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
167 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
1f681688 168 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
fa853dda 169 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
b24eb6ae
MC		 170 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
171 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
fbc9a523 172 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 173 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
174 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
1f681688
MC		 175 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
176 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
b24eb6ae
MC		 177 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
178 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
179 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
180 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
1f681688 181 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
5049e33b 182 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
1f681688
MC		 183 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
184 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
185 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
186 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
187 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
adbc8305
MC		 188 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
1f681688 190 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
adbc8305 191 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
1f681688 192 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
adbc8305 193 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
4a58139b 194 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
32b40798 195 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
4a58139b 196 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
8ed693b7 197 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
c0c050c5 198#ifdef CONFIG_BNXT_SRIOV
c7ef35eb
DK		 199 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
200 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
adbc8305
MC		 201 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
202 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
203 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
204 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
205 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
206 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
618784e3 207 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
c0c050c5
MC		 208#endif
209 { 0 }
210};
211
212MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
213
214static const u16 bnxt_vf_req_snif[] = {
215 HWRM_FUNC_CFG,
91cdda40 216 HWRM_FUNC_VF_CFG,
c0c050c5
MC		 217 HWRM_PORT_PHY_QCFG,
218 HWRM_CFA_L2_FILTER_ALLOC,
219};
220
25be8623 221static const u16 bnxt_async_events_arr[] = {
87c374de
MC		 222 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
223 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
224 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
225 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
226 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
25be8623
MC		 227};
228
c213eae8
MC		 229static struct workqueue_struct *bnxt_pf_wq;
230
c0c050c5
MC		 231static bool bnxt_vf_pciid(enum board_idx idx)
232{
618784e3
RM		 233 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
234 idx == NETXTREME_S_VF);
c0c050c5
MC		 235}
236
237#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
238#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
239#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
240
241#define BNXT_CP_DB_REARM(db, raw_cons) \
242 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
243
244#define BNXT_CP_DB(db, raw_cons) \
245 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
246
247#define BNXT_CP_DB_IRQ_DIS(db) \
248 writel(DB_CP_IRQ_DIS_FLAGS, db)
249
38413406 250const u16 bnxt_lhint_arr[] = {
c0c050c5
MC		 251 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
252 TX_BD_FLAGS_LHINT_512_TO_1023,
253 TX_BD_FLAGS_LHINT_1024_TO_2047,
254 TX_BD_FLAGS_LHINT_1024_TO_2047,
255 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
256 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
257 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
258 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
259 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
260 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
261 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
262 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
263 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
264 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
265 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
266 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
267 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
268 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
269 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
270};
271
ee5c7fb3
SP		 272static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
273{
274 struct metadata_dst *md_dst = skb_metadata_dst(skb);
275
276 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
277 return 0;
278
279 return md_dst->u.port_info.port_id;
280}
281
c0c050c5
MC		 282static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
283{
284 struct bnxt *bp = netdev_priv(dev);
285 struct tx_bd *txbd;
286 struct tx_bd_ext *txbd1;
287 struct netdev_queue *txq;
288 int i;
289 dma_addr_t mapping;
290 unsigned int length, pad = 0;
291 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
292 u16 prod, last_frag;
293 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 294 struct bnxt_tx_ring_info *txr;
295 struct bnxt_sw_tx_bd *tx_buf;
296
297 i = skb_get_queue_mapping(skb);
298 if (unlikely(i >= bp->tx_nr_rings)) {
299 dev_kfree_skb_any(skb);
300 return NETDEV_TX_OK;
301 }
302
c0c050c5 303 txq = netdev_get_tx_queue(dev, i);
a960dec9 304 txr = &bp->tx_ring[bp->tx_ring_map[i]];
c0c050c5
MC		 305 prod = txr->tx_prod;
306
307 free_size = bnxt_tx_avail(bp, txr);
308 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
309 netif_tx_stop_queue(txq);
310 return NETDEV_TX_BUSY;
311 }
312
313 length = skb->len;
314 len = skb_headlen(skb);
315 last_frag = skb_shinfo(skb)->nr_frags;
316
317 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
318
319 txbd->tx_bd_opaque = prod;
320
321 tx_buf = &txr->tx_buf_ring[prod];
322 tx_buf->skb = skb;
323 tx_buf->nr_frags = last_frag;
324
325 vlan_tag_flags = 0;
ee5c7fb3 326 cfa_action = bnxt_xmit_get_cfa_action(skb);
c0c050c5
MC		 327 if (skb_vlan_tag_present(skb)) {
328 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
329 skb_vlan_tag_get(skb);
330 /* Currently supports 8021Q, 8021AD vlan offloads
331 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
332 */
333 if (skb->vlan_proto == htons(ETH_P_8021Q))
334 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
335 }
336
337 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 338 struct tx_push_buffer *tx_push_buf = txr->tx_push;
339 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
340 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
341 void *pdata = tx_push_buf->data;
342 u64 *end;
343 int j, push_len;
c0c050c5
MC		 344
345 /* Set COAL_NOW to be ready quickly for the next push */
346 tx_push->tx_bd_len_flags_type =
347 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
348 TX_BD_TYPE_LONG_TX_BD |
349 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
350 TX_BD_FLAGS_COAL_NOW |
351 TX_BD_FLAGS_PACKET_END |
352 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
353
354 if (skb->ip_summed == CHECKSUM_PARTIAL)
355 tx_push1->tx_bd_hsize_lflags =
356 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
357 else
358 tx_push1->tx_bd_hsize_lflags = 0;
359
360 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
ee5c7fb3
SP		 361 tx_push1->tx_bd_cfa_action =
362 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
c0c050c5 363
fbb0fa8b
MC		 364 end = pdata + length;
365 end = PTR_ALIGN(end, 8) - 1;
4419dbe6
MC		 366 *end = 0;
367
c0c050c5
MC		 368 skb_copy_from_linear_data(skb, pdata, len);
369 pdata += len;
370 for (j = 0; j < last_frag; j++) {
371 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
372 void *fptr;
373
374 fptr = skb_frag_address_safe(frag);
375 if (!fptr)
376 goto normal_tx;
377
378 memcpy(pdata, fptr, skb_frag_size(frag));
379 pdata += skb_frag_size(frag);
380 }
381
4419dbe6
MC		 382 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
383 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 384 prod = NEXT_TX(prod);
385 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
386 memcpy(txbd, tx_push1, sizeof(*txbd));
387 prod = NEXT_TX(prod);
4419dbe6 388 tx_push->doorbell =
c0c050c5
MC		 389 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
390 txr->tx_prod = prod;
391
b9a8460a 392 tx_buf->is_push = 1;
c0c050c5 393 netdev_tx_sent_queue(txq, skb->len);
b9a8460a 394 wmb(); /* Sync is_push and byte queue before pushing data */
c0c050c5 395
4419dbe6
MC		 396 push_len = (length + sizeof(*tx_push) + 7) / 8;
397 if (push_len > 16) {
398 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
9d13744b
MC		 399 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
400 (push_len - 16) << 1);
4419dbe6
MC		 401 } else {
402 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
403 push_len);
404 }
c0c050c5 405
c0c050c5
MC		 406 goto tx_done;
407 }
408
409normal_tx:
410 if (length < BNXT_MIN_PKT_SIZE) {
411 pad = BNXT_MIN_PKT_SIZE - length;
412 if (skb_pad(skb, pad)) {
413 /* SKB already freed. */
414 tx_buf->skb = NULL;
415 return NETDEV_TX_OK;
416 }
417 length = BNXT_MIN_PKT_SIZE;
418 }
419
420 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
421
422 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
423 dev_kfree_skb_any(skb);
424 tx_buf->skb = NULL;
425 return NETDEV_TX_OK;
426 }
427
428 dma_unmap_addr_set(tx_buf, mapping, mapping);
429 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
430 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
431
432 txbd->tx_bd_haddr = cpu_to_le64(mapping);
433
434 prod = NEXT_TX(prod);
435 txbd1 = (struct tx_bd_ext *)
436 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
437
438 txbd1->tx_bd_hsize_lflags = 0;
439 if (skb_is_gso(skb)) {
440 u32 hdr_len;
441
442 if (skb->encapsulation)
443 hdr_len = skb_inner_network_offset(skb) +
444 skb_inner_network_header_len(skb) +
445 inner_tcp_hdrlen(skb);
446 else
447 hdr_len = skb_transport_offset(skb) +
448 tcp_hdrlen(skb);
449
450 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
451 TX_BD_FLAGS_T_IPID |
452 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
453 length = skb_shinfo(skb)->gso_size;
454 txbd1->tx_bd_mss = cpu_to_le32(length);
455 length += hdr_len;
456 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
457 txbd1->tx_bd_hsize_lflags =
458 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
459 txbd1->tx_bd_mss = 0;
460 }
461
462 length >>= 9;
463 flags |= bnxt_lhint_arr[length];
464 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
465
466 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
ee5c7fb3
SP		 467 txbd1->tx_bd_cfa_action =
468 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
c0c050c5
MC		 469 for (i = 0; i < last_frag; i++) {
470 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
471
472 prod = NEXT_TX(prod);
473 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
474
475 len = skb_frag_size(frag);
476 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
477 DMA_TO_DEVICE);
478
479 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
480 goto tx_dma_error;
481
482 tx_buf = &txr->tx_buf_ring[prod];
483 dma_unmap_addr_set(tx_buf, mapping, mapping);
484
485 txbd->tx_bd_haddr = cpu_to_le64(mapping);
486
487 flags = len << TX_BD_LEN_SHIFT;
488 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
489 }
490
491 flags &= ~TX_BD_LEN;
492 txbd->tx_bd_len_flags_type =
493 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
494 TX_BD_FLAGS_PACKET_END);
495
496 netdev_tx_sent_queue(txq, skb->len);
497
498 /* Sync BD data before updating doorbell */
499 wmb();
500
501 prod = NEXT_TX(prod);
502 txr->tx_prod = prod;
503
ffe40645 504 if (!skb->xmit_more || netif_xmit_stopped(txq))
4d172f21 505 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
c0c050c5
MC		 506
507tx_done:
508
509 mmiowb();
510
511 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
4d172f21
MC		 512 if (skb->xmit_more && !tx_buf->is_push)
513 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
514
c0c050c5
MC		 515 netif_tx_stop_queue(txq);
516
517 /* netif_tx_stop_queue() must be done before checking
518 * tx index in bnxt_tx_avail() below, because in
519 * bnxt_tx_int(), we update tx index before checking for
520 * netif_tx_queue_stopped().
521 */
522 smp_mb();
523 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
524 netif_tx_wake_queue(txq);
525 }
526 return NETDEV_TX_OK;
527
528tx_dma_error:
529 last_frag = i;
530
531 /* start back at beginning and unmap skb */
532 prod = txr->tx_prod;
533 tx_buf = &txr->tx_buf_ring[prod];
534 tx_buf->skb = NULL;
535 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
536 skb_headlen(skb), PCI_DMA_TODEVICE);
537 prod = NEXT_TX(prod);
538
539 /* unmap remaining mapped pages */
540 for (i = 0; i < last_frag; i++) {
541 prod = NEXT_TX(prod);
542 tx_buf = &txr->tx_buf_ring[prod];
543 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
544 skb_frag_size(&skb_shinfo(skb)->frags[i]),
545 PCI_DMA_TODEVICE);
546 }
547
548 dev_kfree_skb_any(skb);
549 return NETDEV_TX_OK;
550}
551
552static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
553{
b6ab4b01 554 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
a960dec9 555 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
c0c050c5
MC		 556 u16 cons = txr->tx_cons;
557 struct pci_dev *pdev = bp->pdev;
558 int i;
559 unsigned int tx_bytes = 0;
560
561 for (i = 0; i < nr_pkts; i++) {
562 struct bnxt_sw_tx_bd *tx_buf;
563 struct sk_buff *skb;
564 int j, last;
565
566 tx_buf = &txr->tx_buf_ring[cons];
567 cons = NEXT_TX(cons);
568 skb = tx_buf->skb;
569 tx_buf->skb = NULL;
570
571 if (tx_buf->is_push) {
572 tx_buf->is_push = 0;
573 goto next_tx_int;
574 }
575
576 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
577 skb_headlen(skb), PCI_DMA_TODEVICE);
578 last = tx_buf->nr_frags;
579
580 for (j = 0; j < last; j++) {
581 cons = NEXT_TX(cons);
582 tx_buf = &txr->tx_buf_ring[cons];
583 dma_unmap_page(
584 &pdev->dev,
585 dma_unmap_addr(tx_buf, mapping),
586 skb_frag_size(&skb_shinfo(skb)->frags[j]),
587 PCI_DMA_TODEVICE);
588 }
589
590next_tx_int:
591 cons = NEXT_TX(cons);
592
593 tx_bytes += skb->len;
594 dev_kfree_skb_any(skb);
595 }
596
597 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
598 txr->tx_cons = cons;
599
600 /* Need to make the tx_cons update visible to bnxt_start_xmit()
601 * before checking for netif_tx_queue_stopped(). Without the
602 * memory barrier, there is a small possibility that bnxt_start_xmit()
603 * will miss it and cause the queue to be stopped forever.
604 */
605 smp_mb();
606
607 if (unlikely(netif_tx_queue_stopped(txq)) &&
608 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
609 __netif_tx_lock(txq, smp_processor_id());
610 if (netif_tx_queue_stopped(txq) &&
611 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
612 txr->dev_state != BNXT_DEV_STATE_CLOSING)
613 netif_tx_wake_queue(txq);
614 __netif_tx_unlock(txq);
615 }
616}
617
c61fb99c
MC		 618static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
619 gfp_t gfp)
620{
621 struct device *dev = &bp->pdev->dev;
622 struct page *page;
623
624 page = alloc_page(gfp);
625 if (!page)
626 return NULL;
627
c519fe9a
SN		 628 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
629 DMA_ATTR_WEAK_ORDERING);
c61fb99c
MC		 630 if (dma_mapping_error(dev, *mapping)) {
631 __free_page(page);
632 return NULL;
633 }
634 *mapping += bp->rx_dma_offset;
635 return page;
636}
637
c0c050c5
MC		 638static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
639 gfp_t gfp)
640{
641 u8 *data;
642 struct pci_dev *pdev = bp->pdev;
643
644 data = kmalloc(bp->rx_buf_size, gfp);
645 if (!data)
646 return NULL;
647
c519fe9a
SN		 648 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
649 bp->rx_buf_use_size, bp->rx_dir,
650 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 651
652 if (dma_mapping_error(&pdev->dev, *mapping)) {
653 kfree(data);
654 data = NULL;
655 }
656 return data;
657}
658
38413406
MC		 659int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
660 u16 prod, gfp_t gfp)
c0c050c5
MC		 661{
662 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
663 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
c0c050c5
MC		 664 dma_addr_t mapping;
665
c61fb99c
MC		 666 if (BNXT_RX_PAGE_MODE(bp)) {
667 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
c0c050c5 668
c61fb99c
MC		 669 if (!page)
670 return -ENOMEM;
671
672 rx_buf->data = page;
673 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
674 } else {
675 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
676
677 if (!data)
678 return -ENOMEM;
679
680 rx_buf->data = data;
681 rx_buf->data_ptr = data + bp->rx_offset;
682 }
11cd119d 683 rx_buf->mapping = mapping;
c0c050c5
MC		 684
685 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
c0c050c5
MC		 686 return 0;
687}
688
c6d30e83 689void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
c0c050c5
MC		 690{
691 u16 prod = rxr->rx_prod;
692 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
693 struct rx_bd *cons_bd, *prod_bd;
694
695 prod_rx_buf = &rxr->rx_buf_ring[prod];
696 cons_rx_buf = &rxr->rx_buf_ring[cons];
697
698 prod_rx_buf->data = data;
6bb19474 699 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
c0c050c5 700
11cd119d 701 prod_rx_buf->mapping = cons_rx_buf->mapping;
c0c050c5
MC		 702
703 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
704 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
705
706 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
707}
708
709static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
710{
711 u16 next, max = rxr->rx_agg_bmap_size;
712
713 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
714 if (next >= max)
715 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
716 return next;
717}
718
719static inline int bnxt_alloc_rx_page(struct bnxt *bp,
720 struct bnxt_rx_ring_info *rxr,
721 u16 prod, gfp_t gfp)
722{
723 struct rx_bd *rxbd =
724 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
725 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
726 struct pci_dev *pdev = bp->pdev;
727 struct page *page;
728 dma_addr_t mapping;
729 u16 sw_prod = rxr->rx_sw_agg_prod;
89d0a06c 730 unsigned int offset = 0;
c0c050c5 731
89d0a06c
MC		 732 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
733 page = rxr->rx_page;
734 if (!page) {
735 page = alloc_page(gfp);
736 if (!page)
737 return -ENOMEM;
738 rxr->rx_page = page;
739 rxr->rx_page_offset = 0;
740 }
741 offset = rxr->rx_page_offset;
742 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
743 if (rxr->rx_page_offset == PAGE_SIZE)
744 rxr->rx_page = NULL;
745 else
746 get_page(page);
747 } else {
748 page = alloc_page(gfp);
749 if (!page)
750 return -ENOMEM;
751 }
c0c050c5 752
c519fe9a
SN		 753 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
754 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
755 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 756 if (dma_mapping_error(&pdev->dev, mapping)) {
757 __free_page(page);
758 return -EIO;
759 }
760
761 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
762 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
763
764 __set_bit(sw_prod, rxr->rx_agg_bmap);
765 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
766 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
767
768 rx_agg_buf->page = page;
89d0a06c 769 rx_agg_buf->offset = offset;
c0c050c5
MC		 770 rx_agg_buf->mapping = mapping;
771 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
772 rxbd->rx_bd_opaque = sw_prod;
773 return 0;
774}
775
776static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
777 u32 agg_bufs)
778{
779 struct bnxt *bp = bnapi->bp;
780 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 781 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 782 u16 prod = rxr->rx_agg_prod;
783 u16 sw_prod = rxr->rx_sw_agg_prod;
784 u32 i;
785
786 for (i = 0; i < agg_bufs; i++) {
787 u16 cons;
788 struct rx_agg_cmp *agg;
789 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
790 struct rx_bd *prod_bd;
791 struct page *page;
792
793 agg = (struct rx_agg_cmp *)
794 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
795 cons = agg->rx_agg_cmp_opaque;
796 __clear_bit(cons, rxr->rx_agg_bmap);
797
798 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
799 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
800
801 __set_bit(sw_prod, rxr->rx_agg_bmap);
802 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
803 cons_rx_buf = &rxr->rx_agg_ring[cons];
804
805 /* It is possible for sw_prod to be equal to cons, so
806 * set cons_rx_buf->page to NULL first.
807 */
808 page = cons_rx_buf->page;
809 cons_rx_buf->page = NULL;
810 prod_rx_buf->page = page;
89d0a06c 811 prod_rx_buf->offset = cons_rx_buf->offset;
c0c050c5
MC		 812
813 prod_rx_buf->mapping = cons_rx_buf->mapping;
814
815 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
816
817 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
818 prod_bd->rx_bd_opaque = sw_prod;
819
820 prod = NEXT_RX_AGG(prod);
821 sw_prod = NEXT_RX_AGG(sw_prod);
822 cp_cons = NEXT_CMP(cp_cons);
823 }
824 rxr->rx_agg_prod = prod;
825 rxr->rx_sw_agg_prod = sw_prod;
826}
827
c61fb99c
MC		 828static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
829 struct bnxt_rx_ring_info *rxr,
830 u16 cons, void *data, u8 *data_ptr,
831 dma_addr_t dma_addr,
832 unsigned int offset_and_len)
833{
834 unsigned int payload = offset_and_len >> 16;
835 unsigned int len = offset_and_len & 0xffff;
836 struct skb_frag_struct *frag;
837 struct page *page = data;
838 u16 prod = rxr->rx_prod;
839 struct sk_buff *skb;
840 int off, err;
841
842 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
843 if (unlikely(err)) {
844 bnxt_reuse_rx_data(rxr, cons, data);
845 return NULL;
846 }
847 dma_addr -= bp->rx_dma_offset;
c519fe9a
SN		 848 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
849 DMA_ATTR_WEAK_ORDERING);
c61fb99c
MC		 850
851 if (unlikely(!payload))
852 payload = eth_get_headlen(data_ptr, len);
853
854 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
855 if (!skb) {
856 __free_page(page);
857 return NULL;
858 }
859
860 off = (void *)data_ptr - page_address(page);
861 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
862 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
863 payload + NET_IP_ALIGN);
864
865 frag = &skb_shinfo(skb)->frags[0];
866 skb_frag_size_sub(frag, payload);
867 frag->page_offset += payload;
868 skb->data_len -= payload;
869 skb->tail += payload;
870
871 return skb;
872}
873
c0c050c5
MC		 874static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
875 struct bnxt_rx_ring_info *rxr, u16 cons,
6bb19474
MC		 876 void *data, u8 *data_ptr,
877 dma_addr_t dma_addr,
878 unsigned int offset_and_len)
c0c050c5 879{
6bb19474 880 u16 prod = rxr->rx_prod;
c0c050c5 881 struct sk_buff *skb;
6bb19474 882 int err;
c0c050c5
MC		 883
884 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
885 if (unlikely(err)) {
886 bnxt_reuse_rx_data(rxr, cons, data);
887 return NULL;
888 }
889
890 skb = build_skb(data, 0);
c519fe9a
SN		 891 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
892 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 893 if (!skb) {
894 kfree(data);
895 return NULL;
896 }
897
b3dba77c 898 skb_reserve(skb, bp->rx_offset);
6bb19474 899 skb_put(skb, offset_and_len & 0xffff);
c0c050c5
MC		 900 return skb;
901}
902
903static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
904 struct sk_buff *skb, u16 cp_cons,
905 u32 agg_bufs)
906{
907 struct pci_dev *pdev = bp->pdev;
908 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 909 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 910 u16 prod = rxr->rx_agg_prod;
911 u32 i;
912
913 for (i = 0; i < agg_bufs; i++) {
914 u16 cons, frag_len;
915 struct rx_agg_cmp *agg;
916 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
917 struct page *page;
918 dma_addr_t mapping;
919
920 agg = (struct rx_agg_cmp *)
921 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
922 cons = agg->rx_agg_cmp_opaque;
923 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
924 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
925
926 cons_rx_buf = &rxr->rx_agg_ring[cons];
89d0a06c
MC		 927 skb_fill_page_desc(skb, i, cons_rx_buf->page,
928 cons_rx_buf->offset, frag_len);
c0c050c5
MC		 929 __clear_bit(cons, rxr->rx_agg_bmap);
930
931 /* It is possible for bnxt_alloc_rx_page() to allocate
932 * a sw_prod index that equals the cons index, so we
933 * need to clear the cons entry now.
934 */
11cd119d 935 mapping = cons_rx_buf->mapping;
c0c050c5
MC		 936 page = cons_rx_buf->page;
937 cons_rx_buf->page = NULL;
938
939 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
940 struct skb_shared_info *shinfo;
941 unsigned int nr_frags;
942
943 shinfo = skb_shinfo(skb);
944 nr_frags = --shinfo->nr_frags;
945 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
946
947 dev_kfree_skb(skb);
948
949 cons_rx_buf->page = page;
950
951 /* Update prod since possibly some pages have been
952 * allocated already.
953 */
954 rxr->rx_agg_prod = prod;
955 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
956 return NULL;
957 }
958
c519fe9a
SN		 959 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
960 PCI_DMA_FROMDEVICE,
961 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 962
963 skb->data_len += frag_len;
964 skb->len += frag_len;
965 skb->truesize += PAGE_SIZE;
966
967 prod = NEXT_RX_AGG(prod);
968 cp_cons = NEXT_CMP(cp_cons);
969 }
970 rxr->rx_agg_prod = prod;
971 return skb;
972}
973
974static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
975 u8 agg_bufs, u32 *raw_cons)
976{
977 u16 last;
978 struct rx_agg_cmp *agg;
979
980 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
981 last = RING_CMP(*raw_cons);
982 agg = (struct rx_agg_cmp *)
983 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
984 return RX_AGG_CMP_VALID(agg, *raw_cons);
985}
986
987static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
988 unsigned int len,
989 dma_addr_t mapping)
990{
991 struct bnxt *bp = bnapi->bp;
992 struct pci_dev *pdev = bp->pdev;
993 struct sk_buff *skb;
994
995 skb = napi_alloc_skb(&bnapi->napi, len);
996 if (!skb)
997 return NULL;
998
745fc05c
MC		 999 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1000 bp->rx_dir);
c0c050c5 1001
6bb19474
MC		 1002 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1003 len + NET_IP_ALIGN);
c0c050c5 1004
745fc05c
MC		 1005 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1006 bp->rx_dir);
c0c050c5
MC		 1007
1008 skb_put(skb, len);
1009 return skb;
1010}
1011
fa7e2812
MC		 1012static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1013 u32 *raw_cons, void *cmp)
1014{
1015 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1016 struct rx_cmp *rxcmp = cmp;
1017 u32 tmp_raw_cons = *raw_cons;
1018 u8 cmp_type, agg_bufs = 0;
1019
1020 cmp_type = RX_CMP_TYPE(rxcmp);
1021
1022 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1023 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1024 RX_CMP_AGG_BUFS) >>
1025 RX_CMP_AGG_BUFS_SHIFT;
1026 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1027 struct rx_tpa_end_cmp *tpa_end = cmp;
1028
1029 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1030 RX_TPA_END_CMP_AGG_BUFS) >>
1031 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1032 }
1033
1034 if (agg_bufs) {
1035 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1036 return -EBUSY;
1037 }
1038 *raw_cons = tmp_raw_cons;
1039 return 0;
1040}
1041
c213eae8
MC		 1042static void bnxt_queue_sp_work(struct bnxt *bp)
1043{
1044 if (BNXT_PF(bp))
1045 queue_work(bnxt_pf_wq, &bp->sp_task);
1046 else
1047 schedule_work(&bp->sp_task);
1048}
1049
1050static void bnxt_cancel_sp_work(struct bnxt *bp)
1051{
1052 if (BNXT_PF(bp))
1053 flush_workqueue(bnxt_pf_wq);
1054 else
1055 cancel_work_sync(&bp->sp_task);
1056}
1057
fa7e2812
MC		 1058static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1059{
1060 if (!rxr->bnapi->in_reset) {
1061 rxr->bnapi->in_reset = true;
1062 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
c213eae8 1063 bnxt_queue_sp_work(bp);
fa7e2812
MC		 1064 }
1065 rxr->rx_next_cons = 0xffff;
1066}
1067
c0c050c5
MC		 1068static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1069 struct rx_tpa_start_cmp *tpa_start,
1070 struct rx_tpa_start_cmp_ext *tpa_start1)
1071{
1072 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1073 u16 cons, prod;
1074 struct bnxt_tpa_info *tpa_info;
1075 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1076 struct rx_bd *prod_bd;
1077 dma_addr_t mapping;
1078
1079 cons = tpa_start->rx_tpa_start_cmp_opaque;
1080 prod = rxr->rx_prod;
1081 cons_rx_buf = &rxr->rx_buf_ring[cons];
1082 prod_rx_buf = &rxr->rx_buf_ring[prod];
1083 tpa_info = &rxr->rx_tpa[agg_id];
1084
fa7e2812
MC		 1085 if (unlikely(cons != rxr->rx_next_cons)) {
1086 bnxt_sched_reset(bp, rxr);
1087 return;
1088 }
ee5c7fb3
SP		 1089 /* Store cfa_code in tpa_info to use in tpa_end
1090 * completion processing.
1091 */
1092 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
c0c050c5 1093 prod_rx_buf->data = tpa_info->data;
6bb19474 1094 prod_rx_buf->data_ptr = tpa_info->data_ptr;
c0c050c5
MC		 1095
1096 mapping = tpa_info->mapping;
11cd119d 1097 prod_rx_buf->mapping = mapping;
c0c050c5
MC		 1098
1099 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1100
1101 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1102
1103 tpa_info->data = cons_rx_buf->data;
6bb19474 1104 tpa_info->data_ptr = cons_rx_buf->data_ptr;
c0c050c5 1105 cons_rx_buf->data = NULL;
11cd119d 1106 tpa_info->mapping = cons_rx_buf->mapping;
c0c050c5
MC		 1107
1108 tpa_info->len =
1109 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1110 RX_TPA_START_CMP_LEN_SHIFT;
1111 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1112 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1113
1114 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1115 tpa_info->gso_type = SKB_GSO_TCPV4;
1116 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1117 if (hash_type == 3)
1118 tpa_info->gso_type = SKB_GSO_TCPV6;
1119 tpa_info->rss_hash =
1120 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1121 } else {
1122 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1123 tpa_info->gso_type = 0;
1124 if (netif_msg_rx_err(bp))
1125 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1126 }
1127 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1128 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
94758f8d 1129 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
c0c050c5
MC		 1130
1131 rxr->rx_prod = NEXT_RX(prod);
1132 cons = NEXT_RX(cons);
376a5b86 1133 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1134 cons_rx_buf = &rxr->rx_buf_ring[cons];
1135
1136 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1137 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1138 cons_rx_buf->data = NULL;
1139}
1140
1141static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1142 u16 cp_cons, u32 agg_bufs)
1143{
1144 if (agg_bufs)
1145 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1146}
1147
94758f8d
MC		 1148static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1149 int payload_off, int tcp_ts,
1150 struct sk_buff *skb)
1151{
1152#ifdef CONFIG_INET
1153 struct tcphdr *th;
1154 int len, nw_off;
1155 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1156 u32 hdr_info = tpa_info->hdr_info;
1157 bool loopback = false;
1158
1159 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1160 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1161 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1162
1163 /* If the packet is an internal loopback packet, the offsets will
1164 * have an extra 4 bytes.
1165 */
1166 if (inner_mac_off == 4) {
1167 loopback = true;
1168 } else if (inner_mac_off > 4) {
1169 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1170 ETH_HLEN - 2));
1171
1172 /* We only support inner iPv4/ipv6. If we don't see the
1173 * correct protocol ID, it must be a loopback packet where
1174 * the offsets are off by 4.
1175 */
09a7636a 1176 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
94758f8d
MC		 1177 loopback = true;
1178 }
1179 if (loopback) {
1180 /* internal loopback packet, subtract all offsets by 4 */
1181 inner_ip_off -= 4;
1182 inner_mac_off -= 4;
1183 outer_ip_off -= 4;
1184 }
1185
1186 nw_off = inner_ip_off - ETH_HLEN;
1187 skb_set_network_header(skb, nw_off);
1188 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1189 struct ipv6hdr *iph = ipv6_hdr(skb);
1190
1191 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1192 len = skb->len - skb_transport_offset(skb);
1193 th = tcp_hdr(skb);
1194 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1195 } else {
1196 struct iphdr *iph = ip_hdr(skb);
1197
1198 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1199 len = skb->len - skb_transport_offset(skb);
1200 th = tcp_hdr(skb);
1201 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1202 }
1203
1204 if (inner_mac_off) { /* tunnel */
1205 struct udphdr *uh = NULL;
1206 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1207 ETH_HLEN - 2));
1208
1209 if (proto == htons(ETH_P_IP)) {
1210 struct iphdr *iph = (struct iphdr *)skb->data;
1211
1212 if (iph->protocol == IPPROTO_UDP)
1213 uh = (struct udphdr *)(iph + 1);
1214 } else {
1215 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1216
1217 if (iph->nexthdr == IPPROTO_UDP)
1218 uh = (struct udphdr *)(iph + 1);
1219 }
1220 if (uh) {
1221 if (uh->check)
1222 skb_shinfo(skb)->gso_type |=
1223 SKB_GSO_UDP_TUNNEL_CSUM;
1224 else
1225 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1226 }
1227 }
1228#endif
1229 return skb;
1230}
1231
c0c050c5
MC		 1232#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1233#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1234
309369c9
MC		 1235static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1236 int payload_off, int tcp_ts,
c0c050c5
MC		 1237 struct sk_buff *skb)
1238{
d1611c3a 1239#ifdef CONFIG_INET
c0c050c5 1240 struct tcphdr *th;
719ca811 1241 int len, nw_off, tcp_opt_len = 0;
27e24189 1242
309369c9 1243 if (tcp_ts)
c0c050c5
MC		 1244 tcp_opt_len = 12;
1245
c0c050c5
MC		 1246 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1247 struct iphdr *iph;
1248
1249 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1250 ETH_HLEN;
1251 skb_set_network_header(skb, nw_off);
1252 iph = ip_hdr(skb);
1253 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1254 len = skb->len - skb_transport_offset(skb);
1255 th = tcp_hdr(skb);
1256 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1257 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1258 struct ipv6hdr *iph;
1259
1260 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1261 ETH_HLEN;
1262 skb_set_network_header(skb, nw_off);
1263 iph = ipv6_hdr(skb);
1264 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1265 len = skb->len - skb_transport_offset(skb);
1266 th = tcp_hdr(skb);
1267 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1268 } else {
1269 dev_kfree_skb_any(skb);
1270 return NULL;
1271 }
c0c050c5
MC		 1272
1273 if (nw_off) { /* tunnel */
1274 struct udphdr *uh = NULL;
1275
1276 if (skb->protocol == htons(ETH_P_IP)) {
1277 struct iphdr *iph = (struct iphdr *)skb->data;
1278
1279 if (iph->protocol == IPPROTO_UDP)
1280 uh = (struct udphdr *)(iph + 1);
1281 } else {
1282 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1283
1284 if (iph->nexthdr == IPPROTO_UDP)
1285 uh = (struct udphdr *)(iph + 1);
1286 }
1287 if (uh) {
1288 if (uh->check)
1289 skb_shinfo(skb)->gso_type |=
1290 SKB_GSO_UDP_TUNNEL_CSUM;
1291 else
1292 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1293 }
1294 }
1295#endif
1296 return skb;
1297}
1298
309369c9
MC		 1299static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1300 struct bnxt_tpa_info *tpa_info,
1301 struct rx_tpa_end_cmp *tpa_end,
1302 struct rx_tpa_end_cmp_ext *tpa_end1,
1303 struct sk_buff *skb)
1304{
1305#ifdef CONFIG_INET
1306 int payload_off;
1307 u16 segs;
1308
1309 segs = TPA_END_TPA_SEGS(tpa_end);
1310 if (segs == 1)
1311 return skb;
1312
1313 NAPI_GRO_CB(skb)->count = segs;
1314 skb_shinfo(skb)->gso_size =
1315 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1316 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1317 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1318 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1319 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1320 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
5910906c
MC		 1321 if (likely(skb))
1322 tcp_gro_complete(skb);
309369c9
MC		 1323#endif
1324 return skb;
1325}
1326
ee5c7fb3
SP		 1327/* Given the cfa_code of a received packet determine which
1328 * netdev (vf-rep or PF) the packet is destined to.
1329 */
1330static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1331{
1332 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1333
1334 /* if vf-rep dev is NULL, the must belongs to the PF */
1335 return dev ? dev : bp->dev;
1336}
1337
c0c050c5
MC		 1338static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1339 struct bnxt_napi *bnapi,
1340 u32 *raw_cons,
1341 struct rx_tpa_end_cmp *tpa_end,
1342 struct rx_tpa_end_cmp_ext *tpa_end1,
4e5dbbda 1343 u8 *event)
c0c050c5
MC		 1344{
1345 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1346 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5 1347 u8 agg_id = TPA_END_AGG_ID(tpa_end);
6bb19474 1348 u8 *data_ptr, agg_bufs;
c0c050c5
MC		 1349 u16 cp_cons = RING_CMP(*raw_cons);
1350 unsigned int len;
1351 struct bnxt_tpa_info *tpa_info;
1352 dma_addr_t mapping;
1353 struct sk_buff *skb;
6bb19474 1354 void *data;
c0c050c5 1355
fa7e2812
MC		 1356 if (unlikely(bnapi->in_reset)) {
1357 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1358
1359 if (rc < 0)
1360 return ERR_PTR(-EBUSY);
1361 return NULL;
1362 }
1363
c0c050c5
MC		 1364 tpa_info = &rxr->rx_tpa[agg_id];
1365 data = tpa_info->data;
6bb19474
MC		 1366 data_ptr = tpa_info->data_ptr;
1367 prefetch(data_ptr);
c0c050c5
MC		 1368 len = tpa_info->len;
1369 mapping = tpa_info->mapping;
1370
1371 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1372 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1373
1374 if (agg_bufs) {
1375 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1376 return ERR_PTR(-EBUSY);
1377
4e5dbbda 1378 *event |= BNXT_AGG_EVENT;
c0c050c5
MC		 1379 cp_cons = NEXT_CMP(cp_cons);
1380 }
1381
69c149e2 1382 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
c0c050c5 1383 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
69c149e2
MC		 1384 if (agg_bufs > MAX_SKB_FRAGS)
1385 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1386 agg_bufs, (int)MAX_SKB_FRAGS);
c0c050c5
MC		 1387 return NULL;
1388 }
1389
1390 if (len <= bp->rx_copy_thresh) {
6bb19474 1391 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
c0c050c5
MC		 1392 if (!skb) {
1393 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1394 return NULL;
1395 }
1396 } else {
1397 u8 *new_data;
1398 dma_addr_t new_mapping;
1399
1400 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1401 if (!new_data) {
1402 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1403 return NULL;
1404 }
1405
1406 tpa_info->data = new_data;
b3dba77c 1407 tpa_info->data_ptr = new_data + bp->rx_offset;
c0c050c5
MC		 1408 tpa_info->mapping = new_mapping;
1409
1410 skb = build_skb(data, 0);
c519fe9a
SN		 1411 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1412 bp->rx_buf_use_size, bp->rx_dir,
1413 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 1414
1415 if (!skb) {
1416 kfree(data);
1417 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1418 return NULL;
1419 }
b3dba77c 1420 skb_reserve(skb, bp->rx_offset);
c0c050c5
MC		 1421 skb_put(skb, len);
1422 }
1423
1424 if (agg_bufs) {
1425 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1426 if (!skb) {
1427 /* Page reuse already handled by bnxt_rx_pages(). */
1428 return NULL;
1429 }
1430 }
ee5c7fb3
SP		 1431
1432 skb->protocol =
1433 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
c0c050c5
MC		 1434
1435 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1436 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1437
8852ddb4
MC		 1438 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1439 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5
MC		 1440 u16 vlan_proto = tpa_info->metadata >>
1441 RX_CMP_FLAGS2_METADATA_TPID_SFT;
8852ddb4 1442 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5 1443
8852ddb4 1444 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1445 }
1446
1447 skb_checksum_none_assert(skb);
1448 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1449 skb->ip_summed = CHECKSUM_UNNECESSARY;
1450 skb->csum_level =
1451 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1452 }
1453
1454 if (TPA_END_GRO(tpa_end))
309369c9 1455 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
c0c050c5
MC		 1456
1457 return skb;
1458}
1459
ee5c7fb3
SP		 1460static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1461 struct sk_buff *skb)
1462{
1463 if (skb->dev != bp->dev) {
1464 /* this packet belongs to a vf-rep */
1465 bnxt_vf_rep_rx(bp, skb);
1466 return;
1467 }
1468 skb_record_rx_queue(skb, bnapi->index);
1469 napi_gro_receive(&bnapi->napi, skb);
1470}
1471
c0c050c5
MC		 1472/* returns the following:
1473 * 1 - 1 packet successfully received
1474 * 0 - successful TPA_START, packet not completed yet
1475 * -EBUSY - completion ring does not have all the agg buffers yet
1476 * -ENOMEM - packet aborted due to out of memory
1477 * -EIO - packet aborted due to hw error indicated in BD
1478 */
1479static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
4e5dbbda 1480 u8 *event)
c0c050c5
MC		 1481{
1482 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1483 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1484 struct net_device *dev = bp->dev;
1485 struct rx_cmp *rxcmp;
1486 struct rx_cmp_ext *rxcmp1;
1487 u32 tmp_raw_cons = *raw_cons;
ee5c7fb3 1488 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
c0c050c5
MC		 1489 struct bnxt_sw_rx_bd *rx_buf;
1490 unsigned int len;
6bb19474 1491 u8 *data_ptr, agg_bufs, cmp_type;
c0c050c5
MC		 1492 dma_addr_t dma_addr;
1493 struct sk_buff *skb;
6bb19474 1494 void *data;
c0c050c5 1495 int rc = 0;
c61fb99c 1496 u32 misc;
c0c050c5
MC		 1497
1498 rxcmp = (struct rx_cmp *)
1499 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1500
1501 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1502 cp_cons = RING_CMP(tmp_raw_cons);
1503 rxcmp1 = (struct rx_cmp_ext *)
1504 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1505
1506 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1507 return -EBUSY;
1508
1509 cmp_type = RX_CMP_TYPE(rxcmp);
1510
1511 prod = rxr->rx_prod;
1512
1513 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1514 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1515 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1516
4e5dbbda 1517 *event |= BNXT_RX_EVENT;
e7e70fa6 1518 goto next_rx_no_prod_no_len;
c0c050c5
MC		 1519
1520 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1521 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1522 (struct rx_tpa_end_cmp *)rxcmp,
4e5dbbda 1523 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
c0c050c5 1524
1fac4b2f 1525 if (IS_ERR(skb))
c0c050c5
MC		 1526 return -EBUSY;
1527
1528 rc = -ENOMEM;
1529 if (likely(skb)) {
ee5c7fb3 1530 bnxt_deliver_skb(bp, bnapi, skb);
c0c050c5
MC		 1531 rc = 1;
1532 }
4e5dbbda 1533 *event |= BNXT_RX_EVENT;
e7e70fa6 1534 goto next_rx_no_prod_no_len;
c0c050c5
MC		 1535 }
1536
1537 cons = rxcmp->rx_cmp_opaque;
1538 rx_buf = &rxr->rx_buf_ring[cons];
1539 data = rx_buf->data;
6bb19474 1540 data_ptr = rx_buf->data_ptr;
fa7e2812
MC		 1541 if (unlikely(cons != rxr->rx_next_cons)) {
1542 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1543
1544 bnxt_sched_reset(bp, rxr);
1545 return rc1;
1546 }
6bb19474 1547 prefetch(data_ptr);
c0c050c5 1548
c61fb99c
MC		 1549 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1550 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
c0c050c5
MC		 1551
1552 if (agg_bufs) {
1553 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1554 return -EBUSY;
1555
1556 cp_cons = NEXT_CMP(cp_cons);
4e5dbbda 1557 *event |= BNXT_AGG_EVENT;
c0c050c5 1558 }
4e5dbbda 1559 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1560
1561 rx_buf->data = NULL;
1562 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1563 bnxt_reuse_rx_data(rxr, cons, data);
1564 if (agg_bufs)
1565 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1566
1567 rc = -EIO;
1568 goto next_rx;
1569 }
1570
1571 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
11cd119d 1572 dma_addr = rx_buf->mapping;
c0c050c5 1573
c6d30e83
MC		 1574 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1575 rc = 1;
1576 goto next_rx;
1577 }
1578
c0c050c5 1579 if (len <= bp->rx_copy_thresh) {
6bb19474 1580 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
c0c050c5
MC		 1581 bnxt_reuse_rx_data(rxr, cons, data);
1582 if (!skb) {
1583 rc = -ENOMEM;
1584 goto next_rx;
1585 }
1586 } else {
c61fb99c
MC		 1587 u32 payload;
1588
c6d30e83
MC		 1589 if (rx_buf->data_ptr == data_ptr)
1590 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1591 else
1592 payload = 0;
6bb19474 1593 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
c61fb99c 1594 payload | len);
c0c050c5
MC		 1595 if (!skb) {
1596 rc = -ENOMEM;
1597 goto next_rx;
1598 }
1599 }
1600
1601 if (agg_bufs) {
1602 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1603 if (!skb) {
1604 rc = -ENOMEM;
1605 goto next_rx;
1606 }
1607 }
1608
1609 if (RX_CMP_HASH_VALID(rxcmp)) {
1610 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1611 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1612
1613 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1614 if (hash_type != 1 && hash_type != 3)
1615 type = PKT_HASH_TYPE_L3;
1616 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1617 }
1618
ee5c7fb3
SP		 1619 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1620 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
c0c050c5 1621
8852ddb4
MC		 1622 if ((rxcmp1->rx_cmp_flags2 &
1623 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1624 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5 1625 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
8852ddb4 1626 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5
MC		 1627 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1628
8852ddb4 1629 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1630 }
1631
1632 skb_checksum_none_assert(skb);
1633 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1634 if (dev->features & NETIF_F_RXCSUM) {
1635 skb->ip_summed = CHECKSUM_UNNECESSARY;
1636 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1637 }
1638 } else {
665e350d
SB		 1639 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1640 if (dev->features & NETIF_F_RXCSUM)
1641 cpr->rx_l4_csum_errors++;
1642 }
c0c050c5
MC		 1643 }
1644
ee5c7fb3 1645 bnxt_deliver_skb(bp, bnapi, skb);
c0c050c5
MC		 1646 rc = 1;
1647
1648next_rx:
1649 rxr->rx_prod = NEXT_RX(prod);
376a5b86 1650 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5 1651
6a8788f2
AG		 1652 cpr->rx_packets += 1;
1653 cpr->rx_bytes += len;
e7e70fa6
CIK		 1654
1655next_rx_no_prod_no_len:
c0c050c5
MC		 1656 *raw_cons = tmp_raw_cons;
1657
1658 return rc;
1659}
1660
2270bc5d
MC		 1661/* In netpoll mode, if we are using a combined completion ring, we need to
1662 * discard the rx packets and recycle the buffers.
1663 */
1664static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1665 u32 *raw_cons, u8 *event)
1666{
1667 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1668 u32 tmp_raw_cons = *raw_cons;
1669 struct rx_cmp_ext *rxcmp1;
1670 struct rx_cmp *rxcmp;
1671 u16 cp_cons;
1672 u8 cmp_type;
1673
1674 cp_cons = RING_CMP(tmp_raw_cons);
1675 rxcmp = (struct rx_cmp *)
1676 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1677
1678 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1679 cp_cons = RING_CMP(tmp_raw_cons);
1680 rxcmp1 = (struct rx_cmp_ext *)
1681 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1682
1683 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1684 return -EBUSY;
1685
1686 cmp_type = RX_CMP_TYPE(rxcmp);
1687 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1688 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1689 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1690 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1691 struct rx_tpa_end_cmp_ext *tpa_end1;
1692
1693 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1694 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1695 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1696 }
1697 return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1698}
1699
4bb13abf 1700#define BNXT_GET_EVENT_PORT(data) \
87c374de
MC		 1701 ((data) & \
1702 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
4bb13abf 1703
c0c050c5
MC		 1704static int bnxt_async_event_process(struct bnxt *bp,
1705 struct hwrm_async_event_cmpl *cmpl)
1706{
1707 u16 event_id = le16_to_cpu(cmpl->event_id);
1708
1709 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1710 switch (event_id) {
87c374de 1711 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
8cbde117
MC		 1712 u32 data1 = le32_to_cpu(cmpl->event_data1);
1713 struct bnxt_link_info *link_info = &bp->link_info;
1714
1715 if (BNXT_VF(bp))
1716 goto async_event_process_exit;
a8168b6c
MC		 1717
1718 /* print unsupported speed warning in forced speed mode only */
1719 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1720 (data1 & 0x20000)) {
8cbde117
MC		 1721 u16 fw_speed = link_info->force_link_speed;
1722 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1723
a8168b6c
MC		 1724 if (speed != SPEED_UNKNOWN)
1725 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1726 speed);
8cbde117 1727 }
286ef9d6 1728 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
8cbde117
MC		 1729 /* fall thru */
1730 }
87c374de 1731 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
c0c050c5 1732 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368 1733 break;
87c374de 1734 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
19241368 1735 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5 1736 break;
87c374de 1737 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
4bb13abf
MC		 1738 u32 data1 = le32_to_cpu(cmpl->event_data1);
1739 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1740
1741 if (BNXT_VF(bp))
1742 break;
1743
1744 if (bp->pf.port_id != port_id)
1745 break;
1746
4bb13abf
MC		 1747 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1748 break;
1749 }
87c374de 1750 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
fc0f1929
MC		 1751 if (BNXT_PF(bp))
1752 goto async_event_process_exit;
1753 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1754 break;
c0c050c5 1755 default:
19241368 1756 goto async_event_process_exit;
c0c050c5 1757 }
c213eae8 1758 bnxt_queue_sp_work(bp);
19241368 1759async_event_process_exit:
a588e458 1760 bnxt_ulp_async_events(bp, cmpl);
c0c050c5
MC		 1761 return 0;
1762}
1763
1764static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1765{
1766 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1767 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1768 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1769 (struct hwrm_fwd_req_cmpl *)txcmp;
1770
1771 switch (cmpl_type) {
1772 case CMPL_BASE_TYPE_HWRM_DONE:
1773 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1774 if (seq_id == bp->hwrm_intr_seq_id)
1775 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1776 else
1777 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1778 break;
1779
1780 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1781 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1782
1783 if ((vf_id < bp->pf.first_vf_id) ||
1784 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1785 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1786 vf_id);
1787 return -EINVAL;
1788 }
1789
1790 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1791 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
c213eae8 1792 bnxt_queue_sp_work(bp);
c0c050c5
MC		 1793 break;
1794
1795 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1796 bnxt_async_event_process(bp,
1797 (struct hwrm_async_event_cmpl *)txcmp);
1798
1799 default:
1800 break;
1801 }
1802
1803 return 0;
1804}
1805
1806static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1807{
1808 struct bnxt_napi *bnapi = dev_instance;
1809 struct bnxt *bp = bnapi->bp;
1810 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1811 u32 cons = RING_CMP(cpr->cp_raw_cons);
1812
6a8788f2 1813 cpr->event_ctr++;
c0c050c5
MC		 1814 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1815 napi_schedule(&bnapi->napi);
1816 return IRQ_HANDLED;
1817}
1818
1819static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1820{
1821 u32 raw_cons = cpr->cp_raw_cons;
1822 u16 cons = RING_CMP(raw_cons);
1823 struct tx_cmp *txcmp;
1824
1825 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1826
1827 return TX_CMP_VALID(txcmp, raw_cons);
1828}
1829
c0c050c5
MC		 1830static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1831{
1832 struct bnxt_napi *bnapi = dev_instance;
1833 struct bnxt *bp = bnapi->bp;
1834 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1835 u32 cons = RING_CMP(cpr->cp_raw_cons);
1836 u32 int_status;
1837
1838 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1839
1840 if (!bnxt_has_work(bp, cpr)) {
11809490 1841 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1842 /* return if erroneous interrupt */
1843 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1844 return IRQ_NONE;
1845 }
1846
1847 /* disable ring IRQ */
1848 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1849
1850 /* Return here if interrupt is shared and is disabled. */
1851 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1852 return IRQ_HANDLED;
1853
1854 napi_schedule(&bnapi->napi);
1855 return IRQ_HANDLED;
1856}
1857
1858static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1859{
1860 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1861 u32 raw_cons = cpr->cp_raw_cons;
1862 u32 cons;
1863 int tx_pkts = 0;
1864 int rx_pkts = 0;
4e5dbbda 1865 u8 event = 0;
c0c050c5
MC		 1866 struct tx_cmp *txcmp;
1867
1868 while (1) {
1869 int rc;
1870
1871 cons = RING_CMP(raw_cons);
1872 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1873
1874 if (!TX_CMP_VALID(txcmp, raw_cons))
1875 break;
1876
67a95e20
MC		 1877 /* The valid test of the entry must be done first before
1878 * reading any further.
1879 */
b67daab0 1880 dma_rmb();
c0c050c5
MC		 1881 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1882 tx_pkts++;
1883 /* return full budget so NAPI will complete. */
1884 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1885 rx_pkts = budget;
1886 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2270bc5d
MC		 1887 if (likely(budget))
1888 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1889 else
1890 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1891 &event);
c0c050c5
MC		 1892 if (likely(rc >= 0))
1893 rx_pkts += rc;
903649e7
MC		 1894 /* Increment rx_pkts when rc is -ENOMEM to count towards
1895 * the NAPI budget. Otherwise, we may potentially loop
1896 * here forever if we consistently cannot allocate
1897 * buffers.
1898 */
2edbdb31 1899 else if (rc == -ENOMEM && budget)
903649e7 1900 rx_pkts++;
c0c050c5
MC		 1901 else if (rc == -EBUSY) /* partial completion */
1902 break;
c0c050c5
MC		 1903 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1904 CMPL_BASE_TYPE_HWRM_DONE) ||
1905 (TX_CMP_TYPE(txcmp) ==
1906 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1907 (TX_CMP_TYPE(txcmp) ==
1908 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1909 bnxt_hwrm_handler(bp, txcmp);
1910 }
1911 raw_cons = NEXT_RAW_CMP(raw_cons);
1912
1913 if (rx_pkts == budget)
1914 break;
1915 }
1916
38413406
MC		 1917 if (event & BNXT_TX_EVENT) {
1918 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1919 void __iomem *db = txr->tx_doorbell;
1920 u16 prod = txr->tx_prod;
1921
1922 /* Sync BD data before updating doorbell */
1923 wmb();
1924
434c975a 1925 bnxt_db_write(bp, db, DB_KEY_TX | prod);
38413406
MC		 1926 }
1927
c0c050c5
MC		 1928 cpr->cp_raw_cons = raw_cons;
1929 /* ACK completion ring before freeing tx ring and producing new
1930 * buffers in rx/agg rings to prevent overflowing the completion
1931 * ring.
1932 */
1933 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1934
1935 if (tx_pkts)
fa3e93e8 1936 bnapi->tx_int(bp, bnapi, tx_pkts);
c0c050c5 1937
4e5dbbda 1938 if (event & BNXT_RX_EVENT) {
b6ab4b01 1939 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5 1940
434c975a
MC		 1941 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1942 if (event & BNXT_AGG_EVENT)
1943 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1944 DB_KEY_RX | rxr->rx_agg_prod);
c0c050c5
MC		 1945 }
1946 return rx_pkts;
1947}
1948
10bbdaf5
PS		 1949static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1950{
1951 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1952 struct bnxt *bp = bnapi->bp;
1953 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1954 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1955 struct tx_cmp *txcmp;
1956 struct rx_cmp_ext *rxcmp1;
1957 u32 cp_cons, tmp_raw_cons;
1958 u32 raw_cons = cpr->cp_raw_cons;
1959 u32 rx_pkts = 0;
4e5dbbda 1960 u8 event = 0;
10bbdaf5
PS		 1961
1962 while (1) {
1963 int rc;
1964
1965 cp_cons = RING_CMP(raw_cons);
1966 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1967
1968 if (!TX_CMP_VALID(txcmp, raw_cons))
1969 break;
1970
1971 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1972 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1973 cp_cons = RING_CMP(tmp_raw_cons);
1974 rxcmp1 = (struct rx_cmp_ext *)
1975 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1976
1977 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1978 break;
1979
1980 /* force an error to recycle the buffer */
1981 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1982 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1983
4e5dbbda 1984 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
2edbdb31 1985 if (likely(rc == -EIO) && budget)
10bbdaf5
PS		 1986 rx_pkts++;
1987 else if (rc == -EBUSY) /* partial completion */
1988 break;
1989 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1990 CMPL_BASE_TYPE_HWRM_DONE)) {
1991 bnxt_hwrm_handler(bp, txcmp);
1992 } else {
1993 netdev_err(bp->dev,
1994 "Invalid completion received on special ring\n");
1995 }
1996 raw_cons = NEXT_RAW_CMP(raw_cons);
1997
1998 if (rx_pkts == budget)
1999 break;
2000 }
2001
2002 cpr->cp_raw_cons = raw_cons;
2003 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
434c975a 2004 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
10bbdaf5 2005
434c975a
MC		 2006 if (event & BNXT_AGG_EVENT)
2007 bnxt_db_write(bp, rxr->rx_agg_doorbell,
2008 DB_KEY_RX | rxr->rx_agg_prod);
10bbdaf5
PS		 2009
2010 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
6ad20165 2011 napi_complete_done(napi, rx_pkts);
10bbdaf5
PS		 2012 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2013 }
2014 return rx_pkts;
2015}
2016
c0c050c5
MC		 2017static int bnxt_poll(struct napi_struct *napi, int budget)
2018{
2019 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2020 struct bnxt *bp = bnapi->bp;
2021 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2022 int work_done = 0;
2023
c0c050c5
MC		 2024 while (1) {
2025 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2026
2027 if (work_done >= budget)
2028 break;
2029
2030 if (!bnxt_has_work(bp, cpr)) {
e7b95691
MC		 2031 if (napi_complete_done(napi, work_done))
2032 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2033 cpr->cp_raw_cons);
c0c050c5
MC		 2034 break;
2035 }
2036 }
6a8788f2
AG		 2037 if (bp->flags & BNXT_FLAG_DIM) {
2038 struct net_dim_sample dim_sample;
2039
2040 net_dim_sample(cpr->event_ctr,
2041 cpr->rx_packets,
2042 cpr->rx_bytes,
2043 &dim_sample);
2044 net_dim(&cpr->dim, dim_sample);
2045 }
c0c050c5 2046 mmiowb();
c0c050c5
MC		 2047 return work_done;
2048}
2049
c0c050c5
MC		 2050static void bnxt_free_tx_skbs(struct bnxt *bp)
2051{
2052 int i, max_idx;
2053 struct pci_dev *pdev = bp->pdev;
2054
b6ab4b01 2055 if (!bp->tx_ring)
c0c050c5
MC		 2056 return;
2057
2058 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2059 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2060 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2061 int j;
2062
c0c050c5
MC		 2063 for (j = 0; j < max_idx;) {
2064 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2065 struct sk_buff *skb = tx_buf->skb;
2066 int k, last;
2067
2068 if (!skb) {
2069 j++;
2070 continue;
2071 }
2072
2073 tx_buf->skb = NULL;
2074
2075 if (tx_buf->is_push) {
2076 dev_kfree_skb(skb);
2077 j += 2;
2078 continue;
2079 }
2080
2081 dma_unmap_single(&pdev->dev,
2082 dma_unmap_addr(tx_buf, mapping),
2083 skb_headlen(skb),
2084 PCI_DMA_TODEVICE);
2085
2086 last = tx_buf->nr_frags;
2087 j += 2;
d612a579
MC		 2088 for (k = 0; k < last; k++, j++) {
2089 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 2090 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2091
d612a579 2092 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 2093 dma_unmap_page(
2094 &pdev->dev,
2095 dma_unmap_addr(tx_buf, mapping),
2096 skb_frag_size(frag), PCI_DMA_TODEVICE);
2097 }
2098 dev_kfree_skb(skb);
2099 }
2100 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2101 }
2102}
2103
2104static void bnxt_free_rx_skbs(struct bnxt *bp)
2105{
2106 int i, max_idx, max_agg_idx;
2107 struct pci_dev *pdev = bp->pdev;
2108
b6ab4b01 2109 if (!bp->rx_ring)
c0c050c5
MC		 2110 return;
2111
2112 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2113 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2114 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2115 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2116 int j;
2117
c0c050c5
MC		 2118 if (rxr->rx_tpa) {
2119 for (j = 0; j < MAX_TPA; j++) {
2120 struct bnxt_tpa_info *tpa_info =
2121 &rxr->rx_tpa[j];
2122 u8 *data = tpa_info->data;
2123
2124 if (!data)
2125 continue;
2126
c519fe9a
SN		 2127 dma_unmap_single_attrs(&pdev->dev,
2128 tpa_info->mapping,
2129 bp->rx_buf_use_size,
2130 bp->rx_dir,
2131 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 2132
2133 tpa_info->data = NULL;
2134
2135 kfree(data);
2136 }
2137 }
2138
2139 for (j = 0; j < max_idx; j++) {
2140 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
3ed3a83e 2141 dma_addr_t mapping = rx_buf->mapping;
6bb19474 2142 void *data = rx_buf->data;
c0c050c5
MC		 2143
2144 if (!data)
2145 continue;
2146
c0c050c5
MC		 2147 rx_buf->data = NULL;
2148
3ed3a83e
MC		 2149 if (BNXT_RX_PAGE_MODE(bp)) {
2150 mapping -= bp->rx_dma_offset;
c519fe9a
SN		 2151 dma_unmap_page_attrs(&pdev->dev, mapping,
2152 PAGE_SIZE, bp->rx_dir,
2153 DMA_ATTR_WEAK_ORDERING);
c61fb99c 2154 __free_page(data);
3ed3a83e 2155 } else {
c519fe9a
SN		 2156 dma_unmap_single_attrs(&pdev->dev, mapping,
2157 bp->rx_buf_use_size,
2158 bp->rx_dir,
2159 DMA_ATTR_WEAK_ORDERING);
c61fb99c 2160 kfree(data);
3ed3a83e 2161 }
c0c050c5
MC		 2162 }
2163
2164 for (j = 0; j < max_agg_idx; j++) {
2165 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2166 &rxr->rx_agg_ring[j];
2167 struct page *page = rx_agg_buf->page;
2168
2169 if (!page)
2170 continue;
2171
c519fe9a
SN		 2172 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2173 BNXT_RX_PAGE_SIZE,
2174 PCI_DMA_FROMDEVICE,
2175 DMA_ATTR_WEAK_ORDERING);
c0c050c5
MC		 2176
2177 rx_agg_buf->page = NULL;
2178 __clear_bit(j, rxr->rx_agg_bmap);
2179
2180 __free_page(page);
2181 }
89d0a06c
MC		 2182 if (rxr->rx_page) {
2183 __free_page(rxr->rx_page);
2184 rxr->rx_page = NULL;
2185 }
c0c050c5
MC		 2186 }
2187}
2188
2189static void bnxt_free_skbs(struct bnxt *bp)
2190{
2191 bnxt_free_tx_skbs(bp);
2192 bnxt_free_rx_skbs(bp);
2193}
2194
2195static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2196{
2197 struct pci_dev *pdev = bp->pdev;
2198 int i;
2199
2200 for (i = 0; i < ring->nr_pages; i++) {
2201 if (!ring->pg_arr[i])
2202 continue;
2203
2204 dma_free_coherent(&pdev->dev, ring->page_size,
2205 ring->pg_arr[i], ring->dma_arr[i]);
2206
2207 ring->pg_arr[i] = NULL;
2208 }
2209 if (ring->pg_tbl) {
2210 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2211 ring->pg_tbl, ring->pg_tbl_map);
2212 ring->pg_tbl = NULL;
2213 }
2214 if (ring->vmem_size && *ring->vmem) {
2215 vfree(*ring->vmem);
2216 *ring->vmem = NULL;
2217 }
2218}
2219
2220static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2221{
2222 int i;
2223 struct pci_dev *pdev = bp->pdev;
2224
2225 if (ring->nr_pages > 1) {
2226 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2227 ring->nr_pages * 8,
2228 &ring->pg_tbl_map,
2229 GFP_KERNEL);
2230 if (!ring->pg_tbl)
2231 return -ENOMEM;
2232 }
2233
2234 for (i = 0; i < ring->nr_pages; i++) {
2235 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2236 ring->page_size,
2237 &ring->dma_arr[i],
2238 GFP_KERNEL);
2239 if (!ring->pg_arr[i])
2240 return -ENOMEM;
2241
2242 if (ring->nr_pages > 1)
2243 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2244 }
2245
2246 if (ring->vmem_size) {
2247 *ring->vmem = vzalloc(ring->vmem_size);
2248 if (!(*ring->vmem))
2249 return -ENOMEM;
2250 }
2251 return 0;
2252}
2253
2254static void bnxt_free_rx_rings(struct bnxt *bp)
2255{
2256 int i;
2257
b6ab4b01 2258 if (!bp->rx_ring)
c0c050c5
MC		 2259 return;
2260
2261 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2262 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2263 struct bnxt_ring_struct *ring;
2264
c6d30e83
MC		 2265 if (rxr->xdp_prog)
2266 bpf_prog_put(rxr->xdp_prog);
2267
96a8604f
JDB		 2268 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2269 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2270
c0c050c5
MC		 2271 kfree(rxr->rx_tpa);
2272 rxr->rx_tpa = NULL;
2273
2274 kfree(rxr->rx_agg_bmap);
2275 rxr->rx_agg_bmap = NULL;
2276
2277 ring = &rxr->rx_ring_struct;
2278 bnxt_free_ring(bp, ring);
2279
2280 ring = &rxr->rx_agg_ring_struct;
2281 bnxt_free_ring(bp, ring);
2282 }
2283}
2284
2285static int bnxt_alloc_rx_rings(struct bnxt *bp)
2286{
2287 int i, rc, agg_rings = 0, tpa_rings = 0;
2288
b6ab4b01
MC		 2289 if (!bp->rx_ring)
2290 return -ENOMEM;
2291
c0c050c5
MC		 2292 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2293 agg_rings = 1;
2294
2295 if (bp->flags & BNXT_FLAG_TPA)
2296 tpa_rings = 1;
2297
2298 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2299 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2300 struct bnxt_ring_struct *ring;
2301
c0c050c5
MC		 2302 ring = &rxr->rx_ring_struct;
2303
96a8604f
JDB		 2304 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2305 if (rc < 0)
2306 return rc;
2307
c0c050c5
MC		 2308 rc = bnxt_alloc_ring(bp, ring);
2309 if (rc)
2310 return rc;
2311
2312 if (agg_rings) {
2313 u16 mem_size;
2314
2315 ring = &rxr->rx_agg_ring_struct;
2316 rc = bnxt_alloc_ring(bp, ring);
2317 if (rc)
2318 return rc;
2319
2320 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2321 mem_size = rxr->rx_agg_bmap_size / 8;
2322 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2323 if (!rxr->rx_agg_bmap)
2324 return -ENOMEM;
2325
2326 if (tpa_rings) {
2327 rxr->rx_tpa = kcalloc(MAX_TPA,
2328 sizeof(struct bnxt_tpa_info),
2329 GFP_KERNEL);
2330 if (!rxr->rx_tpa)
2331 return -ENOMEM;
2332 }
2333 }
2334 }
2335 return 0;
2336}
2337
2338static void bnxt_free_tx_rings(struct bnxt *bp)
2339{
2340 int i;
2341 struct pci_dev *pdev = bp->pdev;
2342
b6ab4b01 2343 if (!bp->tx_ring)
c0c050c5
MC		 2344 return;
2345
2346 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2347 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2348 struct bnxt_ring_struct *ring;
2349
c0c050c5
MC		 2350 if (txr->tx_push) {
2351 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2352 txr->tx_push, txr->tx_push_mapping);
2353 txr->tx_push = NULL;
2354 }
2355
2356 ring = &txr->tx_ring_struct;
2357
2358 bnxt_free_ring(bp, ring);
2359 }
2360}
2361
2362static int bnxt_alloc_tx_rings(struct bnxt *bp)
2363{
2364 int i, j, rc;
2365 struct pci_dev *pdev = bp->pdev;
2366
2367 bp->tx_push_size = 0;
2368 if (bp->tx_push_thresh) {
2369 int push_size;
2370
2371 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2372 bp->tx_push_thresh);
2373
4419dbe6 2374 if (push_size > 256) {
c0c050c5
MC		 2375 push_size = 0;
2376 bp->tx_push_thresh = 0;
2377 }
2378
2379 bp->tx_push_size = push_size;
2380 }
2381
2382 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2383 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2384 struct bnxt_ring_struct *ring;
2385
c0c050c5
MC		 2386 ring = &txr->tx_ring_struct;
2387
2388 rc = bnxt_alloc_ring(bp, ring);
2389 if (rc)
2390 return rc;
2391
2392 if (bp->tx_push_size) {
c0c050c5
MC		 2393 dma_addr_t mapping;
2394
2395 /* One pre-allocated DMA buffer to backup
2396 * TX push operation
2397 */
2398 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2399 bp->tx_push_size,
2400 &txr->tx_push_mapping,
2401 GFP_KERNEL);
2402
2403 if (!txr->tx_push)
2404 return -ENOMEM;
2405
c0c050c5
MC		 2406 mapping = txr->tx_push_mapping +
2407 sizeof(struct tx_push_bd);
4419dbe6 2408 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 2409
4419dbe6 2410 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5
MC		 2411 }
2412 ring->queue_id = bp->q_info[j].queue_id;
5f449249
MC		 2413 if (i < bp->tx_nr_rings_xdp)
2414 continue;
c0c050c5
MC		 2415 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2416 j++;
2417 }
2418 return 0;
2419}
2420
2421static void bnxt_free_cp_rings(struct bnxt *bp)
2422{
2423 int i;
2424
2425 if (!bp->bnapi)
2426 return;
2427
2428 for (i = 0; i < bp->cp_nr_rings; i++) {
2429 struct bnxt_napi *bnapi = bp->bnapi[i];
2430 struct bnxt_cp_ring_info *cpr;
2431 struct bnxt_ring_struct *ring;
2432
2433 if (!bnapi)
2434 continue;
2435
2436 cpr = &bnapi->cp_ring;
2437 ring = &cpr->cp_ring_struct;
2438
2439 bnxt_free_ring(bp, ring);
2440 }
2441}
2442
2443static int bnxt_alloc_cp_rings(struct bnxt *bp)
2444{
2445 int i, rc;
2446
2447 for (i = 0; i < bp->cp_nr_rings; i++) {
2448 struct bnxt_napi *bnapi = bp->bnapi[i];
2449 struct bnxt_cp_ring_info *cpr;
2450 struct bnxt_ring_struct *ring;
2451
2452 if (!bnapi)
2453 continue;
2454
2455 cpr = &bnapi->cp_ring;
2456 ring = &cpr->cp_ring_struct;
2457
2458 rc = bnxt_alloc_ring(bp, ring);
2459 if (rc)
2460 return rc;
2461 }
2462 return 0;
2463}
2464
2465static void bnxt_init_ring_struct(struct bnxt *bp)
2466{
2467 int i;
2468
2469 for (i = 0; i < bp->cp_nr_rings; i++) {
2470 struct bnxt_napi *bnapi = bp->bnapi[i];
2471 struct bnxt_cp_ring_info *cpr;
2472 struct bnxt_rx_ring_info *rxr;
2473 struct bnxt_tx_ring_info *txr;
2474 struct bnxt_ring_struct *ring;
2475
2476 if (!bnapi)
2477 continue;
2478
2479 cpr = &bnapi->cp_ring;
2480 ring = &cpr->cp_ring_struct;
2481 ring->nr_pages = bp->cp_nr_pages;
2482 ring->page_size = HW_CMPD_RING_SIZE;
2483 ring->pg_arr = (void **)cpr->cp_desc_ring;
2484 ring->dma_arr = cpr->cp_desc_mapping;
2485 ring->vmem_size = 0;
2486
b6ab4b01 2487 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2488 if (!rxr)
2489 goto skip_rx;
2490
c0c050c5
MC		 2491 ring = &rxr->rx_ring_struct;
2492 ring->nr_pages = bp->rx_nr_pages;
2493 ring->page_size = HW_RXBD_RING_SIZE;
2494 ring->pg_arr = (void **)rxr->rx_desc_ring;
2495 ring->dma_arr = rxr->rx_desc_mapping;
2496 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2497 ring->vmem = (void **)&rxr->rx_buf_ring;
2498
2499 ring = &rxr->rx_agg_ring_struct;
2500 ring->nr_pages = bp->rx_agg_nr_pages;
2501 ring->page_size = HW_RXBD_RING_SIZE;
2502 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2503 ring->dma_arr = rxr->rx_agg_desc_mapping;
2504 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2505 ring->vmem = (void **)&rxr->rx_agg_ring;
2506
3b2b7d9d 2507skip_rx:
b6ab4b01 2508 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2509 if (!txr)
2510 continue;
2511
c0c050c5
MC		 2512 ring = &txr->tx_ring_struct;
2513 ring->nr_pages = bp->tx_nr_pages;
2514 ring->page_size = HW_RXBD_RING_SIZE;
2515 ring->pg_arr = (void **)txr->tx_desc_ring;
2516 ring->dma_arr = txr->tx_desc_mapping;
2517 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2518 ring->vmem = (void **)&txr->tx_buf_ring;
2519 }
2520}
2521
2522static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2523{
2524 int i;
2525 u32 prod;
2526 struct rx_bd **rx_buf_ring;
2527
2528 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2529 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2530 int j;
2531 struct rx_bd *rxbd;
2532
2533 rxbd = rx_buf_ring[i];
2534 if (!rxbd)
2535 continue;
2536
2537 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2538 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2539 rxbd->rx_bd_opaque = prod;
2540 }
2541 }
2542}
2543
2544static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2545{
2546 struct net_device *dev = bp->dev;
c0c050c5
MC		 2547 struct bnxt_rx_ring_info *rxr;
2548 struct bnxt_ring_struct *ring;
2549 u32 prod, type;
2550 int i;
2551
c0c050c5
MC		 2552 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2553 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2554
2555 if (NET_IP_ALIGN == 2)
2556 type |= RX_BD_FLAGS_SOP;
2557
b6ab4b01 2558 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 2559 ring = &rxr->rx_ring_struct;
2560 bnxt_init_rxbd_pages(ring, type);
2561
c6d30e83
MC		 2562 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2563 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2564 if (IS_ERR(rxr->xdp_prog)) {
2565 int rc = PTR_ERR(rxr->xdp_prog);
2566
2567 rxr->xdp_prog = NULL;
2568 return rc;
2569 }
2570 }
c0c050c5
MC		 2571 prod = rxr->rx_prod;
2572 for (i = 0; i < bp->rx_ring_size; i++) {
2573 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2574 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2575 ring_nr, i, bp->rx_ring_size);
2576 break;
2577 }
2578 prod = NEXT_RX(prod);
2579 }
2580 rxr->rx_prod = prod;
2581 ring->fw_ring_id = INVALID_HW_RING_ID;
2582
edd0c2cc
MC		 2583 ring = &rxr->rx_agg_ring_struct;
2584 ring->fw_ring_id = INVALID_HW_RING_ID;
2585
c0c050c5
MC		 2586 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2587 return 0;
2588
2839f28b 2589 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
c0c050c5
MC		 2590 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2591
2592 bnxt_init_rxbd_pages(ring, type);
2593
2594 prod = rxr->rx_agg_prod;
2595 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2596 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2597 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2598 ring_nr, i, bp->rx_ring_size);
2599 break;
2600 }
2601 prod = NEXT_RX_AGG(prod);
2602 }
2603 rxr->rx_agg_prod = prod;
c0c050c5
MC		 2604
2605 if (bp->flags & BNXT_FLAG_TPA) {
2606 if (rxr->rx_tpa) {
2607 u8 *data;
2608 dma_addr_t mapping;
2609
2610 for (i = 0; i < MAX_TPA; i++) {
2611 data = __bnxt_alloc_rx_data(bp, &mapping,
2612 GFP_KERNEL);
2613 if (!data)
2614 return -ENOMEM;
2615
2616 rxr->rx_tpa[i].data = data;
b3dba77c 2617 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
c0c050c5
MC		 2618 rxr->rx_tpa[i].mapping = mapping;
2619 }
2620 } else {
2621 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2622 return -ENOMEM;
2623 }
2624 }
2625
2626 return 0;
2627}
2628
2247925f
SP		 2629static void bnxt_init_cp_rings(struct bnxt *bp)
2630{
2631 int i;
2632
2633 for (i = 0; i < bp->cp_nr_rings; i++) {
2634 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2635 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2636
2637 ring->fw_ring_id = INVALID_HW_RING_ID;
6a8788f2
AG		 2638 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2639 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2247925f
SP		 2640 }
2641}
2642
c0c050c5
MC		 2643static int bnxt_init_rx_rings(struct bnxt *bp)
2644{
2645 int i, rc = 0;
2646
c61fb99c 2647 if (BNXT_RX_PAGE_MODE(bp)) {
c6d30e83
MC		 2648 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2649 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
c61fb99c
MC		 2650 } else {
2651 bp->rx_offset = BNXT_RX_OFFSET;
2652 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2653 }
b3dba77c 2654
c0c050c5
MC		 2655 for (i = 0; i < bp->rx_nr_rings; i++) {
2656 rc = bnxt_init_one_rx_ring(bp, i);
2657 if (rc)
2658 break;
2659 }
2660
2661 return rc;
2662}
2663
2664static int bnxt_init_tx_rings(struct bnxt *bp)
2665{
2666 u16 i;
2667
2668 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2669 MAX_SKB_FRAGS + 1);
2670
2671 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2672 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2673 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2674
2675 ring->fw_ring_id = INVALID_HW_RING_ID;
2676 }
2677
2678 return 0;
2679}
2680
2681static void bnxt_free_ring_grps(struct bnxt *bp)
2682{
2683 kfree(bp->grp_info);
2684 bp->grp_info = NULL;
2685}
2686
2687static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2688{
2689 int i;
2690
2691 if (irq_re_init) {
2692 bp->grp_info = kcalloc(bp->cp_nr_rings,
2693 sizeof(struct bnxt_ring_grp_info),
2694 GFP_KERNEL);
2695 if (!bp->grp_info)
2696 return -ENOMEM;
2697 }
2698 for (i = 0; i < bp->cp_nr_rings; i++) {
2699 if (irq_re_init)
2700 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2701 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2702 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2703 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2704 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2705 }
2706 return 0;
2707}
2708
2709static void bnxt_free_vnics(struct bnxt *bp)
2710{
2711 kfree(bp->vnic_info);
2712 bp->vnic_info = NULL;
2713 bp->nr_vnics = 0;
2714}
2715
2716static int bnxt_alloc_vnics(struct bnxt *bp)
2717{
2718 int num_vnics = 1;
2719
2720#ifdef CONFIG_RFS_ACCEL
2721 if (bp->flags & BNXT_FLAG_RFS)
2722 num_vnics += bp->rx_nr_rings;
2723#endif
2724
dc52c6c7
PS		 2725 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2726 num_vnics++;
2727
c0c050c5
MC		 2728 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2729 GFP_KERNEL);
2730 if (!bp->vnic_info)
2731 return -ENOMEM;
2732
2733 bp->nr_vnics = num_vnics;
2734 return 0;
2735}
2736
2737static void bnxt_init_vnics(struct bnxt *bp)
2738{
2739 int i;
2740
2741 for (i = 0; i < bp->nr_vnics; i++) {
2742 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2743
2744 vnic->fw_vnic_id = INVALID_HW_RING_ID;
94ce9caa
PS		 2745 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2746 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 2747 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2748
2749 if (bp->vnic_info[i].rss_hash_key) {
2750 if (i == 0)
2751 prandom_bytes(vnic->rss_hash_key,
2752 HW_HASH_KEY_SIZE);
2753 else
2754 memcpy(vnic->rss_hash_key,
2755 bp->vnic_info[0].rss_hash_key,
2756 HW_HASH_KEY_SIZE);
2757 }
2758 }
2759}
2760
2761static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2762{
2763 int pages;
2764
2765 pages = ring_size / desc_per_pg;
2766
2767 if (!pages)
2768 return 1;
2769
2770 pages++;
2771
2772 while (pages & (pages - 1))
2773 pages++;
2774
2775 return pages;
2776}
2777
c6d30e83 2778void bnxt_set_tpa_flags(struct bnxt *bp)
c0c050c5
MC		 2779{
2780 bp->flags &= ~BNXT_FLAG_TPA;
341138c3
MC		 2781 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2782 return;
c0c050c5
MC		 2783 if (bp->dev->features & NETIF_F_LRO)
2784 bp->flags |= BNXT_FLAG_LRO;
1054aee8 2785 else if (bp->dev->features & NETIF_F_GRO_HW)
c0c050c5
MC		 2786 bp->flags |= BNXT_FLAG_GRO;
2787}
2788
2789/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2790 * be set on entry.
2791 */
2792void bnxt_set_ring_params(struct bnxt *bp)
2793{
2794 u32 ring_size, rx_size, rx_space;
2795 u32 agg_factor = 0, agg_ring_size = 0;
2796
2797 /* 8 for CRC and VLAN */
2798 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2799
2800 rx_space = rx_size + NET_SKB_PAD +
2801 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2802
2803 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2804 ring_size = bp->rx_ring_size;
2805 bp->rx_agg_ring_size = 0;
2806 bp->rx_agg_nr_pages = 0;
2807
2808 if (bp->flags & BNXT_FLAG_TPA)
2839f28b 2809 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
c0c050c5
MC		 2810
2811 bp->flags &= ~BNXT_FLAG_JUMBO;
bdbd1eb5 2812 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
c0c050c5
MC		 2813 u32 jumbo_factor;
2814
2815 bp->flags |= BNXT_FLAG_JUMBO;
2816 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2817 if (jumbo_factor > agg_factor)
2818 agg_factor = jumbo_factor;
2819 }
2820 agg_ring_size = ring_size * agg_factor;
2821
2822 if (agg_ring_size) {
2823 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2824 RX_DESC_CNT);
2825 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2826 u32 tmp = agg_ring_size;
2827
2828 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2829 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2830 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2831 tmp, agg_ring_size);
2832 }
2833 bp->rx_agg_ring_size = agg_ring_size;
2834 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2835 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2836 rx_space = rx_size + NET_SKB_PAD +
2837 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2838 }
2839
2840 bp->rx_buf_use_size = rx_size;
2841 bp->rx_buf_size = rx_space;
2842
2843 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2844 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2845
2846 ring_size = bp->tx_ring_size;
2847 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2848 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2849
2850 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2851 bp->cp_ring_size = ring_size;
2852
2853 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2854 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2855 bp->cp_nr_pages = MAX_CP_PAGES;
2856 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2857 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2858 ring_size, bp->cp_ring_size);
2859 }
2860 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2861 bp->cp_ring_mask = bp->cp_bit - 1;
2862}
2863
96a8604f
JDB		 2864/* Changing allocation mode of RX rings.
2865 * TODO: Update when extending xdp_rxq_info to support allocation modes.
2866 */
c61fb99c 2867int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
6bb19474 2868{
c61fb99c
MC		 2869 if (page_mode) {
2870 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2871 return -EOPNOTSUPP;
7eb9bb3a
MC		 2872 bp->dev->max_mtu =
2873 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
c61fb99c
MC		 2874 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2875 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
c61fb99c
MC		 2876 bp->rx_dir = DMA_BIDIRECTIONAL;
2877 bp->rx_skb_func = bnxt_rx_page_skb;
1054aee8
MC		 2878 /* Disable LRO or GRO_HW */
2879 netdev_update_features(bp->dev);
c61fb99c 2880 } else {
7eb9bb3a 2881 bp->dev->max_mtu = bp->max_mtu;
c61fb99c
MC		 2882 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2883 bp->rx_dir = DMA_FROM_DEVICE;
2884 bp->rx_skb_func = bnxt_rx_skb;
2885 }
6bb19474
MC		 2886 return 0;
2887}
2888
c0c050c5
MC		 2889static void bnxt_free_vnic_attributes(struct bnxt *bp)
2890{
2891 int i;
2892 struct bnxt_vnic_info *vnic;
2893 struct pci_dev *pdev = bp->pdev;
2894
2895 if (!bp->vnic_info)
2896 return;
2897
2898 for (i = 0; i < bp->nr_vnics; i++) {
2899 vnic = &bp->vnic_info[i];
2900
2901 kfree(vnic->fw_grp_ids);
2902 vnic->fw_grp_ids = NULL;
2903
2904 kfree(vnic->uc_list);
2905 vnic->uc_list = NULL;
2906
2907 if (vnic->mc_list) {
2908 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2909 vnic->mc_list, vnic->mc_list_mapping);
2910 vnic->mc_list = NULL;
2911 }
2912
2913 if (vnic->rss_table) {
2914 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2915 vnic->rss_table,
2916 vnic->rss_table_dma_addr);
2917 vnic->rss_table = NULL;
2918 }
2919
2920 vnic->rss_hash_key = NULL;
2921 vnic->flags = 0;
2922 }
2923}
2924
2925static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2926{
2927 int i, rc = 0, size;
2928 struct bnxt_vnic_info *vnic;
2929 struct pci_dev *pdev = bp->pdev;
2930 int max_rings;
2931
2932 for (i = 0; i < bp->nr_vnics; i++) {
2933 vnic = &bp->vnic_info[i];
2934
2935 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2936 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2937
2938 if (mem_size > 0) {
2939 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2940 if (!vnic->uc_list) {
2941 rc = -ENOMEM;
2942 goto out;
2943 }
2944 }
2945 }
2946
2947 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2948 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2949 vnic->mc_list =
2950 dma_alloc_coherent(&pdev->dev,
2951 vnic->mc_list_size,
2952 &vnic->mc_list_mapping,
2953 GFP_KERNEL);
2954 if (!vnic->mc_list) {
2955 rc = -ENOMEM;
2956 goto out;
2957 }
2958 }
2959
2960 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2961 max_rings = bp->rx_nr_rings;
2962 else
2963 max_rings = 1;
2964
2965 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2966 if (!vnic->fw_grp_ids) {
2967 rc = -ENOMEM;
2968 goto out;
2969 }
2970
ae10ae74
MC		 2971 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2972 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2973 continue;
2974
c0c050c5
MC		 2975 /* Allocate rss table and hash key */
2976 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2977 &vnic->rss_table_dma_addr,
2978 GFP_KERNEL);
2979 if (!vnic->rss_table) {
2980 rc = -ENOMEM;
2981 goto out;
2982 }
2983
2984 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2985
2986 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2987 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2988 }
2989 return 0;
2990
2991out:
2992 return rc;
2993}
2994
2995static void bnxt_free_hwrm_resources(struct bnxt *bp)
2996{
2997 struct pci_dev *pdev = bp->pdev;
2998
2999 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3000 bp->hwrm_cmd_resp_dma_addr);
3001
3002 bp->hwrm_cmd_resp_addr = NULL;
3003 if (bp->hwrm_dbg_resp_addr) {
3004 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
3005 bp->hwrm_dbg_resp_addr,
3006 bp->hwrm_dbg_resp_dma_addr);
3007
3008 bp->hwrm_dbg_resp_addr = NULL;
3009 }
3010}
3011
3012static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3013{
3014 struct pci_dev *pdev = bp->pdev;
3015
3016 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3017 &bp->hwrm_cmd_resp_dma_addr,
3018 GFP_KERNEL);
3019 if (!bp->hwrm_cmd_resp_addr)
3020 return -ENOMEM;
3021 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
3022 HWRM_DBG_REG_BUF_SIZE,
3023 &bp->hwrm_dbg_resp_dma_addr,
3024 GFP_KERNEL);
3025 if (!bp->hwrm_dbg_resp_addr)
3026 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
3027
3028 return 0;
3029}
3030
e605db80
DK		 3031static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3032{
3033 if (bp->hwrm_short_cmd_req_addr) {
3034 struct pci_dev *pdev = bp->pdev;
3035
3036 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3037 bp->hwrm_short_cmd_req_addr,
3038 bp->hwrm_short_cmd_req_dma_addr);
3039 bp->hwrm_short_cmd_req_addr = NULL;
3040 }
3041}
3042
3043static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3044{
3045 struct pci_dev *pdev = bp->pdev;
3046
3047 bp->hwrm_short_cmd_req_addr =
3048 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3049 &bp->hwrm_short_cmd_req_dma_addr,
3050 GFP_KERNEL);
3051 if (!bp->hwrm_short_cmd_req_addr)
3052 return -ENOMEM;
3053
3054 return 0;
3055}
3056
c0c050c5
MC		 3057static void bnxt_free_stats(struct bnxt *bp)
3058{
3059 u32 size, i;
3060 struct pci_dev *pdev = bp->pdev;
3061
3bdf56c4
MC		 3062 if (bp->hw_rx_port_stats) {
3063 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3064 bp->hw_rx_port_stats,
3065 bp->hw_rx_port_stats_map);
3066 bp->hw_rx_port_stats = NULL;
3067 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3068 }
3069
c0c050c5
MC		 3070 if (!bp->bnapi)
3071 return;
3072
3073 size = sizeof(struct ctx_hw_stats);
3074
3075 for (i = 0; i < bp->cp_nr_rings; i++) {
3076 struct bnxt_napi *bnapi = bp->bnapi[i];
3077 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3078
3079 if (cpr->hw_stats) {
3080 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3081 cpr->hw_stats_map);
3082 cpr->hw_stats = NULL;
3083 }
3084 }
3085}
3086
3087static int bnxt_alloc_stats(struct bnxt *bp)
3088{
3089 u32 size, i;
3090 struct pci_dev *pdev = bp->pdev;
3091
3092 size = sizeof(struct ctx_hw_stats);
3093
3094 for (i = 0; i < bp->cp_nr_rings; i++) {
3095 struct bnxt_napi *bnapi = bp->bnapi[i];
3096 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3097
3098 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3099 &cpr->hw_stats_map,
3100 GFP_KERNEL);
3101 if (!cpr->hw_stats)
3102 return -ENOMEM;
3103
3104 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3105 }
3bdf56c4 3106
3e8060fa 3107 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3bdf56c4
MC		 3108 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3109 sizeof(struct tx_port_stats) + 1024;
3110
3111 bp->hw_rx_port_stats =
3112 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3113 &bp->hw_rx_port_stats_map,
3114 GFP_KERNEL);
3115 if (!bp->hw_rx_port_stats)
3116 return -ENOMEM;
3117
3118 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3119 512;
3120 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3121 sizeof(struct rx_port_stats) + 512;
3122 bp->flags |= BNXT_FLAG_PORT_STATS;
3123 }
c0c050c5
MC		 3124 return 0;
3125}
3126
3127static void bnxt_clear_ring_indices(struct bnxt *bp)
3128{
3129 int i;
3130
3131 if (!bp->bnapi)
3132 return;
3133
3134 for (i = 0; i < bp->cp_nr_rings; i++) {
3135 struct bnxt_napi *bnapi = bp->bnapi[i];
3136 struct bnxt_cp_ring_info *cpr;
3137 struct bnxt_rx_ring_info *rxr;
3138 struct bnxt_tx_ring_info *txr;
3139
3140 if (!bnapi)
3141 continue;
3142
3143 cpr = &bnapi->cp_ring;
3144 cpr->cp_raw_cons = 0;
3145
b6ab4b01 3146 txr = bnapi->tx_ring;
3b2b7d9d
MC		 3147 if (txr) {
3148 txr->tx_prod = 0;
3149 txr->tx_cons = 0;
3150 }
c0c050c5 3151
b6ab4b01 3152 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 3153 if (rxr) {
3154 rxr->rx_prod = 0;
3155 rxr->rx_agg_prod = 0;
3156 rxr->rx_sw_agg_prod = 0;
376a5b86 3157 rxr->rx_next_cons = 0;
3b2b7d9d 3158 }
c0c050c5
MC		 3159 }
3160}
3161
3162static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3163{
3164#ifdef CONFIG_RFS_ACCEL
3165 int i;
3166
3167 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3168 * safe to delete the hash table.
3169 */
3170 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3171 struct hlist_head *head;
3172 struct hlist_node *tmp;
3173 struct bnxt_ntuple_filter *fltr;
3174
3175 head = &bp->ntp_fltr_hash_tbl[i];
3176 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3177 hlist_del(&fltr->hash);
3178 kfree(fltr);
3179 }
3180 }
3181 if (irq_reinit) {
3182 kfree(bp->ntp_fltr_bmap);
3183 bp->ntp_fltr_bmap = NULL;
3184 }
3185 bp->ntp_fltr_count = 0;
3186#endif
3187}
3188
3189static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3190{
3191#ifdef CONFIG_RFS_ACCEL
3192 int i, rc = 0;
3193
3194 if (!(bp->flags & BNXT_FLAG_RFS))
3195 return 0;
3196
3197 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3198 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3199
3200 bp->ntp_fltr_count = 0;
ac45bd93
DC		 3201 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3202 sizeof(long),
c0c050c5
MC		 3203 GFP_KERNEL);
3204
3205 if (!bp->ntp_fltr_bmap)
3206 rc = -ENOMEM;
3207
3208 return rc;
3209#else
3210 return 0;
3211#endif
3212}
3213
3214static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3215{
3216 bnxt_free_vnic_attributes(bp);
3217 bnxt_free_tx_rings(bp);
3218 bnxt_free_rx_rings(bp);
3219 bnxt_free_cp_rings(bp);
3220 bnxt_free_ntp_fltrs(bp, irq_re_init);
3221 if (irq_re_init) {
3222 bnxt_free_stats(bp);
3223 bnxt_free_ring_grps(bp);
3224 bnxt_free_vnics(bp);
a960dec9
MC		 3225 kfree(bp->tx_ring_map);
3226 bp->tx_ring_map = NULL;
b6ab4b01
MC		 3227 kfree(bp->tx_ring);
3228 bp->tx_ring = NULL;
3229 kfree(bp->rx_ring);
3230 bp->rx_ring = NULL;
c0c050c5
MC		 3231 kfree(bp->bnapi);
3232 bp->bnapi = NULL;
3233 } else {
3234 bnxt_clear_ring_indices(bp);
3235 }
3236}
3237
3238static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3239{
01657bcd 3240 int i, j, rc, size, arr_size;
c0c050c5
MC		 3241 void *bnapi;
3242
3243 if (irq_re_init) {
3244 /* Allocate bnapi mem pointer array and mem block for
3245 * all queues
3246 */
3247 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3248 bp->cp_nr_rings);
3249 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3250 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3251 if (!bnapi)
3252 return -ENOMEM;
3253
3254 bp->bnapi = bnapi;
3255 bnapi += arr_size;
3256 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3257 bp->bnapi[i] = bnapi;
3258 bp->bnapi[i]->index = i;
3259 bp->bnapi[i]->bp = bp;
3260 }
3261
b6ab4b01
MC		 3262 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3263 sizeof(struct bnxt_rx_ring_info),
3264 GFP_KERNEL);
3265 if (!bp->rx_ring)
3266 return -ENOMEM;
3267
3268 for (i = 0; i < bp->rx_nr_rings; i++) {
3269 bp->rx_ring[i].bnapi = bp->bnapi[i];
3270 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3271 }
3272
3273 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3274 sizeof(struct bnxt_tx_ring_info),
3275 GFP_KERNEL);
3276 if (!bp->tx_ring)
3277 return -ENOMEM;
3278
a960dec9
MC		 3279 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3280 GFP_KERNEL);
3281
3282 if (!bp->tx_ring_map)
3283 return -ENOMEM;
3284
01657bcd
MC		 3285 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3286 j = 0;
3287 else
3288 j = bp->rx_nr_rings;
3289
3290 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3291 bp->tx_ring[i].bnapi = bp->bnapi[j];
3292 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
5f449249 3293 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
38413406 3294 if (i >= bp->tx_nr_rings_xdp) {
5f449249
MC		 3295 bp->tx_ring[i].txq_index = i -
3296 bp->tx_nr_rings_xdp;
38413406
MC		 3297 bp->bnapi[j]->tx_int = bnxt_tx_int;
3298 } else {
fa3e93e8 3299 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
38413406
MC		 3300 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3301 }
b6ab4b01
MC		 3302 }
3303
c0c050c5
MC		 3304 rc = bnxt_alloc_stats(bp);
3305 if (rc)
3306 goto alloc_mem_err;
3307
3308 rc = bnxt_alloc_ntp_fltrs(bp);
3309 if (rc)
3310 goto alloc_mem_err;
3311
3312 rc = bnxt_alloc_vnics(bp);
3313 if (rc)
3314 goto alloc_mem_err;
3315 }
3316
3317 bnxt_init_ring_struct(bp);
3318
3319 rc = bnxt_alloc_rx_rings(bp);
3320 if (rc)
3321 goto alloc_mem_err;
3322
3323 rc = bnxt_alloc_tx_rings(bp);
3324 if (rc)
3325 goto alloc_mem_err;
3326
3327 rc = bnxt_alloc_cp_rings(bp);
3328 if (rc)
3329 goto alloc_mem_err;
3330
3331 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3332 BNXT_VNIC_UCAST_FLAG;
3333 rc = bnxt_alloc_vnic_attributes(bp);
3334 if (rc)
3335 goto alloc_mem_err;
3336 return 0;
3337
3338alloc_mem_err:
3339 bnxt_free_mem(bp, true);
3340 return rc;
3341}
3342
9d8bc097
MC		 3343static void bnxt_disable_int(struct bnxt *bp)
3344{
3345 int i;
3346
3347 if (!bp->bnapi)
3348 return;
3349
3350 for (i = 0; i < bp->cp_nr_rings; i++) {
3351 struct bnxt_napi *bnapi = bp->bnapi[i];
3352 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
daf1f1e7 3353 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
9d8bc097 3354
daf1f1e7
MC		 3355 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3356 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
9d8bc097
MC		 3357 }
3358}
3359
3360static void bnxt_disable_int_sync(struct bnxt *bp)
3361{
3362 int i;
3363
3364 atomic_inc(&bp->intr_sem);
3365
3366 bnxt_disable_int(bp);
3367 for (i = 0; i < bp->cp_nr_rings; i++)
3368 synchronize_irq(bp->irq_tbl[i].vector);
3369}
3370
3371static void bnxt_enable_int(struct bnxt *bp)
3372{
3373 int i;
3374
3375 atomic_set(&bp->intr_sem, 0);
3376 for (i = 0; i < bp->cp_nr_rings; i++) {
3377 struct bnxt_napi *bnapi = bp->bnapi[i];
3378 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3379
3380 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3381 }
3382}
3383
c0c050c5
MC		 3384void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3385 u16 cmpl_ring, u16 target_id)
3386{
a8643e16 3387 struct input *req = request;
c0c050c5 3388
a8643e16
MC		 3389 req->req_type = cpu_to_le16(req_type);
3390 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3391 req->target_id = cpu_to_le16(target_id);
c0c050c5
MC		 3392 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3393}
3394
fbfbc485
MC		 3395static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3396 int timeout, bool silent)
c0c050c5 3397{
a11fa2be 3398 int i, intr_process, rc, tmo_count;
a8643e16 3399 struct input *req = msg;
c0c050c5
MC		 3400 u32 *data = msg;
3401 __le32 *resp_len, *valid;
3402 u16 cp_ring_id, len = 0;
3403 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
e605db80 3404 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
ebd5818c 3405 struct hwrm_short_input short_input = {0};
c0c050c5 3406
a8643e16 3407 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
c0c050c5 3408 memset(resp, 0, PAGE_SIZE);
a8643e16 3409 cp_ring_id = le16_to_cpu(req->cmpl_ring);
c0c050c5
MC		 3410 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3411
e605db80
DK		 3412 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
3413 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
e605db80
DK		 3414
3415 memcpy(short_cmd_req, req, msg_len);
3416 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3417 msg_len);
3418
3419 short_input.req_type = req->req_type;
3420 short_input.signature =
3421 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3422 short_input.size = cpu_to_le16(msg_len);
3423 short_input.req_addr =
3424 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3425
3426 data = (u32 *)&short_input;
3427 msg_len = sizeof(short_input);
3428
3429 /* Sync memory write before updating doorbell */
3430 wmb();
3431
3432 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3433 }
3434
c0c050c5
MC		 3435 /* Write request msg to hwrm channel */
3436 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3437
e605db80 3438 for (i = msg_len; i < max_req_len; i += 4)
d79979a1
MC		 3439 writel(0, bp->bar0 + i);
3440
c0c050c5
MC		 3441 /* currently supports only one outstanding message */
3442 if (intr_process)
a8643e16 3443 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
c0c050c5
MC		 3444
3445 /* Ring channel doorbell */
3446 writel(1, bp->bar0 + 0x100);
3447
ff4fe81d
MC		 3448 if (!timeout)
3449 timeout = DFLT_HWRM_CMD_TIMEOUT;
3450
c0c050c5 3451 i = 0;
a11fa2be 3452 tmo_count = timeout * 40;
c0c050c5
MC		 3453 if (intr_process) {
3454 /* Wait until hwrm response cmpl interrupt is processed */
3455 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
a11fa2be
MC		 3456 i++ < tmo_count) {
3457 usleep_range(25, 40);
c0c050c5
MC		 3458 }
3459
3460 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3461 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
a8643e16 3462 le16_to_cpu(req->req_type));
c0c050c5
MC		 3463 return -1;
3464 }
3465 } else {
3466 /* Check if response len is updated */
3467 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
a11fa2be 3468 for (i = 0; i < tmo_count; i++) {
c0c050c5
MC		 3469 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3470 HWRM_RESP_LEN_SFT;
3471 if (len)
3472 break;
a11fa2be 3473 usleep_range(25, 40);
c0c050c5
MC		 3474 }
3475
a11fa2be 3476 if (i >= tmo_count) {
c0c050c5 3477 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
a8643e16 3478 timeout, le16_to_cpu(req->req_type),
8578d6c1 3479 le16_to_cpu(req->seq_id), len);
c0c050c5
MC		 3480 return -1;
3481 }
3482
3483 /* Last word of resp contains valid bit */
3484 valid = bp->hwrm_cmd_resp_addr + len - 4;
a11fa2be 3485 for (i = 0; i < 5; i++) {
c0c050c5
MC		 3486 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3487 break;
a11fa2be 3488 udelay(1);
c0c050c5
MC		 3489 }
3490
a11fa2be 3491 if (i >= 5) {
c0c050c5 3492 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
a8643e16
MC		 3493 timeout, le16_to_cpu(req->req_type),
3494 le16_to_cpu(req->seq_id), len, *valid);
c0c050c5
MC		 3495 return -1;
3496 }
3497 }
3498
3499 rc = le16_to_cpu(resp->error_code);
fbfbc485 3500 if (rc && !silent)
c0c050c5
MC		 3501 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3502 le16_to_cpu(resp->req_type),
3503 le16_to_cpu(resp->seq_id), rc);
fbfbc485
MC		 3504 return rc;
3505}
3506
3507int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3508{
3509 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
c0c050c5
MC		 3510}
3511
cc72f3b1
MC		 3512int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3513 int timeout)
3514{
3515 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3516}
3517
c0c050c5
MC		 3518int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3519{
3520 int rc;
3521
3522 mutex_lock(&bp->hwrm_cmd_lock);
3523 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3524 mutex_unlock(&bp->hwrm_cmd_lock);
3525 return rc;
3526}
3527
90e20921
MC		 3528int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3529 int timeout)
3530{
3531 int rc;
3532
3533 mutex_lock(&bp->hwrm_cmd_lock);
3534 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3535 mutex_unlock(&bp->hwrm_cmd_lock);
3536 return rc;
3537}
3538
a1653b13
MC		 3539int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3540 int bmap_size)
c0c050c5
MC		 3541{
3542 struct hwrm_func_drv_rgtr_input req = {0};
25be8623
MC		 3543 DECLARE_BITMAP(async_events_bmap, 256);
3544 u32 *events = (u32 *)async_events_bmap;
a1653b13 3545 int i;
c0c050c5
MC		 3546
3547 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3548
3549 req.enables =
a1653b13 3550 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
c0c050c5 3551
25be8623
MC		 3552 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3553 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3554 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3555
a1653b13
MC		 3556 if (bmap && bmap_size) {
3557 for (i = 0; i < bmap_size; i++) {
3558 if (test_bit(i, bmap))
3559 __set_bit(i, async_events_bmap);
3560 }
3561 }
3562
25be8623
MC		 3563 for (i = 0; i < 8; i++)
3564 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3565
a1653b13
MC		 3566 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3567}
3568
3569static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3570{
3571 struct hwrm_func_drv_rgtr_input req = {0};
3572
3573 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3574
3575 req.enables =
3576 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3577 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3578
11f15ed3 3579 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
c0c050c5
MC		 3580 req.ver_maj = DRV_VER_MAJ;
3581 req.ver_min = DRV_VER_MIN;
3582 req.ver_upd = DRV_VER_UPD;
3583
3584 if (BNXT_PF(bp)) {
9b0436c3 3585 u32 data[8];
a1653b13 3586 int i;
c0c050c5 3587
9b0436c3
MC		 3588 memset(data, 0, sizeof(data));
3589 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3590 u16 cmd = bnxt_vf_req_snif[i];
3591 unsigned int bit, idx;
3592
3593 idx = cmd / 32;
3594 bit = cmd % 32;
3595 data[idx] |= 1 << bit;
3596 }
c0c050c5 3597
de68f5de
MC		 3598 for (i = 0; i < 8; i++)
3599 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3600
c0c050c5
MC		 3601 req.enables |=
3602 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3603 }
3604
3605 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3606}
3607
be58a0da
JH		 3608static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3609{
3610 struct hwrm_func_drv_unrgtr_input req = {0};
3611
3612 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3613 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3614}
3615
c0c050c5
MC		 3616static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3617{
3618 u32 rc = 0;
3619 struct hwrm_tunnel_dst_port_free_input req = {0};
3620
3621 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3622 req.tunnel_type = tunnel_type;
3623
3624 switch (tunnel_type) {
3625 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3626 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3627 break;
3628 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3629 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3630 break;
3631 default:
3632 break;
3633 }
3634
3635 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3636 if (rc)
3637 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3638 rc);
3639 return rc;
3640}
3641
3642static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3643 u8 tunnel_type)
3644{
3645 u32 rc = 0;
3646 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3647 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3648
3649 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3650
3651 req.tunnel_type = tunnel_type;
3652 req.tunnel_dst_port_val = port;
3653
3654 mutex_lock(&bp->hwrm_cmd_lock);
3655 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3656 if (rc) {
3657 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3658 rc);
3659 goto err_out;
3660 }
3661
57aac71b
CJ		 3662 switch (tunnel_type) {
3663 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
c0c050c5 3664 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3665 break;
3666 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
c0c050c5 3667 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3668 break;
3669 default:
3670 break;
3671 }
3672
c0c050c5
MC		 3673err_out:
3674 mutex_unlock(&bp->hwrm_cmd_lock);
3675 return rc;
3676}
3677
3678static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3679{
3680 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3681 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3682
3683 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 3684 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 3685
3686 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3687 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3688 req.mask = cpu_to_le32(vnic->rx_mask);
3689 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3690}
3691
3692#ifdef CONFIG_RFS_ACCEL
3693static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3694 struct bnxt_ntuple_filter *fltr)
3695{
3696 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3697
3698 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3699 req.ntuple_filter_id = fltr->filter_id;
3700 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3701}
3702
3703#define BNXT_NTP_FLTR_FLAGS \
3704 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3705 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3706 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3707 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3708 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3709 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3710 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3711 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3712 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3713 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3714 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3715 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3716 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 3717 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5 3718
61aad724
MC		 3719#define BNXT_NTP_TUNNEL_FLTR_FLAG \
3720 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3721
c0c050c5
MC		 3722static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3723 struct bnxt_ntuple_filter *fltr)
3724{
3725 int rc = 0;
3726 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3727 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3728 bp->hwrm_cmd_resp_addr;
3729 struct flow_keys *keys = &fltr->fkeys;
3730 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3731
3732 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
a54c4d74 3733 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
c0c050c5
MC		 3734
3735 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3736
3737 req.ethertype = htons(ETH_P_IP);
3738 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 3739 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 3740 req.ip_protocol = keys->basic.ip_proto;
3741
dda0e746
MC		 3742 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3743 int i;
3744
3745 req.ethertype = htons(ETH_P_IPV6);
3746 req.ip_addr_type =
3747 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3748 *(struct in6_addr *)&req.src_ipaddr[0] =
3749 keys->addrs.v6addrs.src;
3750 *(struct in6_addr *)&req.dst_ipaddr[0] =
3751 keys->addrs.v6addrs.dst;
3752 for (i = 0; i < 4; i++) {
3753 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3754 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3755 }
3756 } else {
3757 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3758 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3759 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3760 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3761 }
61aad724
MC		 3762 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3763 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3764 req.tunnel_type =
3765 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3766 }
c0c050c5
MC		 3767
3768 req.src_port = keys->ports.src;
3769 req.src_port_mask = cpu_to_be16(0xffff);
3770 req.dst_port = keys->ports.dst;
3771 req.dst_port_mask = cpu_to_be16(0xffff);
3772
c193554e 3773 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 3774 mutex_lock(&bp->hwrm_cmd_lock);
3775 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3776 if (!rc)
3777 fltr->filter_id = resp->ntuple_filter_id;
3778 mutex_unlock(&bp->hwrm_cmd_lock);
3779 return rc;
3780}
3781#endif
3782
3783static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3784 u8 *mac_addr)
3785{
3786 u32 rc = 0;
3787 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3788 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3789
3790 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
dc52c6c7
PS		 3791 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3792 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3793 req.flags |=
3794 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 3795 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 3796 req.enables =
3797 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 3798 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 3799 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3800 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3801 req.l2_addr_mask[0] = 0xff;
3802 req.l2_addr_mask[1] = 0xff;
3803 req.l2_addr_mask[2] = 0xff;
3804 req.l2_addr_mask[3] = 0xff;
3805 req.l2_addr_mask[4] = 0xff;
3806 req.l2_addr_mask[5] = 0xff;
3807
3808 mutex_lock(&bp->hwrm_cmd_lock);
3809 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3810 if (!rc)
3811 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3812 resp->l2_filter_id;
3813 mutex_unlock(&bp->hwrm_cmd_lock);
3814 return rc;
3815}
3816
3817static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3818{
3819 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3820 int rc = 0;
3821
3822 /* Any associated ntuple filters will also be cleared by firmware. */
3823 mutex_lock(&bp->hwrm_cmd_lock);
3824 for (i = 0; i < num_of_vnics; i++) {
3825 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3826
3827 for (j = 0; j < vnic->uc_filter_count; j++) {
3828 struct hwrm_cfa_l2_filter_free_input req = {0};
3829
3830 bnxt_hwrm_cmd_hdr_init(bp, &req,
3831 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3832
3833 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3834
3835 rc = _hwrm_send_message(bp, &req, sizeof(req),
3836 HWRM_CMD_TIMEOUT);
3837 }
3838 vnic->uc_filter_count = 0;
3839 }
3840 mutex_unlock(&bp->hwrm_cmd_lock);
3841
3842 return rc;
3843}
3844
3845static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3846{
3847 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3848 struct hwrm_vnic_tpa_cfg_input req = {0};
3849
3850 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3851
3852 if (tpa_flags) {
3853 u16 mss = bp->dev->mtu - 40;
3854 u32 nsegs, n, segs = 0, flags;
3855
3856 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3857 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3858 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3859 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3860 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3861 if (tpa_flags & BNXT_FLAG_GRO)
3862 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3863
3864 req.flags = cpu_to_le32(flags);
3865
3866 req.enables =
3867 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 3868 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3869 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 3870
3871 /* Number of segs are log2 units, and first packet is not
3872 * included as part of this units.
3873 */
2839f28b
MC		 3874 if (mss <= BNXT_RX_PAGE_SIZE) {
3875 n = BNXT_RX_PAGE_SIZE / mss;
c0c050c5
MC		 3876 nsegs = (MAX_SKB_FRAGS - 1) * n;
3877 } else {
2839f28b
MC		 3878 n = mss / BNXT_RX_PAGE_SIZE;
3879 if (mss & (BNXT_RX_PAGE_SIZE - 1))
c0c050c5
MC		 3880 n++;
3881 nsegs = (MAX_SKB_FRAGS - n) / n;
3882 }
3883
3884 segs = ilog2(nsegs);
3885 req.max_agg_segs = cpu_to_le16(segs);
3886 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 3887
3888 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 3889 }
3890 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3891
3892 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3893}
3894
3895static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3896{
3897 u32 i, j, max_rings;
3898 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3899 struct hwrm_vnic_rss_cfg_input req = {0};
3900
94ce9caa 3901 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
c0c050c5
MC		 3902 return 0;
3903
3904 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3905 if (set_rss) {
87da7f79 3906 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
dc52c6c7
PS		 3907 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3908 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3909 max_rings = bp->rx_nr_rings - 1;
3910 else
3911 max_rings = bp->rx_nr_rings;
3912 } else {
c0c050c5 3913 max_rings = 1;
dc52c6c7 3914 }
c0c050c5
MC		 3915
3916 /* Fill the RSS indirection table with ring group ids */
3917 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3918 if (j == max_rings)
3919 j = 0;
3920 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3921 }
3922
3923 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3924 req.hash_key_tbl_addr =
3925 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3926 }
94ce9caa 3927 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
c0c050c5
MC		 3928 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3929}
3930
3931static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3932{
3933 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3934 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3935
3936 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3937 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3938 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3939 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3940 req.enables =
3941 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3942 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3943 /* thresholds not implemented in firmware yet */
3944 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3945 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3946 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3947 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3948}
3949
94ce9caa
PS		 3950static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3951 u16 ctx_idx)
c0c050c5
MC		 3952{
3953 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3954
3955 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3956 req.rss_cos_lb_ctx_id =
94ce9caa 3957 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
c0c050c5
MC		 3958
3959 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
94ce9caa 3960 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
c0c050c5
MC		 3961}
3962
3963static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3964{
94ce9caa 3965 int i, j;
c0c050c5
MC		 3966
3967 for (i = 0; i < bp->nr_vnics; i++) {
3968 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3969
94ce9caa
PS		 3970 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3971 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3972 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3973 }
c0c050c5
MC		 3974 }
3975 bp->rsscos_nr_ctxs = 0;
3976}
3977
94ce9caa 3978static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
c0c050c5
MC		 3979{
3980 int rc;
3981 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3982 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3983 bp->hwrm_cmd_resp_addr;
3984
3985 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3986 -1);
3987
3988 mutex_lock(&bp->hwrm_cmd_lock);
3989 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3990 if (!rc)
94ce9caa 3991 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
c0c050c5
MC		 3992 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3993 mutex_unlock(&bp->hwrm_cmd_lock);
3994
3995 return rc;
3996}
3997
a588e458 3998int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
c0c050c5 3999{
b81a90d3 4000 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 4001 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4002 struct hwrm_vnic_cfg_input req = {0};
cf6645f8 4003 u16 def_vlan = 0;
c0c050c5
MC		 4004
4005 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
dc52c6c7
PS		 4006
4007 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
c0c050c5 4008 /* Only RSS support for now TBD: COS & LB */
dc52c6c7
PS		 4009 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4010 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4011 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4012 VNIC_CFG_REQ_ENABLES_MRU);
ae10ae74
MC		 4013 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4014 req.rss_rule =
4015 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4016 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4017 VNIC_CFG_REQ_ENABLES_MRU);
4018 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
dc52c6c7
PS		 4019 } else {
4020 req.rss_rule = cpu_to_le16(0xffff);
4021 }
94ce9caa 4022
dc52c6c7
PS		 4023 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4024 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
94ce9caa
PS		 4025 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4026 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4027 } else {
4028 req.cos_rule = cpu_to_le16(0xffff);
4029 }
4030
c0c050c5 4031 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 4032 ring = 0;
c0c050c5 4033 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 4034 ring = vnic_id - 1;
76595193
PS		 4035 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4036 ring = bp->rx_nr_rings - 1;
c0c050c5 4037
b81a90d3 4038 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5
MC		 4039 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4040 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4041
4042 req.lb_rule = cpu_to_le16(0xffff);
4043 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4044 VLAN_HLEN);
4045
cf6645f8
MC		 4046#ifdef CONFIG_BNXT_SRIOV
4047 if (BNXT_VF(bp))
4048 def_vlan = bp->vf.vlan;
4049#endif
4050 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
c0c050c5 4051 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
a588e458
MC		 4052 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4053 req.flags |=
4054 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
c0c050c5
MC		 4055
4056 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4057}
4058
4059static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4060{
4061 u32 rc = 0;
4062
4063 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4064 struct hwrm_vnic_free_input req = {0};
4065
4066 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4067 req.vnic_id =
4068 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4069
4070 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4071 if (rc)
4072 return rc;
4073 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4074 }
4075 return rc;
4076}
4077
4078static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4079{
4080 u16 i;
4081
4082 for (i = 0; i < bp->nr_vnics; i++)
4083 bnxt_hwrm_vnic_free_one(bp, i);
4084}
4085
b81a90d3
MC		 4086static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4087 unsigned int start_rx_ring_idx,
4088 unsigned int nr_rings)
c0c050c5 4089{
b81a90d3
MC		 4090 int rc = 0;
4091 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 4092 struct hwrm_vnic_alloc_input req = {0};
4093 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4094
4095 /* map ring groups to this vnic */
b81a90d3
MC		 4096 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4097 grp_idx = bp->rx_ring[i].bnapi->index;
4098 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 4099 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 4100 j, nr_rings);
c0c050c5
MC		 4101 break;
4102 }
4103 bp->vnic_info[vnic_id].fw_grp_ids[j] =
b81a90d3 4104 bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 4105 }
4106
94ce9caa
PS		 4107 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4108 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 4109 if (vnic_id == 0)
4110 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4111
4112 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4113
4114 mutex_lock(&bp->hwrm_cmd_lock);
4115 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4116 if (!rc)
4117 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4118 mutex_unlock(&bp->hwrm_cmd_lock);
4119 return rc;
4120}
4121
8fdefd63
MC		 4122static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4123{
4124 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4125 struct hwrm_vnic_qcaps_input req = {0};
4126 int rc;
4127
4128 if (bp->hwrm_spec_code < 0x10600)
4129 return 0;
4130
4131 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4132 mutex_lock(&bp->hwrm_cmd_lock);
4133 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4134 if (!rc) {
4135 if (resp->flags &
4136 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4137 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4138 }
4139 mutex_unlock(&bp->hwrm_cmd_lock);
4140 return rc;
4141}
4142
c0c050c5
MC		 4143static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4144{
4145 u16 i;
4146 u32 rc = 0;
4147
4148 mutex_lock(&bp->hwrm_cmd_lock);
4149 for (i = 0; i < bp->rx_nr_rings; i++) {
4150 struct hwrm_ring_grp_alloc_input req = {0};
4151 struct hwrm_ring_grp_alloc_output *resp =
4152 bp->hwrm_cmd_resp_addr;
b81a90d3 4153 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 4154
4155 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4156
b81a90d3
MC		 4157 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4158 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4159 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4160 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 4161
4162 rc = _hwrm_send_message(bp, &req, sizeof(req),
4163 HWRM_CMD_TIMEOUT);
4164 if (rc)
4165 break;
4166
b81a90d3
MC		 4167 bp->grp_info[grp_idx].fw_grp_id =
4168 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 4169 }
4170 mutex_unlock(&bp->hwrm_cmd_lock);
4171 return rc;
4172}
4173
4174static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4175{
4176 u16 i;
4177 u32 rc = 0;
4178 struct hwrm_ring_grp_free_input req = {0};
4179
4180 if (!bp->grp_info)
4181 return 0;
4182
4183 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4184
4185 mutex_lock(&bp->hwrm_cmd_lock);
4186 for (i = 0; i < bp->cp_nr_rings; i++) {
4187 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4188 continue;
4189 req.ring_group_id =
4190 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4191
4192 rc = _hwrm_send_message(bp, &req, sizeof(req),
4193 HWRM_CMD_TIMEOUT);
4194 if (rc)
4195 break;
4196 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4197 }
4198 mutex_unlock(&bp->hwrm_cmd_lock);
4199 return rc;
4200}
4201
4202static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4203 struct bnxt_ring_struct *ring,
4204 u32 ring_type, u32 map_index,
4205 u32 stats_ctx_id)
4206{
4207 int rc = 0, err = 0;
4208 struct hwrm_ring_alloc_input req = {0};
4209 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4210 u16 ring_id;
4211
4212 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4213
4214 req.enables = 0;
4215 if (ring->nr_pages > 1) {
4216 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4217 /* Page size is in log2 units */
4218 req.page_size = BNXT_PAGE_SHIFT;
4219 req.page_tbl_depth = 1;
4220 } else {
4221 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
4222 }
4223 req.fbo = 0;
4224 /* Association of ring index with doorbell index and MSIX number */
4225 req.logical_id = cpu_to_le16(map_index);
4226
4227 switch (ring_type) {
4228 case HWRM_RING_ALLOC_TX:
4229 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4230 /* Association of transmit ring with completion ring */
4231 req.cmpl_ring_id =
4232 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
4233 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4234 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
4235 req.queue_id = cpu_to_le16(ring->queue_id);
4236 break;
4237 case HWRM_RING_ALLOC_RX:
4238 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4239 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4240 break;
4241 case HWRM_RING_ALLOC_AGG:
4242 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4243 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4244 break;
4245 case HWRM_RING_ALLOC_CMPL:
bac9a7e0 4246 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
c0c050c5
MC		 4247 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4248 if (bp->flags & BNXT_FLAG_USING_MSIX)
4249 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4250 break;
4251 default:
4252 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4253 ring_type);
4254 return -1;
4255 }
4256
4257 mutex_lock(&bp->hwrm_cmd_lock);
4258 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4259 err = le16_to_cpu(resp->error_code);
4260 ring_id = le16_to_cpu(resp->ring_id);
4261 mutex_unlock(&bp->hwrm_cmd_lock);
4262
4263 if (rc || err) {
4264 switch (ring_type) {
bac9a7e0 4265 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
c0c050c5
MC		 4266 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4267 rc, err);
4268 return -1;
4269
4270 case RING_FREE_REQ_RING_TYPE_RX:
4271 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4272 rc, err);
4273 return -1;
4274
4275 case RING_FREE_REQ_RING_TYPE_TX:
4276 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4277 rc, err);
4278 return -1;
4279
4280 default:
4281 netdev_err(bp->dev, "Invalid ring\n");
4282 return -1;
4283 }
4284 }
4285 ring->fw_ring_id = ring_id;
4286 return rc;
4287}
4288
486b5c22
MC		 4289static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4290{
4291 int rc;
4292
4293 if (BNXT_PF(bp)) {
4294 struct hwrm_func_cfg_input req = {0};
4295
4296 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4297 req.fid = cpu_to_le16(0xffff);
4298 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4299 req.async_event_cr = cpu_to_le16(idx);
4300 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4301 } else {
4302 struct hwrm_func_vf_cfg_input req = {0};
4303
4304 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4305 req.enables =
4306 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4307 req.async_event_cr = cpu_to_le16(idx);
4308 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4309 }
4310 return rc;
4311}
4312
c0c050c5
MC		 4313static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4314{
4315 int i, rc = 0;
4316
edd0c2cc
MC		 4317 for (i = 0; i < bp->cp_nr_rings; i++) {
4318 struct bnxt_napi *bnapi = bp->bnapi[i];
4319 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4320 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
c0c050c5 4321
33e52d88 4322 cpr->cp_doorbell = bp->bar1 + i * 0x80;
edd0c2cc
MC		 4323 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4324 INVALID_STATS_CTX_ID);
4325 if (rc)
4326 goto err_out;
edd0c2cc
MC		 4327 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4328 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
486b5c22
MC		 4329
4330 if (!i) {
4331 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4332 if (rc)
4333 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4334 }
c0c050c5
MC		 4335 }
4336
edd0c2cc 4337 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4338 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 4339 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 4340 u32 map_idx = txr->bnapi->index;
4341 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
c0c050c5 4342
b81a90d3
MC		 4343 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4344 map_idx, fw_stats_ctx);
edd0c2cc
MC		 4345 if (rc)
4346 goto err_out;
b81a90d3 4347 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 4348 }
4349
edd0c2cc 4350 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4351 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4352 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 4353 u32 map_idx = rxr->bnapi->index;
c0c050c5 4354
b81a90d3
MC		 4355 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4356 map_idx, INVALID_STATS_CTX_ID);
edd0c2cc
MC		 4357 if (rc)
4358 goto err_out;
b81a90d3 4359 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
edd0c2cc 4360 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
b81a90d3 4361 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 4362 }
4363
4364 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4365 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4366 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 4367 struct bnxt_ring_struct *ring =
4368 &rxr->rx_agg_ring_struct;
b81a90d3
MC		 4369 u32 grp_idx = rxr->bnapi->index;
4370 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5
MC		 4371
4372 rc = hwrm_ring_alloc_send_msg(bp, ring,
4373 HWRM_RING_ALLOC_AGG,
b81a90d3 4374 map_idx,
c0c050c5
MC		 4375 INVALID_STATS_CTX_ID);
4376 if (rc)
4377 goto err_out;
4378
b81a90d3 4379 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 4380 writel(DB_KEY_RX | rxr->rx_agg_prod,
4381 rxr->rx_agg_doorbell);
b81a90d3 4382 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 4383 }
4384 }
4385err_out:
4386 return rc;
4387}
4388
4389static int hwrm_ring_free_send_msg(struct bnxt *bp,
4390 struct bnxt_ring_struct *ring,
4391 u32 ring_type, int cmpl_ring_id)
4392{
4393 int rc;
4394 struct hwrm_ring_free_input req = {0};
4395 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4396 u16 error_code;
4397
74608fc9 4398 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 4399 req.ring_type = ring_type;
4400 req.ring_id = cpu_to_le16(ring->fw_ring_id);
4401
4402 mutex_lock(&bp->hwrm_cmd_lock);
4403 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4404 error_code = le16_to_cpu(resp->error_code);
4405 mutex_unlock(&bp->hwrm_cmd_lock);
4406
4407 if (rc || error_code) {
4408 switch (ring_type) {
bac9a7e0 4409 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
c0c050c5
MC		 4410 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4411 rc);
4412 return rc;
4413 case RING_FREE_REQ_RING_TYPE_RX:
4414 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4415 rc);
4416 return rc;
4417 case RING_FREE_REQ_RING_TYPE_TX:
4418 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4419 rc);
4420 return rc;
4421 default:
4422 netdev_err(bp->dev, "Invalid ring\n");
4423 return -1;
4424 }
4425 }
4426 return 0;
4427}
4428
edd0c2cc 4429static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 4430{
edd0c2cc 4431 int i;
c0c050c5
MC		 4432
4433 if (!bp->bnapi)
edd0c2cc 4434 return;
c0c050c5 4435
edd0c2cc 4436 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4437 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 4438 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 4439 u32 grp_idx = txr->bnapi->index;
4440 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4441
4442 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4443 hwrm_ring_free_send_msg(bp, ring,
4444 RING_FREE_REQ_RING_TYPE_TX,
4445 close_path ? cmpl_ring_id :
4446 INVALID_HW_RING_ID);
4447 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4448 }
4449 }
4450
edd0c2cc 4451 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4452 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4453 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3
MC		 4454 u32 grp_idx = rxr->bnapi->index;
4455 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4456
4457 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4458 hwrm_ring_free_send_msg(bp, ring,
4459 RING_FREE_REQ_RING_TYPE_RX,
4460 close_path ? cmpl_ring_id :
4461 INVALID_HW_RING_ID);
4462 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4463 bp->grp_info[grp_idx].rx_fw_ring_id =
4464 INVALID_HW_RING_ID;
c0c050c5
MC		 4465 }
4466 }
4467
edd0c2cc 4468 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4469 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4470 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3
MC		 4471 u32 grp_idx = rxr->bnapi->index;
4472 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4473
4474 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4475 hwrm_ring_free_send_msg(bp, ring,
4476 RING_FREE_REQ_RING_TYPE_RX,
4477 close_path ? cmpl_ring_id :
4478 INVALID_HW_RING_ID);
4479 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4480 bp->grp_info[grp_idx].agg_fw_ring_id =
4481 INVALID_HW_RING_ID;
c0c050c5
MC		 4482 }
4483 }
4484
9d8bc097
MC		 4485 /* The completion rings are about to be freed. After that the
4486 * IRQ doorbell will not work anymore. So we need to disable
4487 * IRQ here.
4488 */
4489 bnxt_disable_int_sync(bp);
4490
edd0c2cc
MC		 4491 for (i = 0; i < bp->cp_nr_rings; i++) {
4492 struct bnxt_napi *bnapi = bp->bnapi[i];
4493 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4494 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4495
4496 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4497 hwrm_ring_free_send_msg(bp, ring,
bac9a7e0 4498 RING_FREE_REQ_RING_TYPE_L2_CMPL,
edd0c2cc
MC		 4499 INVALID_HW_RING_ID);
4500 ring->fw_ring_id = INVALID_HW_RING_ID;
4501 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4502 }
4503 }
c0c050c5
MC		 4504}
4505
674f50a5
MC		 4506static int bnxt_hwrm_get_rings(struct bnxt *bp)
4507{
4508 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4509 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4510 struct hwrm_func_qcfg_input req = {0};
4511 int rc;
4512
4513 if (bp->hwrm_spec_code < 0x10601)
4514 return 0;
4515
4516 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4517 req.fid = cpu_to_le16(0xffff);
4518 mutex_lock(&bp->hwrm_cmd_lock);
4519 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4520 if (rc) {
4521 mutex_unlock(&bp->hwrm_cmd_lock);
4522 return -EIO;
4523 }
4524
4525 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4526 if (bp->flags & BNXT_FLAG_NEW_RM) {
4527 u16 cp, stats;
4528
4529 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
4530 hw_resc->resv_hw_ring_grps =
4531 le32_to_cpu(resp->alloc_hw_ring_grps);
4532 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
4533 cp = le16_to_cpu(resp->alloc_cmpl_rings);
4534 stats = le16_to_cpu(resp->alloc_stat_ctx);
4535 cp = min_t(u16, cp, stats);
4536 hw_resc->resv_cp_rings = cp;
4537 }
4538 mutex_unlock(&bp->hwrm_cmd_lock);
4539 return 0;
4540}
4541
391be5c2
MC		 4542/* Caller must hold bp->hwrm_cmd_lock */
4543int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4544{
4545 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4546 struct hwrm_func_qcfg_input req = {0};
4547 int rc;
4548
4549 if (bp->hwrm_spec_code < 0x10601)
4550 return 0;
4551
4552 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4553 req.fid = cpu_to_le16(fid);
4554 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4555 if (!rc)
4556 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4557
4558 return rc;
4559}
4560
674f50a5
MC		 4561static int
4562bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4563 int ring_grps, int cp_rings, int vnics)
391be5c2
MC		 4564{
4565 struct hwrm_func_cfg_input req = {0};
674f50a5 4566 u32 enables = 0;
391be5c2
MC		 4567 int rc;
4568
674f50a5
MC		 4569 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4570 req.fid = cpu_to_le16(0xffff);
4571 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4572 req.num_tx_rings = cpu_to_le16(tx_rings);
4573 if (bp->flags & BNXT_FLAG_NEW_RM) {
4574 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4575 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4576 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4577 enables |= ring_grps ?
4578 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4579 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4580
4581 req.num_rx_rings = cpu_to_le16(rx_rings);
4582 req.num_hw_ring_grps = cpu_to_le16(ring_grps);
4583 req.num_cmpl_rings = cpu_to_le16(cp_rings);
4584 req.num_stat_ctxs = req.num_cmpl_rings;
4585 req.num_vnics = cpu_to_le16(vnics);
4586 }
4587 if (!enables)
391be5c2
MC		 4588 return 0;
4589
674f50a5
MC		 4590 req.enables = cpu_to_le32(enables);
4591 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4592 if (rc)
4593 return -ENOMEM;
4594
4595 if (bp->hwrm_spec_code < 0x10601)
4596 bp->hw_resc.resv_tx_rings = tx_rings;
4597
4598 rc = bnxt_hwrm_get_rings(bp);
4599 return rc;
4600}
4601
4602static int
4603bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4604 int ring_grps, int cp_rings, int vnics)
4605{
4606 struct hwrm_func_vf_cfg_input req = {0};
4607 u32 enables = 0;
4608 int rc;
4609
4610 if (!(bp->flags & BNXT_FLAG_NEW_RM)) {
4611 bp->hw_resc.resv_tx_rings = tx_rings;
391be5c2 4612 return 0;
674f50a5 4613 }
391be5c2 4614
674f50a5
MC		 4615 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4616 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4617 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4618 enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4619 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4620 enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4621 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4622
4623 req.num_tx_rings = cpu_to_le16(tx_rings);
4624 req.num_rx_rings = cpu_to_le16(rx_rings);
4625 req.num_hw_ring_grps = cpu_to_le16(ring_grps);
4626 req.num_cmpl_rings = cpu_to_le16(cp_rings);
4627 req.num_stat_ctxs = req.num_cmpl_rings;
4628 req.num_vnics = cpu_to_le16(vnics);
4629
4630 req.enables = cpu_to_le32(enables);
391be5c2 4631 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
674f50a5
MC		 4632 if (rc)
4633 return -ENOMEM;
4634
4635 rc = bnxt_hwrm_get_rings(bp);
4636 return rc;
4637}
4638
4639static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
4640 int cp, int vnic)
4641{
4642 if (BNXT_PF(bp))
4643 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic);
4644 else
4645 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic);
4646}
4647
4648static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4649 bool shared);
4650
4651static int __bnxt_reserve_rings(struct bnxt *bp)
4652{
4653 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4654 int tx = bp->tx_nr_rings;
4655 int rx = bp->rx_nr_rings;
4656 int cp = bp->cp_nr_rings;
4657 int grp, rx_rings, rc;
4658 bool sh = false;
4659 int vnic = 1;
4660
4661 if (bp->hwrm_spec_code < 0x10601)
4662 return 0;
4663
4664 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4665 sh = true;
4666 if (bp->flags & BNXT_FLAG_RFS)
4667 vnic = rx + 1;
4668 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4669 rx <<= 1;
4670
4671 grp = bp->rx_nr_rings;
4672 if (tx == hw_resc->resv_tx_rings &&
4673 (!(bp->flags & BNXT_FLAG_NEW_RM) ||
4674 (rx == hw_resc->resv_rx_rings &&
4675 grp == hw_resc->resv_hw_ring_grps &&
4676 cp == hw_resc->resv_cp_rings && vnic == hw_resc->resv_vnics)))
4677 return 0;
4678
4679 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic);
391be5c2
MC		 4680 if (rc)
4681 return rc;
4682
674f50a5
MC		 4683 tx = hw_resc->resv_tx_rings;
4684 if (bp->flags & BNXT_FLAG_NEW_RM) {
4685 rx = hw_resc->resv_rx_rings;
4686 cp = hw_resc->resv_cp_rings;
4687 grp = hw_resc->resv_hw_ring_grps;
4688 vnic = hw_resc->resv_vnics;
4689 }
4690
4691 rx_rings = rx;
4692 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4693 if (rx >= 2) {
4694 rx_rings = rx >> 1;
4695 } else {
4696 if (netif_running(bp->dev))
4697 return -ENOMEM;
4698
4699 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
4700 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4701 bp->dev->hw_features &= ~NETIF_F_LRO;
4702 bp->dev->features &= ~NETIF_F_LRO;
4703 bnxt_set_ring_params(bp);
4704 }
4705 }
4706 rx_rings = min_t(int, rx_rings, grp);
4707 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
4708 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4709 rx = rx_rings << 1;
4710 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
4711 bp->tx_nr_rings = tx;
4712 bp->rx_nr_rings = rx_rings;
4713 bp->cp_nr_rings = cp;
4714
4715 if (!tx || !rx || !cp || !grp || !vnic)
4716 return -ENOMEM;
4717
391be5c2
MC		 4718 return rc;
4719}
4720
674f50a5
MC		 4721static bool bnxt_need_reserve_rings(struct bnxt *bp)
4722{
4723 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4724 int rx = bp->rx_nr_rings;
4725 int vnic = 1;
4726
4727 if (bp->hwrm_spec_code < 0x10601)
4728 return false;
4729
4730 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
4731 return true;
4732
4733 if (bp->flags & BNXT_FLAG_RFS)
4734 vnic = rx + 1;
4735 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4736 rx <<= 1;
4737 if ((bp->flags & BNXT_FLAG_NEW_RM) &&
4738 (hw_resc->resv_rx_rings != rx ||
4739 hw_resc->resv_cp_rings != bp->cp_nr_rings ||
4740 hw_resc->resv_vnics != vnic))
4741 return true;
4742 return false;
4743}
4744
8f23d638
MC		 4745static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4746 int ring_grps, int cp_rings)
98fdbe73 4747{
8f23d638
MC		 4748 struct hwrm_func_vf_cfg_input req = {0};
4749 u32 flags, enables;
98fdbe73
MC		 4750 int rc;
4751
8f23d638 4752 if (!(bp->flags & BNXT_FLAG_NEW_RM))
98fdbe73
MC		 4753 return 0;
4754
8f23d638
MC		 4755 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4756 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
4757 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4758 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4759 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4760 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4761 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4762 enables = FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS |
4763 FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
4764 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4765 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
4766 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS |
4767 FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS;
4768
4769 req.flags = cpu_to_le32(flags);
4770 req.enables = cpu_to_le32(enables);
4771 req.num_tx_rings = cpu_to_le16(tx_rings);
4772 req.num_rx_rings = cpu_to_le16(rx_rings);
4773 req.num_cmpl_rings = cpu_to_le16(cp_rings);
4774 req.num_hw_ring_grps = cpu_to_le16(ring_grps);
4775 req.num_stat_ctxs = cpu_to_le16(cp_rings);
4776 req.num_vnics = cpu_to_le16(1);
4777 if (bp->flags & BNXT_FLAG_RFS)
4778 req.num_vnics = cpu_to_le16(rx_rings + 1);
4779 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4780 if (rc)
4781 return -ENOMEM;
4782 return 0;
4783}
4784
4785static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4786 int ring_grps, int cp_rings)
4787{
4788 struct hwrm_func_cfg_input req = {0};
4789 u32 flags, enables;
4790 int rc;
98fdbe73
MC		 4791
4792 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4793 req.fid = cpu_to_le16(0xffff);
8f23d638
MC		 4794 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
4795 enables = FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS;
98fdbe73 4796 req.num_tx_rings = cpu_to_le16(tx_rings);
8f23d638
MC		 4797 if (bp->flags & BNXT_FLAG_NEW_RM) {
4798 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4799 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4800 FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4801 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4802 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4803 enables |= FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS |
4804 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4805 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
4806 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS |
4807 FUNC_CFG_REQ_ENABLES_NUM_VNICS;
4808 req.num_rx_rings = cpu_to_le16(rx_rings);
4809 req.num_cmpl_rings = cpu_to_le16(cp_rings);
4810 req.num_hw_ring_grps = cpu_to_le16(ring_grps);
4811 req.num_stat_ctxs = cpu_to_le16(cp_rings);
4812 req.num_vnics = cpu_to_le16(1);
4813 if (bp->flags & BNXT_FLAG_RFS)
4814 req.num_vnics = cpu_to_le16(rx_rings + 1);
4815 }
4816 req.flags = cpu_to_le32(flags);
4817 req.enables = cpu_to_le32(enables);
98fdbe73
MC		 4818 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4819 if (rc)
4820 return -ENOMEM;
4821 return 0;
4822}
4823
8f23d638
MC		 4824static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4825 int ring_grps, int cp_rings)
4826{
4827 if (bp->hwrm_spec_code < 0x10801)
4828 return 0;
4829
4830 if (BNXT_PF(bp))
4831 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
4832 ring_grps, cp_rings);
4833
4834 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
4835 cp_rings);
4836}
4837
f8503969 4838static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
bb053f52
MC		 4839 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4840{
f8503969
MC		 4841 u16 val, tmr, max, flags;
4842
4843 max = hw_coal->bufs_per_record * 128;
4844 if (hw_coal->budget)
4845 max = hw_coal->bufs_per_record * hw_coal->budget;
4846
4847 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4848 req->num_cmpl_aggr_int = cpu_to_le16(val);
b153cbc5
MC		 4849
4850 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4851 val = min_t(u16, val, 63);
f8503969
MC		 4852 req->num_cmpl_dma_aggr = cpu_to_le16(val);
4853
b153cbc5
MC		 4854 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4855 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
f8503969
MC		 4856 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4857
4858 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4859 tmr = max_t(u16, tmr, 1);
4860 req->int_lat_tmr_max = cpu_to_le16(tmr);
4861
4862 /* min timer set to 1/2 of interrupt timer */
4863 val = tmr / 2;
4864 req->int_lat_tmr_min = cpu_to_le16(val);
4865
4866 /* buf timer set to 1/4 of interrupt timer */
4867 val = max_t(u16, tmr / 4, 1);
4868 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4869
4870 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4871 tmr = max_t(u16, tmr, 1);
4872 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
4873
4874 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4875 if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4876 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
bb053f52 4877 req->flags = cpu_to_le16(flags);
bb053f52
MC		 4878}
4879
6a8788f2
AG		 4880int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
4881{
4882 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
4883 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4884 struct bnxt_coal coal;
4885 unsigned int grp_idx;
4886
4887 /* Tick values in micro seconds.
4888 * 1 coal_buf x bufs_per_record = 1 completion record.
4889 */
4890 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
4891
4892 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
4893 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
4894
4895 if (!bnapi->rx_ring)
4896 return -ENODEV;
4897
4898 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4899 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4900
4901 bnxt_hwrm_set_coal_params(&coal, &req_rx);
4902
4903 grp_idx = bnapi->index;
4904 req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4905
4906 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
4907 HWRM_CMD_TIMEOUT);
4908}
4909
c0c050c5
MC		 4910int bnxt_hwrm_set_coal(struct bnxt *bp)
4911{
4912 int i, rc = 0;
dfc9c94a
MC		 4913 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4914 req_tx = {0}, *req;
c0c050c5 4915
dfc9c94a
MC		 4916 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4917 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4918 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4919 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
c0c050c5 4920
f8503969
MC		 4921 bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
4922 bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
c0c050c5
MC		 4923
4924 mutex_lock(&bp->hwrm_cmd_lock);
4925 for (i = 0; i < bp->cp_nr_rings; i++) {
dfc9c94a 4926 struct bnxt_napi *bnapi = bp->bnapi[i];
c0c050c5 4927
dfc9c94a
MC		 4928 req = &req_rx;
4929 if (!bnapi->rx_ring)
4930 req = &req_tx;
4931 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4932
4933 rc = _hwrm_send_message(bp, req, sizeof(*req),
c0c050c5
MC		 4934 HWRM_CMD_TIMEOUT);
4935 if (rc)
4936 break;
4937 }
4938 mutex_unlock(&bp->hwrm_cmd_lock);
4939 return rc;
4940}
4941
4942static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4943{
4944 int rc = 0, i;
4945 struct hwrm_stat_ctx_free_input req = {0};
4946
4947 if (!bp->bnapi)
4948 return 0;
4949
3e8060fa
PS		 4950 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4951 return 0;
4952
c0c050c5
MC		 4953 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4954
4955 mutex_lock(&bp->hwrm_cmd_lock);
4956 for (i = 0; i < bp->cp_nr_rings; i++) {
4957 struct bnxt_napi *bnapi = bp->bnapi[i];
4958 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4959
4960 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4961 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4962
4963 rc = _hwrm_send_message(bp, &req, sizeof(req),
4964 HWRM_CMD_TIMEOUT);
4965 if (rc)
4966 break;
4967
4968 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4969 }
4970 }
4971 mutex_unlock(&bp->hwrm_cmd_lock);
4972 return rc;
4973}
4974
4975static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4976{
4977 int rc = 0, i;
4978 struct hwrm_stat_ctx_alloc_input req = {0};
4979 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4980
3e8060fa
PS		 4981 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4982 return 0;
4983
c0c050c5
MC		 4984 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4985
51f30785 4986 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
c0c050c5
MC		 4987
4988 mutex_lock(&bp->hwrm_cmd_lock);
4989 for (i = 0; i < bp->cp_nr_rings; i++) {
4990 struct bnxt_napi *bnapi = bp->bnapi[i];
4991 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4992
4993 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4994
4995 rc = _hwrm_send_message(bp, &req, sizeof(req),
4996 HWRM_CMD_TIMEOUT);
4997 if (rc)
4998 break;
4999
5000 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5001
5002 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5003 }
5004 mutex_unlock(&bp->hwrm_cmd_lock);
89aa8445 5005 return rc;
c0c050c5
MC		 5006}
5007
cf6645f8
MC		 5008static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5009{
5010 struct hwrm_func_qcfg_input req = {0};
567b2abe 5011 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9315edca 5012 u16 flags;
cf6645f8
MC		 5013 int rc;
5014
5015 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5016 req.fid = cpu_to_le16(0xffff);
5017 mutex_lock(&bp->hwrm_cmd_lock);
5018 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5019 if (rc)
5020 goto func_qcfg_exit;
5021
5022#ifdef CONFIG_BNXT_SRIOV
5023 if (BNXT_VF(bp)) {
cf6645f8
MC		 5024 struct bnxt_vf_info *vf = &bp->vf;
5025
5026 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5027 }
5028#endif
9315edca
MC		 5029 flags = le16_to_cpu(resp->flags);
5030 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5031 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5032 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
5033 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5034 bp->flags |= BNXT_FLAG_FW_DCBX_AGENT;
5035 }
5036 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5037 bp->flags |= BNXT_FLAG_MULTI_HOST;
bc39f885 5038
567b2abe
SB		 5039 switch (resp->port_partition_type) {
5040 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5041 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5042 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5043 bp->port_partition_type = resp->port_partition_type;
5044 break;
5045 }
32e8239c
MC		 5046 if (bp->hwrm_spec_code < 0x10707 ||
5047 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5048 bp->br_mode = BRIDGE_MODE_VEB;
5049 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5050 bp->br_mode = BRIDGE_MODE_VEPA;
5051 else
5052 bp->br_mode = BRIDGE_MODE_UNDEF;
cf6645f8 5053
7eb9bb3a
MC		 5054 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5055 if (!bp->max_mtu)
5056 bp->max_mtu = BNXT_MAX_MTU;
5057
cf6645f8
MC		 5058func_qcfg_exit:
5059 mutex_unlock(&bp->hwrm_cmd_lock);
5060 return rc;
5061}
5062
be0dd9c4
MC		 5063static int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
5064{
5065 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5066 struct hwrm_func_resource_qcaps_input req = {0};
5067 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5068 int rc;
5069
5070 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
5071 req.fid = cpu_to_le16(0xffff);
5072
5073 mutex_lock(&bp->hwrm_cmd_lock);
5074 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5075 if (rc) {
5076 rc = -EIO;
5077 goto hwrm_func_resc_qcaps_exit;
5078 }
5079
5080 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
5081 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5082 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
5083 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5084 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
5085 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5086 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
5087 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5088 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
5089 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
5090 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
5091 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5092 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
5093 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5094 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
5095 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5096
4673d664
MC		 5097 if (BNXT_PF(bp)) {
5098 struct bnxt_pf_info *pf = &bp->pf;
5099
5100 pf->vf_resv_strategy =
5101 le16_to_cpu(resp->vf_reservation_strategy);
5102 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL)
5103 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
5104 }
be0dd9c4
MC		 5105hwrm_func_resc_qcaps_exit:
5106 mutex_unlock(&bp->hwrm_cmd_lock);
5107 return rc;
5108}
5109
5110static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 5111{
5112 int rc = 0;
5113 struct hwrm_func_qcaps_input req = {0};
5114 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6a4f2947
MC		 5115 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5116 u32 flags;
c0c050c5
MC		 5117
5118 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
5119 req.fid = cpu_to_le16(0xffff);
5120
5121 mutex_lock(&bp->hwrm_cmd_lock);
5122 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5123 if (rc)
5124 goto hwrm_func_qcaps_exit;
5125
6a4f2947
MC		 5126 flags = le32_to_cpu(resp->flags);
5127 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
e4060d30 5128 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6a4f2947 5129 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
e4060d30
MC		 5130 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
5131
7cc5a20e 5132 bp->tx_push_thresh = 0;
6a4f2947 5133 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
7cc5a20e
MC		 5134 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
5135
6a4f2947
MC		 5136 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5137 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5138 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5139 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5140 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
5141 if (!hw_resc->max_hw_ring_grps)
5142 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
5143 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5144 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5145 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5146
c0c050c5
MC		 5147 if (BNXT_PF(bp)) {
5148 struct bnxt_pf_info *pf = &bp->pf;
5149
5150 pf->fw_fid = le16_to_cpu(resp->fid);
5151 pf->port_id = le16_to_cpu(resp->port_id);
87027db1 5152 bp->dev->dev_port = pf->port_id;
11f15ed3 5153 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
c0c050c5
MC		 5154 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
5155 pf->max_vfs = le16_to_cpu(resp->max_vfs);
5156 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
5157 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
5158 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
5159 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
5160 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
5161 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6a4f2947 5162 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
c1ef146a 5163 bp->flags |= BNXT_FLAG_WOL_CAP;
c0c050c5 5164 } else {
379a80a1 5165#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 5166 struct bnxt_vf_info *vf = &bp->vf;
5167
5168 vf->fw_fid = le16_to_cpu(resp->fid);
7cc5a20e 5169 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
379a80a1 5170#endif
c0c050c5
MC		 5171 }
5172
c0c050c5
MC		 5173hwrm_func_qcaps_exit:
5174 mutex_unlock(&bp->hwrm_cmd_lock);
5175 return rc;
5176}
5177
be0dd9c4
MC		 5178static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
5179{
5180 int rc;
5181
5182 rc = __bnxt_hwrm_func_qcaps(bp);
5183 if (rc)
5184 return rc;
5185 if (bp->hwrm_spec_code >= 0x10803) {
5186 rc = bnxt_hwrm_func_resc_qcaps(bp);
5187 if (!rc)
5188 bp->flags |= BNXT_FLAG_NEW_RM;
5189 }
5190 return 0;
5191}
5192
c0c050c5
MC		 5193static int bnxt_hwrm_func_reset(struct bnxt *bp)
5194{
5195 struct hwrm_func_reset_input req = {0};
5196
5197 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
5198 req.enables = 0;
5199
5200 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
5201}
5202
5203static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
5204{
5205 int rc = 0;
5206 struct hwrm_queue_qportcfg_input req = {0};
5207 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
5208 u8 i, *qptr;
5209
5210 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
5211
5212 mutex_lock(&bp->hwrm_cmd_lock);
5213 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5214 if (rc)
5215 goto qportcfg_exit;
5216
5217 if (!resp->max_configurable_queues) {
5218 rc = -EINVAL;
5219 goto qportcfg_exit;
5220 }
5221 bp->max_tc = resp->max_configurable_queues;
87c374de 5222 bp->max_lltc = resp->max_configurable_lossless_queues;
c0c050c5
MC		 5223 if (bp->max_tc > BNXT_MAX_QUEUE)
5224 bp->max_tc = BNXT_MAX_QUEUE;
5225
441cabbb
MC		 5226 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
5227 bp->max_tc = 1;
5228
87c374de
MC		 5229 if (bp->max_lltc > bp->max_tc)
5230 bp->max_lltc = bp->max_tc;
5231
c0c050c5
MC		 5232 qptr = &resp->queue_id0;
5233 for (i = 0; i < bp->max_tc; i++) {
5234 bp->q_info[i].queue_id = *qptr++;
5235 bp->q_info[i].queue_profile = *qptr++;
5236 }
5237
5238qportcfg_exit:
5239 mutex_unlock(&bp->hwrm_cmd_lock);
5240 return rc;
5241}
5242
5243static int bnxt_hwrm_ver_get(struct bnxt *bp)
5244{
5245 int rc;
5246 struct hwrm_ver_get_input req = {0};
5247 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
e605db80 5248 u32 dev_caps_cfg;
c0c050c5 5249
e6ef2699 5250 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
c0c050c5
MC		 5251 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
5252 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
5253 req.hwrm_intf_min = HWRM_VERSION_MINOR;
5254 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
5255 mutex_lock(&bp->hwrm_cmd_lock);
5256 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5257 if (rc)
5258 goto hwrm_ver_get_exit;
5259
5260 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
5261
894aa69a
MC		 5262 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
5263 resp->hwrm_intf_min_8b << 8 |
5264 resp->hwrm_intf_upd_8b;
5265 if (resp->hwrm_intf_maj_8b < 1) {
c193554e 5266 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
894aa69a
MC		 5267 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
5268 resp->hwrm_intf_upd_8b);
c193554e 5269 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5 5270 }
431aa1eb 5271 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
894aa69a
MC		 5272 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
5273 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
c0c050c5 5274
ff4fe81d
MC		 5275 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
5276 if (!bp->hwrm_cmd_timeout)
5277 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
5278
894aa69a 5279 if (resp->hwrm_intf_maj_8b >= 1)
e6ef2699
MC		 5280 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
5281
659c805c 5282 bp->chip_num = le16_to_cpu(resp->chip_num);
3e8060fa
PS		 5283 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
5284 !resp->chip_metal)
5285 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
659c805c 5286
e605db80
DK		 5287 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
5288 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
5289 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
5290 bp->flags |= BNXT_FLAG_SHORT_CMD;
5291
c0c050c5
MC		 5292hwrm_ver_get_exit:
5293 mutex_unlock(&bp->hwrm_cmd_lock);
5294 return rc;
5295}
5296
5ac67d8b
RS		 5297int bnxt_hwrm_fw_set_time(struct bnxt *bp)
5298{
5299 struct hwrm_fw_set_time_input req = {0};
7dfaa7bc
AB		 5300 struct tm tm;
5301 time64_t now = ktime_get_real_seconds();
5ac67d8b
RS		 5302
5303 if (bp->hwrm_spec_code < 0x10400)
5304 return -EOPNOTSUPP;
5305
7dfaa7bc 5306 time64_to_tm(now, 0, &tm);
5ac67d8b
RS		 5307 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
5308 req.year = cpu_to_le16(1900 + tm.tm_year);
5309 req.month = 1 + tm.tm_mon;
5310 req.day = tm.tm_mday;
5311 req.hour = tm.tm_hour;
5312 req.minute = tm.tm_min;
5313 req.second = tm.tm_sec;
5314 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5315}
5316
3bdf56c4
MC		 5317static int bnxt_hwrm_port_qstats(struct bnxt *bp)
5318{
5319 int rc;
5320 struct bnxt_pf_info *pf = &bp->pf;
5321 struct hwrm_port_qstats_input req = {0};
5322
5323 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
5324 return 0;
5325
5326 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
5327 req.port_id = cpu_to_le16(pf->port_id);
5328 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
5329 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
5330 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5331 return rc;
5332}
5333
c0c050c5
MC		 5334static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
5335{
5336 if (bp->vxlan_port_cnt) {
5337 bnxt_hwrm_tunnel_dst_port_free(
5338 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5339 }
5340 bp->vxlan_port_cnt = 0;
5341 if (bp->nge_port_cnt) {
5342 bnxt_hwrm_tunnel_dst_port_free(
5343 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5344 }
5345 bp->nge_port_cnt = 0;
5346}
5347
5348static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
5349{
5350 int rc, i;
5351 u32 tpa_flags = 0;
5352
5353 if (set_tpa)
5354 tpa_flags = bp->flags & BNXT_FLAG_TPA;
5355 for (i = 0; i < bp->nr_vnics; i++) {
5356 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5357 if (rc) {
5358 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
23e12c89 5359 i, rc);
c0c050c5
MC		 5360 return rc;
5361 }
5362 }
5363 return 0;
5364}
5365
5366static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
5367{
5368 int i;
5369
5370 for (i = 0; i < bp->nr_vnics; i++)
5371 bnxt_hwrm_vnic_set_rss(bp, i, false);
5372}
5373
5374static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5375 bool irq_re_init)
5376{
5377 if (bp->vnic_info) {
5378 bnxt_hwrm_clear_vnic_filter(bp);
5379 /* clear all RSS setting before free vnic ctx */
5380 bnxt_hwrm_clear_vnic_rss(bp);
5381 bnxt_hwrm_vnic_ctx_free(bp);
5382 /* before free the vnic, undo the vnic tpa settings */
5383 if (bp->flags & BNXT_FLAG_TPA)
5384 bnxt_set_tpa(bp, false);
5385 bnxt_hwrm_vnic_free(bp);
5386 }
5387 bnxt_hwrm_ring_free(bp, close_path);
5388 bnxt_hwrm_ring_grp_free(bp);
5389 if (irq_re_init) {
5390 bnxt_hwrm_stat_ctx_free(bp);
5391 bnxt_hwrm_free_tunnel_ports(bp);
5392 }
5393}
5394
39d8ba2e
MC		 5395static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5396{
5397 struct hwrm_func_cfg_input req = {0};
5398 int rc;
5399
5400 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5401 req.fid = cpu_to_le16(0xffff);
5402 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5403 if (br_mode == BRIDGE_MODE_VEB)
5404 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5405 else if (br_mode == BRIDGE_MODE_VEPA)
5406 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5407 else
5408 return -EINVAL;
5409 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5410 if (rc)
5411 rc = -EIO;
5412 return rc;
5413}
5414
c3480a60
MC		 5415static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
5416{
5417 struct hwrm_func_cfg_input req = {0};
5418 int rc;
5419
5420 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
5421 return 0;
5422
5423 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5424 req.fid = cpu_to_le16(0xffff);
5425 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
5426 req.cache_linesize = FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_64;
5427 if (size == 128)
5428 req.cache_linesize =
5429 FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_128;
5430
5431 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5432 if (rc)
5433 rc = -EIO;
5434 return rc;
5435}
5436
c0c050c5
MC		 5437static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5438{
ae10ae74 5439 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
c0c050c5
MC		 5440 int rc;
5441
ae10ae74
MC		 5442 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5443 goto skip_rss_ctx;
5444
c0c050c5 5445 /* allocate context for vnic */
94ce9caa 5446 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
c0c050c5
MC		 5447 if (rc) {
5448 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5449 vnic_id, rc);
5450 goto vnic_setup_err;
5451 }
5452 bp->rsscos_nr_ctxs++;
5453
94ce9caa
PS		 5454 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5455 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5456 if (rc) {
5457 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5458 vnic_id, rc);
5459 goto vnic_setup_err;
5460 }
5461 bp->rsscos_nr_ctxs++;
5462 }
5463
ae10ae74 5464skip_rss_ctx:
c0c050c5
MC		 5465 /* configure default vnic, ring grp */
5466 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5467 if (rc) {
5468 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5469 vnic_id, rc);
5470 goto vnic_setup_err;
5471 }
5472
5473 /* Enable RSS hashing on vnic */
5474 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5475 if (rc) {
5476 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5477 vnic_id, rc);
5478 goto vnic_setup_err;
5479 }
5480
5481 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5482 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5483 if (rc) {
5484 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5485 vnic_id, rc);
5486 }
5487 }
5488
5489vnic_setup_err:
5490 return rc;
5491}
5492
5493static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5494{
5495#ifdef CONFIG_RFS_ACCEL
5496 int i, rc = 0;
5497
5498 for (i = 0; i < bp->rx_nr_rings; i++) {
ae10ae74 5499 struct bnxt_vnic_info *vnic;
c0c050c5
MC		 5500 u16 vnic_id = i + 1;
5501 u16 ring_id = i;
5502
5503 if (vnic_id >= bp->nr_vnics)
5504 break;
5505
ae10ae74
MC		 5506 vnic = &bp->vnic_info[vnic_id];
5507 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5508 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5509 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
b81a90d3 5510 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 5511 if (rc) {
5512 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5513 vnic_id, rc);
5514 break;
5515 }
5516 rc = bnxt_setup_vnic(bp, vnic_id);
5517 if (rc)
5518 break;
5519 }
5520 return rc;
5521#else
5522 return 0;
5523#endif
5524}
5525
17c71ac3
MC		 5526/* Allow PF and VF with default VLAN to be in promiscuous mode */
5527static bool bnxt_promisc_ok(struct bnxt *bp)
5528{
5529#ifdef CONFIG_BNXT_SRIOV
5530 if (BNXT_VF(bp) && !bp->vf.vlan)
5531 return false;
5532#endif
5533 return true;
5534}
5535
dc52c6c7
PS		 5536static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5537{
5538 unsigned int rc = 0;
5539
5540 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5541 if (rc) {
5542 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5543 rc);
5544 return rc;
5545 }
5546
5547 rc = bnxt_hwrm_vnic_cfg(bp, 1);
5548 if (rc) {
5549 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5550 rc);
5551 return rc;
5552 }
5553 return rc;
5554}
5555
b664f008 5556static int bnxt_cfg_rx_mode(struct bnxt *);
7d2837dd 5557static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
b664f008 5558
c0c050c5
MC		 5559static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5560{
7d2837dd 5561 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
c0c050c5 5562 int rc = 0;
76595193 5563 unsigned int rx_nr_rings = bp->rx_nr_rings;
c0c050c5
MC		 5564
5565 if (irq_re_init) {
5566 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5567 if (rc) {
5568 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5569 rc);
5570 goto err_out;
5571 }
5572 }
5573
5574 rc = bnxt_hwrm_ring_alloc(bp);
5575 if (rc) {
5576 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5577 goto err_out;
5578 }
5579
5580 rc = bnxt_hwrm_ring_grp_alloc(bp);
5581 if (rc) {
5582 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5583 goto err_out;
5584 }
5585
76595193
PS		 5586 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5587 rx_nr_rings--;
5588
c0c050c5 5589 /* default vnic 0 */
76595193 5590 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
c0c050c5
MC		 5591 if (rc) {
5592 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5593 goto err_out;
5594 }
5595
5596 rc = bnxt_setup_vnic(bp, 0);
5597 if (rc)
5598 goto err_out;
5599
5600 if (bp->flags & BNXT_FLAG_RFS) {
5601 rc = bnxt_alloc_rfs_vnics(bp);
5602 if (rc)
5603 goto err_out;
5604 }
5605
5606 if (bp->flags & BNXT_FLAG_TPA) {
5607 rc = bnxt_set_tpa(bp, true);
5608 if (rc)
5609 goto err_out;
5610 }
5611
5612 if (BNXT_VF(bp))
5613 bnxt_update_vf_mac(bp);
5614
5615 /* Filter for default vnic 0 */
5616 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5617 if (rc) {
5618 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5619 goto err_out;
5620 }
7d2837dd 5621 vnic->uc_filter_count = 1;
c0c050c5 5622
7d2837dd 5623 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5 5624
17c71ac3 5625 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7d2837dd
MC		 5626 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5627
5628 if (bp->dev->flags & IFF_ALLMULTI) {
5629 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5630 vnic->mc_list_count = 0;
5631 } else {
5632 u32 mask = 0;
5633
5634 bnxt_mc_list_updated(bp, &mask);
5635 vnic->rx_mask |= mask;
5636 }
c0c050c5 5637
b664f008
MC		 5638 rc = bnxt_cfg_rx_mode(bp);
5639 if (rc)
c0c050c5 5640 goto err_out;
c0c050c5
MC		 5641
5642 rc = bnxt_hwrm_set_coal(bp);
5643 if (rc)
5644 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
dc52c6c7
PS		 5645 rc);
5646
5647 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5648 rc = bnxt_setup_nitroa0_vnic(bp);
5649 if (rc)
5650 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5651 rc);
5652 }
c0c050c5 5653
cf6645f8
MC		 5654 if (BNXT_VF(bp)) {
5655 bnxt_hwrm_func_qcfg(bp);
5656 netdev_update_features(bp->dev);
5657 }
5658
c0c050c5
MC		 5659 return 0;
5660
5661err_out:
5662 bnxt_hwrm_resource_free(bp, 0, true);
5663
5664 return rc;
5665}
5666
5667static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5668{
5669 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5670 return 0;
5671}
5672
5673static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5674{
2247925f 5675 bnxt_init_cp_rings(bp);
c0c050c5
MC		 5676 bnxt_init_rx_rings(bp);
5677 bnxt_init_tx_rings(bp);
5678 bnxt_init_ring_grps(bp, irq_re_init);
5679 bnxt_init_vnics(bp);
5680
5681 return bnxt_init_chip(bp, irq_re_init);
5682}
5683
c0c050c5
MC		 5684static int bnxt_set_real_num_queues(struct bnxt *bp)
5685{
5686 int rc;
5687 struct net_device *dev = bp->dev;
5688
5f449249
MC		 5689 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5690 bp->tx_nr_rings_xdp);
c0c050c5
MC		 5691 if (rc)
5692 return rc;
5693
5694 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5695 if (rc)
5696 return rc;
5697
5698#ifdef CONFIG_RFS_ACCEL
45019a18 5699 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 5700 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 5701#endif
5702
5703 return rc;
5704}
5705
6e6c5a57
MC		 5706static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5707 bool shared)
5708{
5709 int _rx = *rx, _tx = *tx;
5710
5711 if (shared) {
5712 *rx = min_t(int, _rx, max);
5713 *tx = min_t(int, _tx, max);
5714 } else {
5715 if (max < 2)
5716 return -ENOMEM;
5717
5718 while (_rx + _tx > max) {
5719 if (_rx > _tx && _rx > 1)
5720 _rx--;
5721 else if (_tx > 1)
5722 _tx--;
5723 }
5724 *rx = _rx;
5725 *tx = _tx;
5726 }
5727 return 0;
5728}
5729
7809592d
MC		 5730static void bnxt_setup_msix(struct bnxt *bp)
5731{
5732 const int len = sizeof(bp->irq_tbl[0].name);
5733 struct net_device *dev = bp->dev;
5734 int tcs, i;
5735
5736 tcs = netdev_get_num_tc(dev);
5737 if (tcs > 1) {
d1e7925e 5738 int i, off, count;
7809592d 5739
d1e7925e
MC		 5740 for (i = 0; i < tcs; i++) {
5741 count = bp->tx_nr_rings_per_tc;
5742 off = i * count;
5743 netdev_set_tc_queue(dev, i, count, off);
7809592d
MC		 5744 }
5745 }
5746
5747 for (i = 0; i < bp->cp_nr_rings; i++) {
5748 char *attr;
5749
5750 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5751 attr = "TxRx";
5752 else if (i < bp->rx_nr_rings)
5753 attr = "rx";
5754 else
5755 attr = "tx";
5756
5757 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5758 i);
5759 bp->irq_tbl[i].handler = bnxt_msix;
5760 }
5761}
5762
5763static void bnxt_setup_inta(struct bnxt *bp)
5764{
5765 const int len = sizeof(bp->irq_tbl[0].name);
5766
5767 if (netdev_get_num_tc(bp->dev))
5768 netdev_reset_tc(bp->dev);
5769
5770 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5771 0);
5772 bp->irq_tbl[0].handler = bnxt_inta;
5773}
5774
5775static int bnxt_setup_int_mode(struct bnxt *bp)
5776{
5777 int rc;
5778
5779 if (bp->flags & BNXT_FLAG_USING_MSIX)
5780 bnxt_setup_msix(bp);
5781 else
5782 bnxt_setup_inta(bp);
5783
5784 rc = bnxt_set_real_num_queues(bp);
5785 return rc;
5786}
5787
b7429954 5788#ifdef CONFIG_RFS_ACCEL
8079e8f1
MC		 5789static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5790{
6a4f2947 5791 return bp->hw_resc.max_rsscos_ctxs;
8079e8f1
MC		 5792}
5793
5794static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5795{
6a4f2947 5796 return bp->hw_resc.max_vnics;
8079e8f1 5797}
b7429954 5798#endif
8079e8f1 5799
e4060d30
MC		 5800unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5801{
6a4f2947 5802 return bp->hw_resc.max_stat_ctxs;
e4060d30
MC		 5803}
5804
a588e458
MC		 5805void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5806{
6a4f2947 5807 bp->hw_resc.max_stat_ctxs = max;
a588e458
MC		 5808}
5809
e4060d30
MC		 5810unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5811{
6a4f2947 5812 return bp->hw_resc.max_cp_rings;
e4060d30
MC		 5813}
5814
a588e458
MC		 5815void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5816{
6a4f2947 5817 bp->hw_resc.max_cp_rings = max;
a588e458
MC		 5818}
5819
7809592d
MC		 5820static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5821{
6a4f2947
MC		 5822 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5823
5824 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7809592d
MC		 5825}
5826
33c2657e
MC		 5827void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5828{
6a4f2947 5829 bp->hw_resc.max_irqs = max_irqs;
33c2657e
MC		 5830}
5831
7809592d 5832static int bnxt_init_msix(struct bnxt *bp)
c0c050c5 5833{
01657bcd 5834 int i, total_vecs, rc = 0, min = 1;
7809592d 5835 struct msix_entry *msix_ent;
c0c050c5 5836
7809592d 5837 total_vecs = bnxt_get_max_func_irqs(bp);
c0c050c5
MC		 5838 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5839 if (!msix_ent)
5840 return -ENOMEM;
5841
5842 for (i = 0; i < total_vecs; i++) {
5843 msix_ent[i].entry = i;
5844 msix_ent[i].vector = 0;
5845 }
5846
01657bcd
MC		 5847 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5848 min = 2;
5849
5850 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
c0c050c5
MC		 5851 if (total_vecs < 0) {
5852 rc = -ENODEV;
5853 goto msix_setup_exit;
5854 }
5855
5856 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5857 if (bp->irq_tbl) {
7809592d
MC		 5858 for (i = 0; i < total_vecs; i++)
5859 bp->irq_tbl[i].vector = msix_ent[i].vector;
c0c050c5 5860
7809592d 5861 bp->total_irqs = total_vecs;
c0c050c5 5862 /* Trim rings based upon num of vectors allocated */
6e6c5a57 5863 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
01657bcd 5864 total_vecs, min == 1);
6e6c5a57
MC		 5865 if (rc)
5866 goto msix_setup_exit;
5867
c0c050c5 5868 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7809592d
MC		 5869 bp->cp_nr_rings = (min == 1) ?
5870 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5871 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5 5872
c0c050c5
MC		 5873 } else {
5874 rc = -ENOMEM;
5875 goto msix_setup_exit;
5876 }
5877 bp->flags |= BNXT_FLAG_USING_MSIX;
5878 kfree(msix_ent);
5879 return 0;
5880
5881msix_setup_exit:
7809592d
MC		 5882 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5883 kfree(bp->irq_tbl);
5884 bp->irq_tbl = NULL;
c0c050c5
MC		 5885 pci_disable_msix(bp->pdev);
5886 kfree(msix_ent);
5887 return rc;
5888}
5889
7809592d 5890static int bnxt_init_inta(struct bnxt *bp)
c0c050c5 5891{
c0c050c5 5892 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7809592d
MC		 5893 if (!bp->irq_tbl)
5894 return -ENOMEM;
5895
5896 bp->total_irqs = 1;
c0c050c5
MC		 5897 bp->rx_nr_rings = 1;
5898 bp->tx_nr_rings = 1;
5899 bp->cp_nr_rings = 1;
5900 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
01657bcd 5901 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5 5902 bp->irq_tbl[0].vector = bp->pdev->irq;
7809592d 5903 return 0;
c0c050c5
MC		 5904}
5905
7809592d 5906static int bnxt_init_int_mode(struct bnxt *bp)
c0c050c5
MC		 5907{
5908 int rc = 0;
5909
5910 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7809592d 5911 rc = bnxt_init_msix(bp);
c0c050c5 5912
1fa72e29 5913 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
c0c050c5 5914 /* fallback to INTA */
7809592d 5915 rc = bnxt_init_inta(bp);
c0c050c5
MC		 5916 }
5917 return rc;
5918}
5919
7809592d
MC		 5920static void bnxt_clear_int_mode(struct bnxt *bp)
5921{
5922 if (bp->flags & BNXT_FLAG_USING_MSIX)
5923 pci_disable_msix(bp->pdev);
5924
5925 kfree(bp->irq_tbl);
5926 bp->irq_tbl = NULL;
5927 bp->flags &= ~BNXT_FLAG_USING_MSIX;
5928}
5929
674f50a5
MC		 5930static int bnxt_reserve_rings(struct bnxt *bp)
5931{
5932 int orig_cp = bp->hw_resc.resv_cp_rings;
5933 int tcs = netdev_get_num_tc(bp->dev);
5934 int rc;
5935
5936 if (!bnxt_need_reserve_rings(bp))
5937 return 0;
5938
5939 rc = __bnxt_reserve_rings(bp);
5940 if (rc) {
5941 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc);
5942 return rc;
5943 }
5944 if ((bp->flags & BNXT_FLAG_NEW_RM) && bp->cp_nr_rings > orig_cp) {
5945 bnxt_clear_int_mode(bp);
5946 rc = bnxt_init_int_mode(bp);
5947 if (rc)
5948 return rc;
5949 }
5950 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
5951 netdev_err(bp->dev, "tx ring reservation failure\n");
5952 netdev_reset_tc(bp->dev);
5953 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5954 return -ENOMEM;
5955 }
5956 bp->num_stat_ctxs = bp->cp_nr_rings;
5957 return 0;
5958}
5959
c0c050c5
MC		 5960static void bnxt_free_irq(struct bnxt *bp)
5961{
5962 struct bnxt_irq *irq;
5963 int i;
5964
5965#ifdef CONFIG_RFS_ACCEL
5966 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5967 bp->dev->rx_cpu_rmap = NULL;
5968#endif
5969 if (!bp->irq_tbl)
5970 return;
5971
5972 for (i = 0; i < bp->cp_nr_rings; i++) {
5973 irq = &bp->irq_tbl[i];
56f0fd80
VV		 5974 if (irq->requested) {
5975 if (irq->have_cpumask) {
5976 irq_set_affinity_hint(irq->vector, NULL);
5977 free_cpumask_var(irq->cpu_mask);
5978 irq->have_cpumask = 0;
5979 }
c0c050c5 5980 free_irq(irq->vector, bp->bnapi[i]);
56f0fd80
VV		 5981 }
5982
c0c050c5
MC		 5983 irq->requested = 0;
5984 }
c0c050c5
MC		 5985}
5986
5987static int bnxt_request_irq(struct bnxt *bp)
5988{
b81a90d3 5989 int i, j, rc = 0;
c0c050c5
MC		 5990 unsigned long flags = 0;
5991#ifdef CONFIG_RFS_ACCEL
5992 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5993#endif
5994
5995 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5996 flags = IRQF_SHARED;
5997
b81a90d3 5998 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
c0c050c5
MC		 5999 struct bnxt_irq *irq = &bp->irq_tbl[i];
6000#ifdef CONFIG_RFS_ACCEL
b81a90d3 6001 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 6002 rc = irq_cpu_rmap_add(rmap, irq->vector);
6003 if (rc)
6004 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 6005 j);
6006 j++;
c0c050c5
MC		 6007 }
6008#endif
6009 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6010 bp->bnapi[i]);
6011 if (rc)
6012 break;
6013
6014 irq->requested = 1;
56f0fd80
VV		 6015
6016 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
6017 int numa_node = dev_to_node(&bp->pdev->dev);
6018
6019 irq->have_cpumask = 1;
6020 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
6021 irq->cpu_mask);
6022 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
6023 if (rc) {
6024 netdev_warn(bp->dev,
6025 "Set affinity failed, IRQ = %d\n",
6026 irq->vector);
6027 break;
6028 }
6029 }
c0c050c5
MC		 6030 }
6031 return rc;
6032}
6033
6034static void bnxt_del_napi(struct bnxt *bp)
6035{
6036 int i;
6037
6038 if (!bp->bnapi)
6039 return;
6040
6041 for (i = 0; i < bp->cp_nr_rings; i++) {
6042 struct bnxt_napi *bnapi = bp->bnapi[i];
6043
6044 napi_hash_del(&bnapi->napi);
6045 netif_napi_del(&bnapi->napi);
6046 }
e5f6f564
ED		 6047 /* We called napi_hash_del() before netif_napi_del(), we need
6048 * to respect an RCU grace period before freeing napi structures.
6049 */
6050 synchronize_net();
c0c050c5
MC		 6051}
6052
6053static void bnxt_init_napi(struct bnxt *bp)
6054{
6055 int i;
10bbdaf5 6056 unsigned int cp_nr_rings = bp->cp_nr_rings;
c0c050c5
MC		 6057 struct bnxt_napi *bnapi;
6058
6059 if (bp->flags & BNXT_FLAG_USING_MSIX) {
10bbdaf5
PS		 6060 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6061 cp_nr_rings--;
6062 for (i = 0; i < cp_nr_rings; i++) {
c0c050c5
MC		 6063 bnapi = bp->bnapi[i];
6064 netif_napi_add(bp->dev, &bnapi->napi,
6065 bnxt_poll, 64);
c0c050c5 6066 }
10bbdaf5
PS		 6067 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6068 bnapi = bp->bnapi[cp_nr_rings];
6069 netif_napi_add(bp->dev, &bnapi->napi,
6070 bnxt_poll_nitroa0, 64);
10bbdaf5 6071 }
c0c050c5
MC		 6072 } else {
6073 bnapi = bp->bnapi[0];
6074 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 6075 }
6076}
6077
6078static void bnxt_disable_napi(struct bnxt *bp)
6079{
6080 int i;
6081
6082 if (!bp->bnapi)
6083 return;
6084
b356a2e7 6085 for (i = 0; i < bp->cp_nr_rings; i++)
c0c050c5 6086 napi_disable(&bp->bnapi[i]->napi);
c0c050c5
MC		 6087}
6088
6089static void bnxt_enable_napi(struct bnxt *bp)
6090{
6091 int i;
6092
6093 for (i = 0; i < bp->cp_nr_rings; i++) {
6a8788f2 6094 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
fa7e2812 6095 bp->bnapi[i]->in_reset = false;
6a8788f2
AG		 6096
6097 if (bp->bnapi[i]->rx_ring) {
6098 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
6099 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
6100 }
c0c050c5
MC		 6101 napi_enable(&bp->bnapi[i]->napi);
6102 }
6103}
6104
7df4ae9f 6105void bnxt_tx_disable(struct bnxt *bp)
c0c050c5
MC		 6106{
6107 int i;
c0c050c5 6108 struct bnxt_tx_ring_info *txr;
c0c050c5 6109
b6ab4b01 6110 if (bp->tx_ring) {
c0c050c5 6111 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 6112 txr = &bp->tx_ring[i];
c0c050c5 6113 txr->dev_state = BNXT_DEV_STATE_CLOSING;
c0c050c5
MC		 6114 }
6115 }
6116 /* Stop all TX queues */
6117 netif_tx_disable(bp->dev);
6118 netif_carrier_off(bp->dev);
6119}
6120
7df4ae9f 6121void bnxt_tx_enable(struct bnxt *bp)
c0c050c5
MC		 6122{
6123 int i;
c0c050c5 6124 struct bnxt_tx_ring_info *txr;
c0c050c5
MC		 6125
6126 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 6127 txr = &bp->tx_ring[i];
c0c050c5
MC		 6128 txr->dev_state = 0;
6129 }
6130 netif_tx_wake_all_queues(bp->dev);
6131 if (bp->link_info.link_up)
6132 netif_carrier_on(bp->dev);
6133}
6134
6135static void bnxt_report_link(struct bnxt *bp)
6136{
6137 if (bp->link_info.link_up) {
6138 const char *duplex;
6139 const char *flow_ctrl;
38a21b34
DK		 6140 u32 speed;
6141 u16 fec;
c0c050c5
MC		 6142
6143 netif_carrier_on(bp->dev);
6144 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
6145 duplex = "full";
6146 else
6147 duplex = "half";
6148 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
6149 flow_ctrl = "ON - receive & transmit";
6150 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
6151 flow_ctrl = "ON - transmit";
6152 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
6153 flow_ctrl = "ON - receive";
6154 else
6155 flow_ctrl = "none";
6156 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
38a21b34 6157 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
c0c050c5 6158 speed, duplex, flow_ctrl);
170ce013
MC		 6159 if (bp->flags & BNXT_FLAG_EEE_CAP)
6160 netdev_info(bp->dev, "EEE is %s\n",
6161 bp->eee.eee_active ? "active" :
6162 "not active");
e70c752f
MC		 6163 fec = bp->link_info.fec_cfg;
6164 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
6165 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
6166 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
6167 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
6168 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
c0c050c5
MC		 6169 } else {
6170 netif_carrier_off(bp->dev);
6171 netdev_err(bp->dev, "NIC Link is Down\n");
6172 }
6173}
6174
170ce013
MC		 6175static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
6176{
6177 int rc = 0;
6178 struct hwrm_port_phy_qcaps_input req = {0};
6179 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
93ed8117 6180 struct bnxt_link_info *link_info = &bp->link_info;
170ce013
MC		 6181
6182 if (bp->hwrm_spec_code < 0x10201)
6183 return 0;
6184
6185 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
6186
6187 mutex_lock(&bp->hwrm_cmd_lock);
6188 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6189 if (rc)
6190 goto hwrm_phy_qcaps_exit;
6191
acb20054 6192 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
170ce013
MC		 6193 struct ethtool_eee *eee = &bp->eee;
6194 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
6195
6196 bp->flags |= BNXT_FLAG_EEE_CAP;
6197 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6198 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
6199 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
6200 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
6201 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
6202 }
520ad89a
MC		 6203 if (resp->supported_speeds_auto_mode)
6204 link_info->support_auto_speeds =
6205 le16_to_cpu(resp->supported_speeds_auto_mode);
170ce013 6206
d5430d31
MC		 6207 bp->port_count = resp->port_cnt;
6208
170ce013
MC		 6209hwrm_phy_qcaps_exit:
6210 mutex_unlock(&bp->hwrm_cmd_lock);
6211 return rc;
6212}
6213
c0c050c5
MC		 6214static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
6215{
6216 int rc = 0;
6217 struct bnxt_link_info *link_info = &bp->link_info;
6218 struct hwrm_port_phy_qcfg_input req = {0};
6219 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6220 u8 link_up = link_info->link_up;
286ef9d6 6221 u16 diff;
c0c050c5
MC		 6222
6223 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
6224
6225 mutex_lock(&bp->hwrm_cmd_lock);
6226 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6227 if (rc) {
6228 mutex_unlock(&bp->hwrm_cmd_lock);
6229 return rc;
6230 }
6231
6232 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
6233 link_info->phy_link_status = resp->link;
acb20054
MC		 6234 link_info->duplex = resp->duplex_cfg;
6235 if (bp->hwrm_spec_code >= 0x10800)
6236 link_info->duplex = resp->duplex_state;
c0c050c5
MC		 6237 link_info->pause = resp->pause;
6238 link_info->auto_mode = resp->auto_mode;
6239 link_info->auto_pause_setting = resp->auto_pause;
3277360e 6240 link_info->lp_pause = resp->link_partner_adv_pause;
c0c050c5 6241 link_info->force_pause_setting = resp->force_pause;
acb20054 6242 link_info->duplex_setting = resp->duplex_cfg;
c0c050c5
MC		 6243 if (link_info->phy_link_status == BNXT_LINK_LINK)
6244 link_info->link_speed = le16_to_cpu(resp->link_speed);
6245 else
6246 link_info->link_speed = 0;
6247 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
c0c050c5
MC		 6248 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
6249 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
3277360e
MC		 6250 link_info->lp_auto_link_speeds =
6251 le16_to_cpu(resp->link_partner_adv_speeds);
c0c050c5
MC		 6252 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
6253 link_info->phy_ver[0] = resp->phy_maj;
6254 link_info->phy_ver[1] = resp->phy_min;
6255 link_info->phy_ver[2] = resp->phy_bld;
6256 link_info->media_type = resp->media_type;
03efbec0 6257 link_info->phy_type = resp->phy_type;
11f15ed3 6258 link_info->transceiver = resp->xcvr_pkg_type;
170ce013
MC		 6259 link_info->phy_addr = resp->eee_config_phy_addr &
6260 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
42ee18fe 6261 link_info->module_status = resp->module_status;
170ce013
MC		 6262
6263 if (bp->flags & BNXT_FLAG_EEE_CAP) {
6264 struct ethtool_eee *eee = &bp->eee;
6265 u16 fw_speeds;
6266
6267 eee->eee_active = 0;
6268 if (resp->eee_config_phy_addr &
6269 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
6270 eee->eee_active = 1;
6271 fw_speeds = le16_to_cpu(
6272 resp->link_partner_adv_eee_link_speed_mask);
6273 eee->lp_advertised =
6274 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6275 }
6276
6277 /* Pull initial EEE config */
6278 if (!chng_link_state) {
6279 if (resp->eee_config_phy_addr &
6280 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
6281 eee->eee_enabled = 1;
c0c050c5 6282
170ce013
MC		 6283 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
6284 eee->advertised =
6285 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6286
6287 if (resp->eee_config_phy_addr &
6288 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
6289 __le32 tmr;
6290
6291 eee->tx_lpi_enabled = 1;
6292 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
6293 eee->tx_lpi_timer = le32_to_cpu(tmr) &
6294 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
6295 }
6296 }
6297 }
e70c752f
MC		 6298
6299 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
6300 if (bp->hwrm_spec_code >= 0x10504)
6301 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
6302
c0c050c5
MC		 6303 /* TODO: need to add more logic to report VF link */
6304 if (chng_link_state) {
6305 if (link_info->phy_link_status == BNXT_LINK_LINK)
6306 link_info->link_up = 1;
6307 else
6308 link_info->link_up = 0;
6309 if (link_up != link_info->link_up)
6310 bnxt_report_link(bp);
6311 } else {
6312 /* alwasy link down if not require to update link state */
6313 link_info->link_up = 0;
6314 }
6315 mutex_unlock(&bp->hwrm_cmd_lock);
286ef9d6
MC		 6316
6317 diff = link_info->support_auto_speeds ^ link_info->advertising;
6318 if ((link_info->support_auto_speeds | diff) !=
6319 link_info->support_auto_speeds) {
6320 /* An advertised speed is no longer supported, so we need to
0eaa24b9
MC		 6321 * update the advertisement settings. Caller holds RTNL
6322 * so we can modify link settings.
286ef9d6 6323 */
286ef9d6 6324 link_info->advertising = link_info->support_auto_speeds;
0eaa24b9 6325 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
286ef9d6 6326 bnxt_hwrm_set_link_setting(bp, true, false);
286ef9d6 6327 }
c0c050c5
MC		 6328 return 0;
6329}
6330
10289bec
MC		 6331static void bnxt_get_port_module_status(struct bnxt *bp)
6332{
6333 struct bnxt_link_info *link_info = &bp->link_info;
6334 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
6335 u8 module_status;
6336
6337 if (bnxt_update_link(bp, true))
6338 return;
6339
6340 module_status = link_info->module_status;
6341 switch (module_status) {
6342 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
6343 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
6344 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
6345 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
6346 bp->pf.port_id);
6347 if (bp->hwrm_spec_code >= 0x10201) {
6348 netdev_warn(bp->dev, "Module part number %s\n",
6349 resp->phy_vendor_partnumber);
6350 }
6351 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
6352 netdev_warn(bp->dev, "TX is disabled\n");
6353 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
6354 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
6355 }
6356}
6357
c0c050c5
MC		 6358static void
6359bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
6360{
6361 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
c9ee9516
MC		 6362 if (bp->hwrm_spec_code >= 0x10201)
6363 req->auto_pause =
6364 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
c0c050c5
MC		 6365 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6366 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
6367 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
49b5c7a1 6368 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
c0c050c5
MC		 6369 req->enables |=
6370 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6371 } else {
6372 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6373 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
6374 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6375 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
6376 req->enables |=
6377 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
c9ee9516
MC		 6378 if (bp->hwrm_spec_code >= 0x10201) {
6379 req->auto_pause = req->force_pause;
6380 req->enables |= cpu_to_le32(
6381 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6382 }
c0c050c5
MC		 6383 }
6384}
6385
6386static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6387 struct hwrm_port_phy_cfg_input *req)
6388{
6389 u8 autoneg = bp->link_info.autoneg;
6390 u16 fw_link_speed = bp->link_info.req_link_speed;
68515a18 6391 u16 advertising = bp->link_info.advertising;
c0c050c5
MC		 6392
6393 if (autoneg & BNXT_AUTONEG_SPEED) {
6394 req->auto_mode |=
11f15ed3 6395 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
c0c050c5
MC		 6396
6397 req->enables |= cpu_to_le32(
6398 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6399 req->auto_link_speed_mask = cpu_to_le16(advertising);
6400
6401 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6402 req->flags |=
6403 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6404 } else {
6405 req->force_link_speed = cpu_to_le16(fw_link_speed);
6406 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6407 }
6408
c0c050c5
MC		 6409 /* tell chimp that the setting takes effect immediately */
6410 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6411}
6412
6413int bnxt_hwrm_set_pause(struct bnxt *bp)
6414{
6415 struct hwrm_port_phy_cfg_input req = {0};
6416 int rc;
6417
6418 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6419 bnxt_hwrm_set_pause_common(bp, &req);
6420
6421 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6422 bp->link_info.force_link_chng)
6423 bnxt_hwrm_set_link_common(bp, &req);
6424
6425 mutex_lock(&bp->hwrm_cmd_lock);
6426 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6427 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6428 /* since changing of pause setting doesn't trigger any link
6429 * change event, the driver needs to update the current pause
6430 * result upon successfully return of the phy_cfg command
6431 */
6432 bp->link_info.pause =
6433 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6434 bp->link_info.auto_pause_setting = 0;
6435 if (!bp->link_info.force_link_chng)
6436 bnxt_report_link(bp);
6437 }
6438 bp->link_info.force_link_chng = false;
6439 mutex_unlock(&bp->hwrm_cmd_lock);
6440 return rc;
6441}
6442
939f7f0c
MC		 6443static void bnxt_hwrm_set_eee(struct bnxt *bp,
6444 struct hwrm_port_phy_cfg_input *req)
6445{
6446 struct ethtool_eee *eee = &bp->eee;
6447
6448 if (eee->eee_enabled) {
6449 u16 eee_speeds;
6450 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6451
6452 if (eee->tx_lpi_enabled)
6453 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6454 else
6455 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6456
6457 req->flags |= cpu_to_le32(flags);
6458 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6459 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6460 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6461 } else {
6462 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6463 }
6464}
6465
6466int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
c0c050c5
MC		 6467{
6468 struct hwrm_port_phy_cfg_input req = {0};
6469
6470 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6471 if (set_pause)
6472 bnxt_hwrm_set_pause_common(bp, &req);
6473
6474 bnxt_hwrm_set_link_common(bp, &req);
939f7f0c
MC		 6475
6476 if (set_eee)
6477 bnxt_hwrm_set_eee(bp, &req);
c0c050c5
MC		 6478 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6479}
6480
33f7d55f
MC		 6481static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6482{
6483 struct hwrm_port_phy_cfg_input req = {0};
6484
567b2abe 6485 if (!BNXT_SINGLE_PF(bp))
33f7d55f
MC		 6486 return 0;
6487
6488 if (pci_num_vf(bp->pdev))
6489 return 0;
6490
6491 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
16d663a6 6492 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
33f7d55f
MC		 6493 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6494}
6495
5ad2cbee
MC		 6496static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6497{
6498 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6499 struct hwrm_port_led_qcaps_input req = {0};
6500 struct bnxt_pf_info *pf = &bp->pf;
6501 int rc;
6502
6503 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6504 return 0;
6505
6506 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6507 req.port_id = cpu_to_le16(pf->port_id);
6508 mutex_lock(&bp->hwrm_cmd_lock);
6509 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6510 if (rc) {
6511 mutex_unlock(&bp->hwrm_cmd_lock);
6512 return rc;
6513 }
6514 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6515 int i;
6516
6517 bp->num_leds = resp->num_leds;
6518 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6519 bp->num_leds);
6520 for (i = 0; i < bp->num_leds; i++) {
6521 struct bnxt_led_info *led = &bp->leds[i];
6522 __le16 caps = led->led_state_caps;
6523
6524 if (!led->led_group_id ||
6525 !BNXT_LED_ALT_BLINK_CAP(caps)) {
6526 bp->num_leds = 0;
6527 break;
6528 }
6529 }
6530 }
6531 mutex_unlock(&bp->hwrm_cmd_lock);
6532 return 0;
6533}
6534
5282db6c
MC		 6535int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6536{
6537 struct hwrm_wol_filter_alloc_input req = {0};
6538 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6539 int rc;
6540
6541 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6542 req.port_id = cpu_to_le16(bp->pf.port_id);
6543 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6544 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6545 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6546 mutex_lock(&bp->hwrm_cmd_lock);
6547 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6548 if (!rc)
6549 bp->wol_filter_id = resp->wol_filter_id;
6550 mutex_unlock(&bp->hwrm_cmd_lock);
6551 return rc;
6552}
6553
6554int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6555{
6556 struct hwrm_wol_filter_free_input req = {0};
6557 int rc;
6558
6559 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6560 req.port_id = cpu_to_le16(bp->pf.port_id);
6561 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6562 req.wol_filter_id = bp->wol_filter_id;
6563 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6564 return rc;
6565}
6566
c1ef146a
MC		 6567static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6568{
6569 struct hwrm_wol_filter_qcfg_input req = {0};
6570 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6571 u16 next_handle = 0;
6572 int rc;
6573
6574 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6575 req.port_id = cpu_to_le16(bp->pf.port_id);
6576 req.handle = cpu_to_le16(handle);
6577 mutex_lock(&bp->hwrm_cmd_lock);
6578 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6579 if (!rc) {
6580 next_handle = le16_to_cpu(resp->next_handle);
6581 if (next_handle != 0) {
6582 if (resp->wol_type ==
6583 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6584 bp->wol = 1;
6585 bp->wol_filter_id = resp->wol_filter_id;
6586 }
6587 }
6588 }
6589 mutex_unlock(&bp->hwrm_cmd_lock);
6590 return next_handle;
6591}
6592
6593static void bnxt_get_wol_settings(struct bnxt *bp)
6594{
6595 u16 handle = 0;
6596
6597 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6598 return;
6599
6600 do {
6601 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6602 } while (handle && handle != 0xffff);
6603}
6604
939f7f0c
MC		 6605static bool bnxt_eee_config_ok(struct bnxt *bp)
6606{
6607 struct ethtool_eee *eee = &bp->eee;
6608 struct bnxt_link_info *link_info = &bp->link_info;
6609
6610 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6611 return true;
6612
6613 if (eee->eee_enabled) {
6614 u32 advertising =
6615 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6616
6617 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6618 eee->eee_enabled = 0;
6619 return false;
6620 }
6621 if (eee->advertised & ~advertising) {
6622 eee->advertised = advertising & eee->supported;
6623 return false;
6624 }
6625 }
6626 return true;
6627}
6628
c0c050c5
MC		 6629static int bnxt_update_phy_setting(struct bnxt *bp)
6630{
6631 int rc;
6632 bool update_link = false;
6633 bool update_pause = false;
939f7f0c 6634 bool update_eee = false;
c0c050c5
MC		 6635 struct bnxt_link_info *link_info = &bp->link_info;
6636
6637 rc = bnxt_update_link(bp, true);
6638 if (rc) {
6639 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6640 rc);
6641 return rc;
6642 }
33dac24a
MC		 6643 if (!BNXT_SINGLE_PF(bp))
6644 return 0;
6645
c0c050c5 6646 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
c9ee9516
MC		 6647 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6648 link_info->req_flow_ctrl)
c0c050c5
MC		 6649 update_pause = true;
6650 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6651 link_info->force_pause_setting != link_info->req_flow_ctrl)
6652 update_pause = true;
c0c050c5
MC		 6653 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6654 if (BNXT_AUTO_MODE(link_info->auto_mode))
6655 update_link = true;
6656 if (link_info->req_link_speed != link_info->force_link_speed)
6657 update_link = true;
de73018f
MC		 6658 if (link_info->req_duplex != link_info->duplex_setting)
6659 update_link = true;
c0c050c5
MC		 6660 } else {
6661 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6662 update_link = true;
6663 if (link_info->advertising != link_info->auto_link_speeds)
6664 update_link = true;
c0c050c5
MC		 6665 }
6666
16d663a6
MC		 6667 /* The last close may have shutdown the link, so need to call
6668 * PHY_CFG to bring it back up.
6669 */
6670 if (!netif_carrier_ok(bp->dev))
6671 update_link = true;
6672
939f7f0c
MC		 6673 if (!bnxt_eee_config_ok(bp))
6674 update_eee = true;
6675
c0c050c5 6676 if (update_link)
939f7f0c 6677 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
c0c050c5
MC		 6678 else if (update_pause)
6679 rc = bnxt_hwrm_set_pause(bp);
6680 if (rc) {
6681 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6682 rc);
6683 return rc;
6684 }
6685
6686 return rc;
6687}
6688
11809490
JH		 6689/* Common routine to pre-map certain register block to different GRC window.
6690 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6691 * in PF and 3 windows in VF that can be customized to map in different
6692 * register blocks.
6693 */
6694static void bnxt_preset_reg_win(struct bnxt *bp)
6695{
6696 if (BNXT_PF(bp)) {
6697 /* CAG registers map to GRC window #4 */
6698 writel(BNXT_CAG_REG_BASE,
6699 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6700 }
6701}
6702
c0c050c5
MC		 6703static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6704{
6705 int rc = 0;
6706
11809490 6707 bnxt_preset_reg_win(bp);
c0c050c5
MC		 6708 netif_carrier_off(bp->dev);
6709 if (irq_re_init) {
674f50a5
MC		 6710 rc = bnxt_reserve_rings(bp);
6711 if (rc)
6712 return rc;
6713
c0c050c5
MC		 6714 rc = bnxt_setup_int_mode(bp);
6715 if (rc) {
6716 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6717 rc);
6718 return rc;
6719 }
6720 }
6721 if ((bp->flags & BNXT_FLAG_RFS) &&
6722 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6723 /* disable RFS if falling back to INTA */
6724 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6725 bp->flags &= ~BNXT_FLAG_RFS;
6726 }
6727
6728 rc = bnxt_alloc_mem(bp, irq_re_init);
6729 if (rc) {
6730 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6731 goto open_err_free_mem;
6732 }
6733
6734 if (irq_re_init) {
6735 bnxt_init_napi(bp);
6736 rc = bnxt_request_irq(bp);
6737 if (rc) {
6738 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6739 goto open_err;
6740 }
6741 }
6742
6743 bnxt_enable_napi(bp);
6744
6745 rc = bnxt_init_nic(bp, irq_re_init);
6746 if (rc) {
6747 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6748 goto open_err;
6749 }
6750
6751 if (link_re_init) {
e2dc9b6e 6752 mutex_lock(&bp->link_lock);
c0c050c5 6753 rc = bnxt_update_phy_setting(bp);
e2dc9b6e 6754 mutex_unlock(&bp->link_lock);
c0c050c5 6755 if (rc)
ba41d46f 6756 netdev_warn(bp->dev, "failed to update phy settings\n");
c0c050c5
MC		 6757 }
6758
7cdd5fc3 6759 if (irq_re_init)
ad51b8e9 6760 udp_tunnel_get_rx_info(bp->dev);
c0c050c5 6761
caefe526 6762 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 6763 bnxt_enable_int(bp);
6764 /* Enable TX queues */
6765 bnxt_tx_enable(bp);
6766 mod_timer(&bp->timer, jiffies + bp->current_interval);
10289bec
MC		 6767 /* Poll link status and check for SFP+ module status */
6768 bnxt_get_port_module_status(bp);
c0c050c5 6769
ee5c7fb3
SP		 6770 /* VF-reps may need to be re-opened after the PF is re-opened */
6771 if (BNXT_PF(bp))
6772 bnxt_vf_reps_open(bp);
c0c050c5
MC		 6773 return 0;
6774
6775open_err:
6776 bnxt_disable_napi(bp);
6777 bnxt_del_napi(bp);
6778
6779open_err_free_mem:
6780 bnxt_free_skbs(bp);
6781 bnxt_free_irq(bp);
6782 bnxt_free_mem(bp, true);
6783 return rc;
6784}
6785
6786/* rtnl_lock held */
6787int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6788{
6789 int rc = 0;
6790
6791 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6792 if (rc) {
6793 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6794 dev_close(bp->dev);
6795 }
6796 return rc;
6797}
6798
f7dc1ea6
MC		 6799/* rtnl_lock held, open the NIC half way by allocating all resources, but
6800 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
6801 * self tests.
6802 */
6803int bnxt_half_open_nic(struct bnxt *bp)
6804{
6805 int rc = 0;
6806
6807 rc = bnxt_alloc_mem(bp, false);
6808 if (rc) {
6809 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6810 goto half_open_err;
6811 }
6812 rc = bnxt_init_nic(bp, false);
6813 if (rc) {
6814 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6815 goto half_open_err;
6816 }
6817 return 0;
6818
6819half_open_err:
6820 bnxt_free_skbs(bp);
6821 bnxt_free_mem(bp, false);
6822 dev_close(bp->dev);
6823 return rc;
6824}
6825
6826/* rtnl_lock held, this call can only be made after a previous successful
6827 * call to bnxt_half_open_nic().
6828 */
6829void bnxt_half_close_nic(struct bnxt *bp)
6830{
6831 bnxt_hwrm_resource_free(bp, false, false);
6832 bnxt_free_skbs(bp);
6833 bnxt_free_mem(bp, false);
6834}
6835
c0c050c5
MC		 6836static int bnxt_open(struct net_device *dev)
6837{
6838 struct bnxt *bp = netdev_priv(dev);
c0c050c5 6839
c0c050c5
MC		 6840 return __bnxt_open_nic(bp, true, true);
6841}
6842
f9b76ebd
MC		 6843static bool bnxt_drv_busy(struct bnxt *bp)
6844{
6845 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
6846 test_bit(BNXT_STATE_READ_STATS, &bp->state));
6847}
6848
86e953db
MC		 6849static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
6850 bool link_re_init)
c0c050c5 6851{
ee5c7fb3
SP		 6852 /* Close the VF-reps before closing PF */
6853 if (BNXT_PF(bp))
6854 bnxt_vf_reps_close(bp);
86e953db 6855
c0c050c5
MC		 6856 /* Change device state to avoid TX queue wake up's */
6857 bnxt_tx_disable(bp);
6858
caefe526 6859 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec 6860 smp_mb__after_atomic();
f9b76ebd 6861 while (bnxt_drv_busy(bp))
4cebdcec 6862 msleep(20);
c0c050c5 6863
9d8bc097 6864 /* Flush rings and and disable interrupts */
c0c050c5
MC		 6865 bnxt_shutdown_nic(bp, irq_re_init);
6866
6867 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6868
6869 bnxt_disable_napi(bp);
c0c050c5
MC		 6870 del_timer_sync(&bp->timer);
6871 bnxt_free_skbs(bp);
6872
6873 if (irq_re_init) {
6874 bnxt_free_irq(bp);
6875 bnxt_del_napi(bp);
6876 }
6877 bnxt_free_mem(bp, irq_re_init);
86e953db
MC		 6878}
6879
6880int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6881{
6882 int rc = 0;
6883
6884#ifdef CONFIG_BNXT_SRIOV
6885 if (bp->sriov_cfg) {
6886 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6887 !bp->sriov_cfg,
6888 BNXT_SRIOV_CFG_WAIT_TMO);
6889 if (rc)
6890 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6891 }
6892#endif
6893 __bnxt_close_nic(bp, irq_re_init, link_re_init);
c0c050c5
MC		 6894 return rc;
6895}
6896
6897static int bnxt_close(struct net_device *dev)
6898{
6899 struct bnxt *bp = netdev_priv(dev);
6900
6901 bnxt_close_nic(bp, true, true);
33f7d55f 6902 bnxt_hwrm_shutdown_link(bp);
c0c050c5
MC		 6903 return 0;
6904}
6905
6906/* rtnl_lock held */
6907static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6908{
6909 switch (cmd) {
6910 case SIOCGMIIPHY:
6911 /* fallthru */
6912 case SIOCGMIIREG: {
6913 if (!netif_running(dev))
6914 return -EAGAIN;
6915
6916 return 0;
6917 }
6918
6919 case SIOCSMIIREG:
6920 if (!netif_running(dev))
6921 return -EAGAIN;
6922
6923 return 0;
6924
6925 default:
6926 /* do nothing */
6927 break;
6928 }
6929 return -EOPNOTSUPP;
6930}
6931
bc1f4470 6932static void
c0c050c5
MC		 6933bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6934{
6935 u32 i;
6936 struct bnxt *bp = netdev_priv(dev);
6937
f9b76ebd
MC		 6938 set_bit(BNXT_STATE_READ_STATS, &bp->state);
6939 /* Make sure bnxt_close_nic() sees that we are reading stats before
6940 * we check the BNXT_STATE_OPEN flag.
6941 */
6942 smp_mb__after_atomic();
6943 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6944 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
bc1f4470 6945 return;
f9b76ebd 6946 }
c0c050c5
MC		 6947
6948 /* TODO check if we need to synchronize with bnxt_close path */
6949 for (i = 0; i < bp->cp_nr_rings; i++) {
6950 struct bnxt_napi *bnapi = bp->bnapi[i];
6951 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6952 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6953
6954 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6955 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6956 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6957
6958 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6959 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6960 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6961
6962 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6963 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6964 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6965
6966 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6967 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6968 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6969
6970 stats->rx_missed_errors +=
6971 le64_to_cpu(hw_stats->rx_discard_pkts);
6972
6973 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6974
c0c050c5
MC		 6975 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6976 }
6977
9947f83f
MC		 6978 if (bp->flags & BNXT_FLAG_PORT_STATS) {
6979 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6980 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6981
6982 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6983 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6984 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6985 le64_to_cpu(rx->rx_ovrsz_frames) +
6986 le64_to_cpu(rx->rx_runt_frames);
6987 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6988 le64_to_cpu(rx->rx_jbr_frames);
6989 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6990 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6991 stats->tx_errors = le64_to_cpu(tx->tx_err);
6992 }
f9b76ebd 6993 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
c0c050c5
MC		 6994}
6995
6996static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6997{
6998 struct net_device *dev = bp->dev;
6999 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7000 struct netdev_hw_addr *ha;
7001 u8 *haddr;
7002 int mc_count = 0;
7003 bool update = false;
7004 int off = 0;
7005
7006 netdev_for_each_mc_addr(ha, dev) {
7007 if (mc_count >= BNXT_MAX_MC_ADDRS) {
7008 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7009 vnic->mc_list_count = 0;
7010 return false;
7011 }
7012 haddr = ha->addr;
7013 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
7014 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
7015 update = true;
7016 }
7017 off += ETH_ALEN;
7018 mc_count++;
7019 }
7020 if (mc_count)
7021 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
7022
7023 if (mc_count != vnic->mc_list_count) {
7024 vnic->mc_list_count = mc_count;
7025 update = true;
7026 }
7027 return update;
7028}
7029
7030static bool bnxt_uc_list_updated(struct bnxt *bp)
7031{
7032 struct net_device *dev = bp->dev;
7033 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7034 struct netdev_hw_addr *ha;
7035 int off = 0;
7036
7037 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
7038 return true;
7039
7040 netdev_for_each_uc_addr(ha, dev) {
7041 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
7042 return true;
7043
7044 off += ETH_ALEN;
7045 }
7046 return false;
7047}
7048
7049static void bnxt_set_rx_mode(struct net_device *dev)
7050{
7051 struct bnxt *bp = netdev_priv(dev);
7052 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7053 u32 mask = vnic->rx_mask;
7054 bool mc_update = false;
7055 bool uc_update;
7056
7057 if (!netif_running(dev))
7058 return;
7059
7060 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
7061 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
7062 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
7063
17c71ac3 7064 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
c0c050c5
MC		 7065 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7066
7067 uc_update = bnxt_uc_list_updated(bp);
7068
7069 if (dev->flags & IFF_ALLMULTI) {
7070 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7071 vnic->mc_list_count = 0;
7072 } else {
7073 mc_update = bnxt_mc_list_updated(bp, &mask);
7074 }
7075
7076 if (mask != vnic->rx_mask || uc_update || mc_update) {
7077 vnic->rx_mask = mask;
7078
7079 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
c213eae8 7080 bnxt_queue_sp_work(bp);
c0c050c5
MC		 7081 }
7082}
7083
b664f008 7084static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 7085{
7086 struct net_device *dev = bp->dev;
7087 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7088 struct netdev_hw_addr *ha;
7089 int i, off = 0, rc;
7090 bool uc_update;
7091
7092 netif_addr_lock_bh(dev);
7093 uc_update = bnxt_uc_list_updated(bp);
7094 netif_addr_unlock_bh(dev);
7095
7096 if (!uc_update)
7097 goto skip_uc;
7098
7099 mutex_lock(&bp->hwrm_cmd_lock);
7100 for (i = 1; i < vnic->uc_filter_count; i++) {
7101 struct hwrm_cfa_l2_filter_free_input req = {0};
7102
7103 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
7104 -1);
7105
7106 req.l2_filter_id = vnic->fw_l2_filter_id[i];
7107
7108 rc = _hwrm_send_message(bp, &req, sizeof(req),
7109 HWRM_CMD_TIMEOUT);
7110 }
7111 mutex_unlock(&bp->hwrm_cmd_lock);
7112
7113 vnic->uc_filter_count = 1;
7114
7115 netif_addr_lock_bh(dev);
7116 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
7117 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7118 } else {
7119 netdev_for_each_uc_addr(ha, dev) {
7120 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
7121 off += ETH_ALEN;
7122 vnic->uc_filter_count++;
7123 }
7124 }
7125 netif_addr_unlock_bh(dev);
7126
7127 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
7128 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
7129 if (rc) {
7130 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
7131 rc);
7132 vnic->uc_filter_count = i;
b664f008 7133 return rc;
c0c050c5
MC		 7134 }
7135 }
7136
7137skip_uc:
7138 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
7139 if (rc)
7140 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
7141 rc);
b664f008
MC		 7142
7143 return rc;
c0c050c5
MC		 7144}
7145
8079e8f1
MC		 7146/* If the chip and firmware supports RFS */
7147static bool bnxt_rfs_supported(struct bnxt *bp)
7148{
7149 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
7150 return true;
ae10ae74
MC		 7151 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7152 return true;
8079e8f1
MC		 7153 return false;
7154}
7155
7156/* If runtime conditions support RFS */
2bcfa6f6
MC		 7157static bool bnxt_rfs_capable(struct bnxt *bp)
7158{
7159#ifdef CONFIG_RFS_ACCEL
8079e8f1 7160 int vnics, max_vnics, max_rss_ctxs;
2bcfa6f6 7161
964fd480 7162 if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
2bcfa6f6
MC		 7163 return false;
7164
7165 vnics = 1 + bp->rx_nr_rings;
8079e8f1
MC		 7166 max_vnics = bnxt_get_max_func_vnics(bp);
7167 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
ae10ae74
MC		 7168
7169 /* RSS contexts not a limiting factor */
7170 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7171 max_rss_ctxs = max_vnics;
8079e8f1 7172 if (vnics > max_vnics || vnics > max_rss_ctxs) {
6a1eef5b
MC		 7173 if (bp->rx_nr_rings > 1)
7174 netdev_warn(bp->dev,
7175 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
7176 min(max_rss_ctxs - 1, max_vnics - 1));
2bcfa6f6 7177 return false;
a2304909 7178 }
2bcfa6f6 7179
6a1eef5b
MC		 7180 if (!(bp->flags & BNXT_FLAG_NEW_RM))
7181 return true;
7182
7183 if (vnics == bp->hw_resc.resv_vnics)
7184 return true;
7185
7186 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics);
7187 if (vnics <= bp->hw_resc.resv_vnics)
7188 return true;
7189
7190 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
7191 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1);
7192 return false;
2bcfa6f6
MC		 7193#else
7194 return false;
7195#endif
7196}
7197
c0c050c5
MC		 7198static netdev_features_t bnxt_fix_features(struct net_device *dev,
7199 netdev_features_t features)
7200{
2bcfa6f6
MC		 7201 struct bnxt *bp = netdev_priv(dev);
7202
a2304909 7203 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
2bcfa6f6 7204 features &= ~NETIF_F_NTUPLE;
5a9f6b23 7205
1054aee8
MC		 7206 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7207 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
7208
7209 if (!(features & NETIF_F_GRO))
7210 features &= ~NETIF_F_GRO_HW;
7211
7212 if (features & NETIF_F_GRO_HW)
7213 features &= ~NETIF_F_LRO;
7214
5a9f6b23
MC		 7215 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
7216 * turned on or off together.
7217 */
7218 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
7219 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
7220 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
7221 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7222 NETIF_F_HW_VLAN_STAG_RX);
7223 else
7224 features |= NETIF_F_HW_VLAN_CTAG_RX |
7225 NETIF_F_HW_VLAN_STAG_RX;
7226 }
cf6645f8
MC		 7227#ifdef CONFIG_BNXT_SRIOV
7228 if (BNXT_VF(bp)) {
7229 if (bp->vf.vlan) {
7230 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7231 NETIF_F_HW_VLAN_STAG_RX);
7232 }
7233 }
7234#endif
c0c050c5
MC		 7235 return features;
7236}
7237
7238static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
7239{
7240 struct bnxt *bp = netdev_priv(dev);
7241 u32 flags = bp->flags;
7242 u32 changes;
7243 int rc = 0;
7244 bool re_init = false;
7245 bool update_tpa = false;
7246
7247 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
1054aee8 7248 if (features & NETIF_F_GRO_HW)
c0c050c5 7249 flags |= BNXT_FLAG_GRO;
1054aee8 7250 else if (features & NETIF_F_LRO)
c0c050c5
MC		 7251 flags |= BNXT_FLAG_LRO;
7252
bdbd1eb5
MC		 7253 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7254 flags &= ~BNXT_FLAG_TPA;
7255
c0c050c5
MC		 7256 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7257 flags |= BNXT_FLAG_STRIP_VLAN;
7258
7259 if (features & NETIF_F_NTUPLE)
7260 flags |= BNXT_FLAG_RFS;
7261
7262 changes = flags ^ bp->flags;
7263 if (changes & BNXT_FLAG_TPA) {
7264 update_tpa = true;
7265 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
7266 (flags & BNXT_FLAG_TPA) == 0)
7267 re_init = true;
7268 }
7269
7270 if (changes & ~BNXT_FLAG_TPA)
7271 re_init = true;
7272
7273 if (flags != bp->flags) {
7274 u32 old_flags = bp->flags;
7275
7276 bp->flags = flags;
7277
2bcfa6f6 7278 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 7279 if (update_tpa)
7280 bnxt_set_ring_params(bp);
7281 return rc;
7282 }
7283
7284 if (re_init) {
7285 bnxt_close_nic(bp, false, false);
7286 if (update_tpa)
7287 bnxt_set_ring_params(bp);
7288
7289 return bnxt_open_nic(bp, false, false);
7290 }
7291 if (update_tpa) {
7292 rc = bnxt_set_tpa(bp,
7293 (flags & BNXT_FLAG_TPA) ?
7294 true : false);
7295 if (rc)
7296 bp->flags = old_flags;
7297 }
7298 }
7299 return rc;
7300}
7301
9f554590
MC		 7302static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
7303{
b6ab4b01 7304 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 7305 int i = bnapi->index;
7306
3b2b7d9d
MC		 7307 if (!txr)
7308 return;
7309
9f554590
MC		 7310 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
7311 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
7312 txr->tx_cons);
7313}
7314
7315static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
7316{
b6ab4b01 7317 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 7318 int i = bnapi->index;
7319
3b2b7d9d
MC		 7320 if (!rxr)
7321 return;
7322
9f554590
MC		 7323 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
7324 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
7325 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
7326 rxr->rx_sw_agg_prod);
7327}
7328
7329static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
7330{
7331 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7332 int i = bnapi->index;
7333
7334 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
7335 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
7336}
7337
c0c050c5
MC		 7338static void bnxt_dbg_dump_states(struct bnxt *bp)
7339{
7340 int i;
7341 struct bnxt_napi *bnapi;
c0c050c5
MC		 7342
7343 for (i = 0; i < bp->cp_nr_rings; i++) {
7344 bnapi = bp->bnapi[i];
c0c050c5 7345 if (netif_msg_drv(bp)) {
9f554590
MC		 7346 bnxt_dump_tx_sw_state(bnapi);
7347 bnxt_dump_rx_sw_state(bnapi);
7348 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 7349 }
7350 }
7351}
7352
6988bd92 7353static void bnxt_reset_task(struct bnxt *bp, bool silent)
c0c050c5 7354{
6988bd92
MC		 7355 if (!silent)
7356 bnxt_dbg_dump_states(bp);
028de140 7357 if (netif_running(bp->dev)) {
b386cd36
MC		 7358 int rc;
7359
7360 if (!silent)
7361 bnxt_ulp_stop(bp);
028de140 7362 bnxt_close_nic(bp, false, false);
b386cd36
MC		 7363 rc = bnxt_open_nic(bp, false, false);
7364 if (!silent && !rc)
7365 bnxt_ulp_start(bp);
028de140 7366 }
c0c050c5
MC		 7367}
7368
7369static void bnxt_tx_timeout(struct net_device *dev)
7370{
7371 struct bnxt *bp = netdev_priv(dev);
7372
7373 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
7374 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
c213eae8 7375 bnxt_queue_sp_work(bp);
c0c050c5
MC		 7376}
7377
7378#ifdef CONFIG_NET_POLL_CONTROLLER
7379static void bnxt_poll_controller(struct net_device *dev)
7380{
7381 struct bnxt *bp = netdev_priv(dev);
7382 int i;
7383
2270bc5d
MC		 7384 /* Only process tx rings/combined rings in netpoll mode. */
7385 for (i = 0; i < bp->tx_nr_rings; i++) {
7386 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5 7387
2270bc5d 7388 napi_schedule(&txr->bnapi->napi);
c0c050c5
MC		 7389 }
7390}
7391#endif
7392
e99e88a9 7393static void bnxt_timer(struct timer_list *t)
c0c050c5 7394{
e99e88a9 7395 struct bnxt *bp = from_timer(bp, t, timer);
c0c050c5
MC		 7396 struct net_device *dev = bp->dev;
7397
7398 if (!netif_running(dev))
7399 return;
7400
7401 if (atomic_read(&bp->intr_sem) != 0)
7402 goto bnxt_restart_timer;
7403
adcc331e
MC		 7404 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
7405 bp->stats_coal_ticks) {
3bdf56c4 7406 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
c213eae8 7407 bnxt_queue_sp_work(bp);
3bdf56c4 7408 }
5a84acbe
SP		 7409
7410 if (bnxt_tc_flower_enabled(bp)) {
7411 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
7412 bnxt_queue_sp_work(bp);
7413 }
c0c050c5
MC		 7414bnxt_restart_timer:
7415 mod_timer(&bp->timer, jiffies + bp->current_interval);
7416}
7417
a551ee94 7418static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6988bd92 7419{
a551ee94
MC		 7420 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
7421 * set. If the device is being closed, bnxt_close() may be holding
6988bd92
MC		 7422 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
7423 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7424 */
7425 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7426 rtnl_lock();
a551ee94
MC		 7427}
7428
7429static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7430{
6988bd92
MC		 7431 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7432 rtnl_unlock();
7433}
7434
a551ee94
MC		 7435/* Only called from bnxt_sp_task() */
7436static void bnxt_reset(struct bnxt *bp, bool silent)
7437{
7438 bnxt_rtnl_lock_sp(bp);
7439 if (test_bit(BNXT_STATE_OPEN, &bp->state))
7440 bnxt_reset_task(bp, silent);
7441 bnxt_rtnl_unlock_sp(bp);
7442}
7443
c0c050c5
MC		 7444static void bnxt_cfg_ntp_filters(struct bnxt *);
7445
7446static void bnxt_sp_task(struct work_struct *work)
7447{
7448 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
c0c050c5 7449
4cebdcec
MC		 7450 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7451 smp_mb__after_atomic();
7452 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7453 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 7454 return;
4cebdcec 7455 }
c0c050c5
MC		 7456
7457 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7458 bnxt_cfg_rx_mode(bp);
7459
7460 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7461 bnxt_cfg_ntp_filters(bp);
c0c050c5
MC		 7462 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7463 bnxt_hwrm_exec_fwd_req(bp);
7464 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7465 bnxt_hwrm_tunnel_dst_port_alloc(
7466 bp, bp->vxlan_port,
7467 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7468 }
7469 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7470 bnxt_hwrm_tunnel_dst_port_free(
7471 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7472 }
7cdd5fc3
AD		 7473 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7474 bnxt_hwrm_tunnel_dst_port_alloc(
7475 bp, bp->nge_port,
7476 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7477 }
7478 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7479 bnxt_hwrm_tunnel_dst_port_free(
7480 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7481 }
3bdf56c4
MC		 7482 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
7483 bnxt_hwrm_port_qstats(bp);
7484
0eaa24b9 7485 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
e2dc9b6e 7486 int rc;
0eaa24b9 7487
e2dc9b6e 7488 mutex_lock(&bp->link_lock);
0eaa24b9
MC		 7489 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7490 &bp->sp_event))
7491 bnxt_hwrm_phy_qcaps(bp);
7492
e2dc9b6e
MC		 7493 rc = bnxt_update_link(bp, true);
7494 mutex_unlock(&bp->link_lock);
0eaa24b9
MC		 7495 if (rc)
7496 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7497 rc);
7498 }
90c694bb 7499 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
e2dc9b6e
MC		 7500 mutex_lock(&bp->link_lock);
7501 bnxt_get_port_module_status(bp);
7502 mutex_unlock(&bp->link_lock);
90c694bb 7503 }
5a84acbe
SP		 7504
7505 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7506 bnxt_tc_flow_stats_work(bp);
7507
e2dc9b6e
MC		 7508 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
7509 * must be the last functions to be called before exiting.
7510 */
6988bd92
MC		 7511 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7512 bnxt_reset(bp, false);
4cebdcec 7513
fc0f1929
MC		 7514 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7515 bnxt_reset(bp, true);
7516
4cebdcec
MC		 7517 smp_mb__before_atomic();
7518 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 7519}
7520
d1e7925e 7521/* Under rtnl_lock */
98fdbe73
MC		 7522int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7523 int tx_xdp)
d1e7925e
MC		 7524{
7525 int max_rx, max_tx, tx_sets = 1;
7526 int tx_rings_needed;
8f23d638
MC		 7527 int rx_rings = rx;
7528 int cp, rc;
d1e7925e 7529
d1e7925e
MC		 7530 if (tcs)
7531 tx_sets = tcs;
7532
7533 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7534 if (rc)
7535 return rc;
7536
7537 if (max_rx < rx)
7538 return -ENOMEM;
7539
5f449249 7540 tx_rings_needed = tx * tx_sets + tx_xdp;
d1e7925e
MC		 7541 if (max_tx < tx_rings_needed)
7542 return -ENOMEM;
7543
8f23d638
MC		 7544 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7545 rx_rings <<= 1;
7546 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
7547 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp);
d1e7925e
MC		 7548}
7549
17086399
SP		 7550static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7551{
7552 if (bp->bar2) {
7553 pci_iounmap(pdev, bp->bar2);
7554 bp->bar2 = NULL;
7555 }
7556
7557 if (bp->bar1) {
7558 pci_iounmap(pdev, bp->bar1);
7559 bp->bar1 = NULL;
7560 }
7561
7562 if (bp->bar0) {
7563 pci_iounmap(pdev, bp->bar0);
7564 bp->bar0 = NULL;
7565 }
7566}
7567
7568static void bnxt_cleanup_pci(struct bnxt *bp)
7569{
7570 bnxt_unmap_bars(bp, bp->pdev);
7571 pci_release_regions(bp->pdev);
7572 pci_disable_device(bp->pdev);
7573}
7574
18775aa8
MC		 7575static void bnxt_init_dflt_coal(struct bnxt *bp)
7576{
7577 struct bnxt_coal *coal;
7578
7579 /* Tick values in micro seconds.
7580 * 1 coal_buf x bufs_per_record = 1 completion record.
7581 */
7582 coal = &bp->rx_coal;
7583 coal->coal_ticks = 14;
7584 coal->coal_bufs = 30;
7585 coal->coal_ticks_irq = 1;
7586 coal->coal_bufs_irq = 2;
7587 coal->idle_thresh = 25;
7588 coal->bufs_per_record = 2;
7589 coal->budget = 64; /* NAPI budget */
7590
7591 coal = &bp->tx_coal;
7592 coal->coal_ticks = 28;
7593 coal->coal_bufs = 30;
7594 coal->coal_ticks_irq = 2;
7595 coal->coal_bufs_irq = 2;
7596 coal->bufs_per_record = 1;
7597
7598 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7599}
7600
c0c050c5
MC		 7601static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7602{
7603 int rc;
7604 struct bnxt *bp = netdev_priv(dev);
7605
7606 SET_NETDEV_DEV(dev, &pdev->dev);
7607
7608 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7609 rc = pci_enable_device(pdev);
7610 if (rc) {
7611 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7612 goto init_err;
7613 }
7614
7615 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7616 dev_err(&pdev->dev,
7617 "Cannot find PCI device base address, aborting\n");
7618 rc = -ENODEV;
7619 goto init_err_disable;
7620 }
7621
7622 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7623 if (rc) {
7624 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7625 goto init_err_disable;
7626 }
7627
7628 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
7629 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
7630 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7631 goto init_err_disable;
7632 }
7633
7634 pci_set_master(pdev);
7635
7636 bp->dev = dev;
7637 bp->pdev = pdev;
7638
7639 bp->bar0 = pci_ioremap_bar(pdev, 0);
7640 if (!bp->bar0) {
7641 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
7642 rc = -ENOMEM;
7643 goto init_err_release;
7644 }
7645
7646 bp->bar1 = pci_ioremap_bar(pdev, 2);
7647 if (!bp->bar1) {
7648 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
7649 rc = -ENOMEM;
7650 goto init_err_release;
7651 }
7652
7653 bp->bar2 = pci_ioremap_bar(pdev, 4);
7654 if (!bp->bar2) {
7655 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
7656 rc = -ENOMEM;
7657 goto init_err_release;
7658 }
7659
6316ea6d
SB		 7660 pci_enable_pcie_error_reporting(pdev);
7661
c0c050c5
MC		 7662 INIT_WORK(&bp->sp_task, bnxt_sp_task);
7663
7664 spin_lock_init(&bp->ntp_fltr_lock);
7665
7666 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
7667 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
7668
18775aa8 7669 bnxt_init_dflt_coal(bp);
51f30785 7670
e99e88a9 7671 timer_setup(&bp->timer, bnxt_timer, 0);
c0c050c5
MC		 7672 bp->current_interval = BNXT_TIMER_INTERVAL;
7673
caefe526 7674 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 7675 return 0;
7676
7677init_err_release:
17086399 7678 bnxt_unmap_bars(bp, pdev);
c0c050c5
MC		 7679 pci_release_regions(pdev);
7680
7681init_err_disable:
7682 pci_disable_device(pdev);
7683
7684init_err:
7685 return rc;
7686}
7687
7688/* rtnl_lock held */
7689static int bnxt_change_mac_addr(struct net_device *dev, void *p)
7690{
7691 struct sockaddr *addr = p;
1fc2cfd0
JH		 7692 struct bnxt *bp = netdev_priv(dev);
7693 int rc = 0;
c0c050c5
MC		 7694
7695 if (!is_valid_ether_addr(addr->sa_data))
7696 return -EADDRNOTAVAIL;
7697
c1a7bdff
MC		 7698 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
7699 return 0;
7700
84c33dd3
MC		 7701 rc = bnxt_approve_mac(bp, addr->sa_data);
7702 if (rc)
7703 return rc;
bdd4347b 7704
c0c050c5 7705 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 7706 if (netif_running(dev)) {
7707 bnxt_close_nic(bp, false, false);
7708 rc = bnxt_open_nic(bp, false, false);
7709 }
c0c050c5 7710
1fc2cfd0 7711 return rc;
c0c050c5
MC		 7712}
7713
7714/* rtnl_lock held */
7715static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
7716{
7717 struct bnxt *bp = netdev_priv(dev);
7718
c0c050c5
MC		 7719 if (netif_running(dev))
7720 bnxt_close_nic(bp, false, false);
7721
7722 dev->mtu = new_mtu;
7723 bnxt_set_ring_params(bp);
7724
7725 if (netif_running(dev))
7726 return bnxt_open_nic(bp, false, false);
7727
7728 return 0;
7729}
7730
c5e3deb8 7731int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
c0c050c5
MC		 7732{
7733 struct bnxt *bp = netdev_priv(dev);
3ffb6a39 7734 bool sh = false;
d1e7925e 7735 int rc;
16e5cc64 7736
c0c050c5 7737 if (tc > bp->max_tc) {
b451c8b6 7738 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
c0c050c5
MC		 7739 tc, bp->max_tc);
7740 return -EINVAL;
7741 }
7742
7743 if (netdev_get_num_tc(dev) == tc)
7744 return 0;
7745
3ffb6a39
MC		 7746 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7747 sh = true;
7748
98fdbe73
MC		 7749 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7750 sh, tc, bp->tx_nr_rings_xdp);
d1e7925e
MC		 7751 if (rc)
7752 return rc;
c0c050c5
MC		 7753
7754 /* Needs to close the device and do hw resource re-allocations */
7755 if (netif_running(bp->dev))
7756 bnxt_close_nic(bp, true, false);
7757
7758 if (tc) {
7759 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7760 netdev_set_num_tc(dev, tc);
7761 } else {
7762 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7763 netdev_reset_tc(dev);
7764 }
87e9b377 7765 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
3ffb6a39
MC		 7766 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7767 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5
MC		 7768 bp->num_stat_ctxs = bp->cp_nr_rings;
7769
7770 if (netif_running(bp->dev))
7771 return bnxt_open_nic(bp, true, false);
7772
7773 return 0;
7774}
7775
9e0fd15d
JP		 7776static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
7777 void *cb_priv)
c5e3deb8 7778{
9e0fd15d 7779 struct bnxt *bp = cb_priv;
de4784ca 7780
44ae12a7 7781 if (!bnxt_tc_flower_enabled(bp) || !tc_can_offload(bp->dev))
38cf0426 7782 return -EOPNOTSUPP;
c5e3deb8 7783
9e0fd15d
JP		 7784 switch (type) {
7785 case TC_SETUP_CLSFLOWER:
7786 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
7787 default:
7788 return -EOPNOTSUPP;
7789 }
7790}
7791
7792static int bnxt_setup_tc_block(struct net_device *dev,
7793 struct tc_block_offload *f)
7794{
7795 struct bnxt *bp = netdev_priv(dev);
7796
7797 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
7798 return -EOPNOTSUPP;
7799
7800 switch (f->command) {
7801 case TC_BLOCK_BIND:
7802 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
7803 bp, bp);
7804 case TC_BLOCK_UNBIND:
7805 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
7806 return 0;
7807 default:
7808 return -EOPNOTSUPP;
7809 }
2ae7408f
SP		 7810}
7811
7812static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
7813 void *type_data)
7814{
7815 switch (type) {
9e0fd15d
JP		 7816 case TC_SETUP_BLOCK:
7817 return bnxt_setup_tc_block(dev, type_data);
575ed7d3 7818 case TC_SETUP_QDISC_MQPRIO: {
2ae7408f
SP		 7819 struct tc_mqprio_qopt *mqprio = type_data;
7820
7821 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
56f36acd 7822
2ae7408f
SP		 7823 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
7824 }
7825 default:
7826 return -EOPNOTSUPP;
7827 }
c5e3deb8
MC		 7828}
7829
c0c050c5
MC		 7830#ifdef CONFIG_RFS_ACCEL
7831static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7832 struct bnxt_ntuple_filter *f2)
7833{
7834 struct flow_keys *keys1 = &f1->fkeys;
7835 struct flow_keys *keys2 = &f2->fkeys;
7836
7837 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
7838 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
7839 keys1->ports.ports == keys2->ports.ports &&
7840 keys1->basic.ip_proto == keys2->basic.ip_proto &&
7841 keys1->basic.n_proto == keys2->basic.n_proto &&
61aad724 7842 keys1->control.flags == keys2->control.flags &&
a54c4d74
MC		 7843 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7844 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
c0c050c5
MC		 7845 return true;
7846
7847 return false;
7848}
7849
7850static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7851 u16 rxq_index, u32 flow_id)
7852{
7853 struct bnxt *bp = netdev_priv(dev);
7854 struct bnxt_ntuple_filter *fltr, *new_fltr;
7855 struct flow_keys *fkeys;
7856 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
a54c4d74 7857 int rc = 0, idx, bit_id, l2_idx = 0;
c0c050c5
MC		 7858 struct hlist_head *head;
7859
a54c4d74
MC		 7860 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
7861 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7862 int off = 0, j;
7863
7864 netif_addr_lock_bh(dev);
7865 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
7866 if (ether_addr_equal(eth->h_dest,
7867 vnic->uc_list + off)) {
7868 l2_idx = j + 1;
7869 break;
7870 }
7871 }
7872 netif_addr_unlock_bh(dev);
7873 if (!l2_idx)
7874 return -EINVAL;
7875 }
c0c050c5
MC		 7876 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
7877 if (!new_fltr)
7878 return -ENOMEM;
7879
7880 fkeys = &new_fltr->fkeys;
7881 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
7882 rc = -EPROTONOSUPPORT;
7883 goto err_free;
7884 }
7885
dda0e746
MC		 7886 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
7887 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
c0c050c5
MC		 7888 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
7889 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
7890 rc = -EPROTONOSUPPORT;
7891 goto err_free;
7892 }
dda0e746
MC		 7893 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
7894 bp->hwrm_spec_code < 0x10601) {
7895 rc = -EPROTONOSUPPORT;
7896 goto err_free;
7897 }
61aad724
MC		 7898 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
7899 bp->hwrm_spec_code < 0x10601) {
7900 rc = -EPROTONOSUPPORT;
7901 goto err_free;
7902 }
c0c050c5 7903
a54c4d74 7904 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
c0c050c5
MC		 7905 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
7906
7907 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
7908 head = &bp->ntp_fltr_hash_tbl[idx];
7909 rcu_read_lock();
7910 hlist_for_each_entry_rcu(fltr, head, hash) {
7911 if (bnxt_fltr_match(fltr, new_fltr)) {
7912 rcu_read_unlock();
7913 rc = 0;
7914 goto err_free;
7915 }
7916 }
7917 rcu_read_unlock();
7918
7919 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 7920 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
7921 BNXT_NTP_FLTR_MAX_FLTR, 0);
7922 if (bit_id < 0) {
c0c050c5
MC		 7923 spin_unlock_bh(&bp->ntp_fltr_lock);
7924 rc = -ENOMEM;
7925 goto err_free;
7926 }
7927
84e86b98 7928 new_fltr->sw_id = (u16)bit_id;
c0c050c5 7929 new_fltr->flow_id = flow_id;
a54c4d74 7930 new_fltr->l2_fltr_idx = l2_idx;
c0c050c5
MC		 7931 new_fltr->rxq = rxq_index;
7932 hlist_add_head_rcu(&new_fltr->hash, head);
7933 bp->ntp_fltr_count++;
7934 spin_unlock_bh(&bp->ntp_fltr_lock);
7935
7936 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
c213eae8 7937 bnxt_queue_sp_work(bp);
c0c050c5
MC		 7938
7939 return new_fltr->sw_id;
7940
7941err_free:
7942 kfree(new_fltr);
7943 return rc;
7944}
7945
7946static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7947{
7948 int i;
7949
7950 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7951 struct hlist_head *head;
7952 struct hlist_node *tmp;
7953 struct bnxt_ntuple_filter *fltr;
7954 int rc;
7955
7956 head = &bp->ntp_fltr_hash_tbl[i];
7957 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7958 bool del = false;
7959
7960 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7961 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7962 fltr->flow_id,
7963 fltr->sw_id)) {
7964 bnxt_hwrm_cfa_ntuple_filter_free(bp,
7965 fltr);
7966 del = true;
7967 }
7968 } else {
7969 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7970 fltr);
7971 if (rc)
7972 del = true;
7973 else
7974 set_bit(BNXT_FLTR_VALID, &fltr->state);
7975 }
7976
7977 if (del) {
7978 spin_lock_bh(&bp->ntp_fltr_lock);
7979 hlist_del_rcu(&fltr->hash);
7980 bp->ntp_fltr_count--;
7981 spin_unlock_bh(&bp->ntp_fltr_lock);
7982 synchronize_rcu();
7983 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7984 kfree(fltr);
7985 }
7986 }
7987 }
19241368
JH		 7988 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7989 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 7990}
7991
7992#else
7993
7994static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7995{
7996}
7997
7998#endif /* CONFIG_RFS_ACCEL */
7999
ad51b8e9
AD		 8000static void bnxt_udp_tunnel_add(struct net_device *dev,
8001 struct udp_tunnel_info *ti)
c0c050c5
MC		 8002{
8003 struct bnxt *bp = netdev_priv(dev);
8004
ad51b8e9 8005 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 8006 return;
8007
ad51b8e9 8008 if (!netif_running(dev))
c0c050c5
MC		 8009 return;
8010
ad51b8e9
AD		 8011 switch (ti->type) {
8012 case UDP_TUNNEL_TYPE_VXLAN:
8013 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
8014 return;
c0c050c5 8015
ad51b8e9
AD		 8016 bp->vxlan_port_cnt++;
8017 if (bp->vxlan_port_cnt == 1) {
8018 bp->vxlan_port = ti->port;
8019 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
c213eae8 8020 bnxt_queue_sp_work(bp);
ad51b8e9
AD		 8021 }
8022 break;
7cdd5fc3
AD		 8023 case UDP_TUNNEL_TYPE_GENEVE:
8024 if (bp->nge_port_cnt && bp->nge_port != ti->port)
8025 return;
8026
8027 bp->nge_port_cnt++;
8028 if (bp->nge_port_cnt == 1) {
8029 bp->nge_port = ti->port;
8030 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
8031 }
8032 break;
ad51b8e9
AD		 8033 default:
8034 return;
c0c050c5 8035 }
ad51b8e9 8036
c213eae8 8037 bnxt_queue_sp_work(bp);
c0c050c5
MC		 8038}
8039
ad51b8e9
AD		 8040static void bnxt_udp_tunnel_del(struct net_device *dev,
8041 struct udp_tunnel_info *ti)
c0c050c5
MC		 8042{
8043 struct bnxt *bp = netdev_priv(dev);
8044
ad51b8e9 8045 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 8046 return;
8047
ad51b8e9 8048 if (!netif_running(dev))
c0c050c5
MC		 8049 return;
8050
ad51b8e9
AD		 8051 switch (ti->type) {
8052 case UDP_TUNNEL_TYPE_VXLAN:
8053 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
8054 return;
c0c050c5
MC		 8055 bp->vxlan_port_cnt--;
8056
ad51b8e9
AD		 8057 if (bp->vxlan_port_cnt != 0)
8058 return;
8059
8060 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
8061 break;
7cdd5fc3
AD		 8062 case UDP_TUNNEL_TYPE_GENEVE:
8063 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
8064 return;
8065 bp->nge_port_cnt--;
8066
8067 if (bp->nge_port_cnt != 0)
8068 return;
8069
8070 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
8071 break;
ad51b8e9
AD		 8072 default:
8073 return;
c0c050c5 8074 }
ad51b8e9 8075
c213eae8 8076 bnxt_queue_sp_work(bp);
c0c050c5
MC		 8077}
8078
39d8ba2e
MC		 8079static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8080 struct net_device *dev, u32 filter_mask,
8081 int nlflags)
8082{
8083 struct bnxt *bp = netdev_priv(dev);
8084
8085 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
8086 nlflags, filter_mask, NULL);
8087}
8088
8089static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
8090 u16 flags)
8091{
8092 struct bnxt *bp = netdev_priv(dev);
8093 struct nlattr *attr, *br_spec;
8094 int rem, rc = 0;
8095
8096 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
8097 return -EOPNOTSUPP;
8098
8099 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8100 if (!br_spec)
8101 return -EINVAL;
8102
8103 nla_for_each_nested(attr, br_spec, rem) {
8104 u16 mode;
8105
8106 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8107 continue;
8108
8109 if (nla_len(attr) < sizeof(mode))
8110 return -EINVAL;
8111
8112 mode = nla_get_u16(attr);
8113 if (mode == bp->br_mode)
8114 break;
8115
8116 rc = bnxt_hwrm_set_br_mode(bp, mode);
8117 if (!rc)
8118 bp->br_mode = mode;
8119 break;
8120 }
8121 return rc;
8122}
8123
c124a62f
SP		 8124static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
8125 size_t len)
8126{
8127 struct bnxt *bp = netdev_priv(dev);
8128 int rc;
8129
8130 /* The PF and it's VF-reps only support the switchdev framework */
8131 if (!BNXT_PF(bp))
8132 return -EOPNOTSUPP;
8133
53f70b8b 8134 rc = snprintf(buf, len, "p%d", bp->pf.port_id);
c124a62f
SP		 8135
8136 if (rc >= len)
8137 return -EOPNOTSUPP;
8138 return 0;
8139}
8140
8141int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
8142{
8143 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
8144 return -EOPNOTSUPP;
8145
8146 /* The PF and it's VF-reps only support the switchdev framework */
8147 if (!BNXT_PF(bp))
8148 return -EOPNOTSUPP;
8149
8150 switch (attr->id) {
8151 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
8152 /* In SRIOV each PF-pool (PF + child VFs) serves as a
8153 * switching domain, the PF's perm mac-addr can be used
8154 * as the unique parent-id
8155 */
8156 attr->u.ppid.id_len = ETH_ALEN;
8157 ether_addr_copy(attr->u.ppid.id, bp->pf.mac_addr);
8158 break;
8159 default:
8160 return -EOPNOTSUPP;
8161 }
8162 return 0;
8163}
8164
8165static int bnxt_swdev_port_attr_get(struct net_device *dev,
8166 struct switchdev_attr *attr)
8167{
8168 return bnxt_port_attr_get(netdev_priv(dev), attr);
8169}
8170
8171static const struct switchdev_ops bnxt_switchdev_ops = {
8172 .switchdev_port_attr_get = bnxt_swdev_port_attr_get
8173};
8174
c0c050c5
MC		 8175static const struct net_device_ops bnxt_netdev_ops = {
8176 .ndo_open = bnxt_open,
8177 .ndo_start_xmit = bnxt_start_xmit,
8178 .ndo_stop = bnxt_close,
8179 .ndo_get_stats64 = bnxt_get_stats64,
8180 .ndo_set_rx_mode = bnxt_set_rx_mode,
8181 .ndo_do_ioctl = bnxt_ioctl,
8182 .ndo_validate_addr = eth_validate_addr,
8183 .ndo_set_mac_address = bnxt_change_mac_addr,
8184 .ndo_change_mtu = bnxt_change_mtu,
8185 .ndo_fix_features = bnxt_fix_features,
8186 .ndo_set_features = bnxt_set_features,
8187 .ndo_tx_timeout = bnxt_tx_timeout,
8188#ifdef CONFIG_BNXT_SRIOV
8189 .ndo_get_vf_config = bnxt_get_vf_config,
8190 .ndo_set_vf_mac = bnxt_set_vf_mac,
8191 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
8192 .ndo_set_vf_rate = bnxt_set_vf_bw,
8193 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
8194 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
8195#endif
8196#ifdef CONFIG_NET_POLL_CONTROLLER
8197 .ndo_poll_controller = bnxt_poll_controller,
8198#endif
8199 .ndo_setup_tc = bnxt_setup_tc,
8200#ifdef CONFIG_RFS_ACCEL
8201 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
8202#endif
ad51b8e9
AD		 8203 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
8204 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
f4e63525 8205 .ndo_bpf = bnxt_xdp,
39d8ba2e
MC		 8206 .ndo_bridge_getlink = bnxt_bridge_getlink,
8207 .ndo_bridge_setlink = bnxt_bridge_setlink,
c124a62f 8208 .ndo_get_phys_port_name = bnxt_get_phys_port_name
c0c050c5
MC		 8209};
8210
8211static void bnxt_remove_one(struct pci_dev *pdev)
8212{
8213 struct net_device *dev = pci_get_drvdata(pdev);
8214 struct bnxt *bp = netdev_priv(dev);
8215
4ab0c6a8 8216 if (BNXT_PF(bp)) {
c0c050c5 8217 bnxt_sriov_disable(bp);
4ab0c6a8
SP		 8218 bnxt_dl_unregister(bp);
8219 }
c0c050c5 8220
6316ea6d 8221 pci_disable_pcie_error_reporting(pdev);
c0c050c5 8222 unregister_netdev(dev);
2ae7408f 8223 bnxt_shutdown_tc(bp);
c213eae8 8224 bnxt_cancel_sp_work(bp);
c0c050c5
MC		 8225 bp->sp_event = 0;
8226
7809592d 8227 bnxt_clear_int_mode(bp);
be58a0da 8228 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5 8229 bnxt_free_hwrm_resources(bp);
e605db80 8230 bnxt_free_hwrm_short_cmd_req(bp);
eb513658 8231 bnxt_ethtool_free(bp);
7df4ae9f 8232 bnxt_dcb_free(bp);
a588e458
MC		 8233 kfree(bp->edev);
8234 bp->edev = NULL;
17086399 8235 bnxt_cleanup_pci(bp);
c0c050c5 8236 free_netdev(dev);
c0c050c5
MC		 8237}
8238
8239static int bnxt_probe_phy(struct bnxt *bp)
8240{
8241 int rc = 0;
8242 struct bnxt_link_info *link_info = &bp->link_info;
c0c050c5 8243
170ce013
MC		 8244 rc = bnxt_hwrm_phy_qcaps(bp);
8245 if (rc) {
8246 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
8247 rc);
8248 return rc;
8249 }
e2dc9b6e 8250 mutex_init(&bp->link_lock);
170ce013 8251
c0c050c5
MC		 8252 rc = bnxt_update_link(bp, false);
8253 if (rc) {
8254 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
8255 rc);
8256 return rc;
8257 }
8258
93ed8117
MC		 8259 /* Older firmware does not have supported_auto_speeds, so assume
8260 * that all supported speeds can be autonegotiated.
8261 */
8262 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
8263 link_info->support_auto_speeds = link_info->support_speeds;
8264
c0c050c5 8265 /*initialize the ethool setting copy with NVM settings */
0d8abf02 8266 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
c9ee9516
MC		 8267 link_info->autoneg = BNXT_AUTONEG_SPEED;
8268 if (bp->hwrm_spec_code >= 0x10201) {
8269 if (link_info->auto_pause_setting &
8270 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
8271 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8272 } else {
8273 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8274 }
0d8abf02 8275 link_info->advertising = link_info->auto_link_speeds;
0d8abf02
MC		 8276 } else {
8277 link_info->req_link_speed = link_info->force_link_speed;
8278 link_info->req_duplex = link_info->duplex_setting;
c0c050c5 8279 }
c9ee9516
MC		 8280 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
8281 link_info->req_flow_ctrl =
8282 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
8283 else
8284 link_info->req_flow_ctrl = link_info->force_pause_setting;
c0c050c5
MC		 8285 return rc;
8286}
8287
8288static int bnxt_get_max_irq(struct pci_dev *pdev)
8289{
8290 u16 ctrl;
8291
8292 if (!pdev->msix_cap)
8293 return 1;
8294
8295 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
8296 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
8297}
8298
6e6c5a57
MC		 8299static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8300 int *max_cp)
c0c050c5 8301{
6a4f2947 8302 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6e6c5a57 8303 int max_ring_grps = 0;
c0c050c5 8304
6a4f2947
MC		 8305 *max_tx = hw_resc->max_tx_rings;
8306 *max_rx = hw_resc->max_rx_rings;
8307 *max_cp = min_t(int, hw_resc->max_irqs, hw_resc->max_cp_rings);
8308 *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs);
8309 max_ring_grps = hw_resc->max_hw_ring_grps;
76595193
PS		 8310 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
8311 *max_cp -= 1;
8312 *max_rx -= 2;
8313 }
c0c050c5
MC		 8314 if (bp->flags & BNXT_FLAG_AGG_RINGS)
8315 *max_rx >>= 1;
b72d4a68 8316 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 8317}
8318
8319int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
8320{
8321 int rx, tx, cp;
8322
8323 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
8324 if (!rx || !tx || !cp)
8325 return -ENOMEM;
8326
8327 *max_rx = rx;
8328 *max_tx = tx;
8329 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
8330}
8331
e4060d30
MC		 8332static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8333 bool shared)
8334{
8335 int rc;
8336
8337 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
bdbd1eb5
MC		 8338 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
8339 /* Not enough rings, try disabling agg rings. */
8340 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
8341 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8342 if (rc)
8343 return rc;
8344 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
1054aee8
MC		 8345 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8346 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
bdbd1eb5
MC		 8347 bnxt_set_ring_params(bp);
8348 }
e4060d30
MC		 8349
8350 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
8351 int max_cp, max_stat, max_irq;
8352
8353 /* Reserve minimum resources for RoCE */
8354 max_cp = bnxt_get_max_func_cp_rings(bp);
8355 max_stat = bnxt_get_max_func_stat_ctxs(bp);
8356 max_irq = bnxt_get_max_func_irqs(bp);
8357 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
8358 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
8359 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
8360 return 0;
8361
8362 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
8363 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
8364 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
8365 max_cp = min_t(int, max_cp, max_irq);
8366 max_cp = min_t(int, max_cp, max_stat);
8367 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
8368 if (rc)
8369 rc = 0;
8370 }
8371 return rc;
8372}
8373
58ea801a
MC		 8374/* In initial default shared ring setting, each shared ring must have a
8375 * RX/TX ring pair.
8376 */
8377static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
8378{
8379 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
8380 bp->rx_nr_rings = bp->cp_nr_rings;
8381 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
8382 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8383}
8384
702c221c 8385static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
6e6c5a57
MC		 8386{
8387 int dflt_rings, max_rx_rings, max_tx_rings, rc;
6e6c5a57
MC		 8388
8389 if (sh)
8390 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8391 dflt_rings = netif_get_num_default_rss_queues();
d5430d31
MC		 8392 /* Reduce default rings to reduce memory usage on multi-port cards */
8393 if (bp->port_count > 1)
8394 dflt_rings = min_t(int, dflt_rings, 4);
e4060d30 8395 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57
MC		 8396 if (rc)
8397 return rc;
8398 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
8399 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
58ea801a
MC		 8400 if (sh)
8401 bnxt_trim_dflt_sh_rings(bp);
8402 else
8403 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
8404 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
391be5c2 8405
674f50a5 8406 rc = __bnxt_reserve_rings(bp);
391be5c2
MC		 8407 if (rc)
8408 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
58ea801a
MC		 8409 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8410 if (sh)
8411 bnxt_trim_dflt_sh_rings(bp);
391be5c2 8412
674f50a5
MC		 8413 /* Rings may have been trimmed, re-reserve the trimmed rings. */
8414 if (bnxt_need_reserve_rings(bp)) {
8415 rc = __bnxt_reserve_rings(bp);
8416 if (rc)
8417 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
8418 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8419 }
6e6c5a57 8420 bp->num_stat_ctxs = bp->cp_nr_rings;
76595193
PS		 8421 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8422 bp->rx_nr_rings++;
8423 bp->cp_nr_rings++;
8424 }
6e6c5a57 8425 return rc;
c0c050c5
MC		 8426}
8427
80fcaf46 8428int bnxt_restore_pf_fw_resources(struct bnxt *bp)
7b08f661 8429{
80fcaf46
MC		 8430 int rc;
8431
7b08f661 8432 ASSERT_RTNL();
80fcaf46
MC		 8433 if (bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
8434 return 0;
8435
7b08f661 8436 bnxt_hwrm_func_qcaps(bp);
80fcaf46
MC		 8437 __bnxt_close_nic(bp, true, false);
8438 bnxt_clear_int_mode(bp);
8439 rc = bnxt_init_int_mode(bp);
8440 if (rc)
8441 dev_close(bp->dev);
8442 else
8443 rc = bnxt_open_nic(bp, true, false);
8444 return rc;
7b08f661
MC		 8445}
8446
a22a6ac2
MC		 8447static int bnxt_init_mac_addr(struct bnxt *bp)
8448{
8449 int rc = 0;
8450
8451 if (BNXT_PF(bp)) {
8452 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
8453 } else {
8454#ifdef CONFIG_BNXT_SRIOV
8455 struct bnxt_vf_info *vf = &bp->vf;
8456
8457 if (is_valid_ether_addr(vf->mac_addr)) {
91cdda40 8458 /* overwrite netdev dev_addr with admin VF MAC */
a22a6ac2
MC		 8459 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8460 } else {
8461 eth_hw_addr_random(bp->dev);
8462 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
8463 }
8464#endif
8465 }
8466 return rc;
8467}
8468
90c4f788
AK		 8469static void bnxt_parse_log_pcie_link(struct bnxt *bp)
8470{
8471 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
8472 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
8473
7ab0760f 8474 if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) ||
90c4f788
AK		 8475 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
8476 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
8477 else
8478 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
8479 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
8480 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
8481 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
8482 "Unknown", width);
8483}
8484
c0c050c5
MC		 8485static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8486{
8487 static int version_printed;
8488 struct net_device *dev;
8489 struct bnxt *bp;
6e6c5a57 8490 int rc, max_irqs;
c0c050c5 8491
4e00338a 8492 if (pci_is_bridge(pdev))
fa853dda
PS		 8493 return -ENODEV;
8494
c0c050c5
MC		 8495 if (version_printed++ == 0)
8496 pr_info("%s", version);
8497
8498 max_irqs = bnxt_get_max_irq(pdev);
8499 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8500 if (!dev)
8501 return -ENOMEM;
8502
8503 bp = netdev_priv(dev);
8504
8505 if (bnxt_vf_pciid(ent->driver_data))
8506 bp->flags |= BNXT_FLAG_VF;
8507
2bcfa6f6 8508 if (pdev->msix_cap)
c0c050c5 8509 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 8510
8511 rc = bnxt_init_board(pdev, dev);
8512 if (rc < 0)
8513 goto init_err_free;
8514
8515 dev->netdev_ops = &bnxt_netdev_ops;
8516 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8517 dev->ethtool_ops = &bnxt_ethtool_ops;
bc88055a 8518 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
c0c050c5
MC		 8519 pci_set_drvdata(pdev, dev);
8520
3e8060fa
PS		 8521 rc = bnxt_alloc_hwrm_resources(bp);
8522 if (rc)
17086399 8523 goto init_err_pci_clean;
3e8060fa
PS		 8524
8525 mutex_init(&bp->hwrm_cmd_lock);
8526 rc = bnxt_hwrm_ver_get(bp);
8527 if (rc)
17086399 8528 goto init_err_pci_clean;
3e8060fa 8529
e605db80
DK		 8530 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
8531 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8532 if (rc)
8533 goto init_err_pci_clean;
8534 }
8535
3c2217a6
MC		 8536 rc = bnxt_hwrm_func_reset(bp);
8537 if (rc)
8538 goto init_err_pci_clean;
8539
5ac67d8b
RS		 8540 bnxt_hwrm_fw_set_time(bp);
8541
c0c050c5
MC		 8542 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8543 NETIF_F_TSO | NETIF_F_TSO6 |
8544 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7e13318d 8545 NETIF_F_GSO_IPXIP4 |
152971ee
AD		 8546 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8547 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
3e8060fa
PS		 8548 NETIF_F_RXCSUM | NETIF_F_GRO;
8549
8550 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8551 dev->hw_features |= NETIF_F_LRO;
c0c050c5 8552
c0c050c5
MC		 8553 dev->hw_enc_features =
8554 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8555 NETIF_F_TSO | NETIF_F_TSO6 |
8556 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
152971ee 8557 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7e13318d 8558 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
152971ee
AD		 8559 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
8560 NETIF_F_GSO_GRE_CSUM;
c0c050c5
MC		 8561 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
8562 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
8563 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
1054aee8
MC		 8564 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8565 dev->hw_features |= NETIF_F_GRO_HW;
c0c050c5 8566 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
1054aee8
MC		 8567 if (dev->features & NETIF_F_GRO_HW)
8568 dev->features &= ~NETIF_F_LRO;
c0c050c5
MC		 8569 dev->priv_flags |= IFF_UNICAST_FLT;
8570
8571#ifdef CONFIG_BNXT_SRIOV
8572 init_waitqueue_head(&bp->sriov_cfg_wait);
4ab0c6a8 8573 mutex_init(&bp->sriov_lock);
c0c050c5 8574#endif
309369c9 8575 bp->gro_func = bnxt_gro_func_5730x;
3284f9e1 8576 if (BNXT_CHIP_P4_PLUS(bp))
94758f8d 8577 bp->gro_func = bnxt_gro_func_5731x;
434c975a
MC		 8578 else
8579 bp->flags |= BNXT_FLAG_DOUBLE_DB;
309369c9 8580
c0c050c5
MC		 8581 rc = bnxt_hwrm_func_drv_rgtr(bp);
8582 if (rc)
17086399 8583 goto init_err_pci_clean;
c0c050c5 8584
a1653b13
MC		 8585 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
8586 if (rc)
17086399 8587 goto init_err_pci_clean;
a1653b13 8588
a588e458
MC		 8589 bp->ulp_probe = bnxt_ulp_probe;
8590
c0c050c5
MC		 8591 /* Get the MAX capabilities for this function */
8592 rc = bnxt_hwrm_func_qcaps(bp);
8593 if (rc) {
8594 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
8595 rc);
8596 rc = -1;
17086399 8597 goto init_err_pci_clean;
c0c050c5 8598 }
a22a6ac2
MC		 8599 rc = bnxt_init_mac_addr(bp);
8600 if (rc) {
8601 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
8602 rc = -EADDRNOTAVAIL;
8603 goto init_err_pci_clean;
8604 }
c0c050c5
MC		 8605 rc = bnxt_hwrm_queue_qportcfg(bp);
8606 if (rc) {
8607 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
8608 rc);
8609 rc = -1;
17086399 8610 goto init_err_pci_clean;
c0c050c5
MC		 8611 }
8612
567b2abe 8613 bnxt_hwrm_func_qcfg(bp);
5ad2cbee 8614 bnxt_hwrm_port_led_qcaps(bp);
eb513658 8615 bnxt_ethtool_init(bp);
87fe6032 8616 bnxt_dcb_init(bp);
567b2abe 8617
7eb9bb3a
MC		 8618 /* MTU range: 60 - FW defined max */
8619 dev->min_mtu = ETH_ZLEN;
8620 dev->max_mtu = bp->max_mtu;
8621
d5430d31
MC		 8622 rc = bnxt_probe_phy(bp);
8623 if (rc)
8624 goto init_err_pci_clean;
8625
c61fb99c 8626 bnxt_set_rx_skb_mode(bp, false);
c0c050c5
MC		 8627 bnxt_set_tpa_flags(bp);
8628 bnxt_set_ring_params(bp);
33c2657e 8629 bnxt_set_max_func_irqs(bp, max_irqs);
702c221c 8630 rc = bnxt_set_dflt_rings(bp, true);
bdbd1eb5
MC		 8631 if (rc) {
8632 netdev_err(bp->dev, "Not enough rings available.\n");
8633 rc = -ENOMEM;
17086399 8634 goto init_err_pci_clean;
bdbd1eb5 8635 }
c0c050c5 8636
87da7f79
MC		 8637 /* Default RSS hash cfg. */
8638 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
8639 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
8640 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
8641 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
3284f9e1 8642 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
87da7f79
MC		 8643 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
8644 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
8645 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
8646 }
8647
8fdefd63 8648 bnxt_hwrm_vnic_qcaps(bp);
8079e8f1 8649 if (bnxt_rfs_supported(bp)) {
2bcfa6f6
MC		 8650 dev->hw_features |= NETIF_F_NTUPLE;
8651 if (bnxt_rfs_capable(bp)) {
8652 bp->flags |= BNXT_FLAG_RFS;
8653 dev->features |= NETIF_F_NTUPLE;
8654 }
8655 }
8656
c0c050c5
MC		 8657 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
8658 bp->flags |= BNXT_FLAG_STRIP_VLAN;
8659
7809592d 8660 rc = bnxt_init_int_mode(bp);
c0c050c5 8661 if (rc)
17086399 8662 goto init_err_pci_clean;
c0c050c5 8663
c1ef146a 8664 bnxt_get_wol_settings(bp);
d196ece7
MC		 8665 if (bp->flags & BNXT_FLAG_WOL_CAP)
8666 device_set_wakeup_enable(&pdev->dev, bp->wol);
8667 else
8668 device_set_wakeup_capable(&pdev->dev, false);
c1ef146a 8669
c3480a60
MC		 8670 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
8671
c213eae8
MC		 8672 if (BNXT_PF(bp)) {
8673 if (!bnxt_pf_wq) {
8674 bnxt_pf_wq =
8675 create_singlethread_workqueue("bnxt_pf_wq");
8676 if (!bnxt_pf_wq) {
8677 dev_err(&pdev->dev, "Unable to create workqueue.\n");
8678 goto init_err_pci_clean;
8679 }
8680 }
2ae7408f 8681 bnxt_init_tc(bp);
c213eae8 8682 }
2ae7408f 8683
7809592d
MC		 8684 rc = register_netdev(dev);
8685 if (rc)
2ae7408f 8686 goto init_err_cleanup_tc;
7809592d 8687
4ab0c6a8
SP		 8688 if (BNXT_PF(bp))
8689 bnxt_dl_register(bp);
8690
c0c050c5
MC		 8691 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
8692 board_info[ent->driver_data].name,
8693 (long)pci_resource_start(pdev, 0), dev->dev_addr);
8694
90c4f788
AK		 8695 bnxt_parse_log_pcie_link(bp);
8696
c0c050c5
MC		 8697 return 0;
8698
2ae7408f
SP		 8699init_err_cleanup_tc:
8700 bnxt_shutdown_tc(bp);
7809592d
MC		 8701 bnxt_clear_int_mode(bp);
8702
17086399
SP		 8703init_err_pci_clean:
8704 bnxt_cleanup_pci(bp);
c0c050c5
MC		 8705
8706init_err_free:
8707 free_netdev(dev);
8708 return rc;
8709}
8710
d196ece7
MC		 8711static void bnxt_shutdown(struct pci_dev *pdev)
8712{
8713 struct net_device *dev = pci_get_drvdata(pdev);
8714 struct bnxt *bp;
8715
8716 if (!dev)
8717 return;
8718
8719 rtnl_lock();
8720 bp = netdev_priv(dev);
8721 if (!bp)
8722 goto shutdown_exit;
8723
8724 if (netif_running(dev))
8725 dev_close(dev);
8726
a7f3f939
RJ		 8727 bnxt_ulp_shutdown(bp);
8728
d196ece7
MC		 8729 if (system_state == SYSTEM_POWER_OFF) {
8730 bnxt_clear_int_mode(bp);
8731 pci_wake_from_d3(pdev, bp->wol);
8732 pci_set_power_state(pdev, PCI_D3hot);
8733 }
8734
8735shutdown_exit:
8736 rtnl_unlock();
8737}
8738
f65a2044
MC		 8739#ifdef CONFIG_PM_SLEEP
8740static int bnxt_suspend(struct device *device)
8741{
8742 struct pci_dev *pdev = to_pci_dev(device);
8743 struct net_device *dev = pci_get_drvdata(pdev);
8744 struct bnxt *bp = netdev_priv(dev);
8745 int rc = 0;
8746
8747 rtnl_lock();
8748 if (netif_running(dev)) {
8749 netif_device_detach(dev);
8750 rc = bnxt_close(dev);
8751 }
8752 bnxt_hwrm_func_drv_unrgtr(bp);
8753 rtnl_unlock();
8754 return rc;
8755}
8756
8757static int bnxt_resume(struct device *device)
8758{
8759 struct pci_dev *pdev = to_pci_dev(device);
8760 struct net_device *dev = pci_get_drvdata(pdev);
8761 struct bnxt *bp = netdev_priv(dev);
8762 int rc = 0;
8763
8764 rtnl_lock();
8765 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
8766 rc = -ENODEV;
8767 goto resume_exit;
8768 }
8769 rc = bnxt_hwrm_func_reset(bp);
8770 if (rc) {
8771 rc = -EBUSY;
8772 goto resume_exit;
8773 }
8774 bnxt_get_wol_settings(bp);
8775 if (netif_running(dev)) {
8776 rc = bnxt_open(dev);
8777 if (!rc)
8778 netif_device_attach(dev);
8779 }
8780
8781resume_exit:
8782 rtnl_unlock();
8783 return rc;
8784}
8785
8786static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
8787#define BNXT_PM_OPS (&bnxt_pm_ops)
8788
8789#else
8790
8791#define BNXT_PM_OPS NULL
8792
8793#endif /* CONFIG_PM_SLEEP */
8794
6316ea6d
SB		 8795/**
8796 * bnxt_io_error_detected - called when PCI error is detected
8797 * @pdev: Pointer to PCI device
8798 * @state: The current pci connection state
8799 *
8800 * This function is called after a PCI bus error affecting
8801 * this device has been detected.
8802 */
8803static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
8804 pci_channel_state_t state)
8805{
8806 struct net_device *netdev = pci_get_drvdata(pdev);
a588e458 8807 struct bnxt *bp = netdev_priv(netdev);
6316ea6d
SB		 8808
8809 netdev_info(netdev, "PCI I/O error detected\n");
8810
8811 rtnl_lock();
8812 netif_device_detach(netdev);
8813
a588e458
MC		 8814 bnxt_ulp_stop(bp);
8815
6316ea6d
SB		 8816 if (state == pci_channel_io_perm_failure) {
8817 rtnl_unlock();
8818 return PCI_ERS_RESULT_DISCONNECT;
8819 }
8820
8821 if (netif_running(netdev))
8822 bnxt_close(netdev);
8823
8824 pci_disable_device(pdev);
8825 rtnl_unlock();
8826
8827 /* Request a slot slot reset. */
8828 return PCI_ERS_RESULT_NEED_RESET;
8829}
8830
8831/**
8832 * bnxt_io_slot_reset - called after the pci bus has been reset.
8833 * @pdev: Pointer to PCI device
8834 *
8835 * Restart the card from scratch, as if from a cold-boot.
8836 * At this point, the card has exprienced a hard reset,
8837 * followed by fixups by BIOS, and has its config space
8838 * set up identically to what it was at cold boot.
8839 */
8840static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
8841{
8842 struct net_device *netdev = pci_get_drvdata(pdev);
8843 struct bnxt *bp = netdev_priv(netdev);
8844 int err = 0;
8845 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8846
8847 netdev_info(bp->dev, "PCI Slot Reset\n");
8848
8849 rtnl_lock();
8850
8851 if (pci_enable_device(pdev)) {
8852 dev_err(&pdev->dev,
8853 "Cannot re-enable PCI device after reset.\n");
8854 } else {
8855 pci_set_master(pdev);
8856
aa8ed021
MC		 8857 err = bnxt_hwrm_func_reset(bp);
8858 if (!err && netif_running(netdev))
6316ea6d
SB		 8859 err = bnxt_open(netdev);
8860
a588e458 8861 if (!err) {
6316ea6d 8862 result = PCI_ERS_RESULT_RECOVERED;
a588e458
MC		 8863 bnxt_ulp_start(bp);
8864 }
6316ea6d
SB		 8865 }
8866
8867 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
8868 dev_close(netdev);
8869
8870 rtnl_unlock();
8871
8872 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8873 if (err) {
8874 dev_err(&pdev->dev,
8875 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8876 err); /* non-fatal, continue */
8877 }
8878
8879 return PCI_ERS_RESULT_RECOVERED;
8880}
8881
8882/**
8883 * bnxt_io_resume - called when traffic can start flowing again.
8884 * @pdev: Pointer to PCI device
8885 *
8886 * This callback is called when the error recovery driver tells
8887 * us that its OK to resume normal operation.
8888 */
8889static void bnxt_io_resume(struct pci_dev *pdev)
8890{
8891 struct net_device *netdev = pci_get_drvdata(pdev);
8892
8893 rtnl_lock();
8894
8895 netif_device_attach(netdev);
8896
8897 rtnl_unlock();
8898}
8899
8900static const struct pci_error_handlers bnxt_err_handler = {
8901 .error_detected = bnxt_io_error_detected,
8902 .slot_reset = bnxt_io_slot_reset,
8903 .resume = bnxt_io_resume
8904};
8905
c0c050c5
MC		 8906static struct pci_driver bnxt_pci_driver = {
8907 .name = DRV_MODULE_NAME,
8908 .id_table = bnxt_pci_tbl,
8909 .probe = bnxt_init_one,
8910 .remove = bnxt_remove_one,
d196ece7 8911 .shutdown = bnxt_shutdown,
f65a2044 8912 .driver.pm = BNXT_PM_OPS,
6316ea6d 8913 .err_handler = &bnxt_err_handler,
c0c050c5
MC		 8914#if defined(CONFIG_BNXT_SRIOV)
8915 .sriov_configure = bnxt_sriov_configure,
8916#endif
8917};
8918
c213eae8
MC		 8919static int __init bnxt_init(void)
8920{
8921 return pci_register_driver(&bnxt_pci_driver);
8922}
8923
8924static void __exit bnxt_exit(void)
8925{
8926 pci_unregister_driver(&bnxt_pci_driver);
8927 if (bnxt_pf_wq)
8928 destroy_workqueue(bnxt_pf_wq);
8929}
8930
8931module_init(bnxt_init);
8932module_exit(bnxt_exit);
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