]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/ethernet/broadcom/bnxt/bnxt.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
bnxt_en: Reserve RDMA resources by default.
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
11f15ed3 3 * Copyright (c) 2014-2016 Broadcom Corporation
c0c050c5
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11
12#include <linux/stringify.h>
13#include <linux/kernel.h>
14#include <linux/timer.h>
15#include <linux/errno.h>
16#include <linux/ioport.h>
17#include <linux/slab.h>
18#include <linux/vmalloc.h>
19#include <linux/interrupt.h>
20#include <linux/pci.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/dma-mapping.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/delay.h>
29#include <asm/byteorder.h>
30#include <asm/page.h>
31#include <linux/time.h>
32#include <linux/mii.h>
33#include <linux/if.h>
34#include <linux/if_vlan.h>
5ac67d8b 35#include <linux/rtc.h>
c0c050c5
MC		 36#include <net/ip.h>
37#include <net/tcp.h>
38#include <net/udp.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
ad51b8e9 41#include <net/udp_tunnel.h>
c0c050c5
MC		 42#ifdef CONFIG_NET_RX_BUSY_POLL
43#include <net/busy_poll.h>
44#endif
45#include <linux/workqueue.h>
46#include <linux/prefetch.h>
47#include <linux/cache.h>
48#include <linux/log2.h>
49#include <linux/aer.h>
50#include <linux/bitmap.h>
51#include <linux/cpu_rmap.h>
52
53#include "bnxt_hsi.h"
54#include "bnxt.h"
55#include "bnxt_sriov.h"
56#include "bnxt_ethtool.h"
7df4ae9f 57#include "bnxt_dcb.h"
c0c050c5
MC		 58
59#define BNXT_TX_TIMEOUT (5 * HZ)
60
61static const char version[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63
64MODULE_LICENSE("GPL");
65MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66MODULE_VERSION(DRV_MODULE_VERSION);
67
68#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70#define BNXT_RX_COPY_THRESH 256
71
4419dbe6 72#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 73
74enum board_idx {
fbc9a523 75 BCM57301,
c0c050c5
MC		 76 BCM57302,
77 BCM57304,
1f681688 78 BCM57417_NPAR,
fa853dda 79 BCM58700,
b24eb6ae
MC		 80 BCM57311,
81 BCM57312,
fbc9a523 82 BCM57402,
c0c050c5
MC		 83 BCM57404,
84 BCM57406,
1f681688
MC		 85 BCM57402_NPAR,
86 BCM57407,
b24eb6ae
MC		 87 BCM57412,
88 BCM57414,
89 BCM57416,
90 BCM57417,
1f681688 91 BCM57412_NPAR,
5049e33b 92 BCM57314,
1f681688
MC		 93 BCM57417_SFP,
94 BCM57416_SFP,
95 BCM57404_NPAR,
96 BCM57406_NPAR,
97 BCM57407_SFP,
adbc8305 98 BCM57407_NPAR,
1f681688
MC		 99 BCM57414_NPAR,
100 BCM57416_NPAR,
adbc8305
MC		 101 NETXTREME_E_VF,
102 NETXTREME_C_VF,
c0c050c5
MC		 103};
104
105/* indexed by enum above */
106static const struct {
107 char *name;
108} board_info[] = {
adbc8305
MC		 109 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
110 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
111 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
1f681688 112 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 113 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
114 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
115 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
116 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
117 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
118 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
1f681688 119 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 120 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
121 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
122 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
123 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
124 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
1f681688 125 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 126 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
127 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
128 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
1f681688
MC		 129 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
130 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 131 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
132 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
1f681688
MC		 133 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
134 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 135 { "Broadcom NetXtreme-E Ethernet Virtual Function" },
136 { "Broadcom NetXtreme-C Ethernet Virtual Function" },
c0c050c5
MC		 137};
138
139static const struct pci_device_id bnxt_pci_tbl[] = {
adbc8305 140 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
fbc9a523 141 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 142 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
143 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
1f681688 144 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
fa853dda 145 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
b24eb6ae
MC		 146 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
147 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
fbc9a523 148 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 149 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
150 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
1f681688
MC		 151 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
152 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
b24eb6ae
MC		 153 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
154 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
155 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
156 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
1f681688 157 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
5049e33b 158 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
1f681688
MC		 159 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
160 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
161 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
162 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
163 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
adbc8305
MC		 164 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
165 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
1f681688 166 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
adbc8305 167 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
1f681688 168 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
adbc8305 169 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
c0c050c5 170#ifdef CONFIG_BNXT_SRIOV
adbc8305
MC		 171 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
172 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
173 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
174 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
175 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
176 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
c0c050c5
MC		 177#endif
178 { 0 }
179};
180
181MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
182
183static const u16 bnxt_vf_req_snif[] = {
184 HWRM_FUNC_CFG,
185 HWRM_PORT_PHY_QCFG,
186 HWRM_CFA_L2_FILTER_ALLOC,
187};
188
25be8623 189static const u16 bnxt_async_events_arr[] = {
87c374de
MC		 190 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
191 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
192 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
193 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
194 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
25be8623
MC		 195};
196
c0c050c5
MC		 197static bool bnxt_vf_pciid(enum board_idx idx)
198{
adbc8305 199 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
c0c050c5
MC		 200}
201
202#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
203#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
204#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
205
206#define BNXT_CP_DB_REARM(db, raw_cons) \
207 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
208
209#define BNXT_CP_DB(db, raw_cons) \
210 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
211
212#define BNXT_CP_DB_IRQ_DIS(db) \
213 writel(DB_CP_IRQ_DIS_FLAGS, db)
214
215static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
216{
217 /* Tell compiler to fetch tx indices from memory. */
218 barrier();
219
220 return bp->tx_ring_size -
221 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
222}
223
224static const u16 bnxt_lhint_arr[] = {
225 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
226 TX_BD_FLAGS_LHINT_512_TO_1023,
227 TX_BD_FLAGS_LHINT_1024_TO_2047,
228 TX_BD_FLAGS_LHINT_1024_TO_2047,
229 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
230 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
231 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
232 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
233 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
234 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
235 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
236 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
237 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
238 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
239 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
240 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
241 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
242 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
243 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
244};
245
246static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
247{
248 struct bnxt *bp = netdev_priv(dev);
249 struct tx_bd *txbd;
250 struct tx_bd_ext *txbd1;
251 struct netdev_queue *txq;
252 int i;
253 dma_addr_t mapping;
254 unsigned int length, pad = 0;
255 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
256 u16 prod, last_frag;
257 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 258 struct bnxt_tx_ring_info *txr;
259 struct bnxt_sw_tx_bd *tx_buf;
260
261 i = skb_get_queue_mapping(skb);
262 if (unlikely(i >= bp->tx_nr_rings)) {
263 dev_kfree_skb_any(skb);
264 return NETDEV_TX_OK;
265 }
266
b6ab4b01 267 txr = &bp->tx_ring[i];
c0c050c5
MC		 268 txq = netdev_get_tx_queue(dev, i);
269 prod = txr->tx_prod;
270
271 free_size = bnxt_tx_avail(bp, txr);
272 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
273 netif_tx_stop_queue(txq);
274 return NETDEV_TX_BUSY;
275 }
276
277 length = skb->len;
278 len = skb_headlen(skb);
279 last_frag = skb_shinfo(skb)->nr_frags;
280
281 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
282
283 txbd->tx_bd_opaque = prod;
284
285 tx_buf = &txr->tx_buf_ring[prod];
286 tx_buf->skb = skb;
287 tx_buf->nr_frags = last_frag;
288
289 vlan_tag_flags = 0;
290 cfa_action = 0;
291 if (skb_vlan_tag_present(skb)) {
292 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
293 skb_vlan_tag_get(skb);
294 /* Currently supports 8021Q, 8021AD vlan offloads
295 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
296 */
297 if (skb->vlan_proto == htons(ETH_P_8021Q))
298 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
299 }
300
301 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 302 struct tx_push_buffer *tx_push_buf = txr->tx_push;
303 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
304 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
305 void *pdata = tx_push_buf->data;
306 u64 *end;
307 int j, push_len;
c0c050c5
MC		 308
309 /* Set COAL_NOW to be ready quickly for the next push */
310 tx_push->tx_bd_len_flags_type =
311 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
312 TX_BD_TYPE_LONG_TX_BD |
313 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
314 TX_BD_FLAGS_COAL_NOW |
315 TX_BD_FLAGS_PACKET_END |
316 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
317
318 if (skb->ip_summed == CHECKSUM_PARTIAL)
319 tx_push1->tx_bd_hsize_lflags =
320 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
321 else
322 tx_push1->tx_bd_hsize_lflags = 0;
323
324 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
325 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
326
fbb0fa8b
MC		 327 end = pdata + length;
328 end = PTR_ALIGN(end, 8) - 1;
4419dbe6
MC		 329 *end = 0;
330
c0c050c5
MC		 331 skb_copy_from_linear_data(skb, pdata, len);
332 pdata += len;
333 for (j = 0; j < last_frag; j++) {
334 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
335 void *fptr;
336
337 fptr = skb_frag_address_safe(frag);
338 if (!fptr)
339 goto normal_tx;
340
341 memcpy(pdata, fptr, skb_frag_size(frag));
342 pdata += skb_frag_size(frag);
343 }
344
4419dbe6
MC		 345 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
346 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 347 prod = NEXT_TX(prod);
348 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
349 memcpy(txbd, tx_push1, sizeof(*txbd));
350 prod = NEXT_TX(prod);
4419dbe6 351 tx_push->doorbell =
c0c050c5
MC		 352 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
353 txr->tx_prod = prod;
354
b9a8460a 355 tx_buf->is_push = 1;
c0c050c5 356 netdev_tx_sent_queue(txq, skb->len);
b9a8460a 357 wmb(); /* Sync is_push and byte queue before pushing data */
c0c050c5 358
4419dbe6
MC		 359 push_len = (length + sizeof(*tx_push) + 7) / 8;
360 if (push_len > 16) {
361 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
9d13744b
MC		 362 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
363 (push_len - 16) << 1);
4419dbe6
MC		 364 } else {
365 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
366 push_len);
367 }
c0c050c5 368
c0c050c5
MC		 369 goto tx_done;
370 }
371
372normal_tx:
373 if (length < BNXT_MIN_PKT_SIZE) {
374 pad = BNXT_MIN_PKT_SIZE - length;
375 if (skb_pad(skb, pad)) {
376 /* SKB already freed. */
377 tx_buf->skb = NULL;
378 return NETDEV_TX_OK;
379 }
380 length = BNXT_MIN_PKT_SIZE;
381 }
382
383 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
384
385 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
386 dev_kfree_skb_any(skb);
387 tx_buf->skb = NULL;
388 return NETDEV_TX_OK;
389 }
390
391 dma_unmap_addr_set(tx_buf, mapping, mapping);
392 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
393 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
394
395 txbd->tx_bd_haddr = cpu_to_le64(mapping);
396
397 prod = NEXT_TX(prod);
398 txbd1 = (struct tx_bd_ext *)
399 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
400
401 txbd1->tx_bd_hsize_lflags = 0;
402 if (skb_is_gso(skb)) {
403 u32 hdr_len;
404
405 if (skb->encapsulation)
406 hdr_len = skb_inner_network_offset(skb) +
407 skb_inner_network_header_len(skb) +
408 inner_tcp_hdrlen(skb);
409 else
410 hdr_len = skb_transport_offset(skb) +
411 tcp_hdrlen(skb);
412
413 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
414 TX_BD_FLAGS_T_IPID |
415 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
416 length = skb_shinfo(skb)->gso_size;
417 txbd1->tx_bd_mss = cpu_to_le32(length);
418 length += hdr_len;
419 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
420 txbd1->tx_bd_hsize_lflags =
421 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
422 txbd1->tx_bd_mss = 0;
423 }
424
425 length >>= 9;
426 flags |= bnxt_lhint_arr[length];
427 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
428
429 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
430 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
431 for (i = 0; i < last_frag; i++) {
432 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
433
434 prod = NEXT_TX(prod);
435 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
436
437 len = skb_frag_size(frag);
438 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
439 DMA_TO_DEVICE);
440
441 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
442 goto tx_dma_error;
443
444 tx_buf = &txr->tx_buf_ring[prod];
445 dma_unmap_addr_set(tx_buf, mapping, mapping);
446
447 txbd->tx_bd_haddr = cpu_to_le64(mapping);
448
449 flags = len << TX_BD_LEN_SHIFT;
450 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
451 }
452
453 flags &= ~TX_BD_LEN;
454 txbd->tx_bd_len_flags_type =
455 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
456 TX_BD_FLAGS_PACKET_END);
457
458 netdev_tx_sent_queue(txq, skb->len);
459
460 /* Sync BD data before updating doorbell */
461 wmb();
462
463 prod = NEXT_TX(prod);
464 txr->tx_prod = prod;
465
466 writel(DB_KEY_TX | prod, txr->tx_doorbell);
467 writel(DB_KEY_TX | prod, txr->tx_doorbell);
468
469tx_done:
470
471 mmiowb();
472
473 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
474 netif_tx_stop_queue(txq);
475
476 /* netif_tx_stop_queue() must be done before checking
477 * tx index in bnxt_tx_avail() below, because in
478 * bnxt_tx_int(), we update tx index before checking for
479 * netif_tx_queue_stopped().
480 */
481 smp_mb();
482 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
483 netif_tx_wake_queue(txq);
484 }
485 return NETDEV_TX_OK;
486
487tx_dma_error:
488 last_frag = i;
489
490 /* start back at beginning and unmap skb */
491 prod = txr->tx_prod;
492 tx_buf = &txr->tx_buf_ring[prod];
493 tx_buf->skb = NULL;
494 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
495 skb_headlen(skb), PCI_DMA_TODEVICE);
496 prod = NEXT_TX(prod);
497
498 /* unmap remaining mapped pages */
499 for (i = 0; i < last_frag; i++) {
500 prod = NEXT_TX(prod);
501 tx_buf = &txr->tx_buf_ring[prod];
502 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
503 skb_frag_size(&skb_shinfo(skb)->frags[i]),
504 PCI_DMA_TODEVICE);
505 }
506
507 dev_kfree_skb_any(skb);
508 return NETDEV_TX_OK;
509}
510
511static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
512{
b6ab4b01 513 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
b81a90d3 514 int index = txr - &bp->tx_ring[0];
c0c050c5
MC		 515 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
516 u16 cons = txr->tx_cons;
517 struct pci_dev *pdev = bp->pdev;
518 int i;
519 unsigned int tx_bytes = 0;
520
521 for (i = 0; i < nr_pkts; i++) {
522 struct bnxt_sw_tx_bd *tx_buf;
523 struct sk_buff *skb;
524 int j, last;
525
526 tx_buf = &txr->tx_buf_ring[cons];
527 cons = NEXT_TX(cons);
528 skb = tx_buf->skb;
529 tx_buf->skb = NULL;
530
531 if (tx_buf->is_push) {
532 tx_buf->is_push = 0;
533 goto next_tx_int;
534 }
535
536 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
537 skb_headlen(skb), PCI_DMA_TODEVICE);
538 last = tx_buf->nr_frags;
539
540 for (j = 0; j < last; j++) {
541 cons = NEXT_TX(cons);
542 tx_buf = &txr->tx_buf_ring[cons];
543 dma_unmap_page(
544 &pdev->dev,
545 dma_unmap_addr(tx_buf, mapping),
546 skb_frag_size(&skb_shinfo(skb)->frags[j]),
547 PCI_DMA_TODEVICE);
548 }
549
550next_tx_int:
551 cons = NEXT_TX(cons);
552
553 tx_bytes += skb->len;
554 dev_kfree_skb_any(skb);
555 }
556
557 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
558 txr->tx_cons = cons;
559
560 /* Need to make the tx_cons update visible to bnxt_start_xmit()
561 * before checking for netif_tx_queue_stopped(). Without the
562 * memory barrier, there is a small possibility that bnxt_start_xmit()
563 * will miss it and cause the queue to be stopped forever.
564 */
565 smp_mb();
566
567 if (unlikely(netif_tx_queue_stopped(txq)) &&
568 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
569 __netif_tx_lock(txq, smp_processor_id());
570 if (netif_tx_queue_stopped(txq) &&
571 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
572 txr->dev_state != BNXT_DEV_STATE_CLOSING)
573 netif_tx_wake_queue(txq);
574 __netif_tx_unlock(txq);
575 }
576}
577
578static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
579 gfp_t gfp)
580{
581 u8 *data;
582 struct pci_dev *pdev = bp->pdev;
583
584 data = kmalloc(bp->rx_buf_size, gfp);
585 if (!data)
586 return NULL;
587
588 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
589 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
590
591 if (dma_mapping_error(&pdev->dev, *mapping)) {
592 kfree(data);
593 data = NULL;
594 }
595 return data;
596}
597
598static inline int bnxt_alloc_rx_data(struct bnxt *bp,
599 struct bnxt_rx_ring_info *rxr,
600 u16 prod, gfp_t gfp)
601{
602 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
603 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
604 u8 *data;
605 dma_addr_t mapping;
606
607 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
608 if (!data)
609 return -ENOMEM;
610
611 rx_buf->data = data;
612 dma_unmap_addr_set(rx_buf, mapping, mapping);
613
614 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
615
616 return 0;
617}
618
619static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
620 u8 *data)
621{
622 u16 prod = rxr->rx_prod;
623 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
624 struct rx_bd *cons_bd, *prod_bd;
625
626 prod_rx_buf = &rxr->rx_buf_ring[prod];
627 cons_rx_buf = &rxr->rx_buf_ring[cons];
628
629 prod_rx_buf->data = data;
630
631 dma_unmap_addr_set(prod_rx_buf, mapping,
632 dma_unmap_addr(cons_rx_buf, mapping));
633
634 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
635 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
636
637 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
638}
639
640static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
641{
642 u16 next, max = rxr->rx_agg_bmap_size;
643
644 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
645 if (next >= max)
646 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
647 return next;
648}
649
650static inline int bnxt_alloc_rx_page(struct bnxt *bp,
651 struct bnxt_rx_ring_info *rxr,
652 u16 prod, gfp_t gfp)
653{
654 struct rx_bd *rxbd =
655 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
656 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
657 struct pci_dev *pdev = bp->pdev;
658 struct page *page;
659 dma_addr_t mapping;
660 u16 sw_prod = rxr->rx_sw_agg_prod;
89d0a06c 661 unsigned int offset = 0;
c0c050c5 662
89d0a06c
MC		 663 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
664 page = rxr->rx_page;
665 if (!page) {
666 page = alloc_page(gfp);
667 if (!page)
668 return -ENOMEM;
669 rxr->rx_page = page;
670 rxr->rx_page_offset = 0;
671 }
672 offset = rxr->rx_page_offset;
673 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
674 if (rxr->rx_page_offset == PAGE_SIZE)
675 rxr->rx_page = NULL;
676 else
677 get_page(page);
678 } else {
679 page = alloc_page(gfp);
680 if (!page)
681 return -ENOMEM;
682 }
c0c050c5 683
89d0a06c 684 mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
c0c050c5
MC		 685 PCI_DMA_FROMDEVICE);
686 if (dma_mapping_error(&pdev->dev, mapping)) {
687 __free_page(page);
688 return -EIO;
689 }
690
691 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
692 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
693
694 __set_bit(sw_prod, rxr->rx_agg_bmap);
695 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
696 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
697
698 rx_agg_buf->page = page;
89d0a06c 699 rx_agg_buf->offset = offset;
c0c050c5
MC		 700 rx_agg_buf->mapping = mapping;
701 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
702 rxbd->rx_bd_opaque = sw_prod;
703 return 0;
704}
705
706static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
707 u32 agg_bufs)
708{
709 struct bnxt *bp = bnapi->bp;
710 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 711 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 712 u16 prod = rxr->rx_agg_prod;
713 u16 sw_prod = rxr->rx_sw_agg_prod;
714 u32 i;
715
716 for (i = 0; i < agg_bufs; i++) {
717 u16 cons;
718 struct rx_agg_cmp *agg;
719 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
720 struct rx_bd *prod_bd;
721 struct page *page;
722
723 agg = (struct rx_agg_cmp *)
724 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
725 cons = agg->rx_agg_cmp_opaque;
726 __clear_bit(cons, rxr->rx_agg_bmap);
727
728 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
729 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
730
731 __set_bit(sw_prod, rxr->rx_agg_bmap);
732 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
733 cons_rx_buf = &rxr->rx_agg_ring[cons];
734
735 /* It is possible for sw_prod to be equal to cons, so
736 * set cons_rx_buf->page to NULL first.
737 */
738 page = cons_rx_buf->page;
739 cons_rx_buf->page = NULL;
740 prod_rx_buf->page = page;
89d0a06c 741 prod_rx_buf->offset = cons_rx_buf->offset;
c0c050c5
MC		 742
743 prod_rx_buf->mapping = cons_rx_buf->mapping;
744
745 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
746
747 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
748 prod_bd->rx_bd_opaque = sw_prod;
749
750 prod = NEXT_RX_AGG(prod);
751 sw_prod = NEXT_RX_AGG(sw_prod);
752 cp_cons = NEXT_CMP(cp_cons);
753 }
754 rxr->rx_agg_prod = prod;
755 rxr->rx_sw_agg_prod = sw_prod;
756}
757
758static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
759 struct bnxt_rx_ring_info *rxr, u16 cons,
760 u16 prod, u8 *data, dma_addr_t dma_addr,
761 unsigned int len)
762{
763 int err;
764 struct sk_buff *skb;
765
766 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
767 if (unlikely(err)) {
768 bnxt_reuse_rx_data(rxr, cons, data);
769 return NULL;
770 }
771
772 skb = build_skb(data, 0);
773 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
774 PCI_DMA_FROMDEVICE);
775 if (!skb) {
776 kfree(data);
777 return NULL;
778 }
779
780 skb_reserve(skb, BNXT_RX_OFFSET);
781 skb_put(skb, len);
782 return skb;
783}
784
785static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
786 struct sk_buff *skb, u16 cp_cons,
787 u32 agg_bufs)
788{
789 struct pci_dev *pdev = bp->pdev;
790 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 791 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 792 u16 prod = rxr->rx_agg_prod;
793 u32 i;
794
795 for (i = 0; i < agg_bufs; i++) {
796 u16 cons, frag_len;
797 struct rx_agg_cmp *agg;
798 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
799 struct page *page;
800 dma_addr_t mapping;
801
802 agg = (struct rx_agg_cmp *)
803 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
804 cons = agg->rx_agg_cmp_opaque;
805 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
806 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
807
808 cons_rx_buf = &rxr->rx_agg_ring[cons];
89d0a06c
MC		 809 skb_fill_page_desc(skb, i, cons_rx_buf->page,
810 cons_rx_buf->offset, frag_len);
c0c050c5
MC		 811 __clear_bit(cons, rxr->rx_agg_bmap);
812
813 /* It is possible for bnxt_alloc_rx_page() to allocate
814 * a sw_prod index that equals the cons index, so we
815 * need to clear the cons entry now.
816 */
817 mapping = dma_unmap_addr(cons_rx_buf, mapping);
818 page = cons_rx_buf->page;
819 cons_rx_buf->page = NULL;
820
821 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
822 struct skb_shared_info *shinfo;
823 unsigned int nr_frags;
824
825 shinfo = skb_shinfo(skb);
826 nr_frags = --shinfo->nr_frags;
827 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
828
829 dev_kfree_skb(skb);
830
831 cons_rx_buf->page = page;
832
833 /* Update prod since possibly some pages have been
834 * allocated already.
835 */
836 rxr->rx_agg_prod = prod;
837 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
838 return NULL;
839 }
840
2839f28b 841 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
c0c050c5
MC		 842 PCI_DMA_FROMDEVICE);
843
844 skb->data_len += frag_len;
845 skb->len += frag_len;
846 skb->truesize += PAGE_SIZE;
847
848 prod = NEXT_RX_AGG(prod);
849 cp_cons = NEXT_CMP(cp_cons);
850 }
851 rxr->rx_agg_prod = prod;
852 return skb;
853}
854
855static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
856 u8 agg_bufs, u32 *raw_cons)
857{
858 u16 last;
859 struct rx_agg_cmp *agg;
860
861 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
862 last = RING_CMP(*raw_cons);
863 agg = (struct rx_agg_cmp *)
864 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
865 return RX_AGG_CMP_VALID(agg, *raw_cons);
866}
867
868static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
869 unsigned int len,
870 dma_addr_t mapping)
871{
872 struct bnxt *bp = bnapi->bp;
873 struct pci_dev *pdev = bp->pdev;
874 struct sk_buff *skb;
875
876 skb = napi_alloc_skb(&bnapi->napi, len);
877 if (!skb)
878 return NULL;
879
880 dma_sync_single_for_cpu(&pdev->dev, mapping,
881 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
882
883 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
884
885 dma_sync_single_for_device(&pdev->dev, mapping,
886 bp->rx_copy_thresh,
887 PCI_DMA_FROMDEVICE);
888
889 skb_put(skb, len);
890 return skb;
891}
892
fa7e2812
MC		 893static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
894 u32 *raw_cons, void *cmp)
895{
896 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
897 struct rx_cmp *rxcmp = cmp;
898 u32 tmp_raw_cons = *raw_cons;
899 u8 cmp_type, agg_bufs = 0;
900
901 cmp_type = RX_CMP_TYPE(rxcmp);
902
903 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
904 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
905 RX_CMP_AGG_BUFS) >>
906 RX_CMP_AGG_BUFS_SHIFT;
907 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
908 struct rx_tpa_end_cmp *tpa_end = cmp;
909
910 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
911 RX_TPA_END_CMP_AGG_BUFS) >>
912 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
913 }
914
915 if (agg_bufs) {
916 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
917 return -EBUSY;
918 }
919 *raw_cons = tmp_raw_cons;
920 return 0;
921}
922
923static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
924{
925 if (!rxr->bnapi->in_reset) {
926 rxr->bnapi->in_reset = true;
927 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
928 schedule_work(&bp->sp_task);
929 }
930 rxr->rx_next_cons = 0xffff;
931}
932
c0c050c5
MC		 933static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
934 struct rx_tpa_start_cmp *tpa_start,
935 struct rx_tpa_start_cmp_ext *tpa_start1)
936{
937 u8 agg_id = TPA_START_AGG_ID(tpa_start);
938 u16 cons, prod;
939 struct bnxt_tpa_info *tpa_info;
940 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
941 struct rx_bd *prod_bd;
942 dma_addr_t mapping;
943
944 cons = tpa_start->rx_tpa_start_cmp_opaque;
945 prod = rxr->rx_prod;
946 cons_rx_buf = &rxr->rx_buf_ring[cons];
947 prod_rx_buf = &rxr->rx_buf_ring[prod];
948 tpa_info = &rxr->rx_tpa[agg_id];
949
fa7e2812
MC		 950 if (unlikely(cons != rxr->rx_next_cons)) {
951 bnxt_sched_reset(bp, rxr);
952 return;
953 }
954
c0c050c5
MC		 955 prod_rx_buf->data = tpa_info->data;
956
957 mapping = tpa_info->mapping;
958 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
959
960 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
961
962 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
963
964 tpa_info->data = cons_rx_buf->data;
965 cons_rx_buf->data = NULL;
966 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
967
968 tpa_info->len =
969 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
970 RX_TPA_START_CMP_LEN_SHIFT;
971 if (likely(TPA_START_HASH_VALID(tpa_start))) {
972 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
973
974 tpa_info->hash_type = PKT_HASH_TYPE_L4;
975 tpa_info->gso_type = SKB_GSO_TCPV4;
976 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
977 if (hash_type == 3)
978 tpa_info->gso_type = SKB_GSO_TCPV6;
979 tpa_info->rss_hash =
980 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
981 } else {
982 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
983 tpa_info->gso_type = 0;
984 if (netif_msg_rx_err(bp))
985 netdev_warn(bp->dev, "TPA packet without valid hash\n");
986 }
987 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
988 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
94758f8d 989 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
c0c050c5
MC		 990
991 rxr->rx_prod = NEXT_RX(prod);
992 cons = NEXT_RX(cons);
376a5b86 993 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 994 cons_rx_buf = &rxr->rx_buf_ring[cons];
995
996 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
997 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
998 cons_rx_buf->data = NULL;
999}
1000
1001static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1002 u16 cp_cons, u32 agg_bufs)
1003{
1004 if (agg_bufs)
1005 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1006}
1007
94758f8d
MC		 1008static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1009 int payload_off, int tcp_ts,
1010 struct sk_buff *skb)
1011{
1012#ifdef CONFIG_INET
1013 struct tcphdr *th;
1014 int len, nw_off;
1015 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1016 u32 hdr_info = tpa_info->hdr_info;
1017 bool loopback = false;
1018
1019 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1020 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1021 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1022
1023 /* If the packet is an internal loopback packet, the offsets will
1024 * have an extra 4 bytes.
1025 */
1026 if (inner_mac_off == 4) {
1027 loopback = true;
1028 } else if (inner_mac_off > 4) {
1029 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1030 ETH_HLEN - 2));
1031
1032 /* We only support inner iPv4/ipv6. If we don't see the
1033 * correct protocol ID, it must be a loopback packet where
1034 * the offsets are off by 4.
1035 */
09a7636a 1036 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
94758f8d
MC		 1037 loopback = true;
1038 }
1039 if (loopback) {
1040 /* internal loopback packet, subtract all offsets by 4 */
1041 inner_ip_off -= 4;
1042 inner_mac_off -= 4;
1043 outer_ip_off -= 4;
1044 }
1045
1046 nw_off = inner_ip_off - ETH_HLEN;
1047 skb_set_network_header(skb, nw_off);
1048 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1049 struct ipv6hdr *iph = ipv6_hdr(skb);
1050
1051 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1052 len = skb->len - skb_transport_offset(skb);
1053 th = tcp_hdr(skb);
1054 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1055 } else {
1056 struct iphdr *iph = ip_hdr(skb);
1057
1058 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1059 len = skb->len - skb_transport_offset(skb);
1060 th = tcp_hdr(skb);
1061 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1062 }
1063
1064 if (inner_mac_off) { /* tunnel */
1065 struct udphdr *uh = NULL;
1066 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1067 ETH_HLEN - 2));
1068
1069 if (proto == htons(ETH_P_IP)) {
1070 struct iphdr *iph = (struct iphdr *)skb->data;
1071
1072 if (iph->protocol == IPPROTO_UDP)
1073 uh = (struct udphdr *)(iph + 1);
1074 } else {
1075 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1076
1077 if (iph->nexthdr == IPPROTO_UDP)
1078 uh = (struct udphdr *)(iph + 1);
1079 }
1080 if (uh) {
1081 if (uh->check)
1082 skb_shinfo(skb)->gso_type |=
1083 SKB_GSO_UDP_TUNNEL_CSUM;
1084 else
1085 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1086 }
1087 }
1088#endif
1089 return skb;
1090}
1091
c0c050c5
MC		 1092#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1093#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1094
309369c9
MC		 1095static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1096 int payload_off, int tcp_ts,
c0c050c5
MC		 1097 struct sk_buff *skb)
1098{
d1611c3a 1099#ifdef CONFIG_INET
c0c050c5 1100 struct tcphdr *th;
309369c9 1101 int len, nw_off, tcp_opt_len;
27e24189 1102
309369c9 1103 if (tcp_ts)
c0c050c5
MC		 1104 tcp_opt_len = 12;
1105
c0c050c5
MC		 1106 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1107 struct iphdr *iph;
1108
1109 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1110 ETH_HLEN;
1111 skb_set_network_header(skb, nw_off);
1112 iph = ip_hdr(skb);
1113 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1114 len = skb->len - skb_transport_offset(skb);
1115 th = tcp_hdr(skb);
1116 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1117 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1118 struct ipv6hdr *iph;
1119
1120 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1121 ETH_HLEN;
1122 skb_set_network_header(skb, nw_off);
1123 iph = ipv6_hdr(skb);
1124 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1125 len = skb->len - skb_transport_offset(skb);
1126 th = tcp_hdr(skb);
1127 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1128 } else {
1129 dev_kfree_skb_any(skb);
1130 return NULL;
1131 }
1132 tcp_gro_complete(skb);
1133
1134 if (nw_off) { /* tunnel */
1135 struct udphdr *uh = NULL;
1136
1137 if (skb->protocol == htons(ETH_P_IP)) {
1138 struct iphdr *iph = (struct iphdr *)skb->data;
1139
1140 if (iph->protocol == IPPROTO_UDP)
1141 uh = (struct udphdr *)(iph + 1);
1142 } else {
1143 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1144
1145 if (iph->nexthdr == IPPROTO_UDP)
1146 uh = (struct udphdr *)(iph + 1);
1147 }
1148 if (uh) {
1149 if (uh->check)
1150 skb_shinfo(skb)->gso_type |=
1151 SKB_GSO_UDP_TUNNEL_CSUM;
1152 else
1153 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1154 }
1155 }
1156#endif
1157 return skb;
1158}
1159
309369c9
MC		 1160static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1161 struct bnxt_tpa_info *tpa_info,
1162 struct rx_tpa_end_cmp *tpa_end,
1163 struct rx_tpa_end_cmp_ext *tpa_end1,
1164 struct sk_buff *skb)
1165{
1166#ifdef CONFIG_INET
1167 int payload_off;
1168 u16 segs;
1169
1170 segs = TPA_END_TPA_SEGS(tpa_end);
1171 if (segs == 1)
1172 return skb;
1173
1174 NAPI_GRO_CB(skb)->count = segs;
1175 skb_shinfo(skb)->gso_size =
1176 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1177 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1178 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1179 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1180 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1181 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1182#endif
1183 return skb;
1184}
1185
c0c050c5
MC		 1186static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1187 struct bnxt_napi *bnapi,
1188 u32 *raw_cons,
1189 struct rx_tpa_end_cmp *tpa_end,
1190 struct rx_tpa_end_cmp_ext *tpa_end1,
1191 bool *agg_event)
1192{
1193 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1194 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1195 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1196 u8 *data, agg_bufs;
1197 u16 cp_cons = RING_CMP(*raw_cons);
1198 unsigned int len;
1199 struct bnxt_tpa_info *tpa_info;
1200 dma_addr_t mapping;
1201 struct sk_buff *skb;
1202
fa7e2812
MC		 1203 if (unlikely(bnapi->in_reset)) {
1204 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1205
1206 if (rc < 0)
1207 return ERR_PTR(-EBUSY);
1208 return NULL;
1209 }
1210
c0c050c5
MC		 1211 tpa_info = &rxr->rx_tpa[agg_id];
1212 data = tpa_info->data;
1213 prefetch(data);
1214 len = tpa_info->len;
1215 mapping = tpa_info->mapping;
1216
1217 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1218 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1219
1220 if (agg_bufs) {
1221 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1222 return ERR_PTR(-EBUSY);
1223
1224 *agg_event = true;
1225 cp_cons = NEXT_CMP(cp_cons);
1226 }
1227
1228 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1229 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1230 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1231 agg_bufs, (int)MAX_SKB_FRAGS);
1232 return NULL;
1233 }
1234
1235 if (len <= bp->rx_copy_thresh) {
1236 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1237 if (!skb) {
1238 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1239 return NULL;
1240 }
1241 } else {
1242 u8 *new_data;
1243 dma_addr_t new_mapping;
1244
1245 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1246 if (!new_data) {
1247 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1248 return NULL;
1249 }
1250
1251 tpa_info->data = new_data;
1252 tpa_info->mapping = new_mapping;
1253
1254 skb = build_skb(data, 0);
1255 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1256 PCI_DMA_FROMDEVICE);
1257
1258 if (!skb) {
1259 kfree(data);
1260 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1261 return NULL;
1262 }
1263 skb_reserve(skb, BNXT_RX_OFFSET);
1264 skb_put(skb, len);
1265 }
1266
1267 if (agg_bufs) {
1268 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1269 if (!skb) {
1270 /* Page reuse already handled by bnxt_rx_pages(). */
1271 return NULL;
1272 }
1273 }
1274 skb->protocol = eth_type_trans(skb, bp->dev);
1275
1276 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1277 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1278
8852ddb4
MC		 1279 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1280 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5
MC		 1281 u16 vlan_proto = tpa_info->metadata >>
1282 RX_CMP_FLAGS2_METADATA_TPID_SFT;
8852ddb4 1283 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5 1284
8852ddb4 1285 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1286 }
1287
1288 skb_checksum_none_assert(skb);
1289 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1290 skb->ip_summed = CHECKSUM_UNNECESSARY;
1291 skb->csum_level =
1292 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1293 }
1294
1295 if (TPA_END_GRO(tpa_end))
309369c9 1296 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
c0c050c5
MC		 1297
1298 return skb;
1299}
1300
1301/* returns the following:
1302 * 1 - 1 packet successfully received
1303 * 0 - successful TPA_START, packet not completed yet
1304 * -EBUSY - completion ring does not have all the agg buffers yet
1305 * -ENOMEM - packet aborted due to out of memory
1306 * -EIO - packet aborted due to hw error indicated in BD
1307 */
1308static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1309 bool *agg_event)
1310{
1311 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1312 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1313 struct net_device *dev = bp->dev;
1314 struct rx_cmp *rxcmp;
1315 struct rx_cmp_ext *rxcmp1;
1316 u32 tmp_raw_cons = *raw_cons;
1317 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1318 struct bnxt_sw_rx_bd *rx_buf;
1319 unsigned int len;
1320 u8 *data, agg_bufs, cmp_type;
1321 dma_addr_t dma_addr;
1322 struct sk_buff *skb;
1323 int rc = 0;
1324
1325 rxcmp = (struct rx_cmp *)
1326 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1327
1328 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1329 cp_cons = RING_CMP(tmp_raw_cons);
1330 rxcmp1 = (struct rx_cmp_ext *)
1331 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1332
1333 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1334 return -EBUSY;
1335
1336 cmp_type = RX_CMP_TYPE(rxcmp);
1337
1338 prod = rxr->rx_prod;
1339
1340 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1341 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1342 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1343
1344 goto next_rx_no_prod;
1345
1346 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1347 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1348 (struct rx_tpa_end_cmp *)rxcmp,
1349 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1350 agg_event);
1351
1352 if (unlikely(IS_ERR(skb)))
1353 return -EBUSY;
1354
1355 rc = -ENOMEM;
1356 if (likely(skb)) {
1357 skb_record_rx_queue(skb, bnapi->index);
1358 skb_mark_napi_id(skb, &bnapi->napi);
1359 if (bnxt_busy_polling(bnapi))
1360 netif_receive_skb(skb);
1361 else
1362 napi_gro_receive(&bnapi->napi, skb);
1363 rc = 1;
1364 }
1365 goto next_rx_no_prod;
1366 }
1367
1368 cons = rxcmp->rx_cmp_opaque;
1369 rx_buf = &rxr->rx_buf_ring[cons];
1370 data = rx_buf->data;
fa7e2812
MC		 1371 if (unlikely(cons != rxr->rx_next_cons)) {
1372 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1373
1374 bnxt_sched_reset(bp, rxr);
1375 return rc1;
1376 }
c0c050c5
MC		 1377 prefetch(data);
1378
1379 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1380 RX_CMP_AGG_BUFS_SHIFT;
1381
1382 if (agg_bufs) {
1383 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1384 return -EBUSY;
1385
1386 cp_cons = NEXT_CMP(cp_cons);
1387 *agg_event = true;
1388 }
1389
1390 rx_buf->data = NULL;
1391 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1392 bnxt_reuse_rx_data(rxr, cons, data);
1393 if (agg_bufs)
1394 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1395
1396 rc = -EIO;
1397 goto next_rx;
1398 }
1399
1400 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1401 dma_addr = dma_unmap_addr(rx_buf, mapping);
1402
1403 if (len <= bp->rx_copy_thresh) {
1404 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1405 bnxt_reuse_rx_data(rxr, cons, data);
1406 if (!skb) {
1407 rc = -ENOMEM;
1408 goto next_rx;
1409 }
1410 } else {
1411 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1412 if (!skb) {
1413 rc = -ENOMEM;
1414 goto next_rx;
1415 }
1416 }
1417
1418 if (agg_bufs) {
1419 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1420 if (!skb) {
1421 rc = -ENOMEM;
1422 goto next_rx;
1423 }
1424 }
1425
1426 if (RX_CMP_HASH_VALID(rxcmp)) {
1427 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1428 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1429
1430 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1431 if (hash_type != 1 && hash_type != 3)
1432 type = PKT_HASH_TYPE_L3;
1433 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1434 }
1435
1436 skb->protocol = eth_type_trans(skb, dev);
1437
8852ddb4
MC		 1438 if ((rxcmp1->rx_cmp_flags2 &
1439 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1440 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5 1441 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
8852ddb4 1442 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5
MC		 1443 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1444
8852ddb4 1445 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1446 }
1447
1448 skb_checksum_none_assert(skb);
1449 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1450 if (dev->features & NETIF_F_RXCSUM) {
1451 skb->ip_summed = CHECKSUM_UNNECESSARY;
1452 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1453 }
1454 } else {
665e350d
SB		 1455 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1456 if (dev->features & NETIF_F_RXCSUM)
1457 cpr->rx_l4_csum_errors++;
1458 }
c0c050c5
MC		 1459 }
1460
1461 skb_record_rx_queue(skb, bnapi->index);
1462 skb_mark_napi_id(skb, &bnapi->napi);
1463 if (bnxt_busy_polling(bnapi))
1464 netif_receive_skb(skb);
1465 else
1466 napi_gro_receive(&bnapi->napi, skb);
1467 rc = 1;
1468
1469next_rx:
1470 rxr->rx_prod = NEXT_RX(prod);
376a5b86 1471 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1472
1473next_rx_no_prod:
1474 *raw_cons = tmp_raw_cons;
1475
1476 return rc;
1477}
1478
4bb13abf 1479#define BNXT_GET_EVENT_PORT(data) \
87c374de
MC		 1480 ((data) & \
1481 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
4bb13abf 1482
c0c050c5
MC		 1483static int bnxt_async_event_process(struct bnxt *bp,
1484 struct hwrm_async_event_cmpl *cmpl)
1485{
1486 u16 event_id = le16_to_cpu(cmpl->event_id);
1487
1488 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1489 switch (event_id) {
87c374de 1490 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
8cbde117
MC		 1491 u32 data1 = le32_to_cpu(cmpl->event_data1);
1492 struct bnxt_link_info *link_info = &bp->link_info;
1493
1494 if (BNXT_VF(bp))
1495 goto async_event_process_exit;
1496 if (data1 & 0x20000) {
1497 u16 fw_speed = link_info->force_link_speed;
1498 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1499
1500 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1501 speed);
1502 }
286ef9d6 1503 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
8cbde117
MC		 1504 /* fall thru */
1505 }
87c374de 1506 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
c0c050c5 1507 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368 1508 break;
87c374de 1509 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
19241368 1510 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5 1511 break;
87c374de 1512 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
4bb13abf
MC		 1513 u32 data1 = le32_to_cpu(cmpl->event_data1);
1514 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1515
1516 if (BNXT_VF(bp))
1517 break;
1518
1519 if (bp->pf.port_id != port_id)
1520 break;
1521
4bb13abf
MC		 1522 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1523 break;
1524 }
87c374de 1525 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
fc0f1929
MC		 1526 if (BNXT_PF(bp))
1527 goto async_event_process_exit;
1528 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1529 break;
c0c050c5
MC		 1530 default:
1531 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1532 event_id);
19241368 1533 goto async_event_process_exit;
c0c050c5 1534 }
19241368
JH		 1535 schedule_work(&bp->sp_task);
1536async_event_process_exit:
c0c050c5
MC		 1537 return 0;
1538}
1539
1540static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1541{
1542 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1543 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1544 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1545 (struct hwrm_fwd_req_cmpl *)txcmp;
1546
1547 switch (cmpl_type) {
1548 case CMPL_BASE_TYPE_HWRM_DONE:
1549 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1550 if (seq_id == bp->hwrm_intr_seq_id)
1551 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1552 else
1553 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1554 break;
1555
1556 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1557 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1558
1559 if ((vf_id < bp->pf.first_vf_id) ||
1560 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1561 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1562 vf_id);
1563 return -EINVAL;
1564 }
1565
1566 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1567 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1568 schedule_work(&bp->sp_task);
1569 break;
1570
1571 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1572 bnxt_async_event_process(bp,
1573 (struct hwrm_async_event_cmpl *)txcmp);
1574
1575 default:
1576 break;
1577 }
1578
1579 return 0;
1580}
1581
1582static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1583{
1584 struct bnxt_napi *bnapi = dev_instance;
1585 struct bnxt *bp = bnapi->bp;
1586 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1587 u32 cons = RING_CMP(cpr->cp_raw_cons);
1588
1589 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1590 napi_schedule(&bnapi->napi);
1591 return IRQ_HANDLED;
1592}
1593
1594static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1595{
1596 u32 raw_cons = cpr->cp_raw_cons;
1597 u16 cons = RING_CMP(raw_cons);
1598 struct tx_cmp *txcmp;
1599
1600 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1601
1602 return TX_CMP_VALID(txcmp, raw_cons);
1603}
1604
c0c050c5
MC		 1605static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1606{
1607 struct bnxt_napi *bnapi = dev_instance;
1608 struct bnxt *bp = bnapi->bp;
1609 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1610 u32 cons = RING_CMP(cpr->cp_raw_cons);
1611 u32 int_status;
1612
1613 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1614
1615 if (!bnxt_has_work(bp, cpr)) {
11809490 1616 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1617 /* return if erroneous interrupt */
1618 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1619 return IRQ_NONE;
1620 }
1621
1622 /* disable ring IRQ */
1623 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1624
1625 /* Return here if interrupt is shared and is disabled. */
1626 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1627 return IRQ_HANDLED;
1628
1629 napi_schedule(&bnapi->napi);
1630 return IRQ_HANDLED;
1631}
1632
1633static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1634{
1635 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1636 u32 raw_cons = cpr->cp_raw_cons;
1637 u32 cons;
1638 int tx_pkts = 0;
1639 int rx_pkts = 0;
1640 bool rx_event = false;
1641 bool agg_event = false;
1642 struct tx_cmp *txcmp;
1643
1644 while (1) {
1645 int rc;
1646
1647 cons = RING_CMP(raw_cons);
1648 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1649
1650 if (!TX_CMP_VALID(txcmp, raw_cons))
1651 break;
1652
67a95e20
MC		 1653 /* The valid test of the entry must be done first before
1654 * reading any further.
1655 */
b67daab0 1656 dma_rmb();
c0c050c5
MC		 1657 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1658 tx_pkts++;
1659 /* return full budget so NAPI will complete. */
1660 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1661 rx_pkts = budget;
1662 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1663 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1664 if (likely(rc >= 0))
1665 rx_pkts += rc;
1666 else if (rc == -EBUSY) /* partial completion */
1667 break;
1668 rx_event = true;
1669 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1670 CMPL_BASE_TYPE_HWRM_DONE) ||
1671 (TX_CMP_TYPE(txcmp) ==
1672 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1673 (TX_CMP_TYPE(txcmp) ==
1674 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1675 bnxt_hwrm_handler(bp, txcmp);
1676 }
1677 raw_cons = NEXT_RAW_CMP(raw_cons);
1678
1679 if (rx_pkts == budget)
1680 break;
1681 }
1682
1683 cpr->cp_raw_cons = raw_cons;
1684 /* ACK completion ring before freeing tx ring and producing new
1685 * buffers in rx/agg rings to prevent overflowing the completion
1686 * ring.
1687 */
1688 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1689
1690 if (tx_pkts)
1691 bnxt_tx_int(bp, bnapi, tx_pkts);
1692
1693 if (rx_event) {
b6ab4b01 1694 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1695
1696 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1697 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1698 if (agg_event) {
1699 writel(DB_KEY_RX | rxr->rx_agg_prod,
1700 rxr->rx_agg_doorbell);
1701 writel(DB_KEY_RX | rxr->rx_agg_prod,
1702 rxr->rx_agg_doorbell);
1703 }
1704 }
1705 return rx_pkts;
1706}
1707
10bbdaf5
PS		 1708static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1709{
1710 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1711 struct bnxt *bp = bnapi->bp;
1712 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1713 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1714 struct tx_cmp *txcmp;
1715 struct rx_cmp_ext *rxcmp1;
1716 u32 cp_cons, tmp_raw_cons;
1717 u32 raw_cons = cpr->cp_raw_cons;
1718 u32 rx_pkts = 0;
1719 bool agg_event = false;
1720
1721 while (1) {
1722 int rc;
1723
1724 cp_cons = RING_CMP(raw_cons);
1725 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1726
1727 if (!TX_CMP_VALID(txcmp, raw_cons))
1728 break;
1729
1730 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1731 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1732 cp_cons = RING_CMP(tmp_raw_cons);
1733 rxcmp1 = (struct rx_cmp_ext *)
1734 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1735
1736 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1737 break;
1738
1739 /* force an error to recycle the buffer */
1740 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1741 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1742
1743 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1744 if (likely(rc == -EIO))
1745 rx_pkts++;
1746 else if (rc == -EBUSY) /* partial completion */
1747 break;
1748 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1749 CMPL_BASE_TYPE_HWRM_DONE)) {
1750 bnxt_hwrm_handler(bp, txcmp);
1751 } else {
1752 netdev_err(bp->dev,
1753 "Invalid completion received on special ring\n");
1754 }
1755 raw_cons = NEXT_RAW_CMP(raw_cons);
1756
1757 if (rx_pkts == budget)
1758 break;
1759 }
1760
1761 cpr->cp_raw_cons = raw_cons;
1762 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1763 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1764 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1765
1766 if (agg_event) {
1767 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1768 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1769 }
1770
1771 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
1772 napi_complete(napi);
1773 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1774 }
1775 return rx_pkts;
1776}
1777
c0c050c5
MC		 1778static int bnxt_poll(struct napi_struct *napi, int budget)
1779{
1780 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1781 struct bnxt *bp = bnapi->bp;
1782 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1783 int work_done = 0;
1784
1785 if (!bnxt_lock_napi(bnapi))
1786 return budget;
1787
1788 while (1) {
1789 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1790
1791 if (work_done >= budget)
1792 break;
1793
1794 if (!bnxt_has_work(bp, cpr)) {
1795 napi_complete(napi);
1796 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1797 break;
1798 }
1799 }
1800 mmiowb();
1801 bnxt_unlock_napi(bnapi);
1802 return work_done;
1803}
1804
1805#ifdef CONFIG_NET_RX_BUSY_POLL
1806static int bnxt_busy_poll(struct napi_struct *napi)
1807{
1808 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1809 struct bnxt *bp = bnapi->bp;
1810 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1811 int rx_work, budget = 4;
1812
1813 if (atomic_read(&bp->intr_sem) != 0)
1814 return LL_FLUSH_FAILED;
1815
867d1212
AG		 1816 if (!bp->link_info.link_up)
1817 return LL_FLUSH_FAILED;
1818
c0c050c5
MC		 1819 if (!bnxt_lock_poll(bnapi))
1820 return LL_FLUSH_BUSY;
1821
1822 rx_work = bnxt_poll_work(bp, bnapi, budget);
1823
1824 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1825
1826 bnxt_unlock_poll(bnapi);
1827 return rx_work;
1828}
1829#endif
1830
1831static void bnxt_free_tx_skbs(struct bnxt *bp)
1832{
1833 int i, max_idx;
1834 struct pci_dev *pdev = bp->pdev;
1835
b6ab4b01 1836 if (!bp->tx_ring)
c0c050c5
MC		 1837 return;
1838
1839 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1840 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1841 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1842 int j;
1843
c0c050c5
MC		 1844 for (j = 0; j < max_idx;) {
1845 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1846 struct sk_buff *skb = tx_buf->skb;
1847 int k, last;
1848
1849 if (!skb) {
1850 j++;
1851 continue;
1852 }
1853
1854 tx_buf->skb = NULL;
1855
1856 if (tx_buf->is_push) {
1857 dev_kfree_skb(skb);
1858 j += 2;
1859 continue;
1860 }
1861
1862 dma_unmap_single(&pdev->dev,
1863 dma_unmap_addr(tx_buf, mapping),
1864 skb_headlen(skb),
1865 PCI_DMA_TODEVICE);
1866
1867 last = tx_buf->nr_frags;
1868 j += 2;
d612a579
MC		 1869 for (k = 0; k < last; k++, j++) {
1870 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 1871 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1872
d612a579 1873 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 1874 dma_unmap_page(
1875 &pdev->dev,
1876 dma_unmap_addr(tx_buf, mapping),
1877 skb_frag_size(frag), PCI_DMA_TODEVICE);
1878 }
1879 dev_kfree_skb(skb);
1880 }
1881 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1882 }
1883}
1884
1885static void bnxt_free_rx_skbs(struct bnxt *bp)
1886{
1887 int i, max_idx, max_agg_idx;
1888 struct pci_dev *pdev = bp->pdev;
1889
b6ab4b01 1890 if (!bp->rx_ring)
c0c050c5
MC		 1891 return;
1892
1893 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1894 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1895 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1896 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1897 int j;
1898
c0c050c5
MC		 1899 if (rxr->rx_tpa) {
1900 for (j = 0; j < MAX_TPA; j++) {
1901 struct bnxt_tpa_info *tpa_info =
1902 &rxr->rx_tpa[j];
1903 u8 *data = tpa_info->data;
1904
1905 if (!data)
1906 continue;
1907
1908 dma_unmap_single(
1909 &pdev->dev,
1910 dma_unmap_addr(tpa_info, mapping),
1911 bp->rx_buf_use_size,
1912 PCI_DMA_FROMDEVICE);
1913
1914 tpa_info->data = NULL;
1915
1916 kfree(data);
1917 }
1918 }
1919
1920 for (j = 0; j < max_idx; j++) {
1921 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1922 u8 *data = rx_buf->data;
1923
1924 if (!data)
1925 continue;
1926
1927 dma_unmap_single(&pdev->dev,
1928 dma_unmap_addr(rx_buf, mapping),
1929 bp->rx_buf_use_size,
1930 PCI_DMA_FROMDEVICE);
1931
1932 rx_buf->data = NULL;
1933
1934 kfree(data);
1935 }
1936
1937 for (j = 0; j < max_agg_idx; j++) {
1938 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1939 &rxr->rx_agg_ring[j];
1940 struct page *page = rx_agg_buf->page;
1941
1942 if (!page)
1943 continue;
1944
1945 dma_unmap_page(&pdev->dev,
1946 dma_unmap_addr(rx_agg_buf, mapping),
2839f28b 1947 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
c0c050c5
MC		 1948
1949 rx_agg_buf->page = NULL;
1950 __clear_bit(j, rxr->rx_agg_bmap);
1951
1952 __free_page(page);
1953 }
89d0a06c
MC		 1954 if (rxr->rx_page) {
1955 __free_page(rxr->rx_page);
1956 rxr->rx_page = NULL;
1957 }
c0c050c5
MC		 1958 }
1959}
1960
1961static void bnxt_free_skbs(struct bnxt *bp)
1962{
1963 bnxt_free_tx_skbs(bp);
1964 bnxt_free_rx_skbs(bp);
1965}
1966
1967static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1968{
1969 struct pci_dev *pdev = bp->pdev;
1970 int i;
1971
1972 for (i = 0; i < ring->nr_pages; i++) {
1973 if (!ring->pg_arr[i])
1974 continue;
1975
1976 dma_free_coherent(&pdev->dev, ring->page_size,
1977 ring->pg_arr[i], ring->dma_arr[i]);
1978
1979 ring->pg_arr[i] = NULL;
1980 }
1981 if (ring->pg_tbl) {
1982 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1983 ring->pg_tbl, ring->pg_tbl_map);
1984 ring->pg_tbl = NULL;
1985 }
1986 if (ring->vmem_size && *ring->vmem) {
1987 vfree(*ring->vmem);
1988 *ring->vmem = NULL;
1989 }
1990}
1991
1992static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1993{
1994 int i;
1995 struct pci_dev *pdev = bp->pdev;
1996
1997 if (ring->nr_pages > 1) {
1998 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1999 ring->nr_pages * 8,
2000 &ring->pg_tbl_map,
2001 GFP_KERNEL);
2002 if (!ring->pg_tbl)
2003 return -ENOMEM;
2004 }
2005
2006 for (i = 0; i < ring->nr_pages; i++) {
2007 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2008 ring->page_size,
2009 &ring->dma_arr[i],
2010 GFP_KERNEL);
2011 if (!ring->pg_arr[i])
2012 return -ENOMEM;
2013
2014 if (ring->nr_pages > 1)
2015 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2016 }
2017
2018 if (ring->vmem_size) {
2019 *ring->vmem = vzalloc(ring->vmem_size);
2020 if (!(*ring->vmem))
2021 return -ENOMEM;
2022 }
2023 return 0;
2024}
2025
2026static void bnxt_free_rx_rings(struct bnxt *bp)
2027{
2028 int i;
2029
b6ab4b01 2030 if (!bp->rx_ring)
c0c050c5
MC		 2031 return;
2032
2033 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2034 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2035 struct bnxt_ring_struct *ring;
2036
c0c050c5
MC		 2037 kfree(rxr->rx_tpa);
2038 rxr->rx_tpa = NULL;
2039
2040 kfree(rxr->rx_agg_bmap);
2041 rxr->rx_agg_bmap = NULL;
2042
2043 ring = &rxr->rx_ring_struct;
2044 bnxt_free_ring(bp, ring);
2045
2046 ring = &rxr->rx_agg_ring_struct;
2047 bnxt_free_ring(bp, ring);
2048 }
2049}
2050
2051static int bnxt_alloc_rx_rings(struct bnxt *bp)
2052{
2053 int i, rc, agg_rings = 0, tpa_rings = 0;
2054
b6ab4b01
MC		 2055 if (!bp->rx_ring)
2056 return -ENOMEM;
2057
c0c050c5
MC		 2058 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2059 agg_rings = 1;
2060
2061 if (bp->flags & BNXT_FLAG_TPA)
2062 tpa_rings = 1;
2063
2064 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2065 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2066 struct bnxt_ring_struct *ring;
2067
c0c050c5
MC		 2068 ring = &rxr->rx_ring_struct;
2069
2070 rc = bnxt_alloc_ring(bp, ring);
2071 if (rc)
2072 return rc;
2073
2074 if (agg_rings) {
2075 u16 mem_size;
2076
2077 ring = &rxr->rx_agg_ring_struct;
2078 rc = bnxt_alloc_ring(bp, ring);
2079 if (rc)
2080 return rc;
2081
2082 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2083 mem_size = rxr->rx_agg_bmap_size / 8;
2084 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2085 if (!rxr->rx_agg_bmap)
2086 return -ENOMEM;
2087
2088 if (tpa_rings) {
2089 rxr->rx_tpa = kcalloc(MAX_TPA,
2090 sizeof(struct bnxt_tpa_info),
2091 GFP_KERNEL);
2092 if (!rxr->rx_tpa)
2093 return -ENOMEM;
2094 }
2095 }
2096 }
2097 return 0;
2098}
2099
2100static void bnxt_free_tx_rings(struct bnxt *bp)
2101{
2102 int i;
2103 struct pci_dev *pdev = bp->pdev;
2104
b6ab4b01 2105 if (!bp->tx_ring)
c0c050c5
MC		 2106 return;
2107
2108 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2109 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2110 struct bnxt_ring_struct *ring;
2111
c0c050c5
MC		 2112 if (txr->tx_push) {
2113 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2114 txr->tx_push, txr->tx_push_mapping);
2115 txr->tx_push = NULL;
2116 }
2117
2118 ring = &txr->tx_ring_struct;
2119
2120 bnxt_free_ring(bp, ring);
2121 }
2122}
2123
2124static int bnxt_alloc_tx_rings(struct bnxt *bp)
2125{
2126 int i, j, rc;
2127 struct pci_dev *pdev = bp->pdev;
2128
2129 bp->tx_push_size = 0;
2130 if (bp->tx_push_thresh) {
2131 int push_size;
2132
2133 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2134 bp->tx_push_thresh);
2135
4419dbe6 2136 if (push_size > 256) {
c0c050c5
MC		 2137 push_size = 0;
2138 bp->tx_push_thresh = 0;
2139 }
2140
2141 bp->tx_push_size = push_size;
2142 }
2143
2144 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2145 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2146 struct bnxt_ring_struct *ring;
2147
c0c050c5
MC		 2148 ring = &txr->tx_ring_struct;
2149
2150 rc = bnxt_alloc_ring(bp, ring);
2151 if (rc)
2152 return rc;
2153
2154 if (bp->tx_push_size) {
c0c050c5
MC		 2155 dma_addr_t mapping;
2156
2157 /* One pre-allocated DMA buffer to backup
2158 * TX push operation
2159 */
2160 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2161 bp->tx_push_size,
2162 &txr->tx_push_mapping,
2163 GFP_KERNEL);
2164
2165 if (!txr->tx_push)
2166 return -ENOMEM;
2167
c0c050c5
MC		 2168 mapping = txr->tx_push_mapping +
2169 sizeof(struct tx_push_bd);
4419dbe6 2170 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 2171
4419dbe6 2172 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5
MC		 2173 }
2174 ring->queue_id = bp->q_info[j].queue_id;
2175 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2176 j++;
2177 }
2178 return 0;
2179}
2180
2181static void bnxt_free_cp_rings(struct bnxt *bp)
2182{
2183 int i;
2184
2185 if (!bp->bnapi)
2186 return;
2187
2188 for (i = 0; i < bp->cp_nr_rings; i++) {
2189 struct bnxt_napi *bnapi = bp->bnapi[i];
2190 struct bnxt_cp_ring_info *cpr;
2191 struct bnxt_ring_struct *ring;
2192
2193 if (!bnapi)
2194 continue;
2195
2196 cpr = &bnapi->cp_ring;
2197 ring = &cpr->cp_ring_struct;
2198
2199 bnxt_free_ring(bp, ring);
2200 }
2201}
2202
2203static int bnxt_alloc_cp_rings(struct bnxt *bp)
2204{
2205 int i, rc;
2206
2207 for (i = 0; i < bp->cp_nr_rings; i++) {
2208 struct bnxt_napi *bnapi = bp->bnapi[i];
2209 struct bnxt_cp_ring_info *cpr;
2210 struct bnxt_ring_struct *ring;
2211
2212 if (!bnapi)
2213 continue;
2214
2215 cpr = &bnapi->cp_ring;
2216 ring = &cpr->cp_ring_struct;
2217
2218 rc = bnxt_alloc_ring(bp, ring);
2219 if (rc)
2220 return rc;
2221 }
2222 return 0;
2223}
2224
2225static void bnxt_init_ring_struct(struct bnxt *bp)
2226{
2227 int i;
2228
2229 for (i = 0; i < bp->cp_nr_rings; i++) {
2230 struct bnxt_napi *bnapi = bp->bnapi[i];
2231 struct bnxt_cp_ring_info *cpr;
2232 struct bnxt_rx_ring_info *rxr;
2233 struct bnxt_tx_ring_info *txr;
2234 struct bnxt_ring_struct *ring;
2235
2236 if (!bnapi)
2237 continue;
2238
2239 cpr = &bnapi->cp_ring;
2240 ring = &cpr->cp_ring_struct;
2241 ring->nr_pages = bp->cp_nr_pages;
2242 ring->page_size = HW_CMPD_RING_SIZE;
2243 ring->pg_arr = (void **)cpr->cp_desc_ring;
2244 ring->dma_arr = cpr->cp_desc_mapping;
2245 ring->vmem_size = 0;
2246
b6ab4b01 2247 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2248 if (!rxr)
2249 goto skip_rx;
2250
c0c050c5
MC		 2251 ring = &rxr->rx_ring_struct;
2252 ring->nr_pages = bp->rx_nr_pages;
2253 ring->page_size = HW_RXBD_RING_SIZE;
2254 ring->pg_arr = (void **)rxr->rx_desc_ring;
2255 ring->dma_arr = rxr->rx_desc_mapping;
2256 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2257 ring->vmem = (void **)&rxr->rx_buf_ring;
2258
2259 ring = &rxr->rx_agg_ring_struct;
2260 ring->nr_pages = bp->rx_agg_nr_pages;
2261 ring->page_size = HW_RXBD_RING_SIZE;
2262 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2263 ring->dma_arr = rxr->rx_agg_desc_mapping;
2264 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2265 ring->vmem = (void **)&rxr->rx_agg_ring;
2266
3b2b7d9d 2267skip_rx:
b6ab4b01 2268 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2269 if (!txr)
2270 continue;
2271
c0c050c5
MC		 2272 ring = &txr->tx_ring_struct;
2273 ring->nr_pages = bp->tx_nr_pages;
2274 ring->page_size = HW_RXBD_RING_SIZE;
2275 ring->pg_arr = (void **)txr->tx_desc_ring;
2276 ring->dma_arr = txr->tx_desc_mapping;
2277 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2278 ring->vmem = (void **)&txr->tx_buf_ring;
2279 }
2280}
2281
2282static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2283{
2284 int i;
2285 u32 prod;
2286 struct rx_bd **rx_buf_ring;
2287
2288 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2289 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2290 int j;
2291 struct rx_bd *rxbd;
2292
2293 rxbd = rx_buf_ring[i];
2294 if (!rxbd)
2295 continue;
2296
2297 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2298 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2299 rxbd->rx_bd_opaque = prod;
2300 }
2301 }
2302}
2303
2304static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2305{
2306 struct net_device *dev = bp->dev;
c0c050c5
MC		 2307 struct bnxt_rx_ring_info *rxr;
2308 struct bnxt_ring_struct *ring;
2309 u32 prod, type;
2310 int i;
2311
c0c050c5
MC		 2312 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2313 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2314
2315 if (NET_IP_ALIGN == 2)
2316 type |= RX_BD_FLAGS_SOP;
2317
b6ab4b01 2318 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 2319 ring = &rxr->rx_ring_struct;
2320 bnxt_init_rxbd_pages(ring, type);
2321
2322 prod = rxr->rx_prod;
2323 for (i = 0; i < bp->rx_ring_size; i++) {
2324 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2325 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2326 ring_nr, i, bp->rx_ring_size);
2327 break;
2328 }
2329 prod = NEXT_RX(prod);
2330 }
2331 rxr->rx_prod = prod;
2332 ring->fw_ring_id = INVALID_HW_RING_ID;
2333
edd0c2cc
MC		 2334 ring = &rxr->rx_agg_ring_struct;
2335 ring->fw_ring_id = INVALID_HW_RING_ID;
2336
c0c050c5
MC		 2337 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2338 return 0;
2339
2839f28b 2340 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
c0c050c5
MC		 2341 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2342
2343 bnxt_init_rxbd_pages(ring, type);
2344
2345 prod = rxr->rx_agg_prod;
2346 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2347 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2348 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2349 ring_nr, i, bp->rx_ring_size);
2350 break;
2351 }
2352 prod = NEXT_RX_AGG(prod);
2353 }
2354 rxr->rx_agg_prod = prod;
c0c050c5
MC		 2355
2356 if (bp->flags & BNXT_FLAG_TPA) {
2357 if (rxr->rx_tpa) {
2358 u8 *data;
2359 dma_addr_t mapping;
2360
2361 for (i = 0; i < MAX_TPA; i++) {
2362 data = __bnxt_alloc_rx_data(bp, &mapping,
2363 GFP_KERNEL);
2364 if (!data)
2365 return -ENOMEM;
2366
2367 rxr->rx_tpa[i].data = data;
2368 rxr->rx_tpa[i].mapping = mapping;
2369 }
2370 } else {
2371 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2372 return -ENOMEM;
2373 }
2374 }
2375
2376 return 0;
2377}
2378
2379static int bnxt_init_rx_rings(struct bnxt *bp)
2380{
2381 int i, rc = 0;
2382
2383 for (i = 0; i < bp->rx_nr_rings; i++) {
2384 rc = bnxt_init_one_rx_ring(bp, i);
2385 if (rc)
2386 break;
2387 }
2388
2389 return rc;
2390}
2391
2392static int bnxt_init_tx_rings(struct bnxt *bp)
2393{
2394 u16 i;
2395
2396 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2397 MAX_SKB_FRAGS + 1);
2398
2399 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2400 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2401 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2402
2403 ring->fw_ring_id = INVALID_HW_RING_ID;
2404 }
2405
2406 return 0;
2407}
2408
2409static void bnxt_free_ring_grps(struct bnxt *bp)
2410{
2411 kfree(bp->grp_info);
2412 bp->grp_info = NULL;
2413}
2414
2415static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2416{
2417 int i;
2418
2419 if (irq_re_init) {
2420 bp->grp_info = kcalloc(bp->cp_nr_rings,
2421 sizeof(struct bnxt_ring_grp_info),
2422 GFP_KERNEL);
2423 if (!bp->grp_info)
2424 return -ENOMEM;
2425 }
2426 for (i = 0; i < bp->cp_nr_rings; i++) {
2427 if (irq_re_init)
2428 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2429 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2430 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2431 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2432 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2433 }
2434 return 0;
2435}
2436
2437static void bnxt_free_vnics(struct bnxt *bp)
2438{
2439 kfree(bp->vnic_info);
2440 bp->vnic_info = NULL;
2441 bp->nr_vnics = 0;
2442}
2443
2444static int bnxt_alloc_vnics(struct bnxt *bp)
2445{
2446 int num_vnics = 1;
2447
2448#ifdef CONFIG_RFS_ACCEL
2449 if (bp->flags & BNXT_FLAG_RFS)
2450 num_vnics += bp->rx_nr_rings;
2451#endif
2452
dc52c6c7
PS		 2453 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2454 num_vnics++;
2455
c0c050c5
MC		 2456 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2457 GFP_KERNEL);
2458 if (!bp->vnic_info)
2459 return -ENOMEM;
2460
2461 bp->nr_vnics = num_vnics;
2462 return 0;
2463}
2464
2465static void bnxt_init_vnics(struct bnxt *bp)
2466{
2467 int i;
2468
2469 for (i = 0; i < bp->nr_vnics; i++) {
2470 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2471
2472 vnic->fw_vnic_id = INVALID_HW_RING_ID;
94ce9caa
PS		 2473 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2474 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 2475 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2476
2477 if (bp->vnic_info[i].rss_hash_key) {
2478 if (i == 0)
2479 prandom_bytes(vnic->rss_hash_key,
2480 HW_HASH_KEY_SIZE);
2481 else
2482 memcpy(vnic->rss_hash_key,
2483 bp->vnic_info[0].rss_hash_key,
2484 HW_HASH_KEY_SIZE);
2485 }
2486 }
2487}
2488
2489static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2490{
2491 int pages;
2492
2493 pages = ring_size / desc_per_pg;
2494
2495 if (!pages)
2496 return 1;
2497
2498 pages++;
2499
2500 while (pages & (pages - 1))
2501 pages++;
2502
2503 return pages;
2504}
2505
2506static void bnxt_set_tpa_flags(struct bnxt *bp)
2507{
2508 bp->flags &= ~BNXT_FLAG_TPA;
2509 if (bp->dev->features & NETIF_F_LRO)
2510 bp->flags |= BNXT_FLAG_LRO;
94758f8d 2511 if (bp->dev->features & NETIF_F_GRO)
c0c050c5
MC		 2512 bp->flags |= BNXT_FLAG_GRO;
2513}
2514
2515/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2516 * be set on entry.
2517 */
2518void bnxt_set_ring_params(struct bnxt *bp)
2519{
2520 u32 ring_size, rx_size, rx_space;
2521 u32 agg_factor = 0, agg_ring_size = 0;
2522
2523 /* 8 for CRC and VLAN */
2524 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2525
2526 rx_space = rx_size + NET_SKB_PAD +
2527 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2528
2529 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2530 ring_size = bp->rx_ring_size;
2531 bp->rx_agg_ring_size = 0;
2532 bp->rx_agg_nr_pages = 0;
2533
2534 if (bp->flags & BNXT_FLAG_TPA)
2839f28b 2535 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
c0c050c5
MC		 2536
2537 bp->flags &= ~BNXT_FLAG_JUMBO;
2538 if (rx_space > PAGE_SIZE) {
2539 u32 jumbo_factor;
2540
2541 bp->flags |= BNXT_FLAG_JUMBO;
2542 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2543 if (jumbo_factor > agg_factor)
2544 agg_factor = jumbo_factor;
2545 }
2546 agg_ring_size = ring_size * agg_factor;
2547
2548 if (agg_ring_size) {
2549 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2550 RX_DESC_CNT);
2551 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2552 u32 tmp = agg_ring_size;
2553
2554 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2555 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2556 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2557 tmp, agg_ring_size);
2558 }
2559 bp->rx_agg_ring_size = agg_ring_size;
2560 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2561 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2562 rx_space = rx_size + NET_SKB_PAD +
2563 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2564 }
2565
2566 bp->rx_buf_use_size = rx_size;
2567 bp->rx_buf_size = rx_space;
2568
2569 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2570 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2571
2572 ring_size = bp->tx_ring_size;
2573 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2574 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2575
2576 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2577 bp->cp_ring_size = ring_size;
2578
2579 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2580 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2581 bp->cp_nr_pages = MAX_CP_PAGES;
2582 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2583 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2584 ring_size, bp->cp_ring_size);
2585 }
2586 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2587 bp->cp_ring_mask = bp->cp_bit - 1;
2588}
2589
2590static void bnxt_free_vnic_attributes(struct bnxt *bp)
2591{
2592 int i;
2593 struct bnxt_vnic_info *vnic;
2594 struct pci_dev *pdev = bp->pdev;
2595
2596 if (!bp->vnic_info)
2597 return;
2598
2599 for (i = 0; i < bp->nr_vnics; i++) {
2600 vnic = &bp->vnic_info[i];
2601
2602 kfree(vnic->fw_grp_ids);
2603 vnic->fw_grp_ids = NULL;
2604
2605 kfree(vnic->uc_list);
2606 vnic->uc_list = NULL;
2607
2608 if (vnic->mc_list) {
2609 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2610 vnic->mc_list, vnic->mc_list_mapping);
2611 vnic->mc_list = NULL;
2612 }
2613
2614 if (vnic->rss_table) {
2615 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2616 vnic->rss_table,
2617 vnic->rss_table_dma_addr);
2618 vnic->rss_table = NULL;
2619 }
2620
2621 vnic->rss_hash_key = NULL;
2622 vnic->flags = 0;
2623 }
2624}
2625
2626static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2627{
2628 int i, rc = 0, size;
2629 struct bnxt_vnic_info *vnic;
2630 struct pci_dev *pdev = bp->pdev;
2631 int max_rings;
2632
2633 for (i = 0; i < bp->nr_vnics; i++) {
2634 vnic = &bp->vnic_info[i];
2635
2636 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2637 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2638
2639 if (mem_size > 0) {
2640 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2641 if (!vnic->uc_list) {
2642 rc = -ENOMEM;
2643 goto out;
2644 }
2645 }
2646 }
2647
2648 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2649 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2650 vnic->mc_list =
2651 dma_alloc_coherent(&pdev->dev,
2652 vnic->mc_list_size,
2653 &vnic->mc_list_mapping,
2654 GFP_KERNEL);
2655 if (!vnic->mc_list) {
2656 rc = -ENOMEM;
2657 goto out;
2658 }
2659 }
2660
2661 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2662 max_rings = bp->rx_nr_rings;
2663 else
2664 max_rings = 1;
2665
2666 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2667 if (!vnic->fw_grp_ids) {
2668 rc = -ENOMEM;
2669 goto out;
2670 }
2671
2672 /* Allocate rss table and hash key */
2673 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2674 &vnic->rss_table_dma_addr,
2675 GFP_KERNEL);
2676 if (!vnic->rss_table) {
2677 rc = -ENOMEM;
2678 goto out;
2679 }
2680
2681 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2682
2683 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2684 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2685 }
2686 return 0;
2687
2688out:
2689 return rc;
2690}
2691
2692static void bnxt_free_hwrm_resources(struct bnxt *bp)
2693{
2694 struct pci_dev *pdev = bp->pdev;
2695
2696 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2697 bp->hwrm_cmd_resp_dma_addr);
2698
2699 bp->hwrm_cmd_resp_addr = NULL;
2700 if (bp->hwrm_dbg_resp_addr) {
2701 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2702 bp->hwrm_dbg_resp_addr,
2703 bp->hwrm_dbg_resp_dma_addr);
2704
2705 bp->hwrm_dbg_resp_addr = NULL;
2706 }
2707}
2708
2709static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2710{
2711 struct pci_dev *pdev = bp->pdev;
2712
2713 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2714 &bp->hwrm_cmd_resp_dma_addr,
2715 GFP_KERNEL);
2716 if (!bp->hwrm_cmd_resp_addr)
2717 return -ENOMEM;
2718 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2719 HWRM_DBG_REG_BUF_SIZE,
2720 &bp->hwrm_dbg_resp_dma_addr,
2721 GFP_KERNEL);
2722 if (!bp->hwrm_dbg_resp_addr)
2723 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2724
2725 return 0;
2726}
2727
2728static void bnxt_free_stats(struct bnxt *bp)
2729{
2730 u32 size, i;
2731 struct pci_dev *pdev = bp->pdev;
2732
3bdf56c4
MC		 2733 if (bp->hw_rx_port_stats) {
2734 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2735 bp->hw_rx_port_stats,
2736 bp->hw_rx_port_stats_map);
2737 bp->hw_rx_port_stats = NULL;
2738 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2739 }
2740
c0c050c5
MC		 2741 if (!bp->bnapi)
2742 return;
2743
2744 size = sizeof(struct ctx_hw_stats);
2745
2746 for (i = 0; i < bp->cp_nr_rings; i++) {
2747 struct bnxt_napi *bnapi = bp->bnapi[i];
2748 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2749
2750 if (cpr->hw_stats) {
2751 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2752 cpr->hw_stats_map);
2753 cpr->hw_stats = NULL;
2754 }
2755 }
2756}
2757
2758static int bnxt_alloc_stats(struct bnxt *bp)
2759{
2760 u32 size, i;
2761 struct pci_dev *pdev = bp->pdev;
2762
2763 size = sizeof(struct ctx_hw_stats);
2764
2765 for (i = 0; i < bp->cp_nr_rings; i++) {
2766 struct bnxt_napi *bnapi = bp->bnapi[i];
2767 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2768
2769 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2770 &cpr->hw_stats_map,
2771 GFP_KERNEL);
2772 if (!cpr->hw_stats)
2773 return -ENOMEM;
2774
2775 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2776 }
3bdf56c4 2777
3e8060fa 2778 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3bdf56c4
MC		 2779 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2780 sizeof(struct tx_port_stats) + 1024;
2781
2782 bp->hw_rx_port_stats =
2783 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2784 &bp->hw_rx_port_stats_map,
2785 GFP_KERNEL);
2786 if (!bp->hw_rx_port_stats)
2787 return -ENOMEM;
2788
2789 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2790 512;
2791 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2792 sizeof(struct rx_port_stats) + 512;
2793 bp->flags |= BNXT_FLAG_PORT_STATS;
2794 }
c0c050c5
MC		 2795 return 0;
2796}
2797
2798static void bnxt_clear_ring_indices(struct bnxt *bp)
2799{
2800 int i;
2801
2802 if (!bp->bnapi)
2803 return;
2804
2805 for (i = 0; i < bp->cp_nr_rings; i++) {
2806 struct bnxt_napi *bnapi = bp->bnapi[i];
2807 struct bnxt_cp_ring_info *cpr;
2808 struct bnxt_rx_ring_info *rxr;
2809 struct bnxt_tx_ring_info *txr;
2810
2811 if (!bnapi)
2812 continue;
2813
2814 cpr = &bnapi->cp_ring;
2815 cpr->cp_raw_cons = 0;
2816
b6ab4b01 2817 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2818 if (txr) {
2819 txr->tx_prod = 0;
2820 txr->tx_cons = 0;
2821 }
c0c050c5 2822
b6ab4b01 2823 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2824 if (rxr) {
2825 rxr->rx_prod = 0;
2826 rxr->rx_agg_prod = 0;
2827 rxr->rx_sw_agg_prod = 0;
376a5b86 2828 rxr->rx_next_cons = 0;
3b2b7d9d 2829 }
c0c050c5
MC		 2830 }
2831}
2832
2833static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2834{
2835#ifdef CONFIG_RFS_ACCEL
2836 int i;
2837
2838 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2839 * safe to delete the hash table.
2840 */
2841 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2842 struct hlist_head *head;
2843 struct hlist_node *tmp;
2844 struct bnxt_ntuple_filter *fltr;
2845
2846 head = &bp->ntp_fltr_hash_tbl[i];
2847 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2848 hlist_del(&fltr->hash);
2849 kfree(fltr);
2850 }
2851 }
2852 if (irq_reinit) {
2853 kfree(bp->ntp_fltr_bmap);
2854 bp->ntp_fltr_bmap = NULL;
2855 }
2856 bp->ntp_fltr_count = 0;
2857#endif
2858}
2859
2860static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2861{
2862#ifdef CONFIG_RFS_ACCEL
2863 int i, rc = 0;
2864
2865 if (!(bp->flags & BNXT_FLAG_RFS))
2866 return 0;
2867
2868 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2869 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2870
2871 bp->ntp_fltr_count = 0;
2872 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2873 GFP_KERNEL);
2874
2875 if (!bp->ntp_fltr_bmap)
2876 rc = -ENOMEM;
2877
2878 return rc;
2879#else
2880 return 0;
2881#endif
2882}
2883
2884static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2885{
2886 bnxt_free_vnic_attributes(bp);
2887 bnxt_free_tx_rings(bp);
2888 bnxt_free_rx_rings(bp);
2889 bnxt_free_cp_rings(bp);
2890 bnxt_free_ntp_fltrs(bp, irq_re_init);
2891 if (irq_re_init) {
2892 bnxt_free_stats(bp);
2893 bnxt_free_ring_grps(bp);
2894 bnxt_free_vnics(bp);
b6ab4b01
MC		 2895 kfree(bp->tx_ring);
2896 bp->tx_ring = NULL;
2897 kfree(bp->rx_ring);
2898 bp->rx_ring = NULL;
c0c050c5
MC		 2899 kfree(bp->bnapi);
2900 bp->bnapi = NULL;
2901 } else {
2902 bnxt_clear_ring_indices(bp);
2903 }
2904}
2905
2906static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2907{
01657bcd 2908 int i, j, rc, size, arr_size;
c0c050c5
MC		 2909 void *bnapi;
2910
2911 if (irq_re_init) {
2912 /* Allocate bnapi mem pointer array and mem block for
2913 * all queues
2914 */
2915 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2916 bp->cp_nr_rings);
2917 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2918 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2919 if (!bnapi)
2920 return -ENOMEM;
2921
2922 bp->bnapi = bnapi;
2923 bnapi += arr_size;
2924 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2925 bp->bnapi[i] = bnapi;
2926 bp->bnapi[i]->index = i;
2927 bp->bnapi[i]->bp = bp;
2928 }
2929
b6ab4b01
MC		 2930 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2931 sizeof(struct bnxt_rx_ring_info),
2932 GFP_KERNEL);
2933 if (!bp->rx_ring)
2934 return -ENOMEM;
2935
2936 for (i = 0; i < bp->rx_nr_rings; i++) {
2937 bp->rx_ring[i].bnapi = bp->bnapi[i];
2938 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2939 }
2940
2941 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2942 sizeof(struct bnxt_tx_ring_info),
2943 GFP_KERNEL);
2944 if (!bp->tx_ring)
2945 return -ENOMEM;
2946
01657bcd
MC		 2947 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2948 j = 0;
2949 else
2950 j = bp->rx_nr_rings;
2951
2952 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2953 bp->tx_ring[i].bnapi = bp->bnapi[j];
2954 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
b6ab4b01
MC		 2955 }
2956
c0c050c5
MC		 2957 rc = bnxt_alloc_stats(bp);
2958 if (rc)
2959 goto alloc_mem_err;
2960
2961 rc = bnxt_alloc_ntp_fltrs(bp);
2962 if (rc)
2963 goto alloc_mem_err;
2964
2965 rc = bnxt_alloc_vnics(bp);
2966 if (rc)
2967 goto alloc_mem_err;
2968 }
2969
2970 bnxt_init_ring_struct(bp);
2971
2972 rc = bnxt_alloc_rx_rings(bp);
2973 if (rc)
2974 goto alloc_mem_err;
2975
2976 rc = bnxt_alloc_tx_rings(bp);
2977 if (rc)
2978 goto alloc_mem_err;
2979
2980 rc = bnxt_alloc_cp_rings(bp);
2981 if (rc)
2982 goto alloc_mem_err;
2983
2984 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2985 BNXT_VNIC_UCAST_FLAG;
2986 rc = bnxt_alloc_vnic_attributes(bp);
2987 if (rc)
2988 goto alloc_mem_err;
2989 return 0;
2990
2991alloc_mem_err:
2992 bnxt_free_mem(bp, true);
2993 return rc;
2994}
2995
2996void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2997 u16 cmpl_ring, u16 target_id)
2998{
a8643e16 2999 struct input *req = request;
c0c050c5 3000
a8643e16
MC		 3001 req->req_type = cpu_to_le16(req_type);
3002 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3003 req->target_id = cpu_to_le16(target_id);
c0c050c5
MC		 3004 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3005}
3006
fbfbc485
MC		 3007static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3008 int timeout, bool silent)
c0c050c5 3009{
a11fa2be 3010 int i, intr_process, rc, tmo_count;
a8643e16 3011 struct input *req = msg;
c0c050c5
MC		 3012 u32 *data = msg;
3013 __le32 *resp_len, *valid;
3014 u16 cp_ring_id, len = 0;
3015 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3016
a8643e16 3017 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
c0c050c5 3018 memset(resp, 0, PAGE_SIZE);
a8643e16 3019 cp_ring_id = le16_to_cpu(req->cmpl_ring);
c0c050c5
MC		 3020 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3021
3022 /* Write request msg to hwrm channel */
3023 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3024
e6ef2699 3025 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
d79979a1
MC		 3026 writel(0, bp->bar0 + i);
3027
c0c050c5
MC		 3028 /* currently supports only one outstanding message */
3029 if (intr_process)
a8643e16 3030 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
c0c050c5
MC		 3031
3032 /* Ring channel doorbell */
3033 writel(1, bp->bar0 + 0x100);
3034
ff4fe81d
MC		 3035 if (!timeout)
3036 timeout = DFLT_HWRM_CMD_TIMEOUT;
3037
c0c050c5 3038 i = 0;
a11fa2be 3039 tmo_count = timeout * 40;
c0c050c5
MC		 3040 if (intr_process) {
3041 /* Wait until hwrm response cmpl interrupt is processed */
3042 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
a11fa2be
MC		 3043 i++ < tmo_count) {
3044 usleep_range(25, 40);
c0c050c5
MC		 3045 }
3046
3047 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3048 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
a8643e16 3049 le16_to_cpu(req->req_type));
c0c050c5
MC		 3050 return -1;
3051 }
3052 } else {
3053 /* Check if response len is updated */
3054 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
a11fa2be 3055 for (i = 0; i < tmo_count; i++) {
c0c050c5
MC		 3056 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3057 HWRM_RESP_LEN_SFT;
3058 if (len)
3059 break;
a11fa2be 3060 usleep_range(25, 40);
c0c050c5
MC		 3061 }
3062
a11fa2be 3063 if (i >= tmo_count) {
c0c050c5 3064 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
a8643e16 3065 timeout, le16_to_cpu(req->req_type),
8578d6c1 3066 le16_to_cpu(req->seq_id), len);
c0c050c5
MC		 3067 return -1;
3068 }
3069
3070 /* Last word of resp contains valid bit */
3071 valid = bp->hwrm_cmd_resp_addr + len - 4;
a11fa2be 3072 for (i = 0; i < 5; i++) {
c0c050c5
MC		 3073 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3074 break;
a11fa2be 3075 udelay(1);
c0c050c5
MC		 3076 }
3077
a11fa2be 3078 if (i >= 5) {
c0c050c5 3079 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
a8643e16
MC		 3080 timeout, le16_to_cpu(req->req_type),
3081 le16_to_cpu(req->seq_id), len, *valid);
c0c050c5
MC		 3082 return -1;
3083 }
3084 }
3085
3086 rc = le16_to_cpu(resp->error_code);
fbfbc485 3087 if (rc && !silent)
c0c050c5
MC		 3088 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3089 le16_to_cpu(resp->req_type),
3090 le16_to_cpu(resp->seq_id), rc);
fbfbc485
MC		 3091 return rc;
3092}
3093
3094int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3095{
3096 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
c0c050c5
MC		 3097}
3098
3099int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3100{
3101 int rc;
3102
3103 mutex_lock(&bp->hwrm_cmd_lock);
3104 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3105 mutex_unlock(&bp->hwrm_cmd_lock);
3106 return rc;
3107}
3108
90e20921
MC		 3109int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3110 int timeout)
3111{
3112 int rc;
3113
3114 mutex_lock(&bp->hwrm_cmd_lock);
3115 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3116 mutex_unlock(&bp->hwrm_cmd_lock);
3117 return rc;
3118}
3119
c0c050c5
MC		 3120static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3121{
3122 struct hwrm_func_drv_rgtr_input req = {0};
3123 int i;
25be8623
MC		 3124 DECLARE_BITMAP(async_events_bmap, 256);
3125 u32 *events = (u32 *)async_events_bmap;
c0c050c5
MC		 3126
3127 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3128
3129 req.enables =
3130 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3131 FUNC_DRV_RGTR_REQ_ENABLES_VER |
3132 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3133
25be8623
MC		 3134 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3135 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3136 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3137
3138 for (i = 0; i < 8; i++)
3139 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3140
11f15ed3 3141 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
c0c050c5
MC		 3142 req.ver_maj = DRV_VER_MAJ;
3143 req.ver_min = DRV_VER_MIN;
3144 req.ver_upd = DRV_VER_UPD;
3145
3146 if (BNXT_PF(bp)) {
de68f5de 3147 DECLARE_BITMAP(vf_req_snif_bmap, 256);
c0c050c5
MC		 3148 u32 *data = (u32 *)vf_req_snif_bmap;
3149
de68f5de 3150 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
c0c050c5
MC		 3151 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3152 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3153
de68f5de
MC		 3154 for (i = 0; i < 8; i++)
3155 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3156
c0c050c5
MC		 3157 req.enables |=
3158 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3159 }
3160
3161 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3162}
3163
be58a0da
JH		 3164static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3165{
3166 struct hwrm_func_drv_unrgtr_input req = {0};
3167
3168 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3169 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3170}
3171
c0c050c5
MC		 3172static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3173{
3174 u32 rc = 0;
3175 struct hwrm_tunnel_dst_port_free_input req = {0};
3176
3177 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3178 req.tunnel_type = tunnel_type;
3179
3180 switch (tunnel_type) {
3181 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3182 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3183 break;
3184 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3185 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3186 break;
3187 default:
3188 break;
3189 }
3190
3191 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3192 if (rc)
3193 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3194 rc);
3195 return rc;
3196}
3197
3198static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3199 u8 tunnel_type)
3200{
3201 u32 rc = 0;
3202 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3203 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3204
3205 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3206
3207 req.tunnel_type = tunnel_type;
3208 req.tunnel_dst_port_val = port;
3209
3210 mutex_lock(&bp->hwrm_cmd_lock);
3211 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3212 if (rc) {
3213 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3214 rc);
3215 goto err_out;
3216 }
3217
57aac71b
CJ		 3218 switch (tunnel_type) {
3219 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
c0c050c5 3220 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3221 break;
3222 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
c0c050c5 3223 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3224 break;
3225 default:
3226 break;
3227 }
3228
c0c050c5
MC		 3229err_out:
3230 mutex_unlock(&bp->hwrm_cmd_lock);
3231 return rc;
3232}
3233
3234static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3235{
3236 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3237 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3238
3239 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 3240 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 3241
3242 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3243 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3244 req.mask = cpu_to_le32(vnic->rx_mask);
3245 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3246}
3247
3248#ifdef CONFIG_RFS_ACCEL
3249static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3250 struct bnxt_ntuple_filter *fltr)
3251{
3252 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3253
3254 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3255 req.ntuple_filter_id = fltr->filter_id;
3256 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3257}
3258
3259#define BNXT_NTP_FLTR_FLAGS \
3260 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3261 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3262 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3263 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3264 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3265 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3266 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3267 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3268 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3269 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3270 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3271 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3272 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 3273 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5
MC		 3274
3275static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3276 struct bnxt_ntuple_filter *fltr)
3277{
3278 int rc = 0;
3279 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3280 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3281 bp->hwrm_cmd_resp_addr;
3282 struct flow_keys *keys = &fltr->fkeys;
3283 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3284
3285 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
a54c4d74 3286 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
c0c050c5
MC		 3287
3288 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3289
3290 req.ethertype = htons(ETH_P_IP);
3291 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 3292 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 3293 req.ip_protocol = keys->basic.ip_proto;
3294
3295 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3296 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3297 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3298 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3299
3300 req.src_port = keys->ports.src;
3301 req.src_port_mask = cpu_to_be16(0xffff);
3302 req.dst_port = keys->ports.dst;
3303 req.dst_port_mask = cpu_to_be16(0xffff);
3304
c193554e 3305 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 3306 mutex_lock(&bp->hwrm_cmd_lock);
3307 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3308 if (!rc)
3309 fltr->filter_id = resp->ntuple_filter_id;
3310 mutex_unlock(&bp->hwrm_cmd_lock);
3311 return rc;
3312}
3313#endif
3314
3315static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3316 u8 *mac_addr)
3317{
3318 u32 rc = 0;
3319 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3320 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3321
3322 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
dc52c6c7
PS		 3323 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3324 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3325 req.flags |=
3326 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 3327 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 3328 req.enables =
3329 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 3330 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 3331 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3332 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3333 req.l2_addr_mask[0] = 0xff;
3334 req.l2_addr_mask[1] = 0xff;
3335 req.l2_addr_mask[2] = 0xff;
3336 req.l2_addr_mask[3] = 0xff;
3337 req.l2_addr_mask[4] = 0xff;
3338 req.l2_addr_mask[5] = 0xff;
3339
3340 mutex_lock(&bp->hwrm_cmd_lock);
3341 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3342 if (!rc)
3343 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3344 resp->l2_filter_id;
3345 mutex_unlock(&bp->hwrm_cmd_lock);
3346 return rc;
3347}
3348
3349static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3350{
3351 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3352 int rc = 0;
3353
3354 /* Any associated ntuple filters will also be cleared by firmware. */
3355 mutex_lock(&bp->hwrm_cmd_lock);
3356 for (i = 0; i < num_of_vnics; i++) {
3357 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3358
3359 for (j = 0; j < vnic->uc_filter_count; j++) {
3360 struct hwrm_cfa_l2_filter_free_input req = {0};
3361
3362 bnxt_hwrm_cmd_hdr_init(bp, &req,
3363 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3364
3365 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3366
3367 rc = _hwrm_send_message(bp, &req, sizeof(req),
3368 HWRM_CMD_TIMEOUT);
3369 }
3370 vnic->uc_filter_count = 0;
3371 }
3372 mutex_unlock(&bp->hwrm_cmd_lock);
3373
3374 return rc;
3375}
3376
3377static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3378{
3379 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3380 struct hwrm_vnic_tpa_cfg_input req = {0};
3381
3382 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3383
3384 if (tpa_flags) {
3385 u16 mss = bp->dev->mtu - 40;
3386 u32 nsegs, n, segs = 0, flags;
3387
3388 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3389 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3390 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3391 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3392 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3393 if (tpa_flags & BNXT_FLAG_GRO)
3394 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3395
3396 req.flags = cpu_to_le32(flags);
3397
3398 req.enables =
3399 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 3400 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3401 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 3402
3403 /* Number of segs are log2 units, and first packet is not
3404 * included as part of this units.
3405 */
2839f28b
MC		 3406 if (mss <= BNXT_RX_PAGE_SIZE) {
3407 n = BNXT_RX_PAGE_SIZE / mss;
c0c050c5
MC		 3408 nsegs = (MAX_SKB_FRAGS - 1) * n;
3409 } else {
2839f28b
MC		 3410 n = mss / BNXT_RX_PAGE_SIZE;
3411 if (mss & (BNXT_RX_PAGE_SIZE - 1))
c0c050c5
MC		 3412 n++;
3413 nsegs = (MAX_SKB_FRAGS - n) / n;
3414 }
3415
3416 segs = ilog2(nsegs);
3417 req.max_agg_segs = cpu_to_le16(segs);
3418 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 3419
3420 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 3421 }
3422 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3423
3424 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3425}
3426
3427static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3428{
3429 u32 i, j, max_rings;
3430 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3431 struct hwrm_vnic_rss_cfg_input req = {0};
3432
94ce9caa 3433 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
c0c050c5
MC		 3434 return 0;
3435
3436 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3437 if (set_rss) {
87da7f79 3438 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
dc52c6c7
PS		 3439 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3440 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3441 max_rings = bp->rx_nr_rings - 1;
3442 else
3443 max_rings = bp->rx_nr_rings;
3444 } else {
c0c050c5 3445 max_rings = 1;
dc52c6c7 3446 }
c0c050c5
MC		 3447
3448 /* Fill the RSS indirection table with ring group ids */
3449 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3450 if (j == max_rings)
3451 j = 0;
3452 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3453 }
3454
3455 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3456 req.hash_key_tbl_addr =
3457 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3458 }
94ce9caa 3459 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
c0c050c5
MC		 3460 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3461}
3462
3463static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3464{
3465 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3466 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3467
3468 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3469 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3470 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3471 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3472 req.enables =
3473 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3474 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3475 /* thresholds not implemented in firmware yet */
3476 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3477 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3478 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3479 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3480}
3481
94ce9caa
PS		 3482static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3483 u16 ctx_idx)
c0c050c5
MC		 3484{
3485 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3486
3487 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3488 req.rss_cos_lb_ctx_id =
94ce9caa 3489 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
c0c050c5
MC		 3490
3491 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
94ce9caa 3492 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
c0c050c5
MC		 3493}
3494
3495static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3496{
94ce9caa 3497 int i, j;
c0c050c5
MC		 3498
3499 for (i = 0; i < bp->nr_vnics; i++) {
3500 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3501
94ce9caa
PS		 3502 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3503 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3504 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3505 }
c0c050c5
MC		 3506 }
3507 bp->rsscos_nr_ctxs = 0;
3508}
3509
94ce9caa 3510static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
c0c050c5
MC		 3511{
3512 int rc;
3513 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3514 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3515 bp->hwrm_cmd_resp_addr;
3516
3517 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3518 -1);
3519
3520 mutex_lock(&bp->hwrm_cmd_lock);
3521 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3522 if (!rc)
94ce9caa 3523 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
c0c050c5
MC		 3524 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3525 mutex_unlock(&bp->hwrm_cmd_lock);
3526
3527 return rc;
3528}
3529
3530static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3531{
b81a90d3 3532 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 3533 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3534 struct hwrm_vnic_cfg_input req = {0};
cf6645f8 3535 u16 def_vlan = 0;
c0c050c5
MC		 3536
3537 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
dc52c6c7
PS		 3538
3539 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
c0c050c5 3540 /* Only RSS support for now TBD: COS & LB */
dc52c6c7
PS		 3541 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3542 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3543 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3544 VNIC_CFG_REQ_ENABLES_MRU);
3545 } else {
3546 req.rss_rule = cpu_to_le16(0xffff);
3547 }
94ce9caa 3548
dc52c6c7
PS		 3549 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3550 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
94ce9caa
PS		 3551 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3552 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3553 } else {
3554 req.cos_rule = cpu_to_le16(0xffff);
3555 }
3556
c0c050c5 3557 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 3558 ring = 0;
c0c050c5 3559 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 3560 ring = vnic_id - 1;
76595193
PS		 3561 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3562 ring = bp->rx_nr_rings - 1;
c0c050c5 3563
b81a90d3 3564 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5
MC		 3565 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3566 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3567
3568 req.lb_rule = cpu_to_le16(0xffff);
3569 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3570 VLAN_HLEN);
3571
cf6645f8
MC		 3572#ifdef CONFIG_BNXT_SRIOV
3573 if (BNXT_VF(bp))
3574 def_vlan = bp->vf.vlan;
3575#endif
3576 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
c0c050c5
MC		 3577 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3578
3579 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3580}
3581
3582static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3583{
3584 u32 rc = 0;
3585
3586 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3587 struct hwrm_vnic_free_input req = {0};
3588
3589 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3590 req.vnic_id =
3591 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3592
3593 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3594 if (rc)
3595 return rc;
3596 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3597 }
3598 return rc;
3599}
3600
3601static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3602{
3603 u16 i;
3604
3605 for (i = 0; i < bp->nr_vnics; i++)
3606 bnxt_hwrm_vnic_free_one(bp, i);
3607}
3608
b81a90d3
MC		 3609static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3610 unsigned int start_rx_ring_idx,
3611 unsigned int nr_rings)
c0c050c5 3612{
b81a90d3
MC		 3613 int rc = 0;
3614 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 3615 struct hwrm_vnic_alloc_input req = {0};
3616 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3617
3618 /* map ring groups to this vnic */
b81a90d3
MC		 3619 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3620 grp_idx = bp->rx_ring[i].bnapi->index;
3621 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 3622 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 3623 j, nr_rings);
c0c050c5
MC		 3624 break;
3625 }
3626 bp->vnic_info[vnic_id].fw_grp_ids[j] =
b81a90d3 3627 bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 3628 }
3629
94ce9caa
PS		 3630 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3631 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 3632 if (vnic_id == 0)
3633 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3634
3635 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3636
3637 mutex_lock(&bp->hwrm_cmd_lock);
3638 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3639 if (!rc)
3640 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3641 mutex_unlock(&bp->hwrm_cmd_lock);
3642 return rc;
3643}
3644
3645static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3646{
3647 u16 i;
3648 u32 rc = 0;
3649
3650 mutex_lock(&bp->hwrm_cmd_lock);
3651 for (i = 0; i < bp->rx_nr_rings; i++) {
3652 struct hwrm_ring_grp_alloc_input req = {0};
3653 struct hwrm_ring_grp_alloc_output *resp =
3654 bp->hwrm_cmd_resp_addr;
b81a90d3 3655 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 3656
3657 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3658
b81a90d3
MC		 3659 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3660 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3661 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3662 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 3663
3664 rc = _hwrm_send_message(bp, &req, sizeof(req),
3665 HWRM_CMD_TIMEOUT);
3666 if (rc)
3667 break;
3668
b81a90d3
MC		 3669 bp->grp_info[grp_idx].fw_grp_id =
3670 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 3671 }
3672 mutex_unlock(&bp->hwrm_cmd_lock);
3673 return rc;
3674}
3675
3676static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3677{
3678 u16 i;
3679 u32 rc = 0;
3680 struct hwrm_ring_grp_free_input req = {0};
3681
3682 if (!bp->grp_info)
3683 return 0;
3684
3685 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3686
3687 mutex_lock(&bp->hwrm_cmd_lock);
3688 for (i = 0; i < bp->cp_nr_rings; i++) {
3689 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3690 continue;
3691 req.ring_group_id =
3692 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3693
3694 rc = _hwrm_send_message(bp, &req, sizeof(req),
3695 HWRM_CMD_TIMEOUT);
3696 if (rc)
3697 break;
3698 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3699 }
3700 mutex_unlock(&bp->hwrm_cmd_lock);
3701 return rc;
3702}
3703
3704static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3705 struct bnxt_ring_struct *ring,
3706 u32 ring_type, u32 map_index,
3707 u32 stats_ctx_id)
3708{
3709 int rc = 0, err = 0;
3710 struct hwrm_ring_alloc_input req = {0};
3711 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3712 u16 ring_id;
3713
3714 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3715
3716 req.enables = 0;
3717 if (ring->nr_pages > 1) {
3718 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3719 /* Page size is in log2 units */
3720 req.page_size = BNXT_PAGE_SHIFT;
3721 req.page_tbl_depth = 1;
3722 } else {
3723 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3724 }
3725 req.fbo = 0;
3726 /* Association of ring index with doorbell index and MSIX number */
3727 req.logical_id = cpu_to_le16(map_index);
3728
3729 switch (ring_type) {
3730 case HWRM_RING_ALLOC_TX:
3731 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3732 /* Association of transmit ring with completion ring */
3733 req.cmpl_ring_id =
3734 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3735 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3736 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3737 req.queue_id = cpu_to_le16(ring->queue_id);
3738 break;
3739 case HWRM_RING_ALLOC_RX:
3740 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3741 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3742 break;
3743 case HWRM_RING_ALLOC_AGG:
3744 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3745 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3746 break;
3747 case HWRM_RING_ALLOC_CMPL:
3748 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3749 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3750 if (bp->flags & BNXT_FLAG_USING_MSIX)
3751 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3752 break;
3753 default:
3754 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3755 ring_type);
3756 return -1;
3757 }
3758
3759 mutex_lock(&bp->hwrm_cmd_lock);
3760 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3761 err = le16_to_cpu(resp->error_code);
3762 ring_id = le16_to_cpu(resp->ring_id);
3763 mutex_unlock(&bp->hwrm_cmd_lock);
3764
3765 if (rc || err) {
3766 switch (ring_type) {
3767 case RING_FREE_REQ_RING_TYPE_CMPL:
3768 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3769 rc, err);
3770 return -1;
3771
3772 case RING_FREE_REQ_RING_TYPE_RX:
3773 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3774 rc, err);
3775 return -1;
3776
3777 case RING_FREE_REQ_RING_TYPE_TX:
3778 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3779 rc, err);
3780 return -1;
3781
3782 default:
3783 netdev_err(bp->dev, "Invalid ring\n");
3784 return -1;
3785 }
3786 }
3787 ring->fw_ring_id = ring_id;
3788 return rc;
3789}
3790
3791static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3792{
3793 int i, rc = 0;
3794
edd0c2cc
MC		 3795 for (i = 0; i < bp->cp_nr_rings; i++) {
3796 struct bnxt_napi *bnapi = bp->bnapi[i];
3797 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3798 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
c0c050c5 3799
33e52d88 3800 cpr->cp_doorbell = bp->bar1 + i * 0x80;
edd0c2cc
MC		 3801 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3802 INVALID_STATS_CTX_ID);
3803 if (rc)
3804 goto err_out;
edd0c2cc
MC		 3805 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3806 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3807 }
3808
edd0c2cc 3809 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3810 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3811 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3812 u32 map_idx = txr->bnapi->index;
3813 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
c0c050c5 3814
b81a90d3
MC		 3815 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3816 map_idx, fw_stats_ctx);
edd0c2cc
MC		 3817 if (rc)
3818 goto err_out;
b81a90d3 3819 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3820 }
3821
edd0c2cc 3822 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3823 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3824 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 3825 u32 map_idx = rxr->bnapi->index;
c0c050c5 3826
b81a90d3
MC		 3827 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3828 map_idx, INVALID_STATS_CTX_ID);
edd0c2cc
MC		 3829 if (rc)
3830 goto err_out;
b81a90d3 3831 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
edd0c2cc 3832 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
b81a90d3 3833 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3834 }
3835
3836 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3837 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3838 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 3839 struct bnxt_ring_struct *ring =
3840 &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3841 u32 grp_idx = rxr->bnapi->index;
3842 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5
MC		 3843
3844 rc = hwrm_ring_alloc_send_msg(bp, ring,
3845 HWRM_RING_ALLOC_AGG,
b81a90d3 3846 map_idx,
c0c050c5
MC		 3847 INVALID_STATS_CTX_ID);
3848 if (rc)
3849 goto err_out;
3850
b81a90d3 3851 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3852 writel(DB_KEY_RX | rxr->rx_agg_prod,
3853 rxr->rx_agg_doorbell);
b81a90d3 3854 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3855 }
3856 }
3857err_out:
3858 return rc;
3859}
3860
3861static int hwrm_ring_free_send_msg(struct bnxt *bp,
3862 struct bnxt_ring_struct *ring,
3863 u32 ring_type, int cmpl_ring_id)
3864{
3865 int rc;
3866 struct hwrm_ring_free_input req = {0};
3867 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3868 u16 error_code;
3869
74608fc9 3870 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 3871 req.ring_type = ring_type;
3872 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3873
3874 mutex_lock(&bp->hwrm_cmd_lock);
3875 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3876 error_code = le16_to_cpu(resp->error_code);
3877 mutex_unlock(&bp->hwrm_cmd_lock);
3878
3879 if (rc || error_code) {
3880 switch (ring_type) {
3881 case RING_FREE_REQ_RING_TYPE_CMPL:
3882 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3883 rc);
3884 return rc;
3885 case RING_FREE_REQ_RING_TYPE_RX:
3886 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3887 rc);
3888 return rc;
3889 case RING_FREE_REQ_RING_TYPE_TX:
3890 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3891 rc);
3892 return rc;
3893 default:
3894 netdev_err(bp->dev, "Invalid ring\n");
3895 return -1;
3896 }
3897 }
3898 return 0;
3899}
3900
edd0c2cc 3901static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 3902{
edd0c2cc 3903 int i;
c0c050c5
MC		 3904
3905 if (!bp->bnapi)
edd0c2cc 3906 return;
c0c050c5 3907
edd0c2cc 3908 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3909 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3910 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3911 u32 grp_idx = txr->bnapi->index;
3912 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3913
3914 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3915 hwrm_ring_free_send_msg(bp, ring,
3916 RING_FREE_REQ_RING_TYPE_TX,
3917 close_path ? cmpl_ring_id :
3918 INVALID_HW_RING_ID);
3919 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 3920 }
3921 }
3922
edd0c2cc 3923 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3924 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3925 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3
MC		 3926 u32 grp_idx = rxr->bnapi->index;
3927 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3928
3929 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3930 hwrm_ring_free_send_msg(bp, ring,
3931 RING_FREE_REQ_RING_TYPE_RX,
3932 close_path ? cmpl_ring_id :
3933 INVALID_HW_RING_ID);
3934 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 3935 bp->grp_info[grp_idx].rx_fw_ring_id =
3936 INVALID_HW_RING_ID;
c0c050c5
MC		 3937 }
3938 }
3939
edd0c2cc 3940 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3941 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3942 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3943 u32 grp_idx = rxr->bnapi->index;
3944 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 3945
3946 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3947 hwrm_ring_free_send_msg(bp, ring,
3948 RING_FREE_REQ_RING_TYPE_RX,
3949 close_path ? cmpl_ring_id :
3950 INVALID_HW_RING_ID);
3951 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 3952 bp->grp_info[grp_idx].agg_fw_ring_id =
3953 INVALID_HW_RING_ID;
c0c050c5
MC		 3954 }
3955 }
3956
edd0c2cc
MC		 3957 for (i = 0; i < bp->cp_nr_rings; i++) {
3958 struct bnxt_napi *bnapi = bp->bnapi[i];
3959 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3960 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3961
3962 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3963 hwrm_ring_free_send_msg(bp, ring,
3964 RING_FREE_REQ_RING_TYPE_CMPL,
3965 INVALID_HW_RING_ID);
3966 ring->fw_ring_id = INVALID_HW_RING_ID;
3967 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 3968 }
3969 }
c0c050c5
MC		 3970}
3971
bb053f52
MC		 3972static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3973 u32 buf_tmrs, u16 flags,
3974 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3975{
3976 req->flags = cpu_to_le16(flags);
3977 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3978 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3979 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3980 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3981 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3982 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3983 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3984 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3985}
3986
c0c050c5
MC		 3987int bnxt_hwrm_set_coal(struct bnxt *bp)
3988{
3989 int i, rc = 0;
dfc9c94a
MC		 3990 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3991 req_tx = {0}, *req;
c0c050c5
MC		 3992 u16 max_buf, max_buf_irq;
3993 u16 buf_tmr, buf_tmr_irq;
3994 u32 flags;
3995
dfc9c94a
MC		 3996 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3997 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3998 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3999 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
c0c050c5 4000
dfb5b894
MC		 4001 /* Each rx completion (2 records) should be DMAed immediately.
4002 * DMA 1/4 of the completion buffers at a time.
4003 */
4004 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
c0c050c5
MC		 4005 /* max_buf must not be zero */
4006 max_buf = clamp_t(u16, max_buf, 1, 63);
dfb5b894
MC		 4007 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4008 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4009 /* buf timer set to 1/4 of interrupt timer */
4010 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4011 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4012 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
c0c050c5
MC		 4013
4014 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4015
4016 /* RING_IDLE generates more IRQs for lower latency. Enable it only
4017 * if coal_ticks is less than 25 us.
4018 */
dfb5b894 4019 if (bp->rx_coal_ticks < 25)
c0c050c5
MC		 4020 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4021
bb053f52 4022 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
dfc9c94a
MC		 4023 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4024
4025 /* max_buf must not be zero */
4026 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4027 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4028 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4029 /* buf timer set to 1/4 of interrupt timer */
4030 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4031 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4032 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4033
4034 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4035 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4036 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
c0c050c5
MC		 4037
4038 mutex_lock(&bp->hwrm_cmd_lock);
4039 for (i = 0; i < bp->cp_nr_rings; i++) {
dfc9c94a 4040 struct bnxt_napi *bnapi = bp->bnapi[i];
c0c050c5 4041
dfc9c94a
MC		 4042 req = &req_rx;
4043 if (!bnapi->rx_ring)
4044 req = &req_tx;
4045 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4046
4047 rc = _hwrm_send_message(bp, req, sizeof(*req),
c0c050c5
MC		 4048 HWRM_CMD_TIMEOUT);
4049 if (rc)
4050 break;
4051 }
4052 mutex_unlock(&bp->hwrm_cmd_lock);
4053 return rc;
4054}
4055
4056static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4057{
4058 int rc = 0, i;
4059 struct hwrm_stat_ctx_free_input req = {0};
4060
4061 if (!bp->bnapi)
4062 return 0;
4063
3e8060fa
PS		 4064 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4065 return 0;
4066
c0c050c5
MC		 4067 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4068
4069 mutex_lock(&bp->hwrm_cmd_lock);
4070 for (i = 0; i < bp->cp_nr_rings; i++) {
4071 struct bnxt_napi *bnapi = bp->bnapi[i];
4072 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4073
4074 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4075 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4076
4077 rc = _hwrm_send_message(bp, &req, sizeof(req),
4078 HWRM_CMD_TIMEOUT);
4079 if (rc)
4080 break;
4081
4082 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4083 }
4084 }
4085 mutex_unlock(&bp->hwrm_cmd_lock);
4086 return rc;
4087}
4088
4089static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4090{
4091 int rc = 0, i;
4092 struct hwrm_stat_ctx_alloc_input req = {0};
4093 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4094
3e8060fa
PS		 4095 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4096 return 0;
4097
c0c050c5
MC		 4098 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4099
51f30785 4100 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
c0c050c5
MC		 4101
4102 mutex_lock(&bp->hwrm_cmd_lock);
4103 for (i = 0; i < bp->cp_nr_rings; i++) {
4104 struct bnxt_napi *bnapi = bp->bnapi[i];
4105 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4106
4107 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4108
4109 rc = _hwrm_send_message(bp, &req, sizeof(req),
4110 HWRM_CMD_TIMEOUT);
4111 if (rc)
4112 break;
4113
4114 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4115
4116 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4117 }
4118 mutex_unlock(&bp->hwrm_cmd_lock);
89aa8445 4119 return rc;
c0c050c5
MC		 4120}
4121
cf6645f8
MC		 4122static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4123{
4124 struct hwrm_func_qcfg_input req = {0};
567b2abe 4125 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
cf6645f8
MC		 4126 int rc;
4127
4128 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4129 req.fid = cpu_to_le16(0xffff);
4130 mutex_lock(&bp->hwrm_cmd_lock);
4131 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4132 if (rc)
4133 goto func_qcfg_exit;
4134
4135#ifdef CONFIG_BNXT_SRIOV
4136 if (BNXT_VF(bp)) {
cf6645f8
MC		 4137 struct bnxt_vf_info *vf = &bp->vf;
4138
4139 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4140 }
4141#endif
567b2abe
SB		 4142 switch (resp->port_partition_type) {
4143 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4144 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4145 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4146 bp->port_partition_type = resp->port_partition_type;
4147 break;
4148 }
cf6645f8
MC		 4149
4150func_qcfg_exit:
4151 mutex_unlock(&bp->hwrm_cmd_lock);
4152 return rc;
4153}
4154
7b08f661 4155static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 4156{
4157 int rc = 0;
4158 struct hwrm_func_qcaps_input req = {0};
4159 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4160
4161 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4162 req.fid = cpu_to_le16(0xffff);
4163
4164 mutex_lock(&bp->hwrm_cmd_lock);
4165 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4166 if (rc)
4167 goto hwrm_func_qcaps_exit;
4168
e4060d30
MC		 4169 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4170 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4171 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4172 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4173
7cc5a20e
MC		 4174 bp->tx_push_thresh = 0;
4175 if (resp->flags &
4176 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4177 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4178
c0c050c5
MC		 4179 if (BNXT_PF(bp)) {
4180 struct bnxt_pf_info *pf = &bp->pf;
4181
4182 pf->fw_fid = le16_to_cpu(resp->fid);
4183 pf->port_id = le16_to_cpu(resp->port_id);
87027db1 4184 bp->dev->dev_port = pf->port_id;
11f15ed3 4185 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
bdd4347b 4186 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
c0c050c5
MC		 4187 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4188 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4189 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
c0c050c5 4190 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4191 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4192 if (!pf->max_hw_ring_grps)
4193 pf->max_hw_ring_grps = pf->max_tx_rings;
c0c050c5
MC		 4194 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4195 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4196 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4197 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4198 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4199 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4200 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4201 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4202 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4203 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4204 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4205 } else {
379a80a1 4206#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 4207 struct bnxt_vf_info *vf = &bp->vf;
4208
4209 vf->fw_fid = le16_to_cpu(resp->fid);
c0c050c5
MC		 4210
4211 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4212 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4213 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4214 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4215 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4216 if (!vf->max_hw_ring_grps)
4217 vf->max_hw_ring_grps = vf->max_tx_rings;
c0c050c5
MC		 4218 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4219 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4220 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7cc5a20e
MC		 4221
4222 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
001154eb
MC		 4223 mutex_unlock(&bp->hwrm_cmd_lock);
4224
4225 if (is_valid_ether_addr(vf->mac_addr)) {
7cc5a20e
MC		 4226 /* overwrite netdev dev_adr with admin VF MAC */
4227 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
001154eb 4228 } else {
7cc5a20e 4229 random_ether_addr(bp->dev->dev_addr);
001154eb
MC		 4230 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4231 }
4232 return rc;
379a80a1 4233#endif
c0c050c5
MC		 4234 }
4235
c0c050c5
MC		 4236hwrm_func_qcaps_exit:
4237 mutex_unlock(&bp->hwrm_cmd_lock);
4238 return rc;
4239}
4240
4241static int bnxt_hwrm_func_reset(struct bnxt *bp)
4242{
4243 struct hwrm_func_reset_input req = {0};
4244
4245 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4246 req.enables = 0;
4247
4248 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4249}
4250
4251static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4252{
4253 int rc = 0;
4254 struct hwrm_queue_qportcfg_input req = {0};
4255 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4256 u8 i, *qptr;
4257
4258 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4259
4260 mutex_lock(&bp->hwrm_cmd_lock);
4261 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4262 if (rc)
4263 goto qportcfg_exit;
4264
4265 if (!resp->max_configurable_queues) {
4266 rc = -EINVAL;
4267 goto qportcfg_exit;
4268 }
4269 bp->max_tc = resp->max_configurable_queues;
87c374de 4270 bp->max_lltc = resp->max_configurable_lossless_queues;
c0c050c5
MC		 4271 if (bp->max_tc > BNXT_MAX_QUEUE)
4272 bp->max_tc = BNXT_MAX_QUEUE;
4273
441cabbb
MC		 4274 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4275 bp->max_tc = 1;
4276
87c374de
MC		 4277 if (bp->max_lltc > bp->max_tc)
4278 bp->max_lltc = bp->max_tc;
4279
c0c050c5
MC		 4280 qptr = &resp->queue_id0;
4281 for (i = 0; i < bp->max_tc; i++) {
4282 bp->q_info[i].queue_id = *qptr++;
4283 bp->q_info[i].queue_profile = *qptr++;
4284 }
4285
4286qportcfg_exit:
4287 mutex_unlock(&bp->hwrm_cmd_lock);
4288 return rc;
4289}
4290
4291static int bnxt_hwrm_ver_get(struct bnxt *bp)
4292{
4293 int rc;
4294 struct hwrm_ver_get_input req = {0};
4295 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4296
e6ef2699 4297 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
c0c050c5
MC		 4298 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4299 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4300 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4301 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4302 mutex_lock(&bp->hwrm_cmd_lock);
4303 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4304 if (rc)
4305 goto hwrm_ver_get_exit;
4306
4307 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4308
11f15ed3
MC		 4309 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4310 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
c193554e
MC		 4311 if (resp->hwrm_intf_maj < 1) {
4312 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
c0c050c5 4313 resp->hwrm_intf_maj, resp->hwrm_intf_min,
c193554e
MC		 4314 resp->hwrm_intf_upd);
4315 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5 4316 }
3ebf6f0a 4317 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
c0c050c5
MC		 4318 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4319 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4320
ff4fe81d
MC		 4321 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4322 if (!bp->hwrm_cmd_timeout)
4323 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4324
e6ef2699
MC		 4325 if (resp->hwrm_intf_maj >= 1)
4326 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4327
659c805c 4328 bp->chip_num = le16_to_cpu(resp->chip_num);
3e8060fa
PS		 4329 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4330 !resp->chip_metal)
4331 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
659c805c 4332
c0c050c5
MC		 4333hwrm_ver_get_exit:
4334 mutex_unlock(&bp->hwrm_cmd_lock);
4335 return rc;
4336}
4337
5ac67d8b
RS		 4338int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4339{
878786d9 4340#if IS_ENABLED(CONFIG_RTC_LIB)
5ac67d8b
RS		 4341 struct hwrm_fw_set_time_input req = {0};
4342 struct rtc_time tm;
4343 struct timeval tv;
4344
4345 if (bp->hwrm_spec_code < 0x10400)
4346 return -EOPNOTSUPP;
4347
4348 do_gettimeofday(&tv);
4349 rtc_time_to_tm(tv.tv_sec, &tm);
4350 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4351 req.year = cpu_to_le16(1900 + tm.tm_year);
4352 req.month = 1 + tm.tm_mon;
4353 req.day = tm.tm_mday;
4354 req.hour = tm.tm_hour;
4355 req.minute = tm.tm_min;
4356 req.second = tm.tm_sec;
4357 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
878786d9
RS		 4358#else
4359 return -EOPNOTSUPP;
4360#endif
5ac67d8b
RS		 4361}
4362
3bdf56c4
MC		 4363static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4364{
4365 int rc;
4366 struct bnxt_pf_info *pf = &bp->pf;
4367 struct hwrm_port_qstats_input req = {0};
4368
4369 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4370 return 0;
4371
4372 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4373 req.port_id = cpu_to_le16(pf->port_id);
4374 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4375 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4376 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4377 return rc;
4378}
4379
c0c050c5
MC		 4380static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4381{
4382 if (bp->vxlan_port_cnt) {
4383 bnxt_hwrm_tunnel_dst_port_free(
4384 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4385 }
4386 bp->vxlan_port_cnt = 0;
4387 if (bp->nge_port_cnt) {
4388 bnxt_hwrm_tunnel_dst_port_free(
4389 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4390 }
4391 bp->nge_port_cnt = 0;
4392}
4393
4394static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4395{
4396 int rc, i;
4397 u32 tpa_flags = 0;
4398
4399 if (set_tpa)
4400 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4401 for (i = 0; i < bp->nr_vnics; i++) {
4402 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4403 if (rc) {
4404 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4405 rc, i);
4406 return rc;
4407 }
4408 }
4409 return 0;
4410}
4411
4412static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4413{
4414 int i;
4415
4416 for (i = 0; i < bp->nr_vnics; i++)
4417 bnxt_hwrm_vnic_set_rss(bp, i, false);
4418}
4419
4420static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4421 bool irq_re_init)
4422{
4423 if (bp->vnic_info) {
4424 bnxt_hwrm_clear_vnic_filter(bp);
4425 /* clear all RSS setting before free vnic ctx */
4426 bnxt_hwrm_clear_vnic_rss(bp);
4427 bnxt_hwrm_vnic_ctx_free(bp);
4428 /* before free the vnic, undo the vnic tpa settings */
4429 if (bp->flags & BNXT_FLAG_TPA)
4430 bnxt_set_tpa(bp, false);
4431 bnxt_hwrm_vnic_free(bp);
4432 }
4433 bnxt_hwrm_ring_free(bp, close_path);
4434 bnxt_hwrm_ring_grp_free(bp);
4435 if (irq_re_init) {
4436 bnxt_hwrm_stat_ctx_free(bp);
4437 bnxt_hwrm_free_tunnel_ports(bp);
4438 }
4439}
4440
4441static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4442{
4443 int rc;
4444
4445 /* allocate context for vnic */
94ce9caa 4446 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
c0c050c5
MC		 4447 if (rc) {
4448 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4449 vnic_id, rc);
4450 goto vnic_setup_err;
4451 }
4452 bp->rsscos_nr_ctxs++;
4453
94ce9caa
PS		 4454 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4455 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4456 if (rc) {
4457 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4458 vnic_id, rc);
4459 goto vnic_setup_err;
4460 }
4461 bp->rsscos_nr_ctxs++;
4462 }
4463
c0c050c5
MC		 4464 /* configure default vnic, ring grp */
4465 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4466 if (rc) {
4467 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4468 vnic_id, rc);
4469 goto vnic_setup_err;
4470 }
4471
4472 /* Enable RSS hashing on vnic */
4473 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4474 if (rc) {
4475 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4476 vnic_id, rc);
4477 goto vnic_setup_err;
4478 }
4479
4480 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4481 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4482 if (rc) {
4483 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4484 vnic_id, rc);
4485 }
4486 }
4487
4488vnic_setup_err:
4489 return rc;
4490}
4491
4492static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4493{
4494#ifdef CONFIG_RFS_ACCEL
4495 int i, rc = 0;
4496
4497 for (i = 0; i < bp->rx_nr_rings; i++) {
4498 u16 vnic_id = i + 1;
4499 u16 ring_id = i;
4500
4501 if (vnic_id >= bp->nr_vnics)
4502 break;
4503
4504 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
b81a90d3 4505 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 4506 if (rc) {
4507 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4508 vnic_id, rc);
4509 break;
4510 }
4511 rc = bnxt_setup_vnic(bp, vnic_id);
4512 if (rc)
4513 break;
4514 }
4515 return rc;
4516#else
4517 return 0;
4518#endif
4519}
4520
17c71ac3
MC		 4521/* Allow PF and VF with default VLAN to be in promiscuous mode */
4522static bool bnxt_promisc_ok(struct bnxt *bp)
4523{
4524#ifdef CONFIG_BNXT_SRIOV
4525 if (BNXT_VF(bp) && !bp->vf.vlan)
4526 return false;
4527#endif
4528 return true;
4529}
4530
dc52c6c7
PS		 4531static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4532{
4533 unsigned int rc = 0;
4534
4535 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4536 if (rc) {
4537 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4538 rc);
4539 return rc;
4540 }
4541
4542 rc = bnxt_hwrm_vnic_cfg(bp, 1);
4543 if (rc) {
4544 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4545 rc);
4546 return rc;
4547 }
4548 return rc;
4549}
4550
b664f008 4551static int bnxt_cfg_rx_mode(struct bnxt *);
7d2837dd 4552static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
b664f008 4553
c0c050c5
MC		 4554static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4555{
7d2837dd 4556 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
c0c050c5 4557 int rc = 0;
76595193 4558 unsigned int rx_nr_rings = bp->rx_nr_rings;
c0c050c5
MC		 4559
4560 if (irq_re_init) {
4561 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4562 if (rc) {
4563 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4564 rc);
4565 goto err_out;
4566 }
4567 }
4568
4569 rc = bnxt_hwrm_ring_alloc(bp);
4570 if (rc) {
4571 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4572 goto err_out;
4573 }
4574
4575 rc = bnxt_hwrm_ring_grp_alloc(bp);
4576 if (rc) {
4577 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4578 goto err_out;
4579 }
4580
76595193
PS		 4581 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4582 rx_nr_rings--;
4583
c0c050c5 4584 /* default vnic 0 */
76595193 4585 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
c0c050c5
MC		 4586 if (rc) {
4587 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4588 goto err_out;
4589 }
4590
4591 rc = bnxt_setup_vnic(bp, 0);
4592 if (rc)
4593 goto err_out;
4594
4595 if (bp->flags & BNXT_FLAG_RFS) {
4596 rc = bnxt_alloc_rfs_vnics(bp);
4597 if (rc)
4598 goto err_out;
4599 }
4600
4601 if (bp->flags & BNXT_FLAG_TPA) {
4602 rc = bnxt_set_tpa(bp, true);
4603 if (rc)
4604 goto err_out;
4605 }
4606
4607 if (BNXT_VF(bp))
4608 bnxt_update_vf_mac(bp);
4609
4610 /* Filter for default vnic 0 */
4611 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4612 if (rc) {
4613 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4614 goto err_out;
4615 }
7d2837dd 4616 vnic->uc_filter_count = 1;
c0c050c5 4617
7d2837dd 4618 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5 4619
17c71ac3 4620 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7d2837dd
MC		 4621 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4622
4623 if (bp->dev->flags & IFF_ALLMULTI) {
4624 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4625 vnic->mc_list_count = 0;
4626 } else {
4627 u32 mask = 0;
4628
4629 bnxt_mc_list_updated(bp, &mask);
4630 vnic->rx_mask |= mask;
4631 }
c0c050c5 4632
b664f008
MC		 4633 rc = bnxt_cfg_rx_mode(bp);
4634 if (rc)
c0c050c5 4635 goto err_out;
c0c050c5
MC		 4636
4637 rc = bnxt_hwrm_set_coal(bp);
4638 if (rc)
4639 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
dc52c6c7
PS		 4640 rc);
4641
4642 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4643 rc = bnxt_setup_nitroa0_vnic(bp);
4644 if (rc)
4645 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
4646 rc);
4647 }
c0c050c5 4648
cf6645f8
MC		 4649 if (BNXT_VF(bp)) {
4650 bnxt_hwrm_func_qcfg(bp);
4651 netdev_update_features(bp->dev);
4652 }
4653
c0c050c5
MC		 4654 return 0;
4655
4656err_out:
4657 bnxt_hwrm_resource_free(bp, 0, true);
4658
4659 return rc;
4660}
4661
4662static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4663{
4664 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4665 return 0;
4666}
4667
4668static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4669{
4670 bnxt_init_rx_rings(bp);
4671 bnxt_init_tx_rings(bp);
4672 bnxt_init_ring_grps(bp, irq_re_init);
4673 bnxt_init_vnics(bp);
4674
4675 return bnxt_init_chip(bp, irq_re_init);
4676}
4677
4678static void bnxt_disable_int(struct bnxt *bp)
4679{
4680 int i;
4681
4682 if (!bp->bnapi)
4683 return;
4684
4685 for (i = 0; i < bp->cp_nr_rings; i++) {
4686 struct bnxt_napi *bnapi = bp->bnapi[i];
4687 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4688
4689 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4690 }
4691}
4692
4693static void bnxt_enable_int(struct bnxt *bp)
4694{
4695 int i;
4696
4697 atomic_set(&bp->intr_sem, 0);
4698 for (i = 0; i < bp->cp_nr_rings; i++) {
4699 struct bnxt_napi *bnapi = bp->bnapi[i];
4700 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4701
4702 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4703 }
4704}
4705
4706static int bnxt_set_real_num_queues(struct bnxt *bp)
4707{
4708 int rc;
4709 struct net_device *dev = bp->dev;
4710
4711 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4712 if (rc)
4713 return rc;
4714
4715 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4716 if (rc)
4717 return rc;
4718
4719#ifdef CONFIG_RFS_ACCEL
45019a18 4720 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 4721 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 4722#endif
4723
4724 return rc;
4725}
4726
6e6c5a57
MC		 4727static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4728 bool shared)
4729{
4730 int _rx = *rx, _tx = *tx;
4731
4732 if (shared) {
4733 *rx = min_t(int, _rx, max);
4734 *tx = min_t(int, _tx, max);
4735 } else {
4736 if (max < 2)
4737 return -ENOMEM;
4738
4739 while (_rx + _tx > max) {
4740 if (_rx > _tx && _rx > 1)
4741 _rx--;
4742 else if (_tx > 1)
4743 _tx--;
4744 }
4745 *rx = _rx;
4746 *tx = _tx;
4747 }
4748 return 0;
4749}
4750
7809592d
MC		 4751static void bnxt_setup_msix(struct bnxt *bp)
4752{
4753 const int len = sizeof(bp->irq_tbl[0].name);
4754 struct net_device *dev = bp->dev;
4755 int tcs, i;
4756
4757 tcs = netdev_get_num_tc(dev);
4758 if (tcs > 1) {
4759 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4760 if (bp->tx_nr_rings_per_tc == 0) {
4761 netdev_reset_tc(dev);
4762 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4763 } else {
4764 int i, off, count;
4765
4766 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4767 for (i = 0; i < tcs; i++) {
4768 count = bp->tx_nr_rings_per_tc;
4769 off = i * count;
4770 netdev_set_tc_queue(dev, i, count, off);
4771 }
4772 }
4773 }
4774
4775 for (i = 0; i < bp->cp_nr_rings; i++) {
4776 char *attr;
4777
4778 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4779 attr = "TxRx";
4780 else if (i < bp->rx_nr_rings)
4781 attr = "rx";
4782 else
4783 attr = "tx";
4784
4785 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
4786 i);
4787 bp->irq_tbl[i].handler = bnxt_msix;
4788 }
4789}
4790
4791static void bnxt_setup_inta(struct bnxt *bp)
4792{
4793 const int len = sizeof(bp->irq_tbl[0].name);
4794
4795 if (netdev_get_num_tc(bp->dev))
4796 netdev_reset_tc(bp->dev);
4797
4798 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
4799 0);
4800 bp->irq_tbl[0].handler = bnxt_inta;
4801}
4802
4803static int bnxt_setup_int_mode(struct bnxt *bp)
4804{
4805 int rc;
4806
4807 if (bp->flags & BNXT_FLAG_USING_MSIX)
4808 bnxt_setup_msix(bp);
4809 else
4810 bnxt_setup_inta(bp);
4811
4812 rc = bnxt_set_real_num_queues(bp);
4813 return rc;
4814}
4815
e4060d30
MC		 4816unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
4817{
4818#if defined(CONFIG_BNXT_SRIOV)
4819 if (BNXT_VF(bp))
4820 return bp->vf.max_stat_ctxs;
4821#endif
4822 return bp->pf.max_stat_ctxs;
4823}
4824
4825unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
4826{
4827#if defined(CONFIG_BNXT_SRIOV)
4828 if (BNXT_VF(bp))
4829 return bp->vf.max_cp_rings;
4830#endif
4831 return bp->pf.max_cp_rings;
4832}
4833
7809592d
MC		 4834static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
4835{
4836#if defined(CONFIG_BNXT_SRIOV)
4837 if (BNXT_VF(bp))
4838 return bp->vf.max_irqs;
4839#endif
4840 return bp->pf.max_irqs;
4841}
4842
33c2657e
MC		 4843void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
4844{
4845#if defined(CONFIG_BNXT_SRIOV)
4846 if (BNXT_VF(bp))
4847 bp->vf.max_irqs = max_irqs;
4848 else
4849#endif
4850 bp->pf.max_irqs = max_irqs;
4851}
4852
7809592d 4853static int bnxt_init_msix(struct bnxt *bp)
c0c050c5 4854{
01657bcd 4855 int i, total_vecs, rc = 0, min = 1;
7809592d 4856 struct msix_entry *msix_ent;
c0c050c5 4857
7809592d 4858 total_vecs = bnxt_get_max_func_irqs(bp);
c0c050c5
MC		 4859 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4860 if (!msix_ent)
4861 return -ENOMEM;
4862
4863 for (i = 0; i < total_vecs; i++) {
4864 msix_ent[i].entry = i;
4865 msix_ent[i].vector = 0;
4866 }
4867
01657bcd
MC		 4868 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4869 min = 2;
4870
4871 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
c0c050c5
MC		 4872 if (total_vecs < 0) {
4873 rc = -ENODEV;
4874 goto msix_setup_exit;
4875 }
4876
4877 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4878 if (bp->irq_tbl) {
7809592d
MC		 4879 for (i = 0; i < total_vecs; i++)
4880 bp->irq_tbl[i].vector = msix_ent[i].vector;
c0c050c5 4881
7809592d 4882 bp->total_irqs = total_vecs;
c0c050c5 4883 /* Trim rings based upon num of vectors allocated */
6e6c5a57 4884 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
01657bcd 4885 total_vecs, min == 1);
6e6c5a57
MC		 4886 if (rc)
4887 goto msix_setup_exit;
4888
c0c050c5 4889 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7809592d
MC		 4890 bp->cp_nr_rings = (min == 1) ?
4891 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
4892 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5 4893
c0c050c5
MC		 4894 } else {
4895 rc = -ENOMEM;
4896 goto msix_setup_exit;
4897 }
4898 bp->flags |= BNXT_FLAG_USING_MSIX;
4899 kfree(msix_ent);
4900 return 0;
4901
4902msix_setup_exit:
7809592d
MC		 4903 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
4904 kfree(bp->irq_tbl);
4905 bp->irq_tbl = NULL;
c0c050c5
MC		 4906 pci_disable_msix(bp->pdev);
4907 kfree(msix_ent);
4908 return rc;
4909}
4910
7809592d 4911static int bnxt_init_inta(struct bnxt *bp)
c0c050c5 4912{
c0c050c5 4913 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7809592d
MC		 4914 if (!bp->irq_tbl)
4915 return -ENOMEM;
4916
4917 bp->total_irqs = 1;
c0c050c5
MC		 4918 bp->rx_nr_rings = 1;
4919 bp->tx_nr_rings = 1;
4920 bp->cp_nr_rings = 1;
4921 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
01657bcd 4922 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5 4923 bp->irq_tbl[0].vector = bp->pdev->irq;
7809592d 4924 return 0;
c0c050c5
MC		 4925}
4926
7809592d 4927static int bnxt_init_int_mode(struct bnxt *bp)
c0c050c5
MC		 4928{
4929 int rc = 0;
4930
4931 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7809592d 4932 rc = bnxt_init_msix(bp);
c0c050c5 4933
1fa72e29 4934 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
c0c050c5 4935 /* fallback to INTA */
7809592d 4936 rc = bnxt_init_inta(bp);
c0c050c5
MC		 4937 }
4938 return rc;
4939}
4940
7809592d
MC		 4941static void bnxt_clear_int_mode(struct bnxt *bp)
4942{
4943 if (bp->flags & BNXT_FLAG_USING_MSIX)
4944 pci_disable_msix(bp->pdev);
4945
4946 kfree(bp->irq_tbl);
4947 bp->irq_tbl = NULL;
4948 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4949}
4950
c0c050c5
MC		 4951static void bnxt_free_irq(struct bnxt *bp)
4952{
4953 struct bnxt_irq *irq;
4954 int i;
4955
4956#ifdef CONFIG_RFS_ACCEL
4957 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4958 bp->dev->rx_cpu_rmap = NULL;
4959#endif
4960 if (!bp->irq_tbl)
4961 return;
4962
4963 for (i = 0; i < bp->cp_nr_rings; i++) {
4964 irq = &bp->irq_tbl[i];
4965 if (irq->requested)
4966 free_irq(irq->vector, bp->bnapi[i]);
4967 irq->requested = 0;
4968 }
c0c050c5
MC		 4969}
4970
4971static int bnxt_request_irq(struct bnxt *bp)
4972{
b81a90d3 4973 int i, j, rc = 0;
c0c050c5
MC		 4974 unsigned long flags = 0;
4975#ifdef CONFIG_RFS_ACCEL
4976 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4977#endif
4978
4979 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4980 flags = IRQF_SHARED;
4981
b81a90d3 4982 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
c0c050c5
MC		 4983 struct bnxt_irq *irq = &bp->irq_tbl[i];
4984#ifdef CONFIG_RFS_ACCEL
b81a90d3 4985 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 4986 rc = irq_cpu_rmap_add(rmap, irq->vector);
4987 if (rc)
4988 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 4989 j);
4990 j++;
c0c050c5
MC		 4991 }
4992#endif
4993 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4994 bp->bnapi[i]);
4995 if (rc)
4996 break;
4997
4998 irq->requested = 1;
4999 }
5000 return rc;
5001}
5002
5003static void bnxt_del_napi(struct bnxt *bp)
5004{
5005 int i;
5006
5007 if (!bp->bnapi)
5008 return;
5009
5010 for (i = 0; i < bp->cp_nr_rings; i++) {
5011 struct bnxt_napi *bnapi = bp->bnapi[i];
5012
5013 napi_hash_del(&bnapi->napi);
5014 netif_napi_del(&bnapi->napi);
5015 }
e5f6f564
ED		 5016 /* We called napi_hash_del() before netif_napi_del(), we need
5017 * to respect an RCU grace period before freeing napi structures.
5018 */
5019 synchronize_net();
c0c050c5
MC		 5020}
5021
5022static void bnxt_init_napi(struct bnxt *bp)
5023{
5024 int i;
10bbdaf5 5025 unsigned int cp_nr_rings = bp->cp_nr_rings;
c0c050c5
MC		 5026 struct bnxt_napi *bnapi;
5027
5028 if (bp->flags & BNXT_FLAG_USING_MSIX) {
10bbdaf5
PS		 5029 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5030 cp_nr_rings--;
5031 for (i = 0; i < cp_nr_rings; i++) {
c0c050c5
MC		 5032 bnapi = bp->bnapi[i];
5033 netif_napi_add(bp->dev, &bnapi->napi,
5034 bnxt_poll, 64);
c0c050c5 5035 }
10bbdaf5
PS		 5036 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5037 bnapi = bp->bnapi[cp_nr_rings];
5038 netif_napi_add(bp->dev, &bnapi->napi,
5039 bnxt_poll_nitroa0, 64);
10bbdaf5 5040 }
c0c050c5
MC		 5041 } else {
5042 bnapi = bp->bnapi[0];
5043 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 5044 }
5045}
5046
5047static void bnxt_disable_napi(struct bnxt *bp)
5048{
5049 int i;
5050
5051 if (!bp->bnapi)
5052 return;
5053
5054 for (i = 0; i < bp->cp_nr_rings; i++) {
5055 napi_disable(&bp->bnapi[i]->napi);
5056 bnxt_disable_poll(bp->bnapi[i]);
5057 }
5058}
5059
5060static void bnxt_enable_napi(struct bnxt *bp)
5061{
5062 int i;
5063
5064 for (i = 0; i < bp->cp_nr_rings; i++) {
fa7e2812 5065 bp->bnapi[i]->in_reset = false;
c0c050c5
MC		 5066 bnxt_enable_poll(bp->bnapi[i]);
5067 napi_enable(&bp->bnapi[i]->napi);
5068 }
5069}
5070
7df4ae9f 5071void bnxt_tx_disable(struct bnxt *bp)
c0c050c5
MC		 5072{
5073 int i;
c0c050c5
MC		 5074 struct bnxt_tx_ring_info *txr;
5075 struct netdev_queue *txq;
5076
b6ab4b01 5077 if (bp->tx_ring) {
c0c050c5 5078 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 5079 txr = &bp->tx_ring[i];
c0c050c5 5080 txq = netdev_get_tx_queue(bp->dev, i);
c0c050c5 5081 txr->dev_state = BNXT_DEV_STATE_CLOSING;
c0c050c5
MC		 5082 }
5083 }
5084 /* Stop all TX queues */
5085 netif_tx_disable(bp->dev);
5086 netif_carrier_off(bp->dev);
5087}
5088
7df4ae9f 5089void bnxt_tx_enable(struct bnxt *bp)
c0c050c5
MC		 5090{
5091 int i;
c0c050c5
MC		 5092 struct bnxt_tx_ring_info *txr;
5093 struct netdev_queue *txq;
5094
5095 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 5096 txr = &bp->tx_ring[i];
c0c050c5
MC		 5097 txq = netdev_get_tx_queue(bp->dev, i);
5098 txr->dev_state = 0;
5099 }
5100 netif_tx_wake_all_queues(bp->dev);
5101 if (bp->link_info.link_up)
5102 netif_carrier_on(bp->dev);
5103}
5104
5105static void bnxt_report_link(struct bnxt *bp)
5106{
5107 if (bp->link_info.link_up) {
5108 const char *duplex;
5109 const char *flow_ctrl;
5110 u16 speed;
5111
5112 netif_carrier_on(bp->dev);
5113 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5114 duplex = "full";
5115 else
5116 duplex = "half";
5117 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5118 flow_ctrl = "ON - receive & transmit";
5119 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5120 flow_ctrl = "ON - transmit";
5121 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5122 flow_ctrl = "ON - receive";
5123 else
5124 flow_ctrl = "none";
5125 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5126 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
5127 speed, duplex, flow_ctrl);
170ce013
MC		 5128 if (bp->flags & BNXT_FLAG_EEE_CAP)
5129 netdev_info(bp->dev, "EEE is %s\n",
5130 bp->eee.eee_active ? "active" :
5131 "not active");
c0c050c5
MC		 5132 } else {
5133 netif_carrier_off(bp->dev);
5134 netdev_err(bp->dev, "NIC Link is Down\n");
5135 }
5136}
5137
170ce013
MC		 5138static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5139{
5140 int rc = 0;
5141 struct hwrm_port_phy_qcaps_input req = {0};
5142 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
93ed8117 5143 struct bnxt_link_info *link_info = &bp->link_info;
170ce013
MC		 5144
5145 if (bp->hwrm_spec_code < 0x10201)
5146 return 0;
5147
5148 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5149
5150 mutex_lock(&bp->hwrm_cmd_lock);
5151 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5152 if (rc)
5153 goto hwrm_phy_qcaps_exit;
5154
5155 if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5156 struct ethtool_eee *eee = &bp->eee;
5157 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5158
5159 bp->flags |= BNXT_FLAG_EEE_CAP;
5160 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5161 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5162 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5163 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5164 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5165 }
93ed8117
MC		 5166 link_info->support_auto_speeds =
5167 le16_to_cpu(resp->supported_speeds_auto_mode);
170ce013
MC		 5168
5169hwrm_phy_qcaps_exit:
5170 mutex_unlock(&bp->hwrm_cmd_lock);
5171 return rc;
5172}
5173
c0c050c5
MC		 5174static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5175{
5176 int rc = 0;
5177 struct bnxt_link_info *link_info = &bp->link_info;
5178 struct hwrm_port_phy_qcfg_input req = {0};
5179 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5180 u8 link_up = link_info->link_up;
286ef9d6 5181 u16 diff;
c0c050c5
MC		 5182
5183 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5184
5185 mutex_lock(&bp->hwrm_cmd_lock);
5186 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5187 if (rc) {
5188 mutex_unlock(&bp->hwrm_cmd_lock);
5189 return rc;
5190 }
5191
5192 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5193 link_info->phy_link_status = resp->link;
5194 link_info->duplex = resp->duplex;
5195 link_info->pause = resp->pause;
5196 link_info->auto_mode = resp->auto_mode;
5197 link_info->auto_pause_setting = resp->auto_pause;
3277360e 5198 link_info->lp_pause = resp->link_partner_adv_pause;
c0c050c5 5199 link_info->force_pause_setting = resp->force_pause;
c193554e 5200 link_info->duplex_setting = resp->duplex;
c0c050c5
MC		 5201 if (link_info->phy_link_status == BNXT_LINK_LINK)
5202 link_info->link_speed = le16_to_cpu(resp->link_speed);
5203 else
5204 link_info->link_speed = 0;
5205 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
c0c050c5
MC		 5206 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5207 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
3277360e
MC		 5208 link_info->lp_auto_link_speeds =
5209 le16_to_cpu(resp->link_partner_adv_speeds);
c0c050c5
MC		 5210 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5211 link_info->phy_ver[0] = resp->phy_maj;
5212 link_info->phy_ver[1] = resp->phy_min;
5213 link_info->phy_ver[2] = resp->phy_bld;
5214 link_info->media_type = resp->media_type;
03efbec0 5215 link_info->phy_type = resp->phy_type;
11f15ed3 5216 link_info->transceiver = resp->xcvr_pkg_type;
170ce013
MC		 5217 link_info->phy_addr = resp->eee_config_phy_addr &
5218 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
42ee18fe 5219 link_info->module_status = resp->module_status;
170ce013
MC		 5220
5221 if (bp->flags & BNXT_FLAG_EEE_CAP) {
5222 struct ethtool_eee *eee = &bp->eee;
5223 u16 fw_speeds;
5224
5225 eee->eee_active = 0;
5226 if (resp->eee_config_phy_addr &
5227 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5228 eee->eee_active = 1;
5229 fw_speeds = le16_to_cpu(
5230 resp->link_partner_adv_eee_link_speed_mask);
5231 eee->lp_advertised =
5232 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5233 }
5234
5235 /* Pull initial EEE config */
5236 if (!chng_link_state) {
5237 if (resp->eee_config_phy_addr &
5238 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5239 eee->eee_enabled = 1;
c0c050c5 5240
170ce013
MC		 5241 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5242 eee->advertised =
5243 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5244
5245 if (resp->eee_config_phy_addr &
5246 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5247 __le32 tmr;
5248
5249 eee->tx_lpi_enabled = 1;
5250 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5251 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5252 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5253 }
5254 }
5255 }
c0c050c5
MC		 5256 /* TODO: need to add more logic to report VF link */
5257 if (chng_link_state) {
5258 if (link_info->phy_link_status == BNXT_LINK_LINK)
5259 link_info->link_up = 1;
5260 else
5261 link_info->link_up = 0;
5262 if (link_up != link_info->link_up)
5263 bnxt_report_link(bp);
5264 } else {
5265 /* alwasy link down if not require to update link state */
5266 link_info->link_up = 0;
5267 }
5268 mutex_unlock(&bp->hwrm_cmd_lock);
286ef9d6
MC		 5269
5270 diff = link_info->support_auto_speeds ^ link_info->advertising;
5271 if ((link_info->support_auto_speeds | diff) !=
5272 link_info->support_auto_speeds) {
5273 /* An advertised speed is no longer supported, so we need to
5274 * update the advertisement settings. See bnxt_reset() for
5275 * comments about the rtnl_lock() sequence below.
5276 */
5277 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5278 rtnl_lock();
5279 link_info->advertising = link_info->support_auto_speeds;
5280 if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
5281 (link_info->autoneg & BNXT_AUTONEG_SPEED))
5282 bnxt_hwrm_set_link_setting(bp, true, false);
5283 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5284 rtnl_unlock();
5285 }
c0c050c5
MC		 5286 return 0;
5287}
5288
10289bec
MC		 5289static void bnxt_get_port_module_status(struct bnxt *bp)
5290{
5291 struct bnxt_link_info *link_info = &bp->link_info;
5292 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5293 u8 module_status;
5294
5295 if (bnxt_update_link(bp, true))
5296 return;
5297
5298 module_status = link_info->module_status;
5299 switch (module_status) {
5300 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5301 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5302 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5303 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5304 bp->pf.port_id);
5305 if (bp->hwrm_spec_code >= 0x10201) {
5306 netdev_warn(bp->dev, "Module part number %s\n",
5307 resp->phy_vendor_partnumber);
5308 }
5309 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5310 netdev_warn(bp->dev, "TX is disabled\n");
5311 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5312 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5313 }
5314}
5315
c0c050c5
MC		 5316static void
5317bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5318{
5319 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
c9ee9516
MC		 5320 if (bp->hwrm_spec_code >= 0x10201)
5321 req->auto_pause =
5322 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
c0c050c5
MC		 5323 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5324 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5325 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
49b5c7a1 5326 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
c0c050c5
MC		 5327 req->enables |=
5328 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5329 } else {
5330 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5331 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5332 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5333 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5334 req->enables |=
5335 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
c9ee9516
MC		 5336 if (bp->hwrm_spec_code >= 0x10201) {
5337 req->auto_pause = req->force_pause;
5338 req->enables |= cpu_to_le32(
5339 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5340 }
c0c050c5
MC		 5341 }
5342}
5343
5344static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5345 struct hwrm_port_phy_cfg_input *req)
5346{
5347 u8 autoneg = bp->link_info.autoneg;
5348 u16 fw_link_speed = bp->link_info.req_link_speed;
5349 u32 advertising = bp->link_info.advertising;
5350
5351 if (autoneg & BNXT_AUTONEG_SPEED) {
5352 req->auto_mode |=
11f15ed3 5353 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
c0c050c5
MC		 5354
5355 req->enables |= cpu_to_le32(
5356 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5357 req->auto_link_speed_mask = cpu_to_le16(advertising);
5358
5359 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5360 req->flags |=
5361 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5362 } else {
5363 req->force_link_speed = cpu_to_le16(fw_link_speed);
5364 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5365 }
5366
c0c050c5
MC		 5367 /* tell chimp that the setting takes effect immediately */
5368 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5369}
5370
5371int bnxt_hwrm_set_pause(struct bnxt *bp)
5372{
5373 struct hwrm_port_phy_cfg_input req = {0};
5374 int rc;
5375
5376 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5377 bnxt_hwrm_set_pause_common(bp, &req);
5378
5379 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5380 bp->link_info.force_link_chng)
5381 bnxt_hwrm_set_link_common(bp, &req);
5382
5383 mutex_lock(&bp->hwrm_cmd_lock);
5384 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5385 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5386 /* since changing of pause setting doesn't trigger any link
5387 * change event, the driver needs to update the current pause
5388 * result upon successfully return of the phy_cfg command
5389 */
5390 bp->link_info.pause =
5391 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5392 bp->link_info.auto_pause_setting = 0;
5393 if (!bp->link_info.force_link_chng)
5394 bnxt_report_link(bp);
5395 }
5396 bp->link_info.force_link_chng = false;
5397 mutex_unlock(&bp->hwrm_cmd_lock);
5398 return rc;
5399}
5400
939f7f0c
MC		 5401static void bnxt_hwrm_set_eee(struct bnxt *bp,
5402 struct hwrm_port_phy_cfg_input *req)
5403{
5404 struct ethtool_eee *eee = &bp->eee;
5405
5406 if (eee->eee_enabled) {
5407 u16 eee_speeds;
5408 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5409
5410 if (eee->tx_lpi_enabled)
5411 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5412 else
5413 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5414
5415 req->flags |= cpu_to_le32(flags);
5416 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5417 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5418 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5419 } else {
5420 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5421 }
5422}
5423
5424int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
c0c050c5
MC		 5425{
5426 struct hwrm_port_phy_cfg_input req = {0};
5427
5428 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5429 if (set_pause)
5430 bnxt_hwrm_set_pause_common(bp, &req);
5431
5432 bnxt_hwrm_set_link_common(bp, &req);
939f7f0c
MC		 5433
5434 if (set_eee)
5435 bnxt_hwrm_set_eee(bp, &req);
c0c050c5
MC		 5436 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5437}
5438
33f7d55f
MC		 5439static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5440{
5441 struct hwrm_port_phy_cfg_input req = {0};
5442
567b2abe 5443 if (!BNXT_SINGLE_PF(bp))
33f7d55f
MC		 5444 return 0;
5445
5446 if (pci_num_vf(bp->pdev))
5447 return 0;
5448
5449 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
16d663a6 5450 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
33f7d55f
MC		 5451 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5452}
5453
939f7f0c
MC		 5454static bool bnxt_eee_config_ok(struct bnxt *bp)
5455{
5456 struct ethtool_eee *eee = &bp->eee;
5457 struct bnxt_link_info *link_info = &bp->link_info;
5458
5459 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5460 return true;
5461
5462 if (eee->eee_enabled) {
5463 u32 advertising =
5464 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5465
5466 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5467 eee->eee_enabled = 0;
5468 return false;
5469 }
5470 if (eee->advertised & ~advertising) {
5471 eee->advertised = advertising & eee->supported;
5472 return false;
5473 }
5474 }
5475 return true;
5476}
5477
c0c050c5
MC		 5478static int bnxt_update_phy_setting(struct bnxt *bp)
5479{
5480 int rc;
5481 bool update_link = false;
5482 bool update_pause = false;
939f7f0c 5483 bool update_eee = false;
c0c050c5
MC		 5484 struct bnxt_link_info *link_info = &bp->link_info;
5485
5486 rc = bnxt_update_link(bp, true);
5487 if (rc) {
5488 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5489 rc);
5490 return rc;
5491 }
5492 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
c9ee9516
MC		 5493 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5494 link_info->req_flow_ctrl)
c0c050c5
MC		 5495 update_pause = true;
5496 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5497 link_info->force_pause_setting != link_info->req_flow_ctrl)
5498 update_pause = true;
c0c050c5
MC		 5499 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5500 if (BNXT_AUTO_MODE(link_info->auto_mode))
5501 update_link = true;
5502 if (link_info->req_link_speed != link_info->force_link_speed)
5503 update_link = true;
de73018f
MC		 5504 if (link_info->req_duplex != link_info->duplex_setting)
5505 update_link = true;
c0c050c5
MC		 5506 } else {
5507 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5508 update_link = true;
5509 if (link_info->advertising != link_info->auto_link_speeds)
5510 update_link = true;
c0c050c5
MC		 5511 }
5512
16d663a6
MC		 5513 /* The last close may have shutdown the link, so need to call
5514 * PHY_CFG to bring it back up.
5515 */
5516 if (!netif_carrier_ok(bp->dev))
5517 update_link = true;
5518
939f7f0c
MC		 5519 if (!bnxt_eee_config_ok(bp))
5520 update_eee = true;
5521
c0c050c5 5522 if (update_link)
939f7f0c 5523 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
c0c050c5
MC		 5524 else if (update_pause)
5525 rc = bnxt_hwrm_set_pause(bp);
5526 if (rc) {
5527 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5528 rc);
5529 return rc;
5530 }
5531
5532 return rc;
5533}
5534
11809490
JH		 5535/* Common routine to pre-map certain register block to different GRC window.
5536 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5537 * in PF and 3 windows in VF that can be customized to map in different
5538 * register blocks.
5539 */
5540static void bnxt_preset_reg_win(struct bnxt *bp)
5541{
5542 if (BNXT_PF(bp)) {
5543 /* CAG registers map to GRC window #4 */
5544 writel(BNXT_CAG_REG_BASE,
5545 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5546 }
5547}
5548
c0c050c5
MC		 5549static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5550{
5551 int rc = 0;
5552
11809490 5553 bnxt_preset_reg_win(bp);
c0c050c5
MC		 5554 netif_carrier_off(bp->dev);
5555 if (irq_re_init) {
5556 rc = bnxt_setup_int_mode(bp);
5557 if (rc) {
5558 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5559 rc);
5560 return rc;
5561 }
5562 }
5563 if ((bp->flags & BNXT_FLAG_RFS) &&
5564 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5565 /* disable RFS if falling back to INTA */
5566 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5567 bp->flags &= ~BNXT_FLAG_RFS;
5568 }
5569
5570 rc = bnxt_alloc_mem(bp, irq_re_init);
5571 if (rc) {
5572 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5573 goto open_err_free_mem;
5574 }
5575
5576 if (irq_re_init) {
5577 bnxt_init_napi(bp);
5578 rc = bnxt_request_irq(bp);
5579 if (rc) {
5580 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5581 goto open_err;
5582 }
5583 }
5584
5585 bnxt_enable_napi(bp);
5586
5587 rc = bnxt_init_nic(bp, irq_re_init);
5588 if (rc) {
5589 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5590 goto open_err;
5591 }
5592
5593 if (link_re_init) {
5594 rc = bnxt_update_phy_setting(bp);
5595 if (rc)
ba41d46f 5596 netdev_warn(bp->dev, "failed to update phy settings\n");
c0c050c5
MC		 5597 }
5598
7cdd5fc3 5599 if (irq_re_init)
ad51b8e9 5600 udp_tunnel_get_rx_info(bp->dev);
c0c050c5 5601
caefe526 5602 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 5603 bnxt_enable_int(bp);
5604 /* Enable TX queues */
5605 bnxt_tx_enable(bp);
5606 mod_timer(&bp->timer, jiffies + bp->current_interval);
10289bec
MC		 5607 /* Poll link status and check for SFP+ module status */
5608 bnxt_get_port_module_status(bp);
c0c050c5
MC		 5609
5610 return 0;
5611
5612open_err:
5613 bnxt_disable_napi(bp);
5614 bnxt_del_napi(bp);
5615
5616open_err_free_mem:
5617 bnxt_free_skbs(bp);
5618 bnxt_free_irq(bp);
5619 bnxt_free_mem(bp, true);
5620 return rc;
5621}
5622
5623/* rtnl_lock held */
5624int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5625{
5626 int rc = 0;
5627
5628 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5629 if (rc) {
5630 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5631 dev_close(bp->dev);
5632 }
5633 return rc;
5634}
5635
5636static int bnxt_open(struct net_device *dev)
5637{
5638 struct bnxt *bp = netdev_priv(dev);
c0c050c5 5639
c0c050c5
MC		 5640 return __bnxt_open_nic(bp, true, true);
5641}
5642
5643static void bnxt_disable_int_sync(struct bnxt *bp)
5644{
5645 int i;
5646
5647 atomic_inc(&bp->intr_sem);
5648 if (!netif_running(bp->dev))
5649 return;
5650
5651 bnxt_disable_int(bp);
5652 for (i = 0; i < bp->cp_nr_rings; i++)
5653 synchronize_irq(bp->irq_tbl[i].vector);
5654}
5655
5656int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5657{
5658 int rc = 0;
5659
5660#ifdef CONFIG_BNXT_SRIOV
5661 if (bp->sriov_cfg) {
5662 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5663 !bp->sriov_cfg,
5664 BNXT_SRIOV_CFG_WAIT_TMO);
5665 if (rc)
5666 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5667 }
5668#endif
5669 /* Change device state to avoid TX queue wake up's */
5670 bnxt_tx_disable(bp);
5671
caefe526 5672 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec
MC		 5673 smp_mb__after_atomic();
5674 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5675 msleep(20);
c0c050c5
MC		 5676
5677 /* Flush rings before disabling interrupts */
5678 bnxt_shutdown_nic(bp, irq_re_init);
5679
5680 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5681
5682 bnxt_disable_napi(bp);
5683 bnxt_disable_int_sync(bp);
5684 del_timer_sync(&bp->timer);
5685 bnxt_free_skbs(bp);
5686
5687 if (irq_re_init) {
5688 bnxt_free_irq(bp);
5689 bnxt_del_napi(bp);
5690 }
5691 bnxt_free_mem(bp, irq_re_init);
5692 return rc;
5693}
5694
5695static int bnxt_close(struct net_device *dev)
5696{
5697 struct bnxt *bp = netdev_priv(dev);
5698
5699 bnxt_close_nic(bp, true, true);
33f7d55f 5700 bnxt_hwrm_shutdown_link(bp);
c0c050c5
MC		 5701 return 0;
5702}
5703
5704/* rtnl_lock held */
5705static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5706{
5707 switch (cmd) {
5708 case SIOCGMIIPHY:
5709 /* fallthru */
5710 case SIOCGMIIREG: {
5711 if (!netif_running(dev))
5712 return -EAGAIN;
5713
5714 return 0;
5715 }
5716
5717 case SIOCSMIIREG:
5718 if (!netif_running(dev))
5719 return -EAGAIN;
5720
5721 return 0;
5722
5723 default:
5724 /* do nothing */
5725 break;
5726 }
5727 return -EOPNOTSUPP;
5728}
5729
5730static struct rtnl_link_stats64 *
5731bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5732{
5733 u32 i;
5734 struct bnxt *bp = netdev_priv(dev);
5735
5736 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5737
5738 if (!bp->bnapi)
5739 return stats;
5740
5741 /* TODO check if we need to synchronize with bnxt_close path */
5742 for (i = 0; i < bp->cp_nr_rings; i++) {
5743 struct bnxt_napi *bnapi = bp->bnapi[i];
5744 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5745 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
5746
5747 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
5748 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
5749 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
5750
5751 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
5752 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
5753 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
5754
5755 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
5756 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
5757 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
5758
5759 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
5760 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
5761 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
5762
5763 stats->rx_missed_errors +=
5764 le64_to_cpu(hw_stats->rx_discard_pkts);
5765
5766 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
5767
c0c050c5
MC		 5768 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
5769 }
5770
9947f83f
MC		 5771 if (bp->flags & BNXT_FLAG_PORT_STATS) {
5772 struct rx_port_stats *rx = bp->hw_rx_port_stats;
5773 struct tx_port_stats *tx = bp->hw_tx_port_stats;
5774
5775 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
5776 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
5777 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
5778 le64_to_cpu(rx->rx_ovrsz_frames) +
5779 le64_to_cpu(rx->rx_runt_frames);
5780 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
5781 le64_to_cpu(rx->rx_jbr_frames);
5782 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
5783 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
5784 stats->tx_errors = le64_to_cpu(tx->tx_err);
5785 }
5786
c0c050c5
MC		 5787 return stats;
5788}
5789
5790static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
5791{
5792 struct net_device *dev = bp->dev;
5793 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5794 struct netdev_hw_addr *ha;
5795 u8 *haddr;
5796 int mc_count = 0;
5797 bool update = false;
5798 int off = 0;
5799
5800 netdev_for_each_mc_addr(ha, dev) {
5801 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5802 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5803 vnic->mc_list_count = 0;
5804 return false;
5805 }
5806 haddr = ha->addr;
5807 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5808 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5809 update = true;
5810 }
5811 off += ETH_ALEN;
5812 mc_count++;
5813 }
5814 if (mc_count)
5815 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5816
5817 if (mc_count != vnic->mc_list_count) {
5818 vnic->mc_list_count = mc_count;
5819 update = true;
5820 }
5821 return update;
5822}
5823
5824static bool bnxt_uc_list_updated(struct bnxt *bp)
5825{
5826 struct net_device *dev = bp->dev;
5827 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5828 struct netdev_hw_addr *ha;
5829 int off = 0;
5830
5831 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5832 return true;
5833
5834 netdev_for_each_uc_addr(ha, dev) {
5835 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5836 return true;
5837
5838 off += ETH_ALEN;
5839 }
5840 return false;
5841}
5842
5843static void bnxt_set_rx_mode(struct net_device *dev)
5844{
5845 struct bnxt *bp = netdev_priv(dev);
5846 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5847 u32 mask = vnic->rx_mask;
5848 bool mc_update = false;
5849 bool uc_update;
5850
5851 if (!netif_running(dev))
5852 return;
5853
5854 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5855 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5856 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5857
17c71ac3 5858 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
c0c050c5
MC		 5859 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5860
5861 uc_update = bnxt_uc_list_updated(bp);
5862
5863 if (dev->flags & IFF_ALLMULTI) {
5864 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5865 vnic->mc_list_count = 0;
5866 } else {
5867 mc_update = bnxt_mc_list_updated(bp, &mask);
5868 }
5869
5870 if (mask != vnic->rx_mask || uc_update || mc_update) {
5871 vnic->rx_mask = mask;
5872
5873 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5874 schedule_work(&bp->sp_task);
5875 }
5876}
5877
b664f008 5878static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 5879{
5880 struct net_device *dev = bp->dev;
5881 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5882 struct netdev_hw_addr *ha;
5883 int i, off = 0, rc;
5884 bool uc_update;
5885
5886 netif_addr_lock_bh(dev);
5887 uc_update = bnxt_uc_list_updated(bp);
5888 netif_addr_unlock_bh(dev);
5889
5890 if (!uc_update)
5891 goto skip_uc;
5892
5893 mutex_lock(&bp->hwrm_cmd_lock);
5894 for (i = 1; i < vnic->uc_filter_count; i++) {
5895 struct hwrm_cfa_l2_filter_free_input req = {0};
5896
5897 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5898 -1);
5899
5900 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5901
5902 rc = _hwrm_send_message(bp, &req, sizeof(req),
5903 HWRM_CMD_TIMEOUT);
5904 }
5905 mutex_unlock(&bp->hwrm_cmd_lock);
5906
5907 vnic->uc_filter_count = 1;
5908
5909 netif_addr_lock_bh(dev);
5910 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5911 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5912 } else {
5913 netdev_for_each_uc_addr(ha, dev) {
5914 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5915 off += ETH_ALEN;
5916 vnic->uc_filter_count++;
5917 }
5918 }
5919 netif_addr_unlock_bh(dev);
5920
5921 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5922 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5923 if (rc) {
5924 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5925 rc);
5926 vnic->uc_filter_count = i;
b664f008 5927 return rc;
c0c050c5
MC		 5928 }
5929 }
5930
5931skip_uc:
5932 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5933 if (rc)
5934 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5935 rc);
b664f008
MC		 5936
5937 return rc;
c0c050c5
MC		 5938}
5939
2bcfa6f6
MC		 5940static bool bnxt_rfs_capable(struct bnxt *bp)
5941{
5942#ifdef CONFIG_RFS_ACCEL
5943 struct bnxt_pf_info *pf = &bp->pf;
5944 int vnics;
5945
5946 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5947 return false;
5948
5949 vnics = 1 + bp->rx_nr_rings;
a2304909
VV		 5950 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics) {
5951 netdev_warn(bp->dev,
5952 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
5953 min(pf->max_rsscos_ctxs - 1, pf->max_vnics - 1));
2bcfa6f6 5954 return false;
a2304909 5955 }
2bcfa6f6
MC		 5956
5957 return true;
5958#else
5959 return false;
5960#endif
5961}
5962
c0c050c5
MC		 5963static netdev_features_t bnxt_fix_features(struct net_device *dev,
5964 netdev_features_t features)
5965{
2bcfa6f6
MC		 5966 struct bnxt *bp = netdev_priv(dev);
5967
a2304909 5968 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
2bcfa6f6 5969 features &= ~NETIF_F_NTUPLE;
5a9f6b23
MC		 5970
5971 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
5972 * turned on or off together.
5973 */
5974 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
5975 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
5976 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
5977 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5978 NETIF_F_HW_VLAN_STAG_RX);
5979 else
5980 features |= NETIF_F_HW_VLAN_CTAG_RX |
5981 NETIF_F_HW_VLAN_STAG_RX;
5982 }
cf6645f8
MC		 5983#ifdef CONFIG_BNXT_SRIOV
5984 if (BNXT_VF(bp)) {
5985 if (bp->vf.vlan) {
5986 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5987 NETIF_F_HW_VLAN_STAG_RX);
5988 }
5989 }
5990#endif
c0c050c5
MC		 5991 return features;
5992}
5993
5994static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5995{
5996 struct bnxt *bp = netdev_priv(dev);
5997 u32 flags = bp->flags;
5998 u32 changes;
5999 int rc = 0;
6000 bool re_init = false;
6001 bool update_tpa = false;
6002
6003 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
3e8060fa 6004 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
c0c050c5
MC		 6005 flags |= BNXT_FLAG_GRO;
6006 if (features & NETIF_F_LRO)
6007 flags |= BNXT_FLAG_LRO;
6008
6009 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6010 flags |= BNXT_FLAG_STRIP_VLAN;
6011
6012 if (features & NETIF_F_NTUPLE)
6013 flags |= BNXT_FLAG_RFS;
6014
6015 changes = flags ^ bp->flags;
6016 if (changes & BNXT_FLAG_TPA) {
6017 update_tpa = true;
6018 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6019 (flags & BNXT_FLAG_TPA) == 0)
6020 re_init = true;
6021 }
6022
6023 if (changes & ~BNXT_FLAG_TPA)
6024 re_init = true;
6025
6026 if (flags != bp->flags) {
6027 u32 old_flags = bp->flags;
6028
6029 bp->flags = flags;
6030
2bcfa6f6 6031 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 6032 if (update_tpa)
6033 bnxt_set_ring_params(bp);
6034 return rc;
6035 }
6036
6037 if (re_init) {
6038 bnxt_close_nic(bp, false, false);
6039 if (update_tpa)
6040 bnxt_set_ring_params(bp);
6041
6042 return bnxt_open_nic(bp, false, false);
6043 }
6044 if (update_tpa) {
6045 rc = bnxt_set_tpa(bp,
6046 (flags & BNXT_FLAG_TPA) ?
6047 true : false);
6048 if (rc)
6049 bp->flags = old_flags;
6050 }
6051 }
6052 return rc;
6053}
6054
9f554590
MC		 6055static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6056{
b6ab4b01 6057 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 6058 int i = bnapi->index;
6059
3b2b7d9d
MC		 6060 if (!txr)
6061 return;
6062
9f554590
MC		 6063 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6064 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6065 txr->tx_cons);
6066}
6067
6068static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6069{
b6ab4b01 6070 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 6071 int i = bnapi->index;
6072
3b2b7d9d
MC		 6073 if (!rxr)
6074 return;
6075
9f554590
MC		 6076 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6077 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6078 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6079 rxr->rx_sw_agg_prod);
6080}
6081
6082static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6083{
6084 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6085 int i = bnapi->index;
6086
6087 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6088 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6089}
6090
c0c050c5
MC		 6091static void bnxt_dbg_dump_states(struct bnxt *bp)
6092{
6093 int i;
6094 struct bnxt_napi *bnapi;
c0c050c5
MC		 6095
6096 for (i = 0; i < bp->cp_nr_rings; i++) {
6097 bnapi = bp->bnapi[i];
c0c050c5 6098 if (netif_msg_drv(bp)) {
9f554590
MC		 6099 bnxt_dump_tx_sw_state(bnapi);
6100 bnxt_dump_rx_sw_state(bnapi);
6101 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 6102 }
6103 }
6104}
6105
6988bd92 6106static void bnxt_reset_task(struct bnxt *bp, bool silent)
c0c050c5 6107{
6988bd92
MC		 6108 if (!silent)
6109 bnxt_dbg_dump_states(bp);
028de140
MC		 6110 if (netif_running(bp->dev)) {
6111 bnxt_close_nic(bp, false, false);
6112 bnxt_open_nic(bp, false, false);
6113 }
c0c050c5
MC		 6114}
6115
6116static void bnxt_tx_timeout(struct net_device *dev)
6117{
6118 struct bnxt *bp = netdev_priv(dev);
6119
6120 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
6121 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6122 schedule_work(&bp->sp_task);
6123}
6124
6125#ifdef CONFIG_NET_POLL_CONTROLLER
6126static void bnxt_poll_controller(struct net_device *dev)
6127{
6128 struct bnxt *bp = netdev_priv(dev);
6129 int i;
6130
6131 for (i = 0; i < bp->cp_nr_rings; i++) {
6132 struct bnxt_irq *irq = &bp->irq_tbl[i];
6133
6134 disable_irq(irq->vector);
6135 irq->handler(irq->vector, bp->bnapi[i]);
6136 enable_irq(irq->vector);
6137 }
6138}
6139#endif
6140
6141static void bnxt_timer(unsigned long data)
6142{
6143 struct bnxt *bp = (struct bnxt *)data;
6144 struct net_device *dev = bp->dev;
6145
6146 if (!netif_running(dev))
6147 return;
6148
6149 if (atomic_read(&bp->intr_sem) != 0)
6150 goto bnxt_restart_timer;
6151
3bdf56c4
MC		 6152 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6153 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6154 schedule_work(&bp->sp_task);
6155 }
c0c050c5
MC		 6156bnxt_restart_timer:
6157 mod_timer(&bp->timer, jiffies + bp->current_interval);
6158}
6159
6988bd92
MC		 6160/* Only called from bnxt_sp_task() */
6161static void bnxt_reset(struct bnxt *bp, bool silent)
6162{
6163 /* bnxt_reset_task() calls bnxt_close_nic() which waits
6164 * for BNXT_STATE_IN_SP_TASK to clear.
6165 * If there is a parallel dev_close(), bnxt_close() may be holding
6166 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
6167 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6168 */
6169 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6170 rtnl_lock();
6171 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6172 bnxt_reset_task(bp, silent);
6173 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6174 rtnl_unlock();
6175}
6176
c0c050c5
MC		 6177static void bnxt_cfg_ntp_filters(struct bnxt *);
6178
6179static void bnxt_sp_task(struct work_struct *work)
6180{
6181 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
6182 int rc;
6183
4cebdcec
MC		 6184 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6185 smp_mb__after_atomic();
6186 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6187 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 6188 return;
4cebdcec 6189 }
c0c050c5
MC		 6190
6191 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6192 bnxt_cfg_rx_mode(bp);
6193
6194 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6195 bnxt_cfg_ntp_filters(bp);
6196 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
286ef9d6
MC		 6197 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
6198 &bp->sp_event))
6199 bnxt_hwrm_phy_qcaps(bp);
6200
c0c050c5
MC		 6201 rc = bnxt_update_link(bp, true);
6202 if (rc)
6203 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6204 rc);
6205 }
6206 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6207 bnxt_hwrm_exec_fwd_req(bp);
6208 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6209 bnxt_hwrm_tunnel_dst_port_alloc(
6210 bp, bp->vxlan_port,
6211 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6212 }
6213 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6214 bnxt_hwrm_tunnel_dst_port_free(
6215 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6216 }
7cdd5fc3
AD		 6217 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6218 bnxt_hwrm_tunnel_dst_port_alloc(
6219 bp, bp->nge_port,
6220 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6221 }
6222 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6223 bnxt_hwrm_tunnel_dst_port_free(
6224 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6225 }
6988bd92
MC		 6226 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6227 bnxt_reset(bp, false);
4cebdcec 6228
fc0f1929
MC		 6229 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6230 bnxt_reset(bp, true);
6231
4bb13abf 6232 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event))
10289bec 6233 bnxt_get_port_module_status(bp);
4bb13abf 6234
3bdf56c4
MC		 6235 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6236 bnxt_hwrm_port_qstats(bp);
6237
4cebdcec
MC		 6238 smp_mb__before_atomic();
6239 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 6240}
6241
6242static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6243{
6244 int rc;
6245 struct bnxt *bp = netdev_priv(dev);
6246
6247 SET_NETDEV_DEV(dev, &pdev->dev);
6248
6249 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6250 rc = pci_enable_device(pdev);
6251 if (rc) {
6252 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6253 goto init_err;
6254 }
6255
6256 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6257 dev_err(&pdev->dev,
6258 "Cannot find PCI device base address, aborting\n");
6259 rc = -ENODEV;
6260 goto init_err_disable;
6261 }
6262
6263 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6264 if (rc) {
6265 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6266 goto init_err_disable;
6267 }
6268
6269 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6270 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6271 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6272 goto init_err_disable;
6273 }
6274
6275 pci_set_master(pdev);
6276
6277 bp->dev = dev;
6278 bp->pdev = pdev;
6279
6280 bp->bar0 = pci_ioremap_bar(pdev, 0);
6281 if (!bp->bar0) {
6282 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6283 rc = -ENOMEM;
6284 goto init_err_release;
6285 }
6286
6287 bp->bar1 = pci_ioremap_bar(pdev, 2);
6288 if (!bp->bar1) {
6289 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6290 rc = -ENOMEM;
6291 goto init_err_release;
6292 }
6293
6294 bp->bar2 = pci_ioremap_bar(pdev, 4);
6295 if (!bp->bar2) {
6296 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6297 rc = -ENOMEM;
6298 goto init_err_release;
6299 }
6300
6316ea6d
SB		 6301 pci_enable_pcie_error_reporting(pdev);
6302
c0c050c5
MC		 6303 INIT_WORK(&bp->sp_task, bnxt_sp_task);
6304
6305 spin_lock_init(&bp->ntp_fltr_lock);
6306
6307 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6308 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6309
dfb5b894 6310 /* tick values in micro seconds */
dfc9c94a
MC		 6311 bp->rx_coal_ticks = 12;
6312 bp->rx_coal_bufs = 30;
dfb5b894
MC		 6313 bp->rx_coal_ticks_irq = 1;
6314 bp->rx_coal_bufs_irq = 2;
c0c050c5 6315
dfc9c94a
MC		 6316 bp->tx_coal_ticks = 25;
6317 bp->tx_coal_bufs = 30;
6318 bp->tx_coal_ticks_irq = 2;
6319 bp->tx_coal_bufs_irq = 2;
6320
51f30785
MC		 6321 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6322
c0c050c5
MC		 6323 init_timer(&bp->timer);
6324 bp->timer.data = (unsigned long)bp;
6325 bp->timer.function = bnxt_timer;
6326 bp->current_interval = BNXT_TIMER_INTERVAL;
6327
caefe526 6328 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 6329
6330 return 0;
6331
6332init_err_release:
6333 if (bp->bar2) {
6334 pci_iounmap(pdev, bp->bar2);
6335 bp->bar2 = NULL;
6336 }
6337
6338 if (bp->bar1) {
6339 pci_iounmap(pdev, bp->bar1);
6340 bp->bar1 = NULL;
6341 }
6342
6343 if (bp->bar0) {
6344 pci_iounmap(pdev, bp->bar0);
6345 bp->bar0 = NULL;
6346 }
6347
6348 pci_release_regions(pdev);
6349
6350init_err_disable:
6351 pci_disable_device(pdev);
6352
6353init_err:
6354 return rc;
6355}
6356
6357/* rtnl_lock held */
6358static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6359{
6360 struct sockaddr *addr = p;
1fc2cfd0
JH		 6361 struct bnxt *bp = netdev_priv(dev);
6362 int rc = 0;
c0c050c5
MC		 6363
6364 if (!is_valid_ether_addr(addr->sa_data))
6365 return -EADDRNOTAVAIL;
6366
84c33dd3
MC		 6367 rc = bnxt_approve_mac(bp, addr->sa_data);
6368 if (rc)
6369 return rc;
bdd4347b 6370
1fc2cfd0
JH		 6371 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6372 return 0;
6373
c0c050c5 6374 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 6375 if (netif_running(dev)) {
6376 bnxt_close_nic(bp, false, false);
6377 rc = bnxt_open_nic(bp, false, false);
6378 }
c0c050c5 6379
1fc2cfd0 6380 return rc;
c0c050c5
MC		 6381}
6382
6383/* rtnl_lock held */
6384static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6385{
6386 struct bnxt *bp = netdev_priv(dev);
6387
c0c050c5
MC		 6388 if (netif_running(dev))
6389 bnxt_close_nic(bp, false, false);
6390
6391 dev->mtu = new_mtu;
6392 bnxt_set_ring_params(bp);
6393
6394 if (netif_running(dev))
6395 return bnxt_open_nic(bp, false, false);
6396
6397 return 0;
6398}
6399
c5e3deb8 6400int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
c0c050c5
MC		 6401{
6402 struct bnxt *bp = netdev_priv(dev);
3ffb6a39 6403 bool sh = false;
16e5cc64 6404
c0c050c5
MC		 6405 if (tc > bp->max_tc) {
6406 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
6407 tc, bp->max_tc);
6408 return -EINVAL;
6409 }
6410
6411 if (netdev_get_num_tc(dev) == tc)
6412 return 0;
6413
3ffb6a39
MC		 6414 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6415 sh = true;
6416
c0c050c5 6417 if (tc) {
6e6c5a57 6418 int max_rx_rings, max_tx_rings, rc;
c0c050c5 6419
01657bcd 6420 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57 6421 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
c0c050c5
MC		 6422 return -ENOMEM;
6423 }
6424
6425 /* Needs to close the device and do hw resource re-allocations */
6426 if (netif_running(bp->dev))
6427 bnxt_close_nic(bp, true, false);
6428
6429 if (tc) {
6430 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6431 netdev_set_num_tc(dev, tc);
6432 } else {
6433 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6434 netdev_reset_tc(dev);
6435 }
3ffb6a39
MC		 6436 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6437 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5
MC		 6438 bp->num_stat_ctxs = bp->cp_nr_rings;
6439
6440 if (netif_running(bp->dev))
6441 return bnxt_open_nic(bp, true, false);
6442
6443 return 0;
6444}
6445
c5e3deb8
MC		 6446static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6447 struct tc_to_netdev *ntc)
6448{
6449 if (ntc->type != TC_SETUP_MQPRIO)
6450 return -EINVAL;
6451
6452 return bnxt_setup_mq_tc(dev, ntc->tc);
6453}
6454
c0c050c5
MC		 6455#ifdef CONFIG_RFS_ACCEL
6456static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6457 struct bnxt_ntuple_filter *f2)
6458{
6459 struct flow_keys *keys1 = &f1->fkeys;
6460 struct flow_keys *keys2 = &f2->fkeys;
6461
6462 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6463 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6464 keys1->ports.ports == keys2->ports.ports &&
6465 keys1->basic.ip_proto == keys2->basic.ip_proto &&
6466 keys1->basic.n_proto == keys2->basic.n_proto &&
a54c4d74
MC		 6467 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
6468 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
c0c050c5
MC		 6469 return true;
6470
6471 return false;
6472}
6473
6474static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6475 u16 rxq_index, u32 flow_id)
6476{
6477 struct bnxt *bp = netdev_priv(dev);
6478 struct bnxt_ntuple_filter *fltr, *new_fltr;
6479 struct flow_keys *fkeys;
6480 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
a54c4d74 6481 int rc = 0, idx, bit_id, l2_idx = 0;
c0c050c5
MC		 6482 struct hlist_head *head;
6483
6484 if (skb->encapsulation)
6485 return -EPROTONOSUPPORT;
6486
a54c4d74
MC		 6487 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
6488 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6489 int off = 0, j;
6490
6491 netif_addr_lock_bh(dev);
6492 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
6493 if (ether_addr_equal(eth->h_dest,
6494 vnic->uc_list + off)) {
6495 l2_idx = j + 1;
6496 break;
6497 }
6498 }
6499 netif_addr_unlock_bh(dev);
6500 if (!l2_idx)
6501 return -EINVAL;
6502 }
c0c050c5
MC		 6503 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6504 if (!new_fltr)
6505 return -ENOMEM;
6506
6507 fkeys = &new_fltr->fkeys;
6508 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6509 rc = -EPROTONOSUPPORT;
6510 goto err_free;
6511 }
6512
6513 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
6514 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6515 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6516 rc = -EPROTONOSUPPORT;
6517 goto err_free;
6518 }
6519
a54c4d74 6520 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
c0c050c5
MC		 6521 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6522
6523 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6524 head = &bp->ntp_fltr_hash_tbl[idx];
6525 rcu_read_lock();
6526 hlist_for_each_entry_rcu(fltr, head, hash) {
6527 if (bnxt_fltr_match(fltr, new_fltr)) {
6528 rcu_read_unlock();
6529 rc = 0;
6530 goto err_free;
6531 }
6532 }
6533 rcu_read_unlock();
6534
6535 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 6536 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6537 BNXT_NTP_FLTR_MAX_FLTR, 0);
6538 if (bit_id < 0) {
c0c050c5
MC		 6539 spin_unlock_bh(&bp->ntp_fltr_lock);
6540 rc = -ENOMEM;
6541 goto err_free;
6542 }
6543
84e86b98 6544 new_fltr->sw_id = (u16)bit_id;
c0c050c5 6545 new_fltr->flow_id = flow_id;
a54c4d74 6546 new_fltr->l2_fltr_idx = l2_idx;
c0c050c5
MC		 6547 new_fltr->rxq = rxq_index;
6548 hlist_add_head_rcu(&new_fltr->hash, head);
6549 bp->ntp_fltr_count++;
6550 spin_unlock_bh(&bp->ntp_fltr_lock);
6551
6552 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6553 schedule_work(&bp->sp_task);
6554
6555 return new_fltr->sw_id;
6556
6557err_free:
6558 kfree(new_fltr);
6559 return rc;
6560}
6561
6562static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6563{
6564 int i;
6565
6566 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6567 struct hlist_head *head;
6568 struct hlist_node *tmp;
6569 struct bnxt_ntuple_filter *fltr;
6570 int rc;
6571
6572 head = &bp->ntp_fltr_hash_tbl[i];
6573 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6574 bool del = false;
6575
6576 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6577 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6578 fltr->flow_id,
6579 fltr->sw_id)) {
6580 bnxt_hwrm_cfa_ntuple_filter_free(bp,
6581 fltr);
6582 del = true;
6583 }
6584 } else {
6585 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6586 fltr);
6587 if (rc)
6588 del = true;
6589 else
6590 set_bit(BNXT_FLTR_VALID, &fltr->state);
6591 }
6592
6593 if (del) {
6594 spin_lock_bh(&bp->ntp_fltr_lock);
6595 hlist_del_rcu(&fltr->hash);
6596 bp->ntp_fltr_count--;
6597 spin_unlock_bh(&bp->ntp_fltr_lock);
6598 synchronize_rcu();
6599 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6600 kfree(fltr);
6601 }
6602 }
6603 }
19241368
JH		 6604 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6605 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 6606}
6607
6608#else
6609
6610static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6611{
6612}
6613
6614#endif /* CONFIG_RFS_ACCEL */
6615
ad51b8e9
AD		 6616static void bnxt_udp_tunnel_add(struct net_device *dev,
6617 struct udp_tunnel_info *ti)
c0c050c5
MC		 6618{
6619 struct bnxt *bp = netdev_priv(dev);
6620
ad51b8e9 6621 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 6622 return;
6623
ad51b8e9 6624 if (!netif_running(dev))
c0c050c5
MC		 6625 return;
6626
ad51b8e9
AD		 6627 switch (ti->type) {
6628 case UDP_TUNNEL_TYPE_VXLAN:
6629 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
6630 return;
c0c050c5 6631
ad51b8e9
AD		 6632 bp->vxlan_port_cnt++;
6633 if (bp->vxlan_port_cnt == 1) {
6634 bp->vxlan_port = ti->port;
6635 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
6636 schedule_work(&bp->sp_task);
6637 }
6638 break;
7cdd5fc3
AD		 6639 case UDP_TUNNEL_TYPE_GENEVE:
6640 if (bp->nge_port_cnt && bp->nge_port != ti->port)
6641 return;
6642
6643 bp->nge_port_cnt++;
6644 if (bp->nge_port_cnt == 1) {
6645 bp->nge_port = ti->port;
6646 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
6647 }
6648 break;
ad51b8e9
AD		 6649 default:
6650 return;
c0c050c5 6651 }
ad51b8e9
AD		 6652
6653 schedule_work(&bp->sp_task);
c0c050c5
MC		 6654}
6655
ad51b8e9
AD		 6656static void bnxt_udp_tunnel_del(struct net_device *dev,
6657 struct udp_tunnel_info *ti)
c0c050c5
MC		 6658{
6659 struct bnxt *bp = netdev_priv(dev);
6660
ad51b8e9 6661 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 6662 return;
6663
ad51b8e9 6664 if (!netif_running(dev))
c0c050c5
MC		 6665 return;
6666
ad51b8e9
AD		 6667 switch (ti->type) {
6668 case UDP_TUNNEL_TYPE_VXLAN:
6669 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
6670 return;
c0c050c5
MC		 6671 bp->vxlan_port_cnt--;
6672
ad51b8e9
AD		 6673 if (bp->vxlan_port_cnt != 0)
6674 return;
6675
6676 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
6677 break;
7cdd5fc3
AD		 6678 case UDP_TUNNEL_TYPE_GENEVE:
6679 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
6680 return;
6681 bp->nge_port_cnt--;
6682
6683 if (bp->nge_port_cnt != 0)
6684 return;
6685
6686 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
6687 break;
ad51b8e9
AD		 6688 default:
6689 return;
c0c050c5 6690 }
ad51b8e9
AD		 6691
6692 schedule_work(&bp->sp_task);
c0c050c5
MC		 6693}
6694
6695static const struct net_device_ops bnxt_netdev_ops = {
6696 .ndo_open = bnxt_open,
6697 .ndo_start_xmit = bnxt_start_xmit,
6698 .ndo_stop = bnxt_close,
6699 .ndo_get_stats64 = bnxt_get_stats64,
6700 .ndo_set_rx_mode = bnxt_set_rx_mode,
6701 .ndo_do_ioctl = bnxt_ioctl,
6702 .ndo_validate_addr = eth_validate_addr,
6703 .ndo_set_mac_address = bnxt_change_mac_addr,
6704 .ndo_change_mtu = bnxt_change_mtu,
6705 .ndo_fix_features = bnxt_fix_features,
6706 .ndo_set_features = bnxt_set_features,
6707 .ndo_tx_timeout = bnxt_tx_timeout,
6708#ifdef CONFIG_BNXT_SRIOV
6709 .ndo_get_vf_config = bnxt_get_vf_config,
6710 .ndo_set_vf_mac = bnxt_set_vf_mac,
6711 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
6712 .ndo_set_vf_rate = bnxt_set_vf_bw,
6713 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
6714 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
6715#endif
6716#ifdef CONFIG_NET_POLL_CONTROLLER
6717 .ndo_poll_controller = bnxt_poll_controller,
6718#endif
6719 .ndo_setup_tc = bnxt_setup_tc,
6720#ifdef CONFIG_RFS_ACCEL
6721 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
6722#endif
ad51b8e9
AD		 6723 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
6724 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
c0c050c5
MC		 6725#ifdef CONFIG_NET_RX_BUSY_POLL
6726 .ndo_busy_poll = bnxt_busy_poll,
6727#endif
6728};
6729
6730static void bnxt_remove_one(struct pci_dev *pdev)
6731{
6732 struct net_device *dev = pci_get_drvdata(pdev);
6733 struct bnxt *bp = netdev_priv(dev);
6734
6735 if (BNXT_PF(bp))
6736 bnxt_sriov_disable(bp);
6737
6316ea6d 6738 pci_disable_pcie_error_reporting(pdev);
c0c050c5
MC		 6739 unregister_netdev(dev);
6740 cancel_work_sync(&bp->sp_task);
6741 bp->sp_event = 0;
6742
7809592d 6743 bnxt_clear_int_mode(bp);
be58a0da 6744 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5 6745 bnxt_free_hwrm_resources(bp);
7df4ae9f 6746 bnxt_dcb_free(bp);
c0c050c5
MC		 6747 pci_iounmap(pdev, bp->bar2);
6748 pci_iounmap(pdev, bp->bar1);
6749 pci_iounmap(pdev, bp->bar0);
6750 free_netdev(dev);
6751
6752 pci_release_regions(pdev);
6753 pci_disable_device(pdev);
6754}
6755
6756static int bnxt_probe_phy(struct bnxt *bp)
6757{
6758 int rc = 0;
6759 struct bnxt_link_info *link_info = &bp->link_info;
c0c050c5 6760
170ce013
MC		 6761 rc = bnxt_hwrm_phy_qcaps(bp);
6762 if (rc) {
6763 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
6764 rc);
6765 return rc;
6766 }
6767
c0c050c5
MC		 6768 rc = bnxt_update_link(bp, false);
6769 if (rc) {
6770 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
6771 rc);
6772 return rc;
6773 }
6774
93ed8117
MC		 6775 /* Older firmware does not have supported_auto_speeds, so assume
6776 * that all supported speeds can be autonegotiated.
6777 */
6778 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
6779 link_info->support_auto_speeds = link_info->support_speeds;
6780
c0c050c5 6781 /*initialize the ethool setting copy with NVM settings */
0d8abf02 6782 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
c9ee9516
MC		 6783 link_info->autoneg = BNXT_AUTONEG_SPEED;
6784 if (bp->hwrm_spec_code >= 0x10201) {
6785 if (link_info->auto_pause_setting &
6786 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
6787 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6788 } else {
6789 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6790 }
0d8abf02 6791 link_info->advertising = link_info->auto_link_speeds;
0d8abf02
MC		 6792 } else {
6793 link_info->req_link_speed = link_info->force_link_speed;
6794 link_info->req_duplex = link_info->duplex_setting;
c0c050c5 6795 }
c9ee9516
MC		 6796 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
6797 link_info->req_flow_ctrl =
6798 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
6799 else
6800 link_info->req_flow_ctrl = link_info->force_pause_setting;
c0c050c5
MC		 6801 return rc;
6802}
6803
6804static int bnxt_get_max_irq(struct pci_dev *pdev)
6805{
6806 u16 ctrl;
6807
6808 if (!pdev->msix_cap)
6809 return 1;
6810
6811 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
6812 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
6813}
6814
6e6c5a57
MC		 6815static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
6816 int *max_cp)
c0c050c5 6817{
6e6c5a57 6818 int max_ring_grps = 0;
c0c050c5 6819
379a80a1 6820#ifdef CONFIG_BNXT_SRIOV
415b6f19 6821 if (!BNXT_PF(bp)) {
c0c050c5
MC		 6822 *max_tx = bp->vf.max_tx_rings;
6823 *max_rx = bp->vf.max_rx_rings;
6e6c5a57
MC		 6824 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
6825 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
b72d4a68 6826 max_ring_grps = bp->vf.max_hw_ring_grps;
415b6f19 6827 } else
379a80a1 6828#endif
415b6f19
AB		 6829 {
6830 *max_tx = bp->pf.max_tx_rings;
6831 *max_rx = bp->pf.max_rx_rings;
6832 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
6833 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
6834 max_ring_grps = bp->pf.max_hw_ring_grps;
c0c050c5 6835 }
76595193
PS		 6836 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
6837 *max_cp -= 1;
6838 *max_rx -= 2;
6839 }
c0c050c5
MC		 6840 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6841 *max_rx >>= 1;
b72d4a68 6842 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 6843}
6844
6845int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
6846{
6847 int rx, tx, cp;
6848
6849 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
6850 if (!rx || !tx || !cp)
6851 return -ENOMEM;
6852
6853 *max_rx = rx;
6854 *max_tx = tx;
6855 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
6856}
6857
e4060d30
MC		 6858static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
6859 bool shared)
6860{
6861 int rc;
6862
6863 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
6864 if (rc)
6865 return rc;
6866
6867 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
6868 int max_cp, max_stat, max_irq;
6869
6870 /* Reserve minimum resources for RoCE */
6871 max_cp = bnxt_get_max_func_cp_rings(bp);
6872 max_stat = bnxt_get_max_func_stat_ctxs(bp);
6873 max_irq = bnxt_get_max_func_irqs(bp);
6874 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
6875 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
6876 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
6877 return 0;
6878
6879 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
6880 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
6881 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
6882 max_cp = min_t(int, max_cp, max_irq);
6883 max_cp = min_t(int, max_cp, max_stat);
6884 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
6885 if (rc)
6886 rc = 0;
6887 }
6888 return rc;
6889}
6890
6e6c5a57
MC		 6891static int bnxt_set_dflt_rings(struct bnxt *bp)
6892{
6893 int dflt_rings, max_rx_rings, max_tx_rings, rc;
6894 bool sh = true;
6895
6896 if (sh)
6897 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6898 dflt_rings = netif_get_num_default_rss_queues();
e4060d30 6899 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57
MC		 6900 if (rc)
6901 return rc;
6902 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
6903 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
6904 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6905 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6906 bp->tx_nr_rings + bp->rx_nr_rings;
6907 bp->num_stat_ctxs = bp->cp_nr_rings;
76595193
PS		 6908 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6909 bp->rx_nr_rings++;
6910 bp->cp_nr_rings++;
6911 }
6e6c5a57 6912 return rc;
c0c050c5
MC		 6913}
6914
7b08f661
MC		 6915void bnxt_restore_pf_fw_resources(struct bnxt *bp)
6916{
6917 ASSERT_RTNL();
6918 bnxt_hwrm_func_qcaps(bp);
6919}
6920
90c4f788
AK		 6921static void bnxt_parse_log_pcie_link(struct bnxt *bp)
6922{
6923 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
6924 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
6925
6926 if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
6927 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
6928 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
6929 else
6930 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
6931 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
6932 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
6933 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
6934 "Unknown", width);
6935}
6936
c0c050c5
MC		 6937static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6938{
6939 static int version_printed;
6940 struct net_device *dev;
6941 struct bnxt *bp;
6e6c5a57 6942 int rc, max_irqs;
c0c050c5 6943
fa853dda
PS		 6944 if (pdev->device == 0x16cd && pci_is_bridge(pdev))
6945 return -ENODEV;
6946
c0c050c5
MC		 6947 if (version_printed++ == 0)
6948 pr_info("%s", version);
6949
6950 max_irqs = bnxt_get_max_irq(pdev);
6951 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
6952 if (!dev)
6953 return -ENOMEM;
6954
6955 bp = netdev_priv(dev);
6956
6957 if (bnxt_vf_pciid(ent->driver_data))
6958 bp->flags |= BNXT_FLAG_VF;
6959
2bcfa6f6 6960 if (pdev->msix_cap)
c0c050c5 6961 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 6962
6963 rc = bnxt_init_board(pdev, dev);
6964 if (rc < 0)
6965 goto init_err_free;
6966
6967 dev->netdev_ops = &bnxt_netdev_ops;
6968 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
6969 dev->ethtool_ops = &bnxt_ethtool_ops;
6970
6971 pci_set_drvdata(pdev, dev);
6972
3e8060fa
PS		 6973 rc = bnxt_alloc_hwrm_resources(bp);
6974 if (rc)
6975 goto init_err;
6976
6977 mutex_init(&bp->hwrm_cmd_lock);
6978 rc = bnxt_hwrm_ver_get(bp);
6979 if (rc)
6980 goto init_err;
6981
5ac67d8b
RS		 6982 bnxt_hwrm_fw_set_time(bp);
6983
c0c050c5
MC		 6984 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6985 NETIF_F_TSO | NETIF_F_TSO6 |
6986 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7e13318d 6987 NETIF_F_GSO_IPXIP4 |
152971ee
AD		 6988 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6989 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
3e8060fa
PS		 6990 NETIF_F_RXCSUM | NETIF_F_GRO;
6991
6992 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
6993 dev->hw_features |= NETIF_F_LRO;
c0c050c5 6994
c0c050c5
MC		 6995 dev->hw_enc_features =
6996 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6997 NETIF_F_TSO | NETIF_F_TSO6 |
6998 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
152971ee 6999 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7e13318d 7000 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
152971ee
AD		 7001 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
7002 NETIF_F_GSO_GRE_CSUM;
c0c050c5
MC		 7003 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
7004 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7005 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
7006 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
7007 dev->priv_flags |= IFF_UNICAST_FLT;
7008
e1c6dcca
JW		 7009 /* MTU range: 60 - 9500 */
7010 dev->min_mtu = ETH_ZLEN;
7011 dev->max_mtu = 9500;
7012
7df4ae9f
MC		 7013 bnxt_dcb_init(bp);
7014
c0c050c5
MC		 7015#ifdef CONFIG_BNXT_SRIOV
7016 init_waitqueue_head(&bp->sriov_cfg_wait);
7017#endif
309369c9 7018 bp->gro_func = bnxt_gro_func_5730x;
94758f8d
MC		 7019 if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
7020 bp->gro_func = bnxt_gro_func_5731x;
309369c9 7021
c0c050c5
MC		 7022 rc = bnxt_hwrm_func_drv_rgtr(bp);
7023 if (rc)
7024 goto init_err;
7025
7026 /* Get the MAX capabilities for this function */
7027 rc = bnxt_hwrm_func_qcaps(bp);
7028 if (rc) {
7029 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
7030 rc);
7031 rc = -1;
7032 goto init_err;
7033 }
7034
7035 rc = bnxt_hwrm_queue_qportcfg(bp);
7036 if (rc) {
7037 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
7038 rc);
7039 rc = -1;
7040 goto init_err;
7041 }
7042
567b2abe
SB		 7043 bnxt_hwrm_func_qcfg(bp);
7044
c0c050c5
MC		 7045 bnxt_set_tpa_flags(bp);
7046 bnxt_set_ring_params(bp);
33c2657e 7047 bnxt_set_max_func_irqs(bp, max_irqs);
6e6c5a57 7048 bnxt_set_dflt_rings(bp);
c0c050c5 7049
87da7f79
MC		 7050 /* Default RSS hash cfg. */
7051 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
7052 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
7053 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
7054 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
7055 if (!BNXT_CHIP_NUM_57X0X(bp->chip_num) &&
7056 !BNXT_CHIP_TYPE_NITRO_A0(bp) &&
7057 bp->hwrm_spec_code >= 0x10501) {
7058 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
7059 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
7060 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
7061 }
7062
3e8060fa 7063 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) {
2bcfa6f6
MC		 7064 dev->hw_features |= NETIF_F_NTUPLE;
7065 if (bnxt_rfs_capable(bp)) {
7066 bp->flags |= BNXT_FLAG_RFS;
7067 dev->features |= NETIF_F_NTUPLE;
7068 }
7069 }
7070
c0c050c5
MC		 7071 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
7072 bp->flags |= BNXT_FLAG_STRIP_VLAN;
7073
7074 rc = bnxt_probe_phy(bp);
7075 if (rc)
7076 goto init_err;
7077
aa8ed021
MC		 7078 rc = bnxt_hwrm_func_reset(bp);
7079 if (rc)
7080 goto init_err;
7081
7809592d 7082 rc = bnxt_init_int_mode(bp);
c0c050c5
MC		 7083 if (rc)
7084 goto init_err;
7085
7809592d
MC		 7086 rc = register_netdev(dev);
7087 if (rc)
7088 goto init_err_clr_int;
7089
c0c050c5
MC		 7090 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
7091 board_info[ent->driver_data].name,
7092 (long)pci_resource_start(pdev, 0), dev->dev_addr);
7093
90c4f788
AK		 7094 bnxt_parse_log_pcie_link(bp);
7095
c0c050c5
MC		 7096 return 0;
7097
7809592d
MC		 7098init_err_clr_int:
7099 bnxt_clear_int_mode(bp);
7100
c0c050c5
MC		 7101init_err:
7102 pci_iounmap(pdev, bp->bar0);
7103 pci_release_regions(pdev);
7104 pci_disable_device(pdev);
7105
7106init_err_free:
7107 free_netdev(dev);
7108 return rc;
7109}
7110
6316ea6d
SB		 7111/**
7112 * bnxt_io_error_detected - called when PCI error is detected
7113 * @pdev: Pointer to PCI device
7114 * @state: The current pci connection state
7115 *
7116 * This function is called after a PCI bus error affecting
7117 * this device has been detected.
7118 */
7119static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
7120 pci_channel_state_t state)
7121{
7122 struct net_device *netdev = pci_get_drvdata(pdev);
7123
7124 netdev_info(netdev, "PCI I/O error detected\n");
7125
7126 rtnl_lock();
7127 netif_device_detach(netdev);
7128
7129 if (state == pci_channel_io_perm_failure) {
7130 rtnl_unlock();
7131 return PCI_ERS_RESULT_DISCONNECT;
7132 }
7133
7134 if (netif_running(netdev))
7135 bnxt_close(netdev);
7136
7137 pci_disable_device(pdev);
7138 rtnl_unlock();
7139
7140 /* Request a slot slot reset. */
7141 return PCI_ERS_RESULT_NEED_RESET;
7142}
7143
7144/**
7145 * bnxt_io_slot_reset - called after the pci bus has been reset.
7146 * @pdev: Pointer to PCI device
7147 *
7148 * Restart the card from scratch, as if from a cold-boot.
7149 * At this point, the card has exprienced a hard reset,
7150 * followed by fixups by BIOS, and has its config space
7151 * set up identically to what it was at cold boot.
7152 */
7153static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
7154{
7155 struct net_device *netdev = pci_get_drvdata(pdev);
7156 struct bnxt *bp = netdev_priv(netdev);
7157 int err = 0;
7158 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7159
7160 netdev_info(bp->dev, "PCI Slot Reset\n");
7161
7162 rtnl_lock();
7163
7164 if (pci_enable_device(pdev)) {
7165 dev_err(&pdev->dev,
7166 "Cannot re-enable PCI device after reset.\n");
7167 } else {
7168 pci_set_master(pdev);
7169
aa8ed021
MC		 7170 err = bnxt_hwrm_func_reset(bp);
7171 if (!err && netif_running(netdev))
6316ea6d
SB		 7172 err = bnxt_open(netdev);
7173
7174 if (!err)
7175 result = PCI_ERS_RESULT_RECOVERED;
7176 }
7177
7178 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7179 dev_close(netdev);
7180
7181 rtnl_unlock();
7182
7183 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7184 if (err) {
7185 dev_err(&pdev->dev,
7186 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7187 err); /* non-fatal, continue */
7188 }
7189
7190 return PCI_ERS_RESULT_RECOVERED;
7191}
7192
7193/**
7194 * bnxt_io_resume - called when traffic can start flowing again.
7195 * @pdev: Pointer to PCI device
7196 *
7197 * This callback is called when the error recovery driver tells
7198 * us that its OK to resume normal operation.
7199 */
7200static void bnxt_io_resume(struct pci_dev *pdev)
7201{
7202 struct net_device *netdev = pci_get_drvdata(pdev);
7203
7204 rtnl_lock();
7205
7206 netif_device_attach(netdev);
7207
7208 rtnl_unlock();
7209}
7210
7211static const struct pci_error_handlers bnxt_err_handler = {
7212 .error_detected = bnxt_io_error_detected,
7213 .slot_reset = bnxt_io_slot_reset,
7214 .resume = bnxt_io_resume
7215};
7216
c0c050c5
MC		 7217static struct pci_driver bnxt_pci_driver = {
7218 .name = DRV_MODULE_NAME,
7219 .id_table = bnxt_pci_tbl,
7220 .probe = bnxt_init_one,
7221 .remove = bnxt_remove_one,
6316ea6d 7222 .err_handler = &bnxt_err_handler,
c0c050c5
MC		 7223#if defined(CONFIG_BNXT_SRIOV)
7224 .sriov_configure = bnxt_sriov_configure,
7225#endif
7226};
7227
7228module_pci_driver(bnxt_pci_driver);
Ubuntu Jammy Linux kernel mirror