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bnxt_en: Refactor tx completion path.
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
11f15ed3 3 * Copyright (c) 2014-2016 Broadcom Corporation
c0c050c5
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11
12#include <linux/stringify.h>
13#include <linux/kernel.h>
14#include <linux/timer.h>
15#include <linux/errno.h>
16#include <linux/ioport.h>
17#include <linux/slab.h>
18#include <linux/vmalloc.h>
19#include <linux/interrupt.h>
20#include <linux/pci.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/dma-mapping.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/delay.h>
29#include <asm/byteorder.h>
30#include <asm/page.h>
31#include <linux/time.h>
32#include <linux/mii.h>
33#include <linux/if.h>
34#include <linux/if_vlan.h>
5ac67d8b 35#include <linux/rtc.h>
c0c050c5
MC		 36#include <net/ip.h>
37#include <net/tcp.h>
38#include <net/udp.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
ad51b8e9 41#include <net/udp_tunnel.h>
c0c050c5
MC		 42#include <linux/workqueue.h>
43#include <linux/prefetch.h>
44#include <linux/cache.h>
45#include <linux/log2.h>
46#include <linux/aer.h>
47#include <linux/bitmap.h>
48#include <linux/cpu_rmap.h>
49
50#include "bnxt_hsi.h"
51#include "bnxt.h"
a588e458 52#include "bnxt_ulp.h"
c0c050c5
MC		 53#include "bnxt_sriov.h"
54#include "bnxt_ethtool.h"
7df4ae9f 55#include "bnxt_dcb.h"
c0c050c5
MC		 56
57#define BNXT_TX_TIMEOUT (5 * HZ)
58
59static const char version[] =
60 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
61
62MODULE_LICENSE("GPL");
63MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
64MODULE_VERSION(DRV_MODULE_VERSION);
65
66#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
67#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
68#define BNXT_RX_COPY_THRESH 256
69
4419dbe6 70#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 71
72enum board_idx {
fbc9a523 73 BCM57301,
c0c050c5
MC		 74 BCM57302,
75 BCM57304,
1f681688 76 BCM57417_NPAR,
fa853dda 77 BCM58700,
b24eb6ae
MC		 78 BCM57311,
79 BCM57312,
fbc9a523 80 BCM57402,
c0c050c5
MC		 81 BCM57404,
82 BCM57406,
1f681688
MC		 83 BCM57402_NPAR,
84 BCM57407,
b24eb6ae
MC		 85 BCM57412,
86 BCM57414,
87 BCM57416,
88 BCM57417,
1f681688 89 BCM57412_NPAR,
5049e33b 90 BCM57314,
1f681688
MC		 91 BCM57417_SFP,
92 BCM57416_SFP,
93 BCM57404_NPAR,
94 BCM57406_NPAR,
95 BCM57407_SFP,
adbc8305 96 BCM57407_NPAR,
1f681688
MC		 97 BCM57414_NPAR,
98 BCM57416_NPAR,
adbc8305
MC		 99 NETXTREME_E_VF,
100 NETXTREME_C_VF,
c0c050c5
MC		 101};
102
103/* indexed by enum above */
104static const struct {
105 char *name;
106} board_info[] = {
adbc8305
MC		 107 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
108 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
109 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
1f681688 110 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 111 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
112 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
113 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
114 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
115 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
116 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
1f681688 117 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 118 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
119 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
120 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
121 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
122 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
1f681688 123 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 124 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
125 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
126 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
1f681688
MC		 127 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
128 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 129 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
130 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
1f681688
MC		 131 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
132 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 133 { "Broadcom NetXtreme-E Ethernet Virtual Function" },
134 { "Broadcom NetXtreme-C Ethernet Virtual Function" },
c0c050c5
MC		 135};
136
137static const struct pci_device_id bnxt_pci_tbl[] = {
adbc8305 138 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
fbc9a523 139 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 140 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
141 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
1f681688 142 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
fa853dda 143 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
b24eb6ae
MC		 144 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
145 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
fbc9a523 146 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 147 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
148 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
1f681688
MC		 149 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
150 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
b24eb6ae
MC		 151 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
152 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
153 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
154 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
1f681688 155 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
5049e33b 156 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
1f681688
MC		 157 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
158 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
159 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
160 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
161 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
adbc8305
MC		 162 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
163 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
1f681688 164 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
adbc8305 165 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
1f681688 166 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
adbc8305 167 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
c0c050c5 168#ifdef CONFIG_BNXT_SRIOV
adbc8305
MC		 169 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
170 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
171 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
172 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
173 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
174 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
c0c050c5
MC		 175#endif
176 { 0 }
177};
178
179MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
180
181static const u16 bnxt_vf_req_snif[] = {
182 HWRM_FUNC_CFG,
183 HWRM_PORT_PHY_QCFG,
184 HWRM_CFA_L2_FILTER_ALLOC,
185};
186
25be8623 187static const u16 bnxt_async_events_arr[] = {
87c374de
MC		 188 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
189 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
190 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
191 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
192 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
25be8623
MC		 193};
194
c0c050c5
MC		 195static bool bnxt_vf_pciid(enum board_idx idx)
196{
adbc8305 197 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
c0c050c5
MC		 198}
199
200#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
201#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
202#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
203
204#define BNXT_CP_DB_REARM(db, raw_cons) \
205 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
206
207#define BNXT_CP_DB(db, raw_cons) \
208 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
209
210#define BNXT_CP_DB_IRQ_DIS(db) \
211 writel(DB_CP_IRQ_DIS_FLAGS, db)
212
213static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
214{
215 /* Tell compiler to fetch tx indices from memory. */
216 barrier();
217
218 return bp->tx_ring_size -
219 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
220}
221
222static const u16 bnxt_lhint_arr[] = {
223 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
224 TX_BD_FLAGS_LHINT_512_TO_1023,
225 TX_BD_FLAGS_LHINT_1024_TO_2047,
226 TX_BD_FLAGS_LHINT_1024_TO_2047,
227 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
228 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
229 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
230 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
231 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
232 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
233 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
234 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
235 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
236 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
237 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
238 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
239 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
240 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
241 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
242};
243
244static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
245{
246 struct bnxt *bp = netdev_priv(dev);
247 struct tx_bd *txbd;
248 struct tx_bd_ext *txbd1;
249 struct netdev_queue *txq;
250 int i;
251 dma_addr_t mapping;
252 unsigned int length, pad = 0;
253 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
254 u16 prod, last_frag;
255 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 256 struct bnxt_tx_ring_info *txr;
257 struct bnxt_sw_tx_bd *tx_buf;
258
259 i = skb_get_queue_mapping(skb);
260 if (unlikely(i >= bp->tx_nr_rings)) {
261 dev_kfree_skb_any(skb);
262 return NETDEV_TX_OK;
263 }
264
c0c050c5 265 txq = netdev_get_tx_queue(dev, i);
a960dec9 266 txr = &bp->tx_ring[bp->tx_ring_map[i]];
c0c050c5
MC		 267 prod = txr->tx_prod;
268
269 free_size = bnxt_tx_avail(bp, txr);
270 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
271 netif_tx_stop_queue(txq);
272 return NETDEV_TX_BUSY;
273 }
274
275 length = skb->len;
276 len = skb_headlen(skb);
277 last_frag = skb_shinfo(skb)->nr_frags;
278
279 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
280
281 txbd->tx_bd_opaque = prod;
282
283 tx_buf = &txr->tx_buf_ring[prod];
284 tx_buf->skb = skb;
285 tx_buf->nr_frags = last_frag;
286
287 vlan_tag_flags = 0;
288 cfa_action = 0;
289 if (skb_vlan_tag_present(skb)) {
290 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
291 skb_vlan_tag_get(skb);
292 /* Currently supports 8021Q, 8021AD vlan offloads
293 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
294 */
295 if (skb->vlan_proto == htons(ETH_P_8021Q))
296 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
297 }
298
299 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 300 struct tx_push_buffer *tx_push_buf = txr->tx_push;
301 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
302 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
303 void *pdata = tx_push_buf->data;
304 u64 *end;
305 int j, push_len;
c0c050c5
MC		 306
307 /* Set COAL_NOW to be ready quickly for the next push */
308 tx_push->tx_bd_len_flags_type =
309 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
310 TX_BD_TYPE_LONG_TX_BD |
311 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
312 TX_BD_FLAGS_COAL_NOW |
313 TX_BD_FLAGS_PACKET_END |
314 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
315
316 if (skb->ip_summed == CHECKSUM_PARTIAL)
317 tx_push1->tx_bd_hsize_lflags =
318 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
319 else
320 tx_push1->tx_bd_hsize_lflags = 0;
321
322 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
323 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
324
fbb0fa8b
MC		 325 end = pdata + length;
326 end = PTR_ALIGN(end, 8) - 1;
4419dbe6
MC		 327 *end = 0;
328
c0c050c5
MC		 329 skb_copy_from_linear_data(skb, pdata, len);
330 pdata += len;
331 for (j = 0; j < last_frag; j++) {
332 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
333 void *fptr;
334
335 fptr = skb_frag_address_safe(frag);
336 if (!fptr)
337 goto normal_tx;
338
339 memcpy(pdata, fptr, skb_frag_size(frag));
340 pdata += skb_frag_size(frag);
341 }
342
4419dbe6
MC		 343 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
344 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 345 prod = NEXT_TX(prod);
346 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
347 memcpy(txbd, tx_push1, sizeof(*txbd));
348 prod = NEXT_TX(prod);
4419dbe6 349 tx_push->doorbell =
c0c050c5
MC		 350 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
351 txr->tx_prod = prod;
352
b9a8460a 353 tx_buf->is_push = 1;
c0c050c5 354 netdev_tx_sent_queue(txq, skb->len);
b9a8460a 355 wmb(); /* Sync is_push and byte queue before pushing data */
c0c050c5 356
4419dbe6
MC		 357 push_len = (length + sizeof(*tx_push) + 7) / 8;
358 if (push_len > 16) {
359 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
9d13744b
MC		 360 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
361 (push_len - 16) << 1);
4419dbe6
MC		 362 } else {
363 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
364 push_len);
365 }
c0c050c5 366
c0c050c5
MC		 367 goto tx_done;
368 }
369
370normal_tx:
371 if (length < BNXT_MIN_PKT_SIZE) {
372 pad = BNXT_MIN_PKT_SIZE - length;
373 if (skb_pad(skb, pad)) {
374 /* SKB already freed. */
375 tx_buf->skb = NULL;
376 return NETDEV_TX_OK;
377 }
378 length = BNXT_MIN_PKT_SIZE;
379 }
380
381 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
382
383 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
384 dev_kfree_skb_any(skb);
385 tx_buf->skb = NULL;
386 return NETDEV_TX_OK;
387 }
388
389 dma_unmap_addr_set(tx_buf, mapping, mapping);
390 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
391 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
392
393 txbd->tx_bd_haddr = cpu_to_le64(mapping);
394
395 prod = NEXT_TX(prod);
396 txbd1 = (struct tx_bd_ext *)
397 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
398
399 txbd1->tx_bd_hsize_lflags = 0;
400 if (skb_is_gso(skb)) {
401 u32 hdr_len;
402
403 if (skb->encapsulation)
404 hdr_len = skb_inner_network_offset(skb) +
405 skb_inner_network_header_len(skb) +
406 inner_tcp_hdrlen(skb);
407 else
408 hdr_len = skb_transport_offset(skb) +
409 tcp_hdrlen(skb);
410
411 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
412 TX_BD_FLAGS_T_IPID |
413 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
414 length = skb_shinfo(skb)->gso_size;
415 txbd1->tx_bd_mss = cpu_to_le32(length);
416 length += hdr_len;
417 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
418 txbd1->tx_bd_hsize_lflags =
419 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
420 txbd1->tx_bd_mss = 0;
421 }
422
423 length >>= 9;
424 flags |= bnxt_lhint_arr[length];
425 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
426
427 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
428 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
429 for (i = 0; i < last_frag; i++) {
430 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
431
432 prod = NEXT_TX(prod);
433 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
434
435 len = skb_frag_size(frag);
436 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
437 DMA_TO_DEVICE);
438
439 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
440 goto tx_dma_error;
441
442 tx_buf = &txr->tx_buf_ring[prod];
443 dma_unmap_addr_set(tx_buf, mapping, mapping);
444
445 txbd->tx_bd_haddr = cpu_to_le64(mapping);
446
447 flags = len << TX_BD_LEN_SHIFT;
448 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
449 }
450
451 flags &= ~TX_BD_LEN;
452 txbd->tx_bd_len_flags_type =
453 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
454 TX_BD_FLAGS_PACKET_END);
455
456 netdev_tx_sent_queue(txq, skb->len);
457
458 /* Sync BD data before updating doorbell */
459 wmb();
460
461 prod = NEXT_TX(prod);
462 txr->tx_prod = prod;
463
464 writel(DB_KEY_TX | prod, txr->tx_doorbell);
465 writel(DB_KEY_TX | prod, txr->tx_doorbell);
466
467tx_done:
468
469 mmiowb();
470
471 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
472 netif_tx_stop_queue(txq);
473
474 /* netif_tx_stop_queue() must be done before checking
475 * tx index in bnxt_tx_avail() below, because in
476 * bnxt_tx_int(), we update tx index before checking for
477 * netif_tx_queue_stopped().
478 */
479 smp_mb();
480 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
481 netif_tx_wake_queue(txq);
482 }
483 return NETDEV_TX_OK;
484
485tx_dma_error:
486 last_frag = i;
487
488 /* start back at beginning and unmap skb */
489 prod = txr->tx_prod;
490 tx_buf = &txr->tx_buf_ring[prod];
491 tx_buf->skb = NULL;
492 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
493 skb_headlen(skb), PCI_DMA_TODEVICE);
494 prod = NEXT_TX(prod);
495
496 /* unmap remaining mapped pages */
497 for (i = 0; i < last_frag; i++) {
498 prod = NEXT_TX(prod);
499 tx_buf = &txr->tx_buf_ring[prod];
500 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
501 skb_frag_size(&skb_shinfo(skb)->frags[i]),
502 PCI_DMA_TODEVICE);
503 }
504
505 dev_kfree_skb_any(skb);
506 return NETDEV_TX_OK;
507}
508
509static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
510{
b6ab4b01 511 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
a960dec9 512 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
c0c050c5
MC		 513 u16 cons = txr->tx_cons;
514 struct pci_dev *pdev = bp->pdev;
515 int i;
516 unsigned int tx_bytes = 0;
517
518 for (i = 0; i < nr_pkts; i++) {
519 struct bnxt_sw_tx_bd *tx_buf;
520 struct sk_buff *skb;
521 int j, last;
522
523 tx_buf = &txr->tx_buf_ring[cons];
524 cons = NEXT_TX(cons);
525 skb = tx_buf->skb;
526 tx_buf->skb = NULL;
527
528 if (tx_buf->is_push) {
529 tx_buf->is_push = 0;
530 goto next_tx_int;
531 }
532
533 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
534 skb_headlen(skb), PCI_DMA_TODEVICE);
535 last = tx_buf->nr_frags;
536
537 for (j = 0; j < last; j++) {
538 cons = NEXT_TX(cons);
539 tx_buf = &txr->tx_buf_ring[cons];
540 dma_unmap_page(
541 &pdev->dev,
542 dma_unmap_addr(tx_buf, mapping),
543 skb_frag_size(&skb_shinfo(skb)->frags[j]),
544 PCI_DMA_TODEVICE);
545 }
546
547next_tx_int:
548 cons = NEXT_TX(cons);
549
550 tx_bytes += skb->len;
551 dev_kfree_skb_any(skb);
552 }
553
554 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
555 txr->tx_cons = cons;
556
557 /* Need to make the tx_cons update visible to bnxt_start_xmit()
558 * before checking for netif_tx_queue_stopped(). Without the
559 * memory barrier, there is a small possibility that bnxt_start_xmit()
560 * will miss it and cause the queue to be stopped forever.
561 */
562 smp_mb();
563
564 if (unlikely(netif_tx_queue_stopped(txq)) &&
565 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
566 __netif_tx_lock(txq, smp_processor_id());
567 if (netif_tx_queue_stopped(txq) &&
568 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
569 txr->dev_state != BNXT_DEV_STATE_CLOSING)
570 netif_tx_wake_queue(txq);
571 __netif_tx_unlock(txq);
572 }
573}
574
c61fb99c
MC		 575static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
576 gfp_t gfp)
577{
578 struct device *dev = &bp->pdev->dev;
579 struct page *page;
580
581 page = alloc_page(gfp);
582 if (!page)
583 return NULL;
584
585 *mapping = dma_map_page(dev, page, 0, PAGE_SIZE, bp->rx_dir);
586 if (dma_mapping_error(dev, *mapping)) {
587 __free_page(page);
588 return NULL;
589 }
590 *mapping += bp->rx_dma_offset;
591 return page;
592}
593
c0c050c5
MC		 594static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
595 gfp_t gfp)
596{
597 u8 *data;
598 struct pci_dev *pdev = bp->pdev;
599
600 data = kmalloc(bp->rx_buf_size, gfp);
601 if (!data)
602 return NULL;
603
b3dba77c 604 *mapping = dma_map_single(&pdev->dev, data + bp->rx_dma_offset,
745fc05c 605 bp->rx_buf_use_size, bp->rx_dir);
c0c050c5
MC		 606
607 if (dma_mapping_error(&pdev->dev, *mapping)) {
608 kfree(data);
609 data = NULL;
610 }
611 return data;
612}
613
614static inline int bnxt_alloc_rx_data(struct bnxt *bp,
615 struct bnxt_rx_ring_info *rxr,
616 u16 prod, gfp_t gfp)
617{
618 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
619 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
c0c050c5
MC		 620 dma_addr_t mapping;
621
c61fb99c
MC		 622 if (BNXT_RX_PAGE_MODE(bp)) {
623 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
c0c050c5 624
c61fb99c
MC		 625 if (!page)
626 return -ENOMEM;
627
628 rx_buf->data = page;
629 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
630 } else {
631 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
632
633 if (!data)
634 return -ENOMEM;
635
636 rx_buf->data = data;
637 rx_buf->data_ptr = data + bp->rx_offset;
638 }
11cd119d 639 rx_buf->mapping = mapping;
c0c050c5
MC		 640
641 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
c0c050c5
MC		 642 return 0;
643}
644
645static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
6bb19474 646 void *data)
c0c050c5
MC		 647{
648 u16 prod = rxr->rx_prod;
649 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
650 struct rx_bd *cons_bd, *prod_bd;
651
652 prod_rx_buf = &rxr->rx_buf_ring[prod];
653 cons_rx_buf = &rxr->rx_buf_ring[cons];
654
655 prod_rx_buf->data = data;
6bb19474 656 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
c0c050c5 657
11cd119d 658 prod_rx_buf->mapping = cons_rx_buf->mapping;
c0c050c5
MC		 659
660 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
661 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
662
663 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
664}
665
666static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
667{
668 u16 next, max = rxr->rx_agg_bmap_size;
669
670 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
671 if (next >= max)
672 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
673 return next;
674}
675
676static inline int bnxt_alloc_rx_page(struct bnxt *bp,
677 struct bnxt_rx_ring_info *rxr,
678 u16 prod, gfp_t gfp)
679{
680 struct rx_bd *rxbd =
681 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
682 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
683 struct pci_dev *pdev = bp->pdev;
684 struct page *page;
685 dma_addr_t mapping;
686 u16 sw_prod = rxr->rx_sw_agg_prod;
89d0a06c 687 unsigned int offset = 0;
c0c050c5 688
89d0a06c
MC		 689 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
690 page = rxr->rx_page;
691 if (!page) {
692 page = alloc_page(gfp);
693 if (!page)
694 return -ENOMEM;
695 rxr->rx_page = page;
696 rxr->rx_page_offset = 0;
697 }
698 offset = rxr->rx_page_offset;
699 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
700 if (rxr->rx_page_offset == PAGE_SIZE)
701 rxr->rx_page = NULL;
702 else
703 get_page(page);
704 } else {
705 page = alloc_page(gfp);
706 if (!page)
707 return -ENOMEM;
708 }
c0c050c5 709
89d0a06c 710 mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
c0c050c5
MC		 711 PCI_DMA_FROMDEVICE);
712 if (dma_mapping_error(&pdev->dev, mapping)) {
713 __free_page(page);
714 return -EIO;
715 }
716
717 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
718 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
719
720 __set_bit(sw_prod, rxr->rx_agg_bmap);
721 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
722 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
723
724 rx_agg_buf->page = page;
89d0a06c 725 rx_agg_buf->offset = offset;
c0c050c5
MC		 726 rx_agg_buf->mapping = mapping;
727 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
728 rxbd->rx_bd_opaque = sw_prod;
729 return 0;
730}
731
732static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
733 u32 agg_bufs)
734{
735 struct bnxt *bp = bnapi->bp;
736 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 737 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 738 u16 prod = rxr->rx_agg_prod;
739 u16 sw_prod = rxr->rx_sw_agg_prod;
740 u32 i;
741
742 for (i = 0; i < agg_bufs; i++) {
743 u16 cons;
744 struct rx_agg_cmp *agg;
745 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
746 struct rx_bd *prod_bd;
747 struct page *page;
748
749 agg = (struct rx_agg_cmp *)
750 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
751 cons = agg->rx_agg_cmp_opaque;
752 __clear_bit(cons, rxr->rx_agg_bmap);
753
754 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
755 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
756
757 __set_bit(sw_prod, rxr->rx_agg_bmap);
758 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
759 cons_rx_buf = &rxr->rx_agg_ring[cons];
760
761 /* It is possible for sw_prod to be equal to cons, so
762 * set cons_rx_buf->page to NULL first.
763 */
764 page = cons_rx_buf->page;
765 cons_rx_buf->page = NULL;
766 prod_rx_buf->page = page;
89d0a06c 767 prod_rx_buf->offset = cons_rx_buf->offset;
c0c050c5
MC		 768
769 prod_rx_buf->mapping = cons_rx_buf->mapping;
770
771 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
772
773 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
774 prod_bd->rx_bd_opaque = sw_prod;
775
776 prod = NEXT_RX_AGG(prod);
777 sw_prod = NEXT_RX_AGG(sw_prod);
778 cp_cons = NEXT_CMP(cp_cons);
779 }
780 rxr->rx_agg_prod = prod;
781 rxr->rx_sw_agg_prod = sw_prod;
782}
783
c61fb99c
MC		 784static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
785 struct bnxt_rx_ring_info *rxr,
786 u16 cons, void *data, u8 *data_ptr,
787 dma_addr_t dma_addr,
788 unsigned int offset_and_len)
789{
790 unsigned int payload = offset_and_len >> 16;
791 unsigned int len = offset_and_len & 0xffff;
792 struct skb_frag_struct *frag;
793 struct page *page = data;
794 u16 prod = rxr->rx_prod;
795 struct sk_buff *skb;
796 int off, err;
797
798 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
799 if (unlikely(err)) {
800 bnxt_reuse_rx_data(rxr, cons, data);
801 return NULL;
802 }
803 dma_addr -= bp->rx_dma_offset;
804 dma_unmap_page(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir);
805
806 if (unlikely(!payload))
807 payload = eth_get_headlen(data_ptr, len);
808
809 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
810 if (!skb) {
811 __free_page(page);
812 return NULL;
813 }
814
815 off = (void *)data_ptr - page_address(page);
816 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
817 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
818 payload + NET_IP_ALIGN);
819
820 frag = &skb_shinfo(skb)->frags[0];
821 skb_frag_size_sub(frag, payload);
822 frag->page_offset += payload;
823 skb->data_len -= payload;
824 skb->tail += payload;
825
826 return skb;
827}
828
c0c050c5
MC		 829static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
830 struct bnxt_rx_ring_info *rxr, u16 cons,
6bb19474
MC		 831 void *data, u8 *data_ptr,
832 dma_addr_t dma_addr,
833 unsigned int offset_and_len)
c0c050c5 834{
6bb19474 835 u16 prod = rxr->rx_prod;
c0c050c5 836 struct sk_buff *skb;
6bb19474 837 int err;
c0c050c5
MC		 838
839 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
840 if (unlikely(err)) {
841 bnxt_reuse_rx_data(rxr, cons, data);
842 return NULL;
843 }
844
845 skb = build_skb(data, 0);
846 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
745fc05c 847 bp->rx_dir);
c0c050c5
MC		 848 if (!skb) {
849 kfree(data);
850 return NULL;
851 }
852
b3dba77c 853 skb_reserve(skb, bp->rx_offset);
6bb19474 854 skb_put(skb, offset_and_len & 0xffff);
c0c050c5
MC		 855 return skb;
856}
857
858static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
859 struct sk_buff *skb, u16 cp_cons,
860 u32 agg_bufs)
861{
862 struct pci_dev *pdev = bp->pdev;
863 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 864 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 865 u16 prod = rxr->rx_agg_prod;
866 u32 i;
867
868 for (i = 0; i < agg_bufs; i++) {
869 u16 cons, frag_len;
870 struct rx_agg_cmp *agg;
871 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
872 struct page *page;
873 dma_addr_t mapping;
874
875 agg = (struct rx_agg_cmp *)
876 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
877 cons = agg->rx_agg_cmp_opaque;
878 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
879 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
880
881 cons_rx_buf = &rxr->rx_agg_ring[cons];
89d0a06c
MC		 882 skb_fill_page_desc(skb, i, cons_rx_buf->page,
883 cons_rx_buf->offset, frag_len);
c0c050c5
MC		 884 __clear_bit(cons, rxr->rx_agg_bmap);
885
886 /* It is possible for bnxt_alloc_rx_page() to allocate
887 * a sw_prod index that equals the cons index, so we
888 * need to clear the cons entry now.
889 */
11cd119d 890 mapping = cons_rx_buf->mapping;
c0c050c5
MC		 891 page = cons_rx_buf->page;
892 cons_rx_buf->page = NULL;
893
894 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
895 struct skb_shared_info *shinfo;
896 unsigned int nr_frags;
897
898 shinfo = skb_shinfo(skb);
899 nr_frags = --shinfo->nr_frags;
900 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
901
902 dev_kfree_skb(skb);
903
904 cons_rx_buf->page = page;
905
906 /* Update prod since possibly some pages have been
907 * allocated already.
908 */
909 rxr->rx_agg_prod = prod;
910 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
911 return NULL;
912 }
913
2839f28b 914 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
c0c050c5
MC		 915 PCI_DMA_FROMDEVICE);
916
917 skb->data_len += frag_len;
918 skb->len += frag_len;
919 skb->truesize += PAGE_SIZE;
920
921 prod = NEXT_RX_AGG(prod);
922 cp_cons = NEXT_CMP(cp_cons);
923 }
924 rxr->rx_agg_prod = prod;
925 return skb;
926}
927
928static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
929 u8 agg_bufs, u32 *raw_cons)
930{
931 u16 last;
932 struct rx_agg_cmp *agg;
933
934 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
935 last = RING_CMP(*raw_cons);
936 agg = (struct rx_agg_cmp *)
937 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
938 return RX_AGG_CMP_VALID(agg, *raw_cons);
939}
940
941static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
942 unsigned int len,
943 dma_addr_t mapping)
944{
945 struct bnxt *bp = bnapi->bp;
946 struct pci_dev *pdev = bp->pdev;
947 struct sk_buff *skb;
948
949 skb = napi_alloc_skb(&bnapi->napi, len);
950 if (!skb)
951 return NULL;
952
745fc05c
MC		 953 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
954 bp->rx_dir);
c0c050c5 955
6bb19474
MC		 956 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
957 len + NET_IP_ALIGN);
c0c050c5 958
745fc05c
MC		 959 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
960 bp->rx_dir);
c0c050c5
MC		 961
962 skb_put(skb, len);
963 return skb;
964}
965
fa7e2812
MC		 966static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
967 u32 *raw_cons, void *cmp)
968{
969 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
970 struct rx_cmp *rxcmp = cmp;
971 u32 tmp_raw_cons = *raw_cons;
972 u8 cmp_type, agg_bufs = 0;
973
974 cmp_type = RX_CMP_TYPE(rxcmp);
975
976 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
977 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
978 RX_CMP_AGG_BUFS) >>
979 RX_CMP_AGG_BUFS_SHIFT;
980 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
981 struct rx_tpa_end_cmp *tpa_end = cmp;
982
983 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
984 RX_TPA_END_CMP_AGG_BUFS) >>
985 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
986 }
987
988 if (agg_bufs) {
989 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
990 return -EBUSY;
991 }
992 *raw_cons = tmp_raw_cons;
993 return 0;
994}
995
996static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
997{
998 if (!rxr->bnapi->in_reset) {
999 rxr->bnapi->in_reset = true;
1000 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1001 schedule_work(&bp->sp_task);
1002 }
1003 rxr->rx_next_cons = 0xffff;
1004}
1005
c0c050c5
MC		 1006static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1007 struct rx_tpa_start_cmp *tpa_start,
1008 struct rx_tpa_start_cmp_ext *tpa_start1)
1009{
1010 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1011 u16 cons, prod;
1012 struct bnxt_tpa_info *tpa_info;
1013 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1014 struct rx_bd *prod_bd;
1015 dma_addr_t mapping;
1016
1017 cons = tpa_start->rx_tpa_start_cmp_opaque;
1018 prod = rxr->rx_prod;
1019 cons_rx_buf = &rxr->rx_buf_ring[cons];
1020 prod_rx_buf = &rxr->rx_buf_ring[prod];
1021 tpa_info = &rxr->rx_tpa[agg_id];
1022
fa7e2812
MC		 1023 if (unlikely(cons != rxr->rx_next_cons)) {
1024 bnxt_sched_reset(bp, rxr);
1025 return;
1026 }
1027
c0c050c5 1028 prod_rx_buf->data = tpa_info->data;
6bb19474 1029 prod_rx_buf->data_ptr = tpa_info->data_ptr;
c0c050c5
MC		 1030
1031 mapping = tpa_info->mapping;
11cd119d 1032 prod_rx_buf->mapping = mapping;
c0c050c5
MC		 1033
1034 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1035
1036 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1037
1038 tpa_info->data = cons_rx_buf->data;
6bb19474 1039 tpa_info->data_ptr = cons_rx_buf->data_ptr;
c0c050c5 1040 cons_rx_buf->data = NULL;
11cd119d 1041 tpa_info->mapping = cons_rx_buf->mapping;
c0c050c5
MC		 1042
1043 tpa_info->len =
1044 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1045 RX_TPA_START_CMP_LEN_SHIFT;
1046 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1047 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1048
1049 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1050 tpa_info->gso_type = SKB_GSO_TCPV4;
1051 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1052 if (hash_type == 3)
1053 tpa_info->gso_type = SKB_GSO_TCPV6;
1054 tpa_info->rss_hash =
1055 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1056 } else {
1057 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1058 tpa_info->gso_type = 0;
1059 if (netif_msg_rx_err(bp))
1060 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1061 }
1062 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1063 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
94758f8d 1064 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
c0c050c5
MC		 1065
1066 rxr->rx_prod = NEXT_RX(prod);
1067 cons = NEXT_RX(cons);
376a5b86 1068 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1069 cons_rx_buf = &rxr->rx_buf_ring[cons];
1070
1071 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1072 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1073 cons_rx_buf->data = NULL;
1074}
1075
1076static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1077 u16 cp_cons, u32 agg_bufs)
1078{
1079 if (agg_bufs)
1080 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1081}
1082
94758f8d
MC		 1083static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1084 int payload_off, int tcp_ts,
1085 struct sk_buff *skb)
1086{
1087#ifdef CONFIG_INET
1088 struct tcphdr *th;
1089 int len, nw_off;
1090 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1091 u32 hdr_info = tpa_info->hdr_info;
1092 bool loopback = false;
1093
1094 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1095 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1096 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1097
1098 /* If the packet is an internal loopback packet, the offsets will
1099 * have an extra 4 bytes.
1100 */
1101 if (inner_mac_off == 4) {
1102 loopback = true;
1103 } else if (inner_mac_off > 4) {
1104 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1105 ETH_HLEN - 2));
1106
1107 /* We only support inner iPv4/ipv6. If we don't see the
1108 * correct protocol ID, it must be a loopback packet where
1109 * the offsets are off by 4.
1110 */
09a7636a 1111 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
94758f8d
MC		 1112 loopback = true;
1113 }
1114 if (loopback) {
1115 /* internal loopback packet, subtract all offsets by 4 */
1116 inner_ip_off -= 4;
1117 inner_mac_off -= 4;
1118 outer_ip_off -= 4;
1119 }
1120
1121 nw_off = inner_ip_off - ETH_HLEN;
1122 skb_set_network_header(skb, nw_off);
1123 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1124 struct ipv6hdr *iph = ipv6_hdr(skb);
1125
1126 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1127 len = skb->len - skb_transport_offset(skb);
1128 th = tcp_hdr(skb);
1129 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1130 } else {
1131 struct iphdr *iph = ip_hdr(skb);
1132
1133 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1134 len = skb->len - skb_transport_offset(skb);
1135 th = tcp_hdr(skb);
1136 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1137 }
1138
1139 if (inner_mac_off) { /* tunnel */
1140 struct udphdr *uh = NULL;
1141 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1142 ETH_HLEN - 2));
1143
1144 if (proto == htons(ETH_P_IP)) {
1145 struct iphdr *iph = (struct iphdr *)skb->data;
1146
1147 if (iph->protocol == IPPROTO_UDP)
1148 uh = (struct udphdr *)(iph + 1);
1149 } else {
1150 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1151
1152 if (iph->nexthdr == IPPROTO_UDP)
1153 uh = (struct udphdr *)(iph + 1);
1154 }
1155 if (uh) {
1156 if (uh->check)
1157 skb_shinfo(skb)->gso_type |=
1158 SKB_GSO_UDP_TUNNEL_CSUM;
1159 else
1160 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1161 }
1162 }
1163#endif
1164 return skb;
1165}
1166
c0c050c5
MC		 1167#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1168#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1169
309369c9
MC		 1170static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1171 int payload_off, int tcp_ts,
c0c050c5
MC		 1172 struct sk_buff *skb)
1173{
d1611c3a 1174#ifdef CONFIG_INET
c0c050c5 1175 struct tcphdr *th;
719ca811 1176 int len, nw_off, tcp_opt_len = 0;
27e24189 1177
309369c9 1178 if (tcp_ts)
c0c050c5
MC		 1179 tcp_opt_len = 12;
1180
c0c050c5
MC		 1181 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1182 struct iphdr *iph;
1183
1184 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1185 ETH_HLEN;
1186 skb_set_network_header(skb, nw_off);
1187 iph = ip_hdr(skb);
1188 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1189 len = skb->len - skb_transport_offset(skb);
1190 th = tcp_hdr(skb);
1191 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1192 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1193 struct ipv6hdr *iph;
1194
1195 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1196 ETH_HLEN;
1197 skb_set_network_header(skb, nw_off);
1198 iph = ipv6_hdr(skb);
1199 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1200 len = skb->len - skb_transport_offset(skb);
1201 th = tcp_hdr(skb);
1202 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1203 } else {
1204 dev_kfree_skb_any(skb);
1205 return NULL;
1206 }
c0c050c5
MC		 1207
1208 if (nw_off) { /* tunnel */
1209 struct udphdr *uh = NULL;
1210
1211 if (skb->protocol == htons(ETH_P_IP)) {
1212 struct iphdr *iph = (struct iphdr *)skb->data;
1213
1214 if (iph->protocol == IPPROTO_UDP)
1215 uh = (struct udphdr *)(iph + 1);
1216 } else {
1217 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1218
1219 if (iph->nexthdr == IPPROTO_UDP)
1220 uh = (struct udphdr *)(iph + 1);
1221 }
1222 if (uh) {
1223 if (uh->check)
1224 skb_shinfo(skb)->gso_type |=
1225 SKB_GSO_UDP_TUNNEL_CSUM;
1226 else
1227 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1228 }
1229 }
1230#endif
1231 return skb;
1232}
1233
309369c9
MC		 1234static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1235 struct bnxt_tpa_info *tpa_info,
1236 struct rx_tpa_end_cmp *tpa_end,
1237 struct rx_tpa_end_cmp_ext *tpa_end1,
1238 struct sk_buff *skb)
1239{
1240#ifdef CONFIG_INET
1241 int payload_off;
1242 u16 segs;
1243
1244 segs = TPA_END_TPA_SEGS(tpa_end);
1245 if (segs == 1)
1246 return skb;
1247
1248 NAPI_GRO_CB(skb)->count = segs;
1249 skb_shinfo(skb)->gso_size =
1250 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1251 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1252 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1253 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1254 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1255 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
5910906c
MC		 1256 if (likely(skb))
1257 tcp_gro_complete(skb);
309369c9
MC		 1258#endif
1259 return skb;
1260}
1261
c0c050c5
MC		 1262static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1263 struct bnxt_napi *bnapi,
1264 u32 *raw_cons,
1265 struct rx_tpa_end_cmp *tpa_end,
1266 struct rx_tpa_end_cmp_ext *tpa_end1,
4e5dbbda 1267 u8 *event)
c0c050c5
MC		 1268{
1269 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1270 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5 1271 u8 agg_id = TPA_END_AGG_ID(tpa_end);
6bb19474 1272 u8 *data_ptr, agg_bufs;
c0c050c5
MC		 1273 u16 cp_cons = RING_CMP(*raw_cons);
1274 unsigned int len;
1275 struct bnxt_tpa_info *tpa_info;
1276 dma_addr_t mapping;
1277 struct sk_buff *skb;
6bb19474 1278 void *data;
c0c050c5 1279
fa7e2812
MC		 1280 if (unlikely(bnapi->in_reset)) {
1281 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1282
1283 if (rc < 0)
1284 return ERR_PTR(-EBUSY);
1285 return NULL;
1286 }
1287
c0c050c5
MC		 1288 tpa_info = &rxr->rx_tpa[agg_id];
1289 data = tpa_info->data;
6bb19474
MC		 1290 data_ptr = tpa_info->data_ptr;
1291 prefetch(data_ptr);
c0c050c5
MC		 1292 len = tpa_info->len;
1293 mapping = tpa_info->mapping;
1294
1295 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1296 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1297
1298 if (agg_bufs) {
1299 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1300 return ERR_PTR(-EBUSY);
1301
4e5dbbda 1302 *event |= BNXT_AGG_EVENT;
c0c050c5
MC		 1303 cp_cons = NEXT_CMP(cp_cons);
1304 }
1305
1306 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1307 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1308 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1309 agg_bufs, (int)MAX_SKB_FRAGS);
1310 return NULL;
1311 }
1312
1313 if (len <= bp->rx_copy_thresh) {
6bb19474 1314 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
c0c050c5
MC		 1315 if (!skb) {
1316 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1317 return NULL;
1318 }
1319 } else {
1320 u8 *new_data;
1321 dma_addr_t new_mapping;
1322
1323 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1324 if (!new_data) {
1325 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1326 return NULL;
1327 }
1328
1329 tpa_info->data = new_data;
b3dba77c 1330 tpa_info->data_ptr = new_data + bp->rx_offset;
c0c050c5
MC		 1331 tpa_info->mapping = new_mapping;
1332
1333 skb = build_skb(data, 0);
1334 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
745fc05c 1335 bp->rx_dir);
c0c050c5
MC		 1336
1337 if (!skb) {
1338 kfree(data);
1339 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1340 return NULL;
1341 }
b3dba77c 1342 skb_reserve(skb, bp->rx_offset);
c0c050c5
MC		 1343 skb_put(skb, len);
1344 }
1345
1346 if (agg_bufs) {
1347 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1348 if (!skb) {
1349 /* Page reuse already handled by bnxt_rx_pages(). */
1350 return NULL;
1351 }
1352 }
1353 skb->protocol = eth_type_trans(skb, bp->dev);
1354
1355 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1356 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1357
8852ddb4
MC		 1358 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1359 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5
MC		 1360 u16 vlan_proto = tpa_info->metadata >>
1361 RX_CMP_FLAGS2_METADATA_TPID_SFT;
8852ddb4 1362 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5 1363
8852ddb4 1364 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1365 }
1366
1367 skb_checksum_none_assert(skb);
1368 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1369 skb->ip_summed = CHECKSUM_UNNECESSARY;
1370 skb->csum_level =
1371 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1372 }
1373
1374 if (TPA_END_GRO(tpa_end))
309369c9 1375 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
c0c050c5
MC		 1376
1377 return skb;
1378}
1379
1380/* returns the following:
1381 * 1 - 1 packet successfully received
1382 * 0 - successful TPA_START, packet not completed yet
1383 * -EBUSY - completion ring does not have all the agg buffers yet
1384 * -ENOMEM - packet aborted due to out of memory
1385 * -EIO - packet aborted due to hw error indicated in BD
1386 */
1387static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
4e5dbbda 1388 u8 *event)
c0c050c5
MC		 1389{
1390 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1391 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1392 struct net_device *dev = bp->dev;
1393 struct rx_cmp *rxcmp;
1394 struct rx_cmp_ext *rxcmp1;
1395 u32 tmp_raw_cons = *raw_cons;
1396 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1397 struct bnxt_sw_rx_bd *rx_buf;
1398 unsigned int len;
6bb19474 1399 u8 *data_ptr, agg_bufs, cmp_type;
c0c050c5
MC		 1400 dma_addr_t dma_addr;
1401 struct sk_buff *skb;
6bb19474 1402 void *data;
c0c050c5 1403 int rc = 0;
c61fb99c 1404 u32 misc;
c0c050c5
MC		 1405
1406 rxcmp = (struct rx_cmp *)
1407 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1408
1409 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1410 cp_cons = RING_CMP(tmp_raw_cons);
1411 rxcmp1 = (struct rx_cmp_ext *)
1412 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1413
1414 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1415 return -EBUSY;
1416
1417 cmp_type = RX_CMP_TYPE(rxcmp);
1418
1419 prod = rxr->rx_prod;
1420
1421 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1422 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1423 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1424
4e5dbbda 1425 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1426 goto next_rx_no_prod;
1427
1428 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1429 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1430 (struct rx_tpa_end_cmp *)rxcmp,
4e5dbbda 1431 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
c0c050c5
MC		 1432
1433 if (unlikely(IS_ERR(skb)))
1434 return -EBUSY;
1435
1436 rc = -ENOMEM;
1437 if (likely(skb)) {
1438 skb_record_rx_queue(skb, bnapi->index);
b356a2e7 1439 napi_gro_receive(&bnapi->napi, skb);
c0c050c5
MC		 1440 rc = 1;
1441 }
4e5dbbda 1442 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1443 goto next_rx_no_prod;
1444 }
1445
1446 cons = rxcmp->rx_cmp_opaque;
1447 rx_buf = &rxr->rx_buf_ring[cons];
1448 data = rx_buf->data;
6bb19474 1449 data_ptr = rx_buf->data_ptr;
fa7e2812
MC		 1450 if (unlikely(cons != rxr->rx_next_cons)) {
1451 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1452
1453 bnxt_sched_reset(bp, rxr);
1454 return rc1;
1455 }
6bb19474 1456 prefetch(data_ptr);
c0c050c5 1457
c61fb99c
MC		 1458 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1459 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
c0c050c5
MC		 1460
1461 if (agg_bufs) {
1462 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1463 return -EBUSY;
1464
1465 cp_cons = NEXT_CMP(cp_cons);
4e5dbbda 1466 *event |= BNXT_AGG_EVENT;
c0c050c5 1467 }
4e5dbbda 1468 *event |= BNXT_RX_EVENT;
c0c050c5
MC		 1469
1470 rx_buf->data = NULL;
1471 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1472 bnxt_reuse_rx_data(rxr, cons, data);
1473 if (agg_bufs)
1474 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1475
1476 rc = -EIO;
1477 goto next_rx;
1478 }
1479
1480 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
11cd119d 1481 dma_addr = rx_buf->mapping;
c0c050c5
MC		 1482
1483 if (len <= bp->rx_copy_thresh) {
6bb19474 1484 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
c0c050c5
MC		 1485 bnxt_reuse_rx_data(rxr, cons, data);
1486 if (!skb) {
1487 rc = -ENOMEM;
1488 goto next_rx;
1489 }
1490 } else {
c61fb99c
MC		 1491 u32 payload;
1492
1493 payload = misc & RX_CMP_PAYLOAD_OFFSET;
6bb19474 1494 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
c61fb99c 1495 payload | len);
c0c050c5
MC		 1496 if (!skb) {
1497 rc = -ENOMEM;
1498 goto next_rx;
1499 }
1500 }
1501
1502 if (agg_bufs) {
1503 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1504 if (!skb) {
1505 rc = -ENOMEM;
1506 goto next_rx;
1507 }
1508 }
1509
1510 if (RX_CMP_HASH_VALID(rxcmp)) {
1511 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1512 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1513
1514 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1515 if (hash_type != 1 && hash_type != 3)
1516 type = PKT_HASH_TYPE_L3;
1517 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1518 }
1519
1520 skb->protocol = eth_type_trans(skb, dev);
1521
8852ddb4
MC		 1522 if ((rxcmp1->rx_cmp_flags2 &
1523 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1524 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5 1525 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
8852ddb4 1526 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5
MC		 1527 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1528
8852ddb4 1529 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1530 }
1531
1532 skb_checksum_none_assert(skb);
1533 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1534 if (dev->features & NETIF_F_RXCSUM) {
1535 skb->ip_summed = CHECKSUM_UNNECESSARY;
1536 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1537 }
1538 } else {
665e350d
SB		 1539 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1540 if (dev->features & NETIF_F_RXCSUM)
1541 cpr->rx_l4_csum_errors++;
1542 }
c0c050c5
MC		 1543 }
1544
1545 skb_record_rx_queue(skb, bnapi->index);
b356a2e7 1546 napi_gro_receive(&bnapi->napi, skb);
c0c050c5
MC		 1547 rc = 1;
1548
1549next_rx:
1550 rxr->rx_prod = NEXT_RX(prod);
376a5b86 1551 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1552
1553next_rx_no_prod:
1554 *raw_cons = tmp_raw_cons;
1555
1556 return rc;
1557}
1558
4bb13abf 1559#define BNXT_GET_EVENT_PORT(data) \
87c374de
MC		 1560 ((data) & \
1561 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
4bb13abf 1562
c0c050c5
MC		 1563static int bnxt_async_event_process(struct bnxt *bp,
1564 struct hwrm_async_event_cmpl *cmpl)
1565{
1566 u16 event_id = le16_to_cpu(cmpl->event_id);
1567
1568 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1569 switch (event_id) {
87c374de 1570 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
8cbde117
MC		 1571 u32 data1 = le32_to_cpu(cmpl->event_data1);
1572 struct bnxt_link_info *link_info = &bp->link_info;
1573
1574 if (BNXT_VF(bp))
1575 goto async_event_process_exit;
1576 if (data1 & 0x20000) {
1577 u16 fw_speed = link_info->force_link_speed;
1578 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1579
1580 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1581 speed);
1582 }
286ef9d6 1583 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
8cbde117
MC		 1584 /* fall thru */
1585 }
87c374de 1586 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
c0c050c5 1587 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368 1588 break;
87c374de 1589 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
19241368 1590 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5 1591 break;
87c374de 1592 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
4bb13abf
MC		 1593 u32 data1 = le32_to_cpu(cmpl->event_data1);
1594 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1595
1596 if (BNXT_VF(bp))
1597 break;
1598
1599 if (bp->pf.port_id != port_id)
1600 break;
1601
4bb13abf
MC		 1602 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1603 break;
1604 }
87c374de 1605 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
fc0f1929
MC		 1606 if (BNXT_PF(bp))
1607 goto async_event_process_exit;
1608 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1609 break;
c0c050c5 1610 default:
19241368 1611 goto async_event_process_exit;
c0c050c5 1612 }
19241368
JH		 1613 schedule_work(&bp->sp_task);
1614async_event_process_exit:
a588e458 1615 bnxt_ulp_async_events(bp, cmpl);
c0c050c5
MC		 1616 return 0;
1617}
1618
1619static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1620{
1621 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1622 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1623 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1624 (struct hwrm_fwd_req_cmpl *)txcmp;
1625
1626 switch (cmpl_type) {
1627 case CMPL_BASE_TYPE_HWRM_DONE:
1628 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1629 if (seq_id == bp->hwrm_intr_seq_id)
1630 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1631 else
1632 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1633 break;
1634
1635 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1636 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1637
1638 if ((vf_id < bp->pf.first_vf_id) ||
1639 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1640 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1641 vf_id);
1642 return -EINVAL;
1643 }
1644
1645 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1646 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1647 schedule_work(&bp->sp_task);
1648 break;
1649
1650 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1651 bnxt_async_event_process(bp,
1652 (struct hwrm_async_event_cmpl *)txcmp);
1653
1654 default:
1655 break;
1656 }
1657
1658 return 0;
1659}
1660
1661static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1662{
1663 struct bnxt_napi *bnapi = dev_instance;
1664 struct bnxt *bp = bnapi->bp;
1665 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1666 u32 cons = RING_CMP(cpr->cp_raw_cons);
1667
1668 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1669 napi_schedule(&bnapi->napi);
1670 return IRQ_HANDLED;
1671}
1672
1673static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1674{
1675 u32 raw_cons = cpr->cp_raw_cons;
1676 u16 cons = RING_CMP(raw_cons);
1677 struct tx_cmp *txcmp;
1678
1679 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1680
1681 return TX_CMP_VALID(txcmp, raw_cons);
1682}
1683
c0c050c5
MC		 1684static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1685{
1686 struct bnxt_napi *bnapi = dev_instance;
1687 struct bnxt *bp = bnapi->bp;
1688 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1689 u32 cons = RING_CMP(cpr->cp_raw_cons);
1690 u32 int_status;
1691
1692 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1693
1694 if (!bnxt_has_work(bp, cpr)) {
11809490 1695 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1696 /* return if erroneous interrupt */
1697 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1698 return IRQ_NONE;
1699 }
1700
1701 /* disable ring IRQ */
1702 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1703
1704 /* Return here if interrupt is shared and is disabled. */
1705 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1706 return IRQ_HANDLED;
1707
1708 napi_schedule(&bnapi->napi);
1709 return IRQ_HANDLED;
1710}
1711
1712static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1713{
1714 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1715 u32 raw_cons = cpr->cp_raw_cons;
1716 u32 cons;
1717 int tx_pkts = 0;
1718 int rx_pkts = 0;
4e5dbbda 1719 u8 event = 0;
c0c050c5
MC		 1720 struct tx_cmp *txcmp;
1721
1722 while (1) {
1723 int rc;
1724
1725 cons = RING_CMP(raw_cons);
1726 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1727
1728 if (!TX_CMP_VALID(txcmp, raw_cons))
1729 break;
1730
67a95e20
MC		 1731 /* The valid test of the entry must be done first before
1732 * reading any further.
1733 */
b67daab0 1734 dma_rmb();
c0c050c5
MC		 1735 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1736 tx_pkts++;
1737 /* return full budget so NAPI will complete. */
1738 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1739 rx_pkts = budget;
1740 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
4e5dbbda 1741 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
c0c050c5
MC		 1742 if (likely(rc >= 0))
1743 rx_pkts += rc;
1744 else if (rc == -EBUSY) /* partial completion */
1745 break;
c0c050c5
MC		 1746 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1747 CMPL_BASE_TYPE_HWRM_DONE) ||
1748 (TX_CMP_TYPE(txcmp) ==
1749 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1750 (TX_CMP_TYPE(txcmp) ==
1751 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1752 bnxt_hwrm_handler(bp, txcmp);
1753 }
1754 raw_cons = NEXT_RAW_CMP(raw_cons);
1755
1756 if (rx_pkts == budget)
1757 break;
1758 }
1759
1760 cpr->cp_raw_cons = raw_cons;
1761 /* ACK completion ring before freeing tx ring and producing new
1762 * buffers in rx/agg rings to prevent overflowing the completion
1763 * ring.
1764 */
1765 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1766
1767 if (tx_pkts)
fa3e93e8 1768 bnapi->tx_int(bp, bnapi, tx_pkts);
c0c050c5 1769
4e5dbbda 1770 if (event & BNXT_RX_EVENT) {
b6ab4b01 1771 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1772
1773 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1774 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4e5dbbda 1775 if (event & BNXT_AGG_EVENT) {
c0c050c5
MC		 1776 writel(DB_KEY_RX | rxr->rx_agg_prod,
1777 rxr->rx_agg_doorbell);
1778 writel(DB_KEY_RX | rxr->rx_agg_prod,
1779 rxr->rx_agg_doorbell);
1780 }
1781 }
1782 return rx_pkts;
1783}
1784
10bbdaf5
PS		 1785static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1786{
1787 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1788 struct bnxt *bp = bnapi->bp;
1789 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1790 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1791 struct tx_cmp *txcmp;
1792 struct rx_cmp_ext *rxcmp1;
1793 u32 cp_cons, tmp_raw_cons;
1794 u32 raw_cons = cpr->cp_raw_cons;
1795 u32 rx_pkts = 0;
4e5dbbda 1796 u8 event = 0;
10bbdaf5
PS		 1797
1798 while (1) {
1799 int rc;
1800
1801 cp_cons = RING_CMP(raw_cons);
1802 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1803
1804 if (!TX_CMP_VALID(txcmp, raw_cons))
1805 break;
1806
1807 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1808 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1809 cp_cons = RING_CMP(tmp_raw_cons);
1810 rxcmp1 = (struct rx_cmp_ext *)
1811 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1812
1813 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1814 break;
1815
1816 /* force an error to recycle the buffer */
1817 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1818 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1819
4e5dbbda 1820 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
10bbdaf5
PS		 1821 if (likely(rc == -EIO))
1822 rx_pkts++;
1823 else if (rc == -EBUSY) /* partial completion */
1824 break;
1825 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1826 CMPL_BASE_TYPE_HWRM_DONE)) {
1827 bnxt_hwrm_handler(bp, txcmp);
1828 } else {
1829 netdev_err(bp->dev,
1830 "Invalid completion received on special ring\n");
1831 }
1832 raw_cons = NEXT_RAW_CMP(raw_cons);
1833
1834 if (rx_pkts == budget)
1835 break;
1836 }
1837
1838 cpr->cp_raw_cons = raw_cons;
1839 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1840 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1841 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1842
4e5dbbda 1843 if (event & BNXT_AGG_EVENT) {
10bbdaf5
PS		 1844 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1845 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1846 }
1847
1848 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
6ad20165 1849 napi_complete_done(napi, rx_pkts);
10bbdaf5
PS		 1850 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1851 }
1852 return rx_pkts;
1853}
1854
c0c050c5
MC		 1855static int bnxt_poll(struct napi_struct *napi, int budget)
1856{
1857 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1858 struct bnxt *bp = bnapi->bp;
1859 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1860 int work_done = 0;
1861
c0c050c5
MC		 1862 while (1) {
1863 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1864
1865 if (work_done >= budget)
1866 break;
1867
1868 if (!bnxt_has_work(bp, cpr)) {
e7b95691
MC		 1869 if (napi_complete_done(napi, work_done))
1870 BNXT_CP_DB_REARM(cpr->cp_doorbell,
1871 cpr->cp_raw_cons);
c0c050c5
MC		 1872 break;
1873 }
1874 }
1875 mmiowb();
c0c050c5
MC		 1876 return work_done;
1877}
1878
c0c050c5
MC		 1879static void bnxt_free_tx_skbs(struct bnxt *bp)
1880{
1881 int i, max_idx;
1882 struct pci_dev *pdev = bp->pdev;
1883
b6ab4b01 1884 if (!bp->tx_ring)
c0c050c5
MC		 1885 return;
1886
1887 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1888 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1889 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1890 int j;
1891
c0c050c5
MC		 1892 for (j = 0; j < max_idx;) {
1893 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1894 struct sk_buff *skb = tx_buf->skb;
1895 int k, last;
1896
1897 if (!skb) {
1898 j++;
1899 continue;
1900 }
1901
1902 tx_buf->skb = NULL;
1903
1904 if (tx_buf->is_push) {
1905 dev_kfree_skb(skb);
1906 j += 2;
1907 continue;
1908 }
1909
1910 dma_unmap_single(&pdev->dev,
1911 dma_unmap_addr(tx_buf, mapping),
1912 skb_headlen(skb),
1913 PCI_DMA_TODEVICE);
1914
1915 last = tx_buf->nr_frags;
1916 j += 2;
d612a579
MC		 1917 for (k = 0; k < last; k++, j++) {
1918 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 1919 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1920
d612a579 1921 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 1922 dma_unmap_page(
1923 &pdev->dev,
1924 dma_unmap_addr(tx_buf, mapping),
1925 skb_frag_size(frag), PCI_DMA_TODEVICE);
1926 }
1927 dev_kfree_skb(skb);
1928 }
1929 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1930 }
1931}
1932
1933static void bnxt_free_rx_skbs(struct bnxt *bp)
1934{
1935 int i, max_idx, max_agg_idx;
1936 struct pci_dev *pdev = bp->pdev;
1937
b6ab4b01 1938 if (!bp->rx_ring)
c0c050c5
MC		 1939 return;
1940
1941 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1942 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1943 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1944 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1945 int j;
1946
c0c050c5
MC		 1947 if (rxr->rx_tpa) {
1948 for (j = 0; j < MAX_TPA; j++) {
1949 struct bnxt_tpa_info *tpa_info =
1950 &rxr->rx_tpa[j];
1951 u8 *data = tpa_info->data;
1952
1953 if (!data)
1954 continue;
1955
745fc05c
MC		 1956 dma_unmap_single(&pdev->dev, tpa_info->mapping,
1957 bp->rx_buf_use_size,
1958 bp->rx_dir);
c0c050c5
MC		 1959
1960 tpa_info->data = NULL;
1961
1962 kfree(data);
1963 }
1964 }
1965
1966 for (j = 0; j < max_idx; j++) {
1967 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
6bb19474 1968 void *data = rx_buf->data;
c0c050c5
MC		 1969
1970 if (!data)
1971 continue;
1972
11cd119d 1973 dma_unmap_single(&pdev->dev, rx_buf->mapping,
745fc05c 1974 bp->rx_buf_use_size, bp->rx_dir);
c0c050c5
MC		 1975
1976 rx_buf->data = NULL;
1977
c61fb99c
MC		 1978 if (BNXT_RX_PAGE_MODE(bp))
1979 __free_page(data);
1980 else
1981 kfree(data);
c0c050c5
MC		 1982 }
1983
1984 for (j = 0; j < max_agg_idx; j++) {
1985 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1986 &rxr->rx_agg_ring[j];
1987 struct page *page = rx_agg_buf->page;
1988
1989 if (!page)
1990 continue;
1991
11cd119d 1992 dma_unmap_page(&pdev->dev, rx_agg_buf->mapping,
2839f28b 1993 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
c0c050c5
MC		 1994
1995 rx_agg_buf->page = NULL;
1996 __clear_bit(j, rxr->rx_agg_bmap);
1997
1998 __free_page(page);
1999 }
89d0a06c
MC		 2000 if (rxr->rx_page) {
2001 __free_page(rxr->rx_page);
2002 rxr->rx_page = NULL;
2003 }
c0c050c5
MC		 2004 }
2005}
2006
2007static void bnxt_free_skbs(struct bnxt *bp)
2008{
2009 bnxt_free_tx_skbs(bp);
2010 bnxt_free_rx_skbs(bp);
2011}
2012
2013static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2014{
2015 struct pci_dev *pdev = bp->pdev;
2016 int i;
2017
2018 for (i = 0; i < ring->nr_pages; i++) {
2019 if (!ring->pg_arr[i])
2020 continue;
2021
2022 dma_free_coherent(&pdev->dev, ring->page_size,
2023 ring->pg_arr[i], ring->dma_arr[i]);
2024
2025 ring->pg_arr[i] = NULL;
2026 }
2027 if (ring->pg_tbl) {
2028 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2029 ring->pg_tbl, ring->pg_tbl_map);
2030 ring->pg_tbl = NULL;
2031 }
2032 if (ring->vmem_size && *ring->vmem) {
2033 vfree(*ring->vmem);
2034 *ring->vmem = NULL;
2035 }
2036}
2037
2038static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2039{
2040 int i;
2041 struct pci_dev *pdev = bp->pdev;
2042
2043 if (ring->nr_pages > 1) {
2044 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2045 ring->nr_pages * 8,
2046 &ring->pg_tbl_map,
2047 GFP_KERNEL);
2048 if (!ring->pg_tbl)
2049 return -ENOMEM;
2050 }
2051
2052 for (i = 0; i < ring->nr_pages; i++) {
2053 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2054 ring->page_size,
2055 &ring->dma_arr[i],
2056 GFP_KERNEL);
2057 if (!ring->pg_arr[i])
2058 return -ENOMEM;
2059
2060 if (ring->nr_pages > 1)
2061 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2062 }
2063
2064 if (ring->vmem_size) {
2065 *ring->vmem = vzalloc(ring->vmem_size);
2066 if (!(*ring->vmem))
2067 return -ENOMEM;
2068 }
2069 return 0;
2070}
2071
2072static void bnxt_free_rx_rings(struct bnxt *bp)
2073{
2074 int i;
2075
b6ab4b01 2076 if (!bp->rx_ring)
c0c050c5
MC		 2077 return;
2078
2079 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2080 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2081 struct bnxt_ring_struct *ring;
2082
c0c050c5
MC		 2083 kfree(rxr->rx_tpa);
2084 rxr->rx_tpa = NULL;
2085
2086 kfree(rxr->rx_agg_bmap);
2087 rxr->rx_agg_bmap = NULL;
2088
2089 ring = &rxr->rx_ring_struct;
2090 bnxt_free_ring(bp, ring);
2091
2092 ring = &rxr->rx_agg_ring_struct;
2093 bnxt_free_ring(bp, ring);
2094 }
2095}
2096
2097static int bnxt_alloc_rx_rings(struct bnxt *bp)
2098{
2099 int i, rc, agg_rings = 0, tpa_rings = 0;
2100
b6ab4b01
MC		 2101 if (!bp->rx_ring)
2102 return -ENOMEM;
2103
c0c050c5
MC		 2104 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2105 agg_rings = 1;
2106
2107 if (bp->flags & BNXT_FLAG_TPA)
2108 tpa_rings = 1;
2109
2110 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2111 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2112 struct bnxt_ring_struct *ring;
2113
c0c050c5
MC		 2114 ring = &rxr->rx_ring_struct;
2115
2116 rc = bnxt_alloc_ring(bp, ring);
2117 if (rc)
2118 return rc;
2119
2120 if (agg_rings) {
2121 u16 mem_size;
2122
2123 ring = &rxr->rx_agg_ring_struct;
2124 rc = bnxt_alloc_ring(bp, ring);
2125 if (rc)
2126 return rc;
2127
2128 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2129 mem_size = rxr->rx_agg_bmap_size / 8;
2130 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2131 if (!rxr->rx_agg_bmap)
2132 return -ENOMEM;
2133
2134 if (tpa_rings) {
2135 rxr->rx_tpa = kcalloc(MAX_TPA,
2136 sizeof(struct bnxt_tpa_info),
2137 GFP_KERNEL);
2138 if (!rxr->rx_tpa)
2139 return -ENOMEM;
2140 }
2141 }
2142 }
2143 return 0;
2144}
2145
2146static void bnxt_free_tx_rings(struct bnxt *bp)
2147{
2148 int i;
2149 struct pci_dev *pdev = bp->pdev;
2150
b6ab4b01 2151 if (!bp->tx_ring)
c0c050c5
MC		 2152 return;
2153
2154 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2155 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2156 struct bnxt_ring_struct *ring;
2157
c0c050c5
MC		 2158 if (txr->tx_push) {
2159 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2160 txr->tx_push, txr->tx_push_mapping);
2161 txr->tx_push = NULL;
2162 }
2163
2164 ring = &txr->tx_ring_struct;
2165
2166 bnxt_free_ring(bp, ring);
2167 }
2168}
2169
2170static int bnxt_alloc_tx_rings(struct bnxt *bp)
2171{
2172 int i, j, rc;
2173 struct pci_dev *pdev = bp->pdev;
2174
2175 bp->tx_push_size = 0;
2176 if (bp->tx_push_thresh) {
2177 int push_size;
2178
2179 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2180 bp->tx_push_thresh);
2181
4419dbe6 2182 if (push_size > 256) {
c0c050c5
MC		 2183 push_size = 0;
2184 bp->tx_push_thresh = 0;
2185 }
2186
2187 bp->tx_push_size = push_size;
2188 }
2189
2190 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2191 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2192 struct bnxt_ring_struct *ring;
2193
c0c050c5
MC		 2194 ring = &txr->tx_ring_struct;
2195
2196 rc = bnxt_alloc_ring(bp, ring);
2197 if (rc)
2198 return rc;
2199
2200 if (bp->tx_push_size) {
c0c050c5
MC		 2201 dma_addr_t mapping;
2202
2203 /* One pre-allocated DMA buffer to backup
2204 * TX push operation
2205 */
2206 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2207 bp->tx_push_size,
2208 &txr->tx_push_mapping,
2209 GFP_KERNEL);
2210
2211 if (!txr->tx_push)
2212 return -ENOMEM;
2213
c0c050c5
MC		 2214 mapping = txr->tx_push_mapping +
2215 sizeof(struct tx_push_bd);
4419dbe6 2216 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 2217
4419dbe6 2218 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5
MC		 2219 }
2220 ring->queue_id = bp->q_info[j].queue_id;
5f449249
MC		 2221 if (i < bp->tx_nr_rings_xdp)
2222 continue;
c0c050c5
MC		 2223 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2224 j++;
2225 }
2226 return 0;
2227}
2228
2229static void bnxt_free_cp_rings(struct bnxt *bp)
2230{
2231 int i;
2232
2233 if (!bp->bnapi)
2234 return;
2235
2236 for (i = 0; i < bp->cp_nr_rings; i++) {
2237 struct bnxt_napi *bnapi = bp->bnapi[i];
2238 struct bnxt_cp_ring_info *cpr;
2239 struct bnxt_ring_struct *ring;
2240
2241 if (!bnapi)
2242 continue;
2243
2244 cpr = &bnapi->cp_ring;
2245 ring = &cpr->cp_ring_struct;
2246
2247 bnxt_free_ring(bp, ring);
2248 }
2249}
2250
2251static int bnxt_alloc_cp_rings(struct bnxt *bp)
2252{
2253 int i, rc;
2254
2255 for (i = 0; i < bp->cp_nr_rings; i++) {
2256 struct bnxt_napi *bnapi = bp->bnapi[i];
2257 struct bnxt_cp_ring_info *cpr;
2258 struct bnxt_ring_struct *ring;
2259
2260 if (!bnapi)
2261 continue;
2262
2263 cpr = &bnapi->cp_ring;
2264 ring = &cpr->cp_ring_struct;
2265
2266 rc = bnxt_alloc_ring(bp, ring);
2267 if (rc)
2268 return rc;
2269 }
2270 return 0;
2271}
2272
2273static void bnxt_init_ring_struct(struct bnxt *bp)
2274{
2275 int i;
2276
2277 for (i = 0; i < bp->cp_nr_rings; i++) {
2278 struct bnxt_napi *bnapi = bp->bnapi[i];
2279 struct bnxt_cp_ring_info *cpr;
2280 struct bnxt_rx_ring_info *rxr;
2281 struct bnxt_tx_ring_info *txr;
2282 struct bnxt_ring_struct *ring;
2283
2284 if (!bnapi)
2285 continue;
2286
2287 cpr = &bnapi->cp_ring;
2288 ring = &cpr->cp_ring_struct;
2289 ring->nr_pages = bp->cp_nr_pages;
2290 ring->page_size = HW_CMPD_RING_SIZE;
2291 ring->pg_arr = (void **)cpr->cp_desc_ring;
2292 ring->dma_arr = cpr->cp_desc_mapping;
2293 ring->vmem_size = 0;
2294
b6ab4b01 2295 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2296 if (!rxr)
2297 goto skip_rx;
2298
c0c050c5
MC		 2299 ring = &rxr->rx_ring_struct;
2300 ring->nr_pages = bp->rx_nr_pages;
2301 ring->page_size = HW_RXBD_RING_SIZE;
2302 ring->pg_arr = (void **)rxr->rx_desc_ring;
2303 ring->dma_arr = rxr->rx_desc_mapping;
2304 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2305 ring->vmem = (void **)&rxr->rx_buf_ring;
2306
2307 ring = &rxr->rx_agg_ring_struct;
2308 ring->nr_pages = bp->rx_agg_nr_pages;
2309 ring->page_size = HW_RXBD_RING_SIZE;
2310 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2311 ring->dma_arr = rxr->rx_agg_desc_mapping;
2312 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2313 ring->vmem = (void **)&rxr->rx_agg_ring;
2314
3b2b7d9d 2315skip_rx:
b6ab4b01 2316 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2317 if (!txr)
2318 continue;
2319
c0c050c5
MC		 2320 ring = &txr->tx_ring_struct;
2321 ring->nr_pages = bp->tx_nr_pages;
2322 ring->page_size = HW_RXBD_RING_SIZE;
2323 ring->pg_arr = (void **)txr->tx_desc_ring;
2324 ring->dma_arr = txr->tx_desc_mapping;
2325 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2326 ring->vmem = (void **)&txr->tx_buf_ring;
2327 }
2328}
2329
2330static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2331{
2332 int i;
2333 u32 prod;
2334 struct rx_bd **rx_buf_ring;
2335
2336 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2337 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2338 int j;
2339 struct rx_bd *rxbd;
2340
2341 rxbd = rx_buf_ring[i];
2342 if (!rxbd)
2343 continue;
2344
2345 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2346 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2347 rxbd->rx_bd_opaque = prod;
2348 }
2349 }
2350}
2351
2352static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2353{
2354 struct net_device *dev = bp->dev;
c0c050c5
MC		 2355 struct bnxt_rx_ring_info *rxr;
2356 struct bnxt_ring_struct *ring;
2357 u32 prod, type;
2358 int i;
2359
c0c050c5
MC		 2360 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2361 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2362
2363 if (NET_IP_ALIGN == 2)
2364 type |= RX_BD_FLAGS_SOP;
2365
b6ab4b01 2366 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 2367 ring = &rxr->rx_ring_struct;
2368 bnxt_init_rxbd_pages(ring, type);
2369
2370 prod = rxr->rx_prod;
2371 for (i = 0; i < bp->rx_ring_size; i++) {
2372 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2373 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2374 ring_nr, i, bp->rx_ring_size);
2375 break;
2376 }
2377 prod = NEXT_RX(prod);
2378 }
2379 rxr->rx_prod = prod;
2380 ring->fw_ring_id = INVALID_HW_RING_ID;
2381
edd0c2cc
MC		 2382 ring = &rxr->rx_agg_ring_struct;
2383 ring->fw_ring_id = INVALID_HW_RING_ID;
2384
c0c050c5
MC		 2385 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2386 return 0;
2387
2839f28b 2388 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
c0c050c5
MC		 2389 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2390
2391 bnxt_init_rxbd_pages(ring, type);
2392
2393 prod = rxr->rx_agg_prod;
2394 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2395 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2396 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2397 ring_nr, i, bp->rx_ring_size);
2398 break;
2399 }
2400 prod = NEXT_RX_AGG(prod);
2401 }
2402 rxr->rx_agg_prod = prod;
c0c050c5
MC		 2403
2404 if (bp->flags & BNXT_FLAG_TPA) {
2405 if (rxr->rx_tpa) {
2406 u8 *data;
2407 dma_addr_t mapping;
2408
2409 for (i = 0; i < MAX_TPA; i++) {
2410 data = __bnxt_alloc_rx_data(bp, &mapping,
2411 GFP_KERNEL);
2412 if (!data)
2413 return -ENOMEM;
2414
2415 rxr->rx_tpa[i].data = data;
b3dba77c 2416 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
c0c050c5
MC		 2417 rxr->rx_tpa[i].mapping = mapping;
2418 }
2419 } else {
2420 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2421 return -ENOMEM;
2422 }
2423 }
2424
2425 return 0;
2426}
2427
2428static int bnxt_init_rx_rings(struct bnxt *bp)
2429{
2430 int i, rc = 0;
2431
c61fb99c
MC		 2432 if (BNXT_RX_PAGE_MODE(bp)) {
2433 bp->rx_offset = NET_IP_ALIGN;
2434 bp->rx_dma_offset = 0;
2435 } else {
2436 bp->rx_offset = BNXT_RX_OFFSET;
2437 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2438 }
b3dba77c 2439
c0c050c5
MC		 2440 for (i = 0; i < bp->rx_nr_rings; i++) {
2441 rc = bnxt_init_one_rx_ring(bp, i);
2442 if (rc)
2443 break;
2444 }
2445
2446 return rc;
2447}
2448
2449static int bnxt_init_tx_rings(struct bnxt *bp)
2450{
2451 u16 i;
2452
2453 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2454 MAX_SKB_FRAGS + 1);
2455
2456 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2457 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2458 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2459
2460 ring->fw_ring_id = INVALID_HW_RING_ID;
2461 }
2462
2463 return 0;
2464}
2465
2466static void bnxt_free_ring_grps(struct bnxt *bp)
2467{
2468 kfree(bp->grp_info);
2469 bp->grp_info = NULL;
2470}
2471
2472static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2473{
2474 int i;
2475
2476 if (irq_re_init) {
2477 bp->grp_info = kcalloc(bp->cp_nr_rings,
2478 sizeof(struct bnxt_ring_grp_info),
2479 GFP_KERNEL);
2480 if (!bp->grp_info)
2481 return -ENOMEM;
2482 }
2483 for (i = 0; i < bp->cp_nr_rings; i++) {
2484 if (irq_re_init)
2485 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2486 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2487 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2488 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2489 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2490 }
2491 return 0;
2492}
2493
2494static void bnxt_free_vnics(struct bnxt *bp)
2495{
2496 kfree(bp->vnic_info);
2497 bp->vnic_info = NULL;
2498 bp->nr_vnics = 0;
2499}
2500
2501static int bnxt_alloc_vnics(struct bnxt *bp)
2502{
2503 int num_vnics = 1;
2504
2505#ifdef CONFIG_RFS_ACCEL
2506 if (bp->flags & BNXT_FLAG_RFS)
2507 num_vnics += bp->rx_nr_rings;
2508#endif
2509
dc52c6c7
PS		 2510 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2511 num_vnics++;
2512
c0c050c5
MC		 2513 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2514 GFP_KERNEL);
2515 if (!bp->vnic_info)
2516 return -ENOMEM;
2517
2518 bp->nr_vnics = num_vnics;
2519 return 0;
2520}
2521
2522static void bnxt_init_vnics(struct bnxt *bp)
2523{
2524 int i;
2525
2526 for (i = 0; i < bp->nr_vnics; i++) {
2527 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2528
2529 vnic->fw_vnic_id = INVALID_HW_RING_ID;
94ce9caa
PS		 2530 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2531 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 2532 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2533
2534 if (bp->vnic_info[i].rss_hash_key) {
2535 if (i == 0)
2536 prandom_bytes(vnic->rss_hash_key,
2537 HW_HASH_KEY_SIZE);
2538 else
2539 memcpy(vnic->rss_hash_key,
2540 bp->vnic_info[0].rss_hash_key,
2541 HW_HASH_KEY_SIZE);
2542 }
2543 }
2544}
2545
2546static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2547{
2548 int pages;
2549
2550 pages = ring_size / desc_per_pg;
2551
2552 if (!pages)
2553 return 1;
2554
2555 pages++;
2556
2557 while (pages & (pages - 1))
2558 pages++;
2559
2560 return pages;
2561}
2562
2563static void bnxt_set_tpa_flags(struct bnxt *bp)
2564{
2565 bp->flags &= ~BNXT_FLAG_TPA;
341138c3
MC		 2566 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2567 return;
c0c050c5
MC		 2568 if (bp->dev->features & NETIF_F_LRO)
2569 bp->flags |= BNXT_FLAG_LRO;
94758f8d 2570 if (bp->dev->features & NETIF_F_GRO)
c0c050c5
MC		 2571 bp->flags |= BNXT_FLAG_GRO;
2572}
2573
2574/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2575 * be set on entry.
2576 */
2577void bnxt_set_ring_params(struct bnxt *bp)
2578{
2579 u32 ring_size, rx_size, rx_space;
2580 u32 agg_factor = 0, agg_ring_size = 0;
2581
2582 /* 8 for CRC and VLAN */
2583 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2584
2585 rx_space = rx_size + NET_SKB_PAD +
2586 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2587
2588 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2589 ring_size = bp->rx_ring_size;
2590 bp->rx_agg_ring_size = 0;
2591 bp->rx_agg_nr_pages = 0;
2592
2593 if (bp->flags & BNXT_FLAG_TPA)
2839f28b 2594 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
c0c050c5
MC		 2595
2596 bp->flags &= ~BNXT_FLAG_JUMBO;
bdbd1eb5 2597 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
c0c050c5
MC		 2598 u32 jumbo_factor;
2599
2600 bp->flags |= BNXT_FLAG_JUMBO;
2601 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2602 if (jumbo_factor > agg_factor)
2603 agg_factor = jumbo_factor;
2604 }
2605 agg_ring_size = ring_size * agg_factor;
2606
2607 if (agg_ring_size) {
2608 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2609 RX_DESC_CNT);
2610 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2611 u32 tmp = agg_ring_size;
2612
2613 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2614 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2615 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2616 tmp, agg_ring_size);
2617 }
2618 bp->rx_agg_ring_size = agg_ring_size;
2619 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2620 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2621 rx_space = rx_size + NET_SKB_PAD +
2622 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2623 }
2624
2625 bp->rx_buf_use_size = rx_size;
2626 bp->rx_buf_size = rx_space;
2627
2628 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2629 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2630
2631 ring_size = bp->tx_ring_size;
2632 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2633 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2634
2635 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2636 bp->cp_ring_size = ring_size;
2637
2638 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2639 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2640 bp->cp_nr_pages = MAX_CP_PAGES;
2641 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2642 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2643 ring_size, bp->cp_ring_size);
2644 }
2645 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2646 bp->cp_ring_mask = bp->cp_bit - 1;
2647}
2648
c61fb99c 2649int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
6bb19474 2650{
c61fb99c
MC		 2651 if (page_mode) {
2652 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2653 return -EOPNOTSUPP;
2654 bp->dev->max_mtu = BNXT_MAX_PAGE_MODE_MTU;
2655 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2656 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2657 bp->dev->hw_features &= ~NETIF_F_LRO;
2658 bp->dev->features &= ~NETIF_F_LRO;
2659 bp->rx_dir = DMA_BIDIRECTIONAL;
2660 bp->rx_skb_func = bnxt_rx_page_skb;
2661 } else {
2662 bp->dev->max_mtu = BNXT_MAX_MTU;
2663 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2664 bp->rx_dir = DMA_FROM_DEVICE;
2665 bp->rx_skb_func = bnxt_rx_skb;
2666 }
6bb19474
MC		 2667 return 0;
2668}
2669
c0c050c5
MC		 2670static void bnxt_free_vnic_attributes(struct bnxt *bp)
2671{
2672 int i;
2673 struct bnxt_vnic_info *vnic;
2674 struct pci_dev *pdev = bp->pdev;
2675
2676 if (!bp->vnic_info)
2677 return;
2678
2679 for (i = 0; i < bp->nr_vnics; i++) {
2680 vnic = &bp->vnic_info[i];
2681
2682 kfree(vnic->fw_grp_ids);
2683 vnic->fw_grp_ids = NULL;
2684
2685 kfree(vnic->uc_list);
2686 vnic->uc_list = NULL;
2687
2688 if (vnic->mc_list) {
2689 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2690 vnic->mc_list, vnic->mc_list_mapping);
2691 vnic->mc_list = NULL;
2692 }
2693
2694 if (vnic->rss_table) {
2695 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2696 vnic->rss_table,
2697 vnic->rss_table_dma_addr);
2698 vnic->rss_table = NULL;
2699 }
2700
2701 vnic->rss_hash_key = NULL;
2702 vnic->flags = 0;
2703 }
2704}
2705
2706static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2707{
2708 int i, rc = 0, size;
2709 struct bnxt_vnic_info *vnic;
2710 struct pci_dev *pdev = bp->pdev;
2711 int max_rings;
2712
2713 for (i = 0; i < bp->nr_vnics; i++) {
2714 vnic = &bp->vnic_info[i];
2715
2716 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2717 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2718
2719 if (mem_size > 0) {
2720 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2721 if (!vnic->uc_list) {
2722 rc = -ENOMEM;
2723 goto out;
2724 }
2725 }
2726 }
2727
2728 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2729 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2730 vnic->mc_list =
2731 dma_alloc_coherent(&pdev->dev,
2732 vnic->mc_list_size,
2733 &vnic->mc_list_mapping,
2734 GFP_KERNEL);
2735 if (!vnic->mc_list) {
2736 rc = -ENOMEM;
2737 goto out;
2738 }
2739 }
2740
2741 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2742 max_rings = bp->rx_nr_rings;
2743 else
2744 max_rings = 1;
2745
2746 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2747 if (!vnic->fw_grp_ids) {
2748 rc = -ENOMEM;
2749 goto out;
2750 }
2751
ae10ae74
MC		 2752 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2753 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2754 continue;
2755
c0c050c5
MC		 2756 /* Allocate rss table and hash key */
2757 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2758 &vnic->rss_table_dma_addr,
2759 GFP_KERNEL);
2760 if (!vnic->rss_table) {
2761 rc = -ENOMEM;
2762 goto out;
2763 }
2764
2765 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2766
2767 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2768 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2769 }
2770 return 0;
2771
2772out:
2773 return rc;
2774}
2775
2776static void bnxt_free_hwrm_resources(struct bnxt *bp)
2777{
2778 struct pci_dev *pdev = bp->pdev;
2779
2780 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2781 bp->hwrm_cmd_resp_dma_addr);
2782
2783 bp->hwrm_cmd_resp_addr = NULL;
2784 if (bp->hwrm_dbg_resp_addr) {
2785 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2786 bp->hwrm_dbg_resp_addr,
2787 bp->hwrm_dbg_resp_dma_addr);
2788
2789 bp->hwrm_dbg_resp_addr = NULL;
2790 }
2791}
2792
2793static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2794{
2795 struct pci_dev *pdev = bp->pdev;
2796
2797 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2798 &bp->hwrm_cmd_resp_dma_addr,
2799 GFP_KERNEL);
2800 if (!bp->hwrm_cmd_resp_addr)
2801 return -ENOMEM;
2802 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2803 HWRM_DBG_REG_BUF_SIZE,
2804 &bp->hwrm_dbg_resp_dma_addr,
2805 GFP_KERNEL);
2806 if (!bp->hwrm_dbg_resp_addr)
2807 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2808
2809 return 0;
2810}
2811
2812static void bnxt_free_stats(struct bnxt *bp)
2813{
2814 u32 size, i;
2815 struct pci_dev *pdev = bp->pdev;
2816
3bdf56c4
MC		 2817 if (bp->hw_rx_port_stats) {
2818 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2819 bp->hw_rx_port_stats,
2820 bp->hw_rx_port_stats_map);
2821 bp->hw_rx_port_stats = NULL;
2822 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2823 }
2824
c0c050c5
MC		 2825 if (!bp->bnapi)
2826 return;
2827
2828 size = sizeof(struct ctx_hw_stats);
2829
2830 for (i = 0; i < bp->cp_nr_rings; i++) {
2831 struct bnxt_napi *bnapi = bp->bnapi[i];
2832 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2833
2834 if (cpr->hw_stats) {
2835 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2836 cpr->hw_stats_map);
2837 cpr->hw_stats = NULL;
2838 }
2839 }
2840}
2841
2842static int bnxt_alloc_stats(struct bnxt *bp)
2843{
2844 u32 size, i;
2845 struct pci_dev *pdev = bp->pdev;
2846
2847 size = sizeof(struct ctx_hw_stats);
2848
2849 for (i = 0; i < bp->cp_nr_rings; i++) {
2850 struct bnxt_napi *bnapi = bp->bnapi[i];
2851 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2852
2853 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2854 &cpr->hw_stats_map,
2855 GFP_KERNEL);
2856 if (!cpr->hw_stats)
2857 return -ENOMEM;
2858
2859 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2860 }
3bdf56c4 2861
3e8060fa 2862 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3bdf56c4
MC		 2863 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2864 sizeof(struct tx_port_stats) + 1024;
2865
2866 bp->hw_rx_port_stats =
2867 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2868 &bp->hw_rx_port_stats_map,
2869 GFP_KERNEL);
2870 if (!bp->hw_rx_port_stats)
2871 return -ENOMEM;
2872
2873 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2874 512;
2875 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2876 sizeof(struct rx_port_stats) + 512;
2877 bp->flags |= BNXT_FLAG_PORT_STATS;
2878 }
c0c050c5
MC		 2879 return 0;
2880}
2881
2882static void bnxt_clear_ring_indices(struct bnxt *bp)
2883{
2884 int i;
2885
2886 if (!bp->bnapi)
2887 return;
2888
2889 for (i = 0; i < bp->cp_nr_rings; i++) {
2890 struct bnxt_napi *bnapi = bp->bnapi[i];
2891 struct bnxt_cp_ring_info *cpr;
2892 struct bnxt_rx_ring_info *rxr;
2893 struct bnxt_tx_ring_info *txr;
2894
2895 if (!bnapi)
2896 continue;
2897
2898 cpr = &bnapi->cp_ring;
2899 cpr->cp_raw_cons = 0;
2900
b6ab4b01 2901 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2902 if (txr) {
2903 txr->tx_prod = 0;
2904 txr->tx_cons = 0;
2905 }
c0c050c5 2906
b6ab4b01 2907 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2908 if (rxr) {
2909 rxr->rx_prod = 0;
2910 rxr->rx_agg_prod = 0;
2911 rxr->rx_sw_agg_prod = 0;
376a5b86 2912 rxr->rx_next_cons = 0;
3b2b7d9d 2913 }
c0c050c5
MC		 2914 }
2915}
2916
2917static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2918{
2919#ifdef CONFIG_RFS_ACCEL
2920 int i;
2921
2922 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2923 * safe to delete the hash table.
2924 */
2925 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2926 struct hlist_head *head;
2927 struct hlist_node *tmp;
2928 struct bnxt_ntuple_filter *fltr;
2929
2930 head = &bp->ntp_fltr_hash_tbl[i];
2931 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2932 hlist_del(&fltr->hash);
2933 kfree(fltr);
2934 }
2935 }
2936 if (irq_reinit) {
2937 kfree(bp->ntp_fltr_bmap);
2938 bp->ntp_fltr_bmap = NULL;
2939 }
2940 bp->ntp_fltr_count = 0;
2941#endif
2942}
2943
2944static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2945{
2946#ifdef CONFIG_RFS_ACCEL
2947 int i, rc = 0;
2948
2949 if (!(bp->flags & BNXT_FLAG_RFS))
2950 return 0;
2951
2952 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2953 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2954
2955 bp->ntp_fltr_count = 0;
2956 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2957 GFP_KERNEL);
2958
2959 if (!bp->ntp_fltr_bmap)
2960 rc = -ENOMEM;
2961
2962 return rc;
2963#else
2964 return 0;
2965#endif
2966}
2967
2968static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2969{
2970 bnxt_free_vnic_attributes(bp);
2971 bnxt_free_tx_rings(bp);
2972 bnxt_free_rx_rings(bp);
2973 bnxt_free_cp_rings(bp);
2974 bnxt_free_ntp_fltrs(bp, irq_re_init);
2975 if (irq_re_init) {
2976 bnxt_free_stats(bp);
2977 bnxt_free_ring_grps(bp);
2978 bnxt_free_vnics(bp);
a960dec9
MC		 2979 kfree(bp->tx_ring_map);
2980 bp->tx_ring_map = NULL;
b6ab4b01
MC		 2981 kfree(bp->tx_ring);
2982 bp->tx_ring = NULL;
2983 kfree(bp->rx_ring);
2984 bp->rx_ring = NULL;
c0c050c5
MC		 2985 kfree(bp->bnapi);
2986 bp->bnapi = NULL;
2987 } else {
2988 bnxt_clear_ring_indices(bp);
2989 }
2990}
2991
2992static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2993{
01657bcd 2994 int i, j, rc, size, arr_size;
c0c050c5
MC		 2995 void *bnapi;
2996
2997 if (irq_re_init) {
2998 /* Allocate bnapi mem pointer array and mem block for
2999 * all queues
3000 */
3001 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3002 bp->cp_nr_rings);
3003 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3004 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3005 if (!bnapi)
3006 return -ENOMEM;
3007
3008 bp->bnapi = bnapi;
3009 bnapi += arr_size;
3010 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3011 bp->bnapi[i] = bnapi;
3012 bp->bnapi[i]->index = i;
3013 bp->bnapi[i]->bp = bp;
3014 }
3015
b6ab4b01
MC		 3016 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3017 sizeof(struct bnxt_rx_ring_info),
3018 GFP_KERNEL);
3019 if (!bp->rx_ring)
3020 return -ENOMEM;
3021
3022 for (i = 0; i < bp->rx_nr_rings; i++) {
3023 bp->rx_ring[i].bnapi = bp->bnapi[i];
3024 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3025 }
3026
3027 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3028 sizeof(struct bnxt_tx_ring_info),
3029 GFP_KERNEL);
3030 if (!bp->tx_ring)
3031 return -ENOMEM;
3032
a960dec9
MC		 3033 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3034 GFP_KERNEL);
3035
3036 if (!bp->tx_ring_map)
3037 return -ENOMEM;
3038
01657bcd
MC		 3039 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3040 j = 0;
3041 else
3042 j = bp->rx_nr_rings;
3043
3044 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3045 bp->tx_ring[i].bnapi = bp->bnapi[j];
3046 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
5f449249
MC		 3047 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3048 if (i >= bp->tx_nr_rings_xdp)
3049 bp->tx_ring[i].txq_index = i -
3050 bp->tx_nr_rings_xdp;
fa3e93e8
MC		 3051 else
3052 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3053 bp->bnapi[j]->tx_int = bnxt_tx_int;
b6ab4b01
MC		 3054 }
3055
c0c050c5
MC		 3056 rc = bnxt_alloc_stats(bp);
3057 if (rc)
3058 goto alloc_mem_err;
3059
3060 rc = bnxt_alloc_ntp_fltrs(bp);
3061 if (rc)
3062 goto alloc_mem_err;
3063
3064 rc = bnxt_alloc_vnics(bp);
3065 if (rc)
3066 goto alloc_mem_err;
3067 }
3068
3069 bnxt_init_ring_struct(bp);
3070
3071 rc = bnxt_alloc_rx_rings(bp);
3072 if (rc)
3073 goto alloc_mem_err;
3074
3075 rc = bnxt_alloc_tx_rings(bp);
3076 if (rc)
3077 goto alloc_mem_err;
3078
3079 rc = bnxt_alloc_cp_rings(bp);
3080 if (rc)
3081 goto alloc_mem_err;
3082
3083 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3084 BNXT_VNIC_UCAST_FLAG;
3085 rc = bnxt_alloc_vnic_attributes(bp);
3086 if (rc)
3087 goto alloc_mem_err;
3088 return 0;
3089
3090alloc_mem_err:
3091 bnxt_free_mem(bp, true);
3092 return rc;
3093}
3094
9d8bc097
MC		 3095static void bnxt_disable_int(struct bnxt *bp)
3096{
3097 int i;
3098
3099 if (!bp->bnapi)
3100 return;
3101
3102 for (i = 0; i < bp->cp_nr_rings; i++) {
3103 struct bnxt_napi *bnapi = bp->bnapi[i];
3104 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3105
3106 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3107 }
3108}
3109
3110static void bnxt_disable_int_sync(struct bnxt *bp)
3111{
3112 int i;
3113
3114 atomic_inc(&bp->intr_sem);
3115
3116 bnxt_disable_int(bp);
3117 for (i = 0; i < bp->cp_nr_rings; i++)
3118 synchronize_irq(bp->irq_tbl[i].vector);
3119}
3120
3121static void bnxt_enable_int(struct bnxt *bp)
3122{
3123 int i;
3124
3125 atomic_set(&bp->intr_sem, 0);
3126 for (i = 0; i < bp->cp_nr_rings; i++) {
3127 struct bnxt_napi *bnapi = bp->bnapi[i];
3128 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3129
3130 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3131 }
3132}
3133
c0c050c5
MC		 3134void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3135 u16 cmpl_ring, u16 target_id)
3136{
a8643e16 3137 struct input *req = request;
c0c050c5 3138
a8643e16
MC		 3139 req->req_type = cpu_to_le16(req_type);
3140 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3141 req->target_id = cpu_to_le16(target_id);
c0c050c5
MC		 3142 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3143}
3144
fbfbc485
MC		 3145static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3146 int timeout, bool silent)
c0c050c5 3147{
a11fa2be 3148 int i, intr_process, rc, tmo_count;
a8643e16 3149 struct input *req = msg;
c0c050c5
MC		 3150 u32 *data = msg;
3151 __le32 *resp_len, *valid;
3152 u16 cp_ring_id, len = 0;
3153 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3154
a8643e16 3155 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
c0c050c5 3156 memset(resp, 0, PAGE_SIZE);
a8643e16 3157 cp_ring_id = le16_to_cpu(req->cmpl_ring);
c0c050c5
MC		 3158 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3159
3160 /* Write request msg to hwrm channel */
3161 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3162
e6ef2699 3163 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
d79979a1
MC		 3164 writel(0, bp->bar0 + i);
3165
c0c050c5
MC		 3166 /* currently supports only one outstanding message */
3167 if (intr_process)
a8643e16 3168 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
c0c050c5
MC		 3169
3170 /* Ring channel doorbell */
3171 writel(1, bp->bar0 + 0x100);
3172
ff4fe81d
MC		 3173 if (!timeout)
3174 timeout = DFLT_HWRM_CMD_TIMEOUT;
3175
c0c050c5 3176 i = 0;
a11fa2be 3177 tmo_count = timeout * 40;
c0c050c5
MC		 3178 if (intr_process) {
3179 /* Wait until hwrm response cmpl interrupt is processed */
3180 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
a11fa2be
MC		 3181 i++ < tmo_count) {
3182 usleep_range(25, 40);
c0c050c5
MC		 3183 }
3184
3185 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3186 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
a8643e16 3187 le16_to_cpu(req->req_type));
c0c050c5
MC		 3188 return -1;
3189 }
3190 } else {
3191 /* Check if response len is updated */
3192 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
a11fa2be 3193 for (i = 0; i < tmo_count; i++) {
c0c050c5
MC		 3194 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3195 HWRM_RESP_LEN_SFT;
3196 if (len)
3197 break;
a11fa2be 3198 usleep_range(25, 40);
c0c050c5
MC		 3199 }
3200
a11fa2be 3201 if (i >= tmo_count) {
c0c050c5 3202 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
a8643e16 3203 timeout, le16_to_cpu(req->req_type),
8578d6c1 3204 le16_to_cpu(req->seq_id), len);
c0c050c5
MC		 3205 return -1;
3206 }
3207
3208 /* Last word of resp contains valid bit */
3209 valid = bp->hwrm_cmd_resp_addr + len - 4;
a11fa2be 3210 for (i = 0; i < 5; i++) {
c0c050c5
MC		 3211 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3212 break;
a11fa2be 3213 udelay(1);
c0c050c5
MC		 3214 }
3215
a11fa2be 3216 if (i >= 5) {
c0c050c5 3217 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
a8643e16
MC		 3218 timeout, le16_to_cpu(req->req_type),
3219 le16_to_cpu(req->seq_id), len, *valid);
c0c050c5
MC		 3220 return -1;
3221 }
3222 }
3223
3224 rc = le16_to_cpu(resp->error_code);
fbfbc485 3225 if (rc && !silent)
c0c050c5
MC		 3226 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3227 le16_to_cpu(resp->req_type),
3228 le16_to_cpu(resp->seq_id), rc);
fbfbc485
MC		 3229 return rc;
3230}
3231
3232int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3233{
3234 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
c0c050c5
MC		 3235}
3236
3237int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3238{
3239 int rc;
3240
3241 mutex_lock(&bp->hwrm_cmd_lock);
3242 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3243 mutex_unlock(&bp->hwrm_cmd_lock);
3244 return rc;
3245}
3246
90e20921
MC		 3247int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3248 int timeout)
3249{
3250 int rc;
3251
3252 mutex_lock(&bp->hwrm_cmd_lock);
3253 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3254 mutex_unlock(&bp->hwrm_cmd_lock);
3255 return rc;
3256}
3257
a1653b13
MC		 3258int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3259 int bmap_size)
c0c050c5
MC		 3260{
3261 struct hwrm_func_drv_rgtr_input req = {0};
25be8623
MC		 3262 DECLARE_BITMAP(async_events_bmap, 256);
3263 u32 *events = (u32 *)async_events_bmap;
a1653b13 3264 int i;
c0c050c5
MC		 3265
3266 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3267
3268 req.enables =
a1653b13 3269 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
c0c050c5 3270
25be8623
MC		 3271 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3272 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3273 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3274
a1653b13
MC		 3275 if (bmap && bmap_size) {
3276 for (i = 0; i < bmap_size; i++) {
3277 if (test_bit(i, bmap))
3278 __set_bit(i, async_events_bmap);
3279 }
3280 }
3281
25be8623
MC		 3282 for (i = 0; i < 8; i++)
3283 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3284
a1653b13
MC		 3285 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3286}
3287
3288static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3289{
3290 struct hwrm_func_drv_rgtr_input req = {0};
3291
3292 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3293
3294 req.enables =
3295 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3296 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3297
11f15ed3 3298 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
c0c050c5
MC		 3299 req.ver_maj = DRV_VER_MAJ;
3300 req.ver_min = DRV_VER_MIN;
3301 req.ver_upd = DRV_VER_UPD;
3302
3303 if (BNXT_PF(bp)) {
de68f5de 3304 DECLARE_BITMAP(vf_req_snif_bmap, 256);
c0c050c5 3305 u32 *data = (u32 *)vf_req_snif_bmap;
a1653b13 3306 int i;
c0c050c5 3307
de68f5de 3308 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
c0c050c5
MC		 3309 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3310 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3311
de68f5de
MC		 3312 for (i = 0; i < 8; i++)
3313 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3314
c0c050c5
MC		 3315 req.enables |=
3316 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3317 }
3318
3319 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3320}
3321
be58a0da
JH		 3322static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3323{
3324 struct hwrm_func_drv_unrgtr_input req = {0};
3325
3326 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3327 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3328}
3329
c0c050c5
MC		 3330static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3331{
3332 u32 rc = 0;
3333 struct hwrm_tunnel_dst_port_free_input req = {0};
3334
3335 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3336 req.tunnel_type = tunnel_type;
3337
3338 switch (tunnel_type) {
3339 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3340 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3341 break;
3342 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3343 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3344 break;
3345 default:
3346 break;
3347 }
3348
3349 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3350 if (rc)
3351 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3352 rc);
3353 return rc;
3354}
3355
3356static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3357 u8 tunnel_type)
3358{
3359 u32 rc = 0;
3360 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3361 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3362
3363 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3364
3365 req.tunnel_type = tunnel_type;
3366 req.tunnel_dst_port_val = port;
3367
3368 mutex_lock(&bp->hwrm_cmd_lock);
3369 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3370 if (rc) {
3371 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3372 rc);
3373 goto err_out;
3374 }
3375
57aac71b
CJ		 3376 switch (tunnel_type) {
3377 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
c0c050c5 3378 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3379 break;
3380 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
c0c050c5 3381 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3382 break;
3383 default:
3384 break;
3385 }
3386
c0c050c5
MC		 3387err_out:
3388 mutex_unlock(&bp->hwrm_cmd_lock);
3389 return rc;
3390}
3391
3392static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3393{
3394 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3395 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3396
3397 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 3398 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 3399
3400 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3401 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3402 req.mask = cpu_to_le32(vnic->rx_mask);
3403 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3404}
3405
3406#ifdef CONFIG_RFS_ACCEL
3407static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3408 struct bnxt_ntuple_filter *fltr)
3409{
3410 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3411
3412 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3413 req.ntuple_filter_id = fltr->filter_id;
3414 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3415}
3416
3417#define BNXT_NTP_FLTR_FLAGS \
3418 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3419 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3420 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3421 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3422 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3423 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3424 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3425 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3426 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3427 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3428 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3429 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3430 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 3431 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5
MC		 3432
3433static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3434 struct bnxt_ntuple_filter *fltr)
3435{
3436 int rc = 0;
3437 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3438 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3439 bp->hwrm_cmd_resp_addr;
3440 struct flow_keys *keys = &fltr->fkeys;
3441 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3442
3443 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
a54c4d74 3444 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
c0c050c5
MC		 3445
3446 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3447
3448 req.ethertype = htons(ETH_P_IP);
3449 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 3450 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 3451 req.ip_protocol = keys->basic.ip_proto;
3452
dda0e746
MC		 3453 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3454 int i;
3455
3456 req.ethertype = htons(ETH_P_IPV6);
3457 req.ip_addr_type =
3458 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3459 *(struct in6_addr *)&req.src_ipaddr[0] =
3460 keys->addrs.v6addrs.src;
3461 *(struct in6_addr *)&req.dst_ipaddr[0] =
3462 keys->addrs.v6addrs.dst;
3463 for (i = 0; i < 4; i++) {
3464 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3465 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3466 }
3467 } else {
3468 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3469 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3470 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3471 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3472 }
c0c050c5
MC		 3473
3474 req.src_port = keys->ports.src;
3475 req.src_port_mask = cpu_to_be16(0xffff);
3476 req.dst_port = keys->ports.dst;
3477 req.dst_port_mask = cpu_to_be16(0xffff);
3478
c193554e 3479 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 3480 mutex_lock(&bp->hwrm_cmd_lock);
3481 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3482 if (!rc)
3483 fltr->filter_id = resp->ntuple_filter_id;
3484 mutex_unlock(&bp->hwrm_cmd_lock);
3485 return rc;
3486}
3487#endif
3488
3489static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3490 u8 *mac_addr)
3491{
3492 u32 rc = 0;
3493 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3494 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3495
3496 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
dc52c6c7
PS		 3497 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3498 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3499 req.flags |=
3500 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 3501 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 3502 req.enables =
3503 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 3504 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 3505 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3506 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3507 req.l2_addr_mask[0] = 0xff;
3508 req.l2_addr_mask[1] = 0xff;
3509 req.l2_addr_mask[2] = 0xff;
3510 req.l2_addr_mask[3] = 0xff;
3511 req.l2_addr_mask[4] = 0xff;
3512 req.l2_addr_mask[5] = 0xff;
3513
3514 mutex_lock(&bp->hwrm_cmd_lock);
3515 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3516 if (!rc)
3517 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3518 resp->l2_filter_id;
3519 mutex_unlock(&bp->hwrm_cmd_lock);
3520 return rc;
3521}
3522
3523static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3524{
3525 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3526 int rc = 0;
3527
3528 /* Any associated ntuple filters will also be cleared by firmware. */
3529 mutex_lock(&bp->hwrm_cmd_lock);
3530 for (i = 0; i < num_of_vnics; i++) {
3531 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3532
3533 for (j = 0; j < vnic->uc_filter_count; j++) {
3534 struct hwrm_cfa_l2_filter_free_input req = {0};
3535
3536 bnxt_hwrm_cmd_hdr_init(bp, &req,
3537 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3538
3539 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3540
3541 rc = _hwrm_send_message(bp, &req, sizeof(req),
3542 HWRM_CMD_TIMEOUT);
3543 }
3544 vnic->uc_filter_count = 0;
3545 }
3546 mutex_unlock(&bp->hwrm_cmd_lock);
3547
3548 return rc;
3549}
3550
3551static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3552{
3553 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3554 struct hwrm_vnic_tpa_cfg_input req = {0};
3555
3556 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3557
3558 if (tpa_flags) {
3559 u16 mss = bp->dev->mtu - 40;
3560 u32 nsegs, n, segs = 0, flags;
3561
3562 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3563 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3564 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3565 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3566 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3567 if (tpa_flags & BNXT_FLAG_GRO)
3568 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3569
3570 req.flags = cpu_to_le32(flags);
3571
3572 req.enables =
3573 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 3574 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3575 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 3576
3577 /* Number of segs are log2 units, and first packet is not
3578 * included as part of this units.
3579 */
2839f28b
MC		 3580 if (mss <= BNXT_RX_PAGE_SIZE) {
3581 n = BNXT_RX_PAGE_SIZE / mss;
c0c050c5
MC		 3582 nsegs = (MAX_SKB_FRAGS - 1) * n;
3583 } else {
2839f28b
MC		 3584 n = mss / BNXT_RX_PAGE_SIZE;
3585 if (mss & (BNXT_RX_PAGE_SIZE - 1))
c0c050c5
MC		 3586 n++;
3587 nsegs = (MAX_SKB_FRAGS - n) / n;
3588 }
3589
3590 segs = ilog2(nsegs);
3591 req.max_agg_segs = cpu_to_le16(segs);
3592 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 3593
3594 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 3595 }
3596 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3597
3598 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3599}
3600
3601static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3602{
3603 u32 i, j, max_rings;
3604 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3605 struct hwrm_vnic_rss_cfg_input req = {0};
3606
94ce9caa 3607 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
c0c050c5
MC		 3608 return 0;
3609
3610 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3611 if (set_rss) {
87da7f79 3612 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
dc52c6c7
PS		 3613 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3614 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3615 max_rings = bp->rx_nr_rings - 1;
3616 else
3617 max_rings = bp->rx_nr_rings;
3618 } else {
c0c050c5 3619 max_rings = 1;
dc52c6c7 3620 }
c0c050c5
MC		 3621
3622 /* Fill the RSS indirection table with ring group ids */
3623 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3624 if (j == max_rings)
3625 j = 0;
3626 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3627 }
3628
3629 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3630 req.hash_key_tbl_addr =
3631 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3632 }
94ce9caa 3633 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
c0c050c5
MC		 3634 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3635}
3636
3637static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3638{
3639 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3640 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3641
3642 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3643 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3644 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3645 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3646 req.enables =
3647 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3648 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3649 /* thresholds not implemented in firmware yet */
3650 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3651 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3652 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3653 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3654}
3655
94ce9caa
PS		 3656static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3657 u16 ctx_idx)
c0c050c5
MC		 3658{
3659 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3660
3661 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3662 req.rss_cos_lb_ctx_id =
94ce9caa 3663 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
c0c050c5
MC		 3664
3665 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
94ce9caa 3666 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
c0c050c5
MC		 3667}
3668
3669static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3670{
94ce9caa 3671 int i, j;
c0c050c5
MC		 3672
3673 for (i = 0; i < bp->nr_vnics; i++) {
3674 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3675
94ce9caa
PS		 3676 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3677 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3678 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3679 }
c0c050c5
MC		 3680 }
3681 bp->rsscos_nr_ctxs = 0;
3682}
3683
94ce9caa 3684static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
c0c050c5
MC		 3685{
3686 int rc;
3687 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3688 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3689 bp->hwrm_cmd_resp_addr;
3690
3691 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3692 -1);
3693
3694 mutex_lock(&bp->hwrm_cmd_lock);
3695 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3696 if (!rc)
94ce9caa 3697 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
c0c050c5
MC		 3698 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3699 mutex_unlock(&bp->hwrm_cmd_lock);
3700
3701 return rc;
3702}
3703
a588e458 3704int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
c0c050c5 3705{
b81a90d3 3706 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 3707 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3708 struct hwrm_vnic_cfg_input req = {0};
cf6645f8 3709 u16 def_vlan = 0;
c0c050c5
MC		 3710
3711 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
dc52c6c7
PS		 3712
3713 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
c0c050c5 3714 /* Only RSS support for now TBD: COS & LB */
dc52c6c7
PS		 3715 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3716 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3717 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3718 VNIC_CFG_REQ_ENABLES_MRU);
ae10ae74
MC		 3719 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
3720 req.rss_rule =
3721 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
3722 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3723 VNIC_CFG_REQ_ENABLES_MRU);
3724 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
dc52c6c7
PS		 3725 } else {
3726 req.rss_rule = cpu_to_le16(0xffff);
3727 }
94ce9caa 3728
dc52c6c7
PS		 3729 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3730 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
94ce9caa
PS		 3731 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3732 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3733 } else {
3734 req.cos_rule = cpu_to_le16(0xffff);
3735 }
3736
c0c050c5 3737 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 3738 ring = 0;
c0c050c5 3739 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 3740 ring = vnic_id - 1;
76595193
PS		 3741 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3742 ring = bp->rx_nr_rings - 1;
c0c050c5 3743
b81a90d3 3744 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5
MC		 3745 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3746 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3747
3748 req.lb_rule = cpu_to_le16(0xffff);
3749 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3750 VLAN_HLEN);
3751
cf6645f8
MC		 3752#ifdef CONFIG_BNXT_SRIOV
3753 if (BNXT_VF(bp))
3754 def_vlan = bp->vf.vlan;
3755#endif
3756 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
c0c050c5 3757 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
a588e458
MC		 3758 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
3759 req.flags |=
3760 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
c0c050c5
MC		 3761
3762 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3763}
3764
3765static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3766{
3767 u32 rc = 0;
3768
3769 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3770 struct hwrm_vnic_free_input req = {0};
3771
3772 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3773 req.vnic_id =
3774 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3775
3776 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3777 if (rc)
3778 return rc;
3779 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3780 }
3781 return rc;
3782}
3783
3784static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3785{
3786 u16 i;
3787
3788 for (i = 0; i < bp->nr_vnics; i++)
3789 bnxt_hwrm_vnic_free_one(bp, i);
3790}
3791
b81a90d3
MC		 3792static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3793 unsigned int start_rx_ring_idx,
3794 unsigned int nr_rings)
c0c050c5 3795{
b81a90d3
MC		 3796 int rc = 0;
3797 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 3798 struct hwrm_vnic_alloc_input req = {0};
3799 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3800
3801 /* map ring groups to this vnic */
b81a90d3
MC		 3802 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3803 grp_idx = bp->rx_ring[i].bnapi->index;
3804 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 3805 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 3806 j, nr_rings);
c0c050c5
MC		 3807 break;
3808 }
3809 bp->vnic_info[vnic_id].fw_grp_ids[j] =
b81a90d3 3810 bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 3811 }
3812
94ce9caa
PS		 3813 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3814 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 3815 if (vnic_id == 0)
3816 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3817
3818 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3819
3820 mutex_lock(&bp->hwrm_cmd_lock);
3821 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3822 if (!rc)
3823 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3824 mutex_unlock(&bp->hwrm_cmd_lock);
3825 return rc;
3826}
3827
8fdefd63
MC		 3828static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
3829{
3830 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3831 struct hwrm_vnic_qcaps_input req = {0};
3832 int rc;
3833
3834 if (bp->hwrm_spec_code < 0x10600)
3835 return 0;
3836
3837 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
3838 mutex_lock(&bp->hwrm_cmd_lock);
3839 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3840 if (!rc) {
3841 if (resp->flags &
3842 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
3843 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
3844 }
3845 mutex_unlock(&bp->hwrm_cmd_lock);
3846 return rc;
3847}
3848
c0c050c5
MC		 3849static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3850{
3851 u16 i;
3852 u32 rc = 0;
3853
3854 mutex_lock(&bp->hwrm_cmd_lock);
3855 for (i = 0; i < bp->rx_nr_rings; i++) {
3856 struct hwrm_ring_grp_alloc_input req = {0};
3857 struct hwrm_ring_grp_alloc_output *resp =
3858 bp->hwrm_cmd_resp_addr;
b81a90d3 3859 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 3860
3861 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3862
b81a90d3
MC		 3863 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3864 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3865 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3866 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 3867
3868 rc = _hwrm_send_message(bp, &req, sizeof(req),
3869 HWRM_CMD_TIMEOUT);
3870 if (rc)
3871 break;
3872
b81a90d3
MC		 3873 bp->grp_info[grp_idx].fw_grp_id =
3874 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 3875 }
3876 mutex_unlock(&bp->hwrm_cmd_lock);
3877 return rc;
3878}
3879
3880static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3881{
3882 u16 i;
3883 u32 rc = 0;
3884 struct hwrm_ring_grp_free_input req = {0};
3885
3886 if (!bp->grp_info)
3887 return 0;
3888
3889 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3890
3891 mutex_lock(&bp->hwrm_cmd_lock);
3892 for (i = 0; i < bp->cp_nr_rings; i++) {
3893 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3894 continue;
3895 req.ring_group_id =
3896 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3897
3898 rc = _hwrm_send_message(bp, &req, sizeof(req),
3899 HWRM_CMD_TIMEOUT);
3900 if (rc)
3901 break;
3902 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3903 }
3904 mutex_unlock(&bp->hwrm_cmd_lock);
3905 return rc;
3906}
3907
3908static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3909 struct bnxt_ring_struct *ring,
3910 u32 ring_type, u32 map_index,
3911 u32 stats_ctx_id)
3912{
3913 int rc = 0, err = 0;
3914 struct hwrm_ring_alloc_input req = {0};
3915 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3916 u16 ring_id;
3917
3918 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3919
3920 req.enables = 0;
3921 if (ring->nr_pages > 1) {
3922 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3923 /* Page size is in log2 units */
3924 req.page_size = BNXT_PAGE_SHIFT;
3925 req.page_tbl_depth = 1;
3926 } else {
3927 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3928 }
3929 req.fbo = 0;
3930 /* Association of ring index with doorbell index and MSIX number */
3931 req.logical_id = cpu_to_le16(map_index);
3932
3933 switch (ring_type) {
3934 case HWRM_RING_ALLOC_TX:
3935 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3936 /* Association of transmit ring with completion ring */
3937 req.cmpl_ring_id =
3938 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3939 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3940 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3941 req.queue_id = cpu_to_le16(ring->queue_id);
3942 break;
3943 case HWRM_RING_ALLOC_RX:
3944 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3945 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3946 break;
3947 case HWRM_RING_ALLOC_AGG:
3948 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3949 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3950 break;
3951 case HWRM_RING_ALLOC_CMPL:
3952 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3953 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3954 if (bp->flags & BNXT_FLAG_USING_MSIX)
3955 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3956 break;
3957 default:
3958 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3959 ring_type);
3960 return -1;
3961 }
3962
3963 mutex_lock(&bp->hwrm_cmd_lock);
3964 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3965 err = le16_to_cpu(resp->error_code);
3966 ring_id = le16_to_cpu(resp->ring_id);
3967 mutex_unlock(&bp->hwrm_cmd_lock);
3968
3969 if (rc || err) {
3970 switch (ring_type) {
3971 case RING_FREE_REQ_RING_TYPE_CMPL:
3972 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3973 rc, err);
3974 return -1;
3975
3976 case RING_FREE_REQ_RING_TYPE_RX:
3977 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3978 rc, err);
3979 return -1;
3980
3981 case RING_FREE_REQ_RING_TYPE_TX:
3982 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3983 rc, err);
3984 return -1;
3985
3986 default:
3987 netdev_err(bp->dev, "Invalid ring\n");
3988 return -1;
3989 }
3990 }
3991 ring->fw_ring_id = ring_id;
3992 return rc;
3993}
3994
486b5c22
MC		 3995static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
3996{
3997 int rc;
3998
3999 if (BNXT_PF(bp)) {
4000 struct hwrm_func_cfg_input req = {0};
4001
4002 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4003 req.fid = cpu_to_le16(0xffff);
4004 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4005 req.async_event_cr = cpu_to_le16(idx);
4006 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4007 } else {
4008 struct hwrm_func_vf_cfg_input req = {0};
4009
4010 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4011 req.enables =
4012 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4013 req.async_event_cr = cpu_to_le16(idx);
4014 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4015 }
4016 return rc;
4017}
4018
c0c050c5
MC		 4019static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4020{
4021 int i, rc = 0;
4022
edd0c2cc
MC		 4023 for (i = 0; i < bp->cp_nr_rings; i++) {
4024 struct bnxt_napi *bnapi = bp->bnapi[i];
4025 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4026 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
c0c050c5 4027
33e52d88 4028 cpr->cp_doorbell = bp->bar1 + i * 0x80;
edd0c2cc
MC		 4029 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4030 INVALID_STATS_CTX_ID);
4031 if (rc)
4032 goto err_out;
edd0c2cc
MC		 4033 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4034 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
486b5c22
MC		 4035
4036 if (!i) {
4037 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4038 if (rc)
4039 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4040 }
c0c050c5
MC		 4041 }
4042
edd0c2cc 4043 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4044 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 4045 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 4046 u32 map_idx = txr->bnapi->index;
4047 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
c0c050c5 4048
b81a90d3
MC		 4049 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4050 map_idx, fw_stats_ctx);
edd0c2cc
MC		 4051 if (rc)
4052 goto err_out;
b81a90d3 4053 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 4054 }
4055
edd0c2cc 4056 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4057 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4058 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 4059 u32 map_idx = rxr->bnapi->index;
c0c050c5 4060
b81a90d3
MC		 4061 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4062 map_idx, INVALID_STATS_CTX_ID);
edd0c2cc
MC		 4063 if (rc)
4064 goto err_out;
b81a90d3 4065 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
edd0c2cc 4066 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
b81a90d3 4067 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 4068 }
4069
4070 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4071 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4072 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 4073 struct bnxt_ring_struct *ring =
4074 &rxr->rx_agg_ring_struct;
b81a90d3
MC		 4075 u32 grp_idx = rxr->bnapi->index;
4076 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5
MC		 4077
4078 rc = hwrm_ring_alloc_send_msg(bp, ring,
4079 HWRM_RING_ALLOC_AGG,
b81a90d3 4080 map_idx,
c0c050c5
MC		 4081 INVALID_STATS_CTX_ID);
4082 if (rc)
4083 goto err_out;
4084
b81a90d3 4085 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 4086 writel(DB_KEY_RX | rxr->rx_agg_prod,
4087 rxr->rx_agg_doorbell);
b81a90d3 4088 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 4089 }
4090 }
4091err_out:
4092 return rc;
4093}
4094
4095static int hwrm_ring_free_send_msg(struct bnxt *bp,
4096 struct bnxt_ring_struct *ring,
4097 u32 ring_type, int cmpl_ring_id)
4098{
4099 int rc;
4100 struct hwrm_ring_free_input req = {0};
4101 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4102 u16 error_code;
4103
74608fc9 4104 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 4105 req.ring_type = ring_type;
4106 req.ring_id = cpu_to_le16(ring->fw_ring_id);
4107
4108 mutex_lock(&bp->hwrm_cmd_lock);
4109 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4110 error_code = le16_to_cpu(resp->error_code);
4111 mutex_unlock(&bp->hwrm_cmd_lock);
4112
4113 if (rc || error_code) {
4114 switch (ring_type) {
4115 case RING_FREE_REQ_RING_TYPE_CMPL:
4116 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4117 rc);
4118 return rc;
4119 case RING_FREE_REQ_RING_TYPE_RX:
4120 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4121 rc);
4122 return rc;
4123 case RING_FREE_REQ_RING_TYPE_TX:
4124 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4125 rc);
4126 return rc;
4127 default:
4128 netdev_err(bp->dev, "Invalid ring\n");
4129 return -1;
4130 }
4131 }
4132 return 0;
4133}
4134
edd0c2cc 4135static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 4136{
edd0c2cc 4137 int i;
c0c050c5
MC		 4138
4139 if (!bp->bnapi)
edd0c2cc 4140 return;
c0c050c5 4141
edd0c2cc 4142 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4143 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 4144 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 4145 u32 grp_idx = txr->bnapi->index;
4146 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4147
4148 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4149 hwrm_ring_free_send_msg(bp, ring,
4150 RING_FREE_REQ_RING_TYPE_TX,
4151 close_path ? cmpl_ring_id :
4152 INVALID_HW_RING_ID);
4153 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4154 }
4155 }
4156
edd0c2cc 4157 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4158 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4159 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3
MC		 4160 u32 grp_idx = rxr->bnapi->index;
4161 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4162
4163 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4164 hwrm_ring_free_send_msg(bp, ring,
4165 RING_FREE_REQ_RING_TYPE_RX,
4166 close_path ? cmpl_ring_id :
4167 INVALID_HW_RING_ID);
4168 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4169 bp->grp_info[grp_idx].rx_fw_ring_id =
4170 INVALID_HW_RING_ID;
c0c050c5
MC		 4171 }
4172 }
4173
edd0c2cc 4174 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4175 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4176 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3
MC		 4177 u32 grp_idx = rxr->bnapi->index;
4178 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4179
4180 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4181 hwrm_ring_free_send_msg(bp, ring,
4182 RING_FREE_REQ_RING_TYPE_RX,
4183 close_path ? cmpl_ring_id :
4184 INVALID_HW_RING_ID);
4185 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4186 bp->grp_info[grp_idx].agg_fw_ring_id =
4187 INVALID_HW_RING_ID;
c0c050c5
MC		 4188 }
4189 }
4190
9d8bc097
MC		 4191 /* The completion rings are about to be freed. After that the
4192 * IRQ doorbell will not work anymore. So we need to disable
4193 * IRQ here.
4194 */
4195 bnxt_disable_int_sync(bp);
4196
edd0c2cc
MC		 4197 for (i = 0; i < bp->cp_nr_rings; i++) {
4198 struct bnxt_napi *bnapi = bp->bnapi[i];
4199 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4200 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4201
4202 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4203 hwrm_ring_free_send_msg(bp, ring,
4204 RING_FREE_REQ_RING_TYPE_CMPL,
4205 INVALID_HW_RING_ID);
4206 ring->fw_ring_id = INVALID_HW_RING_ID;
4207 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4208 }
4209 }
c0c050c5
MC		 4210}
4211
391be5c2
MC		 4212/* Caller must hold bp->hwrm_cmd_lock */
4213int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4214{
4215 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4216 struct hwrm_func_qcfg_input req = {0};
4217 int rc;
4218
4219 if (bp->hwrm_spec_code < 0x10601)
4220 return 0;
4221
4222 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4223 req.fid = cpu_to_le16(fid);
4224 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4225 if (!rc)
4226 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4227
4228 return rc;
4229}
4230
d1e7925e 4231static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
391be5c2
MC		 4232{
4233 struct hwrm_func_cfg_input req = {0};
4234 int rc;
4235
4236 if (bp->hwrm_spec_code < 0x10601)
4237 return 0;
4238
4239 if (BNXT_VF(bp))
4240 return 0;
4241
4242 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4243 req.fid = cpu_to_le16(0xffff);
4244 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4245 req.num_tx_rings = cpu_to_le16(*tx_rings);
4246 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4247 if (rc)
4248 return rc;
4249
4250 mutex_lock(&bp->hwrm_cmd_lock);
4251 rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4252 mutex_unlock(&bp->hwrm_cmd_lock);
4253 return rc;
4254}
4255
bb053f52
MC		 4256static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
4257 u32 buf_tmrs, u16 flags,
4258 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4259{
4260 req->flags = cpu_to_le16(flags);
4261 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
4262 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
4263 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
4264 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
4265 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4266 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
4267 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
4268 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
4269}
4270
c0c050c5
MC		 4271int bnxt_hwrm_set_coal(struct bnxt *bp)
4272{
4273 int i, rc = 0;
dfc9c94a
MC		 4274 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4275 req_tx = {0}, *req;
c0c050c5
MC		 4276 u16 max_buf, max_buf_irq;
4277 u16 buf_tmr, buf_tmr_irq;
4278 u32 flags;
4279
dfc9c94a
MC		 4280 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4281 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4282 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4283 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
c0c050c5 4284
dfb5b894
MC		 4285 /* Each rx completion (2 records) should be DMAed immediately.
4286 * DMA 1/4 of the completion buffers at a time.
4287 */
4288 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
c0c050c5
MC		 4289 /* max_buf must not be zero */
4290 max_buf = clamp_t(u16, max_buf, 1, 63);
dfb5b894
MC		 4291 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4292 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4293 /* buf timer set to 1/4 of interrupt timer */
4294 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4295 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4296 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
c0c050c5
MC		 4297
4298 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4299
4300 /* RING_IDLE generates more IRQs for lower latency. Enable it only
4301 * if coal_ticks is less than 25 us.
4302 */
dfb5b894 4303 if (bp->rx_coal_ticks < 25)
c0c050c5
MC		 4304 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4305
bb053f52 4306 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
dfc9c94a
MC		 4307 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4308
4309 /* max_buf must not be zero */
4310 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4311 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4312 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4313 /* buf timer set to 1/4 of interrupt timer */
4314 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4315 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4316 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4317
4318 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4319 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4320 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
c0c050c5
MC		 4321
4322 mutex_lock(&bp->hwrm_cmd_lock);
4323 for (i = 0; i < bp->cp_nr_rings; i++) {
dfc9c94a 4324 struct bnxt_napi *bnapi = bp->bnapi[i];
c0c050c5 4325
dfc9c94a
MC		 4326 req = &req_rx;
4327 if (!bnapi->rx_ring)
4328 req = &req_tx;
4329 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4330
4331 rc = _hwrm_send_message(bp, req, sizeof(*req),
c0c050c5
MC		 4332 HWRM_CMD_TIMEOUT);
4333 if (rc)
4334 break;
4335 }
4336 mutex_unlock(&bp->hwrm_cmd_lock);
4337 return rc;
4338}
4339
4340static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4341{
4342 int rc = 0, i;
4343 struct hwrm_stat_ctx_free_input req = {0};
4344
4345 if (!bp->bnapi)
4346 return 0;
4347
3e8060fa
PS		 4348 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4349 return 0;
4350
c0c050c5
MC		 4351 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4352
4353 mutex_lock(&bp->hwrm_cmd_lock);
4354 for (i = 0; i < bp->cp_nr_rings; i++) {
4355 struct bnxt_napi *bnapi = bp->bnapi[i];
4356 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4357
4358 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4359 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4360
4361 rc = _hwrm_send_message(bp, &req, sizeof(req),
4362 HWRM_CMD_TIMEOUT);
4363 if (rc)
4364 break;
4365
4366 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4367 }
4368 }
4369 mutex_unlock(&bp->hwrm_cmd_lock);
4370 return rc;
4371}
4372
4373static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4374{
4375 int rc = 0, i;
4376 struct hwrm_stat_ctx_alloc_input req = {0};
4377 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4378
3e8060fa
PS		 4379 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4380 return 0;
4381
c0c050c5
MC		 4382 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4383
51f30785 4384 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
c0c050c5
MC		 4385
4386 mutex_lock(&bp->hwrm_cmd_lock);
4387 for (i = 0; i < bp->cp_nr_rings; i++) {
4388 struct bnxt_napi *bnapi = bp->bnapi[i];
4389 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4390
4391 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4392
4393 rc = _hwrm_send_message(bp, &req, sizeof(req),
4394 HWRM_CMD_TIMEOUT);
4395 if (rc)
4396 break;
4397
4398 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4399
4400 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4401 }
4402 mutex_unlock(&bp->hwrm_cmd_lock);
89aa8445 4403 return rc;
c0c050c5
MC		 4404}
4405
cf6645f8
MC		 4406static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4407{
4408 struct hwrm_func_qcfg_input req = {0};
567b2abe 4409 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
cf6645f8
MC		 4410 int rc;
4411
4412 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4413 req.fid = cpu_to_le16(0xffff);
4414 mutex_lock(&bp->hwrm_cmd_lock);
4415 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4416 if (rc)
4417 goto func_qcfg_exit;
4418
4419#ifdef CONFIG_BNXT_SRIOV
4420 if (BNXT_VF(bp)) {
cf6645f8
MC		 4421 struct bnxt_vf_info *vf = &bp->vf;
4422
4423 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4424 }
4425#endif
567b2abe
SB		 4426 switch (resp->port_partition_type) {
4427 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4428 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4429 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4430 bp->port_partition_type = resp->port_partition_type;
4431 break;
4432 }
cf6645f8
MC		 4433
4434func_qcfg_exit:
4435 mutex_unlock(&bp->hwrm_cmd_lock);
4436 return rc;
4437}
4438
7b08f661 4439static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 4440{
4441 int rc = 0;
4442 struct hwrm_func_qcaps_input req = {0};
4443 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4444
4445 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4446 req.fid = cpu_to_le16(0xffff);
4447
4448 mutex_lock(&bp->hwrm_cmd_lock);
4449 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4450 if (rc)
4451 goto hwrm_func_qcaps_exit;
4452
e4060d30
MC		 4453 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4454 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4455 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4456 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4457
7cc5a20e
MC		 4458 bp->tx_push_thresh = 0;
4459 if (resp->flags &
4460 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4461 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4462
c0c050c5
MC		 4463 if (BNXT_PF(bp)) {
4464 struct bnxt_pf_info *pf = &bp->pf;
4465
4466 pf->fw_fid = le16_to_cpu(resp->fid);
4467 pf->port_id = le16_to_cpu(resp->port_id);
87027db1 4468 bp->dev->dev_port = pf->port_id;
11f15ed3 4469 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
bdd4347b 4470 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
c0c050c5
MC		 4471 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4472 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4473 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
c0c050c5 4474 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4475 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4476 if (!pf->max_hw_ring_grps)
4477 pf->max_hw_ring_grps = pf->max_tx_rings;
c0c050c5
MC		 4478 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4479 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4480 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4481 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4482 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4483 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4484 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4485 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4486 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4487 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4488 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4489 } else {
379a80a1 4490#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 4491 struct bnxt_vf_info *vf = &bp->vf;
4492
4493 vf->fw_fid = le16_to_cpu(resp->fid);
c0c050c5
MC		 4494
4495 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4496 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4497 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4498 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4499 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4500 if (!vf->max_hw_ring_grps)
4501 vf->max_hw_ring_grps = vf->max_tx_rings;
c0c050c5
MC		 4502 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4503 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4504 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7cc5a20e
MC		 4505
4506 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
001154eb
MC		 4507 mutex_unlock(&bp->hwrm_cmd_lock);
4508
4509 if (is_valid_ether_addr(vf->mac_addr)) {
7cc5a20e
MC		 4510 /* overwrite netdev dev_adr with admin VF MAC */
4511 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
001154eb 4512 } else {
7cc5a20e 4513 random_ether_addr(bp->dev->dev_addr);
001154eb
MC		 4514 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4515 }
4516 return rc;
379a80a1 4517#endif
c0c050c5
MC		 4518 }
4519
c0c050c5
MC		 4520hwrm_func_qcaps_exit:
4521 mutex_unlock(&bp->hwrm_cmd_lock);
4522 return rc;
4523}
4524
4525static int bnxt_hwrm_func_reset(struct bnxt *bp)
4526{
4527 struct hwrm_func_reset_input req = {0};
4528
4529 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4530 req.enables = 0;
4531
4532 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4533}
4534
4535static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4536{
4537 int rc = 0;
4538 struct hwrm_queue_qportcfg_input req = {0};
4539 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4540 u8 i, *qptr;
4541
4542 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4543
4544 mutex_lock(&bp->hwrm_cmd_lock);
4545 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4546 if (rc)
4547 goto qportcfg_exit;
4548
4549 if (!resp->max_configurable_queues) {
4550 rc = -EINVAL;
4551 goto qportcfg_exit;
4552 }
4553 bp->max_tc = resp->max_configurable_queues;
87c374de 4554 bp->max_lltc = resp->max_configurable_lossless_queues;
c0c050c5
MC		 4555 if (bp->max_tc > BNXT_MAX_QUEUE)
4556 bp->max_tc = BNXT_MAX_QUEUE;
4557
441cabbb
MC		 4558 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4559 bp->max_tc = 1;
4560
87c374de
MC		 4561 if (bp->max_lltc > bp->max_tc)
4562 bp->max_lltc = bp->max_tc;
4563
c0c050c5
MC		 4564 qptr = &resp->queue_id0;
4565 for (i = 0; i < bp->max_tc; i++) {
4566 bp->q_info[i].queue_id = *qptr++;
4567 bp->q_info[i].queue_profile = *qptr++;
4568 }
4569
4570qportcfg_exit:
4571 mutex_unlock(&bp->hwrm_cmd_lock);
4572 return rc;
4573}
4574
4575static int bnxt_hwrm_ver_get(struct bnxt *bp)
4576{
4577 int rc;
4578 struct hwrm_ver_get_input req = {0};
4579 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4580
e6ef2699 4581 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
c0c050c5
MC		 4582 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4583 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4584 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4585 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4586 mutex_lock(&bp->hwrm_cmd_lock);
4587 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4588 if (rc)
4589 goto hwrm_ver_get_exit;
4590
4591 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4592
11f15ed3
MC		 4593 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4594 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
c193554e
MC		 4595 if (resp->hwrm_intf_maj < 1) {
4596 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
c0c050c5 4597 resp->hwrm_intf_maj, resp->hwrm_intf_min,
c193554e
MC		 4598 resp->hwrm_intf_upd);
4599 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5 4600 }
3ebf6f0a 4601 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
c0c050c5
MC		 4602 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4603 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4604
ff4fe81d
MC		 4605 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4606 if (!bp->hwrm_cmd_timeout)
4607 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4608
e6ef2699
MC		 4609 if (resp->hwrm_intf_maj >= 1)
4610 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4611
659c805c 4612 bp->chip_num = le16_to_cpu(resp->chip_num);
3e8060fa
PS		 4613 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4614 !resp->chip_metal)
4615 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
659c805c 4616
c0c050c5
MC		 4617hwrm_ver_get_exit:
4618 mutex_unlock(&bp->hwrm_cmd_lock);
4619 return rc;
4620}
4621
5ac67d8b
RS		 4622int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4623{
878786d9 4624#if IS_ENABLED(CONFIG_RTC_LIB)
5ac67d8b
RS		 4625 struct hwrm_fw_set_time_input req = {0};
4626 struct rtc_time tm;
4627 struct timeval tv;
4628
4629 if (bp->hwrm_spec_code < 0x10400)
4630 return -EOPNOTSUPP;
4631
4632 do_gettimeofday(&tv);
4633 rtc_time_to_tm(tv.tv_sec, &tm);
4634 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4635 req.year = cpu_to_le16(1900 + tm.tm_year);
4636 req.month = 1 + tm.tm_mon;
4637 req.day = tm.tm_mday;
4638 req.hour = tm.tm_hour;
4639 req.minute = tm.tm_min;
4640 req.second = tm.tm_sec;
4641 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
878786d9
RS		 4642#else
4643 return -EOPNOTSUPP;
4644#endif
5ac67d8b
RS		 4645}
4646
3bdf56c4
MC		 4647static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4648{
4649 int rc;
4650 struct bnxt_pf_info *pf = &bp->pf;
4651 struct hwrm_port_qstats_input req = {0};
4652
4653 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4654 return 0;
4655
4656 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4657 req.port_id = cpu_to_le16(pf->port_id);
4658 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4659 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4660 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4661 return rc;
4662}
4663
c0c050c5
MC		 4664static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4665{
4666 if (bp->vxlan_port_cnt) {
4667 bnxt_hwrm_tunnel_dst_port_free(
4668 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4669 }
4670 bp->vxlan_port_cnt = 0;
4671 if (bp->nge_port_cnt) {
4672 bnxt_hwrm_tunnel_dst_port_free(
4673 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4674 }
4675 bp->nge_port_cnt = 0;
4676}
4677
4678static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4679{
4680 int rc, i;
4681 u32 tpa_flags = 0;
4682
4683 if (set_tpa)
4684 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4685 for (i = 0; i < bp->nr_vnics; i++) {
4686 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4687 if (rc) {
4688 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4689 rc, i);
4690 return rc;
4691 }
4692 }
4693 return 0;
4694}
4695
4696static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4697{
4698 int i;
4699
4700 for (i = 0; i < bp->nr_vnics; i++)
4701 bnxt_hwrm_vnic_set_rss(bp, i, false);
4702}
4703
4704static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4705 bool irq_re_init)
4706{
4707 if (bp->vnic_info) {
4708 bnxt_hwrm_clear_vnic_filter(bp);
4709 /* clear all RSS setting before free vnic ctx */
4710 bnxt_hwrm_clear_vnic_rss(bp);
4711 bnxt_hwrm_vnic_ctx_free(bp);
4712 /* before free the vnic, undo the vnic tpa settings */
4713 if (bp->flags & BNXT_FLAG_TPA)
4714 bnxt_set_tpa(bp, false);
4715 bnxt_hwrm_vnic_free(bp);
4716 }
4717 bnxt_hwrm_ring_free(bp, close_path);
4718 bnxt_hwrm_ring_grp_free(bp);
4719 if (irq_re_init) {
4720 bnxt_hwrm_stat_ctx_free(bp);
4721 bnxt_hwrm_free_tunnel_ports(bp);
4722 }
4723}
4724
4725static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4726{
ae10ae74 4727 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
c0c050c5
MC		 4728 int rc;
4729
ae10ae74
MC		 4730 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
4731 goto skip_rss_ctx;
4732
c0c050c5 4733 /* allocate context for vnic */
94ce9caa 4734 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
c0c050c5
MC		 4735 if (rc) {
4736 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4737 vnic_id, rc);
4738 goto vnic_setup_err;
4739 }
4740 bp->rsscos_nr_ctxs++;
4741
94ce9caa
PS		 4742 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4743 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4744 if (rc) {
4745 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4746 vnic_id, rc);
4747 goto vnic_setup_err;
4748 }
4749 bp->rsscos_nr_ctxs++;
4750 }
4751
ae10ae74 4752skip_rss_ctx:
c0c050c5
MC		 4753 /* configure default vnic, ring grp */
4754 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4755 if (rc) {
4756 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4757 vnic_id, rc);
4758 goto vnic_setup_err;
4759 }
4760
4761 /* Enable RSS hashing on vnic */
4762 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4763 if (rc) {
4764 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4765 vnic_id, rc);
4766 goto vnic_setup_err;
4767 }
4768
4769 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4770 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4771 if (rc) {
4772 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4773 vnic_id, rc);
4774 }
4775 }
4776
4777vnic_setup_err:
4778 return rc;
4779}
4780
4781static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4782{
4783#ifdef CONFIG_RFS_ACCEL
4784 int i, rc = 0;
4785
4786 for (i = 0; i < bp->rx_nr_rings; i++) {
ae10ae74 4787 struct bnxt_vnic_info *vnic;
c0c050c5
MC		 4788 u16 vnic_id = i + 1;
4789 u16 ring_id = i;
4790
4791 if (vnic_id >= bp->nr_vnics)
4792 break;
4793
ae10ae74
MC		 4794 vnic = &bp->vnic_info[vnic_id];
4795 vnic->flags |= BNXT_VNIC_RFS_FLAG;
4796 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
4797 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
b81a90d3 4798 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 4799 if (rc) {
4800 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4801 vnic_id, rc);
4802 break;
4803 }
4804 rc = bnxt_setup_vnic(bp, vnic_id);
4805 if (rc)
4806 break;
4807 }
4808 return rc;
4809#else
4810 return 0;
4811#endif
4812}
4813
17c71ac3
MC		 4814/* Allow PF and VF with default VLAN to be in promiscuous mode */
4815static bool bnxt_promisc_ok(struct bnxt *bp)
4816{
4817#ifdef CONFIG_BNXT_SRIOV
4818 if (BNXT_VF(bp) && !bp->vf.vlan)
4819 return false;
4820#endif
4821 return true;
4822}
4823
dc52c6c7
PS		 4824static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4825{
4826 unsigned int rc = 0;
4827
4828 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4829 if (rc) {
4830 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4831 rc);
4832 return rc;
4833 }
4834
4835 rc = bnxt_hwrm_vnic_cfg(bp, 1);
4836 if (rc) {
4837 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4838 rc);
4839 return rc;
4840 }
4841 return rc;
4842}
4843
b664f008 4844static int bnxt_cfg_rx_mode(struct bnxt *);
7d2837dd 4845static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
b664f008 4846
c0c050c5
MC		 4847static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4848{
7d2837dd 4849 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
c0c050c5 4850 int rc = 0;
76595193 4851 unsigned int rx_nr_rings = bp->rx_nr_rings;
c0c050c5
MC		 4852
4853 if (irq_re_init) {
4854 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4855 if (rc) {
4856 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4857 rc);
4858 goto err_out;
4859 }
4860 }
4861
4862 rc = bnxt_hwrm_ring_alloc(bp);
4863 if (rc) {
4864 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4865 goto err_out;
4866 }
4867
4868 rc = bnxt_hwrm_ring_grp_alloc(bp);
4869 if (rc) {
4870 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4871 goto err_out;
4872 }
4873
76595193
PS		 4874 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4875 rx_nr_rings--;
4876
c0c050c5 4877 /* default vnic 0 */
76595193 4878 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
c0c050c5
MC		 4879 if (rc) {
4880 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4881 goto err_out;
4882 }
4883
4884 rc = bnxt_setup_vnic(bp, 0);
4885 if (rc)
4886 goto err_out;
4887
4888 if (bp->flags & BNXT_FLAG_RFS) {
4889 rc = bnxt_alloc_rfs_vnics(bp);
4890 if (rc)
4891 goto err_out;
4892 }
4893
4894 if (bp->flags & BNXT_FLAG_TPA) {
4895 rc = bnxt_set_tpa(bp, true);
4896 if (rc)
4897 goto err_out;
4898 }
4899
4900 if (BNXT_VF(bp))
4901 bnxt_update_vf_mac(bp);
4902
4903 /* Filter for default vnic 0 */
4904 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4905 if (rc) {
4906 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4907 goto err_out;
4908 }
7d2837dd 4909 vnic->uc_filter_count = 1;
c0c050c5 4910
7d2837dd 4911 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5 4912
17c71ac3 4913 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7d2837dd
MC		 4914 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4915
4916 if (bp->dev->flags & IFF_ALLMULTI) {
4917 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4918 vnic->mc_list_count = 0;
4919 } else {
4920 u32 mask = 0;
4921
4922 bnxt_mc_list_updated(bp, &mask);
4923 vnic->rx_mask |= mask;
4924 }
c0c050c5 4925
b664f008
MC		 4926 rc = bnxt_cfg_rx_mode(bp);
4927 if (rc)
c0c050c5 4928 goto err_out;
c0c050c5
MC		 4929
4930 rc = bnxt_hwrm_set_coal(bp);
4931 if (rc)
4932 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
dc52c6c7
PS		 4933 rc);
4934
4935 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4936 rc = bnxt_setup_nitroa0_vnic(bp);
4937 if (rc)
4938 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
4939 rc);
4940 }
c0c050c5 4941
cf6645f8
MC		 4942 if (BNXT_VF(bp)) {
4943 bnxt_hwrm_func_qcfg(bp);
4944 netdev_update_features(bp->dev);
4945 }
4946
c0c050c5
MC		 4947 return 0;
4948
4949err_out:
4950 bnxt_hwrm_resource_free(bp, 0, true);
4951
4952 return rc;
4953}
4954
4955static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4956{
4957 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4958 return 0;
4959}
4960
4961static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4962{
4963 bnxt_init_rx_rings(bp);
4964 bnxt_init_tx_rings(bp);
4965 bnxt_init_ring_grps(bp, irq_re_init);
4966 bnxt_init_vnics(bp);
4967
4968 return bnxt_init_chip(bp, irq_re_init);
4969}
4970
c0c050c5
MC		 4971static int bnxt_set_real_num_queues(struct bnxt *bp)
4972{
4973 int rc;
4974 struct net_device *dev = bp->dev;
4975
5f449249
MC		 4976 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
4977 bp->tx_nr_rings_xdp);
c0c050c5
MC		 4978 if (rc)
4979 return rc;
4980
4981 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4982 if (rc)
4983 return rc;
4984
4985#ifdef CONFIG_RFS_ACCEL
45019a18 4986 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 4987 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 4988#endif
4989
4990 return rc;
4991}
4992
6e6c5a57
MC		 4993static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4994 bool shared)
4995{
4996 int _rx = *rx, _tx = *tx;
4997
4998 if (shared) {
4999 *rx = min_t(int, _rx, max);
5000 *tx = min_t(int, _tx, max);
5001 } else {
5002 if (max < 2)
5003 return -ENOMEM;
5004
5005 while (_rx + _tx > max) {
5006 if (_rx > _tx && _rx > 1)
5007 _rx--;
5008 else if (_tx > 1)
5009 _tx--;
5010 }
5011 *rx = _rx;
5012 *tx = _tx;
5013 }
5014 return 0;
5015}
5016
7809592d
MC		 5017static void bnxt_setup_msix(struct bnxt *bp)
5018{
5019 const int len = sizeof(bp->irq_tbl[0].name);
5020 struct net_device *dev = bp->dev;
5021 int tcs, i;
5022
5023 tcs = netdev_get_num_tc(dev);
5024 if (tcs > 1) {
d1e7925e 5025 int i, off, count;
7809592d 5026
d1e7925e
MC		 5027 for (i = 0; i < tcs; i++) {
5028 count = bp->tx_nr_rings_per_tc;
5029 off = i * count;
5030 netdev_set_tc_queue(dev, i, count, off);
7809592d
MC		 5031 }
5032 }
5033
5034 for (i = 0; i < bp->cp_nr_rings; i++) {
5035 char *attr;
5036
5037 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5038 attr = "TxRx";
5039 else if (i < bp->rx_nr_rings)
5040 attr = "rx";
5041 else
5042 attr = "tx";
5043
5044 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5045 i);
5046 bp->irq_tbl[i].handler = bnxt_msix;
5047 }
5048}
5049
5050static void bnxt_setup_inta(struct bnxt *bp)
5051{
5052 const int len = sizeof(bp->irq_tbl[0].name);
5053
5054 if (netdev_get_num_tc(bp->dev))
5055 netdev_reset_tc(bp->dev);
5056
5057 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5058 0);
5059 bp->irq_tbl[0].handler = bnxt_inta;
5060}
5061
5062static int bnxt_setup_int_mode(struct bnxt *bp)
5063{
5064 int rc;
5065
5066 if (bp->flags & BNXT_FLAG_USING_MSIX)
5067 bnxt_setup_msix(bp);
5068 else
5069 bnxt_setup_inta(bp);
5070
5071 rc = bnxt_set_real_num_queues(bp);
5072 return rc;
5073}
5074
b7429954 5075#ifdef CONFIG_RFS_ACCEL
8079e8f1
MC		 5076static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5077{
5078#if defined(CONFIG_BNXT_SRIOV)
5079 if (BNXT_VF(bp))
5080 return bp->vf.max_rsscos_ctxs;
5081#endif
5082 return bp->pf.max_rsscos_ctxs;
5083}
5084
5085static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5086{
5087#if defined(CONFIG_BNXT_SRIOV)
5088 if (BNXT_VF(bp))
5089 return bp->vf.max_vnics;
5090#endif
5091 return bp->pf.max_vnics;
5092}
b7429954 5093#endif
8079e8f1 5094
e4060d30
MC		 5095unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5096{
5097#if defined(CONFIG_BNXT_SRIOV)
5098 if (BNXT_VF(bp))
5099 return bp->vf.max_stat_ctxs;
5100#endif
5101 return bp->pf.max_stat_ctxs;
5102}
5103
a588e458
MC		 5104void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5105{
5106#if defined(CONFIG_BNXT_SRIOV)
5107 if (BNXT_VF(bp))
5108 bp->vf.max_stat_ctxs = max;
5109 else
5110#endif
5111 bp->pf.max_stat_ctxs = max;
5112}
5113
e4060d30
MC		 5114unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5115{
5116#if defined(CONFIG_BNXT_SRIOV)
5117 if (BNXT_VF(bp))
5118 return bp->vf.max_cp_rings;
5119#endif
5120 return bp->pf.max_cp_rings;
5121}
5122
a588e458
MC		 5123void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5124{
5125#if defined(CONFIG_BNXT_SRIOV)
5126 if (BNXT_VF(bp))
5127 bp->vf.max_cp_rings = max;
5128 else
5129#endif
5130 bp->pf.max_cp_rings = max;
5131}
5132
7809592d
MC		 5133static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5134{
5135#if defined(CONFIG_BNXT_SRIOV)
5136 if (BNXT_VF(bp))
5137 return bp->vf.max_irqs;
5138#endif
5139 return bp->pf.max_irqs;
5140}
5141
33c2657e
MC		 5142void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5143{
5144#if defined(CONFIG_BNXT_SRIOV)
5145 if (BNXT_VF(bp))
5146 bp->vf.max_irqs = max_irqs;
5147 else
5148#endif
5149 bp->pf.max_irqs = max_irqs;
5150}
5151
7809592d 5152static int bnxt_init_msix(struct bnxt *bp)
c0c050c5 5153{
01657bcd 5154 int i, total_vecs, rc = 0, min = 1;
7809592d 5155 struct msix_entry *msix_ent;
c0c050c5 5156
7809592d 5157 total_vecs = bnxt_get_max_func_irqs(bp);
c0c050c5
MC		 5158 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5159 if (!msix_ent)
5160 return -ENOMEM;
5161
5162 for (i = 0; i < total_vecs; i++) {
5163 msix_ent[i].entry = i;
5164 msix_ent[i].vector = 0;
5165 }
5166
01657bcd
MC		 5167 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5168 min = 2;
5169
5170 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
c0c050c5
MC		 5171 if (total_vecs < 0) {
5172 rc = -ENODEV;
5173 goto msix_setup_exit;
5174 }
5175
5176 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5177 if (bp->irq_tbl) {
7809592d
MC		 5178 for (i = 0; i < total_vecs; i++)
5179 bp->irq_tbl[i].vector = msix_ent[i].vector;
c0c050c5 5180
7809592d 5181 bp->total_irqs = total_vecs;
c0c050c5 5182 /* Trim rings based upon num of vectors allocated */
6e6c5a57 5183 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
01657bcd 5184 total_vecs, min == 1);
6e6c5a57
MC		 5185 if (rc)
5186 goto msix_setup_exit;
5187
c0c050c5 5188 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7809592d
MC		 5189 bp->cp_nr_rings = (min == 1) ?
5190 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5191 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5 5192
c0c050c5
MC		 5193 } else {
5194 rc = -ENOMEM;
5195 goto msix_setup_exit;
5196 }
5197 bp->flags |= BNXT_FLAG_USING_MSIX;
5198 kfree(msix_ent);
5199 return 0;
5200
5201msix_setup_exit:
7809592d
MC		 5202 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5203 kfree(bp->irq_tbl);
5204 bp->irq_tbl = NULL;
c0c050c5
MC		 5205 pci_disable_msix(bp->pdev);
5206 kfree(msix_ent);
5207 return rc;
5208}
5209
7809592d 5210static int bnxt_init_inta(struct bnxt *bp)
c0c050c5 5211{
c0c050c5 5212 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7809592d
MC		 5213 if (!bp->irq_tbl)
5214 return -ENOMEM;
5215
5216 bp->total_irqs = 1;
c0c050c5
MC		 5217 bp->rx_nr_rings = 1;
5218 bp->tx_nr_rings = 1;
5219 bp->cp_nr_rings = 1;
5220 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
01657bcd 5221 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5 5222 bp->irq_tbl[0].vector = bp->pdev->irq;
7809592d 5223 return 0;
c0c050c5
MC		 5224}
5225
7809592d 5226static int bnxt_init_int_mode(struct bnxt *bp)
c0c050c5
MC		 5227{
5228 int rc = 0;
5229
5230 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7809592d 5231 rc = bnxt_init_msix(bp);
c0c050c5 5232
1fa72e29 5233 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
c0c050c5 5234 /* fallback to INTA */
7809592d 5235 rc = bnxt_init_inta(bp);
c0c050c5
MC		 5236 }
5237 return rc;
5238}
5239
7809592d
MC		 5240static void bnxt_clear_int_mode(struct bnxt *bp)
5241{
5242 if (bp->flags & BNXT_FLAG_USING_MSIX)
5243 pci_disable_msix(bp->pdev);
5244
5245 kfree(bp->irq_tbl);
5246 bp->irq_tbl = NULL;
5247 bp->flags &= ~BNXT_FLAG_USING_MSIX;
5248}
5249
c0c050c5
MC		 5250static void bnxt_free_irq(struct bnxt *bp)
5251{
5252 struct bnxt_irq *irq;
5253 int i;
5254
5255#ifdef CONFIG_RFS_ACCEL
5256 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5257 bp->dev->rx_cpu_rmap = NULL;
5258#endif
5259 if (!bp->irq_tbl)
5260 return;
5261
5262 for (i = 0; i < bp->cp_nr_rings; i++) {
5263 irq = &bp->irq_tbl[i];
5264 if (irq->requested)
5265 free_irq(irq->vector, bp->bnapi[i]);
5266 irq->requested = 0;
5267 }
c0c050c5
MC		 5268}
5269
5270static int bnxt_request_irq(struct bnxt *bp)
5271{
b81a90d3 5272 int i, j, rc = 0;
c0c050c5
MC		 5273 unsigned long flags = 0;
5274#ifdef CONFIG_RFS_ACCEL
5275 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5276#endif
5277
5278 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5279 flags = IRQF_SHARED;
5280
b81a90d3 5281 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
c0c050c5
MC		 5282 struct bnxt_irq *irq = &bp->irq_tbl[i];
5283#ifdef CONFIG_RFS_ACCEL
b81a90d3 5284 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 5285 rc = irq_cpu_rmap_add(rmap, irq->vector);
5286 if (rc)
5287 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 5288 j);
5289 j++;
c0c050c5
MC		 5290 }
5291#endif
5292 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5293 bp->bnapi[i]);
5294 if (rc)
5295 break;
5296
5297 irq->requested = 1;
5298 }
5299 return rc;
5300}
5301
5302static void bnxt_del_napi(struct bnxt *bp)
5303{
5304 int i;
5305
5306 if (!bp->bnapi)
5307 return;
5308
5309 for (i = 0; i < bp->cp_nr_rings; i++) {
5310 struct bnxt_napi *bnapi = bp->bnapi[i];
5311
5312 napi_hash_del(&bnapi->napi);
5313 netif_napi_del(&bnapi->napi);
5314 }
e5f6f564
ED		 5315 /* We called napi_hash_del() before netif_napi_del(), we need
5316 * to respect an RCU grace period before freeing napi structures.
5317 */
5318 synchronize_net();
c0c050c5
MC		 5319}
5320
5321static void bnxt_init_napi(struct bnxt *bp)
5322{
5323 int i;
10bbdaf5 5324 unsigned int cp_nr_rings = bp->cp_nr_rings;
c0c050c5
MC		 5325 struct bnxt_napi *bnapi;
5326
5327 if (bp->flags & BNXT_FLAG_USING_MSIX) {
10bbdaf5
PS		 5328 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5329 cp_nr_rings--;
5330 for (i = 0; i < cp_nr_rings; i++) {
c0c050c5
MC		 5331 bnapi = bp->bnapi[i];
5332 netif_napi_add(bp->dev, &bnapi->napi,
5333 bnxt_poll, 64);
c0c050c5 5334 }
10bbdaf5
PS		 5335 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5336 bnapi = bp->bnapi[cp_nr_rings];
5337 netif_napi_add(bp->dev, &bnapi->napi,
5338 bnxt_poll_nitroa0, 64);
10bbdaf5 5339 }
c0c050c5
MC		 5340 } else {
5341 bnapi = bp->bnapi[0];
5342 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 5343 }
5344}
5345
5346static void bnxt_disable_napi(struct bnxt *bp)
5347{
5348 int i;
5349
5350 if (!bp->bnapi)
5351 return;
5352
b356a2e7 5353 for (i = 0; i < bp->cp_nr_rings; i++)
c0c050c5 5354 napi_disable(&bp->bnapi[i]->napi);
c0c050c5
MC		 5355}
5356
5357static void bnxt_enable_napi(struct bnxt *bp)
5358{
5359 int i;
5360
5361 for (i = 0; i < bp->cp_nr_rings; i++) {
fa7e2812 5362 bp->bnapi[i]->in_reset = false;
c0c050c5
MC		 5363 napi_enable(&bp->bnapi[i]->napi);
5364 }
5365}
5366
7df4ae9f 5367void bnxt_tx_disable(struct bnxt *bp)
c0c050c5
MC		 5368{
5369 int i;
c0c050c5
MC		 5370 struct bnxt_tx_ring_info *txr;
5371 struct netdev_queue *txq;
5372
b6ab4b01 5373 if (bp->tx_ring) {
c0c050c5 5374 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 5375 txr = &bp->tx_ring[i];
c0c050c5 5376 txq = netdev_get_tx_queue(bp->dev, i);
c0c050c5 5377 txr->dev_state = BNXT_DEV_STATE_CLOSING;
c0c050c5
MC		 5378 }
5379 }
5380 /* Stop all TX queues */
5381 netif_tx_disable(bp->dev);
5382 netif_carrier_off(bp->dev);
5383}
5384
7df4ae9f 5385void bnxt_tx_enable(struct bnxt *bp)
c0c050c5
MC		 5386{
5387 int i;
c0c050c5
MC		 5388 struct bnxt_tx_ring_info *txr;
5389 struct netdev_queue *txq;
5390
5391 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 5392 txr = &bp->tx_ring[i];
c0c050c5
MC		 5393 txq = netdev_get_tx_queue(bp->dev, i);
5394 txr->dev_state = 0;
5395 }
5396 netif_tx_wake_all_queues(bp->dev);
5397 if (bp->link_info.link_up)
5398 netif_carrier_on(bp->dev);
5399}
5400
5401static void bnxt_report_link(struct bnxt *bp)
5402{
5403 if (bp->link_info.link_up) {
5404 const char *duplex;
5405 const char *flow_ctrl;
5406 u16 speed;
5407
5408 netif_carrier_on(bp->dev);
5409 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5410 duplex = "full";
5411 else
5412 duplex = "half";
5413 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5414 flow_ctrl = "ON - receive & transmit";
5415 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5416 flow_ctrl = "ON - transmit";
5417 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5418 flow_ctrl = "ON - receive";
5419 else
5420 flow_ctrl = "none";
5421 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5422 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
5423 speed, duplex, flow_ctrl);
170ce013
MC		 5424 if (bp->flags & BNXT_FLAG_EEE_CAP)
5425 netdev_info(bp->dev, "EEE is %s\n",
5426 bp->eee.eee_active ? "active" :
5427 "not active");
c0c050c5
MC		 5428 } else {
5429 netif_carrier_off(bp->dev);
5430 netdev_err(bp->dev, "NIC Link is Down\n");
5431 }
5432}
5433
170ce013
MC		 5434static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5435{
5436 int rc = 0;
5437 struct hwrm_port_phy_qcaps_input req = {0};
5438 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
93ed8117 5439 struct bnxt_link_info *link_info = &bp->link_info;
170ce013
MC		 5440
5441 if (bp->hwrm_spec_code < 0x10201)
5442 return 0;
5443
5444 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5445
5446 mutex_lock(&bp->hwrm_cmd_lock);
5447 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5448 if (rc)
5449 goto hwrm_phy_qcaps_exit;
5450
5451 if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5452 struct ethtool_eee *eee = &bp->eee;
5453 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5454
5455 bp->flags |= BNXT_FLAG_EEE_CAP;
5456 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5457 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5458 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5459 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5460 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5461 }
93ed8117
MC		 5462 link_info->support_auto_speeds =
5463 le16_to_cpu(resp->supported_speeds_auto_mode);
170ce013
MC		 5464
5465hwrm_phy_qcaps_exit:
5466 mutex_unlock(&bp->hwrm_cmd_lock);
5467 return rc;
5468}
5469
c0c050c5
MC		 5470static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5471{
5472 int rc = 0;
5473 struct bnxt_link_info *link_info = &bp->link_info;
5474 struct hwrm_port_phy_qcfg_input req = {0};
5475 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5476 u8 link_up = link_info->link_up;
286ef9d6 5477 u16 diff;
c0c050c5
MC		 5478
5479 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5480
5481 mutex_lock(&bp->hwrm_cmd_lock);
5482 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5483 if (rc) {
5484 mutex_unlock(&bp->hwrm_cmd_lock);
5485 return rc;
5486 }
5487
5488 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5489 link_info->phy_link_status = resp->link;
5490 link_info->duplex = resp->duplex;
5491 link_info->pause = resp->pause;
5492 link_info->auto_mode = resp->auto_mode;
5493 link_info->auto_pause_setting = resp->auto_pause;
3277360e 5494 link_info->lp_pause = resp->link_partner_adv_pause;
c0c050c5 5495 link_info->force_pause_setting = resp->force_pause;
c193554e 5496 link_info->duplex_setting = resp->duplex;
c0c050c5
MC		 5497 if (link_info->phy_link_status == BNXT_LINK_LINK)
5498 link_info->link_speed = le16_to_cpu(resp->link_speed);
5499 else
5500 link_info->link_speed = 0;
5501 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
c0c050c5
MC		 5502 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5503 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
3277360e
MC		 5504 link_info->lp_auto_link_speeds =
5505 le16_to_cpu(resp->link_partner_adv_speeds);
c0c050c5
MC		 5506 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5507 link_info->phy_ver[0] = resp->phy_maj;
5508 link_info->phy_ver[1] = resp->phy_min;
5509 link_info->phy_ver[2] = resp->phy_bld;
5510 link_info->media_type = resp->media_type;
03efbec0 5511 link_info->phy_type = resp->phy_type;
11f15ed3 5512 link_info->transceiver = resp->xcvr_pkg_type;
170ce013
MC		 5513 link_info->phy_addr = resp->eee_config_phy_addr &
5514 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
42ee18fe 5515 link_info->module_status = resp->module_status;
170ce013
MC		 5516
5517 if (bp->flags & BNXT_FLAG_EEE_CAP) {
5518 struct ethtool_eee *eee = &bp->eee;
5519 u16 fw_speeds;
5520
5521 eee->eee_active = 0;
5522 if (resp->eee_config_phy_addr &
5523 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5524 eee->eee_active = 1;
5525 fw_speeds = le16_to_cpu(
5526 resp->link_partner_adv_eee_link_speed_mask);
5527 eee->lp_advertised =
5528 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5529 }
5530
5531 /* Pull initial EEE config */
5532 if (!chng_link_state) {
5533 if (resp->eee_config_phy_addr &
5534 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5535 eee->eee_enabled = 1;
c0c050c5 5536
170ce013
MC		 5537 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5538 eee->advertised =
5539 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5540
5541 if (resp->eee_config_phy_addr &
5542 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5543 __le32 tmr;
5544
5545 eee->tx_lpi_enabled = 1;
5546 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5547 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5548 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5549 }
5550 }
5551 }
c0c050c5
MC		 5552 /* TODO: need to add more logic to report VF link */
5553 if (chng_link_state) {
5554 if (link_info->phy_link_status == BNXT_LINK_LINK)
5555 link_info->link_up = 1;
5556 else
5557 link_info->link_up = 0;
5558 if (link_up != link_info->link_up)
5559 bnxt_report_link(bp);
5560 } else {
5561 /* alwasy link down if not require to update link state */
5562 link_info->link_up = 0;
5563 }
5564 mutex_unlock(&bp->hwrm_cmd_lock);
286ef9d6
MC		 5565
5566 diff = link_info->support_auto_speeds ^ link_info->advertising;
5567 if ((link_info->support_auto_speeds | diff) !=
5568 link_info->support_auto_speeds) {
5569 /* An advertised speed is no longer supported, so we need to
0eaa24b9
MC		 5570 * update the advertisement settings. Caller holds RTNL
5571 * so we can modify link settings.
286ef9d6 5572 */
286ef9d6 5573 link_info->advertising = link_info->support_auto_speeds;
0eaa24b9 5574 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
286ef9d6 5575 bnxt_hwrm_set_link_setting(bp, true, false);
286ef9d6 5576 }
c0c050c5
MC		 5577 return 0;
5578}
5579
10289bec
MC		 5580static void bnxt_get_port_module_status(struct bnxt *bp)
5581{
5582 struct bnxt_link_info *link_info = &bp->link_info;
5583 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5584 u8 module_status;
5585
5586 if (bnxt_update_link(bp, true))
5587 return;
5588
5589 module_status = link_info->module_status;
5590 switch (module_status) {
5591 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5592 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5593 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5594 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5595 bp->pf.port_id);
5596 if (bp->hwrm_spec_code >= 0x10201) {
5597 netdev_warn(bp->dev, "Module part number %s\n",
5598 resp->phy_vendor_partnumber);
5599 }
5600 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5601 netdev_warn(bp->dev, "TX is disabled\n");
5602 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5603 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5604 }
5605}
5606
c0c050c5
MC		 5607static void
5608bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5609{
5610 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
c9ee9516
MC		 5611 if (bp->hwrm_spec_code >= 0x10201)
5612 req->auto_pause =
5613 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
c0c050c5
MC		 5614 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5615 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5616 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
49b5c7a1 5617 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
c0c050c5
MC		 5618 req->enables |=
5619 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5620 } else {
5621 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5622 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5623 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5624 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5625 req->enables |=
5626 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
c9ee9516
MC		 5627 if (bp->hwrm_spec_code >= 0x10201) {
5628 req->auto_pause = req->force_pause;
5629 req->enables |= cpu_to_le32(
5630 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5631 }
c0c050c5
MC		 5632 }
5633}
5634
5635static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5636 struct hwrm_port_phy_cfg_input *req)
5637{
5638 u8 autoneg = bp->link_info.autoneg;
5639 u16 fw_link_speed = bp->link_info.req_link_speed;
68515a18 5640 u16 advertising = bp->link_info.advertising;
c0c050c5
MC		 5641
5642 if (autoneg & BNXT_AUTONEG_SPEED) {
5643 req->auto_mode |=
11f15ed3 5644 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
c0c050c5
MC		 5645
5646 req->enables |= cpu_to_le32(
5647 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5648 req->auto_link_speed_mask = cpu_to_le16(advertising);
5649
5650 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5651 req->flags |=
5652 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5653 } else {
5654 req->force_link_speed = cpu_to_le16(fw_link_speed);
5655 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5656 }
5657
c0c050c5
MC		 5658 /* tell chimp that the setting takes effect immediately */
5659 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5660}
5661
5662int bnxt_hwrm_set_pause(struct bnxt *bp)
5663{
5664 struct hwrm_port_phy_cfg_input req = {0};
5665 int rc;
5666
5667 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5668 bnxt_hwrm_set_pause_common(bp, &req);
5669
5670 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5671 bp->link_info.force_link_chng)
5672 bnxt_hwrm_set_link_common(bp, &req);
5673
5674 mutex_lock(&bp->hwrm_cmd_lock);
5675 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5676 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5677 /* since changing of pause setting doesn't trigger any link
5678 * change event, the driver needs to update the current pause
5679 * result upon successfully return of the phy_cfg command
5680 */
5681 bp->link_info.pause =
5682 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5683 bp->link_info.auto_pause_setting = 0;
5684 if (!bp->link_info.force_link_chng)
5685 bnxt_report_link(bp);
5686 }
5687 bp->link_info.force_link_chng = false;
5688 mutex_unlock(&bp->hwrm_cmd_lock);
5689 return rc;
5690}
5691
939f7f0c
MC		 5692static void bnxt_hwrm_set_eee(struct bnxt *bp,
5693 struct hwrm_port_phy_cfg_input *req)
5694{
5695 struct ethtool_eee *eee = &bp->eee;
5696
5697 if (eee->eee_enabled) {
5698 u16 eee_speeds;
5699 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5700
5701 if (eee->tx_lpi_enabled)
5702 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5703 else
5704 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5705
5706 req->flags |= cpu_to_le32(flags);
5707 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5708 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5709 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5710 } else {
5711 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5712 }
5713}
5714
5715int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
c0c050c5
MC		 5716{
5717 struct hwrm_port_phy_cfg_input req = {0};
5718
5719 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5720 if (set_pause)
5721 bnxt_hwrm_set_pause_common(bp, &req);
5722
5723 bnxt_hwrm_set_link_common(bp, &req);
939f7f0c
MC		 5724
5725 if (set_eee)
5726 bnxt_hwrm_set_eee(bp, &req);
c0c050c5
MC		 5727 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5728}
5729
33f7d55f
MC		 5730static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5731{
5732 struct hwrm_port_phy_cfg_input req = {0};
5733
567b2abe 5734 if (!BNXT_SINGLE_PF(bp))
33f7d55f
MC		 5735 return 0;
5736
5737 if (pci_num_vf(bp->pdev))
5738 return 0;
5739
5740 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
16d663a6 5741 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
33f7d55f
MC		 5742 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5743}
5744
5ad2cbee
MC		 5745static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
5746{
5747 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5748 struct hwrm_port_led_qcaps_input req = {0};
5749 struct bnxt_pf_info *pf = &bp->pf;
5750 int rc;
5751
5752 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
5753 return 0;
5754
5755 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
5756 req.port_id = cpu_to_le16(pf->port_id);
5757 mutex_lock(&bp->hwrm_cmd_lock);
5758 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5759 if (rc) {
5760 mutex_unlock(&bp->hwrm_cmd_lock);
5761 return rc;
5762 }
5763 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
5764 int i;
5765
5766 bp->num_leds = resp->num_leds;
5767 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
5768 bp->num_leds);
5769 for (i = 0; i < bp->num_leds; i++) {
5770 struct bnxt_led_info *led = &bp->leds[i];
5771 __le16 caps = led->led_state_caps;
5772
5773 if (!led->led_group_id ||
5774 !BNXT_LED_ALT_BLINK_CAP(caps)) {
5775 bp->num_leds = 0;
5776 break;
5777 }
5778 }
5779 }
5780 mutex_unlock(&bp->hwrm_cmd_lock);
5781 return 0;
5782}
5783
939f7f0c
MC		 5784static bool bnxt_eee_config_ok(struct bnxt *bp)
5785{
5786 struct ethtool_eee *eee = &bp->eee;
5787 struct bnxt_link_info *link_info = &bp->link_info;
5788
5789 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5790 return true;
5791
5792 if (eee->eee_enabled) {
5793 u32 advertising =
5794 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5795
5796 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5797 eee->eee_enabled = 0;
5798 return false;
5799 }
5800 if (eee->advertised & ~advertising) {
5801 eee->advertised = advertising & eee->supported;
5802 return false;
5803 }
5804 }
5805 return true;
5806}
5807
c0c050c5
MC		 5808static int bnxt_update_phy_setting(struct bnxt *bp)
5809{
5810 int rc;
5811 bool update_link = false;
5812 bool update_pause = false;
939f7f0c 5813 bool update_eee = false;
c0c050c5
MC		 5814 struct bnxt_link_info *link_info = &bp->link_info;
5815
5816 rc = bnxt_update_link(bp, true);
5817 if (rc) {
5818 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5819 rc);
5820 return rc;
5821 }
5822 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
c9ee9516
MC		 5823 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5824 link_info->req_flow_ctrl)
c0c050c5
MC		 5825 update_pause = true;
5826 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5827 link_info->force_pause_setting != link_info->req_flow_ctrl)
5828 update_pause = true;
c0c050c5
MC		 5829 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5830 if (BNXT_AUTO_MODE(link_info->auto_mode))
5831 update_link = true;
5832 if (link_info->req_link_speed != link_info->force_link_speed)
5833 update_link = true;
de73018f
MC		 5834 if (link_info->req_duplex != link_info->duplex_setting)
5835 update_link = true;
c0c050c5
MC		 5836 } else {
5837 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5838 update_link = true;
5839 if (link_info->advertising != link_info->auto_link_speeds)
5840 update_link = true;
c0c050c5
MC		 5841 }
5842
16d663a6
MC		 5843 /* The last close may have shutdown the link, so need to call
5844 * PHY_CFG to bring it back up.
5845 */
5846 if (!netif_carrier_ok(bp->dev))
5847 update_link = true;
5848
939f7f0c
MC		 5849 if (!bnxt_eee_config_ok(bp))
5850 update_eee = true;
5851
c0c050c5 5852 if (update_link)
939f7f0c 5853 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
c0c050c5
MC		 5854 else if (update_pause)
5855 rc = bnxt_hwrm_set_pause(bp);
5856 if (rc) {
5857 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5858 rc);
5859 return rc;
5860 }
5861
5862 return rc;
5863}
5864
11809490
JH		 5865/* Common routine to pre-map certain register block to different GRC window.
5866 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5867 * in PF and 3 windows in VF that can be customized to map in different
5868 * register blocks.
5869 */
5870static void bnxt_preset_reg_win(struct bnxt *bp)
5871{
5872 if (BNXT_PF(bp)) {
5873 /* CAG registers map to GRC window #4 */
5874 writel(BNXT_CAG_REG_BASE,
5875 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5876 }
5877}
5878
c0c050c5
MC		 5879static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5880{
5881 int rc = 0;
5882
11809490 5883 bnxt_preset_reg_win(bp);
c0c050c5
MC		 5884 netif_carrier_off(bp->dev);
5885 if (irq_re_init) {
5886 rc = bnxt_setup_int_mode(bp);
5887 if (rc) {
5888 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5889 rc);
5890 return rc;
5891 }
5892 }
5893 if ((bp->flags & BNXT_FLAG_RFS) &&
5894 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5895 /* disable RFS if falling back to INTA */
5896 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5897 bp->flags &= ~BNXT_FLAG_RFS;
5898 }
5899
5900 rc = bnxt_alloc_mem(bp, irq_re_init);
5901 if (rc) {
5902 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5903 goto open_err_free_mem;
5904 }
5905
5906 if (irq_re_init) {
5907 bnxt_init_napi(bp);
5908 rc = bnxt_request_irq(bp);
5909 if (rc) {
5910 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5911 goto open_err;
5912 }
5913 }
5914
5915 bnxt_enable_napi(bp);
5916
5917 rc = bnxt_init_nic(bp, irq_re_init);
5918 if (rc) {
5919 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5920 goto open_err;
5921 }
5922
5923 if (link_re_init) {
5924 rc = bnxt_update_phy_setting(bp);
5925 if (rc)
ba41d46f 5926 netdev_warn(bp->dev, "failed to update phy settings\n");
c0c050c5
MC		 5927 }
5928
7cdd5fc3 5929 if (irq_re_init)
ad51b8e9 5930 udp_tunnel_get_rx_info(bp->dev);
c0c050c5 5931
caefe526 5932 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 5933 bnxt_enable_int(bp);
5934 /* Enable TX queues */
5935 bnxt_tx_enable(bp);
5936 mod_timer(&bp->timer, jiffies + bp->current_interval);
10289bec
MC		 5937 /* Poll link status and check for SFP+ module status */
5938 bnxt_get_port_module_status(bp);
c0c050c5
MC		 5939
5940 return 0;
5941
5942open_err:
5943 bnxt_disable_napi(bp);
5944 bnxt_del_napi(bp);
5945
5946open_err_free_mem:
5947 bnxt_free_skbs(bp);
5948 bnxt_free_irq(bp);
5949 bnxt_free_mem(bp, true);
5950 return rc;
5951}
5952
5953/* rtnl_lock held */
5954int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5955{
5956 int rc = 0;
5957
5958 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5959 if (rc) {
5960 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5961 dev_close(bp->dev);
5962 }
5963 return rc;
5964}
5965
5966static int bnxt_open(struct net_device *dev)
5967{
5968 struct bnxt *bp = netdev_priv(dev);
c0c050c5 5969
c0c050c5
MC		 5970 return __bnxt_open_nic(bp, true, true);
5971}
5972
c0c050c5
MC		 5973int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5974{
5975 int rc = 0;
5976
5977#ifdef CONFIG_BNXT_SRIOV
5978 if (bp->sriov_cfg) {
5979 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5980 !bp->sriov_cfg,
5981 BNXT_SRIOV_CFG_WAIT_TMO);
5982 if (rc)
5983 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5984 }
5985#endif
5986 /* Change device state to avoid TX queue wake up's */
5987 bnxt_tx_disable(bp);
5988
caefe526 5989 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec
MC		 5990 smp_mb__after_atomic();
5991 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5992 msleep(20);
c0c050c5 5993
9d8bc097 5994 /* Flush rings and and disable interrupts */
c0c050c5
MC		 5995 bnxt_shutdown_nic(bp, irq_re_init);
5996
5997 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5998
5999 bnxt_disable_napi(bp);
c0c050c5
MC		 6000 del_timer_sync(&bp->timer);
6001 bnxt_free_skbs(bp);
6002
6003 if (irq_re_init) {
6004 bnxt_free_irq(bp);
6005 bnxt_del_napi(bp);
6006 }
6007 bnxt_free_mem(bp, irq_re_init);
6008 return rc;
6009}
6010
6011static int bnxt_close(struct net_device *dev)
6012{
6013 struct bnxt *bp = netdev_priv(dev);
6014
6015 bnxt_close_nic(bp, true, true);
33f7d55f 6016 bnxt_hwrm_shutdown_link(bp);
c0c050c5
MC		 6017 return 0;
6018}
6019
6020/* rtnl_lock held */
6021static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6022{
6023 switch (cmd) {
6024 case SIOCGMIIPHY:
6025 /* fallthru */
6026 case SIOCGMIIREG: {
6027 if (!netif_running(dev))
6028 return -EAGAIN;
6029
6030 return 0;
6031 }
6032
6033 case SIOCSMIIREG:
6034 if (!netif_running(dev))
6035 return -EAGAIN;
6036
6037 return 0;
6038
6039 default:
6040 /* do nothing */
6041 break;
6042 }
6043 return -EOPNOTSUPP;
6044}
6045
bc1f4470 6046static void
c0c050c5
MC		 6047bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6048{
6049 u32 i;
6050 struct bnxt *bp = netdev_priv(dev);
6051
c0c050c5 6052 if (!bp->bnapi)
bc1f4470 6053 return;
c0c050c5
MC		 6054
6055 /* TODO check if we need to synchronize with bnxt_close path */
6056 for (i = 0; i < bp->cp_nr_rings; i++) {
6057 struct bnxt_napi *bnapi = bp->bnapi[i];
6058 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6059 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6060
6061 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6062 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6063 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6064
6065 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6066 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6067 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6068
6069 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6070 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6071 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6072
6073 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6074 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6075 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6076
6077 stats->rx_missed_errors +=
6078 le64_to_cpu(hw_stats->rx_discard_pkts);
6079
6080 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6081
c0c050c5
MC		 6082 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6083 }
6084
9947f83f
MC		 6085 if (bp->flags & BNXT_FLAG_PORT_STATS) {
6086 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6087 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6088
6089 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6090 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6091 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6092 le64_to_cpu(rx->rx_ovrsz_frames) +
6093 le64_to_cpu(rx->rx_runt_frames);
6094 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6095 le64_to_cpu(rx->rx_jbr_frames);
6096 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6097 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6098 stats->tx_errors = le64_to_cpu(tx->tx_err);
6099 }
c0c050c5
MC		 6100}
6101
6102static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6103{
6104 struct net_device *dev = bp->dev;
6105 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6106 struct netdev_hw_addr *ha;
6107 u8 *haddr;
6108 int mc_count = 0;
6109 bool update = false;
6110 int off = 0;
6111
6112 netdev_for_each_mc_addr(ha, dev) {
6113 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6114 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6115 vnic->mc_list_count = 0;
6116 return false;
6117 }
6118 haddr = ha->addr;
6119 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6120 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6121 update = true;
6122 }
6123 off += ETH_ALEN;
6124 mc_count++;
6125 }
6126 if (mc_count)
6127 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6128
6129 if (mc_count != vnic->mc_list_count) {
6130 vnic->mc_list_count = mc_count;
6131 update = true;
6132 }
6133 return update;
6134}
6135
6136static bool bnxt_uc_list_updated(struct bnxt *bp)
6137{
6138 struct net_device *dev = bp->dev;
6139 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6140 struct netdev_hw_addr *ha;
6141 int off = 0;
6142
6143 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6144 return true;
6145
6146 netdev_for_each_uc_addr(ha, dev) {
6147 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6148 return true;
6149
6150 off += ETH_ALEN;
6151 }
6152 return false;
6153}
6154
6155static void bnxt_set_rx_mode(struct net_device *dev)
6156{
6157 struct bnxt *bp = netdev_priv(dev);
6158 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6159 u32 mask = vnic->rx_mask;
6160 bool mc_update = false;
6161 bool uc_update;
6162
6163 if (!netif_running(dev))
6164 return;
6165
6166 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6167 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6168 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6169
17c71ac3 6170 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
c0c050c5
MC		 6171 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6172
6173 uc_update = bnxt_uc_list_updated(bp);
6174
6175 if (dev->flags & IFF_ALLMULTI) {
6176 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6177 vnic->mc_list_count = 0;
6178 } else {
6179 mc_update = bnxt_mc_list_updated(bp, &mask);
6180 }
6181
6182 if (mask != vnic->rx_mask || uc_update || mc_update) {
6183 vnic->rx_mask = mask;
6184
6185 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6186 schedule_work(&bp->sp_task);
6187 }
6188}
6189
b664f008 6190static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 6191{
6192 struct net_device *dev = bp->dev;
6193 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6194 struct netdev_hw_addr *ha;
6195 int i, off = 0, rc;
6196 bool uc_update;
6197
6198 netif_addr_lock_bh(dev);
6199 uc_update = bnxt_uc_list_updated(bp);
6200 netif_addr_unlock_bh(dev);
6201
6202 if (!uc_update)
6203 goto skip_uc;
6204
6205 mutex_lock(&bp->hwrm_cmd_lock);
6206 for (i = 1; i < vnic->uc_filter_count; i++) {
6207 struct hwrm_cfa_l2_filter_free_input req = {0};
6208
6209 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6210 -1);
6211
6212 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6213
6214 rc = _hwrm_send_message(bp, &req, sizeof(req),
6215 HWRM_CMD_TIMEOUT);
6216 }
6217 mutex_unlock(&bp->hwrm_cmd_lock);
6218
6219 vnic->uc_filter_count = 1;
6220
6221 netif_addr_lock_bh(dev);
6222 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6223 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6224 } else {
6225 netdev_for_each_uc_addr(ha, dev) {
6226 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6227 off += ETH_ALEN;
6228 vnic->uc_filter_count++;
6229 }
6230 }
6231 netif_addr_unlock_bh(dev);
6232
6233 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6234 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6235 if (rc) {
6236 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6237 rc);
6238 vnic->uc_filter_count = i;
b664f008 6239 return rc;
c0c050c5
MC		 6240 }
6241 }
6242
6243skip_uc:
6244 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6245 if (rc)
6246 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6247 rc);
b664f008
MC		 6248
6249 return rc;
c0c050c5
MC		 6250}
6251
8079e8f1
MC		 6252/* If the chip and firmware supports RFS */
6253static bool bnxt_rfs_supported(struct bnxt *bp)
6254{
6255 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6256 return true;
ae10ae74
MC		 6257 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6258 return true;
8079e8f1
MC		 6259 return false;
6260}
6261
6262/* If runtime conditions support RFS */
2bcfa6f6
MC		 6263static bool bnxt_rfs_capable(struct bnxt *bp)
6264{
6265#ifdef CONFIG_RFS_ACCEL
8079e8f1 6266 int vnics, max_vnics, max_rss_ctxs;
2bcfa6f6
MC		 6267
6268 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
6269 return false;
6270
6271 vnics = 1 + bp->rx_nr_rings;
8079e8f1
MC		 6272 max_vnics = bnxt_get_max_func_vnics(bp);
6273 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
ae10ae74
MC		 6274
6275 /* RSS contexts not a limiting factor */
6276 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6277 max_rss_ctxs = max_vnics;
8079e8f1 6278 if (vnics > max_vnics || vnics > max_rss_ctxs) {
a2304909
VV		 6279 netdev_warn(bp->dev,
6280 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
8079e8f1 6281 min(max_rss_ctxs - 1, max_vnics - 1));
2bcfa6f6 6282 return false;
a2304909 6283 }
2bcfa6f6
MC		 6284
6285 return true;
6286#else
6287 return false;
6288#endif
6289}
6290
c0c050c5
MC		 6291static netdev_features_t bnxt_fix_features(struct net_device *dev,
6292 netdev_features_t features)
6293{
2bcfa6f6
MC		 6294 struct bnxt *bp = netdev_priv(dev);
6295
a2304909 6296 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
2bcfa6f6 6297 features &= ~NETIF_F_NTUPLE;
5a9f6b23
MC		 6298
6299 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6300 * turned on or off together.
6301 */
6302 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6303 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6304 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6305 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6306 NETIF_F_HW_VLAN_STAG_RX);
6307 else
6308 features |= NETIF_F_HW_VLAN_CTAG_RX |
6309 NETIF_F_HW_VLAN_STAG_RX;
6310 }
cf6645f8
MC		 6311#ifdef CONFIG_BNXT_SRIOV
6312 if (BNXT_VF(bp)) {
6313 if (bp->vf.vlan) {
6314 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6315 NETIF_F_HW_VLAN_STAG_RX);
6316 }
6317 }
6318#endif
c0c050c5
MC		 6319 return features;
6320}
6321
6322static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6323{
6324 struct bnxt *bp = netdev_priv(dev);
6325 u32 flags = bp->flags;
6326 u32 changes;
6327 int rc = 0;
6328 bool re_init = false;
6329 bool update_tpa = false;
6330
6331 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
3e8060fa 6332 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
c0c050c5
MC		 6333 flags |= BNXT_FLAG_GRO;
6334 if (features & NETIF_F_LRO)
6335 flags |= BNXT_FLAG_LRO;
6336
bdbd1eb5
MC		 6337 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6338 flags &= ~BNXT_FLAG_TPA;
6339
c0c050c5
MC		 6340 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6341 flags |= BNXT_FLAG_STRIP_VLAN;
6342
6343 if (features & NETIF_F_NTUPLE)
6344 flags |= BNXT_FLAG_RFS;
6345
6346 changes = flags ^ bp->flags;
6347 if (changes & BNXT_FLAG_TPA) {
6348 update_tpa = true;
6349 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6350 (flags & BNXT_FLAG_TPA) == 0)
6351 re_init = true;
6352 }
6353
6354 if (changes & ~BNXT_FLAG_TPA)
6355 re_init = true;
6356
6357 if (flags != bp->flags) {
6358 u32 old_flags = bp->flags;
6359
6360 bp->flags = flags;
6361
2bcfa6f6 6362 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 6363 if (update_tpa)
6364 bnxt_set_ring_params(bp);
6365 return rc;
6366 }
6367
6368 if (re_init) {
6369 bnxt_close_nic(bp, false, false);
6370 if (update_tpa)
6371 bnxt_set_ring_params(bp);
6372
6373 return bnxt_open_nic(bp, false, false);
6374 }
6375 if (update_tpa) {
6376 rc = bnxt_set_tpa(bp,
6377 (flags & BNXT_FLAG_TPA) ?
6378 true : false);
6379 if (rc)
6380 bp->flags = old_flags;
6381 }
6382 }
6383 return rc;
6384}
6385
9f554590
MC		 6386static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6387{
b6ab4b01 6388 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 6389 int i = bnapi->index;
6390
3b2b7d9d
MC		 6391 if (!txr)
6392 return;
6393
9f554590
MC		 6394 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6395 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6396 txr->tx_cons);
6397}
6398
6399static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6400{
b6ab4b01 6401 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 6402 int i = bnapi->index;
6403
3b2b7d9d
MC		 6404 if (!rxr)
6405 return;
6406
9f554590
MC		 6407 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6408 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6409 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6410 rxr->rx_sw_agg_prod);
6411}
6412
6413static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6414{
6415 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6416 int i = bnapi->index;
6417
6418 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6419 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6420}
6421
c0c050c5
MC		 6422static void bnxt_dbg_dump_states(struct bnxt *bp)
6423{
6424 int i;
6425 struct bnxt_napi *bnapi;
c0c050c5
MC		 6426
6427 for (i = 0; i < bp->cp_nr_rings; i++) {
6428 bnapi = bp->bnapi[i];
c0c050c5 6429 if (netif_msg_drv(bp)) {
9f554590
MC		 6430 bnxt_dump_tx_sw_state(bnapi);
6431 bnxt_dump_rx_sw_state(bnapi);
6432 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 6433 }
6434 }
6435}
6436
6988bd92 6437static void bnxt_reset_task(struct bnxt *bp, bool silent)
c0c050c5 6438{
6988bd92
MC		 6439 if (!silent)
6440 bnxt_dbg_dump_states(bp);
028de140
MC		 6441 if (netif_running(bp->dev)) {
6442 bnxt_close_nic(bp, false, false);
6443 bnxt_open_nic(bp, false, false);
6444 }
c0c050c5
MC		 6445}
6446
6447static void bnxt_tx_timeout(struct net_device *dev)
6448{
6449 struct bnxt *bp = netdev_priv(dev);
6450
6451 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
6452 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6453 schedule_work(&bp->sp_task);
6454}
6455
6456#ifdef CONFIG_NET_POLL_CONTROLLER
6457static void bnxt_poll_controller(struct net_device *dev)
6458{
6459 struct bnxt *bp = netdev_priv(dev);
6460 int i;
6461
6462 for (i = 0; i < bp->cp_nr_rings; i++) {
6463 struct bnxt_irq *irq = &bp->irq_tbl[i];
6464
6465 disable_irq(irq->vector);
6466 irq->handler(irq->vector, bp->bnapi[i]);
6467 enable_irq(irq->vector);
6468 }
6469}
6470#endif
6471
6472static void bnxt_timer(unsigned long data)
6473{
6474 struct bnxt *bp = (struct bnxt *)data;
6475 struct net_device *dev = bp->dev;
6476
6477 if (!netif_running(dev))
6478 return;
6479
6480 if (atomic_read(&bp->intr_sem) != 0)
6481 goto bnxt_restart_timer;
6482
3bdf56c4
MC		 6483 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6484 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6485 schedule_work(&bp->sp_task);
6486 }
c0c050c5
MC		 6487bnxt_restart_timer:
6488 mod_timer(&bp->timer, jiffies + bp->current_interval);
6489}
6490
a551ee94 6491static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6988bd92 6492{
a551ee94
MC		 6493 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6494 * set. If the device is being closed, bnxt_close() may be holding
6988bd92
MC		 6495 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
6496 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6497 */
6498 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6499 rtnl_lock();
a551ee94
MC		 6500}
6501
6502static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
6503{
6988bd92
MC		 6504 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6505 rtnl_unlock();
6506}
6507
a551ee94
MC		 6508/* Only called from bnxt_sp_task() */
6509static void bnxt_reset(struct bnxt *bp, bool silent)
6510{
6511 bnxt_rtnl_lock_sp(bp);
6512 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6513 bnxt_reset_task(bp, silent);
6514 bnxt_rtnl_unlock_sp(bp);
6515}
6516
c0c050c5
MC		 6517static void bnxt_cfg_ntp_filters(struct bnxt *);
6518
6519static void bnxt_sp_task(struct work_struct *work)
6520{
6521 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
c0c050c5 6522
4cebdcec
MC		 6523 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6524 smp_mb__after_atomic();
6525 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6526 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 6527 return;
4cebdcec 6528 }
c0c050c5
MC		 6529
6530 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6531 bnxt_cfg_rx_mode(bp);
6532
6533 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6534 bnxt_cfg_ntp_filters(bp);
c0c050c5
MC		 6535 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6536 bnxt_hwrm_exec_fwd_req(bp);
6537 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6538 bnxt_hwrm_tunnel_dst_port_alloc(
6539 bp, bp->vxlan_port,
6540 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6541 }
6542 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6543 bnxt_hwrm_tunnel_dst_port_free(
6544 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6545 }
7cdd5fc3
AD		 6546 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6547 bnxt_hwrm_tunnel_dst_port_alloc(
6548 bp, bp->nge_port,
6549 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6550 }
6551 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6552 bnxt_hwrm_tunnel_dst_port_free(
6553 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6554 }
3bdf56c4
MC		 6555 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6556 bnxt_hwrm_port_qstats(bp);
6557
a551ee94
MC		 6558 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
6559 * must be the last functions to be called before exiting.
6560 */
0eaa24b9
MC		 6561 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
6562 int rc = 0;
6563
6564 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
6565 &bp->sp_event))
6566 bnxt_hwrm_phy_qcaps(bp);
6567
6568 bnxt_rtnl_lock_sp(bp);
6569 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6570 rc = bnxt_update_link(bp, true);
6571 bnxt_rtnl_unlock_sp(bp);
6572 if (rc)
6573 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6574 rc);
6575 }
90c694bb
MC		 6576 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
6577 bnxt_rtnl_lock_sp(bp);
6578 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6579 bnxt_get_port_module_status(bp);
6580 bnxt_rtnl_unlock_sp(bp);
6581 }
6988bd92
MC		 6582 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6583 bnxt_reset(bp, false);
4cebdcec 6584
fc0f1929
MC		 6585 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6586 bnxt_reset(bp, true);
6587
4cebdcec
MC		 6588 smp_mb__before_atomic();
6589 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 6590}
6591
d1e7925e 6592/* Under rtnl_lock */
5f449249 6593int bnxt_reserve_rings(struct bnxt *bp, int tx, int rx, int tcs, int tx_xdp)
d1e7925e
MC		 6594{
6595 int max_rx, max_tx, tx_sets = 1;
6596 int tx_rings_needed;
6597 bool sh = true;
6598 int rc;
6599
6600 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
6601 sh = false;
6602
6603 if (tcs)
6604 tx_sets = tcs;
6605
6606 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
6607 if (rc)
6608 return rc;
6609
6610 if (max_rx < rx)
6611 return -ENOMEM;
6612
5f449249 6613 tx_rings_needed = tx * tx_sets + tx_xdp;
d1e7925e
MC		 6614 if (max_tx < tx_rings_needed)
6615 return -ENOMEM;
6616
6617 if (bnxt_hwrm_reserve_tx_rings(bp, &tx_rings_needed) ||
5f449249 6618 tx_rings_needed < (tx * tx_sets + tx_xdp))
d1e7925e
MC		 6619 return -ENOMEM;
6620 return 0;
6621}
6622
c0c050c5
MC		 6623static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6624{
6625 int rc;
6626 struct bnxt *bp = netdev_priv(dev);
6627
6628 SET_NETDEV_DEV(dev, &pdev->dev);
6629
6630 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6631 rc = pci_enable_device(pdev);
6632 if (rc) {
6633 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6634 goto init_err;
6635 }
6636
6637 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6638 dev_err(&pdev->dev,
6639 "Cannot find PCI device base address, aborting\n");
6640 rc = -ENODEV;
6641 goto init_err_disable;
6642 }
6643
6644 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6645 if (rc) {
6646 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6647 goto init_err_disable;
6648 }
6649
6650 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6651 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6652 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6653 goto init_err_disable;
6654 }
6655
6656 pci_set_master(pdev);
6657
6658 bp->dev = dev;
6659 bp->pdev = pdev;
6660
6661 bp->bar0 = pci_ioremap_bar(pdev, 0);
6662 if (!bp->bar0) {
6663 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6664 rc = -ENOMEM;
6665 goto init_err_release;
6666 }
6667
6668 bp->bar1 = pci_ioremap_bar(pdev, 2);
6669 if (!bp->bar1) {
6670 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6671 rc = -ENOMEM;
6672 goto init_err_release;
6673 }
6674
6675 bp->bar2 = pci_ioremap_bar(pdev, 4);
6676 if (!bp->bar2) {
6677 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6678 rc = -ENOMEM;
6679 goto init_err_release;
6680 }
6681
6316ea6d
SB		 6682 pci_enable_pcie_error_reporting(pdev);
6683
c0c050c5
MC		 6684 INIT_WORK(&bp->sp_task, bnxt_sp_task);
6685
6686 spin_lock_init(&bp->ntp_fltr_lock);
6687
6688 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6689 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6690
dfb5b894 6691 /* tick values in micro seconds */
dfc9c94a
MC		 6692 bp->rx_coal_ticks = 12;
6693 bp->rx_coal_bufs = 30;
dfb5b894
MC		 6694 bp->rx_coal_ticks_irq = 1;
6695 bp->rx_coal_bufs_irq = 2;
c0c050c5 6696
dfc9c94a
MC		 6697 bp->tx_coal_ticks = 25;
6698 bp->tx_coal_bufs = 30;
6699 bp->tx_coal_ticks_irq = 2;
6700 bp->tx_coal_bufs_irq = 2;
6701
51f30785
MC		 6702 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6703
c0c050c5
MC		 6704 init_timer(&bp->timer);
6705 bp->timer.data = (unsigned long)bp;
6706 bp->timer.function = bnxt_timer;
6707 bp->current_interval = BNXT_TIMER_INTERVAL;
6708
caefe526 6709 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 6710
6711 return 0;
6712
6713init_err_release:
6714 if (bp->bar2) {
6715 pci_iounmap(pdev, bp->bar2);
6716 bp->bar2 = NULL;
6717 }
6718
6719 if (bp->bar1) {
6720 pci_iounmap(pdev, bp->bar1);
6721 bp->bar1 = NULL;
6722 }
6723
6724 if (bp->bar0) {
6725 pci_iounmap(pdev, bp->bar0);
6726 bp->bar0 = NULL;
6727 }
6728
6729 pci_release_regions(pdev);
6730
6731init_err_disable:
6732 pci_disable_device(pdev);
6733
6734init_err:
6735 return rc;
6736}
6737
6738/* rtnl_lock held */
6739static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6740{
6741 struct sockaddr *addr = p;
1fc2cfd0
JH		 6742 struct bnxt *bp = netdev_priv(dev);
6743 int rc = 0;
c0c050c5
MC		 6744
6745 if (!is_valid_ether_addr(addr->sa_data))
6746 return -EADDRNOTAVAIL;
6747
84c33dd3
MC		 6748 rc = bnxt_approve_mac(bp, addr->sa_data);
6749 if (rc)
6750 return rc;
bdd4347b 6751
1fc2cfd0
JH		 6752 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6753 return 0;
6754
c0c050c5 6755 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 6756 if (netif_running(dev)) {
6757 bnxt_close_nic(bp, false, false);
6758 rc = bnxt_open_nic(bp, false, false);
6759 }
c0c050c5 6760
1fc2cfd0 6761 return rc;
c0c050c5
MC		 6762}
6763
6764/* rtnl_lock held */
6765static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6766{
6767 struct bnxt *bp = netdev_priv(dev);
6768
c0c050c5
MC		 6769 if (netif_running(dev))
6770 bnxt_close_nic(bp, false, false);
6771
6772 dev->mtu = new_mtu;
6773 bnxt_set_ring_params(bp);
6774
6775 if (netif_running(dev))
6776 return bnxt_open_nic(bp, false, false);
6777
6778 return 0;
6779}
6780
c5e3deb8 6781int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
c0c050c5
MC		 6782{
6783 struct bnxt *bp = netdev_priv(dev);
3ffb6a39 6784 bool sh = false;
d1e7925e 6785 int rc;
16e5cc64 6786
c0c050c5
MC		 6787 if (tc > bp->max_tc) {
6788 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
6789 tc, bp->max_tc);
6790 return -EINVAL;
6791 }
6792
6793 if (netdev_get_num_tc(dev) == tc)
6794 return 0;
6795
3ffb6a39
MC		 6796 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6797 sh = true;
6798
5f449249
MC		 6799 rc = bnxt_reserve_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
6800 tc, bp->tx_nr_rings_xdp);
d1e7925e
MC		 6801 if (rc)
6802 return rc;
c0c050c5
MC		 6803
6804 /* Needs to close the device and do hw resource re-allocations */
6805 if (netif_running(bp->dev))
6806 bnxt_close_nic(bp, true, false);
6807
6808 if (tc) {
6809 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6810 netdev_set_num_tc(dev, tc);
6811 } else {
6812 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6813 netdev_reset_tc(dev);
6814 }
3ffb6a39
MC		 6815 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6816 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5
MC		 6817 bp->num_stat_ctxs = bp->cp_nr_rings;
6818
6819 if (netif_running(bp->dev))
6820 return bnxt_open_nic(bp, true, false);
6821
6822 return 0;
6823}
6824
c5e3deb8
MC		 6825static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6826 struct tc_to_netdev *ntc)
6827{
6828 if (ntc->type != TC_SETUP_MQPRIO)
6829 return -EINVAL;
6830
6831 return bnxt_setup_mq_tc(dev, ntc->tc);
6832}
6833
c0c050c5
MC		 6834#ifdef CONFIG_RFS_ACCEL
6835static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6836 struct bnxt_ntuple_filter *f2)
6837{
6838 struct flow_keys *keys1 = &f1->fkeys;
6839 struct flow_keys *keys2 = &f2->fkeys;
6840
6841 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6842 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6843 keys1->ports.ports == keys2->ports.ports &&
6844 keys1->basic.ip_proto == keys2->basic.ip_proto &&
6845 keys1->basic.n_proto == keys2->basic.n_proto &&
a54c4d74
MC		 6846 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
6847 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
c0c050c5
MC		 6848 return true;
6849
6850 return false;
6851}
6852
6853static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6854 u16 rxq_index, u32 flow_id)
6855{
6856 struct bnxt *bp = netdev_priv(dev);
6857 struct bnxt_ntuple_filter *fltr, *new_fltr;
6858 struct flow_keys *fkeys;
6859 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
a54c4d74 6860 int rc = 0, idx, bit_id, l2_idx = 0;
c0c050c5
MC		 6861 struct hlist_head *head;
6862
6863 if (skb->encapsulation)
6864 return -EPROTONOSUPPORT;
6865
a54c4d74
MC		 6866 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
6867 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6868 int off = 0, j;
6869
6870 netif_addr_lock_bh(dev);
6871 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
6872 if (ether_addr_equal(eth->h_dest,
6873 vnic->uc_list + off)) {
6874 l2_idx = j + 1;
6875 break;
6876 }
6877 }
6878 netif_addr_unlock_bh(dev);
6879 if (!l2_idx)
6880 return -EINVAL;
6881 }
c0c050c5
MC		 6882 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6883 if (!new_fltr)
6884 return -ENOMEM;
6885
6886 fkeys = &new_fltr->fkeys;
6887 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6888 rc = -EPROTONOSUPPORT;
6889 goto err_free;
6890 }
6891
dda0e746
MC		 6892 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
6893 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
c0c050c5
MC		 6894 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6895 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6896 rc = -EPROTONOSUPPORT;
6897 goto err_free;
6898 }
dda0e746
MC		 6899 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
6900 bp->hwrm_spec_code < 0x10601) {
6901 rc = -EPROTONOSUPPORT;
6902 goto err_free;
6903 }
c0c050c5 6904
a54c4d74 6905 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
c0c050c5
MC		 6906 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6907
6908 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6909 head = &bp->ntp_fltr_hash_tbl[idx];
6910 rcu_read_lock();
6911 hlist_for_each_entry_rcu(fltr, head, hash) {
6912 if (bnxt_fltr_match(fltr, new_fltr)) {
6913 rcu_read_unlock();
6914 rc = 0;
6915 goto err_free;
6916 }
6917 }
6918 rcu_read_unlock();
6919
6920 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 6921 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6922 BNXT_NTP_FLTR_MAX_FLTR, 0);
6923 if (bit_id < 0) {
c0c050c5
MC		 6924 spin_unlock_bh(&bp->ntp_fltr_lock);
6925 rc = -ENOMEM;
6926 goto err_free;
6927 }
6928
84e86b98 6929 new_fltr->sw_id = (u16)bit_id;
c0c050c5 6930 new_fltr->flow_id = flow_id;
a54c4d74 6931 new_fltr->l2_fltr_idx = l2_idx;
c0c050c5
MC		 6932 new_fltr->rxq = rxq_index;
6933 hlist_add_head_rcu(&new_fltr->hash, head);
6934 bp->ntp_fltr_count++;
6935 spin_unlock_bh(&bp->ntp_fltr_lock);
6936
6937 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6938 schedule_work(&bp->sp_task);
6939
6940 return new_fltr->sw_id;
6941
6942err_free:
6943 kfree(new_fltr);
6944 return rc;
6945}
6946
6947static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6948{
6949 int i;
6950
6951 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6952 struct hlist_head *head;
6953 struct hlist_node *tmp;
6954 struct bnxt_ntuple_filter *fltr;
6955 int rc;
6956
6957 head = &bp->ntp_fltr_hash_tbl[i];
6958 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6959 bool del = false;
6960
6961 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6962 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6963 fltr->flow_id,
6964 fltr->sw_id)) {
6965 bnxt_hwrm_cfa_ntuple_filter_free(bp,
6966 fltr);
6967 del = true;
6968 }
6969 } else {
6970 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6971 fltr);
6972 if (rc)
6973 del = true;
6974 else
6975 set_bit(BNXT_FLTR_VALID, &fltr->state);
6976 }
6977
6978 if (del) {
6979 spin_lock_bh(&bp->ntp_fltr_lock);
6980 hlist_del_rcu(&fltr->hash);
6981 bp->ntp_fltr_count--;
6982 spin_unlock_bh(&bp->ntp_fltr_lock);
6983 synchronize_rcu();
6984 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6985 kfree(fltr);
6986 }
6987 }
6988 }
19241368
JH		 6989 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6990 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 6991}
6992
6993#else
6994
6995static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6996{
6997}
6998
6999#endif /* CONFIG_RFS_ACCEL */
7000
ad51b8e9
AD		 7001static void bnxt_udp_tunnel_add(struct net_device *dev,
7002 struct udp_tunnel_info *ti)
c0c050c5
MC		 7003{
7004 struct bnxt *bp = netdev_priv(dev);
7005
ad51b8e9 7006 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 7007 return;
7008
ad51b8e9 7009 if (!netif_running(dev))
c0c050c5
MC		 7010 return;
7011
ad51b8e9
AD		 7012 switch (ti->type) {
7013 case UDP_TUNNEL_TYPE_VXLAN:
7014 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7015 return;
c0c050c5 7016
ad51b8e9
AD		 7017 bp->vxlan_port_cnt++;
7018 if (bp->vxlan_port_cnt == 1) {
7019 bp->vxlan_port = ti->port;
7020 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
7021 schedule_work(&bp->sp_task);
7022 }
7023 break;
7cdd5fc3
AD		 7024 case UDP_TUNNEL_TYPE_GENEVE:
7025 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7026 return;
7027
7028 bp->nge_port_cnt++;
7029 if (bp->nge_port_cnt == 1) {
7030 bp->nge_port = ti->port;
7031 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7032 }
7033 break;
ad51b8e9
AD		 7034 default:
7035 return;
c0c050c5 7036 }
ad51b8e9
AD		 7037
7038 schedule_work(&bp->sp_task);
c0c050c5
MC		 7039}
7040
ad51b8e9
AD		 7041static void bnxt_udp_tunnel_del(struct net_device *dev,
7042 struct udp_tunnel_info *ti)
c0c050c5
MC		 7043{
7044 struct bnxt *bp = netdev_priv(dev);
7045
ad51b8e9 7046 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 7047 return;
7048
ad51b8e9 7049 if (!netif_running(dev))
c0c050c5
MC		 7050 return;
7051
ad51b8e9
AD		 7052 switch (ti->type) {
7053 case UDP_TUNNEL_TYPE_VXLAN:
7054 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7055 return;
c0c050c5
MC		 7056 bp->vxlan_port_cnt--;
7057
ad51b8e9
AD		 7058 if (bp->vxlan_port_cnt != 0)
7059 return;
7060
7061 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7062 break;
7cdd5fc3
AD		 7063 case UDP_TUNNEL_TYPE_GENEVE:
7064 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7065 return;
7066 bp->nge_port_cnt--;
7067
7068 if (bp->nge_port_cnt != 0)
7069 return;
7070
7071 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7072 break;
ad51b8e9
AD		 7073 default:
7074 return;
c0c050c5 7075 }
ad51b8e9
AD		 7076
7077 schedule_work(&bp->sp_task);
c0c050c5
MC		 7078}
7079
7080static const struct net_device_ops bnxt_netdev_ops = {
7081 .ndo_open = bnxt_open,
7082 .ndo_start_xmit = bnxt_start_xmit,
7083 .ndo_stop = bnxt_close,
7084 .ndo_get_stats64 = bnxt_get_stats64,
7085 .ndo_set_rx_mode = bnxt_set_rx_mode,
7086 .ndo_do_ioctl = bnxt_ioctl,
7087 .ndo_validate_addr = eth_validate_addr,
7088 .ndo_set_mac_address = bnxt_change_mac_addr,
7089 .ndo_change_mtu = bnxt_change_mtu,
7090 .ndo_fix_features = bnxt_fix_features,
7091 .ndo_set_features = bnxt_set_features,
7092 .ndo_tx_timeout = bnxt_tx_timeout,
7093#ifdef CONFIG_BNXT_SRIOV
7094 .ndo_get_vf_config = bnxt_get_vf_config,
7095 .ndo_set_vf_mac = bnxt_set_vf_mac,
7096 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
7097 .ndo_set_vf_rate = bnxt_set_vf_bw,
7098 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
7099 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
7100#endif
7101#ifdef CONFIG_NET_POLL_CONTROLLER
7102 .ndo_poll_controller = bnxt_poll_controller,
7103#endif
7104 .ndo_setup_tc = bnxt_setup_tc,
7105#ifdef CONFIG_RFS_ACCEL
7106 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
7107#endif
ad51b8e9
AD		 7108 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
7109 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
c0c050c5
MC		 7110};
7111
7112static void bnxt_remove_one(struct pci_dev *pdev)
7113{
7114 struct net_device *dev = pci_get_drvdata(pdev);
7115 struct bnxt *bp = netdev_priv(dev);
7116
7117 if (BNXT_PF(bp))
7118 bnxt_sriov_disable(bp);
7119
6316ea6d 7120 pci_disable_pcie_error_reporting(pdev);
c0c050c5
MC		 7121 unregister_netdev(dev);
7122 cancel_work_sync(&bp->sp_task);
7123 bp->sp_event = 0;
7124
7809592d 7125 bnxt_clear_int_mode(bp);
be58a0da 7126 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5 7127 bnxt_free_hwrm_resources(bp);
7df4ae9f 7128 bnxt_dcb_free(bp);
c0c050c5
MC		 7129 pci_iounmap(pdev, bp->bar2);
7130 pci_iounmap(pdev, bp->bar1);
7131 pci_iounmap(pdev, bp->bar0);
a588e458
MC		 7132 kfree(bp->edev);
7133 bp->edev = NULL;
c0c050c5
MC		 7134 free_netdev(dev);
7135
7136 pci_release_regions(pdev);
7137 pci_disable_device(pdev);
7138}
7139
7140static int bnxt_probe_phy(struct bnxt *bp)
7141{
7142 int rc = 0;
7143 struct bnxt_link_info *link_info = &bp->link_info;
c0c050c5 7144
170ce013
MC		 7145 rc = bnxt_hwrm_phy_qcaps(bp);
7146 if (rc) {
7147 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7148 rc);
7149 return rc;
7150 }
7151
c0c050c5
MC		 7152 rc = bnxt_update_link(bp, false);
7153 if (rc) {
7154 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7155 rc);
7156 return rc;
7157 }
7158
93ed8117
MC		 7159 /* Older firmware does not have supported_auto_speeds, so assume
7160 * that all supported speeds can be autonegotiated.
7161 */
7162 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7163 link_info->support_auto_speeds = link_info->support_speeds;
7164
c0c050c5 7165 /*initialize the ethool setting copy with NVM settings */
0d8abf02 7166 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
c9ee9516
MC		 7167 link_info->autoneg = BNXT_AUTONEG_SPEED;
7168 if (bp->hwrm_spec_code >= 0x10201) {
7169 if (link_info->auto_pause_setting &
7170 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7171 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7172 } else {
7173 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7174 }
0d8abf02 7175 link_info->advertising = link_info->auto_link_speeds;
0d8abf02
MC		 7176 } else {
7177 link_info->req_link_speed = link_info->force_link_speed;
7178 link_info->req_duplex = link_info->duplex_setting;
c0c050c5 7179 }
c9ee9516
MC		 7180 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7181 link_info->req_flow_ctrl =
7182 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7183 else
7184 link_info->req_flow_ctrl = link_info->force_pause_setting;
c0c050c5
MC		 7185 return rc;
7186}
7187
7188static int bnxt_get_max_irq(struct pci_dev *pdev)
7189{
7190 u16 ctrl;
7191
7192 if (!pdev->msix_cap)
7193 return 1;
7194
7195 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7196 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7197}
7198
6e6c5a57
MC		 7199static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7200 int *max_cp)
c0c050c5 7201{
6e6c5a57 7202 int max_ring_grps = 0;
c0c050c5 7203
379a80a1 7204#ifdef CONFIG_BNXT_SRIOV
415b6f19 7205 if (!BNXT_PF(bp)) {
c0c050c5
MC		 7206 *max_tx = bp->vf.max_tx_rings;
7207 *max_rx = bp->vf.max_rx_rings;
6e6c5a57
MC		 7208 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7209 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
b72d4a68 7210 max_ring_grps = bp->vf.max_hw_ring_grps;
415b6f19 7211 } else
379a80a1 7212#endif
415b6f19
AB		 7213 {
7214 *max_tx = bp->pf.max_tx_rings;
7215 *max_rx = bp->pf.max_rx_rings;
7216 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7217 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7218 max_ring_grps = bp->pf.max_hw_ring_grps;
c0c050c5 7219 }
76595193
PS		 7220 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7221 *max_cp -= 1;
7222 *max_rx -= 2;
7223 }
c0c050c5
MC		 7224 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7225 *max_rx >>= 1;
b72d4a68 7226 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 7227}
7228
7229int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7230{
7231 int rx, tx, cp;
7232
7233 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7234 if (!rx || !tx || !cp)
7235 return -ENOMEM;
7236
7237 *max_rx = rx;
7238 *max_tx = tx;
7239 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7240}
7241
e4060d30
MC		 7242static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7243 bool shared)
7244{
7245 int rc;
7246
7247 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
bdbd1eb5
MC		 7248 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7249 /* Not enough rings, try disabling agg rings. */
7250 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7251 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7252 if (rc)
7253 return rc;
7254 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7255 bp->dev->hw_features &= ~NETIF_F_LRO;
7256 bp->dev->features &= ~NETIF_F_LRO;
7257 bnxt_set_ring_params(bp);
7258 }
e4060d30
MC		 7259
7260 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7261 int max_cp, max_stat, max_irq;
7262
7263 /* Reserve minimum resources for RoCE */
7264 max_cp = bnxt_get_max_func_cp_rings(bp);
7265 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7266 max_irq = bnxt_get_max_func_irqs(bp);
7267 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7268 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7269 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7270 return 0;
7271
7272 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7273 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7274 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7275 max_cp = min_t(int, max_cp, max_irq);
7276 max_cp = min_t(int, max_cp, max_stat);
7277 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7278 if (rc)
7279 rc = 0;
7280 }
7281 return rc;
7282}
7283
6e6c5a57
MC		 7284static int bnxt_set_dflt_rings(struct bnxt *bp)
7285{
7286 int dflt_rings, max_rx_rings, max_tx_rings, rc;
7287 bool sh = true;
7288
7289 if (sh)
7290 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7291 dflt_rings = netif_get_num_default_rss_queues();
e4060d30 7292 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57
MC		 7293 if (rc)
7294 return rc;
7295 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7296 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
391be5c2
MC		 7297
7298 rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
7299 if (rc)
7300 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
7301
6e6c5a57
MC		 7302 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7303 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7304 bp->tx_nr_rings + bp->rx_nr_rings;
7305 bp->num_stat_ctxs = bp->cp_nr_rings;
76595193
PS		 7306 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7307 bp->rx_nr_rings++;
7308 bp->cp_nr_rings++;
7309 }
6e6c5a57 7310 return rc;
c0c050c5
MC		 7311}
7312
7b08f661
MC		 7313void bnxt_restore_pf_fw_resources(struct bnxt *bp)
7314{
7315 ASSERT_RTNL();
7316 bnxt_hwrm_func_qcaps(bp);
a588e458 7317 bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
7b08f661
MC		 7318}
7319
90c4f788
AK		 7320static void bnxt_parse_log_pcie_link(struct bnxt *bp)
7321{
7322 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
7323 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
7324
7325 if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
7326 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
7327 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
7328 else
7329 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
7330 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
7331 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
7332 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
7333 "Unknown", width);
7334}
7335
c0c050c5
MC		 7336static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7337{
7338 static int version_printed;
7339 struct net_device *dev;
7340 struct bnxt *bp;
6e6c5a57 7341 int rc, max_irqs;
c0c050c5 7342
fa853dda
PS		 7343 if (pdev->device == 0x16cd && pci_is_bridge(pdev))
7344 return -ENODEV;
7345
c0c050c5
MC		 7346 if (version_printed++ == 0)
7347 pr_info("%s", version);
7348
7349 max_irqs = bnxt_get_max_irq(pdev);
7350 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
7351 if (!dev)
7352 return -ENOMEM;
7353
7354 bp = netdev_priv(dev);
7355
7356 if (bnxt_vf_pciid(ent->driver_data))
7357 bp->flags |= BNXT_FLAG_VF;
7358
2bcfa6f6 7359 if (pdev->msix_cap)
c0c050c5 7360 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 7361
7362 rc = bnxt_init_board(pdev, dev);
7363 if (rc < 0)
7364 goto init_err_free;
7365
7366 dev->netdev_ops = &bnxt_netdev_ops;
7367 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
7368 dev->ethtool_ops = &bnxt_ethtool_ops;
7369
7370 pci_set_drvdata(pdev, dev);
7371
3e8060fa
PS		 7372 rc = bnxt_alloc_hwrm_resources(bp);
7373 if (rc)
7374 goto init_err;
7375
7376 mutex_init(&bp->hwrm_cmd_lock);
7377 rc = bnxt_hwrm_ver_get(bp);
7378 if (rc)
7379 goto init_err;
7380
5ac67d8b
RS		 7381 bnxt_hwrm_fw_set_time(bp);
7382
c0c050c5
MC		 7383 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7384 NETIF_F_TSO | NETIF_F_TSO6 |
7385 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7e13318d 7386 NETIF_F_GSO_IPXIP4 |
152971ee
AD		 7387 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7388 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
3e8060fa
PS		 7389 NETIF_F_RXCSUM | NETIF_F_GRO;
7390
7391 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
7392 dev->hw_features |= NETIF_F_LRO;
c0c050c5 7393
c0c050c5
MC		 7394 dev->hw_enc_features =
7395 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7396 NETIF_F_TSO | NETIF_F_TSO6 |
7397 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
152971ee 7398 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7e13318d 7399 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
152971ee
AD		 7400 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
7401 NETIF_F_GSO_GRE_CSUM;
c0c050c5
MC		 7402 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
7403 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7404 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
7405 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
7406 dev->priv_flags |= IFF_UNICAST_FLT;
7407
e1c6dcca
JW		 7408 /* MTU range: 60 - 9500 */
7409 dev->min_mtu = ETH_ZLEN;
c61fb99c 7410 dev->max_mtu = BNXT_MAX_MTU;
e1c6dcca 7411
7df4ae9f
MC		 7412 bnxt_dcb_init(bp);
7413
c0c050c5
MC		 7414#ifdef CONFIG_BNXT_SRIOV
7415 init_waitqueue_head(&bp->sriov_cfg_wait);
7416#endif
309369c9 7417 bp->gro_func = bnxt_gro_func_5730x;
94758f8d
MC		 7418 if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
7419 bp->gro_func = bnxt_gro_func_5731x;
309369c9 7420
c0c050c5
MC		 7421 rc = bnxt_hwrm_func_drv_rgtr(bp);
7422 if (rc)
7423 goto init_err;
7424
a1653b13
MC		 7425 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
7426 if (rc)
7427 goto init_err;
7428
a588e458
MC		 7429 bp->ulp_probe = bnxt_ulp_probe;
7430
c0c050c5
MC		 7431 /* Get the MAX capabilities for this function */
7432 rc = bnxt_hwrm_func_qcaps(bp);
7433 if (rc) {
7434 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
7435 rc);
7436 rc = -1;
7437 goto init_err;
7438 }
7439
7440 rc = bnxt_hwrm_queue_qportcfg(bp);
7441 if (rc) {
7442 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
7443 rc);
7444 rc = -1;
7445 goto init_err;
7446 }
7447
567b2abe 7448 bnxt_hwrm_func_qcfg(bp);
5ad2cbee 7449 bnxt_hwrm_port_led_qcaps(bp);
567b2abe 7450
c61fb99c 7451 bnxt_set_rx_skb_mode(bp, false);
c0c050c5
MC		 7452 bnxt_set_tpa_flags(bp);
7453 bnxt_set_ring_params(bp);
33c2657e 7454 bnxt_set_max_func_irqs(bp, max_irqs);
bdbd1eb5
MC		 7455 rc = bnxt_set_dflt_rings(bp);
7456 if (rc) {
7457 netdev_err(bp->dev, "Not enough rings available.\n");
7458 rc = -ENOMEM;
7459 goto init_err;
7460 }
c0c050c5 7461
87da7f79
MC		 7462 /* Default RSS hash cfg. */
7463 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
7464 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
7465 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
7466 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
7467 if (!BNXT_CHIP_NUM_57X0X(bp->chip_num) &&
7468 !BNXT_CHIP_TYPE_NITRO_A0(bp) &&
7469 bp->hwrm_spec_code >= 0x10501) {
7470 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
7471 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
7472 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
7473 }
7474
8fdefd63 7475 bnxt_hwrm_vnic_qcaps(bp);
8079e8f1 7476 if (bnxt_rfs_supported(bp)) {
2bcfa6f6
MC		 7477 dev->hw_features |= NETIF_F_NTUPLE;
7478 if (bnxt_rfs_capable(bp)) {
7479 bp->flags |= BNXT_FLAG_RFS;
7480 dev->features |= NETIF_F_NTUPLE;
7481 }
7482 }
7483
c0c050c5
MC		 7484 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
7485 bp->flags |= BNXT_FLAG_STRIP_VLAN;
7486
7487 rc = bnxt_probe_phy(bp);
7488 if (rc)
7489 goto init_err;
7490
aa8ed021
MC		 7491 rc = bnxt_hwrm_func_reset(bp);
7492 if (rc)
7493 goto init_err;
7494
7809592d 7495 rc = bnxt_init_int_mode(bp);
c0c050c5
MC		 7496 if (rc)
7497 goto init_err;
7498
7809592d
MC		 7499 rc = register_netdev(dev);
7500 if (rc)
7501 goto init_err_clr_int;
7502
c0c050c5
MC		 7503 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
7504 board_info[ent->driver_data].name,
7505 (long)pci_resource_start(pdev, 0), dev->dev_addr);
7506
90c4f788
AK		 7507 bnxt_parse_log_pcie_link(bp);
7508
c0c050c5
MC		 7509 return 0;
7510
7809592d
MC		 7511init_err_clr_int:
7512 bnxt_clear_int_mode(bp);
7513
c0c050c5
MC		 7514init_err:
7515 pci_iounmap(pdev, bp->bar0);
7516 pci_release_regions(pdev);
7517 pci_disable_device(pdev);
7518
7519init_err_free:
7520 free_netdev(dev);
7521 return rc;
7522}
7523
6316ea6d
SB		 7524/**
7525 * bnxt_io_error_detected - called when PCI error is detected
7526 * @pdev: Pointer to PCI device
7527 * @state: The current pci connection state
7528 *
7529 * This function is called after a PCI bus error affecting
7530 * this device has been detected.
7531 */
7532static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
7533 pci_channel_state_t state)
7534{
7535 struct net_device *netdev = pci_get_drvdata(pdev);
a588e458 7536 struct bnxt *bp = netdev_priv(netdev);
6316ea6d
SB		 7537
7538 netdev_info(netdev, "PCI I/O error detected\n");
7539
7540 rtnl_lock();
7541 netif_device_detach(netdev);
7542
a588e458
MC		 7543 bnxt_ulp_stop(bp);
7544
6316ea6d
SB		 7545 if (state == pci_channel_io_perm_failure) {
7546 rtnl_unlock();
7547 return PCI_ERS_RESULT_DISCONNECT;
7548 }
7549
7550 if (netif_running(netdev))
7551 bnxt_close(netdev);
7552
7553 pci_disable_device(pdev);
7554 rtnl_unlock();
7555
7556 /* Request a slot slot reset. */
7557 return PCI_ERS_RESULT_NEED_RESET;
7558}
7559
7560/**
7561 * bnxt_io_slot_reset - called after the pci bus has been reset.
7562 * @pdev: Pointer to PCI device
7563 *
7564 * Restart the card from scratch, as if from a cold-boot.
7565 * At this point, the card has exprienced a hard reset,
7566 * followed by fixups by BIOS, and has its config space
7567 * set up identically to what it was at cold boot.
7568 */
7569static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
7570{
7571 struct net_device *netdev = pci_get_drvdata(pdev);
7572 struct bnxt *bp = netdev_priv(netdev);
7573 int err = 0;
7574 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7575
7576 netdev_info(bp->dev, "PCI Slot Reset\n");
7577
7578 rtnl_lock();
7579
7580 if (pci_enable_device(pdev)) {
7581 dev_err(&pdev->dev,
7582 "Cannot re-enable PCI device after reset.\n");
7583 } else {
7584 pci_set_master(pdev);
7585
aa8ed021
MC		 7586 err = bnxt_hwrm_func_reset(bp);
7587 if (!err && netif_running(netdev))
6316ea6d
SB		 7588 err = bnxt_open(netdev);
7589
a588e458 7590 if (!err) {
6316ea6d 7591 result = PCI_ERS_RESULT_RECOVERED;
a588e458
MC		 7592 bnxt_ulp_start(bp);
7593 }
6316ea6d
SB		 7594 }
7595
7596 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7597 dev_close(netdev);
7598
7599 rtnl_unlock();
7600
7601 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7602 if (err) {
7603 dev_err(&pdev->dev,
7604 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7605 err); /* non-fatal, continue */
7606 }
7607
7608 return PCI_ERS_RESULT_RECOVERED;
7609}
7610
7611/**
7612 * bnxt_io_resume - called when traffic can start flowing again.
7613 * @pdev: Pointer to PCI device
7614 *
7615 * This callback is called when the error recovery driver tells
7616 * us that its OK to resume normal operation.
7617 */
7618static void bnxt_io_resume(struct pci_dev *pdev)
7619{
7620 struct net_device *netdev = pci_get_drvdata(pdev);
7621
7622 rtnl_lock();
7623
7624 netif_device_attach(netdev);
7625
7626 rtnl_unlock();
7627}
7628
7629static const struct pci_error_handlers bnxt_err_handler = {
7630 .error_detected = bnxt_io_error_detected,
7631 .slot_reset = bnxt_io_slot_reset,
7632 .resume = bnxt_io_resume
7633};
7634
c0c050c5
MC		 7635static struct pci_driver bnxt_pci_driver = {
7636 .name = DRV_MODULE_NAME,
7637 .id_table = bnxt_pci_tbl,
7638 .probe = bnxt_init_one,
7639 .remove = bnxt_remove_one,
6316ea6d 7640 .err_handler = &bnxt_err_handler,
c0c050c5
MC		 7641#if defined(CONFIG_BNXT_SRIOV)
7642 .sriov_configure = bnxt_sriov_configure,
7643#endif
7644};
7645
7646module_pci_driver(bnxt_pci_driver);
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