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3c8c20db EP |
1 | /* Broadcom NetXtreme-C/E network driver. |
2 | * | |
3 | * Copyright (c) 2020 Broadcom Limited | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #ifndef BNXT_HWRM_H | |
11 | #define BNXT_HWRM_H | |
12 | ||
13 | #include "bnxt_hsi.h" | |
14 | ||
f9ff5782 EP |
15 | enum bnxt_hwrm_ctx_flags { |
16 | /* Update the HWRM_API_FLAGS right below for any new non-internal bit added here */ | |
17 | BNXT_HWRM_INTERNAL_CTX_OWNED = BIT(0), /* caller owns the context */ | |
18 | BNXT_HWRM_INTERNAL_RESP_DIRTY = BIT(1), /* response contains data */ | |
19 | BNXT_HWRM_CTX_SILENT = BIT(2), /* squelch firmware errors */ | |
20 | BNXT_HWRM_FULL_WAIT = BIT(3), /* wait for full timeout of HWRM command */ | |
21 | }; | |
22 | ||
23 | #define HWRM_API_FLAGS (BNXT_HWRM_CTX_SILENT | BNXT_HWRM_FULL_WAIT) | |
24 | ||
25 | struct bnxt_hwrm_ctx { | |
26 | u64 sentinel; | |
27 | dma_addr_t dma_handle; | |
28 | struct output *resp; | |
29 | struct input *req; | |
21380817 EP |
30 | dma_addr_t slice_handle; |
31 | void *slice_addr; | |
32 | u32 slice_size; | |
f9ff5782 EP |
33 | u32 req_len; |
34 | enum bnxt_hwrm_ctx_flags flags; | |
35 | unsigned int timeout; | |
21380817 EP |
36 | u32 allocated; |
37 | gfp_t gfp; | |
f9ff5782 EP |
38 | }; |
39 | ||
68f684e2 EP |
40 | enum bnxt_hwrm_wait_state { |
41 | BNXT_HWRM_PENDING, | |
42 | BNXT_HWRM_DEFERRED, | |
43 | BNXT_HWRM_COMPLETE, | |
44 | BNXT_HWRM_CANCELLED, | |
45 | }; | |
46 | ||
47 | enum bnxt_hwrm_chnl { BNXT_HWRM_CHNL_CHIMP, BNXT_HWRM_CHNL_KONG }; | |
48 | ||
49 | struct bnxt_hwrm_wait_token { | |
50 | struct rcu_head rcu; | |
51 | struct hlist_node node; | |
52 | enum bnxt_hwrm_wait_state state; | |
53 | enum bnxt_hwrm_chnl dst; | |
54 | u16 seq_id; | |
55 | }; | |
56 | ||
57 | void hwrm_update_token(struct bnxt *bp, u16 seq, enum bnxt_hwrm_wait_state s); | |
58 | ||
3c8c20db EP |
59 | #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len) |
60 | #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) | |
f668a21c | 61 | #define HWRM_CMD_MAX_TIMEOUT 40000U |
3c8c20db EP |
62 | #define SHORT_HWRM_CMD_TIMEOUT 20 |
63 | #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout) | |
64 | #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4) | |
f9ff5782 EP |
65 | #define BNXT_HWRM_TARGET 0xffff |
66 | #define BNXT_HWRM_NO_CMPL_RING -1 | |
3c8c20db | 67 | #define BNXT_HWRM_REQ_MAX_SIZE 128 |
f9ff5782 EP |
68 | #define BNXT_HWRM_DMA_SIZE (2 * PAGE_SIZE) /* space for req+resp */ |
69 | #define BNXT_HWRM_RESP_RESERVED PAGE_SIZE | |
70 | #define BNXT_HWRM_RESP_OFFSET (BNXT_HWRM_DMA_SIZE - \ | |
71 | BNXT_HWRM_RESP_RESERVED) | |
72 | #define BNXT_HWRM_CTX_OFFSET (BNXT_HWRM_RESP_OFFSET - \ | |
73 | sizeof(struct bnxt_hwrm_ctx)) | |
74 | #define BNXT_HWRM_DMA_ALIGN 16 | |
75 | #define BNXT_HWRM_SENTINEL 0xb6e1f68a12e9a7eb /* arbitrary value */ | |
3c8c20db EP |
76 | #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \ |
77 | BNXT_HWRM_REQ_MAX_SIZE) | |
78 | #define HWRM_SHORT_MIN_TIMEOUT 3 | |
79 | #define HWRM_SHORT_MAX_TIMEOUT 10 | |
80 | #define HWRM_SHORT_TIMEOUT_COUNTER 5 | |
81 | ||
82 | #define HWRM_MIN_TIMEOUT 25 | |
83 | #define HWRM_MAX_TIMEOUT 40 | |
84 | ||
f9ff5782 EP |
85 | #define HWRM_WAIT_MUST_ABORT(bp, ctx) \ |
86 | (le16_to_cpu((ctx)->req->req_type) != HWRM_VER_GET && \ | |
3c8c20db EP |
87 | !bnxt_is_fw_healthy(bp)) |
88 | ||
f9ff5782 EP |
89 | static inline unsigned int hwrm_total_timeout(unsigned int n) |
90 | { | |
91 | return n <= HWRM_SHORT_TIMEOUT_COUNTER ? n * HWRM_SHORT_MIN_TIMEOUT : | |
92 | HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + | |
93 | (n - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT; | |
94 | } | |
95 | ||
3c8c20db | 96 | |
acd883e5 | 97 | #define HWRM_VALID_BIT_DELAY_USEC 50000 |
3c8c20db | 98 | |
3c8c20db EP |
99 | static inline bool bnxt_cfa_hwrm_message(u16 req_type) |
100 | { | |
101 | switch (req_type) { | |
102 | case HWRM_CFA_ENCAP_RECORD_ALLOC: | |
103 | case HWRM_CFA_ENCAP_RECORD_FREE: | |
104 | case HWRM_CFA_DECAP_FILTER_ALLOC: | |
105 | case HWRM_CFA_DECAP_FILTER_FREE: | |
106 | case HWRM_CFA_EM_FLOW_ALLOC: | |
107 | case HWRM_CFA_EM_FLOW_FREE: | |
108 | case HWRM_CFA_EM_FLOW_CFG: | |
109 | case HWRM_CFA_FLOW_ALLOC: | |
110 | case HWRM_CFA_FLOW_FREE: | |
111 | case HWRM_CFA_FLOW_INFO: | |
112 | case HWRM_CFA_FLOW_FLUSH: | |
113 | case HWRM_CFA_FLOW_STATS: | |
114 | case HWRM_CFA_METER_PROFILE_ALLOC: | |
115 | case HWRM_CFA_METER_PROFILE_FREE: | |
116 | case HWRM_CFA_METER_PROFILE_CFG: | |
117 | case HWRM_CFA_METER_INSTANCE_ALLOC: | |
118 | case HWRM_CFA_METER_INSTANCE_FREE: | |
119 | return true; | |
120 | default: | |
121 | return false; | |
122 | } | |
123 | } | |
124 | ||
125 | static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req) | |
126 | { | |
127 | return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL && | |
128 | (bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)) || | |
129 | le16_to_cpu(req->target_id) == HWRM_TARGET_ID_KONG)); | |
130 | } | |
131 | ||
f9ff5782 EP |
132 | int __hwrm_req_init(struct bnxt *bp, void **req, u16 req_type, u32 req_len); |
133 | #define hwrm_req_init(bp, req, req_type) \ | |
134 | __hwrm_req_init((bp), (void **)&(req), (req_type), sizeof(*(req))) | |
135 | void *hwrm_req_hold(struct bnxt *bp, void *req); | |
136 | void hwrm_req_drop(struct bnxt *bp, void *req); | |
137 | void hwrm_req_flags(struct bnxt *bp, void *req, enum bnxt_hwrm_ctx_flags flags); | |
138 | void hwrm_req_timeout(struct bnxt *bp, void *req, unsigned int timeout); | |
139 | int hwrm_req_send(struct bnxt *bp, void *req); | |
140 | int hwrm_req_send_silent(struct bnxt *bp, void *req); | |
ecddc29d | 141 | int hwrm_req_replace(struct bnxt *bp, void *req, void *new_req, u32 len); |
21380817 EP |
142 | void hwrm_req_alloc_flags(struct bnxt *bp, void *req, gfp_t flags); |
143 | void *hwrm_req_dma_slice(struct bnxt *bp, void *req, u32 size, dma_addr_t *dma); | |
3c8c20db | 144 | #endif |