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d7afae05 | 1 | /* cnic.h: QLogic CNIC core network driver. |
a4636960 | 2 | * |
c3661283 | 3 | * Copyright (c) 2006-2014 Broadcom Corporation |
d7afae05 | 4 | * Copyright (c) 2014 QLogic Corporation |
a4636960 MC |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
12 | ||
13 | #ifndef CNIC_H | |
14 | #define CNIC_H | |
15 | ||
523224a3 DK |
16 | #define HC_INDEX_ISCSI_EQ_CONS 6 |
17 | ||
18 | #define HC_INDEX_FCOE_EQ_CONS 3 | |
19 | ||
20 | #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 | |
21 | #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 | |
22 | ||
a4636960 MC |
23 | #define KWQ_PAGE_CNT 4 |
24 | #define KCQ_PAGE_CNT 16 | |
25 | ||
26 | #define KWQ_CID 24 | |
27 | #define KCQ_CID 25 | |
28 | ||
29 | /* | |
30 | * krnlq_context definition | |
31 | */ | |
32 | #define L5_KRNLQ_FLAGS 0x00000000 | |
33 | #define L5_KRNLQ_SIZE 0x00000000 | |
34 | #define L5_KRNLQ_TYPE 0x00000000 | |
35 | #define KRNLQ_FLAGS_PG_SZ (0xf<<0) | |
36 | #define KRNLQ_FLAGS_PG_SZ_256 (0<<0) | |
37 | #define KRNLQ_FLAGS_PG_SZ_512 (1<<0) | |
38 | #define KRNLQ_FLAGS_PG_SZ_1K (2<<0) | |
39 | #define KRNLQ_FLAGS_PG_SZ_2K (3<<0) | |
40 | #define KRNLQ_FLAGS_PG_SZ_4K (4<<0) | |
41 | #define KRNLQ_FLAGS_PG_SZ_8K (5<<0) | |
42 | #define KRNLQ_FLAGS_PG_SZ_16K (6<<0) | |
43 | #define KRNLQ_FLAGS_PG_SZ_32K (7<<0) | |
44 | #define KRNLQ_FLAGS_PG_SZ_64K (8<<0) | |
45 | #define KRNLQ_FLAGS_PG_SZ_128K (9<<0) | |
46 | #define KRNLQ_FLAGS_PG_SZ_256K (10<<0) | |
47 | #define KRNLQ_FLAGS_PG_SZ_512K (11<<0) | |
48 | #define KRNLQ_FLAGS_PG_SZ_1M (12<<0) | |
49 | #define KRNLQ_FLAGS_PG_SZ_2M (13<<0) | |
50 | #define KRNLQ_FLAGS_QE_SELF_SEQ (1<<15) | |
51 | #define KRNLQ_SIZE_TYPE_SIZE ((((0x28 + 0x1f) & ~0x1f) / 0x20) << 16) | |
52 | #define KRNLQ_TYPE_TYPE (0xf<<28) | |
53 | #define KRNLQ_TYPE_TYPE_EMPTY (0<<28) | |
54 | #define KRNLQ_TYPE_TYPE_KRNLQ (6<<28) | |
55 | ||
56 | #define L5_KRNLQ_HOST_QIDX 0x00000004 | |
57 | #define L5_KRNLQ_HOST_FW_QIDX 0x00000008 | |
58 | #define L5_KRNLQ_NX_QE_SELF_SEQ 0x0000000c | |
59 | #define L5_KRNLQ_QE_SELF_SEQ_MAX 0x0000000c | |
60 | #define L5_KRNLQ_NX_QE_HADDR_HI 0x00000010 | |
61 | #define L5_KRNLQ_NX_QE_HADDR_LO 0x00000014 | |
62 | #define L5_KRNLQ_PGTBL_PGIDX 0x00000018 | |
63 | #define L5_KRNLQ_NX_PG_QIDX 0x00000018 | |
64 | #define L5_KRNLQ_PGTBL_NPAGES 0x0000001c | |
65 | #define L5_KRNLQ_QIDX_INCR 0x0000001c | |
66 | #define L5_KRNLQ_PGTBL_HADDR_HI 0x00000020 | |
67 | #define L5_KRNLQ_PGTBL_HADDR_LO 0x00000024 | |
68 | ||
69 | #define BNX2_PG_CTX_MAP 0x1a0034 | |
70 | #define BNX2_ISCSI_CTX_MAP 0x1a0074 | |
71 | ||
a4636960 MC |
72 | #define MAX_COMPLETED_KCQE 64 |
73 | ||
74 | #define MAX_CNIC_L5_CONTEXT 256 | |
75 | ||
76 | #define MAX_CM_SK_TBL_SZ MAX_CNIC_L5_CONTEXT | |
77 | ||
78 | #define MAX_ISCSI_TBL_SZ 256 | |
79 | ||
80 | #define CNIC_LOCAL_PORT_MIN 60000 | |
9b093360 | 81 | #define CNIC_LOCAL_PORT_MAX 61024 |
a4636960 MC |
82 | #define CNIC_LOCAL_PORT_RANGE (CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN) |
83 | ||
2bc4078e MC |
84 | #define KWQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kwqe)) |
85 | #define KCQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kcqe)) | |
a4636960 MC |
86 | #define MAX_KWQE_CNT (KWQE_CNT - 1) |
87 | #define MAX_KCQE_CNT (KCQE_CNT - 1) | |
88 | ||
89 | #define MAX_KWQ_IDX ((KWQ_PAGE_CNT * KWQE_CNT) - 1) | |
90 | #define MAX_KCQ_IDX ((KCQ_PAGE_CNT * KCQE_CNT) - 1) | |
91 | ||
2bc4078e | 92 | #define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BNX2_PAGE_BITS - 5)) |
a4636960 MC |
93 | #define KWQ_IDX(x) ((x) & MAX_KWQE_CNT) |
94 | ||
2bc4078e | 95 | #define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BNX2_PAGE_BITS - 5)) |
a4636960 MC |
96 | #define KCQ_IDX(x) ((x) & MAX_KCQE_CNT) |
97 | ||
98 | #define BNX2X_NEXT_KCQE(x) (((x) & (MAX_KCQE_CNT - 1)) == \ | |
99 | (MAX_KCQE_CNT - 1)) ? \ | |
100 | (x) + 2 : (x) + 1 | |
101 | ||
102 | #define BNX2X_KWQ_DATA_PG(cp, x) ((x) / (cp)->kwq_16_data_pp) | |
103 | #define BNX2X_KWQ_DATA_IDX(cp, x) ((x) % (cp)->kwq_16_data_pp) | |
104 | #define BNX2X_KWQ_DATA(cp, x) \ | |
105 | &(cp)->kwq_16_data[BNX2X_KWQ_DATA_PG(cp, x)][BNX2X_KWQ_DATA_IDX(cp, x)] | |
106 | ||
a9736c08 | 107 | #define DEF_IPID_START 0x8000 |
a4636960 MC |
108 | |
109 | #define DEF_KA_TIMEOUT 10000 | |
110 | #define DEF_KA_INTERVAL 300000 | |
111 | #define DEF_KA_MAX_PROBE_COUNT 3 | |
112 | #define DEF_TOS 0 | |
113 | #define DEF_TTL 0xfe | |
114 | #define DEF_SND_SEQ_SCALE 0 | |
115 | #define DEF_RCV_BUF 0xffff | |
116 | #define DEF_SND_BUF 0xffff | |
117 | #define DEF_SEED 0 | |
118 | #define DEF_MAX_RT_TIME 500 | |
119 | #define DEF_MAX_DA_COUNT 2 | |
120 | #define DEF_SWS_TIMER 1000 | |
121 | #define DEF_MAX_CWND 0xffff | |
122 | ||
123 | struct cnic_ctx { | |
124 | u32 cid; | |
125 | void *ctx; | |
126 | dma_addr_t mapping; | |
127 | }; | |
128 | ||
129 | #define BNX2_MAX_CID 0x2000 | |
130 | ||
131 | struct cnic_dma { | |
132 | int num_pages; | |
133 | void **pg_arr; | |
134 | dma_addr_t *pg_map_arr; | |
135 | int pgtbl_size; | |
136 | u32 *pgtbl; | |
137 | dma_addr_t pgtbl_map; | |
138 | }; | |
139 | ||
140 | struct cnic_id_tbl { | |
141 | spinlock_t lock; | |
142 | u32 start; | |
143 | u32 max; | |
144 | u32 next; | |
145 | unsigned long *table; | |
146 | }; | |
147 | ||
148 | #define CNIC_KWQ16_DATA_SIZE 128 | |
149 | ||
150 | struct kwqe_16_data { | |
151 | u8 data[CNIC_KWQ16_DATA_SIZE]; | |
152 | }; | |
153 | ||
154 | struct cnic_iscsi { | |
155 | struct cnic_dma task_array_info; | |
156 | struct cnic_dma r2tq_info; | |
157 | struct cnic_dma hq_info; | |
158 | }; | |
159 | ||
160 | struct cnic_context { | |
161 | u32 cid; | |
162 | struct kwqe_16_data *kwqe_data; | |
163 | dma_addr_t kwqe_data_mapping; | |
164 | wait_queue_head_t waitq; | |
165 | int wait_cond; | |
166 | unsigned long timestamp; | |
6e0dda0c MC |
167 | unsigned long ctx_flags; |
168 | #define CTX_FL_OFFLD_START 0 | |
fdf24086 | 169 | #define CTX_FL_DELETE_WAIT 1 |
619c5cb6 | 170 | #define CTX_FL_CID_ERROR 2 |
a4636960 MC |
171 | u8 ulp_proto_id; |
172 | union { | |
173 | struct cnic_iscsi *iscsi; | |
174 | } proto; | |
175 | }; | |
176 | ||
e6c28894 MC |
177 | struct kcq_info { |
178 | struct cnic_dma dma; | |
179 | struct kcqe **kcq; | |
180 | ||
181 | u16 *hw_prod_idx_ptr; | |
182 | u16 sw_prod_idx; | |
183 | u16 *status_idx_ptr; | |
184 | u32 io_addr; | |
59e51373 MC |
185 | |
186 | u16 (*next_idx)(u16); | |
187 | u16 (*hw_idx)(u16); | |
e6c28894 MC |
188 | }; |
189 | ||
d15e2a92 EW |
190 | #define UIO_USE_TX_DOORBELL 0x017855DB |
191 | ||
cd801536 MC |
192 | struct cnic_uio_dev { |
193 | struct uio_info cnic_uinfo; | |
194 | u32 uio_dev; | |
195 | ||
196 | int l2_ring_size; | |
197 | void *l2_ring; | |
198 | dma_addr_t l2_ring_map; | |
199 | ||
200 | int l2_buf_size; | |
201 | void *l2_buf; | |
202 | dma_addr_t l2_buf_map; | |
203 | ||
204 | struct cnic_dev *dev; | |
205 | struct pci_dev *pdev; | |
206 | struct list_head list; | |
207 | }; | |
208 | ||
a4636960 MC |
209 | struct cnic_local { |
210 | ||
211 | spinlock_t cnic_ulp_lock; | |
212 | void *ulp_handle[MAX_CNIC_ULP_TYPE]; | |
213 | unsigned long ulp_flags[MAX_CNIC_ULP_TYPE]; | |
214 | #define ULP_F_INIT 0 | |
215 | #define ULP_F_START 1 | |
681dbd71 | 216 | #define ULP_F_CALL_PENDING 2 |
13707f9e | 217 | struct cnic_ulp_ops __rcu *ulp_ops[MAX_CNIC_ULP_TYPE]; |
a4636960 | 218 | |
1f1332a3 MC |
219 | unsigned long cnic_local_flags; |
220 | #define CNIC_LCL_FL_KWQ_INIT 0x0 | |
48f753d2 | 221 | #define CNIC_LCL_FL_L2_WAIT 0x1 |
541a7810 | 222 | #define CNIC_LCL_FL_RINGS_INITED 0x2 |
fab0dc89 | 223 | #define CNIC_LCL_FL_STOP_ISCSI 0x4 |
a4636960 MC |
224 | |
225 | struct cnic_dev *dev; | |
226 | ||
227 | struct cnic_eth_dev *ethdev; | |
228 | ||
cd801536 | 229 | struct cnic_uio_dev *udev; |
a4636960 | 230 | |
cd801536 | 231 | int l2_rx_ring_size; |
a4636960 MC |
232 | int l2_single_buf_size; |
233 | ||
234 | u16 *rx_cons_ptr; | |
235 | u16 *tx_cons_ptr; | |
236 | u16 rx_cons; | |
237 | u16 tx_cons; | |
238 | ||
a4636960 MC |
239 | struct cnic_dma kwq_info; |
240 | struct kwqe **kwq; | |
241 | ||
242 | struct cnic_dma kwq_16_data_info; | |
243 | ||
244 | u16 max_kwq_idx; | |
245 | ||
246 | u16 kwq_prod_idx; | |
247 | u32 kwq_io_addr; | |
248 | ||
249 | u16 *kwq_con_idx_ptr; | |
250 | u16 kwq_con_idx; | |
251 | ||
e6c28894 | 252 | struct kcq_info kcq1; |
e21ba414 | 253 | struct kcq_info kcq2; |
a4636960 | 254 | |
a4dde3ab MC |
255 | union { |
256 | void *gen; | |
257 | struct status_block_msix *bnx2; | |
523224a3 DK |
258 | struct host_hc_status_block_e1x *bnx2x_e1x; |
259 | /* index values - which counter to update */ | |
260 | #define SM_RX_ID 0 | |
261 | #define SM_TX_ID 1 | |
a4dde3ab MC |
262 | } status_blk; |
263 | ||
523224a3 | 264 | struct host_sp_status_block *bnx2x_def_status_blk; |
a4636960 MC |
265 | |
266 | u32 status_blk_num; | |
523224a3 | 267 | u32 bnx2x_igu_sb_id; |
a4636960 MC |
268 | u32 int_num; |
269 | u32 last_status_idx; | |
270 | struct tasklet_struct cnic_irq_task; | |
271 | ||
272 | struct kcqe *completed_kcq[MAX_COMPLETED_KCQE]; | |
273 | ||
274 | struct cnic_sock *csk_tbl; | |
275 | struct cnic_id_tbl csk_port_tbl; | |
276 | ||
a4636960 MC |
277 | struct cnic_dma gbl_buf_info; |
278 | ||
279 | struct cnic_iscsi *iscsi_tbl; | |
280 | struct cnic_context *ctx_tbl; | |
281 | struct cnic_id_tbl cid_tbl; | |
a4636960 | 282 | atomic_t iscsi_conn; |
520efdf4 MC |
283 | u32 iscsi_start_cid; |
284 | ||
e1928c86 MC |
285 | u32 fcoe_init_cid; |
286 | u32 fcoe_start_cid; | |
287 | struct cnic_id_tbl fcoe_cid_tbl; | |
288 | ||
520efdf4 | 289 | u32 max_cid_space; |
a4636960 MC |
290 | |
291 | /* per connection parameters */ | |
292 | int num_iscsi_tasks; | |
293 | int num_ccells; | |
294 | int task_array_size; | |
295 | int r2tq_size; | |
296 | int hq_size; | |
297 | int num_cqs; | |
298 | ||
fdf24086 MC |
299 | struct delayed_work delete_task; |
300 | ||
a4636960 MC |
301 | struct cnic_ctx *ctx_arr; |
302 | int ctx_blks; | |
303 | int ctx_blk_size; | |
e2513065 | 304 | unsigned long ctx_align; |
a4636960 MC |
305 | int cids_per_blk; |
306 | ||
307 | u32 chip_id; | |
308 | int func; | |
619c5cb6 | 309 | |
a4636960 MC |
310 | u32 shmem_base; |
311 | ||
a4636960 MC |
312 | struct cnic_ops *cnic_ops; |
313 | int (*start_hw)(struct cnic_dev *); | |
314 | void (*stop_hw)(struct cnic_dev *); | |
315 | void (*setup_pgtbl)(struct cnic_dev *, | |
316 | struct cnic_dma *); | |
317 | int (*alloc_resc)(struct cnic_dev *); | |
318 | void (*free_resc)(struct cnic_dev *); | |
319 | int (*start_cm)(struct cnic_dev *); | |
320 | void (*stop_cm)(struct cnic_dev *); | |
321 | void (*enable_int)(struct cnic_dev *); | |
322 | void (*disable_int_sync)(struct cnic_dev *); | |
323 | void (*ack_int)(struct cnic_dev *); | |
8cc0e028 | 324 | void (*arm_int)(struct cnic_dev *, u32 index); |
a4636960 | 325 | void (*close_conn)(struct cnic_sock *, u32 opcode); |
a4636960 MC |
326 | }; |
327 | ||
328 | struct bnx2x_bd_chain_next { | |
329 | u32 addr_lo; | |
330 | u32 addr_hi; | |
331 | u8 reserved[8]; | |
332 | }; | |
333 | ||
e2513065 MC |
334 | #define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1) |
335 | ||
a4636960 MC |
336 | #define ISCSI_RAMROD_CMD_ID_UPDATE_CONN (ISCSI_KCQE_OPCODE_UPDATE_CONN) |
337 | #define ISCSI_RAMROD_CMD_ID_INIT (ISCSI_KCQE_OPCODE_INIT) | |
338 | ||
339 | #define CDU_REGION_NUMBER_XCM_AG 2 | |
340 | #define CDU_REGION_NUMBER_UCM_AG 4 | |
341 | ||
e2513065 MC |
342 | #define CDU_VALID_DATA(_cid, _region, _type) \ |
343 | (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) | |
344 | ||
345 | #define CDU_CRC8(_cid, _region, _type) \ | |
346 | (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) | |
347 | ||
348 | #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \ | |
349 | (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) | |
350 | ||
351 | #define BNX2X_CONTEXT_MEM_SIZE 1024 | |
352 | #define BNX2X_FCOE_CID 16 | |
353 | ||
e2513065 MC |
354 | #define BNX2X_ISCSI_START_CID 18 |
355 | #define BNX2X_ISCSI_NUM_CONNECTIONS 128 | |
356 | #define BNX2X_ISCSI_TASK_CONTEXT_SIZE 128 | |
357 | #define BNX2X_ISCSI_MAX_PENDING_R2TS 4 | |
358 | #define BNX2X_ISCSI_R2TQE_SIZE 8 | |
359 | #define BNX2X_ISCSI_HQ_BD_SIZE 64 | |
e2513065 MC |
360 | #define BNX2X_ISCSI_GLB_BUF_SIZE 64 |
361 | #define BNX2X_ISCSI_PBL_NOT_CACHED 0xff | |
362 | #define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff | |
ceb7e1c7 | 363 | |
dc219a2e | 364 | #define BNX2X_FCOE_NUM_CONNECTIONS 1024 |
e1928c86 MC |
365 | |
366 | #define BNX2X_FCOE_L5_CID_BASE MAX_ISCSI_TBL_SZ | |
367 | ||
104a43ed | 368 | #define BNX2X_CHIP_IS_E2_PLUS(bp) (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) |
ee87a82a | 369 | |
2bc4078e MC |
370 | #define BNX2X_RX_DESC_CNT (BNX2_PAGE_SIZE / \ |
371 | sizeof(struct eth_rx_bd)) | |
e2513065 | 372 | #define BNX2X_MAX_RX_DESC_CNT (BNX2X_RX_DESC_CNT - 2) |
2bc4078e MC |
373 | #define BNX2X_RCQ_DESC_CNT (BNX2_PAGE_SIZE / \ |
374 | sizeof(union eth_rx_cqe)) | |
e2513065 MC |
375 | #define BNX2X_MAX_RCQ_DESC_CNT (BNX2X_RCQ_DESC_CNT - 1) |
376 | ||
48f753d2 MC |
377 | #define BNX2X_NEXT_RCQE(x) (((x) & BNX2X_MAX_RCQ_DESC_CNT) == \ |
378 | (BNX2X_MAX_RCQ_DESC_CNT - 1)) ? \ | |
379 | ((x) + 2) : ((x) + 1) | |
380 | ||
523224a3 | 381 | #define BNX2X_DEF_SB_ID HC_SP_SB_ID |
e2513065 | 382 | |
523224a3 | 383 | #define BNX2X_SHMEM_MF_BLK_OFFSET 0x7e4 |
e2513065 MC |
384 | |
385 | #define BNX2X_SHMEM_ADDR(base, field) (base + \ | |
386 | offsetof(struct shmem_region, field)) | |
387 | ||
523224a3 DK |
388 | #define BNX2X_SHMEM2_ADDR(base, field) (base + \ |
389 | offsetof(struct shmem2_region, field)) | |
390 | ||
391 | #define BNX2X_SHMEM2_HAS(base, field) \ | |
392 | ((base) && \ | |
393 | (CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \ | |
394 | offsetof(struct shmem2_region, field))) | |
395 | ||
4aacb7af MC |
396 | #define BNX2X_MF_CFG_ADDR(base, field) \ |
397 | ((base) + offsetof(struct mf_cfg, field)) | |
398 | ||
e1928c86 MC |
399 | #ifndef ETH_MAX_RX_CLIENTS_E2 |
400 | #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H | |
401 | #endif | |
402 | ||
e2513065 | 403 | #define CNIC_FUNC(cp) ((cp)->func) |
e2513065 | 404 | |
5e65789f MC |
405 | #define BNX2X_HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
406 | (BP_VN(bp) << 17) | (x)) | |
ceb7e1c7 MC |
407 | |
408 | #define BNX2X_SW_CID(x) (x & 0x1ffff) | |
409 | ||
104a43ed MC |
410 | #define BNX2X_CL_QZONE_ID(bp, cli) \ |
411 | (BNX2X_CHIP_IS_E2_PLUS(bp) ? cli : \ | |
412 | cli + (BP_PORT(bp) * ETH_MAX_RX_CLIENTS_E1H)) | |
619c5cb6 VZ |
413 | |
414 | #ifndef MAX_STAT_COUNTER_ID | |
415 | #define MAX_STAT_COUNTER_ID \ | |
104a43ed MC |
416 | (CHIP_IS_E1H(bp) ? MAX_STAT_COUNTER_ID_E1H : \ |
417 | ((BNX2X_CHIP_IS_E2_PLUS(bp)) ? MAX_STAT_COUNTER_ID_E2 : \ | |
619c5cb6 VZ |
418 | MAX_STAT_COUNTER_ID_E1)) |
419 | #endif | |
523224a3 | 420 | |
104a43ed MC |
421 | #define CNIC_SUPPORTS_FCOE(cp) \ |
422 | (BNX2X_CHIP_IS_E2_PLUS(bp) && !NO_FCOE(bp)) | |
51a8f54d | 423 | |
dcc7e3a6 MC |
424 | #define CNIC_RAMROD_TMO (HZ / 4) |
425 | ||
a4636960 MC |
426 | #endif |
427 |