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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 106{
107 dmadesc_set_length_status(priv, d, val);
108 dmadesc_set_addr(priv, d, addr);
109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
1c1008c7
FF		 200};
201
202static const u8 bcmgenet_dma_regs_v3plus[] = {
203 [DMA_RING_CFG] = 0x00,
204 [DMA_CTRL] = 0x04,
205 [DMA_STATUS] = 0x08,
206 [DMA_SCB_BURST_SIZE] = 0x0C,
207 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 208 [DMA_PRIORITY_0] = 0x30,
209 [DMA_PRIORITY_1] = 0x34,
210 [DMA_PRIORITY_2] = 0x38,
1c1008c7
FF		 211};
212
213static const u8 bcmgenet_dma_regs_v2[] = {
214 [DMA_RING_CFG] = 0x00,
215 [DMA_CTRL] = 0x04,
216 [DMA_STATUS] = 0x08,
217 [DMA_SCB_BURST_SIZE] = 0x0C,
218 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 219 [DMA_PRIORITY_0] = 0x34,
220 [DMA_PRIORITY_1] = 0x38,
221 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 222};
223
224static const u8 bcmgenet_dma_regs_v1[] = {
225 [DMA_CTRL] = 0x00,
226 [DMA_STATUS] = 0x04,
227 [DMA_SCB_BURST_SIZE] = 0x0C,
228 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 229 [DMA_PRIORITY_0] = 0x34,
230 [DMA_PRIORITY_1] = 0x38,
231 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 232};
233
234/* Set at runtime once bcmgenet version is known */
235static const u8 *bcmgenet_dma_regs;
236
237static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
238{
239 return netdev_priv(dev_get_drvdata(dev));
240}
241
242static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 243 enum dma_reg r)
1c1008c7
FF		 244{
245 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
246 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
247}
248
249static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
250 u32 val, enum dma_reg r)
251{
252 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
253 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
254}
255
256static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 257 enum dma_reg r)
1c1008c7
FF		 258{
259 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
260 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
261}
262
263static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
264 u32 val, enum dma_reg r)
265{
266 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
267 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
268}
269
270/* RDMA/TDMA ring registers and accessors
271 * we merge the common fields and just prefix with T/D the registers
272 * having different meaning depending on the direction
273 */
274enum dma_ring_reg {
275 TDMA_READ_PTR = 0,
276 RDMA_WRITE_PTR = TDMA_READ_PTR,
277 TDMA_READ_PTR_HI,
278 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
279 TDMA_CONS_INDEX,
280 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
281 TDMA_PROD_INDEX,
282 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
283 DMA_RING_BUF_SIZE,
284 DMA_START_ADDR,
285 DMA_START_ADDR_HI,
286 DMA_END_ADDR,
287 DMA_END_ADDR_HI,
288 DMA_MBUF_DONE_THRESH,
289 TDMA_FLOW_PERIOD,
290 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
291 TDMA_WRITE_PTR,
292 RDMA_READ_PTR = TDMA_WRITE_PTR,
293 TDMA_WRITE_PTR_HI,
294 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
295};
296
297/* GENET v4 supports 40-bits pointer addressing
298 * for obvious reasons the LO and HI word parts
299 * are contiguous, but this offsets the other
300 * registers.
301 */
302static const u8 genet_dma_ring_regs_v4[] = {
303 [TDMA_READ_PTR] = 0x00,
304 [TDMA_READ_PTR_HI] = 0x04,
305 [TDMA_CONS_INDEX] = 0x08,
306 [TDMA_PROD_INDEX] = 0x0C,
307 [DMA_RING_BUF_SIZE] = 0x10,
308 [DMA_START_ADDR] = 0x14,
309 [DMA_START_ADDR_HI] = 0x18,
310 [DMA_END_ADDR] = 0x1C,
311 [DMA_END_ADDR_HI] = 0x20,
312 [DMA_MBUF_DONE_THRESH] = 0x24,
313 [TDMA_FLOW_PERIOD] = 0x28,
314 [TDMA_WRITE_PTR] = 0x2C,
315 [TDMA_WRITE_PTR_HI] = 0x30,
316};
317
318static const u8 genet_dma_ring_regs_v123[] = {
319 [TDMA_READ_PTR] = 0x00,
320 [TDMA_CONS_INDEX] = 0x04,
321 [TDMA_PROD_INDEX] = 0x08,
322 [DMA_RING_BUF_SIZE] = 0x0C,
323 [DMA_START_ADDR] = 0x10,
324 [DMA_END_ADDR] = 0x14,
325 [DMA_MBUF_DONE_THRESH] = 0x18,
326 [TDMA_FLOW_PERIOD] = 0x1C,
327 [TDMA_WRITE_PTR] = 0x20,
328};
329
330/* Set at runtime once GENET version is known */
331static const u8 *genet_dma_ring_regs;
332
333static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 334 unsigned int ring,
335 enum dma_ring_reg r)
1c1008c7
FF		 336{
337 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
338 (DMA_RING_SIZE * ring) +
339 genet_dma_ring_regs[r]);
340}
341
342static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 343 unsigned int ring, u32 val,
344 enum dma_ring_reg r)
1c1008c7
FF		 345{
346 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
347 (DMA_RING_SIZE * ring) +
348 genet_dma_ring_regs[r]);
349}
350
351static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 352 unsigned int ring,
353 enum dma_ring_reg r)
1c1008c7
FF		 354{
355 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
356 (DMA_RING_SIZE * ring) +
357 genet_dma_ring_regs[r]);
358}
359
360static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 361 unsigned int ring, u32 val,
362 enum dma_ring_reg r)
1c1008c7
FF		 363{
364 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
365 (DMA_RING_SIZE * ring) +
366 genet_dma_ring_regs[r]);
367}
368
369static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 370 struct ethtool_cmd *cmd)
1c1008c7
FF		 371{
372 struct bcmgenet_priv *priv = netdev_priv(dev);
373
374 if (!netif_running(dev))
375 return -EINVAL;
376
377 if (!priv->phydev)
378 return -ENODEV;
379
380 return phy_ethtool_gset(priv->phydev, cmd);
381}
382
383static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 384 struct ethtool_cmd *cmd)
1c1008c7
FF		 385{
386 struct bcmgenet_priv *priv = netdev_priv(dev);
387
388 if (!netif_running(dev))
389 return -EINVAL;
390
391 if (!priv->phydev)
392 return -ENODEV;
393
394 return phy_ethtool_sset(priv->phydev, cmd);
395}
396
397static int bcmgenet_set_rx_csum(struct net_device *dev,
398 netdev_features_t wanted)
399{
400 struct bcmgenet_priv *priv = netdev_priv(dev);
401 u32 rbuf_chk_ctrl;
402 bool rx_csum_en;
403
404 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
405
406 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
407
408 /* enable rx checksumming */
409 if (rx_csum_en)
410 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
411 else
412 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
413 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 414
415 /* If UniMAC forwards CRC, we need to skip over it to get
416 * a valid CHK bit to be set in the per-packet status word
417 */
418 if (rx_csum_en && priv->crc_fwd_en)
419 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
420 else
421 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
422
1c1008c7
FF		 423 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
424
425 return 0;
426}
427
428static int bcmgenet_set_tx_csum(struct net_device *dev,
429 netdev_features_t wanted)
430{
431 struct bcmgenet_priv *priv = netdev_priv(dev);
432 bool desc_64b_en;
433 u32 tbuf_ctrl, rbuf_ctrl;
434
435 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
436 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
437
438 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
439
440 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
441 if (desc_64b_en) {
442 tbuf_ctrl |= RBUF_64B_EN;
443 rbuf_ctrl |= RBUF_64B_EN;
444 } else {
445 tbuf_ctrl &= ~RBUF_64B_EN;
446 rbuf_ctrl &= ~RBUF_64B_EN;
447 }
448 priv->desc_64b_en = desc_64b_en;
449
450 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
451 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
452
453 return 0;
454}
455
456static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 457 netdev_features_t features)
1c1008c7
FF		 458{
459 netdev_features_t changed = features ^ dev->features;
460 netdev_features_t wanted = dev->wanted_features;
461 int ret = 0;
462
463 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
464 ret = bcmgenet_set_tx_csum(dev, wanted);
465 if (changed & (NETIF_F_RXCSUM))
466 ret = bcmgenet_set_rx_csum(dev, wanted);
467
468 return ret;
469}
470
471static u32 bcmgenet_get_msglevel(struct net_device *dev)
472{
473 struct bcmgenet_priv *priv = netdev_priv(dev);
474
475 return priv->msg_enable;
476}
477
478static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
479{
480 struct bcmgenet_priv *priv = netdev_priv(dev);
481
482 priv->msg_enable = level;
483}
484
485/* standard ethtool support functions. */
486enum bcmgenet_stat_type {
487 BCMGENET_STAT_NETDEV = -1,
488 BCMGENET_STAT_MIB_RX,
489 BCMGENET_STAT_MIB_TX,
490 BCMGENET_STAT_RUNT,
491 BCMGENET_STAT_MISC,
f62ba9c1 492 BCMGENET_STAT_SOFT,
1c1008c7
FF		 493};
494
495struct bcmgenet_stats {
496 char stat_string[ETH_GSTRING_LEN];
497 int stat_sizeof;
498 int stat_offset;
499 enum bcmgenet_stat_type type;
500 /* reg offset from UMAC base for misc counters */
501 u16 reg_offset;
502};
503
504#define STAT_NETDEV(m) { \
505 .stat_string = __stringify(m), \
506 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
507 .stat_offset = offsetof(struct net_device_stats, m), \
508 .type = BCMGENET_STAT_NETDEV, \
509}
510
511#define STAT_GENET_MIB(str, m, _type) { \
512 .stat_string = str, \
513 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
514 .stat_offset = offsetof(struct bcmgenet_priv, m), \
515 .type = _type, \
516}
517
518#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
519#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
520#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 521#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 522
523#define STAT_GENET_MISC(str, m, offset) { \
524 .stat_string = str, \
525 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
526 .stat_offset = offsetof(struct bcmgenet_priv, m), \
527 .type = BCMGENET_STAT_MISC, \
528 .reg_offset = offset, \
529}
530
531
532/* There is a 0xC gap between the end of RX and beginning of TX stats and then
533 * between the end of TX stats and the beginning of the RX RUNT
534 */
535#define BCMGENET_STAT_OFFSET 0xc
536
537/* Hardware counters must be kept in sync because the order/offset
538 * is important here (order in structure declaration = order in hardware)
539 */
540static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
541 /* general stats */
542 STAT_NETDEV(rx_packets),
543 STAT_NETDEV(tx_packets),
544 STAT_NETDEV(rx_bytes),
545 STAT_NETDEV(tx_bytes),
546 STAT_NETDEV(rx_errors),
547 STAT_NETDEV(tx_errors),
548 STAT_NETDEV(rx_dropped),
549 STAT_NETDEV(tx_dropped),
550 STAT_NETDEV(multicast),
551 /* UniMAC RSV counters */
552 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
553 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
554 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
555 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
556 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
557 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
558 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
559 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
560 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
561 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
562 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
563 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
564 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
565 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
566 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
567 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
568 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
569 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
570 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
571 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
572 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
573 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
574 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
575 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
576 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
577 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
578 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
579 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
580 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
581 /* UniMAC TSV counters */
582 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
583 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
584 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
585 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
586 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
587 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
588 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
589 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
590 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
591 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
592 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
593 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
594 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
595 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
596 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
597 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
598 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
599 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
600 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
601 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
602 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
603 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
604 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
605 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
606 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
607 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
608 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
609 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
610 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
611 /* UniMAC RUNT counters */
612 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
613 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
614 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
615 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
616 /* Misc UniMAC counters */
617 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
618 UMAC_RBUF_OVFL_CNT),
619 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
620 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 621 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
622 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
623 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 624};
625
626#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
627
628static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 629 struct ethtool_drvinfo *info)
1c1008c7
FF		 630{
631 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
632 strlcpy(info->version, "v2.0", sizeof(info->version));
633 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 634}
635
636static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
637{
638 switch (string_set) {
639 case ETH_SS_STATS:
640 return BCMGENET_STATS_LEN;
641 default:
642 return -EOPNOTSUPP;
643 }
644}
645
c91b7f66
FF		 646static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
647 u8 *data)
1c1008c7
FF		 648{
649 int i;
650
651 switch (stringset) {
652 case ETH_SS_STATS:
653 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
654 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 655 bcmgenet_gstrings_stats[i].stat_string,
656 ETH_GSTRING_LEN);
1c1008c7
FF		 657 }
658 break;
659 }
660}
661
662static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
663{
664 int i, j = 0;
665
666 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
667 const struct bcmgenet_stats *s;
668 u8 offset = 0;
669 u32 val = 0;
670 char *p;
671
672 s = &bcmgenet_gstrings_stats[i];
673 switch (s->type) {
674 case BCMGENET_STAT_NETDEV:
f62ba9c1 675 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 676 continue;
677 case BCMGENET_STAT_MIB_RX:
678 case BCMGENET_STAT_MIB_TX:
679 case BCMGENET_STAT_RUNT:
680 if (s->type != BCMGENET_STAT_MIB_RX)
681 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 682 val = bcmgenet_umac_readl(priv,
683 UMAC_MIB_START + j + offset);
1c1008c7
FF		 684 break;
685 case BCMGENET_STAT_MISC:
686 val = bcmgenet_umac_readl(priv, s->reg_offset);
687 /* clear if overflowed */
688 if (val == ~0)
689 bcmgenet_umac_writel(priv, 0, s->reg_offset);
690 break;
691 }
692
693 j += s->stat_sizeof;
694 p = (char *)priv + s->stat_offset;
695 *(u32 *)p = val;
696 }
697}
698
699static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 700 struct ethtool_stats *stats,
701 u64 *data)
1c1008c7
FF		 702{
703 struct bcmgenet_priv *priv = netdev_priv(dev);
704 int i;
705
706 if (netif_running(dev))
707 bcmgenet_update_mib_counters(priv);
708
709 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
710 const struct bcmgenet_stats *s;
711 char *p;
712
713 s = &bcmgenet_gstrings_stats[i];
714 if (s->type == BCMGENET_STAT_NETDEV)
715 p = (char *)&dev->stats;
716 else
717 p = (char *)priv;
718 p += s->stat_offset;
719 data[i] = *(u32 *)p;
720 }
721}
722
6ef398ea
FF		 723static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
724{
725 struct bcmgenet_priv *priv = netdev_priv(dev);
726 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
727 u32 reg;
728
729 if (enable && !priv->clk_eee_enabled) {
730 clk_prepare_enable(priv->clk_eee);
731 priv->clk_eee_enabled = true;
732 }
733
734 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
735 if (enable)
736 reg |= EEE_EN;
737 else
738 reg &= ~EEE_EN;
739 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
740
741 /* Enable EEE and switch to a 27Mhz clock automatically */
742 reg = __raw_readl(priv->base + off);
743 if (enable)
744 reg |= TBUF_EEE_EN | TBUF_PM_EN;
745 else
746 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
747 __raw_writel(reg, priv->base + off);
748
749 /* Do the same for thing for RBUF */
750 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
751 if (enable)
752 reg |= RBUF_EEE_EN | RBUF_PM_EN;
753 else
754 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
755 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
756
757 if (!enable && priv->clk_eee_enabled) {
758 clk_disable_unprepare(priv->clk_eee);
759 priv->clk_eee_enabled = false;
760 }
761
762 priv->eee.eee_enabled = enable;
763 priv->eee.eee_active = enable;
764}
765
766static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
767{
768 struct bcmgenet_priv *priv = netdev_priv(dev);
769 struct ethtool_eee *p = &priv->eee;
770
771 if (GENET_IS_V1(priv))
772 return -EOPNOTSUPP;
773
774 e->eee_enabled = p->eee_enabled;
775 e->eee_active = p->eee_active;
776 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
777
778 return phy_ethtool_get_eee(priv->phydev, e);
779}
780
781static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
782{
783 struct bcmgenet_priv *priv = netdev_priv(dev);
784 struct ethtool_eee *p = &priv->eee;
785 int ret = 0;
786
787 if (GENET_IS_V1(priv))
788 return -EOPNOTSUPP;
789
790 p->eee_enabled = e->eee_enabled;
791
792 if (!p->eee_enabled) {
793 bcmgenet_eee_enable_set(dev, false);
794 } else {
795 ret = phy_init_eee(priv->phydev, 0);
796 if (ret) {
797 netif_err(priv, hw, dev, "EEE initialization failed\n");
798 return ret;
799 }
800
801 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
802 bcmgenet_eee_enable_set(dev, true);
803 }
804
805 return phy_ethtool_set_eee(priv->phydev, e);
806}
807
6b0c5406
FF		 808static int bcmgenet_nway_reset(struct net_device *dev)
809{
810 struct bcmgenet_priv *priv = netdev_priv(dev);
811
812 return genphy_restart_aneg(priv->phydev);
813}
814
1c1008c7
FF		 815/* standard ethtool support functions. */
816static struct ethtool_ops bcmgenet_ethtool_ops = {
817 .get_strings = bcmgenet_get_strings,
818 .get_sset_count = bcmgenet_get_sset_count,
819 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
820 .get_settings = bcmgenet_get_settings,
821 .set_settings = bcmgenet_set_settings,
822 .get_drvinfo = bcmgenet_get_drvinfo,
823 .get_link = ethtool_op_get_link,
824 .get_msglevel = bcmgenet_get_msglevel,
825 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 826 .get_wol = bcmgenet_get_wol,
827 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 828 .get_eee = bcmgenet_get_eee,
829 .set_eee = bcmgenet_set_eee,
6b0c5406 830 .nway_reset = bcmgenet_nway_reset,
1c1008c7
FF		 831};
832
833/* Power down the unimac, based on mode. */
834static void bcmgenet_power_down(struct bcmgenet_priv *priv,
835 enum bcmgenet_power_mode mode)
836{
837 u32 reg;
838
839 switch (mode) {
840 case GENET_POWER_CABLE_SENSE:
80d8e96d 841 phy_detach(priv->phydev);
1c1008c7
FF		 842 break;
843
c3ae64ae
FF		 844 case GENET_POWER_WOL_MAGIC:
845 bcmgenet_wol_power_down_cfg(priv, mode);
846 break;
847
1c1008c7
FF		 848 case GENET_POWER_PASSIVE:
849 /* Power down LED */
1c1008c7
FF		 850 if (priv->hw_params->flags & GENET_HAS_EXT) {
851 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
852 reg |= (EXT_PWR_DOWN_PHY |
853 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
854 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
855 }
856 break;
857 default:
858 break;
859 }
860}
861
862static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 863 enum bcmgenet_power_mode mode)
1c1008c7
FF		 864{
865 u32 reg;
866
867 if (!(priv->hw_params->flags & GENET_HAS_EXT))
868 return;
869
870 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
871
872 switch (mode) {
873 case GENET_POWER_PASSIVE:
874 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
875 EXT_PWR_DOWN_BIAS);
876 /* fallthrough */
877 case GENET_POWER_CABLE_SENSE:
878 /* enable APD */
879 reg |= EXT_PWR_DN_EN_LD;
880 break;
c3ae64ae
FF		 881 case GENET_POWER_WOL_MAGIC:
882 bcmgenet_wol_power_up_cfg(priv, mode);
883 return;
1c1008c7
FF		 884 default:
885 break;
886 }
887
888 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
cc013fb4
FF		 889
890 if (mode == GENET_POWER_PASSIVE)
891 bcmgenet_mii_reset(priv->dev);
1c1008c7
FF		 892}
893
894/* ioctl handle special commands that are not present in ethtool. */
895static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
896{
897 struct bcmgenet_priv *priv = netdev_priv(dev);
898 int val = 0;
899
900 if (!netif_running(dev))
901 return -EINVAL;
902
903 switch (cmd) {
904 case SIOCGMIIPHY:
905 case SIOCGMIIREG:
906 case SIOCSMIIREG:
907 if (!priv->phydev)
908 val = -ENODEV;
909 else
910 val = phy_mii_ioctl(priv->phydev, rq, cmd);
911 break;
912
913 default:
914 val = -EINVAL;
915 break;
916 }
917
918 return val;
919}
920
921static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
922 struct bcmgenet_tx_ring *ring)
923{
924 struct enet_cb *tx_cb_ptr;
925
926 tx_cb_ptr = ring->cbs;
927 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 928
1c1008c7
FF		 929 /* Advancing local write pointer */
930 if (ring->write_ptr == ring->end_ptr)
931 ring->write_ptr = ring->cb_ptr;
932 else
933 ring->write_ptr++;
934
935 return tx_cb_ptr;
936}
937
938/* Simple helper to free a control block's resources */
939static void bcmgenet_free_cb(struct enet_cb *cb)
940{
941 dev_kfree_skb_any(cb->skb);
942 cb->skb = NULL;
943 dma_unmap_addr_set(cb, dma_addr, 0);
944}
945
946static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
947 struct bcmgenet_tx_ring *ring)
948{
949 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 950 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
951 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 952}
953
954static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
955 struct bcmgenet_tx_ring *ring)
956{
957 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 958 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
959 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 960}
961
962static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
c91b7f66 963 struct bcmgenet_tx_ring *ring)
1c1008c7 964{
c91b7f66
FF		 965 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
966 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 967 priv->int1_mask &= ~(1 << ring->index);
968}
969
970static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
971 struct bcmgenet_tx_ring *ring)
972{
c91b7f66
FF		 973 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
974 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 975 priv->int1_mask |= (1 << ring->index);
976}
977
978/* Unlocked version of the reclaim routine */
4092e6ac
JS		 979static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
980 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 981{
982 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 983 struct enet_cb *tx_cb_ptr;
b2cde2cc 984 struct netdev_queue *txq;
4092e6ac 985 unsigned int pkts_compl = 0;
1c1008c7 986 unsigned int c_index;
66d06757
PG		 987 unsigned int txbds_ready;
988 unsigned int txbds_processed = 0;
1c1008c7 989
7fc527f9 990 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 991 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 992 c_index &= DMA_C_INDEX_MASK;
1c1008c7 993
66d06757
PG		 994 if (likely(c_index >= ring->c_index))
995 txbds_ready = c_index - ring->c_index;
1c1008c7 996 else
66d06757 997 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 998
999 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1000 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1001 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1002
1003 /* Reclaim transmitted buffers */
66d06757
PG		 1004 while (txbds_processed < txbds_ready) {
1005 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1006 if (tx_cb_ptr->skb) {
4092e6ac 1007 pkts_compl++;
66d06757 1008 dev->stats.tx_packets++;
1c1008c7
FF		 1009 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1010 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1011 dma_unmap_addr(tx_cb_ptr, dma_addr),
1012 tx_cb_ptr->skb->len,
1013 DMA_TO_DEVICE);
1c1008c7
FF		 1014 bcmgenet_free_cb(tx_cb_ptr);
1015 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1016 dev->stats.tx_bytes +=
1017 dma_unmap_len(tx_cb_ptr, dma_len);
1018 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1019 dma_unmap_addr(tx_cb_ptr, dma_addr),
1020 dma_unmap_len(tx_cb_ptr, dma_len),
1021 DMA_TO_DEVICE);
1c1008c7
FF		 1022 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1023 }
1c1008c7 1024
66d06757
PG		 1025 txbds_processed++;
1026 if (likely(ring->clean_ptr < ring->end_ptr))
1027 ring->clean_ptr++;
1028 else
1029 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1030 }
1031
66d06757
PG		 1032 ring->free_bds += txbds_processed;
1033 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1034
4092e6ac 1035 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
66d06757 1036 txq = netdev_get_tx_queue(dev, ring->queue);
4092e6ac
JS		 1037 if (netif_tx_queue_stopped(txq))
1038 netif_tx_wake_queue(txq);
1039 }
1c1008c7 1040
4092e6ac 1041 return pkts_compl;
1c1008c7
FF		 1042}
1043
4092e6ac 1044static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1045 struct bcmgenet_tx_ring *ring)
1c1008c7 1046{
4092e6ac 1047 unsigned int released;
1c1008c7
FF		 1048 unsigned long flags;
1049
1050 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1051 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1052 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1053
1054 return released;
1055}
1056
1057static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1058{
1059 struct bcmgenet_tx_ring *ring =
1060 container_of(napi, struct bcmgenet_tx_ring, napi);
1061 unsigned int work_done = 0;
1062
1063 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1064
1065 if (work_done == 0) {
1066 napi_complete(napi);
1067 ring->int_enable(ring->priv, ring);
1068
1069 return 0;
1070 }
1071
1072 return budget;
1c1008c7
FF		 1073}
1074
1075static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1076{
1077 struct bcmgenet_priv *priv = netdev_priv(dev);
1078 int i;
1079
1080 if (netif_is_multiqueue(dev)) {
1081 for (i = 0; i < priv->hw_params->tx_queues; i++)
1082 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1083 }
1084
1085 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1086}
1087
1088/* Transmits a single SKB (either head of a fragment or a single SKB)
1089 * caller must hold priv->lock
1090 */
1091static int bcmgenet_xmit_single(struct net_device *dev,
1092 struct sk_buff *skb,
1093 u16 dma_desc_flags,
1094 struct bcmgenet_tx_ring *ring)
1095{
1096 struct bcmgenet_priv *priv = netdev_priv(dev);
1097 struct device *kdev = &priv->pdev->dev;
1098 struct enet_cb *tx_cb_ptr;
1099 unsigned int skb_len;
1100 dma_addr_t mapping;
1101 u32 length_status;
1102 int ret;
1103
1104 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1105
1106 if (unlikely(!tx_cb_ptr))
1107 BUG();
1108
1109 tx_cb_ptr->skb = skb;
1110
1111 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1112
1113 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1114 ret = dma_mapping_error(kdev, mapping);
1115 if (ret) {
44c8bc3c 1116 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1117 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1118 dev_kfree_skb(skb);
1119 return ret;
1120 }
1121
1122 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1123 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1124 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1125 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1126 DMA_TX_APPEND_CRC;
1127
1128 if (skb->ip_summed == CHECKSUM_PARTIAL)
1129 length_status |= DMA_TX_DO_CSUM;
1130
1131 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1132
1133 /* Decrement total BD count and advance our write pointer */
1134 ring->free_bds -= 1;
1135 ring->prod_index += 1;
1136 ring->prod_index &= DMA_P_INDEX_MASK;
1137
1138 return 0;
1139}
1140
7fc527f9 1141/* Transmit a SKB fragment */
1c1008c7 1142static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1143 skb_frag_t *frag,
1144 u16 dma_desc_flags,
1145 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1146{
1147 struct bcmgenet_priv *priv = netdev_priv(dev);
1148 struct device *kdev = &priv->pdev->dev;
1149 struct enet_cb *tx_cb_ptr;
1150 dma_addr_t mapping;
1151 int ret;
1152
1153 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1154
1155 if (unlikely(!tx_cb_ptr))
1156 BUG();
1157 tx_cb_ptr->skb = NULL;
1158
1159 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1160 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1161 ret = dma_mapping_error(kdev, mapping);
1162 if (ret) {
44c8bc3c 1163 priv->mib.tx_dma_failed++;
1c1008c7 1164 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1165 __func__);
1c1008c7
FF		 1166 return ret;
1167 }
1168
1169 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1170 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1171
1172 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1173 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1174 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7
FF		 1175
1176
1177 ring->free_bds -= 1;
1178 ring->prod_index += 1;
1179 ring->prod_index &= DMA_P_INDEX_MASK;
1180
1181 return 0;
1182}
1183
1184/* Reallocate the SKB to put enough headroom in front of it and insert
1185 * the transmit checksum offsets in the descriptors
1186 */
bc23333b
PG		 1187static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1188 struct sk_buff *skb)
1c1008c7
FF		 1189{
1190 struct status_64 *status = NULL;
1191 struct sk_buff *new_skb;
1192 u16 offset;
1193 u8 ip_proto;
1194 u16 ip_ver;
1195 u32 tx_csum_info;
1196
1197 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1198 /* If 64 byte status block enabled, must make sure skb has
1199 * enough headroom for us to insert 64B status block.
1200 */
1201 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1202 dev_kfree_skb(skb);
1203 if (!new_skb) {
1204 dev->stats.tx_errors++;
1205 dev->stats.tx_dropped++;
bc23333b 1206 return NULL;
1c1008c7
FF		 1207 }
1208 skb = new_skb;
1209 }
1210
1211 skb_push(skb, sizeof(*status));
1212 status = (struct status_64 *)skb->data;
1213
1214 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1215 ip_ver = htons(skb->protocol);
1216 switch (ip_ver) {
1217 case ETH_P_IP:
1218 ip_proto = ip_hdr(skb)->protocol;
1219 break;
1220 case ETH_P_IPV6:
1221 ip_proto = ipv6_hdr(skb)->nexthdr;
1222 break;
1223 default:
bc23333b 1224 return skb;
1c1008c7
FF		 1225 }
1226
1227 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1228 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1229 (offset + skb->csum_offset);
1230
1231 /* Set the length valid bit for TCP and UDP and just set
1232 * the special UDP flag for IPv4, else just set to 0.
1233 */
1234 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1235 tx_csum_info |= STATUS_TX_CSUM_LV;
1236 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1237 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1238 } else {
1c1008c7 1239 tx_csum_info = 0;
8900ea57 1240 }
1c1008c7
FF		 1241
1242 status->tx_csum_info = tx_csum_info;
1243 }
1244
bc23333b 1245 return skb;
1c1008c7
FF		 1246}
1247
1248static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1249{
1250 struct bcmgenet_priv *priv = netdev_priv(dev);
1251 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1252 struct netdev_queue *txq;
1c1008c7
FF		 1253 unsigned long flags = 0;
1254 int nr_frags, index;
1255 u16 dma_desc_flags;
1256 int ret;
1257 int i;
1258
1259 index = skb_get_queue_mapping(skb);
1260 /* Mapping strategy:
1261 * queue_mapping = 0, unclassified, packet xmited through ring16
1262 * queue_mapping = 1, goes to ring 0. (highest priority queue
1263 * queue_mapping = 2, goes to ring 1.
1264 * queue_mapping = 3, goes to ring 2.
1265 * queue_mapping = 4, goes to ring 3.
1266 */
1267 if (index == 0)
1268 index = DESC_INDEX;
1269 else
1270 index -= 1;
1271
1c1008c7
FF		 1272 nr_frags = skb_shinfo(skb)->nr_frags;
1273 ring = &priv->tx_rings[index];
b2cde2cc 1274 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1275
1276 spin_lock_irqsave(&ring->lock, flags);
1277 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1278 netif_tx_stop_queue(txq);
1c1008c7 1279 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1280 __func__, index, ring->queue);
1c1008c7
FF		 1281 ret = NETDEV_TX_BUSY;
1282 goto out;
1283 }
1284
474ea9ca
FF		 1285 if (skb_padto(skb, ETH_ZLEN)) {
1286 ret = NETDEV_TX_OK;
1287 goto out;
1288 }
1289
1c1008c7
FF		 1290 /* set the SKB transmit checksum */
1291 if (priv->desc_64b_en) {
bc23333b
PG		 1292 skb = bcmgenet_put_tx_csum(dev, skb);
1293 if (!skb) {
1c1008c7
FF		 1294 ret = NETDEV_TX_OK;
1295 goto out;
1296 }
1297 }
1298
1299 dma_desc_flags = DMA_SOP;
1300 if (nr_frags == 0)
1301 dma_desc_flags |= DMA_EOP;
1302
1303 /* Transmit single SKB or head of fragment list */
1304 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1305 if (ret) {
1306 ret = NETDEV_TX_OK;
1307 goto out;
1308 }
1309
1310 /* xmit fragment */
1311 for (i = 0; i < nr_frags; i++) {
1312 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1313 &skb_shinfo(skb)->frags[i],
1314 (i == nr_frags - 1) ? DMA_EOP : 0,
1315 ring);
1c1008c7
FF		 1316 if (ret) {
1317 ret = NETDEV_TX_OK;
1318 goto out;
1319 }
1320 }
1321
d03825fb
FF		 1322 skb_tx_timestamp(skb);
1323
1c1008c7
FF		 1324 /* we kept a software copy of how much we should advance the TDMA
1325 * producer index, now write it down to the hardware
1326 */
1327 bcmgenet_tdma_ring_writel(priv, ring->index,
c91b7f66 1328 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7 1329
4092e6ac 1330 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1331 netif_tx_stop_queue(txq);
1c1008c7
FF		 1332
1333out:
1334 spin_unlock_irqrestore(&ring->lock, flags);
1335
1336 return ret;
1337}
1338
1339
c91b7f66 1340static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1c1008c7
FF		 1341{
1342 struct device *kdev = &priv->pdev->dev;
1343 struct sk_buff *skb;
1344 dma_addr_t mapping;
1345 int ret;
1346
c91b7f66 1347 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1c1008c7
FF		 1348 if (!skb)
1349 return -ENOMEM;
1350
1351 /* a caller did not release this control block */
1352 WARN_ON(cb->skb != NULL);
1353 cb->skb = skb;
1354 mapping = dma_map_single(kdev, skb->data,
c91b7f66 1355 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1356 ret = dma_mapping_error(kdev, mapping);
1357 if (ret) {
44c8bc3c 1358 priv->mib.rx_dma_failed++;
1c1008c7
FF		 1359 bcmgenet_free_cb(cb);
1360 netif_err(priv, rx_err, priv->dev,
c91b7f66 1361 "%s DMA map failed\n", __func__);
1c1008c7
FF		 1362 return ret;
1363 }
1364
1365 dma_unmap_addr_set(cb, dma_addr, mapping);
1366 /* assign packet, prepare descriptor, and advance pointer */
1367
1368 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1369
1370 /* turn on the newly assigned BD for DMA to use */
1371 priv->rx_bd_assign_index++;
1372 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1373
1374 priv->rx_bd_assign_ptr = priv->rx_bds +
1375 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1376
1377 return 0;
1378}
1379
1380/* bcmgenet_desc_rx - descriptor based rx process.
1381 * this could be called from bottom half, or from NAPI polling method.
1382 */
1383static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1384 unsigned int budget)
1385{
1386 struct net_device *dev = priv->dev;
1387 struct enet_cb *cb;
1388 struct sk_buff *skb;
1389 u32 dma_length_status;
1390 unsigned long dma_flag;
1391 int len, err;
1392 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1393 unsigned int p_index;
1394 unsigned int chksum_ok = 0;
1395
c91b7f66 1396 p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX);
1c1008c7
FF		 1397 p_index &= DMA_P_INDEX_MASK;
1398
1399 if (p_index < priv->rx_c_index)
1400 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1401 priv->rx_c_index + p_index;
1402 else
1403 rxpkttoprocess = p_index - priv->rx_c_index;
1404
1405 netif_dbg(priv, rx_status, dev,
c91b7f66 1406 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1407
1408 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1409 (rxpktprocessed < budget)) {
b629be5c
FF		 1410 cb = &priv->rx_cbs[priv->rx_read_ptr];
1411 skb = cb->skb;
1412
b629be5c
FF		 1413 /* We do not have a backing SKB, so we do not have a
1414 * corresponding DMA mapping for this incoming packet since
1415 * bcmgenet_rx_refill always either has both skb and mapping or
1416 * none.
1417 */
1418 if (unlikely(!skb)) {
1419 dev->stats.rx_dropped++;
1420 dev->stats.rx_errors++;
1421 goto refill;
1422 }
1423
1c1008c7
FF		 1424 /* Unmap the packet contents such that we can use the
1425 * RSV from the 64 bytes descriptor when enabled and save
1426 * a 32-bits register read
1427 */
1c1008c7 1428 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
c91b7f66 1429 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1430
1431 if (!priv->desc_64b_en) {
c91b7f66
FF		 1432 dma_length_status =
1433 dmadesc_get_length_status(priv,
1434 priv->rx_bds +
1435 (priv->rx_read_ptr *
1436 DMA_DESC_SIZE));
1c1008c7
FF		 1437 } else {
1438 struct status_64 *status;
164d4f20 1439
1c1008c7
FF		 1440 status = (struct status_64 *)skb->data;
1441 dma_length_status = status->length_status;
1442 }
1443
1444 /* DMA flags and length are still valid no matter how
1445 * we got the Receive Status Vector (64B RSB or register)
1446 */
1447 dma_flag = dma_length_status & 0xffff;
1448 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1449
1450 netif_dbg(priv, rx_status, dev,
c91b7f66
FF		 1451 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1452 __func__, p_index, priv->rx_c_index,
1453 priv->rx_read_ptr, dma_length_status);
1c1008c7 1454
1c1008c7
FF		 1455 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1456 netif_err(priv, rx_status, dev,
c91b7f66 1457 "dropping fragmented packet!\n");
1c1008c7
FF		 1458 dev->stats.rx_dropped++;
1459 dev->stats.rx_errors++;
1460 dev_kfree_skb_any(cb->skb);
1461 cb->skb = NULL;
1462 goto refill;
1463 }
1464 /* report errors */
1465 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1466 DMA_RX_OV |
1467 DMA_RX_NO |
1468 DMA_RX_LG |
1469 DMA_RX_RXER))) {
1470 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1471 (unsigned int)dma_flag);
1c1008c7
FF		 1472 if (dma_flag & DMA_RX_CRC_ERROR)
1473 dev->stats.rx_crc_errors++;
1474 if (dma_flag & DMA_RX_OV)
1475 dev->stats.rx_over_errors++;
1476 if (dma_flag & DMA_RX_NO)
1477 dev->stats.rx_frame_errors++;
1478 if (dma_flag & DMA_RX_LG)
1479 dev->stats.rx_length_errors++;
1480 dev->stats.rx_dropped++;
1481 dev->stats.rx_errors++;
1482
1483 /* discard the packet and advance consumer index.*/
1484 dev_kfree_skb_any(cb->skb);
1485 cb->skb = NULL;
1486 goto refill;
1487 } /* error packet */
1488
1489 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1490 priv->desc_rxchk_en;
1c1008c7
FF		 1491
1492 skb_put(skb, len);
1493 if (priv->desc_64b_en) {
1494 skb_pull(skb, 64);
1495 len -= 64;
1496 }
1497
1498 if (likely(chksum_ok))
1499 skb->ip_summed = CHECKSUM_UNNECESSARY;
1500
1501 /* remove hardware 2bytes added for IP alignment */
1502 skb_pull(skb, 2);
1503 len -= 2;
1504
1505 if (priv->crc_fwd_en) {
1506 skb_trim(skb, len - ETH_FCS_LEN);
1507 len -= ETH_FCS_LEN;
1508 }
1509
1510 /*Finish setting up the received SKB and send it to the kernel*/
1511 skb->protocol = eth_type_trans(skb, priv->dev);
1512 dev->stats.rx_packets++;
1513 dev->stats.rx_bytes += len;
1514 if (dma_flag & DMA_RX_MULT)
1515 dev->stats.multicast++;
1516
1517 /* Notify kernel */
1518 napi_gro_receive(&priv->napi, skb);
1519 cb->skb = NULL;
1520 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1521
1522 /* refill RX path on the current control block */
1523refill:
1524 err = bcmgenet_rx_refill(priv, cb);
44c8bc3c
FF		 1525 if (err) {
1526 priv->mib.alloc_rx_buff_failed++;
1c1008c7 1527 netif_err(priv, rx_err, dev, "Rx refill failed\n");
44c8bc3c 1528 }
cf377d88
FF		 1529
1530 rxpktprocessed++;
1531 priv->rx_read_ptr++;
1532 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1c1008c7
FF		 1533 }
1534
1535 return rxpktprocessed;
1536}
1537
1538/* Assign skb to RX DMA descriptor. */
1539static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1540{
1541 struct enet_cb *cb;
1542 int ret = 0;
1543 int i;
1544
1545 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1546
1547 /* loop here for each buffer needing assign */
1548 for (i = 0; i < priv->num_rx_bds; i++) {
1549 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1550 if (cb->skb)
1551 continue;
1552
1c1008c7
FF		 1553 ret = bcmgenet_rx_refill(priv, cb);
1554 if (ret)
1555 break;
1c1008c7
FF		 1556 }
1557
1558 return ret;
1559}
1560
1561static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1562{
1563 struct enet_cb *cb;
1564 int i;
1565
1566 for (i = 0; i < priv->num_rx_bds; i++) {
1567 cb = &priv->rx_cbs[i];
1568
1569 if (dma_unmap_addr(cb, dma_addr)) {
1570 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1571 dma_unmap_addr(cb, dma_addr),
1572 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1573 dma_unmap_addr_set(cb, dma_addr, 0);
1574 }
1575
1576 if (cb->skb)
1577 bcmgenet_free_cb(cb);
1578 }
1579}
1580
c91b7f66 1581static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1582{
1583 u32 reg;
1584
1585 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1586 if (enable)
1587 reg |= mask;
1588 else
1589 reg &= ~mask;
1590 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1591
1592 /* UniMAC stops on a packet boundary, wait for a full-size packet
1593 * to be processed
1594 */
1595 if (enable == 0)
1596 usleep_range(1000, 2000);
1597}
1598
1c1008c7
FF		 1599static int reset_umac(struct bcmgenet_priv *priv)
1600{
1601 struct device *kdev = &priv->pdev->dev;
1602 unsigned int timeout = 0;
1603 u32 reg;
1604
1605 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1606 bcmgenet_rbuf_ctrl_set(priv, 0);
1607 udelay(10);
1608
1609 /* disable MAC while updating its registers */
1610 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1611
1612 /* issue soft reset, wait for it to complete */
1613 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1614 while (timeout++ < 1000) {
1615 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1616 if (!(reg & CMD_SW_RESET))
1617 return 0;
1618
1619 udelay(1);
1620 }
1621
1622 if (timeout == 1000) {
1623 dev_err(kdev,
7fc527f9 1624 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1625 return -ETIMEDOUT;
1626 }
1627
1628 return 0;
1629}
1630
909ff5ef
FF		 1631static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1632{
1633 /* Mask all interrupts.*/
1634 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1635 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1636 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1637 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1638 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1639 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1640}
1641
1c1008c7
FF		 1642static int init_umac(struct bcmgenet_priv *priv)
1643{
1644 struct device *kdev = &priv->pdev->dev;
1645 int ret;
1646 u32 reg, cpu_mask_clear;
4092e6ac 1647 int index;
1c1008c7
FF		 1648
1649 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1650
1651 ret = reset_umac(priv);
1652 if (ret)
1653 return ret;
1654
1655 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1656 /* clear tx/rx counter */
1657 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1658 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1659 UMAC_MIB_CTRL);
1c1008c7
FF		 1660 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1661
1662 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1663
1664 /* init rx registers, enable ip header optimization */
1665 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1666 reg |= RBUF_ALIGN_2B;
1667 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1668
1669 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1670 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1671
909ff5ef 1672 bcmgenet_intr_disable(priv);
1c1008c7 1673
4092e6ac 1674 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_TXDMA_BDONE;
1c1008c7
FF		 1675
1676 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1677
7fc527f9 1678 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1679 if (phy_is_internal(priv->phydev)) {
1c1008c7 1680 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1681 } else if (priv->ext_phy) {
1c1008c7 1682 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1683 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1684 reg = bcmgenet_bp_mc_get(priv);
1685 reg |= BIT(priv->hw_params->bp_in_en_shift);
1686
1687 /* bp_mask: back pressure mask */
1688 if (netif_is_multiqueue(priv->dev))
1689 reg |= priv->hw_params->bp_in_mask;
1690 else
1691 reg &= ~priv->hw_params->bp_in_mask;
1692 bcmgenet_bp_mc_set(priv, reg);
1693 }
1694
1695 /* Enable MDIO interrupts on GENET v3+ */
1696 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1697 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1698
c91b7f66 1699 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1c1008c7 1700
4092e6ac
JS		 1701 for (index = 0; index < priv->hw_params->tx_queues; index++)
1702 bcmgenet_intrl2_1_writel(priv, (1 << index),
1703 INTRL2_CPU_MASK_CLEAR);
1704
1c1008c7
FF		 1705 /* Enable rx/tx engine.*/
1706 dev_dbg(kdev, "done init umac\n");
1707
1708 return 0;
1709}
1710
4f8b2d7d 1711/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1712static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1713 unsigned int index, unsigned int size,
4f8b2d7d 1714 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1715{
1716 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1717 u32 words_per_bd = WORDS_PER_BD(priv);
1718 u32 flow_period_val = 0;
1c1008c7
FF		 1719
1720 spin_lock_init(&ring->lock);
4092e6ac
JS		 1721 ring->priv = priv;
1722 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1c1008c7
FF		 1723 ring->index = index;
1724 if (index == DESC_INDEX) {
1725 ring->queue = 0;
1726 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1727 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1728 } else {
1729 ring->queue = index + 1;
1730 ring->int_enable = bcmgenet_tx_ring_int_enable;
1731 ring->int_disable = bcmgenet_tx_ring_int_disable;
1732 }
4f8b2d7d 1733 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1734 ring->size = size;
66d06757 1735 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1736 ring->c_index = 0;
1737 ring->free_bds = size;
4f8b2d7d
PG		 1738 ring->write_ptr = start_ptr;
1739 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1740 ring->end_ptr = end_ptr - 1;
1741 ring->prod_index = 0;
1742
1743 /* Set flow period for ring != 16 */
1744 if (index != DESC_INDEX)
1745 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1746
1747 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1748 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1749 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1750 /* Disable rate control for now */
1751 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1752 TDMA_FLOW_PERIOD);
1c1008c7 1753 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1754 ((size << DMA_RING_SIZE_SHIFT) |
1755 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1756
1c1008c7 1757 /* Set start and end address, read and write pointers */
4f8b2d7d 1758 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1759 DMA_START_ADDR);
4f8b2d7d 1760 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1761 TDMA_READ_PTR);
4f8b2d7d 1762 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1763 TDMA_WRITE_PTR);
1c1008c7 1764 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1765 DMA_END_ADDR);
4092e6ac
JS		 1766
1767 napi_enable(&ring->napi);
1768}
1769
1770static void bcmgenet_fini_tx_ring(struct bcmgenet_priv *priv,
1771 unsigned int index)
1772{
1773 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1774
1775 napi_disable(&ring->napi);
1776 netif_napi_del(&ring->napi);
1c1008c7
FF		 1777}
1778
1779/* Initialize a RDMA ring */
1780static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
c91b7f66 1781 unsigned int index, unsigned int size)
1c1008c7
FF		 1782{
1783 u32 words_per_bd = WORDS_PER_BD(priv);
1784 int ret;
1785
1c1008c7
FF		 1786 priv->rx_bd_assign_ptr = priv->rx_bds;
1787 priv->rx_bd_assign_index = 0;
1788 priv->rx_c_index = 0;
1789 priv->rx_read_ptr = 0;
1c1008c7
FF		 1790
1791 ret = bcmgenet_alloc_rx_buffers(priv);
1792 if (ret) {
1c1008c7
FF		 1793 return ret;
1794 }
1795
1c1008c7
FF		 1796 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1797 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 1798 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 1799 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1800 ((size << DMA_RING_SIZE_SHIFT) |
1801 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1802 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1803 (DMA_FC_THRESH_LO <<
1804 DMA_XOFF_THRESHOLD_SHIFT) |
1805 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 1806
1807 /* Set start and end address, read and write pointers */
1808 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1c1008c7 1809 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
6f5a272c
PG		 1810 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1811 bcmgenet_rdma_ring_writel(priv, index, words_per_bd * size - 1,
1812 DMA_END_ADDR);
1c1008c7
FF		 1813
1814 return ret;
1815}
1816
16c6d667 1817/* Initialize Tx queues
1c1008c7 1818 *
16c6d667 1819 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 1820 * with queue 0 being the highest priority queue.
1821 *
16c6d667 1822 * Queue 16 is the default Tx queue with
51a966a7 1823 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 1824 *
16c6d667
PG		 1825 * The transmit control block pool is then partitioned as follows:
1826 * - Tx queue 0 uses tx_cbs[0..31]
1827 * - Tx queue 1 uses tx_cbs[32..63]
1828 * - Tx queue 2 uses tx_cbs[64..95]
1829 * - Tx queue 3 uses tx_cbs[96..127]
1830 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 1831 */
16c6d667 1832static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 1833{
1834 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 1835 u32 i, dma_enable;
1836 u32 dma_ctrl, ring_cfg;
37742166 1837 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 1838
1c1008c7
FF		 1839 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1840 dma_enable = dma_ctrl & DMA_EN;
1841 dma_ctrl &= ~DMA_EN;
1842 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1843
16c6d667
PG		 1844 dma_ctrl = 0;
1845 ring_cfg = 0;
1846
1c1008c7
FF		 1847 /* Enable strict priority arbiter mode */
1848 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1849
16c6d667 1850 /* Initialize Tx priority queues */
1c1008c7 1851 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 1852 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
1853 i * priv->hw_params->tx_bds_per_q,
1854 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 1855 ring_cfg |= (1 << i);
1856 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1857 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1858 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 1859 }
1860
16c6d667 1861 /* Initialize Tx default queue 16 */
51a966a7 1862 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 1863 priv->hw_params->tx_queues *
51a966a7 1864 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 1865 TOTAL_DESC);
1866 ring_cfg |= (1 << DESC_INDEX);
1867 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1868 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1869 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1870 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 1871
1872 /* Set Tx queue priorities */
37742166
PG		 1873 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1874 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1875 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1876
16c6d667
PG		 1877 /* Enable Tx queues */
1878 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 1879
16c6d667 1880 /* Enable Tx DMA */
1c1008c7 1881 if (dma_enable)
16c6d667
PG		 1882 dma_ctrl |= DMA_EN;
1883 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 1884}
1885
4a0c081e
FF		 1886static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1887{
1888 int ret = 0;
1889 int timeout = 0;
1890 u32 reg;
1891
1892 /* Disable TDMA to stop add more frames in TX DMA */
1893 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1894 reg &= ~DMA_EN;
1895 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1896
1897 /* Check TDMA status register to confirm TDMA is disabled */
1898 while (timeout++ < DMA_TIMEOUT_VAL) {
1899 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1900 if (reg & DMA_DISABLED)
1901 break;
1902
1903 udelay(1);
1904 }
1905
1906 if (timeout == DMA_TIMEOUT_VAL) {
1907 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1908 ret = -ETIMEDOUT;
1909 }
1910
1911 /* Wait 10ms for packet drain in both tx and rx dma */
1912 usleep_range(10000, 20000);
1913
1914 /* Disable RDMA */
1915 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1916 reg &= ~DMA_EN;
1917 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1918
1919 timeout = 0;
1920 /* Check RDMA status register to confirm RDMA is disabled */
1921 while (timeout++ < DMA_TIMEOUT_VAL) {
1922 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
1923 if (reg & DMA_DISABLED)
1924 break;
1925
1926 udelay(1);
1927 }
1928
1929 if (timeout == DMA_TIMEOUT_VAL) {
1930 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
1931 ret = -ETIMEDOUT;
1932 }
1933
1934 return ret;
1935}
1936
4092e6ac 1937static void __bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 1938{
1939 int i;
1940
1941 /* disable DMA */
4a0c081e 1942 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 1943
1944 for (i = 0; i < priv->num_tx_bds; i++) {
1945 if (priv->tx_cbs[i].skb != NULL) {
1946 dev_kfree_skb(priv->tx_cbs[i].skb);
1947 priv->tx_cbs[i].skb = NULL;
1948 }
1949 }
1950
1951 bcmgenet_free_rx_buffers(priv);
1952 kfree(priv->rx_cbs);
1953 kfree(priv->tx_cbs);
1954}
1955
4092e6ac
JS		 1956static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1957{
1958 int i;
1959
1960 bcmgenet_fini_tx_ring(priv, DESC_INDEX);
1961
1962 for (i = 0; i < priv->hw_params->tx_queues; i++)
1963 bcmgenet_fini_tx_ring(priv, i);
1964
1965 __bcmgenet_fini_dma(priv);
1966}
1967
1c1008c7
FF		 1968/* init_edma: Initialize DMA control register */
1969static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1970{
1971 int ret;
014012a4
PG		 1972 unsigned int i;
1973 struct enet_cb *cb;
1c1008c7 1974
6f5a272c 1975 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 1976
6f5a272c
PG		 1977 /* Init rDma */
1978 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1979
1980 /* Initialize common Rx ring structures */
1981 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1982 priv->num_rx_bds = TOTAL_DESC;
1983 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
1984 GFP_KERNEL);
1985 if (!priv->rx_cbs)
1986 return -ENOMEM;
1987
1988 for (i = 0; i < priv->num_rx_bds; i++) {
1989 cb = priv->rx_cbs + i;
1990 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
1991 }
1992
1993 /* Initialize Rx default queue 16 */
1c1008c7
FF		 1994 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1995 if (ret) {
1996 netdev_err(priv->dev, "failed to initialize RX ring\n");
6f5a272c
PG		 1997 bcmgenet_free_rx_buffers(priv);
1998 kfree(priv->rx_cbs);
1c1008c7
FF		 1999 return ret;
2000 }
2001
1c1008c7
FF		 2002 /* Init tDma */
2003 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2004
7fc527f9 2005 /* Initialize common TX ring structures */
1c1008c7
FF		 2006 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2007 priv->num_tx_bds = TOTAL_DESC;
c489be08 2008 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2009 GFP_KERNEL);
1c1008c7 2010 if (!priv->tx_cbs) {
4092e6ac 2011 __bcmgenet_fini_dma(priv);
1c1008c7
FF		 2012 return -ENOMEM;
2013 }
2014
014012a4
PG		 2015 for (i = 0; i < priv->num_tx_bds; i++) {
2016 cb = priv->tx_cbs + i;
2017 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2018 }
2019
16c6d667
PG		 2020 /* Initialize Tx queues */
2021 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2022
2023 return 0;
2024}
2025
2026/* NAPI polling method*/
2027static int bcmgenet_poll(struct napi_struct *napi, int budget)
2028{
2029 struct bcmgenet_priv *priv = container_of(napi,
2030 struct bcmgenet_priv, napi);
2031 unsigned int work_done;
2032
1c1008c7
FF		 2033 work_done = bcmgenet_desc_rx(priv, budget);
2034
2035 /* Advancing our consumer index*/
2036 priv->rx_c_index += work_done;
2037 priv->rx_c_index &= DMA_C_INDEX_MASK;
2038 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
c91b7f66 2039 priv->rx_c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 2040 if (work_done < budget) {
2041 napi_complete(napi);
c91b7f66
FF		 2042 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2043 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 2044 }
2045
2046 return work_done;
2047}
2048
2049/* Interrupt bottom half */
2050static void bcmgenet_irq_task(struct work_struct *work)
2051{
2052 struct bcmgenet_priv *priv = container_of(
2053 work, struct bcmgenet_priv, bcmgenet_irq_work);
2054
2055 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2056
8fdb0e0f
FF		 2057 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2058 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2059 netif_dbg(priv, wol, priv->dev,
2060 "magic packet detected, waking up\n");
2061 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2062 }
2063
1c1008c7
FF		 2064 /* Link UP/DOWN event */
2065 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2066 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d 2067 phy_mac_interrupt(priv->phydev,
c91b7f66 2068 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 2069 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
2070 }
2071}
2072
2073/* bcmgenet_isr1: interrupt handler for ring buffer. */
2074static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2075{
2076 struct bcmgenet_priv *priv = dev_id;
4092e6ac 2077 struct bcmgenet_tx_ring *ring;
1c1008c7
FF		 2078 unsigned int index;
2079
2080 /* Save irq status for bottom-half processing. */
2081 priv->irq1_stat =
2082 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2083 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2084 /* clear interrupts */
1c1008c7
FF		 2085 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2086
2087 netif_dbg(priv, intr, priv->dev,
c91b7f66 2088 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2089
1c1008c7
FF		 2090 /* Check the MBDONE interrupts.
2091 * packet is done, reclaim descriptors
2092 */
4092e6ac
JS		 2093 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2094 if (!(priv->irq1_stat & BIT(index)))
2095 continue;
2096
2097 ring = &priv->tx_rings[index];
2098
2099 if (likely(napi_schedule_prep(&ring->napi))) {
2100 ring->int_disable(priv, ring);
2101 __napi_schedule(&ring->napi);
1c1008c7
FF		 2102 }
2103 }
4092e6ac 2104
1c1008c7
FF		 2105 return IRQ_HANDLED;
2106}
2107
2108/* bcmgenet_isr0: Handle various interrupts. */
2109static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2110{
2111 struct bcmgenet_priv *priv = dev_id;
2112
2113 /* Save irq status for bottom-half processing. */
2114 priv->irq0_stat =
2115 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2116 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2117 /* clear interrupts */
1c1008c7
FF		 2118 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2119
2120 netif_dbg(priv, intr, priv->dev,
c91b7f66 2121 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7
FF		 2122
2123 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
2124 /* We use NAPI(software interrupt throttling, if
2125 * Rx Descriptor throttling is not used.
2126 * Disable interrupt, will be enabled in the poll method.
2127 */
2128 if (likely(napi_schedule_prep(&priv->napi))) {
c91b7f66
FF		 2129 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2130 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 2131 __napi_schedule(&priv->napi);
2132 }
2133 }
2134 if (priv->irq0_stat &
2135 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
4092e6ac
JS		 2136 struct bcmgenet_tx_ring *ring = &priv->tx_rings[DESC_INDEX];
2137
2138 if (likely(napi_schedule_prep(&ring->napi))) {
2139 ring->int_disable(priv, ring);
2140 __napi_schedule(&ring->napi);
2141 }
1c1008c7
FF		 2142 }
2143 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2144 UMAC_IRQ_PHY_DET_F |
2145 UMAC_IRQ_LINK_UP |
2146 UMAC_IRQ_LINK_DOWN |
2147 UMAC_IRQ_HFB_SM |
2148 UMAC_IRQ_HFB_MM |
2149 UMAC_IRQ_MPD_R)) {
2150 /* all other interested interrupts handled in bottom half */
2151 schedule_work(&priv->bcmgenet_irq_work);
2152 }
2153
2154 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2155 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2156 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2157 wake_up(&priv->wq);
2158 }
2159
2160 return IRQ_HANDLED;
2161}
2162
8562056f
FF		 2163static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2164{
2165 struct bcmgenet_priv *priv = dev_id;
2166
2167 pm_wakeup_event(&priv->pdev->dev, 0);
2168
2169 return IRQ_HANDLED;
2170}
2171
1c1008c7
FF		 2172static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2173{
2174 u32 reg;
2175
2176 reg = bcmgenet_rbuf_ctrl_get(priv);
2177 reg |= BIT(1);
2178 bcmgenet_rbuf_ctrl_set(priv, reg);
2179 udelay(10);
2180
2181 reg &= ~BIT(1);
2182 bcmgenet_rbuf_ctrl_set(priv, reg);
2183 udelay(10);
2184}
2185
2186static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2187 unsigned char *addr)
1c1008c7
FF		 2188{
2189 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2190 (addr[2] << 8) | addr[3], UMAC_MAC0);
2191 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2192}
2193
1c1008c7
FF		 2194/* Returns a reusable dma control register value */
2195static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2196{
2197 u32 reg;
2198 u32 dma_ctrl;
2199
2200 /* disable DMA */
2201 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2202 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2203 reg &= ~dma_ctrl;
2204 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2205
2206 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2207 reg &= ~dma_ctrl;
2208 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2209
2210 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2211 udelay(10);
2212 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2213
2214 return dma_ctrl;
2215}
2216
2217static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2218{
2219 u32 reg;
2220
2221 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2222 reg |= dma_ctrl;
2223 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2224
2225 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2226 reg |= dma_ctrl;
2227 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2228}
2229
909ff5ef
FF		 2230static void bcmgenet_netif_start(struct net_device *dev)
2231{
2232 struct bcmgenet_priv *priv = netdev_priv(dev);
2233
2234 /* Start the network engine */
2235 napi_enable(&priv->napi);
2236
2237 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2238
2239 if (phy_is_internal(priv->phydev))
2240 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2241
2242 netif_tx_start_all_queues(dev);
2243
2244 phy_start(priv->phydev);
2245}
2246
1c1008c7
FF		 2247static int bcmgenet_open(struct net_device *dev)
2248{
2249 struct bcmgenet_priv *priv = netdev_priv(dev);
2250 unsigned long dma_ctrl;
2251 u32 reg;
2252 int ret;
2253
2254 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2255
2256 /* Turn on the clock */
2257 if (!IS_ERR(priv->clk))
2258 clk_prepare_enable(priv->clk);
2259
2260 /* take MAC out of reset */
2261 bcmgenet_umac_reset(priv);
2262
2263 ret = init_umac(priv);
2264 if (ret)
2265 goto err_clk_disable;
2266
2267 /* disable ethernet MAC while updating its registers */
e29585b8 2268 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2269
909ff5ef
FF		 2270 /* Make sure we reflect the value of CRC_CMD_FWD */
2271 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2272 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2273
1c1008c7
FF		 2274 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2275
1c1008c7
FF		 2276 if (phy_is_internal(priv->phydev)) {
2277 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2278 reg |= EXT_ENERGY_DET_MASK;
2279 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2280 }
2281
2282 /* Disable RX/TX DMA and flush TX queues */
2283 dma_ctrl = bcmgenet_dma_disable(priv);
2284
2285 /* Reinitialize TDMA and RDMA and SW housekeeping */
2286 ret = bcmgenet_init_dma(priv);
2287 if (ret) {
2288 netdev_err(dev, "failed to initialize DMA\n");
2289 goto err_fini_dma;
2290 }
2291
2292 /* Always enable ring 16 - descriptor ring */
2293 bcmgenet_enable_dma(priv, dma_ctrl);
2294
2295 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2296 dev->name, priv);
1c1008c7
FF		 2297 if (ret < 0) {
2298 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2299 goto err_fini_dma;
2300 }
2301
2302 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2303 dev->name, priv);
1c1008c7
FF		 2304 if (ret < 0) {
2305 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2306 goto err_irq0;
2307 }
2308
dbd479db
FF		 2309 /* Re-configure the port multiplexer towards the PHY device */
2310 bcmgenet_mii_config(priv->dev, false);
2311
c96e731c
FF		 2312 phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2313 priv->phy_interface);
2314
909ff5ef 2315 bcmgenet_netif_start(dev);
1c1008c7
FF		 2316
2317 return 0;
2318
2319err_irq0:
2320 free_irq(priv->irq0, dev);
2321err_fini_dma:
2322 bcmgenet_fini_dma(priv);
2323err_clk_disable:
2324 if (!IS_ERR(priv->clk))
2325 clk_disable_unprepare(priv->clk);
2326 return ret;
2327}
2328
909ff5ef
FF		 2329static void bcmgenet_netif_stop(struct net_device *dev)
2330{
2331 struct bcmgenet_priv *priv = netdev_priv(dev);
2332
2333 netif_tx_stop_all_queues(dev);
2334 napi_disable(&priv->napi);
2335 phy_stop(priv->phydev);
2336
2337 bcmgenet_intr_disable(priv);
2338
2339 /* Wait for pending work items to complete. Since interrupts are
2340 * disabled no new work will be scheduled.
2341 */
2342 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2343
cc013fb4 2344 priv->old_link = -1;
5ad6e6c5 2345 priv->old_speed = -1;
cc013fb4 2346 priv->old_duplex = -1;
5ad6e6c5 2347 priv->old_pause = -1;
909ff5ef
FF		 2348}
2349
1c1008c7
FF		 2350static int bcmgenet_close(struct net_device *dev)
2351{
2352 struct bcmgenet_priv *priv = netdev_priv(dev);
2353 int ret;
1c1008c7
FF		 2354
2355 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2356
909ff5ef 2357 bcmgenet_netif_stop(dev);
1c1008c7 2358
c96e731c
FF		 2359 /* Really kill the PHY state machine and disconnect from it */
2360 phy_disconnect(priv->phydev);
2361
1c1008c7 2362 /* Disable MAC receive */
e29585b8 2363 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2364
1c1008c7
FF		 2365 ret = bcmgenet_dma_teardown(priv);
2366 if (ret)
2367 return ret;
2368
2369 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2370 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2371
1c1008c7
FF		 2372 /* tx reclaim */
2373 bcmgenet_tx_reclaim_all(dev);
2374 bcmgenet_fini_dma(priv);
2375
2376 free_irq(priv->irq0, priv);
2377 free_irq(priv->irq1, priv);
2378
1c1008c7
FF		 2379 if (phy_is_internal(priv->phydev))
2380 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2381
1c1008c7
FF		 2382 if (!IS_ERR(priv->clk))
2383 clk_disable_unprepare(priv->clk);
2384
2385 return 0;
2386}
2387
2388static void bcmgenet_timeout(struct net_device *dev)
2389{
2390 struct bcmgenet_priv *priv = netdev_priv(dev);
2391
2392 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2393
2394 dev->trans_start = jiffies;
2395
2396 dev->stats.tx_errors++;
2397
2398 netif_tx_wake_all_queues(dev);
2399}
2400
2401#define MAX_MC_COUNT 16
2402
2403static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2404 unsigned char *addr,
2405 int *i,
2406 int *mc)
2407{
2408 u32 reg;
2409
c91b7f66
FF		 2410 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2411 UMAC_MDF_ADDR + (*i * 4));
2412 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2413 addr[4] << 8 | addr[5],
2414 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2415 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2416 reg |= (1 << (MAX_MC_COUNT - *mc));
2417 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2418 *i += 2;
2419 (*mc)++;
2420}
2421
2422static void bcmgenet_set_rx_mode(struct net_device *dev)
2423{
2424 struct bcmgenet_priv *priv = netdev_priv(dev);
2425 struct netdev_hw_addr *ha;
2426 int i, mc;
2427 u32 reg;
2428
2429 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2430
7fc527f9 2431 /* Promiscuous mode */
1c1008c7
FF		 2432 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2433 if (dev->flags & IFF_PROMISC) {
2434 reg |= CMD_PROMISC;
2435 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2436 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2437 return;
2438 } else {
2439 reg &= ~CMD_PROMISC;
2440 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2441 }
2442
2443 /* UniMac doesn't support ALLMULTI */
2444 if (dev->flags & IFF_ALLMULTI) {
2445 netdev_warn(dev, "ALLMULTI is not supported\n");
2446 return;
2447 }
2448
2449 /* update MDF filter */
2450 i = 0;
2451 mc = 0;
2452 /* Broadcast */
2453 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2454 /* my own address.*/
2455 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2456 /* Unicast list*/
2457 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2458 return;
2459
2460 if (!netdev_uc_empty(dev))
2461 netdev_for_each_uc_addr(ha, dev)
2462 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2463 /* Multicast */
2464 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2465 return;
2466
2467 netdev_for_each_mc_addr(ha, dev)
2468 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2469}
2470
2471/* Set the hardware MAC address. */
2472static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2473{
2474 struct sockaddr *addr = p;
2475
2476 /* Setting the MAC address at the hardware level is not possible
2477 * without disabling the UniMAC RX/TX enable bits.
2478 */
2479 if (netif_running(dev))
2480 return -EBUSY;
2481
2482 ether_addr_copy(dev->dev_addr, addr->sa_data);
2483
2484 return 0;
2485}
2486
1c1008c7
FF		 2487static const struct net_device_ops bcmgenet_netdev_ops = {
2488 .ndo_open = bcmgenet_open,
2489 .ndo_stop = bcmgenet_close,
2490 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2491 .ndo_tx_timeout = bcmgenet_timeout,
2492 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2493 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2494 .ndo_do_ioctl = bcmgenet_ioctl,
2495 .ndo_set_features = bcmgenet_set_features,
2496};
2497
2498/* Array of GENET hardware parameters/characteristics */
2499static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2500 [GENET_V1] = {
2501 .tx_queues = 0,
51a966a7 2502 .tx_bds_per_q = 0,
1c1008c7 2503 .rx_queues = 0,
3feafa02 2504 .rx_bds_per_q = 0,
1c1008c7
FF		 2505 .bp_in_en_shift = 16,
2506 .bp_in_mask = 0xffff,
2507 .hfb_filter_cnt = 16,
2508 .qtag_mask = 0x1F,
2509 .hfb_offset = 0x1000,
2510 .rdma_offset = 0x2000,
2511 .tdma_offset = 0x3000,
2512 .words_per_bd = 2,
2513 },
2514 [GENET_V2] = {
2515 .tx_queues = 4,
51a966a7 2516 .tx_bds_per_q = 32,
7e906e02 2517 .rx_queues = 0,
3feafa02 2518 .rx_bds_per_q = 0,
1c1008c7
FF		 2519 .bp_in_en_shift = 16,
2520 .bp_in_mask = 0xffff,
2521 .hfb_filter_cnt = 16,
2522 .qtag_mask = 0x1F,
2523 .tbuf_offset = 0x0600,
2524 .hfb_offset = 0x1000,
2525 .hfb_reg_offset = 0x2000,
2526 .rdma_offset = 0x3000,
2527 .tdma_offset = 0x4000,
2528 .words_per_bd = 2,
2529 .flags = GENET_HAS_EXT,
2530 },
2531 [GENET_V3] = {
2532 .tx_queues = 4,
51a966a7 2533 .tx_bds_per_q = 32,
7e906e02 2534 .rx_queues = 0,
3feafa02 2535 .rx_bds_per_q = 0,
1c1008c7
FF		 2536 .bp_in_en_shift = 17,
2537 .bp_in_mask = 0x1ffff,
2538 .hfb_filter_cnt = 48,
2539 .qtag_mask = 0x3F,
2540 .tbuf_offset = 0x0600,
2541 .hfb_offset = 0x8000,
2542 .hfb_reg_offset = 0xfc00,
2543 .rdma_offset = 0x10000,
2544 .tdma_offset = 0x11000,
2545 .words_per_bd = 2,
2546 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2547 },
2548 [GENET_V4] = {
2549 .tx_queues = 4,
51a966a7 2550 .tx_bds_per_q = 32,
7e906e02 2551 .rx_queues = 0,
3feafa02 2552 .rx_bds_per_q = 0,
1c1008c7
FF		 2553 .bp_in_en_shift = 17,
2554 .bp_in_mask = 0x1ffff,
2555 .hfb_filter_cnt = 48,
2556 .qtag_mask = 0x3F,
2557 .tbuf_offset = 0x0600,
2558 .hfb_offset = 0x8000,
2559 .hfb_reg_offset = 0xfc00,
2560 .rdma_offset = 0x2000,
2561 .tdma_offset = 0x4000,
2562 .words_per_bd = 3,
2563 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2564 },
2565};
2566
2567/* Infer hardware parameters from the detected GENET version */
2568static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2569{
2570 struct bcmgenet_hw_params *params;
2571 u32 reg;
2572 u8 major;
b04a2f5b 2573 u16 gphy_rev;
1c1008c7
FF		 2574
2575 if (GENET_IS_V4(priv)) {
2576 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2577 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2578 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2579 priv->version = GENET_V4;
2580 } else if (GENET_IS_V3(priv)) {
2581 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2582 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2583 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2584 priv->version = GENET_V3;
2585 } else if (GENET_IS_V2(priv)) {
2586 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2587 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2588 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2589 priv->version = GENET_V2;
2590 } else if (GENET_IS_V1(priv)) {
2591 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2592 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2593 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2594 priv->version = GENET_V1;
2595 }
2596
2597 /* enum genet_version starts at 1 */
2598 priv->hw_params = &bcmgenet_hw_params[priv->version];
2599 params = priv->hw_params;
2600
2601 /* Read GENET HW version */
2602 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2603 major = (reg >> 24 & 0x0f);
2604 if (major == 5)
2605 major = 4;
2606 else if (major == 0)
2607 major = 1;
2608 if (major != priv->version) {
2609 dev_err(&priv->pdev->dev,
2610 "GENET version mismatch, got: %d, configured for: %d\n",
2611 major, priv->version);
2612 }
2613
2614 /* Print the GENET core version */
2615 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 2616 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 2617
487320c5
FF		 2618 /* Store the integrated PHY revision for the MDIO probing function
2619 * to pass this information to the PHY driver. The PHY driver expects
2620 * to find the PHY major revision in bits 15:8 while the GENET register
2621 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 2622 *
2623 * On newer chips, starting with PHY revision G0, a new scheme is
2624 * deployed similar to the Starfighter 2 switch with GPHY major
2625 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
2626 * is reserved as well as special value 0x01ff, we have a small
2627 * heuristic to check for the new GPHY revision and re-arrange things
2628 * so the GPHY driver is happy.
487320c5 2629 */
b04a2f5b
FF		 2630 gphy_rev = reg & 0xffff;
2631
2632 /* This is the good old scheme, just GPHY major, no minor nor patch */
2633 if ((gphy_rev & 0xf0) != 0)
2634 priv->gphy_rev = gphy_rev << 8;
2635
2636 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
2637 else if ((gphy_rev & 0xff00) != 0)
2638 priv->gphy_rev = gphy_rev;
2639
2640 /* This is reserved so should require special treatment */
2641 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
2642 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
2643 return;
2644 }
487320c5 2645
1c1008c7
FF		 2646#ifdef CONFIG_PHYS_ADDR_T_64BIT
2647 if (!(params->flags & GENET_HAS_40BITS))
2648 pr_warn("GENET does not support 40-bits PA\n");
2649#endif
2650
2651 pr_debug("Configuration for version: %d\n"
3feafa02 2652 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 2653 "BP << en: %2d, BP msk: 0x%05x\n"
2654 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2655 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2656 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2657 "Words/BD: %d\n",
2658 priv->version,
51a966a7 2659 params->tx_queues, params->tx_bds_per_q,
3feafa02 2660 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 2661 params->bp_in_en_shift, params->bp_in_mask,
2662 params->hfb_filter_cnt, params->qtag_mask,
2663 params->tbuf_offset, params->hfb_offset,
2664 params->hfb_reg_offset,
2665 params->rdma_offset, params->tdma_offset,
2666 params->words_per_bd);
2667}
2668
2669static const struct of_device_id bcmgenet_match[] = {
2670 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2671 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2672 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2673 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2674 { },
2675};
2676
2677static int bcmgenet_probe(struct platform_device *pdev)
2678{
b0ba512e 2679 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 2680 struct device_node *dn = pdev->dev.of_node;
b0ba512e 2681 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 2682 struct bcmgenet_priv *priv;
2683 struct net_device *dev;
2684 const void *macaddr;
2685 struct resource *r;
2686 int err = -EIO;
2687
3feafeed
PG		 2688 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
2689 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
2690 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 2691 if (!dev) {
2692 dev_err(&pdev->dev, "can't allocate net device\n");
2693 return -ENOMEM;
2694 }
2695
b0ba512e
PG		 2696 if (dn) {
2697 of_id = of_match_node(bcmgenet_match, dn);
2698 if (!of_id)
2699 return -EINVAL;
2700 }
1c1008c7
FF		 2701
2702 priv = netdev_priv(dev);
2703 priv->irq0 = platform_get_irq(pdev, 0);
2704 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2705 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2706 if (!priv->irq0 || !priv->irq1) {
2707 dev_err(&pdev->dev, "can't find IRQs\n");
2708 err = -EINVAL;
2709 goto err;
2710 }
2711
b0ba512e
PG		 2712 if (dn) {
2713 macaddr = of_get_mac_address(dn);
2714 if (!macaddr) {
2715 dev_err(&pdev->dev, "can't find MAC address\n");
2716 err = -EINVAL;
2717 goto err;
2718 }
2719 } else {
2720 macaddr = pd->mac_address;
1c1008c7
FF		 2721 }
2722
2723 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2724 priv->base = devm_ioremap_resource(&pdev->dev, r);
2725 if (IS_ERR(priv->base)) {
2726 err = PTR_ERR(priv->base);
1c1008c7
FF		 2727 goto err;
2728 }
2729
2730 SET_NETDEV_DEV(dev, &pdev->dev);
2731 dev_set_drvdata(&pdev->dev, dev);
2732 ether_addr_copy(dev->dev_addr, macaddr);
2733 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2734 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2735 dev->netdev_ops = &bcmgenet_netdev_ops;
2736 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2737
2738 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2739
2740 /* Set hardware features */
2741 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2742 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2743
8562056f
FF		 2744 /* Request the WOL interrupt and advertise suspend if available */
2745 priv->wol_irq_disabled = true;
2746 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2747 dev->name, priv);
2748 if (!err)
2749 device_set_wakeup_capable(&pdev->dev, 1);
2750
1c1008c7
FF		 2751 /* Set the needed headroom to account for any possible
2752 * features enabling/disabling at runtime
2753 */
2754 dev->needed_headroom += 64;
2755
2756 netdev_boot_setup_check(dev);
2757
2758 priv->dev = dev;
2759 priv->pdev = pdev;
b0ba512e
PG		 2760 if (of_id)
2761 priv->version = (enum bcmgenet_version)of_id->data;
2762 else
2763 priv->version = pd->genet_version;
1c1008c7 2764
e4a60a93
FF		 2765 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2766 if (IS_ERR(priv->clk))
2767 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2768
2769 if (!IS_ERR(priv->clk))
2770 clk_prepare_enable(priv->clk);
2771
1c1008c7
FF		 2772 bcmgenet_set_hw_params(priv);
2773
1c1008c7
FF		 2774 /* Mii wait queue */
2775 init_waitqueue_head(&priv->wq);
2776 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2777 priv->rx_buf_len = RX_BUF_LENGTH;
2778 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2779
1c1008c7
FF		 2780 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2781 if (IS_ERR(priv->clk_wol))
2782 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2783
6ef398ea
FF		 2784 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
2785 if (IS_ERR(priv->clk_eee)) {
2786 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
2787 priv->clk_eee = NULL;
2788 }
2789
1c1008c7
FF		 2790 err = reset_umac(priv);
2791 if (err)
2792 goto err_clk_disable;
2793
2794 err = bcmgenet_mii_init(dev);
2795 if (err)
2796 goto err_clk_disable;
2797
2798 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2799 * just the ring 16 descriptor based TX
2800 */
2801 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2802 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2803
219575eb
FF		 2804 /* libphy will determine the link state */
2805 netif_carrier_off(dev);
2806
1c1008c7
FF		 2807 /* Turn off the main clock, WOL clock is handled separately */
2808 if (!IS_ERR(priv->clk))
2809 clk_disable_unprepare(priv->clk);
2810
0f50ce96
FF		 2811 err = register_netdev(dev);
2812 if (err)
2813 goto err;
2814
1c1008c7
FF		 2815 return err;
2816
2817err_clk_disable:
2818 if (!IS_ERR(priv->clk))
2819 clk_disable_unprepare(priv->clk);
2820err:
2821 free_netdev(dev);
2822 return err;
2823}
2824
2825static int bcmgenet_remove(struct platform_device *pdev)
2826{
2827 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2828
2829 dev_set_drvdata(&pdev->dev, NULL);
2830 unregister_netdev(priv->dev);
2831 bcmgenet_mii_exit(priv->dev);
2832 free_netdev(priv->dev);
2833
2834 return 0;
2835}
2836
b6e978e5
FF		 2837#ifdef CONFIG_PM_SLEEP
2838static int bcmgenet_suspend(struct device *d)
2839{
2840 struct net_device *dev = dev_get_drvdata(d);
2841 struct bcmgenet_priv *priv = netdev_priv(dev);
2842 int ret;
2843
2844 if (!netif_running(dev))
2845 return 0;
2846
2847 bcmgenet_netif_stop(dev);
2848
cc013fb4
FF		 2849 phy_suspend(priv->phydev);
2850
b6e978e5
FF		 2851 netif_device_detach(dev);
2852
2853 /* Disable MAC receive */
2854 umac_enable_set(priv, CMD_RX_EN, false);
2855
2856 ret = bcmgenet_dma_teardown(priv);
2857 if (ret)
2858 return ret;
2859
2860 /* Disable MAC transmit. TX DMA disabled have to done before this */
2861 umac_enable_set(priv, CMD_TX_EN, false);
2862
2863 /* tx reclaim */
2864 bcmgenet_tx_reclaim_all(dev);
2865 bcmgenet_fini_dma(priv);
2866
8c90db72
FF		 2867 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2868 if (device_may_wakeup(d) && priv->wolopts) {
2869 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2870 clk_prepare_enable(priv->clk_wol);
2871 }
2872
b6e978e5
FF		 2873 /* Turn off the clocks */
2874 clk_disable_unprepare(priv->clk);
2875
2876 return 0;
2877}
2878
2879static int bcmgenet_resume(struct device *d)
2880{
2881 struct net_device *dev = dev_get_drvdata(d);
2882 struct bcmgenet_priv *priv = netdev_priv(dev);
2883 unsigned long dma_ctrl;
2884 int ret;
2885 u32 reg;
2886
2887 if (!netif_running(dev))
2888 return 0;
2889
2890 /* Turn on the clock */
2891 ret = clk_prepare_enable(priv->clk);
2892 if (ret)
2893 return ret;
2894
2895 bcmgenet_umac_reset(priv);
2896
2897 ret = init_umac(priv);
2898 if (ret)
2899 goto out_clk_disable;
2900
0a29b3da
TK		 2901 /* From WOL-enabled suspend, switch to regular clock */
2902 if (priv->wolopts)
2903 clk_disable_unprepare(priv->clk_wol);
2904
2905 phy_init_hw(priv->phydev);
2906 /* Speed settings must be restored */
dbd479db 2907 bcmgenet_mii_config(priv->dev, false);
8c90db72 2908
b6e978e5
FF		 2909 /* disable ethernet MAC while updating its registers */
2910 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2911
2912 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2913
2914 if (phy_is_internal(priv->phydev)) {
2915 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2916 reg |= EXT_ENERGY_DET_MASK;
2917 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2918 }
2919
98bb7399
FF		 2920 if (priv->wolopts)
2921 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2922
b6e978e5
FF		 2923 /* Disable RX/TX DMA and flush TX queues */
2924 dma_ctrl = bcmgenet_dma_disable(priv);
2925
2926 /* Reinitialize TDMA and RDMA and SW housekeeping */
2927 ret = bcmgenet_init_dma(priv);
2928 if (ret) {
2929 netdev_err(dev, "failed to initialize DMA\n");
2930 goto out_clk_disable;
2931 }
2932
2933 /* Always enable ring 16 - descriptor ring */
2934 bcmgenet_enable_dma(priv, dma_ctrl);
2935
2936 netif_device_attach(dev);
2937
cc013fb4
FF		 2938 phy_resume(priv->phydev);
2939
6ef398ea
FF		 2940 if (priv->eee.eee_enabled)
2941 bcmgenet_eee_enable_set(dev, true);
2942
b6e978e5
FF		 2943 bcmgenet_netif_start(dev);
2944
2945 return 0;
2946
2947out_clk_disable:
2948 clk_disable_unprepare(priv->clk);
2949 return ret;
2950}
2951#endif /* CONFIG_PM_SLEEP */
2952
2953static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2954
1c1008c7
FF		 2955static struct platform_driver bcmgenet_driver = {
2956 .probe = bcmgenet_probe,
2957 .remove = bcmgenet_remove,
2958 .driver = {
2959 .name = "bcmgenet",
1c1008c7 2960 .of_match_table = bcmgenet_match,
b6e978e5 2961 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 2962 },
2963};
2964module_platform_driver(bcmgenet_driver);
2965
2966MODULE_AUTHOR("Broadcom Corporation");
2967MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2968MODULE_ALIAS("platform:bcmgenet");
2969MODULE_LICENSE("GPL");
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