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1c1008c7 FF |
1 | /* |
2 | * Broadcom GENET (Gigabit Ethernet) controller driver | |
3 | * | |
4 | * Copyright (c) 2014 Broadcom Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
1c1008c7 FF |
9 | */ |
10 | ||
11 | #define pr_fmt(fmt) "bcmgenet: " fmt | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/fcntl.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/if_ether.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/clk.h> | |
1c1008c7 FF |
28 | #include <linux/of.h> |
29 | #include <linux/of_address.h> | |
30 | #include <linux/of_irq.h> | |
31 | #include <linux/of_net.h> | |
32 | #include <linux/of_platform.h> | |
33 | #include <net/arp.h> | |
34 | ||
35 | #include <linux/mii.h> | |
36 | #include <linux/ethtool.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/inetdevice.h> | |
39 | #include <linux/etherdevice.h> | |
40 | #include <linux/skbuff.h> | |
41 | #include <linux/in.h> | |
42 | #include <linux/ip.h> | |
43 | #include <linux/ipv6.h> | |
44 | #include <linux/phy.h> | |
45 | ||
46 | #include <asm/unaligned.h> | |
47 | ||
48 | #include "bcmgenet.h" | |
49 | ||
50 | /* Maximum number of hardware queues, downsized if needed */ | |
51 | #define GENET_MAX_MQ_CNT 4 | |
52 | ||
53 | /* Default highest priority queue for multi queue support */ | |
54 | #define GENET_Q0_PRIORITY 0 | |
55 | ||
56 | #define GENET_DEFAULT_BD_CNT \ | |
57 | (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt) | |
58 | ||
59 | #define RX_BUF_LENGTH 2048 | |
60 | #define SKB_ALIGNMENT 32 | |
61 | ||
62 | /* Tx/Rx DMA register offset, skip 256 descriptors */ | |
63 | #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) | |
64 | #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) | |
65 | ||
66 | #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ | |
67 | TOTAL_DESC * DMA_DESC_SIZE) | |
68 | ||
69 | #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ | |
70 | TOTAL_DESC * DMA_DESC_SIZE) | |
71 | ||
72 | static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, | |
c91b7f66 | 73 | void __iomem *d, u32 value) |
1c1008c7 FF |
74 | { |
75 | __raw_writel(value, d + DMA_DESC_LENGTH_STATUS); | |
76 | } | |
77 | ||
78 | static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv, | |
c91b7f66 | 79 | void __iomem *d) |
1c1008c7 FF |
80 | { |
81 | return __raw_readl(d + DMA_DESC_LENGTH_STATUS); | |
82 | } | |
83 | ||
84 | static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, | |
85 | void __iomem *d, | |
86 | dma_addr_t addr) | |
87 | { | |
88 | __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); | |
89 | ||
90 | /* Register writes to GISB bus can take couple hundred nanoseconds | |
91 | * and are done for each packet, save these expensive writes unless | |
92 | * the platform is explicitely configured for 64-bits/LPAE. | |
93 | */ | |
94 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
95 | if (priv->hw_params->flags & GENET_HAS_40BITS) | |
96 | __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); | |
97 | #endif | |
98 | } | |
99 | ||
100 | /* Combined address + length/status setter */ | |
101 | static inline void dmadesc_set(struct bcmgenet_priv *priv, | |
c91b7f66 | 102 | void __iomem *d, dma_addr_t addr, u32 val) |
1c1008c7 FF |
103 | { |
104 | dmadesc_set_length_status(priv, d, val); | |
105 | dmadesc_set_addr(priv, d, addr); | |
106 | } | |
107 | ||
108 | static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, | |
109 | void __iomem *d) | |
110 | { | |
111 | dma_addr_t addr; | |
112 | ||
113 | addr = __raw_readl(d + DMA_DESC_ADDRESS_LO); | |
114 | ||
115 | /* Register writes to GISB bus can take couple hundred nanoseconds | |
116 | * and are done for each packet, save these expensive writes unless | |
117 | * the platform is explicitely configured for 64-bits/LPAE. | |
118 | */ | |
119 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
120 | if (priv->hw_params->flags & GENET_HAS_40BITS) | |
121 | addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32; | |
122 | #endif | |
123 | return addr; | |
124 | } | |
125 | ||
126 | #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" | |
127 | ||
128 | #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ | |
129 | NETIF_MSG_LINK) | |
130 | ||
131 | static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) | |
132 | { | |
133 | if (GENET_IS_V1(priv)) | |
134 | return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); | |
135 | else | |
136 | return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); | |
137 | } | |
138 | ||
139 | static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) | |
140 | { | |
141 | if (GENET_IS_V1(priv)) | |
142 | bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); | |
143 | else | |
144 | bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); | |
145 | } | |
146 | ||
147 | /* These macros are defined to deal with register map change | |
148 | * between GENET1.1 and GENET2. Only those currently being used | |
149 | * by driver are defined. | |
150 | */ | |
151 | static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) | |
152 | { | |
153 | if (GENET_IS_V1(priv)) | |
154 | return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); | |
155 | else | |
156 | return __raw_readl(priv->base + | |
157 | priv->hw_params->tbuf_offset + TBUF_CTRL); | |
158 | } | |
159 | ||
160 | static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) | |
161 | { | |
162 | if (GENET_IS_V1(priv)) | |
163 | bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); | |
164 | else | |
165 | __raw_writel(val, priv->base + | |
166 | priv->hw_params->tbuf_offset + TBUF_CTRL); | |
167 | } | |
168 | ||
169 | static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) | |
170 | { | |
171 | if (GENET_IS_V1(priv)) | |
172 | return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); | |
173 | else | |
174 | return __raw_readl(priv->base + | |
175 | priv->hw_params->tbuf_offset + TBUF_BP_MC); | |
176 | } | |
177 | ||
178 | static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) | |
179 | { | |
180 | if (GENET_IS_V1(priv)) | |
181 | bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); | |
182 | else | |
183 | __raw_writel(val, priv->base + | |
184 | priv->hw_params->tbuf_offset + TBUF_BP_MC); | |
185 | } | |
186 | ||
187 | /* RX/TX DMA register accessors */ | |
188 | enum dma_reg { | |
189 | DMA_RING_CFG = 0, | |
190 | DMA_CTRL, | |
191 | DMA_STATUS, | |
192 | DMA_SCB_BURST_SIZE, | |
193 | DMA_ARB_CTRL, | |
194 | DMA_PRIORITY, | |
195 | DMA_RING_PRIORITY, | |
196 | }; | |
197 | ||
198 | static const u8 bcmgenet_dma_regs_v3plus[] = { | |
199 | [DMA_RING_CFG] = 0x00, | |
200 | [DMA_CTRL] = 0x04, | |
201 | [DMA_STATUS] = 0x08, | |
202 | [DMA_SCB_BURST_SIZE] = 0x0C, | |
203 | [DMA_ARB_CTRL] = 0x2C, | |
204 | [DMA_PRIORITY] = 0x30, | |
205 | [DMA_RING_PRIORITY] = 0x38, | |
206 | }; | |
207 | ||
208 | static const u8 bcmgenet_dma_regs_v2[] = { | |
209 | [DMA_RING_CFG] = 0x00, | |
210 | [DMA_CTRL] = 0x04, | |
211 | [DMA_STATUS] = 0x08, | |
212 | [DMA_SCB_BURST_SIZE] = 0x0C, | |
213 | [DMA_ARB_CTRL] = 0x30, | |
214 | [DMA_PRIORITY] = 0x34, | |
215 | [DMA_RING_PRIORITY] = 0x3C, | |
216 | }; | |
217 | ||
218 | static const u8 bcmgenet_dma_regs_v1[] = { | |
219 | [DMA_CTRL] = 0x00, | |
220 | [DMA_STATUS] = 0x04, | |
221 | [DMA_SCB_BURST_SIZE] = 0x0C, | |
222 | [DMA_ARB_CTRL] = 0x30, | |
223 | [DMA_PRIORITY] = 0x34, | |
224 | [DMA_RING_PRIORITY] = 0x3C, | |
225 | }; | |
226 | ||
227 | /* Set at runtime once bcmgenet version is known */ | |
228 | static const u8 *bcmgenet_dma_regs; | |
229 | ||
230 | static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) | |
231 | { | |
232 | return netdev_priv(dev_get_drvdata(dev)); | |
233 | } | |
234 | ||
235 | static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, | |
c91b7f66 | 236 | enum dma_reg r) |
1c1008c7 FF |
237 | { |
238 | return __raw_readl(priv->base + GENET_TDMA_REG_OFF + | |
239 | DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); | |
240 | } | |
241 | ||
242 | static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, | |
243 | u32 val, enum dma_reg r) | |
244 | { | |
245 | __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + | |
246 | DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); | |
247 | } | |
248 | ||
249 | static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, | |
c91b7f66 | 250 | enum dma_reg r) |
1c1008c7 FF |
251 | { |
252 | return __raw_readl(priv->base + GENET_RDMA_REG_OFF + | |
253 | DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); | |
254 | } | |
255 | ||
256 | static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, | |
257 | u32 val, enum dma_reg r) | |
258 | { | |
259 | __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + | |
260 | DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); | |
261 | } | |
262 | ||
263 | /* RDMA/TDMA ring registers and accessors | |
264 | * we merge the common fields and just prefix with T/D the registers | |
265 | * having different meaning depending on the direction | |
266 | */ | |
267 | enum dma_ring_reg { | |
268 | TDMA_READ_PTR = 0, | |
269 | RDMA_WRITE_PTR = TDMA_READ_PTR, | |
270 | TDMA_READ_PTR_HI, | |
271 | RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, | |
272 | TDMA_CONS_INDEX, | |
273 | RDMA_PROD_INDEX = TDMA_CONS_INDEX, | |
274 | TDMA_PROD_INDEX, | |
275 | RDMA_CONS_INDEX = TDMA_PROD_INDEX, | |
276 | DMA_RING_BUF_SIZE, | |
277 | DMA_START_ADDR, | |
278 | DMA_START_ADDR_HI, | |
279 | DMA_END_ADDR, | |
280 | DMA_END_ADDR_HI, | |
281 | DMA_MBUF_DONE_THRESH, | |
282 | TDMA_FLOW_PERIOD, | |
283 | RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, | |
284 | TDMA_WRITE_PTR, | |
285 | RDMA_READ_PTR = TDMA_WRITE_PTR, | |
286 | TDMA_WRITE_PTR_HI, | |
287 | RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI | |
288 | }; | |
289 | ||
290 | /* GENET v4 supports 40-bits pointer addressing | |
291 | * for obvious reasons the LO and HI word parts | |
292 | * are contiguous, but this offsets the other | |
293 | * registers. | |
294 | */ | |
295 | static const u8 genet_dma_ring_regs_v4[] = { | |
296 | [TDMA_READ_PTR] = 0x00, | |
297 | [TDMA_READ_PTR_HI] = 0x04, | |
298 | [TDMA_CONS_INDEX] = 0x08, | |
299 | [TDMA_PROD_INDEX] = 0x0C, | |
300 | [DMA_RING_BUF_SIZE] = 0x10, | |
301 | [DMA_START_ADDR] = 0x14, | |
302 | [DMA_START_ADDR_HI] = 0x18, | |
303 | [DMA_END_ADDR] = 0x1C, | |
304 | [DMA_END_ADDR_HI] = 0x20, | |
305 | [DMA_MBUF_DONE_THRESH] = 0x24, | |
306 | [TDMA_FLOW_PERIOD] = 0x28, | |
307 | [TDMA_WRITE_PTR] = 0x2C, | |
308 | [TDMA_WRITE_PTR_HI] = 0x30, | |
309 | }; | |
310 | ||
311 | static const u8 genet_dma_ring_regs_v123[] = { | |
312 | [TDMA_READ_PTR] = 0x00, | |
313 | [TDMA_CONS_INDEX] = 0x04, | |
314 | [TDMA_PROD_INDEX] = 0x08, | |
315 | [DMA_RING_BUF_SIZE] = 0x0C, | |
316 | [DMA_START_ADDR] = 0x10, | |
317 | [DMA_END_ADDR] = 0x14, | |
318 | [DMA_MBUF_DONE_THRESH] = 0x18, | |
319 | [TDMA_FLOW_PERIOD] = 0x1C, | |
320 | [TDMA_WRITE_PTR] = 0x20, | |
321 | }; | |
322 | ||
323 | /* Set at runtime once GENET version is known */ | |
324 | static const u8 *genet_dma_ring_regs; | |
325 | ||
326 | static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, | |
c91b7f66 FF |
327 | unsigned int ring, |
328 | enum dma_ring_reg r) | |
1c1008c7 FF |
329 | { |
330 | return __raw_readl(priv->base + GENET_TDMA_REG_OFF + | |
331 | (DMA_RING_SIZE * ring) + | |
332 | genet_dma_ring_regs[r]); | |
333 | } | |
334 | ||
335 | static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, | |
c91b7f66 FF |
336 | unsigned int ring, u32 val, |
337 | enum dma_ring_reg r) | |
1c1008c7 FF |
338 | { |
339 | __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + | |
340 | (DMA_RING_SIZE * ring) + | |
341 | genet_dma_ring_regs[r]); | |
342 | } | |
343 | ||
344 | static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, | |
c91b7f66 FF |
345 | unsigned int ring, |
346 | enum dma_ring_reg r) | |
1c1008c7 FF |
347 | { |
348 | return __raw_readl(priv->base + GENET_RDMA_REG_OFF + | |
349 | (DMA_RING_SIZE * ring) + | |
350 | genet_dma_ring_regs[r]); | |
351 | } | |
352 | ||
353 | static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, | |
c91b7f66 FF |
354 | unsigned int ring, u32 val, |
355 | enum dma_ring_reg r) | |
1c1008c7 FF |
356 | { |
357 | __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + | |
358 | (DMA_RING_SIZE * ring) + | |
359 | genet_dma_ring_regs[r]); | |
360 | } | |
361 | ||
362 | static int bcmgenet_get_settings(struct net_device *dev, | |
c91b7f66 | 363 | struct ethtool_cmd *cmd) |
1c1008c7 FF |
364 | { |
365 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
366 | ||
367 | if (!netif_running(dev)) | |
368 | return -EINVAL; | |
369 | ||
370 | if (!priv->phydev) | |
371 | return -ENODEV; | |
372 | ||
373 | return phy_ethtool_gset(priv->phydev, cmd); | |
374 | } | |
375 | ||
376 | static int bcmgenet_set_settings(struct net_device *dev, | |
c91b7f66 | 377 | struct ethtool_cmd *cmd) |
1c1008c7 FF |
378 | { |
379 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
380 | ||
381 | if (!netif_running(dev)) | |
382 | return -EINVAL; | |
383 | ||
384 | if (!priv->phydev) | |
385 | return -ENODEV; | |
386 | ||
387 | return phy_ethtool_sset(priv->phydev, cmd); | |
388 | } | |
389 | ||
390 | static int bcmgenet_set_rx_csum(struct net_device *dev, | |
391 | netdev_features_t wanted) | |
392 | { | |
393 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
394 | u32 rbuf_chk_ctrl; | |
395 | bool rx_csum_en; | |
396 | ||
397 | rx_csum_en = !!(wanted & NETIF_F_RXCSUM); | |
398 | ||
399 | rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); | |
400 | ||
401 | /* enable rx checksumming */ | |
402 | if (rx_csum_en) | |
403 | rbuf_chk_ctrl |= RBUF_RXCHK_EN; | |
404 | else | |
405 | rbuf_chk_ctrl &= ~RBUF_RXCHK_EN; | |
406 | priv->desc_rxchk_en = rx_csum_en; | |
ebe5e3c6 FF |
407 | |
408 | /* If UniMAC forwards CRC, we need to skip over it to get | |
409 | * a valid CHK bit to be set in the per-packet status word | |
410 | */ | |
411 | if (rx_csum_en && priv->crc_fwd_en) | |
412 | rbuf_chk_ctrl |= RBUF_SKIP_FCS; | |
413 | else | |
414 | rbuf_chk_ctrl &= ~RBUF_SKIP_FCS; | |
415 | ||
1c1008c7 FF |
416 | bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL); |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
421 | static int bcmgenet_set_tx_csum(struct net_device *dev, | |
422 | netdev_features_t wanted) | |
423 | { | |
424 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
425 | bool desc_64b_en; | |
426 | u32 tbuf_ctrl, rbuf_ctrl; | |
427 | ||
428 | tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv); | |
429 | rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL); | |
430 | ||
431 | desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); | |
432 | ||
433 | /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */ | |
434 | if (desc_64b_en) { | |
435 | tbuf_ctrl |= RBUF_64B_EN; | |
436 | rbuf_ctrl |= RBUF_64B_EN; | |
437 | } else { | |
438 | tbuf_ctrl &= ~RBUF_64B_EN; | |
439 | rbuf_ctrl &= ~RBUF_64B_EN; | |
440 | } | |
441 | priv->desc_64b_en = desc_64b_en; | |
442 | ||
443 | bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl); | |
444 | bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL); | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
449 | static int bcmgenet_set_features(struct net_device *dev, | |
c91b7f66 | 450 | netdev_features_t features) |
1c1008c7 FF |
451 | { |
452 | netdev_features_t changed = features ^ dev->features; | |
453 | netdev_features_t wanted = dev->wanted_features; | |
454 | int ret = 0; | |
455 | ||
456 | if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) | |
457 | ret = bcmgenet_set_tx_csum(dev, wanted); | |
458 | if (changed & (NETIF_F_RXCSUM)) | |
459 | ret = bcmgenet_set_rx_csum(dev, wanted); | |
460 | ||
461 | return ret; | |
462 | } | |
463 | ||
464 | static u32 bcmgenet_get_msglevel(struct net_device *dev) | |
465 | { | |
466 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
467 | ||
468 | return priv->msg_enable; | |
469 | } | |
470 | ||
471 | static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) | |
472 | { | |
473 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
474 | ||
475 | priv->msg_enable = level; | |
476 | } | |
477 | ||
478 | /* standard ethtool support functions. */ | |
479 | enum bcmgenet_stat_type { | |
480 | BCMGENET_STAT_NETDEV = -1, | |
481 | BCMGENET_STAT_MIB_RX, | |
482 | BCMGENET_STAT_MIB_TX, | |
483 | BCMGENET_STAT_RUNT, | |
484 | BCMGENET_STAT_MISC, | |
485 | }; | |
486 | ||
487 | struct bcmgenet_stats { | |
488 | char stat_string[ETH_GSTRING_LEN]; | |
489 | int stat_sizeof; | |
490 | int stat_offset; | |
491 | enum bcmgenet_stat_type type; | |
492 | /* reg offset from UMAC base for misc counters */ | |
493 | u16 reg_offset; | |
494 | }; | |
495 | ||
496 | #define STAT_NETDEV(m) { \ | |
497 | .stat_string = __stringify(m), \ | |
498 | .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ | |
499 | .stat_offset = offsetof(struct net_device_stats, m), \ | |
500 | .type = BCMGENET_STAT_NETDEV, \ | |
501 | } | |
502 | ||
503 | #define STAT_GENET_MIB(str, m, _type) { \ | |
504 | .stat_string = str, \ | |
505 | .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ | |
506 | .stat_offset = offsetof(struct bcmgenet_priv, m), \ | |
507 | .type = _type, \ | |
508 | } | |
509 | ||
510 | #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) | |
511 | #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) | |
512 | #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) | |
513 | ||
514 | #define STAT_GENET_MISC(str, m, offset) { \ | |
515 | .stat_string = str, \ | |
516 | .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ | |
517 | .stat_offset = offsetof(struct bcmgenet_priv, m), \ | |
518 | .type = BCMGENET_STAT_MISC, \ | |
519 | .reg_offset = offset, \ | |
520 | } | |
521 | ||
522 | ||
523 | /* There is a 0xC gap between the end of RX and beginning of TX stats and then | |
524 | * between the end of TX stats and the beginning of the RX RUNT | |
525 | */ | |
526 | #define BCMGENET_STAT_OFFSET 0xc | |
527 | ||
528 | /* Hardware counters must be kept in sync because the order/offset | |
529 | * is important here (order in structure declaration = order in hardware) | |
530 | */ | |
531 | static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { | |
532 | /* general stats */ | |
533 | STAT_NETDEV(rx_packets), | |
534 | STAT_NETDEV(tx_packets), | |
535 | STAT_NETDEV(rx_bytes), | |
536 | STAT_NETDEV(tx_bytes), | |
537 | STAT_NETDEV(rx_errors), | |
538 | STAT_NETDEV(tx_errors), | |
539 | STAT_NETDEV(rx_dropped), | |
540 | STAT_NETDEV(tx_dropped), | |
541 | STAT_NETDEV(multicast), | |
542 | /* UniMAC RSV counters */ | |
543 | STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), | |
544 | STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), | |
545 | STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), | |
546 | STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), | |
547 | STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), | |
548 | STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), | |
549 | STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), | |
550 | STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), | |
551 | STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), | |
552 | STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), | |
553 | STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), | |
554 | STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), | |
555 | STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), | |
556 | STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), | |
557 | STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), | |
558 | STAT_GENET_MIB_RX("rx_control", mib.rx.cf), | |
559 | STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), | |
560 | STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), | |
561 | STAT_GENET_MIB_RX("rx_align", mib.rx.aln), | |
562 | STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), | |
563 | STAT_GENET_MIB_RX("rx_code", mib.rx.cde), | |
564 | STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), | |
565 | STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), | |
566 | STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), | |
567 | STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), | |
568 | STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), | |
569 | STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), | |
570 | STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), | |
571 | STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), | |
572 | /* UniMAC TSV counters */ | |
573 | STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), | |
574 | STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), | |
575 | STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), | |
576 | STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), | |
577 | STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), | |
578 | STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), | |
579 | STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), | |
580 | STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), | |
581 | STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), | |
582 | STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), | |
583 | STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), | |
584 | STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), | |
585 | STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), | |
586 | STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), | |
587 | STAT_GENET_MIB_TX("tx_control", mib.tx.cf), | |
588 | STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), | |
589 | STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), | |
590 | STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), | |
591 | STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), | |
592 | STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), | |
593 | STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), | |
594 | STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), | |
595 | STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), | |
596 | STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), | |
597 | STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), | |
598 | STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), | |
599 | STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), | |
600 | STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), | |
601 | STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), | |
602 | /* UniMAC RUNT counters */ | |
603 | STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), | |
604 | STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), | |
605 | STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), | |
606 | STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), | |
607 | /* Misc UniMAC counters */ | |
608 | STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, | |
609 | UMAC_RBUF_OVFL_CNT), | |
610 | STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT), | |
611 | STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), | |
612 | }; | |
613 | ||
614 | #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) | |
615 | ||
616 | static void bcmgenet_get_drvinfo(struct net_device *dev, | |
c91b7f66 | 617 | struct ethtool_drvinfo *info) |
1c1008c7 FF |
618 | { |
619 | strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); | |
620 | strlcpy(info->version, "v2.0", sizeof(info->version)); | |
621 | info->n_stats = BCMGENET_STATS_LEN; | |
1c1008c7 FF |
622 | } |
623 | ||
624 | static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) | |
625 | { | |
626 | switch (string_set) { | |
627 | case ETH_SS_STATS: | |
628 | return BCMGENET_STATS_LEN; | |
629 | default: | |
630 | return -EOPNOTSUPP; | |
631 | } | |
632 | } | |
633 | ||
c91b7f66 FF |
634 | static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, |
635 | u8 *data) | |
1c1008c7 FF |
636 | { |
637 | int i; | |
638 | ||
639 | switch (stringset) { | |
640 | case ETH_SS_STATS: | |
641 | for (i = 0; i < BCMGENET_STATS_LEN; i++) { | |
642 | memcpy(data + i * ETH_GSTRING_LEN, | |
c91b7f66 FF |
643 | bcmgenet_gstrings_stats[i].stat_string, |
644 | ETH_GSTRING_LEN); | |
1c1008c7 FF |
645 | } |
646 | break; | |
647 | } | |
648 | } | |
649 | ||
650 | static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) | |
651 | { | |
652 | int i, j = 0; | |
653 | ||
654 | for (i = 0; i < BCMGENET_STATS_LEN; i++) { | |
655 | const struct bcmgenet_stats *s; | |
656 | u8 offset = 0; | |
657 | u32 val = 0; | |
658 | char *p; | |
659 | ||
660 | s = &bcmgenet_gstrings_stats[i]; | |
661 | switch (s->type) { | |
662 | case BCMGENET_STAT_NETDEV: | |
663 | continue; | |
664 | case BCMGENET_STAT_MIB_RX: | |
665 | case BCMGENET_STAT_MIB_TX: | |
666 | case BCMGENET_STAT_RUNT: | |
667 | if (s->type != BCMGENET_STAT_MIB_RX) | |
668 | offset = BCMGENET_STAT_OFFSET; | |
c91b7f66 FF |
669 | val = bcmgenet_umac_readl(priv, |
670 | UMAC_MIB_START + j + offset); | |
1c1008c7 FF |
671 | break; |
672 | case BCMGENET_STAT_MISC: | |
673 | val = bcmgenet_umac_readl(priv, s->reg_offset); | |
674 | /* clear if overflowed */ | |
675 | if (val == ~0) | |
676 | bcmgenet_umac_writel(priv, 0, s->reg_offset); | |
677 | break; | |
678 | } | |
679 | ||
680 | j += s->stat_sizeof; | |
681 | p = (char *)priv + s->stat_offset; | |
682 | *(u32 *)p = val; | |
683 | } | |
684 | } | |
685 | ||
686 | static void bcmgenet_get_ethtool_stats(struct net_device *dev, | |
c91b7f66 FF |
687 | struct ethtool_stats *stats, |
688 | u64 *data) | |
1c1008c7 FF |
689 | { |
690 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
691 | int i; | |
692 | ||
693 | if (netif_running(dev)) | |
694 | bcmgenet_update_mib_counters(priv); | |
695 | ||
696 | for (i = 0; i < BCMGENET_STATS_LEN; i++) { | |
697 | const struct bcmgenet_stats *s; | |
698 | char *p; | |
699 | ||
700 | s = &bcmgenet_gstrings_stats[i]; | |
701 | if (s->type == BCMGENET_STAT_NETDEV) | |
702 | p = (char *)&dev->stats; | |
703 | else | |
704 | p = (char *)priv; | |
705 | p += s->stat_offset; | |
706 | data[i] = *(u32 *)p; | |
707 | } | |
708 | } | |
709 | ||
710 | /* standard ethtool support functions. */ | |
711 | static struct ethtool_ops bcmgenet_ethtool_ops = { | |
712 | .get_strings = bcmgenet_get_strings, | |
713 | .get_sset_count = bcmgenet_get_sset_count, | |
714 | .get_ethtool_stats = bcmgenet_get_ethtool_stats, | |
715 | .get_settings = bcmgenet_get_settings, | |
716 | .set_settings = bcmgenet_set_settings, | |
717 | .get_drvinfo = bcmgenet_get_drvinfo, | |
718 | .get_link = ethtool_op_get_link, | |
719 | .get_msglevel = bcmgenet_get_msglevel, | |
720 | .set_msglevel = bcmgenet_set_msglevel, | |
06ba8375 FF |
721 | .get_wol = bcmgenet_get_wol, |
722 | .set_wol = bcmgenet_set_wol, | |
1c1008c7 FF |
723 | }; |
724 | ||
725 | /* Power down the unimac, based on mode. */ | |
726 | static void bcmgenet_power_down(struct bcmgenet_priv *priv, | |
727 | enum bcmgenet_power_mode mode) | |
728 | { | |
729 | u32 reg; | |
730 | ||
731 | switch (mode) { | |
732 | case GENET_POWER_CABLE_SENSE: | |
80d8e96d | 733 | phy_detach(priv->phydev); |
1c1008c7 FF |
734 | break; |
735 | ||
c3ae64ae FF |
736 | case GENET_POWER_WOL_MAGIC: |
737 | bcmgenet_wol_power_down_cfg(priv, mode); | |
738 | break; | |
739 | ||
1c1008c7 FF |
740 | case GENET_POWER_PASSIVE: |
741 | /* Power down LED */ | |
742 | bcmgenet_mii_reset(priv->dev); | |
743 | if (priv->hw_params->flags & GENET_HAS_EXT) { | |
744 | reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); | |
745 | reg |= (EXT_PWR_DOWN_PHY | | |
746 | EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); | |
747 | bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); | |
748 | } | |
749 | break; | |
750 | default: | |
751 | break; | |
752 | } | |
753 | } | |
754 | ||
755 | static void bcmgenet_power_up(struct bcmgenet_priv *priv, | |
c91b7f66 | 756 | enum bcmgenet_power_mode mode) |
1c1008c7 FF |
757 | { |
758 | u32 reg; | |
759 | ||
760 | if (!(priv->hw_params->flags & GENET_HAS_EXT)) | |
761 | return; | |
762 | ||
763 | reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); | |
764 | ||
765 | switch (mode) { | |
766 | case GENET_POWER_PASSIVE: | |
767 | reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY | | |
768 | EXT_PWR_DOWN_BIAS); | |
769 | /* fallthrough */ | |
770 | case GENET_POWER_CABLE_SENSE: | |
771 | /* enable APD */ | |
772 | reg |= EXT_PWR_DN_EN_LD; | |
773 | break; | |
c3ae64ae FF |
774 | case GENET_POWER_WOL_MAGIC: |
775 | bcmgenet_wol_power_up_cfg(priv, mode); | |
776 | return; | |
1c1008c7 FF |
777 | default: |
778 | break; | |
779 | } | |
780 | ||
781 | bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); | |
782 | bcmgenet_mii_reset(priv->dev); | |
783 | } | |
784 | ||
785 | /* ioctl handle special commands that are not present in ethtool. */ | |
786 | static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
787 | { | |
788 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
789 | int val = 0; | |
790 | ||
791 | if (!netif_running(dev)) | |
792 | return -EINVAL; | |
793 | ||
794 | switch (cmd) { | |
795 | case SIOCGMIIPHY: | |
796 | case SIOCGMIIREG: | |
797 | case SIOCSMIIREG: | |
798 | if (!priv->phydev) | |
799 | val = -ENODEV; | |
800 | else | |
801 | val = phy_mii_ioctl(priv->phydev, rq, cmd); | |
802 | break; | |
803 | ||
804 | default: | |
805 | val = -EINVAL; | |
806 | break; | |
807 | } | |
808 | ||
809 | return val; | |
810 | } | |
811 | ||
812 | static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, | |
813 | struct bcmgenet_tx_ring *ring) | |
814 | { | |
815 | struct enet_cb *tx_cb_ptr; | |
816 | ||
817 | tx_cb_ptr = ring->cbs; | |
818 | tx_cb_ptr += ring->write_ptr - ring->cb_ptr; | |
819 | tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE; | |
820 | /* Advancing local write pointer */ | |
821 | if (ring->write_ptr == ring->end_ptr) | |
822 | ring->write_ptr = ring->cb_ptr; | |
823 | else | |
824 | ring->write_ptr++; | |
825 | ||
826 | return tx_cb_ptr; | |
827 | } | |
828 | ||
829 | /* Simple helper to free a control block's resources */ | |
830 | static void bcmgenet_free_cb(struct enet_cb *cb) | |
831 | { | |
832 | dev_kfree_skb_any(cb->skb); | |
833 | cb->skb = NULL; | |
834 | dma_unmap_addr_set(cb, dma_addr, 0); | |
835 | } | |
836 | ||
837 | static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv, | |
838 | struct bcmgenet_tx_ring *ring) | |
839 | { | |
840 | bcmgenet_intrl2_0_writel(priv, | |
c91b7f66 FF |
841 | UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE, |
842 | INTRL2_CPU_MASK_SET); | |
1c1008c7 FF |
843 | } |
844 | ||
845 | static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv, | |
846 | struct bcmgenet_tx_ring *ring) | |
847 | { | |
848 | bcmgenet_intrl2_0_writel(priv, | |
c91b7f66 FF |
849 | UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE, |
850 | INTRL2_CPU_MASK_CLEAR); | |
1c1008c7 FF |
851 | } |
852 | ||
853 | static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv, | |
c91b7f66 | 854 | struct bcmgenet_tx_ring *ring) |
1c1008c7 | 855 | { |
c91b7f66 FF |
856 | bcmgenet_intrl2_1_writel(priv, (1 << ring->index), |
857 | INTRL2_CPU_MASK_CLEAR); | |
1c1008c7 FF |
858 | priv->int1_mask &= ~(1 << ring->index); |
859 | } | |
860 | ||
861 | static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv, | |
862 | struct bcmgenet_tx_ring *ring) | |
863 | { | |
c91b7f66 FF |
864 | bcmgenet_intrl2_1_writel(priv, (1 << ring->index), |
865 | INTRL2_CPU_MASK_SET); | |
1c1008c7 FF |
866 | priv->int1_mask |= (1 << ring->index); |
867 | } | |
868 | ||
869 | /* Unlocked version of the reclaim routine */ | |
870 | static void __bcmgenet_tx_reclaim(struct net_device *dev, | |
c91b7f66 | 871 | struct bcmgenet_tx_ring *ring) |
1c1008c7 FF |
872 | { |
873 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
874 | int last_tx_cn, last_c_index, num_tx_bds; | |
875 | struct enet_cb *tx_cb_ptr; | |
b2cde2cc | 876 | struct netdev_queue *txq; |
1c1008c7 FF |
877 | unsigned int c_index; |
878 | ||
879 | /* Compute how many buffers are transmited since last xmit call */ | |
880 | c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); | |
b2cde2cc | 881 | txq = netdev_get_tx_queue(dev, ring->queue); |
1c1008c7 FF |
882 | |
883 | last_c_index = ring->c_index; | |
884 | num_tx_bds = ring->size; | |
885 | ||
886 | c_index &= (num_tx_bds - 1); | |
887 | ||
888 | if (c_index >= last_c_index) | |
889 | last_tx_cn = c_index - last_c_index; | |
890 | else | |
891 | last_tx_cn = num_tx_bds - last_c_index + c_index; | |
892 | ||
893 | netif_dbg(priv, tx_done, dev, | |
c91b7f66 FF |
894 | "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n", |
895 | __func__, ring->index, | |
896 | c_index, last_tx_cn, last_c_index); | |
1c1008c7 FF |
897 | |
898 | /* Reclaim transmitted buffers */ | |
899 | while (last_tx_cn-- > 0) { | |
900 | tx_cb_ptr = ring->cbs + last_c_index; | |
901 | if (tx_cb_ptr->skb) { | |
902 | dev->stats.tx_bytes += tx_cb_ptr->skb->len; | |
903 | dma_unmap_single(&dev->dev, | |
c91b7f66 FF |
904 | dma_unmap_addr(tx_cb_ptr, dma_addr), |
905 | tx_cb_ptr->skb->len, | |
906 | DMA_TO_DEVICE); | |
1c1008c7 FF |
907 | bcmgenet_free_cb(tx_cb_ptr); |
908 | } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) { | |
909 | dev->stats.tx_bytes += | |
910 | dma_unmap_len(tx_cb_ptr, dma_len); | |
911 | dma_unmap_page(&dev->dev, | |
c91b7f66 FF |
912 | dma_unmap_addr(tx_cb_ptr, dma_addr), |
913 | dma_unmap_len(tx_cb_ptr, dma_len), | |
914 | DMA_TO_DEVICE); | |
1c1008c7 FF |
915 | dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0); |
916 | } | |
917 | dev->stats.tx_packets++; | |
918 | ring->free_bds += 1; | |
919 | ||
920 | last_c_index++; | |
921 | last_c_index &= (num_tx_bds - 1); | |
922 | } | |
923 | ||
924 | if (ring->free_bds > (MAX_SKB_FRAGS + 1)) | |
925 | ring->int_disable(priv, ring); | |
926 | ||
b2cde2cc FF |
927 | if (netif_tx_queue_stopped(txq)) |
928 | netif_tx_wake_queue(txq); | |
1c1008c7 FF |
929 | |
930 | ring->c_index = c_index; | |
931 | } | |
932 | ||
933 | static void bcmgenet_tx_reclaim(struct net_device *dev, | |
c91b7f66 | 934 | struct bcmgenet_tx_ring *ring) |
1c1008c7 FF |
935 | { |
936 | unsigned long flags; | |
937 | ||
938 | spin_lock_irqsave(&ring->lock, flags); | |
939 | __bcmgenet_tx_reclaim(dev, ring); | |
940 | spin_unlock_irqrestore(&ring->lock, flags); | |
941 | } | |
942 | ||
943 | static void bcmgenet_tx_reclaim_all(struct net_device *dev) | |
944 | { | |
945 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
946 | int i; | |
947 | ||
948 | if (netif_is_multiqueue(dev)) { | |
949 | for (i = 0; i < priv->hw_params->tx_queues; i++) | |
950 | bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); | |
951 | } | |
952 | ||
953 | bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); | |
954 | } | |
955 | ||
956 | /* Transmits a single SKB (either head of a fragment or a single SKB) | |
957 | * caller must hold priv->lock | |
958 | */ | |
959 | static int bcmgenet_xmit_single(struct net_device *dev, | |
960 | struct sk_buff *skb, | |
961 | u16 dma_desc_flags, | |
962 | struct bcmgenet_tx_ring *ring) | |
963 | { | |
964 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
965 | struct device *kdev = &priv->pdev->dev; | |
966 | struct enet_cb *tx_cb_ptr; | |
967 | unsigned int skb_len; | |
968 | dma_addr_t mapping; | |
969 | u32 length_status; | |
970 | int ret; | |
971 | ||
972 | tx_cb_ptr = bcmgenet_get_txcb(priv, ring); | |
973 | ||
974 | if (unlikely(!tx_cb_ptr)) | |
975 | BUG(); | |
976 | ||
977 | tx_cb_ptr->skb = skb; | |
978 | ||
979 | skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb); | |
980 | ||
981 | mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); | |
982 | ret = dma_mapping_error(kdev, mapping); | |
983 | if (ret) { | |
984 | netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); | |
985 | dev_kfree_skb(skb); | |
986 | return ret; | |
987 | } | |
988 | ||
989 | dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); | |
990 | dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len); | |
991 | length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags | | |
992 | (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) | | |
993 | DMA_TX_APPEND_CRC; | |
994 | ||
995 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
996 | length_status |= DMA_TX_DO_CSUM; | |
997 | ||
998 | dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status); | |
999 | ||
1000 | /* Decrement total BD count and advance our write pointer */ | |
1001 | ring->free_bds -= 1; | |
1002 | ring->prod_index += 1; | |
1003 | ring->prod_index &= DMA_P_INDEX_MASK; | |
1004 | ||
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | /* Transmit a SKB fragement */ | |
1009 | static int bcmgenet_xmit_frag(struct net_device *dev, | |
c91b7f66 FF |
1010 | skb_frag_t *frag, |
1011 | u16 dma_desc_flags, | |
1012 | struct bcmgenet_tx_ring *ring) | |
1c1008c7 FF |
1013 | { |
1014 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
1015 | struct device *kdev = &priv->pdev->dev; | |
1016 | struct enet_cb *tx_cb_ptr; | |
1017 | dma_addr_t mapping; | |
1018 | int ret; | |
1019 | ||
1020 | tx_cb_ptr = bcmgenet_get_txcb(priv, ring); | |
1021 | ||
1022 | if (unlikely(!tx_cb_ptr)) | |
1023 | BUG(); | |
1024 | tx_cb_ptr->skb = NULL; | |
1025 | ||
1026 | mapping = skb_frag_dma_map(kdev, frag, 0, | |
c91b7f66 | 1027 | skb_frag_size(frag), DMA_TO_DEVICE); |
1c1008c7 FF |
1028 | ret = dma_mapping_error(kdev, mapping); |
1029 | if (ret) { | |
1030 | netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n", | |
c91b7f66 | 1031 | __func__); |
1c1008c7 FF |
1032 | return ret; |
1033 | } | |
1034 | ||
1035 | dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); | |
1036 | dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size); | |
1037 | ||
1038 | dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, | |
c91b7f66 FF |
1039 | (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags | |
1040 | (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT)); | |
1c1008c7 FF |
1041 | |
1042 | ||
1043 | ring->free_bds -= 1; | |
1044 | ring->prod_index += 1; | |
1045 | ring->prod_index &= DMA_P_INDEX_MASK; | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | /* Reallocate the SKB to put enough headroom in front of it and insert | |
1051 | * the transmit checksum offsets in the descriptors | |
1052 | */ | |
1053 | static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb) | |
1054 | { | |
1055 | struct status_64 *status = NULL; | |
1056 | struct sk_buff *new_skb; | |
1057 | u16 offset; | |
1058 | u8 ip_proto; | |
1059 | u16 ip_ver; | |
1060 | u32 tx_csum_info; | |
1061 | ||
1062 | if (unlikely(skb_headroom(skb) < sizeof(*status))) { | |
1063 | /* If 64 byte status block enabled, must make sure skb has | |
1064 | * enough headroom for us to insert 64B status block. | |
1065 | */ | |
1066 | new_skb = skb_realloc_headroom(skb, sizeof(*status)); | |
1067 | dev_kfree_skb(skb); | |
1068 | if (!new_skb) { | |
1069 | dev->stats.tx_errors++; | |
1070 | dev->stats.tx_dropped++; | |
1071 | return -ENOMEM; | |
1072 | } | |
1073 | skb = new_skb; | |
1074 | } | |
1075 | ||
1076 | skb_push(skb, sizeof(*status)); | |
1077 | status = (struct status_64 *)skb->data; | |
1078 | ||
1079 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1080 | ip_ver = htons(skb->protocol); | |
1081 | switch (ip_ver) { | |
1082 | case ETH_P_IP: | |
1083 | ip_proto = ip_hdr(skb)->protocol; | |
1084 | break; | |
1085 | case ETH_P_IPV6: | |
1086 | ip_proto = ipv6_hdr(skb)->nexthdr; | |
1087 | break; | |
1088 | default: | |
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | offset = skb_checksum_start_offset(skb) - sizeof(*status); | |
1093 | tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | | |
1094 | (offset + skb->csum_offset); | |
1095 | ||
1096 | /* Set the length valid bit for TCP and UDP and just set | |
1097 | * the special UDP flag for IPv4, else just set to 0. | |
1098 | */ | |
1099 | if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { | |
1100 | tx_csum_info |= STATUS_TX_CSUM_LV; | |
1101 | if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) | |
1102 | tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; | |
8900ea57 | 1103 | } else { |
1c1008c7 | 1104 | tx_csum_info = 0; |
8900ea57 | 1105 | } |
1c1008c7 FF |
1106 | |
1107 | status->tx_csum_info = tx_csum_info; | |
1108 | } | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) | |
1114 | { | |
1115 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
1116 | struct bcmgenet_tx_ring *ring = NULL; | |
b2cde2cc | 1117 | struct netdev_queue *txq; |
1c1008c7 FF |
1118 | unsigned long flags = 0; |
1119 | int nr_frags, index; | |
1120 | u16 dma_desc_flags; | |
1121 | int ret; | |
1122 | int i; | |
1123 | ||
1124 | index = skb_get_queue_mapping(skb); | |
1125 | /* Mapping strategy: | |
1126 | * queue_mapping = 0, unclassified, packet xmited through ring16 | |
1127 | * queue_mapping = 1, goes to ring 0. (highest priority queue | |
1128 | * queue_mapping = 2, goes to ring 1. | |
1129 | * queue_mapping = 3, goes to ring 2. | |
1130 | * queue_mapping = 4, goes to ring 3. | |
1131 | */ | |
1132 | if (index == 0) | |
1133 | index = DESC_INDEX; | |
1134 | else | |
1135 | index -= 1; | |
1136 | ||
1c1008c7 FF |
1137 | nr_frags = skb_shinfo(skb)->nr_frags; |
1138 | ring = &priv->tx_rings[index]; | |
b2cde2cc | 1139 | txq = netdev_get_tx_queue(dev, ring->queue); |
1c1008c7 FF |
1140 | |
1141 | spin_lock_irqsave(&ring->lock, flags); | |
1142 | if (ring->free_bds <= nr_frags + 1) { | |
b2cde2cc | 1143 | netif_tx_stop_queue(txq); |
1c1008c7 | 1144 | netdev_err(dev, "%s: tx ring %d full when queue %d awake\n", |
c91b7f66 | 1145 | __func__, index, ring->queue); |
1c1008c7 FF |
1146 | ret = NETDEV_TX_BUSY; |
1147 | goto out; | |
1148 | } | |
1149 | ||
1c1008c7 FF |
1150 | /* set the SKB transmit checksum */ |
1151 | if (priv->desc_64b_en) { | |
1152 | ret = bcmgenet_put_tx_csum(dev, skb); | |
1153 | if (ret) { | |
1154 | ret = NETDEV_TX_OK; | |
1155 | goto out; | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | dma_desc_flags = DMA_SOP; | |
1160 | if (nr_frags == 0) | |
1161 | dma_desc_flags |= DMA_EOP; | |
1162 | ||
1163 | /* Transmit single SKB or head of fragment list */ | |
1164 | ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring); | |
1165 | if (ret) { | |
1166 | ret = NETDEV_TX_OK; | |
1167 | goto out; | |
1168 | } | |
1169 | ||
1170 | /* xmit fragment */ | |
1171 | for (i = 0; i < nr_frags; i++) { | |
1172 | ret = bcmgenet_xmit_frag(dev, | |
c91b7f66 FF |
1173 | &skb_shinfo(skb)->frags[i], |
1174 | (i == nr_frags - 1) ? DMA_EOP : 0, | |
1175 | ring); | |
1c1008c7 FF |
1176 | if (ret) { |
1177 | ret = NETDEV_TX_OK; | |
1178 | goto out; | |
1179 | } | |
1180 | } | |
1181 | ||
d03825fb FF |
1182 | skb_tx_timestamp(skb); |
1183 | ||
1c1008c7 FF |
1184 | /* we kept a software copy of how much we should advance the TDMA |
1185 | * producer index, now write it down to the hardware | |
1186 | */ | |
1187 | bcmgenet_tdma_ring_writel(priv, ring->index, | |
c91b7f66 | 1188 | ring->prod_index, TDMA_PROD_INDEX); |
1c1008c7 FF |
1189 | |
1190 | if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) { | |
b2cde2cc | 1191 | netif_tx_stop_queue(txq); |
1c1008c7 FF |
1192 | ring->int_enable(priv, ring); |
1193 | } | |
1194 | ||
1195 | out: | |
1196 | spin_unlock_irqrestore(&ring->lock, flags); | |
1197 | ||
1198 | return ret; | |
1199 | } | |
1200 | ||
1201 | ||
c91b7f66 | 1202 | static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb) |
1c1008c7 FF |
1203 | { |
1204 | struct device *kdev = &priv->pdev->dev; | |
1205 | struct sk_buff *skb; | |
1206 | dma_addr_t mapping; | |
1207 | int ret; | |
1208 | ||
c91b7f66 | 1209 | skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT); |
1c1008c7 FF |
1210 | if (!skb) |
1211 | return -ENOMEM; | |
1212 | ||
1213 | /* a caller did not release this control block */ | |
1214 | WARN_ON(cb->skb != NULL); | |
1215 | cb->skb = skb; | |
1216 | mapping = dma_map_single(kdev, skb->data, | |
c91b7f66 | 1217 | priv->rx_buf_len, DMA_FROM_DEVICE); |
1c1008c7 FF |
1218 | ret = dma_mapping_error(kdev, mapping); |
1219 | if (ret) { | |
1220 | bcmgenet_free_cb(cb); | |
1221 | netif_err(priv, rx_err, priv->dev, | |
c91b7f66 | 1222 | "%s DMA map failed\n", __func__); |
1c1008c7 FF |
1223 | return ret; |
1224 | } | |
1225 | ||
1226 | dma_unmap_addr_set(cb, dma_addr, mapping); | |
1227 | /* assign packet, prepare descriptor, and advance pointer */ | |
1228 | ||
1229 | dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping); | |
1230 | ||
1231 | /* turn on the newly assigned BD for DMA to use */ | |
1232 | priv->rx_bd_assign_index++; | |
1233 | priv->rx_bd_assign_index &= (priv->num_rx_bds - 1); | |
1234 | ||
1235 | priv->rx_bd_assign_ptr = priv->rx_bds + | |
1236 | (priv->rx_bd_assign_index * DMA_DESC_SIZE); | |
1237 | ||
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | /* bcmgenet_desc_rx - descriptor based rx process. | |
1242 | * this could be called from bottom half, or from NAPI polling method. | |
1243 | */ | |
1244 | static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv, | |
1245 | unsigned int budget) | |
1246 | { | |
1247 | struct net_device *dev = priv->dev; | |
1248 | struct enet_cb *cb; | |
1249 | struct sk_buff *skb; | |
1250 | u32 dma_length_status; | |
1251 | unsigned long dma_flag; | |
1252 | int len, err; | |
1253 | unsigned int rxpktprocessed = 0, rxpkttoprocess; | |
1254 | unsigned int p_index; | |
1255 | unsigned int chksum_ok = 0; | |
1256 | ||
c91b7f66 | 1257 | p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX); |
1c1008c7 FF |
1258 | p_index &= DMA_P_INDEX_MASK; |
1259 | ||
1260 | if (p_index < priv->rx_c_index) | |
1261 | rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - | |
1262 | priv->rx_c_index + p_index; | |
1263 | else | |
1264 | rxpkttoprocess = p_index - priv->rx_c_index; | |
1265 | ||
1266 | netif_dbg(priv, rx_status, dev, | |
c91b7f66 | 1267 | "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); |
1c1008c7 FF |
1268 | |
1269 | while ((rxpktprocessed < rxpkttoprocess) && | |
c91b7f66 | 1270 | (rxpktprocessed < budget)) { |
1c1008c7 FF |
1271 | /* Unmap the packet contents such that we can use the |
1272 | * RSV from the 64 bytes descriptor when enabled and save | |
1273 | * a 32-bits register read | |
1274 | */ | |
1275 | cb = &priv->rx_cbs[priv->rx_read_ptr]; | |
1276 | skb = cb->skb; | |
1277 | dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr), | |
c91b7f66 | 1278 | priv->rx_buf_len, DMA_FROM_DEVICE); |
1c1008c7 FF |
1279 | |
1280 | if (!priv->desc_64b_en) { | |
c91b7f66 FF |
1281 | dma_length_status = |
1282 | dmadesc_get_length_status(priv, | |
1283 | priv->rx_bds + | |
1284 | (priv->rx_read_ptr * | |
1285 | DMA_DESC_SIZE)); | |
1c1008c7 FF |
1286 | } else { |
1287 | struct status_64 *status; | |
164d4f20 | 1288 | |
1c1008c7 FF |
1289 | status = (struct status_64 *)skb->data; |
1290 | dma_length_status = status->length_status; | |
1291 | } | |
1292 | ||
1293 | /* DMA flags and length are still valid no matter how | |
1294 | * we got the Receive Status Vector (64B RSB or register) | |
1295 | */ | |
1296 | dma_flag = dma_length_status & 0xffff; | |
1297 | len = dma_length_status >> DMA_BUFLENGTH_SHIFT; | |
1298 | ||
1299 | netif_dbg(priv, rx_status, dev, | |
c91b7f66 FF |
1300 | "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", |
1301 | __func__, p_index, priv->rx_c_index, | |
1302 | priv->rx_read_ptr, dma_length_status); | |
1c1008c7 FF |
1303 | |
1304 | rxpktprocessed++; | |
1305 | ||
1306 | priv->rx_read_ptr++; | |
1307 | priv->rx_read_ptr &= (priv->num_rx_bds - 1); | |
1308 | ||
1309 | /* out of memory, just drop packets at the hardware level */ | |
1310 | if (unlikely(!skb)) { | |
1311 | dev->stats.rx_dropped++; | |
1312 | dev->stats.rx_errors++; | |
1313 | goto refill; | |
1314 | } | |
1315 | ||
1316 | if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { | |
1317 | netif_err(priv, rx_status, dev, | |
c91b7f66 | 1318 | "dropping fragmented packet!\n"); |
1c1008c7 FF |
1319 | dev->stats.rx_dropped++; |
1320 | dev->stats.rx_errors++; | |
1321 | dev_kfree_skb_any(cb->skb); | |
1322 | cb->skb = NULL; | |
1323 | goto refill; | |
1324 | } | |
1325 | /* report errors */ | |
1326 | if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | | |
1327 | DMA_RX_OV | | |
1328 | DMA_RX_NO | | |
1329 | DMA_RX_LG | | |
1330 | DMA_RX_RXER))) { | |
1331 | netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", | |
c91b7f66 | 1332 | (unsigned int)dma_flag); |
1c1008c7 FF |
1333 | if (dma_flag & DMA_RX_CRC_ERROR) |
1334 | dev->stats.rx_crc_errors++; | |
1335 | if (dma_flag & DMA_RX_OV) | |
1336 | dev->stats.rx_over_errors++; | |
1337 | if (dma_flag & DMA_RX_NO) | |
1338 | dev->stats.rx_frame_errors++; | |
1339 | if (dma_flag & DMA_RX_LG) | |
1340 | dev->stats.rx_length_errors++; | |
1341 | dev->stats.rx_dropped++; | |
1342 | dev->stats.rx_errors++; | |
1343 | ||
1344 | /* discard the packet and advance consumer index.*/ | |
1345 | dev_kfree_skb_any(cb->skb); | |
1346 | cb->skb = NULL; | |
1347 | goto refill; | |
1348 | } /* error packet */ | |
1349 | ||
1350 | chksum_ok = (dma_flag & priv->dma_rx_chk_bit) && | |
c91b7f66 | 1351 | priv->desc_rxchk_en; |
1c1008c7 FF |
1352 | |
1353 | skb_put(skb, len); | |
1354 | if (priv->desc_64b_en) { | |
1355 | skb_pull(skb, 64); | |
1356 | len -= 64; | |
1357 | } | |
1358 | ||
1359 | if (likely(chksum_ok)) | |
1360 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1361 | ||
1362 | /* remove hardware 2bytes added for IP alignment */ | |
1363 | skb_pull(skb, 2); | |
1364 | len -= 2; | |
1365 | ||
1366 | if (priv->crc_fwd_en) { | |
1367 | skb_trim(skb, len - ETH_FCS_LEN); | |
1368 | len -= ETH_FCS_LEN; | |
1369 | } | |
1370 | ||
1371 | /*Finish setting up the received SKB and send it to the kernel*/ | |
1372 | skb->protocol = eth_type_trans(skb, priv->dev); | |
1373 | dev->stats.rx_packets++; | |
1374 | dev->stats.rx_bytes += len; | |
1375 | if (dma_flag & DMA_RX_MULT) | |
1376 | dev->stats.multicast++; | |
1377 | ||
1378 | /* Notify kernel */ | |
1379 | napi_gro_receive(&priv->napi, skb); | |
1380 | cb->skb = NULL; | |
1381 | netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); | |
1382 | ||
1383 | /* refill RX path on the current control block */ | |
1384 | refill: | |
1385 | err = bcmgenet_rx_refill(priv, cb); | |
1386 | if (err) | |
1387 | netif_err(priv, rx_err, dev, "Rx refill failed\n"); | |
1388 | } | |
1389 | ||
1390 | return rxpktprocessed; | |
1391 | } | |
1392 | ||
1393 | /* Assign skb to RX DMA descriptor. */ | |
1394 | static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv) | |
1395 | { | |
1396 | struct enet_cb *cb; | |
1397 | int ret = 0; | |
1398 | int i; | |
1399 | ||
1400 | netif_dbg(priv, hw, priv->dev, "%s:\n", __func__); | |
1401 | ||
1402 | /* loop here for each buffer needing assign */ | |
1403 | for (i = 0; i < priv->num_rx_bds; i++) { | |
1404 | cb = &priv->rx_cbs[priv->rx_bd_assign_index]; | |
1405 | if (cb->skb) | |
1406 | continue; | |
1407 | ||
1c1008c7 FF |
1408 | ret = bcmgenet_rx_refill(priv, cb); |
1409 | if (ret) | |
1410 | break; | |
1c1008c7 FF |
1411 | } |
1412 | ||
1413 | return ret; | |
1414 | } | |
1415 | ||
1416 | static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) | |
1417 | { | |
1418 | struct enet_cb *cb; | |
1419 | int i; | |
1420 | ||
1421 | for (i = 0; i < priv->num_rx_bds; i++) { | |
1422 | cb = &priv->rx_cbs[i]; | |
1423 | ||
1424 | if (dma_unmap_addr(cb, dma_addr)) { | |
1425 | dma_unmap_single(&priv->dev->dev, | |
c91b7f66 FF |
1426 | dma_unmap_addr(cb, dma_addr), |
1427 | priv->rx_buf_len, DMA_FROM_DEVICE); | |
1c1008c7 FF |
1428 | dma_unmap_addr_set(cb, dma_addr, 0); |
1429 | } | |
1430 | ||
1431 | if (cb->skb) | |
1432 | bcmgenet_free_cb(cb); | |
1433 | } | |
1434 | } | |
1435 | ||
c91b7f66 | 1436 | static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) |
e29585b8 FF |
1437 | { |
1438 | u32 reg; | |
1439 | ||
1440 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); | |
1441 | if (enable) | |
1442 | reg |= mask; | |
1443 | else | |
1444 | reg &= ~mask; | |
1445 | bcmgenet_umac_writel(priv, reg, UMAC_CMD); | |
1446 | ||
1447 | /* UniMAC stops on a packet boundary, wait for a full-size packet | |
1448 | * to be processed | |
1449 | */ | |
1450 | if (enable == 0) | |
1451 | usleep_range(1000, 2000); | |
1452 | } | |
1453 | ||
1c1008c7 FF |
1454 | static int reset_umac(struct bcmgenet_priv *priv) |
1455 | { | |
1456 | struct device *kdev = &priv->pdev->dev; | |
1457 | unsigned int timeout = 0; | |
1458 | u32 reg; | |
1459 | ||
1460 | /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ | |
1461 | bcmgenet_rbuf_ctrl_set(priv, 0); | |
1462 | udelay(10); | |
1463 | ||
1464 | /* disable MAC while updating its registers */ | |
1465 | bcmgenet_umac_writel(priv, 0, UMAC_CMD); | |
1466 | ||
1467 | /* issue soft reset, wait for it to complete */ | |
1468 | bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); | |
1469 | while (timeout++ < 1000) { | |
1470 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); | |
1471 | if (!(reg & CMD_SW_RESET)) | |
1472 | return 0; | |
1473 | ||
1474 | udelay(1); | |
1475 | } | |
1476 | ||
1477 | if (timeout == 1000) { | |
1478 | dev_err(kdev, | |
1479 | "timeout waiting for MAC to come out of resetn\n"); | |
1480 | return -ETIMEDOUT; | |
1481 | } | |
1482 | ||
1483 | return 0; | |
1484 | } | |
1485 | ||
909ff5ef FF |
1486 | static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) |
1487 | { | |
1488 | /* Mask all interrupts.*/ | |
1489 | bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); | |
1490 | bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); | |
1491 | bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); | |
1492 | bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); | |
1493 | bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); | |
1494 | bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); | |
1495 | } | |
1496 | ||
1c1008c7 FF |
1497 | static int init_umac(struct bcmgenet_priv *priv) |
1498 | { | |
1499 | struct device *kdev = &priv->pdev->dev; | |
1500 | int ret; | |
1501 | u32 reg, cpu_mask_clear; | |
1502 | ||
1503 | dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); | |
1504 | ||
1505 | ret = reset_umac(priv); | |
1506 | if (ret) | |
1507 | return ret; | |
1508 | ||
1509 | bcmgenet_umac_writel(priv, 0, UMAC_CMD); | |
1510 | /* clear tx/rx counter */ | |
1511 | bcmgenet_umac_writel(priv, | |
c91b7f66 FF |
1512 | MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, |
1513 | UMAC_MIB_CTRL); | |
1c1008c7 FF |
1514 | bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); |
1515 | ||
1516 | bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); | |
1517 | ||
1518 | /* init rx registers, enable ip header optimization */ | |
1519 | reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); | |
1520 | reg |= RBUF_ALIGN_2B; | |
1521 | bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); | |
1522 | ||
1523 | if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) | |
1524 | bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); | |
1525 | ||
909ff5ef | 1526 | bcmgenet_intr_disable(priv); |
1c1008c7 FF |
1527 | |
1528 | cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE; | |
1529 | ||
1530 | dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__); | |
1531 | ||
1532 | /* Monitor cable plug/unpluged event for internal PHY */ | |
8900ea57 | 1533 | if (phy_is_internal(priv->phydev)) { |
1c1008c7 | 1534 | cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP); |
8900ea57 | 1535 | } else if (priv->ext_phy) { |
1c1008c7 | 1536 | cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP); |
8900ea57 | 1537 | } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { |
1c1008c7 FF |
1538 | reg = bcmgenet_bp_mc_get(priv); |
1539 | reg |= BIT(priv->hw_params->bp_in_en_shift); | |
1540 | ||
1541 | /* bp_mask: back pressure mask */ | |
1542 | if (netif_is_multiqueue(priv->dev)) | |
1543 | reg |= priv->hw_params->bp_in_mask; | |
1544 | else | |
1545 | reg &= ~priv->hw_params->bp_in_mask; | |
1546 | bcmgenet_bp_mc_set(priv, reg); | |
1547 | } | |
1548 | ||
1549 | /* Enable MDIO interrupts on GENET v3+ */ | |
1550 | if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) | |
1551 | cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR; | |
1552 | ||
c91b7f66 | 1553 | bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR); |
1c1008c7 FF |
1554 | |
1555 | /* Enable rx/tx engine.*/ | |
1556 | dev_dbg(kdev, "done init umac\n"); | |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
1561 | /* Initialize all house-keeping variables for a TX ring, along | |
1562 | * with corresponding hardware registers | |
1563 | */ | |
1564 | static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, | |
1565 | unsigned int index, unsigned int size, | |
1566 | unsigned int write_ptr, unsigned int end_ptr) | |
1567 | { | |
1568 | struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; | |
1569 | u32 words_per_bd = WORDS_PER_BD(priv); | |
1570 | u32 flow_period_val = 0; | |
1571 | unsigned int first_bd; | |
1572 | ||
1573 | spin_lock_init(&ring->lock); | |
1574 | ring->index = index; | |
1575 | if (index == DESC_INDEX) { | |
1576 | ring->queue = 0; | |
1577 | ring->int_enable = bcmgenet_tx_ring16_int_enable; | |
1578 | ring->int_disable = bcmgenet_tx_ring16_int_disable; | |
1579 | } else { | |
1580 | ring->queue = index + 1; | |
1581 | ring->int_enable = bcmgenet_tx_ring_int_enable; | |
1582 | ring->int_disable = bcmgenet_tx_ring_int_disable; | |
1583 | } | |
1584 | ring->cbs = priv->tx_cbs + write_ptr; | |
1585 | ring->size = size; | |
1586 | ring->c_index = 0; | |
1587 | ring->free_bds = size; | |
1588 | ring->write_ptr = write_ptr; | |
1589 | ring->cb_ptr = write_ptr; | |
1590 | ring->end_ptr = end_ptr - 1; | |
1591 | ring->prod_index = 0; | |
1592 | ||
1593 | /* Set flow period for ring != 16 */ | |
1594 | if (index != DESC_INDEX) | |
1595 | flow_period_val = ENET_MAX_MTU_SIZE << 16; | |
1596 | ||
1597 | bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); | |
1598 | bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); | |
1599 | bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); | |
1600 | /* Disable rate control for now */ | |
1601 | bcmgenet_tdma_ring_writel(priv, index, flow_period_val, | |
c91b7f66 | 1602 | TDMA_FLOW_PERIOD); |
1c1008c7 FF |
1603 | /* Unclassified traffic goes to ring 16 */ |
1604 | bcmgenet_tdma_ring_writel(priv, index, | |
c91b7f66 FF |
1605 | ((size << DMA_RING_SIZE_SHIFT) | |
1606 | RX_BUF_LENGTH), DMA_RING_BUF_SIZE); | |
1c1008c7 FF |
1607 | |
1608 | first_bd = write_ptr; | |
1609 | ||
1610 | /* Set start and end address, read and write pointers */ | |
1611 | bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd, | |
c91b7f66 | 1612 | DMA_START_ADDR); |
1c1008c7 | 1613 | bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd, |
c91b7f66 | 1614 | TDMA_READ_PTR); |
1c1008c7 | 1615 | bcmgenet_tdma_ring_writel(priv, index, first_bd, |
c91b7f66 | 1616 | TDMA_WRITE_PTR); |
1c1008c7 | 1617 | bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, |
c91b7f66 | 1618 | DMA_END_ADDR); |
1c1008c7 FF |
1619 | } |
1620 | ||
1621 | /* Initialize a RDMA ring */ | |
1622 | static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, | |
c91b7f66 | 1623 | unsigned int index, unsigned int size) |
1c1008c7 FF |
1624 | { |
1625 | u32 words_per_bd = WORDS_PER_BD(priv); | |
1626 | int ret; | |
1627 | ||
1628 | priv->num_rx_bds = TOTAL_DESC; | |
1629 | priv->rx_bds = priv->base + priv->hw_params->rdma_offset; | |
1630 | priv->rx_bd_assign_ptr = priv->rx_bds; | |
1631 | priv->rx_bd_assign_index = 0; | |
1632 | priv->rx_c_index = 0; | |
1633 | priv->rx_read_ptr = 0; | |
1634 | priv->rx_cbs = kzalloc(priv->num_rx_bds * sizeof(struct enet_cb), | |
1635 | GFP_KERNEL); | |
1636 | if (!priv->rx_cbs) | |
1637 | return -ENOMEM; | |
1638 | ||
1639 | ret = bcmgenet_alloc_rx_buffers(priv); | |
1640 | if (ret) { | |
1641 | kfree(priv->rx_cbs); | |
1642 | return ret; | |
1643 | } | |
1644 | ||
1645 | bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR); | |
1646 | bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); | |
1647 | bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); | |
1648 | bcmgenet_rdma_ring_writel(priv, index, | |
c91b7f66 FF |
1649 | ((size << DMA_RING_SIZE_SHIFT) | |
1650 | RX_BUF_LENGTH), DMA_RING_BUF_SIZE); | |
1c1008c7 FF |
1651 | bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR); |
1652 | bcmgenet_rdma_ring_writel(priv, index, | |
c91b7f66 | 1653 | words_per_bd * size - 1, DMA_END_ADDR); |
1c1008c7 | 1654 | bcmgenet_rdma_ring_writel(priv, index, |
c91b7f66 FF |
1655 | (DMA_FC_THRESH_LO << |
1656 | DMA_XOFF_THRESHOLD_SHIFT) | | |
1657 | DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); | |
1c1008c7 FF |
1658 | bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR); |
1659 | ||
1660 | return ret; | |
1661 | } | |
1662 | ||
1663 | /* init multi xmit queues, only available for GENET2+ | |
1664 | * the queue is partitioned as follows: | |
1665 | * | |
1666 | * queue 0 - 3 is priority based, each one has 32 descriptors, | |
1667 | * with queue 0 being the highest priority queue. | |
1668 | * | |
1669 | * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT | |
1670 | * descriptors: 256 - (number of tx queues * bds per queues) = 128 | |
1671 | * descriptors. | |
1672 | * | |
1673 | * The transmit control block pool is then partitioned as following: | |
1674 | * - tx_cbs[0...127] are for queue 16 | |
1675 | * - tx_ring_cbs[0] points to tx_cbs[128..159] | |
1676 | * - tx_ring_cbs[1] points to tx_cbs[160..191] | |
1677 | * - tx_ring_cbs[2] points to tx_cbs[192..223] | |
1678 | * - tx_ring_cbs[3] points to tx_cbs[224..255] | |
1679 | */ | |
1680 | static void bcmgenet_init_multiq(struct net_device *dev) | |
1681 | { | |
1682 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
1683 | unsigned int i, dma_enable; | |
1684 | u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0; | |
1685 | ||
1686 | if (!netif_is_multiqueue(dev)) { | |
1687 | netdev_warn(dev, "called with non multi queue aware HW\n"); | |
1688 | return; | |
1689 | } | |
1690 | ||
1691 | dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); | |
1692 | dma_enable = dma_ctrl & DMA_EN; | |
1693 | dma_ctrl &= ~DMA_EN; | |
1694 | bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); | |
1695 | ||
1696 | /* Enable strict priority arbiter mode */ | |
1697 | bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); | |
1698 | ||
1699 | for (i = 0; i < priv->hw_params->tx_queues; i++) { | |
1700 | /* first 64 tx_cbs are reserved for default tx queue | |
1701 | * (ring 16) | |
1702 | */ | |
1703 | bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt, | |
c91b7f66 FF |
1704 | i * priv->hw_params->bds_cnt, |
1705 | (i + 1) * priv->hw_params->bds_cnt); | |
1c1008c7 FF |
1706 | |
1707 | /* Configure ring as decriptor ring and setup priority */ | |
1708 | ring_cfg |= 1 << i; | |
1709 | dma_priority |= ((GENET_Q0_PRIORITY + i) << | |
1710 | (GENET_MAX_MQ_CNT + 1) * i); | |
1711 | dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT); | |
1712 | } | |
1713 | ||
1714 | /* Enable rings */ | |
1715 | reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG); | |
1716 | reg |= ring_cfg; | |
1717 | bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG); | |
1718 | ||
1719 | /* Use configured rings priority and set ring #16 priority */ | |
1720 | reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY); | |
1721 | reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20); | |
1722 | reg |= dma_priority; | |
1723 | bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY); | |
1724 | ||
1725 | /* Configure ring as descriptor ring and re-enable DMA if enabled */ | |
1726 | reg = bcmgenet_tdma_readl(priv, DMA_CTRL); | |
1727 | reg |= dma_ctrl; | |
1728 | if (dma_enable) | |
1729 | reg |= DMA_EN; | |
1730 | bcmgenet_tdma_writel(priv, reg, DMA_CTRL); | |
1731 | } | |
1732 | ||
1733 | static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) | |
1734 | { | |
1735 | int i; | |
1736 | ||
1737 | /* disable DMA */ | |
1738 | bcmgenet_rdma_writel(priv, 0, DMA_CTRL); | |
1739 | bcmgenet_tdma_writel(priv, 0, DMA_CTRL); | |
1740 | ||
1741 | for (i = 0; i < priv->num_tx_bds; i++) { | |
1742 | if (priv->tx_cbs[i].skb != NULL) { | |
1743 | dev_kfree_skb(priv->tx_cbs[i].skb); | |
1744 | priv->tx_cbs[i].skb = NULL; | |
1745 | } | |
1746 | } | |
1747 | ||
1748 | bcmgenet_free_rx_buffers(priv); | |
1749 | kfree(priv->rx_cbs); | |
1750 | kfree(priv->tx_cbs); | |
1751 | } | |
1752 | ||
1753 | /* init_edma: Initialize DMA control register */ | |
1754 | static int bcmgenet_init_dma(struct bcmgenet_priv *priv) | |
1755 | { | |
1756 | int ret; | |
1757 | ||
1758 | netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n"); | |
1759 | ||
1760 | /* by default, enable ring 16 (descriptor based) */ | |
1761 | ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC); | |
1762 | if (ret) { | |
1763 | netdev_err(priv->dev, "failed to initialize RX ring\n"); | |
1764 | return ret; | |
1765 | } | |
1766 | ||
1767 | /* init rDma */ | |
1768 | bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); | |
1769 | ||
1770 | /* Init tDma */ | |
1771 | bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); | |
1772 | ||
1773 | /* Initialize commont TX ring structures */ | |
1774 | priv->tx_bds = priv->base + priv->hw_params->tdma_offset; | |
1775 | priv->num_tx_bds = TOTAL_DESC; | |
1776 | priv->tx_cbs = kzalloc(priv->num_tx_bds * sizeof(struct enet_cb), | |
c91b7f66 | 1777 | GFP_KERNEL); |
1c1008c7 FF |
1778 | if (!priv->tx_cbs) { |
1779 | bcmgenet_fini_dma(priv); | |
1780 | return -ENOMEM; | |
1781 | } | |
1782 | ||
1783 | /* initialize multi xmit queue */ | |
1784 | bcmgenet_init_multiq(priv->dev); | |
1785 | ||
1786 | /* initialize special ring 16 */ | |
1787 | bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT, | |
c91b7f66 FF |
1788 | priv->hw_params->tx_queues * |
1789 | priv->hw_params->bds_cnt, | |
1790 | TOTAL_DESC); | |
1c1008c7 FF |
1791 | |
1792 | return 0; | |
1793 | } | |
1794 | ||
1795 | /* NAPI polling method*/ | |
1796 | static int bcmgenet_poll(struct napi_struct *napi, int budget) | |
1797 | { | |
1798 | struct bcmgenet_priv *priv = container_of(napi, | |
1799 | struct bcmgenet_priv, napi); | |
1800 | unsigned int work_done; | |
1801 | ||
1802 | /* tx reclaim */ | |
1803 | bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]); | |
1804 | ||
1805 | work_done = bcmgenet_desc_rx(priv, budget); | |
1806 | ||
1807 | /* Advancing our consumer index*/ | |
1808 | priv->rx_c_index += work_done; | |
1809 | priv->rx_c_index &= DMA_C_INDEX_MASK; | |
1810 | bcmgenet_rdma_ring_writel(priv, DESC_INDEX, | |
c91b7f66 | 1811 | priv->rx_c_index, RDMA_CONS_INDEX); |
1c1008c7 FF |
1812 | if (work_done < budget) { |
1813 | napi_complete(napi); | |
c91b7f66 FF |
1814 | bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE, |
1815 | INTRL2_CPU_MASK_CLEAR); | |
1c1008c7 FF |
1816 | } |
1817 | ||
1818 | return work_done; | |
1819 | } | |
1820 | ||
1821 | /* Interrupt bottom half */ | |
1822 | static void bcmgenet_irq_task(struct work_struct *work) | |
1823 | { | |
1824 | struct bcmgenet_priv *priv = container_of( | |
1825 | work, struct bcmgenet_priv, bcmgenet_irq_work); | |
1826 | ||
1827 | netif_dbg(priv, intr, priv->dev, "%s\n", __func__); | |
1828 | ||
8fdb0e0f FF |
1829 | if (priv->irq0_stat & UMAC_IRQ_MPD_R) { |
1830 | priv->irq0_stat &= ~UMAC_IRQ_MPD_R; | |
1831 | netif_dbg(priv, wol, priv->dev, | |
1832 | "magic packet detected, waking up\n"); | |
1833 | bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); | |
1834 | } | |
1835 | ||
1c1008c7 FF |
1836 | /* Link UP/DOWN event */ |
1837 | if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && | |
c91b7f66 | 1838 | (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) { |
80d8e96d | 1839 | phy_mac_interrupt(priv->phydev, |
c91b7f66 | 1840 | priv->irq0_stat & UMAC_IRQ_LINK_UP); |
1c1008c7 FF |
1841 | priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN); |
1842 | } | |
1843 | } | |
1844 | ||
1845 | /* bcmgenet_isr1: interrupt handler for ring buffer. */ | |
1846 | static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) | |
1847 | { | |
1848 | struct bcmgenet_priv *priv = dev_id; | |
1849 | unsigned int index; | |
1850 | ||
1851 | /* Save irq status for bottom-half processing. */ | |
1852 | priv->irq1_stat = | |
1853 | bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & | |
1854 | ~priv->int1_mask; | |
1855 | /* clear inerrupts*/ | |
1856 | bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); | |
1857 | ||
1858 | netif_dbg(priv, intr, priv->dev, | |
c91b7f66 | 1859 | "%s: IRQ=0x%x\n", __func__, priv->irq1_stat); |
1c1008c7 FF |
1860 | /* Check the MBDONE interrupts. |
1861 | * packet is done, reclaim descriptors | |
1862 | */ | |
1863 | if (priv->irq1_stat & 0x0000ffff) { | |
1864 | index = 0; | |
1865 | for (index = 0; index < 16; index++) { | |
1866 | if (priv->irq1_stat & (1 << index)) | |
1867 | bcmgenet_tx_reclaim(priv->dev, | |
c91b7f66 | 1868 | &priv->tx_rings[index]); |
1c1008c7 FF |
1869 | } |
1870 | } | |
1871 | return IRQ_HANDLED; | |
1872 | } | |
1873 | ||
1874 | /* bcmgenet_isr0: Handle various interrupts. */ | |
1875 | static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) | |
1876 | { | |
1877 | struct bcmgenet_priv *priv = dev_id; | |
1878 | ||
1879 | /* Save irq status for bottom-half processing. */ | |
1880 | priv->irq0_stat = | |
1881 | bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & | |
1882 | ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); | |
1883 | /* clear inerrupts*/ | |
1884 | bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); | |
1885 | ||
1886 | netif_dbg(priv, intr, priv->dev, | |
c91b7f66 | 1887 | "IRQ=0x%x\n", priv->irq0_stat); |
1c1008c7 FF |
1888 | |
1889 | if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) { | |
1890 | /* We use NAPI(software interrupt throttling, if | |
1891 | * Rx Descriptor throttling is not used. | |
1892 | * Disable interrupt, will be enabled in the poll method. | |
1893 | */ | |
1894 | if (likely(napi_schedule_prep(&priv->napi))) { | |
c91b7f66 FF |
1895 | bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE, |
1896 | INTRL2_CPU_MASK_SET); | |
1c1008c7 FF |
1897 | __napi_schedule(&priv->napi); |
1898 | } | |
1899 | } | |
1900 | if (priv->irq0_stat & | |
1901 | (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) { | |
1902 | /* Tx reclaim */ | |
1903 | bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]); | |
1904 | } | |
1905 | if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R | | |
1906 | UMAC_IRQ_PHY_DET_F | | |
1907 | UMAC_IRQ_LINK_UP | | |
1908 | UMAC_IRQ_LINK_DOWN | | |
1909 | UMAC_IRQ_HFB_SM | | |
1910 | UMAC_IRQ_HFB_MM | | |
1911 | UMAC_IRQ_MPD_R)) { | |
1912 | /* all other interested interrupts handled in bottom half */ | |
1913 | schedule_work(&priv->bcmgenet_irq_work); | |
1914 | } | |
1915 | ||
1916 | if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && | |
c91b7f66 | 1917 | priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { |
1c1008c7 FF |
1918 | priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); |
1919 | wake_up(&priv->wq); | |
1920 | } | |
1921 | ||
1922 | return IRQ_HANDLED; | |
1923 | } | |
1924 | ||
8562056f FF |
1925 | static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) |
1926 | { | |
1927 | struct bcmgenet_priv *priv = dev_id; | |
1928 | ||
1929 | pm_wakeup_event(&priv->pdev->dev, 0); | |
1930 | ||
1931 | return IRQ_HANDLED; | |
1932 | } | |
1933 | ||
1c1008c7 FF |
1934 | static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) |
1935 | { | |
1936 | u32 reg; | |
1937 | ||
1938 | reg = bcmgenet_rbuf_ctrl_get(priv); | |
1939 | reg |= BIT(1); | |
1940 | bcmgenet_rbuf_ctrl_set(priv, reg); | |
1941 | udelay(10); | |
1942 | ||
1943 | reg &= ~BIT(1); | |
1944 | bcmgenet_rbuf_ctrl_set(priv, reg); | |
1945 | udelay(10); | |
1946 | } | |
1947 | ||
1948 | static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, | |
c91b7f66 | 1949 | unsigned char *addr) |
1c1008c7 FF |
1950 | { |
1951 | bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | | |
1952 | (addr[2] << 8) | addr[3], UMAC_MAC0); | |
1953 | bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); | |
1954 | } | |
1955 | ||
1956 | static int bcmgenet_wol_resume(struct bcmgenet_priv *priv) | |
1957 | { | |
1c1008c7 | 1958 | /* From WOL-enabled suspend, switch to regular clock */ |
1c3c1e79 | 1959 | clk_disable_unprepare(priv->clk_wol); |
1c1008c7 | 1960 | |
80d8e96d | 1961 | phy_init_hw(priv->phydev); |
1c1008c7 FF |
1962 | /* Speed settings must be restored */ |
1963 | bcmgenet_mii_config(priv->dev); | |
1964 | ||
1965 | return 0; | |
1966 | } | |
1967 | ||
1968 | /* Returns a reusable dma control register value */ | |
1969 | static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) | |
1970 | { | |
1971 | u32 reg; | |
1972 | u32 dma_ctrl; | |
1973 | ||
1974 | /* disable DMA */ | |
1975 | dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; | |
1976 | reg = bcmgenet_tdma_readl(priv, DMA_CTRL); | |
1977 | reg &= ~dma_ctrl; | |
1978 | bcmgenet_tdma_writel(priv, reg, DMA_CTRL); | |
1979 | ||
1980 | reg = bcmgenet_rdma_readl(priv, DMA_CTRL); | |
1981 | reg &= ~dma_ctrl; | |
1982 | bcmgenet_rdma_writel(priv, reg, DMA_CTRL); | |
1983 | ||
1984 | bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); | |
1985 | udelay(10); | |
1986 | bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); | |
1987 | ||
1988 | return dma_ctrl; | |
1989 | } | |
1990 | ||
1991 | static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) | |
1992 | { | |
1993 | u32 reg; | |
1994 | ||
1995 | reg = bcmgenet_rdma_readl(priv, DMA_CTRL); | |
1996 | reg |= dma_ctrl; | |
1997 | bcmgenet_rdma_writel(priv, reg, DMA_CTRL); | |
1998 | ||
1999 | reg = bcmgenet_tdma_readl(priv, DMA_CTRL); | |
2000 | reg |= dma_ctrl; | |
2001 | bcmgenet_tdma_writel(priv, reg, DMA_CTRL); | |
2002 | } | |
2003 | ||
909ff5ef FF |
2004 | static void bcmgenet_netif_start(struct net_device *dev) |
2005 | { | |
2006 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2007 | ||
2008 | /* Start the network engine */ | |
2009 | napi_enable(&priv->napi); | |
2010 | ||
2011 | umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); | |
2012 | ||
2013 | if (phy_is_internal(priv->phydev)) | |
2014 | bcmgenet_power_up(priv, GENET_POWER_PASSIVE); | |
2015 | ||
2016 | netif_tx_start_all_queues(dev); | |
2017 | ||
2018 | phy_start(priv->phydev); | |
2019 | } | |
2020 | ||
1c1008c7 FF |
2021 | static int bcmgenet_open(struct net_device *dev) |
2022 | { | |
2023 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2024 | unsigned long dma_ctrl; | |
2025 | u32 reg; | |
2026 | int ret; | |
2027 | ||
2028 | netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); | |
2029 | ||
2030 | /* Turn on the clock */ | |
2031 | if (!IS_ERR(priv->clk)) | |
2032 | clk_prepare_enable(priv->clk); | |
2033 | ||
2034 | /* take MAC out of reset */ | |
2035 | bcmgenet_umac_reset(priv); | |
2036 | ||
2037 | ret = init_umac(priv); | |
2038 | if (ret) | |
2039 | goto err_clk_disable; | |
2040 | ||
2041 | /* disable ethernet MAC while updating its registers */ | |
e29585b8 | 2042 | umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); |
1c1008c7 | 2043 | |
909ff5ef FF |
2044 | /* Make sure we reflect the value of CRC_CMD_FWD */ |
2045 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); | |
2046 | priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); | |
2047 | ||
1c1008c7 FF |
2048 | bcmgenet_set_hw_addr(priv, dev->dev_addr); |
2049 | ||
1c1008c7 FF |
2050 | if (phy_is_internal(priv->phydev)) { |
2051 | reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); | |
2052 | reg |= EXT_ENERGY_DET_MASK; | |
2053 | bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); | |
2054 | } | |
2055 | ||
2056 | /* Disable RX/TX DMA and flush TX queues */ | |
2057 | dma_ctrl = bcmgenet_dma_disable(priv); | |
2058 | ||
2059 | /* Reinitialize TDMA and RDMA and SW housekeeping */ | |
2060 | ret = bcmgenet_init_dma(priv); | |
2061 | if (ret) { | |
2062 | netdev_err(dev, "failed to initialize DMA\n"); | |
2063 | goto err_fini_dma; | |
2064 | } | |
2065 | ||
2066 | /* Always enable ring 16 - descriptor ring */ | |
2067 | bcmgenet_enable_dma(priv, dma_ctrl); | |
2068 | ||
2069 | ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, | |
c91b7f66 | 2070 | dev->name, priv); |
1c1008c7 FF |
2071 | if (ret < 0) { |
2072 | netdev_err(dev, "can't request IRQ %d\n", priv->irq0); | |
2073 | goto err_fini_dma; | |
2074 | } | |
2075 | ||
2076 | ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, | |
c91b7f66 | 2077 | dev->name, priv); |
1c1008c7 FF |
2078 | if (ret < 0) { |
2079 | netdev_err(dev, "can't request IRQ %d\n", priv->irq1); | |
2080 | goto err_irq0; | |
2081 | } | |
2082 | ||
909ff5ef | 2083 | bcmgenet_netif_start(dev); |
1c1008c7 FF |
2084 | |
2085 | return 0; | |
2086 | ||
2087 | err_irq0: | |
2088 | free_irq(priv->irq0, dev); | |
2089 | err_fini_dma: | |
2090 | bcmgenet_fini_dma(priv); | |
2091 | err_clk_disable: | |
2092 | if (!IS_ERR(priv->clk)) | |
2093 | clk_disable_unprepare(priv->clk); | |
2094 | return ret; | |
2095 | } | |
2096 | ||
2097 | static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) | |
2098 | { | |
2099 | int ret = 0; | |
2100 | int timeout = 0; | |
2101 | u32 reg; | |
2102 | ||
2103 | /* Disable TDMA to stop add more frames in TX DMA */ | |
2104 | reg = bcmgenet_tdma_readl(priv, DMA_CTRL); | |
2105 | reg &= ~DMA_EN; | |
2106 | bcmgenet_tdma_writel(priv, reg, DMA_CTRL); | |
2107 | ||
2108 | /* Check TDMA status register to confirm TDMA is disabled */ | |
2109 | while (timeout++ < DMA_TIMEOUT_VAL) { | |
2110 | reg = bcmgenet_tdma_readl(priv, DMA_STATUS); | |
2111 | if (reg & DMA_DISABLED) | |
2112 | break; | |
2113 | ||
2114 | udelay(1); | |
2115 | } | |
2116 | ||
2117 | if (timeout == DMA_TIMEOUT_VAL) { | |
c91b7f66 | 2118 | netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); |
1c1008c7 FF |
2119 | ret = -ETIMEDOUT; |
2120 | } | |
2121 | ||
2122 | /* Wait 10ms for packet drain in both tx and rx dma */ | |
2123 | usleep_range(10000, 20000); | |
2124 | ||
2125 | /* Disable RDMA */ | |
2126 | reg = bcmgenet_rdma_readl(priv, DMA_CTRL); | |
2127 | reg &= ~DMA_EN; | |
2128 | bcmgenet_rdma_writel(priv, reg, DMA_CTRL); | |
2129 | ||
2130 | timeout = 0; | |
2131 | /* Check RDMA status register to confirm RDMA is disabled */ | |
2132 | while (timeout++ < DMA_TIMEOUT_VAL) { | |
2133 | reg = bcmgenet_rdma_readl(priv, DMA_STATUS); | |
2134 | if (reg & DMA_DISABLED) | |
2135 | break; | |
2136 | ||
2137 | udelay(1); | |
2138 | } | |
2139 | ||
2140 | if (timeout == DMA_TIMEOUT_VAL) { | |
c91b7f66 FF |
2141 | netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); |
2142 | ret = -ETIMEDOUT; | |
1c1008c7 FF |
2143 | } |
2144 | ||
2145 | return ret; | |
2146 | } | |
2147 | ||
909ff5ef FF |
2148 | static void bcmgenet_netif_stop(struct net_device *dev) |
2149 | { | |
2150 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2151 | ||
2152 | netif_tx_stop_all_queues(dev); | |
2153 | napi_disable(&priv->napi); | |
2154 | phy_stop(priv->phydev); | |
2155 | ||
2156 | bcmgenet_intr_disable(priv); | |
2157 | ||
2158 | /* Wait for pending work items to complete. Since interrupts are | |
2159 | * disabled no new work will be scheduled. | |
2160 | */ | |
2161 | cancel_work_sync(&priv->bcmgenet_irq_work); | |
2162 | } | |
2163 | ||
1c1008c7 FF |
2164 | static int bcmgenet_close(struct net_device *dev) |
2165 | { | |
2166 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2167 | int ret; | |
1c1008c7 FF |
2168 | |
2169 | netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); | |
2170 | ||
909ff5ef | 2171 | bcmgenet_netif_stop(dev); |
1c1008c7 FF |
2172 | |
2173 | /* Disable MAC receive */ | |
e29585b8 | 2174 | umac_enable_set(priv, CMD_RX_EN, false); |
1c1008c7 | 2175 | |
1c1008c7 FF |
2176 | ret = bcmgenet_dma_teardown(priv); |
2177 | if (ret) | |
2178 | return ret; | |
2179 | ||
2180 | /* Disable MAC transmit. TX DMA disabled have to done before this */ | |
e29585b8 | 2181 | umac_enable_set(priv, CMD_TX_EN, false); |
1c1008c7 | 2182 | |
1c1008c7 FF |
2183 | /* tx reclaim */ |
2184 | bcmgenet_tx_reclaim_all(dev); | |
2185 | bcmgenet_fini_dma(priv); | |
2186 | ||
2187 | free_irq(priv->irq0, priv); | |
2188 | free_irq(priv->irq1, priv); | |
2189 | ||
1c1008c7 FF |
2190 | if (phy_is_internal(priv->phydev)) |
2191 | bcmgenet_power_down(priv, GENET_POWER_PASSIVE); | |
2192 | ||
1c1008c7 FF |
2193 | if (!IS_ERR(priv->clk)) |
2194 | clk_disable_unprepare(priv->clk); | |
2195 | ||
2196 | return 0; | |
2197 | } | |
2198 | ||
2199 | static void bcmgenet_timeout(struct net_device *dev) | |
2200 | { | |
2201 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2202 | ||
2203 | netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); | |
2204 | ||
2205 | dev->trans_start = jiffies; | |
2206 | ||
2207 | dev->stats.tx_errors++; | |
2208 | ||
2209 | netif_tx_wake_all_queues(dev); | |
2210 | } | |
2211 | ||
2212 | #define MAX_MC_COUNT 16 | |
2213 | ||
2214 | static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, | |
2215 | unsigned char *addr, | |
2216 | int *i, | |
2217 | int *mc) | |
2218 | { | |
2219 | u32 reg; | |
2220 | ||
c91b7f66 FF |
2221 | bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], |
2222 | UMAC_MDF_ADDR + (*i * 4)); | |
2223 | bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | | |
2224 | addr[4] << 8 | addr[5], | |
2225 | UMAC_MDF_ADDR + ((*i + 1) * 4)); | |
1c1008c7 FF |
2226 | reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL); |
2227 | reg |= (1 << (MAX_MC_COUNT - *mc)); | |
2228 | bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); | |
2229 | *i += 2; | |
2230 | (*mc)++; | |
2231 | } | |
2232 | ||
2233 | static void bcmgenet_set_rx_mode(struct net_device *dev) | |
2234 | { | |
2235 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2236 | struct netdev_hw_addr *ha; | |
2237 | int i, mc; | |
2238 | u32 reg; | |
2239 | ||
2240 | netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); | |
2241 | ||
2242 | /* Promiscous mode */ | |
2243 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); | |
2244 | if (dev->flags & IFF_PROMISC) { | |
2245 | reg |= CMD_PROMISC; | |
2246 | bcmgenet_umac_writel(priv, reg, UMAC_CMD); | |
2247 | bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); | |
2248 | return; | |
2249 | } else { | |
2250 | reg &= ~CMD_PROMISC; | |
2251 | bcmgenet_umac_writel(priv, reg, UMAC_CMD); | |
2252 | } | |
2253 | ||
2254 | /* UniMac doesn't support ALLMULTI */ | |
2255 | if (dev->flags & IFF_ALLMULTI) { | |
2256 | netdev_warn(dev, "ALLMULTI is not supported\n"); | |
2257 | return; | |
2258 | } | |
2259 | ||
2260 | /* update MDF filter */ | |
2261 | i = 0; | |
2262 | mc = 0; | |
2263 | /* Broadcast */ | |
2264 | bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc); | |
2265 | /* my own address.*/ | |
2266 | bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc); | |
2267 | /* Unicast list*/ | |
2268 | if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc)) | |
2269 | return; | |
2270 | ||
2271 | if (!netdev_uc_empty(dev)) | |
2272 | netdev_for_each_uc_addr(ha, dev) | |
2273 | bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); | |
2274 | /* Multicast */ | |
2275 | if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc)) | |
2276 | return; | |
2277 | ||
2278 | netdev_for_each_mc_addr(ha, dev) | |
2279 | bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); | |
2280 | } | |
2281 | ||
2282 | /* Set the hardware MAC address. */ | |
2283 | static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) | |
2284 | { | |
2285 | struct sockaddr *addr = p; | |
2286 | ||
2287 | /* Setting the MAC address at the hardware level is not possible | |
2288 | * without disabling the UniMAC RX/TX enable bits. | |
2289 | */ | |
2290 | if (netif_running(dev)) | |
2291 | return -EBUSY; | |
2292 | ||
2293 | ether_addr_copy(dev->dev_addr, addr->sa_data); | |
2294 | ||
2295 | return 0; | |
2296 | } | |
2297 | ||
1c1008c7 FF |
2298 | static const struct net_device_ops bcmgenet_netdev_ops = { |
2299 | .ndo_open = bcmgenet_open, | |
2300 | .ndo_stop = bcmgenet_close, | |
2301 | .ndo_start_xmit = bcmgenet_xmit, | |
1c1008c7 FF |
2302 | .ndo_tx_timeout = bcmgenet_timeout, |
2303 | .ndo_set_rx_mode = bcmgenet_set_rx_mode, | |
2304 | .ndo_set_mac_address = bcmgenet_set_mac_addr, | |
2305 | .ndo_do_ioctl = bcmgenet_ioctl, | |
2306 | .ndo_set_features = bcmgenet_set_features, | |
2307 | }; | |
2308 | ||
2309 | /* Array of GENET hardware parameters/characteristics */ | |
2310 | static struct bcmgenet_hw_params bcmgenet_hw_params[] = { | |
2311 | [GENET_V1] = { | |
2312 | .tx_queues = 0, | |
2313 | .rx_queues = 0, | |
2314 | .bds_cnt = 0, | |
2315 | .bp_in_en_shift = 16, | |
2316 | .bp_in_mask = 0xffff, | |
2317 | .hfb_filter_cnt = 16, | |
2318 | .qtag_mask = 0x1F, | |
2319 | .hfb_offset = 0x1000, | |
2320 | .rdma_offset = 0x2000, | |
2321 | .tdma_offset = 0x3000, | |
2322 | .words_per_bd = 2, | |
2323 | }, | |
2324 | [GENET_V2] = { | |
2325 | .tx_queues = 4, | |
2326 | .rx_queues = 4, | |
2327 | .bds_cnt = 32, | |
2328 | .bp_in_en_shift = 16, | |
2329 | .bp_in_mask = 0xffff, | |
2330 | .hfb_filter_cnt = 16, | |
2331 | .qtag_mask = 0x1F, | |
2332 | .tbuf_offset = 0x0600, | |
2333 | .hfb_offset = 0x1000, | |
2334 | .hfb_reg_offset = 0x2000, | |
2335 | .rdma_offset = 0x3000, | |
2336 | .tdma_offset = 0x4000, | |
2337 | .words_per_bd = 2, | |
2338 | .flags = GENET_HAS_EXT, | |
2339 | }, | |
2340 | [GENET_V3] = { | |
2341 | .tx_queues = 4, | |
2342 | .rx_queues = 4, | |
2343 | .bds_cnt = 32, | |
2344 | .bp_in_en_shift = 17, | |
2345 | .bp_in_mask = 0x1ffff, | |
2346 | .hfb_filter_cnt = 48, | |
2347 | .qtag_mask = 0x3F, | |
2348 | .tbuf_offset = 0x0600, | |
2349 | .hfb_offset = 0x8000, | |
2350 | .hfb_reg_offset = 0xfc00, | |
2351 | .rdma_offset = 0x10000, | |
2352 | .tdma_offset = 0x11000, | |
2353 | .words_per_bd = 2, | |
2354 | .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR, | |
2355 | }, | |
2356 | [GENET_V4] = { | |
2357 | .tx_queues = 4, | |
2358 | .rx_queues = 4, | |
2359 | .bds_cnt = 32, | |
2360 | .bp_in_en_shift = 17, | |
2361 | .bp_in_mask = 0x1ffff, | |
2362 | .hfb_filter_cnt = 48, | |
2363 | .qtag_mask = 0x3F, | |
2364 | .tbuf_offset = 0x0600, | |
2365 | .hfb_offset = 0x8000, | |
2366 | .hfb_reg_offset = 0xfc00, | |
2367 | .rdma_offset = 0x2000, | |
2368 | .tdma_offset = 0x4000, | |
2369 | .words_per_bd = 3, | |
2370 | .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR, | |
2371 | }, | |
2372 | }; | |
2373 | ||
2374 | /* Infer hardware parameters from the detected GENET version */ | |
2375 | static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) | |
2376 | { | |
2377 | struct bcmgenet_hw_params *params; | |
2378 | u32 reg; | |
2379 | u8 major; | |
2380 | ||
2381 | if (GENET_IS_V4(priv)) { | |
2382 | bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; | |
2383 | genet_dma_ring_regs = genet_dma_ring_regs_v4; | |
2384 | priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; | |
2385 | priv->version = GENET_V4; | |
2386 | } else if (GENET_IS_V3(priv)) { | |
2387 | bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; | |
2388 | genet_dma_ring_regs = genet_dma_ring_regs_v123; | |
2389 | priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; | |
2390 | priv->version = GENET_V3; | |
2391 | } else if (GENET_IS_V2(priv)) { | |
2392 | bcmgenet_dma_regs = bcmgenet_dma_regs_v2; | |
2393 | genet_dma_ring_regs = genet_dma_ring_regs_v123; | |
2394 | priv->dma_rx_chk_bit = DMA_RX_CHK_V12; | |
2395 | priv->version = GENET_V2; | |
2396 | } else if (GENET_IS_V1(priv)) { | |
2397 | bcmgenet_dma_regs = bcmgenet_dma_regs_v1; | |
2398 | genet_dma_ring_regs = genet_dma_ring_regs_v123; | |
2399 | priv->dma_rx_chk_bit = DMA_RX_CHK_V12; | |
2400 | priv->version = GENET_V1; | |
2401 | } | |
2402 | ||
2403 | /* enum genet_version starts at 1 */ | |
2404 | priv->hw_params = &bcmgenet_hw_params[priv->version]; | |
2405 | params = priv->hw_params; | |
2406 | ||
2407 | /* Read GENET HW version */ | |
2408 | reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); | |
2409 | major = (reg >> 24 & 0x0f); | |
2410 | if (major == 5) | |
2411 | major = 4; | |
2412 | else if (major == 0) | |
2413 | major = 1; | |
2414 | if (major != priv->version) { | |
2415 | dev_err(&priv->pdev->dev, | |
2416 | "GENET version mismatch, got: %d, configured for: %d\n", | |
2417 | major, priv->version); | |
2418 | } | |
2419 | ||
2420 | /* Print the GENET core version */ | |
2421 | dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, | |
c91b7f66 | 2422 | major, (reg >> 16) & 0x0f, reg & 0xffff); |
1c1008c7 FF |
2423 | |
2424 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
2425 | if (!(params->flags & GENET_HAS_40BITS)) | |
2426 | pr_warn("GENET does not support 40-bits PA\n"); | |
2427 | #endif | |
2428 | ||
2429 | pr_debug("Configuration for version: %d\n" | |
2430 | "TXq: %1d, RXq: %1d, BDs: %1d\n" | |
2431 | "BP << en: %2d, BP msk: 0x%05x\n" | |
2432 | "HFB count: %2d, QTAQ msk: 0x%05x\n" | |
2433 | "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" | |
2434 | "RDMA: 0x%05x, TDMA: 0x%05x\n" | |
2435 | "Words/BD: %d\n", | |
2436 | priv->version, | |
2437 | params->tx_queues, params->rx_queues, params->bds_cnt, | |
2438 | params->bp_in_en_shift, params->bp_in_mask, | |
2439 | params->hfb_filter_cnt, params->qtag_mask, | |
2440 | params->tbuf_offset, params->hfb_offset, | |
2441 | params->hfb_reg_offset, | |
2442 | params->rdma_offset, params->tdma_offset, | |
2443 | params->words_per_bd); | |
2444 | } | |
2445 | ||
2446 | static const struct of_device_id bcmgenet_match[] = { | |
2447 | { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 }, | |
2448 | { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 }, | |
2449 | { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 }, | |
2450 | { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 }, | |
2451 | { }, | |
2452 | }; | |
2453 | ||
2454 | static int bcmgenet_probe(struct platform_device *pdev) | |
2455 | { | |
2456 | struct device_node *dn = pdev->dev.of_node; | |
2457 | const struct of_device_id *of_id; | |
2458 | struct bcmgenet_priv *priv; | |
2459 | struct net_device *dev; | |
2460 | const void *macaddr; | |
2461 | struct resource *r; | |
2462 | int err = -EIO; | |
2463 | ||
2464 | /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */ | |
2465 | dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1); | |
2466 | if (!dev) { | |
2467 | dev_err(&pdev->dev, "can't allocate net device\n"); | |
2468 | return -ENOMEM; | |
2469 | } | |
2470 | ||
2471 | of_id = of_match_node(bcmgenet_match, dn); | |
2472 | if (!of_id) | |
2473 | return -EINVAL; | |
2474 | ||
2475 | priv = netdev_priv(dev); | |
2476 | priv->irq0 = platform_get_irq(pdev, 0); | |
2477 | priv->irq1 = platform_get_irq(pdev, 1); | |
8562056f | 2478 | priv->wol_irq = platform_get_irq(pdev, 2); |
1c1008c7 FF |
2479 | if (!priv->irq0 || !priv->irq1) { |
2480 | dev_err(&pdev->dev, "can't find IRQs\n"); | |
2481 | err = -EINVAL; | |
2482 | goto err; | |
2483 | } | |
2484 | ||
2485 | macaddr = of_get_mac_address(dn); | |
2486 | if (!macaddr) { | |
2487 | dev_err(&pdev->dev, "can't find MAC address\n"); | |
2488 | err = -EINVAL; | |
2489 | goto err; | |
2490 | } | |
2491 | ||
2492 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
5343a10d FE |
2493 | priv->base = devm_ioremap_resource(&pdev->dev, r); |
2494 | if (IS_ERR(priv->base)) { | |
2495 | err = PTR_ERR(priv->base); | |
1c1008c7 FF |
2496 | goto err; |
2497 | } | |
2498 | ||
2499 | SET_NETDEV_DEV(dev, &pdev->dev); | |
2500 | dev_set_drvdata(&pdev->dev, dev); | |
2501 | ether_addr_copy(dev->dev_addr, macaddr); | |
2502 | dev->watchdog_timeo = 2 * HZ; | |
7ad24ea4 | 2503 | dev->ethtool_ops = &bcmgenet_ethtool_ops; |
1c1008c7 FF |
2504 | dev->netdev_ops = &bcmgenet_netdev_ops; |
2505 | netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64); | |
2506 | ||
2507 | priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); | |
2508 | ||
2509 | /* Set hardware features */ | |
2510 | dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | | |
2511 | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM; | |
2512 | ||
8562056f FF |
2513 | /* Request the WOL interrupt and advertise suspend if available */ |
2514 | priv->wol_irq_disabled = true; | |
2515 | err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, | |
2516 | dev->name, priv); | |
2517 | if (!err) | |
2518 | device_set_wakeup_capable(&pdev->dev, 1); | |
2519 | ||
1c1008c7 FF |
2520 | /* Set the needed headroom to account for any possible |
2521 | * features enabling/disabling at runtime | |
2522 | */ | |
2523 | dev->needed_headroom += 64; | |
2524 | ||
2525 | netdev_boot_setup_check(dev); | |
2526 | ||
2527 | priv->dev = dev; | |
2528 | priv->pdev = pdev; | |
2529 | priv->version = (enum bcmgenet_version)of_id->data; | |
2530 | ||
2531 | bcmgenet_set_hw_params(priv); | |
2532 | ||
1c1008c7 FF |
2533 | /* Mii wait queue */ |
2534 | init_waitqueue_head(&priv->wq); | |
2535 | /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ | |
2536 | priv->rx_buf_len = RX_BUF_LENGTH; | |
2537 | INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); | |
2538 | ||
2539 | priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); | |
2540 | if (IS_ERR(priv->clk)) | |
2541 | dev_warn(&priv->pdev->dev, "failed to get enet clock\n"); | |
2542 | ||
2543 | priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); | |
2544 | if (IS_ERR(priv->clk_wol)) | |
2545 | dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n"); | |
2546 | ||
2547 | if (!IS_ERR(priv->clk)) | |
2548 | clk_prepare_enable(priv->clk); | |
2549 | ||
2550 | err = reset_umac(priv); | |
2551 | if (err) | |
2552 | goto err_clk_disable; | |
2553 | ||
2554 | err = bcmgenet_mii_init(dev); | |
2555 | if (err) | |
2556 | goto err_clk_disable; | |
2557 | ||
2558 | /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues | |
2559 | * just the ring 16 descriptor based TX | |
2560 | */ | |
2561 | netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); | |
2562 | netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); | |
2563 | ||
219575eb FF |
2564 | /* libphy will determine the link state */ |
2565 | netif_carrier_off(dev); | |
2566 | ||
1c1008c7 FF |
2567 | /* Turn off the main clock, WOL clock is handled separately */ |
2568 | if (!IS_ERR(priv->clk)) | |
2569 | clk_disable_unprepare(priv->clk); | |
2570 | ||
0f50ce96 FF |
2571 | err = register_netdev(dev); |
2572 | if (err) | |
2573 | goto err; | |
2574 | ||
1c1008c7 FF |
2575 | return err; |
2576 | ||
2577 | err_clk_disable: | |
2578 | if (!IS_ERR(priv->clk)) | |
2579 | clk_disable_unprepare(priv->clk); | |
2580 | err: | |
2581 | free_netdev(dev); | |
2582 | return err; | |
2583 | } | |
2584 | ||
2585 | static int bcmgenet_remove(struct platform_device *pdev) | |
2586 | { | |
2587 | struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); | |
2588 | ||
2589 | dev_set_drvdata(&pdev->dev, NULL); | |
2590 | unregister_netdev(priv->dev); | |
2591 | bcmgenet_mii_exit(priv->dev); | |
2592 | free_netdev(priv->dev); | |
2593 | ||
2594 | return 0; | |
2595 | } | |
2596 | ||
b6e978e5 FF |
2597 | #ifdef CONFIG_PM_SLEEP |
2598 | static int bcmgenet_suspend(struct device *d) | |
2599 | { | |
2600 | struct net_device *dev = dev_get_drvdata(d); | |
2601 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2602 | int ret; | |
2603 | ||
2604 | if (!netif_running(dev)) | |
2605 | return 0; | |
2606 | ||
2607 | bcmgenet_netif_stop(dev); | |
2608 | ||
2609 | netif_device_detach(dev); | |
2610 | ||
2611 | /* Disable MAC receive */ | |
2612 | umac_enable_set(priv, CMD_RX_EN, false); | |
2613 | ||
2614 | ret = bcmgenet_dma_teardown(priv); | |
2615 | if (ret) | |
2616 | return ret; | |
2617 | ||
2618 | /* Disable MAC transmit. TX DMA disabled have to done before this */ | |
2619 | umac_enable_set(priv, CMD_TX_EN, false); | |
2620 | ||
2621 | /* tx reclaim */ | |
2622 | bcmgenet_tx_reclaim_all(dev); | |
2623 | bcmgenet_fini_dma(priv); | |
2624 | ||
8c90db72 FF |
2625 | /* Prepare the device for Wake-on-LAN and switch to the slow clock */ |
2626 | if (device_may_wakeup(d) && priv->wolopts) { | |
2627 | bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); | |
2628 | clk_prepare_enable(priv->clk_wol); | |
2629 | } | |
2630 | ||
b6e978e5 FF |
2631 | /* Turn off the clocks */ |
2632 | clk_disable_unprepare(priv->clk); | |
2633 | ||
2634 | return 0; | |
2635 | } | |
2636 | ||
2637 | static int bcmgenet_resume(struct device *d) | |
2638 | { | |
2639 | struct net_device *dev = dev_get_drvdata(d); | |
2640 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2641 | unsigned long dma_ctrl; | |
2642 | int ret; | |
2643 | u32 reg; | |
2644 | ||
2645 | if (!netif_running(dev)) | |
2646 | return 0; | |
2647 | ||
2648 | /* Turn on the clock */ | |
2649 | ret = clk_prepare_enable(priv->clk); | |
2650 | if (ret) | |
2651 | return ret; | |
2652 | ||
2653 | bcmgenet_umac_reset(priv); | |
2654 | ||
2655 | ret = init_umac(priv); | |
2656 | if (ret) | |
2657 | goto out_clk_disable; | |
2658 | ||
8c90db72 FF |
2659 | if (priv->wolopts) |
2660 | ret = bcmgenet_wol_resume(priv); | |
2661 | ||
2662 | if (ret) | |
2663 | goto out_clk_disable; | |
2664 | ||
b6e978e5 FF |
2665 | /* disable ethernet MAC while updating its registers */ |
2666 | umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); | |
2667 | ||
2668 | bcmgenet_set_hw_addr(priv, dev->dev_addr); | |
2669 | ||
2670 | if (phy_is_internal(priv->phydev)) { | |
2671 | reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); | |
2672 | reg |= EXT_ENERGY_DET_MASK; | |
2673 | bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); | |
2674 | } | |
2675 | ||
2676 | /* Disable RX/TX DMA and flush TX queues */ | |
2677 | dma_ctrl = bcmgenet_dma_disable(priv); | |
2678 | ||
2679 | /* Reinitialize TDMA and RDMA and SW housekeeping */ | |
2680 | ret = bcmgenet_init_dma(priv); | |
2681 | if (ret) { | |
2682 | netdev_err(dev, "failed to initialize DMA\n"); | |
2683 | goto out_clk_disable; | |
2684 | } | |
2685 | ||
2686 | /* Always enable ring 16 - descriptor ring */ | |
2687 | bcmgenet_enable_dma(priv, dma_ctrl); | |
2688 | ||
2689 | netif_device_attach(dev); | |
2690 | ||
2691 | bcmgenet_netif_start(dev); | |
2692 | ||
2693 | return 0; | |
2694 | ||
2695 | out_clk_disable: | |
2696 | clk_disable_unprepare(priv->clk); | |
2697 | return ret; | |
2698 | } | |
2699 | #endif /* CONFIG_PM_SLEEP */ | |
2700 | ||
2701 | static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); | |
2702 | ||
1c1008c7 FF |
2703 | static struct platform_driver bcmgenet_driver = { |
2704 | .probe = bcmgenet_probe, | |
2705 | .remove = bcmgenet_remove, | |
2706 | .driver = { | |
2707 | .name = "bcmgenet", | |
2708 | .owner = THIS_MODULE, | |
2709 | .of_match_table = bcmgenet_match, | |
b6e978e5 | 2710 | .pm = &bcmgenet_pm_ops, |
1c1008c7 FF |
2711 | }, |
2712 | }; | |
2713 | module_platform_driver(bcmgenet_driver); | |
2714 | ||
2715 | MODULE_AUTHOR("Broadcom Corporation"); | |
2716 | MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); | |
2717 | MODULE_ALIAS("platform:bcmgenet"); | |
2718 | MODULE_LICENSE("GPL"); |