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net: bcmgenet: suspend and resume from Wake-on-LAN
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
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1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20#define pr_fmt(fmt) "bcmgenet: " fmt
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/sched.h>
25#include <linux/types.h>
26#include <linux/fcntl.h>
27#include <linux/interrupt.h>
28#include <linux/string.h>
29#include <linux/if_ether.h>
30#include <linux/init.h>
31#include <linux/errno.h>
32#include <linux/delay.h>
33#include <linux/platform_device.h>
34#include <linux/dma-mapping.h>
35#include <linux/pm.h>
36#include <linux/clk.h>
1c1008c7
FF		 37#include <linux/of.h>
38#include <linux/of_address.h>
39#include <linux/of_irq.h>
40#include <linux/of_net.h>
41#include <linux/of_platform.h>
42#include <net/arp.h>
43
44#include <linux/mii.h>
45#include <linux/ethtool.h>
46#include <linux/netdevice.h>
47#include <linux/inetdevice.h>
48#include <linux/etherdevice.h>
49#include <linux/skbuff.h>
50#include <linux/in.h>
51#include <linux/ip.h>
52#include <linux/ipv6.h>
53#include <linux/phy.h>
54
55#include <asm/unaligned.h>
56
57#include "bcmgenet.h"
58
59/* Maximum number of hardware queues, downsized if needed */
60#define GENET_MAX_MQ_CNT 4
61
62/* Default highest priority queue for multi queue support */
63#define GENET_Q0_PRIORITY 0
64
65#define GENET_DEFAULT_BD_CNT \
66 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
67
68#define RX_BUF_LENGTH 2048
69#define SKB_ALIGNMENT 32
70
71/* Tx/Rx DMA register offset, skip 256 descriptors */
72#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
73#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
74
75#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
76 TOTAL_DESC * DMA_DESC_SIZE)
77
78#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
79 TOTAL_DESC * DMA_DESC_SIZE)
80
81static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
82 void __iomem *d, u32 value)
83{
84 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
88 void __iomem *d)
89{
90 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
91}
92
93static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
94 void __iomem *d,
95 dma_addr_t addr)
96{
97 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
98
99 /* Register writes to GISB bus can take couple hundred nanoseconds
100 * and are done for each packet, save these expensive writes unless
101 * the platform is explicitely configured for 64-bits/LPAE.
102 */
103#ifdef CONFIG_PHYS_ADDR_T_64BIT
104 if (priv->hw_params->flags & GENET_HAS_40BITS)
105 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
106#endif
107}
108
109/* Combined address + length/status setter */
110static inline void dmadesc_set(struct bcmgenet_priv *priv,
111 void __iomem *d, dma_addr_t addr, u32 val)
112{
113 dmadesc_set_length_status(priv, d, val);
114 dmadesc_set_addr(priv, d, addr);
115}
116
117static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
118 void __iomem *d)
119{
120 dma_addr_t addr;
121
122 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
123
124 /* Register writes to GISB bus can take couple hundred nanoseconds
125 * and are done for each packet, save these expensive writes unless
126 * the platform is explicitely configured for 64-bits/LPAE.
127 */
128#ifdef CONFIG_PHYS_ADDR_T_64BIT
129 if (priv->hw_params->flags & GENET_HAS_40BITS)
130 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
131#endif
132 return addr;
133}
134
135#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
136
137#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
138 NETIF_MSG_LINK)
139
140static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
141{
142 if (GENET_IS_V1(priv))
143 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
144 else
145 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
146}
147
148static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
149{
150 if (GENET_IS_V1(priv))
151 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
152 else
153 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
154}
155
156/* These macros are defined to deal with register map change
157 * between GENET1.1 and GENET2. Only those currently being used
158 * by driver are defined.
159 */
160static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
161{
162 if (GENET_IS_V1(priv))
163 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
164 else
165 return __raw_readl(priv->base +
166 priv->hw_params->tbuf_offset + TBUF_CTRL);
167}
168
169static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
170{
171 if (GENET_IS_V1(priv))
172 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
173 else
174 __raw_writel(val, priv->base +
175 priv->hw_params->tbuf_offset + TBUF_CTRL);
176}
177
178static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
179{
180 if (GENET_IS_V1(priv))
181 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
182 else
183 return __raw_readl(priv->base +
184 priv->hw_params->tbuf_offset + TBUF_BP_MC);
185}
186
187static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
188{
189 if (GENET_IS_V1(priv))
190 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
191 else
192 __raw_writel(val, priv->base +
193 priv->hw_params->tbuf_offset + TBUF_BP_MC);
194}
195
196/* RX/TX DMA register accessors */
197enum dma_reg {
198 DMA_RING_CFG = 0,
199 DMA_CTRL,
200 DMA_STATUS,
201 DMA_SCB_BURST_SIZE,
202 DMA_ARB_CTRL,
203 DMA_PRIORITY,
204 DMA_RING_PRIORITY,
205};
206
207static const u8 bcmgenet_dma_regs_v3plus[] = {
208 [DMA_RING_CFG] = 0x00,
209 [DMA_CTRL] = 0x04,
210 [DMA_STATUS] = 0x08,
211 [DMA_SCB_BURST_SIZE] = 0x0C,
212 [DMA_ARB_CTRL] = 0x2C,
213 [DMA_PRIORITY] = 0x30,
214 [DMA_RING_PRIORITY] = 0x38,
215};
216
217static const u8 bcmgenet_dma_regs_v2[] = {
218 [DMA_RING_CFG] = 0x00,
219 [DMA_CTRL] = 0x04,
220 [DMA_STATUS] = 0x08,
221 [DMA_SCB_BURST_SIZE] = 0x0C,
222 [DMA_ARB_CTRL] = 0x30,
223 [DMA_PRIORITY] = 0x34,
224 [DMA_RING_PRIORITY] = 0x3C,
225};
226
227static const u8 bcmgenet_dma_regs_v1[] = {
228 [DMA_CTRL] = 0x00,
229 [DMA_STATUS] = 0x04,
230 [DMA_SCB_BURST_SIZE] = 0x0C,
231 [DMA_ARB_CTRL] = 0x30,
232 [DMA_PRIORITY] = 0x34,
233 [DMA_RING_PRIORITY] = 0x3C,
234};
235
236/* Set at runtime once bcmgenet version is known */
237static const u8 *bcmgenet_dma_regs;
238
239static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
240{
241 return netdev_priv(dev_get_drvdata(dev));
242}
243
244static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
245 enum dma_reg r)
246{
247 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
248 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
249}
250
251static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
252 u32 val, enum dma_reg r)
253{
254 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
255 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
256}
257
258static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
259 enum dma_reg r)
260{
261 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
262 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
263}
264
265static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
266 u32 val, enum dma_reg r)
267{
268 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
269 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
270}
271
272/* RDMA/TDMA ring registers and accessors
273 * we merge the common fields and just prefix with T/D the registers
274 * having different meaning depending on the direction
275 */
276enum dma_ring_reg {
277 TDMA_READ_PTR = 0,
278 RDMA_WRITE_PTR = TDMA_READ_PTR,
279 TDMA_READ_PTR_HI,
280 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
281 TDMA_CONS_INDEX,
282 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
283 TDMA_PROD_INDEX,
284 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
285 DMA_RING_BUF_SIZE,
286 DMA_START_ADDR,
287 DMA_START_ADDR_HI,
288 DMA_END_ADDR,
289 DMA_END_ADDR_HI,
290 DMA_MBUF_DONE_THRESH,
291 TDMA_FLOW_PERIOD,
292 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
293 TDMA_WRITE_PTR,
294 RDMA_READ_PTR = TDMA_WRITE_PTR,
295 TDMA_WRITE_PTR_HI,
296 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
297};
298
299/* GENET v4 supports 40-bits pointer addressing
300 * for obvious reasons the LO and HI word parts
301 * are contiguous, but this offsets the other
302 * registers.
303 */
304static const u8 genet_dma_ring_regs_v4[] = {
305 [TDMA_READ_PTR] = 0x00,
306 [TDMA_READ_PTR_HI] = 0x04,
307 [TDMA_CONS_INDEX] = 0x08,
308 [TDMA_PROD_INDEX] = 0x0C,
309 [DMA_RING_BUF_SIZE] = 0x10,
310 [DMA_START_ADDR] = 0x14,
311 [DMA_START_ADDR_HI] = 0x18,
312 [DMA_END_ADDR] = 0x1C,
313 [DMA_END_ADDR_HI] = 0x20,
314 [DMA_MBUF_DONE_THRESH] = 0x24,
315 [TDMA_FLOW_PERIOD] = 0x28,
316 [TDMA_WRITE_PTR] = 0x2C,
317 [TDMA_WRITE_PTR_HI] = 0x30,
318};
319
320static const u8 genet_dma_ring_regs_v123[] = {
321 [TDMA_READ_PTR] = 0x00,
322 [TDMA_CONS_INDEX] = 0x04,
323 [TDMA_PROD_INDEX] = 0x08,
324 [DMA_RING_BUF_SIZE] = 0x0C,
325 [DMA_START_ADDR] = 0x10,
326 [DMA_END_ADDR] = 0x14,
327 [DMA_MBUF_DONE_THRESH] = 0x18,
328 [TDMA_FLOW_PERIOD] = 0x1C,
329 [TDMA_WRITE_PTR] = 0x20,
330};
331
332/* Set at runtime once GENET version is known */
333static const u8 *genet_dma_ring_regs;
334
335static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
336 unsigned int ring,
337 enum dma_ring_reg r)
338{
339 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
340 (DMA_RING_SIZE * ring) +
341 genet_dma_ring_regs[r]);
342}
343
344static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
345 unsigned int ring,
346 u32 val,
347 enum dma_ring_reg r)
348{
349 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
350 (DMA_RING_SIZE * ring) +
351 genet_dma_ring_regs[r]);
352}
353
354static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
355 unsigned int ring,
356 enum dma_ring_reg r)
357{
358 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
359 (DMA_RING_SIZE * ring) +
360 genet_dma_ring_regs[r]);
361}
362
363static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
364 unsigned int ring,
365 u32 val,
366 enum dma_ring_reg r)
367{
368 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
369 (DMA_RING_SIZE * ring) +
370 genet_dma_ring_regs[r]);
371}
372
373static int bcmgenet_get_settings(struct net_device *dev,
374 struct ethtool_cmd *cmd)
375{
376 struct bcmgenet_priv *priv = netdev_priv(dev);
377
378 if (!netif_running(dev))
379 return -EINVAL;
380
381 if (!priv->phydev)
382 return -ENODEV;
383
384 return phy_ethtool_gset(priv->phydev, cmd);
385}
386
387static int bcmgenet_set_settings(struct net_device *dev,
388 struct ethtool_cmd *cmd)
389{
390 struct bcmgenet_priv *priv = netdev_priv(dev);
391
392 if (!netif_running(dev))
393 return -EINVAL;
394
395 if (!priv->phydev)
396 return -ENODEV;
397
398 return phy_ethtool_sset(priv->phydev, cmd);
399}
400
401static int bcmgenet_set_rx_csum(struct net_device *dev,
402 netdev_features_t wanted)
403{
404 struct bcmgenet_priv *priv = netdev_priv(dev);
405 u32 rbuf_chk_ctrl;
406 bool rx_csum_en;
407
408 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
409
410 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
411
412 /* enable rx checksumming */
413 if (rx_csum_en)
414 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
415 else
416 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
417 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 418
419 /* If UniMAC forwards CRC, we need to skip over it to get
420 * a valid CHK bit to be set in the per-packet status word
421 */
422 if (rx_csum_en && priv->crc_fwd_en)
423 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
424 else
425 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
426
1c1008c7
FF		 427 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
428
429 return 0;
430}
431
432static int bcmgenet_set_tx_csum(struct net_device *dev,
433 netdev_features_t wanted)
434{
435 struct bcmgenet_priv *priv = netdev_priv(dev);
436 bool desc_64b_en;
437 u32 tbuf_ctrl, rbuf_ctrl;
438
439 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
440 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
441
442 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
443
444 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
445 if (desc_64b_en) {
446 tbuf_ctrl |= RBUF_64B_EN;
447 rbuf_ctrl |= RBUF_64B_EN;
448 } else {
449 tbuf_ctrl &= ~RBUF_64B_EN;
450 rbuf_ctrl &= ~RBUF_64B_EN;
451 }
452 priv->desc_64b_en = desc_64b_en;
453
454 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
455 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
456
457 return 0;
458}
459
460static int bcmgenet_set_features(struct net_device *dev,
461 netdev_features_t features)
462{
463 netdev_features_t changed = features ^ dev->features;
464 netdev_features_t wanted = dev->wanted_features;
465 int ret = 0;
466
467 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
468 ret = bcmgenet_set_tx_csum(dev, wanted);
469 if (changed & (NETIF_F_RXCSUM))
470 ret = bcmgenet_set_rx_csum(dev, wanted);
471
472 return ret;
473}
474
475static u32 bcmgenet_get_msglevel(struct net_device *dev)
476{
477 struct bcmgenet_priv *priv = netdev_priv(dev);
478
479 return priv->msg_enable;
480}
481
482static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
483{
484 struct bcmgenet_priv *priv = netdev_priv(dev);
485
486 priv->msg_enable = level;
487}
488
489/* standard ethtool support functions. */
490enum bcmgenet_stat_type {
491 BCMGENET_STAT_NETDEV = -1,
492 BCMGENET_STAT_MIB_RX,
493 BCMGENET_STAT_MIB_TX,
494 BCMGENET_STAT_RUNT,
495 BCMGENET_STAT_MISC,
496};
497
498struct bcmgenet_stats {
499 char stat_string[ETH_GSTRING_LEN];
500 int stat_sizeof;
501 int stat_offset;
502 enum bcmgenet_stat_type type;
503 /* reg offset from UMAC base for misc counters */
504 u16 reg_offset;
505};
506
507#define STAT_NETDEV(m) { \
508 .stat_string = __stringify(m), \
509 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
510 .stat_offset = offsetof(struct net_device_stats, m), \
511 .type = BCMGENET_STAT_NETDEV, \
512}
513
514#define STAT_GENET_MIB(str, m, _type) { \
515 .stat_string = str, \
516 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
517 .stat_offset = offsetof(struct bcmgenet_priv, m), \
518 .type = _type, \
519}
520
521#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
522#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
523#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
524
525#define STAT_GENET_MISC(str, m, offset) { \
526 .stat_string = str, \
527 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
528 .stat_offset = offsetof(struct bcmgenet_priv, m), \
529 .type = BCMGENET_STAT_MISC, \
530 .reg_offset = offset, \
531}
532
533
534/* There is a 0xC gap between the end of RX and beginning of TX stats and then
535 * between the end of TX stats and the beginning of the RX RUNT
536 */
537#define BCMGENET_STAT_OFFSET 0xc
538
539/* Hardware counters must be kept in sync because the order/offset
540 * is important here (order in structure declaration = order in hardware)
541 */
542static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
543 /* general stats */
544 STAT_NETDEV(rx_packets),
545 STAT_NETDEV(tx_packets),
546 STAT_NETDEV(rx_bytes),
547 STAT_NETDEV(tx_bytes),
548 STAT_NETDEV(rx_errors),
549 STAT_NETDEV(tx_errors),
550 STAT_NETDEV(rx_dropped),
551 STAT_NETDEV(tx_dropped),
552 STAT_NETDEV(multicast),
553 /* UniMAC RSV counters */
554 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
555 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
556 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
557 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
558 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
559 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
560 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
561 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
562 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
563 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
564 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
565 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
566 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
567 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
568 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
569 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
570 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
571 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
572 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
573 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
574 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
575 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
576 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
577 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
578 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
579 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
580 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
581 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
582 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
583 /* UniMAC TSV counters */
584 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
585 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
586 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
587 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
588 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
589 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
590 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
591 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
592 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
593 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
594 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
595 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
596 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
597 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
598 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
599 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
600 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
601 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
602 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
603 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
604 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
605 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
606 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
607 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
608 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
609 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
610 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
611 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
612 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
613 /* UniMAC RUNT counters */
614 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
615 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
616 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
617 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
618 /* Misc UniMAC counters */
619 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
620 UMAC_RBUF_OVFL_CNT),
621 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
622 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
623};
624
625#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
626
627static void bcmgenet_get_drvinfo(struct net_device *dev,
628 struct ethtool_drvinfo *info)
629{
630 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
631 strlcpy(info->version, "v2.0", sizeof(info->version));
632 info->n_stats = BCMGENET_STATS_LEN;
633
634}
635
636static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
637{
638 switch (string_set) {
639 case ETH_SS_STATS:
640 return BCMGENET_STATS_LEN;
641 default:
642 return -EOPNOTSUPP;
643 }
644}
645
646static void bcmgenet_get_strings(struct net_device *dev,
647 u32 stringset, u8 *data)
648{
649 int i;
650
651 switch (stringset) {
652 case ETH_SS_STATS:
653 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
654 memcpy(data + i * ETH_GSTRING_LEN,
655 bcmgenet_gstrings_stats[i].stat_string,
656 ETH_GSTRING_LEN);
657 }
658 break;
659 }
660}
661
662static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
663{
664 int i, j = 0;
665
666 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
667 const struct bcmgenet_stats *s;
668 u8 offset = 0;
669 u32 val = 0;
670 char *p;
671
672 s = &bcmgenet_gstrings_stats[i];
673 switch (s->type) {
674 case BCMGENET_STAT_NETDEV:
675 continue;
676 case BCMGENET_STAT_MIB_RX:
677 case BCMGENET_STAT_MIB_TX:
678 case BCMGENET_STAT_RUNT:
679 if (s->type != BCMGENET_STAT_MIB_RX)
680 offset = BCMGENET_STAT_OFFSET;
681 val = bcmgenet_umac_readl(priv, UMAC_MIB_START +
682 j + offset);
683 break;
684 case BCMGENET_STAT_MISC:
685 val = bcmgenet_umac_readl(priv, s->reg_offset);
686 /* clear if overflowed */
687 if (val == ~0)
688 bcmgenet_umac_writel(priv, 0, s->reg_offset);
689 break;
690 }
691
692 j += s->stat_sizeof;
693 p = (char *)priv + s->stat_offset;
694 *(u32 *)p = val;
695 }
696}
697
698static void bcmgenet_get_ethtool_stats(struct net_device *dev,
699 struct ethtool_stats *stats,
700 u64 *data)
701{
702 struct bcmgenet_priv *priv = netdev_priv(dev);
703 int i;
704
705 if (netif_running(dev))
706 bcmgenet_update_mib_counters(priv);
707
708 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
709 const struct bcmgenet_stats *s;
710 char *p;
711
712 s = &bcmgenet_gstrings_stats[i];
713 if (s->type == BCMGENET_STAT_NETDEV)
714 p = (char *)&dev->stats;
715 else
716 p = (char *)priv;
717 p += s->stat_offset;
718 data[i] = *(u32 *)p;
719 }
720}
721
722/* standard ethtool support functions. */
723static struct ethtool_ops bcmgenet_ethtool_ops = {
724 .get_strings = bcmgenet_get_strings,
725 .get_sset_count = bcmgenet_get_sset_count,
726 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
727 .get_settings = bcmgenet_get_settings,
728 .set_settings = bcmgenet_set_settings,
729 .get_drvinfo = bcmgenet_get_drvinfo,
730 .get_link = ethtool_op_get_link,
731 .get_msglevel = bcmgenet_get_msglevel,
732 .set_msglevel = bcmgenet_set_msglevel,
733};
734
735/* Power down the unimac, based on mode. */
736static void bcmgenet_power_down(struct bcmgenet_priv *priv,
737 enum bcmgenet_power_mode mode)
738{
739 u32 reg;
740
741 switch (mode) {
742 case GENET_POWER_CABLE_SENSE:
80d8e96d 743 phy_detach(priv->phydev);
1c1008c7
FF		 744 break;
745
c3ae64ae
FF		 746 case GENET_POWER_WOL_MAGIC:
747 bcmgenet_wol_power_down_cfg(priv, mode);
748 break;
749
1c1008c7
FF		 750 case GENET_POWER_PASSIVE:
751 /* Power down LED */
752 bcmgenet_mii_reset(priv->dev);
753 if (priv->hw_params->flags & GENET_HAS_EXT) {
754 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
755 reg |= (EXT_PWR_DOWN_PHY |
756 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
757 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
758 }
759 break;
760 default:
761 break;
762 }
763}
764
765static void bcmgenet_power_up(struct bcmgenet_priv *priv,
766 enum bcmgenet_power_mode mode)
767{
768 u32 reg;
769
770 if (!(priv->hw_params->flags & GENET_HAS_EXT))
771 return;
772
773 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
774
775 switch (mode) {
776 case GENET_POWER_PASSIVE:
777 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
778 EXT_PWR_DOWN_BIAS);
779 /* fallthrough */
780 case GENET_POWER_CABLE_SENSE:
781 /* enable APD */
782 reg |= EXT_PWR_DN_EN_LD;
783 break;
c3ae64ae
FF		 784 case GENET_POWER_WOL_MAGIC:
785 bcmgenet_wol_power_up_cfg(priv, mode);
786 return;
1c1008c7
FF		 787 default:
788 break;
789 }
790
791 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
792 bcmgenet_mii_reset(priv->dev);
793}
794
795/* ioctl handle special commands that are not present in ethtool. */
796static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
797{
798 struct bcmgenet_priv *priv = netdev_priv(dev);
799 int val = 0;
800
801 if (!netif_running(dev))
802 return -EINVAL;
803
804 switch (cmd) {
805 case SIOCGMIIPHY:
806 case SIOCGMIIREG:
807 case SIOCSMIIREG:
808 if (!priv->phydev)
809 val = -ENODEV;
810 else
811 val = phy_mii_ioctl(priv->phydev, rq, cmd);
812 break;
813
814 default:
815 val = -EINVAL;
816 break;
817 }
818
819 return val;
820}
821
822static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
823 struct bcmgenet_tx_ring *ring)
824{
825 struct enet_cb *tx_cb_ptr;
826
827 tx_cb_ptr = ring->cbs;
828 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
829 tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
830 /* Advancing local write pointer */
831 if (ring->write_ptr == ring->end_ptr)
832 ring->write_ptr = ring->cb_ptr;
833 else
834 ring->write_ptr++;
835
836 return tx_cb_ptr;
837}
838
839/* Simple helper to free a control block's resources */
840static void bcmgenet_free_cb(struct enet_cb *cb)
841{
842 dev_kfree_skb_any(cb->skb);
843 cb->skb = NULL;
844 dma_unmap_addr_set(cb, dma_addr, 0);
845}
846
847static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
848 struct bcmgenet_tx_ring *ring)
849{
850 bcmgenet_intrl2_0_writel(priv,
851 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
852 INTRL2_CPU_MASK_SET);
853}
854
855static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
856 struct bcmgenet_tx_ring *ring)
857{
858 bcmgenet_intrl2_0_writel(priv,
859 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
860 INTRL2_CPU_MASK_CLEAR);
861}
862
863static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
864 struct bcmgenet_tx_ring *ring)
865{
866 bcmgenet_intrl2_1_writel(priv,
867 (1 << ring->index), INTRL2_CPU_MASK_CLEAR);
868 priv->int1_mask &= ~(1 << ring->index);
869}
870
871static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
872 struct bcmgenet_tx_ring *ring)
873{
874 bcmgenet_intrl2_1_writel(priv,
875 (1 << ring->index), INTRL2_CPU_MASK_SET);
876 priv->int1_mask |= (1 << ring->index);
877}
878
879/* Unlocked version of the reclaim routine */
880static void __bcmgenet_tx_reclaim(struct net_device *dev,
881 struct bcmgenet_tx_ring *ring)
882{
883 struct bcmgenet_priv *priv = netdev_priv(dev);
884 int last_tx_cn, last_c_index, num_tx_bds;
885 struct enet_cb *tx_cb_ptr;
b2cde2cc 886 struct netdev_queue *txq;
1c1008c7
FF		 887 unsigned int c_index;
888
889 /* Compute how many buffers are transmited since last xmit call */
890 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
b2cde2cc 891 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 892
893 last_c_index = ring->c_index;
894 num_tx_bds = ring->size;
895
896 c_index &= (num_tx_bds - 1);
897
898 if (c_index >= last_c_index)
899 last_tx_cn = c_index - last_c_index;
900 else
901 last_tx_cn = num_tx_bds - last_c_index + c_index;
902
903 netif_dbg(priv, tx_done, dev,
904 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
905 __func__, ring->index,
906 c_index, last_tx_cn, last_c_index);
907
908 /* Reclaim transmitted buffers */
909 while (last_tx_cn-- > 0) {
910 tx_cb_ptr = ring->cbs + last_c_index;
911 if (tx_cb_ptr->skb) {
912 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
913 dma_unmap_single(&dev->dev,
914 dma_unmap_addr(tx_cb_ptr, dma_addr),
915 tx_cb_ptr->skb->len,
916 DMA_TO_DEVICE);
917 bcmgenet_free_cb(tx_cb_ptr);
918 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
919 dev->stats.tx_bytes +=
920 dma_unmap_len(tx_cb_ptr, dma_len);
921 dma_unmap_page(&dev->dev,
922 dma_unmap_addr(tx_cb_ptr, dma_addr),
923 dma_unmap_len(tx_cb_ptr, dma_len),
924 DMA_TO_DEVICE);
925 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
926 }
927 dev->stats.tx_packets++;
928 ring->free_bds += 1;
929
930 last_c_index++;
931 last_c_index &= (num_tx_bds - 1);
932 }
933
934 if (ring->free_bds > (MAX_SKB_FRAGS + 1))
935 ring->int_disable(priv, ring);
936
b2cde2cc
FF		 937 if (netif_tx_queue_stopped(txq))
938 netif_tx_wake_queue(txq);
1c1008c7
FF		 939
940 ring->c_index = c_index;
941}
942
943static void bcmgenet_tx_reclaim(struct net_device *dev,
944 struct bcmgenet_tx_ring *ring)
945{
946 unsigned long flags;
947
948 spin_lock_irqsave(&ring->lock, flags);
949 __bcmgenet_tx_reclaim(dev, ring);
950 spin_unlock_irqrestore(&ring->lock, flags);
951}
952
953static void bcmgenet_tx_reclaim_all(struct net_device *dev)
954{
955 struct bcmgenet_priv *priv = netdev_priv(dev);
956 int i;
957
958 if (netif_is_multiqueue(dev)) {
959 for (i = 0; i < priv->hw_params->tx_queues; i++)
960 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
961 }
962
963 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
964}
965
966/* Transmits a single SKB (either head of a fragment or a single SKB)
967 * caller must hold priv->lock
968 */
969static int bcmgenet_xmit_single(struct net_device *dev,
970 struct sk_buff *skb,
971 u16 dma_desc_flags,
972 struct bcmgenet_tx_ring *ring)
973{
974 struct bcmgenet_priv *priv = netdev_priv(dev);
975 struct device *kdev = &priv->pdev->dev;
976 struct enet_cb *tx_cb_ptr;
977 unsigned int skb_len;
978 dma_addr_t mapping;
979 u32 length_status;
980 int ret;
981
982 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
983
984 if (unlikely(!tx_cb_ptr))
985 BUG();
986
987 tx_cb_ptr->skb = skb;
988
989 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
990
991 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
992 ret = dma_mapping_error(kdev, mapping);
993 if (ret) {
994 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
995 dev_kfree_skb(skb);
996 return ret;
997 }
998
999 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1000 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1001 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1002 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1003 DMA_TX_APPEND_CRC;
1004
1005 if (skb->ip_summed == CHECKSUM_PARTIAL)
1006 length_status |= DMA_TX_DO_CSUM;
1007
1008 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1009
1010 /* Decrement total BD count and advance our write pointer */
1011 ring->free_bds -= 1;
1012 ring->prod_index += 1;
1013 ring->prod_index &= DMA_P_INDEX_MASK;
1014
1015 return 0;
1016}
1017
1018/* Transmit a SKB fragement */
1019static int bcmgenet_xmit_frag(struct net_device *dev,
1020 skb_frag_t *frag,
1021 u16 dma_desc_flags,
1022 struct bcmgenet_tx_ring *ring)
1023{
1024 struct bcmgenet_priv *priv = netdev_priv(dev);
1025 struct device *kdev = &priv->pdev->dev;
1026 struct enet_cb *tx_cb_ptr;
1027 dma_addr_t mapping;
1028 int ret;
1029
1030 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1031
1032 if (unlikely(!tx_cb_ptr))
1033 BUG();
1034 tx_cb_ptr->skb = NULL;
1035
1036 mapping = skb_frag_dma_map(kdev, frag, 0,
1037 skb_frag_size(frag), DMA_TO_DEVICE);
1038 ret = dma_mapping_error(kdev, mapping);
1039 if (ret) {
1040 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1041 __func__);
1042 return ret;
1043 }
1044
1045 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1046 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1047
1048 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1049 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1050 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1051
1052
1053 ring->free_bds -= 1;
1054 ring->prod_index += 1;
1055 ring->prod_index &= DMA_P_INDEX_MASK;
1056
1057 return 0;
1058}
1059
1060/* Reallocate the SKB to put enough headroom in front of it and insert
1061 * the transmit checksum offsets in the descriptors
1062 */
1063static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb)
1064{
1065 struct status_64 *status = NULL;
1066 struct sk_buff *new_skb;
1067 u16 offset;
1068 u8 ip_proto;
1069 u16 ip_ver;
1070 u32 tx_csum_info;
1071
1072 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1073 /* If 64 byte status block enabled, must make sure skb has
1074 * enough headroom for us to insert 64B status block.
1075 */
1076 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1077 dev_kfree_skb(skb);
1078 if (!new_skb) {
1079 dev->stats.tx_errors++;
1080 dev->stats.tx_dropped++;
1081 return -ENOMEM;
1082 }
1083 skb = new_skb;
1084 }
1085
1086 skb_push(skb, sizeof(*status));
1087 status = (struct status_64 *)skb->data;
1088
1089 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1090 ip_ver = htons(skb->protocol);
1091 switch (ip_ver) {
1092 case ETH_P_IP:
1093 ip_proto = ip_hdr(skb)->protocol;
1094 break;
1095 case ETH_P_IPV6:
1096 ip_proto = ipv6_hdr(skb)->nexthdr;
1097 break;
1098 default:
1099 return 0;
1100 }
1101
1102 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1103 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1104 (offset + skb->csum_offset);
1105
1106 /* Set the length valid bit for TCP and UDP and just set
1107 * the special UDP flag for IPv4, else just set to 0.
1108 */
1109 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1110 tx_csum_info |= STATUS_TX_CSUM_LV;
1111 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1112 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1113 } else
1114 tx_csum_info = 0;
1115
1116 status->tx_csum_info = tx_csum_info;
1117 }
1118
1119 return 0;
1120}
1121
1122static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1123{
1124 struct bcmgenet_priv *priv = netdev_priv(dev);
1125 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1126 struct netdev_queue *txq;
1c1008c7
FF		 1127 unsigned long flags = 0;
1128 int nr_frags, index;
1129 u16 dma_desc_flags;
1130 int ret;
1131 int i;
1132
1133 index = skb_get_queue_mapping(skb);
1134 /* Mapping strategy:
1135 * queue_mapping = 0, unclassified, packet xmited through ring16
1136 * queue_mapping = 1, goes to ring 0. (highest priority queue
1137 * queue_mapping = 2, goes to ring 1.
1138 * queue_mapping = 3, goes to ring 2.
1139 * queue_mapping = 4, goes to ring 3.
1140 */
1141 if (index == 0)
1142 index = DESC_INDEX;
1143 else
1144 index -= 1;
1145
1c1008c7
FF		 1146 nr_frags = skb_shinfo(skb)->nr_frags;
1147 ring = &priv->tx_rings[index];
b2cde2cc 1148 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1149
1150 spin_lock_irqsave(&ring->lock, flags);
1151 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1152 netif_tx_stop_queue(txq);
1c1008c7
FF		 1153 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1154 __func__, index, ring->queue);
1155 ret = NETDEV_TX_BUSY;
1156 goto out;
1157 }
1158
1c1008c7
FF		 1159 /* set the SKB transmit checksum */
1160 if (priv->desc_64b_en) {
1161 ret = bcmgenet_put_tx_csum(dev, skb);
1162 if (ret) {
1163 ret = NETDEV_TX_OK;
1164 goto out;
1165 }
1166 }
1167
1168 dma_desc_flags = DMA_SOP;
1169 if (nr_frags == 0)
1170 dma_desc_flags |= DMA_EOP;
1171
1172 /* Transmit single SKB or head of fragment list */
1173 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1174 if (ret) {
1175 ret = NETDEV_TX_OK;
1176 goto out;
1177 }
1178
1179 /* xmit fragment */
1180 for (i = 0; i < nr_frags; i++) {
1181 ret = bcmgenet_xmit_frag(dev,
1182 &skb_shinfo(skb)->frags[i],
1183 (i == nr_frags - 1) ? DMA_EOP : 0, ring);
1184 if (ret) {
1185 ret = NETDEV_TX_OK;
1186 goto out;
1187 }
1188 }
1189
d03825fb
FF		 1190 skb_tx_timestamp(skb);
1191
1c1008c7
FF		 1192 /* we kept a software copy of how much we should advance the TDMA
1193 * producer index, now write it down to the hardware
1194 */
1195 bcmgenet_tdma_ring_writel(priv, ring->index,
1196 ring->prod_index, TDMA_PROD_INDEX);
1197
1198 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
b2cde2cc 1199 netif_tx_stop_queue(txq);
1c1008c7
FF		 1200 ring->int_enable(priv, ring);
1201 }
1202
1203out:
1204 spin_unlock_irqrestore(&ring->lock, flags);
1205
1206 return ret;
1207}
1208
1209
1210static int bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1211 struct enet_cb *cb)
1212{
1213 struct device *kdev = &priv->pdev->dev;
1214 struct sk_buff *skb;
1215 dma_addr_t mapping;
1216 int ret;
1217
1218 skb = netdev_alloc_skb(priv->dev,
1219 priv->rx_buf_len + SKB_ALIGNMENT);
1220 if (!skb)
1221 return -ENOMEM;
1222
1223 /* a caller did not release this control block */
1224 WARN_ON(cb->skb != NULL);
1225 cb->skb = skb;
1226 mapping = dma_map_single(kdev, skb->data,
1227 priv->rx_buf_len, DMA_FROM_DEVICE);
1228 ret = dma_mapping_error(kdev, mapping);
1229 if (ret) {
1230 bcmgenet_free_cb(cb);
1231 netif_err(priv, rx_err, priv->dev,
1232 "%s DMA map failed\n", __func__);
1233 return ret;
1234 }
1235
1236 dma_unmap_addr_set(cb, dma_addr, mapping);
1237 /* assign packet, prepare descriptor, and advance pointer */
1238
1239 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1240
1241 /* turn on the newly assigned BD for DMA to use */
1242 priv->rx_bd_assign_index++;
1243 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1244
1245 priv->rx_bd_assign_ptr = priv->rx_bds +
1246 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1247
1248 return 0;
1249}
1250
1251/* bcmgenet_desc_rx - descriptor based rx process.
1252 * this could be called from bottom half, or from NAPI polling method.
1253 */
1254static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1255 unsigned int budget)
1256{
1257 struct net_device *dev = priv->dev;
1258 struct enet_cb *cb;
1259 struct sk_buff *skb;
1260 u32 dma_length_status;
1261 unsigned long dma_flag;
1262 int len, err;
1263 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1264 unsigned int p_index;
1265 unsigned int chksum_ok = 0;
1266
1267 p_index = bcmgenet_rdma_ring_readl(priv,
1268 DESC_INDEX, RDMA_PROD_INDEX);
1269 p_index &= DMA_P_INDEX_MASK;
1270
1271 if (p_index < priv->rx_c_index)
1272 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1273 priv->rx_c_index + p_index;
1274 else
1275 rxpkttoprocess = p_index - priv->rx_c_index;
1276
1277 netif_dbg(priv, rx_status, dev,
1278 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1279
1280 while ((rxpktprocessed < rxpkttoprocess) &&
1281 (rxpktprocessed < budget)) {
1282
1283 /* Unmap the packet contents such that we can use the
1284 * RSV from the 64 bytes descriptor when enabled and save
1285 * a 32-bits register read
1286 */
1287 cb = &priv->rx_cbs[priv->rx_read_ptr];
1288 skb = cb->skb;
1289 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1290 priv->rx_buf_len, DMA_FROM_DEVICE);
1291
1292 if (!priv->desc_64b_en) {
1293 dma_length_status = dmadesc_get_length_status(priv,
1294 priv->rx_bds +
1295 (priv->rx_read_ptr *
1296 DMA_DESC_SIZE));
1297 } else {
1298 struct status_64 *status;
1299 status = (struct status_64 *)skb->data;
1300 dma_length_status = status->length_status;
1301 }
1302
1303 /* DMA flags and length are still valid no matter how
1304 * we got the Receive Status Vector (64B RSB or register)
1305 */
1306 dma_flag = dma_length_status & 0xffff;
1307 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1308
1309 netif_dbg(priv, rx_status, dev,
1310 "%s: p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1311 __func__, p_index, priv->rx_c_index, priv->rx_read_ptr,
1312 dma_length_status);
1313
1314 rxpktprocessed++;
1315
1316 priv->rx_read_ptr++;
1317 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1318
1319 /* out of memory, just drop packets at the hardware level */
1320 if (unlikely(!skb)) {
1321 dev->stats.rx_dropped++;
1322 dev->stats.rx_errors++;
1323 goto refill;
1324 }
1325
1326 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1327 netif_err(priv, rx_status, dev,
1328 "Droping fragmented packet!\n");
1329 dev->stats.rx_dropped++;
1330 dev->stats.rx_errors++;
1331 dev_kfree_skb_any(cb->skb);
1332 cb->skb = NULL;
1333 goto refill;
1334 }
1335 /* report errors */
1336 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1337 DMA_RX_OV |
1338 DMA_RX_NO |
1339 DMA_RX_LG |
1340 DMA_RX_RXER))) {
1341 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1342 (unsigned int)dma_flag);
1343 if (dma_flag & DMA_RX_CRC_ERROR)
1344 dev->stats.rx_crc_errors++;
1345 if (dma_flag & DMA_RX_OV)
1346 dev->stats.rx_over_errors++;
1347 if (dma_flag & DMA_RX_NO)
1348 dev->stats.rx_frame_errors++;
1349 if (dma_flag & DMA_RX_LG)
1350 dev->stats.rx_length_errors++;
1351 dev->stats.rx_dropped++;
1352 dev->stats.rx_errors++;
1353
1354 /* discard the packet and advance consumer index.*/
1355 dev_kfree_skb_any(cb->skb);
1356 cb->skb = NULL;
1357 goto refill;
1358 } /* error packet */
1359
1360 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1361 priv->desc_rxchk_en;
1362
1363 skb_put(skb, len);
1364 if (priv->desc_64b_en) {
1365 skb_pull(skb, 64);
1366 len -= 64;
1367 }
1368
1369 if (likely(chksum_ok))
1370 skb->ip_summed = CHECKSUM_UNNECESSARY;
1371
1372 /* remove hardware 2bytes added for IP alignment */
1373 skb_pull(skb, 2);
1374 len -= 2;
1375
1376 if (priv->crc_fwd_en) {
1377 skb_trim(skb, len - ETH_FCS_LEN);
1378 len -= ETH_FCS_LEN;
1379 }
1380
1381 /*Finish setting up the received SKB and send it to the kernel*/
1382 skb->protocol = eth_type_trans(skb, priv->dev);
1383 dev->stats.rx_packets++;
1384 dev->stats.rx_bytes += len;
1385 if (dma_flag & DMA_RX_MULT)
1386 dev->stats.multicast++;
1387
1388 /* Notify kernel */
1389 napi_gro_receive(&priv->napi, skb);
1390 cb->skb = NULL;
1391 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1392
1393 /* refill RX path on the current control block */
1394refill:
1395 err = bcmgenet_rx_refill(priv, cb);
1396 if (err)
1397 netif_err(priv, rx_err, dev, "Rx refill failed\n");
1398 }
1399
1400 return rxpktprocessed;
1401}
1402
1403/* Assign skb to RX DMA descriptor. */
1404static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1405{
1406 struct enet_cb *cb;
1407 int ret = 0;
1408 int i;
1409
1410 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1411
1412 /* loop here for each buffer needing assign */
1413 for (i = 0; i < priv->num_rx_bds; i++) {
1414 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1415 if (cb->skb)
1416 continue;
1417
1c1008c7
FF		 1418 ret = bcmgenet_rx_refill(priv, cb);
1419 if (ret)
1420 break;
1421
1422 }
1423
1424 return ret;
1425}
1426
1427static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1428{
1429 struct enet_cb *cb;
1430 int i;
1431
1432 for (i = 0; i < priv->num_rx_bds; i++) {
1433 cb = &priv->rx_cbs[i];
1434
1435 if (dma_unmap_addr(cb, dma_addr)) {
1436 dma_unmap_single(&priv->dev->dev,
1437 dma_unmap_addr(cb, dma_addr),
1438 priv->rx_buf_len, DMA_FROM_DEVICE);
1439 dma_unmap_addr_set(cb, dma_addr, 0);
1440 }
1441
1442 if (cb->skb)
1443 bcmgenet_free_cb(cb);
1444 }
1445}
1446
e29585b8
FF		 1447static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask,
1448 bool enable)
1449{
1450 u32 reg;
1451
1452 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1453 if (enable)
1454 reg |= mask;
1455 else
1456 reg &= ~mask;
1457 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1458
1459 /* UniMAC stops on a packet boundary, wait for a full-size packet
1460 * to be processed
1461 */
1462 if (enable == 0)
1463 usleep_range(1000, 2000);
1464}
1465
1c1008c7
FF		 1466static int reset_umac(struct bcmgenet_priv *priv)
1467{
1468 struct device *kdev = &priv->pdev->dev;
1469 unsigned int timeout = 0;
1470 u32 reg;
1471
1472 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1473 bcmgenet_rbuf_ctrl_set(priv, 0);
1474 udelay(10);
1475
1476 /* disable MAC while updating its registers */
1477 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1478
1479 /* issue soft reset, wait for it to complete */
1480 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1481 while (timeout++ < 1000) {
1482 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1483 if (!(reg & CMD_SW_RESET))
1484 return 0;
1485
1486 udelay(1);
1487 }
1488
1489 if (timeout == 1000) {
1490 dev_err(kdev,
1491 "timeout waiting for MAC to come out of resetn\n");
1492 return -ETIMEDOUT;
1493 }
1494
1495 return 0;
1496}
1497
909ff5ef
FF		 1498static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1499{
1500 /* Mask all interrupts.*/
1501 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1502 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1503 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1504 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1505 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1506 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1507}
1508
1c1008c7
FF		 1509static int init_umac(struct bcmgenet_priv *priv)
1510{
1511 struct device *kdev = &priv->pdev->dev;
1512 int ret;
1513 u32 reg, cpu_mask_clear;
1514
1515 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1516
1517 ret = reset_umac(priv);
1518 if (ret)
1519 return ret;
1520
1521 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1522 /* clear tx/rx counter */
1523 bcmgenet_umac_writel(priv,
1524 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, UMAC_MIB_CTRL);
1525 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1526
1527 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1528
1529 /* init rx registers, enable ip header optimization */
1530 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1531 reg |= RBUF_ALIGN_2B;
1532 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1533
1534 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1535 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1536
909ff5ef 1537 bcmgenet_intr_disable(priv);
1c1008c7
FF		 1538
1539 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1540
1541 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1542
1543 /* Monitor cable plug/unpluged event for internal PHY */
1544 if (phy_is_internal(priv->phydev))
1545 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1546 else if (priv->ext_phy)
1547 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1548 else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1549 reg = bcmgenet_bp_mc_get(priv);
1550 reg |= BIT(priv->hw_params->bp_in_en_shift);
1551
1552 /* bp_mask: back pressure mask */
1553 if (netif_is_multiqueue(priv->dev))
1554 reg |= priv->hw_params->bp_in_mask;
1555 else
1556 reg &= ~priv->hw_params->bp_in_mask;
1557 bcmgenet_bp_mc_set(priv, reg);
1558 }
1559
1560 /* Enable MDIO interrupts on GENET v3+ */
1561 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1562 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1563
1564 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear,
1565 INTRL2_CPU_MASK_CLEAR);
1566
1567 /* Enable rx/tx engine.*/
1568 dev_dbg(kdev, "done init umac\n");
1569
1570 return 0;
1571}
1572
1573/* Initialize all house-keeping variables for a TX ring, along
1574 * with corresponding hardware registers
1575 */
1576static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1577 unsigned int index, unsigned int size,
1578 unsigned int write_ptr, unsigned int end_ptr)
1579{
1580 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1581 u32 words_per_bd = WORDS_PER_BD(priv);
1582 u32 flow_period_val = 0;
1583 unsigned int first_bd;
1584
1585 spin_lock_init(&ring->lock);
1586 ring->index = index;
1587 if (index == DESC_INDEX) {
1588 ring->queue = 0;
1589 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1590 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1591 } else {
1592 ring->queue = index + 1;
1593 ring->int_enable = bcmgenet_tx_ring_int_enable;
1594 ring->int_disable = bcmgenet_tx_ring_int_disable;
1595 }
1596 ring->cbs = priv->tx_cbs + write_ptr;
1597 ring->size = size;
1598 ring->c_index = 0;
1599 ring->free_bds = size;
1600 ring->write_ptr = write_ptr;
1601 ring->cb_ptr = write_ptr;
1602 ring->end_ptr = end_ptr - 1;
1603 ring->prod_index = 0;
1604
1605 /* Set flow period for ring != 16 */
1606 if (index != DESC_INDEX)
1607 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1608
1609 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1610 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1611 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1612 /* Disable rate control for now */
1613 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1614 TDMA_FLOW_PERIOD);
1615 /* Unclassified traffic goes to ring 16 */
1616 bcmgenet_tdma_ring_writel(priv, index,
1617 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1618 DMA_RING_BUF_SIZE);
1619
1620 first_bd = write_ptr;
1621
1622 /* Set start and end address, read and write pointers */
1623 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1624 DMA_START_ADDR);
1625 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1626 TDMA_READ_PTR);
1627 bcmgenet_tdma_ring_writel(priv, index, first_bd,
1628 TDMA_WRITE_PTR);
1629 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1630 DMA_END_ADDR);
1631}
1632
1633/* Initialize a RDMA ring */
1634static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1635 unsigned int index, unsigned int size)
1636{
1637 u32 words_per_bd = WORDS_PER_BD(priv);
1638 int ret;
1639
1640 priv->num_rx_bds = TOTAL_DESC;
1641 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1642 priv->rx_bd_assign_ptr = priv->rx_bds;
1643 priv->rx_bd_assign_index = 0;
1644 priv->rx_c_index = 0;
1645 priv->rx_read_ptr = 0;
1646 priv->rx_cbs = kzalloc(priv->num_rx_bds * sizeof(struct enet_cb),
1647 GFP_KERNEL);
1648 if (!priv->rx_cbs)
1649 return -ENOMEM;
1650
1651 ret = bcmgenet_alloc_rx_buffers(priv);
1652 if (ret) {
1653 kfree(priv->rx_cbs);
1654 return ret;
1655 }
1656
1657 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1658 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1659 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1660 bcmgenet_rdma_ring_writel(priv, index,
1661 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1662 DMA_RING_BUF_SIZE);
1663 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1664 bcmgenet_rdma_ring_writel(priv, index,
1665 words_per_bd * size - 1, DMA_END_ADDR);
1666 bcmgenet_rdma_ring_writel(priv, index,
1667 (DMA_FC_THRESH_LO << DMA_XOFF_THRESHOLD_SHIFT) |
1668 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1669 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1670
1671 return ret;
1672}
1673
1674/* init multi xmit queues, only available for GENET2+
1675 * the queue is partitioned as follows:
1676 *
1677 * queue 0 - 3 is priority based, each one has 32 descriptors,
1678 * with queue 0 being the highest priority queue.
1679 *
1680 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1681 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1682 * descriptors.
1683 *
1684 * The transmit control block pool is then partitioned as following:
1685 * - tx_cbs[0...127] are for queue 16
1686 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1687 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1688 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1689 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1690 */
1691static void bcmgenet_init_multiq(struct net_device *dev)
1692{
1693 struct bcmgenet_priv *priv = netdev_priv(dev);
1694 unsigned int i, dma_enable;
1695 u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
1696
1697 if (!netif_is_multiqueue(dev)) {
1698 netdev_warn(dev, "called with non multi queue aware HW\n");
1699 return;
1700 }
1701
1702 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1703 dma_enable = dma_ctrl & DMA_EN;
1704 dma_ctrl &= ~DMA_EN;
1705 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1706
1707 /* Enable strict priority arbiter mode */
1708 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1709
1710 for (i = 0; i < priv->hw_params->tx_queues; i++) {
1711 /* first 64 tx_cbs are reserved for default tx queue
1712 * (ring 16)
1713 */
1714 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1715 i * priv->hw_params->bds_cnt,
1716 (i + 1) * priv->hw_params->bds_cnt);
1717
1718 /* Configure ring as decriptor ring and setup priority */
1719 ring_cfg |= 1 << i;
1720 dma_priority |= ((GENET_Q0_PRIORITY + i) <<
1721 (GENET_MAX_MQ_CNT + 1) * i);
1722 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1723 }
1724
1725 /* Enable rings */
1726 reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1727 reg |= ring_cfg;
1728 bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1729
1730 /* Use configured rings priority and set ring #16 priority */
1731 reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
1732 reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
1733 reg |= dma_priority;
1734 bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
1735
1736 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1737 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1738 reg |= dma_ctrl;
1739 if (dma_enable)
1740 reg |= DMA_EN;
1741 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1742}
1743
1744static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1745{
1746 int i;
1747
1748 /* disable DMA */
1749 bcmgenet_rdma_writel(priv, 0, DMA_CTRL);
1750 bcmgenet_tdma_writel(priv, 0, DMA_CTRL);
1751
1752 for (i = 0; i < priv->num_tx_bds; i++) {
1753 if (priv->tx_cbs[i].skb != NULL) {
1754 dev_kfree_skb(priv->tx_cbs[i].skb);
1755 priv->tx_cbs[i].skb = NULL;
1756 }
1757 }
1758
1759 bcmgenet_free_rx_buffers(priv);
1760 kfree(priv->rx_cbs);
1761 kfree(priv->tx_cbs);
1762}
1763
1764/* init_edma: Initialize DMA control register */
1765static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1766{
1767 int ret;
1768
1769 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1770
1771 /* by default, enable ring 16 (descriptor based) */
1772 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1773 if (ret) {
1774 netdev_err(priv->dev, "failed to initialize RX ring\n");
1775 return ret;
1776 }
1777
1778 /* init rDma */
1779 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1780
1781 /* Init tDma */
1782 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1783
1784 /* Initialize commont TX ring structures */
1785 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1786 priv->num_tx_bds = TOTAL_DESC;
1787 priv->tx_cbs = kzalloc(priv->num_tx_bds * sizeof(struct enet_cb),
1788 GFP_KERNEL);
1789 if (!priv->tx_cbs) {
1790 bcmgenet_fini_dma(priv);
1791 return -ENOMEM;
1792 }
1793
1794 /* initialize multi xmit queue */
1795 bcmgenet_init_multiq(priv->dev);
1796
1797 /* initialize special ring 16 */
1798 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1799 priv->hw_params->tx_queues * priv->hw_params->bds_cnt,
1800 TOTAL_DESC);
1801
1802 return 0;
1803}
1804
1805/* NAPI polling method*/
1806static int bcmgenet_poll(struct napi_struct *napi, int budget)
1807{
1808 struct bcmgenet_priv *priv = container_of(napi,
1809 struct bcmgenet_priv, napi);
1810 unsigned int work_done;
1811
1812 /* tx reclaim */
1813 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1814
1815 work_done = bcmgenet_desc_rx(priv, budget);
1816
1817 /* Advancing our consumer index*/
1818 priv->rx_c_index += work_done;
1819 priv->rx_c_index &= DMA_C_INDEX_MASK;
1820 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1821 priv->rx_c_index, RDMA_CONS_INDEX);
1822 if (work_done < budget) {
1823 napi_complete(napi);
1824 bcmgenet_intrl2_0_writel(priv,
1825 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_CLEAR);
1826 }
1827
1828 return work_done;
1829}
1830
1831/* Interrupt bottom half */
1832static void bcmgenet_irq_task(struct work_struct *work)
1833{
1834 struct bcmgenet_priv *priv = container_of(
1835 work, struct bcmgenet_priv, bcmgenet_irq_work);
1836
1837 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1838
8fdb0e0f
FF		 1839 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
1840 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
1841 netif_dbg(priv, wol, priv->dev,
1842 "magic packet detected, waking up\n");
1843 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
1844 }
1845
1c1008c7
FF		 1846 /* Link UP/DOWN event */
1847 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1848 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d
FF		 1849 phy_mac_interrupt(priv->phydev,
1850 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 1851 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
1852 }
1853}
1854
1855/* bcmgenet_isr1: interrupt handler for ring buffer. */
1856static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
1857{
1858 struct bcmgenet_priv *priv = dev_id;
1859 unsigned int index;
1860
1861 /* Save irq status for bottom-half processing. */
1862 priv->irq1_stat =
1863 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
1864 ~priv->int1_mask;
1865 /* clear inerrupts*/
1866 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
1867
1868 netif_dbg(priv, intr, priv->dev,
1869 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1870 /* Check the MBDONE interrupts.
1871 * packet is done, reclaim descriptors
1872 */
1873 if (priv->irq1_stat & 0x0000ffff) {
1874 index = 0;
1875 for (index = 0; index < 16; index++) {
1876 if (priv->irq1_stat & (1 << index))
1877 bcmgenet_tx_reclaim(priv->dev,
1878 &priv->tx_rings[index]);
1879 }
1880 }
1881 return IRQ_HANDLED;
1882}
1883
1884/* bcmgenet_isr0: Handle various interrupts. */
1885static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
1886{
1887 struct bcmgenet_priv *priv = dev_id;
1888
1889 /* Save irq status for bottom-half processing. */
1890 priv->irq0_stat =
1891 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1892 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1893 /* clear inerrupts*/
1894 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1895
1896 netif_dbg(priv, intr, priv->dev,
1897 "IRQ=0x%x\n", priv->irq0_stat);
1898
1899 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
1900 /* We use NAPI(software interrupt throttling, if
1901 * Rx Descriptor throttling is not used.
1902 * Disable interrupt, will be enabled in the poll method.
1903 */
1904 if (likely(napi_schedule_prep(&priv->napi))) {
1905 bcmgenet_intrl2_0_writel(priv,
1906 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_SET);
1907 __napi_schedule(&priv->napi);
1908 }
1909 }
1910 if (priv->irq0_stat &
1911 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
1912 /* Tx reclaim */
1913 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1914 }
1915 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
1916 UMAC_IRQ_PHY_DET_F |
1917 UMAC_IRQ_LINK_UP |
1918 UMAC_IRQ_LINK_DOWN |
1919 UMAC_IRQ_HFB_SM |
1920 UMAC_IRQ_HFB_MM |
1921 UMAC_IRQ_MPD_R)) {
1922 /* all other interested interrupts handled in bottom half */
1923 schedule_work(&priv->bcmgenet_irq_work);
1924 }
1925
1926 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1927 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1928 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1929 wake_up(&priv->wq);
1930 }
1931
1932 return IRQ_HANDLED;
1933}
1934
8562056f
FF		 1935static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
1936{
1937 struct bcmgenet_priv *priv = dev_id;
1938
1939 pm_wakeup_event(&priv->pdev->dev, 0);
1940
1941 return IRQ_HANDLED;
1942}
1943
1c1008c7
FF		 1944static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
1945{
1946 u32 reg;
1947
1948 reg = bcmgenet_rbuf_ctrl_get(priv);
1949 reg |= BIT(1);
1950 bcmgenet_rbuf_ctrl_set(priv, reg);
1951 udelay(10);
1952
1953 reg &= ~BIT(1);
1954 bcmgenet_rbuf_ctrl_set(priv, reg);
1955 udelay(10);
1956}
1957
1958static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
1959 unsigned char *addr)
1960{
1961 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1962 (addr[2] << 8) | addr[3], UMAC_MAC0);
1963 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1964}
1965
1966static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
1967{
1c1008c7 1968 /* From WOL-enabled suspend, switch to regular clock */
1c3c1e79 1969 clk_disable_unprepare(priv->clk_wol);
1c1008c7 1970
80d8e96d 1971 phy_init_hw(priv->phydev);
1c1008c7
FF		 1972 /* Speed settings must be restored */
1973 bcmgenet_mii_config(priv->dev);
1974
1975 return 0;
1976}
1977
1978/* Returns a reusable dma control register value */
1979static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
1980{
1981 u32 reg;
1982 u32 dma_ctrl;
1983
1984 /* disable DMA */
1985 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
1986 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1987 reg &= ~dma_ctrl;
1988 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1989
1990 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1991 reg &= ~dma_ctrl;
1992 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1993
1994 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
1995 udelay(10);
1996 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
1997
1998 return dma_ctrl;
1999}
2000
2001static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2002{
2003 u32 reg;
2004
2005 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2006 reg |= dma_ctrl;
2007 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2008
2009 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2010 reg |= dma_ctrl;
2011 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2012}
2013
909ff5ef
FF		 2014static void bcmgenet_netif_start(struct net_device *dev)
2015{
2016 struct bcmgenet_priv *priv = netdev_priv(dev);
2017
2018 /* Start the network engine */
2019 napi_enable(&priv->napi);
2020
2021 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2022
2023 if (phy_is_internal(priv->phydev))
2024 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2025
2026 netif_tx_start_all_queues(dev);
2027
2028 phy_start(priv->phydev);
2029}
2030
1c1008c7
FF		 2031static int bcmgenet_open(struct net_device *dev)
2032{
2033 struct bcmgenet_priv *priv = netdev_priv(dev);
2034 unsigned long dma_ctrl;
2035 u32 reg;
2036 int ret;
2037
2038 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2039
2040 /* Turn on the clock */
2041 if (!IS_ERR(priv->clk))
2042 clk_prepare_enable(priv->clk);
2043
2044 /* take MAC out of reset */
2045 bcmgenet_umac_reset(priv);
2046
2047 ret = init_umac(priv);
2048 if (ret)
2049 goto err_clk_disable;
2050
2051 /* disable ethernet MAC while updating its registers */
e29585b8 2052 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2053
909ff5ef
FF		 2054 /* Make sure we reflect the value of CRC_CMD_FWD */
2055 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2056 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2057
1c1008c7
FF		 2058 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2059
1c1008c7
FF		 2060 if (phy_is_internal(priv->phydev)) {
2061 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2062 reg |= EXT_ENERGY_DET_MASK;
2063 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2064 }
2065
2066 /* Disable RX/TX DMA and flush TX queues */
2067 dma_ctrl = bcmgenet_dma_disable(priv);
2068
2069 /* Reinitialize TDMA and RDMA and SW housekeeping */
2070 ret = bcmgenet_init_dma(priv);
2071 if (ret) {
2072 netdev_err(dev, "failed to initialize DMA\n");
2073 goto err_fini_dma;
2074 }
2075
2076 /* Always enable ring 16 - descriptor ring */
2077 bcmgenet_enable_dma(priv, dma_ctrl);
2078
2079 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2080 dev->name, priv);
2081 if (ret < 0) {
2082 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2083 goto err_fini_dma;
2084 }
2085
2086 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2087 dev->name, priv);
2088 if (ret < 0) {
2089 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2090 goto err_irq0;
2091 }
2092
909ff5ef 2093 bcmgenet_netif_start(dev);
1c1008c7
FF		 2094
2095 return 0;
2096
2097err_irq0:
2098 free_irq(priv->irq0, dev);
2099err_fini_dma:
2100 bcmgenet_fini_dma(priv);
2101err_clk_disable:
2102 if (!IS_ERR(priv->clk))
2103 clk_disable_unprepare(priv->clk);
2104 return ret;
2105}
2106
2107static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2108{
2109 int ret = 0;
2110 int timeout = 0;
2111 u32 reg;
2112
2113 /* Disable TDMA to stop add more frames in TX DMA */
2114 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2115 reg &= ~DMA_EN;
2116 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2117
2118 /* Check TDMA status register to confirm TDMA is disabled */
2119 while (timeout++ < DMA_TIMEOUT_VAL) {
2120 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2121 if (reg & DMA_DISABLED)
2122 break;
2123
2124 udelay(1);
2125 }
2126
2127 if (timeout == DMA_TIMEOUT_VAL) {
2128 netdev_warn(priv->dev,
2129 "Timed out while disabling TX DMA\n");
2130 ret = -ETIMEDOUT;
2131 }
2132
2133 /* Wait 10ms for packet drain in both tx and rx dma */
2134 usleep_range(10000, 20000);
2135
2136 /* Disable RDMA */
2137 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2138 reg &= ~DMA_EN;
2139 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2140
2141 timeout = 0;
2142 /* Check RDMA status register to confirm RDMA is disabled */
2143 while (timeout++ < DMA_TIMEOUT_VAL) {
2144 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2145 if (reg & DMA_DISABLED)
2146 break;
2147
2148 udelay(1);
2149 }
2150
2151 if (timeout == DMA_TIMEOUT_VAL) {
2152 netdev_warn(priv->dev,
2153 "Timed out while disabling RX DMA\n");
2154 ret = -ETIMEDOUT;
2155 }
2156
2157 return ret;
2158}
2159
909ff5ef
FF		 2160static void bcmgenet_netif_stop(struct net_device *dev)
2161{
2162 struct bcmgenet_priv *priv = netdev_priv(dev);
2163
2164 netif_tx_stop_all_queues(dev);
2165 napi_disable(&priv->napi);
2166 phy_stop(priv->phydev);
2167
2168 bcmgenet_intr_disable(priv);
2169
2170 /* Wait for pending work items to complete. Since interrupts are
2171 * disabled no new work will be scheduled.
2172 */
2173 cancel_work_sync(&priv->bcmgenet_irq_work);
2174}
2175
1c1008c7
FF		 2176static int bcmgenet_close(struct net_device *dev)
2177{
2178 struct bcmgenet_priv *priv = netdev_priv(dev);
2179 int ret;
1c1008c7
FF		 2180
2181 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2182
909ff5ef 2183 bcmgenet_netif_stop(dev);
1c1008c7
FF		 2184
2185 /* Disable MAC receive */
e29585b8 2186 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2187
1c1008c7
FF		 2188 ret = bcmgenet_dma_teardown(priv);
2189 if (ret)
2190 return ret;
2191
2192 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2193 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2194
1c1008c7
FF		 2195 /* tx reclaim */
2196 bcmgenet_tx_reclaim_all(dev);
2197 bcmgenet_fini_dma(priv);
2198
2199 free_irq(priv->irq0, priv);
2200 free_irq(priv->irq1, priv);
2201
1c1008c7
FF		 2202 if (phy_is_internal(priv->phydev))
2203 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2204
1c1008c7
FF		 2205 if (!IS_ERR(priv->clk))
2206 clk_disable_unprepare(priv->clk);
2207
2208 return 0;
2209}
2210
2211static void bcmgenet_timeout(struct net_device *dev)
2212{
2213 struct bcmgenet_priv *priv = netdev_priv(dev);
2214
2215 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2216
2217 dev->trans_start = jiffies;
2218
2219 dev->stats.tx_errors++;
2220
2221 netif_tx_wake_all_queues(dev);
2222}
2223
2224#define MAX_MC_COUNT 16
2225
2226static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2227 unsigned char *addr,
2228 int *i,
2229 int *mc)
2230{
2231 u32 reg;
2232
2233 bcmgenet_umac_writel(priv,
2234 addr[0] << 8 | addr[1], UMAC_MDF_ADDR + (*i * 4));
2235 bcmgenet_umac_writel(priv,
2236 addr[2] << 24 | addr[3] << 16 |
2237 addr[4] << 8 | addr[5],
2238 UMAC_MDF_ADDR + ((*i + 1) * 4));
2239 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2240 reg |= (1 << (MAX_MC_COUNT - *mc));
2241 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2242 *i += 2;
2243 (*mc)++;
2244}
2245
2246static void bcmgenet_set_rx_mode(struct net_device *dev)
2247{
2248 struct bcmgenet_priv *priv = netdev_priv(dev);
2249 struct netdev_hw_addr *ha;
2250 int i, mc;
2251 u32 reg;
2252
2253 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2254
2255 /* Promiscous mode */
2256 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2257 if (dev->flags & IFF_PROMISC) {
2258 reg |= CMD_PROMISC;
2259 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2260 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2261 return;
2262 } else {
2263 reg &= ~CMD_PROMISC;
2264 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2265 }
2266
2267 /* UniMac doesn't support ALLMULTI */
2268 if (dev->flags & IFF_ALLMULTI) {
2269 netdev_warn(dev, "ALLMULTI is not supported\n");
2270 return;
2271 }
2272
2273 /* update MDF filter */
2274 i = 0;
2275 mc = 0;
2276 /* Broadcast */
2277 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2278 /* my own address.*/
2279 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2280 /* Unicast list*/
2281 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2282 return;
2283
2284 if (!netdev_uc_empty(dev))
2285 netdev_for_each_uc_addr(ha, dev)
2286 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2287 /* Multicast */
2288 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2289 return;
2290
2291 netdev_for_each_mc_addr(ha, dev)
2292 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2293}
2294
2295/* Set the hardware MAC address. */
2296static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2297{
2298 struct sockaddr *addr = p;
2299
2300 /* Setting the MAC address at the hardware level is not possible
2301 * without disabling the UniMAC RX/TX enable bits.
2302 */
2303 if (netif_running(dev))
2304 return -EBUSY;
2305
2306 ether_addr_copy(dev->dev_addr, addr->sa_data);
2307
2308 return 0;
2309}
2310
1c1008c7
FF		 2311static const struct net_device_ops bcmgenet_netdev_ops = {
2312 .ndo_open = bcmgenet_open,
2313 .ndo_stop = bcmgenet_close,
2314 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2315 .ndo_tx_timeout = bcmgenet_timeout,
2316 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2317 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2318 .ndo_do_ioctl = bcmgenet_ioctl,
2319 .ndo_set_features = bcmgenet_set_features,
2320};
2321
2322/* Array of GENET hardware parameters/characteristics */
2323static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2324 [GENET_V1] = {
2325 .tx_queues = 0,
2326 .rx_queues = 0,
2327 .bds_cnt = 0,
2328 .bp_in_en_shift = 16,
2329 .bp_in_mask = 0xffff,
2330 .hfb_filter_cnt = 16,
2331 .qtag_mask = 0x1F,
2332 .hfb_offset = 0x1000,
2333 .rdma_offset = 0x2000,
2334 .tdma_offset = 0x3000,
2335 .words_per_bd = 2,
2336 },
2337 [GENET_V2] = {
2338 .tx_queues = 4,
2339 .rx_queues = 4,
2340 .bds_cnt = 32,
2341 .bp_in_en_shift = 16,
2342 .bp_in_mask = 0xffff,
2343 .hfb_filter_cnt = 16,
2344 .qtag_mask = 0x1F,
2345 .tbuf_offset = 0x0600,
2346 .hfb_offset = 0x1000,
2347 .hfb_reg_offset = 0x2000,
2348 .rdma_offset = 0x3000,
2349 .tdma_offset = 0x4000,
2350 .words_per_bd = 2,
2351 .flags = GENET_HAS_EXT,
2352 },
2353 [GENET_V3] = {
2354 .tx_queues = 4,
2355 .rx_queues = 4,
2356 .bds_cnt = 32,
2357 .bp_in_en_shift = 17,
2358 .bp_in_mask = 0x1ffff,
2359 .hfb_filter_cnt = 48,
2360 .qtag_mask = 0x3F,
2361 .tbuf_offset = 0x0600,
2362 .hfb_offset = 0x8000,
2363 .hfb_reg_offset = 0xfc00,
2364 .rdma_offset = 0x10000,
2365 .tdma_offset = 0x11000,
2366 .words_per_bd = 2,
2367 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2368 },
2369 [GENET_V4] = {
2370 .tx_queues = 4,
2371 .rx_queues = 4,
2372 .bds_cnt = 32,
2373 .bp_in_en_shift = 17,
2374 .bp_in_mask = 0x1ffff,
2375 .hfb_filter_cnt = 48,
2376 .qtag_mask = 0x3F,
2377 .tbuf_offset = 0x0600,
2378 .hfb_offset = 0x8000,
2379 .hfb_reg_offset = 0xfc00,
2380 .rdma_offset = 0x2000,
2381 .tdma_offset = 0x4000,
2382 .words_per_bd = 3,
2383 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2384 },
2385};
2386
2387/* Infer hardware parameters from the detected GENET version */
2388static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2389{
2390 struct bcmgenet_hw_params *params;
2391 u32 reg;
2392 u8 major;
2393
2394 if (GENET_IS_V4(priv)) {
2395 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2396 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2397 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2398 priv->version = GENET_V4;
2399 } else if (GENET_IS_V3(priv)) {
2400 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2401 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2402 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2403 priv->version = GENET_V3;
2404 } else if (GENET_IS_V2(priv)) {
2405 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2406 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2407 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2408 priv->version = GENET_V2;
2409 } else if (GENET_IS_V1(priv)) {
2410 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2411 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2412 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2413 priv->version = GENET_V1;
2414 }
2415
2416 /* enum genet_version starts at 1 */
2417 priv->hw_params = &bcmgenet_hw_params[priv->version];
2418 params = priv->hw_params;
2419
2420 /* Read GENET HW version */
2421 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2422 major = (reg >> 24 & 0x0f);
2423 if (major == 5)
2424 major = 4;
2425 else if (major == 0)
2426 major = 1;
2427 if (major != priv->version) {
2428 dev_err(&priv->pdev->dev,
2429 "GENET version mismatch, got: %d, configured for: %d\n",
2430 major, priv->version);
2431 }
2432
2433 /* Print the GENET core version */
2434 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2435 major, (reg >> 16) & 0x0f, reg & 0xffff);
2436
2437#ifdef CONFIG_PHYS_ADDR_T_64BIT
2438 if (!(params->flags & GENET_HAS_40BITS))
2439 pr_warn("GENET does not support 40-bits PA\n");
2440#endif
2441
2442 pr_debug("Configuration for version: %d\n"
2443 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2444 "BP << en: %2d, BP msk: 0x%05x\n"
2445 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2446 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2447 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2448 "Words/BD: %d\n",
2449 priv->version,
2450 params->tx_queues, params->rx_queues, params->bds_cnt,
2451 params->bp_in_en_shift, params->bp_in_mask,
2452 params->hfb_filter_cnt, params->qtag_mask,
2453 params->tbuf_offset, params->hfb_offset,
2454 params->hfb_reg_offset,
2455 params->rdma_offset, params->tdma_offset,
2456 params->words_per_bd);
2457}
2458
2459static const struct of_device_id bcmgenet_match[] = {
2460 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2461 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2462 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2463 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2464 { },
2465};
2466
2467static int bcmgenet_probe(struct platform_device *pdev)
2468{
2469 struct device_node *dn = pdev->dev.of_node;
2470 const struct of_device_id *of_id;
2471 struct bcmgenet_priv *priv;
2472 struct net_device *dev;
2473 const void *macaddr;
2474 struct resource *r;
2475 int err = -EIO;
2476
2477 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2478 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2479 if (!dev) {
2480 dev_err(&pdev->dev, "can't allocate net device\n");
2481 return -ENOMEM;
2482 }
2483
2484 of_id = of_match_node(bcmgenet_match, dn);
2485 if (!of_id)
2486 return -EINVAL;
2487
2488 priv = netdev_priv(dev);
2489 priv->irq0 = platform_get_irq(pdev, 0);
2490 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2491 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2492 if (!priv->irq0 || !priv->irq1) {
2493 dev_err(&pdev->dev, "can't find IRQs\n");
2494 err = -EINVAL;
2495 goto err;
2496 }
2497
2498 macaddr = of_get_mac_address(dn);
2499 if (!macaddr) {
2500 dev_err(&pdev->dev, "can't find MAC address\n");
2501 err = -EINVAL;
2502 goto err;
2503 }
2504
2505 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2506 priv->base = devm_ioremap_resource(&pdev->dev, r);
2507 if (IS_ERR(priv->base)) {
2508 err = PTR_ERR(priv->base);
1c1008c7
FF		 2509 goto err;
2510 }
2511
2512 SET_NETDEV_DEV(dev, &pdev->dev);
2513 dev_set_drvdata(&pdev->dev, dev);
2514 ether_addr_copy(dev->dev_addr, macaddr);
2515 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2516 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2517 dev->netdev_ops = &bcmgenet_netdev_ops;
2518 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2519
2520 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2521
2522 /* Set hardware features */
2523 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2524 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2525
8562056f
FF		 2526 /* Request the WOL interrupt and advertise suspend if available */
2527 priv->wol_irq_disabled = true;
2528 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2529 dev->name, priv);
2530 if (!err)
2531 device_set_wakeup_capable(&pdev->dev, 1);
2532
1c1008c7
FF		 2533 /* Set the needed headroom to account for any possible
2534 * features enabling/disabling at runtime
2535 */
2536 dev->needed_headroom += 64;
2537
2538 netdev_boot_setup_check(dev);
2539
2540 priv->dev = dev;
2541 priv->pdev = pdev;
2542 priv->version = (enum bcmgenet_version)of_id->data;
2543
2544 bcmgenet_set_hw_params(priv);
2545
1c1008c7
FF		 2546 /* Mii wait queue */
2547 init_waitqueue_head(&priv->wq);
2548 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2549 priv->rx_buf_len = RX_BUF_LENGTH;
2550 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2551
2552 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2553 if (IS_ERR(priv->clk))
2554 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2555
2556 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2557 if (IS_ERR(priv->clk_wol))
2558 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2559
2560 if (!IS_ERR(priv->clk))
2561 clk_prepare_enable(priv->clk);
2562
2563 err = reset_umac(priv);
2564 if (err)
2565 goto err_clk_disable;
2566
2567 err = bcmgenet_mii_init(dev);
2568 if (err)
2569 goto err_clk_disable;
2570
2571 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2572 * just the ring 16 descriptor based TX
2573 */
2574 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2575 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2576
219575eb
FF		 2577 /* libphy will determine the link state */
2578 netif_carrier_off(dev);
2579
1c1008c7
FF		 2580 /* Turn off the main clock, WOL clock is handled separately */
2581 if (!IS_ERR(priv->clk))
2582 clk_disable_unprepare(priv->clk);
2583
0f50ce96
FF		 2584 err = register_netdev(dev);
2585 if (err)
2586 goto err;
2587
1c1008c7
FF		 2588 return err;
2589
2590err_clk_disable:
2591 if (!IS_ERR(priv->clk))
2592 clk_disable_unprepare(priv->clk);
2593err:
2594 free_netdev(dev);
2595 return err;
2596}
2597
2598static int bcmgenet_remove(struct platform_device *pdev)
2599{
2600 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2601
2602 dev_set_drvdata(&pdev->dev, NULL);
2603 unregister_netdev(priv->dev);
2604 bcmgenet_mii_exit(priv->dev);
2605 free_netdev(priv->dev);
2606
2607 return 0;
2608}
2609
b6e978e5
FF		 2610#ifdef CONFIG_PM_SLEEP
2611static int bcmgenet_suspend(struct device *d)
2612{
2613 struct net_device *dev = dev_get_drvdata(d);
2614 struct bcmgenet_priv *priv = netdev_priv(dev);
2615 int ret;
2616
2617 if (!netif_running(dev))
2618 return 0;
2619
2620 bcmgenet_netif_stop(dev);
2621
2622 netif_device_detach(dev);
2623
2624 /* Disable MAC receive */
2625 umac_enable_set(priv, CMD_RX_EN, false);
2626
2627 ret = bcmgenet_dma_teardown(priv);
2628 if (ret)
2629 return ret;
2630
2631 /* Disable MAC transmit. TX DMA disabled have to done before this */
2632 umac_enable_set(priv, CMD_TX_EN, false);
2633
2634 /* tx reclaim */
2635 bcmgenet_tx_reclaim_all(dev);
2636 bcmgenet_fini_dma(priv);
2637
8c90db72
FF		 2638 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2639 if (device_may_wakeup(d) && priv->wolopts) {
2640 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2641 clk_prepare_enable(priv->clk_wol);
2642 }
2643
b6e978e5
FF		 2644 /* Turn off the clocks */
2645 clk_disable_unprepare(priv->clk);
2646
2647 return 0;
2648}
2649
2650static int bcmgenet_resume(struct device *d)
2651{
2652 struct net_device *dev = dev_get_drvdata(d);
2653 struct bcmgenet_priv *priv = netdev_priv(dev);
2654 unsigned long dma_ctrl;
2655 int ret;
2656 u32 reg;
2657
2658 if (!netif_running(dev))
2659 return 0;
2660
2661 /* Turn on the clock */
2662 ret = clk_prepare_enable(priv->clk);
2663 if (ret)
2664 return ret;
2665
2666 bcmgenet_umac_reset(priv);
2667
2668 ret = init_umac(priv);
2669 if (ret)
2670 goto out_clk_disable;
2671
8c90db72
FF		 2672 if (priv->wolopts)
2673 ret = bcmgenet_wol_resume(priv);
2674
2675 if (ret)
2676 goto out_clk_disable;
2677
b6e978e5
FF		 2678 /* disable ethernet MAC while updating its registers */
2679 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2680
2681 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2682
2683 if (phy_is_internal(priv->phydev)) {
2684 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2685 reg |= EXT_ENERGY_DET_MASK;
2686 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2687 }
2688
2689 /* Disable RX/TX DMA and flush TX queues */
2690 dma_ctrl = bcmgenet_dma_disable(priv);
2691
2692 /* Reinitialize TDMA and RDMA and SW housekeeping */
2693 ret = bcmgenet_init_dma(priv);
2694 if (ret) {
2695 netdev_err(dev, "failed to initialize DMA\n");
2696 goto out_clk_disable;
2697 }
2698
2699 /* Always enable ring 16 - descriptor ring */
2700 bcmgenet_enable_dma(priv, dma_ctrl);
2701
2702 netif_device_attach(dev);
2703
2704 bcmgenet_netif_start(dev);
2705
2706 return 0;
2707
2708out_clk_disable:
2709 clk_disable_unprepare(priv->clk);
2710 return ret;
2711}
2712#endif /* CONFIG_PM_SLEEP */
2713
2714static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2715
1c1008c7
FF		 2716static struct platform_driver bcmgenet_driver = {
2717 .probe = bcmgenet_probe,
2718 .remove = bcmgenet_remove,
2719 .driver = {
2720 .name = "bcmgenet",
2721 .owner = THIS_MODULE,
2722 .of_match_table = bcmgenet_match,
b6e978e5 2723 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 2724 },
2725};
2726module_platform_driver(bcmgenet_driver);
2727
2728MODULE_AUTHOR("Broadcom Corporation");
2729MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2730MODULE_ALIAS("platform:bcmgenet");
2731MODULE_LICENSE("GPL");
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