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lan78xx: Remove not defined MAC_CR_GMII_EN_ bit from MAC_CR.
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 106{
107 dmadesc_set_length_status(priv, d, val);
108 dmadesc_set_addr(priv, d, addr);
109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
0034de41
PG		 200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
1c1008c7
FF		 208};
209
210static const u8 bcmgenet_dma_regs_v3plus[] = {
211 [DMA_RING_CFG] = 0x00,
212 [DMA_CTRL] = 0x04,
213 [DMA_STATUS] = 0x08,
214 [DMA_SCB_BURST_SIZE] = 0x0C,
215 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 216 [DMA_PRIORITY_0] = 0x30,
217 [DMA_PRIORITY_1] = 0x34,
218 [DMA_PRIORITY_2] = 0x38,
0034de41
PG		 219 [DMA_INDEX2RING_0] = 0x70,
220 [DMA_INDEX2RING_1] = 0x74,
221 [DMA_INDEX2RING_2] = 0x78,
222 [DMA_INDEX2RING_3] = 0x7C,
223 [DMA_INDEX2RING_4] = 0x80,
224 [DMA_INDEX2RING_5] = 0x84,
225 [DMA_INDEX2RING_6] = 0x88,
226 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 227};
228
229static const u8 bcmgenet_dma_regs_v2[] = {
230 [DMA_RING_CFG] = 0x00,
231 [DMA_CTRL] = 0x04,
232 [DMA_STATUS] = 0x08,
233 [DMA_SCB_BURST_SIZE] = 0x0C,
234 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 235 [DMA_PRIORITY_0] = 0x34,
236 [DMA_PRIORITY_1] = 0x38,
237 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 238};
239
240static const u8 bcmgenet_dma_regs_v1[] = {
241 [DMA_CTRL] = 0x00,
242 [DMA_STATUS] = 0x04,
243 [DMA_SCB_BURST_SIZE] = 0x0C,
244 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 245 [DMA_PRIORITY_0] = 0x34,
246 [DMA_PRIORITY_1] = 0x38,
247 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 248};
249
250/* Set at runtime once bcmgenet version is known */
251static const u8 *bcmgenet_dma_regs;
252
253static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
254{
255 return netdev_priv(dev_get_drvdata(dev));
256}
257
258static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 259 enum dma_reg r)
1c1008c7
FF		 260{
261 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
262 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
263}
264
265static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
266 u32 val, enum dma_reg r)
267{
268 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
269 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
270}
271
272static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 273 enum dma_reg r)
1c1008c7
FF		 274{
275 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
276 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
277}
278
279static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
280 u32 val, enum dma_reg r)
281{
282 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
283 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
284}
285
286/* RDMA/TDMA ring registers and accessors
287 * we merge the common fields and just prefix with T/D the registers
288 * having different meaning depending on the direction
289 */
290enum dma_ring_reg {
291 TDMA_READ_PTR = 0,
292 RDMA_WRITE_PTR = TDMA_READ_PTR,
293 TDMA_READ_PTR_HI,
294 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
295 TDMA_CONS_INDEX,
296 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
297 TDMA_PROD_INDEX,
298 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
299 DMA_RING_BUF_SIZE,
300 DMA_START_ADDR,
301 DMA_START_ADDR_HI,
302 DMA_END_ADDR,
303 DMA_END_ADDR_HI,
304 DMA_MBUF_DONE_THRESH,
305 TDMA_FLOW_PERIOD,
306 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
307 TDMA_WRITE_PTR,
308 RDMA_READ_PTR = TDMA_WRITE_PTR,
309 TDMA_WRITE_PTR_HI,
310 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
311};
312
313/* GENET v4 supports 40-bits pointer addressing
314 * for obvious reasons the LO and HI word parts
315 * are contiguous, but this offsets the other
316 * registers.
317 */
318static const u8 genet_dma_ring_regs_v4[] = {
319 [TDMA_READ_PTR] = 0x00,
320 [TDMA_READ_PTR_HI] = 0x04,
321 [TDMA_CONS_INDEX] = 0x08,
322 [TDMA_PROD_INDEX] = 0x0C,
323 [DMA_RING_BUF_SIZE] = 0x10,
324 [DMA_START_ADDR] = 0x14,
325 [DMA_START_ADDR_HI] = 0x18,
326 [DMA_END_ADDR] = 0x1C,
327 [DMA_END_ADDR_HI] = 0x20,
328 [DMA_MBUF_DONE_THRESH] = 0x24,
329 [TDMA_FLOW_PERIOD] = 0x28,
330 [TDMA_WRITE_PTR] = 0x2C,
331 [TDMA_WRITE_PTR_HI] = 0x30,
332};
333
334static const u8 genet_dma_ring_regs_v123[] = {
335 [TDMA_READ_PTR] = 0x00,
336 [TDMA_CONS_INDEX] = 0x04,
337 [TDMA_PROD_INDEX] = 0x08,
338 [DMA_RING_BUF_SIZE] = 0x0C,
339 [DMA_START_ADDR] = 0x10,
340 [DMA_END_ADDR] = 0x14,
341 [DMA_MBUF_DONE_THRESH] = 0x18,
342 [TDMA_FLOW_PERIOD] = 0x1C,
343 [TDMA_WRITE_PTR] = 0x20,
344};
345
346/* Set at runtime once GENET version is known */
347static const u8 *genet_dma_ring_regs;
348
349static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 350 unsigned int ring,
351 enum dma_ring_reg r)
1c1008c7
FF		 352{
353 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
354 (DMA_RING_SIZE * ring) +
355 genet_dma_ring_regs[r]);
356}
357
358static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 359 unsigned int ring, u32 val,
360 enum dma_ring_reg r)
1c1008c7
FF		 361{
362 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
363 (DMA_RING_SIZE * ring) +
364 genet_dma_ring_regs[r]);
365}
366
367static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 368 unsigned int ring,
369 enum dma_ring_reg r)
1c1008c7
FF		 370{
371 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
372 (DMA_RING_SIZE * ring) +
373 genet_dma_ring_regs[r]);
374}
375
376static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 377 unsigned int ring, u32 val,
378 enum dma_ring_reg r)
1c1008c7
FF		 379{
380 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
381 (DMA_RING_SIZE * ring) +
382 genet_dma_ring_regs[r]);
383}
384
385static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 386 struct ethtool_cmd *cmd)
1c1008c7
FF		 387{
388 struct bcmgenet_priv *priv = netdev_priv(dev);
389
390 if (!netif_running(dev))
391 return -EINVAL;
392
393 if (!priv->phydev)
394 return -ENODEV;
395
396 return phy_ethtool_gset(priv->phydev, cmd);
397}
398
399static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 400 struct ethtool_cmd *cmd)
1c1008c7
FF		 401{
402 struct bcmgenet_priv *priv = netdev_priv(dev);
403
404 if (!netif_running(dev))
405 return -EINVAL;
406
407 if (!priv->phydev)
408 return -ENODEV;
409
410 return phy_ethtool_sset(priv->phydev, cmd);
411}
412
413static int bcmgenet_set_rx_csum(struct net_device *dev,
414 netdev_features_t wanted)
415{
416 struct bcmgenet_priv *priv = netdev_priv(dev);
417 u32 rbuf_chk_ctrl;
418 bool rx_csum_en;
419
420 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
421
422 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
423
424 /* enable rx checksumming */
425 if (rx_csum_en)
426 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
427 else
428 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
429 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 430
431 /* If UniMAC forwards CRC, we need to skip over it to get
432 * a valid CHK bit to be set in the per-packet status word
433 */
434 if (rx_csum_en && priv->crc_fwd_en)
435 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
436 else
437 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
438
1c1008c7
FF		 439 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
440
441 return 0;
442}
443
444static int bcmgenet_set_tx_csum(struct net_device *dev,
445 netdev_features_t wanted)
446{
447 struct bcmgenet_priv *priv = netdev_priv(dev);
448 bool desc_64b_en;
449 u32 tbuf_ctrl, rbuf_ctrl;
450
451 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
452 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
453
454 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
455
456 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
457 if (desc_64b_en) {
458 tbuf_ctrl |= RBUF_64B_EN;
459 rbuf_ctrl |= RBUF_64B_EN;
460 } else {
461 tbuf_ctrl &= ~RBUF_64B_EN;
462 rbuf_ctrl &= ~RBUF_64B_EN;
463 }
464 priv->desc_64b_en = desc_64b_en;
465
466 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
467 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
468
469 return 0;
470}
471
472static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 473 netdev_features_t features)
1c1008c7
FF		 474{
475 netdev_features_t changed = features ^ dev->features;
476 netdev_features_t wanted = dev->wanted_features;
477 int ret = 0;
478
479 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
480 ret = bcmgenet_set_tx_csum(dev, wanted);
481 if (changed & (NETIF_F_RXCSUM))
482 ret = bcmgenet_set_rx_csum(dev, wanted);
483
484 return ret;
485}
486
487static u32 bcmgenet_get_msglevel(struct net_device *dev)
488{
489 struct bcmgenet_priv *priv = netdev_priv(dev);
490
491 return priv->msg_enable;
492}
493
494static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
495{
496 struct bcmgenet_priv *priv = netdev_priv(dev);
497
498 priv->msg_enable = level;
499}
500
501/* standard ethtool support functions. */
502enum bcmgenet_stat_type {
503 BCMGENET_STAT_NETDEV = -1,
504 BCMGENET_STAT_MIB_RX,
505 BCMGENET_STAT_MIB_TX,
506 BCMGENET_STAT_RUNT,
507 BCMGENET_STAT_MISC,
f62ba9c1 508 BCMGENET_STAT_SOFT,
1c1008c7
FF		 509};
510
511struct bcmgenet_stats {
512 char stat_string[ETH_GSTRING_LEN];
513 int stat_sizeof;
514 int stat_offset;
515 enum bcmgenet_stat_type type;
516 /* reg offset from UMAC base for misc counters */
517 u16 reg_offset;
518};
519
520#define STAT_NETDEV(m) { \
521 .stat_string = __stringify(m), \
522 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
523 .stat_offset = offsetof(struct net_device_stats, m), \
524 .type = BCMGENET_STAT_NETDEV, \
525}
526
527#define STAT_GENET_MIB(str, m, _type) { \
528 .stat_string = str, \
529 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
530 .stat_offset = offsetof(struct bcmgenet_priv, m), \
531 .type = _type, \
532}
533
534#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
535#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
536#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 537#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 538
539#define STAT_GENET_MISC(str, m, offset) { \
540 .stat_string = str, \
541 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
542 .stat_offset = offsetof(struct bcmgenet_priv, m), \
543 .type = BCMGENET_STAT_MISC, \
544 .reg_offset = offset, \
545}
546
547
548/* There is a 0xC gap between the end of RX and beginning of TX stats and then
549 * between the end of TX stats and the beginning of the RX RUNT
550 */
551#define BCMGENET_STAT_OFFSET 0xc
552
553/* Hardware counters must be kept in sync because the order/offset
554 * is important here (order in structure declaration = order in hardware)
555 */
556static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
557 /* general stats */
558 STAT_NETDEV(rx_packets),
559 STAT_NETDEV(tx_packets),
560 STAT_NETDEV(rx_bytes),
561 STAT_NETDEV(tx_bytes),
562 STAT_NETDEV(rx_errors),
563 STAT_NETDEV(tx_errors),
564 STAT_NETDEV(rx_dropped),
565 STAT_NETDEV(tx_dropped),
566 STAT_NETDEV(multicast),
567 /* UniMAC RSV counters */
568 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
569 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
570 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
571 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
572 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
573 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
574 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
575 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
576 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
577 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
578 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
579 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
580 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
581 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
582 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
583 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
584 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
585 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
586 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
587 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
588 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
589 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
590 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
591 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
592 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
593 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
594 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
595 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
596 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
597 /* UniMAC TSV counters */
598 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
599 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
600 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
601 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
602 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
603 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
604 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
605 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
606 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
607 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
608 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
609 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
610 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
611 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
612 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
613 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
614 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
615 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
616 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
617 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
618 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
619 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
620 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
621 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
622 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
623 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
624 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
625 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
626 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
627 /* UniMAC RUNT counters */
628 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
629 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
630 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
631 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
632 /* Misc UniMAC counters */
633 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
634 UMAC_RBUF_OVFL_CNT),
635 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
636 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 637 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
638 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
639 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 640};
641
642#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
643
644static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 645 struct ethtool_drvinfo *info)
1c1008c7
FF		 646{
647 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
648 strlcpy(info->version, "v2.0", sizeof(info->version));
649 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 650}
651
652static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
653{
654 switch (string_set) {
655 case ETH_SS_STATS:
656 return BCMGENET_STATS_LEN;
657 default:
658 return -EOPNOTSUPP;
659 }
660}
661
c91b7f66
FF		 662static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
663 u8 *data)
1c1008c7
FF		 664{
665 int i;
666
667 switch (stringset) {
668 case ETH_SS_STATS:
669 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
670 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 671 bcmgenet_gstrings_stats[i].stat_string,
672 ETH_GSTRING_LEN);
1c1008c7
FF		 673 }
674 break;
675 }
676}
677
678static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
679{
680 int i, j = 0;
681
682 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
683 const struct bcmgenet_stats *s;
684 u8 offset = 0;
685 u32 val = 0;
686 char *p;
687
688 s = &bcmgenet_gstrings_stats[i];
689 switch (s->type) {
690 case BCMGENET_STAT_NETDEV:
f62ba9c1 691 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 692 continue;
693 case BCMGENET_STAT_MIB_RX:
694 case BCMGENET_STAT_MIB_TX:
695 case BCMGENET_STAT_RUNT:
696 if (s->type != BCMGENET_STAT_MIB_RX)
697 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 698 val = bcmgenet_umac_readl(priv,
699 UMAC_MIB_START + j + offset);
1c1008c7
FF		 700 break;
701 case BCMGENET_STAT_MISC:
702 val = bcmgenet_umac_readl(priv, s->reg_offset);
703 /* clear if overflowed */
704 if (val == ~0)
705 bcmgenet_umac_writel(priv, 0, s->reg_offset);
706 break;
707 }
708
709 j += s->stat_sizeof;
710 p = (char *)priv + s->stat_offset;
711 *(u32 *)p = val;
712 }
713}
714
715static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 716 struct ethtool_stats *stats,
717 u64 *data)
1c1008c7
FF		 718{
719 struct bcmgenet_priv *priv = netdev_priv(dev);
720 int i;
721
722 if (netif_running(dev))
723 bcmgenet_update_mib_counters(priv);
724
725 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
726 const struct bcmgenet_stats *s;
727 char *p;
728
729 s = &bcmgenet_gstrings_stats[i];
730 if (s->type == BCMGENET_STAT_NETDEV)
731 p = (char *)&dev->stats;
732 else
733 p = (char *)priv;
734 p += s->stat_offset;
735 data[i] = *(u32 *)p;
736 }
737}
738
6ef398ea
FF		 739static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
740{
741 struct bcmgenet_priv *priv = netdev_priv(dev);
742 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
743 u32 reg;
744
745 if (enable && !priv->clk_eee_enabled) {
746 clk_prepare_enable(priv->clk_eee);
747 priv->clk_eee_enabled = true;
748 }
749
750 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
751 if (enable)
752 reg |= EEE_EN;
753 else
754 reg &= ~EEE_EN;
755 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
756
757 /* Enable EEE and switch to a 27Mhz clock automatically */
758 reg = __raw_readl(priv->base + off);
759 if (enable)
760 reg |= TBUF_EEE_EN | TBUF_PM_EN;
761 else
762 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
763 __raw_writel(reg, priv->base + off);
764
765 /* Do the same for thing for RBUF */
766 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
767 if (enable)
768 reg |= RBUF_EEE_EN | RBUF_PM_EN;
769 else
770 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
771 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
772
773 if (!enable && priv->clk_eee_enabled) {
774 clk_disable_unprepare(priv->clk_eee);
775 priv->clk_eee_enabled = false;
776 }
777
778 priv->eee.eee_enabled = enable;
779 priv->eee.eee_active = enable;
780}
781
782static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
783{
784 struct bcmgenet_priv *priv = netdev_priv(dev);
785 struct ethtool_eee *p = &priv->eee;
786
787 if (GENET_IS_V1(priv))
788 return -EOPNOTSUPP;
789
790 e->eee_enabled = p->eee_enabled;
791 e->eee_active = p->eee_active;
792 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
793
794 return phy_ethtool_get_eee(priv->phydev, e);
795}
796
797static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
798{
799 struct bcmgenet_priv *priv = netdev_priv(dev);
800 struct ethtool_eee *p = &priv->eee;
801 int ret = 0;
802
803 if (GENET_IS_V1(priv))
804 return -EOPNOTSUPP;
805
806 p->eee_enabled = e->eee_enabled;
807
808 if (!p->eee_enabled) {
809 bcmgenet_eee_enable_set(dev, false);
810 } else {
811 ret = phy_init_eee(priv->phydev, 0);
812 if (ret) {
813 netif_err(priv, hw, dev, "EEE initialization failed\n");
814 return ret;
815 }
816
817 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
818 bcmgenet_eee_enable_set(dev, true);
819 }
820
821 return phy_ethtool_set_eee(priv->phydev, e);
822}
823
6b0c5406
FF		 824static int bcmgenet_nway_reset(struct net_device *dev)
825{
826 struct bcmgenet_priv *priv = netdev_priv(dev);
827
828 return genphy_restart_aneg(priv->phydev);
829}
830
1c1008c7
FF		 831/* standard ethtool support functions. */
832static struct ethtool_ops bcmgenet_ethtool_ops = {
833 .get_strings = bcmgenet_get_strings,
834 .get_sset_count = bcmgenet_get_sset_count,
835 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
836 .get_settings = bcmgenet_get_settings,
837 .set_settings = bcmgenet_set_settings,
838 .get_drvinfo = bcmgenet_get_drvinfo,
839 .get_link = ethtool_op_get_link,
840 .get_msglevel = bcmgenet_get_msglevel,
841 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 842 .get_wol = bcmgenet_get_wol,
843 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 844 .get_eee = bcmgenet_get_eee,
845 .set_eee = bcmgenet_set_eee,
6b0c5406 846 .nway_reset = bcmgenet_nway_reset,
1c1008c7
FF		 847};
848
849/* Power down the unimac, based on mode. */
ca8cf341 850static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 851 enum bcmgenet_power_mode mode)
852{
ca8cf341 853 int ret = 0;
1c1008c7
FF		 854 u32 reg;
855
856 switch (mode) {
857 case GENET_POWER_CABLE_SENSE:
80d8e96d 858 phy_detach(priv->phydev);
1c1008c7
FF		 859 break;
860
c3ae64ae 861 case GENET_POWER_WOL_MAGIC:
ca8cf341 862 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 863 break;
864
1c1008c7
FF		 865 case GENET_POWER_PASSIVE:
866 /* Power down LED */
1c1008c7
FF		 867 if (priv->hw_params->flags & GENET_HAS_EXT) {
868 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
869 reg |= (EXT_PWR_DOWN_PHY |
870 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
871 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 872
873 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 874 }
875 break;
876 default:
877 break;
878 }
ca8cf341
FF		 879
880 return 0;
1c1008c7
FF		 881}
882
883static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 884 enum bcmgenet_power_mode mode)
1c1008c7
FF		 885{
886 u32 reg;
887
888 if (!(priv->hw_params->flags & GENET_HAS_EXT))
889 return;
890
891 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
892
893 switch (mode) {
894 case GENET_POWER_PASSIVE:
895 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
896 EXT_PWR_DOWN_BIAS);
897 /* fallthrough */
898 case GENET_POWER_CABLE_SENSE:
899 /* enable APD */
900 reg |= EXT_PWR_DN_EN_LD;
901 break;
c3ae64ae
FF		 902 case GENET_POWER_WOL_MAGIC:
903 bcmgenet_wol_power_up_cfg(priv, mode);
904 return;
1c1008c7
FF		 905 default:
906 break;
907 }
908
909 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
bd4060a6
FF		 910 if (mode == GENET_POWER_PASSIVE)
911 bcmgenet_phy_power_set(priv->dev, true);
1c1008c7
FF		 912}
913
914/* ioctl handle special commands that are not present in ethtool. */
915static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
916{
917 struct bcmgenet_priv *priv = netdev_priv(dev);
918 int val = 0;
919
920 if (!netif_running(dev))
921 return -EINVAL;
922
923 switch (cmd) {
924 case SIOCGMIIPHY:
925 case SIOCGMIIREG:
926 case SIOCSMIIREG:
927 if (!priv->phydev)
928 val = -ENODEV;
929 else
930 val = phy_mii_ioctl(priv->phydev, rq, cmd);
931 break;
932
933 default:
934 val = -EINVAL;
935 break;
936 }
937
938 return val;
939}
940
941static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
942 struct bcmgenet_tx_ring *ring)
943{
944 struct enet_cb *tx_cb_ptr;
945
946 tx_cb_ptr = ring->cbs;
947 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 948
1c1008c7
FF		 949 /* Advancing local write pointer */
950 if (ring->write_ptr == ring->end_ptr)
951 ring->write_ptr = ring->cb_ptr;
952 else
953 ring->write_ptr++;
954
955 return tx_cb_ptr;
956}
957
958/* Simple helper to free a control block's resources */
959static void bcmgenet_free_cb(struct enet_cb *cb)
960{
961 dev_kfree_skb_any(cb->skb);
962 cb->skb = NULL;
963 dma_unmap_addr_set(cb, dma_addr, 0);
964}
965
4055eaef
PG		 966static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
967{
ee7d8c20 968 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 969 INTRL2_CPU_MASK_SET);
970}
971
972static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
973{
ee7d8c20 974 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 975 INTRL2_CPU_MASK_CLEAR);
976}
977
978static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
979{
980 bcmgenet_intrl2_1_writel(ring->priv,
981 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
982 INTRL2_CPU_MASK_SET);
983}
984
985static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
986{
987 bcmgenet_intrl2_1_writel(ring->priv,
988 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
989 INTRL2_CPU_MASK_CLEAR);
990}
991
9dbac28f 992static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 993{
ee7d8c20 994 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 995 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 996}
997
9dbac28f 998static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 999{
ee7d8c20 1000 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1001 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1002}
1003
9dbac28f 1004static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1005{
9dbac28f 1006 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1007 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1008}
1009
9dbac28f 1010static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1011{
9dbac28f 1012 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1013 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1014}
1015
1016/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1017static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1018 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1019{
1020 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 1021 struct enet_cb *tx_cb_ptr;
b2cde2cc 1022 struct netdev_queue *txq;
4092e6ac 1023 unsigned int pkts_compl = 0;
1c1008c7 1024 unsigned int c_index;
66d06757
PG		 1025 unsigned int txbds_ready;
1026 unsigned int txbds_processed = 0;
1c1008c7 1027
7fc527f9 1028 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 1029 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 1030 c_index &= DMA_C_INDEX_MASK;
1c1008c7 1031
66d06757
PG		 1032 if (likely(c_index >= ring->c_index))
1033 txbds_ready = c_index - ring->c_index;
1c1008c7 1034 else
66d06757 1035 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 1036
1037 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1038 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1039 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1040
1041 /* Reclaim transmitted buffers */
66d06757
PG		 1042 while (txbds_processed < txbds_ready) {
1043 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1044 if (tx_cb_ptr->skb) {
4092e6ac 1045 pkts_compl++;
66d06757 1046 dev->stats.tx_packets++;
1c1008c7
FF		 1047 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1048 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1049 dma_unmap_addr(tx_cb_ptr, dma_addr),
1050 tx_cb_ptr->skb->len,
1051 DMA_TO_DEVICE);
1c1008c7
FF		 1052 bcmgenet_free_cb(tx_cb_ptr);
1053 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1054 dev->stats.tx_bytes +=
1055 dma_unmap_len(tx_cb_ptr, dma_len);
1056 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1057 dma_unmap_addr(tx_cb_ptr, dma_addr),
1058 dma_unmap_len(tx_cb_ptr, dma_len),
1059 DMA_TO_DEVICE);
1c1008c7
FF		 1060 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1061 }
1c1008c7 1062
66d06757
PG		 1063 txbds_processed++;
1064 if (likely(ring->clean_ptr < ring->end_ptr))
1065 ring->clean_ptr++;
1066 else
1067 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1068 }
1069
66d06757
PG		 1070 ring->free_bds += txbds_processed;
1071 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1072
4092e6ac 1073 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
66d06757 1074 txq = netdev_get_tx_queue(dev, ring->queue);
4092e6ac
JS		 1075 if (netif_tx_queue_stopped(txq))
1076 netif_tx_wake_queue(txq);
1077 }
1c1008c7 1078
4092e6ac 1079 return pkts_compl;
1c1008c7
FF		 1080}
1081
4092e6ac 1082static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1083 struct bcmgenet_tx_ring *ring)
1c1008c7 1084{
4092e6ac 1085 unsigned int released;
1c1008c7
FF		 1086 unsigned long flags;
1087
1088 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1089 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1090 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1091
1092 return released;
1093}
1094
1095static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1096{
1097 struct bcmgenet_tx_ring *ring =
1098 container_of(napi, struct bcmgenet_tx_ring, napi);
1099 unsigned int work_done = 0;
1100
1101 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1102
1103 if (work_done == 0) {
1104 napi_complete(napi);
9dbac28f 1105 ring->int_enable(ring);
4092e6ac
JS		 1106
1107 return 0;
1108 }
1109
1110 return budget;
1c1008c7
FF		 1111}
1112
1113static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1114{
1115 struct bcmgenet_priv *priv = netdev_priv(dev);
1116 int i;
1117
1118 if (netif_is_multiqueue(dev)) {
1119 for (i = 0; i < priv->hw_params->tx_queues; i++)
1120 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1121 }
1122
1123 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1124}
1125
1126/* Transmits a single SKB (either head of a fragment or a single SKB)
1127 * caller must hold priv->lock
1128 */
1129static int bcmgenet_xmit_single(struct net_device *dev,
1130 struct sk_buff *skb,
1131 u16 dma_desc_flags,
1132 struct bcmgenet_tx_ring *ring)
1133{
1134 struct bcmgenet_priv *priv = netdev_priv(dev);
1135 struct device *kdev = &priv->pdev->dev;
1136 struct enet_cb *tx_cb_ptr;
1137 unsigned int skb_len;
1138 dma_addr_t mapping;
1139 u32 length_status;
1140 int ret;
1141
1142 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1143
1144 if (unlikely(!tx_cb_ptr))
1145 BUG();
1146
1147 tx_cb_ptr->skb = skb;
1148
1149 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1150
1151 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1152 ret = dma_mapping_error(kdev, mapping);
1153 if (ret) {
44c8bc3c 1154 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1155 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1156 dev_kfree_skb(skb);
1157 return ret;
1158 }
1159
1160 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1161 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1162 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1163 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1164 DMA_TX_APPEND_CRC;
1165
1166 if (skb->ip_summed == CHECKSUM_PARTIAL)
1167 length_status |= DMA_TX_DO_CSUM;
1168
1169 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1170
1c1008c7
FF		 1171 return 0;
1172}
1173
7fc527f9 1174/* Transmit a SKB fragment */
1c1008c7 1175static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1176 skb_frag_t *frag,
1177 u16 dma_desc_flags,
1178 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1179{
1180 struct bcmgenet_priv *priv = netdev_priv(dev);
1181 struct device *kdev = &priv->pdev->dev;
1182 struct enet_cb *tx_cb_ptr;
1183 dma_addr_t mapping;
1184 int ret;
1185
1186 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1187
1188 if (unlikely(!tx_cb_ptr))
1189 BUG();
1190 tx_cb_ptr->skb = NULL;
1191
1192 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1193 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1194 ret = dma_mapping_error(kdev, mapping);
1195 if (ret) {
44c8bc3c 1196 priv->mib.tx_dma_failed++;
1c1008c7 1197 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1198 __func__);
1c1008c7
FF		 1199 return ret;
1200 }
1201
1202 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1203 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1204
1205 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1206 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1207 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7 1208
1c1008c7
FF		 1209 return 0;
1210}
1211
1212/* Reallocate the SKB to put enough headroom in front of it and insert
1213 * the transmit checksum offsets in the descriptors
1214 */
bc23333b
PG		 1215static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1216 struct sk_buff *skb)
1c1008c7
FF		 1217{
1218 struct status_64 *status = NULL;
1219 struct sk_buff *new_skb;
1220 u16 offset;
1221 u8 ip_proto;
1222 u16 ip_ver;
1223 u32 tx_csum_info;
1224
1225 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1226 /* If 64 byte status block enabled, must make sure skb has
1227 * enough headroom for us to insert 64B status block.
1228 */
1229 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1230 dev_kfree_skb(skb);
1231 if (!new_skb) {
1c1008c7 1232 dev->stats.tx_dropped++;
bc23333b 1233 return NULL;
1c1008c7
FF		 1234 }
1235 skb = new_skb;
1236 }
1237
1238 skb_push(skb, sizeof(*status));
1239 status = (struct status_64 *)skb->data;
1240
1241 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1242 ip_ver = htons(skb->protocol);
1243 switch (ip_ver) {
1244 case ETH_P_IP:
1245 ip_proto = ip_hdr(skb)->protocol;
1246 break;
1247 case ETH_P_IPV6:
1248 ip_proto = ipv6_hdr(skb)->nexthdr;
1249 break;
1250 default:
bc23333b 1251 return skb;
1c1008c7
FF		 1252 }
1253
1254 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1255 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1256 (offset + skb->csum_offset);
1257
1258 /* Set the length valid bit for TCP and UDP and just set
1259 * the special UDP flag for IPv4, else just set to 0.
1260 */
1261 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1262 tx_csum_info |= STATUS_TX_CSUM_LV;
1263 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1264 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1265 } else {
1c1008c7 1266 tx_csum_info = 0;
8900ea57 1267 }
1c1008c7
FF		 1268
1269 status->tx_csum_info = tx_csum_info;
1270 }
1271
bc23333b 1272 return skb;
1c1008c7
FF		 1273}
1274
1275static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1276{
1277 struct bcmgenet_priv *priv = netdev_priv(dev);
1278 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1279 struct netdev_queue *txq;
1c1008c7
FF		 1280 unsigned long flags = 0;
1281 int nr_frags, index;
1282 u16 dma_desc_flags;
1283 int ret;
1284 int i;
1285
1286 index = skb_get_queue_mapping(skb);
1287 /* Mapping strategy:
1288 * queue_mapping = 0, unclassified, packet xmited through ring16
1289 * queue_mapping = 1, goes to ring 0. (highest priority queue
1290 * queue_mapping = 2, goes to ring 1.
1291 * queue_mapping = 3, goes to ring 2.
1292 * queue_mapping = 4, goes to ring 3.
1293 */
1294 if (index == 0)
1295 index = DESC_INDEX;
1296 else
1297 index -= 1;
1298
1c1008c7
FF		 1299 nr_frags = skb_shinfo(skb)->nr_frags;
1300 ring = &priv->tx_rings[index];
b2cde2cc 1301 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1302
1303 spin_lock_irqsave(&ring->lock, flags);
1304 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1305 netif_tx_stop_queue(txq);
1c1008c7 1306 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1307 __func__, index, ring->queue);
1c1008c7
FF		 1308 ret = NETDEV_TX_BUSY;
1309 goto out;
1310 }
1311
474ea9ca
FF		 1312 if (skb_padto(skb, ETH_ZLEN)) {
1313 ret = NETDEV_TX_OK;
1314 goto out;
1315 }
1316
1c1008c7
FF		 1317 /* set the SKB transmit checksum */
1318 if (priv->desc_64b_en) {
bc23333b
PG		 1319 skb = bcmgenet_put_tx_csum(dev, skb);
1320 if (!skb) {
1c1008c7
FF		 1321 ret = NETDEV_TX_OK;
1322 goto out;
1323 }
1324 }
1325
1326 dma_desc_flags = DMA_SOP;
1327 if (nr_frags == 0)
1328 dma_desc_flags |= DMA_EOP;
1329
1330 /* Transmit single SKB or head of fragment list */
1331 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1332 if (ret) {
1333 ret = NETDEV_TX_OK;
1334 goto out;
1335 }
1336
1337 /* xmit fragment */
1338 for (i = 0; i < nr_frags; i++) {
1339 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1340 &skb_shinfo(skb)->frags[i],
1341 (i == nr_frags - 1) ? DMA_EOP : 0,
1342 ring);
1c1008c7
FF		 1343 if (ret) {
1344 ret = NETDEV_TX_OK;
1345 goto out;
1346 }
1347 }
1348
d03825fb
FF		 1349 skb_tx_timestamp(skb);
1350
ae67bf01
FF		 1351 /* Decrement total BD count and advance our write pointer */
1352 ring->free_bds -= nr_frags + 1;
1353 ring->prod_index += nr_frags + 1;
1354 ring->prod_index &= DMA_P_INDEX_MASK;
1355
4092e6ac 1356 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1357 netif_tx_stop_queue(txq);
1c1008c7 1358
ddd0ca5d
FF		 1359 if (!skb->xmit_more || netif_xmit_stopped(txq))
1360 /* Packets are ready, update producer index */
1361 bcmgenet_tdma_ring_writel(priv, ring->index,
1362 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1363out:
1364 spin_unlock_irqrestore(&ring->lock, flags);
1365
1366 return ret;
1367}
1368
d6707bec
PG		 1369static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1370 struct enet_cb *cb)
1c1008c7
FF		 1371{
1372 struct device *kdev = &priv->pdev->dev;
1373 struct sk_buff *skb;
d6707bec 1374 struct sk_buff *rx_skb;
1c1008c7 1375 dma_addr_t mapping;
1c1008c7 1376
d6707bec 1377 /* Allocate a new Rx skb */
c91b7f66 1378 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
d6707bec
PG		 1379 if (!skb) {
1380 priv->mib.alloc_rx_buff_failed++;
1381 netif_err(priv, rx_err, priv->dev,
1382 "%s: Rx skb allocation failed\n", __func__);
1383 return NULL;
1384 }
1c1008c7 1385
d6707bec
PG		 1386 /* DMA-map the new Rx skb */
1387 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1388 DMA_FROM_DEVICE);
1389 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 1390 priv->mib.rx_dma_failed++;
d6707bec 1391 dev_kfree_skb_any(skb);
1c1008c7 1392 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 1393 "%s: Rx skb DMA mapping failed\n", __func__);
1394 return NULL;
1c1008c7
FF		 1395 }
1396
d6707bec
PG		 1397 /* Grab the current Rx skb from the ring and DMA-unmap it */
1398 rx_skb = cb->skb;
1399 if (likely(rx_skb))
1400 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1401 priv->rx_buf_len, DMA_FROM_DEVICE);
1402
1403 /* Put the new Rx skb on the ring */
1404 cb->skb = skb;
1c1008c7 1405 dma_unmap_addr_set(cb, dma_addr, mapping);
8ac467e8 1406 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 1407
d6707bec
PG		 1408 /* Return the current Rx skb to caller */
1409 return rx_skb;
1c1008c7
FF		 1410}
1411
1412/* bcmgenet_desc_rx - descriptor based rx process.
1413 * this could be called from bottom half, or from NAPI polling method.
1414 */
4055eaef 1415static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 1416 unsigned int budget)
1417{
4055eaef 1418 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 1419 struct net_device *dev = priv->dev;
1420 struct enet_cb *cb;
1421 struct sk_buff *skb;
1422 u32 dma_length_status;
1423 unsigned long dma_flag;
d6707bec 1424 int len;
1c1008c7
FF		 1425 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1426 unsigned int p_index;
d26ea6cc 1427 unsigned int discards;
1c1008c7
FF		 1428 unsigned int chksum_ok = 0;
1429
4055eaef 1430 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 1431
1432 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1433 DMA_P_INDEX_DISCARD_CNT_MASK;
1434 if (discards > ring->old_discards) {
1435 discards = discards - ring->old_discards;
1436 dev->stats.rx_missed_errors += discards;
1437 dev->stats.rx_errors += discards;
1438 ring->old_discards += discards;
1439
1440 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1441 if (ring->old_discards >= 0xC000) {
1442 ring->old_discards = 0;
4055eaef 1443 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 1444 RDMA_PROD_INDEX);
1445 }
1446 }
1447
1c1008c7
FF		 1448 p_index &= DMA_P_INDEX_MASK;
1449
8ac467e8
PG		 1450 if (likely(p_index >= ring->c_index))
1451 rxpkttoprocess = p_index - ring->c_index;
1c1008c7 1452 else
8ac467e8
PG		 1453 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1454 p_index;
1c1008c7
FF		 1455
1456 netif_dbg(priv, rx_status, dev,
c91b7f66 1457 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1458
1459 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1460 (rxpktprocessed < budget)) {
8ac467e8 1461 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 1462 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 1463
b629be5c
FF		 1464 if (unlikely(!skb)) {
1465 dev->stats.rx_dropped++;
d6707bec 1466 goto next;
b629be5c
FF		 1467 }
1468
1c1008c7 1469 if (!priv->desc_64b_en) {
c91b7f66 1470 dma_length_status =
8ac467e8 1471 dmadesc_get_length_status(priv, cb->bd_addr);
1c1008c7
FF		 1472 } else {
1473 struct status_64 *status;
164d4f20 1474
1c1008c7
FF		 1475 status = (struct status_64 *)skb->data;
1476 dma_length_status = status->length_status;
1477 }
1478
1479 /* DMA flags and length are still valid no matter how
1480 * we got the Receive Status Vector (64B RSB or register)
1481 */
1482 dma_flag = dma_length_status & 0xffff;
1483 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1484
1485 netif_dbg(priv, rx_status, dev,
c91b7f66 1486 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1487 __func__, p_index, ring->c_index,
1488 ring->read_ptr, dma_length_status);
1c1008c7 1489
1c1008c7
FF		 1490 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1491 netif_err(priv, rx_status, dev,
c91b7f66 1492 "dropping fragmented packet!\n");
1c1008c7 1493 dev->stats.rx_errors++;
d6707bec
PG		 1494 dev_kfree_skb_any(skb);
1495 goto next;
1c1008c7 1496 }
d6707bec 1497
1c1008c7
FF		 1498 /* report errors */
1499 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1500 DMA_RX_OV |
1501 DMA_RX_NO |
1502 DMA_RX_LG |
1503 DMA_RX_RXER))) {
1504 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1505 (unsigned int)dma_flag);
1c1008c7
FF		 1506 if (dma_flag & DMA_RX_CRC_ERROR)
1507 dev->stats.rx_crc_errors++;
1508 if (dma_flag & DMA_RX_OV)
1509 dev->stats.rx_over_errors++;
1510 if (dma_flag & DMA_RX_NO)
1511 dev->stats.rx_frame_errors++;
1512 if (dma_flag & DMA_RX_LG)
1513 dev->stats.rx_length_errors++;
1c1008c7 1514 dev->stats.rx_errors++;
d6707bec
PG		 1515 dev_kfree_skb_any(skb);
1516 goto next;
1c1008c7
FF		 1517 } /* error packet */
1518
1519 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1520 priv->desc_rxchk_en;
1c1008c7
FF		 1521
1522 skb_put(skb, len);
1523 if (priv->desc_64b_en) {
1524 skb_pull(skb, 64);
1525 len -= 64;
1526 }
1527
1528 if (likely(chksum_ok))
1529 skb->ip_summed = CHECKSUM_UNNECESSARY;
1530
1531 /* remove hardware 2bytes added for IP alignment */
1532 skb_pull(skb, 2);
1533 len -= 2;
1534
1535 if (priv->crc_fwd_en) {
1536 skb_trim(skb, len - ETH_FCS_LEN);
1537 len -= ETH_FCS_LEN;
1538 }
1539
1540 /*Finish setting up the received SKB and send it to the kernel*/
1541 skb->protocol = eth_type_trans(skb, priv->dev);
1542 dev->stats.rx_packets++;
1543 dev->stats.rx_bytes += len;
1544 if (dma_flag & DMA_RX_MULT)
1545 dev->stats.multicast++;
1546
1547 /* Notify kernel */
4055eaef 1548 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 1549 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1550
d6707bec 1551next:
cf377d88 1552 rxpktprocessed++;
8ac467e8
PG		 1553 if (likely(ring->read_ptr < ring->end_ptr))
1554 ring->read_ptr++;
1555 else
1556 ring->read_ptr = ring->cb_ptr;
1557
1558 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 1559 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1560 }
1561
1562 return rxpktprocessed;
1563}
1564
3ab11339
PG		 1565/* Rx NAPI polling method */
1566static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1567{
4055eaef
PG		 1568 struct bcmgenet_rx_ring *ring = container_of(napi,
1569 struct bcmgenet_rx_ring, napi);
3ab11339
PG		 1570 unsigned int work_done;
1571
4055eaef 1572 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 1573
1574 if (work_done < budget) {
1575 napi_complete(napi);
4055eaef 1576 ring->int_enable(ring);
3ab11339
PG		 1577 }
1578
1579 return work_done;
1580}
1581
1c1008c7 1582/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1583static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1584 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1585{
1586 struct enet_cb *cb;
d6707bec 1587 struct sk_buff *skb;
1c1008c7
FF		 1588 int i;
1589
8ac467e8 1590 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1591
1592 /* loop here for each buffer needing assign */
8ac467e8
PG		 1593 for (i = 0; i < ring->size; i++) {
1594 cb = ring->cbs + i;
d6707bec
PG		 1595 skb = bcmgenet_rx_refill(priv, cb);
1596 if (skb)
1597 dev_kfree_skb_any(skb);
1598 if (!cb->skb)
1599 return -ENOMEM;
1c1008c7
FF		 1600 }
1601
d6707bec 1602 return 0;
1c1008c7
FF		 1603}
1604
1605static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1606{
1607 struct enet_cb *cb;
1608 int i;
1609
1610 for (i = 0; i < priv->num_rx_bds; i++) {
1611 cb = &priv->rx_cbs[i];
1612
1613 if (dma_unmap_addr(cb, dma_addr)) {
1614 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1615 dma_unmap_addr(cb, dma_addr),
1616 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1617 dma_unmap_addr_set(cb, dma_addr, 0);
1618 }
1619
1620 if (cb->skb)
1621 bcmgenet_free_cb(cb);
1622 }
1623}
1624
c91b7f66 1625static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1626{
1627 u32 reg;
1628
1629 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1630 if (enable)
1631 reg |= mask;
1632 else
1633 reg &= ~mask;
1634 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1635
1636 /* UniMAC stops on a packet boundary, wait for a full-size packet
1637 * to be processed
1638 */
1639 if (enable == 0)
1640 usleep_range(1000, 2000);
1641}
1642
1c1008c7
FF		 1643static int reset_umac(struct bcmgenet_priv *priv)
1644{
1645 struct device *kdev = &priv->pdev->dev;
1646 unsigned int timeout = 0;
1647 u32 reg;
1648
1649 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1650 bcmgenet_rbuf_ctrl_set(priv, 0);
1651 udelay(10);
1652
1653 /* disable MAC while updating its registers */
1654 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1655
1656 /* issue soft reset, wait for it to complete */
1657 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1658 while (timeout++ < 1000) {
1659 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1660 if (!(reg & CMD_SW_RESET))
1661 return 0;
1662
1663 udelay(1);
1664 }
1665
1666 if (timeout == 1000) {
1667 dev_err(kdev,
7fc527f9 1668 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1669 return -ETIMEDOUT;
1670 }
1671
1672 return 0;
1673}
1674
909ff5ef
FF		 1675static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1676{
1677 /* Mask all interrupts.*/
1678 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1679 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1680 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1681 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1682 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1683 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1684}
1685
1c1008c7
FF		 1686static int init_umac(struct bcmgenet_priv *priv)
1687{
1688 struct device *kdev = &priv->pdev->dev;
1689 int ret;
b2e97eca
PG		 1690 u32 reg;
1691 u32 int0_enable = 0;
1692 u32 int1_enable = 0;
1693 int i;
1c1008c7
FF		 1694
1695 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1696
1697 ret = reset_umac(priv);
1698 if (ret)
1699 return ret;
1700
1701 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1702 /* clear tx/rx counter */
1703 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1704 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1705 UMAC_MIB_CTRL);
1c1008c7
FF		 1706 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1707
1708 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1709
1710 /* init rx registers, enable ip header optimization */
1711 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1712 reg |= RBUF_ALIGN_2B;
1713 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1714
1715 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1716 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1717
909ff5ef 1718 bcmgenet_intr_disable(priv);
1c1008c7 1719
b2e97eca 1720 /* Enable Rx default queue 16 interrupts */
ee7d8c20 1721 int0_enable |= UMAC_IRQ_RXDMA_DONE;
1c1008c7 1722
b2e97eca 1723 /* Enable Tx default queue 16 interrupts */
ee7d8c20 1724 int0_enable |= UMAC_IRQ_TXDMA_DONE;
1c1008c7 1725
7fc527f9 1726 /* Monitor cable plug/unplugged event for internal PHY */
c624f891 1727 if (priv->internal_phy) {
e122966d 1728 int0_enable |= UMAC_IRQ_LINK_EVENT;
8900ea57 1729 } else if (priv->ext_phy) {
e122966d 1730 int0_enable |= UMAC_IRQ_LINK_EVENT;
8900ea57 1731 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
8d88c6eb
PG		 1732 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1733 int0_enable |= UMAC_IRQ_LINK_EVENT;
1734
1c1008c7
FF		 1735 reg = bcmgenet_bp_mc_get(priv);
1736 reg |= BIT(priv->hw_params->bp_in_en_shift);
1737
1738 /* bp_mask: back pressure mask */
1739 if (netif_is_multiqueue(priv->dev))
1740 reg |= priv->hw_params->bp_in_mask;
1741 else
1742 reg &= ~priv->hw_params->bp_in_mask;
1743 bcmgenet_bp_mc_set(priv, reg);
1744 }
1745
1746 /* Enable MDIO interrupts on GENET v3+ */
1747 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 1748 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 1749
4055eaef
PG		 1750 /* Enable Rx priority queue interrupts */
1751 for (i = 0; i < priv->hw_params->rx_queues; ++i)
1752 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1753
b2e97eca
PG		 1754 /* Enable Tx priority queue interrupts */
1755 for (i = 0; i < priv->hw_params->tx_queues; ++i)
1756 int1_enable |= (1 << i);
1c1008c7 1757
b2e97eca
PG		 1758 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1759 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 1760
1c1008c7
FF		 1761 /* Enable rx/tx engine.*/
1762 dev_dbg(kdev, "done init umac\n");
1763
1764 return 0;
1765}
1766
4f8b2d7d 1767/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1768static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1769 unsigned int index, unsigned int size,
4f8b2d7d 1770 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1771{
1772 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1773 u32 words_per_bd = WORDS_PER_BD(priv);
1774 u32 flow_period_val = 0;
1c1008c7
FF		 1775
1776 spin_lock_init(&ring->lock);
4092e6ac 1777 ring->priv = priv;
1c1008c7
FF		 1778 ring->index = index;
1779 if (index == DESC_INDEX) {
1780 ring->queue = 0;
1781 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1782 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1783 } else {
1784 ring->queue = index + 1;
1785 ring->int_enable = bcmgenet_tx_ring_int_enable;
1786 ring->int_disable = bcmgenet_tx_ring_int_disable;
1787 }
4f8b2d7d 1788 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1789 ring->size = size;
66d06757 1790 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1791 ring->c_index = 0;
1792 ring->free_bds = size;
4f8b2d7d
PG		 1793 ring->write_ptr = start_ptr;
1794 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1795 ring->end_ptr = end_ptr - 1;
1796 ring->prod_index = 0;
1797
1798 /* Set flow period for ring != 16 */
1799 if (index != DESC_INDEX)
1800 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1801
1802 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1803 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1804 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1805 /* Disable rate control for now */
1806 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1807 TDMA_FLOW_PERIOD);
1c1008c7 1808 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1809 ((size << DMA_RING_SIZE_SHIFT) |
1810 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1811
1c1008c7 1812 /* Set start and end address, read and write pointers */
4f8b2d7d 1813 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1814 DMA_START_ADDR);
4f8b2d7d 1815 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1816 TDMA_READ_PTR);
4f8b2d7d 1817 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1818 TDMA_WRITE_PTR);
1c1008c7 1819 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1820 DMA_END_ADDR);
1c1008c7
FF		 1821}
1822
1823/* Initialize a RDMA ring */
1824static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 1825 unsigned int index, unsigned int size,
1826 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 1827{
8ac467e8 1828 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 1829 u32 words_per_bd = WORDS_PER_BD(priv);
1830 int ret;
1831
4055eaef 1832 ring->priv = priv;
8ac467e8 1833 ring->index = index;
4055eaef
PG		 1834 if (index == DESC_INDEX) {
1835 ring->int_enable = bcmgenet_rx_ring16_int_enable;
1836 ring->int_disable = bcmgenet_rx_ring16_int_disable;
1837 } else {
1838 ring->int_enable = bcmgenet_rx_ring_int_enable;
1839 ring->int_disable = bcmgenet_rx_ring_int_disable;
1840 }
8ac467e8
PG		 1841 ring->cbs = priv->rx_cbs + start_ptr;
1842 ring->size = size;
1843 ring->c_index = 0;
1844 ring->read_ptr = start_ptr;
1845 ring->cb_ptr = start_ptr;
1846 ring->end_ptr = end_ptr - 1;
1c1008c7 1847
8ac467e8
PG		 1848 ret = bcmgenet_alloc_rx_buffers(priv, ring);
1849 if (ret)
1c1008c7 1850 return ret;
1c1008c7 1851
1c1008c7
FF		 1852 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1853 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 1854 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 1855 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1856 ((size << DMA_RING_SIZE_SHIFT) |
1857 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1858 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1859 (DMA_FC_THRESH_LO <<
1860 DMA_XOFF_THRESHOLD_SHIFT) |
1861 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 1862
1863 /* Set start and end address, read and write pointers */
8ac467e8
PG		 1864 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1865 DMA_START_ADDR);
1866 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1867 RDMA_READ_PTR);
1868 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1869 RDMA_WRITE_PTR);
1870 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 1871 DMA_END_ADDR);
1c1008c7
FF		 1872
1873 return ret;
1874}
1875
e2aadb4a
PG		 1876static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
1877{
1878 unsigned int i;
1879 struct bcmgenet_tx_ring *ring;
1880
1881 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1882 ring = &priv->tx_rings[i];
1883 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1884 }
1885
1886 ring = &priv->tx_rings[DESC_INDEX];
1887 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1888}
1889
1890static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
1891{
1892 unsigned int i;
1893 struct bcmgenet_tx_ring *ring;
1894
1895 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1896 ring = &priv->tx_rings[i];
1897 napi_enable(&ring->napi);
1898 }
1899
1900 ring = &priv->tx_rings[DESC_INDEX];
1901 napi_enable(&ring->napi);
1902}
1903
1904static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
1905{
1906 unsigned int i;
1907 struct bcmgenet_tx_ring *ring;
1908
1909 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1910 ring = &priv->tx_rings[i];
1911 napi_disable(&ring->napi);
1912 }
1913
1914 ring = &priv->tx_rings[DESC_INDEX];
1915 napi_disable(&ring->napi);
1916}
1917
1918static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
1919{
1920 unsigned int i;
1921 struct bcmgenet_tx_ring *ring;
1922
1923 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1924 ring = &priv->tx_rings[i];
1925 netif_napi_del(&ring->napi);
1926 }
1927
1928 ring = &priv->tx_rings[DESC_INDEX];
1929 netif_napi_del(&ring->napi);
1930}
1931
16c6d667 1932/* Initialize Tx queues
1c1008c7 1933 *
16c6d667 1934 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 1935 * with queue 0 being the highest priority queue.
1936 *
16c6d667 1937 * Queue 16 is the default Tx queue with
51a966a7 1938 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 1939 *
16c6d667
PG		 1940 * The transmit control block pool is then partitioned as follows:
1941 * - Tx queue 0 uses tx_cbs[0..31]
1942 * - Tx queue 1 uses tx_cbs[32..63]
1943 * - Tx queue 2 uses tx_cbs[64..95]
1944 * - Tx queue 3 uses tx_cbs[96..127]
1945 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 1946 */
16c6d667 1947static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 1948{
1949 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 1950 u32 i, dma_enable;
1951 u32 dma_ctrl, ring_cfg;
37742166 1952 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 1953
1c1008c7
FF		 1954 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1955 dma_enable = dma_ctrl & DMA_EN;
1956 dma_ctrl &= ~DMA_EN;
1957 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1958
16c6d667
PG		 1959 dma_ctrl = 0;
1960 ring_cfg = 0;
1961
1c1008c7
FF		 1962 /* Enable strict priority arbiter mode */
1963 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1964
16c6d667 1965 /* Initialize Tx priority queues */
1c1008c7 1966 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 1967 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
1968 i * priv->hw_params->tx_bds_per_q,
1969 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 1970 ring_cfg |= (1 << i);
1971 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1972 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1973 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 1974 }
1975
16c6d667 1976 /* Initialize Tx default queue 16 */
51a966a7 1977 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 1978 priv->hw_params->tx_queues *
51a966a7 1979 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 1980 TOTAL_DESC);
1981 ring_cfg |= (1 << DESC_INDEX);
1982 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1983 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1984 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1985 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 1986
1987 /* Set Tx queue priorities */
37742166
PG		 1988 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1989 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1990 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1991
e2aadb4a
PG		 1992 /* Initialize Tx NAPI */
1993 bcmgenet_init_tx_napi(priv);
1994
16c6d667
PG		 1995 /* Enable Tx queues */
1996 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 1997
16c6d667 1998 /* Enable Tx DMA */
1c1008c7 1999 if (dma_enable)
16c6d667
PG		 2000 dma_ctrl |= DMA_EN;
2001 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2002}
2003
3ab11339
PG		 2004static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2005{
4055eaef
PG		 2006 unsigned int i;
2007 struct bcmgenet_rx_ring *ring;
2008
2009 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2010 ring = &priv->rx_rings[i];
2011 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2012 }
2013
2014 ring = &priv->rx_rings[DESC_INDEX];
2015 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
3ab11339
PG		 2016}
2017
2018static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2019{
4055eaef
PG		 2020 unsigned int i;
2021 struct bcmgenet_rx_ring *ring;
2022
2023 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2024 ring = &priv->rx_rings[i];
2025 napi_enable(&ring->napi);
2026 }
2027
2028 ring = &priv->rx_rings[DESC_INDEX];
2029 napi_enable(&ring->napi);
3ab11339
PG		 2030}
2031
2032static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2033{
4055eaef
PG		 2034 unsigned int i;
2035 struct bcmgenet_rx_ring *ring;
2036
2037 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2038 ring = &priv->rx_rings[i];
2039 napi_disable(&ring->napi);
2040 }
2041
2042 ring = &priv->rx_rings[DESC_INDEX];
2043 napi_disable(&ring->napi);
3ab11339
PG		 2044}
2045
2046static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2047{
4055eaef
PG		 2048 unsigned int i;
2049 struct bcmgenet_rx_ring *ring;
2050
2051 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2052 ring = &priv->rx_rings[i];
2053 netif_napi_del(&ring->napi);
2054 }
2055
2056 ring = &priv->rx_rings[DESC_INDEX];
2057 netif_napi_del(&ring->napi);
3ab11339
PG		 2058}
2059
8ac467e8
PG		 2060/* Initialize Rx queues
2061 *
2062 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2063 * used to direct traffic to these queues.
2064 *
2065 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2066 */
2067static int bcmgenet_init_rx_queues(struct net_device *dev)
2068{
2069 struct bcmgenet_priv *priv = netdev_priv(dev);
2070 u32 i;
2071 u32 dma_enable;
2072 u32 dma_ctrl;
2073 u32 ring_cfg;
2074 int ret;
2075
2076 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2077 dma_enable = dma_ctrl & DMA_EN;
2078 dma_ctrl &= ~DMA_EN;
2079 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2080
2081 dma_ctrl = 0;
2082 ring_cfg = 0;
2083
2084 /* Initialize Rx priority queues */
2085 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2086 ret = bcmgenet_init_rx_ring(priv, i,
2087 priv->hw_params->rx_bds_per_q,
2088 i * priv->hw_params->rx_bds_per_q,
2089 (i + 1) *
2090 priv->hw_params->rx_bds_per_q);
2091 if (ret)
2092 return ret;
2093
2094 ring_cfg |= (1 << i);
2095 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2096 }
2097
2098 /* Initialize Rx default queue 16 */
2099 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2100 priv->hw_params->rx_queues *
2101 priv->hw_params->rx_bds_per_q,
2102 TOTAL_DESC);
2103 if (ret)
2104 return ret;
2105
2106 ring_cfg |= (1 << DESC_INDEX);
2107 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2108
3ab11339
PG		 2109 /* Initialize Rx NAPI */
2110 bcmgenet_init_rx_napi(priv);
2111
8ac467e8
PG		 2112 /* Enable rings */
2113 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2114
2115 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2116 if (dma_enable)
2117 dma_ctrl |= DMA_EN;
2118 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2119
2120 return 0;
2121}
2122
4a0c081e
FF		 2123static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2124{
2125 int ret = 0;
2126 int timeout = 0;
2127 u32 reg;
b6df7d61
JS		 2128 u32 dma_ctrl;
2129 int i;
4a0c081e
FF		 2130
2131 /* Disable TDMA to stop add more frames in TX DMA */
2132 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2133 reg &= ~DMA_EN;
2134 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2135
2136 /* Check TDMA status register to confirm TDMA is disabled */
2137 while (timeout++ < DMA_TIMEOUT_VAL) {
2138 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2139 if (reg & DMA_DISABLED)
2140 break;
2141
2142 udelay(1);
2143 }
2144
2145 if (timeout == DMA_TIMEOUT_VAL) {
2146 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2147 ret = -ETIMEDOUT;
2148 }
2149
2150 /* Wait 10ms for packet drain in both tx and rx dma */
2151 usleep_range(10000, 20000);
2152
2153 /* Disable RDMA */
2154 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2155 reg &= ~DMA_EN;
2156 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2157
2158 timeout = 0;
2159 /* Check RDMA status register to confirm RDMA is disabled */
2160 while (timeout++ < DMA_TIMEOUT_VAL) {
2161 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2162 if (reg & DMA_DISABLED)
2163 break;
2164
2165 udelay(1);
2166 }
2167
2168 if (timeout == DMA_TIMEOUT_VAL) {
2169 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2170 ret = -ETIMEDOUT;
2171 }
2172
b6df7d61
JS		 2173 dma_ctrl = 0;
2174 for (i = 0; i < priv->hw_params->rx_queues; i++)
2175 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2176 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2177 reg &= ~dma_ctrl;
2178 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2179
2180 dma_ctrl = 0;
2181 for (i = 0; i < priv->hw_params->tx_queues; i++)
2182 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2183 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2184 reg &= ~dma_ctrl;
2185 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2186
4a0c081e
FF		 2187 return ret;
2188}
2189
9abab96d 2190static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 2191{
2192 int i;
2193
9abab96d
PG		 2194 bcmgenet_fini_rx_napi(priv);
2195 bcmgenet_fini_tx_napi(priv);
2196
1c1008c7 2197 /* disable DMA */
4a0c081e 2198 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2199
2200 for (i = 0; i < priv->num_tx_bds; i++) {
2201 if (priv->tx_cbs[i].skb != NULL) {
2202 dev_kfree_skb(priv->tx_cbs[i].skb);
2203 priv->tx_cbs[i].skb = NULL;
2204 }
2205 }
2206
2207 bcmgenet_free_rx_buffers(priv);
2208 kfree(priv->rx_cbs);
2209 kfree(priv->tx_cbs);
2210}
2211
2212/* init_edma: Initialize DMA control register */
2213static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2214{
2215 int ret;
014012a4
PG		 2216 unsigned int i;
2217 struct enet_cb *cb;
1c1008c7 2218
6f5a272c 2219 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2220
6f5a272c
PG		 2221 /* Initialize common Rx ring structures */
2222 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2223 priv->num_rx_bds = TOTAL_DESC;
2224 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2225 GFP_KERNEL);
2226 if (!priv->rx_cbs)
2227 return -ENOMEM;
2228
2229 for (i = 0; i < priv->num_rx_bds; i++) {
2230 cb = priv->rx_cbs + i;
2231 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2232 }
2233
7fc527f9 2234 /* Initialize common TX ring structures */
1c1008c7
FF		 2235 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2236 priv->num_tx_bds = TOTAL_DESC;
c489be08 2237 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2238 GFP_KERNEL);
1c1008c7 2239 if (!priv->tx_cbs) {
ebbd96fb 2240 kfree(priv->rx_cbs);
1c1008c7
FF		 2241 return -ENOMEM;
2242 }
2243
014012a4
PG		 2244 for (i = 0; i < priv->num_tx_bds; i++) {
2245 cb = priv->tx_cbs + i;
2246 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2247 }
2248
ebbd96fb
PG		 2249 /* Init rDma */
2250 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2251
2252 /* Initialize Rx queues */
2253 ret = bcmgenet_init_rx_queues(priv->dev);
2254 if (ret) {
2255 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2256 bcmgenet_free_rx_buffers(priv);
2257 kfree(priv->rx_cbs);
2258 kfree(priv->tx_cbs);
2259 return ret;
2260 }
2261
2262 /* Init tDma */
2263 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2264
16c6d667
PG		 2265 /* Initialize Tx queues */
2266 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2267
2268 return 0;
2269}
2270
1c1008c7
FF		 2271/* Interrupt bottom half */
2272static void bcmgenet_irq_task(struct work_struct *work)
2273{
2274 struct bcmgenet_priv *priv = container_of(
2275 work, struct bcmgenet_priv, bcmgenet_irq_work);
2276
2277 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2278
8fdb0e0f
FF		 2279 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2280 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2281 netif_dbg(priv, wol, priv->dev,
2282 "magic packet detected, waking up\n");
2283 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2284 }
2285
1c1008c7
FF		 2286 /* Link UP/DOWN event */
2287 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
e122966d 2288 (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) {
80d8e96d 2289 phy_mac_interrupt(priv->phydev,
451e1ca2 2290 !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
e122966d 2291 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
1c1008c7
FF		 2292 }
2293}
2294
4055eaef 2295/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 2296static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2297{
2298 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2299 struct bcmgenet_rx_ring *rx_ring;
2300 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2301 unsigned int index;
2302
2303 /* Save irq status for bottom-half processing. */
2304 priv->irq1_stat =
2305 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2306 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2307
7fc527f9 2308 /* clear interrupts */
1c1008c7
FF		 2309 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2310
2311 netif_dbg(priv, intr, priv->dev,
c91b7f66 2312 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2313
4055eaef
PG		 2314 /* Check Rx priority queue interrupts */
2315 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2316 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2317 continue;
2318
2319 rx_ring = &priv->rx_rings[index];
2320
2321 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2322 rx_ring->int_disable(rx_ring);
2323 __napi_schedule(&rx_ring->napi);
2324 }
2325 }
2326
2327 /* Check Tx priority queue interrupts */
4092e6ac
JS		 2328 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2329 if (!(priv->irq1_stat & BIT(index)))
2330 continue;
2331
4055eaef 2332 tx_ring = &priv->tx_rings[index];
4092e6ac 2333
4055eaef
PG		 2334 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2335 tx_ring->int_disable(tx_ring);
2336 __napi_schedule(&tx_ring->napi);
1c1008c7
FF		 2337 }
2338 }
4092e6ac 2339
1c1008c7
FF		 2340 return IRQ_HANDLED;
2341}
2342
4055eaef 2343/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 2344static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2345{
2346 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2347 struct bcmgenet_rx_ring *rx_ring;
2348 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2349
2350 /* Save irq status for bottom-half processing. */
2351 priv->irq0_stat =
2352 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2353 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2354
7fc527f9 2355 /* clear interrupts */
1c1008c7
FF		 2356 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2357
2358 netif_dbg(priv, intr, priv->dev,
c91b7f66 2359 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7 2360
ee7d8c20 2361 if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
4055eaef
PG		 2362 rx_ring = &priv->rx_rings[DESC_INDEX];
2363
2364 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2365 rx_ring->int_disable(rx_ring);
2366 __napi_schedule(&rx_ring->napi);
1c1008c7
FF		 2367 }
2368 }
4092e6ac 2369
ee7d8c20 2370 if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 2371 tx_ring = &priv->tx_rings[DESC_INDEX];
2372
2373 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2374 tx_ring->int_disable(tx_ring);
2375 __napi_schedule(&tx_ring->napi);
4092e6ac 2376 }
1c1008c7 2377 }
4055eaef 2378
1c1008c7
FF		 2379 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2380 UMAC_IRQ_PHY_DET_F |
e122966d 2381 UMAC_IRQ_LINK_EVENT |
1c1008c7
FF		 2382 UMAC_IRQ_HFB_SM |
2383 UMAC_IRQ_HFB_MM |
2384 UMAC_IRQ_MPD_R)) {
2385 /* all other interested interrupts handled in bottom half */
2386 schedule_work(&priv->bcmgenet_irq_work);
2387 }
2388
2389 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2390 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2391 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2392 wake_up(&priv->wq);
2393 }
2394
2395 return IRQ_HANDLED;
2396}
2397
8562056f
FF		 2398static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2399{
2400 struct bcmgenet_priv *priv = dev_id;
2401
2402 pm_wakeup_event(&priv->pdev->dev, 0);
2403
2404 return IRQ_HANDLED;
2405}
2406
4d2e8882
FF		 2407#ifdef CONFIG_NET_POLL_CONTROLLER
2408static void bcmgenet_poll_controller(struct net_device *dev)
2409{
2410 struct bcmgenet_priv *priv = netdev_priv(dev);
2411
2412 /* Invoke the main RX/TX interrupt handler */
2413 disable_irq(priv->irq0);
2414 bcmgenet_isr0(priv->irq0, priv);
2415 enable_irq(priv->irq0);
2416
2417 /* And the interrupt handler for RX/TX priority queues */
2418 disable_irq(priv->irq1);
2419 bcmgenet_isr1(priv->irq1, priv);
2420 enable_irq(priv->irq1);
2421}
2422#endif
2423
1c1008c7
FF		 2424static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2425{
2426 u32 reg;
2427
2428 reg = bcmgenet_rbuf_ctrl_get(priv);
2429 reg |= BIT(1);
2430 bcmgenet_rbuf_ctrl_set(priv, reg);
2431 udelay(10);
2432
2433 reg &= ~BIT(1);
2434 bcmgenet_rbuf_ctrl_set(priv, reg);
2435 udelay(10);
2436}
2437
2438static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2439 unsigned char *addr)
1c1008c7
FF		 2440{
2441 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2442 (addr[2] << 8) | addr[3], UMAC_MAC0);
2443 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2444}
2445
1c1008c7
FF		 2446/* Returns a reusable dma control register value */
2447static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2448{
2449 u32 reg;
2450 u32 dma_ctrl;
2451
2452 /* disable DMA */
2453 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2454 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2455 reg &= ~dma_ctrl;
2456 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2457
2458 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2459 reg &= ~dma_ctrl;
2460 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2461
2462 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2463 udelay(10);
2464 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2465
2466 return dma_ctrl;
2467}
2468
2469static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2470{
2471 u32 reg;
2472
2473 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2474 reg |= dma_ctrl;
2475 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2476
2477 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2478 reg |= dma_ctrl;
2479 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2480}
2481
0034de41
PG		 2482static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2483 u32 f_index)
2484{
2485 u32 offset;
2486 u32 reg;
2487
2488 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2489 reg = bcmgenet_hfb_reg_readl(priv, offset);
2490 return !!(reg & (1 << (f_index % 32)));
2491}
2492
2493static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2494{
2495 u32 offset;
2496 u32 reg;
2497
2498 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2499 reg = bcmgenet_hfb_reg_readl(priv, offset);
2500 reg |= (1 << (f_index % 32));
2501 bcmgenet_hfb_reg_writel(priv, reg, offset);
2502}
2503
2504static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2505 u32 f_index, u32 rx_queue)
2506{
2507 u32 offset;
2508 u32 reg;
2509
2510 offset = f_index / 8;
2511 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2512 reg &= ~(0xF << (4 * (f_index % 8)));
2513 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2514 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2515}
2516
2517static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2518 u32 f_index, u32 f_length)
2519{
2520 u32 offset;
2521 u32 reg;
2522
2523 offset = HFB_FLT_LEN_V3PLUS +
2524 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2525 sizeof(u32);
2526 reg = bcmgenet_hfb_reg_readl(priv, offset);
2527 reg &= ~(0xFF << (8 * (f_index % 4)));
2528 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2529 bcmgenet_hfb_reg_writel(priv, reg, offset);
2530}
2531
2532static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2533{
2534 u32 f_index;
2535
2536 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2537 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2538 return f_index;
2539
2540 return -ENOMEM;
2541}
2542
2543/* bcmgenet_hfb_add_filter
2544 *
2545 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2546 * desired Rx queue.
2547 *
2548 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2549 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2550 *
2551 * bits 31:20 - unused
2552 * bit 19 - nibble 0 match enable
2553 * bit 18 - nibble 1 match enable
2554 * bit 17 - nibble 2 match enable
2555 * bit 16 - nibble 3 match enable
2556 * bits 15:12 - nibble 0 data
2557 * bits 11:8 - nibble 1 data
2558 * bits 7:4 - nibble 2 data
2559 * bits 3:0 - nibble 3 data
2560 *
2561 * Example:
2562 * In order to match:
2563 * - Ethernet frame type = 0x0800 (IP)
2564 * - IP version field = 4
2565 * - IP protocol field = 0x11 (UDP)
2566 *
2567 * The following filter is needed:
2568 * u32 hfb_filter_ipv4_udp[] = {
2569 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2570 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2571 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2572 * };
2573 *
2574 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2575 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2576 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2577 */
2578int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2579 u32 f_length, u32 rx_queue)
2580{
2581 int f_index;
2582 u32 i;
2583
2584 f_index = bcmgenet_hfb_find_unused_filter(priv);
2585 if (f_index < 0)
2586 return -ENOMEM;
2587
2588 if (f_length > priv->hw_params->hfb_filter_size)
2589 return -EINVAL;
2590
2591 for (i = 0; i < f_length; i++)
2592 bcmgenet_hfb_writel(priv, f_data[i],
2593 (f_index * priv->hw_params->hfb_filter_size + i) *
2594 sizeof(u32));
2595
2596 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2597 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2598 bcmgenet_hfb_enable_filter(priv, f_index);
2599 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2600
2601 return 0;
2602}
2603
2604/* bcmgenet_hfb_clear
2605 *
2606 * Clear Hardware Filter Block and disable all filtering.
2607 */
2608static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2609{
2610 u32 i;
2611
2612 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2613 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2614 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2615
2616 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2617 bcmgenet_rdma_writel(priv, 0x0, i);
2618
2619 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2620 bcmgenet_hfb_reg_writel(priv, 0x0,
2621 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2622
2623 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2624 priv->hw_params->hfb_filter_size; i++)
2625 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2626}
2627
2628static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2629{
2630 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2631 return;
2632
2633 bcmgenet_hfb_clear(priv);
2634}
2635
909ff5ef
FF		 2636static void bcmgenet_netif_start(struct net_device *dev)
2637{
2638 struct bcmgenet_priv *priv = netdev_priv(dev);
2639
2640 /* Start the network engine */
3ab11339 2641 bcmgenet_enable_rx_napi(priv);
e2aadb4a 2642 bcmgenet_enable_tx_napi(priv);
909ff5ef
FF		 2643
2644 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2645
909ff5ef
FF		 2646 netif_tx_start_all_queues(dev);
2647
2648 phy_start(priv->phydev);
2649}
2650
1c1008c7
FF		 2651static int bcmgenet_open(struct net_device *dev)
2652{
2653 struct bcmgenet_priv *priv = netdev_priv(dev);
2654 unsigned long dma_ctrl;
2655 u32 reg;
2656 int ret;
2657
2658 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2659
2660 /* Turn on the clock */
7d5d3075 2661 clk_prepare_enable(priv->clk);
1c1008c7 2662
a642c4f7
FF		 2663 /* If this is an internal GPHY, power it back on now, before UniMAC is
2664 * brought out of reset as absolutely no UniMAC activity is allowed
2665 */
c624f891 2666 if (priv->internal_phy)
a642c4f7
FF		 2667 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2668
1c1008c7
FF		 2669 /* take MAC out of reset */
2670 bcmgenet_umac_reset(priv);
2671
2672 ret = init_umac(priv);
2673 if (ret)
2674 goto err_clk_disable;
2675
2676 /* disable ethernet MAC while updating its registers */
e29585b8 2677 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2678
909ff5ef
FF		 2679 /* Make sure we reflect the value of CRC_CMD_FWD */
2680 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2681 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2682
1c1008c7
FF		 2683 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2684
c624f891 2685 if (priv->internal_phy) {
1c1008c7
FF		 2686 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2687 reg |= EXT_ENERGY_DET_MASK;
2688 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2689 }
2690
2691 /* Disable RX/TX DMA and flush TX queues */
2692 dma_ctrl = bcmgenet_dma_disable(priv);
2693
2694 /* Reinitialize TDMA and RDMA and SW housekeeping */
2695 ret = bcmgenet_init_dma(priv);
2696 if (ret) {
2697 netdev_err(dev, "failed to initialize DMA\n");
fac25940 2698 goto err_clk_disable;
1c1008c7
FF		 2699 }
2700
2701 /* Always enable ring 16 - descriptor ring */
2702 bcmgenet_enable_dma(priv, dma_ctrl);
2703
0034de41
PG		 2704 /* HFB init */
2705 bcmgenet_hfb_init(priv);
2706
1c1008c7 2707 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2708 dev->name, priv);
1c1008c7
FF		 2709 if (ret < 0) {
2710 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2711 goto err_fini_dma;
2712 }
2713
2714 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2715 dev->name, priv);
1c1008c7
FF		 2716 if (ret < 0) {
2717 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2718 goto err_irq0;
2719 }
2720
6cc8e6d4
FF		 2721 ret = bcmgenet_mii_probe(dev);
2722 if (ret) {
2723 netdev_err(dev, "failed to connect to PHY\n");
2724 goto err_irq1;
2725 }
c96e731c 2726
909ff5ef 2727 bcmgenet_netif_start(dev);
1c1008c7
FF		 2728
2729 return 0;
2730
6cc8e6d4
FF		 2731err_irq1:
2732 free_irq(priv->irq1, priv);
1c1008c7 2733err_irq0:
978ffac4 2734 free_irq(priv->irq0, priv);
1c1008c7
FF		 2735err_fini_dma:
2736 bcmgenet_fini_dma(priv);
2737err_clk_disable:
7d5d3075 2738 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 2739 return ret;
2740}
2741
909ff5ef
FF		 2742static void bcmgenet_netif_stop(struct net_device *dev)
2743{
2744 struct bcmgenet_priv *priv = netdev_priv(dev);
2745
2746 netif_tx_stop_all_queues(dev);
909ff5ef 2747 phy_stop(priv->phydev);
909ff5ef 2748 bcmgenet_intr_disable(priv);
3ab11339 2749 bcmgenet_disable_rx_napi(priv);
e2aadb4a 2750 bcmgenet_disable_tx_napi(priv);
909ff5ef
FF		 2751
2752 /* Wait for pending work items to complete. Since interrupts are
2753 * disabled no new work will be scheduled.
2754 */
2755 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2756
cc013fb4 2757 priv->old_link = -1;
5ad6e6c5 2758 priv->old_speed = -1;
cc013fb4 2759 priv->old_duplex = -1;
5ad6e6c5 2760 priv->old_pause = -1;
909ff5ef
FF		 2761}
2762
1c1008c7
FF		 2763static int bcmgenet_close(struct net_device *dev)
2764{
2765 struct bcmgenet_priv *priv = netdev_priv(dev);
2766 int ret;
1c1008c7
FF		 2767
2768 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2769
909ff5ef 2770 bcmgenet_netif_stop(dev);
1c1008c7 2771
c96e731c
FF		 2772 /* Really kill the PHY state machine and disconnect from it */
2773 phy_disconnect(priv->phydev);
2774
1c1008c7 2775 /* Disable MAC receive */
e29585b8 2776 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2777
1c1008c7
FF		 2778 ret = bcmgenet_dma_teardown(priv);
2779 if (ret)
2780 return ret;
2781
2782 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2783 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2784
1c1008c7
FF		 2785 /* tx reclaim */
2786 bcmgenet_tx_reclaim_all(dev);
2787 bcmgenet_fini_dma(priv);
2788
2789 free_irq(priv->irq0, priv);
2790 free_irq(priv->irq1, priv);
2791
c624f891 2792 if (priv->internal_phy)
ca8cf341 2793 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 2794
7d5d3075 2795 clk_disable_unprepare(priv->clk);
1c1008c7 2796
ca8cf341 2797 return ret;
1c1008c7
FF		 2798}
2799
13ea6578
FF		 2800static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2801{
2802 struct bcmgenet_priv *priv = ring->priv;
2803 u32 p_index, c_index, intsts, intmsk;
2804 struct netdev_queue *txq;
2805 unsigned int free_bds;
2806 unsigned long flags;
2807 bool txq_stopped;
2808
2809 if (!netif_msg_tx_err(priv))
2810 return;
2811
2812 txq = netdev_get_tx_queue(priv->dev, ring->queue);
2813
2814 spin_lock_irqsave(&ring->lock, flags);
2815 if (ring->index == DESC_INDEX) {
2816 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2817 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2818 } else {
2819 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2820 intmsk = 1 << ring->index;
2821 }
2822 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2823 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2824 txq_stopped = netif_tx_queue_stopped(txq);
2825 free_bds = ring->free_bds;
2826 spin_unlock_irqrestore(&ring->lock, flags);
2827
2828 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2829 "TX queue status: %s, interrupts: %s\n"
2830 "(sw)free_bds: %d (sw)size: %d\n"
2831 "(sw)p_index: %d (hw)p_index: %d\n"
2832 "(sw)c_index: %d (hw)c_index: %d\n"
2833 "(sw)clean_p: %d (sw)write_p: %d\n"
2834 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2835 ring->index, ring->queue,
2836 txq_stopped ? "stopped" : "active",
2837 intsts & intmsk ? "enabled" : "disabled",
2838 free_bds, ring->size,
2839 ring->prod_index, p_index & DMA_P_INDEX_MASK,
2840 ring->c_index, c_index & DMA_C_INDEX_MASK,
2841 ring->clean_ptr, ring->write_ptr,
2842 ring->cb_ptr, ring->end_ptr);
2843}
2844
1c1008c7
FF		 2845static void bcmgenet_timeout(struct net_device *dev)
2846{
2847 struct bcmgenet_priv *priv = netdev_priv(dev);
13ea6578
FF		 2848 u32 int0_enable = 0;
2849 u32 int1_enable = 0;
2850 unsigned int q;
1c1008c7
FF		 2851
2852 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2853
13ea6578
FF		 2854 for (q = 0; q < priv->hw_params->tx_queues; q++)
2855 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
2856 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
2857
2858 bcmgenet_tx_reclaim_all(dev);
2859
2860 for (q = 0; q < priv->hw_params->tx_queues; q++)
2861 int1_enable |= (1 << q);
2862
2863 int0_enable = UMAC_IRQ_TXDMA_DONE;
2864
2865 /* Re-enable TX interrupts if disabled */
2866 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2867 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2868
1c1008c7
FF		 2869 dev->trans_start = jiffies;
2870
2871 dev->stats.tx_errors++;
2872
2873 netif_tx_wake_all_queues(dev);
2874}
2875
2876#define MAX_MC_COUNT 16
2877
2878static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2879 unsigned char *addr,
2880 int *i,
2881 int *mc)
2882{
2883 u32 reg;
2884
c91b7f66
FF		 2885 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2886 UMAC_MDF_ADDR + (*i * 4));
2887 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2888 addr[4] << 8 | addr[5],
2889 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2890 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2891 reg |= (1 << (MAX_MC_COUNT - *mc));
2892 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2893 *i += 2;
2894 (*mc)++;
2895}
2896
2897static void bcmgenet_set_rx_mode(struct net_device *dev)
2898{
2899 struct bcmgenet_priv *priv = netdev_priv(dev);
2900 struct netdev_hw_addr *ha;
2901 int i, mc;
2902 u32 reg;
2903
2904 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2905
7fc527f9 2906 /* Promiscuous mode */
1c1008c7
FF		 2907 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2908 if (dev->flags & IFF_PROMISC) {
2909 reg |= CMD_PROMISC;
2910 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2911 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2912 return;
2913 } else {
2914 reg &= ~CMD_PROMISC;
2915 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2916 }
2917
2918 /* UniMac doesn't support ALLMULTI */
2919 if (dev->flags & IFF_ALLMULTI) {
2920 netdev_warn(dev, "ALLMULTI is not supported\n");
2921 return;
2922 }
2923
2924 /* update MDF filter */
2925 i = 0;
2926 mc = 0;
2927 /* Broadcast */
2928 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2929 /* my own address.*/
2930 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2931 /* Unicast list*/
2932 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2933 return;
2934
2935 if (!netdev_uc_empty(dev))
2936 netdev_for_each_uc_addr(ha, dev)
2937 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2938 /* Multicast */
2939 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2940 return;
2941
2942 netdev_for_each_mc_addr(ha, dev)
2943 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2944}
2945
2946/* Set the hardware MAC address. */
2947static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2948{
2949 struct sockaddr *addr = p;
2950
2951 /* Setting the MAC address at the hardware level is not possible
2952 * without disabling the UniMAC RX/TX enable bits.
2953 */
2954 if (netif_running(dev))
2955 return -EBUSY;
2956
2957 ether_addr_copy(dev->dev_addr, addr->sa_data);
2958
2959 return 0;
2960}
2961
1c1008c7
FF		 2962static const struct net_device_ops bcmgenet_netdev_ops = {
2963 .ndo_open = bcmgenet_open,
2964 .ndo_stop = bcmgenet_close,
2965 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2966 .ndo_tx_timeout = bcmgenet_timeout,
2967 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2968 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2969 .ndo_do_ioctl = bcmgenet_ioctl,
2970 .ndo_set_features = bcmgenet_set_features,
4d2e8882
FF		 2971#ifdef CONFIG_NET_POLL_CONTROLLER
2972 .ndo_poll_controller = bcmgenet_poll_controller,
2973#endif
1c1008c7
FF		 2974};
2975
2976/* Array of GENET hardware parameters/characteristics */
2977static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2978 [GENET_V1] = {
2979 .tx_queues = 0,
51a966a7 2980 .tx_bds_per_q = 0,
1c1008c7 2981 .rx_queues = 0,
3feafa02 2982 .rx_bds_per_q = 0,
1c1008c7
FF		 2983 .bp_in_en_shift = 16,
2984 .bp_in_mask = 0xffff,
2985 .hfb_filter_cnt = 16,
2986 .qtag_mask = 0x1F,
2987 .hfb_offset = 0x1000,
2988 .rdma_offset = 0x2000,
2989 .tdma_offset = 0x3000,
2990 .words_per_bd = 2,
2991 },
2992 [GENET_V2] = {
2993 .tx_queues = 4,
51a966a7 2994 .tx_bds_per_q = 32,
7e906e02 2995 .rx_queues = 0,
3feafa02 2996 .rx_bds_per_q = 0,
1c1008c7
FF		 2997 .bp_in_en_shift = 16,
2998 .bp_in_mask = 0xffff,
2999 .hfb_filter_cnt = 16,
3000 .qtag_mask = 0x1F,
3001 .tbuf_offset = 0x0600,
3002 .hfb_offset = 0x1000,
3003 .hfb_reg_offset = 0x2000,
3004 .rdma_offset = 0x3000,
3005 .tdma_offset = 0x4000,
3006 .words_per_bd = 2,
3007 .flags = GENET_HAS_EXT,
3008 },
3009 [GENET_V3] = {
3010 .tx_queues = 4,
51a966a7 3011 .tx_bds_per_q = 32,
7e906e02 3012 .rx_queues = 0,
3feafa02 3013 .rx_bds_per_q = 0,
1c1008c7
FF		 3014 .bp_in_en_shift = 17,
3015 .bp_in_mask = 0x1ffff,
3016 .hfb_filter_cnt = 48,
0034de41 3017 .hfb_filter_size = 128,
1c1008c7
FF		 3018 .qtag_mask = 0x3F,
3019 .tbuf_offset = 0x0600,
3020 .hfb_offset = 0x8000,
3021 .hfb_reg_offset = 0xfc00,
3022 .rdma_offset = 0x10000,
3023 .tdma_offset = 0x11000,
3024 .words_per_bd = 2,
8d88c6eb
PG		 3025 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3026 GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3027 },
3028 [GENET_V4] = {
3029 .tx_queues = 4,
51a966a7 3030 .tx_bds_per_q = 32,
7e906e02 3031 .rx_queues = 0,
3feafa02 3032 .rx_bds_per_q = 0,
1c1008c7
FF		 3033 .bp_in_en_shift = 17,
3034 .bp_in_mask = 0x1ffff,
3035 .hfb_filter_cnt = 48,
0034de41 3036 .hfb_filter_size = 128,
1c1008c7
FF		 3037 .qtag_mask = 0x3F,
3038 .tbuf_offset = 0x0600,
3039 .hfb_offset = 0x8000,
3040 .hfb_reg_offset = 0xfc00,
3041 .rdma_offset = 0x2000,
3042 .tdma_offset = 0x4000,
3043 .words_per_bd = 3,
8d88c6eb
PG		 3044 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3045 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3046 },
3047};
3048
3049/* Infer hardware parameters from the detected GENET version */
3050static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3051{
3052 struct bcmgenet_hw_params *params;
3053 u32 reg;
3054 u8 major;
b04a2f5b 3055 u16 gphy_rev;
1c1008c7
FF		 3056
3057 if (GENET_IS_V4(priv)) {
3058 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3059 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3060 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3061 priv->version = GENET_V4;
3062 } else if (GENET_IS_V3(priv)) {
3063 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3064 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3065 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3066 priv->version = GENET_V3;
3067 } else if (GENET_IS_V2(priv)) {
3068 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3069 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3070 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3071 priv->version = GENET_V2;
3072 } else if (GENET_IS_V1(priv)) {
3073 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3074 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3075 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3076 priv->version = GENET_V1;
3077 }
3078
3079 /* enum genet_version starts at 1 */
3080 priv->hw_params = &bcmgenet_hw_params[priv->version];
3081 params = priv->hw_params;
3082
3083 /* Read GENET HW version */
3084 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3085 major = (reg >> 24 & 0x0f);
3086 if (major == 5)
3087 major = 4;
3088 else if (major == 0)
3089 major = 1;
3090 if (major != priv->version) {
3091 dev_err(&priv->pdev->dev,
3092 "GENET version mismatch, got: %d, configured for: %d\n",
3093 major, priv->version);
3094 }
3095
3096 /* Print the GENET core version */
3097 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3098 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3099
487320c5
FF		 3100 /* Store the integrated PHY revision for the MDIO probing function
3101 * to pass this information to the PHY driver. The PHY driver expects
3102 * to find the PHY major revision in bits 15:8 while the GENET register
3103 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3104 *
3105 * On newer chips, starting with PHY revision G0, a new scheme is
3106 * deployed similar to the Starfighter 2 switch with GPHY major
3107 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3108 * is reserved as well as special value 0x01ff, we have a small
3109 * heuristic to check for the new GPHY revision and re-arrange things
3110 * so the GPHY driver is happy.
487320c5 3111 */
b04a2f5b
FF		 3112 gphy_rev = reg & 0xffff;
3113
3114 /* This is the good old scheme, just GPHY major, no minor nor patch */
3115 if ((gphy_rev & 0xf0) != 0)
3116 priv->gphy_rev = gphy_rev << 8;
3117
3118 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3119 else if ((gphy_rev & 0xff00) != 0)
3120 priv->gphy_rev = gphy_rev;
3121
3122 /* This is reserved so should require special treatment */
3123 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3124 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3125 return;
3126 }
487320c5 3127
1c1008c7
FF		 3128#ifdef CONFIG_PHYS_ADDR_T_64BIT
3129 if (!(params->flags & GENET_HAS_40BITS))
3130 pr_warn("GENET does not support 40-bits PA\n");
3131#endif
3132
3133 pr_debug("Configuration for version: %d\n"
3feafa02 3134 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3135 "BP << en: %2d, BP msk: 0x%05x\n"
3136 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3137 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3138 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3139 "Words/BD: %d\n",
3140 priv->version,
51a966a7 3141 params->tx_queues, params->tx_bds_per_q,
3feafa02 3142 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3143 params->bp_in_en_shift, params->bp_in_mask,
3144 params->hfb_filter_cnt, params->qtag_mask,
3145 params->tbuf_offset, params->hfb_offset,
3146 params->hfb_reg_offset,
3147 params->rdma_offset, params->tdma_offset,
3148 params->words_per_bd);
3149}
3150
3151static const struct of_device_id bcmgenet_match[] = {
3152 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3153 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3154 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3155 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3156 { },
3157};
3158
3159static int bcmgenet_probe(struct platform_device *pdev)
3160{
b0ba512e 3161 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 3162 struct device_node *dn = pdev->dev.of_node;
b0ba512e 3163 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 3164 struct bcmgenet_priv *priv;
3165 struct net_device *dev;
3166 const void *macaddr;
3167 struct resource *r;
3168 int err = -EIO;
3169
3feafeed
PG		 3170 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3171 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3172 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3173 if (!dev) {
3174 dev_err(&pdev->dev, "can't allocate net device\n");
3175 return -ENOMEM;
3176 }
3177
b0ba512e
PG		 3178 if (dn) {
3179 of_id = of_match_node(bcmgenet_match, dn);
3180 if (!of_id)
3181 return -EINVAL;
3182 }
1c1008c7
FF		 3183
3184 priv = netdev_priv(dev);
3185 priv->irq0 = platform_get_irq(pdev, 0);
3186 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 3187 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 3188 if (!priv->irq0 || !priv->irq1) {
3189 dev_err(&pdev->dev, "can't find IRQs\n");
3190 err = -EINVAL;
3191 goto err;
3192 }
3193
b0ba512e
PG		 3194 if (dn) {
3195 macaddr = of_get_mac_address(dn);
3196 if (!macaddr) {
3197 dev_err(&pdev->dev, "can't find MAC address\n");
3198 err = -EINVAL;
3199 goto err;
3200 }
3201 } else {
3202 macaddr = pd->mac_address;
1c1008c7
FF		 3203 }
3204
3205 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 3206 priv->base = devm_ioremap_resource(&pdev->dev, r);
3207 if (IS_ERR(priv->base)) {
3208 err = PTR_ERR(priv->base);
1c1008c7
FF		 3209 goto err;
3210 }
3211
3212 SET_NETDEV_DEV(dev, &pdev->dev);
3213 dev_set_drvdata(&pdev->dev, dev);
3214 ether_addr_copy(dev->dev_addr, macaddr);
3215 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 3216 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 3217 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 3218
3219 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3220
3221 /* Set hardware features */
3222 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3223 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3224
8562056f
FF		 3225 /* Request the WOL interrupt and advertise suspend if available */
3226 priv->wol_irq_disabled = true;
3227 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3228 dev->name, priv);
3229 if (!err)
3230 device_set_wakeup_capable(&pdev->dev, 1);
3231
1c1008c7
FF		 3232 /* Set the needed headroom to account for any possible
3233 * features enabling/disabling at runtime
3234 */
3235 dev->needed_headroom += 64;
3236
3237 netdev_boot_setup_check(dev);
3238
3239 priv->dev = dev;
3240 priv->pdev = pdev;
b0ba512e
PG		 3241 if (of_id)
3242 priv->version = (enum bcmgenet_version)of_id->data;
3243 else
3244 priv->version = pd->genet_version;
1c1008c7 3245
e4a60a93 3246 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
7d5d3075 3247 if (IS_ERR(priv->clk)) {
e4a60a93 3248 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
7d5d3075
FF		 3249 priv->clk = NULL;
3250 }
e4a60a93 3251
7d5d3075 3252 clk_prepare_enable(priv->clk);
e4a60a93 3253
1c1008c7
FF		 3254 bcmgenet_set_hw_params(priv);
3255
1c1008c7
FF		 3256 /* Mii wait queue */
3257 init_waitqueue_head(&priv->wq);
3258 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3259 priv->rx_buf_len = RX_BUF_LENGTH;
3260 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3261
1c1008c7 3262 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
7d5d3075 3263 if (IS_ERR(priv->clk_wol)) {
1c1008c7 3264 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
7d5d3075
FF		 3265 priv->clk_wol = NULL;
3266 }
1c1008c7 3267
6ef398ea
FF		 3268 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3269 if (IS_ERR(priv->clk_eee)) {
3270 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3271 priv->clk_eee = NULL;
3272 }
3273
1c1008c7
FF		 3274 err = reset_umac(priv);
3275 if (err)
3276 goto err_clk_disable;
3277
3278 err = bcmgenet_mii_init(dev);
3279 if (err)
3280 goto err_clk_disable;
3281
3282 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3283 * just the ring 16 descriptor based TX
3284 */
3285 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3286 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3287
219575eb
FF		 3288 /* libphy will determine the link state */
3289 netif_carrier_off(dev);
3290
1c1008c7 3291 /* Turn off the main clock, WOL clock is handled separately */
7d5d3075 3292 clk_disable_unprepare(priv->clk);
1c1008c7 3293
0f50ce96
FF		 3294 err = register_netdev(dev);
3295 if (err)
3296 goto err;
3297
1c1008c7
FF		 3298 return err;
3299
3300err_clk_disable:
7d5d3075 3301 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 3302err:
3303 free_netdev(dev);
3304 return err;
3305}
3306
3307static int bcmgenet_remove(struct platform_device *pdev)
3308{
3309 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3310
3311 dev_set_drvdata(&pdev->dev, NULL);
3312 unregister_netdev(priv->dev);
3313 bcmgenet_mii_exit(priv->dev);
3314 free_netdev(priv->dev);
3315
3316 return 0;
3317}
3318
b6e978e5
FF		 3319#ifdef CONFIG_PM_SLEEP
3320static int bcmgenet_suspend(struct device *d)
3321{
3322 struct net_device *dev = dev_get_drvdata(d);
3323 struct bcmgenet_priv *priv = netdev_priv(dev);
3324 int ret;
3325
3326 if (!netif_running(dev))
3327 return 0;
3328
3329 bcmgenet_netif_stop(dev);
3330
cc013fb4
FF		 3331 phy_suspend(priv->phydev);
3332
b6e978e5
FF		 3333 netif_device_detach(dev);
3334
3335 /* Disable MAC receive */
3336 umac_enable_set(priv, CMD_RX_EN, false);
3337
3338 ret = bcmgenet_dma_teardown(priv);
3339 if (ret)
3340 return ret;
3341
3342 /* Disable MAC transmit. TX DMA disabled have to done before this */
3343 umac_enable_set(priv, CMD_TX_EN, false);
3344
3345 /* tx reclaim */
3346 bcmgenet_tx_reclaim_all(dev);
3347 bcmgenet_fini_dma(priv);
3348
8c90db72
FF		 3349 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3350 if (device_may_wakeup(d) && priv->wolopts) {
ca8cf341 3351 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
8c90db72 3352 clk_prepare_enable(priv->clk_wol);
c624f891 3353 } else if (priv->internal_phy) {
a6f31f5e 3354 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
8c90db72
FF		 3355 }
3356
b6e978e5
FF		 3357 /* Turn off the clocks */
3358 clk_disable_unprepare(priv->clk);
3359
ca8cf341 3360 return ret;
b6e978e5
FF		 3361}
3362
3363static int bcmgenet_resume(struct device *d)
3364{
3365 struct net_device *dev = dev_get_drvdata(d);
3366 struct bcmgenet_priv *priv = netdev_priv(dev);
3367 unsigned long dma_ctrl;
3368 int ret;
3369 u32 reg;
3370
3371 if (!netif_running(dev))
3372 return 0;
3373
3374 /* Turn on the clock */
3375 ret = clk_prepare_enable(priv->clk);
3376 if (ret)
3377 return ret;
3378
a6f31f5e
FF		 3379 /* If this is an internal GPHY, power it back on now, before UniMAC is
3380 * brought out of reset as absolutely no UniMAC activity is allowed
3381 */
c624f891 3382 if (priv->internal_phy)
a6f31f5e
FF		 3383 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3384
b6e978e5
FF		 3385 bcmgenet_umac_reset(priv);
3386
3387 ret = init_umac(priv);
3388 if (ret)
3389 goto out_clk_disable;
3390
0a29b3da
TK		 3391 /* From WOL-enabled suspend, switch to regular clock */
3392 if (priv->wolopts)
3393 clk_disable_unprepare(priv->clk_wol);
3394
3395 phy_init_hw(priv->phydev);
3396 /* Speed settings must be restored */
28b45910 3397 bcmgenet_mii_config(priv->dev);
8c90db72 3398
b6e978e5
FF		 3399 /* disable ethernet MAC while updating its registers */
3400 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3401
3402 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3403
c624f891 3404 if (priv->internal_phy) {
b6e978e5
FF		 3405 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3406 reg |= EXT_ENERGY_DET_MASK;
3407 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3408 }
3409
98bb7399
FF		 3410 if (priv->wolopts)
3411 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3412
b6e978e5
FF		 3413 /* Disable RX/TX DMA and flush TX queues */
3414 dma_ctrl = bcmgenet_dma_disable(priv);
3415
3416 /* Reinitialize TDMA and RDMA and SW housekeeping */
3417 ret = bcmgenet_init_dma(priv);
3418 if (ret) {
3419 netdev_err(dev, "failed to initialize DMA\n");
3420 goto out_clk_disable;
3421 }
3422
3423 /* Always enable ring 16 - descriptor ring */
3424 bcmgenet_enable_dma(priv, dma_ctrl);
3425
3426 netif_device_attach(dev);
3427
cc013fb4
FF		 3428 phy_resume(priv->phydev);
3429
6ef398ea
FF		 3430 if (priv->eee.eee_enabled)
3431 bcmgenet_eee_enable_set(dev, true);
3432
b6e978e5
FF		 3433 bcmgenet_netif_start(dev);
3434
3435 return 0;
3436
3437out_clk_disable:
3438 clk_disable_unprepare(priv->clk);
3439 return ret;
3440}
3441#endif /* CONFIG_PM_SLEEP */
3442
3443static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3444
1c1008c7
FF		 3445static struct platform_driver bcmgenet_driver = {
3446 .probe = bcmgenet_probe,
3447 .remove = bcmgenet_remove,
3448 .driver = {
3449 .name = "bcmgenet",
1c1008c7 3450 .of_match_table = bcmgenet_match,
b6e978e5 3451 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 3452 },
3453};
3454module_platform_driver(bcmgenet_driver);
3455
3456MODULE_AUTHOR("Broadcom Corporation");
3457MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3458MODULE_ALIAS("platform:bcmgenet");
3459MODULE_LICENSE("GPL");
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