]>
Commit | Line | Data |
---|---|---|
1c1008c7 FF |
1 | /* |
2 | * Broadcom GENET (Gigabit Ethernet) controller driver | |
3 | * | |
c298ede2 | 4 | * Copyright (c) 2014-2017 Broadcom |
1c1008c7 FF |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
1c1008c7 FF |
9 | */ |
10 | ||
11 | #define pr_fmt(fmt) "bcmgenet: " fmt | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/fcntl.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/if_ether.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/clk.h> | |
1c1008c7 FF |
28 | #include <linux/of.h> |
29 | #include <linux/of_address.h> | |
30 | #include <linux/of_irq.h> | |
31 | #include <linux/of_net.h> | |
32 | #include <linux/of_platform.h> | |
33 | #include <net/arp.h> | |
34 | ||
35 | #include <linux/mii.h> | |
36 | #include <linux/ethtool.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/inetdevice.h> | |
39 | #include <linux/etherdevice.h> | |
40 | #include <linux/skbuff.h> | |
41 | #include <linux/in.h> | |
42 | #include <linux/ip.h> | |
43 | #include <linux/ipv6.h> | |
44 | #include <linux/phy.h> | |
b0ba512e | 45 | #include <linux/platform_data/bcmgenet.h> |
1c1008c7 FF |
46 | |
47 | #include <asm/unaligned.h> | |
48 | ||
49 | #include "bcmgenet.h" | |
50 | ||
51 | /* Maximum number of hardware queues, downsized if needed */ | |
52 | #define GENET_MAX_MQ_CNT 4 | |
53 | ||
54 | /* Default highest priority queue for multi queue support */ | |
55 | #define GENET_Q0_PRIORITY 0 | |
56 | ||
3feafa02 PG |
57 | #define GENET_Q16_RX_BD_CNT \ |
58 | (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) | |
51a966a7 PG |
59 | #define GENET_Q16_TX_BD_CNT \ |
60 | (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) | |
1c1008c7 FF |
61 | |
62 | #define RX_BUF_LENGTH 2048 | |
63 | #define SKB_ALIGNMENT 32 | |
64 | ||
65 | /* Tx/Rx DMA register offset, skip 256 descriptors */ | |
66 | #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) | |
67 | #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) | |
68 | ||
69 | #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ | |
70 | TOTAL_DESC * DMA_DESC_SIZE) | |
71 | ||
72 | #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ | |
73 | TOTAL_DESC * DMA_DESC_SIZE) | |
74 | ||
75 | static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, | |
c91b7f66 | 76 | void __iomem *d, u32 value) |
1c1008c7 FF |
77 | { |
78 | __raw_writel(value, d + DMA_DESC_LENGTH_STATUS); | |
79 | } | |
80 | ||
81 | static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv, | |
c91b7f66 | 82 | void __iomem *d) |
1c1008c7 FF |
83 | { |
84 | return __raw_readl(d + DMA_DESC_LENGTH_STATUS); | |
85 | } | |
86 | ||
87 | static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, | |
88 | void __iomem *d, | |
89 | dma_addr_t addr) | |
90 | { | |
91 | __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); | |
92 | ||
93 | /* Register writes to GISB bus can take couple hundred nanoseconds | |
94 | * and are done for each packet, save these expensive writes unless | |
7fc527f9 | 95 | * the platform is explicitly configured for 64-bits/LPAE. |
1c1008c7 FF |
96 | */ |
97 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
98 | if (priv->hw_params->flags & GENET_HAS_40BITS) | |
99 | __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); | |
100 | #endif | |
101 | } | |
102 | ||
103 | /* Combined address + length/status setter */ | |
104 | static inline void dmadesc_set(struct bcmgenet_priv *priv, | |
c91b7f66 | 105 | void __iomem *d, dma_addr_t addr, u32 val) |
1c1008c7 | 106 | { |
1c1008c7 | 107 | dmadesc_set_addr(priv, d, addr); |
7ee40625 | 108 | dmadesc_set_length_status(priv, d, val); |
1c1008c7 FF |
109 | } |
110 | ||
111 | static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, | |
112 | void __iomem *d) | |
113 | { | |
114 | dma_addr_t addr; | |
115 | ||
116 | addr = __raw_readl(d + DMA_DESC_ADDRESS_LO); | |
117 | ||
118 | /* Register writes to GISB bus can take couple hundred nanoseconds | |
119 | * and are done for each packet, save these expensive writes unless | |
7fc527f9 | 120 | * the platform is explicitly configured for 64-bits/LPAE. |
1c1008c7 FF |
121 | */ |
122 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
123 | if (priv->hw_params->flags & GENET_HAS_40BITS) | |
124 | addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32; | |
125 | #endif | |
126 | return addr; | |
127 | } | |
128 | ||
129 | #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" | |
130 | ||
131 | #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ | |
132 | NETIF_MSG_LINK) | |
133 | ||
134 | static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) | |
135 | { | |
136 | if (GENET_IS_V1(priv)) | |
137 | return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); | |
138 | else | |
139 | return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); | |
140 | } | |
141 | ||
142 | static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) | |
143 | { | |
144 | if (GENET_IS_V1(priv)) | |
145 | bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); | |
146 | else | |
147 | bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); | |
148 | } | |
149 | ||
150 | /* These macros are defined to deal with register map change | |
151 | * between GENET1.1 and GENET2. Only those currently being used | |
152 | * by driver are defined. | |
153 | */ | |
154 | static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) | |
155 | { | |
156 | if (GENET_IS_V1(priv)) | |
157 | return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); | |
158 | else | |
159 | return __raw_readl(priv->base + | |
160 | priv->hw_params->tbuf_offset + TBUF_CTRL); | |
161 | } | |
162 | ||
163 | static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) | |
164 | { | |
165 | if (GENET_IS_V1(priv)) | |
166 | bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); | |
167 | else | |
168 | __raw_writel(val, priv->base + | |
169 | priv->hw_params->tbuf_offset + TBUF_CTRL); | |
170 | } | |
171 | ||
172 | static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) | |
173 | { | |
174 | if (GENET_IS_V1(priv)) | |
175 | return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); | |
176 | else | |
177 | return __raw_readl(priv->base + | |
178 | priv->hw_params->tbuf_offset + TBUF_BP_MC); | |
179 | } | |
180 | ||
181 | static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) | |
182 | { | |
183 | if (GENET_IS_V1(priv)) | |
184 | bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); | |
185 | else | |
186 | __raw_writel(val, priv->base + | |
187 | priv->hw_params->tbuf_offset + TBUF_BP_MC); | |
188 | } | |
189 | ||
190 | /* RX/TX DMA register accessors */ | |
191 | enum dma_reg { | |
192 | DMA_RING_CFG = 0, | |
193 | DMA_CTRL, | |
194 | DMA_STATUS, | |
195 | DMA_SCB_BURST_SIZE, | |
196 | DMA_ARB_CTRL, | |
37742166 PG |
197 | DMA_PRIORITY_0, |
198 | DMA_PRIORITY_1, | |
199 | DMA_PRIORITY_2, | |
0034de41 PG |
200 | DMA_INDEX2RING_0, |
201 | DMA_INDEX2RING_1, | |
202 | DMA_INDEX2RING_2, | |
203 | DMA_INDEX2RING_3, | |
204 | DMA_INDEX2RING_4, | |
205 | DMA_INDEX2RING_5, | |
206 | DMA_INDEX2RING_6, | |
207 | DMA_INDEX2RING_7, | |
4a29645b FF |
208 | DMA_RING0_TIMEOUT, |
209 | DMA_RING1_TIMEOUT, | |
210 | DMA_RING2_TIMEOUT, | |
211 | DMA_RING3_TIMEOUT, | |
212 | DMA_RING4_TIMEOUT, | |
213 | DMA_RING5_TIMEOUT, | |
214 | DMA_RING6_TIMEOUT, | |
215 | DMA_RING7_TIMEOUT, | |
216 | DMA_RING8_TIMEOUT, | |
217 | DMA_RING9_TIMEOUT, | |
218 | DMA_RING10_TIMEOUT, | |
219 | DMA_RING11_TIMEOUT, | |
220 | DMA_RING12_TIMEOUT, | |
221 | DMA_RING13_TIMEOUT, | |
222 | DMA_RING14_TIMEOUT, | |
223 | DMA_RING15_TIMEOUT, | |
224 | DMA_RING16_TIMEOUT, | |
1c1008c7 FF |
225 | }; |
226 | ||
227 | static const u8 bcmgenet_dma_regs_v3plus[] = { | |
228 | [DMA_RING_CFG] = 0x00, | |
229 | [DMA_CTRL] = 0x04, | |
230 | [DMA_STATUS] = 0x08, | |
231 | [DMA_SCB_BURST_SIZE] = 0x0C, | |
232 | [DMA_ARB_CTRL] = 0x2C, | |
37742166 PG |
233 | [DMA_PRIORITY_0] = 0x30, |
234 | [DMA_PRIORITY_1] = 0x34, | |
235 | [DMA_PRIORITY_2] = 0x38, | |
4a29645b FF |
236 | [DMA_RING0_TIMEOUT] = 0x2C, |
237 | [DMA_RING1_TIMEOUT] = 0x30, | |
238 | [DMA_RING2_TIMEOUT] = 0x34, | |
239 | [DMA_RING3_TIMEOUT] = 0x38, | |
240 | [DMA_RING4_TIMEOUT] = 0x3c, | |
241 | [DMA_RING5_TIMEOUT] = 0x40, | |
242 | [DMA_RING6_TIMEOUT] = 0x44, | |
243 | [DMA_RING7_TIMEOUT] = 0x48, | |
244 | [DMA_RING8_TIMEOUT] = 0x4c, | |
245 | [DMA_RING9_TIMEOUT] = 0x50, | |
246 | [DMA_RING10_TIMEOUT] = 0x54, | |
247 | [DMA_RING11_TIMEOUT] = 0x58, | |
248 | [DMA_RING12_TIMEOUT] = 0x5c, | |
249 | [DMA_RING13_TIMEOUT] = 0x60, | |
250 | [DMA_RING14_TIMEOUT] = 0x64, | |
251 | [DMA_RING15_TIMEOUT] = 0x68, | |
252 | [DMA_RING16_TIMEOUT] = 0x6C, | |
0034de41 PG |
253 | [DMA_INDEX2RING_0] = 0x70, |
254 | [DMA_INDEX2RING_1] = 0x74, | |
255 | [DMA_INDEX2RING_2] = 0x78, | |
256 | [DMA_INDEX2RING_3] = 0x7C, | |
257 | [DMA_INDEX2RING_4] = 0x80, | |
258 | [DMA_INDEX2RING_5] = 0x84, | |
259 | [DMA_INDEX2RING_6] = 0x88, | |
260 | [DMA_INDEX2RING_7] = 0x8C, | |
1c1008c7 FF |
261 | }; |
262 | ||
263 | static const u8 bcmgenet_dma_regs_v2[] = { | |
264 | [DMA_RING_CFG] = 0x00, | |
265 | [DMA_CTRL] = 0x04, | |
266 | [DMA_STATUS] = 0x08, | |
267 | [DMA_SCB_BURST_SIZE] = 0x0C, | |
268 | [DMA_ARB_CTRL] = 0x30, | |
37742166 PG |
269 | [DMA_PRIORITY_0] = 0x34, |
270 | [DMA_PRIORITY_1] = 0x38, | |
271 | [DMA_PRIORITY_2] = 0x3C, | |
4a29645b FF |
272 | [DMA_RING0_TIMEOUT] = 0x2C, |
273 | [DMA_RING1_TIMEOUT] = 0x30, | |
274 | [DMA_RING2_TIMEOUT] = 0x34, | |
275 | [DMA_RING3_TIMEOUT] = 0x38, | |
276 | [DMA_RING4_TIMEOUT] = 0x3c, | |
277 | [DMA_RING5_TIMEOUT] = 0x40, | |
278 | [DMA_RING6_TIMEOUT] = 0x44, | |
279 | [DMA_RING7_TIMEOUT] = 0x48, | |
280 | [DMA_RING8_TIMEOUT] = 0x4c, | |
281 | [DMA_RING9_TIMEOUT] = 0x50, | |
282 | [DMA_RING10_TIMEOUT] = 0x54, | |
283 | [DMA_RING11_TIMEOUT] = 0x58, | |
284 | [DMA_RING12_TIMEOUT] = 0x5c, | |
285 | [DMA_RING13_TIMEOUT] = 0x60, | |
286 | [DMA_RING14_TIMEOUT] = 0x64, | |
287 | [DMA_RING15_TIMEOUT] = 0x68, | |
288 | [DMA_RING16_TIMEOUT] = 0x6C, | |
1c1008c7 FF |
289 | }; |
290 | ||
291 | static const u8 bcmgenet_dma_regs_v1[] = { | |
292 | [DMA_CTRL] = 0x00, | |
293 | [DMA_STATUS] = 0x04, | |
294 | [DMA_SCB_BURST_SIZE] = 0x0C, | |
295 | [DMA_ARB_CTRL] = 0x30, | |
37742166 PG |
296 | [DMA_PRIORITY_0] = 0x34, |
297 | [DMA_PRIORITY_1] = 0x38, | |
298 | [DMA_PRIORITY_2] = 0x3C, | |
4a29645b FF |
299 | [DMA_RING0_TIMEOUT] = 0x2C, |
300 | [DMA_RING1_TIMEOUT] = 0x30, | |
301 | [DMA_RING2_TIMEOUT] = 0x34, | |
302 | [DMA_RING3_TIMEOUT] = 0x38, | |
303 | [DMA_RING4_TIMEOUT] = 0x3c, | |
304 | [DMA_RING5_TIMEOUT] = 0x40, | |
305 | [DMA_RING6_TIMEOUT] = 0x44, | |
306 | [DMA_RING7_TIMEOUT] = 0x48, | |
307 | [DMA_RING8_TIMEOUT] = 0x4c, | |
308 | [DMA_RING9_TIMEOUT] = 0x50, | |
309 | [DMA_RING10_TIMEOUT] = 0x54, | |
310 | [DMA_RING11_TIMEOUT] = 0x58, | |
311 | [DMA_RING12_TIMEOUT] = 0x5c, | |
312 | [DMA_RING13_TIMEOUT] = 0x60, | |
313 | [DMA_RING14_TIMEOUT] = 0x64, | |
314 | [DMA_RING15_TIMEOUT] = 0x68, | |
315 | [DMA_RING16_TIMEOUT] = 0x6C, | |
1c1008c7 FF |
316 | }; |
317 | ||
318 | /* Set at runtime once bcmgenet version is known */ | |
319 | static const u8 *bcmgenet_dma_regs; | |
320 | ||
321 | static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) | |
322 | { | |
323 | return netdev_priv(dev_get_drvdata(dev)); | |
324 | } | |
325 | ||
326 | static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, | |
c91b7f66 | 327 | enum dma_reg r) |
1c1008c7 FF |
328 | { |
329 | return __raw_readl(priv->base + GENET_TDMA_REG_OFF + | |
330 | DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); | |
331 | } | |
332 | ||
333 | static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, | |
334 | u32 val, enum dma_reg r) | |
335 | { | |
336 | __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + | |
337 | DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); | |
338 | } | |
339 | ||
340 | static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, | |
c91b7f66 | 341 | enum dma_reg r) |
1c1008c7 FF |
342 | { |
343 | return __raw_readl(priv->base + GENET_RDMA_REG_OFF + | |
344 | DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); | |
345 | } | |
346 | ||
347 | static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, | |
348 | u32 val, enum dma_reg r) | |
349 | { | |
350 | __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + | |
351 | DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); | |
352 | } | |
353 | ||
354 | /* RDMA/TDMA ring registers and accessors | |
355 | * we merge the common fields and just prefix with T/D the registers | |
356 | * having different meaning depending on the direction | |
357 | */ | |
358 | enum dma_ring_reg { | |
359 | TDMA_READ_PTR = 0, | |
360 | RDMA_WRITE_PTR = TDMA_READ_PTR, | |
361 | TDMA_READ_PTR_HI, | |
362 | RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, | |
363 | TDMA_CONS_INDEX, | |
364 | RDMA_PROD_INDEX = TDMA_CONS_INDEX, | |
365 | TDMA_PROD_INDEX, | |
366 | RDMA_CONS_INDEX = TDMA_PROD_INDEX, | |
367 | DMA_RING_BUF_SIZE, | |
368 | DMA_START_ADDR, | |
369 | DMA_START_ADDR_HI, | |
370 | DMA_END_ADDR, | |
371 | DMA_END_ADDR_HI, | |
372 | DMA_MBUF_DONE_THRESH, | |
373 | TDMA_FLOW_PERIOD, | |
374 | RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, | |
375 | TDMA_WRITE_PTR, | |
376 | RDMA_READ_PTR = TDMA_WRITE_PTR, | |
377 | TDMA_WRITE_PTR_HI, | |
378 | RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI | |
379 | }; | |
380 | ||
381 | /* GENET v4 supports 40-bits pointer addressing | |
382 | * for obvious reasons the LO and HI word parts | |
383 | * are contiguous, but this offsets the other | |
384 | * registers. | |
385 | */ | |
386 | static const u8 genet_dma_ring_regs_v4[] = { | |
387 | [TDMA_READ_PTR] = 0x00, | |
388 | [TDMA_READ_PTR_HI] = 0x04, | |
389 | [TDMA_CONS_INDEX] = 0x08, | |
390 | [TDMA_PROD_INDEX] = 0x0C, | |
391 | [DMA_RING_BUF_SIZE] = 0x10, | |
392 | [DMA_START_ADDR] = 0x14, | |
393 | [DMA_START_ADDR_HI] = 0x18, | |
394 | [DMA_END_ADDR] = 0x1C, | |
395 | [DMA_END_ADDR_HI] = 0x20, | |
396 | [DMA_MBUF_DONE_THRESH] = 0x24, | |
397 | [TDMA_FLOW_PERIOD] = 0x28, | |
398 | [TDMA_WRITE_PTR] = 0x2C, | |
399 | [TDMA_WRITE_PTR_HI] = 0x30, | |
400 | }; | |
401 | ||
402 | static const u8 genet_dma_ring_regs_v123[] = { | |
403 | [TDMA_READ_PTR] = 0x00, | |
404 | [TDMA_CONS_INDEX] = 0x04, | |
405 | [TDMA_PROD_INDEX] = 0x08, | |
406 | [DMA_RING_BUF_SIZE] = 0x0C, | |
407 | [DMA_START_ADDR] = 0x10, | |
408 | [DMA_END_ADDR] = 0x14, | |
409 | [DMA_MBUF_DONE_THRESH] = 0x18, | |
410 | [TDMA_FLOW_PERIOD] = 0x1C, | |
411 | [TDMA_WRITE_PTR] = 0x20, | |
412 | }; | |
413 | ||
414 | /* Set at runtime once GENET version is known */ | |
415 | static const u8 *genet_dma_ring_regs; | |
416 | ||
417 | static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, | |
c91b7f66 FF |
418 | unsigned int ring, |
419 | enum dma_ring_reg r) | |
1c1008c7 FF |
420 | { |
421 | return __raw_readl(priv->base + GENET_TDMA_REG_OFF + | |
422 | (DMA_RING_SIZE * ring) + | |
423 | genet_dma_ring_regs[r]); | |
424 | } | |
425 | ||
426 | static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, | |
c91b7f66 FF |
427 | unsigned int ring, u32 val, |
428 | enum dma_ring_reg r) | |
1c1008c7 FF |
429 | { |
430 | __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + | |
431 | (DMA_RING_SIZE * ring) + | |
432 | genet_dma_ring_regs[r]); | |
433 | } | |
434 | ||
435 | static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, | |
c91b7f66 FF |
436 | unsigned int ring, |
437 | enum dma_ring_reg r) | |
1c1008c7 FF |
438 | { |
439 | return __raw_readl(priv->base + GENET_RDMA_REG_OFF + | |
440 | (DMA_RING_SIZE * ring) + | |
441 | genet_dma_ring_regs[r]); | |
442 | } | |
443 | ||
444 | static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, | |
c91b7f66 FF |
445 | unsigned int ring, u32 val, |
446 | enum dma_ring_reg r) | |
1c1008c7 FF |
447 | { |
448 | __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + | |
449 | (DMA_RING_SIZE * ring) + | |
450 | genet_dma_ring_regs[r]); | |
451 | } | |
452 | ||
fa92bf04 PR |
453 | static int bcmgenet_get_link_ksettings(struct net_device *dev, |
454 | struct ethtool_link_ksettings *cmd) | |
bac65c4b | 455 | { |
0299b6ac FF |
456 | struct bcmgenet_priv *priv = netdev_priv(dev); |
457 | ||
bac65c4b PR |
458 | if (!netif_running(dev)) |
459 | return -EINVAL; | |
460 | ||
0299b6ac | 461 | if (!priv->phydev) |
bac65c4b PR |
462 | return -ENODEV; |
463 | ||
fa92bf04 | 464 | return phy_ethtool_ksettings_get(priv->phydev, cmd); |
bac65c4b PR |
465 | } |
466 | ||
fa92bf04 PR |
467 | static int bcmgenet_set_link_ksettings(struct net_device *dev, |
468 | const struct ethtool_link_ksettings *cmd) | |
bac65c4b | 469 | { |
0299b6ac FF |
470 | struct bcmgenet_priv *priv = netdev_priv(dev); |
471 | ||
bac65c4b PR |
472 | if (!netif_running(dev)) |
473 | return -EINVAL; | |
474 | ||
0299b6ac | 475 | if (!priv->phydev) |
bac65c4b PR |
476 | return -ENODEV; |
477 | ||
fa92bf04 | 478 | return phy_ethtool_ksettings_set(priv->phydev, cmd); |
bac65c4b PR |
479 | } |
480 | ||
1c1008c7 FF |
481 | static int bcmgenet_set_rx_csum(struct net_device *dev, |
482 | netdev_features_t wanted) | |
483 | { | |
484 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
485 | u32 rbuf_chk_ctrl; | |
486 | bool rx_csum_en; | |
487 | ||
488 | rx_csum_en = !!(wanted & NETIF_F_RXCSUM); | |
489 | ||
490 | rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); | |
491 | ||
492 | /* enable rx checksumming */ | |
493 | if (rx_csum_en) | |
494 | rbuf_chk_ctrl |= RBUF_RXCHK_EN; | |
495 | else | |
496 | rbuf_chk_ctrl &= ~RBUF_RXCHK_EN; | |
497 | priv->desc_rxchk_en = rx_csum_en; | |
ebe5e3c6 FF |
498 | |
499 | /* If UniMAC forwards CRC, we need to skip over it to get | |
500 | * a valid CHK bit to be set in the per-packet status word | |
501 | */ | |
502 | if (rx_csum_en && priv->crc_fwd_en) | |
503 | rbuf_chk_ctrl |= RBUF_SKIP_FCS; | |
504 | else | |
505 | rbuf_chk_ctrl &= ~RBUF_SKIP_FCS; | |
506 | ||
1c1008c7 FF |
507 | bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL); |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
512 | static int bcmgenet_set_tx_csum(struct net_device *dev, | |
513 | netdev_features_t wanted) | |
514 | { | |
515 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
516 | bool desc_64b_en; | |
517 | u32 tbuf_ctrl, rbuf_ctrl; | |
518 | ||
519 | tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv); | |
520 | rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL); | |
521 | ||
522 | desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); | |
523 | ||
524 | /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */ | |
525 | if (desc_64b_en) { | |
526 | tbuf_ctrl |= RBUF_64B_EN; | |
527 | rbuf_ctrl |= RBUF_64B_EN; | |
528 | } else { | |
529 | tbuf_ctrl &= ~RBUF_64B_EN; | |
530 | rbuf_ctrl &= ~RBUF_64B_EN; | |
531 | } | |
532 | priv->desc_64b_en = desc_64b_en; | |
533 | ||
534 | bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl); | |
535 | bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL); | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
540 | static int bcmgenet_set_features(struct net_device *dev, | |
c91b7f66 | 541 | netdev_features_t features) |
1c1008c7 FF |
542 | { |
543 | netdev_features_t changed = features ^ dev->features; | |
544 | netdev_features_t wanted = dev->wanted_features; | |
545 | int ret = 0; | |
546 | ||
547 | if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) | |
548 | ret = bcmgenet_set_tx_csum(dev, wanted); | |
549 | if (changed & (NETIF_F_RXCSUM)) | |
550 | ret = bcmgenet_set_rx_csum(dev, wanted); | |
551 | ||
552 | return ret; | |
553 | } | |
554 | ||
555 | static u32 bcmgenet_get_msglevel(struct net_device *dev) | |
556 | { | |
557 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
558 | ||
559 | return priv->msg_enable; | |
560 | } | |
561 | ||
562 | static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) | |
563 | { | |
564 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
565 | ||
566 | priv->msg_enable = level; | |
567 | } | |
568 | ||
2f913070 FF |
569 | static int bcmgenet_get_coalesce(struct net_device *dev, |
570 | struct ethtool_coalesce *ec) | |
571 | { | |
572 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
573 | ||
574 | ec->tx_max_coalesced_frames = | |
575 | bcmgenet_tdma_ring_readl(priv, DESC_INDEX, | |
576 | DMA_MBUF_DONE_THRESH); | |
4a29645b FF |
577 | ec->rx_max_coalesced_frames = |
578 | bcmgenet_rdma_ring_readl(priv, DESC_INDEX, | |
579 | DMA_MBUF_DONE_THRESH); | |
580 | ec->rx_coalesce_usecs = | |
581 | bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; | |
2f913070 FF |
582 | |
583 | return 0; | |
584 | } | |
585 | ||
586 | static int bcmgenet_set_coalesce(struct net_device *dev, | |
587 | struct ethtool_coalesce *ec) | |
588 | { | |
589 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
590 | unsigned int i; | |
4a29645b | 591 | u32 reg; |
2f913070 | 592 | |
4a29645b FF |
593 | /* Base system clock is 125Mhz, DMA timeout is this reference clock |
594 | * divided by 1024, which yields roughly 8.192us, our maximum value | |
595 | * has to fit in the DMA_TIMEOUT_MASK (16 bits) | |
596 | */ | |
2f913070 | 597 | if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || |
4a29645b FF |
598 | ec->tx_max_coalesced_frames == 0 || |
599 | ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || | |
600 | ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) | |
601 | return -EINVAL; | |
602 | ||
603 | if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) | |
2f913070 FF |
604 | return -EINVAL; |
605 | ||
606 | /* GENET TDMA hardware does not support a configurable timeout, but will | |
607 | * always generate an interrupt either after MBDONE packets have been | |
556c2cf4 | 608 | * transmitted, or when the ring is empty. |
2f913070 FF |
609 | */ |
610 | if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high || | |
852bcafb | 611 | ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low) |
2f913070 FF |
612 | return -EOPNOTSUPP; |
613 | ||
614 | /* Program all TX queues with the same values, as there is no | |
615 | * ethtool knob to do coalescing on a per-queue basis | |
616 | */ | |
617 | for (i = 0; i < priv->hw_params->tx_queues; i++) | |
618 | bcmgenet_tdma_ring_writel(priv, i, | |
619 | ec->tx_max_coalesced_frames, | |
620 | DMA_MBUF_DONE_THRESH); | |
621 | bcmgenet_tdma_ring_writel(priv, DESC_INDEX, | |
622 | ec->tx_max_coalesced_frames, | |
623 | DMA_MBUF_DONE_THRESH); | |
624 | ||
4a29645b FF |
625 | for (i = 0; i < priv->hw_params->rx_queues; i++) { |
626 | bcmgenet_rdma_ring_writel(priv, i, | |
627 | ec->rx_max_coalesced_frames, | |
628 | DMA_MBUF_DONE_THRESH); | |
629 | ||
630 | reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); | |
631 | reg &= ~DMA_TIMEOUT_MASK; | |
632 | reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192); | |
633 | bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); | |
634 | } | |
635 | ||
636 | bcmgenet_rdma_ring_writel(priv, DESC_INDEX, | |
637 | ec->rx_max_coalesced_frames, | |
638 | DMA_MBUF_DONE_THRESH); | |
639 | ||
640 | reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT); | |
641 | reg &= ~DMA_TIMEOUT_MASK; | |
642 | reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192); | |
643 | bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT); | |
644 | ||
2f913070 FF |
645 | return 0; |
646 | } | |
647 | ||
1c1008c7 FF |
648 | /* standard ethtool support functions. */ |
649 | enum bcmgenet_stat_type { | |
650 | BCMGENET_STAT_NETDEV = -1, | |
651 | BCMGENET_STAT_MIB_RX, | |
652 | BCMGENET_STAT_MIB_TX, | |
653 | BCMGENET_STAT_RUNT, | |
654 | BCMGENET_STAT_MISC, | |
f62ba9c1 | 655 | BCMGENET_STAT_SOFT, |
1c1008c7 FF |
656 | }; |
657 | ||
658 | struct bcmgenet_stats { | |
659 | char stat_string[ETH_GSTRING_LEN]; | |
660 | int stat_sizeof; | |
661 | int stat_offset; | |
662 | enum bcmgenet_stat_type type; | |
663 | /* reg offset from UMAC base for misc counters */ | |
664 | u16 reg_offset; | |
665 | }; | |
666 | ||
667 | #define STAT_NETDEV(m) { \ | |
668 | .stat_string = __stringify(m), \ | |
669 | .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ | |
670 | .stat_offset = offsetof(struct net_device_stats, m), \ | |
671 | .type = BCMGENET_STAT_NETDEV, \ | |
672 | } | |
673 | ||
674 | #define STAT_GENET_MIB(str, m, _type) { \ | |
675 | .stat_string = str, \ | |
676 | .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ | |
677 | .stat_offset = offsetof(struct bcmgenet_priv, m), \ | |
678 | .type = _type, \ | |
679 | } | |
680 | ||
681 | #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) | |
682 | #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) | |
683 | #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) | |
f62ba9c1 | 684 | #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) |
1c1008c7 FF |
685 | |
686 | #define STAT_GENET_MISC(str, m, offset) { \ | |
687 | .stat_string = str, \ | |
688 | .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ | |
689 | .stat_offset = offsetof(struct bcmgenet_priv, m), \ | |
690 | .type = BCMGENET_STAT_MISC, \ | |
691 | .reg_offset = offset, \ | |
692 | } | |
693 | ||
694 | ||
695 | /* There is a 0xC gap between the end of RX and beginning of TX stats and then | |
696 | * between the end of TX stats and the beginning of the RX RUNT | |
697 | */ | |
698 | #define BCMGENET_STAT_OFFSET 0xc | |
699 | ||
700 | /* Hardware counters must be kept in sync because the order/offset | |
701 | * is important here (order in structure declaration = order in hardware) | |
702 | */ | |
703 | static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { | |
704 | /* general stats */ | |
705 | STAT_NETDEV(rx_packets), | |
706 | STAT_NETDEV(tx_packets), | |
707 | STAT_NETDEV(rx_bytes), | |
708 | STAT_NETDEV(tx_bytes), | |
709 | STAT_NETDEV(rx_errors), | |
710 | STAT_NETDEV(tx_errors), | |
711 | STAT_NETDEV(rx_dropped), | |
712 | STAT_NETDEV(tx_dropped), | |
713 | STAT_NETDEV(multicast), | |
714 | /* UniMAC RSV counters */ | |
715 | STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), | |
716 | STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), | |
717 | STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), | |
718 | STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), | |
719 | STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), | |
720 | STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), | |
721 | STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), | |
722 | STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), | |
723 | STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), | |
724 | STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), | |
725 | STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), | |
726 | STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), | |
727 | STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), | |
728 | STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), | |
729 | STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), | |
730 | STAT_GENET_MIB_RX("rx_control", mib.rx.cf), | |
731 | STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), | |
732 | STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), | |
733 | STAT_GENET_MIB_RX("rx_align", mib.rx.aln), | |
734 | STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), | |
735 | STAT_GENET_MIB_RX("rx_code", mib.rx.cde), | |
736 | STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), | |
737 | STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), | |
738 | STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), | |
739 | STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), | |
740 | STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), | |
741 | STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), | |
742 | STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), | |
743 | STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), | |
744 | /* UniMAC TSV counters */ | |
745 | STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), | |
746 | STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), | |
747 | STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), | |
748 | STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), | |
749 | STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), | |
750 | STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), | |
751 | STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), | |
752 | STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), | |
753 | STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), | |
754 | STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), | |
755 | STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), | |
756 | STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), | |
757 | STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), | |
758 | STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), | |
759 | STAT_GENET_MIB_TX("tx_control", mib.tx.cf), | |
760 | STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), | |
761 | STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), | |
762 | STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), | |
763 | STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), | |
764 | STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), | |
765 | STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), | |
766 | STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), | |
767 | STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), | |
768 | STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), | |
769 | STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), | |
770 | STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), | |
771 | STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), | |
772 | STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), | |
773 | STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), | |
774 | /* UniMAC RUNT counters */ | |
775 | STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), | |
776 | STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), | |
777 | STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), | |
778 | STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), | |
779 | /* Misc UniMAC counters */ | |
780 | STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, | |
781 | UMAC_RBUF_OVFL_CNT), | |
782 | STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT), | |
783 | STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), | |
f62ba9c1 FF |
784 | STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), |
785 | STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), | |
786 | STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), | |
1c1008c7 FF |
787 | }; |
788 | ||
789 | #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) | |
790 | ||
791 | static void bcmgenet_get_drvinfo(struct net_device *dev, | |
c91b7f66 | 792 | struct ethtool_drvinfo *info) |
1c1008c7 FF |
793 | { |
794 | strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); | |
795 | strlcpy(info->version, "v2.0", sizeof(info->version)); | |
1c1008c7 FF |
796 | } |
797 | ||
798 | static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) | |
799 | { | |
800 | switch (string_set) { | |
801 | case ETH_SS_STATS: | |
802 | return BCMGENET_STATS_LEN; | |
803 | default: | |
804 | return -EOPNOTSUPP; | |
805 | } | |
806 | } | |
807 | ||
c91b7f66 FF |
808 | static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, |
809 | u8 *data) | |
1c1008c7 FF |
810 | { |
811 | int i; | |
812 | ||
813 | switch (stringset) { | |
814 | case ETH_SS_STATS: | |
815 | for (i = 0; i < BCMGENET_STATS_LEN; i++) { | |
816 | memcpy(data + i * ETH_GSTRING_LEN, | |
c91b7f66 FF |
817 | bcmgenet_gstrings_stats[i].stat_string, |
818 | ETH_GSTRING_LEN); | |
1c1008c7 FF |
819 | } |
820 | break; | |
821 | } | |
822 | } | |
823 | ||
824 | static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) | |
825 | { | |
826 | int i, j = 0; | |
827 | ||
828 | for (i = 0; i < BCMGENET_STATS_LEN; i++) { | |
829 | const struct bcmgenet_stats *s; | |
830 | u8 offset = 0; | |
831 | u32 val = 0; | |
832 | char *p; | |
833 | ||
834 | s = &bcmgenet_gstrings_stats[i]; | |
835 | switch (s->type) { | |
836 | case BCMGENET_STAT_NETDEV: | |
f62ba9c1 | 837 | case BCMGENET_STAT_SOFT: |
1c1008c7 FF |
838 | continue; |
839 | case BCMGENET_STAT_MIB_RX: | |
840 | case BCMGENET_STAT_MIB_TX: | |
841 | case BCMGENET_STAT_RUNT: | |
842 | if (s->type != BCMGENET_STAT_MIB_RX) | |
843 | offset = BCMGENET_STAT_OFFSET; | |
c91b7f66 FF |
844 | val = bcmgenet_umac_readl(priv, |
845 | UMAC_MIB_START + j + offset); | |
1c1008c7 FF |
846 | break; |
847 | case BCMGENET_STAT_MISC: | |
848 | val = bcmgenet_umac_readl(priv, s->reg_offset); | |
849 | /* clear if overflowed */ | |
850 | if (val == ~0) | |
851 | bcmgenet_umac_writel(priv, 0, s->reg_offset); | |
852 | break; | |
853 | } | |
854 | ||
855 | j += s->stat_sizeof; | |
856 | p = (char *)priv + s->stat_offset; | |
857 | *(u32 *)p = val; | |
858 | } | |
859 | } | |
860 | ||
861 | static void bcmgenet_get_ethtool_stats(struct net_device *dev, | |
c91b7f66 FF |
862 | struct ethtool_stats *stats, |
863 | u64 *data) | |
1c1008c7 FF |
864 | { |
865 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
866 | int i; | |
867 | ||
868 | if (netif_running(dev)) | |
869 | bcmgenet_update_mib_counters(priv); | |
870 | ||
871 | for (i = 0; i < BCMGENET_STATS_LEN; i++) { | |
872 | const struct bcmgenet_stats *s; | |
873 | char *p; | |
874 | ||
875 | s = &bcmgenet_gstrings_stats[i]; | |
876 | if (s->type == BCMGENET_STAT_NETDEV) | |
877 | p = (char *)&dev->stats; | |
878 | else | |
879 | p = (char *)priv; | |
880 | p += s->stat_offset; | |
6517eb59 ED |
881 | if (sizeof(unsigned long) != sizeof(u32) && |
882 | s->stat_sizeof == sizeof(unsigned long)) | |
883 | data[i] = *(unsigned long *)p; | |
884 | else | |
885 | data[i] = *(u32 *)p; | |
1c1008c7 FF |
886 | } |
887 | } | |
888 | ||
6ef398ea FF |
889 | static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) |
890 | { | |
891 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
892 | u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; | |
893 | u32 reg; | |
894 | ||
895 | if (enable && !priv->clk_eee_enabled) { | |
896 | clk_prepare_enable(priv->clk_eee); | |
897 | priv->clk_eee_enabled = true; | |
898 | } | |
899 | ||
900 | reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); | |
901 | if (enable) | |
902 | reg |= EEE_EN; | |
903 | else | |
904 | reg &= ~EEE_EN; | |
905 | bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); | |
906 | ||
907 | /* Enable EEE and switch to a 27Mhz clock automatically */ | |
908 | reg = __raw_readl(priv->base + off); | |
909 | if (enable) | |
910 | reg |= TBUF_EEE_EN | TBUF_PM_EN; | |
911 | else | |
912 | reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); | |
913 | __raw_writel(reg, priv->base + off); | |
914 | ||
915 | /* Do the same for thing for RBUF */ | |
916 | reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); | |
917 | if (enable) | |
918 | reg |= RBUF_EEE_EN | RBUF_PM_EN; | |
919 | else | |
920 | reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); | |
921 | bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); | |
922 | ||
923 | if (!enable && priv->clk_eee_enabled) { | |
924 | clk_disable_unprepare(priv->clk_eee); | |
925 | priv->clk_eee_enabled = false; | |
926 | } | |
927 | ||
928 | priv->eee.eee_enabled = enable; | |
929 | priv->eee.eee_active = enable; | |
930 | } | |
931 | ||
932 | static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) | |
933 | { | |
934 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
935 | struct ethtool_eee *p = &priv->eee; | |
936 | ||
937 | if (GENET_IS_V1(priv)) | |
938 | return -EOPNOTSUPP; | |
939 | ||
940 | e->eee_enabled = p->eee_enabled; | |
941 | e->eee_active = p->eee_active; | |
942 | e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); | |
943 | ||
0299b6ac | 944 | return phy_ethtool_get_eee(priv->phydev, e); |
6ef398ea FF |
945 | } |
946 | ||
947 | static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) | |
948 | { | |
949 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
950 | struct ethtool_eee *p = &priv->eee; | |
951 | int ret = 0; | |
952 | ||
953 | if (GENET_IS_V1(priv)) | |
954 | return -EOPNOTSUPP; | |
955 | ||
956 | p->eee_enabled = e->eee_enabled; | |
957 | ||
958 | if (!p->eee_enabled) { | |
959 | bcmgenet_eee_enable_set(dev, false); | |
960 | } else { | |
0299b6ac | 961 | ret = phy_init_eee(priv->phydev, 0); |
6ef398ea FF |
962 | if (ret) { |
963 | netif_err(priv, hw, dev, "EEE initialization failed\n"); | |
964 | return ret; | |
965 | } | |
966 | ||
967 | bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); | |
968 | bcmgenet_eee_enable_set(dev, true); | |
969 | } | |
970 | ||
0299b6ac | 971 | return phy_ethtool_set_eee(priv->phydev, e); |
6ef398ea FF |
972 | } |
973 | ||
1c1008c7 | 974 | /* standard ethtool support functions. */ |
70591ab9 | 975 | static const struct ethtool_ops bcmgenet_ethtool_ops = { |
1c1008c7 FF |
976 | .get_strings = bcmgenet_get_strings, |
977 | .get_sset_count = bcmgenet_get_sset_count, | |
978 | .get_ethtool_stats = bcmgenet_get_ethtool_stats, | |
1c1008c7 FF |
979 | .get_drvinfo = bcmgenet_get_drvinfo, |
980 | .get_link = ethtool_op_get_link, | |
981 | .get_msglevel = bcmgenet_get_msglevel, | |
982 | .set_msglevel = bcmgenet_set_msglevel, | |
06ba8375 FF |
983 | .get_wol = bcmgenet_get_wol, |
984 | .set_wol = bcmgenet_set_wol, | |
6ef398ea FF |
985 | .get_eee = bcmgenet_get_eee, |
986 | .set_eee = bcmgenet_set_eee, | |
016e770d | 987 | .nway_reset = phy_ethtool_nway_reset, |
2f913070 FF |
988 | .get_coalesce = bcmgenet_get_coalesce, |
989 | .set_coalesce = bcmgenet_set_coalesce, | |
fa92bf04 PR |
990 | .get_link_ksettings = bcmgenet_get_link_ksettings, |
991 | .set_link_ksettings = bcmgenet_set_link_ksettings, | |
1c1008c7 FF |
992 | }; |
993 | ||
994 | /* Power down the unimac, based on mode. */ | |
ca8cf341 | 995 | static int bcmgenet_power_down(struct bcmgenet_priv *priv, |
1c1008c7 FF |
996 | enum bcmgenet_power_mode mode) |
997 | { | |
ca8cf341 | 998 | int ret = 0; |
1c1008c7 FF |
999 | u32 reg; |
1000 | ||
1001 | switch (mode) { | |
1002 | case GENET_POWER_CABLE_SENSE: | |
0299b6ac | 1003 | phy_detach(priv->phydev); |
1c1008c7 FF |
1004 | break; |
1005 | ||
c3ae64ae | 1006 | case GENET_POWER_WOL_MAGIC: |
ca8cf341 | 1007 | ret = bcmgenet_wol_power_down_cfg(priv, mode); |
c3ae64ae FF |
1008 | break; |
1009 | ||
1c1008c7 FF |
1010 | case GENET_POWER_PASSIVE: |
1011 | /* Power down LED */ | |
1c1008c7 FF |
1012 | if (priv->hw_params->flags & GENET_HAS_EXT) { |
1013 | reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); | |
1014 | reg |= (EXT_PWR_DOWN_PHY | | |
1015 | EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); | |
1016 | bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); | |
a642c4f7 FF |
1017 | |
1018 | bcmgenet_phy_power_set(priv->dev, false); | |
1c1008c7 FF |
1019 | } |
1020 | break; | |
1021 | default: | |
1022 | break; | |
1023 | } | |
ca8cf341 FF |
1024 | |
1025 | return 0; | |
1c1008c7 FF |
1026 | } |
1027 | ||
1028 | static void bcmgenet_power_up(struct bcmgenet_priv *priv, | |
c91b7f66 | 1029 | enum bcmgenet_power_mode mode) |
1c1008c7 FF |
1030 | { |
1031 | u32 reg; | |
1032 | ||
1033 | if (!(priv->hw_params->flags & GENET_HAS_EXT)) | |
1034 | return; | |
1035 | ||
1036 | reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); | |
1037 | ||
1038 | switch (mode) { | |
1039 | case GENET_POWER_PASSIVE: | |
1040 | reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY | | |
1041 | EXT_PWR_DOWN_BIAS); | |
1042 | /* fallthrough */ | |
1043 | case GENET_POWER_CABLE_SENSE: | |
1044 | /* enable APD */ | |
1045 | reg |= EXT_PWR_DN_EN_LD; | |
1046 | break; | |
c3ae64ae FF |
1047 | case GENET_POWER_WOL_MAGIC: |
1048 | bcmgenet_wol_power_up_cfg(priv, mode); | |
1049 | return; | |
1c1008c7 FF |
1050 | default: |
1051 | break; | |
1052 | } | |
1053 | ||
1054 | bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); | |
5dbebbb4 | 1055 | if (mode == GENET_POWER_PASSIVE) { |
bd4060a6 | 1056 | bcmgenet_phy_power_set(priv->dev, true); |
5dbebbb4 FF |
1057 | bcmgenet_mii_reset(priv->dev); |
1058 | } | |
1c1008c7 FF |
1059 | } |
1060 | ||
1061 | /* ioctl handle special commands that are not present in ethtool. */ | |
1062 | static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1063 | { | |
0299b6ac | 1064 | struct bcmgenet_priv *priv = netdev_priv(dev); |
1c1008c7 FF |
1065 | int val = 0; |
1066 | ||
1067 | if (!netif_running(dev)) | |
1068 | return -EINVAL; | |
1069 | ||
1070 | switch (cmd) { | |
1071 | case SIOCGMIIPHY: | |
1072 | case SIOCGMIIREG: | |
1073 | case SIOCSMIIREG: | |
0299b6ac | 1074 | if (!priv->phydev) |
1c1008c7 FF |
1075 | val = -ENODEV; |
1076 | else | |
0299b6ac | 1077 | val = phy_mii_ioctl(priv->phydev, rq, cmd); |
1c1008c7 FF |
1078 | break; |
1079 | ||
1080 | default: | |
1081 | val = -EINVAL; | |
1082 | break; | |
1083 | } | |
1084 | ||
1085 | return val; | |
1086 | } | |
1087 | ||
1088 | static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, | |
1089 | struct bcmgenet_tx_ring *ring) | |
1090 | { | |
1091 | struct enet_cb *tx_cb_ptr; | |
1092 | ||
1093 | tx_cb_ptr = ring->cbs; | |
1094 | tx_cb_ptr += ring->write_ptr - ring->cb_ptr; | |
014012a4 | 1095 | |
1c1008c7 FF |
1096 | /* Advancing local write pointer */ |
1097 | if (ring->write_ptr == ring->end_ptr) | |
1098 | ring->write_ptr = ring->cb_ptr; | |
1099 | else | |
1100 | ring->write_ptr++; | |
1101 | ||
1102 | return tx_cb_ptr; | |
1103 | } | |
1104 | ||
1105 | /* Simple helper to free a control block's resources */ | |
1106 | static void bcmgenet_free_cb(struct enet_cb *cb) | |
1107 | { | |
1108 | dev_kfree_skb_any(cb->skb); | |
1109 | cb->skb = NULL; | |
1110 | dma_unmap_addr_set(cb, dma_addr, 0); | |
1111 | } | |
1112 | ||
4055eaef PG |
1113 | static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) |
1114 | { | |
ee7d8c20 | 1115 | bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, |
4055eaef PG |
1116 | INTRL2_CPU_MASK_SET); |
1117 | } | |
1118 | ||
1119 | static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) | |
1120 | { | |
ee7d8c20 | 1121 | bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, |
4055eaef PG |
1122 | INTRL2_CPU_MASK_CLEAR); |
1123 | } | |
1124 | ||
1125 | static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) | |
1126 | { | |
1127 | bcmgenet_intrl2_1_writel(ring->priv, | |
1128 | 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), | |
1129 | INTRL2_CPU_MASK_SET); | |
1130 | } | |
1131 | ||
1132 | static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) | |
1133 | { | |
1134 | bcmgenet_intrl2_1_writel(ring->priv, | |
1135 | 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), | |
1136 | INTRL2_CPU_MASK_CLEAR); | |
1137 | } | |
1138 | ||
9dbac28f | 1139 | static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) |
1c1008c7 | 1140 | { |
ee7d8c20 | 1141 | bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, |
c91b7f66 | 1142 | INTRL2_CPU_MASK_SET); |
1c1008c7 FF |
1143 | } |
1144 | ||
9dbac28f | 1145 | static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) |
1c1008c7 | 1146 | { |
ee7d8c20 | 1147 | bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, |
c91b7f66 | 1148 | INTRL2_CPU_MASK_CLEAR); |
1c1008c7 FF |
1149 | } |
1150 | ||
9dbac28f | 1151 | static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) |
1c1008c7 | 1152 | { |
9dbac28f | 1153 | bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, |
c91b7f66 | 1154 | INTRL2_CPU_MASK_CLEAR); |
1c1008c7 FF |
1155 | } |
1156 | ||
9dbac28f | 1157 | static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) |
1c1008c7 | 1158 | { |
9dbac28f | 1159 | bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, |
c91b7f66 | 1160 | INTRL2_CPU_MASK_SET); |
1c1008c7 FF |
1161 | } |
1162 | ||
1163 | /* Unlocked version of the reclaim routine */ | |
4092e6ac JS |
1164 | static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, |
1165 | struct bcmgenet_tx_ring *ring) | |
1c1008c7 FF |
1166 | { |
1167 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
8c4799ac | 1168 | struct device *kdev = &priv->pdev->dev; |
1c1008c7 | 1169 | struct enet_cb *tx_cb_ptr; |
b2cde2cc | 1170 | struct netdev_queue *txq; |
4092e6ac | 1171 | unsigned int pkts_compl = 0; |
55868120 | 1172 | unsigned int bytes_compl = 0; |
1c1008c7 | 1173 | unsigned int c_index; |
66d06757 PG |
1174 | unsigned int txbds_ready; |
1175 | unsigned int txbds_processed = 0; | |
1c1008c7 | 1176 | |
7fc527f9 | 1177 | /* Compute how many buffers are transmitted since last xmit call */ |
c298ede2 DB |
1178 | c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) |
1179 | & DMA_C_INDEX_MASK; | |
1180 | txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; | |
1c1008c7 FF |
1181 | |
1182 | netif_dbg(priv, tx_done, dev, | |
66d06757 PG |
1183 | "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", |
1184 | __func__, ring->index, ring->c_index, c_index, txbds_ready); | |
1c1008c7 FF |
1185 | |
1186 | /* Reclaim transmitted buffers */ | |
66d06757 PG |
1187 | while (txbds_processed < txbds_ready) { |
1188 | tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr]; | |
1c1008c7 | 1189 | if (tx_cb_ptr->skb) { |
4092e6ac | 1190 | pkts_compl++; |
55868120 | 1191 | bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent; |
8c4799ac | 1192 | dma_unmap_single(kdev, |
c91b7f66 | 1193 | dma_unmap_addr(tx_cb_ptr, dma_addr), |
eee57723 | 1194 | dma_unmap_len(tx_cb_ptr, dma_len), |
c91b7f66 | 1195 | DMA_TO_DEVICE); |
1c1008c7 FF |
1196 | bcmgenet_free_cb(tx_cb_ptr); |
1197 | } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) { | |
8c4799ac | 1198 | dma_unmap_page(kdev, |
c91b7f66 FF |
1199 | dma_unmap_addr(tx_cb_ptr, dma_addr), |
1200 | dma_unmap_len(tx_cb_ptr, dma_len), | |
1201 | DMA_TO_DEVICE); | |
1c1008c7 FF |
1202 | dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0); |
1203 | } | |
1c1008c7 | 1204 | |
66d06757 PG |
1205 | txbds_processed++; |
1206 | if (likely(ring->clean_ptr < ring->end_ptr)) | |
1207 | ring->clean_ptr++; | |
1208 | else | |
1209 | ring->clean_ptr = ring->cb_ptr; | |
1c1008c7 FF |
1210 | } |
1211 | ||
66d06757 PG |
1212 | ring->free_bds += txbds_processed; |
1213 | ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK; | |
1214 | ||
55868120 PG |
1215 | dev->stats.tx_packets += pkts_compl; |
1216 | dev->stats.tx_bytes += bytes_compl; | |
1217 | ||
e178c8c2 PG |
1218 | txq = netdev_get_tx_queue(dev, ring->queue); |
1219 | netdev_tx_completed_queue(txq, pkts_compl, bytes_compl); | |
1220 | ||
4092e6ac JS |
1221 | if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { |
1222 | if (netif_tx_queue_stopped(txq)) | |
1223 | netif_tx_wake_queue(txq); | |
1224 | } | |
1c1008c7 | 1225 | |
4092e6ac | 1226 | return pkts_compl; |
1c1008c7 FF |
1227 | } |
1228 | ||
4092e6ac | 1229 | static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, |
c91b7f66 | 1230 | struct bcmgenet_tx_ring *ring) |
1c1008c7 | 1231 | { |
4092e6ac | 1232 | unsigned int released; |
1c1008c7 FF |
1233 | unsigned long flags; |
1234 | ||
1235 | spin_lock_irqsave(&ring->lock, flags); | |
4092e6ac | 1236 | released = __bcmgenet_tx_reclaim(dev, ring); |
1c1008c7 | 1237 | spin_unlock_irqrestore(&ring->lock, flags); |
4092e6ac JS |
1238 | |
1239 | return released; | |
1240 | } | |
1241 | ||
1242 | static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) | |
1243 | { | |
1244 | struct bcmgenet_tx_ring *ring = | |
1245 | container_of(napi, struct bcmgenet_tx_ring, napi); | |
1246 | unsigned int work_done = 0; | |
1247 | ||
1248 | work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring); | |
1249 | ||
1250 | if (work_done == 0) { | |
1251 | napi_complete(napi); | |
9dbac28f | 1252 | ring->int_enable(ring); |
4092e6ac JS |
1253 | |
1254 | return 0; | |
1255 | } | |
1256 | ||
1257 | return budget; | |
1c1008c7 FF |
1258 | } |
1259 | ||
1260 | static void bcmgenet_tx_reclaim_all(struct net_device *dev) | |
1261 | { | |
1262 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
1263 | int i; | |
1264 | ||
1265 | if (netif_is_multiqueue(dev)) { | |
1266 | for (i = 0; i < priv->hw_params->tx_queues; i++) | |
1267 | bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); | |
1268 | } | |
1269 | ||
1270 | bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); | |
1271 | } | |
1272 | ||
1273 | /* Transmits a single SKB (either head of a fragment or a single SKB) | |
1274 | * caller must hold priv->lock | |
1275 | */ | |
1276 | static int bcmgenet_xmit_single(struct net_device *dev, | |
1277 | struct sk_buff *skb, | |
1278 | u16 dma_desc_flags, | |
1279 | struct bcmgenet_tx_ring *ring) | |
1280 | { | |
1281 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
1282 | struct device *kdev = &priv->pdev->dev; | |
1283 | struct enet_cb *tx_cb_ptr; | |
1284 | unsigned int skb_len; | |
1285 | dma_addr_t mapping; | |
1286 | u32 length_status; | |
1287 | int ret; | |
1288 | ||
1289 | tx_cb_ptr = bcmgenet_get_txcb(priv, ring); | |
1290 | ||
1291 | if (unlikely(!tx_cb_ptr)) | |
1292 | BUG(); | |
1293 | ||
1294 | tx_cb_ptr->skb = skb; | |
1295 | ||
7dd39913 | 1296 | skb_len = skb_headlen(skb); |
1c1008c7 FF |
1297 | |
1298 | mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); | |
1299 | ret = dma_mapping_error(kdev, mapping); | |
1300 | if (ret) { | |
44c8bc3c | 1301 | priv->mib.tx_dma_failed++; |
1c1008c7 FF |
1302 | netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); |
1303 | dev_kfree_skb(skb); | |
1304 | return ret; | |
1305 | } | |
1306 | ||
1307 | dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); | |
eee57723 | 1308 | dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len); |
1c1008c7 FF |
1309 | length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags | |
1310 | (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) | | |
1311 | DMA_TX_APPEND_CRC; | |
1312 | ||
1313 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
1314 | length_status |= DMA_TX_DO_CSUM; | |
1315 | ||
1316 | dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status); | |
1317 | ||
1c1008c7 FF |
1318 | return 0; |
1319 | } | |
1320 | ||
7fc527f9 | 1321 | /* Transmit a SKB fragment */ |
1c1008c7 | 1322 | static int bcmgenet_xmit_frag(struct net_device *dev, |
c91b7f66 FF |
1323 | skb_frag_t *frag, |
1324 | u16 dma_desc_flags, | |
1325 | struct bcmgenet_tx_ring *ring) | |
1c1008c7 FF |
1326 | { |
1327 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
1328 | struct device *kdev = &priv->pdev->dev; | |
1329 | struct enet_cb *tx_cb_ptr; | |
824ba603 | 1330 | unsigned int frag_size; |
1c1008c7 FF |
1331 | dma_addr_t mapping; |
1332 | int ret; | |
1333 | ||
1334 | tx_cb_ptr = bcmgenet_get_txcb(priv, ring); | |
1335 | ||
1336 | if (unlikely(!tx_cb_ptr)) | |
1337 | BUG(); | |
824ba603 | 1338 | |
1c1008c7 FF |
1339 | tx_cb_ptr->skb = NULL; |
1340 | ||
824ba603 PG |
1341 | frag_size = skb_frag_size(frag); |
1342 | ||
1343 | mapping = skb_frag_dma_map(kdev, frag, 0, frag_size, DMA_TO_DEVICE); | |
1c1008c7 FF |
1344 | ret = dma_mapping_error(kdev, mapping); |
1345 | if (ret) { | |
44c8bc3c | 1346 | priv->mib.tx_dma_failed++; |
1c1008c7 | 1347 | netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n", |
c91b7f66 | 1348 | __func__); |
1c1008c7 FF |
1349 | return ret; |
1350 | } | |
1351 | ||
1352 | dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); | |
824ba603 | 1353 | dma_unmap_len_set(tx_cb_ptr, dma_len, frag_size); |
1c1008c7 FF |
1354 | |
1355 | dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, | |
824ba603 | 1356 | (frag_size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags | |
c91b7f66 | 1357 | (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT)); |
1c1008c7 | 1358 | |
1c1008c7 FF |
1359 | return 0; |
1360 | } | |
1361 | ||
1362 | /* Reallocate the SKB to put enough headroom in front of it and insert | |
1363 | * the transmit checksum offsets in the descriptors | |
1364 | */ | |
bc23333b PG |
1365 | static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev, |
1366 | struct sk_buff *skb) | |
1c1008c7 FF |
1367 | { |
1368 | struct status_64 *status = NULL; | |
1369 | struct sk_buff *new_skb; | |
1370 | u16 offset; | |
1371 | u8 ip_proto; | |
1372 | u16 ip_ver; | |
1373 | u32 tx_csum_info; | |
1374 | ||
1375 | if (unlikely(skb_headroom(skb) < sizeof(*status))) { | |
1376 | /* If 64 byte status block enabled, must make sure skb has | |
1377 | * enough headroom for us to insert 64B status block. | |
1378 | */ | |
1379 | new_skb = skb_realloc_headroom(skb, sizeof(*status)); | |
1380 | dev_kfree_skb(skb); | |
1381 | if (!new_skb) { | |
1c1008c7 | 1382 | dev->stats.tx_dropped++; |
bc23333b | 1383 | return NULL; |
1c1008c7 FF |
1384 | } |
1385 | skb = new_skb; | |
1386 | } | |
1387 | ||
1388 | skb_push(skb, sizeof(*status)); | |
1389 | status = (struct status_64 *)skb->data; | |
1390 | ||
1391 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1392 | ip_ver = htons(skb->protocol); | |
1393 | switch (ip_ver) { | |
1394 | case ETH_P_IP: | |
1395 | ip_proto = ip_hdr(skb)->protocol; | |
1396 | break; | |
1397 | case ETH_P_IPV6: | |
1398 | ip_proto = ipv6_hdr(skb)->nexthdr; | |
1399 | break; | |
1400 | default: | |
bc23333b | 1401 | return skb; |
1c1008c7 FF |
1402 | } |
1403 | ||
1404 | offset = skb_checksum_start_offset(skb) - sizeof(*status); | |
1405 | tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | | |
1406 | (offset + skb->csum_offset); | |
1407 | ||
1408 | /* Set the length valid bit for TCP and UDP and just set | |
1409 | * the special UDP flag for IPv4, else just set to 0. | |
1410 | */ | |
1411 | if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { | |
1412 | tx_csum_info |= STATUS_TX_CSUM_LV; | |
1413 | if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) | |
1414 | tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; | |
8900ea57 | 1415 | } else { |
1c1008c7 | 1416 | tx_csum_info = 0; |
8900ea57 | 1417 | } |
1c1008c7 FF |
1418 | |
1419 | status->tx_csum_info = tx_csum_info; | |
1420 | } | |
1421 | ||
bc23333b | 1422 | return skb; |
1c1008c7 FF |
1423 | } |
1424 | ||
1425 | static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) | |
1426 | { | |
1427 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
1428 | struct bcmgenet_tx_ring *ring = NULL; | |
b2cde2cc | 1429 | struct netdev_queue *txq; |
1c1008c7 FF |
1430 | unsigned long flags = 0; |
1431 | int nr_frags, index; | |
1432 | u16 dma_desc_flags; | |
1433 | int ret; | |
1434 | int i; | |
1435 | ||
1436 | index = skb_get_queue_mapping(skb); | |
1437 | /* Mapping strategy: | |
1438 | * queue_mapping = 0, unclassified, packet xmited through ring16 | |
1439 | * queue_mapping = 1, goes to ring 0. (highest priority queue | |
1440 | * queue_mapping = 2, goes to ring 1. | |
1441 | * queue_mapping = 3, goes to ring 2. | |
1442 | * queue_mapping = 4, goes to ring 3. | |
1443 | */ | |
1444 | if (index == 0) | |
1445 | index = DESC_INDEX; | |
1446 | else | |
1447 | index -= 1; | |
1448 | ||
1c1008c7 | 1449 | ring = &priv->tx_rings[index]; |
b2cde2cc | 1450 | txq = netdev_get_tx_queue(dev, ring->queue); |
1c1008c7 | 1451 | |
f5a9ec20 PG |
1452 | nr_frags = skb_shinfo(skb)->nr_frags; |
1453 | ||
1c1008c7 | 1454 | spin_lock_irqsave(&ring->lock, flags); |
f5a9ec20 PG |
1455 | if (ring->free_bds <= (nr_frags + 1)) { |
1456 | if (!netif_tx_queue_stopped(txq)) { | |
1457 | netif_tx_stop_queue(txq); | |
1458 | netdev_err(dev, | |
1459 | "%s: tx ring %d full when queue %d awake\n", | |
1460 | __func__, index, ring->queue); | |
1461 | } | |
1c1008c7 FF |
1462 | ret = NETDEV_TX_BUSY; |
1463 | goto out; | |
1464 | } | |
1465 | ||
474ea9ca FF |
1466 | if (skb_padto(skb, ETH_ZLEN)) { |
1467 | ret = NETDEV_TX_OK; | |
1468 | goto out; | |
1469 | } | |
1470 | ||
55868120 PG |
1471 | /* Retain how many bytes will be sent on the wire, without TSB inserted |
1472 | * by transmit checksum offload | |
1473 | */ | |
1474 | GENET_CB(skb)->bytes_sent = skb->len; | |
1475 | ||
1c1008c7 FF |
1476 | /* set the SKB transmit checksum */ |
1477 | if (priv->desc_64b_en) { | |
bc23333b PG |
1478 | skb = bcmgenet_put_tx_csum(dev, skb); |
1479 | if (!skb) { | |
1c1008c7 FF |
1480 | ret = NETDEV_TX_OK; |
1481 | goto out; | |
1482 | } | |
1483 | } | |
1484 | ||
1485 | dma_desc_flags = DMA_SOP; | |
1486 | if (nr_frags == 0) | |
1487 | dma_desc_flags |= DMA_EOP; | |
1488 | ||
1489 | /* Transmit single SKB or head of fragment list */ | |
1490 | ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring); | |
1491 | if (ret) { | |
1492 | ret = NETDEV_TX_OK; | |
1493 | goto out; | |
1494 | } | |
1495 | ||
1496 | /* xmit fragment */ | |
1497 | for (i = 0; i < nr_frags; i++) { | |
1498 | ret = bcmgenet_xmit_frag(dev, | |
c91b7f66 FF |
1499 | &skb_shinfo(skb)->frags[i], |
1500 | (i == nr_frags - 1) ? DMA_EOP : 0, | |
1501 | ring); | |
1c1008c7 FF |
1502 | if (ret) { |
1503 | ret = NETDEV_TX_OK; | |
1504 | goto out; | |
1505 | } | |
1506 | } | |
1507 | ||
d03825fb FF |
1508 | skb_tx_timestamp(skb); |
1509 | ||
ae67bf01 FF |
1510 | /* Decrement total BD count and advance our write pointer */ |
1511 | ring->free_bds -= nr_frags + 1; | |
1512 | ring->prod_index += nr_frags + 1; | |
1513 | ring->prod_index &= DMA_P_INDEX_MASK; | |
1514 | ||
e178c8c2 PG |
1515 | netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); |
1516 | ||
4092e6ac | 1517 | if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) |
b2cde2cc | 1518 | netif_tx_stop_queue(txq); |
1c1008c7 | 1519 | |
ddd0ca5d FF |
1520 | if (!skb->xmit_more || netif_xmit_stopped(txq)) |
1521 | /* Packets are ready, update producer index */ | |
1522 | bcmgenet_tdma_ring_writel(priv, ring->index, | |
1523 | ring->prod_index, TDMA_PROD_INDEX); | |
1c1008c7 FF |
1524 | out: |
1525 | spin_unlock_irqrestore(&ring->lock, flags); | |
1526 | ||
1527 | return ret; | |
1528 | } | |
1529 | ||
d6707bec PG |
1530 | static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, |
1531 | struct enet_cb *cb) | |
1c1008c7 FF |
1532 | { |
1533 | struct device *kdev = &priv->pdev->dev; | |
1534 | struct sk_buff *skb; | |
d6707bec | 1535 | struct sk_buff *rx_skb; |
1c1008c7 | 1536 | dma_addr_t mapping; |
1c1008c7 | 1537 | |
d6707bec | 1538 | /* Allocate a new Rx skb */ |
c91b7f66 | 1539 | skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT); |
d6707bec PG |
1540 | if (!skb) { |
1541 | priv->mib.alloc_rx_buff_failed++; | |
1542 | netif_err(priv, rx_err, priv->dev, | |
1543 | "%s: Rx skb allocation failed\n", __func__); | |
1544 | return NULL; | |
1545 | } | |
1c1008c7 | 1546 | |
d6707bec PG |
1547 | /* DMA-map the new Rx skb */ |
1548 | mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, | |
1549 | DMA_FROM_DEVICE); | |
1550 | if (dma_mapping_error(kdev, mapping)) { | |
44c8bc3c | 1551 | priv->mib.rx_dma_failed++; |
d6707bec | 1552 | dev_kfree_skb_any(skb); |
1c1008c7 | 1553 | netif_err(priv, rx_err, priv->dev, |
d6707bec PG |
1554 | "%s: Rx skb DMA mapping failed\n", __func__); |
1555 | return NULL; | |
1c1008c7 FF |
1556 | } |
1557 | ||
d6707bec PG |
1558 | /* Grab the current Rx skb from the ring and DMA-unmap it */ |
1559 | rx_skb = cb->skb; | |
1560 | if (likely(rx_skb)) | |
1561 | dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), | |
1562 | priv->rx_buf_len, DMA_FROM_DEVICE); | |
1563 | ||
1564 | /* Put the new Rx skb on the ring */ | |
1565 | cb->skb = skb; | |
1c1008c7 | 1566 | dma_unmap_addr_set(cb, dma_addr, mapping); |
8ac467e8 | 1567 | dmadesc_set_addr(priv, cb->bd_addr, mapping); |
1c1008c7 | 1568 | |
d6707bec PG |
1569 | /* Return the current Rx skb to caller */ |
1570 | return rx_skb; | |
1c1008c7 FF |
1571 | } |
1572 | ||
1573 | /* bcmgenet_desc_rx - descriptor based rx process. | |
1574 | * this could be called from bottom half, or from NAPI polling method. | |
1575 | */ | |
4055eaef | 1576 | static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, |
1c1008c7 FF |
1577 | unsigned int budget) |
1578 | { | |
4055eaef | 1579 | struct bcmgenet_priv *priv = ring->priv; |
1c1008c7 FF |
1580 | struct net_device *dev = priv->dev; |
1581 | struct enet_cb *cb; | |
1582 | struct sk_buff *skb; | |
1583 | u32 dma_length_status; | |
1584 | unsigned long dma_flag; | |
d6707bec | 1585 | int len; |
1c1008c7 FF |
1586 | unsigned int rxpktprocessed = 0, rxpkttoprocess; |
1587 | unsigned int p_index; | |
d26ea6cc | 1588 | unsigned int discards; |
1c1008c7 FF |
1589 | unsigned int chksum_ok = 0; |
1590 | ||
4055eaef | 1591 | p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); |
d26ea6cc PG |
1592 | |
1593 | discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & | |
1594 | DMA_P_INDEX_DISCARD_CNT_MASK; | |
1595 | if (discards > ring->old_discards) { | |
1596 | discards = discards - ring->old_discards; | |
1597 | dev->stats.rx_missed_errors += discards; | |
1598 | dev->stats.rx_errors += discards; | |
1599 | ring->old_discards += discards; | |
1600 | ||
1601 | /* Clear HW register when we reach 75% of maximum 0xFFFF */ | |
1602 | if (ring->old_discards >= 0xC000) { | |
1603 | ring->old_discards = 0; | |
4055eaef | 1604 | bcmgenet_rdma_ring_writel(priv, ring->index, 0, |
d26ea6cc PG |
1605 | RDMA_PROD_INDEX); |
1606 | } | |
1607 | } | |
1608 | ||
1c1008c7 | 1609 | p_index &= DMA_P_INDEX_MASK; |
c298ede2 | 1610 | rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; |
1c1008c7 FF |
1611 | |
1612 | netif_dbg(priv, rx_status, dev, | |
c91b7f66 | 1613 | "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); |
1c1008c7 FF |
1614 | |
1615 | while ((rxpktprocessed < rxpkttoprocess) && | |
c91b7f66 | 1616 | (rxpktprocessed < budget)) { |
8ac467e8 | 1617 | cb = &priv->rx_cbs[ring->read_ptr]; |
d6707bec | 1618 | skb = bcmgenet_rx_refill(priv, cb); |
b629be5c | 1619 | |
b629be5c FF |
1620 | if (unlikely(!skb)) { |
1621 | dev->stats.rx_dropped++; | |
d6707bec | 1622 | goto next; |
b629be5c FF |
1623 | } |
1624 | ||
1c1008c7 | 1625 | if (!priv->desc_64b_en) { |
c91b7f66 | 1626 | dma_length_status = |
8ac467e8 | 1627 | dmadesc_get_length_status(priv, cb->bd_addr); |
1c1008c7 FF |
1628 | } else { |
1629 | struct status_64 *status; | |
164d4f20 | 1630 | |
1c1008c7 FF |
1631 | status = (struct status_64 *)skb->data; |
1632 | dma_length_status = status->length_status; | |
1633 | } | |
1634 | ||
1635 | /* DMA flags and length are still valid no matter how | |
1636 | * we got the Receive Status Vector (64B RSB or register) | |
1637 | */ | |
1638 | dma_flag = dma_length_status & 0xffff; | |
1639 | len = dma_length_status >> DMA_BUFLENGTH_SHIFT; | |
1640 | ||
1641 | netif_dbg(priv, rx_status, dev, | |
c91b7f66 | 1642 | "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", |
8ac467e8 PG |
1643 | __func__, p_index, ring->c_index, |
1644 | ring->read_ptr, dma_length_status); | |
1c1008c7 | 1645 | |
1c1008c7 FF |
1646 | if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { |
1647 | netif_err(priv, rx_status, dev, | |
c91b7f66 | 1648 | "dropping fragmented packet!\n"); |
1c1008c7 | 1649 | dev->stats.rx_errors++; |
d6707bec PG |
1650 | dev_kfree_skb_any(skb); |
1651 | goto next; | |
1c1008c7 | 1652 | } |
d6707bec | 1653 | |
1c1008c7 FF |
1654 | /* report errors */ |
1655 | if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | | |
1656 | DMA_RX_OV | | |
1657 | DMA_RX_NO | | |
1658 | DMA_RX_LG | | |
1659 | DMA_RX_RXER))) { | |
1660 | netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", | |
c91b7f66 | 1661 | (unsigned int)dma_flag); |
1c1008c7 FF |
1662 | if (dma_flag & DMA_RX_CRC_ERROR) |
1663 | dev->stats.rx_crc_errors++; | |
1664 | if (dma_flag & DMA_RX_OV) | |
1665 | dev->stats.rx_over_errors++; | |
1666 | if (dma_flag & DMA_RX_NO) | |
1667 | dev->stats.rx_frame_errors++; | |
1668 | if (dma_flag & DMA_RX_LG) | |
1669 | dev->stats.rx_length_errors++; | |
1c1008c7 | 1670 | dev->stats.rx_errors++; |
d6707bec PG |
1671 | dev_kfree_skb_any(skb); |
1672 | goto next; | |
1c1008c7 FF |
1673 | } /* error packet */ |
1674 | ||
1675 | chksum_ok = (dma_flag & priv->dma_rx_chk_bit) && | |
c91b7f66 | 1676 | priv->desc_rxchk_en; |
1c1008c7 FF |
1677 | |
1678 | skb_put(skb, len); | |
1679 | if (priv->desc_64b_en) { | |
1680 | skb_pull(skb, 64); | |
1681 | len -= 64; | |
1682 | } | |
1683 | ||
1684 | if (likely(chksum_ok)) | |
1685 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1686 | ||
1687 | /* remove hardware 2bytes added for IP alignment */ | |
1688 | skb_pull(skb, 2); | |
1689 | len -= 2; | |
1690 | ||
1691 | if (priv->crc_fwd_en) { | |
1692 | skb_trim(skb, len - ETH_FCS_LEN); | |
1693 | len -= ETH_FCS_LEN; | |
1694 | } | |
1695 | ||
1696 | /*Finish setting up the received SKB and send it to the kernel*/ | |
1697 | skb->protocol = eth_type_trans(skb, priv->dev); | |
1698 | dev->stats.rx_packets++; | |
1699 | dev->stats.rx_bytes += len; | |
1700 | if (dma_flag & DMA_RX_MULT) | |
1701 | dev->stats.multicast++; | |
1702 | ||
1703 | /* Notify kernel */ | |
4055eaef | 1704 | napi_gro_receive(&ring->napi, skb); |
1c1008c7 FF |
1705 | netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); |
1706 | ||
d6707bec | 1707 | next: |
cf377d88 | 1708 | rxpktprocessed++; |
8ac467e8 PG |
1709 | if (likely(ring->read_ptr < ring->end_ptr)) |
1710 | ring->read_ptr++; | |
1711 | else | |
1712 | ring->read_ptr = ring->cb_ptr; | |
1713 | ||
1714 | ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; | |
4055eaef | 1715 | bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); |
1c1008c7 FF |
1716 | } |
1717 | ||
1718 | return rxpktprocessed; | |
1719 | } | |
1720 | ||
3ab11339 PG |
1721 | /* Rx NAPI polling method */ |
1722 | static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) | |
1723 | { | |
4055eaef PG |
1724 | struct bcmgenet_rx_ring *ring = container_of(napi, |
1725 | struct bcmgenet_rx_ring, napi); | |
3ab11339 PG |
1726 | unsigned int work_done; |
1727 | ||
4055eaef | 1728 | work_done = bcmgenet_desc_rx(ring, budget); |
3ab11339 PG |
1729 | |
1730 | if (work_done < budget) { | |
eb96ce01 | 1731 | napi_complete_done(napi, work_done); |
4055eaef | 1732 | ring->int_enable(ring); |
3ab11339 PG |
1733 | } |
1734 | ||
1735 | return work_done; | |
1736 | } | |
1737 | ||
1c1008c7 | 1738 | /* Assign skb to RX DMA descriptor. */ |
8ac467e8 PG |
1739 | static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, |
1740 | struct bcmgenet_rx_ring *ring) | |
1c1008c7 FF |
1741 | { |
1742 | struct enet_cb *cb; | |
d6707bec | 1743 | struct sk_buff *skb; |
1c1008c7 FF |
1744 | int i; |
1745 | ||
8ac467e8 | 1746 | netif_dbg(priv, hw, priv->dev, "%s\n", __func__); |
1c1008c7 FF |
1747 | |
1748 | /* loop here for each buffer needing assign */ | |
8ac467e8 PG |
1749 | for (i = 0; i < ring->size; i++) { |
1750 | cb = ring->cbs + i; | |
d6707bec PG |
1751 | skb = bcmgenet_rx_refill(priv, cb); |
1752 | if (skb) | |
1753 | dev_kfree_skb_any(skb); | |
1754 | if (!cb->skb) | |
1755 | return -ENOMEM; | |
1c1008c7 FF |
1756 | } |
1757 | ||
d6707bec | 1758 | return 0; |
1c1008c7 FF |
1759 | } |
1760 | ||
1761 | static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) | |
1762 | { | |
8c4799ac | 1763 | struct device *kdev = &priv->pdev->dev; |
1c1008c7 FF |
1764 | struct enet_cb *cb; |
1765 | int i; | |
1766 | ||
1767 | for (i = 0; i < priv->num_rx_bds; i++) { | |
1768 | cb = &priv->rx_cbs[i]; | |
1769 | ||
1770 | if (dma_unmap_addr(cb, dma_addr)) { | |
8c4799ac | 1771 | dma_unmap_single(kdev, |
c91b7f66 FF |
1772 | dma_unmap_addr(cb, dma_addr), |
1773 | priv->rx_buf_len, DMA_FROM_DEVICE); | |
1c1008c7 FF |
1774 | dma_unmap_addr_set(cb, dma_addr, 0); |
1775 | } | |
1776 | ||
1777 | if (cb->skb) | |
1778 | bcmgenet_free_cb(cb); | |
1779 | } | |
1780 | } | |
1781 | ||
c91b7f66 | 1782 | static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) |
e29585b8 FF |
1783 | { |
1784 | u32 reg; | |
1785 | ||
1786 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); | |
1787 | if (enable) | |
1788 | reg |= mask; | |
1789 | else | |
1790 | reg &= ~mask; | |
1791 | bcmgenet_umac_writel(priv, reg, UMAC_CMD); | |
1792 | ||
1793 | /* UniMAC stops on a packet boundary, wait for a full-size packet | |
1794 | * to be processed | |
1795 | */ | |
1796 | if (enable == 0) | |
1797 | usleep_range(1000, 2000); | |
1798 | } | |
1799 | ||
1c1008c7 FF |
1800 | static int reset_umac(struct bcmgenet_priv *priv) |
1801 | { | |
1802 | struct device *kdev = &priv->pdev->dev; | |
1803 | unsigned int timeout = 0; | |
1804 | u32 reg; | |
1805 | ||
1806 | /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ | |
1807 | bcmgenet_rbuf_ctrl_set(priv, 0); | |
1808 | udelay(10); | |
1809 | ||
1810 | /* disable MAC while updating its registers */ | |
1811 | bcmgenet_umac_writel(priv, 0, UMAC_CMD); | |
1812 | ||
1813 | /* issue soft reset, wait for it to complete */ | |
1814 | bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); | |
1815 | while (timeout++ < 1000) { | |
1816 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); | |
1817 | if (!(reg & CMD_SW_RESET)) | |
1818 | return 0; | |
1819 | ||
1820 | udelay(1); | |
1821 | } | |
1822 | ||
1823 | if (timeout == 1000) { | |
1824 | dev_err(kdev, | |
7fc527f9 | 1825 | "timeout waiting for MAC to come out of reset\n"); |
1c1008c7 FF |
1826 | return -ETIMEDOUT; |
1827 | } | |
1828 | ||
1829 | return 0; | |
1830 | } | |
1831 | ||
909ff5ef FF |
1832 | static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) |
1833 | { | |
1834 | /* Mask all interrupts.*/ | |
1835 | bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); | |
1836 | bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); | |
909ff5ef FF |
1837 | bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); |
1838 | bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); | |
909ff5ef FF |
1839 | } |
1840 | ||
37850e37 FF |
1841 | static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) |
1842 | { | |
1843 | u32 int0_enable = 0; | |
1844 | ||
1845 | /* Monitor cable plug/unplugged event for internal PHY, external PHY | |
1846 | * and MoCA PHY | |
1847 | */ | |
1848 | if (priv->internal_phy) { | |
1849 | int0_enable |= UMAC_IRQ_LINK_EVENT; | |
1850 | } else if (priv->ext_phy) { | |
1851 | int0_enable |= UMAC_IRQ_LINK_EVENT; | |
1852 | } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { | |
1853 | if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) | |
1854 | int0_enable |= UMAC_IRQ_LINK_EVENT; | |
1855 | } | |
1856 | bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); | |
1857 | } | |
1858 | ||
1c1008c7 FF |
1859 | static int init_umac(struct bcmgenet_priv *priv) |
1860 | { | |
1861 | struct device *kdev = &priv->pdev->dev; | |
1862 | int ret; | |
b2e97eca PG |
1863 | u32 reg; |
1864 | u32 int0_enable = 0; | |
1c1008c7 FF |
1865 | |
1866 | dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); | |
1867 | ||
1868 | ret = reset_umac(priv); | |
1869 | if (ret) | |
1870 | return ret; | |
1871 | ||
1872 | bcmgenet_umac_writel(priv, 0, UMAC_CMD); | |
1873 | /* clear tx/rx counter */ | |
1874 | bcmgenet_umac_writel(priv, | |
c91b7f66 FF |
1875 | MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, |
1876 | UMAC_MIB_CTRL); | |
1c1008c7 FF |
1877 | bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); |
1878 | ||
1879 | bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); | |
1880 | ||
1881 | /* init rx registers, enable ip header optimization */ | |
1882 | reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); | |
1883 | reg |= RBUF_ALIGN_2B; | |
1884 | bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); | |
1885 | ||
1886 | if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) | |
1887 | bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); | |
1888 | ||
909ff5ef | 1889 | bcmgenet_intr_disable(priv); |
1c1008c7 | 1890 | |
37850e37 FF |
1891 | /* Configure backpressure vectors for MoCA */ |
1892 | if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { | |
1c1008c7 FF |
1893 | reg = bcmgenet_bp_mc_get(priv); |
1894 | reg |= BIT(priv->hw_params->bp_in_en_shift); | |
1895 | ||
1896 | /* bp_mask: back pressure mask */ | |
1897 | if (netif_is_multiqueue(priv->dev)) | |
1898 | reg |= priv->hw_params->bp_in_mask; | |
1899 | else | |
1900 | reg &= ~priv->hw_params->bp_in_mask; | |
1901 | bcmgenet_bp_mc_set(priv, reg); | |
1902 | } | |
1903 | ||
1904 | /* Enable MDIO interrupts on GENET v3+ */ | |
1905 | if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) | |
b2e97eca | 1906 | int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); |
1c1008c7 | 1907 | |
b2e97eca | 1908 | bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); |
4092e6ac | 1909 | |
1c1008c7 FF |
1910 | dev_dbg(kdev, "done init umac\n"); |
1911 | ||
1912 | return 0; | |
1913 | } | |
1914 | ||
4f8b2d7d | 1915 | /* Initialize a Tx ring along with corresponding hardware registers */ |
1c1008c7 FF |
1916 | static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, |
1917 | unsigned int index, unsigned int size, | |
4f8b2d7d | 1918 | unsigned int start_ptr, unsigned int end_ptr) |
1c1008c7 FF |
1919 | { |
1920 | struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; | |
1921 | u32 words_per_bd = WORDS_PER_BD(priv); | |
1922 | u32 flow_period_val = 0; | |
1c1008c7 FF |
1923 | |
1924 | spin_lock_init(&ring->lock); | |
4092e6ac | 1925 | ring->priv = priv; |
1c1008c7 FF |
1926 | ring->index = index; |
1927 | if (index == DESC_INDEX) { | |
1928 | ring->queue = 0; | |
1929 | ring->int_enable = bcmgenet_tx_ring16_int_enable; | |
1930 | ring->int_disable = bcmgenet_tx_ring16_int_disable; | |
1931 | } else { | |
1932 | ring->queue = index + 1; | |
1933 | ring->int_enable = bcmgenet_tx_ring_int_enable; | |
1934 | ring->int_disable = bcmgenet_tx_ring_int_disable; | |
1935 | } | |
4f8b2d7d | 1936 | ring->cbs = priv->tx_cbs + start_ptr; |
1c1008c7 | 1937 | ring->size = size; |
66d06757 | 1938 | ring->clean_ptr = start_ptr; |
1c1008c7 FF |
1939 | ring->c_index = 0; |
1940 | ring->free_bds = size; | |
4f8b2d7d PG |
1941 | ring->write_ptr = start_ptr; |
1942 | ring->cb_ptr = start_ptr; | |
1c1008c7 FF |
1943 | ring->end_ptr = end_ptr - 1; |
1944 | ring->prod_index = 0; | |
1945 | ||
1946 | /* Set flow period for ring != 16 */ | |
1947 | if (index != DESC_INDEX) | |
1948 | flow_period_val = ENET_MAX_MTU_SIZE << 16; | |
1949 | ||
1950 | bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); | |
1951 | bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); | |
1952 | bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); | |
1953 | /* Disable rate control for now */ | |
1954 | bcmgenet_tdma_ring_writel(priv, index, flow_period_val, | |
c91b7f66 | 1955 | TDMA_FLOW_PERIOD); |
1c1008c7 | 1956 | bcmgenet_tdma_ring_writel(priv, index, |
c91b7f66 FF |
1957 | ((size << DMA_RING_SIZE_SHIFT) | |
1958 | RX_BUF_LENGTH), DMA_RING_BUF_SIZE); | |
1c1008c7 | 1959 | |
1c1008c7 | 1960 | /* Set start and end address, read and write pointers */ |
4f8b2d7d | 1961 | bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, |
c91b7f66 | 1962 | DMA_START_ADDR); |
4f8b2d7d | 1963 | bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, |
c91b7f66 | 1964 | TDMA_READ_PTR); |
4f8b2d7d | 1965 | bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, |
c91b7f66 | 1966 | TDMA_WRITE_PTR); |
1c1008c7 | 1967 | bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, |
c91b7f66 | 1968 | DMA_END_ADDR); |
1c1008c7 FF |
1969 | } |
1970 | ||
1971 | /* Initialize a RDMA ring */ | |
1972 | static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, | |
8ac467e8 PG |
1973 | unsigned int index, unsigned int size, |
1974 | unsigned int start_ptr, unsigned int end_ptr) | |
1c1008c7 | 1975 | { |
8ac467e8 | 1976 | struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; |
1c1008c7 FF |
1977 | u32 words_per_bd = WORDS_PER_BD(priv); |
1978 | int ret; | |
1979 | ||
4055eaef | 1980 | ring->priv = priv; |
8ac467e8 | 1981 | ring->index = index; |
4055eaef PG |
1982 | if (index == DESC_INDEX) { |
1983 | ring->int_enable = bcmgenet_rx_ring16_int_enable; | |
1984 | ring->int_disable = bcmgenet_rx_ring16_int_disable; | |
1985 | } else { | |
1986 | ring->int_enable = bcmgenet_rx_ring_int_enable; | |
1987 | ring->int_disable = bcmgenet_rx_ring_int_disable; | |
1988 | } | |
8ac467e8 PG |
1989 | ring->cbs = priv->rx_cbs + start_ptr; |
1990 | ring->size = size; | |
1991 | ring->c_index = 0; | |
1992 | ring->read_ptr = start_ptr; | |
1993 | ring->cb_ptr = start_ptr; | |
1994 | ring->end_ptr = end_ptr - 1; | |
1c1008c7 | 1995 | |
8ac467e8 PG |
1996 | ret = bcmgenet_alloc_rx_buffers(priv, ring); |
1997 | if (ret) | |
1c1008c7 | 1998 | return ret; |
1c1008c7 | 1999 | |
1c1008c7 FF |
2000 | bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); |
2001 | bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); | |
6f5a272c | 2002 | bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); |
1c1008c7 | 2003 | bcmgenet_rdma_ring_writel(priv, index, |
c91b7f66 FF |
2004 | ((size << DMA_RING_SIZE_SHIFT) | |
2005 | RX_BUF_LENGTH), DMA_RING_BUF_SIZE); | |
1c1008c7 | 2006 | bcmgenet_rdma_ring_writel(priv, index, |
c91b7f66 FF |
2007 | (DMA_FC_THRESH_LO << |
2008 | DMA_XOFF_THRESHOLD_SHIFT) | | |
2009 | DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); | |
6f5a272c PG |
2010 | |
2011 | /* Set start and end address, read and write pointers */ | |
8ac467e8 PG |
2012 | bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, |
2013 | DMA_START_ADDR); | |
2014 | bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, | |
2015 | RDMA_READ_PTR); | |
2016 | bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, | |
2017 | RDMA_WRITE_PTR); | |
2018 | bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, | |
6f5a272c | 2019 | DMA_END_ADDR); |
1c1008c7 FF |
2020 | |
2021 | return ret; | |
2022 | } | |
2023 | ||
e2aadb4a PG |
2024 | static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv) |
2025 | { | |
2026 | unsigned int i; | |
2027 | struct bcmgenet_tx_ring *ring; | |
2028 | ||
2029 | for (i = 0; i < priv->hw_params->tx_queues; ++i) { | |
2030 | ring = &priv->tx_rings[i]; | |
d64b5e85 | 2031 | netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); |
e2aadb4a PG |
2032 | } |
2033 | ||
2034 | ring = &priv->tx_rings[DESC_INDEX]; | |
d64b5e85 | 2035 | netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); |
e2aadb4a PG |
2036 | } |
2037 | ||
2038 | static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) | |
2039 | { | |
2040 | unsigned int i; | |
6689da15 DB |
2041 | u32 int0_enable = UMAC_IRQ_TXDMA_DONE; |
2042 | u32 int1_enable = 0; | |
e2aadb4a PG |
2043 | struct bcmgenet_tx_ring *ring; |
2044 | ||
2045 | for (i = 0; i < priv->hw_params->tx_queues; ++i) { | |
2046 | ring = &priv->tx_rings[i]; | |
2047 | napi_enable(&ring->napi); | |
6689da15 | 2048 | int1_enable |= (1 << i); |
e2aadb4a PG |
2049 | } |
2050 | ||
2051 | ring = &priv->tx_rings[DESC_INDEX]; | |
2052 | napi_enable(&ring->napi); | |
6689da15 DB |
2053 | |
2054 | bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); | |
2055 | bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); | |
e2aadb4a PG |
2056 | } |
2057 | ||
2058 | static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) | |
2059 | { | |
2060 | unsigned int i; | |
6689da15 DB |
2061 | u32 int0_disable = UMAC_IRQ_TXDMA_DONE; |
2062 | u32 int1_disable = 0xffff; | |
e2aadb4a PG |
2063 | struct bcmgenet_tx_ring *ring; |
2064 | ||
6689da15 DB |
2065 | bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET); |
2066 | bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET); | |
2067 | ||
e2aadb4a PG |
2068 | for (i = 0; i < priv->hw_params->tx_queues; ++i) { |
2069 | ring = &priv->tx_rings[i]; | |
2070 | napi_disable(&ring->napi); | |
2071 | } | |
2072 | ||
2073 | ring = &priv->tx_rings[DESC_INDEX]; | |
2074 | napi_disable(&ring->napi); | |
2075 | } | |
2076 | ||
2077 | static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) | |
2078 | { | |
2079 | unsigned int i; | |
2080 | struct bcmgenet_tx_ring *ring; | |
2081 | ||
2082 | for (i = 0; i < priv->hw_params->tx_queues; ++i) { | |
2083 | ring = &priv->tx_rings[i]; | |
2084 | netif_napi_del(&ring->napi); | |
2085 | } | |
2086 | ||
2087 | ring = &priv->tx_rings[DESC_INDEX]; | |
2088 | netif_napi_del(&ring->napi); | |
2089 | } | |
2090 | ||
16c6d667 | 2091 | /* Initialize Tx queues |
1c1008c7 | 2092 | * |
16c6d667 | 2093 | * Queues 0-3 are priority-based, each one has 32 descriptors, |
1c1008c7 FF |
2094 | * with queue 0 being the highest priority queue. |
2095 | * | |
16c6d667 | 2096 | * Queue 16 is the default Tx queue with |
51a966a7 | 2097 | * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. |
1c1008c7 | 2098 | * |
16c6d667 PG |
2099 | * The transmit control block pool is then partitioned as follows: |
2100 | * - Tx queue 0 uses tx_cbs[0..31] | |
2101 | * - Tx queue 1 uses tx_cbs[32..63] | |
2102 | * - Tx queue 2 uses tx_cbs[64..95] | |
2103 | * - Tx queue 3 uses tx_cbs[96..127] | |
2104 | * - Tx queue 16 uses tx_cbs[128..255] | |
1c1008c7 | 2105 | */ |
16c6d667 | 2106 | static void bcmgenet_init_tx_queues(struct net_device *dev) |
1c1008c7 FF |
2107 | { |
2108 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
16c6d667 PG |
2109 | u32 i, dma_enable; |
2110 | u32 dma_ctrl, ring_cfg; | |
37742166 | 2111 | u32 dma_priority[3] = {0, 0, 0}; |
1c1008c7 | 2112 | |
1c1008c7 FF |
2113 | dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); |
2114 | dma_enable = dma_ctrl & DMA_EN; | |
2115 | dma_ctrl &= ~DMA_EN; | |
2116 | bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); | |
2117 | ||
16c6d667 PG |
2118 | dma_ctrl = 0; |
2119 | ring_cfg = 0; | |
2120 | ||
1c1008c7 FF |
2121 | /* Enable strict priority arbiter mode */ |
2122 | bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); | |
2123 | ||
16c6d667 | 2124 | /* Initialize Tx priority queues */ |
1c1008c7 | 2125 | for (i = 0; i < priv->hw_params->tx_queues; i++) { |
51a966a7 PG |
2126 | bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, |
2127 | i * priv->hw_params->tx_bds_per_q, | |
2128 | (i + 1) * priv->hw_params->tx_bds_per_q); | |
16c6d667 PG |
2129 | ring_cfg |= (1 << i); |
2130 | dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); | |
37742166 PG |
2131 | dma_priority[DMA_PRIO_REG_INDEX(i)] |= |
2132 | ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); | |
1c1008c7 FF |
2133 | } |
2134 | ||
16c6d667 | 2135 | /* Initialize Tx default queue 16 */ |
51a966a7 | 2136 | bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, |
16c6d667 | 2137 | priv->hw_params->tx_queues * |
51a966a7 | 2138 | priv->hw_params->tx_bds_per_q, |
16c6d667 PG |
2139 | TOTAL_DESC); |
2140 | ring_cfg |= (1 << DESC_INDEX); | |
2141 | dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); | |
37742166 PG |
2142 | dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= |
2143 | ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << | |
2144 | DMA_PRIO_REG_SHIFT(DESC_INDEX)); | |
16c6d667 PG |
2145 | |
2146 | /* Set Tx queue priorities */ | |
37742166 PG |
2147 | bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); |
2148 | bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); | |
2149 | bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); | |
2150 | ||
e2aadb4a PG |
2151 | /* Initialize Tx NAPI */ |
2152 | bcmgenet_init_tx_napi(priv); | |
2153 | ||
16c6d667 PG |
2154 | /* Enable Tx queues */ |
2155 | bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); | |
1c1008c7 | 2156 | |
16c6d667 | 2157 | /* Enable Tx DMA */ |
1c1008c7 | 2158 | if (dma_enable) |
16c6d667 PG |
2159 | dma_ctrl |= DMA_EN; |
2160 | bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); | |
1c1008c7 FF |
2161 | } |
2162 | ||
3ab11339 PG |
2163 | static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv) |
2164 | { | |
4055eaef PG |
2165 | unsigned int i; |
2166 | struct bcmgenet_rx_ring *ring; | |
2167 | ||
2168 | for (i = 0; i < priv->hw_params->rx_queues; ++i) { | |
2169 | ring = &priv->rx_rings[i]; | |
2170 | netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64); | |
2171 | } | |
2172 | ||
2173 | ring = &priv->rx_rings[DESC_INDEX]; | |
2174 | netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64); | |
3ab11339 PG |
2175 | } |
2176 | ||
2177 | static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) | |
2178 | { | |
4055eaef | 2179 | unsigned int i; |
6689da15 DB |
2180 | u32 int0_enable = UMAC_IRQ_RXDMA_DONE; |
2181 | u32 int1_enable = 0; | |
4055eaef PG |
2182 | struct bcmgenet_rx_ring *ring; |
2183 | ||
2184 | for (i = 0; i < priv->hw_params->rx_queues; ++i) { | |
2185 | ring = &priv->rx_rings[i]; | |
2186 | napi_enable(&ring->napi); | |
6689da15 | 2187 | int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i)); |
4055eaef PG |
2188 | } |
2189 | ||
2190 | ring = &priv->rx_rings[DESC_INDEX]; | |
2191 | napi_enable(&ring->napi); | |
6689da15 DB |
2192 | |
2193 | bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); | |
2194 | bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); | |
3ab11339 PG |
2195 | } |
2196 | ||
2197 | static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) | |
2198 | { | |
4055eaef | 2199 | unsigned int i; |
6689da15 DB |
2200 | u32 int0_disable = UMAC_IRQ_RXDMA_DONE; |
2201 | u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT; | |
4055eaef PG |
2202 | struct bcmgenet_rx_ring *ring; |
2203 | ||
6689da15 DB |
2204 | bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET); |
2205 | bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET); | |
2206 | ||
4055eaef PG |
2207 | for (i = 0; i < priv->hw_params->rx_queues; ++i) { |
2208 | ring = &priv->rx_rings[i]; | |
2209 | napi_disable(&ring->napi); | |
2210 | } | |
2211 | ||
2212 | ring = &priv->rx_rings[DESC_INDEX]; | |
2213 | napi_disable(&ring->napi); | |
3ab11339 PG |
2214 | } |
2215 | ||
2216 | static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) | |
2217 | { | |
4055eaef PG |
2218 | unsigned int i; |
2219 | struct bcmgenet_rx_ring *ring; | |
2220 | ||
2221 | for (i = 0; i < priv->hw_params->rx_queues; ++i) { | |
2222 | ring = &priv->rx_rings[i]; | |
2223 | netif_napi_del(&ring->napi); | |
2224 | } | |
2225 | ||
2226 | ring = &priv->rx_rings[DESC_INDEX]; | |
2227 | netif_napi_del(&ring->napi); | |
3ab11339 PG |
2228 | } |
2229 | ||
8ac467e8 PG |
2230 | /* Initialize Rx queues |
2231 | * | |
2232 | * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be | |
2233 | * used to direct traffic to these queues. | |
2234 | * | |
2235 | * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. | |
2236 | */ | |
2237 | static int bcmgenet_init_rx_queues(struct net_device *dev) | |
2238 | { | |
2239 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2240 | u32 i; | |
2241 | u32 dma_enable; | |
2242 | u32 dma_ctrl; | |
2243 | u32 ring_cfg; | |
2244 | int ret; | |
2245 | ||
2246 | dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); | |
2247 | dma_enable = dma_ctrl & DMA_EN; | |
2248 | dma_ctrl &= ~DMA_EN; | |
2249 | bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); | |
2250 | ||
2251 | dma_ctrl = 0; | |
2252 | ring_cfg = 0; | |
2253 | ||
2254 | /* Initialize Rx priority queues */ | |
2255 | for (i = 0; i < priv->hw_params->rx_queues; i++) { | |
2256 | ret = bcmgenet_init_rx_ring(priv, i, | |
2257 | priv->hw_params->rx_bds_per_q, | |
2258 | i * priv->hw_params->rx_bds_per_q, | |
2259 | (i + 1) * | |
2260 | priv->hw_params->rx_bds_per_q); | |
2261 | if (ret) | |
2262 | return ret; | |
2263 | ||
2264 | ring_cfg |= (1 << i); | |
2265 | dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); | |
2266 | } | |
2267 | ||
2268 | /* Initialize Rx default queue 16 */ | |
2269 | ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, | |
2270 | priv->hw_params->rx_queues * | |
2271 | priv->hw_params->rx_bds_per_q, | |
2272 | TOTAL_DESC); | |
2273 | if (ret) | |
2274 | return ret; | |
2275 | ||
2276 | ring_cfg |= (1 << DESC_INDEX); | |
2277 | dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); | |
2278 | ||
3ab11339 PG |
2279 | /* Initialize Rx NAPI */ |
2280 | bcmgenet_init_rx_napi(priv); | |
2281 | ||
8ac467e8 PG |
2282 | /* Enable rings */ |
2283 | bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); | |
2284 | ||
2285 | /* Configure ring as descriptor ring and re-enable DMA if enabled */ | |
2286 | if (dma_enable) | |
2287 | dma_ctrl |= DMA_EN; | |
2288 | bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); | |
2289 | ||
2290 | return 0; | |
2291 | } | |
2292 | ||
4a0c081e FF |
2293 | static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) |
2294 | { | |
2295 | int ret = 0; | |
2296 | int timeout = 0; | |
2297 | u32 reg; | |
b6df7d61 JS |
2298 | u32 dma_ctrl; |
2299 | int i; | |
4a0c081e FF |
2300 | |
2301 | /* Disable TDMA to stop add more frames in TX DMA */ | |
2302 | reg = bcmgenet_tdma_readl(priv, DMA_CTRL); | |
2303 | reg &= ~DMA_EN; | |
2304 | bcmgenet_tdma_writel(priv, reg, DMA_CTRL); | |
2305 | ||
2306 | /* Check TDMA status register to confirm TDMA is disabled */ | |
2307 | while (timeout++ < DMA_TIMEOUT_VAL) { | |
2308 | reg = bcmgenet_tdma_readl(priv, DMA_STATUS); | |
2309 | if (reg & DMA_DISABLED) | |
2310 | break; | |
2311 | ||
2312 | udelay(1); | |
2313 | } | |
2314 | ||
2315 | if (timeout == DMA_TIMEOUT_VAL) { | |
2316 | netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); | |
2317 | ret = -ETIMEDOUT; | |
2318 | } | |
2319 | ||
2320 | /* Wait 10ms for packet drain in both tx and rx dma */ | |
2321 | usleep_range(10000, 20000); | |
2322 | ||
2323 | /* Disable RDMA */ | |
2324 | reg = bcmgenet_rdma_readl(priv, DMA_CTRL); | |
2325 | reg &= ~DMA_EN; | |
2326 | bcmgenet_rdma_writel(priv, reg, DMA_CTRL); | |
2327 | ||
2328 | timeout = 0; | |
2329 | /* Check RDMA status register to confirm RDMA is disabled */ | |
2330 | while (timeout++ < DMA_TIMEOUT_VAL) { | |
2331 | reg = bcmgenet_rdma_readl(priv, DMA_STATUS); | |
2332 | if (reg & DMA_DISABLED) | |
2333 | break; | |
2334 | ||
2335 | udelay(1); | |
2336 | } | |
2337 | ||
2338 | if (timeout == DMA_TIMEOUT_VAL) { | |
2339 | netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); | |
2340 | ret = -ETIMEDOUT; | |
2341 | } | |
2342 | ||
b6df7d61 JS |
2343 | dma_ctrl = 0; |
2344 | for (i = 0; i < priv->hw_params->rx_queues; i++) | |
2345 | dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); | |
2346 | reg = bcmgenet_rdma_readl(priv, DMA_CTRL); | |
2347 | reg &= ~dma_ctrl; | |
2348 | bcmgenet_rdma_writel(priv, reg, DMA_CTRL); | |
2349 | ||
2350 | dma_ctrl = 0; | |
2351 | for (i = 0; i < priv->hw_params->tx_queues; i++) | |
2352 | dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); | |
2353 | reg = bcmgenet_tdma_readl(priv, DMA_CTRL); | |
2354 | reg &= ~dma_ctrl; | |
2355 | bcmgenet_tdma_writel(priv, reg, DMA_CTRL); | |
2356 | ||
4a0c081e FF |
2357 | return ret; |
2358 | } | |
2359 | ||
9abab96d | 2360 | static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) |
1c1008c7 FF |
2361 | { |
2362 | int i; | |
e178c8c2 | 2363 | struct netdev_queue *txq; |
1c1008c7 | 2364 | |
9abab96d PG |
2365 | bcmgenet_fini_rx_napi(priv); |
2366 | bcmgenet_fini_tx_napi(priv); | |
2367 | ||
1c1008c7 | 2368 | /* disable DMA */ |
4a0c081e | 2369 | bcmgenet_dma_teardown(priv); |
1c1008c7 FF |
2370 | |
2371 | for (i = 0; i < priv->num_tx_bds; i++) { | |
2372 | if (priv->tx_cbs[i].skb != NULL) { | |
2373 | dev_kfree_skb(priv->tx_cbs[i].skb); | |
2374 | priv->tx_cbs[i].skb = NULL; | |
2375 | } | |
2376 | } | |
2377 | ||
e178c8c2 PG |
2378 | for (i = 0; i < priv->hw_params->tx_queues; i++) { |
2379 | txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); | |
2380 | netdev_tx_reset_queue(txq); | |
2381 | } | |
2382 | ||
2383 | txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); | |
2384 | netdev_tx_reset_queue(txq); | |
2385 | ||
1c1008c7 FF |
2386 | bcmgenet_free_rx_buffers(priv); |
2387 | kfree(priv->rx_cbs); | |
2388 | kfree(priv->tx_cbs); | |
2389 | } | |
2390 | ||
2391 | /* init_edma: Initialize DMA control register */ | |
2392 | static int bcmgenet_init_dma(struct bcmgenet_priv *priv) | |
2393 | { | |
2394 | int ret; | |
014012a4 PG |
2395 | unsigned int i; |
2396 | struct enet_cb *cb; | |
1c1008c7 | 2397 | |
6f5a272c | 2398 | netif_dbg(priv, hw, priv->dev, "%s\n", __func__); |
1c1008c7 | 2399 | |
6f5a272c PG |
2400 | /* Initialize common Rx ring structures */ |
2401 | priv->rx_bds = priv->base + priv->hw_params->rdma_offset; | |
2402 | priv->num_rx_bds = TOTAL_DESC; | |
2403 | priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), | |
2404 | GFP_KERNEL); | |
2405 | if (!priv->rx_cbs) | |
2406 | return -ENOMEM; | |
2407 | ||
2408 | for (i = 0; i < priv->num_rx_bds; i++) { | |
2409 | cb = priv->rx_cbs + i; | |
2410 | cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; | |
2411 | } | |
2412 | ||
7fc527f9 | 2413 | /* Initialize common TX ring structures */ |
1c1008c7 FF |
2414 | priv->tx_bds = priv->base + priv->hw_params->tdma_offset; |
2415 | priv->num_tx_bds = TOTAL_DESC; | |
c489be08 | 2416 | priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), |
c91b7f66 | 2417 | GFP_KERNEL); |
1c1008c7 | 2418 | if (!priv->tx_cbs) { |
ebbd96fb | 2419 | kfree(priv->rx_cbs); |
1c1008c7 FF |
2420 | return -ENOMEM; |
2421 | } | |
2422 | ||
014012a4 PG |
2423 | for (i = 0; i < priv->num_tx_bds; i++) { |
2424 | cb = priv->tx_cbs + i; | |
2425 | cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; | |
2426 | } | |
2427 | ||
ebbd96fb PG |
2428 | /* Init rDma */ |
2429 | bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); | |
2430 | ||
2431 | /* Initialize Rx queues */ | |
2432 | ret = bcmgenet_init_rx_queues(priv->dev); | |
2433 | if (ret) { | |
2434 | netdev_err(priv->dev, "failed to initialize Rx queues\n"); | |
2435 | bcmgenet_free_rx_buffers(priv); | |
2436 | kfree(priv->rx_cbs); | |
2437 | kfree(priv->tx_cbs); | |
2438 | return ret; | |
2439 | } | |
2440 | ||
2441 | /* Init tDma */ | |
2442 | bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); | |
2443 | ||
16c6d667 PG |
2444 | /* Initialize Tx queues */ |
2445 | bcmgenet_init_tx_queues(priv->dev); | |
1c1008c7 FF |
2446 | |
2447 | return 0; | |
2448 | } | |
2449 | ||
1c1008c7 FF |
2450 | /* Interrupt bottom half */ |
2451 | static void bcmgenet_irq_task(struct work_struct *work) | |
2452 | { | |
2453 | struct bcmgenet_priv *priv = container_of( | |
2454 | work, struct bcmgenet_priv, bcmgenet_irq_work); | |
2455 | ||
2456 | netif_dbg(priv, intr, priv->dev, "%s\n", __func__); | |
2457 | ||
2458 | /* Link UP/DOWN event */ | |
d07c0278 | 2459 | if (priv->irq0_stat & UMAC_IRQ_LINK_EVENT) { |
0299b6ac | 2460 | phy_mac_interrupt(priv->phydev, |
451e1ca2 | 2461 | !!(priv->irq0_stat & UMAC_IRQ_LINK_UP)); |
e122966d | 2462 | priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT; |
1c1008c7 FF |
2463 | } |
2464 | } | |
2465 | ||
4055eaef | 2466 | /* bcmgenet_isr1: handle Rx and Tx priority queues */ |
1c1008c7 FF |
2467 | static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) |
2468 | { | |
2469 | struct bcmgenet_priv *priv = dev_id; | |
4055eaef PG |
2470 | struct bcmgenet_rx_ring *rx_ring; |
2471 | struct bcmgenet_tx_ring *tx_ring; | |
1c1008c7 FF |
2472 | unsigned int index; |
2473 | ||
2474 | /* Save irq status for bottom-half processing. */ | |
2475 | priv->irq1_stat = | |
2476 | bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & | |
4092e6ac | 2477 | ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); |
4055eaef | 2478 | |
7fc527f9 | 2479 | /* clear interrupts */ |
1c1008c7 FF |
2480 | bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); |
2481 | ||
2482 | netif_dbg(priv, intr, priv->dev, | |
c91b7f66 | 2483 | "%s: IRQ=0x%x\n", __func__, priv->irq1_stat); |
4092e6ac | 2484 | |
4055eaef PG |
2485 | /* Check Rx priority queue interrupts */ |
2486 | for (index = 0; index < priv->hw_params->rx_queues; index++) { | |
2487 | if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) | |
2488 | continue; | |
2489 | ||
2490 | rx_ring = &priv->rx_rings[index]; | |
2491 | ||
2492 | if (likely(napi_schedule_prep(&rx_ring->napi))) { | |
2493 | rx_ring->int_disable(rx_ring); | |
dac916f8 | 2494 | __napi_schedule_irqoff(&rx_ring->napi); |
4055eaef PG |
2495 | } |
2496 | } | |
2497 | ||
2498 | /* Check Tx priority queue interrupts */ | |
4092e6ac JS |
2499 | for (index = 0; index < priv->hw_params->tx_queues; index++) { |
2500 | if (!(priv->irq1_stat & BIT(index))) | |
2501 | continue; | |
2502 | ||
4055eaef | 2503 | tx_ring = &priv->tx_rings[index]; |
4092e6ac | 2504 | |
4055eaef PG |
2505 | if (likely(napi_schedule_prep(&tx_ring->napi))) { |
2506 | tx_ring->int_disable(tx_ring); | |
dac916f8 | 2507 | __napi_schedule_irqoff(&tx_ring->napi); |
1c1008c7 FF |
2508 | } |
2509 | } | |
4092e6ac | 2510 | |
1c1008c7 FF |
2511 | return IRQ_HANDLED; |
2512 | } | |
2513 | ||
4055eaef | 2514 | /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ |
1c1008c7 FF |
2515 | static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) |
2516 | { | |
2517 | struct bcmgenet_priv *priv = dev_id; | |
4055eaef PG |
2518 | struct bcmgenet_rx_ring *rx_ring; |
2519 | struct bcmgenet_tx_ring *tx_ring; | |
1c1008c7 FF |
2520 | |
2521 | /* Save irq status for bottom-half processing. */ | |
2522 | priv->irq0_stat = | |
2523 | bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & | |
2524 | ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); | |
4055eaef | 2525 | |
7fc527f9 | 2526 | /* clear interrupts */ |
1c1008c7 FF |
2527 | bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); |
2528 | ||
2529 | netif_dbg(priv, intr, priv->dev, | |
c91b7f66 | 2530 | "IRQ=0x%x\n", priv->irq0_stat); |
1c1008c7 | 2531 | |
ee7d8c20 | 2532 | if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) { |
4055eaef PG |
2533 | rx_ring = &priv->rx_rings[DESC_INDEX]; |
2534 | ||
2535 | if (likely(napi_schedule_prep(&rx_ring->napi))) { | |
2536 | rx_ring->int_disable(rx_ring); | |
dac916f8 | 2537 | __napi_schedule_irqoff(&rx_ring->napi); |
1c1008c7 FF |
2538 | } |
2539 | } | |
4092e6ac | 2540 | |
ee7d8c20 | 2541 | if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) { |
4055eaef PG |
2542 | tx_ring = &priv->tx_rings[DESC_INDEX]; |
2543 | ||
2544 | if (likely(napi_schedule_prep(&tx_ring->napi))) { | |
2545 | tx_ring->int_disable(tx_ring); | |
dac916f8 | 2546 | __napi_schedule_irqoff(&tx_ring->napi); |
4092e6ac | 2547 | } |
1c1008c7 | 2548 | } |
4055eaef | 2549 | |
1c1008c7 FF |
2550 | if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R | |
2551 | UMAC_IRQ_PHY_DET_F | | |
e122966d | 2552 | UMAC_IRQ_LINK_EVENT | |
1c1008c7 | 2553 | UMAC_IRQ_HFB_SM | |
b1ec494d | 2554 | UMAC_IRQ_HFB_MM)) { |
1c1008c7 FF |
2555 | /* all other interested interrupts handled in bottom half */ |
2556 | schedule_work(&priv->bcmgenet_irq_work); | |
2557 | } | |
2558 | ||
2559 | if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && | |
c91b7f66 | 2560 | priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { |
1c1008c7 FF |
2561 | priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); |
2562 | wake_up(&priv->wq); | |
2563 | } | |
2564 | ||
2565 | return IRQ_HANDLED; | |
2566 | } | |
2567 | ||
8562056f FF |
2568 | static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) |
2569 | { | |
2570 | struct bcmgenet_priv *priv = dev_id; | |
2571 | ||
2572 | pm_wakeup_event(&priv->pdev->dev, 0); | |
2573 | ||
2574 | return IRQ_HANDLED; | |
2575 | } | |
2576 | ||
4d2e8882 FF |
2577 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2578 | static void bcmgenet_poll_controller(struct net_device *dev) | |
2579 | { | |
2580 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2581 | ||
2582 | /* Invoke the main RX/TX interrupt handler */ | |
2583 | disable_irq(priv->irq0); | |
2584 | bcmgenet_isr0(priv->irq0, priv); | |
2585 | enable_irq(priv->irq0); | |
2586 | ||
2587 | /* And the interrupt handler for RX/TX priority queues */ | |
2588 | disable_irq(priv->irq1); | |
2589 | bcmgenet_isr1(priv->irq1, priv); | |
2590 | enable_irq(priv->irq1); | |
2591 | } | |
2592 | #endif | |
2593 | ||
1c1008c7 FF |
2594 | static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) |
2595 | { | |
2596 | u32 reg; | |
2597 | ||
2598 | reg = bcmgenet_rbuf_ctrl_get(priv); | |
2599 | reg |= BIT(1); | |
2600 | bcmgenet_rbuf_ctrl_set(priv, reg); | |
2601 | udelay(10); | |
2602 | ||
2603 | reg &= ~BIT(1); | |
2604 | bcmgenet_rbuf_ctrl_set(priv, reg); | |
2605 | udelay(10); | |
2606 | } | |
2607 | ||
2608 | static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, | |
c91b7f66 | 2609 | unsigned char *addr) |
1c1008c7 FF |
2610 | { |
2611 | bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | | |
2612 | (addr[2] << 8) | addr[3], UMAC_MAC0); | |
2613 | bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); | |
2614 | } | |
2615 | ||
1c1008c7 FF |
2616 | /* Returns a reusable dma control register value */ |
2617 | static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) | |
2618 | { | |
2619 | u32 reg; | |
2620 | u32 dma_ctrl; | |
2621 | ||
2622 | /* disable DMA */ | |
2623 | dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; | |
2624 | reg = bcmgenet_tdma_readl(priv, DMA_CTRL); | |
2625 | reg &= ~dma_ctrl; | |
2626 | bcmgenet_tdma_writel(priv, reg, DMA_CTRL); | |
2627 | ||
2628 | reg = bcmgenet_rdma_readl(priv, DMA_CTRL); | |
2629 | reg &= ~dma_ctrl; | |
2630 | bcmgenet_rdma_writel(priv, reg, DMA_CTRL); | |
2631 | ||
2632 | bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); | |
2633 | udelay(10); | |
2634 | bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); | |
2635 | ||
2636 | return dma_ctrl; | |
2637 | } | |
2638 | ||
2639 | static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) | |
2640 | { | |
2641 | u32 reg; | |
2642 | ||
2643 | reg = bcmgenet_rdma_readl(priv, DMA_CTRL); | |
2644 | reg |= dma_ctrl; | |
2645 | bcmgenet_rdma_writel(priv, reg, DMA_CTRL); | |
2646 | ||
2647 | reg = bcmgenet_tdma_readl(priv, DMA_CTRL); | |
2648 | reg |= dma_ctrl; | |
2649 | bcmgenet_tdma_writel(priv, reg, DMA_CTRL); | |
2650 | } | |
2651 | ||
0034de41 PG |
2652 | /* bcmgenet_hfb_clear |
2653 | * | |
2654 | * Clear Hardware Filter Block and disable all filtering. | |
2655 | */ | |
2656 | static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) | |
2657 | { | |
2658 | u32 i; | |
2659 | ||
2660 | bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); | |
2661 | bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); | |
2662 | bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); | |
2663 | ||
2664 | for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) | |
2665 | bcmgenet_rdma_writel(priv, 0x0, i); | |
2666 | ||
2667 | for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) | |
2668 | bcmgenet_hfb_reg_writel(priv, 0x0, | |
2669 | HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); | |
2670 | ||
2671 | for (i = 0; i < priv->hw_params->hfb_filter_cnt * | |
2672 | priv->hw_params->hfb_filter_size; i++) | |
2673 | bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); | |
2674 | } | |
2675 | ||
2676 | static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) | |
2677 | { | |
2678 | if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) | |
2679 | return; | |
2680 | ||
2681 | bcmgenet_hfb_clear(priv); | |
2682 | } | |
2683 | ||
909ff5ef FF |
2684 | static void bcmgenet_netif_start(struct net_device *dev) |
2685 | { | |
2686 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2687 | ||
2688 | /* Start the network engine */ | |
3ab11339 | 2689 | bcmgenet_enable_rx_napi(priv); |
e2aadb4a | 2690 | bcmgenet_enable_tx_napi(priv); |
909ff5ef FF |
2691 | |
2692 | umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); | |
2693 | ||
909ff5ef FF |
2694 | netif_tx_start_all_queues(dev); |
2695 | ||
37850e37 FF |
2696 | /* Monitor link interrupts now */ |
2697 | bcmgenet_link_intr_enable(priv); | |
2698 | ||
0299b6ac | 2699 | phy_start(priv->phydev); |
909ff5ef FF |
2700 | } |
2701 | ||
1c1008c7 FF |
2702 | static int bcmgenet_open(struct net_device *dev) |
2703 | { | |
2704 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2705 | unsigned long dma_ctrl; | |
2706 | u32 reg; | |
2707 | int ret; | |
2708 | ||
2709 | netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); | |
2710 | ||
2711 | /* Turn on the clock */ | |
7d5d3075 | 2712 | clk_prepare_enable(priv->clk); |
1c1008c7 | 2713 | |
a642c4f7 FF |
2714 | /* If this is an internal GPHY, power it back on now, before UniMAC is |
2715 | * brought out of reset as absolutely no UniMAC activity is allowed | |
2716 | */ | |
c624f891 | 2717 | if (priv->internal_phy) |
a642c4f7 FF |
2718 | bcmgenet_power_up(priv, GENET_POWER_PASSIVE); |
2719 | ||
1c1008c7 FF |
2720 | /* take MAC out of reset */ |
2721 | bcmgenet_umac_reset(priv); | |
2722 | ||
2723 | ret = init_umac(priv); | |
2724 | if (ret) | |
2725 | goto err_clk_disable; | |
2726 | ||
2727 | /* disable ethernet MAC while updating its registers */ | |
e29585b8 | 2728 | umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); |
1c1008c7 | 2729 | |
909ff5ef FF |
2730 | /* Make sure we reflect the value of CRC_CMD_FWD */ |
2731 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); | |
2732 | priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); | |
2733 | ||
1c1008c7 FF |
2734 | bcmgenet_set_hw_addr(priv, dev->dev_addr); |
2735 | ||
c624f891 | 2736 | if (priv->internal_phy) { |
1c1008c7 FF |
2737 | reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); |
2738 | reg |= EXT_ENERGY_DET_MASK; | |
2739 | bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); | |
2740 | } | |
2741 | ||
2742 | /* Disable RX/TX DMA and flush TX queues */ | |
2743 | dma_ctrl = bcmgenet_dma_disable(priv); | |
2744 | ||
2745 | /* Reinitialize TDMA and RDMA and SW housekeeping */ | |
2746 | ret = bcmgenet_init_dma(priv); | |
2747 | if (ret) { | |
2748 | netdev_err(dev, "failed to initialize DMA\n"); | |
fac25940 | 2749 | goto err_clk_disable; |
1c1008c7 FF |
2750 | } |
2751 | ||
2752 | /* Always enable ring 16 - descriptor ring */ | |
2753 | bcmgenet_enable_dma(priv, dma_ctrl); | |
2754 | ||
0034de41 PG |
2755 | /* HFB init */ |
2756 | bcmgenet_hfb_init(priv); | |
2757 | ||
1c1008c7 | 2758 | ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, |
c91b7f66 | 2759 | dev->name, priv); |
1c1008c7 FF |
2760 | if (ret < 0) { |
2761 | netdev_err(dev, "can't request IRQ %d\n", priv->irq0); | |
2762 | goto err_fini_dma; | |
2763 | } | |
2764 | ||
2765 | ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, | |
c91b7f66 | 2766 | dev->name, priv); |
1c1008c7 FF |
2767 | if (ret < 0) { |
2768 | netdev_err(dev, "can't request IRQ %d\n", priv->irq1); | |
2769 | goto err_irq0; | |
2770 | } | |
2771 | ||
6cc8e6d4 FF |
2772 | ret = bcmgenet_mii_probe(dev); |
2773 | if (ret) { | |
2774 | netdev_err(dev, "failed to connect to PHY\n"); | |
2775 | goto err_irq1; | |
2776 | } | |
c96e731c | 2777 | |
909ff5ef | 2778 | bcmgenet_netif_start(dev); |
1c1008c7 FF |
2779 | |
2780 | return 0; | |
2781 | ||
6cc8e6d4 FF |
2782 | err_irq1: |
2783 | free_irq(priv->irq1, priv); | |
1c1008c7 | 2784 | err_irq0: |
978ffac4 | 2785 | free_irq(priv->irq0, priv); |
1c1008c7 FF |
2786 | err_fini_dma: |
2787 | bcmgenet_fini_dma(priv); | |
2788 | err_clk_disable: | |
7d5d3075 | 2789 | clk_disable_unprepare(priv->clk); |
1c1008c7 FF |
2790 | return ret; |
2791 | } | |
2792 | ||
909ff5ef FF |
2793 | static void bcmgenet_netif_stop(struct net_device *dev) |
2794 | { | |
2795 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2796 | ||
2797 | netif_tx_stop_all_queues(dev); | |
0299b6ac | 2798 | phy_stop(priv->phydev); |
909ff5ef | 2799 | bcmgenet_intr_disable(priv); |
3ab11339 | 2800 | bcmgenet_disable_rx_napi(priv); |
e2aadb4a | 2801 | bcmgenet_disable_tx_napi(priv); |
909ff5ef FF |
2802 | |
2803 | /* Wait for pending work items to complete. Since interrupts are | |
2804 | * disabled no new work will be scheduled. | |
2805 | */ | |
2806 | cancel_work_sync(&priv->bcmgenet_irq_work); | |
cc013fb4 | 2807 | |
cc013fb4 | 2808 | priv->old_link = -1; |
5ad6e6c5 | 2809 | priv->old_speed = -1; |
cc013fb4 | 2810 | priv->old_duplex = -1; |
5ad6e6c5 | 2811 | priv->old_pause = -1; |
909ff5ef FF |
2812 | } |
2813 | ||
1c1008c7 FF |
2814 | static int bcmgenet_close(struct net_device *dev) |
2815 | { | |
2816 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2817 | int ret; | |
1c1008c7 FF |
2818 | |
2819 | netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); | |
2820 | ||
909ff5ef | 2821 | bcmgenet_netif_stop(dev); |
1c1008c7 | 2822 | |
c96e731c | 2823 | /* Really kill the PHY state machine and disconnect from it */ |
0299b6ac | 2824 | phy_disconnect(priv->phydev); |
c96e731c | 2825 | |
1c1008c7 | 2826 | /* Disable MAC receive */ |
e29585b8 | 2827 | umac_enable_set(priv, CMD_RX_EN, false); |
1c1008c7 | 2828 | |
1c1008c7 FF |
2829 | ret = bcmgenet_dma_teardown(priv); |
2830 | if (ret) | |
2831 | return ret; | |
2832 | ||
556c2cf4 | 2833 | /* Disable MAC transmit. TX DMA disabled must be done before this */ |
e29585b8 | 2834 | umac_enable_set(priv, CMD_TX_EN, false); |
1c1008c7 | 2835 | |
1c1008c7 FF |
2836 | /* tx reclaim */ |
2837 | bcmgenet_tx_reclaim_all(dev); | |
2838 | bcmgenet_fini_dma(priv); | |
2839 | ||
2840 | free_irq(priv->irq0, priv); | |
2841 | free_irq(priv->irq1, priv); | |
2842 | ||
c624f891 | 2843 | if (priv->internal_phy) |
ca8cf341 | 2844 | ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); |
1c1008c7 | 2845 | |
7d5d3075 | 2846 | clk_disable_unprepare(priv->clk); |
1c1008c7 | 2847 | |
ca8cf341 | 2848 | return ret; |
1c1008c7 FF |
2849 | } |
2850 | ||
13ea6578 FF |
2851 | static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) |
2852 | { | |
2853 | struct bcmgenet_priv *priv = ring->priv; | |
2854 | u32 p_index, c_index, intsts, intmsk; | |
2855 | struct netdev_queue *txq; | |
2856 | unsigned int free_bds; | |
2857 | unsigned long flags; | |
2858 | bool txq_stopped; | |
2859 | ||
2860 | if (!netif_msg_tx_err(priv)) | |
2861 | return; | |
2862 | ||
2863 | txq = netdev_get_tx_queue(priv->dev, ring->queue); | |
2864 | ||
2865 | spin_lock_irqsave(&ring->lock, flags); | |
2866 | if (ring->index == DESC_INDEX) { | |
2867 | intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); | |
2868 | intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; | |
2869 | } else { | |
2870 | intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); | |
2871 | intmsk = 1 << ring->index; | |
2872 | } | |
2873 | c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); | |
2874 | p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); | |
2875 | txq_stopped = netif_tx_queue_stopped(txq); | |
2876 | free_bds = ring->free_bds; | |
2877 | spin_unlock_irqrestore(&ring->lock, flags); | |
2878 | ||
2879 | netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" | |
2880 | "TX queue status: %s, interrupts: %s\n" | |
2881 | "(sw)free_bds: %d (sw)size: %d\n" | |
2882 | "(sw)p_index: %d (hw)p_index: %d\n" | |
2883 | "(sw)c_index: %d (hw)c_index: %d\n" | |
2884 | "(sw)clean_p: %d (sw)write_p: %d\n" | |
2885 | "(sw)cb_ptr: %d (sw)end_ptr: %d\n", | |
2886 | ring->index, ring->queue, | |
2887 | txq_stopped ? "stopped" : "active", | |
2888 | intsts & intmsk ? "enabled" : "disabled", | |
2889 | free_bds, ring->size, | |
2890 | ring->prod_index, p_index & DMA_P_INDEX_MASK, | |
2891 | ring->c_index, c_index & DMA_C_INDEX_MASK, | |
2892 | ring->clean_ptr, ring->write_ptr, | |
2893 | ring->cb_ptr, ring->end_ptr); | |
2894 | } | |
2895 | ||
1c1008c7 FF |
2896 | static void bcmgenet_timeout(struct net_device *dev) |
2897 | { | |
2898 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
13ea6578 FF |
2899 | u32 int0_enable = 0; |
2900 | u32 int1_enable = 0; | |
2901 | unsigned int q; | |
1c1008c7 FF |
2902 | |
2903 | netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); | |
2904 | ||
13ea6578 FF |
2905 | for (q = 0; q < priv->hw_params->tx_queues; q++) |
2906 | bcmgenet_dump_tx_queue(&priv->tx_rings[q]); | |
2907 | bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); | |
2908 | ||
2909 | bcmgenet_tx_reclaim_all(dev); | |
2910 | ||
2911 | for (q = 0; q < priv->hw_params->tx_queues; q++) | |
2912 | int1_enable |= (1 << q); | |
2913 | ||
2914 | int0_enable = UMAC_IRQ_TXDMA_DONE; | |
2915 | ||
2916 | /* Re-enable TX interrupts if disabled */ | |
2917 | bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); | |
2918 | bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); | |
2919 | ||
860e9538 | 2920 | netif_trans_update(dev); |
1c1008c7 FF |
2921 | |
2922 | dev->stats.tx_errors++; | |
2923 | ||
2924 | netif_tx_wake_all_queues(dev); | |
2925 | } | |
2926 | ||
2927 | #define MAX_MC_COUNT 16 | |
2928 | ||
2929 | static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, | |
2930 | unsigned char *addr, | |
2931 | int *i, | |
2932 | int *mc) | |
2933 | { | |
2934 | u32 reg; | |
2935 | ||
c91b7f66 FF |
2936 | bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], |
2937 | UMAC_MDF_ADDR + (*i * 4)); | |
2938 | bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | | |
2939 | addr[4] << 8 | addr[5], | |
2940 | UMAC_MDF_ADDR + ((*i + 1) * 4)); | |
1c1008c7 FF |
2941 | reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL); |
2942 | reg |= (1 << (MAX_MC_COUNT - *mc)); | |
2943 | bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); | |
2944 | *i += 2; | |
2945 | (*mc)++; | |
2946 | } | |
2947 | ||
2948 | static void bcmgenet_set_rx_mode(struct net_device *dev) | |
2949 | { | |
2950 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
2951 | struct netdev_hw_addr *ha; | |
2952 | int i, mc; | |
2953 | u32 reg; | |
2954 | ||
2955 | netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); | |
2956 | ||
7fc527f9 | 2957 | /* Promiscuous mode */ |
1c1008c7 FF |
2958 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); |
2959 | if (dev->flags & IFF_PROMISC) { | |
2960 | reg |= CMD_PROMISC; | |
2961 | bcmgenet_umac_writel(priv, reg, UMAC_CMD); | |
2962 | bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); | |
2963 | return; | |
2964 | } else { | |
2965 | reg &= ~CMD_PROMISC; | |
2966 | bcmgenet_umac_writel(priv, reg, UMAC_CMD); | |
2967 | } | |
2968 | ||
2969 | /* UniMac doesn't support ALLMULTI */ | |
2970 | if (dev->flags & IFF_ALLMULTI) { | |
2971 | netdev_warn(dev, "ALLMULTI is not supported\n"); | |
2972 | return; | |
2973 | } | |
2974 | ||
2975 | /* update MDF filter */ | |
2976 | i = 0; | |
2977 | mc = 0; | |
2978 | /* Broadcast */ | |
2979 | bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc); | |
2980 | /* my own address.*/ | |
2981 | bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc); | |
2982 | /* Unicast list*/ | |
2983 | if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc)) | |
2984 | return; | |
2985 | ||
2986 | if (!netdev_uc_empty(dev)) | |
2987 | netdev_for_each_uc_addr(ha, dev) | |
2988 | bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); | |
2989 | /* Multicast */ | |
2990 | if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc)) | |
2991 | return; | |
2992 | ||
2993 | netdev_for_each_mc_addr(ha, dev) | |
2994 | bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); | |
2995 | } | |
2996 | ||
2997 | /* Set the hardware MAC address. */ | |
2998 | static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) | |
2999 | { | |
3000 | struct sockaddr *addr = p; | |
3001 | ||
3002 | /* Setting the MAC address at the hardware level is not possible | |
3003 | * without disabling the UniMAC RX/TX enable bits. | |
3004 | */ | |
3005 | if (netif_running(dev)) | |
3006 | return -EBUSY; | |
3007 | ||
3008 | ether_addr_copy(dev->dev_addr, addr->sa_data); | |
3009 | ||
3010 | return 0; | |
3011 | } | |
3012 | ||
1c1008c7 FF |
3013 | static const struct net_device_ops bcmgenet_netdev_ops = { |
3014 | .ndo_open = bcmgenet_open, | |
3015 | .ndo_stop = bcmgenet_close, | |
3016 | .ndo_start_xmit = bcmgenet_xmit, | |
1c1008c7 FF |
3017 | .ndo_tx_timeout = bcmgenet_timeout, |
3018 | .ndo_set_rx_mode = bcmgenet_set_rx_mode, | |
3019 | .ndo_set_mac_address = bcmgenet_set_mac_addr, | |
3020 | .ndo_do_ioctl = bcmgenet_ioctl, | |
3021 | .ndo_set_features = bcmgenet_set_features, | |
4d2e8882 FF |
3022 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3023 | .ndo_poll_controller = bcmgenet_poll_controller, | |
3024 | #endif | |
1c1008c7 FF |
3025 | }; |
3026 | ||
3027 | /* Array of GENET hardware parameters/characteristics */ | |
3028 | static struct bcmgenet_hw_params bcmgenet_hw_params[] = { | |
3029 | [GENET_V1] = { | |
3030 | .tx_queues = 0, | |
51a966a7 | 3031 | .tx_bds_per_q = 0, |
1c1008c7 | 3032 | .rx_queues = 0, |
3feafa02 | 3033 | .rx_bds_per_q = 0, |
1c1008c7 FF |
3034 | .bp_in_en_shift = 16, |
3035 | .bp_in_mask = 0xffff, | |
3036 | .hfb_filter_cnt = 16, | |
3037 | .qtag_mask = 0x1F, | |
3038 | .hfb_offset = 0x1000, | |
3039 | .rdma_offset = 0x2000, | |
3040 | .tdma_offset = 0x3000, | |
3041 | .words_per_bd = 2, | |
3042 | }, | |
3043 | [GENET_V2] = { | |
3044 | .tx_queues = 4, | |
51a966a7 | 3045 | .tx_bds_per_q = 32, |
7e906e02 | 3046 | .rx_queues = 0, |
3feafa02 | 3047 | .rx_bds_per_q = 0, |
1c1008c7 FF |
3048 | .bp_in_en_shift = 16, |
3049 | .bp_in_mask = 0xffff, | |
3050 | .hfb_filter_cnt = 16, | |
3051 | .qtag_mask = 0x1F, | |
3052 | .tbuf_offset = 0x0600, | |
3053 | .hfb_offset = 0x1000, | |
3054 | .hfb_reg_offset = 0x2000, | |
3055 | .rdma_offset = 0x3000, | |
3056 | .tdma_offset = 0x4000, | |
3057 | .words_per_bd = 2, | |
3058 | .flags = GENET_HAS_EXT, | |
3059 | }, | |
3060 | [GENET_V3] = { | |
3061 | .tx_queues = 4, | |
51a966a7 | 3062 | .tx_bds_per_q = 32, |
7e906e02 | 3063 | .rx_queues = 0, |
3feafa02 | 3064 | .rx_bds_per_q = 0, |
1c1008c7 FF |
3065 | .bp_in_en_shift = 17, |
3066 | .bp_in_mask = 0x1ffff, | |
3067 | .hfb_filter_cnt = 48, | |
0034de41 | 3068 | .hfb_filter_size = 128, |
1c1008c7 FF |
3069 | .qtag_mask = 0x3F, |
3070 | .tbuf_offset = 0x0600, | |
3071 | .hfb_offset = 0x8000, | |
3072 | .hfb_reg_offset = 0xfc00, | |
3073 | .rdma_offset = 0x10000, | |
3074 | .tdma_offset = 0x11000, | |
3075 | .words_per_bd = 2, | |
8d88c6eb PG |
3076 | .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | |
3077 | GENET_HAS_MOCA_LINK_DET, | |
1c1008c7 FF |
3078 | }, |
3079 | [GENET_V4] = { | |
3080 | .tx_queues = 4, | |
51a966a7 | 3081 | .tx_bds_per_q = 32, |
7e906e02 | 3082 | .rx_queues = 0, |
3feafa02 | 3083 | .rx_bds_per_q = 0, |
1c1008c7 FF |
3084 | .bp_in_en_shift = 17, |
3085 | .bp_in_mask = 0x1ffff, | |
3086 | .hfb_filter_cnt = 48, | |
0034de41 | 3087 | .hfb_filter_size = 128, |
1c1008c7 FF |
3088 | .qtag_mask = 0x3F, |
3089 | .tbuf_offset = 0x0600, | |
3090 | .hfb_offset = 0x8000, | |
3091 | .hfb_reg_offset = 0xfc00, | |
3092 | .rdma_offset = 0x2000, | |
3093 | .tdma_offset = 0x4000, | |
3094 | .words_per_bd = 3, | |
8d88c6eb PG |
3095 | .flags = GENET_HAS_40BITS | GENET_HAS_EXT | |
3096 | GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, | |
1c1008c7 FF |
3097 | }, |
3098 | }; | |
3099 | ||
3100 | /* Infer hardware parameters from the detected GENET version */ | |
3101 | static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) | |
3102 | { | |
3103 | struct bcmgenet_hw_params *params; | |
3104 | u32 reg; | |
3105 | u8 major; | |
b04a2f5b | 3106 | u16 gphy_rev; |
1c1008c7 FF |
3107 | |
3108 | if (GENET_IS_V4(priv)) { | |
3109 | bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; | |
3110 | genet_dma_ring_regs = genet_dma_ring_regs_v4; | |
3111 | priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; | |
1c1008c7 FF |
3112 | } else if (GENET_IS_V3(priv)) { |
3113 | bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; | |
3114 | genet_dma_ring_regs = genet_dma_ring_regs_v123; | |
3115 | priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; | |
1c1008c7 FF |
3116 | } else if (GENET_IS_V2(priv)) { |
3117 | bcmgenet_dma_regs = bcmgenet_dma_regs_v2; | |
3118 | genet_dma_ring_regs = genet_dma_ring_regs_v123; | |
3119 | priv->dma_rx_chk_bit = DMA_RX_CHK_V12; | |
1c1008c7 FF |
3120 | } else if (GENET_IS_V1(priv)) { |
3121 | bcmgenet_dma_regs = bcmgenet_dma_regs_v1; | |
3122 | genet_dma_ring_regs = genet_dma_ring_regs_v123; | |
3123 | priv->dma_rx_chk_bit = DMA_RX_CHK_V12; | |
1c1008c7 FF |
3124 | } |
3125 | ||
3126 | /* enum genet_version starts at 1 */ | |
3127 | priv->hw_params = &bcmgenet_hw_params[priv->version]; | |
3128 | params = priv->hw_params; | |
3129 | ||
3130 | /* Read GENET HW version */ | |
3131 | reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); | |
3132 | major = (reg >> 24 & 0x0f); | |
3133 | if (major == 5) | |
3134 | major = 4; | |
3135 | else if (major == 0) | |
3136 | major = 1; | |
3137 | if (major != priv->version) { | |
3138 | dev_err(&priv->pdev->dev, | |
3139 | "GENET version mismatch, got: %d, configured for: %d\n", | |
3140 | major, priv->version); | |
3141 | } | |
3142 | ||
3143 | /* Print the GENET core version */ | |
3144 | dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, | |
c91b7f66 | 3145 | major, (reg >> 16) & 0x0f, reg & 0xffff); |
1c1008c7 | 3146 | |
487320c5 FF |
3147 | /* Store the integrated PHY revision for the MDIO probing function |
3148 | * to pass this information to the PHY driver. The PHY driver expects | |
3149 | * to find the PHY major revision in bits 15:8 while the GENET register | |
3150 | * stores that information in bits 7:0, account for that. | |
b04a2f5b FF |
3151 | * |
3152 | * On newer chips, starting with PHY revision G0, a new scheme is | |
3153 | * deployed similar to the Starfighter 2 switch with GPHY major | |
3154 | * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 | |
3155 | * is reserved as well as special value 0x01ff, we have a small | |
3156 | * heuristic to check for the new GPHY revision and re-arrange things | |
3157 | * so the GPHY driver is happy. | |
487320c5 | 3158 | */ |
b04a2f5b FF |
3159 | gphy_rev = reg & 0xffff; |
3160 | ||
3161 | /* This is the good old scheme, just GPHY major, no minor nor patch */ | |
3162 | if ((gphy_rev & 0xf0) != 0) | |
3163 | priv->gphy_rev = gphy_rev << 8; | |
3164 | ||
3165 | /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ | |
3166 | else if ((gphy_rev & 0xff00) != 0) | |
3167 | priv->gphy_rev = gphy_rev; | |
3168 | ||
3169 | /* This is reserved so should require special treatment */ | |
3170 | else if (gphy_rev == 0 || gphy_rev == 0x01ff) { | |
3171 | pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); | |
3172 | return; | |
3173 | } | |
487320c5 | 3174 | |
1c1008c7 FF |
3175 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
3176 | if (!(params->flags & GENET_HAS_40BITS)) | |
3177 | pr_warn("GENET does not support 40-bits PA\n"); | |
3178 | #endif | |
3179 | ||
3180 | pr_debug("Configuration for version: %d\n" | |
3feafa02 | 3181 | "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" |
1c1008c7 FF |
3182 | "BP << en: %2d, BP msk: 0x%05x\n" |
3183 | "HFB count: %2d, QTAQ msk: 0x%05x\n" | |
3184 | "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" | |
3185 | "RDMA: 0x%05x, TDMA: 0x%05x\n" | |
3186 | "Words/BD: %d\n", | |
3187 | priv->version, | |
51a966a7 | 3188 | params->tx_queues, params->tx_bds_per_q, |
3feafa02 | 3189 | params->rx_queues, params->rx_bds_per_q, |
1c1008c7 FF |
3190 | params->bp_in_en_shift, params->bp_in_mask, |
3191 | params->hfb_filter_cnt, params->qtag_mask, | |
3192 | params->tbuf_offset, params->hfb_offset, | |
3193 | params->hfb_reg_offset, | |
3194 | params->rdma_offset, params->tdma_offset, | |
3195 | params->words_per_bd); | |
3196 | } | |
3197 | ||
3198 | static const struct of_device_id bcmgenet_match[] = { | |
3199 | { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 }, | |
3200 | { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 }, | |
3201 | { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 }, | |
3202 | { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 }, | |
3203 | { }, | |
3204 | }; | |
e8048e55 | 3205 | MODULE_DEVICE_TABLE(of, bcmgenet_match); |
1c1008c7 FF |
3206 | |
3207 | static int bcmgenet_probe(struct platform_device *pdev) | |
3208 | { | |
b0ba512e | 3209 | struct bcmgenet_platform_data *pd = pdev->dev.platform_data; |
1c1008c7 | 3210 | struct device_node *dn = pdev->dev.of_node; |
b0ba512e | 3211 | const struct of_device_id *of_id = NULL; |
1c1008c7 FF |
3212 | struct bcmgenet_priv *priv; |
3213 | struct net_device *dev; | |
3214 | const void *macaddr; | |
3215 | struct resource *r; | |
3216 | int err = -EIO; | |
3217 | ||
3feafeed PG |
3218 | /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ |
3219 | dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, | |
3220 | GENET_MAX_MQ_CNT + 1); | |
1c1008c7 FF |
3221 | if (!dev) { |
3222 | dev_err(&pdev->dev, "can't allocate net device\n"); | |
3223 | return -ENOMEM; | |
3224 | } | |
3225 | ||
b0ba512e PG |
3226 | if (dn) { |
3227 | of_id = of_match_node(bcmgenet_match, dn); | |
3228 | if (!of_id) | |
3229 | return -EINVAL; | |
3230 | } | |
1c1008c7 FF |
3231 | |
3232 | priv = netdev_priv(dev); | |
3233 | priv->irq0 = platform_get_irq(pdev, 0); | |
3234 | priv->irq1 = platform_get_irq(pdev, 1); | |
8562056f | 3235 | priv->wol_irq = platform_get_irq(pdev, 2); |
1c1008c7 FF |
3236 | if (!priv->irq0 || !priv->irq1) { |
3237 | dev_err(&pdev->dev, "can't find IRQs\n"); | |
3238 | err = -EINVAL; | |
3239 | goto err; | |
3240 | } | |
3241 | ||
b0ba512e PG |
3242 | if (dn) { |
3243 | macaddr = of_get_mac_address(dn); | |
3244 | if (!macaddr) { | |
3245 | dev_err(&pdev->dev, "can't find MAC address\n"); | |
3246 | err = -EINVAL; | |
3247 | goto err; | |
3248 | } | |
3249 | } else { | |
3250 | macaddr = pd->mac_address; | |
1c1008c7 FF |
3251 | } |
3252 | ||
3253 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
5343a10d FE |
3254 | priv->base = devm_ioremap_resource(&pdev->dev, r); |
3255 | if (IS_ERR(priv->base)) { | |
3256 | err = PTR_ERR(priv->base); | |
1c1008c7 FF |
3257 | goto err; |
3258 | } | |
3259 | ||
3260 | SET_NETDEV_DEV(dev, &pdev->dev); | |
3261 | dev_set_drvdata(&pdev->dev, dev); | |
3262 | ether_addr_copy(dev->dev_addr, macaddr); | |
3263 | dev->watchdog_timeo = 2 * HZ; | |
7ad24ea4 | 3264 | dev->ethtool_ops = &bcmgenet_ethtool_ops; |
1c1008c7 | 3265 | dev->netdev_ops = &bcmgenet_netdev_ops; |
1c1008c7 FF |
3266 | |
3267 | priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); | |
3268 | ||
3269 | /* Set hardware features */ | |
3270 | dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | | |
3271 | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM; | |
3272 | ||
8562056f FF |
3273 | /* Request the WOL interrupt and advertise suspend if available */ |
3274 | priv->wol_irq_disabled = true; | |
3275 | err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, | |
3276 | dev->name, priv); | |
3277 | if (!err) | |
3278 | device_set_wakeup_capable(&pdev->dev, 1); | |
3279 | ||
1c1008c7 FF |
3280 | /* Set the needed headroom to account for any possible |
3281 | * features enabling/disabling at runtime | |
3282 | */ | |
3283 | dev->needed_headroom += 64; | |
3284 | ||
3285 | netdev_boot_setup_check(dev); | |
3286 | ||
3287 | priv->dev = dev; | |
3288 | priv->pdev = pdev; | |
b0ba512e PG |
3289 | if (of_id) |
3290 | priv->version = (enum bcmgenet_version)of_id->data; | |
3291 | else | |
3292 | priv->version = pd->genet_version; | |
1c1008c7 | 3293 | |
e4a60a93 | 3294 | priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); |
7d5d3075 | 3295 | if (IS_ERR(priv->clk)) { |
e4a60a93 | 3296 | dev_warn(&priv->pdev->dev, "failed to get enet clock\n"); |
7d5d3075 FF |
3297 | priv->clk = NULL; |
3298 | } | |
e4a60a93 | 3299 | |
7d5d3075 | 3300 | clk_prepare_enable(priv->clk); |
e4a60a93 | 3301 | |
1c1008c7 FF |
3302 | bcmgenet_set_hw_params(priv); |
3303 | ||
1c1008c7 FF |
3304 | /* Mii wait queue */ |
3305 | init_waitqueue_head(&priv->wq); | |
3306 | /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ | |
3307 | priv->rx_buf_len = RX_BUF_LENGTH; | |
3308 | INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); | |
3309 | ||
1c1008c7 | 3310 | priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); |
7d5d3075 | 3311 | if (IS_ERR(priv->clk_wol)) { |
1c1008c7 | 3312 | dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n"); |
7d5d3075 FF |
3313 | priv->clk_wol = NULL; |
3314 | } | |
1c1008c7 | 3315 | |
6ef398ea FF |
3316 | priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee"); |
3317 | if (IS_ERR(priv->clk_eee)) { | |
3318 | dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n"); | |
3319 | priv->clk_eee = NULL; | |
3320 | } | |
3321 | ||
1c1008c7 FF |
3322 | err = reset_umac(priv); |
3323 | if (err) | |
3324 | goto err_clk_disable; | |
3325 | ||
3326 | err = bcmgenet_mii_init(dev); | |
3327 | if (err) | |
3328 | goto err_clk_disable; | |
3329 | ||
3330 | /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues | |
3331 | * just the ring 16 descriptor based TX | |
3332 | */ | |
3333 | netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); | |
3334 | netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); | |
3335 | ||
219575eb FF |
3336 | /* libphy will determine the link state */ |
3337 | netif_carrier_off(dev); | |
3338 | ||
1c1008c7 | 3339 | /* Turn off the main clock, WOL clock is handled separately */ |
7d5d3075 | 3340 | clk_disable_unprepare(priv->clk); |
1c1008c7 | 3341 | |
0f50ce96 FF |
3342 | err = register_netdev(dev); |
3343 | if (err) | |
3344 | goto err; | |
3345 | ||
1c1008c7 FF |
3346 | return err; |
3347 | ||
3348 | err_clk_disable: | |
7d5d3075 | 3349 | clk_disable_unprepare(priv->clk); |
1c1008c7 FF |
3350 | err: |
3351 | free_netdev(dev); | |
3352 | return err; | |
3353 | } | |
3354 | ||
3355 | static int bcmgenet_remove(struct platform_device *pdev) | |
3356 | { | |
3357 | struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); | |
3358 | ||
3359 | dev_set_drvdata(&pdev->dev, NULL); | |
3360 | unregister_netdev(priv->dev); | |
3361 | bcmgenet_mii_exit(priv->dev); | |
3362 | free_netdev(priv->dev); | |
3363 | ||
3364 | return 0; | |
3365 | } | |
3366 | ||
b6e978e5 FF |
3367 | #ifdef CONFIG_PM_SLEEP |
3368 | static int bcmgenet_suspend(struct device *d) | |
3369 | { | |
3370 | struct net_device *dev = dev_get_drvdata(d); | |
3371 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
3372 | int ret; | |
3373 | ||
3374 | if (!netif_running(dev)) | |
3375 | return 0; | |
3376 | ||
3377 | bcmgenet_netif_stop(dev); | |
3378 | ||
0299b6ac | 3379 | phy_suspend(priv->phydev); |
cc013fb4 | 3380 | |
b6e978e5 FF |
3381 | netif_device_detach(dev); |
3382 | ||
3383 | /* Disable MAC receive */ | |
3384 | umac_enable_set(priv, CMD_RX_EN, false); | |
3385 | ||
3386 | ret = bcmgenet_dma_teardown(priv); | |
3387 | if (ret) | |
3388 | return ret; | |
3389 | ||
556c2cf4 | 3390 | /* Disable MAC transmit. TX DMA disabled must be done before this */ |
b6e978e5 FF |
3391 | umac_enable_set(priv, CMD_TX_EN, false); |
3392 | ||
3393 | /* tx reclaim */ | |
3394 | bcmgenet_tx_reclaim_all(dev); | |
3395 | bcmgenet_fini_dma(priv); | |
3396 | ||
8c90db72 FF |
3397 | /* Prepare the device for Wake-on-LAN and switch to the slow clock */ |
3398 | if (device_may_wakeup(d) && priv->wolopts) { | |
ca8cf341 | 3399 | ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); |
8c90db72 | 3400 | clk_prepare_enable(priv->clk_wol); |
c624f891 | 3401 | } else if (priv->internal_phy) { |
a6f31f5e | 3402 | ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); |
8c90db72 FF |
3403 | } |
3404 | ||
b6e978e5 FF |
3405 | /* Turn off the clocks */ |
3406 | clk_disable_unprepare(priv->clk); | |
3407 | ||
ca8cf341 | 3408 | return ret; |
b6e978e5 FF |
3409 | } |
3410 | ||
3411 | static int bcmgenet_resume(struct device *d) | |
3412 | { | |
3413 | struct net_device *dev = dev_get_drvdata(d); | |
3414 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
3415 | unsigned long dma_ctrl; | |
3416 | int ret; | |
3417 | u32 reg; | |
3418 | ||
3419 | if (!netif_running(dev)) | |
3420 | return 0; | |
3421 | ||
3422 | /* Turn on the clock */ | |
3423 | ret = clk_prepare_enable(priv->clk); | |
3424 | if (ret) | |
3425 | return ret; | |
3426 | ||
a6f31f5e FF |
3427 | /* If this is an internal GPHY, power it back on now, before UniMAC is |
3428 | * brought out of reset as absolutely no UniMAC activity is allowed | |
3429 | */ | |
c624f891 | 3430 | if (priv->internal_phy) |
a6f31f5e FF |
3431 | bcmgenet_power_up(priv, GENET_POWER_PASSIVE); |
3432 | ||
b6e978e5 FF |
3433 | bcmgenet_umac_reset(priv); |
3434 | ||
3435 | ret = init_umac(priv); | |
3436 | if (ret) | |
3437 | goto out_clk_disable; | |
3438 | ||
0a29b3da TK |
3439 | /* From WOL-enabled suspend, switch to regular clock */ |
3440 | if (priv->wolopts) | |
3441 | clk_disable_unprepare(priv->clk_wol); | |
3442 | ||
0299b6ac | 3443 | phy_init_hw(priv->phydev); |
0a29b3da | 3444 | /* Speed settings must be restored */ |
28b45910 | 3445 | bcmgenet_mii_config(priv->dev); |
8c90db72 | 3446 | |
b6e978e5 FF |
3447 | /* disable ethernet MAC while updating its registers */ |
3448 | umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); | |
3449 | ||
3450 | bcmgenet_set_hw_addr(priv, dev->dev_addr); | |
3451 | ||
c624f891 | 3452 | if (priv->internal_phy) { |
b6e978e5 FF |
3453 | reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); |
3454 | reg |= EXT_ENERGY_DET_MASK; | |
3455 | bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); | |
3456 | } | |
3457 | ||
98bb7399 FF |
3458 | if (priv->wolopts) |
3459 | bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); | |
3460 | ||
b6e978e5 FF |
3461 | /* Disable RX/TX DMA and flush TX queues */ |
3462 | dma_ctrl = bcmgenet_dma_disable(priv); | |
3463 | ||
3464 | /* Reinitialize TDMA and RDMA and SW housekeeping */ | |
3465 | ret = bcmgenet_init_dma(priv); | |
3466 | if (ret) { | |
3467 | netdev_err(dev, "failed to initialize DMA\n"); | |
3468 | goto out_clk_disable; | |
3469 | } | |
3470 | ||
3471 | /* Always enable ring 16 - descriptor ring */ | |
3472 | bcmgenet_enable_dma(priv, dma_ctrl); | |
3473 | ||
3474 | netif_device_attach(dev); | |
3475 | ||
0299b6ac | 3476 | phy_resume(priv->phydev); |
cc013fb4 | 3477 | |
6ef398ea FF |
3478 | if (priv->eee.eee_enabled) |
3479 | bcmgenet_eee_enable_set(dev, true); | |
3480 | ||
b6e978e5 FF |
3481 | bcmgenet_netif_start(dev); |
3482 | ||
3483 | return 0; | |
3484 | ||
3485 | out_clk_disable: | |
3486 | clk_disable_unprepare(priv->clk); | |
3487 | return ret; | |
3488 | } | |
3489 | #endif /* CONFIG_PM_SLEEP */ | |
3490 | ||
3491 | static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); | |
3492 | ||
1c1008c7 FF |
3493 | static struct platform_driver bcmgenet_driver = { |
3494 | .probe = bcmgenet_probe, | |
3495 | .remove = bcmgenet_remove, | |
3496 | .driver = { | |
3497 | .name = "bcmgenet", | |
1c1008c7 | 3498 | .of_match_table = bcmgenet_match, |
b6e978e5 | 3499 | .pm = &bcmgenet_pm_ops, |
1c1008c7 FF |
3500 | }, |
3501 | }; | |
3502 | module_platform_driver(bcmgenet_driver); | |
3503 | ||
3504 | MODULE_AUTHOR("Broadcom Corporation"); | |
3505 | MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); | |
3506 | MODULE_ALIAS("platform:bcmgenet"); | |
3507 | MODULE_LICENSE("GPL"); |