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net: bcmgenet: tweak init_umac()
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 106{
107 dmadesc_set_length_status(priv, d, val);
108 dmadesc_set_addr(priv, d, addr);
109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
0034de41
PG		 200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
1c1008c7
FF		 208};
209
210static const u8 bcmgenet_dma_regs_v3plus[] = {
211 [DMA_RING_CFG] = 0x00,
212 [DMA_CTRL] = 0x04,
213 [DMA_STATUS] = 0x08,
214 [DMA_SCB_BURST_SIZE] = 0x0C,
215 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 216 [DMA_PRIORITY_0] = 0x30,
217 [DMA_PRIORITY_1] = 0x34,
218 [DMA_PRIORITY_2] = 0x38,
0034de41
PG		 219 [DMA_INDEX2RING_0] = 0x70,
220 [DMA_INDEX2RING_1] = 0x74,
221 [DMA_INDEX2RING_2] = 0x78,
222 [DMA_INDEX2RING_3] = 0x7C,
223 [DMA_INDEX2RING_4] = 0x80,
224 [DMA_INDEX2RING_5] = 0x84,
225 [DMA_INDEX2RING_6] = 0x88,
226 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 227};
228
229static const u8 bcmgenet_dma_regs_v2[] = {
230 [DMA_RING_CFG] = 0x00,
231 [DMA_CTRL] = 0x04,
232 [DMA_STATUS] = 0x08,
233 [DMA_SCB_BURST_SIZE] = 0x0C,
234 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 235 [DMA_PRIORITY_0] = 0x34,
236 [DMA_PRIORITY_1] = 0x38,
237 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 238};
239
240static const u8 bcmgenet_dma_regs_v1[] = {
241 [DMA_CTRL] = 0x00,
242 [DMA_STATUS] = 0x04,
243 [DMA_SCB_BURST_SIZE] = 0x0C,
244 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 245 [DMA_PRIORITY_0] = 0x34,
246 [DMA_PRIORITY_1] = 0x38,
247 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 248};
249
250/* Set at runtime once bcmgenet version is known */
251static const u8 *bcmgenet_dma_regs;
252
253static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
254{
255 return netdev_priv(dev_get_drvdata(dev));
256}
257
258static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 259 enum dma_reg r)
1c1008c7
FF		 260{
261 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
262 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
263}
264
265static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
266 u32 val, enum dma_reg r)
267{
268 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
269 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
270}
271
272static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 273 enum dma_reg r)
1c1008c7
FF		 274{
275 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
276 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
277}
278
279static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
280 u32 val, enum dma_reg r)
281{
282 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
283 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
284}
285
286/* RDMA/TDMA ring registers and accessors
287 * we merge the common fields and just prefix with T/D the registers
288 * having different meaning depending on the direction
289 */
290enum dma_ring_reg {
291 TDMA_READ_PTR = 0,
292 RDMA_WRITE_PTR = TDMA_READ_PTR,
293 TDMA_READ_PTR_HI,
294 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
295 TDMA_CONS_INDEX,
296 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
297 TDMA_PROD_INDEX,
298 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
299 DMA_RING_BUF_SIZE,
300 DMA_START_ADDR,
301 DMA_START_ADDR_HI,
302 DMA_END_ADDR,
303 DMA_END_ADDR_HI,
304 DMA_MBUF_DONE_THRESH,
305 TDMA_FLOW_PERIOD,
306 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
307 TDMA_WRITE_PTR,
308 RDMA_READ_PTR = TDMA_WRITE_PTR,
309 TDMA_WRITE_PTR_HI,
310 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
311};
312
313/* GENET v4 supports 40-bits pointer addressing
314 * for obvious reasons the LO and HI word parts
315 * are contiguous, but this offsets the other
316 * registers.
317 */
318static const u8 genet_dma_ring_regs_v4[] = {
319 [TDMA_READ_PTR] = 0x00,
320 [TDMA_READ_PTR_HI] = 0x04,
321 [TDMA_CONS_INDEX] = 0x08,
322 [TDMA_PROD_INDEX] = 0x0C,
323 [DMA_RING_BUF_SIZE] = 0x10,
324 [DMA_START_ADDR] = 0x14,
325 [DMA_START_ADDR_HI] = 0x18,
326 [DMA_END_ADDR] = 0x1C,
327 [DMA_END_ADDR_HI] = 0x20,
328 [DMA_MBUF_DONE_THRESH] = 0x24,
329 [TDMA_FLOW_PERIOD] = 0x28,
330 [TDMA_WRITE_PTR] = 0x2C,
331 [TDMA_WRITE_PTR_HI] = 0x30,
332};
333
334static const u8 genet_dma_ring_regs_v123[] = {
335 [TDMA_READ_PTR] = 0x00,
336 [TDMA_CONS_INDEX] = 0x04,
337 [TDMA_PROD_INDEX] = 0x08,
338 [DMA_RING_BUF_SIZE] = 0x0C,
339 [DMA_START_ADDR] = 0x10,
340 [DMA_END_ADDR] = 0x14,
341 [DMA_MBUF_DONE_THRESH] = 0x18,
342 [TDMA_FLOW_PERIOD] = 0x1C,
343 [TDMA_WRITE_PTR] = 0x20,
344};
345
346/* Set at runtime once GENET version is known */
347static const u8 *genet_dma_ring_regs;
348
349static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 350 unsigned int ring,
351 enum dma_ring_reg r)
1c1008c7
FF		 352{
353 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
354 (DMA_RING_SIZE * ring) +
355 genet_dma_ring_regs[r]);
356}
357
358static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 359 unsigned int ring, u32 val,
360 enum dma_ring_reg r)
1c1008c7
FF		 361{
362 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
363 (DMA_RING_SIZE * ring) +
364 genet_dma_ring_regs[r]);
365}
366
367static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 368 unsigned int ring,
369 enum dma_ring_reg r)
1c1008c7
FF		 370{
371 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
372 (DMA_RING_SIZE * ring) +
373 genet_dma_ring_regs[r]);
374}
375
376static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 377 unsigned int ring, u32 val,
378 enum dma_ring_reg r)
1c1008c7
FF		 379{
380 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
381 (DMA_RING_SIZE * ring) +
382 genet_dma_ring_regs[r]);
383}
384
385static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 386 struct ethtool_cmd *cmd)
1c1008c7
FF		 387{
388 struct bcmgenet_priv *priv = netdev_priv(dev);
389
390 if (!netif_running(dev))
391 return -EINVAL;
392
393 if (!priv->phydev)
394 return -ENODEV;
395
396 return phy_ethtool_gset(priv->phydev, cmd);
397}
398
399static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 400 struct ethtool_cmd *cmd)
1c1008c7
FF		 401{
402 struct bcmgenet_priv *priv = netdev_priv(dev);
403
404 if (!netif_running(dev))
405 return -EINVAL;
406
407 if (!priv->phydev)
408 return -ENODEV;
409
410 return phy_ethtool_sset(priv->phydev, cmd);
411}
412
413static int bcmgenet_set_rx_csum(struct net_device *dev,
414 netdev_features_t wanted)
415{
416 struct bcmgenet_priv *priv = netdev_priv(dev);
417 u32 rbuf_chk_ctrl;
418 bool rx_csum_en;
419
420 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
421
422 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
423
424 /* enable rx checksumming */
425 if (rx_csum_en)
426 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
427 else
428 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
429 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 430
431 /* If UniMAC forwards CRC, we need to skip over it to get
432 * a valid CHK bit to be set in the per-packet status word
433 */
434 if (rx_csum_en && priv->crc_fwd_en)
435 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
436 else
437 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
438
1c1008c7
FF		 439 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
440
441 return 0;
442}
443
444static int bcmgenet_set_tx_csum(struct net_device *dev,
445 netdev_features_t wanted)
446{
447 struct bcmgenet_priv *priv = netdev_priv(dev);
448 bool desc_64b_en;
449 u32 tbuf_ctrl, rbuf_ctrl;
450
451 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
452 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
453
454 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
455
456 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
457 if (desc_64b_en) {
458 tbuf_ctrl |= RBUF_64B_EN;
459 rbuf_ctrl |= RBUF_64B_EN;
460 } else {
461 tbuf_ctrl &= ~RBUF_64B_EN;
462 rbuf_ctrl &= ~RBUF_64B_EN;
463 }
464 priv->desc_64b_en = desc_64b_en;
465
466 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
467 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
468
469 return 0;
470}
471
472static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 473 netdev_features_t features)
1c1008c7
FF		 474{
475 netdev_features_t changed = features ^ dev->features;
476 netdev_features_t wanted = dev->wanted_features;
477 int ret = 0;
478
479 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
480 ret = bcmgenet_set_tx_csum(dev, wanted);
481 if (changed & (NETIF_F_RXCSUM))
482 ret = bcmgenet_set_rx_csum(dev, wanted);
483
484 return ret;
485}
486
487static u32 bcmgenet_get_msglevel(struct net_device *dev)
488{
489 struct bcmgenet_priv *priv = netdev_priv(dev);
490
491 return priv->msg_enable;
492}
493
494static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
495{
496 struct bcmgenet_priv *priv = netdev_priv(dev);
497
498 priv->msg_enable = level;
499}
500
501/* standard ethtool support functions. */
502enum bcmgenet_stat_type {
503 BCMGENET_STAT_NETDEV = -1,
504 BCMGENET_STAT_MIB_RX,
505 BCMGENET_STAT_MIB_TX,
506 BCMGENET_STAT_RUNT,
507 BCMGENET_STAT_MISC,
f62ba9c1 508 BCMGENET_STAT_SOFT,
1c1008c7
FF		 509};
510
511struct bcmgenet_stats {
512 char stat_string[ETH_GSTRING_LEN];
513 int stat_sizeof;
514 int stat_offset;
515 enum bcmgenet_stat_type type;
516 /* reg offset from UMAC base for misc counters */
517 u16 reg_offset;
518};
519
520#define STAT_NETDEV(m) { \
521 .stat_string = __stringify(m), \
522 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
523 .stat_offset = offsetof(struct net_device_stats, m), \
524 .type = BCMGENET_STAT_NETDEV, \
525}
526
527#define STAT_GENET_MIB(str, m, _type) { \
528 .stat_string = str, \
529 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
530 .stat_offset = offsetof(struct bcmgenet_priv, m), \
531 .type = _type, \
532}
533
534#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
535#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
536#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 537#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 538
539#define STAT_GENET_MISC(str, m, offset) { \
540 .stat_string = str, \
541 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
542 .stat_offset = offsetof(struct bcmgenet_priv, m), \
543 .type = BCMGENET_STAT_MISC, \
544 .reg_offset = offset, \
545}
546
547
548/* There is a 0xC gap between the end of RX and beginning of TX stats and then
549 * between the end of TX stats and the beginning of the RX RUNT
550 */
551#define BCMGENET_STAT_OFFSET 0xc
552
553/* Hardware counters must be kept in sync because the order/offset
554 * is important here (order in structure declaration = order in hardware)
555 */
556static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
557 /* general stats */
558 STAT_NETDEV(rx_packets),
559 STAT_NETDEV(tx_packets),
560 STAT_NETDEV(rx_bytes),
561 STAT_NETDEV(tx_bytes),
562 STAT_NETDEV(rx_errors),
563 STAT_NETDEV(tx_errors),
564 STAT_NETDEV(rx_dropped),
565 STAT_NETDEV(tx_dropped),
566 STAT_NETDEV(multicast),
567 /* UniMAC RSV counters */
568 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
569 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
570 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
571 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
572 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
573 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
574 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
575 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
576 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
577 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
578 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
579 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
580 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
581 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
582 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
583 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
584 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
585 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
586 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
587 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
588 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
589 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
590 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
591 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
592 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
593 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
594 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
595 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
596 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
597 /* UniMAC TSV counters */
598 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
599 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
600 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
601 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
602 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
603 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
604 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
605 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
606 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
607 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
608 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
609 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
610 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
611 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
612 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
613 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
614 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
615 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
616 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
617 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
618 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
619 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
620 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
621 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
622 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
623 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
624 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
625 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
626 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
627 /* UniMAC RUNT counters */
628 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
629 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
630 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
631 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
632 /* Misc UniMAC counters */
633 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
634 UMAC_RBUF_OVFL_CNT),
635 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
636 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 637 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
638 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
639 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 640};
641
642#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
643
644static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 645 struct ethtool_drvinfo *info)
1c1008c7
FF		 646{
647 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
648 strlcpy(info->version, "v2.0", sizeof(info->version));
649 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 650}
651
652static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
653{
654 switch (string_set) {
655 case ETH_SS_STATS:
656 return BCMGENET_STATS_LEN;
657 default:
658 return -EOPNOTSUPP;
659 }
660}
661
c91b7f66
FF		 662static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
663 u8 *data)
1c1008c7
FF		 664{
665 int i;
666
667 switch (stringset) {
668 case ETH_SS_STATS:
669 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
670 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 671 bcmgenet_gstrings_stats[i].stat_string,
672 ETH_GSTRING_LEN);
1c1008c7
FF		 673 }
674 break;
675 }
676}
677
678static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
679{
680 int i, j = 0;
681
682 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
683 const struct bcmgenet_stats *s;
684 u8 offset = 0;
685 u32 val = 0;
686 char *p;
687
688 s = &bcmgenet_gstrings_stats[i];
689 switch (s->type) {
690 case BCMGENET_STAT_NETDEV:
f62ba9c1 691 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 692 continue;
693 case BCMGENET_STAT_MIB_RX:
694 case BCMGENET_STAT_MIB_TX:
695 case BCMGENET_STAT_RUNT:
696 if (s->type != BCMGENET_STAT_MIB_RX)
697 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 698 val = bcmgenet_umac_readl(priv,
699 UMAC_MIB_START + j + offset);
1c1008c7
FF		 700 break;
701 case BCMGENET_STAT_MISC:
702 val = bcmgenet_umac_readl(priv, s->reg_offset);
703 /* clear if overflowed */
704 if (val == ~0)
705 bcmgenet_umac_writel(priv, 0, s->reg_offset);
706 break;
707 }
708
709 j += s->stat_sizeof;
710 p = (char *)priv + s->stat_offset;
711 *(u32 *)p = val;
712 }
713}
714
715static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 716 struct ethtool_stats *stats,
717 u64 *data)
1c1008c7
FF		 718{
719 struct bcmgenet_priv *priv = netdev_priv(dev);
720 int i;
721
722 if (netif_running(dev))
723 bcmgenet_update_mib_counters(priv);
724
725 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
726 const struct bcmgenet_stats *s;
727 char *p;
728
729 s = &bcmgenet_gstrings_stats[i];
730 if (s->type == BCMGENET_STAT_NETDEV)
731 p = (char *)&dev->stats;
732 else
733 p = (char *)priv;
734 p += s->stat_offset;
735 data[i] = *(u32 *)p;
736 }
737}
738
6ef398ea
FF		 739static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
740{
741 struct bcmgenet_priv *priv = netdev_priv(dev);
742 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
743 u32 reg;
744
745 if (enable && !priv->clk_eee_enabled) {
746 clk_prepare_enable(priv->clk_eee);
747 priv->clk_eee_enabled = true;
748 }
749
750 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
751 if (enable)
752 reg |= EEE_EN;
753 else
754 reg &= ~EEE_EN;
755 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
756
757 /* Enable EEE and switch to a 27Mhz clock automatically */
758 reg = __raw_readl(priv->base + off);
759 if (enable)
760 reg |= TBUF_EEE_EN | TBUF_PM_EN;
761 else
762 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
763 __raw_writel(reg, priv->base + off);
764
765 /* Do the same for thing for RBUF */
766 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
767 if (enable)
768 reg |= RBUF_EEE_EN | RBUF_PM_EN;
769 else
770 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
771 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
772
773 if (!enable && priv->clk_eee_enabled) {
774 clk_disable_unprepare(priv->clk_eee);
775 priv->clk_eee_enabled = false;
776 }
777
778 priv->eee.eee_enabled = enable;
779 priv->eee.eee_active = enable;
780}
781
782static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
783{
784 struct bcmgenet_priv *priv = netdev_priv(dev);
785 struct ethtool_eee *p = &priv->eee;
786
787 if (GENET_IS_V1(priv))
788 return -EOPNOTSUPP;
789
790 e->eee_enabled = p->eee_enabled;
791 e->eee_active = p->eee_active;
792 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
793
794 return phy_ethtool_get_eee(priv->phydev, e);
795}
796
797static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
798{
799 struct bcmgenet_priv *priv = netdev_priv(dev);
800 struct ethtool_eee *p = &priv->eee;
801 int ret = 0;
802
803 if (GENET_IS_V1(priv))
804 return -EOPNOTSUPP;
805
806 p->eee_enabled = e->eee_enabled;
807
808 if (!p->eee_enabled) {
809 bcmgenet_eee_enable_set(dev, false);
810 } else {
811 ret = phy_init_eee(priv->phydev, 0);
812 if (ret) {
813 netif_err(priv, hw, dev, "EEE initialization failed\n");
814 return ret;
815 }
816
817 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
818 bcmgenet_eee_enable_set(dev, true);
819 }
820
821 return phy_ethtool_set_eee(priv->phydev, e);
822}
823
6b0c5406
FF		 824static int bcmgenet_nway_reset(struct net_device *dev)
825{
826 struct bcmgenet_priv *priv = netdev_priv(dev);
827
828 return genphy_restart_aneg(priv->phydev);
829}
830
1c1008c7
FF		 831/* standard ethtool support functions. */
832static struct ethtool_ops bcmgenet_ethtool_ops = {
833 .get_strings = bcmgenet_get_strings,
834 .get_sset_count = bcmgenet_get_sset_count,
835 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
836 .get_settings = bcmgenet_get_settings,
837 .set_settings = bcmgenet_set_settings,
838 .get_drvinfo = bcmgenet_get_drvinfo,
839 .get_link = ethtool_op_get_link,
840 .get_msglevel = bcmgenet_get_msglevel,
841 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 842 .get_wol = bcmgenet_get_wol,
843 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 844 .get_eee = bcmgenet_get_eee,
845 .set_eee = bcmgenet_set_eee,
6b0c5406 846 .nway_reset = bcmgenet_nway_reset,
1c1008c7
FF		 847};
848
849/* Power down the unimac, based on mode. */
ca8cf341 850static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 851 enum bcmgenet_power_mode mode)
852{
ca8cf341 853 int ret = 0;
1c1008c7
FF		 854 u32 reg;
855
856 switch (mode) {
857 case GENET_POWER_CABLE_SENSE:
80d8e96d 858 phy_detach(priv->phydev);
1c1008c7
FF		 859 break;
860
c3ae64ae 861 case GENET_POWER_WOL_MAGIC:
ca8cf341 862 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 863 break;
864
1c1008c7
FF		 865 case GENET_POWER_PASSIVE:
866 /* Power down LED */
1c1008c7
FF		 867 if (priv->hw_params->flags & GENET_HAS_EXT) {
868 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
869 reg |= (EXT_PWR_DOWN_PHY |
870 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
871 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 872
873 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 874 }
875 break;
876 default:
877 break;
878 }
ca8cf341
FF		 879
880 return 0;
1c1008c7
FF		 881}
882
883static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 884 enum bcmgenet_power_mode mode)
1c1008c7
FF		 885{
886 u32 reg;
887
888 if (!(priv->hw_params->flags & GENET_HAS_EXT))
889 return;
890
891 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
892
893 switch (mode) {
894 case GENET_POWER_PASSIVE:
895 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
896 EXT_PWR_DOWN_BIAS);
897 /* fallthrough */
898 case GENET_POWER_CABLE_SENSE:
899 /* enable APD */
900 reg |= EXT_PWR_DN_EN_LD;
901 break;
c3ae64ae
FF		 902 case GENET_POWER_WOL_MAGIC:
903 bcmgenet_wol_power_up_cfg(priv, mode);
904 return;
1c1008c7
FF		 905 default:
906 break;
907 }
908
909 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
cc013fb4
FF		 910
911 if (mode == GENET_POWER_PASSIVE)
912 bcmgenet_mii_reset(priv->dev);
1c1008c7
FF		 913}
914
915/* ioctl handle special commands that are not present in ethtool. */
916static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
917{
918 struct bcmgenet_priv *priv = netdev_priv(dev);
919 int val = 0;
920
921 if (!netif_running(dev))
922 return -EINVAL;
923
924 switch (cmd) {
925 case SIOCGMIIPHY:
926 case SIOCGMIIREG:
927 case SIOCSMIIREG:
928 if (!priv->phydev)
929 val = -ENODEV;
930 else
931 val = phy_mii_ioctl(priv->phydev, rq, cmd);
932 break;
933
934 default:
935 val = -EINVAL;
936 break;
937 }
938
939 return val;
940}
941
942static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
943 struct bcmgenet_tx_ring *ring)
944{
945 struct enet_cb *tx_cb_ptr;
946
947 tx_cb_ptr = ring->cbs;
948 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 949
1c1008c7
FF		 950 /* Advancing local write pointer */
951 if (ring->write_ptr == ring->end_ptr)
952 ring->write_ptr = ring->cb_ptr;
953 else
954 ring->write_ptr++;
955
956 return tx_cb_ptr;
957}
958
959/* Simple helper to free a control block's resources */
960static void bcmgenet_free_cb(struct enet_cb *cb)
961{
962 dev_kfree_skb_any(cb->skb);
963 cb->skb = NULL;
964 dma_unmap_addr_set(cb, dma_addr, 0);
965}
966
9dbac28f 967static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 968{
9dbac28f 969 bcmgenet_intrl2_0_writel(ring->priv,
c91b7f66
FF		 970 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
971 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 972}
973
9dbac28f 974static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 975{
9dbac28f 976 bcmgenet_intrl2_0_writel(ring->priv,
c91b7f66
FF		 977 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
978 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 979}
980
9dbac28f 981static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 982{
9dbac28f 983 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 984 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 985}
986
9dbac28f 987static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 988{
9dbac28f 989 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 990 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 991}
992
993/* Unlocked version of the reclaim routine */
4092e6ac
JS		 994static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
995 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 996{
997 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 998 struct enet_cb *tx_cb_ptr;
b2cde2cc 999 struct netdev_queue *txq;
4092e6ac 1000 unsigned int pkts_compl = 0;
1c1008c7 1001 unsigned int c_index;
66d06757
PG		 1002 unsigned int txbds_ready;
1003 unsigned int txbds_processed = 0;
1c1008c7 1004
7fc527f9 1005 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 1006 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 1007 c_index &= DMA_C_INDEX_MASK;
1c1008c7 1008
66d06757
PG		 1009 if (likely(c_index >= ring->c_index))
1010 txbds_ready = c_index - ring->c_index;
1c1008c7 1011 else
66d06757 1012 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 1013
1014 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1015 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1016 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1017
1018 /* Reclaim transmitted buffers */
66d06757
PG		 1019 while (txbds_processed < txbds_ready) {
1020 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1021 if (tx_cb_ptr->skb) {
4092e6ac 1022 pkts_compl++;
66d06757 1023 dev->stats.tx_packets++;
1c1008c7
FF		 1024 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1025 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1026 dma_unmap_addr(tx_cb_ptr, dma_addr),
1027 tx_cb_ptr->skb->len,
1028 DMA_TO_DEVICE);
1c1008c7
FF		 1029 bcmgenet_free_cb(tx_cb_ptr);
1030 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1031 dev->stats.tx_bytes +=
1032 dma_unmap_len(tx_cb_ptr, dma_len);
1033 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1034 dma_unmap_addr(tx_cb_ptr, dma_addr),
1035 dma_unmap_len(tx_cb_ptr, dma_len),
1036 DMA_TO_DEVICE);
1c1008c7
FF		 1037 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1038 }
1c1008c7 1039
66d06757
PG		 1040 txbds_processed++;
1041 if (likely(ring->clean_ptr < ring->end_ptr))
1042 ring->clean_ptr++;
1043 else
1044 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1045 }
1046
66d06757
PG		 1047 ring->free_bds += txbds_processed;
1048 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1049
4092e6ac 1050 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
66d06757 1051 txq = netdev_get_tx_queue(dev, ring->queue);
4092e6ac
JS		 1052 if (netif_tx_queue_stopped(txq))
1053 netif_tx_wake_queue(txq);
1054 }
1c1008c7 1055
4092e6ac 1056 return pkts_compl;
1c1008c7
FF		 1057}
1058
4092e6ac 1059static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1060 struct bcmgenet_tx_ring *ring)
1c1008c7 1061{
4092e6ac 1062 unsigned int released;
1c1008c7
FF		 1063 unsigned long flags;
1064
1065 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1066 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1067 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1068
1069 return released;
1070}
1071
1072static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1073{
1074 struct bcmgenet_tx_ring *ring =
1075 container_of(napi, struct bcmgenet_tx_ring, napi);
1076 unsigned int work_done = 0;
1077
1078 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1079
1080 if (work_done == 0) {
1081 napi_complete(napi);
9dbac28f 1082 ring->int_enable(ring);
4092e6ac
JS		 1083
1084 return 0;
1085 }
1086
1087 return budget;
1c1008c7
FF		 1088}
1089
1090static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1091{
1092 struct bcmgenet_priv *priv = netdev_priv(dev);
1093 int i;
1094
1095 if (netif_is_multiqueue(dev)) {
1096 for (i = 0; i < priv->hw_params->tx_queues; i++)
1097 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1098 }
1099
1100 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1101}
1102
1103/* Transmits a single SKB (either head of a fragment or a single SKB)
1104 * caller must hold priv->lock
1105 */
1106static int bcmgenet_xmit_single(struct net_device *dev,
1107 struct sk_buff *skb,
1108 u16 dma_desc_flags,
1109 struct bcmgenet_tx_ring *ring)
1110{
1111 struct bcmgenet_priv *priv = netdev_priv(dev);
1112 struct device *kdev = &priv->pdev->dev;
1113 struct enet_cb *tx_cb_ptr;
1114 unsigned int skb_len;
1115 dma_addr_t mapping;
1116 u32 length_status;
1117 int ret;
1118
1119 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1120
1121 if (unlikely(!tx_cb_ptr))
1122 BUG();
1123
1124 tx_cb_ptr->skb = skb;
1125
1126 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1127
1128 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1129 ret = dma_mapping_error(kdev, mapping);
1130 if (ret) {
44c8bc3c 1131 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1132 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1133 dev_kfree_skb(skb);
1134 return ret;
1135 }
1136
1137 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1138 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1139 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1140 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1141 DMA_TX_APPEND_CRC;
1142
1143 if (skb->ip_summed == CHECKSUM_PARTIAL)
1144 length_status |= DMA_TX_DO_CSUM;
1145
1146 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1147
1c1008c7
FF		 1148 return 0;
1149}
1150
7fc527f9 1151/* Transmit a SKB fragment */
1c1008c7 1152static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1153 skb_frag_t *frag,
1154 u16 dma_desc_flags,
1155 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1156{
1157 struct bcmgenet_priv *priv = netdev_priv(dev);
1158 struct device *kdev = &priv->pdev->dev;
1159 struct enet_cb *tx_cb_ptr;
1160 dma_addr_t mapping;
1161 int ret;
1162
1163 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1164
1165 if (unlikely(!tx_cb_ptr))
1166 BUG();
1167 tx_cb_ptr->skb = NULL;
1168
1169 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1170 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1171 ret = dma_mapping_error(kdev, mapping);
1172 if (ret) {
44c8bc3c 1173 priv->mib.tx_dma_failed++;
1c1008c7 1174 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1175 __func__);
1c1008c7
FF		 1176 return ret;
1177 }
1178
1179 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1180 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1181
1182 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1183 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1184 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7 1185
1c1008c7
FF		 1186 return 0;
1187}
1188
1189/* Reallocate the SKB to put enough headroom in front of it and insert
1190 * the transmit checksum offsets in the descriptors
1191 */
bc23333b
PG		 1192static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1193 struct sk_buff *skb)
1c1008c7
FF		 1194{
1195 struct status_64 *status = NULL;
1196 struct sk_buff *new_skb;
1197 u16 offset;
1198 u8 ip_proto;
1199 u16 ip_ver;
1200 u32 tx_csum_info;
1201
1202 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1203 /* If 64 byte status block enabled, must make sure skb has
1204 * enough headroom for us to insert 64B status block.
1205 */
1206 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1207 dev_kfree_skb(skb);
1208 if (!new_skb) {
1209 dev->stats.tx_errors++;
1210 dev->stats.tx_dropped++;
bc23333b 1211 return NULL;
1c1008c7
FF		 1212 }
1213 skb = new_skb;
1214 }
1215
1216 skb_push(skb, sizeof(*status));
1217 status = (struct status_64 *)skb->data;
1218
1219 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1220 ip_ver = htons(skb->protocol);
1221 switch (ip_ver) {
1222 case ETH_P_IP:
1223 ip_proto = ip_hdr(skb)->protocol;
1224 break;
1225 case ETH_P_IPV6:
1226 ip_proto = ipv6_hdr(skb)->nexthdr;
1227 break;
1228 default:
bc23333b 1229 return skb;
1c1008c7
FF		 1230 }
1231
1232 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1233 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1234 (offset + skb->csum_offset);
1235
1236 /* Set the length valid bit for TCP and UDP and just set
1237 * the special UDP flag for IPv4, else just set to 0.
1238 */
1239 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1240 tx_csum_info |= STATUS_TX_CSUM_LV;
1241 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1242 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1243 } else {
1c1008c7 1244 tx_csum_info = 0;
8900ea57 1245 }
1c1008c7
FF		 1246
1247 status->tx_csum_info = tx_csum_info;
1248 }
1249
bc23333b 1250 return skb;
1c1008c7
FF		 1251}
1252
1253static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1254{
1255 struct bcmgenet_priv *priv = netdev_priv(dev);
1256 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1257 struct netdev_queue *txq;
1c1008c7
FF		 1258 unsigned long flags = 0;
1259 int nr_frags, index;
1260 u16 dma_desc_flags;
1261 int ret;
1262 int i;
1263
1264 index = skb_get_queue_mapping(skb);
1265 /* Mapping strategy:
1266 * queue_mapping = 0, unclassified, packet xmited through ring16
1267 * queue_mapping = 1, goes to ring 0. (highest priority queue
1268 * queue_mapping = 2, goes to ring 1.
1269 * queue_mapping = 3, goes to ring 2.
1270 * queue_mapping = 4, goes to ring 3.
1271 */
1272 if (index == 0)
1273 index = DESC_INDEX;
1274 else
1275 index -= 1;
1276
1c1008c7
FF		 1277 nr_frags = skb_shinfo(skb)->nr_frags;
1278 ring = &priv->tx_rings[index];
b2cde2cc 1279 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1280
1281 spin_lock_irqsave(&ring->lock, flags);
1282 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1283 netif_tx_stop_queue(txq);
1c1008c7 1284 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1285 __func__, index, ring->queue);
1c1008c7
FF		 1286 ret = NETDEV_TX_BUSY;
1287 goto out;
1288 }
1289
474ea9ca
FF		 1290 if (skb_padto(skb, ETH_ZLEN)) {
1291 ret = NETDEV_TX_OK;
1292 goto out;
1293 }
1294
1c1008c7
FF		 1295 /* set the SKB transmit checksum */
1296 if (priv->desc_64b_en) {
bc23333b
PG		 1297 skb = bcmgenet_put_tx_csum(dev, skb);
1298 if (!skb) {
1c1008c7
FF		 1299 ret = NETDEV_TX_OK;
1300 goto out;
1301 }
1302 }
1303
1304 dma_desc_flags = DMA_SOP;
1305 if (nr_frags == 0)
1306 dma_desc_flags |= DMA_EOP;
1307
1308 /* Transmit single SKB or head of fragment list */
1309 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1310 if (ret) {
1311 ret = NETDEV_TX_OK;
1312 goto out;
1313 }
1314
1315 /* xmit fragment */
1316 for (i = 0; i < nr_frags; i++) {
1317 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1318 &skb_shinfo(skb)->frags[i],
1319 (i == nr_frags - 1) ? DMA_EOP : 0,
1320 ring);
1c1008c7
FF		 1321 if (ret) {
1322 ret = NETDEV_TX_OK;
1323 goto out;
1324 }
1325 }
1326
d03825fb
FF		 1327 skb_tx_timestamp(skb);
1328
ae67bf01
FF		 1329 /* Decrement total BD count and advance our write pointer */
1330 ring->free_bds -= nr_frags + 1;
1331 ring->prod_index += nr_frags + 1;
1332 ring->prod_index &= DMA_P_INDEX_MASK;
1333
4092e6ac 1334 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1335 netif_tx_stop_queue(txq);
1c1008c7 1336
ddd0ca5d
FF		 1337 if (!skb->xmit_more || netif_xmit_stopped(txq))
1338 /* Packets are ready, update producer index */
1339 bcmgenet_tdma_ring_writel(priv, ring->index,
1340 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1341out:
1342 spin_unlock_irqrestore(&ring->lock, flags);
1343
1344 return ret;
1345}
1346
d6707bec
PG		 1347static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1348 struct enet_cb *cb)
1c1008c7
FF		 1349{
1350 struct device *kdev = &priv->pdev->dev;
1351 struct sk_buff *skb;
d6707bec 1352 struct sk_buff *rx_skb;
1c1008c7 1353 dma_addr_t mapping;
1c1008c7 1354
d6707bec 1355 /* Allocate a new Rx skb */
c91b7f66 1356 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
d6707bec
PG		 1357 if (!skb) {
1358 priv->mib.alloc_rx_buff_failed++;
1359 netif_err(priv, rx_err, priv->dev,
1360 "%s: Rx skb allocation failed\n", __func__);
1361 return NULL;
1362 }
1c1008c7 1363
d6707bec
PG		 1364 /* DMA-map the new Rx skb */
1365 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1366 DMA_FROM_DEVICE);
1367 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 1368 priv->mib.rx_dma_failed++;
d6707bec 1369 dev_kfree_skb_any(skb);
1c1008c7 1370 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 1371 "%s: Rx skb DMA mapping failed\n", __func__);
1372 return NULL;
1c1008c7
FF		 1373 }
1374
d6707bec
PG		 1375 /* Grab the current Rx skb from the ring and DMA-unmap it */
1376 rx_skb = cb->skb;
1377 if (likely(rx_skb))
1378 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1379 priv->rx_buf_len, DMA_FROM_DEVICE);
1380
1381 /* Put the new Rx skb on the ring */
1382 cb->skb = skb;
1c1008c7 1383 dma_unmap_addr_set(cb, dma_addr, mapping);
8ac467e8 1384 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 1385
d6707bec
PG		 1386 /* Return the current Rx skb to caller */
1387 return rx_skb;
1c1008c7
FF		 1388}
1389
1390/* bcmgenet_desc_rx - descriptor based rx process.
1391 * this could be called from bottom half, or from NAPI polling method.
1392 */
1393static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
8ac467e8 1394 unsigned int index,
1c1008c7
FF		 1395 unsigned int budget)
1396{
8ac467e8 1397 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 1398 struct net_device *dev = priv->dev;
1399 struct enet_cb *cb;
1400 struct sk_buff *skb;
1401 u32 dma_length_status;
1402 unsigned long dma_flag;
d6707bec 1403 int len;
1c1008c7
FF		 1404 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1405 unsigned int p_index;
d26ea6cc 1406 unsigned int discards;
1c1008c7
FF		 1407 unsigned int chksum_ok = 0;
1408
8ac467e8 1409 p_index = bcmgenet_rdma_ring_readl(priv, index, RDMA_PROD_INDEX);
d26ea6cc
PG		 1410
1411 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1412 DMA_P_INDEX_DISCARD_CNT_MASK;
1413 if (discards > ring->old_discards) {
1414 discards = discards - ring->old_discards;
1415 dev->stats.rx_missed_errors += discards;
1416 dev->stats.rx_errors += discards;
1417 ring->old_discards += discards;
1418
1419 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1420 if (ring->old_discards >= 0xC000) {
1421 ring->old_discards = 0;
1422 bcmgenet_rdma_ring_writel(priv, index, 0,
1423 RDMA_PROD_INDEX);
1424 }
1425 }
1426
1c1008c7
FF		 1427 p_index &= DMA_P_INDEX_MASK;
1428
8ac467e8
PG		 1429 if (likely(p_index >= ring->c_index))
1430 rxpkttoprocess = p_index - ring->c_index;
1c1008c7 1431 else
8ac467e8
PG		 1432 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1433 p_index;
1c1008c7
FF		 1434
1435 netif_dbg(priv, rx_status, dev,
c91b7f66 1436 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1437
1438 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1439 (rxpktprocessed < budget)) {
8ac467e8 1440 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 1441 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 1442
b629be5c
FF		 1443 if (unlikely(!skb)) {
1444 dev->stats.rx_dropped++;
1445 dev->stats.rx_errors++;
d6707bec 1446 goto next;
b629be5c
FF		 1447 }
1448
1c1008c7 1449 if (!priv->desc_64b_en) {
c91b7f66 1450 dma_length_status =
8ac467e8 1451 dmadesc_get_length_status(priv, cb->bd_addr);
1c1008c7
FF		 1452 } else {
1453 struct status_64 *status;
164d4f20 1454
1c1008c7
FF		 1455 status = (struct status_64 *)skb->data;
1456 dma_length_status = status->length_status;
1457 }
1458
1459 /* DMA flags and length are still valid no matter how
1460 * we got the Receive Status Vector (64B RSB or register)
1461 */
1462 dma_flag = dma_length_status & 0xffff;
1463 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1464
1465 netif_dbg(priv, rx_status, dev,
c91b7f66 1466 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1467 __func__, p_index, ring->c_index,
1468 ring->read_ptr, dma_length_status);
1c1008c7 1469
1c1008c7
FF		 1470 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1471 netif_err(priv, rx_status, dev,
c91b7f66 1472 "dropping fragmented packet!\n");
1c1008c7
FF		 1473 dev->stats.rx_dropped++;
1474 dev->stats.rx_errors++;
d6707bec
PG		 1475 dev_kfree_skb_any(skb);
1476 goto next;
1c1008c7 1477 }
d6707bec 1478
1c1008c7
FF		 1479 /* report errors */
1480 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1481 DMA_RX_OV |
1482 DMA_RX_NO |
1483 DMA_RX_LG |
1484 DMA_RX_RXER))) {
1485 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1486 (unsigned int)dma_flag);
1c1008c7
FF		 1487 if (dma_flag & DMA_RX_CRC_ERROR)
1488 dev->stats.rx_crc_errors++;
1489 if (dma_flag & DMA_RX_OV)
1490 dev->stats.rx_over_errors++;
1491 if (dma_flag & DMA_RX_NO)
1492 dev->stats.rx_frame_errors++;
1493 if (dma_flag & DMA_RX_LG)
1494 dev->stats.rx_length_errors++;
1495 dev->stats.rx_dropped++;
1496 dev->stats.rx_errors++;
d6707bec
PG		 1497 dev_kfree_skb_any(skb);
1498 goto next;
1c1008c7
FF		 1499 } /* error packet */
1500
1501 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1502 priv->desc_rxchk_en;
1c1008c7
FF		 1503
1504 skb_put(skb, len);
1505 if (priv->desc_64b_en) {
1506 skb_pull(skb, 64);
1507 len -= 64;
1508 }
1509
1510 if (likely(chksum_ok))
1511 skb->ip_summed = CHECKSUM_UNNECESSARY;
1512
1513 /* remove hardware 2bytes added for IP alignment */
1514 skb_pull(skb, 2);
1515 len -= 2;
1516
1517 if (priv->crc_fwd_en) {
1518 skb_trim(skb, len - ETH_FCS_LEN);
1519 len -= ETH_FCS_LEN;
1520 }
1521
1522 /*Finish setting up the received SKB and send it to the kernel*/
1523 skb->protocol = eth_type_trans(skb, priv->dev);
1524 dev->stats.rx_packets++;
1525 dev->stats.rx_bytes += len;
1526 if (dma_flag & DMA_RX_MULT)
1527 dev->stats.multicast++;
1528
1529 /* Notify kernel */
1530 napi_gro_receive(&priv->napi, skb);
1c1008c7
FF		 1531 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1532
d6707bec 1533next:
cf377d88 1534 rxpktprocessed++;
8ac467e8
PG		 1535 if (likely(ring->read_ptr < ring->end_ptr))
1536 ring->read_ptr++;
1537 else
1538 ring->read_ptr = ring->cb_ptr;
1539
1540 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1541 bcmgenet_rdma_ring_writel(priv, index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1542 }
1543
1544 return rxpktprocessed;
1545}
1546
1547/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1548static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1549 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1550{
1551 struct enet_cb *cb;
d6707bec 1552 struct sk_buff *skb;
1c1008c7
FF		 1553 int i;
1554
8ac467e8 1555 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1556
1557 /* loop here for each buffer needing assign */
8ac467e8
PG		 1558 for (i = 0; i < ring->size; i++) {
1559 cb = ring->cbs + i;
d6707bec
PG		 1560 skb = bcmgenet_rx_refill(priv, cb);
1561 if (skb)
1562 dev_kfree_skb_any(skb);
1563 if (!cb->skb)
1564 return -ENOMEM;
1c1008c7
FF		 1565 }
1566
d6707bec 1567 return 0;
1c1008c7
FF		 1568}
1569
1570static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1571{
1572 struct enet_cb *cb;
1573 int i;
1574
1575 for (i = 0; i < priv->num_rx_bds; i++) {
1576 cb = &priv->rx_cbs[i];
1577
1578 if (dma_unmap_addr(cb, dma_addr)) {
1579 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1580 dma_unmap_addr(cb, dma_addr),
1581 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1582 dma_unmap_addr_set(cb, dma_addr, 0);
1583 }
1584
1585 if (cb->skb)
1586 bcmgenet_free_cb(cb);
1587 }
1588}
1589
c91b7f66 1590static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1591{
1592 u32 reg;
1593
1594 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1595 if (enable)
1596 reg |= mask;
1597 else
1598 reg &= ~mask;
1599 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1600
1601 /* UniMAC stops on a packet boundary, wait for a full-size packet
1602 * to be processed
1603 */
1604 if (enable == 0)
1605 usleep_range(1000, 2000);
1606}
1607
1c1008c7
FF		 1608static int reset_umac(struct bcmgenet_priv *priv)
1609{
1610 struct device *kdev = &priv->pdev->dev;
1611 unsigned int timeout = 0;
1612 u32 reg;
1613
1614 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1615 bcmgenet_rbuf_ctrl_set(priv, 0);
1616 udelay(10);
1617
1618 /* disable MAC while updating its registers */
1619 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1620
1621 /* issue soft reset, wait for it to complete */
1622 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1623 while (timeout++ < 1000) {
1624 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1625 if (!(reg & CMD_SW_RESET))
1626 return 0;
1627
1628 udelay(1);
1629 }
1630
1631 if (timeout == 1000) {
1632 dev_err(kdev,
7fc527f9 1633 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1634 return -ETIMEDOUT;
1635 }
1636
1637 return 0;
1638}
1639
909ff5ef
FF		 1640static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1641{
1642 /* Mask all interrupts.*/
1643 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1644 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1645 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1646 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1647 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1648 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1649}
1650
1c1008c7
FF		 1651static int init_umac(struct bcmgenet_priv *priv)
1652{
1653 struct device *kdev = &priv->pdev->dev;
1654 int ret;
b2e97eca
PG		 1655 u32 reg;
1656 u32 int0_enable = 0;
1657 u32 int1_enable = 0;
1658 int i;
1c1008c7
FF		 1659
1660 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1661
1662 ret = reset_umac(priv);
1663 if (ret)
1664 return ret;
1665
1666 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1667 /* clear tx/rx counter */
1668 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1669 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1670 UMAC_MIB_CTRL);
1c1008c7
FF		 1671 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1672
1673 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1674
1675 /* init rx registers, enable ip header optimization */
1676 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1677 reg |= RBUF_ALIGN_2B;
1678 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1679
1680 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1681 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1682
909ff5ef 1683 bcmgenet_intr_disable(priv);
1c1008c7 1684
b2e97eca
PG		 1685 /* Enable Rx default queue 16 interrupts */
1686 int0_enable |= (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE);
1c1008c7 1687
b2e97eca
PG		 1688 /* Enable Tx default queue 16 interrupts */
1689 int0_enable |= (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE);
1c1008c7 1690
7fc527f9 1691 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1692 if (phy_is_internal(priv->phydev)) {
b2e97eca 1693 int0_enable |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1694 } else if (priv->ext_phy) {
b2e97eca 1695 int0_enable |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1696 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1697 reg = bcmgenet_bp_mc_get(priv);
1698 reg |= BIT(priv->hw_params->bp_in_en_shift);
1699
1700 /* bp_mask: back pressure mask */
1701 if (netif_is_multiqueue(priv->dev))
1702 reg |= priv->hw_params->bp_in_mask;
1703 else
1704 reg &= ~priv->hw_params->bp_in_mask;
1705 bcmgenet_bp_mc_set(priv, reg);
1706 }
1707
1708 /* Enable MDIO interrupts on GENET v3+ */
1709 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 1710 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 1711
b2e97eca
PG		 1712 /* Enable Tx priority queue interrupts */
1713 for (i = 0; i < priv->hw_params->tx_queues; ++i)
1714 int1_enable |= (1 << i);
1c1008c7 1715
b2e97eca
PG		 1716 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1717 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 1718
1c1008c7
FF		 1719 /* Enable rx/tx engine.*/
1720 dev_dbg(kdev, "done init umac\n");
1721
1722 return 0;
1723}
1724
4f8b2d7d 1725/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1726static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1727 unsigned int index, unsigned int size,
4f8b2d7d 1728 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1729{
1730 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1731 u32 words_per_bd = WORDS_PER_BD(priv);
1732 u32 flow_period_val = 0;
1c1008c7
FF		 1733
1734 spin_lock_init(&ring->lock);
4092e6ac
JS		 1735 ring->priv = priv;
1736 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1c1008c7
FF		 1737 ring->index = index;
1738 if (index == DESC_INDEX) {
1739 ring->queue = 0;
1740 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1741 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1742 } else {
1743 ring->queue = index + 1;
1744 ring->int_enable = bcmgenet_tx_ring_int_enable;
1745 ring->int_disable = bcmgenet_tx_ring_int_disable;
1746 }
4f8b2d7d 1747 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1748 ring->size = size;
66d06757 1749 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1750 ring->c_index = 0;
1751 ring->free_bds = size;
4f8b2d7d
PG		 1752 ring->write_ptr = start_ptr;
1753 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1754 ring->end_ptr = end_ptr - 1;
1755 ring->prod_index = 0;
1756
1757 /* Set flow period for ring != 16 */
1758 if (index != DESC_INDEX)
1759 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1760
1761 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1762 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1763 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1764 /* Disable rate control for now */
1765 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1766 TDMA_FLOW_PERIOD);
1c1008c7 1767 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1768 ((size << DMA_RING_SIZE_SHIFT) |
1769 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1770
1c1008c7 1771 /* Set start and end address, read and write pointers */
4f8b2d7d 1772 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1773 DMA_START_ADDR);
4f8b2d7d 1774 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1775 TDMA_READ_PTR);
4f8b2d7d 1776 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1777 TDMA_WRITE_PTR);
1c1008c7 1778 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1779 DMA_END_ADDR);
4092e6ac
JS		 1780
1781 napi_enable(&ring->napi);
1782}
1783
1784static void bcmgenet_fini_tx_ring(struct bcmgenet_priv *priv,
1785 unsigned int index)
1786{
1787 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1788
1789 napi_disable(&ring->napi);
1790 netif_napi_del(&ring->napi);
1c1008c7
FF		 1791}
1792
1793/* Initialize a RDMA ring */
1794static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 1795 unsigned int index, unsigned int size,
1796 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 1797{
8ac467e8 1798 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 1799 u32 words_per_bd = WORDS_PER_BD(priv);
1800 int ret;
1801
8ac467e8
PG		 1802 ring->index = index;
1803 ring->cbs = priv->rx_cbs + start_ptr;
1804 ring->size = size;
1805 ring->c_index = 0;
1806 ring->read_ptr = start_ptr;
1807 ring->cb_ptr = start_ptr;
1808 ring->end_ptr = end_ptr - 1;
1c1008c7 1809
8ac467e8
PG		 1810 ret = bcmgenet_alloc_rx_buffers(priv, ring);
1811 if (ret)
1c1008c7 1812 return ret;
1c1008c7 1813
1c1008c7
FF		 1814 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1815 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 1816 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 1817 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1818 ((size << DMA_RING_SIZE_SHIFT) |
1819 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1820 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1821 (DMA_FC_THRESH_LO <<
1822 DMA_XOFF_THRESHOLD_SHIFT) |
1823 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 1824
1825 /* Set start and end address, read and write pointers */
8ac467e8
PG		 1826 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1827 DMA_START_ADDR);
1828 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1829 RDMA_READ_PTR);
1830 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1831 RDMA_WRITE_PTR);
1832 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 1833 DMA_END_ADDR);
1c1008c7
FF		 1834
1835 return ret;
1836}
1837
16c6d667 1838/* Initialize Tx queues
1c1008c7 1839 *
16c6d667 1840 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 1841 * with queue 0 being the highest priority queue.
1842 *
16c6d667 1843 * Queue 16 is the default Tx queue with
51a966a7 1844 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 1845 *
16c6d667
PG		 1846 * The transmit control block pool is then partitioned as follows:
1847 * - Tx queue 0 uses tx_cbs[0..31]
1848 * - Tx queue 1 uses tx_cbs[32..63]
1849 * - Tx queue 2 uses tx_cbs[64..95]
1850 * - Tx queue 3 uses tx_cbs[96..127]
1851 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 1852 */
16c6d667 1853static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 1854{
1855 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 1856 u32 i, dma_enable;
1857 u32 dma_ctrl, ring_cfg;
37742166 1858 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 1859
1c1008c7
FF		 1860 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1861 dma_enable = dma_ctrl & DMA_EN;
1862 dma_ctrl &= ~DMA_EN;
1863 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1864
16c6d667
PG		 1865 dma_ctrl = 0;
1866 ring_cfg = 0;
1867
1c1008c7
FF		 1868 /* Enable strict priority arbiter mode */
1869 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1870
16c6d667 1871 /* Initialize Tx priority queues */
1c1008c7 1872 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 1873 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
1874 i * priv->hw_params->tx_bds_per_q,
1875 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 1876 ring_cfg |= (1 << i);
1877 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1878 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1879 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 1880 }
1881
16c6d667 1882 /* Initialize Tx default queue 16 */
51a966a7 1883 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 1884 priv->hw_params->tx_queues *
51a966a7 1885 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 1886 TOTAL_DESC);
1887 ring_cfg |= (1 << DESC_INDEX);
1888 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1889 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1890 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1891 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 1892
1893 /* Set Tx queue priorities */
37742166
PG		 1894 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1895 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1896 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1897
16c6d667
PG		 1898 /* Enable Tx queues */
1899 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 1900
16c6d667 1901 /* Enable Tx DMA */
1c1008c7 1902 if (dma_enable)
16c6d667
PG		 1903 dma_ctrl |= DMA_EN;
1904 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 1905}
1906
8ac467e8
PG		 1907/* Initialize Rx queues
1908 *
1909 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
1910 * used to direct traffic to these queues.
1911 *
1912 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
1913 */
1914static int bcmgenet_init_rx_queues(struct net_device *dev)
1915{
1916 struct bcmgenet_priv *priv = netdev_priv(dev);
1917 u32 i;
1918 u32 dma_enable;
1919 u32 dma_ctrl;
1920 u32 ring_cfg;
1921 int ret;
1922
1923 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
1924 dma_enable = dma_ctrl & DMA_EN;
1925 dma_ctrl &= ~DMA_EN;
1926 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
1927
1928 dma_ctrl = 0;
1929 ring_cfg = 0;
1930
1931 /* Initialize Rx priority queues */
1932 for (i = 0; i < priv->hw_params->rx_queues; i++) {
1933 ret = bcmgenet_init_rx_ring(priv, i,
1934 priv->hw_params->rx_bds_per_q,
1935 i * priv->hw_params->rx_bds_per_q,
1936 (i + 1) *
1937 priv->hw_params->rx_bds_per_q);
1938 if (ret)
1939 return ret;
1940
1941 ring_cfg |= (1 << i);
1942 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
1943 }
1944
1945 /* Initialize Rx default queue 16 */
1946 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
1947 priv->hw_params->rx_queues *
1948 priv->hw_params->rx_bds_per_q,
1949 TOTAL_DESC);
1950 if (ret)
1951 return ret;
1952
1953 ring_cfg |= (1 << DESC_INDEX);
1954 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
1955
1956 /* Enable rings */
1957 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
1958
1959 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1960 if (dma_enable)
1961 dma_ctrl |= DMA_EN;
1962 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
1963
1964 return 0;
1965}
1966
4a0c081e
FF		 1967static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1968{
1969 int ret = 0;
1970 int timeout = 0;
1971 u32 reg;
1972
1973 /* Disable TDMA to stop add more frames in TX DMA */
1974 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1975 reg &= ~DMA_EN;
1976 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1977
1978 /* Check TDMA status register to confirm TDMA is disabled */
1979 while (timeout++ < DMA_TIMEOUT_VAL) {
1980 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1981 if (reg & DMA_DISABLED)
1982 break;
1983
1984 udelay(1);
1985 }
1986
1987 if (timeout == DMA_TIMEOUT_VAL) {
1988 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1989 ret = -ETIMEDOUT;
1990 }
1991
1992 /* Wait 10ms for packet drain in both tx and rx dma */
1993 usleep_range(10000, 20000);
1994
1995 /* Disable RDMA */
1996 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1997 reg &= ~DMA_EN;
1998 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1999
2000 timeout = 0;
2001 /* Check RDMA status register to confirm RDMA is disabled */
2002 while (timeout++ < DMA_TIMEOUT_VAL) {
2003 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2004 if (reg & DMA_DISABLED)
2005 break;
2006
2007 udelay(1);
2008 }
2009
2010 if (timeout == DMA_TIMEOUT_VAL) {
2011 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2012 ret = -ETIMEDOUT;
2013 }
2014
2015 return ret;
2016}
2017
4092e6ac 2018static void __bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 2019{
2020 int i;
2021
2022 /* disable DMA */
4a0c081e 2023 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2024
2025 for (i = 0; i < priv->num_tx_bds; i++) {
2026 if (priv->tx_cbs[i].skb != NULL) {
2027 dev_kfree_skb(priv->tx_cbs[i].skb);
2028 priv->tx_cbs[i].skb = NULL;
2029 }
2030 }
2031
2032 bcmgenet_free_rx_buffers(priv);
2033 kfree(priv->rx_cbs);
2034 kfree(priv->tx_cbs);
2035}
2036
4092e6ac
JS		 2037static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2038{
2039 int i;
2040
2041 bcmgenet_fini_tx_ring(priv, DESC_INDEX);
2042
2043 for (i = 0; i < priv->hw_params->tx_queues; i++)
2044 bcmgenet_fini_tx_ring(priv, i);
2045
2046 __bcmgenet_fini_dma(priv);
2047}
2048
1c1008c7
FF		 2049/* init_edma: Initialize DMA control register */
2050static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2051{
2052 int ret;
014012a4
PG		 2053 unsigned int i;
2054 struct enet_cb *cb;
1c1008c7 2055
6f5a272c 2056 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2057
6f5a272c
PG		 2058 /* Initialize common Rx ring structures */
2059 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2060 priv->num_rx_bds = TOTAL_DESC;
2061 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2062 GFP_KERNEL);
2063 if (!priv->rx_cbs)
2064 return -ENOMEM;
2065
2066 for (i = 0; i < priv->num_rx_bds; i++) {
2067 cb = priv->rx_cbs + i;
2068 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2069 }
2070
7fc527f9 2071 /* Initialize common TX ring structures */
1c1008c7
FF		 2072 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2073 priv->num_tx_bds = TOTAL_DESC;
c489be08 2074 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2075 GFP_KERNEL);
1c1008c7 2076 if (!priv->tx_cbs) {
ebbd96fb 2077 kfree(priv->rx_cbs);
1c1008c7
FF		 2078 return -ENOMEM;
2079 }
2080
014012a4
PG		 2081 for (i = 0; i < priv->num_tx_bds; i++) {
2082 cb = priv->tx_cbs + i;
2083 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2084 }
2085
ebbd96fb
PG		 2086 /* Init rDma */
2087 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2088
2089 /* Initialize Rx queues */
2090 ret = bcmgenet_init_rx_queues(priv->dev);
2091 if (ret) {
2092 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2093 bcmgenet_free_rx_buffers(priv);
2094 kfree(priv->rx_cbs);
2095 kfree(priv->tx_cbs);
2096 return ret;
2097 }
2098
2099 /* Init tDma */
2100 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2101
16c6d667
PG		 2102 /* Initialize Tx queues */
2103 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2104
2105 return 0;
2106}
2107
2108/* NAPI polling method*/
2109static int bcmgenet_poll(struct napi_struct *napi, int budget)
2110{
2111 struct bcmgenet_priv *priv = container_of(napi,
2112 struct bcmgenet_priv, napi);
2113 unsigned int work_done;
2114
8ac467e8 2115 work_done = bcmgenet_desc_rx(priv, DESC_INDEX, budget);
1c1008c7 2116
1c1008c7
FF		 2117 if (work_done < budget) {
2118 napi_complete(napi);
b2e97eca
PG		 2119 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE |
2120 UMAC_IRQ_RXDMA_PDONE,
c91b7f66 2121 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 2122 }
2123
2124 return work_done;
2125}
2126
2127/* Interrupt bottom half */
2128static void bcmgenet_irq_task(struct work_struct *work)
2129{
2130 struct bcmgenet_priv *priv = container_of(
2131 work, struct bcmgenet_priv, bcmgenet_irq_work);
2132
2133 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2134
8fdb0e0f
FF		 2135 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2136 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2137 netif_dbg(priv, wol, priv->dev,
2138 "magic packet detected, waking up\n");
2139 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2140 }
2141
1c1008c7
FF		 2142 /* Link UP/DOWN event */
2143 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2144 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d 2145 phy_mac_interrupt(priv->phydev,
c91b7f66 2146 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 2147 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
2148 }
2149}
2150
2151/* bcmgenet_isr1: interrupt handler for ring buffer. */
2152static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2153{
2154 struct bcmgenet_priv *priv = dev_id;
4092e6ac 2155 struct bcmgenet_tx_ring *ring;
1c1008c7
FF		 2156 unsigned int index;
2157
2158 /* Save irq status for bottom-half processing. */
2159 priv->irq1_stat =
2160 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2161 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2162 /* clear interrupts */
1c1008c7
FF		 2163 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2164
2165 netif_dbg(priv, intr, priv->dev,
c91b7f66 2166 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2167
1c1008c7
FF		 2168 /* Check the MBDONE interrupts.
2169 * packet is done, reclaim descriptors
2170 */
4092e6ac
JS		 2171 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2172 if (!(priv->irq1_stat & BIT(index)))
2173 continue;
2174
2175 ring = &priv->tx_rings[index];
2176
2177 if (likely(napi_schedule_prep(&ring->napi))) {
9dbac28f 2178 ring->int_disable(ring);
4092e6ac 2179 __napi_schedule(&ring->napi);
1c1008c7
FF		 2180 }
2181 }
4092e6ac 2182
1c1008c7
FF		 2183 return IRQ_HANDLED;
2184}
2185
2186/* bcmgenet_isr0: Handle various interrupts. */
2187static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2188{
2189 struct bcmgenet_priv *priv = dev_id;
2190
2191 /* Save irq status for bottom-half processing. */
2192 priv->irq0_stat =
2193 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2194 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2195 /* clear interrupts */
1c1008c7
FF		 2196 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2197
2198 netif_dbg(priv, intr, priv->dev,
c91b7f66 2199 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7
FF		 2200
2201 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
2202 /* We use NAPI(software interrupt throttling, if
2203 * Rx Descriptor throttling is not used.
2204 * Disable interrupt, will be enabled in the poll method.
2205 */
2206 if (likely(napi_schedule_prep(&priv->napi))) {
b2e97eca
PG		 2207 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE |
2208 UMAC_IRQ_RXDMA_PDONE,
c91b7f66 2209 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 2210 __napi_schedule(&priv->napi);
2211 }
2212 }
2213 if (priv->irq0_stat &
2214 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
4092e6ac
JS		 2215 struct bcmgenet_tx_ring *ring = &priv->tx_rings[DESC_INDEX];
2216
2217 if (likely(napi_schedule_prep(&ring->napi))) {
9dbac28f 2218 ring->int_disable(ring);
4092e6ac
JS		 2219 __napi_schedule(&ring->napi);
2220 }
1c1008c7
FF		 2221 }
2222 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2223 UMAC_IRQ_PHY_DET_F |
2224 UMAC_IRQ_LINK_UP |
2225 UMAC_IRQ_LINK_DOWN |
2226 UMAC_IRQ_HFB_SM |
2227 UMAC_IRQ_HFB_MM |
2228 UMAC_IRQ_MPD_R)) {
2229 /* all other interested interrupts handled in bottom half */
2230 schedule_work(&priv->bcmgenet_irq_work);
2231 }
2232
2233 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2234 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2235 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2236 wake_up(&priv->wq);
2237 }
2238
2239 return IRQ_HANDLED;
2240}
2241
8562056f
FF		 2242static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2243{
2244 struct bcmgenet_priv *priv = dev_id;
2245
2246 pm_wakeup_event(&priv->pdev->dev, 0);
2247
2248 return IRQ_HANDLED;
2249}
2250
1c1008c7
FF		 2251static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2252{
2253 u32 reg;
2254
2255 reg = bcmgenet_rbuf_ctrl_get(priv);
2256 reg |= BIT(1);
2257 bcmgenet_rbuf_ctrl_set(priv, reg);
2258 udelay(10);
2259
2260 reg &= ~BIT(1);
2261 bcmgenet_rbuf_ctrl_set(priv, reg);
2262 udelay(10);
2263}
2264
2265static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2266 unsigned char *addr)
1c1008c7
FF		 2267{
2268 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2269 (addr[2] << 8) | addr[3], UMAC_MAC0);
2270 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2271}
2272
1c1008c7
FF		 2273/* Returns a reusable dma control register value */
2274static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2275{
2276 u32 reg;
2277 u32 dma_ctrl;
2278
2279 /* disable DMA */
2280 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2281 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2282 reg &= ~dma_ctrl;
2283 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2284
2285 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2286 reg &= ~dma_ctrl;
2287 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2288
2289 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2290 udelay(10);
2291 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2292
2293 return dma_ctrl;
2294}
2295
2296static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2297{
2298 u32 reg;
2299
2300 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2301 reg |= dma_ctrl;
2302 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2303
2304 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2305 reg |= dma_ctrl;
2306 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2307}
2308
0034de41
PG		 2309static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2310 u32 f_index)
2311{
2312 u32 offset;
2313 u32 reg;
2314
2315 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2316 reg = bcmgenet_hfb_reg_readl(priv, offset);
2317 return !!(reg & (1 << (f_index % 32)));
2318}
2319
2320static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2321{
2322 u32 offset;
2323 u32 reg;
2324
2325 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2326 reg = bcmgenet_hfb_reg_readl(priv, offset);
2327 reg |= (1 << (f_index % 32));
2328 bcmgenet_hfb_reg_writel(priv, reg, offset);
2329}
2330
2331static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2332 u32 f_index, u32 rx_queue)
2333{
2334 u32 offset;
2335 u32 reg;
2336
2337 offset = f_index / 8;
2338 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2339 reg &= ~(0xF << (4 * (f_index % 8)));
2340 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2341 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2342}
2343
2344static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2345 u32 f_index, u32 f_length)
2346{
2347 u32 offset;
2348 u32 reg;
2349
2350 offset = HFB_FLT_LEN_V3PLUS +
2351 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2352 sizeof(u32);
2353 reg = bcmgenet_hfb_reg_readl(priv, offset);
2354 reg &= ~(0xFF << (8 * (f_index % 4)));
2355 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2356 bcmgenet_hfb_reg_writel(priv, reg, offset);
2357}
2358
2359static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2360{
2361 u32 f_index;
2362
2363 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2364 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2365 return f_index;
2366
2367 return -ENOMEM;
2368}
2369
2370/* bcmgenet_hfb_add_filter
2371 *
2372 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2373 * desired Rx queue.
2374 *
2375 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2376 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2377 *
2378 * bits 31:20 - unused
2379 * bit 19 - nibble 0 match enable
2380 * bit 18 - nibble 1 match enable
2381 * bit 17 - nibble 2 match enable
2382 * bit 16 - nibble 3 match enable
2383 * bits 15:12 - nibble 0 data
2384 * bits 11:8 - nibble 1 data
2385 * bits 7:4 - nibble 2 data
2386 * bits 3:0 - nibble 3 data
2387 *
2388 * Example:
2389 * In order to match:
2390 * - Ethernet frame type = 0x0800 (IP)
2391 * - IP version field = 4
2392 * - IP protocol field = 0x11 (UDP)
2393 *
2394 * The following filter is needed:
2395 * u32 hfb_filter_ipv4_udp[] = {
2396 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2397 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2398 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2399 * };
2400 *
2401 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2402 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2403 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2404 */
2405int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2406 u32 f_length, u32 rx_queue)
2407{
2408 int f_index;
2409 u32 i;
2410
2411 f_index = bcmgenet_hfb_find_unused_filter(priv);
2412 if (f_index < 0)
2413 return -ENOMEM;
2414
2415 if (f_length > priv->hw_params->hfb_filter_size)
2416 return -EINVAL;
2417
2418 for (i = 0; i < f_length; i++)
2419 bcmgenet_hfb_writel(priv, f_data[i],
2420 (f_index * priv->hw_params->hfb_filter_size + i) *
2421 sizeof(u32));
2422
2423 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2424 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2425 bcmgenet_hfb_enable_filter(priv, f_index);
2426 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2427
2428 return 0;
2429}
2430
2431/* bcmgenet_hfb_clear
2432 *
2433 * Clear Hardware Filter Block and disable all filtering.
2434 */
2435static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2436{
2437 u32 i;
2438
2439 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2440 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2441 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2442
2443 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2444 bcmgenet_rdma_writel(priv, 0x0, i);
2445
2446 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2447 bcmgenet_hfb_reg_writel(priv, 0x0,
2448 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2449
2450 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2451 priv->hw_params->hfb_filter_size; i++)
2452 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2453}
2454
2455static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2456{
2457 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2458 return;
2459
2460 bcmgenet_hfb_clear(priv);
2461}
2462
909ff5ef
FF		 2463static void bcmgenet_netif_start(struct net_device *dev)
2464{
2465 struct bcmgenet_priv *priv = netdev_priv(dev);
2466
2467 /* Start the network engine */
2468 napi_enable(&priv->napi);
2469
2470 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2471
909ff5ef
FF		 2472 netif_tx_start_all_queues(dev);
2473
2474 phy_start(priv->phydev);
2475}
2476
1c1008c7
FF		 2477static int bcmgenet_open(struct net_device *dev)
2478{
2479 struct bcmgenet_priv *priv = netdev_priv(dev);
2480 unsigned long dma_ctrl;
2481 u32 reg;
2482 int ret;
2483
2484 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2485
2486 /* Turn on the clock */
2487 if (!IS_ERR(priv->clk))
2488 clk_prepare_enable(priv->clk);
2489
a642c4f7
FF		 2490 /* If this is an internal GPHY, power it back on now, before UniMAC is
2491 * brought out of reset as absolutely no UniMAC activity is allowed
2492 */
2493 if (phy_is_internal(priv->phydev))
2494 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2495
1c1008c7
FF		 2496 /* take MAC out of reset */
2497 bcmgenet_umac_reset(priv);
2498
2499 ret = init_umac(priv);
2500 if (ret)
2501 goto err_clk_disable;
2502
2503 /* disable ethernet MAC while updating its registers */
e29585b8 2504 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2505
909ff5ef
FF		 2506 /* Make sure we reflect the value of CRC_CMD_FWD */
2507 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2508 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2509
1c1008c7
FF		 2510 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2511
1c1008c7
FF		 2512 if (phy_is_internal(priv->phydev)) {
2513 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2514 reg |= EXT_ENERGY_DET_MASK;
2515 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2516 }
2517
2518 /* Disable RX/TX DMA and flush TX queues */
2519 dma_ctrl = bcmgenet_dma_disable(priv);
2520
2521 /* Reinitialize TDMA and RDMA and SW housekeeping */
2522 ret = bcmgenet_init_dma(priv);
2523 if (ret) {
2524 netdev_err(dev, "failed to initialize DMA\n");
2525 goto err_fini_dma;
2526 }
2527
2528 /* Always enable ring 16 - descriptor ring */
2529 bcmgenet_enable_dma(priv, dma_ctrl);
2530
0034de41
PG		 2531 /* HFB init */
2532 bcmgenet_hfb_init(priv);
2533
1c1008c7 2534 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2535 dev->name, priv);
1c1008c7
FF		 2536 if (ret < 0) {
2537 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2538 goto err_fini_dma;
2539 }
2540
2541 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2542 dev->name, priv);
1c1008c7
FF		 2543 if (ret < 0) {
2544 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2545 goto err_irq0;
2546 }
2547
dbd479db
FF		 2548 /* Re-configure the port multiplexer towards the PHY device */
2549 bcmgenet_mii_config(priv->dev, false);
2550
c96e731c
FF		 2551 phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2552 priv->phy_interface);
2553
909ff5ef 2554 bcmgenet_netif_start(dev);
1c1008c7
FF		 2555
2556 return 0;
2557
2558err_irq0:
2559 free_irq(priv->irq0, dev);
2560err_fini_dma:
2561 bcmgenet_fini_dma(priv);
2562err_clk_disable:
2563 if (!IS_ERR(priv->clk))
2564 clk_disable_unprepare(priv->clk);
2565 return ret;
2566}
2567
909ff5ef
FF		 2568static void bcmgenet_netif_stop(struct net_device *dev)
2569{
2570 struct bcmgenet_priv *priv = netdev_priv(dev);
2571
2572 netif_tx_stop_all_queues(dev);
2573 napi_disable(&priv->napi);
2574 phy_stop(priv->phydev);
2575
2576 bcmgenet_intr_disable(priv);
2577
2578 /* Wait for pending work items to complete. Since interrupts are
2579 * disabled no new work will be scheduled.
2580 */
2581 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2582
cc013fb4 2583 priv->old_link = -1;
5ad6e6c5 2584 priv->old_speed = -1;
cc013fb4 2585 priv->old_duplex = -1;
5ad6e6c5 2586 priv->old_pause = -1;
909ff5ef
FF		 2587}
2588
1c1008c7
FF		 2589static int bcmgenet_close(struct net_device *dev)
2590{
2591 struct bcmgenet_priv *priv = netdev_priv(dev);
2592 int ret;
1c1008c7
FF		 2593
2594 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2595
909ff5ef 2596 bcmgenet_netif_stop(dev);
1c1008c7 2597
c96e731c
FF		 2598 /* Really kill the PHY state machine and disconnect from it */
2599 phy_disconnect(priv->phydev);
2600
1c1008c7 2601 /* Disable MAC receive */
e29585b8 2602 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2603
1c1008c7
FF		 2604 ret = bcmgenet_dma_teardown(priv);
2605 if (ret)
2606 return ret;
2607
2608 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2609 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2610
1c1008c7
FF		 2611 /* tx reclaim */
2612 bcmgenet_tx_reclaim_all(dev);
2613 bcmgenet_fini_dma(priv);
2614
2615 free_irq(priv->irq0, priv);
2616 free_irq(priv->irq1, priv);
2617
1c1008c7 2618 if (phy_is_internal(priv->phydev))
ca8cf341 2619 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 2620
1c1008c7
FF		 2621 if (!IS_ERR(priv->clk))
2622 clk_disable_unprepare(priv->clk);
2623
ca8cf341 2624 return ret;
1c1008c7
FF		 2625}
2626
2627static void bcmgenet_timeout(struct net_device *dev)
2628{
2629 struct bcmgenet_priv *priv = netdev_priv(dev);
2630
2631 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2632
2633 dev->trans_start = jiffies;
2634
2635 dev->stats.tx_errors++;
2636
2637 netif_tx_wake_all_queues(dev);
2638}
2639
2640#define MAX_MC_COUNT 16
2641
2642static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2643 unsigned char *addr,
2644 int *i,
2645 int *mc)
2646{
2647 u32 reg;
2648
c91b7f66
FF		 2649 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2650 UMAC_MDF_ADDR + (*i * 4));
2651 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2652 addr[4] << 8 | addr[5],
2653 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2654 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2655 reg |= (1 << (MAX_MC_COUNT - *mc));
2656 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2657 *i += 2;
2658 (*mc)++;
2659}
2660
2661static void bcmgenet_set_rx_mode(struct net_device *dev)
2662{
2663 struct bcmgenet_priv *priv = netdev_priv(dev);
2664 struct netdev_hw_addr *ha;
2665 int i, mc;
2666 u32 reg;
2667
2668 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2669
7fc527f9 2670 /* Promiscuous mode */
1c1008c7
FF		 2671 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2672 if (dev->flags & IFF_PROMISC) {
2673 reg |= CMD_PROMISC;
2674 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2675 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2676 return;
2677 } else {
2678 reg &= ~CMD_PROMISC;
2679 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2680 }
2681
2682 /* UniMac doesn't support ALLMULTI */
2683 if (dev->flags & IFF_ALLMULTI) {
2684 netdev_warn(dev, "ALLMULTI is not supported\n");
2685 return;
2686 }
2687
2688 /* update MDF filter */
2689 i = 0;
2690 mc = 0;
2691 /* Broadcast */
2692 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2693 /* my own address.*/
2694 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2695 /* Unicast list*/
2696 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2697 return;
2698
2699 if (!netdev_uc_empty(dev))
2700 netdev_for_each_uc_addr(ha, dev)
2701 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2702 /* Multicast */
2703 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2704 return;
2705
2706 netdev_for_each_mc_addr(ha, dev)
2707 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2708}
2709
2710/* Set the hardware MAC address. */
2711static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2712{
2713 struct sockaddr *addr = p;
2714
2715 /* Setting the MAC address at the hardware level is not possible
2716 * without disabling the UniMAC RX/TX enable bits.
2717 */
2718 if (netif_running(dev))
2719 return -EBUSY;
2720
2721 ether_addr_copy(dev->dev_addr, addr->sa_data);
2722
2723 return 0;
2724}
2725
1c1008c7
FF		 2726static const struct net_device_ops bcmgenet_netdev_ops = {
2727 .ndo_open = bcmgenet_open,
2728 .ndo_stop = bcmgenet_close,
2729 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2730 .ndo_tx_timeout = bcmgenet_timeout,
2731 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2732 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2733 .ndo_do_ioctl = bcmgenet_ioctl,
2734 .ndo_set_features = bcmgenet_set_features,
2735};
2736
2737/* Array of GENET hardware parameters/characteristics */
2738static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2739 [GENET_V1] = {
2740 .tx_queues = 0,
51a966a7 2741 .tx_bds_per_q = 0,
1c1008c7 2742 .rx_queues = 0,
3feafa02 2743 .rx_bds_per_q = 0,
1c1008c7
FF		 2744 .bp_in_en_shift = 16,
2745 .bp_in_mask = 0xffff,
2746 .hfb_filter_cnt = 16,
2747 .qtag_mask = 0x1F,
2748 .hfb_offset = 0x1000,
2749 .rdma_offset = 0x2000,
2750 .tdma_offset = 0x3000,
2751 .words_per_bd = 2,
2752 },
2753 [GENET_V2] = {
2754 .tx_queues = 4,
51a966a7 2755 .tx_bds_per_q = 32,
7e906e02 2756 .rx_queues = 0,
3feafa02 2757 .rx_bds_per_q = 0,
1c1008c7
FF		 2758 .bp_in_en_shift = 16,
2759 .bp_in_mask = 0xffff,
2760 .hfb_filter_cnt = 16,
2761 .qtag_mask = 0x1F,
2762 .tbuf_offset = 0x0600,
2763 .hfb_offset = 0x1000,
2764 .hfb_reg_offset = 0x2000,
2765 .rdma_offset = 0x3000,
2766 .tdma_offset = 0x4000,
2767 .words_per_bd = 2,
2768 .flags = GENET_HAS_EXT,
2769 },
2770 [GENET_V3] = {
2771 .tx_queues = 4,
51a966a7 2772 .tx_bds_per_q = 32,
7e906e02 2773 .rx_queues = 0,
3feafa02 2774 .rx_bds_per_q = 0,
1c1008c7
FF		 2775 .bp_in_en_shift = 17,
2776 .bp_in_mask = 0x1ffff,
2777 .hfb_filter_cnt = 48,
0034de41 2778 .hfb_filter_size = 128,
1c1008c7
FF		 2779 .qtag_mask = 0x3F,
2780 .tbuf_offset = 0x0600,
2781 .hfb_offset = 0x8000,
2782 .hfb_reg_offset = 0xfc00,
2783 .rdma_offset = 0x10000,
2784 .tdma_offset = 0x11000,
2785 .words_per_bd = 2,
2786 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2787 },
2788 [GENET_V4] = {
2789 .tx_queues = 4,
51a966a7 2790 .tx_bds_per_q = 32,
7e906e02 2791 .rx_queues = 0,
3feafa02 2792 .rx_bds_per_q = 0,
1c1008c7
FF		 2793 .bp_in_en_shift = 17,
2794 .bp_in_mask = 0x1ffff,
2795 .hfb_filter_cnt = 48,
0034de41 2796 .hfb_filter_size = 128,
1c1008c7
FF		 2797 .qtag_mask = 0x3F,
2798 .tbuf_offset = 0x0600,
2799 .hfb_offset = 0x8000,
2800 .hfb_reg_offset = 0xfc00,
2801 .rdma_offset = 0x2000,
2802 .tdma_offset = 0x4000,
2803 .words_per_bd = 3,
2804 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2805 },
2806};
2807
2808/* Infer hardware parameters from the detected GENET version */
2809static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2810{
2811 struct bcmgenet_hw_params *params;
2812 u32 reg;
2813 u8 major;
b04a2f5b 2814 u16 gphy_rev;
1c1008c7
FF		 2815
2816 if (GENET_IS_V4(priv)) {
2817 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2818 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2819 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2820 priv->version = GENET_V4;
2821 } else if (GENET_IS_V3(priv)) {
2822 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2823 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2824 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2825 priv->version = GENET_V3;
2826 } else if (GENET_IS_V2(priv)) {
2827 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2828 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2829 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2830 priv->version = GENET_V2;
2831 } else if (GENET_IS_V1(priv)) {
2832 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2833 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2834 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2835 priv->version = GENET_V1;
2836 }
2837
2838 /* enum genet_version starts at 1 */
2839 priv->hw_params = &bcmgenet_hw_params[priv->version];
2840 params = priv->hw_params;
2841
2842 /* Read GENET HW version */
2843 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2844 major = (reg >> 24 & 0x0f);
2845 if (major == 5)
2846 major = 4;
2847 else if (major == 0)
2848 major = 1;
2849 if (major != priv->version) {
2850 dev_err(&priv->pdev->dev,
2851 "GENET version mismatch, got: %d, configured for: %d\n",
2852 major, priv->version);
2853 }
2854
2855 /* Print the GENET core version */
2856 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 2857 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 2858
487320c5
FF		 2859 /* Store the integrated PHY revision for the MDIO probing function
2860 * to pass this information to the PHY driver. The PHY driver expects
2861 * to find the PHY major revision in bits 15:8 while the GENET register
2862 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 2863 *
2864 * On newer chips, starting with PHY revision G0, a new scheme is
2865 * deployed similar to the Starfighter 2 switch with GPHY major
2866 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
2867 * is reserved as well as special value 0x01ff, we have a small
2868 * heuristic to check for the new GPHY revision and re-arrange things
2869 * so the GPHY driver is happy.
487320c5 2870 */
b04a2f5b
FF		 2871 gphy_rev = reg & 0xffff;
2872
2873 /* This is the good old scheme, just GPHY major, no minor nor patch */
2874 if ((gphy_rev & 0xf0) != 0)
2875 priv->gphy_rev = gphy_rev << 8;
2876
2877 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
2878 else if ((gphy_rev & 0xff00) != 0)
2879 priv->gphy_rev = gphy_rev;
2880
2881 /* This is reserved so should require special treatment */
2882 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
2883 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
2884 return;
2885 }
487320c5 2886
1c1008c7
FF		 2887#ifdef CONFIG_PHYS_ADDR_T_64BIT
2888 if (!(params->flags & GENET_HAS_40BITS))
2889 pr_warn("GENET does not support 40-bits PA\n");
2890#endif
2891
2892 pr_debug("Configuration for version: %d\n"
3feafa02 2893 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 2894 "BP << en: %2d, BP msk: 0x%05x\n"
2895 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2896 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2897 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2898 "Words/BD: %d\n",
2899 priv->version,
51a966a7 2900 params->tx_queues, params->tx_bds_per_q,
3feafa02 2901 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 2902 params->bp_in_en_shift, params->bp_in_mask,
2903 params->hfb_filter_cnt, params->qtag_mask,
2904 params->tbuf_offset, params->hfb_offset,
2905 params->hfb_reg_offset,
2906 params->rdma_offset, params->tdma_offset,
2907 params->words_per_bd);
2908}
2909
2910static const struct of_device_id bcmgenet_match[] = {
2911 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2912 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2913 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2914 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2915 { },
2916};
2917
2918static int bcmgenet_probe(struct platform_device *pdev)
2919{
b0ba512e 2920 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 2921 struct device_node *dn = pdev->dev.of_node;
b0ba512e 2922 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 2923 struct bcmgenet_priv *priv;
2924 struct net_device *dev;
2925 const void *macaddr;
2926 struct resource *r;
2927 int err = -EIO;
2928
3feafeed
PG		 2929 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
2930 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
2931 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 2932 if (!dev) {
2933 dev_err(&pdev->dev, "can't allocate net device\n");
2934 return -ENOMEM;
2935 }
2936
b0ba512e
PG		 2937 if (dn) {
2938 of_id = of_match_node(bcmgenet_match, dn);
2939 if (!of_id)
2940 return -EINVAL;
2941 }
1c1008c7
FF		 2942
2943 priv = netdev_priv(dev);
2944 priv->irq0 = platform_get_irq(pdev, 0);
2945 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2946 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2947 if (!priv->irq0 || !priv->irq1) {
2948 dev_err(&pdev->dev, "can't find IRQs\n");
2949 err = -EINVAL;
2950 goto err;
2951 }
2952
b0ba512e
PG		 2953 if (dn) {
2954 macaddr = of_get_mac_address(dn);
2955 if (!macaddr) {
2956 dev_err(&pdev->dev, "can't find MAC address\n");
2957 err = -EINVAL;
2958 goto err;
2959 }
2960 } else {
2961 macaddr = pd->mac_address;
1c1008c7
FF		 2962 }
2963
2964 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2965 priv->base = devm_ioremap_resource(&pdev->dev, r);
2966 if (IS_ERR(priv->base)) {
2967 err = PTR_ERR(priv->base);
1c1008c7
FF		 2968 goto err;
2969 }
2970
2971 SET_NETDEV_DEV(dev, &pdev->dev);
2972 dev_set_drvdata(&pdev->dev, dev);
2973 ether_addr_copy(dev->dev_addr, macaddr);
2974 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2975 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2976 dev->netdev_ops = &bcmgenet_netdev_ops;
2977 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2978
2979 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2980
2981 /* Set hardware features */
2982 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2983 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2984
8562056f
FF		 2985 /* Request the WOL interrupt and advertise suspend if available */
2986 priv->wol_irq_disabled = true;
2987 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2988 dev->name, priv);
2989 if (!err)
2990 device_set_wakeup_capable(&pdev->dev, 1);
2991
1c1008c7
FF		 2992 /* Set the needed headroom to account for any possible
2993 * features enabling/disabling at runtime
2994 */
2995 dev->needed_headroom += 64;
2996
2997 netdev_boot_setup_check(dev);
2998
2999 priv->dev = dev;
3000 priv->pdev = pdev;
b0ba512e
PG		 3001 if (of_id)
3002 priv->version = (enum bcmgenet_version)of_id->data;
3003 else
3004 priv->version = pd->genet_version;
1c1008c7 3005
e4a60a93
FF		 3006 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3007 if (IS_ERR(priv->clk))
3008 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3009
3010 if (!IS_ERR(priv->clk))
3011 clk_prepare_enable(priv->clk);
3012
1c1008c7
FF		 3013 bcmgenet_set_hw_params(priv);
3014
1c1008c7
FF		 3015 /* Mii wait queue */
3016 init_waitqueue_head(&priv->wq);
3017 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3018 priv->rx_buf_len = RX_BUF_LENGTH;
3019 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3020
1c1008c7
FF		 3021 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3022 if (IS_ERR(priv->clk_wol))
3023 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3024
6ef398ea
FF		 3025 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3026 if (IS_ERR(priv->clk_eee)) {
3027 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3028 priv->clk_eee = NULL;
3029 }
3030
1c1008c7
FF		 3031 err = reset_umac(priv);
3032 if (err)
3033 goto err_clk_disable;
3034
3035 err = bcmgenet_mii_init(dev);
3036 if (err)
3037 goto err_clk_disable;
3038
3039 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3040 * just the ring 16 descriptor based TX
3041 */
3042 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3043 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3044
219575eb
FF		 3045 /* libphy will determine the link state */
3046 netif_carrier_off(dev);
3047
1c1008c7
FF		 3048 /* Turn off the main clock, WOL clock is handled separately */
3049 if (!IS_ERR(priv->clk))
3050 clk_disable_unprepare(priv->clk);
3051
0f50ce96
FF		 3052 err = register_netdev(dev);
3053 if (err)
3054 goto err;
3055
1c1008c7
FF		 3056 return err;
3057
3058err_clk_disable:
3059 if (!IS_ERR(priv->clk))
3060 clk_disable_unprepare(priv->clk);
3061err:
3062 free_netdev(dev);
3063 return err;
3064}
3065
3066static int bcmgenet_remove(struct platform_device *pdev)
3067{
3068 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3069
3070 dev_set_drvdata(&pdev->dev, NULL);
3071 unregister_netdev(priv->dev);
3072 bcmgenet_mii_exit(priv->dev);
3073 free_netdev(priv->dev);
3074
3075 return 0;
3076}
3077
b6e978e5
FF		 3078#ifdef CONFIG_PM_SLEEP
3079static int bcmgenet_suspend(struct device *d)
3080{
3081 struct net_device *dev = dev_get_drvdata(d);
3082 struct bcmgenet_priv *priv = netdev_priv(dev);
3083 int ret;
3084
3085 if (!netif_running(dev))
3086 return 0;
3087
3088 bcmgenet_netif_stop(dev);
3089
cc013fb4
FF		 3090 phy_suspend(priv->phydev);
3091
b6e978e5
FF		 3092 netif_device_detach(dev);
3093
3094 /* Disable MAC receive */
3095 umac_enable_set(priv, CMD_RX_EN, false);
3096
3097 ret = bcmgenet_dma_teardown(priv);
3098 if (ret)
3099 return ret;
3100
3101 /* Disable MAC transmit. TX DMA disabled have to done before this */
3102 umac_enable_set(priv, CMD_TX_EN, false);
3103
3104 /* tx reclaim */
3105 bcmgenet_tx_reclaim_all(dev);
3106 bcmgenet_fini_dma(priv);
3107
8c90db72
FF		 3108 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3109 if (device_may_wakeup(d) && priv->wolopts) {
ca8cf341 3110 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
8c90db72 3111 clk_prepare_enable(priv->clk_wol);
a6f31f5e
FF		 3112 } else if (phy_is_internal(priv->phydev)) {
3113 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
8c90db72
FF		 3114 }
3115
b6e978e5
FF		 3116 /* Turn off the clocks */
3117 clk_disable_unprepare(priv->clk);
3118
ca8cf341 3119 return ret;
b6e978e5
FF		 3120}
3121
3122static int bcmgenet_resume(struct device *d)
3123{
3124 struct net_device *dev = dev_get_drvdata(d);
3125 struct bcmgenet_priv *priv = netdev_priv(dev);
3126 unsigned long dma_ctrl;
3127 int ret;
3128 u32 reg;
3129
3130 if (!netif_running(dev))
3131 return 0;
3132
3133 /* Turn on the clock */
3134 ret = clk_prepare_enable(priv->clk);
3135 if (ret)
3136 return ret;
3137
a6f31f5e
FF		 3138 /* If this is an internal GPHY, power it back on now, before UniMAC is
3139 * brought out of reset as absolutely no UniMAC activity is allowed
3140 */
3141 if (phy_is_internal(priv->phydev))
3142 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3143
b6e978e5
FF		 3144 bcmgenet_umac_reset(priv);
3145
3146 ret = init_umac(priv);
3147 if (ret)
3148 goto out_clk_disable;
3149
0a29b3da
TK		 3150 /* From WOL-enabled suspend, switch to regular clock */
3151 if (priv->wolopts)
3152 clk_disable_unprepare(priv->clk_wol);
3153
3154 phy_init_hw(priv->phydev);
3155 /* Speed settings must be restored */
dbd479db 3156 bcmgenet_mii_config(priv->dev, false);
8c90db72 3157
b6e978e5
FF		 3158 /* disable ethernet MAC while updating its registers */
3159 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3160
3161 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3162
3163 if (phy_is_internal(priv->phydev)) {
3164 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3165 reg |= EXT_ENERGY_DET_MASK;
3166 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3167 }
3168
98bb7399
FF		 3169 if (priv->wolopts)
3170 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3171
b6e978e5
FF		 3172 /* Disable RX/TX DMA and flush TX queues */
3173 dma_ctrl = bcmgenet_dma_disable(priv);
3174
3175 /* Reinitialize TDMA and RDMA and SW housekeeping */
3176 ret = bcmgenet_init_dma(priv);
3177 if (ret) {
3178 netdev_err(dev, "failed to initialize DMA\n");
3179 goto out_clk_disable;
3180 }
3181
3182 /* Always enable ring 16 - descriptor ring */
3183 bcmgenet_enable_dma(priv, dma_ctrl);
3184
3185 netif_device_attach(dev);
3186
cc013fb4
FF		 3187 phy_resume(priv->phydev);
3188
6ef398ea
FF		 3189 if (priv->eee.eee_enabled)
3190 bcmgenet_eee_enable_set(dev, true);
3191
b6e978e5
FF		 3192 bcmgenet_netif_start(dev);
3193
3194 return 0;
3195
3196out_clk_disable:
3197 clk_disable_unprepare(priv->clk);
3198 return ret;
3199}
3200#endif /* CONFIG_PM_SLEEP */
3201
3202static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3203
1c1008c7
FF		 3204static struct platform_driver bcmgenet_driver = {
3205 .probe = bcmgenet_probe,
3206 .remove = bcmgenet_remove,
3207 .driver = {
3208 .name = "bcmgenet",
1c1008c7 3209 .of_match_table = bcmgenet_match,
b6e978e5 3210 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 3211 },
3212};
3213module_platform_driver(bcmgenet_driver);
3214
3215MODULE_AUTHOR("Broadcom Corporation");
3216MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3217MODULE_ALIAS("platform:bcmgenet");
3218MODULE_LICENSE("GPL");
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