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net: bcmgenet: remove bogus tx queue checks
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20#define pr_fmt(fmt) "bcmgenet: " fmt
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/sched.h>
25#include <linux/types.h>
26#include <linux/fcntl.h>
27#include <linux/interrupt.h>
28#include <linux/string.h>
29#include <linux/if_ether.h>
30#include <linux/init.h>
31#include <linux/errno.h>
32#include <linux/delay.h>
33#include <linux/platform_device.h>
34#include <linux/dma-mapping.h>
35#include <linux/pm.h>
36#include <linux/clk.h>
37#include <linux/version.h>
38#include <linux/of.h>
39#include <linux/of_address.h>
40#include <linux/of_irq.h>
41#include <linux/of_net.h>
42#include <linux/of_platform.h>
43#include <net/arp.h>
44
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/netdevice.h>
48#include <linux/inetdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/in.h>
52#include <linux/ip.h>
53#include <linux/ipv6.h>
54#include <linux/phy.h>
55
56#include <asm/unaligned.h>
57
58#include "bcmgenet.h"
59
60/* Maximum number of hardware queues, downsized if needed */
61#define GENET_MAX_MQ_CNT 4
62
63/* Default highest priority queue for multi queue support */
64#define GENET_Q0_PRIORITY 0
65
66#define GENET_DEFAULT_BD_CNT \
67 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
68
69#define RX_BUF_LENGTH 2048
70#define SKB_ALIGNMENT 32
71
72/* Tx/Rx DMA register offset, skip 256 descriptors */
73#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
74#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
75
76#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
77 TOTAL_DESC * DMA_DESC_SIZE)
78
79#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
80 TOTAL_DESC * DMA_DESC_SIZE)
81
82static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
83 void __iomem *d, u32 value)
84{
85 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
86}
87
88static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
89 void __iomem *d)
90{
91 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
92}
93
94static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
95 void __iomem *d,
96 dma_addr_t addr)
97{
98 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
99
100 /* Register writes to GISB bus can take couple hundred nanoseconds
101 * and are done for each packet, save these expensive writes unless
102 * the platform is explicitely configured for 64-bits/LPAE.
103 */
104#ifdef CONFIG_PHYS_ADDR_T_64BIT
105 if (priv->hw_params->flags & GENET_HAS_40BITS)
106 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
107#endif
108}
109
110/* Combined address + length/status setter */
111static inline void dmadesc_set(struct bcmgenet_priv *priv,
112 void __iomem *d, dma_addr_t addr, u32 val)
113{
114 dmadesc_set_length_status(priv, d, val);
115 dmadesc_set_addr(priv, d, addr);
116}
117
118static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
119 void __iomem *d)
120{
121 dma_addr_t addr;
122
123 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
124
125 /* Register writes to GISB bus can take couple hundred nanoseconds
126 * and are done for each packet, save these expensive writes unless
127 * the platform is explicitely configured for 64-bits/LPAE.
128 */
129#ifdef CONFIG_PHYS_ADDR_T_64BIT
130 if (priv->hw_params->flags & GENET_HAS_40BITS)
131 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
132#endif
133 return addr;
134}
135
136#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
137
138#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
139 NETIF_MSG_LINK)
140
141static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
142{
143 if (GENET_IS_V1(priv))
144 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
145 else
146 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
147}
148
149static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
150{
151 if (GENET_IS_V1(priv))
152 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
153 else
154 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
155}
156
157/* These macros are defined to deal with register map change
158 * between GENET1.1 and GENET2. Only those currently being used
159 * by driver are defined.
160 */
161static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
162{
163 if (GENET_IS_V1(priv))
164 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
165 else
166 return __raw_readl(priv->base +
167 priv->hw_params->tbuf_offset + TBUF_CTRL);
168}
169
170static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
171{
172 if (GENET_IS_V1(priv))
173 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
174 else
175 __raw_writel(val, priv->base +
176 priv->hw_params->tbuf_offset + TBUF_CTRL);
177}
178
179static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
180{
181 if (GENET_IS_V1(priv))
182 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
183 else
184 return __raw_readl(priv->base +
185 priv->hw_params->tbuf_offset + TBUF_BP_MC);
186}
187
188static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
189{
190 if (GENET_IS_V1(priv))
191 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
192 else
193 __raw_writel(val, priv->base +
194 priv->hw_params->tbuf_offset + TBUF_BP_MC);
195}
196
197/* RX/TX DMA register accessors */
198enum dma_reg {
199 DMA_RING_CFG = 0,
200 DMA_CTRL,
201 DMA_STATUS,
202 DMA_SCB_BURST_SIZE,
203 DMA_ARB_CTRL,
204 DMA_PRIORITY,
205 DMA_RING_PRIORITY,
206};
207
208static const u8 bcmgenet_dma_regs_v3plus[] = {
209 [DMA_RING_CFG] = 0x00,
210 [DMA_CTRL] = 0x04,
211 [DMA_STATUS] = 0x08,
212 [DMA_SCB_BURST_SIZE] = 0x0C,
213 [DMA_ARB_CTRL] = 0x2C,
214 [DMA_PRIORITY] = 0x30,
215 [DMA_RING_PRIORITY] = 0x38,
216};
217
218static const u8 bcmgenet_dma_regs_v2[] = {
219 [DMA_RING_CFG] = 0x00,
220 [DMA_CTRL] = 0x04,
221 [DMA_STATUS] = 0x08,
222 [DMA_SCB_BURST_SIZE] = 0x0C,
223 [DMA_ARB_CTRL] = 0x30,
224 [DMA_PRIORITY] = 0x34,
225 [DMA_RING_PRIORITY] = 0x3C,
226};
227
228static const u8 bcmgenet_dma_regs_v1[] = {
229 [DMA_CTRL] = 0x00,
230 [DMA_STATUS] = 0x04,
231 [DMA_SCB_BURST_SIZE] = 0x0C,
232 [DMA_ARB_CTRL] = 0x30,
233 [DMA_PRIORITY] = 0x34,
234 [DMA_RING_PRIORITY] = 0x3C,
235};
236
237/* Set at runtime once bcmgenet version is known */
238static const u8 *bcmgenet_dma_regs;
239
240static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
241{
242 return netdev_priv(dev_get_drvdata(dev));
243}
244
245static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
246 enum dma_reg r)
247{
248 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
249 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
250}
251
252static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
253 u32 val, enum dma_reg r)
254{
255 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
256 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
257}
258
259static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
260 enum dma_reg r)
261{
262 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
263 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
264}
265
266static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
267 u32 val, enum dma_reg r)
268{
269 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
270 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
271}
272
273/* RDMA/TDMA ring registers and accessors
274 * we merge the common fields and just prefix with T/D the registers
275 * having different meaning depending on the direction
276 */
277enum dma_ring_reg {
278 TDMA_READ_PTR = 0,
279 RDMA_WRITE_PTR = TDMA_READ_PTR,
280 TDMA_READ_PTR_HI,
281 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
282 TDMA_CONS_INDEX,
283 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
284 TDMA_PROD_INDEX,
285 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
286 DMA_RING_BUF_SIZE,
287 DMA_START_ADDR,
288 DMA_START_ADDR_HI,
289 DMA_END_ADDR,
290 DMA_END_ADDR_HI,
291 DMA_MBUF_DONE_THRESH,
292 TDMA_FLOW_PERIOD,
293 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
294 TDMA_WRITE_PTR,
295 RDMA_READ_PTR = TDMA_WRITE_PTR,
296 TDMA_WRITE_PTR_HI,
297 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
298};
299
300/* GENET v4 supports 40-bits pointer addressing
301 * for obvious reasons the LO and HI word parts
302 * are contiguous, but this offsets the other
303 * registers.
304 */
305static const u8 genet_dma_ring_regs_v4[] = {
306 [TDMA_READ_PTR] = 0x00,
307 [TDMA_READ_PTR_HI] = 0x04,
308 [TDMA_CONS_INDEX] = 0x08,
309 [TDMA_PROD_INDEX] = 0x0C,
310 [DMA_RING_BUF_SIZE] = 0x10,
311 [DMA_START_ADDR] = 0x14,
312 [DMA_START_ADDR_HI] = 0x18,
313 [DMA_END_ADDR] = 0x1C,
314 [DMA_END_ADDR_HI] = 0x20,
315 [DMA_MBUF_DONE_THRESH] = 0x24,
316 [TDMA_FLOW_PERIOD] = 0x28,
317 [TDMA_WRITE_PTR] = 0x2C,
318 [TDMA_WRITE_PTR_HI] = 0x30,
319};
320
321static const u8 genet_dma_ring_regs_v123[] = {
322 [TDMA_READ_PTR] = 0x00,
323 [TDMA_CONS_INDEX] = 0x04,
324 [TDMA_PROD_INDEX] = 0x08,
325 [DMA_RING_BUF_SIZE] = 0x0C,
326 [DMA_START_ADDR] = 0x10,
327 [DMA_END_ADDR] = 0x14,
328 [DMA_MBUF_DONE_THRESH] = 0x18,
329 [TDMA_FLOW_PERIOD] = 0x1C,
330 [TDMA_WRITE_PTR] = 0x20,
331};
332
333/* Set at runtime once GENET version is known */
334static const u8 *genet_dma_ring_regs;
335
336static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
337 unsigned int ring,
338 enum dma_ring_reg r)
339{
340 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
341 (DMA_RING_SIZE * ring) +
342 genet_dma_ring_regs[r]);
343}
344
345static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
346 unsigned int ring,
347 u32 val,
348 enum dma_ring_reg r)
349{
350 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
351 (DMA_RING_SIZE * ring) +
352 genet_dma_ring_regs[r]);
353}
354
355static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
356 unsigned int ring,
357 enum dma_ring_reg r)
358{
359 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
360 (DMA_RING_SIZE * ring) +
361 genet_dma_ring_regs[r]);
362}
363
364static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
365 unsigned int ring,
366 u32 val,
367 enum dma_ring_reg r)
368{
369 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
370 (DMA_RING_SIZE * ring) +
371 genet_dma_ring_regs[r]);
372}
373
374static int bcmgenet_get_settings(struct net_device *dev,
375 struct ethtool_cmd *cmd)
376{
377 struct bcmgenet_priv *priv = netdev_priv(dev);
378
379 if (!netif_running(dev))
380 return -EINVAL;
381
382 if (!priv->phydev)
383 return -ENODEV;
384
385 return phy_ethtool_gset(priv->phydev, cmd);
386}
387
388static int bcmgenet_set_settings(struct net_device *dev,
389 struct ethtool_cmd *cmd)
390{
391 struct bcmgenet_priv *priv = netdev_priv(dev);
392
393 if (!netif_running(dev))
394 return -EINVAL;
395
396 if (!priv->phydev)
397 return -ENODEV;
398
399 return phy_ethtool_sset(priv->phydev, cmd);
400}
401
402static int bcmgenet_set_rx_csum(struct net_device *dev,
403 netdev_features_t wanted)
404{
405 struct bcmgenet_priv *priv = netdev_priv(dev);
406 u32 rbuf_chk_ctrl;
407 bool rx_csum_en;
408
409 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
410
411 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
412
413 /* enable rx checksumming */
414 if (rx_csum_en)
415 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
416 else
417 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
418 priv->desc_rxchk_en = rx_csum_en;
419 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
420
421 return 0;
422}
423
424static int bcmgenet_set_tx_csum(struct net_device *dev,
425 netdev_features_t wanted)
426{
427 struct bcmgenet_priv *priv = netdev_priv(dev);
428 bool desc_64b_en;
429 u32 tbuf_ctrl, rbuf_ctrl;
430
431 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
432 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
433
434 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
435
436 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
437 if (desc_64b_en) {
438 tbuf_ctrl |= RBUF_64B_EN;
439 rbuf_ctrl |= RBUF_64B_EN;
440 } else {
441 tbuf_ctrl &= ~RBUF_64B_EN;
442 rbuf_ctrl &= ~RBUF_64B_EN;
443 }
444 priv->desc_64b_en = desc_64b_en;
445
446 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
447 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
448
449 return 0;
450}
451
452static int bcmgenet_set_features(struct net_device *dev,
453 netdev_features_t features)
454{
455 netdev_features_t changed = features ^ dev->features;
456 netdev_features_t wanted = dev->wanted_features;
457 int ret = 0;
458
459 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
460 ret = bcmgenet_set_tx_csum(dev, wanted);
461 if (changed & (NETIF_F_RXCSUM))
462 ret = bcmgenet_set_rx_csum(dev, wanted);
463
464 return ret;
465}
466
467static u32 bcmgenet_get_msglevel(struct net_device *dev)
468{
469 struct bcmgenet_priv *priv = netdev_priv(dev);
470
471 return priv->msg_enable;
472}
473
474static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
475{
476 struct bcmgenet_priv *priv = netdev_priv(dev);
477
478 priv->msg_enable = level;
479}
480
481/* standard ethtool support functions. */
482enum bcmgenet_stat_type {
483 BCMGENET_STAT_NETDEV = -1,
484 BCMGENET_STAT_MIB_RX,
485 BCMGENET_STAT_MIB_TX,
486 BCMGENET_STAT_RUNT,
487 BCMGENET_STAT_MISC,
488};
489
490struct bcmgenet_stats {
491 char stat_string[ETH_GSTRING_LEN];
492 int stat_sizeof;
493 int stat_offset;
494 enum bcmgenet_stat_type type;
495 /* reg offset from UMAC base for misc counters */
496 u16 reg_offset;
497};
498
499#define STAT_NETDEV(m) { \
500 .stat_string = __stringify(m), \
501 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
502 .stat_offset = offsetof(struct net_device_stats, m), \
503 .type = BCMGENET_STAT_NETDEV, \
504}
505
506#define STAT_GENET_MIB(str, m, _type) { \
507 .stat_string = str, \
508 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
509 .stat_offset = offsetof(struct bcmgenet_priv, m), \
510 .type = _type, \
511}
512
513#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
514#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
515#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
516
517#define STAT_GENET_MISC(str, m, offset) { \
518 .stat_string = str, \
519 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
520 .stat_offset = offsetof(struct bcmgenet_priv, m), \
521 .type = BCMGENET_STAT_MISC, \
522 .reg_offset = offset, \
523}
524
525
526/* There is a 0xC gap between the end of RX and beginning of TX stats and then
527 * between the end of TX stats and the beginning of the RX RUNT
528 */
529#define BCMGENET_STAT_OFFSET 0xc
530
531/* Hardware counters must be kept in sync because the order/offset
532 * is important here (order in structure declaration = order in hardware)
533 */
534static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
535 /* general stats */
536 STAT_NETDEV(rx_packets),
537 STAT_NETDEV(tx_packets),
538 STAT_NETDEV(rx_bytes),
539 STAT_NETDEV(tx_bytes),
540 STAT_NETDEV(rx_errors),
541 STAT_NETDEV(tx_errors),
542 STAT_NETDEV(rx_dropped),
543 STAT_NETDEV(tx_dropped),
544 STAT_NETDEV(multicast),
545 /* UniMAC RSV counters */
546 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
547 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
548 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
549 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
550 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
551 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
552 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
553 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
554 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
555 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
556 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
557 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
558 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
559 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
560 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
561 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
562 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
563 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
564 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
565 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
566 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
567 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
568 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
569 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
570 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
571 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
572 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
573 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
574 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
575 /* UniMAC TSV counters */
576 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
577 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
578 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
579 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
580 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
581 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
582 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
583 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
584 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
585 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
586 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
587 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
588 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
589 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
590 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
591 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
592 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
593 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
594 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
595 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
596 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
597 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
598 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
599 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
600 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
601 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
602 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
603 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
604 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
605 /* UniMAC RUNT counters */
606 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
607 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
608 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
609 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
610 /* Misc UniMAC counters */
611 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
612 UMAC_RBUF_OVFL_CNT),
613 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
614 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
615};
616
617#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
618
619static void bcmgenet_get_drvinfo(struct net_device *dev,
620 struct ethtool_drvinfo *info)
621{
622 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
623 strlcpy(info->version, "v2.0", sizeof(info->version));
624 info->n_stats = BCMGENET_STATS_LEN;
625
626}
627
628static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
629{
630 switch (string_set) {
631 case ETH_SS_STATS:
632 return BCMGENET_STATS_LEN;
633 default:
634 return -EOPNOTSUPP;
635 }
636}
637
638static void bcmgenet_get_strings(struct net_device *dev,
639 u32 stringset, u8 *data)
640{
641 int i;
642
643 switch (stringset) {
644 case ETH_SS_STATS:
645 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
646 memcpy(data + i * ETH_GSTRING_LEN,
647 bcmgenet_gstrings_stats[i].stat_string,
648 ETH_GSTRING_LEN);
649 }
650 break;
651 }
652}
653
654static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
655{
656 int i, j = 0;
657
658 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
659 const struct bcmgenet_stats *s;
660 u8 offset = 0;
661 u32 val = 0;
662 char *p;
663
664 s = &bcmgenet_gstrings_stats[i];
665 switch (s->type) {
666 case BCMGENET_STAT_NETDEV:
667 continue;
668 case BCMGENET_STAT_MIB_RX:
669 case BCMGENET_STAT_MIB_TX:
670 case BCMGENET_STAT_RUNT:
671 if (s->type != BCMGENET_STAT_MIB_RX)
672 offset = BCMGENET_STAT_OFFSET;
673 val = bcmgenet_umac_readl(priv, UMAC_MIB_START +
674 j + offset);
675 break;
676 case BCMGENET_STAT_MISC:
677 val = bcmgenet_umac_readl(priv, s->reg_offset);
678 /* clear if overflowed */
679 if (val == ~0)
680 bcmgenet_umac_writel(priv, 0, s->reg_offset);
681 break;
682 }
683
684 j += s->stat_sizeof;
685 p = (char *)priv + s->stat_offset;
686 *(u32 *)p = val;
687 }
688}
689
690static void bcmgenet_get_ethtool_stats(struct net_device *dev,
691 struct ethtool_stats *stats,
692 u64 *data)
693{
694 struct bcmgenet_priv *priv = netdev_priv(dev);
695 int i;
696
697 if (netif_running(dev))
698 bcmgenet_update_mib_counters(priv);
699
700 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
701 const struct bcmgenet_stats *s;
702 char *p;
703
704 s = &bcmgenet_gstrings_stats[i];
705 if (s->type == BCMGENET_STAT_NETDEV)
706 p = (char *)&dev->stats;
707 else
708 p = (char *)priv;
709 p += s->stat_offset;
710 data[i] = *(u32 *)p;
711 }
712}
713
714/* standard ethtool support functions. */
715static struct ethtool_ops bcmgenet_ethtool_ops = {
716 .get_strings = bcmgenet_get_strings,
717 .get_sset_count = bcmgenet_get_sset_count,
718 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
719 .get_settings = bcmgenet_get_settings,
720 .set_settings = bcmgenet_set_settings,
721 .get_drvinfo = bcmgenet_get_drvinfo,
722 .get_link = ethtool_op_get_link,
723 .get_msglevel = bcmgenet_get_msglevel,
724 .set_msglevel = bcmgenet_set_msglevel,
725};
726
727/* Power down the unimac, based on mode. */
728static void bcmgenet_power_down(struct bcmgenet_priv *priv,
729 enum bcmgenet_power_mode mode)
730{
731 u32 reg;
732
733 switch (mode) {
734 case GENET_POWER_CABLE_SENSE:
80d8e96d 735 phy_detach(priv->phydev);
1c1008c7
FF		 736 break;
737
738 case GENET_POWER_PASSIVE:
739 /* Power down LED */
740 bcmgenet_mii_reset(priv->dev);
741 if (priv->hw_params->flags & GENET_HAS_EXT) {
742 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
743 reg |= (EXT_PWR_DOWN_PHY |
744 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
745 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
746 }
747 break;
748 default:
749 break;
750 }
751}
752
753static void bcmgenet_power_up(struct bcmgenet_priv *priv,
754 enum bcmgenet_power_mode mode)
755{
756 u32 reg;
757
758 if (!(priv->hw_params->flags & GENET_HAS_EXT))
759 return;
760
761 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
762
763 switch (mode) {
764 case GENET_POWER_PASSIVE:
765 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
766 EXT_PWR_DOWN_BIAS);
767 /* fallthrough */
768 case GENET_POWER_CABLE_SENSE:
769 /* enable APD */
770 reg |= EXT_PWR_DN_EN_LD;
771 break;
772 default:
773 break;
774 }
775
776 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
777 bcmgenet_mii_reset(priv->dev);
778}
779
780/* ioctl handle special commands that are not present in ethtool. */
781static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
782{
783 struct bcmgenet_priv *priv = netdev_priv(dev);
784 int val = 0;
785
786 if (!netif_running(dev))
787 return -EINVAL;
788
789 switch (cmd) {
790 case SIOCGMIIPHY:
791 case SIOCGMIIREG:
792 case SIOCSMIIREG:
793 if (!priv->phydev)
794 val = -ENODEV;
795 else
796 val = phy_mii_ioctl(priv->phydev, rq, cmd);
797 break;
798
799 default:
800 val = -EINVAL;
801 break;
802 }
803
804 return val;
805}
806
807static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
808 struct bcmgenet_tx_ring *ring)
809{
810 struct enet_cb *tx_cb_ptr;
811
812 tx_cb_ptr = ring->cbs;
813 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
814 tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
815 /* Advancing local write pointer */
816 if (ring->write_ptr == ring->end_ptr)
817 ring->write_ptr = ring->cb_ptr;
818 else
819 ring->write_ptr++;
820
821 return tx_cb_ptr;
822}
823
824/* Simple helper to free a control block's resources */
825static void bcmgenet_free_cb(struct enet_cb *cb)
826{
827 dev_kfree_skb_any(cb->skb);
828 cb->skb = NULL;
829 dma_unmap_addr_set(cb, dma_addr, 0);
830}
831
832static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
833 struct bcmgenet_tx_ring *ring)
834{
835 bcmgenet_intrl2_0_writel(priv,
836 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
837 INTRL2_CPU_MASK_SET);
838}
839
840static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
841 struct bcmgenet_tx_ring *ring)
842{
843 bcmgenet_intrl2_0_writel(priv,
844 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
845 INTRL2_CPU_MASK_CLEAR);
846}
847
848static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
849 struct bcmgenet_tx_ring *ring)
850{
851 bcmgenet_intrl2_1_writel(priv,
852 (1 << ring->index), INTRL2_CPU_MASK_CLEAR);
853 priv->int1_mask &= ~(1 << ring->index);
854}
855
856static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
857 struct bcmgenet_tx_ring *ring)
858{
859 bcmgenet_intrl2_1_writel(priv,
860 (1 << ring->index), INTRL2_CPU_MASK_SET);
861 priv->int1_mask |= (1 << ring->index);
862}
863
864/* Unlocked version of the reclaim routine */
865static void __bcmgenet_tx_reclaim(struct net_device *dev,
866 struct bcmgenet_tx_ring *ring)
867{
868 struct bcmgenet_priv *priv = netdev_priv(dev);
869 int last_tx_cn, last_c_index, num_tx_bds;
870 struct enet_cb *tx_cb_ptr;
871 unsigned int c_index;
872
873 /* Compute how many buffers are transmited since last xmit call */
874 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
875
876 last_c_index = ring->c_index;
877 num_tx_bds = ring->size;
878
879 c_index &= (num_tx_bds - 1);
880
881 if (c_index >= last_c_index)
882 last_tx_cn = c_index - last_c_index;
883 else
884 last_tx_cn = num_tx_bds - last_c_index + c_index;
885
886 netif_dbg(priv, tx_done, dev,
887 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
888 __func__, ring->index,
889 c_index, last_tx_cn, last_c_index);
890
891 /* Reclaim transmitted buffers */
892 while (last_tx_cn-- > 0) {
893 tx_cb_ptr = ring->cbs + last_c_index;
894 if (tx_cb_ptr->skb) {
895 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
896 dma_unmap_single(&dev->dev,
897 dma_unmap_addr(tx_cb_ptr, dma_addr),
898 tx_cb_ptr->skb->len,
899 DMA_TO_DEVICE);
900 bcmgenet_free_cb(tx_cb_ptr);
901 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
902 dev->stats.tx_bytes +=
903 dma_unmap_len(tx_cb_ptr, dma_len);
904 dma_unmap_page(&dev->dev,
905 dma_unmap_addr(tx_cb_ptr, dma_addr),
906 dma_unmap_len(tx_cb_ptr, dma_len),
907 DMA_TO_DEVICE);
908 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
909 }
910 dev->stats.tx_packets++;
911 ring->free_bds += 1;
912
913 last_c_index++;
914 last_c_index &= (num_tx_bds - 1);
915 }
916
917 if (ring->free_bds > (MAX_SKB_FRAGS + 1))
918 ring->int_disable(priv, ring);
919
920 if (__netif_subqueue_stopped(dev, ring->queue))
921 netif_wake_subqueue(dev, ring->queue);
922
923 ring->c_index = c_index;
924}
925
926static void bcmgenet_tx_reclaim(struct net_device *dev,
927 struct bcmgenet_tx_ring *ring)
928{
929 unsigned long flags;
930
931 spin_lock_irqsave(&ring->lock, flags);
932 __bcmgenet_tx_reclaim(dev, ring);
933 spin_unlock_irqrestore(&ring->lock, flags);
934}
935
936static void bcmgenet_tx_reclaim_all(struct net_device *dev)
937{
938 struct bcmgenet_priv *priv = netdev_priv(dev);
939 int i;
940
941 if (netif_is_multiqueue(dev)) {
942 for (i = 0; i < priv->hw_params->tx_queues; i++)
943 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
944 }
945
946 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
947}
948
949/* Transmits a single SKB (either head of a fragment or a single SKB)
950 * caller must hold priv->lock
951 */
952static int bcmgenet_xmit_single(struct net_device *dev,
953 struct sk_buff *skb,
954 u16 dma_desc_flags,
955 struct bcmgenet_tx_ring *ring)
956{
957 struct bcmgenet_priv *priv = netdev_priv(dev);
958 struct device *kdev = &priv->pdev->dev;
959 struct enet_cb *tx_cb_ptr;
960 unsigned int skb_len;
961 dma_addr_t mapping;
962 u32 length_status;
963 int ret;
964
965 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
966
967 if (unlikely(!tx_cb_ptr))
968 BUG();
969
970 tx_cb_ptr->skb = skb;
971
972 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
973
974 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
975 ret = dma_mapping_error(kdev, mapping);
976 if (ret) {
977 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
978 dev_kfree_skb(skb);
979 return ret;
980 }
981
982 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
983 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
984 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
985 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
986 DMA_TX_APPEND_CRC;
987
988 if (skb->ip_summed == CHECKSUM_PARTIAL)
989 length_status |= DMA_TX_DO_CSUM;
990
991 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
992
993 /* Decrement total BD count and advance our write pointer */
994 ring->free_bds -= 1;
995 ring->prod_index += 1;
996 ring->prod_index &= DMA_P_INDEX_MASK;
997
998 return 0;
999}
1000
1001/* Transmit a SKB fragement */
1002static int bcmgenet_xmit_frag(struct net_device *dev,
1003 skb_frag_t *frag,
1004 u16 dma_desc_flags,
1005 struct bcmgenet_tx_ring *ring)
1006{
1007 struct bcmgenet_priv *priv = netdev_priv(dev);
1008 struct device *kdev = &priv->pdev->dev;
1009 struct enet_cb *tx_cb_ptr;
1010 dma_addr_t mapping;
1011 int ret;
1012
1013 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1014
1015 if (unlikely(!tx_cb_ptr))
1016 BUG();
1017 tx_cb_ptr->skb = NULL;
1018
1019 mapping = skb_frag_dma_map(kdev, frag, 0,
1020 skb_frag_size(frag), DMA_TO_DEVICE);
1021 ret = dma_mapping_error(kdev, mapping);
1022 if (ret) {
1023 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1024 __func__);
1025 return ret;
1026 }
1027
1028 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1029 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1030
1031 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1032 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1033 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1034
1035
1036 ring->free_bds -= 1;
1037 ring->prod_index += 1;
1038 ring->prod_index &= DMA_P_INDEX_MASK;
1039
1040 return 0;
1041}
1042
1043/* Reallocate the SKB to put enough headroom in front of it and insert
1044 * the transmit checksum offsets in the descriptors
1045 */
1046static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb)
1047{
1048 struct status_64 *status = NULL;
1049 struct sk_buff *new_skb;
1050 u16 offset;
1051 u8 ip_proto;
1052 u16 ip_ver;
1053 u32 tx_csum_info;
1054
1055 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1056 /* If 64 byte status block enabled, must make sure skb has
1057 * enough headroom for us to insert 64B status block.
1058 */
1059 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1060 dev_kfree_skb(skb);
1061 if (!new_skb) {
1062 dev->stats.tx_errors++;
1063 dev->stats.tx_dropped++;
1064 return -ENOMEM;
1065 }
1066 skb = new_skb;
1067 }
1068
1069 skb_push(skb, sizeof(*status));
1070 status = (struct status_64 *)skb->data;
1071
1072 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1073 ip_ver = htons(skb->protocol);
1074 switch (ip_ver) {
1075 case ETH_P_IP:
1076 ip_proto = ip_hdr(skb)->protocol;
1077 break;
1078 case ETH_P_IPV6:
1079 ip_proto = ipv6_hdr(skb)->nexthdr;
1080 break;
1081 default:
1082 return 0;
1083 }
1084
1085 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1086 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1087 (offset + skb->csum_offset);
1088
1089 /* Set the length valid bit for TCP and UDP and just set
1090 * the special UDP flag for IPv4, else just set to 0.
1091 */
1092 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1093 tx_csum_info |= STATUS_TX_CSUM_LV;
1094 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1095 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1096 } else
1097 tx_csum_info = 0;
1098
1099 status->tx_csum_info = tx_csum_info;
1100 }
1101
1102 return 0;
1103}
1104
1105static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1106{
1107 struct bcmgenet_priv *priv = netdev_priv(dev);
1108 struct bcmgenet_tx_ring *ring = NULL;
1109 unsigned long flags = 0;
1110 int nr_frags, index;
1111 u16 dma_desc_flags;
1112 int ret;
1113 int i;
1114
1115 index = skb_get_queue_mapping(skb);
1116 /* Mapping strategy:
1117 * queue_mapping = 0, unclassified, packet xmited through ring16
1118 * queue_mapping = 1, goes to ring 0. (highest priority queue
1119 * queue_mapping = 2, goes to ring 1.
1120 * queue_mapping = 3, goes to ring 2.
1121 * queue_mapping = 4, goes to ring 3.
1122 */
1123 if (index == 0)
1124 index = DESC_INDEX;
1125 else
1126 index -= 1;
1127
1c1008c7
FF		 1128 nr_frags = skb_shinfo(skb)->nr_frags;
1129 ring = &priv->tx_rings[index];
1130
1131 spin_lock_irqsave(&ring->lock, flags);
1132 if (ring->free_bds <= nr_frags + 1) {
1133 netif_stop_subqueue(dev, ring->queue);
1134 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1135 __func__, index, ring->queue);
1136 ret = NETDEV_TX_BUSY;
1137 goto out;
1138 }
1139
1c1008c7
FF		 1140 /* set the SKB transmit checksum */
1141 if (priv->desc_64b_en) {
1142 ret = bcmgenet_put_tx_csum(dev, skb);
1143 if (ret) {
1144 ret = NETDEV_TX_OK;
1145 goto out;
1146 }
1147 }
1148
1149 dma_desc_flags = DMA_SOP;
1150 if (nr_frags == 0)
1151 dma_desc_flags |= DMA_EOP;
1152
1153 /* Transmit single SKB or head of fragment list */
1154 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1155 if (ret) {
1156 ret = NETDEV_TX_OK;
1157 goto out;
1158 }
1159
1160 /* xmit fragment */
1161 for (i = 0; i < nr_frags; i++) {
1162 ret = bcmgenet_xmit_frag(dev,
1163 &skb_shinfo(skb)->frags[i],
1164 (i == nr_frags - 1) ? DMA_EOP : 0, ring);
1165 if (ret) {
1166 ret = NETDEV_TX_OK;
1167 goto out;
1168 }
1169 }
1170
d03825fb
FF		 1171 skb_tx_timestamp(skb);
1172
1c1008c7
FF		 1173 /* we kept a software copy of how much we should advance the TDMA
1174 * producer index, now write it down to the hardware
1175 */
1176 bcmgenet_tdma_ring_writel(priv, ring->index,
1177 ring->prod_index, TDMA_PROD_INDEX);
1178
1179 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
1180 netif_stop_subqueue(dev, ring->queue);
1181 ring->int_enable(priv, ring);
1182 }
1183
1184out:
1185 spin_unlock_irqrestore(&ring->lock, flags);
1186
1187 return ret;
1188}
1189
1190
1191static int bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1192 struct enet_cb *cb)
1193{
1194 struct device *kdev = &priv->pdev->dev;
1195 struct sk_buff *skb;
1196 dma_addr_t mapping;
1197 int ret;
1198
1199 skb = netdev_alloc_skb(priv->dev,
1200 priv->rx_buf_len + SKB_ALIGNMENT);
1201 if (!skb)
1202 return -ENOMEM;
1203
1204 /* a caller did not release this control block */
1205 WARN_ON(cb->skb != NULL);
1206 cb->skb = skb;
1207 mapping = dma_map_single(kdev, skb->data,
1208 priv->rx_buf_len, DMA_FROM_DEVICE);
1209 ret = dma_mapping_error(kdev, mapping);
1210 if (ret) {
1211 bcmgenet_free_cb(cb);
1212 netif_err(priv, rx_err, priv->dev,
1213 "%s DMA map failed\n", __func__);
1214 return ret;
1215 }
1216
1217 dma_unmap_addr_set(cb, dma_addr, mapping);
1218 /* assign packet, prepare descriptor, and advance pointer */
1219
1220 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1221
1222 /* turn on the newly assigned BD for DMA to use */
1223 priv->rx_bd_assign_index++;
1224 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1225
1226 priv->rx_bd_assign_ptr = priv->rx_bds +
1227 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1228
1229 return 0;
1230}
1231
1232/* bcmgenet_desc_rx - descriptor based rx process.
1233 * this could be called from bottom half, or from NAPI polling method.
1234 */
1235static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1236 unsigned int budget)
1237{
1238 struct net_device *dev = priv->dev;
1239 struct enet_cb *cb;
1240 struct sk_buff *skb;
1241 u32 dma_length_status;
1242 unsigned long dma_flag;
1243 int len, err;
1244 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1245 unsigned int p_index;
1246 unsigned int chksum_ok = 0;
1247
1248 p_index = bcmgenet_rdma_ring_readl(priv,
1249 DESC_INDEX, RDMA_PROD_INDEX);
1250 p_index &= DMA_P_INDEX_MASK;
1251
1252 if (p_index < priv->rx_c_index)
1253 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1254 priv->rx_c_index + p_index;
1255 else
1256 rxpkttoprocess = p_index - priv->rx_c_index;
1257
1258 netif_dbg(priv, rx_status, dev,
1259 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1260
1261 while ((rxpktprocessed < rxpkttoprocess) &&
1262 (rxpktprocessed < budget)) {
1263
1264 /* Unmap the packet contents such that we can use the
1265 * RSV from the 64 bytes descriptor when enabled and save
1266 * a 32-bits register read
1267 */
1268 cb = &priv->rx_cbs[priv->rx_read_ptr];
1269 skb = cb->skb;
1270 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1271 priv->rx_buf_len, DMA_FROM_DEVICE);
1272
1273 if (!priv->desc_64b_en) {
1274 dma_length_status = dmadesc_get_length_status(priv,
1275 priv->rx_bds +
1276 (priv->rx_read_ptr *
1277 DMA_DESC_SIZE));
1278 } else {
1279 struct status_64 *status;
1280 status = (struct status_64 *)skb->data;
1281 dma_length_status = status->length_status;
1282 }
1283
1284 /* DMA flags and length are still valid no matter how
1285 * we got the Receive Status Vector (64B RSB or register)
1286 */
1287 dma_flag = dma_length_status & 0xffff;
1288 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1289
1290 netif_dbg(priv, rx_status, dev,
1291 "%s: p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1292 __func__, p_index, priv->rx_c_index, priv->rx_read_ptr,
1293 dma_length_status);
1294
1295 rxpktprocessed++;
1296
1297 priv->rx_read_ptr++;
1298 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1299
1300 /* out of memory, just drop packets at the hardware level */
1301 if (unlikely(!skb)) {
1302 dev->stats.rx_dropped++;
1303 dev->stats.rx_errors++;
1304 goto refill;
1305 }
1306
1307 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1308 netif_err(priv, rx_status, dev,
1309 "Droping fragmented packet!\n");
1310 dev->stats.rx_dropped++;
1311 dev->stats.rx_errors++;
1312 dev_kfree_skb_any(cb->skb);
1313 cb->skb = NULL;
1314 goto refill;
1315 }
1316 /* report errors */
1317 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1318 DMA_RX_OV |
1319 DMA_RX_NO |
1320 DMA_RX_LG |
1321 DMA_RX_RXER))) {
1322 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1323 (unsigned int)dma_flag);
1324 if (dma_flag & DMA_RX_CRC_ERROR)
1325 dev->stats.rx_crc_errors++;
1326 if (dma_flag & DMA_RX_OV)
1327 dev->stats.rx_over_errors++;
1328 if (dma_flag & DMA_RX_NO)
1329 dev->stats.rx_frame_errors++;
1330 if (dma_flag & DMA_RX_LG)
1331 dev->stats.rx_length_errors++;
1332 dev->stats.rx_dropped++;
1333 dev->stats.rx_errors++;
1334
1335 /* discard the packet and advance consumer index.*/
1336 dev_kfree_skb_any(cb->skb);
1337 cb->skb = NULL;
1338 goto refill;
1339 } /* error packet */
1340
1341 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1342 priv->desc_rxchk_en;
1343
1344 skb_put(skb, len);
1345 if (priv->desc_64b_en) {
1346 skb_pull(skb, 64);
1347 len -= 64;
1348 }
1349
1350 if (likely(chksum_ok))
1351 skb->ip_summed = CHECKSUM_UNNECESSARY;
1352
1353 /* remove hardware 2bytes added for IP alignment */
1354 skb_pull(skb, 2);
1355 len -= 2;
1356
1357 if (priv->crc_fwd_en) {
1358 skb_trim(skb, len - ETH_FCS_LEN);
1359 len -= ETH_FCS_LEN;
1360 }
1361
1362 /*Finish setting up the received SKB and send it to the kernel*/
1363 skb->protocol = eth_type_trans(skb, priv->dev);
1364 dev->stats.rx_packets++;
1365 dev->stats.rx_bytes += len;
1366 if (dma_flag & DMA_RX_MULT)
1367 dev->stats.multicast++;
1368
1369 /* Notify kernel */
1370 napi_gro_receive(&priv->napi, skb);
1371 cb->skb = NULL;
1372 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1373
1374 /* refill RX path on the current control block */
1375refill:
1376 err = bcmgenet_rx_refill(priv, cb);
1377 if (err)
1378 netif_err(priv, rx_err, dev, "Rx refill failed\n");
1379 }
1380
1381 return rxpktprocessed;
1382}
1383
1384/* Assign skb to RX DMA descriptor. */
1385static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1386{
1387 struct enet_cb *cb;
1388 int ret = 0;
1389 int i;
1390
1391 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1392
1393 /* loop here for each buffer needing assign */
1394 for (i = 0; i < priv->num_rx_bds; i++) {
1395 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1396 if (cb->skb)
1397 continue;
1398
1399 /* set the DMA descriptor length once and for all
1400 * it will only change if we support dynamically sizing
1401 * priv->rx_buf_len, but we do not
1402 */
1403 dmadesc_set_length_status(priv, priv->rx_bd_assign_ptr,
1404 priv->rx_buf_len << DMA_BUFLENGTH_SHIFT);
1405
1406 ret = bcmgenet_rx_refill(priv, cb);
1407 if (ret)
1408 break;
1409
1410 }
1411
1412 return ret;
1413}
1414
1415static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1416{
1417 struct enet_cb *cb;
1418 int i;
1419
1420 for (i = 0; i < priv->num_rx_bds; i++) {
1421 cb = &priv->rx_cbs[i];
1422
1423 if (dma_unmap_addr(cb, dma_addr)) {
1424 dma_unmap_single(&priv->dev->dev,
1425 dma_unmap_addr(cb, dma_addr),
1426 priv->rx_buf_len, DMA_FROM_DEVICE);
1427 dma_unmap_addr_set(cb, dma_addr, 0);
1428 }
1429
1430 if (cb->skb)
1431 bcmgenet_free_cb(cb);
1432 }
1433}
1434
1435static int reset_umac(struct bcmgenet_priv *priv)
1436{
1437 struct device *kdev = &priv->pdev->dev;
1438 unsigned int timeout = 0;
1439 u32 reg;
1440
1441 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1442 bcmgenet_rbuf_ctrl_set(priv, 0);
1443 udelay(10);
1444
1445 /* disable MAC while updating its registers */
1446 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1447
1448 /* issue soft reset, wait for it to complete */
1449 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1450 while (timeout++ < 1000) {
1451 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1452 if (!(reg & CMD_SW_RESET))
1453 return 0;
1454
1455 udelay(1);
1456 }
1457
1458 if (timeout == 1000) {
1459 dev_err(kdev,
1460 "timeout waiting for MAC to come out of resetn\n");
1461 return -ETIMEDOUT;
1462 }
1463
1464 return 0;
1465}
1466
1467static int init_umac(struct bcmgenet_priv *priv)
1468{
1469 struct device *kdev = &priv->pdev->dev;
1470 int ret;
1471 u32 reg, cpu_mask_clear;
1472
1473 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1474
1475 ret = reset_umac(priv);
1476 if (ret)
1477 return ret;
1478
1479 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1480 /* clear tx/rx counter */
1481 bcmgenet_umac_writel(priv,
1482 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, UMAC_MIB_CTRL);
1483 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1484
1485 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1486
1487 /* init rx registers, enable ip header optimization */
1488 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1489 reg |= RBUF_ALIGN_2B;
1490 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1491
1492 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1493 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1494
1495 /* Mask all interrupts.*/
1496 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1497 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1498 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1499
1500 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1501
1502 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1503
1504 /* Monitor cable plug/unpluged event for internal PHY */
1505 if (phy_is_internal(priv->phydev))
1506 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1507 else if (priv->ext_phy)
1508 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1509 else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1510 reg = bcmgenet_bp_mc_get(priv);
1511 reg |= BIT(priv->hw_params->bp_in_en_shift);
1512
1513 /* bp_mask: back pressure mask */
1514 if (netif_is_multiqueue(priv->dev))
1515 reg |= priv->hw_params->bp_in_mask;
1516 else
1517 reg &= ~priv->hw_params->bp_in_mask;
1518 bcmgenet_bp_mc_set(priv, reg);
1519 }
1520
1521 /* Enable MDIO interrupts on GENET v3+ */
1522 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1523 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1524
1525 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear,
1526 INTRL2_CPU_MASK_CLEAR);
1527
1528 /* Enable rx/tx engine.*/
1529 dev_dbg(kdev, "done init umac\n");
1530
1531 return 0;
1532}
1533
1534/* Initialize all house-keeping variables for a TX ring, along
1535 * with corresponding hardware registers
1536 */
1537static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1538 unsigned int index, unsigned int size,
1539 unsigned int write_ptr, unsigned int end_ptr)
1540{
1541 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1542 u32 words_per_bd = WORDS_PER_BD(priv);
1543 u32 flow_period_val = 0;
1544 unsigned int first_bd;
1545
1546 spin_lock_init(&ring->lock);
1547 ring->index = index;
1548 if (index == DESC_INDEX) {
1549 ring->queue = 0;
1550 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1551 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1552 } else {
1553 ring->queue = index + 1;
1554 ring->int_enable = bcmgenet_tx_ring_int_enable;
1555 ring->int_disable = bcmgenet_tx_ring_int_disable;
1556 }
1557 ring->cbs = priv->tx_cbs + write_ptr;
1558 ring->size = size;
1559 ring->c_index = 0;
1560 ring->free_bds = size;
1561 ring->write_ptr = write_ptr;
1562 ring->cb_ptr = write_ptr;
1563 ring->end_ptr = end_ptr - 1;
1564 ring->prod_index = 0;
1565
1566 /* Set flow period for ring != 16 */
1567 if (index != DESC_INDEX)
1568 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1569
1570 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1571 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1572 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1573 /* Disable rate control for now */
1574 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1575 TDMA_FLOW_PERIOD);
1576 /* Unclassified traffic goes to ring 16 */
1577 bcmgenet_tdma_ring_writel(priv, index,
1578 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1579 DMA_RING_BUF_SIZE);
1580
1581 first_bd = write_ptr;
1582
1583 /* Set start and end address, read and write pointers */
1584 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1585 DMA_START_ADDR);
1586 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1587 TDMA_READ_PTR);
1588 bcmgenet_tdma_ring_writel(priv, index, first_bd,
1589 TDMA_WRITE_PTR);
1590 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1591 DMA_END_ADDR);
1592}
1593
1594/* Initialize a RDMA ring */
1595static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1596 unsigned int index, unsigned int size)
1597{
1598 u32 words_per_bd = WORDS_PER_BD(priv);
1599 int ret;
1600
1601 priv->num_rx_bds = TOTAL_DESC;
1602 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1603 priv->rx_bd_assign_ptr = priv->rx_bds;
1604 priv->rx_bd_assign_index = 0;
1605 priv->rx_c_index = 0;
1606 priv->rx_read_ptr = 0;
1607 priv->rx_cbs = kzalloc(priv->num_rx_bds * sizeof(struct enet_cb),
1608 GFP_KERNEL);
1609 if (!priv->rx_cbs)
1610 return -ENOMEM;
1611
1612 ret = bcmgenet_alloc_rx_buffers(priv);
1613 if (ret) {
1614 kfree(priv->rx_cbs);
1615 return ret;
1616 }
1617
1618 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1619 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1620 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1621 bcmgenet_rdma_ring_writel(priv, index,
1622 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1623 DMA_RING_BUF_SIZE);
1624 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1625 bcmgenet_rdma_ring_writel(priv, index,
1626 words_per_bd * size - 1, DMA_END_ADDR);
1627 bcmgenet_rdma_ring_writel(priv, index,
1628 (DMA_FC_THRESH_LO << DMA_XOFF_THRESHOLD_SHIFT) |
1629 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1630 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1631
1632 return ret;
1633}
1634
1635/* init multi xmit queues, only available for GENET2+
1636 * the queue is partitioned as follows:
1637 *
1638 * queue 0 - 3 is priority based, each one has 32 descriptors,
1639 * with queue 0 being the highest priority queue.
1640 *
1641 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1642 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1643 * descriptors.
1644 *
1645 * The transmit control block pool is then partitioned as following:
1646 * - tx_cbs[0...127] are for queue 16
1647 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1648 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1649 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1650 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1651 */
1652static void bcmgenet_init_multiq(struct net_device *dev)
1653{
1654 struct bcmgenet_priv *priv = netdev_priv(dev);
1655 unsigned int i, dma_enable;
1656 u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
1657
1658 if (!netif_is_multiqueue(dev)) {
1659 netdev_warn(dev, "called with non multi queue aware HW\n");
1660 return;
1661 }
1662
1663 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1664 dma_enable = dma_ctrl & DMA_EN;
1665 dma_ctrl &= ~DMA_EN;
1666 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1667
1668 /* Enable strict priority arbiter mode */
1669 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1670
1671 for (i = 0; i < priv->hw_params->tx_queues; i++) {
1672 /* first 64 tx_cbs are reserved for default tx queue
1673 * (ring 16)
1674 */
1675 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1676 i * priv->hw_params->bds_cnt,
1677 (i + 1) * priv->hw_params->bds_cnt);
1678
1679 /* Configure ring as decriptor ring and setup priority */
1680 ring_cfg |= 1 << i;
1681 dma_priority |= ((GENET_Q0_PRIORITY + i) <<
1682 (GENET_MAX_MQ_CNT + 1) * i);
1683 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1684 }
1685
1686 /* Enable rings */
1687 reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1688 reg |= ring_cfg;
1689 bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1690
1691 /* Use configured rings priority and set ring #16 priority */
1692 reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
1693 reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
1694 reg |= dma_priority;
1695 bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
1696
1697 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1698 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1699 reg |= dma_ctrl;
1700 if (dma_enable)
1701 reg |= DMA_EN;
1702 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1703}
1704
1705static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1706{
1707 int i;
1708
1709 /* disable DMA */
1710 bcmgenet_rdma_writel(priv, 0, DMA_CTRL);
1711 bcmgenet_tdma_writel(priv, 0, DMA_CTRL);
1712
1713 for (i = 0; i < priv->num_tx_bds; i++) {
1714 if (priv->tx_cbs[i].skb != NULL) {
1715 dev_kfree_skb(priv->tx_cbs[i].skb);
1716 priv->tx_cbs[i].skb = NULL;
1717 }
1718 }
1719
1720 bcmgenet_free_rx_buffers(priv);
1721 kfree(priv->rx_cbs);
1722 kfree(priv->tx_cbs);
1723}
1724
1725/* init_edma: Initialize DMA control register */
1726static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1727{
1728 int ret;
1729
1730 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1731
1732 /* by default, enable ring 16 (descriptor based) */
1733 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1734 if (ret) {
1735 netdev_err(priv->dev, "failed to initialize RX ring\n");
1736 return ret;
1737 }
1738
1739 /* init rDma */
1740 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1741
1742 /* Init tDma */
1743 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1744
1745 /* Initialize commont TX ring structures */
1746 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1747 priv->num_tx_bds = TOTAL_DESC;
1748 priv->tx_cbs = kzalloc(priv->num_tx_bds * sizeof(struct enet_cb),
1749 GFP_KERNEL);
1750 if (!priv->tx_cbs) {
1751 bcmgenet_fini_dma(priv);
1752 return -ENOMEM;
1753 }
1754
1755 /* initialize multi xmit queue */
1756 bcmgenet_init_multiq(priv->dev);
1757
1758 /* initialize special ring 16 */
1759 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1760 priv->hw_params->tx_queues * priv->hw_params->bds_cnt,
1761 TOTAL_DESC);
1762
1763 return 0;
1764}
1765
1766/* NAPI polling method*/
1767static int bcmgenet_poll(struct napi_struct *napi, int budget)
1768{
1769 struct bcmgenet_priv *priv = container_of(napi,
1770 struct bcmgenet_priv, napi);
1771 unsigned int work_done;
1772
1773 /* tx reclaim */
1774 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1775
1776 work_done = bcmgenet_desc_rx(priv, budget);
1777
1778 /* Advancing our consumer index*/
1779 priv->rx_c_index += work_done;
1780 priv->rx_c_index &= DMA_C_INDEX_MASK;
1781 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1782 priv->rx_c_index, RDMA_CONS_INDEX);
1783 if (work_done < budget) {
1784 napi_complete(napi);
1785 bcmgenet_intrl2_0_writel(priv,
1786 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_CLEAR);
1787 }
1788
1789 return work_done;
1790}
1791
1792/* Interrupt bottom half */
1793static void bcmgenet_irq_task(struct work_struct *work)
1794{
1795 struct bcmgenet_priv *priv = container_of(
1796 work, struct bcmgenet_priv, bcmgenet_irq_work);
1797
1798 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1799
1800 /* Link UP/DOWN event */
1801 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1802 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d
FF		 1803 phy_mac_interrupt(priv->phydev,
1804 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 1805 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
1806 }
1807}
1808
1809/* bcmgenet_isr1: interrupt handler for ring buffer. */
1810static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
1811{
1812 struct bcmgenet_priv *priv = dev_id;
1813 unsigned int index;
1814
1815 /* Save irq status for bottom-half processing. */
1816 priv->irq1_stat =
1817 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
1818 ~priv->int1_mask;
1819 /* clear inerrupts*/
1820 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
1821
1822 netif_dbg(priv, intr, priv->dev,
1823 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1824 /* Check the MBDONE interrupts.
1825 * packet is done, reclaim descriptors
1826 */
1827 if (priv->irq1_stat & 0x0000ffff) {
1828 index = 0;
1829 for (index = 0; index < 16; index++) {
1830 if (priv->irq1_stat & (1 << index))
1831 bcmgenet_tx_reclaim(priv->dev,
1832 &priv->tx_rings[index]);
1833 }
1834 }
1835 return IRQ_HANDLED;
1836}
1837
1838/* bcmgenet_isr0: Handle various interrupts. */
1839static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
1840{
1841 struct bcmgenet_priv *priv = dev_id;
1842
1843 /* Save irq status for bottom-half processing. */
1844 priv->irq0_stat =
1845 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1846 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1847 /* clear inerrupts*/
1848 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1849
1850 netif_dbg(priv, intr, priv->dev,
1851 "IRQ=0x%x\n", priv->irq0_stat);
1852
1853 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
1854 /* We use NAPI(software interrupt throttling, if
1855 * Rx Descriptor throttling is not used.
1856 * Disable interrupt, will be enabled in the poll method.
1857 */
1858 if (likely(napi_schedule_prep(&priv->napi))) {
1859 bcmgenet_intrl2_0_writel(priv,
1860 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_SET);
1861 __napi_schedule(&priv->napi);
1862 }
1863 }
1864 if (priv->irq0_stat &
1865 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
1866 /* Tx reclaim */
1867 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1868 }
1869 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
1870 UMAC_IRQ_PHY_DET_F |
1871 UMAC_IRQ_LINK_UP |
1872 UMAC_IRQ_LINK_DOWN |
1873 UMAC_IRQ_HFB_SM |
1874 UMAC_IRQ_HFB_MM |
1875 UMAC_IRQ_MPD_R)) {
1876 /* all other interested interrupts handled in bottom half */
1877 schedule_work(&priv->bcmgenet_irq_work);
1878 }
1879
1880 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1881 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1882 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1883 wake_up(&priv->wq);
1884 }
1885
1886 return IRQ_HANDLED;
1887}
1888
1889static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
1890{
1891 u32 reg;
1892
1893 reg = bcmgenet_rbuf_ctrl_get(priv);
1894 reg |= BIT(1);
1895 bcmgenet_rbuf_ctrl_set(priv, reg);
1896 udelay(10);
1897
1898 reg &= ~BIT(1);
1899 bcmgenet_rbuf_ctrl_set(priv, reg);
1900 udelay(10);
1901}
1902
1903static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
1904 unsigned char *addr)
1905{
1906 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1907 (addr[2] << 8) | addr[3], UMAC_MAC0);
1908 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1909}
1910
1911static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
1912{
1913 int ret;
1914
1915 /* From WOL-enabled suspend, switch to regular clock */
1916 clk_disable(priv->clk_wol);
1917 /* init umac registers to synchronize s/w with h/w */
1918 ret = init_umac(priv);
1919 if (ret)
1920 return ret;
1921
80d8e96d 1922 phy_init_hw(priv->phydev);
1c1008c7
FF		 1923 /* Speed settings must be restored */
1924 bcmgenet_mii_config(priv->dev);
1925
1926 return 0;
1927}
1928
1929/* Returns a reusable dma control register value */
1930static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
1931{
1932 u32 reg;
1933 u32 dma_ctrl;
1934
1935 /* disable DMA */
1936 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
1937 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1938 reg &= ~dma_ctrl;
1939 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1940
1941 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1942 reg &= ~dma_ctrl;
1943 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1944
1945 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
1946 udelay(10);
1947 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
1948
1949 return dma_ctrl;
1950}
1951
1952static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
1953{
1954 u32 reg;
1955
1956 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1957 reg |= dma_ctrl;
1958 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1959
1960 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1961 reg |= dma_ctrl;
1962 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1963}
1964
1965static int bcmgenet_open(struct net_device *dev)
1966{
1967 struct bcmgenet_priv *priv = netdev_priv(dev);
1968 unsigned long dma_ctrl;
1969 u32 reg;
1970 int ret;
1971
1972 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
1973
1974 /* Turn on the clock */
1975 if (!IS_ERR(priv->clk))
1976 clk_prepare_enable(priv->clk);
1977
1978 /* take MAC out of reset */
1979 bcmgenet_umac_reset(priv);
1980
1981 ret = init_umac(priv);
1982 if (ret)
1983 goto err_clk_disable;
1984
1985 /* disable ethernet MAC while updating its registers */
1986 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1987 reg &= ~(CMD_TX_EN | CMD_RX_EN);
1988 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1989
1990 bcmgenet_set_hw_addr(priv, dev->dev_addr);
1991
1992 if (priv->wol_enabled) {
1993 ret = bcmgenet_wol_resume(priv);
1994 if (ret)
1995 return ret;
1996 }
1997
1998 if (phy_is_internal(priv->phydev)) {
1999 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2000 reg |= EXT_ENERGY_DET_MASK;
2001 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2002 }
2003
2004 /* Disable RX/TX DMA and flush TX queues */
2005 dma_ctrl = bcmgenet_dma_disable(priv);
2006
2007 /* Reinitialize TDMA and RDMA and SW housekeeping */
2008 ret = bcmgenet_init_dma(priv);
2009 if (ret) {
2010 netdev_err(dev, "failed to initialize DMA\n");
2011 goto err_fini_dma;
2012 }
2013
2014 /* Always enable ring 16 - descriptor ring */
2015 bcmgenet_enable_dma(priv, dma_ctrl);
2016
2017 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2018 dev->name, priv);
2019 if (ret < 0) {
2020 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2021 goto err_fini_dma;
2022 }
2023
2024 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2025 dev->name, priv);
2026 if (ret < 0) {
2027 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2028 goto err_irq0;
2029 }
2030
2031 /* Start the network engine */
2032 napi_enable(&priv->napi);
2033
2034 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2035 reg |= (CMD_TX_EN | CMD_RX_EN);
2036 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2037
2038 /* Make sure we reflect the value of CRC_CMD_FWD */
2039 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2040
2041 device_set_wakeup_capable(&dev->dev, 1);
2042
2043 if (phy_is_internal(priv->phydev))
2044 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2045
2046 netif_tx_start_all_queues(dev);
2047
80d8e96d 2048 phy_start(priv->phydev);
1c1008c7
FF		 2049
2050 return 0;
2051
2052err_irq0:
2053 free_irq(priv->irq0, dev);
2054err_fini_dma:
2055 bcmgenet_fini_dma(priv);
2056err_clk_disable:
2057 if (!IS_ERR(priv->clk))
2058 clk_disable_unprepare(priv->clk);
2059 return ret;
2060}
2061
2062static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2063{
2064 int ret = 0;
2065 int timeout = 0;
2066 u32 reg;
2067
2068 /* Disable TDMA to stop add more frames in TX DMA */
2069 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2070 reg &= ~DMA_EN;
2071 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2072
2073 /* Check TDMA status register to confirm TDMA is disabled */
2074 while (timeout++ < DMA_TIMEOUT_VAL) {
2075 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2076 if (reg & DMA_DISABLED)
2077 break;
2078
2079 udelay(1);
2080 }
2081
2082 if (timeout == DMA_TIMEOUT_VAL) {
2083 netdev_warn(priv->dev,
2084 "Timed out while disabling TX DMA\n");
2085 ret = -ETIMEDOUT;
2086 }
2087
2088 /* Wait 10ms for packet drain in both tx and rx dma */
2089 usleep_range(10000, 20000);
2090
2091 /* Disable RDMA */
2092 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2093 reg &= ~DMA_EN;
2094 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2095
2096 timeout = 0;
2097 /* Check RDMA status register to confirm RDMA is disabled */
2098 while (timeout++ < DMA_TIMEOUT_VAL) {
2099 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2100 if (reg & DMA_DISABLED)
2101 break;
2102
2103 udelay(1);
2104 }
2105
2106 if (timeout == DMA_TIMEOUT_VAL) {
2107 netdev_warn(priv->dev,
2108 "Timed out while disabling RX DMA\n");
2109 ret = -ETIMEDOUT;
2110 }
2111
2112 return ret;
2113}
2114
2115static int bcmgenet_close(struct net_device *dev)
2116{
2117 struct bcmgenet_priv *priv = netdev_priv(dev);
2118 int ret;
2119 u32 reg;
2120
2121 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2122
80d8e96d 2123 phy_stop(priv->phydev);
1c1008c7
FF		 2124
2125 /* Disable MAC receive */
2126 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2127 reg &= ~CMD_RX_EN;
2128 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2129
2130 netif_tx_stop_all_queues(dev);
2131
2132 ret = bcmgenet_dma_teardown(priv);
2133 if (ret)
2134 return ret;
2135
2136 /* Disable MAC transmit. TX DMA disabled have to done before this */
2137 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2138 reg &= ~CMD_TX_EN;
2139 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2140
2141 napi_disable(&priv->napi);
2142
2143 /* tx reclaim */
2144 bcmgenet_tx_reclaim_all(dev);
2145 bcmgenet_fini_dma(priv);
2146
2147 free_irq(priv->irq0, priv);
2148 free_irq(priv->irq1, priv);
2149
2150 /* Wait for pending work items to complete - we are stopping
2151 * the clock now. Since interrupts are disabled, no new work
2152 * will be scheduled.
2153 */
2154 cancel_work_sync(&priv->bcmgenet_irq_work);
2155
2156 if (phy_is_internal(priv->phydev))
2157 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2158
2159 if (priv->wol_enabled)
2160 clk_enable(priv->clk_wol);
2161
2162 if (!IS_ERR(priv->clk))
2163 clk_disable_unprepare(priv->clk);
2164
2165 return 0;
2166}
2167
2168static void bcmgenet_timeout(struct net_device *dev)
2169{
2170 struct bcmgenet_priv *priv = netdev_priv(dev);
2171
2172 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2173
2174 dev->trans_start = jiffies;
2175
2176 dev->stats.tx_errors++;
2177
2178 netif_tx_wake_all_queues(dev);
2179}
2180
2181#define MAX_MC_COUNT 16
2182
2183static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2184 unsigned char *addr,
2185 int *i,
2186 int *mc)
2187{
2188 u32 reg;
2189
2190 bcmgenet_umac_writel(priv,
2191 addr[0] << 8 | addr[1], UMAC_MDF_ADDR + (*i * 4));
2192 bcmgenet_umac_writel(priv,
2193 addr[2] << 24 | addr[3] << 16 |
2194 addr[4] << 8 | addr[5],
2195 UMAC_MDF_ADDR + ((*i + 1) * 4));
2196 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2197 reg |= (1 << (MAX_MC_COUNT - *mc));
2198 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2199 *i += 2;
2200 (*mc)++;
2201}
2202
2203static void bcmgenet_set_rx_mode(struct net_device *dev)
2204{
2205 struct bcmgenet_priv *priv = netdev_priv(dev);
2206 struct netdev_hw_addr *ha;
2207 int i, mc;
2208 u32 reg;
2209
2210 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2211
2212 /* Promiscous mode */
2213 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2214 if (dev->flags & IFF_PROMISC) {
2215 reg |= CMD_PROMISC;
2216 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2217 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2218 return;
2219 } else {
2220 reg &= ~CMD_PROMISC;
2221 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2222 }
2223
2224 /* UniMac doesn't support ALLMULTI */
2225 if (dev->flags & IFF_ALLMULTI) {
2226 netdev_warn(dev, "ALLMULTI is not supported\n");
2227 return;
2228 }
2229
2230 /* update MDF filter */
2231 i = 0;
2232 mc = 0;
2233 /* Broadcast */
2234 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2235 /* my own address.*/
2236 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2237 /* Unicast list*/
2238 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2239 return;
2240
2241 if (!netdev_uc_empty(dev))
2242 netdev_for_each_uc_addr(ha, dev)
2243 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2244 /* Multicast */
2245 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2246 return;
2247
2248 netdev_for_each_mc_addr(ha, dev)
2249 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2250}
2251
2252/* Set the hardware MAC address. */
2253static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2254{
2255 struct sockaddr *addr = p;
2256
2257 /* Setting the MAC address at the hardware level is not possible
2258 * without disabling the UniMAC RX/TX enable bits.
2259 */
2260 if (netif_running(dev))
2261 return -EBUSY;
2262
2263 ether_addr_copy(dev->dev_addr, addr->sa_data);
2264
2265 return 0;
2266}
2267
1c1008c7
FF		 2268static const struct net_device_ops bcmgenet_netdev_ops = {
2269 .ndo_open = bcmgenet_open,
2270 .ndo_stop = bcmgenet_close,
2271 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2272 .ndo_tx_timeout = bcmgenet_timeout,
2273 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2274 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2275 .ndo_do_ioctl = bcmgenet_ioctl,
2276 .ndo_set_features = bcmgenet_set_features,
2277};
2278
2279/* Array of GENET hardware parameters/characteristics */
2280static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2281 [GENET_V1] = {
2282 .tx_queues = 0,
2283 .rx_queues = 0,
2284 .bds_cnt = 0,
2285 .bp_in_en_shift = 16,
2286 .bp_in_mask = 0xffff,
2287 .hfb_filter_cnt = 16,
2288 .qtag_mask = 0x1F,
2289 .hfb_offset = 0x1000,
2290 .rdma_offset = 0x2000,
2291 .tdma_offset = 0x3000,
2292 .words_per_bd = 2,
2293 },
2294 [GENET_V2] = {
2295 .tx_queues = 4,
2296 .rx_queues = 4,
2297 .bds_cnt = 32,
2298 .bp_in_en_shift = 16,
2299 .bp_in_mask = 0xffff,
2300 .hfb_filter_cnt = 16,
2301 .qtag_mask = 0x1F,
2302 .tbuf_offset = 0x0600,
2303 .hfb_offset = 0x1000,
2304 .hfb_reg_offset = 0x2000,
2305 .rdma_offset = 0x3000,
2306 .tdma_offset = 0x4000,
2307 .words_per_bd = 2,
2308 .flags = GENET_HAS_EXT,
2309 },
2310 [GENET_V3] = {
2311 .tx_queues = 4,
2312 .rx_queues = 4,
2313 .bds_cnt = 32,
2314 .bp_in_en_shift = 17,
2315 .bp_in_mask = 0x1ffff,
2316 .hfb_filter_cnt = 48,
2317 .qtag_mask = 0x3F,
2318 .tbuf_offset = 0x0600,
2319 .hfb_offset = 0x8000,
2320 .hfb_reg_offset = 0xfc00,
2321 .rdma_offset = 0x10000,
2322 .tdma_offset = 0x11000,
2323 .words_per_bd = 2,
2324 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2325 },
2326 [GENET_V4] = {
2327 .tx_queues = 4,
2328 .rx_queues = 4,
2329 .bds_cnt = 32,
2330 .bp_in_en_shift = 17,
2331 .bp_in_mask = 0x1ffff,
2332 .hfb_filter_cnt = 48,
2333 .qtag_mask = 0x3F,
2334 .tbuf_offset = 0x0600,
2335 .hfb_offset = 0x8000,
2336 .hfb_reg_offset = 0xfc00,
2337 .rdma_offset = 0x2000,
2338 .tdma_offset = 0x4000,
2339 .words_per_bd = 3,
2340 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2341 },
2342};
2343
2344/* Infer hardware parameters from the detected GENET version */
2345static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2346{
2347 struct bcmgenet_hw_params *params;
2348 u32 reg;
2349 u8 major;
2350
2351 if (GENET_IS_V4(priv)) {
2352 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2353 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2354 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2355 priv->version = GENET_V4;
2356 } else if (GENET_IS_V3(priv)) {
2357 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2358 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2359 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2360 priv->version = GENET_V3;
2361 } else if (GENET_IS_V2(priv)) {
2362 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2363 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2364 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2365 priv->version = GENET_V2;
2366 } else if (GENET_IS_V1(priv)) {
2367 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2368 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2369 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2370 priv->version = GENET_V1;
2371 }
2372
2373 /* enum genet_version starts at 1 */
2374 priv->hw_params = &bcmgenet_hw_params[priv->version];
2375 params = priv->hw_params;
2376
2377 /* Read GENET HW version */
2378 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2379 major = (reg >> 24 & 0x0f);
2380 if (major == 5)
2381 major = 4;
2382 else if (major == 0)
2383 major = 1;
2384 if (major != priv->version) {
2385 dev_err(&priv->pdev->dev,
2386 "GENET version mismatch, got: %d, configured for: %d\n",
2387 major, priv->version);
2388 }
2389
2390 /* Print the GENET core version */
2391 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2392 major, (reg >> 16) & 0x0f, reg & 0xffff);
2393
2394#ifdef CONFIG_PHYS_ADDR_T_64BIT
2395 if (!(params->flags & GENET_HAS_40BITS))
2396 pr_warn("GENET does not support 40-bits PA\n");
2397#endif
2398
2399 pr_debug("Configuration for version: %d\n"
2400 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2401 "BP << en: %2d, BP msk: 0x%05x\n"
2402 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2403 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2404 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2405 "Words/BD: %d\n",
2406 priv->version,
2407 params->tx_queues, params->rx_queues, params->bds_cnt,
2408 params->bp_in_en_shift, params->bp_in_mask,
2409 params->hfb_filter_cnt, params->qtag_mask,
2410 params->tbuf_offset, params->hfb_offset,
2411 params->hfb_reg_offset,
2412 params->rdma_offset, params->tdma_offset,
2413 params->words_per_bd);
2414}
2415
2416static const struct of_device_id bcmgenet_match[] = {
2417 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2418 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2419 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2420 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2421 { },
2422};
2423
2424static int bcmgenet_probe(struct platform_device *pdev)
2425{
2426 struct device_node *dn = pdev->dev.of_node;
2427 const struct of_device_id *of_id;
2428 struct bcmgenet_priv *priv;
2429 struct net_device *dev;
2430 const void *macaddr;
2431 struct resource *r;
2432 int err = -EIO;
2433
2434 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2435 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2436 if (!dev) {
2437 dev_err(&pdev->dev, "can't allocate net device\n");
2438 return -ENOMEM;
2439 }
2440
2441 of_id = of_match_node(bcmgenet_match, dn);
2442 if (!of_id)
2443 return -EINVAL;
2444
2445 priv = netdev_priv(dev);
2446 priv->irq0 = platform_get_irq(pdev, 0);
2447 priv->irq1 = platform_get_irq(pdev, 1);
2448 if (!priv->irq0 || !priv->irq1) {
2449 dev_err(&pdev->dev, "can't find IRQs\n");
2450 err = -EINVAL;
2451 goto err;
2452 }
2453
2454 macaddr = of_get_mac_address(dn);
2455 if (!macaddr) {
2456 dev_err(&pdev->dev, "can't find MAC address\n");
2457 err = -EINVAL;
2458 goto err;
2459 }
2460
2461 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2462 priv->base = devm_ioremap_resource(&pdev->dev, r);
2463 if (IS_ERR(priv->base)) {
2464 err = PTR_ERR(priv->base);
1c1008c7
FF		 2465 goto err;
2466 }
2467
2468 SET_NETDEV_DEV(dev, &pdev->dev);
2469 dev_set_drvdata(&pdev->dev, dev);
2470 ether_addr_copy(dev->dev_addr, macaddr);
2471 dev->watchdog_timeo = 2 * HZ;
2472 SET_ETHTOOL_OPS(dev, &bcmgenet_ethtool_ops);
2473 dev->netdev_ops = &bcmgenet_netdev_ops;
2474 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2475
2476 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2477
2478 /* Set hardware features */
2479 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2480 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2481
2482 /* Set the needed headroom to account for any possible
2483 * features enabling/disabling at runtime
2484 */
2485 dev->needed_headroom += 64;
2486
2487 netdev_boot_setup_check(dev);
2488
2489 priv->dev = dev;
2490 priv->pdev = pdev;
2491 priv->version = (enum bcmgenet_version)of_id->data;
2492
2493 bcmgenet_set_hw_params(priv);
2494
1c1008c7
FF		 2495 /* Mii wait queue */
2496 init_waitqueue_head(&priv->wq);
2497 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2498 priv->rx_buf_len = RX_BUF_LENGTH;
2499 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2500
2501 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2502 if (IS_ERR(priv->clk))
2503 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2504
2505 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2506 if (IS_ERR(priv->clk_wol))
2507 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2508
2509 if (!IS_ERR(priv->clk))
2510 clk_prepare_enable(priv->clk);
2511
2512 err = reset_umac(priv);
2513 if (err)
2514 goto err_clk_disable;
2515
2516 err = bcmgenet_mii_init(dev);
2517 if (err)
2518 goto err_clk_disable;
2519
2520 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2521 * just the ring 16 descriptor based TX
2522 */
2523 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2524 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2525
2526 err = register_netdev(dev);
2527 if (err)
2528 goto err_clk_disable;
2529
2530 /* Turn off the main clock, WOL clock is handled separately */
2531 if (!IS_ERR(priv->clk))
2532 clk_disable_unprepare(priv->clk);
2533
2534 return err;
2535
2536err_clk_disable:
2537 if (!IS_ERR(priv->clk))
2538 clk_disable_unprepare(priv->clk);
2539err:
2540 free_netdev(dev);
2541 return err;
2542}
2543
2544static int bcmgenet_remove(struct platform_device *pdev)
2545{
2546 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2547
2548 dev_set_drvdata(&pdev->dev, NULL);
2549 unregister_netdev(priv->dev);
2550 bcmgenet_mii_exit(priv->dev);
2551 free_netdev(priv->dev);
2552
2553 return 0;
2554}
2555
2556
2557static struct platform_driver bcmgenet_driver = {
2558 .probe = bcmgenet_probe,
2559 .remove = bcmgenet_remove,
2560 .driver = {
2561 .name = "bcmgenet",
2562 .owner = THIS_MODULE,
2563 .of_match_table = bcmgenet_match,
2564 },
2565};
2566module_platform_driver(bcmgenet_driver);
2567
2568MODULE_AUTHOR("Broadcom Corporation");
2569MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2570MODULE_ALIAS("platform:bcmgenet");
2571MODULE_LICENSE("GPL");
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