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net: bcmgenet: add UMAC_IRQ_LINK_EVENT
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 106{
107 dmadesc_set_length_status(priv, d, val);
108 dmadesc_set_addr(priv, d, addr);
109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
0034de41
PG		 200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
1c1008c7
FF		 208};
209
210static const u8 bcmgenet_dma_regs_v3plus[] = {
211 [DMA_RING_CFG] = 0x00,
212 [DMA_CTRL] = 0x04,
213 [DMA_STATUS] = 0x08,
214 [DMA_SCB_BURST_SIZE] = 0x0C,
215 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 216 [DMA_PRIORITY_0] = 0x30,
217 [DMA_PRIORITY_1] = 0x34,
218 [DMA_PRIORITY_2] = 0x38,
0034de41
PG		 219 [DMA_INDEX2RING_0] = 0x70,
220 [DMA_INDEX2RING_1] = 0x74,
221 [DMA_INDEX2RING_2] = 0x78,
222 [DMA_INDEX2RING_3] = 0x7C,
223 [DMA_INDEX2RING_4] = 0x80,
224 [DMA_INDEX2RING_5] = 0x84,
225 [DMA_INDEX2RING_6] = 0x88,
226 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 227};
228
229static const u8 bcmgenet_dma_regs_v2[] = {
230 [DMA_RING_CFG] = 0x00,
231 [DMA_CTRL] = 0x04,
232 [DMA_STATUS] = 0x08,
233 [DMA_SCB_BURST_SIZE] = 0x0C,
234 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 235 [DMA_PRIORITY_0] = 0x34,
236 [DMA_PRIORITY_1] = 0x38,
237 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 238};
239
240static const u8 bcmgenet_dma_regs_v1[] = {
241 [DMA_CTRL] = 0x00,
242 [DMA_STATUS] = 0x04,
243 [DMA_SCB_BURST_SIZE] = 0x0C,
244 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 245 [DMA_PRIORITY_0] = 0x34,
246 [DMA_PRIORITY_1] = 0x38,
247 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 248};
249
250/* Set at runtime once bcmgenet version is known */
251static const u8 *bcmgenet_dma_regs;
252
253static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
254{
255 return netdev_priv(dev_get_drvdata(dev));
256}
257
258static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 259 enum dma_reg r)
1c1008c7
FF		 260{
261 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
262 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
263}
264
265static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
266 u32 val, enum dma_reg r)
267{
268 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
269 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
270}
271
272static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 273 enum dma_reg r)
1c1008c7
FF		 274{
275 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
276 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
277}
278
279static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
280 u32 val, enum dma_reg r)
281{
282 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
283 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
284}
285
286/* RDMA/TDMA ring registers and accessors
287 * we merge the common fields and just prefix with T/D the registers
288 * having different meaning depending on the direction
289 */
290enum dma_ring_reg {
291 TDMA_READ_PTR = 0,
292 RDMA_WRITE_PTR = TDMA_READ_PTR,
293 TDMA_READ_PTR_HI,
294 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
295 TDMA_CONS_INDEX,
296 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
297 TDMA_PROD_INDEX,
298 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
299 DMA_RING_BUF_SIZE,
300 DMA_START_ADDR,
301 DMA_START_ADDR_HI,
302 DMA_END_ADDR,
303 DMA_END_ADDR_HI,
304 DMA_MBUF_DONE_THRESH,
305 TDMA_FLOW_PERIOD,
306 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
307 TDMA_WRITE_PTR,
308 RDMA_READ_PTR = TDMA_WRITE_PTR,
309 TDMA_WRITE_PTR_HI,
310 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
311};
312
313/* GENET v4 supports 40-bits pointer addressing
314 * for obvious reasons the LO and HI word parts
315 * are contiguous, but this offsets the other
316 * registers.
317 */
318static const u8 genet_dma_ring_regs_v4[] = {
319 [TDMA_READ_PTR] = 0x00,
320 [TDMA_READ_PTR_HI] = 0x04,
321 [TDMA_CONS_INDEX] = 0x08,
322 [TDMA_PROD_INDEX] = 0x0C,
323 [DMA_RING_BUF_SIZE] = 0x10,
324 [DMA_START_ADDR] = 0x14,
325 [DMA_START_ADDR_HI] = 0x18,
326 [DMA_END_ADDR] = 0x1C,
327 [DMA_END_ADDR_HI] = 0x20,
328 [DMA_MBUF_DONE_THRESH] = 0x24,
329 [TDMA_FLOW_PERIOD] = 0x28,
330 [TDMA_WRITE_PTR] = 0x2C,
331 [TDMA_WRITE_PTR_HI] = 0x30,
332};
333
334static const u8 genet_dma_ring_regs_v123[] = {
335 [TDMA_READ_PTR] = 0x00,
336 [TDMA_CONS_INDEX] = 0x04,
337 [TDMA_PROD_INDEX] = 0x08,
338 [DMA_RING_BUF_SIZE] = 0x0C,
339 [DMA_START_ADDR] = 0x10,
340 [DMA_END_ADDR] = 0x14,
341 [DMA_MBUF_DONE_THRESH] = 0x18,
342 [TDMA_FLOW_PERIOD] = 0x1C,
343 [TDMA_WRITE_PTR] = 0x20,
344};
345
346/* Set at runtime once GENET version is known */
347static const u8 *genet_dma_ring_regs;
348
349static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 350 unsigned int ring,
351 enum dma_ring_reg r)
1c1008c7
FF		 352{
353 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
354 (DMA_RING_SIZE * ring) +
355 genet_dma_ring_regs[r]);
356}
357
358static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 359 unsigned int ring, u32 val,
360 enum dma_ring_reg r)
1c1008c7
FF		 361{
362 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
363 (DMA_RING_SIZE * ring) +
364 genet_dma_ring_regs[r]);
365}
366
367static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 368 unsigned int ring,
369 enum dma_ring_reg r)
1c1008c7
FF		 370{
371 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
372 (DMA_RING_SIZE * ring) +
373 genet_dma_ring_regs[r]);
374}
375
376static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 377 unsigned int ring, u32 val,
378 enum dma_ring_reg r)
1c1008c7
FF		 379{
380 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
381 (DMA_RING_SIZE * ring) +
382 genet_dma_ring_regs[r]);
383}
384
385static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 386 struct ethtool_cmd *cmd)
1c1008c7
FF		 387{
388 struct bcmgenet_priv *priv = netdev_priv(dev);
389
390 if (!netif_running(dev))
391 return -EINVAL;
392
393 if (!priv->phydev)
394 return -ENODEV;
395
396 return phy_ethtool_gset(priv->phydev, cmd);
397}
398
399static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 400 struct ethtool_cmd *cmd)
1c1008c7
FF		 401{
402 struct bcmgenet_priv *priv = netdev_priv(dev);
403
404 if (!netif_running(dev))
405 return -EINVAL;
406
407 if (!priv->phydev)
408 return -ENODEV;
409
410 return phy_ethtool_sset(priv->phydev, cmd);
411}
412
413static int bcmgenet_set_rx_csum(struct net_device *dev,
414 netdev_features_t wanted)
415{
416 struct bcmgenet_priv *priv = netdev_priv(dev);
417 u32 rbuf_chk_ctrl;
418 bool rx_csum_en;
419
420 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
421
422 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
423
424 /* enable rx checksumming */
425 if (rx_csum_en)
426 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
427 else
428 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
429 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 430
431 /* If UniMAC forwards CRC, we need to skip over it to get
432 * a valid CHK bit to be set in the per-packet status word
433 */
434 if (rx_csum_en && priv->crc_fwd_en)
435 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
436 else
437 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
438
1c1008c7
FF		 439 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
440
441 return 0;
442}
443
444static int bcmgenet_set_tx_csum(struct net_device *dev,
445 netdev_features_t wanted)
446{
447 struct bcmgenet_priv *priv = netdev_priv(dev);
448 bool desc_64b_en;
449 u32 tbuf_ctrl, rbuf_ctrl;
450
451 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
452 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
453
454 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
455
456 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
457 if (desc_64b_en) {
458 tbuf_ctrl |= RBUF_64B_EN;
459 rbuf_ctrl |= RBUF_64B_EN;
460 } else {
461 tbuf_ctrl &= ~RBUF_64B_EN;
462 rbuf_ctrl &= ~RBUF_64B_EN;
463 }
464 priv->desc_64b_en = desc_64b_en;
465
466 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
467 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
468
469 return 0;
470}
471
472static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 473 netdev_features_t features)
1c1008c7
FF		 474{
475 netdev_features_t changed = features ^ dev->features;
476 netdev_features_t wanted = dev->wanted_features;
477 int ret = 0;
478
479 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
480 ret = bcmgenet_set_tx_csum(dev, wanted);
481 if (changed & (NETIF_F_RXCSUM))
482 ret = bcmgenet_set_rx_csum(dev, wanted);
483
484 return ret;
485}
486
487static u32 bcmgenet_get_msglevel(struct net_device *dev)
488{
489 struct bcmgenet_priv *priv = netdev_priv(dev);
490
491 return priv->msg_enable;
492}
493
494static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
495{
496 struct bcmgenet_priv *priv = netdev_priv(dev);
497
498 priv->msg_enable = level;
499}
500
501/* standard ethtool support functions. */
502enum bcmgenet_stat_type {
503 BCMGENET_STAT_NETDEV = -1,
504 BCMGENET_STAT_MIB_RX,
505 BCMGENET_STAT_MIB_TX,
506 BCMGENET_STAT_RUNT,
507 BCMGENET_STAT_MISC,
f62ba9c1 508 BCMGENET_STAT_SOFT,
1c1008c7
FF		 509};
510
511struct bcmgenet_stats {
512 char stat_string[ETH_GSTRING_LEN];
513 int stat_sizeof;
514 int stat_offset;
515 enum bcmgenet_stat_type type;
516 /* reg offset from UMAC base for misc counters */
517 u16 reg_offset;
518};
519
520#define STAT_NETDEV(m) { \
521 .stat_string = __stringify(m), \
522 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
523 .stat_offset = offsetof(struct net_device_stats, m), \
524 .type = BCMGENET_STAT_NETDEV, \
525}
526
527#define STAT_GENET_MIB(str, m, _type) { \
528 .stat_string = str, \
529 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
530 .stat_offset = offsetof(struct bcmgenet_priv, m), \
531 .type = _type, \
532}
533
534#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
535#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
536#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 537#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 538
539#define STAT_GENET_MISC(str, m, offset) { \
540 .stat_string = str, \
541 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
542 .stat_offset = offsetof(struct bcmgenet_priv, m), \
543 .type = BCMGENET_STAT_MISC, \
544 .reg_offset = offset, \
545}
546
547
548/* There is a 0xC gap between the end of RX and beginning of TX stats and then
549 * between the end of TX stats and the beginning of the RX RUNT
550 */
551#define BCMGENET_STAT_OFFSET 0xc
552
553/* Hardware counters must be kept in sync because the order/offset
554 * is important here (order in structure declaration = order in hardware)
555 */
556static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
557 /* general stats */
558 STAT_NETDEV(rx_packets),
559 STAT_NETDEV(tx_packets),
560 STAT_NETDEV(rx_bytes),
561 STAT_NETDEV(tx_bytes),
562 STAT_NETDEV(rx_errors),
563 STAT_NETDEV(tx_errors),
564 STAT_NETDEV(rx_dropped),
565 STAT_NETDEV(tx_dropped),
566 STAT_NETDEV(multicast),
567 /* UniMAC RSV counters */
568 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
569 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
570 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
571 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
572 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
573 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
574 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
575 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
576 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
577 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
578 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
579 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
580 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
581 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
582 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
583 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
584 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
585 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
586 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
587 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
588 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
589 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
590 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
591 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
592 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
593 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
594 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
595 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
596 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
597 /* UniMAC TSV counters */
598 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
599 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
600 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
601 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
602 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
603 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
604 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
605 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
606 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
607 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
608 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
609 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
610 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
611 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
612 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
613 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
614 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
615 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
616 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
617 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
618 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
619 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
620 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
621 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
622 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
623 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
624 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
625 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
626 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
627 /* UniMAC RUNT counters */
628 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
629 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
630 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
631 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
632 /* Misc UniMAC counters */
633 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
634 UMAC_RBUF_OVFL_CNT),
635 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
636 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 637 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
638 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
639 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 640};
641
642#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
643
644static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 645 struct ethtool_drvinfo *info)
1c1008c7
FF		 646{
647 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
648 strlcpy(info->version, "v2.0", sizeof(info->version));
649 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 650}
651
652static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
653{
654 switch (string_set) {
655 case ETH_SS_STATS:
656 return BCMGENET_STATS_LEN;
657 default:
658 return -EOPNOTSUPP;
659 }
660}
661
c91b7f66
FF		 662static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
663 u8 *data)
1c1008c7
FF		 664{
665 int i;
666
667 switch (stringset) {
668 case ETH_SS_STATS:
669 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
670 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 671 bcmgenet_gstrings_stats[i].stat_string,
672 ETH_GSTRING_LEN);
1c1008c7
FF		 673 }
674 break;
675 }
676}
677
678static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
679{
680 int i, j = 0;
681
682 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
683 const struct bcmgenet_stats *s;
684 u8 offset = 0;
685 u32 val = 0;
686 char *p;
687
688 s = &bcmgenet_gstrings_stats[i];
689 switch (s->type) {
690 case BCMGENET_STAT_NETDEV:
f62ba9c1 691 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 692 continue;
693 case BCMGENET_STAT_MIB_RX:
694 case BCMGENET_STAT_MIB_TX:
695 case BCMGENET_STAT_RUNT:
696 if (s->type != BCMGENET_STAT_MIB_RX)
697 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 698 val = bcmgenet_umac_readl(priv,
699 UMAC_MIB_START + j + offset);
1c1008c7
FF		 700 break;
701 case BCMGENET_STAT_MISC:
702 val = bcmgenet_umac_readl(priv, s->reg_offset);
703 /* clear if overflowed */
704 if (val == ~0)
705 bcmgenet_umac_writel(priv, 0, s->reg_offset);
706 break;
707 }
708
709 j += s->stat_sizeof;
710 p = (char *)priv + s->stat_offset;
711 *(u32 *)p = val;
712 }
713}
714
715static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 716 struct ethtool_stats *stats,
717 u64 *data)
1c1008c7
FF		 718{
719 struct bcmgenet_priv *priv = netdev_priv(dev);
720 int i;
721
722 if (netif_running(dev))
723 bcmgenet_update_mib_counters(priv);
724
725 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
726 const struct bcmgenet_stats *s;
727 char *p;
728
729 s = &bcmgenet_gstrings_stats[i];
730 if (s->type == BCMGENET_STAT_NETDEV)
731 p = (char *)&dev->stats;
732 else
733 p = (char *)priv;
734 p += s->stat_offset;
735 data[i] = *(u32 *)p;
736 }
737}
738
6ef398ea
FF		 739static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
740{
741 struct bcmgenet_priv *priv = netdev_priv(dev);
742 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
743 u32 reg;
744
745 if (enable && !priv->clk_eee_enabled) {
746 clk_prepare_enable(priv->clk_eee);
747 priv->clk_eee_enabled = true;
748 }
749
750 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
751 if (enable)
752 reg |= EEE_EN;
753 else
754 reg &= ~EEE_EN;
755 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
756
757 /* Enable EEE and switch to a 27Mhz clock automatically */
758 reg = __raw_readl(priv->base + off);
759 if (enable)
760 reg |= TBUF_EEE_EN | TBUF_PM_EN;
761 else
762 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
763 __raw_writel(reg, priv->base + off);
764
765 /* Do the same for thing for RBUF */
766 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
767 if (enable)
768 reg |= RBUF_EEE_EN | RBUF_PM_EN;
769 else
770 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
771 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
772
773 if (!enable && priv->clk_eee_enabled) {
774 clk_disable_unprepare(priv->clk_eee);
775 priv->clk_eee_enabled = false;
776 }
777
778 priv->eee.eee_enabled = enable;
779 priv->eee.eee_active = enable;
780}
781
782static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
783{
784 struct bcmgenet_priv *priv = netdev_priv(dev);
785 struct ethtool_eee *p = &priv->eee;
786
787 if (GENET_IS_V1(priv))
788 return -EOPNOTSUPP;
789
790 e->eee_enabled = p->eee_enabled;
791 e->eee_active = p->eee_active;
792 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
793
794 return phy_ethtool_get_eee(priv->phydev, e);
795}
796
797static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
798{
799 struct bcmgenet_priv *priv = netdev_priv(dev);
800 struct ethtool_eee *p = &priv->eee;
801 int ret = 0;
802
803 if (GENET_IS_V1(priv))
804 return -EOPNOTSUPP;
805
806 p->eee_enabled = e->eee_enabled;
807
808 if (!p->eee_enabled) {
809 bcmgenet_eee_enable_set(dev, false);
810 } else {
811 ret = phy_init_eee(priv->phydev, 0);
812 if (ret) {
813 netif_err(priv, hw, dev, "EEE initialization failed\n");
814 return ret;
815 }
816
817 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
818 bcmgenet_eee_enable_set(dev, true);
819 }
820
821 return phy_ethtool_set_eee(priv->phydev, e);
822}
823
6b0c5406
FF		 824static int bcmgenet_nway_reset(struct net_device *dev)
825{
826 struct bcmgenet_priv *priv = netdev_priv(dev);
827
828 return genphy_restart_aneg(priv->phydev);
829}
830
1c1008c7
FF		 831/* standard ethtool support functions. */
832static struct ethtool_ops bcmgenet_ethtool_ops = {
833 .get_strings = bcmgenet_get_strings,
834 .get_sset_count = bcmgenet_get_sset_count,
835 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
836 .get_settings = bcmgenet_get_settings,
837 .set_settings = bcmgenet_set_settings,
838 .get_drvinfo = bcmgenet_get_drvinfo,
839 .get_link = ethtool_op_get_link,
840 .get_msglevel = bcmgenet_get_msglevel,
841 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 842 .get_wol = bcmgenet_get_wol,
843 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 844 .get_eee = bcmgenet_get_eee,
845 .set_eee = bcmgenet_set_eee,
6b0c5406 846 .nway_reset = bcmgenet_nway_reset,
1c1008c7
FF		 847};
848
849/* Power down the unimac, based on mode. */
ca8cf341 850static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 851 enum bcmgenet_power_mode mode)
852{
ca8cf341 853 int ret = 0;
1c1008c7
FF		 854 u32 reg;
855
856 switch (mode) {
857 case GENET_POWER_CABLE_SENSE:
80d8e96d 858 phy_detach(priv->phydev);
1c1008c7
FF		 859 break;
860
c3ae64ae 861 case GENET_POWER_WOL_MAGIC:
ca8cf341 862 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 863 break;
864
1c1008c7
FF		 865 case GENET_POWER_PASSIVE:
866 /* Power down LED */
1c1008c7
FF		 867 if (priv->hw_params->flags & GENET_HAS_EXT) {
868 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
869 reg |= (EXT_PWR_DOWN_PHY |
870 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
871 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 872
873 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 874 }
875 break;
876 default:
877 break;
878 }
ca8cf341
FF		 879
880 return 0;
1c1008c7
FF		 881}
882
883static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 884 enum bcmgenet_power_mode mode)
1c1008c7
FF		 885{
886 u32 reg;
887
888 if (!(priv->hw_params->flags & GENET_HAS_EXT))
889 return;
890
891 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
892
893 switch (mode) {
894 case GENET_POWER_PASSIVE:
895 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
896 EXT_PWR_DOWN_BIAS);
897 /* fallthrough */
898 case GENET_POWER_CABLE_SENSE:
899 /* enable APD */
900 reg |= EXT_PWR_DN_EN_LD;
901 break;
c3ae64ae
FF		 902 case GENET_POWER_WOL_MAGIC:
903 bcmgenet_wol_power_up_cfg(priv, mode);
904 return;
1c1008c7
FF		 905 default:
906 break;
907 }
908
909 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
cc013fb4
FF		 910
911 if (mode == GENET_POWER_PASSIVE)
912 bcmgenet_mii_reset(priv->dev);
1c1008c7
FF		 913}
914
915/* ioctl handle special commands that are not present in ethtool. */
916static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
917{
918 struct bcmgenet_priv *priv = netdev_priv(dev);
919 int val = 0;
920
921 if (!netif_running(dev))
922 return -EINVAL;
923
924 switch (cmd) {
925 case SIOCGMIIPHY:
926 case SIOCGMIIREG:
927 case SIOCSMIIREG:
928 if (!priv->phydev)
929 val = -ENODEV;
930 else
931 val = phy_mii_ioctl(priv->phydev, rq, cmd);
932 break;
933
934 default:
935 val = -EINVAL;
936 break;
937 }
938
939 return val;
940}
941
942static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
943 struct bcmgenet_tx_ring *ring)
944{
945 struct enet_cb *tx_cb_ptr;
946
947 tx_cb_ptr = ring->cbs;
948 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 949
1c1008c7
FF		 950 /* Advancing local write pointer */
951 if (ring->write_ptr == ring->end_ptr)
952 ring->write_ptr = ring->cb_ptr;
953 else
954 ring->write_ptr++;
955
956 return tx_cb_ptr;
957}
958
959/* Simple helper to free a control block's resources */
960static void bcmgenet_free_cb(struct enet_cb *cb)
961{
962 dev_kfree_skb_any(cb->skb);
963 cb->skb = NULL;
964 dma_unmap_addr_set(cb, dma_addr, 0);
965}
966
4055eaef
PG		 967static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
968{
ee7d8c20 969 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 970 INTRL2_CPU_MASK_SET);
971}
972
973static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
974{
ee7d8c20 975 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 976 INTRL2_CPU_MASK_CLEAR);
977}
978
979static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
980{
981 bcmgenet_intrl2_1_writel(ring->priv,
982 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
983 INTRL2_CPU_MASK_SET);
984}
985
986static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
987{
988 bcmgenet_intrl2_1_writel(ring->priv,
989 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
990 INTRL2_CPU_MASK_CLEAR);
991}
992
9dbac28f 993static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 994{
ee7d8c20 995 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 996 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 997}
998
9dbac28f 999static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1000{
ee7d8c20 1001 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1002 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1003}
1004
9dbac28f 1005static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1006{
9dbac28f 1007 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1008 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1009}
1010
9dbac28f 1011static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1012{
9dbac28f 1013 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1014 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1015}
1016
1017/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1018static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1019 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1020{
1021 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 1022 struct enet_cb *tx_cb_ptr;
b2cde2cc 1023 struct netdev_queue *txq;
4092e6ac 1024 unsigned int pkts_compl = 0;
1c1008c7 1025 unsigned int c_index;
66d06757
PG		 1026 unsigned int txbds_ready;
1027 unsigned int txbds_processed = 0;
1c1008c7 1028
7fc527f9 1029 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 1030 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 1031 c_index &= DMA_C_INDEX_MASK;
1c1008c7 1032
66d06757
PG		 1033 if (likely(c_index >= ring->c_index))
1034 txbds_ready = c_index - ring->c_index;
1c1008c7 1035 else
66d06757 1036 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 1037
1038 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1039 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1040 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1041
1042 /* Reclaim transmitted buffers */
66d06757
PG		 1043 while (txbds_processed < txbds_ready) {
1044 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1045 if (tx_cb_ptr->skb) {
4092e6ac 1046 pkts_compl++;
66d06757 1047 dev->stats.tx_packets++;
1c1008c7
FF		 1048 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1049 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1050 dma_unmap_addr(tx_cb_ptr, dma_addr),
1051 tx_cb_ptr->skb->len,
1052 DMA_TO_DEVICE);
1c1008c7
FF		 1053 bcmgenet_free_cb(tx_cb_ptr);
1054 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1055 dev->stats.tx_bytes +=
1056 dma_unmap_len(tx_cb_ptr, dma_len);
1057 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1058 dma_unmap_addr(tx_cb_ptr, dma_addr),
1059 dma_unmap_len(tx_cb_ptr, dma_len),
1060 DMA_TO_DEVICE);
1c1008c7
FF		 1061 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1062 }
1c1008c7 1063
66d06757
PG		 1064 txbds_processed++;
1065 if (likely(ring->clean_ptr < ring->end_ptr))
1066 ring->clean_ptr++;
1067 else
1068 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1069 }
1070
66d06757
PG		 1071 ring->free_bds += txbds_processed;
1072 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1073
4092e6ac 1074 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
66d06757 1075 txq = netdev_get_tx_queue(dev, ring->queue);
4092e6ac
JS		 1076 if (netif_tx_queue_stopped(txq))
1077 netif_tx_wake_queue(txq);
1078 }
1c1008c7 1079
4092e6ac 1080 return pkts_compl;
1c1008c7
FF		 1081}
1082
4092e6ac 1083static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1084 struct bcmgenet_tx_ring *ring)
1c1008c7 1085{
4092e6ac 1086 unsigned int released;
1c1008c7
FF		 1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1090 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1091 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1092
1093 return released;
1094}
1095
1096static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1097{
1098 struct bcmgenet_tx_ring *ring =
1099 container_of(napi, struct bcmgenet_tx_ring, napi);
1100 unsigned int work_done = 0;
1101
1102 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1103
1104 if (work_done == 0) {
1105 napi_complete(napi);
9dbac28f 1106 ring->int_enable(ring);
4092e6ac
JS		 1107
1108 return 0;
1109 }
1110
1111 return budget;
1c1008c7
FF		 1112}
1113
1114static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1115{
1116 struct bcmgenet_priv *priv = netdev_priv(dev);
1117 int i;
1118
1119 if (netif_is_multiqueue(dev)) {
1120 for (i = 0; i < priv->hw_params->tx_queues; i++)
1121 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1122 }
1123
1124 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1125}
1126
1127/* Transmits a single SKB (either head of a fragment or a single SKB)
1128 * caller must hold priv->lock
1129 */
1130static int bcmgenet_xmit_single(struct net_device *dev,
1131 struct sk_buff *skb,
1132 u16 dma_desc_flags,
1133 struct bcmgenet_tx_ring *ring)
1134{
1135 struct bcmgenet_priv *priv = netdev_priv(dev);
1136 struct device *kdev = &priv->pdev->dev;
1137 struct enet_cb *tx_cb_ptr;
1138 unsigned int skb_len;
1139 dma_addr_t mapping;
1140 u32 length_status;
1141 int ret;
1142
1143 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1144
1145 if (unlikely(!tx_cb_ptr))
1146 BUG();
1147
1148 tx_cb_ptr->skb = skb;
1149
1150 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1151
1152 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1153 ret = dma_mapping_error(kdev, mapping);
1154 if (ret) {
44c8bc3c 1155 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1156 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1157 dev_kfree_skb(skb);
1158 return ret;
1159 }
1160
1161 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1162 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1163 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1164 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1165 DMA_TX_APPEND_CRC;
1166
1167 if (skb->ip_summed == CHECKSUM_PARTIAL)
1168 length_status |= DMA_TX_DO_CSUM;
1169
1170 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1171
1c1008c7
FF		 1172 return 0;
1173}
1174
7fc527f9 1175/* Transmit a SKB fragment */
1c1008c7 1176static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1177 skb_frag_t *frag,
1178 u16 dma_desc_flags,
1179 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1180{
1181 struct bcmgenet_priv *priv = netdev_priv(dev);
1182 struct device *kdev = &priv->pdev->dev;
1183 struct enet_cb *tx_cb_ptr;
1184 dma_addr_t mapping;
1185 int ret;
1186
1187 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1188
1189 if (unlikely(!tx_cb_ptr))
1190 BUG();
1191 tx_cb_ptr->skb = NULL;
1192
1193 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1194 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1195 ret = dma_mapping_error(kdev, mapping);
1196 if (ret) {
44c8bc3c 1197 priv->mib.tx_dma_failed++;
1c1008c7 1198 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1199 __func__);
1c1008c7
FF		 1200 return ret;
1201 }
1202
1203 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1204 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1205
1206 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1207 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1208 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7 1209
1c1008c7
FF		 1210 return 0;
1211}
1212
1213/* Reallocate the SKB to put enough headroom in front of it and insert
1214 * the transmit checksum offsets in the descriptors
1215 */
bc23333b
PG		 1216static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1217 struct sk_buff *skb)
1c1008c7
FF		 1218{
1219 struct status_64 *status = NULL;
1220 struct sk_buff *new_skb;
1221 u16 offset;
1222 u8 ip_proto;
1223 u16 ip_ver;
1224 u32 tx_csum_info;
1225
1226 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1227 /* If 64 byte status block enabled, must make sure skb has
1228 * enough headroom for us to insert 64B status block.
1229 */
1230 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1231 dev_kfree_skb(skb);
1232 if (!new_skb) {
1233 dev->stats.tx_errors++;
1234 dev->stats.tx_dropped++;
bc23333b 1235 return NULL;
1c1008c7
FF		 1236 }
1237 skb = new_skb;
1238 }
1239
1240 skb_push(skb, sizeof(*status));
1241 status = (struct status_64 *)skb->data;
1242
1243 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1244 ip_ver = htons(skb->protocol);
1245 switch (ip_ver) {
1246 case ETH_P_IP:
1247 ip_proto = ip_hdr(skb)->protocol;
1248 break;
1249 case ETH_P_IPV6:
1250 ip_proto = ipv6_hdr(skb)->nexthdr;
1251 break;
1252 default:
bc23333b 1253 return skb;
1c1008c7
FF		 1254 }
1255
1256 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1257 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1258 (offset + skb->csum_offset);
1259
1260 /* Set the length valid bit for TCP and UDP and just set
1261 * the special UDP flag for IPv4, else just set to 0.
1262 */
1263 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1264 tx_csum_info |= STATUS_TX_CSUM_LV;
1265 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1266 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1267 } else {
1c1008c7 1268 tx_csum_info = 0;
8900ea57 1269 }
1c1008c7
FF		 1270
1271 status->tx_csum_info = tx_csum_info;
1272 }
1273
bc23333b 1274 return skb;
1c1008c7
FF		 1275}
1276
1277static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1278{
1279 struct bcmgenet_priv *priv = netdev_priv(dev);
1280 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1281 struct netdev_queue *txq;
1c1008c7
FF		 1282 unsigned long flags = 0;
1283 int nr_frags, index;
1284 u16 dma_desc_flags;
1285 int ret;
1286 int i;
1287
1288 index = skb_get_queue_mapping(skb);
1289 /* Mapping strategy:
1290 * queue_mapping = 0, unclassified, packet xmited through ring16
1291 * queue_mapping = 1, goes to ring 0. (highest priority queue
1292 * queue_mapping = 2, goes to ring 1.
1293 * queue_mapping = 3, goes to ring 2.
1294 * queue_mapping = 4, goes to ring 3.
1295 */
1296 if (index == 0)
1297 index = DESC_INDEX;
1298 else
1299 index -= 1;
1300
1c1008c7
FF		 1301 nr_frags = skb_shinfo(skb)->nr_frags;
1302 ring = &priv->tx_rings[index];
b2cde2cc 1303 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1304
1305 spin_lock_irqsave(&ring->lock, flags);
1306 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1307 netif_tx_stop_queue(txq);
1c1008c7 1308 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1309 __func__, index, ring->queue);
1c1008c7
FF		 1310 ret = NETDEV_TX_BUSY;
1311 goto out;
1312 }
1313
474ea9ca
FF		 1314 if (skb_padto(skb, ETH_ZLEN)) {
1315 ret = NETDEV_TX_OK;
1316 goto out;
1317 }
1318
1c1008c7
FF		 1319 /* set the SKB transmit checksum */
1320 if (priv->desc_64b_en) {
bc23333b
PG		 1321 skb = bcmgenet_put_tx_csum(dev, skb);
1322 if (!skb) {
1c1008c7
FF		 1323 ret = NETDEV_TX_OK;
1324 goto out;
1325 }
1326 }
1327
1328 dma_desc_flags = DMA_SOP;
1329 if (nr_frags == 0)
1330 dma_desc_flags |= DMA_EOP;
1331
1332 /* Transmit single SKB or head of fragment list */
1333 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1334 if (ret) {
1335 ret = NETDEV_TX_OK;
1336 goto out;
1337 }
1338
1339 /* xmit fragment */
1340 for (i = 0; i < nr_frags; i++) {
1341 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1342 &skb_shinfo(skb)->frags[i],
1343 (i == nr_frags - 1) ? DMA_EOP : 0,
1344 ring);
1c1008c7
FF		 1345 if (ret) {
1346 ret = NETDEV_TX_OK;
1347 goto out;
1348 }
1349 }
1350
d03825fb
FF		 1351 skb_tx_timestamp(skb);
1352
ae67bf01
FF		 1353 /* Decrement total BD count and advance our write pointer */
1354 ring->free_bds -= nr_frags + 1;
1355 ring->prod_index += nr_frags + 1;
1356 ring->prod_index &= DMA_P_INDEX_MASK;
1357
4092e6ac 1358 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1359 netif_tx_stop_queue(txq);
1c1008c7 1360
ddd0ca5d
FF		 1361 if (!skb->xmit_more || netif_xmit_stopped(txq))
1362 /* Packets are ready, update producer index */
1363 bcmgenet_tdma_ring_writel(priv, ring->index,
1364 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1365out:
1366 spin_unlock_irqrestore(&ring->lock, flags);
1367
1368 return ret;
1369}
1370
d6707bec
PG		 1371static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1372 struct enet_cb *cb)
1c1008c7
FF		 1373{
1374 struct device *kdev = &priv->pdev->dev;
1375 struct sk_buff *skb;
d6707bec 1376 struct sk_buff *rx_skb;
1c1008c7 1377 dma_addr_t mapping;
1c1008c7 1378
d6707bec 1379 /* Allocate a new Rx skb */
c91b7f66 1380 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
d6707bec
PG		 1381 if (!skb) {
1382 priv->mib.alloc_rx_buff_failed++;
1383 netif_err(priv, rx_err, priv->dev,
1384 "%s: Rx skb allocation failed\n", __func__);
1385 return NULL;
1386 }
1c1008c7 1387
d6707bec
PG		 1388 /* DMA-map the new Rx skb */
1389 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1390 DMA_FROM_DEVICE);
1391 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 1392 priv->mib.rx_dma_failed++;
d6707bec 1393 dev_kfree_skb_any(skb);
1c1008c7 1394 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 1395 "%s: Rx skb DMA mapping failed\n", __func__);
1396 return NULL;
1c1008c7
FF		 1397 }
1398
d6707bec
PG		 1399 /* Grab the current Rx skb from the ring and DMA-unmap it */
1400 rx_skb = cb->skb;
1401 if (likely(rx_skb))
1402 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1403 priv->rx_buf_len, DMA_FROM_DEVICE);
1404
1405 /* Put the new Rx skb on the ring */
1406 cb->skb = skb;
1c1008c7 1407 dma_unmap_addr_set(cb, dma_addr, mapping);
8ac467e8 1408 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 1409
d6707bec
PG		 1410 /* Return the current Rx skb to caller */
1411 return rx_skb;
1c1008c7
FF		 1412}
1413
1414/* bcmgenet_desc_rx - descriptor based rx process.
1415 * this could be called from bottom half, or from NAPI polling method.
1416 */
4055eaef 1417static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 1418 unsigned int budget)
1419{
4055eaef 1420 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 1421 struct net_device *dev = priv->dev;
1422 struct enet_cb *cb;
1423 struct sk_buff *skb;
1424 u32 dma_length_status;
1425 unsigned long dma_flag;
d6707bec 1426 int len;
1c1008c7
FF		 1427 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1428 unsigned int p_index;
d26ea6cc 1429 unsigned int discards;
1c1008c7
FF		 1430 unsigned int chksum_ok = 0;
1431
4055eaef 1432 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 1433
1434 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1435 DMA_P_INDEX_DISCARD_CNT_MASK;
1436 if (discards > ring->old_discards) {
1437 discards = discards - ring->old_discards;
1438 dev->stats.rx_missed_errors += discards;
1439 dev->stats.rx_errors += discards;
1440 ring->old_discards += discards;
1441
1442 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1443 if (ring->old_discards >= 0xC000) {
1444 ring->old_discards = 0;
4055eaef 1445 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 1446 RDMA_PROD_INDEX);
1447 }
1448 }
1449
1c1008c7
FF		 1450 p_index &= DMA_P_INDEX_MASK;
1451
8ac467e8
PG		 1452 if (likely(p_index >= ring->c_index))
1453 rxpkttoprocess = p_index - ring->c_index;
1c1008c7 1454 else
8ac467e8
PG		 1455 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1456 p_index;
1c1008c7
FF		 1457
1458 netif_dbg(priv, rx_status, dev,
c91b7f66 1459 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1460
1461 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1462 (rxpktprocessed < budget)) {
8ac467e8 1463 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 1464 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 1465
b629be5c
FF		 1466 if (unlikely(!skb)) {
1467 dev->stats.rx_dropped++;
1468 dev->stats.rx_errors++;
d6707bec 1469 goto next;
b629be5c
FF		 1470 }
1471
1c1008c7 1472 if (!priv->desc_64b_en) {
c91b7f66 1473 dma_length_status =
8ac467e8 1474 dmadesc_get_length_status(priv, cb->bd_addr);
1c1008c7
FF		 1475 } else {
1476 struct status_64 *status;
164d4f20 1477
1c1008c7
FF		 1478 status = (struct status_64 *)skb->data;
1479 dma_length_status = status->length_status;
1480 }
1481
1482 /* DMA flags and length are still valid no matter how
1483 * we got the Receive Status Vector (64B RSB or register)
1484 */
1485 dma_flag = dma_length_status & 0xffff;
1486 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1487
1488 netif_dbg(priv, rx_status, dev,
c91b7f66 1489 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1490 __func__, p_index, ring->c_index,
1491 ring->read_ptr, dma_length_status);
1c1008c7 1492
1c1008c7
FF		 1493 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1494 netif_err(priv, rx_status, dev,
c91b7f66 1495 "dropping fragmented packet!\n");
1c1008c7
FF		 1496 dev->stats.rx_dropped++;
1497 dev->stats.rx_errors++;
d6707bec
PG		 1498 dev_kfree_skb_any(skb);
1499 goto next;
1c1008c7 1500 }
d6707bec 1501
1c1008c7
FF		 1502 /* report errors */
1503 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1504 DMA_RX_OV |
1505 DMA_RX_NO |
1506 DMA_RX_LG |
1507 DMA_RX_RXER))) {
1508 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1509 (unsigned int)dma_flag);
1c1008c7
FF		 1510 if (dma_flag & DMA_RX_CRC_ERROR)
1511 dev->stats.rx_crc_errors++;
1512 if (dma_flag & DMA_RX_OV)
1513 dev->stats.rx_over_errors++;
1514 if (dma_flag & DMA_RX_NO)
1515 dev->stats.rx_frame_errors++;
1516 if (dma_flag & DMA_RX_LG)
1517 dev->stats.rx_length_errors++;
1518 dev->stats.rx_dropped++;
1519 dev->stats.rx_errors++;
d6707bec
PG		 1520 dev_kfree_skb_any(skb);
1521 goto next;
1c1008c7
FF		 1522 } /* error packet */
1523
1524 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1525 priv->desc_rxchk_en;
1c1008c7
FF		 1526
1527 skb_put(skb, len);
1528 if (priv->desc_64b_en) {
1529 skb_pull(skb, 64);
1530 len -= 64;
1531 }
1532
1533 if (likely(chksum_ok))
1534 skb->ip_summed = CHECKSUM_UNNECESSARY;
1535
1536 /* remove hardware 2bytes added for IP alignment */
1537 skb_pull(skb, 2);
1538 len -= 2;
1539
1540 if (priv->crc_fwd_en) {
1541 skb_trim(skb, len - ETH_FCS_LEN);
1542 len -= ETH_FCS_LEN;
1543 }
1544
1545 /*Finish setting up the received SKB and send it to the kernel*/
1546 skb->protocol = eth_type_trans(skb, priv->dev);
1547 dev->stats.rx_packets++;
1548 dev->stats.rx_bytes += len;
1549 if (dma_flag & DMA_RX_MULT)
1550 dev->stats.multicast++;
1551
1552 /* Notify kernel */
4055eaef 1553 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 1554 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1555
d6707bec 1556next:
cf377d88 1557 rxpktprocessed++;
8ac467e8
PG		 1558 if (likely(ring->read_ptr < ring->end_ptr))
1559 ring->read_ptr++;
1560 else
1561 ring->read_ptr = ring->cb_ptr;
1562
1563 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 1564 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1565 }
1566
1567 return rxpktprocessed;
1568}
1569
3ab11339
PG		 1570/* Rx NAPI polling method */
1571static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1572{
4055eaef
PG		 1573 struct bcmgenet_rx_ring *ring = container_of(napi,
1574 struct bcmgenet_rx_ring, napi);
3ab11339
PG		 1575 unsigned int work_done;
1576
4055eaef 1577 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 1578
1579 if (work_done < budget) {
1580 napi_complete(napi);
4055eaef 1581 ring->int_enable(ring);
3ab11339
PG		 1582 }
1583
1584 return work_done;
1585}
1586
1c1008c7 1587/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1588static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1589 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1590{
1591 struct enet_cb *cb;
d6707bec 1592 struct sk_buff *skb;
1c1008c7
FF		 1593 int i;
1594
8ac467e8 1595 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1596
1597 /* loop here for each buffer needing assign */
8ac467e8
PG		 1598 for (i = 0; i < ring->size; i++) {
1599 cb = ring->cbs + i;
d6707bec
PG		 1600 skb = bcmgenet_rx_refill(priv, cb);
1601 if (skb)
1602 dev_kfree_skb_any(skb);
1603 if (!cb->skb)
1604 return -ENOMEM;
1c1008c7
FF		 1605 }
1606
d6707bec 1607 return 0;
1c1008c7
FF		 1608}
1609
1610static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1611{
1612 struct enet_cb *cb;
1613 int i;
1614
1615 for (i = 0; i < priv->num_rx_bds; i++) {
1616 cb = &priv->rx_cbs[i];
1617
1618 if (dma_unmap_addr(cb, dma_addr)) {
1619 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1620 dma_unmap_addr(cb, dma_addr),
1621 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1622 dma_unmap_addr_set(cb, dma_addr, 0);
1623 }
1624
1625 if (cb->skb)
1626 bcmgenet_free_cb(cb);
1627 }
1628}
1629
c91b7f66 1630static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1631{
1632 u32 reg;
1633
1634 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1635 if (enable)
1636 reg |= mask;
1637 else
1638 reg &= ~mask;
1639 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1640
1641 /* UniMAC stops on a packet boundary, wait for a full-size packet
1642 * to be processed
1643 */
1644 if (enable == 0)
1645 usleep_range(1000, 2000);
1646}
1647
1c1008c7
FF		 1648static int reset_umac(struct bcmgenet_priv *priv)
1649{
1650 struct device *kdev = &priv->pdev->dev;
1651 unsigned int timeout = 0;
1652 u32 reg;
1653
1654 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1655 bcmgenet_rbuf_ctrl_set(priv, 0);
1656 udelay(10);
1657
1658 /* disable MAC while updating its registers */
1659 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1660
1661 /* issue soft reset, wait for it to complete */
1662 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1663 while (timeout++ < 1000) {
1664 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1665 if (!(reg & CMD_SW_RESET))
1666 return 0;
1667
1668 udelay(1);
1669 }
1670
1671 if (timeout == 1000) {
1672 dev_err(kdev,
7fc527f9 1673 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1674 return -ETIMEDOUT;
1675 }
1676
1677 return 0;
1678}
1679
909ff5ef
FF		 1680static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1681{
1682 /* Mask all interrupts.*/
1683 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1684 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1685 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1686 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1687 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1688 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1689}
1690
1c1008c7
FF		 1691static int init_umac(struct bcmgenet_priv *priv)
1692{
1693 struct device *kdev = &priv->pdev->dev;
1694 int ret;
b2e97eca
PG		 1695 u32 reg;
1696 u32 int0_enable = 0;
1697 u32 int1_enable = 0;
1698 int i;
1c1008c7
FF		 1699
1700 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1701
1702 ret = reset_umac(priv);
1703 if (ret)
1704 return ret;
1705
1706 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1707 /* clear tx/rx counter */
1708 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1709 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1710 UMAC_MIB_CTRL);
1c1008c7
FF		 1711 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1712
1713 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1714
1715 /* init rx registers, enable ip header optimization */
1716 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1717 reg |= RBUF_ALIGN_2B;
1718 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1719
1720 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1721 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1722
909ff5ef 1723 bcmgenet_intr_disable(priv);
1c1008c7 1724
b2e97eca 1725 /* Enable Rx default queue 16 interrupts */
ee7d8c20 1726 int0_enable |= UMAC_IRQ_RXDMA_DONE;
1c1008c7 1727
b2e97eca 1728 /* Enable Tx default queue 16 interrupts */
ee7d8c20 1729 int0_enable |= UMAC_IRQ_TXDMA_DONE;
1c1008c7 1730
7fc527f9 1731 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1732 if (phy_is_internal(priv->phydev)) {
e122966d 1733 int0_enable |= UMAC_IRQ_LINK_EVENT;
8900ea57 1734 } else if (priv->ext_phy) {
e122966d 1735 int0_enable |= UMAC_IRQ_LINK_EVENT;
8900ea57 1736 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1737 reg = bcmgenet_bp_mc_get(priv);
1738 reg |= BIT(priv->hw_params->bp_in_en_shift);
1739
1740 /* bp_mask: back pressure mask */
1741 if (netif_is_multiqueue(priv->dev))
1742 reg |= priv->hw_params->bp_in_mask;
1743 else
1744 reg &= ~priv->hw_params->bp_in_mask;
1745 bcmgenet_bp_mc_set(priv, reg);
1746 }
1747
1748 /* Enable MDIO interrupts on GENET v3+ */
1749 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 1750 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 1751
4055eaef
PG		 1752 /* Enable Rx priority queue interrupts */
1753 for (i = 0; i < priv->hw_params->rx_queues; ++i)
1754 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1755
b2e97eca
PG		 1756 /* Enable Tx priority queue interrupts */
1757 for (i = 0; i < priv->hw_params->tx_queues; ++i)
1758 int1_enable |= (1 << i);
1c1008c7 1759
b2e97eca
PG		 1760 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1761 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 1762
1c1008c7
FF		 1763 /* Enable rx/tx engine.*/
1764 dev_dbg(kdev, "done init umac\n");
1765
1766 return 0;
1767}
1768
4f8b2d7d 1769/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1770static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1771 unsigned int index, unsigned int size,
4f8b2d7d 1772 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1773{
1774 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1775 u32 words_per_bd = WORDS_PER_BD(priv);
1776 u32 flow_period_val = 0;
1c1008c7
FF		 1777
1778 spin_lock_init(&ring->lock);
4092e6ac 1779 ring->priv = priv;
1c1008c7
FF		 1780 ring->index = index;
1781 if (index == DESC_INDEX) {
1782 ring->queue = 0;
1783 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1784 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1785 } else {
1786 ring->queue = index + 1;
1787 ring->int_enable = bcmgenet_tx_ring_int_enable;
1788 ring->int_disable = bcmgenet_tx_ring_int_disable;
1789 }
4f8b2d7d 1790 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1791 ring->size = size;
66d06757 1792 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1793 ring->c_index = 0;
1794 ring->free_bds = size;
4f8b2d7d
PG		 1795 ring->write_ptr = start_ptr;
1796 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1797 ring->end_ptr = end_ptr - 1;
1798 ring->prod_index = 0;
1799
1800 /* Set flow period for ring != 16 */
1801 if (index != DESC_INDEX)
1802 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1803
1804 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1805 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1806 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1807 /* Disable rate control for now */
1808 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1809 TDMA_FLOW_PERIOD);
1c1008c7 1810 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1811 ((size << DMA_RING_SIZE_SHIFT) |
1812 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1813
1c1008c7 1814 /* Set start and end address, read and write pointers */
4f8b2d7d 1815 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1816 DMA_START_ADDR);
4f8b2d7d 1817 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1818 TDMA_READ_PTR);
4f8b2d7d 1819 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1820 TDMA_WRITE_PTR);
1c1008c7 1821 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1822 DMA_END_ADDR);
1c1008c7
FF		 1823}
1824
1825/* Initialize a RDMA ring */
1826static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 1827 unsigned int index, unsigned int size,
1828 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 1829{
8ac467e8 1830 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 1831 u32 words_per_bd = WORDS_PER_BD(priv);
1832 int ret;
1833
4055eaef 1834 ring->priv = priv;
8ac467e8 1835 ring->index = index;
4055eaef
PG		 1836 if (index == DESC_INDEX) {
1837 ring->int_enable = bcmgenet_rx_ring16_int_enable;
1838 ring->int_disable = bcmgenet_rx_ring16_int_disable;
1839 } else {
1840 ring->int_enable = bcmgenet_rx_ring_int_enable;
1841 ring->int_disable = bcmgenet_rx_ring_int_disable;
1842 }
8ac467e8
PG		 1843 ring->cbs = priv->rx_cbs + start_ptr;
1844 ring->size = size;
1845 ring->c_index = 0;
1846 ring->read_ptr = start_ptr;
1847 ring->cb_ptr = start_ptr;
1848 ring->end_ptr = end_ptr - 1;
1c1008c7 1849
8ac467e8
PG		 1850 ret = bcmgenet_alloc_rx_buffers(priv, ring);
1851 if (ret)
1c1008c7 1852 return ret;
1c1008c7 1853
1c1008c7
FF		 1854 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1855 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 1856 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 1857 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1858 ((size << DMA_RING_SIZE_SHIFT) |
1859 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1860 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1861 (DMA_FC_THRESH_LO <<
1862 DMA_XOFF_THRESHOLD_SHIFT) |
1863 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 1864
1865 /* Set start and end address, read and write pointers */
8ac467e8
PG		 1866 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1867 DMA_START_ADDR);
1868 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1869 RDMA_READ_PTR);
1870 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1871 RDMA_WRITE_PTR);
1872 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 1873 DMA_END_ADDR);
1c1008c7
FF		 1874
1875 return ret;
1876}
1877
e2aadb4a
PG		 1878static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
1879{
1880 unsigned int i;
1881 struct bcmgenet_tx_ring *ring;
1882
1883 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1884 ring = &priv->tx_rings[i];
1885 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1886 }
1887
1888 ring = &priv->tx_rings[DESC_INDEX];
1889 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1890}
1891
1892static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
1893{
1894 unsigned int i;
1895 struct bcmgenet_tx_ring *ring;
1896
1897 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1898 ring = &priv->tx_rings[i];
1899 napi_enable(&ring->napi);
1900 }
1901
1902 ring = &priv->tx_rings[DESC_INDEX];
1903 napi_enable(&ring->napi);
1904}
1905
1906static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
1907{
1908 unsigned int i;
1909 struct bcmgenet_tx_ring *ring;
1910
1911 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1912 ring = &priv->tx_rings[i];
1913 napi_disable(&ring->napi);
1914 }
1915
1916 ring = &priv->tx_rings[DESC_INDEX];
1917 napi_disable(&ring->napi);
1918}
1919
1920static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
1921{
1922 unsigned int i;
1923 struct bcmgenet_tx_ring *ring;
1924
1925 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1926 ring = &priv->tx_rings[i];
1927 netif_napi_del(&ring->napi);
1928 }
1929
1930 ring = &priv->tx_rings[DESC_INDEX];
1931 netif_napi_del(&ring->napi);
1932}
1933
16c6d667 1934/* Initialize Tx queues
1c1008c7 1935 *
16c6d667 1936 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 1937 * with queue 0 being the highest priority queue.
1938 *
16c6d667 1939 * Queue 16 is the default Tx queue with
51a966a7 1940 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 1941 *
16c6d667
PG		 1942 * The transmit control block pool is then partitioned as follows:
1943 * - Tx queue 0 uses tx_cbs[0..31]
1944 * - Tx queue 1 uses tx_cbs[32..63]
1945 * - Tx queue 2 uses tx_cbs[64..95]
1946 * - Tx queue 3 uses tx_cbs[96..127]
1947 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 1948 */
16c6d667 1949static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 1950{
1951 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 1952 u32 i, dma_enable;
1953 u32 dma_ctrl, ring_cfg;
37742166 1954 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 1955
1c1008c7
FF		 1956 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1957 dma_enable = dma_ctrl & DMA_EN;
1958 dma_ctrl &= ~DMA_EN;
1959 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1960
16c6d667
PG		 1961 dma_ctrl = 0;
1962 ring_cfg = 0;
1963
1c1008c7
FF		 1964 /* Enable strict priority arbiter mode */
1965 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1966
16c6d667 1967 /* Initialize Tx priority queues */
1c1008c7 1968 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 1969 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
1970 i * priv->hw_params->tx_bds_per_q,
1971 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 1972 ring_cfg |= (1 << i);
1973 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1974 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1975 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 1976 }
1977
16c6d667 1978 /* Initialize Tx default queue 16 */
51a966a7 1979 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 1980 priv->hw_params->tx_queues *
51a966a7 1981 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 1982 TOTAL_DESC);
1983 ring_cfg |= (1 << DESC_INDEX);
1984 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1985 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1986 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1987 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 1988
1989 /* Set Tx queue priorities */
37742166
PG		 1990 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1991 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1992 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1993
e2aadb4a
PG		 1994 /* Initialize Tx NAPI */
1995 bcmgenet_init_tx_napi(priv);
1996
16c6d667
PG		 1997 /* Enable Tx queues */
1998 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 1999
16c6d667 2000 /* Enable Tx DMA */
1c1008c7 2001 if (dma_enable)
16c6d667
PG		 2002 dma_ctrl |= DMA_EN;
2003 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2004}
2005
3ab11339
PG		 2006static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2007{
4055eaef
PG		 2008 unsigned int i;
2009 struct bcmgenet_rx_ring *ring;
2010
2011 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2012 ring = &priv->rx_rings[i];
2013 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2014 }
2015
2016 ring = &priv->rx_rings[DESC_INDEX];
2017 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
3ab11339
PG		 2018}
2019
2020static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2021{
4055eaef
PG		 2022 unsigned int i;
2023 struct bcmgenet_rx_ring *ring;
2024
2025 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2026 ring = &priv->rx_rings[i];
2027 napi_enable(&ring->napi);
2028 }
2029
2030 ring = &priv->rx_rings[DESC_INDEX];
2031 napi_enable(&ring->napi);
3ab11339
PG		 2032}
2033
2034static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2035{
4055eaef
PG		 2036 unsigned int i;
2037 struct bcmgenet_rx_ring *ring;
2038
2039 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2040 ring = &priv->rx_rings[i];
2041 napi_disable(&ring->napi);
2042 }
2043
2044 ring = &priv->rx_rings[DESC_INDEX];
2045 napi_disable(&ring->napi);
3ab11339
PG		 2046}
2047
2048static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2049{
4055eaef
PG		 2050 unsigned int i;
2051 struct bcmgenet_rx_ring *ring;
2052
2053 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2054 ring = &priv->rx_rings[i];
2055 netif_napi_del(&ring->napi);
2056 }
2057
2058 ring = &priv->rx_rings[DESC_INDEX];
2059 netif_napi_del(&ring->napi);
3ab11339
PG		 2060}
2061
8ac467e8
PG		 2062/* Initialize Rx queues
2063 *
2064 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2065 * used to direct traffic to these queues.
2066 *
2067 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2068 */
2069static int bcmgenet_init_rx_queues(struct net_device *dev)
2070{
2071 struct bcmgenet_priv *priv = netdev_priv(dev);
2072 u32 i;
2073 u32 dma_enable;
2074 u32 dma_ctrl;
2075 u32 ring_cfg;
2076 int ret;
2077
2078 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2079 dma_enable = dma_ctrl & DMA_EN;
2080 dma_ctrl &= ~DMA_EN;
2081 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2082
2083 dma_ctrl = 0;
2084 ring_cfg = 0;
2085
2086 /* Initialize Rx priority queues */
2087 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2088 ret = bcmgenet_init_rx_ring(priv, i,
2089 priv->hw_params->rx_bds_per_q,
2090 i * priv->hw_params->rx_bds_per_q,
2091 (i + 1) *
2092 priv->hw_params->rx_bds_per_q);
2093 if (ret)
2094 return ret;
2095
2096 ring_cfg |= (1 << i);
2097 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2098 }
2099
2100 /* Initialize Rx default queue 16 */
2101 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2102 priv->hw_params->rx_queues *
2103 priv->hw_params->rx_bds_per_q,
2104 TOTAL_DESC);
2105 if (ret)
2106 return ret;
2107
2108 ring_cfg |= (1 << DESC_INDEX);
2109 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2110
3ab11339
PG		 2111 /* Initialize Rx NAPI */
2112 bcmgenet_init_rx_napi(priv);
2113
8ac467e8
PG		 2114 /* Enable rings */
2115 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2116
2117 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2118 if (dma_enable)
2119 dma_ctrl |= DMA_EN;
2120 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2121
2122 return 0;
2123}
2124
4a0c081e
FF		 2125static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2126{
2127 int ret = 0;
2128 int timeout = 0;
2129 u32 reg;
2130
2131 /* Disable TDMA to stop add more frames in TX DMA */
2132 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2133 reg &= ~DMA_EN;
2134 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2135
2136 /* Check TDMA status register to confirm TDMA is disabled */
2137 while (timeout++ < DMA_TIMEOUT_VAL) {
2138 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2139 if (reg & DMA_DISABLED)
2140 break;
2141
2142 udelay(1);
2143 }
2144
2145 if (timeout == DMA_TIMEOUT_VAL) {
2146 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2147 ret = -ETIMEDOUT;
2148 }
2149
2150 /* Wait 10ms for packet drain in both tx and rx dma */
2151 usleep_range(10000, 20000);
2152
2153 /* Disable RDMA */
2154 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2155 reg &= ~DMA_EN;
2156 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2157
2158 timeout = 0;
2159 /* Check RDMA status register to confirm RDMA is disabled */
2160 while (timeout++ < DMA_TIMEOUT_VAL) {
2161 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2162 if (reg & DMA_DISABLED)
2163 break;
2164
2165 udelay(1);
2166 }
2167
2168 if (timeout == DMA_TIMEOUT_VAL) {
2169 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2170 ret = -ETIMEDOUT;
2171 }
2172
2173 return ret;
2174}
2175
9abab96d 2176static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 2177{
2178 int i;
2179
9abab96d
PG		 2180 bcmgenet_fini_rx_napi(priv);
2181 bcmgenet_fini_tx_napi(priv);
2182
1c1008c7 2183 /* disable DMA */
4a0c081e 2184 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2185
2186 for (i = 0; i < priv->num_tx_bds; i++) {
2187 if (priv->tx_cbs[i].skb != NULL) {
2188 dev_kfree_skb(priv->tx_cbs[i].skb);
2189 priv->tx_cbs[i].skb = NULL;
2190 }
2191 }
2192
2193 bcmgenet_free_rx_buffers(priv);
2194 kfree(priv->rx_cbs);
2195 kfree(priv->tx_cbs);
2196}
2197
2198/* init_edma: Initialize DMA control register */
2199static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2200{
2201 int ret;
014012a4
PG		 2202 unsigned int i;
2203 struct enet_cb *cb;
1c1008c7 2204
6f5a272c 2205 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2206
6f5a272c
PG		 2207 /* Initialize common Rx ring structures */
2208 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2209 priv->num_rx_bds = TOTAL_DESC;
2210 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2211 GFP_KERNEL);
2212 if (!priv->rx_cbs)
2213 return -ENOMEM;
2214
2215 for (i = 0; i < priv->num_rx_bds; i++) {
2216 cb = priv->rx_cbs + i;
2217 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2218 }
2219
7fc527f9 2220 /* Initialize common TX ring structures */
1c1008c7
FF		 2221 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2222 priv->num_tx_bds = TOTAL_DESC;
c489be08 2223 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2224 GFP_KERNEL);
1c1008c7 2225 if (!priv->tx_cbs) {
ebbd96fb 2226 kfree(priv->rx_cbs);
1c1008c7
FF		 2227 return -ENOMEM;
2228 }
2229
014012a4
PG		 2230 for (i = 0; i < priv->num_tx_bds; i++) {
2231 cb = priv->tx_cbs + i;
2232 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2233 }
2234
ebbd96fb
PG		 2235 /* Init rDma */
2236 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2237
2238 /* Initialize Rx queues */
2239 ret = bcmgenet_init_rx_queues(priv->dev);
2240 if (ret) {
2241 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2242 bcmgenet_free_rx_buffers(priv);
2243 kfree(priv->rx_cbs);
2244 kfree(priv->tx_cbs);
2245 return ret;
2246 }
2247
2248 /* Init tDma */
2249 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2250
16c6d667
PG		 2251 /* Initialize Tx queues */
2252 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2253
2254 return 0;
2255}
2256
1c1008c7
FF		 2257/* Interrupt bottom half */
2258static void bcmgenet_irq_task(struct work_struct *work)
2259{
2260 struct bcmgenet_priv *priv = container_of(
2261 work, struct bcmgenet_priv, bcmgenet_irq_work);
2262
2263 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2264
8fdb0e0f
FF		 2265 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2266 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2267 netif_dbg(priv, wol, priv->dev,
2268 "magic packet detected, waking up\n");
2269 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2270 }
2271
1c1008c7
FF		 2272 /* Link UP/DOWN event */
2273 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
e122966d 2274 (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) {
80d8e96d 2275 phy_mac_interrupt(priv->phydev,
c91b7f66 2276 priv->irq0_stat & UMAC_IRQ_LINK_UP);
e122966d 2277 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
1c1008c7
FF		 2278 }
2279}
2280
4055eaef 2281/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 2282static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2283{
2284 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2285 struct bcmgenet_rx_ring *rx_ring;
2286 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2287 unsigned int index;
2288
2289 /* Save irq status for bottom-half processing. */
2290 priv->irq1_stat =
2291 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2292 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2293
7fc527f9 2294 /* clear interrupts */
1c1008c7
FF		 2295 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2296
2297 netif_dbg(priv, intr, priv->dev,
c91b7f66 2298 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2299
4055eaef
PG		 2300 /* Check Rx priority queue interrupts */
2301 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2302 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2303 continue;
2304
2305 rx_ring = &priv->rx_rings[index];
2306
2307 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2308 rx_ring->int_disable(rx_ring);
2309 __napi_schedule(&rx_ring->napi);
2310 }
2311 }
2312
2313 /* Check Tx priority queue interrupts */
4092e6ac
JS		 2314 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2315 if (!(priv->irq1_stat & BIT(index)))
2316 continue;
2317
4055eaef 2318 tx_ring = &priv->tx_rings[index];
4092e6ac 2319
4055eaef
PG		 2320 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2321 tx_ring->int_disable(tx_ring);
2322 __napi_schedule(&tx_ring->napi);
1c1008c7
FF		 2323 }
2324 }
4092e6ac 2325
1c1008c7
FF		 2326 return IRQ_HANDLED;
2327}
2328
4055eaef 2329/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 2330static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2331{
2332 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2333 struct bcmgenet_rx_ring *rx_ring;
2334 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2335
2336 /* Save irq status for bottom-half processing. */
2337 priv->irq0_stat =
2338 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2339 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2340
7fc527f9 2341 /* clear interrupts */
1c1008c7
FF		 2342 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2343
2344 netif_dbg(priv, intr, priv->dev,
c91b7f66 2345 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7 2346
ee7d8c20 2347 if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
4055eaef
PG		 2348 rx_ring = &priv->rx_rings[DESC_INDEX];
2349
2350 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2351 rx_ring->int_disable(rx_ring);
2352 __napi_schedule(&rx_ring->napi);
1c1008c7
FF		 2353 }
2354 }
4092e6ac 2355
ee7d8c20 2356 if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 2357 tx_ring = &priv->tx_rings[DESC_INDEX];
2358
2359 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2360 tx_ring->int_disable(tx_ring);
2361 __napi_schedule(&tx_ring->napi);
4092e6ac 2362 }
1c1008c7 2363 }
4055eaef 2364
1c1008c7
FF		 2365 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2366 UMAC_IRQ_PHY_DET_F |
e122966d 2367 UMAC_IRQ_LINK_EVENT |
1c1008c7
FF		 2368 UMAC_IRQ_HFB_SM |
2369 UMAC_IRQ_HFB_MM |
2370 UMAC_IRQ_MPD_R)) {
2371 /* all other interested interrupts handled in bottom half */
2372 schedule_work(&priv->bcmgenet_irq_work);
2373 }
2374
2375 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2376 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2377 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2378 wake_up(&priv->wq);
2379 }
2380
2381 return IRQ_HANDLED;
2382}
2383
8562056f
FF		 2384static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2385{
2386 struct bcmgenet_priv *priv = dev_id;
2387
2388 pm_wakeup_event(&priv->pdev->dev, 0);
2389
2390 return IRQ_HANDLED;
2391}
2392
1c1008c7
FF		 2393static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2394{
2395 u32 reg;
2396
2397 reg = bcmgenet_rbuf_ctrl_get(priv);
2398 reg |= BIT(1);
2399 bcmgenet_rbuf_ctrl_set(priv, reg);
2400 udelay(10);
2401
2402 reg &= ~BIT(1);
2403 bcmgenet_rbuf_ctrl_set(priv, reg);
2404 udelay(10);
2405}
2406
2407static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2408 unsigned char *addr)
1c1008c7
FF		 2409{
2410 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2411 (addr[2] << 8) | addr[3], UMAC_MAC0);
2412 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2413}
2414
1c1008c7
FF		 2415/* Returns a reusable dma control register value */
2416static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2417{
2418 u32 reg;
2419 u32 dma_ctrl;
2420
2421 /* disable DMA */
2422 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2423 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2424 reg &= ~dma_ctrl;
2425 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2426
2427 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2428 reg &= ~dma_ctrl;
2429 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2430
2431 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2432 udelay(10);
2433 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2434
2435 return dma_ctrl;
2436}
2437
2438static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2439{
2440 u32 reg;
2441
2442 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2443 reg |= dma_ctrl;
2444 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2445
2446 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2447 reg |= dma_ctrl;
2448 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2449}
2450
0034de41
PG		 2451static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2452 u32 f_index)
2453{
2454 u32 offset;
2455 u32 reg;
2456
2457 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2458 reg = bcmgenet_hfb_reg_readl(priv, offset);
2459 return !!(reg & (1 << (f_index % 32)));
2460}
2461
2462static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2463{
2464 u32 offset;
2465 u32 reg;
2466
2467 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2468 reg = bcmgenet_hfb_reg_readl(priv, offset);
2469 reg |= (1 << (f_index % 32));
2470 bcmgenet_hfb_reg_writel(priv, reg, offset);
2471}
2472
2473static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2474 u32 f_index, u32 rx_queue)
2475{
2476 u32 offset;
2477 u32 reg;
2478
2479 offset = f_index / 8;
2480 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2481 reg &= ~(0xF << (4 * (f_index % 8)));
2482 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2483 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2484}
2485
2486static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2487 u32 f_index, u32 f_length)
2488{
2489 u32 offset;
2490 u32 reg;
2491
2492 offset = HFB_FLT_LEN_V3PLUS +
2493 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2494 sizeof(u32);
2495 reg = bcmgenet_hfb_reg_readl(priv, offset);
2496 reg &= ~(0xFF << (8 * (f_index % 4)));
2497 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2498 bcmgenet_hfb_reg_writel(priv, reg, offset);
2499}
2500
2501static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2502{
2503 u32 f_index;
2504
2505 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2506 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2507 return f_index;
2508
2509 return -ENOMEM;
2510}
2511
2512/* bcmgenet_hfb_add_filter
2513 *
2514 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2515 * desired Rx queue.
2516 *
2517 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2518 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2519 *
2520 * bits 31:20 - unused
2521 * bit 19 - nibble 0 match enable
2522 * bit 18 - nibble 1 match enable
2523 * bit 17 - nibble 2 match enable
2524 * bit 16 - nibble 3 match enable
2525 * bits 15:12 - nibble 0 data
2526 * bits 11:8 - nibble 1 data
2527 * bits 7:4 - nibble 2 data
2528 * bits 3:0 - nibble 3 data
2529 *
2530 * Example:
2531 * In order to match:
2532 * - Ethernet frame type = 0x0800 (IP)
2533 * - IP version field = 4
2534 * - IP protocol field = 0x11 (UDP)
2535 *
2536 * The following filter is needed:
2537 * u32 hfb_filter_ipv4_udp[] = {
2538 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2539 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2540 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2541 * };
2542 *
2543 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2544 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2545 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2546 */
2547int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2548 u32 f_length, u32 rx_queue)
2549{
2550 int f_index;
2551 u32 i;
2552
2553 f_index = bcmgenet_hfb_find_unused_filter(priv);
2554 if (f_index < 0)
2555 return -ENOMEM;
2556
2557 if (f_length > priv->hw_params->hfb_filter_size)
2558 return -EINVAL;
2559
2560 for (i = 0; i < f_length; i++)
2561 bcmgenet_hfb_writel(priv, f_data[i],
2562 (f_index * priv->hw_params->hfb_filter_size + i) *
2563 sizeof(u32));
2564
2565 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2566 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2567 bcmgenet_hfb_enable_filter(priv, f_index);
2568 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2569
2570 return 0;
2571}
2572
2573/* bcmgenet_hfb_clear
2574 *
2575 * Clear Hardware Filter Block and disable all filtering.
2576 */
2577static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2578{
2579 u32 i;
2580
2581 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2582 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2583 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2584
2585 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2586 bcmgenet_rdma_writel(priv, 0x0, i);
2587
2588 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2589 bcmgenet_hfb_reg_writel(priv, 0x0,
2590 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2591
2592 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2593 priv->hw_params->hfb_filter_size; i++)
2594 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2595}
2596
2597static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2598{
2599 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2600 return;
2601
2602 bcmgenet_hfb_clear(priv);
2603}
2604
909ff5ef
FF		 2605static void bcmgenet_netif_start(struct net_device *dev)
2606{
2607 struct bcmgenet_priv *priv = netdev_priv(dev);
2608
2609 /* Start the network engine */
3ab11339 2610 bcmgenet_enable_rx_napi(priv);
e2aadb4a 2611 bcmgenet_enable_tx_napi(priv);
909ff5ef
FF		 2612
2613 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2614
909ff5ef
FF		 2615 netif_tx_start_all_queues(dev);
2616
2617 phy_start(priv->phydev);
2618}
2619
1c1008c7
FF		 2620static int bcmgenet_open(struct net_device *dev)
2621{
2622 struct bcmgenet_priv *priv = netdev_priv(dev);
2623 unsigned long dma_ctrl;
2624 u32 reg;
2625 int ret;
2626
2627 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2628
2629 /* Turn on the clock */
2630 if (!IS_ERR(priv->clk))
2631 clk_prepare_enable(priv->clk);
2632
a642c4f7
FF		 2633 /* If this is an internal GPHY, power it back on now, before UniMAC is
2634 * brought out of reset as absolutely no UniMAC activity is allowed
2635 */
2636 if (phy_is_internal(priv->phydev))
2637 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2638
1c1008c7
FF		 2639 /* take MAC out of reset */
2640 bcmgenet_umac_reset(priv);
2641
2642 ret = init_umac(priv);
2643 if (ret)
2644 goto err_clk_disable;
2645
2646 /* disable ethernet MAC while updating its registers */
e29585b8 2647 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2648
909ff5ef
FF		 2649 /* Make sure we reflect the value of CRC_CMD_FWD */
2650 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2651 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2652
1c1008c7
FF		 2653 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2654
1c1008c7
FF		 2655 if (phy_is_internal(priv->phydev)) {
2656 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2657 reg |= EXT_ENERGY_DET_MASK;
2658 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2659 }
2660
2661 /* Disable RX/TX DMA and flush TX queues */
2662 dma_ctrl = bcmgenet_dma_disable(priv);
2663
2664 /* Reinitialize TDMA and RDMA and SW housekeeping */
2665 ret = bcmgenet_init_dma(priv);
2666 if (ret) {
2667 netdev_err(dev, "failed to initialize DMA\n");
fac25940 2668 goto err_clk_disable;
1c1008c7
FF		 2669 }
2670
2671 /* Always enable ring 16 - descriptor ring */
2672 bcmgenet_enable_dma(priv, dma_ctrl);
2673
0034de41
PG		 2674 /* HFB init */
2675 bcmgenet_hfb_init(priv);
2676
1c1008c7 2677 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2678 dev->name, priv);
1c1008c7
FF		 2679 if (ret < 0) {
2680 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2681 goto err_fini_dma;
2682 }
2683
2684 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2685 dev->name, priv);
1c1008c7
FF		 2686 if (ret < 0) {
2687 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2688 goto err_irq0;
2689 }
2690
dbd479db
FF		 2691 /* Re-configure the port multiplexer towards the PHY device */
2692 bcmgenet_mii_config(priv->dev, false);
2693
c96e731c
FF		 2694 phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2695 priv->phy_interface);
2696
909ff5ef 2697 bcmgenet_netif_start(dev);
1c1008c7
FF		 2698
2699 return 0;
2700
2701err_irq0:
2702 free_irq(priv->irq0, dev);
2703err_fini_dma:
2704 bcmgenet_fini_dma(priv);
2705err_clk_disable:
2706 if (!IS_ERR(priv->clk))
2707 clk_disable_unprepare(priv->clk);
2708 return ret;
2709}
2710
909ff5ef
FF		 2711static void bcmgenet_netif_stop(struct net_device *dev)
2712{
2713 struct bcmgenet_priv *priv = netdev_priv(dev);
2714
2715 netif_tx_stop_all_queues(dev);
909ff5ef 2716 phy_stop(priv->phydev);
909ff5ef 2717 bcmgenet_intr_disable(priv);
3ab11339 2718 bcmgenet_disable_rx_napi(priv);
e2aadb4a 2719 bcmgenet_disable_tx_napi(priv);
909ff5ef
FF		 2720
2721 /* Wait for pending work items to complete. Since interrupts are
2722 * disabled no new work will be scheduled.
2723 */
2724 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2725
cc013fb4 2726 priv->old_link = -1;
5ad6e6c5 2727 priv->old_speed = -1;
cc013fb4 2728 priv->old_duplex = -1;
5ad6e6c5 2729 priv->old_pause = -1;
909ff5ef
FF		 2730}
2731
1c1008c7
FF		 2732static int bcmgenet_close(struct net_device *dev)
2733{
2734 struct bcmgenet_priv *priv = netdev_priv(dev);
2735 int ret;
1c1008c7
FF		 2736
2737 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2738
909ff5ef 2739 bcmgenet_netif_stop(dev);
1c1008c7 2740
c96e731c
FF		 2741 /* Really kill the PHY state machine and disconnect from it */
2742 phy_disconnect(priv->phydev);
2743
1c1008c7 2744 /* Disable MAC receive */
e29585b8 2745 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2746
1c1008c7
FF		 2747 ret = bcmgenet_dma_teardown(priv);
2748 if (ret)
2749 return ret;
2750
2751 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2752 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2753
1c1008c7
FF		 2754 /* tx reclaim */
2755 bcmgenet_tx_reclaim_all(dev);
2756 bcmgenet_fini_dma(priv);
2757
2758 free_irq(priv->irq0, priv);
2759 free_irq(priv->irq1, priv);
2760
1c1008c7 2761 if (phy_is_internal(priv->phydev))
ca8cf341 2762 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 2763
1c1008c7
FF		 2764 if (!IS_ERR(priv->clk))
2765 clk_disable_unprepare(priv->clk);
2766
ca8cf341 2767 return ret;
1c1008c7
FF		 2768}
2769
2770static void bcmgenet_timeout(struct net_device *dev)
2771{
2772 struct bcmgenet_priv *priv = netdev_priv(dev);
2773
2774 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2775
2776 dev->trans_start = jiffies;
2777
2778 dev->stats.tx_errors++;
2779
2780 netif_tx_wake_all_queues(dev);
2781}
2782
2783#define MAX_MC_COUNT 16
2784
2785static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2786 unsigned char *addr,
2787 int *i,
2788 int *mc)
2789{
2790 u32 reg;
2791
c91b7f66
FF		 2792 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2793 UMAC_MDF_ADDR + (*i * 4));
2794 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2795 addr[4] << 8 | addr[5],
2796 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2797 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2798 reg |= (1 << (MAX_MC_COUNT - *mc));
2799 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2800 *i += 2;
2801 (*mc)++;
2802}
2803
2804static void bcmgenet_set_rx_mode(struct net_device *dev)
2805{
2806 struct bcmgenet_priv *priv = netdev_priv(dev);
2807 struct netdev_hw_addr *ha;
2808 int i, mc;
2809 u32 reg;
2810
2811 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2812
7fc527f9 2813 /* Promiscuous mode */
1c1008c7
FF		 2814 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2815 if (dev->flags & IFF_PROMISC) {
2816 reg |= CMD_PROMISC;
2817 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2818 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2819 return;
2820 } else {
2821 reg &= ~CMD_PROMISC;
2822 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2823 }
2824
2825 /* UniMac doesn't support ALLMULTI */
2826 if (dev->flags & IFF_ALLMULTI) {
2827 netdev_warn(dev, "ALLMULTI is not supported\n");
2828 return;
2829 }
2830
2831 /* update MDF filter */
2832 i = 0;
2833 mc = 0;
2834 /* Broadcast */
2835 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2836 /* my own address.*/
2837 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2838 /* Unicast list*/
2839 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2840 return;
2841
2842 if (!netdev_uc_empty(dev))
2843 netdev_for_each_uc_addr(ha, dev)
2844 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2845 /* Multicast */
2846 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2847 return;
2848
2849 netdev_for_each_mc_addr(ha, dev)
2850 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2851}
2852
2853/* Set the hardware MAC address. */
2854static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2855{
2856 struct sockaddr *addr = p;
2857
2858 /* Setting the MAC address at the hardware level is not possible
2859 * without disabling the UniMAC RX/TX enable bits.
2860 */
2861 if (netif_running(dev))
2862 return -EBUSY;
2863
2864 ether_addr_copy(dev->dev_addr, addr->sa_data);
2865
2866 return 0;
2867}
2868
1c1008c7
FF		 2869static const struct net_device_ops bcmgenet_netdev_ops = {
2870 .ndo_open = bcmgenet_open,
2871 .ndo_stop = bcmgenet_close,
2872 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2873 .ndo_tx_timeout = bcmgenet_timeout,
2874 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2875 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2876 .ndo_do_ioctl = bcmgenet_ioctl,
2877 .ndo_set_features = bcmgenet_set_features,
2878};
2879
2880/* Array of GENET hardware parameters/characteristics */
2881static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2882 [GENET_V1] = {
2883 .tx_queues = 0,
51a966a7 2884 .tx_bds_per_q = 0,
1c1008c7 2885 .rx_queues = 0,
3feafa02 2886 .rx_bds_per_q = 0,
1c1008c7
FF		 2887 .bp_in_en_shift = 16,
2888 .bp_in_mask = 0xffff,
2889 .hfb_filter_cnt = 16,
2890 .qtag_mask = 0x1F,
2891 .hfb_offset = 0x1000,
2892 .rdma_offset = 0x2000,
2893 .tdma_offset = 0x3000,
2894 .words_per_bd = 2,
2895 },
2896 [GENET_V2] = {
2897 .tx_queues = 4,
51a966a7 2898 .tx_bds_per_q = 32,
7e906e02 2899 .rx_queues = 0,
3feafa02 2900 .rx_bds_per_q = 0,
1c1008c7
FF		 2901 .bp_in_en_shift = 16,
2902 .bp_in_mask = 0xffff,
2903 .hfb_filter_cnt = 16,
2904 .qtag_mask = 0x1F,
2905 .tbuf_offset = 0x0600,
2906 .hfb_offset = 0x1000,
2907 .hfb_reg_offset = 0x2000,
2908 .rdma_offset = 0x3000,
2909 .tdma_offset = 0x4000,
2910 .words_per_bd = 2,
2911 .flags = GENET_HAS_EXT,
2912 },
2913 [GENET_V3] = {
2914 .tx_queues = 4,
51a966a7 2915 .tx_bds_per_q = 32,
7e906e02 2916 .rx_queues = 0,
3feafa02 2917 .rx_bds_per_q = 0,
1c1008c7
FF		 2918 .bp_in_en_shift = 17,
2919 .bp_in_mask = 0x1ffff,
2920 .hfb_filter_cnt = 48,
0034de41 2921 .hfb_filter_size = 128,
1c1008c7
FF		 2922 .qtag_mask = 0x3F,
2923 .tbuf_offset = 0x0600,
2924 .hfb_offset = 0x8000,
2925 .hfb_reg_offset = 0xfc00,
2926 .rdma_offset = 0x10000,
2927 .tdma_offset = 0x11000,
2928 .words_per_bd = 2,
2929 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2930 },
2931 [GENET_V4] = {
2932 .tx_queues = 4,
51a966a7 2933 .tx_bds_per_q = 32,
7e906e02 2934 .rx_queues = 0,
3feafa02 2935 .rx_bds_per_q = 0,
1c1008c7
FF		 2936 .bp_in_en_shift = 17,
2937 .bp_in_mask = 0x1ffff,
2938 .hfb_filter_cnt = 48,
0034de41 2939 .hfb_filter_size = 128,
1c1008c7
FF		 2940 .qtag_mask = 0x3F,
2941 .tbuf_offset = 0x0600,
2942 .hfb_offset = 0x8000,
2943 .hfb_reg_offset = 0xfc00,
2944 .rdma_offset = 0x2000,
2945 .tdma_offset = 0x4000,
2946 .words_per_bd = 3,
2947 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2948 },
2949};
2950
2951/* Infer hardware parameters from the detected GENET version */
2952static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2953{
2954 struct bcmgenet_hw_params *params;
2955 u32 reg;
2956 u8 major;
b04a2f5b 2957 u16 gphy_rev;
1c1008c7
FF		 2958
2959 if (GENET_IS_V4(priv)) {
2960 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2961 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2962 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2963 priv->version = GENET_V4;
2964 } else if (GENET_IS_V3(priv)) {
2965 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2966 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2967 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2968 priv->version = GENET_V3;
2969 } else if (GENET_IS_V2(priv)) {
2970 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2971 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2972 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2973 priv->version = GENET_V2;
2974 } else if (GENET_IS_V1(priv)) {
2975 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2976 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2977 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2978 priv->version = GENET_V1;
2979 }
2980
2981 /* enum genet_version starts at 1 */
2982 priv->hw_params = &bcmgenet_hw_params[priv->version];
2983 params = priv->hw_params;
2984
2985 /* Read GENET HW version */
2986 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2987 major = (reg >> 24 & 0x0f);
2988 if (major == 5)
2989 major = 4;
2990 else if (major == 0)
2991 major = 1;
2992 if (major != priv->version) {
2993 dev_err(&priv->pdev->dev,
2994 "GENET version mismatch, got: %d, configured for: %d\n",
2995 major, priv->version);
2996 }
2997
2998 /* Print the GENET core version */
2999 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3000 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3001
487320c5
FF		 3002 /* Store the integrated PHY revision for the MDIO probing function
3003 * to pass this information to the PHY driver. The PHY driver expects
3004 * to find the PHY major revision in bits 15:8 while the GENET register
3005 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3006 *
3007 * On newer chips, starting with PHY revision G0, a new scheme is
3008 * deployed similar to the Starfighter 2 switch with GPHY major
3009 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3010 * is reserved as well as special value 0x01ff, we have a small
3011 * heuristic to check for the new GPHY revision and re-arrange things
3012 * so the GPHY driver is happy.
487320c5 3013 */
b04a2f5b
FF		 3014 gphy_rev = reg & 0xffff;
3015
3016 /* This is the good old scheme, just GPHY major, no minor nor patch */
3017 if ((gphy_rev & 0xf0) != 0)
3018 priv->gphy_rev = gphy_rev << 8;
3019
3020 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3021 else if ((gphy_rev & 0xff00) != 0)
3022 priv->gphy_rev = gphy_rev;
3023
3024 /* This is reserved so should require special treatment */
3025 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3026 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3027 return;
3028 }
487320c5 3029
1c1008c7
FF		 3030#ifdef CONFIG_PHYS_ADDR_T_64BIT
3031 if (!(params->flags & GENET_HAS_40BITS))
3032 pr_warn("GENET does not support 40-bits PA\n");
3033#endif
3034
3035 pr_debug("Configuration for version: %d\n"
3feafa02 3036 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3037 "BP << en: %2d, BP msk: 0x%05x\n"
3038 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3039 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3040 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3041 "Words/BD: %d\n",
3042 priv->version,
51a966a7 3043 params->tx_queues, params->tx_bds_per_q,
3feafa02 3044 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3045 params->bp_in_en_shift, params->bp_in_mask,
3046 params->hfb_filter_cnt, params->qtag_mask,
3047 params->tbuf_offset, params->hfb_offset,
3048 params->hfb_reg_offset,
3049 params->rdma_offset, params->tdma_offset,
3050 params->words_per_bd);
3051}
3052
3053static const struct of_device_id bcmgenet_match[] = {
3054 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3055 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3056 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3057 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3058 { },
3059};
3060
3061static int bcmgenet_probe(struct platform_device *pdev)
3062{
b0ba512e 3063 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 3064 struct device_node *dn = pdev->dev.of_node;
b0ba512e 3065 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 3066 struct bcmgenet_priv *priv;
3067 struct net_device *dev;
3068 const void *macaddr;
3069 struct resource *r;
3070 int err = -EIO;
3071
3feafeed
PG		 3072 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3073 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3074 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3075 if (!dev) {
3076 dev_err(&pdev->dev, "can't allocate net device\n");
3077 return -ENOMEM;
3078 }
3079
b0ba512e
PG		 3080 if (dn) {
3081 of_id = of_match_node(bcmgenet_match, dn);
3082 if (!of_id)
3083 return -EINVAL;
3084 }
1c1008c7
FF		 3085
3086 priv = netdev_priv(dev);
3087 priv->irq0 = platform_get_irq(pdev, 0);
3088 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 3089 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 3090 if (!priv->irq0 || !priv->irq1) {
3091 dev_err(&pdev->dev, "can't find IRQs\n");
3092 err = -EINVAL;
3093 goto err;
3094 }
3095
b0ba512e
PG		 3096 if (dn) {
3097 macaddr = of_get_mac_address(dn);
3098 if (!macaddr) {
3099 dev_err(&pdev->dev, "can't find MAC address\n");
3100 err = -EINVAL;
3101 goto err;
3102 }
3103 } else {
3104 macaddr = pd->mac_address;
1c1008c7
FF		 3105 }
3106
3107 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 3108 priv->base = devm_ioremap_resource(&pdev->dev, r);
3109 if (IS_ERR(priv->base)) {
3110 err = PTR_ERR(priv->base);
1c1008c7
FF		 3111 goto err;
3112 }
3113
3114 SET_NETDEV_DEV(dev, &pdev->dev);
3115 dev_set_drvdata(&pdev->dev, dev);
3116 ether_addr_copy(dev->dev_addr, macaddr);
3117 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 3118 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 3119 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 3120
3121 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3122
3123 /* Set hardware features */
3124 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3125 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3126
8562056f
FF		 3127 /* Request the WOL interrupt and advertise suspend if available */
3128 priv->wol_irq_disabled = true;
3129 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3130 dev->name, priv);
3131 if (!err)
3132 device_set_wakeup_capable(&pdev->dev, 1);
3133
1c1008c7
FF		 3134 /* Set the needed headroom to account for any possible
3135 * features enabling/disabling at runtime
3136 */
3137 dev->needed_headroom += 64;
3138
3139 netdev_boot_setup_check(dev);
3140
3141 priv->dev = dev;
3142 priv->pdev = pdev;
b0ba512e
PG		 3143 if (of_id)
3144 priv->version = (enum bcmgenet_version)of_id->data;
3145 else
3146 priv->version = pd->genet_version;
1c1008c7 3147
e4a60a93
FF		 3148 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3149 if (IS_ERR(priv->clk))
3150 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3151
3152 if (!IS_ERR(priv->clk))
3153 clk_prepare_enable(priv->clk);
3154
1c1008c7
FF		 3155 bcmgenet_set_hw_params(priv);
3156
1c1008c7
FF		 3157 /* Mii wait queue */
3158 init_waitqueue_head(&priv->wq);
3159 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3160 priv->rx_buf_len = RX_BUF_LENGTH;
3161 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3162
1c1008c7
FF		 3163 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3164 if (IS_ERR(priv->clk_wol))
3165 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3166
6ef398ea
FF		 3167 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3168 if (IS_ERR(priv->clk_eee)) {
3169 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3170 priv->clk_eee = NULL;
3171 }
3172
1c1008c7
FF		 3173 err = reset_umac(priv);
3174 if (err)
3175 goto err_clk_disable;
3176
3177 err = bcmgenet_mii_init(dev);
3178 if (err)
3179 goto err_clk_disable;
3180
3181 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3182 * just the ring 16 descriptor based TX
3183 */
3184 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3185 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3186
219575eb
FF		 3187 /* libphy will determine the link state */
3188 netif_carrier_off(dev);
3189
1c1008c7
FF		 3190 /* Turn off the main clock, WOL clock is handled separately */
3191 if (!IS_ERR(priv->clk))
3192 clk_disable_unprepare(priv->clk);
3193
0f50ce96
FF		 3194 err = register_netdev(dev);
3195 if (err)
3196 goto err;
3197
1c1008c7
FF		 3198 return err;
3199
3200err_clk_disable:
3201 if (!IS_ERR(priv->clk))
3202 clk_disable_unprepare(priv->clk);
3203err:
3204 free_netdev(dev);
3205 return err;
3206}
3207
3208static int bcmgenet_remove(struct platform_device *pdev)
3209{
3210 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3211
3212 dev_set_drvdata(&pdev->dev, NULL);
3213 unregister_netdev(priv->dev);
3214 bcmgenet_mii_exit(priv->dev);
3215 free_netdev(priv->dev);
3216
3217 return 0;
3218}
3219
b6e978e5
FF		 3220#ifdef CONFIG_PM_SLEEP
3221static int bcmgenet_suspend(struct device *d)
3222{
3223 struct net_device *dev = dev_get_drvdata(d);
3224 struct bcmgenet_priv *priv = netdev_priv(dev);
3225 int ret;
3226
3227 if (!netif_running(dev))
3228 return 0;
3229
3230 bcmgenet_netif_stop(dev);
3231
cc013fb4
FF		 3232 phy_suspend(priv->phydev);
3233
b6e978e5
FF		 3234 netif_device_detach(dev);
3235
3236 /* Disable MAC receive */
3237 umac_enable_set(priv, CMD_RX_EN, false);
3238
3239 ret = bcmgenet_dma_teardown(priv);
3240 if (ret)
3241 return ret;
3242
3243 /* Disable MAC transmit. TX DMA disabled have to done before this */
3244 umac_enable_set(priv, CMD_TX_EN, false);
3245
3246 /* tx reclaim */
3247 bcmgenet_tx_reclaim_all(dev);
3248 bcmgenet_fini_dma(priv);
3249
8c90db72
FF		 3250 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3251 if (device_may_wakeup(d) && priv->wolopts) {
ca8cf341 3252 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
8c90db72 3253 clk_prepare_enable(priv->clk_wol);
a6f31f5e
FF		 3254 } else if (phy_is_internal(priv->phydev)) {
3255 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
8c90db72
FF		 3256 }
3257
b6e978e5
FF		 3258 /* Turn off the clocks */
3259 clk_disable_unprepare(priv->clk);
3260
ca8cf341 3261 return ret;
b6e978e5
FF		 3262}
3263
3264static int bcmgenet_resume(struct device *d)
3265{
3266 struct net_device *dev = dev_get_drvdata(d);
3267 struct bcmgenet_priv *priv = netdev_priv(dev);
3268 unsigned long dma_ctrl;
3269 int ret;
3270 u32 reg;
3271
3272 if (!netif_running(dev))
3273 return 0;
3274
3275 /* Turn on the clock */
3276 ret = clk_prepare_enable(priv->clk);
3277 if (ret)
3278 return ret;
3279
a6f31f5e
FF		 3280 /* If this is an internal GPHY, power it back on now, before UniMAC is
3281 * brought out of reset as absolutely no UniMAC activity is allowed
3282 */
3283 if (phy_is_internal(priv->phydev))
3284 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3285
b6e978e5
FF		 3286 bcmgenet_umac_reset(priv);
3287
3288 ret = init_umac(priv);
3289 if (ret)
3290 goto out_clk_disable;
3291
0a29b3da
TK		 3292 /* From WOL-enabled suspend, switch to regular clock */
3293 if (priv->wolopts)
3294 clk_disable_unprepare(priv->clk_wol);
3295
3296 phy_init_hw(priv->phydev);
3297 /* Speed settings must be restored */
dbd479db 3298 bcmgenet_mii_config(priv->dev, false);
8c90db72 3299
b6e978e5
FF		 3300 /* disable ethernet MAC while updating its registers */
3301 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3302
3303 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3304
3305 if (phy_is_internal(priv->phydev)) {
3306 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3307 reg |= EXT_ENERGY_DET_MASK;
3308 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3309 }
3310
98bb7399
FF		 3311 if (priv->wolopts)
3312 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3313
b6e978e5
FF		 3314 /* Disable RX/TX DMA and flush TX queues */
3315 dma_ctrl = bcmgenet_dma_disable(priv);
3316
3317 /* Reinitialize TDMA and RDMA and SW housekeeping */
3318 ret = bcmgenet_init_dma(priv);
3319 if (ret) {
3320 netdev_err(dev, "failed to initialize DMA\n");
3321 goto out_clk_disable;
3322 }
3323
3324 /* Always enable ring 16 - descriptor ring */
3325 bcmgenet_enable_dma(priv, dma_ctrl);
3326
3327 netif_device_attach(dev);
3328
cc013fb4
FF		 3329 phy_resume(priv->phydev);
3330
6ef398ea
FF		 3331 if (priv->eee.eee_enabled)
3332 bcmgenet_eee_enable_set(dev, true);
3333
b6e978e5
FF		 3334 bcmgenet_netif_start(dev);
3335
3336 return 0;
3337
3338out_clk_disable:
3339 clk_disable_unprepare(priv->clk);
3340 return ret;
3341}
3342#endif /* CONFIG_PM_SLEEP */
3343
3344static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3345
1c1008c7
FF		 3346static struct platform_driver bcmgenet_driver = {
3347 .probe = bcmgenet_probe,
3348 .remove = bcmgenet_remove,
3349 .driver = {
3350 .name = "bcmgenet",
1c1008c7 3351 .of_match_table = bcmgenet_match,
b6e978e5 3352 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 3353 },
3354};
3355module_platform_driver(bcmgenet_driver);
3356
3357MODULE_AUTHOR("Broadcom Corporation");
3358MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3359MODULE_ALIAS("platform:bcmgenet");
3360MODULE_LICENSE("GPL");
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