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net: bcmgenet: add umac_enable_set helper
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20#define pr_fmt(fmt) "bcmgenet: " fmt
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/sched.h>
25#include <linux/types.h>
26#include <linux/fcntl.h>
27#include <linux/interrupt.h>
28#include <linux/string.h>
29#include <linux/if_ether.h>
30#include <linux/init.h>
31#include <linux/errno.h>
32#include <linux/delay.h>
33#include <linux/platform_device.h>
34#include <linux/dma-mapping.h>
35#include <linux/pm.h>
36#include <linux/clk.h>
1c1008c7
FF		 37#include <linux/of.h>
38#include <linux/of_address.h>
39#include <linux/of_irq.h>
40#include <linux/of_net.h>
41#include <linux/of_platform.h>
42#include <net/arp.h>
43
44#include <linux/mii.h>
45#include <linux/ethtool.h>
46#include <linux/netdevice.h>
47#include <linux/inetdevice.h>
48#include <linux/etherdevice.h>
49#include <linux/skbuff.h>
50#include <linux/in.h>
51#include <linux/ip.h>
52#include <linux/ipv6.h>
53#include <linux/phy.h>
54
55#include <asm/unaligned.h>
56
57#include "bcmgenet.h"
58
59/* Maximum number of hardware queues, downsized if needed */
60#define GENET_MAX_MQ_CNT 4
61
62/* Default highest priority queue for multi queue support */
63#define GENET_Q0_PRIORITY 0
64
65#define GENET_DEFAULT_BD_CNT \
66 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
67
68#define RX_BUF_LENGTH 2048
69#define SKB_ALIGNMENT 32
70
71/* Tx/Rx DMA register offset, skip 256 descriptors */
72#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
73#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
74
75#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
76 TOTAL_DESC * DMA_DESC_SIZE)
77
78#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
79 TOTAL_DESC * DMA_DESC_SIZE)
80
81static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
82 void __iomem *d, u32 value)
83{
84 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
88 void __iomem *d)
89{
90 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
91}
92
93static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
94 void __iomem *d,
95 dma_addr_t addr)
96{
97 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
98
99 /* Register writes to GISB bus can take couple hundred nanoseconds
100 * and are done for each packet, save these expensive writes unless
101 * the platform is explicitely configured for 64-bits/LPAE.
102 */
103#ifdef CONFIG_PHYS_ADDR_T_64BIT
104 if (priv->hw_params->flags & GENET_HAS_40BITS)
105 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
106#endif
107}
108
109/* Combined address + length/status setter */
110static inline void dmadesc_set(struct bcmgenet_priv *priv,
111 void __iomem *d, dma_addr_t addr, u32 val)
112{
113 dmadesc_set_length_status(priv, d, val);
114 dmadesc_set_addr(priv, d, addr);
115}
116
117static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
118 void __iomem *d)
119{
120 dma_addr_t addr;
121
122 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
123
124 /* Register writes to GISB bus can take couple hundred nanoseconds
125 * and are done for each packet, save these expensive writes unless
126 * the platform is explicitely configured for 64-bits/LPAE.
127 */
128#ifdef CONFIG_PHYS_ADDR_T_64BIT
129 if (priv->hw_params->flags & GENET_HAS_40BITS)
130 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
131#endif
132 return addr;
133}
134
135#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
136
137#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
138 NETIF_MSG_LINK)
139
140static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
141{
142 if (GENET_IS_V1(priv))
143 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
144 else
145 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
146}
147
148static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
149{
150 if (GENET_IS_V1(priv))
151 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
152 else
153 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
154}
155
156/* These macros are defined to deal with register map change
157 * between GENET1.1 and GENET2. Only those currently being used
158 * by driver are defined.
159 */
160static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
161{
162 if (GENET_IS_V1(priv))
163 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
164 else
165 return __raw_readl(priv->base +
166 priv->hw_params->tbuf_offset + TBUF_CTRL);
167}
168
169static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
170{
171 if (GENET_IS_V1(priv))
172 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
173 else
174 __raw_writel(val, priv->base +
175 priv->hw_params->tbuf_offset + TBUF_CTRL);
176}
177
178static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
179{
180 if (GENET_IS_V1(priv))
181 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
182 else
183 return __raw_readl(priv->base +
184 priv->hw_params->tbuf_offset + TBUF_BP_MC);
185}
186
187static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
188{
189 if (GENET_IS_V1(priv))
190 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
191 else
192 __raw_writel(val, priv->base +
193 priv->hw_params->tbuf_offset + TBUF_BP_MC);
194}
195
196/* RX/TX DMA register accessors */
197enum dma_reg {
198 DMA_RING_CFG = 0,
199 DMA_CTRL,
200 DMA_STATUS,
201 DMA_SCB_BURST_SIZE,
202 DMA_ARB_CTRL,
203 DMA_PRIORITY,
204 DMA_RING_PRIORITY,
205};
206
207static const u8 bcmgenet_dma_regs_v3plus[] = {
208 [DMA_RING_CFG] = 0x00,
209 [DMA_CTRL] = 0x04,
210 [DMA_STATUS] = 0x08,
211 [DMA_SCB_BURST_SIZE] = 0x0C,
212 [DMA_ARB_CTRL] = 0x2C,
213 [DMA_PRIORITY] = 0x30,
214 [DMA_RING_PRIORITY] = 0x38,
215};
216
217static const u8 bcmgenet_dma_regs_v2[] = {
218 [DMA_RING_CFG] = 0x00,
219 [DMA_CTRL] = 0x04,
220 [DMA_STATUS] = 0x08,
221 [DMA_SCB_BURST_SIZE] = 0x0C,
222 [DMA_ARB_CTRL] = 0x30,
223 [DMA_PRIORITY] = 0x34,
224 [DMA_RING_PRIORITY] = 0x3C,
225};
226
227static const u8 bcmgenet_dma_regs_v1[] = {
228 [DMA_CTRL] = 0x00,
229 [DMA_STATUS] = 0x04,
230 [DMA_SCB_BURST_SIZE] = 0x0C,
231 [DMA_ARB_CTRL] = 0x30,
232 [DMA_PRIORITY] = 0x34,
233 [DMA_RING_PRIORITY] = 0x3C,
234};
235
236/* Set at runtime once bcmgenet version is known */
237static const u8 *bcmgenet_dma_regs;
238
239static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
240{
241 return netdev_priv(dev_get_drvdata(dev));
242}
243
244static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
245 enum dma_reg r)
246{
247 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
248 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
249}
250
251static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
252 u32 val, enum dma_reg r)
253{
254 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
255 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
256}
257
258static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
259 enum dma_reg r)
260{
261 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
262 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
263}
264
265static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
266 u32 val, enum dma_reg r)
267{
268 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
269 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
270}
271
272/* RDMA/TDMA ring registers and accessors
273 * we merge the common fields and just prefix with T/D the registers
274 * having different meaning depending on the direction
275 */
276enum dma_ring_reg {
277 TDMA_READ_PTR = 0,
278 RDMA_WRITE_PTR = TDMA_READ_PTR,
279 TDMA_READ_PTR_HI,
280 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
281 TDMA_CONS_INDEX,
282 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
283 TDMA_PROD_INDEX,
284 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
285 DMA_RING_BUF_SIZE,
286 DMA_START_ADDR,
287 DMA_START_ADDR_HI,
288 DMA_END_ADDR,
289 DMA_END_ADDR_HI,
290 DMA_MBUF_DONE_THRESH,
291 TDMA_FLOW_PERIOD,
292 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
293 TDMA_WRITE_PTR,
294 RDMA_READ_PTR = TDMA_WRITE_PTR,
295 TDMA_WRITE_PTR_HI,
296 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
297};
298
299/* GENET v4 supports 40-bits pointer addressing
300 * for obvious reasons the LO and HI word parts
301 * are contiguous, but this offsets the other
302 * registers.
303 */
304static const u8 genet_dma_ring_regs_v4[] = {
305 [TDMA_READ_PTR] = 0x00,
306 [TDMA_READ_PTR_HI] = 0x04,
307 [TDMA_CONS_INDEX] = 0x08,
308 [TDMA_PROD_INDEX] = 0x0C,
309 [DMA_RING_BUF_SIZE] = 0x10,
310 [DMA_START_ADDR] = 0x14,
311 [DMA_START_ADDR_HI] = 0x18,
312 [DMA_END_ADDR] = 0x1C,
313 [DMA_END_ADDR_HI] = 0x20,
314 [DMA_MBUF_DONE_THRESH] = 0x24,
315 [TDMA_FLOW_PERIOD] = 0x28,
316 [TDMA_WRITE_PTR] = 0x2C,
317 [TDMA_WRITE_PTR_HI] = 0x30,
318};
319
320static const u8 genet_dma_ring_regs_v123[] = {
321 [TDMA_READ_PTR] = 0x00,
322 [TDMA_CONS_INDEX] = 0x04,
323 [TDMA_PROD_INDEX] = 0x08,
324 [DMA_RING_BUF_SIZE] = 0x0C,
325 [DMA_START_ADDR] = 0x10,
326 [DMA_END_ADDR] = 0x14,
327 [DMA_MBUF_DONE_THRESH] = 0x18,
328 [TDMA_FLOW_PERIOD] = 0x1C,
329 [TDMA_WRITE_PTR] = 0x20,
330};
331
332/* Set at runtime once GENET version is known */
333static const u8 *genet_dma_ring_regs;
334
335static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
336 unsigned int ring,
337 enum dma_ring_reg r)
338{
339 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
340 (DMA_RING_SIZE * ring) +
341 genet_dma_ring_regs[r]);
342}
343
344static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
345 unsigned int ring,
346 u32 val,
347 enum dma_ring_reg r)
348{
349 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
350 (DMA_RING_SIZE * ring) +
351 genet_dma_ring_regs[r]);
352}
353
354static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
355 unsigned int ring,
356 enum dma_ring_reg r)
357{
358 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
359 (DMA_RING_SIZE * ring) +
360 genet_dma_ring_regs[r]);
361}
362
363static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
364 unsigned int ring,
365 u32 val,
366 enum dma_ring_reg r)
367{
368 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
369 (DMA_RING_SIZE * ring) +
370 genet_dma_ring_regs[r]);
371}
372
373static int bcmgenet_get_settings(struct net_device *dev,
374 struct ethtool_cmd *cmd)
375{
376 struct bcmgenet_priv *priv = netdev_priv(dev);
377
378 if (!netif_running(dev))
379 return -EINVAL;
380
381 if (!priv->phydev)
382 return -ENODEV;
383
384 return phy_ethtool_gset(priv->phydev, cmd);
385}
386
387static int bcmgenet_set_settings(struct net_device *dev,
388 struct ethtool_cmd *cmd)
389{
390 struct bcmgenet_priv *priv = netdev_priv(dev);
391
392 if (!netif_running(dev))
393 return -EINVAL;
394
395 if (!priv->phydev)
396 return -ENODEV;
397
398 return phy_ethtool_sset(priv->phydev, cmd);
399}
400
401static int bcmgenet_set_rx_csum(struct net_device *dev,
402 netdev_features_t wanted)
403{
404 struct bcmgenet_priv *priv = netdev_priv(dev);
405 u32 rbuf_chk_ctrl;
406 bool rx_csum_en;
407
408 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
409
410 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
411
412 /* enable rx checksumming */
413 if (rx_csum_en)
414 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
415 else
416 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
417 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 418
419 /* If UniMAC forwards CRC, we need to skip over it to get
420 * a valid CHK bit to be set in the per-packet status word
421 */
422 if (rx_csum_en && priv->crc_fwd_en)
423 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
424 else
425 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
426
1c1008c7
FF		 427 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
428
429 return 0;
430}
431
432static int bcmgenet_set_tx_csum(struct net_device *dev,
433 netdev_features_t wanted)
434{
435 struct bcmgenet_priv *priv = netdev_priv(dev);
436 bool desc_64b_en;
437 u32 tbuf_ctrl, rbuf_ctrl;
438
439 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
440 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
441
442 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
443
444 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
445 if (desc_64b_en) {
446 tbuf_ctrl |= RBUF_64B_EN;
447 rbuf_ctrl |= RBUF_64B_EN;
448 } else {
449 tbuf_ctrl &= ~RBUF_64B_EN;
450 rbuf_ctrl &= ~RBUF_64B_EN;
451 }
452 priv->desc_64b_en = desc_64b_en;
453
454 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
455 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
456
457 return 0;
458}
459
460static int bcmgenet_set_features(struct net_device *dev,
461 netdev_features_t features)
462{
463 netdev_features_t changed = features ^ dev->features;
464 netdev_features_t wanted = dev->wanted_features;
465 int ret = 0;
466
467 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
468 ret = bcmgenet_set_tx_csum(dev, wanted);
469 if (changed & (NETIF_F_RXCSUM))
470 ret = bcmgenet_set_rx_csum(dev, wanted);
471
472 return ret;
473}
474
475static u32 bcmgenet_get_msglevel(struct net_device *dev)
476{
477 struct bcmgenet_priv *priv = netdev_priv(dev);
478
479 return priv->msg_enable;
480}
481
482static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
483{
484 struct bcmgenet_priv *priv = netdev_priv(dev);
485
486 priv->msg_enable = level;
487}
488
489/* standard ethtool support functions. */
490enum bcmgenet_stat_type {
491 BCMGENET_STAT_NETDEV = -1,
492 BCMGENET_STAT_MIB_RX,
493 BCMGENET_STAT_MIB_TX,
494 BCMGENET_STAT_RUNT,
495 BCMGENET_STAT_MISC,
496};
497
498struct bcmgenet_stats {
499 char stat_string[ETH_GSTRING_LEN];
500 int stat_sizeof;
501 int stat_offset;
502 enum bcmgenet_stat_type type;
503 /* reg offset from UMAC base for misc counters */
504 u16 reg_offset;
505};
506
507#define STAT_NETDEV(m) { \
508 .stat_string = __stringify(m), \
509 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
510 .stat_offset = offsetof(struct net_device_stats, m), \
511 .type = BCMGENET_STAT_NETDEV, \
512}
513
514#define STAT_GENET_MIB(str, m, _type) { \
515 .stat_string = str, \
516 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
517 .stat_offset = offsetof(struct bcmgenet_priv, m), \
518 .type = _type, \
519}
520
521#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
522#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
523#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
524
525#define STAT_GENET_MISC(str, m, offset) { \
526 .stat_string = str, \
527 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
528 .stat_offset = offsetof(struct bcmgenet_priv, m), \
529 .type = BCMGENET_STAT_MISC, \
530 .reg_offset = offset, \
531}
532
533
534/* There is a 0xC gap between the end of RX and beginning of TX stats and then
535 * between the end of TX stats and the beginning of the RX RUNT
536 */
537#define BCMGENET_STAT_OFFSET 0xc
538
539/* Hardware counters must be kept in sync because the order/offset
540 * is important here (order in structure declaration = order in hardware)
541 */
542static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
543 /* general stats */
544 STAT_NETDEV(rx_packets),
545 STAT_NETDEV(tx_packets),
546 STAT_NETDEV(rx_bytes),
547 STAT_NETDEV(tx_bytes),
548 STAT_NETDEV(rx_errors),
549 STAT_NETDEV(tx_errors),
550 STAT_NETDEV(rx_dropped),
551 STAT_NETDEV(tx_dropped),
552 STAT_NETDEV(multicast),
553 /* UniMAC RSV counters */
554 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
555 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
556 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
557 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
558 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
559 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
560 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
561 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
562 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
563 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
564 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
565 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
566 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
567 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
568 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
569 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
570 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
571 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
572 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
573 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
574 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
575 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
576 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
577 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
578 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
579 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
580 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
581 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
582 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
583 /* UniMAC TSV counters */
584 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
585 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
586 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
587 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
588 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
589 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
590 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
591 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
592 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
593 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
594 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
595 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
596 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
597 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
598 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
599 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
600 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
601 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
602 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
603 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
604 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
605 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
606 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
607 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
608 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
609 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
610 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
611 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
612 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
613 /* UniMAC RUNT counters */
614 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
615 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
616 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
617 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
618 /* Misc UniMAC counters */
619 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
620 UMAC_RBUF_OVFL_CNT),
621 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
622 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
623};
624
625#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
626
627static void bcmgenet_get_drvinfo(struct net_device *dev,
628 struct ethtool_drvinfo *info)
629{
630 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
631 strlcpy(info->version, "v2.0", sizeof(info->version));
632 info->n_stats = BCMGENET_STATS_LEN;
633
634}
635
636static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
637{
638 switch (string_set) {
639 case ETH_SS_STATS:
640 return BCMGENET_STATS_LEN;
641 default:
642 return -EOPNOTSUPP;
643 }
644}
645
646static void bcmgenet_get_strings(struct net_device *dev,
647 u32 stringset, u8 *data)
648{
649 int i;
650
651 switch (stringset) {
652 case ETH_SS_STATS:
653 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
654 memcpy(data + i * ETH_GSTRING_LEN,
655 bcmgenet_gstrings_stats[i].stat_string,
656 ETH_GSTRING_LEN);
657 }
658 break;
659 }
660}
661
662static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
663{
664 int i, j = 0;
665
666 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
667 const struct bcmgenet_stats *s;
668 u8 offset = 0;
669 u32 val = 0;
670 char *p;
671
672 s = &bcmgenet_gstrings_stats[i];
673 switch (s->type) {
674 case BCMGENET_STAT_NETDEV:
675 continue;
676 case BCMGENET_STAT_MIB_RX:
677 case BCMGENET_STAT_MIB_TX:
678 case BCMGENET_STAT_RUNT:
679 if (s->type != BCMGENET_STAT_MIB_RX)
680 offset = BCMGENET_STAT_OFFSET;
681 val = bcmgenet_umac_readl(priv, UMAC_MIB_START +
682 j + offset);
683 break;
684 case BCMGENET_STAT_MISC:
685 val = bcmgenet_umac_readl(priv, s->reg_offset);
686 /* clear if overflowed */
687 if (val == ~0)
688 bcmgenet_umac_writel(priv, 0, s->reg_offset);
689 break;
690 }
691
692 j += s->stat_sizeof;
693 p = (char *)priv + s->stat_offset;
694 *(u32 *)p = val;
695 }
696}
697
698static void bcmgenet_get_ethtool_stats(struct net_device *dev,
699 struct ethtool_stats *stats,
700 u64 *data)
701{
702 struct bcmgenet_priv *priv = netdev_priv(dev);
703 int i;
704
705 if (netif_running(dev))
706 bcmgenet_update_mib_counters(priv);
707
708 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
709 const struct bcmgenet_stats *s;
710 char *p;
711
712 s = &bcmgenet_gstrings_stats[i];
713 if (s->type == BCMGENET_STAT_NETDEV)
714 p = (char *)&dev->stats;
715 else
716 p = (char *)priv;
717 p += s->stat_offset;
718 data[i] = *(u32 *)p;
719 }
720}
721
722/* standard ethtool support functions. */
723static struct ethtool_ops bcmgenet_ethtool_ops = {
724 .get_strings = bcmgenet_get_strings,
725 .get_sset_count = bcmgenet_get_sset_count,
726 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
727 .get_settings = bcmgenet_get_settings,
728 .set_settings = bcmgenet_set_settings,
729 .get_drvinfo = bcmgenet_get_drvinfo,
730 .get_link = ethtool_op_get_link,
731 .get_msglevel = bcmgenet_get_msglevel,
732 .set_msglevel = bcmgenet_set_msglevel,
733};
734
735/* Power down the unimac, based on mode. */
736static void bcmgenet_power_down(struct bcmgenet_priv *priv,
737 enum bcmgenet_power_mode mode)
738{
739 u32 reg;
740
741 switch (mode) {
742 case GENET_POWER_CABLE_SENSE:
80d8e96d 743 phy_detach(priv->phydev);
1c1008c7
FF		 744 break;
745
746 case GENET_POWER_PASSIVE:
747 /* Power down LED */
748 bcmgenet_mii_reset(priv->dev);
749 if (priv->hw_params->flags & GENET_HAS_EXT) {
750 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
751 reg |= (EXT_PWR_DOWN_PHY |
752 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
753 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
754 }
755 break;
756 default:
757 break;
758 }
759}
760
761static void bcmgenet_power_up(struct bcmgenet_priv *priv,
762 enum bcmgenet_power_mode mode)
763{
764 u32 reg;
765
766 if (!(priv->hw_params->flags & GENET_HAS_EXT))
767 return;
768
769 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
770
771 switch (mode) {
772 case GENET_POWER_PASSIVE:
773 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
774 EXT_PWR_DOWN_BIAS);
775 /* fallthrough */
776 case GENET_POWER_CABLE_SENSE:
777 /* enable APD */
778 reg |= EXT_PWR_DN_EN_LD;
779 break;
780 default:
781 break;
782 }
783
784 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
785 bcmgenet_mii_reset(priv->dev);
786}
787
788/* ioctl handle special commands that are not present in ethtool. */
789static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
790{
791 struct bcmgenet_priv *priv = netdev_priv(dev);
792 int val = 0;
793
794 if (!netif_running(dev))
795 return -EINVAL;
796
797 switch (cmd) {
798 case SIOCGMIIPHY:
799 case SIOCGMIIREG:
800 case SIOCSMIIREG:
801 if (!priv->phydev)
802 val = -ENODEV;
803 else
804 val = phy_mii_ioctl(priv->phydev, rq, cmd);
805 break;
806
807 default:
808 val = -EINVAL;
809 break;
810 }
811
812 return val;
813}
814
815static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
816 struct bcmgenet_tx_ring *ring)
817{
818 struct enet_cb *tx_cb_ptr;
819
820 tx_cb_ptr = ring->cbs;
821 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
822 tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
823 /* Advancing local write pointer */
824 if (ring->write_ptr == ring->end_ptr)
825 ring->write_ptr = ring->cb_ptr;
826 else
827 ring->write_ptr++;
828
829 return tx_cb_ptr;
830}
831
832/* Simple helper to free a control block's resources */
833static void bcmgenet_free_cb(struct enet_cb *cb)
834{
835 dev_kfree_skb_any(cb->skb);
836 cb->skb = NULL;
837 dma_unmap_addr_set(cb, dma_addr, 0);
838}
839
840static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
841 struct bcmgenet_tx_ring *ring)
842{
843 bcmgenet_intrl2_0_writel(priv,
844 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
845 INTRL2_CPU_MASK_SET);
846}
847
848static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
849 struct bcmgenet_tx_ring *ring)
850{
851 bcmgenet_intrl2_0_writel(priv,
852 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
853 INTRL2_CPU_MASK_CLEAR);
854}
855
856static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
857 struct bcmgenet_tx_ring *ring)
858{
859 bcmgenet_intrl2_1_writel(priv,
860 (1 << ring->index), INTRL2_CPU_MASK_CLEAR);
861 priv->int1_mask &= ~(1 << ring->index);
862}
863
864static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
865 struct bcmgenet_tx_ring *ring)
866{
867 bcmgenet_intrl2_1_writel(priv,
868 (1 << ring->index), INTRL2_CPU_MASK_SET);
869 priv->int1_mask |= (1 << ring->index);
870}
871
872/* Unlocked version of the reclaim routine */
873static void __bcmgenet_tx_reclaim(struct net_device *dev,
874 struct bcmgenet_tx_ring *ring)
875{
876 struct bcmgenet_priv *priv = netdev_priv(dev);
877 int last_tx_cn, last_c_index, num_tx_bds;
878 struct enet_cb *tx_cb_ptr;
b2cde2cc 879 struct netdev_queue *txq;
1c1008c7
FF		 880 unsigned int c_index;
881
882 /* Compute how many buffers are transmited since last xmit call */
883 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
b2cde2cc 884 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 885
886 last_c_index = ring->c_index;
887 num_tx_bds = ring->size;
888
889 c_index &= (num_tx_bds - 1);
890
891 if (c_index >= last_c_index)
892 last_tx_cn = c_index - last_c_index;
893 else
894 last_tx_cn = num_tx_bds - last_c_index + c_index;
895
896 netif_dbg(priv, tx_done, dev,
897 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
898 __func__, ring->index,
899 c_index, last_tx_cn, last_c_index);
900
901 /* Reclaim transmitted buffers */
902 while (last_tx_cn-- > 0) {
903 tx_cb_ptr = ring->cbs + last_c_index;
904 if (tx_cb_ptr->skb) {
905 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
906 dma_unmap_single(&dev->dev,
907 dma_unmap_addr(tx_cb_ptr, dma_addr),
908 tx_cb_ptr->skb->len,
909 DMA_TO_DEVICE);
910 bcmgenet_free_cb(tx_cb_ptr);
911 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
912 dev->stats.tx_bytes +=
913 dma_unmap_len(tx_cb_ptr, dma_len);
914 dma_unmap_page(&dev->dev,
915 dma_unmap_addr(tx_cb_ptr, dma_addr),
916 dma_unmap_len(tx_cb_ptr, dma_len),
917 DMA_TO_DEVICE);
918 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
919 }
920 dev->stats.tx_packets++;
921 ring->free_bds += 1;
922
923 last_c_index++;
924 last_c_index &= (num_tx_bds - 1);
925 }
926
927 if (ring->free_bds > (MAX_SKB_FRAGS + 1))
928 ring->int_disable(priv, ring);
929
b2cde2cc
FF		 930 if (netif_tx_queue_stopped(txq))
931 netif_tx_wake_queue(txq);
1c1008c7
FF		 932
933 ring->c_index = c_index;
934}
935
936static void bcmgenet_tx_reclaim(struct net_device *dev,
937 struct bcmgenet_tx_ring *ring)
938{
939 unsigned long flags;
940
941 spin_lock_irqsave(&ring->lock, flags);
942 __bcmgenet_tx_reclaim(dev, ring);
943 spin_unlock_irqrestore(&ring->lock, flags);
944}
945
946static void bcmgenet_tx_reclaim_all(struct net_device *dev)
947{
948 struct bcmgenet_priv *priv = netdev_priv(dev);
949 int i;
950
951 if (netif_is_multiqueue(dev)) {
952 for (i = 0; i < priv->hw_params->tx_queues; i++)
953 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
954 }
955
956 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
957}
958
959/* Transmits a single SKB (either head of a fragment or a single SKB)
960 * caller must hold priv->lock
961 */
962static int bcmgenet_xmit_single(struct net_device *dev,
963 struct sk_buff *skb,
964 u16 dma_desc_flags,
965 struct bcmgenet_tx_ring *ring)
966{
967 struct bcmgenet_priv *priv = netdev_priv(dev);
968 struct device *kdev = &priv->pdev->dev;
969 struct enet_cb *tx_cb_ptr;
970 unsigned int skb_len;
971 dma_addr_t mapping;
972 u32 length_status;
973 int ret;
974
975 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
976
977 if (unlikely(!tx_cb_ptr))
978 BUG();
979
980 tx_cb_ptr->skb = skb;
981
982 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
983
984 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
985 ret = dma_mapping_error(kdev, mapping);
986 if (ret) {
987 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
988 dev_kfree_skb(skb);
989 return ret;
990 }
991
992 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
993 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
994 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
995 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
996 DMA_TX_APPEND_CRC;
997
998 if (skb->ip_summed == CHECKSUM_PARTIAL)
999 length_status |= DMA_TX_DO_CSUM;
1000
1001 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1002
1003 /* Decrement total BD count and advance our write pointer */
1004 ring->free_bds -= 1;
1005 ring->prod_index += 1;
1006 ring->prod_index &= DMA_P_INDEX_MASK;
1007
1008 return 0;
1009}
1010
1011/* Transmit a SKB fragement */
1012static int bcmgenet_xmit_frag(struct net_device *dev,
1013 skb_frag_t *frag,
1014 u16 dma_desc_flags,
1015 struct bcmgenet_tx_ring *ring)
1016{
1017 struct bcmgenet_priv *priv = netdev_priv(dev);
1018 struct device *kdev = &priv->pdev->dev;
1019 struct enet_cb *tx_cb_ptr;
1020 dma_addr_t mapping;
1021 int ret;
1022
1023 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1024
1025 if (unlikely(!tx_cb_ptr))
1026 BUG();
1027 tx_cb_ptr->skb = NULL;
1028
1029 mapping = skb_frag_dma_map(kdev, frag, 0,
1030 skb_frag_size(frag), DMA_TO_DEVICE);
1031 ret = dma_mapping_error(kdev, mapping);
1032 if (ret) {
1033 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1034 __func__);
1035 return ret;
1036 }
1037
1038 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1039 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1040
1041 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1042 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1043 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1044
1045
1046 ring->free_bds -= 1;
1047 ring->prod_index += 1;
1048 ring->prod_index &= DMA_P_INDEX_MASK;
1049
1050 return 0;
1051}
1052
1053/* Reallocate the SKB to put enough headroom in front of it and insert
1054 * the transmit checksum offsets in the descriptors
1055 */
1056static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb)
1057{
1058 struct status_64 *status = NULL;
1059 struct sk_buff *new_skb;
1060 u16 offset;
1061 u8 ip_proto;
1062 u16 ip_ver;
1063 u32 tx_csum_info;
1064
1065 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1066 /* If 64 byte status block enabled, must make sure skb has
1067 * enough headroom for us to insert 64B status block.
1068 */
1069 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1070 dev_kfree_skb(skb);
1071 if (!new_skb) {
1072 dev->stats.tx_errors++;
1073 dev->stats.tx_dropped++;
1074 return -ENOMEM;
1075 }
1076 skb = new_skb;
1077 }
1078
1079 skb_push(skb, sizeof(*status));
1080 status = (struct status_64 *)skb->data;
1081
1082 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1083 ip_ver = htons(skb->protocol);
1084 switch (ip_ver) {
1085 case ETH_P_IP:
1086 ip_proto = ip_hdr(skb)->protocol;
1087 break;
1088 case ETH_P_IPV6:
1089 ip_proto = ipv6_hdr(skb)->nexthdr;
1090 break;
1091 default:
1092 return 0;
1093 }
1094
1095 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1096 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1097 (offset + skb->csum_offset);
1098
1099 /* Set the length valid bit for TCP and UDP and just set
1100 * the special UDP flag for IPv4, else just set to 0.
1101 */
1102 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1103 tx_csum_info |= STATUS_TX_CSUM_LV;
1104 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1105 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1106 } else
1107 tx_csum_info = 0;
1108
1109 status->tx_csum_info = tx_csum_info;
1110 }
1111
1112 return 0;
1113}
1114
1115static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1116{
1117 struct bcmgenet_priv *priv = netdev_priv(dev);
1118 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1119 struct netdev_queue *txq;
1c1008c7
FF		 1120 unsigned long flags = 0;
1121 int nr_frags, index;
1122 u16 dma_desc_flags;
1123 int ret;
1124 int i;
1125
1126 index = skb_get_queue_mapping(skb);
1127 /* Mapping strategy:
1128 * queue_mapping = 0, unclassified, packet xmited through ring16
1129 * queue_mapping = 1, goes to ring 0. (highest priority queue
1130 * queue_mapping = 2, goes to ring 1.
1131 * queue_mapping = 3, goes to ring 2.
1132 * queue_mapping = 4, goes to ring 3.
1133 */
1134 if (index == 0)
1135 index = DESC_INDEX;
1136 else
1137 index -= 1;
1138
1c1008c7
FF		 1139 nr_frags = skb_shinfo(skb)->nr_frags;
1140 ring = &priv->tx_rings[index];
b2cde2cc 1141 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1142
1143 spin_lock_irqsave(&ring->lock, flags);
1144 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1145 netif_tx_stop_queue(txq);
1c1008c7
FF		 1146 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1147 __func__, index, ring->queue);
1148 ret = NETDEV_TX_BUSY;
1149 goto out;
1150 }
1151
1c1008c7
FF		 1152 /* set the SKB transmit checksum */
1153 if (priv->desc_64b_en) {
1154 ret = bcmgenet_put_tx_csum(dev, skb);
1155 if (ret) {
1156 ret = NETDEV_TX_OK;
1157 goto out;
1158 }
1159 }
1160
1161 dma_desc_flags = DMA_SOP;
1162 if (nr_frags == 0)
1163 dma_desc_flags |= DMA_EOP;
1164
1165 /* Transmit single SKB or head of fragment list */
1166 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1167 if (ret) {
1168 ret = NETDEV_TX_OK;
1169 goto out;
1170 }
1171
1172 /* xmit fragment */
1173 for (i = 0; i < nr_frags; i++) {
1174 ret = bcmgenet_xmit_frag(dev,
1175 &skb_shinfo(skb)->frags[i],
1176 (i == nr_frags - 1) ? DMA_EOP : 0, ring);
1177 if (ret) {
1178 ret = NETDEV_TX_OK;
1179 goto out;
1180 }
1181 }
1182
d03825fb
FF		 1183 skb_tx_timestamp(skb);
1184
1c1008c7
FF		 1185 /* we kept a software copy of how much we should advance the TDMA
1186 * producer index, now write it down to the hardware
1187 */
1188 bcmgenet_tdma_ring_writel(priv, ring->index,
1189 ring->prod_index, TDMA_PROD_INDEX);
1190
1191 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
b2cde2cc 1192 netif_tx_stop_queue(txq);
1c1008c7
FF		 1193 ring->int_enable(priv, ring);
1194 }
1195
1196out:
1197 spin_unlock_irqrestore(&ring->lock, flags);
1198
1199 return ret;
1200}
1201
1202
1203static int bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1204 struct enet_cb *cb)
1205{
1206 struct device *kdev = &priv->pdev->dev;
1207 struct sk_buff *skb;
1208 dma_addr_t mapping;
1209 int ret;
1210
1211 skb = netdev_alloc_skb(priv->dev,
1212 priv->rx_buf_len + SKB_ALIGNMENT);
1213 if (!skb)
1214 return -ENOMEM;
1215
1216 /* a caller did not release this control block */
1217 WARN_ON(cb->skb != NULL);
1218 cb->skb = skb;
1219 mapping = dma_map_single(kdev, skb->data,
1220 priv->rx_buf_len, DMA_FROM_DEVICE);
1221 ret = dma_mapping_error(kdev, mapping);
1222 if (ret) {
1223 bcmgenet_free_cb(cb);
1224 netif_err(priv, rx_err, priv->dev,
1225 "%s DMA map failed\n", __func__);
1226 return ret;
1227 }
1228
1229 dma_unmap_addr_set(cb, dma_addr, mapping);
1230 /* assign packet, prepare descriptor, and advance pointer */
1231
1232 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1233
1234 /* turn on the newly assigned BD for DMA to use */
1235 priv->rx_bd_assign_index++;
1236 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1237
1238 priv->rx_bd_assign_ptr = priv->rx_bds +
1239 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1240
1241 return 0;
1242}
1243
1244/* bcmgenet_desc_rx - descriptor based rx process.
1245 * this could be called from bottom half, or from NAPI polling method.
1246 */
1247static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1248 unsigned int budget)
1249{
1250 struct net_device *dev = priv->dev;
1251 struct enet_cb *cb;
1252 struct sk_buff *skb;
1253 u32 dma_length_status;
1254 unsigned long dma_flag;
1255 int len, err;
1256 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1257 unsigned int p_index;
1258 unsigned int chksum_ok = 0;
1259
1260 p_index = bcmgenet_rdma_ring_readl(priv,
1261 DESC_INDEX, RDMA_PROD_INDEX);
1262 p_index &= DMA_P_INDEX_MASK;
1263
1264 if (p_index < priv->rx_c_index)
1265 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1266 priv->rx_c_index + p_index;
1267 else
1268 rxpkttoprocess = p_index - priv->rx_c_index;
1269
1270 netif_dbg(priv, rx_status, dev,
1271 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1272
1273 while ((rxpktprocessed < rxpkttoprocess) &&
1274 (rxpktprocessed < budget)) {
1275
1276 /* Unmap the packet contents such that we can use the
1277 * RSV from the 64 bytes descriptor when enabled and save
1278 * a 32-bits register read
1279 */
1280 cb = &priv->rx_cbs[priv->rx_read_ptr];
1281 skb = cb->skb;
1282 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1283 priv->rx_buf_len, DMA_FROM_DEVICE);
1284
1285 if (!priv->desc_64b_en) {
1286 dma_length_status = dmadesc_get_length_status(priv,
1287 priv->rx_bds +
1288 (priv->rx_read_ptr *
1289 DMA_DESC_SIZE));
1290 } else {
1291 struct status_64 *status;
1292 status = (struct status_64 *)skb->data;
1293 dma_length_status = status->length_status;
1294 }
1295
1296 /* DMA flags and length are still valid no matter how
1297 * we got the Receive Status Vector (64B RSB or register)
1298 */
1299 dma_flag = dma_length_status & 0xffff;
1300 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1301
1302 netif_dbg(priv, rx_status, dev,
1303 "%s: p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1304 __func__, p_index, priv->rx_c_index, priv->rx_read_ptr,
1305 dma_length_status);
1306
1307 rxpktprocessed++;
1308
1309 priv->rx_read_ptr++;
1310 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1311
1312 /* out of memory, just drop packets at the hardware level */
1313 if (unlikely(!skb)) {
1314 dev->stats.rx_dropped++;
1315 dev->stats.rx_errors++;
1316 goto refill;
1317 }
1318
1319 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1320 netif_err(priv, rx_status, dev,
1321 "Droping fragmented packet!\n");
1322 dev->stats.rx_dropped++;
1323 dev->stats.rx_errors++;
1324 dev_kfree_skb_any(cb->skb);
1325 cb->skb = NULL;
1326 goto refill;
1327 }
1328 /* report errors */
1329 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1330 DMA_RX_OV |
1331 DMA_RX_NO |
1332 DMA_RX_LG |
1333 DMA_RX_RXER))) {
1334 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1335 (unsigned int)dma_flag);
1336 if (dma_flag & DMA_RX_CRC_ERROR)
1337 dev->stats.rx_crc_errors++;
1338 if (dma_flag & DMA_RX_OV)
1339 dev->stats.rx_over_errors++;
1340 if (dma_flag & DMA_RX_NO)
1341 dev->stats.rx_frame_errors++;
1342 if (dma_flag & DMA_RX_LG)
1343 dev->stats.rx_length_errors++;
1344 dev->stats.rx_dropped++;
1345 dev->stats.rx_errors++;
1346
1347 /* discard the packet and advance consumer index.*/
1348 dev_kfree_skb_any(cb->skb);
1349 cb->skb = NULL;
1350 goto refill;
1351 } /* error packet */
1352
1353 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1354 priv->desc_rxchk_en;
1355
1356 skb_put(skb, len);
1357 if (priv->desc_64b_en) {
1358 skb_pull(skb, 64);
1359 len -= 64;
1360 }
1361
1362 if (likely(chksum_ok))
1363 skb->ip_summed = CHECKSUM_UNNECESSARY;
1364
1365 /* remove hardware 2bytes added for IP alignment */
1366 skb_pull(skb, 2);
1367 len -= 2;
1368
1369 if (priv->crc_fwd_en) {
1370 skb_trim(skb, len - ETH_FCS_LEN);
1371 len -= ETH_FCS_LEN;
1372 }
1373
1374 /*Finish setting up the received SKB and send it to the kernel*/
1375 skb->protocol = eth_type_trans(skb, priv->dev);
1376 dev->stats.rx_packets++;
1377 dev->stats.rx_bytes += len;
1378 if (dma_flag & DMA_RX_MULT)
1379 dev->stats.multicast++;
1380
1381 /* Notify kernel */
1382 napi_gro_receive(&priv->napi, skb);
1383 cb->skb = NULL;
1384 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1385
1386 /* refill RX path on the current control block */
1387refill:
1388 err = bcmgenet_rx_refill(priv, cb);
1389 if (err)
1390 netif_err(priv, rx_err, dev, "Rx refill failed\n");
1391 }
1392
1393 return rxpktprocessed;
1394}
1395
1396/* Assign skb to RX DMA descriptor. */
1397static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1398{
1399 struct enet_cb *cb;
1400 int ret = 0;
1401 int i;
1402
1403 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1404
1405 /* loop here for each buffer needing assign */
1406 for (i = 0; i < priv->num_rx_bds; i++) {
1407 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1408 if (cb->skb)
1409 continue;
1410
1c1008c7
FF		 1411 ret = bcmgenet_rx_refill(priv, cb);
1412 if (ret)
1413 break;
1414
1415 }
1416
1417 return ret;
1418}
1419
1420static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1421{
1422 struct enet_cb *cb;
1423 int i;
1424
1425 for (i = 0; i < priv->num_rx_bds; i++) {
1426 cb = &priv->rx_cbs[i];
1427
1428 if (dma_unmap_addr(cb, dma_addr)) {
1429 dma_unmap_single(&priv->dev->dev,
1430 dma_unmap_addr(cb, dma_addr),
1431 priv->rx_buf_len, DMA_FROM_DEVICE);
1432 dma_unmap_addr_set(cb, dma_addr, 0);
1433 }
1434
1435 if (cb->skb)
1436 bcmgenet_free_cb(cb);
1437 }
1438}
1439
e29585b8
FF		 1440static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask,
1441 bool enable)
1442{
1443 u32 reg;
1444
1445 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1446 if (enable)
1447 reg |= mask;
1448 else
1449 reg &= ~mask;
1450 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1451
1452 /* UniMAC stops on a packet boundary, wait for a full-size packet
1453 * to be processed
1454 */
1455 if (enable == 0)
1456 usleep_range(1000, 2000);
1457}
1458
1c1008c7
FF		 1459static int reset_umac(struct bcmgenet_priv *priv)
1460{
1461 struct device *kdev = &priv->pdev->dev;
1462 unsigned int timeout = 0;
1463 u32 reg;
1464
1465 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1466 bcmgenet_rbuf_ctrl_set(priv, 0);
1467 udelay(10);
1468
1469 /* disable MAC while updating its registers */
1470 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1471
1472 /* issue soft reset, wait for it to complete */
1473 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1474 while (timeout++ < 1000) {
1475 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1476 if (!(reg & CMD_SW_RESET))
1477 return 0;
1478
1479 udelay(1);
1480 }
1481
1482 if (timeout == 1000) {
1483 dev_err(kdev,
1484 "timeout waiting for MAC to come out of resetn\n");
1485 return -ETIMEDOUT;
1486 }
1487
1488 return 0;
1489}
1490
1491static int init_umac(struct bcmgenet_priv *priv)
1492{
1493 struct device *kdev = &priv->pdev->dev;
1494 int ret;
1495 u32 reg, cpu_mask_clear;
1496
1497 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1498
1499 ret = reset_umac(priv);
1500 if (ret)
1501 return ret;
1502
1503 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1504 /* clear tx/rx counter */
1505 bcmgenet_umac_writel(priv,
1506 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, UMAC_MIB_CTRL);
1507 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1508
1509 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1510
1511 /* init rx registers, enable ip header optimization */
1512 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1513 reg |= RBUF_ALIGN_2B;
1514 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1515
1516 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1517 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1518
1519 /* Mask all interrupts.*/
1520 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1521 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1522 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1523
1524 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1525
1526 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1527
1528 /* Monitor cable plug/unpluged event for internal PHY */
1529 if (phy_is_internal(priv->phydev))
1530 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1531 else if (priv->ext_phy)
1532 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1533 else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1534 reg = bcmgenet_bp_mc_get(priv);
1535 reg |= BIT(priv->hw_params->bp_in_en_shift);
1536
1537 /* bp_mask: back pressure mask */
1538 if (netif_is_multiqueue(priv->dev))
1539 reg |= priv->hw_params->bp_in_mask;
1540 else
1541 reg &= ~priv->hw_params->bp_in_mask;
1542 bcmgenet_bp_mc_set(priv, reg);
1543 }
1544
1545 /* Enable MDIO interrupts on GENET v3+ */
1546 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1547 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1548
1549 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear,
1550 INTRL2_CPU_MASK_CLEAR);
1551
1552 /* Enable rx/tx engine.*/
1553 dev_dbg(kdev, "done init umac\n");
1554
1555 return 0;
1556}
1557
1558/* Initialize all house-keeping variables for a TX ring, along
1559 * with corresponding hardware registers
1560 */
1561static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1562 unsigned int index, unsigned int size,
1563 unsigned int write_ptr, unsigned int end_ptr)
1564{
1565 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1566 u32 words_per_bd = WORDS_PER_BD(priv);
1567 u32 flow_period_val = 0;
1568 unsigned int first_bd;
1569
1570 spin_lock_init(&ring->lock);
1571 ring->index = index;
1572 if (index == DESC_INDEX) {
1573 ring->queue = 0;
1574 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1575 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1576 } else {
1577 ring->queue = index + 1;
1578 ring->int_enable = bcmgenet_tx_ring_int_enable;
1579 ring->int_disable = bcmgenet_tx_ring_int_disable;
1580 }
1581 ring->cbs = priv->tx_cbs + write_ptr;
1582 ring->size = size;
1583 ring->c_index = 0;
1584 ring->free_bds = size;
1585 ring->write_ptr = write_ptr;
1586 ring->cb_ptr = write_ptr;
1587 ring->end_ptr = end_ptr - 1;
1588 ring->prod_index = 0;
1589
1590 /* Set flow period for ring != 16 */
1591 if (index != DESC_INDEX)
1592 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1593
1594 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1595 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1596 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1597 /* Disable rate control for now */
1598 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1599 TDMA_FLOW_PERIOD);
1600 /* Unclassified traffic goes to ring 16 */
1601 bcmgenet_tdma_ring_writel(priv, index,
1602 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1603 DMA_RING_BUF_SIZE);
1604
1605 first_bd = write_ptr;
1606
1607 /* Set start and end address, read and write pointers */
1608 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1609 DMA_START_ADDR);
1610 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1611 TDMA_READ_PTR);
1612 bcmgenet_tdma_ring_writel(priv, index, first_bd,
1613 TDMA_WRITE_PTR);
1614 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1615 DMA_END_ADDR);
1616}
1617
1618/* Initialize a RDMA ring */
1619static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1620 unsigned int index, unsigned int size)
1621{
1622 u32 words_per_bd = WORDS_PER_BD(priv);
1623 int ret;
1624
1625 priv->num_rx_bds = TOTAL_DESC;
1626 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1627 priv->rx_bd_assign_ptr = priv->rx_bds;
1628 priv->rx_bd_assign_index = 0;
1629 priv->rx_c_index = 0;
1630 priv->rx_read_ptr = 0;
1631 priv->rx_cbs = kzalloc(priv->num_rx_bds * sizeof(struct enet_cb),
1632 GFP_KERNEL);
1633 if (!priv->rx_cbs)
1634 return -ENOMEM;
1635
1636 ret = bcmgenet_alloc_rx_buffers(priv);
1637 if (ret) {
1638 kfree(priv->rx_cbs);
1639 return ret;
1640 }
1641
1642 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1643 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1644 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1645 bcmgenet_rdma_ring_writel(priv, index,
1646 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1647 DMA_RING_BUF_SIZE);
1648 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1649 bcmgenet_rdma_ring_writel(priv, index,
1650 words_per_bd * size - 1, DMA_END_ADDR);
1651 bcmgenet_rdma_ring_writel(priv, index,
1652 (DMA_FC_THRESH_LO << DMA_XOFF_THRESHOLD_SHIFT) |
1653 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1654 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1655
1656 return ret;
1657}
1658
1659/* init multi xmit queues, only available for GENET2+
1660 * the queue is partitioned as follows:
1661 *
1662 * queue 0 - 3 is priority based, each one has 32 descriptors,
1663 * with queue 0 being the highest priority queue.
1664 *
1665 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1666 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1667 * descriptors.
1668 *
1669 * The transmit control block pool is then partitioned as following:
1670 * - tx_cbs[0...127] are for queue 16
1671 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1672 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1673 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1674 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1675 */
1676static void bcmgenet_init_multiq(struct net_device *dev)
1677{
1678 struct bcmgenet_priv *priv = netdev_priv(dev);
1679 unsigned int i, dma_enable;
1680 u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
1681
1682 if (!netif_is_multiqueue(dev)) {
1683 netdev_warn(dev, "called with non multi queue aware HW\n");
1684 return;
1685 }
1686
1687 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1688 dma_enable = dma_ctrl & DMA_EN;
1689 dma_ctrl &= ~DMA_EN;
1690 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1691
1692 /* Enable strict priority arbiter mode */
1693 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1694
1695 for (i = 0; i < priv->hw_params->tx_queues; i++) {
1696 /* first 64 tx_cbs are reserved for default tx queue
1697 * (ring 16)
1698 */
1699 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1700 i * priv->hw_params->bds_cnt,
1701 (i + 1) * priv->hw_params->bds_cnt);
1702
1703 /* Configure ring as decriptor ring and setup priority */
1704 ring_cfg |= 1 << i;
1705 dma_priority |= ((GENET_Q0_PRIORITY + i) <<
1706 (GENET_MAX_MQ_CNT + 1) * i);
1707 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1708 }
1709
1710 /* Enable rings */
1711 reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1712 reg |= ring_cfg;
1713 bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1714
1715 /* Use configured rings priority and set ring #16 priority */
1716 reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
1717 reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
1718 reg |= dma_priority;
1719 bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
1720
1721 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1722 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1723 reg |= dma_ctrl;
1724 if (dma_enable)
1725 reg |= DMA_EN;
1726 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1727}
1728
1729static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1730{
1731 int i;
1732
1733 /* disable DMA */
1734 bcmgenet_rdma_writel(priv, 0, DMA_CTRL);
1735 bcmgenet_tdma_writel(priv, 0, DMA_CTRL);
1736
1737 for (i = 0; i < priv->num_tx_bds; i++) {
1738 if (priv->tx_cbs[i].skb != NULL) {
1739 dev_kfree_skb(priv->tx_cbs[i].skb);
1740 priv->tx_cbs[i].skb = NULL;
1741 }
1742 }
1743
1744 bcmgenet_free_rx_buffers(priv);
1745 kfree(priv->rx_cbs);
1746 kfree(priv->tx_cbs);
1747}
1748
1749/* init_edma: Initialize DMA control register */
1750static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1751{
1752 int ret;
1753
1754 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1755
1756 /* by default, enable ring 16 (descriptor based) */
1757 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1758 if (ret) {
1759 netdev_err(priv->dev, "failed to initialize RX ring\n");
1760 return ret;
1761 }
1762
1763 /* init rDma */
1764 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1765
1766 /* Init tDma */
1767 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1768
1769 /* Initialize commont TX ring structures */
1770 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1771 priv->num_tx_bds = TOTAL_DESC;
1772 priv->tx_cbs = kzalloc(priv->num_tx_bds * sizeof(struct enet_cb),
1773 GFP_KERNEL);
1774 if (!priv->tx_cbs) {
1775 bcmgenet_fini_dma(priv);
1776 return -ENOMEM;
1777 }
1778
1779 /* initialize multi xmit queue */
1780 bcmgenet_init_multiq(priv->dev);
1781
1782 /* initialize special ring 16 */
1783 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1784 priv->hw_params->tx_queues * priv->hw_params->bds_cnt,
1785 TOTAL_DESC);
1786
1787 return 0;
1788}
1789
1790/* NAPI polling method*/
1791static int bcmgenet_poll(struct napi_struct *napi, int budget)
1792{
1793 struct bcmgenet_priv *priv = container_of(napi,
1794 struct bcmgenet_priv, napi);
1795 unsigned int work_done;
1796
1797 /* tx reclaim */
1798 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1799
1800 work_done = bcmgenet_desc_rx(priv, budget);
1801
1802 /* Advancing our consumer index*/
1803 priv->rx_c_index += work_done;
1804 priv->rx_c_index &= DMA_C_INDEX_MASK;
1805 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1806 priv->rx_c_index, RDMA_CONS_INDEX);
1807 if (work_done < budget) {
1808 napi_complete(napi);
1809 bcmgenet_intrl2_0_writel(priv,
1810 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_CLEAR);
1811 }
1812
1813 return work_done;
1814}
1815
1816/* Interrupt bottom half */
1817static void bcmgenet_irq_task(struct work_struct *work)
1818{
1819 struct bcmgenet_priv *priv = container_of(
1820 work, struct bcmgenet_priv, bcmgenet_irq_work);
1821
1822 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1823
1824 /* Link UP/DOWN event */
1825 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1826 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d
FF		 1827 phy_mac_interrupt(priv->phydev,
1828 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 1829 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
1830 }
1831}
1832
1833/* bcmgenet_isr1: interrupt handler for ring buffer. */
1834static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
1835{
1836 struct bcmgenet_priv *priv = dev_id;
1837 unsigned int index;
1838
1839 /* Save irq status for bottom-half processing. */
1840 priv->irq1_stat =
1841 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
1842 ~priv->int1_mask;
1843 /* clear inerrupts*/
1844 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
1845
1846 netif_dbg(priv, intr, priv->dev,
1847 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1848 /* Check the MBDONE interrupts.
1849 * packet is done, reclaim descriptors
1850 */
1851 if (priv->irq1_stat & 0x0000ffff) {
1852 index = 0;
1853 for (index = 0; index < 16; index++) {
1854 if (priv->irq1_stat & (1 << index))
1855 bcmgenet_tx_reclaim(priv->dev,
1856 &priv->tx_rings[index]);
1857 }
1858 }
1859 return IRQ_HANDLED;
1860}
1861
1862/* bcmgenet_isr0: Handle various interrupts. */
1863static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
1864{
1865 struct bcmgenet_priv *priv = dev_id;
1866
1867 /* Save irq status for bottom-half processing. */
1868 priv->irq0_stat =
1869 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1870 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1871 /* clear inerrupts*/
1872 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1873
1874 netif_dbg(priv, intr, priv->dev,
1875 "IRQ=0x%x\n", priv->irq0_stat);
1876
1877 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
1878 /* We use NAPI(software interrupt throttling, if
1879 * Rx Descriptor throttling is not used.
1880 * Disable interrupt, will be enabled in the poll method.
1881 */
1882 if (likely(napi_schedule_prep(&priv->napi))) {
1883 bcmgenet_intrl2_0_writel(priv,
1884 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_SET);
1885 __napi_schedule(&priv->napi);
1886 }
1887 }
1888 if (priv->irq0_stat &
1889 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
1890 /* Tx reclaim */
1891 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1892 }
1893 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
1894 UMAC_IRQ_PHY_DET_F |
1895 UMAC_IRQ_LINK_UP |
1896 UMAC_IRQ_LINK_DOWN |
1897 UMAC_IRQ_HFB_SM |
1898 UMAC_IRQ_HFB_MM |
1899 UMAC_IRQ_MPD_R)) {
1900 /* all other interested interrupts handled in bottom half */
1901 schedule_work(&priv->bcmgenet_irq_work);
1902 }
1903
1904 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1905 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1906 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1907 wake_up(&priv->wq);
1908 }
1909
1910 return IRQ_HANDLED;
1911}
1912
1913static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
1914{
1915 u32 reg;
1916
1917 reg = bcmgenet_rbuf_ctrl_get(priv);
1918 reg |= BIT(1);
1919 bcmgenet_rbuf_ctrl_set(priv, reg);
1920 udelay(10);
1921
1922 reg &= ~BIT(1);
1923 bcmgenet_rbuf_ctrl_set(priv, reg);
1924 udelay(10);
1925}
1926
1927static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
1928 unsigned char *addr)
1929{
1930 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1931 (addr[2] << 8) | addr[3], UMAC_MAC0);
1932 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1933}
1934
1935static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
1936{
1937 int ret;
1938
1939 /* From WOL-enabled suspend, switch to regular clock */
1940 clk_disable(priv->clk_wol);
1941 /* init umac registers to synchronize s/w with h/w */
1942 ret = init_umac(priv);
1943 if (ret)
1944 return ret;
1945
80d8e96d 1946 phy_init_hw(priv->phydev);
1c1008c7
FF		 1947 /* Speed settings must be restored */
1948 bcmgenet_mii_config(priv->dev);
1949
1950 return 0;
1951}
1952
1953/* Returns a reusable dma control register value */
1954static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
1955{
1956 u32 reg;
1957 u32 dma_ctrl;
1958
1959 /* disable DMA */
1960 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
1961 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1962 reg &= ~dma_ctrl;
1963 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1964
1965 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1966 reg &= ~dma_ctrl;
1967 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1968
1969 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
1970 udelay(10);
1971 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
1972
1973 return dma_ctrl;
1974}
1975
1976static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
1977{
1978 u32 reg;
1979
1980 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1981 reg |= dma_ctrl;
1982 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1983
1984 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1985 reg |= dma_ctrl;
1986 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1987}
1988
1989static int bcmgenet_open(struct net_device *dev)
1990{
1991 struct bcmgenet_priv *priv = netdev_priv(dev);
1992 unsigned long dma_ctrl;
1993 u32 reg;
1994 int ret;
1995
1996 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
1997
1998 /* Turn on the clock */
1999 if (!IS_ERR(priv->clk))
2000 clk_prepare_enable(priv->clk);
2001
2002 /* take MAC out of reset */
2003 bcmgenet_umac_reset(priv);
2004
2005 ret = init_umac(priv);
2006 if (ret)
2007 goto err_clk_disable;
2008
2009 /* disable ethernet MAC while updating its registers */
e29585b8 2010 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7
FF		 2011
2012 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2013
1c1008c7
FF		 2014 if (phy_is_internal(priv->phydev)) {
2015 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2016 reg |= EXT_ENERGY_DET_MASK;
2017 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2018 }
2019
2020 /* Disable RX/TX DMA and flush TX queues */
2021 dma_ctrl = bcmgenet_dma_disable(priv);
2022
2023 /* Reinitialize TDMA and RDMA and SW housekeeping */
2024 ret = bcmgenet_init_dma(priv);
2025 if (ret) {
2026 netdev_err(dev, "failed to initialize DMA\n");
2027 goto err_fini_dma;
2028 }
2029
2030 /* Always enable ring 16 - descriptor ring */
2031 bcmgenet_enable_dma(priv, dma_ctrl);
2032
2033 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2034 dev->name, priv);
2035 if (ret < 0) {
2036 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2037 goto err_fini_dma;
2038 }
2039
2040 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2041 dev->name, priv);
2042 if (ret < 0) {
2043 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2044 goto err_irq0;
2045 }
2046
2047 /* Start the network engine */
2048 napi_enable(&priv->napi);
2049
e29585b8 2050 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
1c1008c7
FF		 2051
2052 /* Make sure we reflect the value of CRC_CMD_FWD */
e29585b8 2053 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1c1008c7
FF		 2054 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2055
2056 device_set_wakeup_capable(&dev->dev, 1);
2057
2058 if (phy_is_internal(priv->phydev))
2059 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2060
2061 netif_tx_start_all_queues(dev);
2062
80d8e96d 2063 phy_start(priv->phydev);
1c1008c7
FF		 2064
2065 return 0;
2066
2067err_irq0:
2068 free_irq(priv->irq0, dev);
2069err_fini_dma:
2070 bcmgenet_fini_dma(priv);
2071err_clk_disable:
2072 if (!IS_ERR(priv->clk))
2073 clk_disable_unprepare(priv->clk);
2074 return ret;
2075}
2076
2077static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2078{
2079 int ret = 0;
2080 int timeout = 0;
2081 u32 reg;
2082
2083 /* Disable TDMA to stop add more frames in TX DMA */
2084 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2085 reg &= ~DMA_EN;
2086 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2087
2088 /* Check TDMA status register to confirm TDMA is disabled */
2089 while (timeout++ < DMA_TIMEOUT_VAL) {
2090 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2091 if (reg & DMA_DISABLED)
2092 break;
2093
2094 udelay(1);
2095 }
2096
2097 if (timeout == DMA_TIMEOUT_VAL) {
2098 netdev_warn(priv->dev,
2099 "Timed out while disabling TX DMA\n");
2100 ret = -ETIMEDOUT;
2101 }
2102
2103 /* Wait 10ms for packet drain in both tx and rx dma */
2104 usleep_range(10000, 20000);
2105
2106 /* Disable RDMA */
2107 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2108 reg &= ~DMA_EN;
2109 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2110
2111 timeout = 0;
2112 /* Check RDMA status register to confirm RDMA is disabled */
2113 while (timeout++ < DMA_TIMEOUT_VAL) {
2114 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2115 if (reg & DMA_DISABLED)
2116 break;
2117
2118 udelay(1);
2119 }
2120
2121 if (timeout == DMA_TIMEOUT_VAL) {
2122 netdev_warn(priv->dev,
2123 "Timed out while disabling RX DMA\n");
2124 ret = -ETIMEDOUT;
2125 }
2126
2127 return ret;
2128}
2129
2130static int bcmgenet_close(struct net_device *dev)
2131{
2132 struct bcmgenet_priv *priv = netdev_priv(dev);
2133 int ret;
1c1008c7
FF		 2134
2135 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2136
80d8e96d 2137 phy_stop(priv->phydev);
1c1008c7
FF		 2138
2139 /* Disable MAC receive */
e29585b8 2140 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7
FF		 2141
2142 netif_tx_stop_all_queues(dev);
2143
2144 ret = bcmgenet_dma_teardown(priv);
2145 if (ret)
2146 return ret;
2147
2148 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2149 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7
FF		 2150
2151 napi_disable(&priv->napi);
2152
2153 /* tx reclaim */
2154 bcmgenet_tx_reclaim_all(dev);
2155 bcmgenet_fini_dma(priv);
2156
2157 free_irq(priv->irq0, priv);
2158 free_irq(priv->irq1, priv);
2159
2160 /* Wait for pending work items to complete - we are stopping
2161 * the clock now. Since interrupts are disabled, no new work
2162 * will be scheduled.
2163 */
2164 cancel_work_sync(&priv->bcmgenet_irq_work);
2165
2166 if (phy_is_internal(priv->phydev))
2167 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2168
1c1008c7
FF		 2169 if (!IS_ERR(priv->clk))
2170 clk_disable_unprepare(priv->clk);
2171
2172 return 0;
2173}
2174
2175static void bcmgenet_timeout(struct net_device *dev)
2176{
2177 struct bcmgenet_priv *priv = netdev_priv(dev);
2178
2179 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2180
2181 dev->trans_start = jiffies;
2182
2183 dev->stats.tx_errors++;
2184
2185 netif_tx_wake_all_queues(dev);
2186}
2187
2188#define MAX_MC_COUNT 16
2189
2190static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2191 unsigned char *addr,
2192 int *i,
2193 int *mc)
2194{
2195 u32 reg;
2196
2197 bcmgenet_umac_writel(priv,
2198 addr[0] << 8 | addr[1], UMAC_MDF_ADDR + (*i * 4));
2199 bcmgenet_umac_writel(priv,
2200 addr[2] << 24 | addr[3] << 16 |
2201 addr[4] << 8 | addr[5],
2202 UMAC_MDF_ADDR + ((*i + 1) * 4));
2203 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2204 reg |= (1 << (MAX_MC_COUNT - *mc));
2205 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2206 *i += 2;
2207 (*mc)++;
2208}
2209
2210static void bcmgenet_set_rx_mode(struct net_device *dev)
2211{
2212 struct bcmgenet_priv *priv = netdev_priv(dev);
2213 struct netdev_hw_addr *ha;
2214 int i, mc;
2215 u32 reg;
2216
2217 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2218
2219 /* Promiscous mode */
2220 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2221 if (dev->flags & IFF_PROMISC) {
2222 reg |= CMD_PROMISC;
2223 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2224 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2225 return;
2226 } else {
2227 reg &= ~CMD_PROMISC;
2228 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2229 }
2230
2231 /* UniMac doesn't support ALLMULTI */
2232 if (dev->flags & IFF_ALLMULTI) {
2233 netdev_warn(dev, "ALLMULTI is not supported\n");
2234 return;
2235 }
2236
2237 /* update MDF filter */
2238 i = 0;
2239 mc = 0;
2240 /* Broadcast */
2241 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2242 /* my own address.*/
2243 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2244 /* Unicast list*/
2245 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2246 return;
2247
2248 if (!netdev_uc_empty(dev))
2249 netdev_for_each_uc_addr(ha, dev)
2250 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2251 /* Multicast */
2252 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2253 return;
2254
2255 netdev_for_each_mc_addr(ha, dev)
2256 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2257}
2258
2259/* Set the hardware MAC address. */
2260static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2261{
2262 struct sockaddr *addr = p;
2263
2264 /* Setting the MAC address at the hardware level is not possible
2265 * without disabling the UniMAC RX/TX enable bits.
2266 */
2267 if (netif_running(dev))
2268 return -EBUSY;
2269
2270 ether_addr_copy(dev->dev_addr, addr->sa_data);
2271
2272 return 0;
2273}
2274
1c1008c7
FF		 2275static const struct net_device_ops bcmgenet_netdev_ops = {
2276 .ndo_open = bcmgenet_open,
2277 .ndo_stop = bcmgenet_close,
2278 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2279 .ndo_tx_timeout = bcmgenet_timeout,
2280 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2281 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2282 .ndo_do_ioctl = bcmgenet_ioctl,
2283 .ndo_set_features = bcmgenet_set_features,
2284};
2285
2286/* Array of GENET hardware parameters/characteristics */
2287static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2288 [GENET_V1] = {
2289 .tx_queues = 0,
2290 .rx_queues = 0,
2291 .bds_cnt = 0,
2292 .bp_in_en_shift = 16,
2293 .bp_in_mask = 0xffff,
2294 .hfb_filter_cnt = 16,
2295 .qtag_mask = 0x1F,
2296 .hfb_offset = 0x1000,
2297 .rdma_offset = 0x2000,
2298 .tdma_offset = 0x3000,
2299 .words_per_bd = 2,
2300 },
2301 [GENET_V2] = {
2302 .tx_queues = 4,
2303 .rx_queues = 4,
2304 .bds_cnt = 32,
2305 .bp_in_en_shift = 16,
2306 .bp_in_mask = 0xffff,
2307 .hfb_filter_cnt = 16,
2308 .qtag_mask = 0x1F,
2309 .tbuf_offset = 0x0600,
2310 .hfb_offset = 0x1000,
2311 .hfb_reg_offset = 0x2000,
2312 .rdma_offset = 0x3000,
2313 .tdma_offset = 0x4000,
2314 .words_per_bd = 2,
2315 .flags = GENET_HAS_EXT,
2316 },
2317 [GENET_V3] = {
2318 .tx_queues = 4,
2319 .rx_queues = 4,
2320 .bds_cnt = 32,
2321 .bp_in_en_shift = 17,
2322 .bp_in_mask = 0x1ffff,
2323 .hfb_filter_cnt = 48,
2324 .qtag_mask = 0x3F,
2325 .tbuf_offset = 0x0600,
2326 .hfb_offset = 0x8000,
2327 .hfb_reg_offset = 0xfc00,
2328 .rdma_offset = 0x10000,
2329 .tdma_offset = 0x11000,
2330 .words_per_bd = 2,
2331 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2332 },
2333 [GENET_V4] = {
2334 .tx_queues = 4,
2335 .rx_queues = 4,
2336 .bds_cnt = 32,
2337 .bp_in_en_shift = 17,
2338 .bp_in_mask = 0x1ffff,
2339 .hfb_filter_cnt = 48,
2340 .qtag_mask = 0x3F,
2341 .tbuf_offset = 0x0600,
2342 .hfb_offset = 0x8000,
2343 .hfb_reg_offset = 0xfc00,
2344 .rdma_offset = 0x2000,
2345 .tdma_offset = 0x4000,
2346 .words_per_bd = 3,
2347 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2348 },
2349};
2350
2351/* Infer hardware parameters from the detected GENET version */
2352static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2353{
2354 struct bcmgenet_hw_params *params;
2355 u32 reg;
2356 u8 major;
2357
2358 if (GENET_IS_V4(priv)) {
2359 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2360 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2361 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2362 priv->version = GENET_V4;
2363 } else if (GENET_IS_V3(priv)) {
2364 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2365 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2366 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2367 priv->version = GENET_V3;
2368 } else if (GENET_IS_V2(priv)) {
2369 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2370 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2371 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2372 priv->version = GENET_V2;
2373 } else if (GENET_IS_V1(priv)) {
2374 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2375 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2376 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2377 priv->version = GENET_V1;
2378 }
2379
2380 /* enum genet_version starts at 1 */
2381 priv->hw_params = &bcmgenet_hw_params[priv->version];
2382 params = priv->hw_params;
2383
2384 /* Read GENET HW version */
2385 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2386 major = (reg >> 24 & 0x0f);
2387 if (major == 5)
2388 major = 4;
2389 else if (major == 0)
2390 major = 1;
2391 if (major != priv->version) {
2392 dev_err(&priv->pdev->dev,
2393 "GENET version mismatch, got: %d, configured for: %d\n",
2394 major, priv->version);
2395 }
2396
2397 /* Print the GENET core version */
2398 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2399 major, (reg >> 16) & 0x0f, reg & 0xffff);
2400
2401#ifdef CONFIG_PHYS_ADDR_T_64BIT
2402 if (!(params->flags & GENET_HAS_40BITS))
2403 pr_warn("GENET does not support 40-bits PA\n");
2404#endif
2405
2406 pr_debug("Configuration for version: %d\n"
2407 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2408 "BP << en: %2d, BP msk: 0x%05x\n"
2409 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2410 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2411 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2412 "Words/BD: %d\n",
2413 priv->version,
2414 params->tx_queues, params->rx_queues, params->bds_cnt,
2415 params->bp_in_en_shift, params->bp_in_mask,
2416 params->hfb_filter_cnt, params->qtag_mask,
2417 params->tbuf_offset, params->hfb_offset,
2418 params->hfb_reg_offset,
2419 params->rdma_offset, params->tdma_offset,
2420 params->words_per_bd);
2421}
2422
2423static const struct of_device_id bcmgenet_match[] = {
2424 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2425 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2426 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2427 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2428 { },
2429};
2430
2431static int bcmgenet_probe(struct platform_device *pdev)
2432{
2433 struct device_node *dn = pdev->dev.of_node;
2434 const struct of_device_id *of_id;
2435 struct bcmgenet_priv *priv;
2436 struct net_device *dev;
2437 const void *macaddr;
2438 struct resource *r;
2439 int err = -EIO;
2440
2441 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2442 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2443 if (!dev) {
2444 dev_err(&pdev->dev, "can't allocate net device\n");
2445 return -ENOMEM;
2446 }
2447
2448 of_id = of_match_node(bcmgenet_match, dn);
2449 if (!of_id)
2450 return -EINVAL;
2451
2452 priv = netdev_priv(dev);
2453 priv->irq0 = platform_get_irq(pdev, 0);
2454 priv->irq1 = platform_get_irq(pdev, 1);
2455 if (!priv->irq0 || !priv->irq1) {
2456 dev_err(&pdev->dev, "can't find IRQs\n");
2457 err = -EINVAL;
2458 goto err;
2459 }
2460
2461 macaddr = of_get_mac_address(dn);
2462 if (!macaddr) {
2463 dev_err(&pdev->dev, "can't find MAC address\n");
2464 err = -EINVAL;
2465 goto err;
2466 }
2467
2468 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2469 priv->base = devm_ioremap_resource(&pdev->dev, r);
2470 if (IS_ERR(priv->base)) {
2471 err = PTR_ERR(priv->base);
1c1008c7
FF		 2472 goto err;
2473 }
2474
2475 SET_NETDEV_DEV(dev, &pdev->dev);
2476 dev_set_drvdata(&pdev->dev, dev);
2477 ether_addr_copy(dev->dev_addr, macaddr);
2478 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2479 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2480 dev->netdev_ops = &bcmgenet_netdev_ops;
2481 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2482
2483 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2484
2485 /* Set hardware features */
2486 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2487 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2488
2489 /* Set the needed headroom to account for any possible
2490 * features enabling/disabling at runtime
2491 */
2492 dev->needed_headroom += 64;
2493
2494 netdev_boot_setup_check(dev);
2495
2496 priv->dev = dev;
2497 priv->pdev = pdev;
2498 priv->version = (enum bcmgenet_version)of_id->data;
2499
2500 bcmgenet_set_hw_params(priv);
2501
1c1008c7
FF		 2502 /* Mii wait queue */
2503 init_waitqueue_head(&priv->wq);
2504 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2505 priv->rx_buf_len = RX_BUF_LENGTH;
2506 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2507
2508 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2509 if (IS_ERR(priv->clk))
2510 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2511
2512 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2513 if (IS_ERR(priv->clk_wol))
2514 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2515
2516 if (!IS_ERR(priv->clk))
2517 clk_prepare_enable(priv->clk);
2518
2519 err = reset_umac(priv);
2520 if (err)
2521 goto err_clk_disable;
2522
2523 err = bcmgenet_mii_init(dev);
2524 if (err)
2525 goto err_clk_disable;
2526
2527 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2528 * just the ring 16 descriptor based TX
2529 */
2530 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2531 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2532
219575eb
FF		 2533 /* libphy will determine the link state */
2534 netif_carrier_off(dev);
2535
1c1008c7
FF		 2536 /* Turn off the main clock, WOL clock is handled separately */
2537 if (!IS_ERR(priv->clk))
2538 clk_disable_unprepare(priv->clk);
2539
0f50ce96
FF		 2540 err = register_netdev(dev);
2541 if (err)
2542 goto err;
2543
1c1008c7
FF		 2544 return err;
2545
2546err_clk_disable:
2547 if (!IS_ERR(priv->clk))
2548 clk_disable_unprepare(priv->clk);
2549err:
2550 free_netdev(dev);
2551 return err;
2552}
2553
2554static int bcmgenet_remove(struct platform_device *pdev)
2555{
2556 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2557
2558 dev_set_drvdata(&pdev->dev, NULL);
2559 unregister_netdev(priv->dev);
2560 bcmgenet_mii_exit(priv->dev);
2561 free_netdev(priv->dev);
2562
2563 return 0;
2564}
2565
2566
2567static struct platform_driver bcmgenet_driver = {
2568 .probe = bcmgenet_probe,
2569 .remove = bcmgenet_remove,
2570 .driver = {
2571 .name = "bcmgenet",
2572 .owner = THIS_MODULE,
2573 .of_match_table = bcmgenet_match,
2574 },
2575};
2576module_platform_driver(bcmgenet_driver);
2577
2578MODULE_AUTHOR("Broadcom Corporation");
2579MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2580MODULE_ALIAS("platform:bcmgenet");
2581MODULE_LICENSE("GPL");
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