[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmmii.c

/*
 * Broadcom GENET MDIO routines
 *
 * Copyright (c) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */


#include <linux/types.h>
#include <linux/delay.h>
#include <linux/wait.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/bitops.h>
#include <linux/netdevice.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/brcmphy.h>
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/platform_data/bcmgenet.h>

#include "bcmgenet.h"

/* read a value from the MII */
static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
{
	int ret;
	struct net_device *dev = bus->priv;
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg;

	bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
			     (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
	/* Start MDIO transaction*/
	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	reg |= MDIO_START_BUSY;
	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	wait_event_timeout(priv->wq,
			   !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
			   & MDIO_START_BUSY),
			   HZ / 100);
	ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);

	/* Some broken devices are known not to release the line during
	 * turn-around, e.g: Broadcom BCM53125 external switches, so check for
	 * that condition here and ignore the MDIO controller read failure
	 * indication.
	 */
	if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL))
		return -EIO;

	return ret & 0xffff;
}

/* write a value to the MII */
static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
			      int location, u16 val)
{
	struct net_device *dev = bus->priv;
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg;

	bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
			     (location << MDIO_REG_SHIFT) | (0xffff & val)),
			     UMAC_MDIO_CMD);
	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	reg |= MDIO_START_BUSY;
	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	wait_event_timeout(priv->wq,
			   !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
			   MDIO_START_BUSY),
			   HZ / 100);

	return 0;
}

/* setup netdev link state when PHY link status change and
 * update UMAC and RGMII block when link up
 */
void bcmgenet_mii_setup(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct phy_device *phydev = priv->phydev;
	u32 reg, cmd_bits = 0;
	bool status_changed = false;

	if (priv->old_link != phydev->link) {
		status_changed = true;
		priv->old_link = phydev->link;
	}

	if (phydev->link) {
		/* check speed/duplex/pause changes */
		if (priv->old_speed != phydev->speed) {
			status_changed = true;
			priv->old_speed = phydev->speed;
		}

		if (priv->old_duplex != phydev->duplex) {
			status_changed = true;
			priv->old_duplex = phydev->duplex;
		}

		if (priv->old_pause != phydev->pause) {
			status_changed = true;
			priv->old_pause = phydev->pause;
		}

		/* done if nothing has changed */
		if (!status_changed)
			return;

		/* speed */
		if (phydev->speed == SPEED_1000)
			cmd_bits = UMAC_SPEED_1000;
		else if (phydev->speed == SPEED_100)
			cmd_bits = UMAC_SPEED_100;
		else
			cmd_bits = UMAC_SPEED_10;
		cmd_bits <<= CMD_SPEED_SHIFT;

		/* duplex */
		if (phydev->duplex != DUPLEX_FULL)
			cmd_bits |= CMD_HD_EN;

		/* pause capability */
		if (!phydev->pause)
			cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;

		/*
		 * Program UMAC and RGMII block based on established
		 * link speed, duplex, and pause. The speed set in
		 * umac->cmd tell RGMII block which clock to use for
		 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
		 * Receive clock is provided by the PHY.
		 */
		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
		reg &= ~OOB_DISABLE;
		reg |= RGMII_LINK;
		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);

		reg = bcmgenet_umac_readl(priv, UMAC_CMD);
		reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
			       CMD_HD_EN |
			       CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
		reg |= cmd_bits;
		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
	} else {
		/* done if nothing has changed */
		if (!status_changed)
			return;

		/* needed for MoCA fixed PHY to reflect correct link status */
		netif_carrier_off(dev);
	}

	phy_print_status(phydev);
}


static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
					  struct fixed_phy_status *status)
{
	if (dev && dev->phydev && status)
		status->link = dev->phydev->link;

	return 0;
}

/* Perform a voluntary PHY software reset, since the EPHY is very finicky about
 * not doing it and will start corrupting packets
 */
void bcmgenet_mii_reset(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);

	if (GENET_IS_V4(priv))
		return;

	if (priv->phydev) {
		phy_init_hw(priv->phydev);
		phy_start_aneg(priv->phydev);
	}
}

void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg = 0;

	/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
	if (!GENET_IS_V4(priv))
		return;

	reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
	if (enable) {
		reg &= ~EXT_CK25_DIS;
		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
		mdelay(1);

		reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
		reg |= EXT_GPHY_RESET;
		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
		mdelay(1);

		reg &= ~EXT_GPHY_RESET;
	} else {
		reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET;
		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
		mdelay(1);
		reg |= EXT_CK25_DIS;
	}
	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
	udelay(60);
}

static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
{
	u32 reg;

	/* Speed settings are set in bcmgenet_mii_setup() */
	reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
	reg |= LED_ACT_SOURCE_MAC;
	bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);

	if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
		fixed_phy_set_link_update(priv->phydev,
					  bcmgenet_fixed_phy_link_update);
}

int bcmgenet_mii_config(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct phy_device *phydev = priv->phydev;
	struct device *kdev = &priv->pdev->dev;
	const char *phy_name = NULL;
	u32 id_mode_dis = 0;
	u32 port_ctrl;
	u32 reg;

	priv->ext_phy = !priv->internal_phy &&
			(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);

	if (priv->internal_phy)
		priv->phy_interface = PHY_INTERFACE_MODE_NA;

	switch (priv->phy_interface) {
	case PHY_INTERFACE_MODE_NA:
	case PHY_INTERFACE_MODE_MOCA:
		/* Irrespective of the actually configured PHY speed (100 or
		 * 1000) GENETv4 only has an internal GPHY so we will just end
		 * up masking the Gigabit features from what we support, not
		 * switching to the EPHY
		 */
		if (GENET_IS_V4(priv))
			port_ctrl = PORT_MODE_INT_GPHY;
		else
			port_ctrl = PORT_MODE_INT_EPHY;

		bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);

		if (priv->internal_phy) {
			phy_name = "internal PHY";
		} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
			phy_name = "MoCA";
			bcmgenet_moca_phy_setup(priv);
		}
		break;

	case PHY_INTERFACE_MODE_MII:
		phy_name = "external MII";
		phydev->supported &= PHY_BASIC_FEATURES;
		bcmgenet_sys_writel(priv,
				    PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
		break;

	case PHY_INTERFACE_MODE_REVMII:
		phy_name = "external RvMII";
		/* of_mdiobus_register took care of reading the 'max-speed'
		 * PHY property for us, effectively limiting the PHY supported
		 * capabilities, use that knowledge to also configure the
		 * Reverse MII interface correctly.
		 */
		if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
				PHY_BASIC_FEATURES)
			port_ctrl = PORT_MODE_EXT_RVMII_25;
		else
			port_ctrl = PORT_MODE_EXT_RVMII_50;
		bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
		break;

	case PHY_INTERFACE_MODE_RGMII:
		/* RGMII_NO_ID: TXC transitions at the same time as TXD
		 *		(requires PCB or receiver-side delay)
		 * RGMII:	Add 2ns delay on TXC (90 degree shift)
		 *
		 * ID is implicitly disabled for 100Mbps (RG)MII operation.
		 */
		id_mode_dis = BIT(16);
		/* fall through */
	case PHY_INTERFACE_MODE_RGMII_TXID:
		if (id_mode_dis)
			phy_name = "external RGMII (no delay)";
		else
			phy_name = "external RGMII (TX delay)";
		bcmgenet_sys_writel(priv,
				    PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
		break;
	default:
		dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
		return -EINVAL;
	}

	/* This is an external PHY (xMII), so we need to enable the RGMII
	 * block for the interface to work
	 */
	if (priv->ext_phy) {
		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
		reg |= RGMII_MODE_EN | id_mode_dis;
		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
	}

	dev_info_once(kdev, "configuring instance for %s\n", phy_name);

	return 0;
}

int bcmgenet_mii_probe(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct device_node *dn = priv->pdev->dev.of_node;
	struct phy_device *phydev;
	u32 phy_flags;
	int ret;

	/* Communicate the integrated PHY revision */
	phy_flags = priv->gphy_rev;

	/* Initialize link state variables that bcmgenet_mii_setup() uses */
	priv->old_link = -1;
	priv->old_speed = -1;
	priv->old_duplex = -1;
	priv->old_pause = -1;

	if (dn) {
		phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
					phy_flags, priv->phy_interface);
		if (!phydev) {
			pr_err("could not attach to PHY\n");
			return -ENODEV;
		}
	} else {
		phydev = priv->phydev;
		phydev->dev_flags = phy_flags;

		ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
					 priv->phy_interface);
		if (ret) {
			pr_err("could not attach to PHY\n");
			return -ENODEV;
		}
	}

	priv->phydev = phydev;

	/* Configure port multiplexer based on what the probed PHY device since
	 * reading the 'max-speed' property determines the maximum supported
	 * PHY speed which is needed for bcmgenet_mii_config() to configure
	 * things appropriately.
	 */
	ret = bcmgenet_mii_config(dev);
	if (ret) {
		phy_disconnect(priv->phydev);
		return ret;
	}

	phydev->advertising = phydev->supported;

	/* The internal PHY has its link interrupts routed to the
	 * Ethernet MAC ISRs
	 */
	if (priv->internal_phy)
		priv->phydev->irq = PHY_IGNORE_INTERRUPT;

	return 0;
}

/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
 * their internal MDIO management controller making them fail to successfully
 * be read from or written to for the first transaction.  We insert a dummy
 * BMSR read here to make sure that phy_get_device() and get_phy_id() can
 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
 * PHY device for this peripheral.
 *
 * Once the PHY driver is registered, we can workaround subsequent reads from
 * there (e.g: during system-wide power management).
 *
 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
 * therefore the right location to stick that workaround. Since we do not want
 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
 * Device Tree scan to limit the search area.
 */
static int bcmgenet_mii_bus_reset(struct mii_bus *bus)
{
	struct net_device *dev = bus->priv;
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct device_node *np = priv->mdio_dn;
	struct device_node *child = NULL;
	u32 read_mask = 0;
	int addr = 0;

	if (!np) {
		read_mask = 1 << priv->phy_addr;
	} else {
		for_each_available_child_of_node(np, child) {
			addr = of_mdio_parse_addr(&dev->dev, child);
			if (addr < 0)
				continue;

			read_mask |= 1 << addr;
		}
	}

	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
		if (read_mask & 1 << addr) {
			dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr);
			mdiobus_read(bus, addr, MII_BMSR);
		}
	}

	return 0;
}

static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
{
	struct mii_bus *bus;

	if (priv->mii_bus)
		return 0;

	priv->mii_bus = mdiobus_alloc();
	if (!priv->mii_bus) {
		pr_err("failed to allocate\n");
		return -ENOMEM;
	}

	bus = priv->mii_bus;
	bus->priv = priv->dev;
	bus->name = "bcmgenet MII bus";
	bus->parent = &priv->pdev->dev;
	bus->read = bcmgenet_mii_read;
	bus->write = bcmgenet_mii_write;
	bus->reset = bcmgenet_mii_bus_reset;
	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
		 priv->pdev->name, priv->pdev->id);

	return 0;
}

static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
{
	struct device_node *dn = priv->pdev->dev.of_node;
	struct device *kdev = &priv->pdev->dev;
	const char *phy_mode_str = NULL;
	struct phy_device *phydev = NULL;
	char *compat;
	int phy_mode;
	int ret;

	compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
	if (!compat)
		return -ENOMEM;

	priv->mdio_dn = of_find_compatible_node(dn, NULL, compat);
	kfree(compat);
	if (!priv->mdio_dn) {
		dev_err(kdev, "unable to find MDIO bus node\n");
		return -ENODEV;
	}

	ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn);
	if (ret) {
		dev_err(kdev, "failed to register MDIO bus\n");
		return ret;
	}

	/* Fetch the PHY phandle */
	priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);

	/* In the case of a fixed PHY, the DT node associated
	 * to the PHY is the Ethernet MAC DT node.
	 */
	if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
		ret = of_phy_register_fixed_link(dn);
		if (ret)
			return ret;

		priv->phy_dn = of_node_get(dn);
	}

	/* Get the link mode */
	phy_mode = of_get_phy_mode(dn);
	priv->phy_interface = phy_mode;

	/* We need to specifically look up whether this PHY interface is internal
	 * or not *before* we even try to probe the PHY driver over MDIO as we
	 * may have shut down the internal PHY for power saving purposes.
	 */
	if (phy_mode < 0) {
		ret = of_property_read_string(dn, "phy-mode", &phy_mode_str);
		if (ret < 0) {
			dev_err(kdev, "invalid PHY mode property\n");
			return ret;
		}

		priv->phy_interface = PHY_INTERFACE_MODE_NA;
		if (!strcasecmp(phy_mode_str, "internal"))
			priv->internal_phy = true;
	}

	/* Make sure we initialize MoCA PHYs with a link down */
	if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
		phydev = of_phy_find_device(dn);
		if (phydev) {
			phydev->link = 0;
			put_device(&phydev->mdio.dev);
		}
	}

	return 0;
}

static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
{
	struct device *kdev = &priv->pdev->dev;
	struct bcmgenet_platform_data *pd = kdev->platform_data;
	struct mii_bus *mdio = priv->mii_bus;
	struct phy_device *phydev;
	int ret;

	if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
		/*
		 * Internal or external PHY with MDIO access
		 */
		if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
			mdio->phy_mask = ~(1 << pd->phy_address);
		else
			mdio->phy_mask = 0;

		ret = mdiobus_register(mdio);
		if (ret) {
			dev_err(kdev, "failed to register MDIO bus\n");
			return ret;
		}

		if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
			phydev = mdiobus_get_phy(mdio, pd->phy_address);
		else
			phydev = phy_find_first(mdio);

		if (!phydev) {
			dev_err(kdev, "failed to register PHY device\n");
			mdiobus_unregister(mdio);
			return -ENODEV;
		}
	} else {
		/*
		 * MoCA port or no MDIO access.
		 * Use fixed PHY to represent the link layer.
		 */
		struct fixed_phy_status fphy_status = {
			.link = 1,
			.speed = pd->phy_speed,
			.duplex = pd->phy_duplex,
			.pause = 0,
			.asym_pause = 0,
		};

		phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
		if (!phydev || IS_ERR(phydev)) {
			dev_err(kdev, "failed to register fixed PHY device\n");
			return -ENODEV;
		}

		/* Make sure we initialize MoCA PHYs with a link down */
		phydev->link = 0;

	}

	priv->phydev = phydev;
	priv->phy_interface = pd->phy_interface;

	return 0;
}

static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
{
	struct device_node *dn = priv->pdev->dev.of_node;

	if (dn)
		return bcmgenet_mii_of_init(priv);
	else
		return bcmgenet_mii_pd_init(priv);
}

int bcmgenet_mii_init(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct device_node *dn = priv->pdev->dev.of_node;
	int ret;

	ret = bcmgenet_mii_alloc(priv);
	if (ret)
		return ret;

	ret = bcmgenet_mii_bus_init(priv);
	if (ret)
		goto out;

	return 0;

out:
	if (of_phy_is_fixed_link(dn))
		of_phy_deregister_fixed_link(dn);
	of_node_put(priv->phy_dn);
	mdiobus_unregister(priv->mii_bus);
	mdiobus_free(priv->mii_bus);
	return ret;
}

void bcmgenet_mii_exit(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct device_node *dn = priv->pdev->dev.of_node;

	if (of_phy_is_fixed_link(dn))
		of_phy_deregister_fixed_link(dn);
	of_node_put(priv->phy_dn);
	mdiobus_unregister(priv->mii_bus);
	mdiobus_free(priv->mii_bus);
}
Commit	Line	Data
aa09677c FF	1	/*
	2	* Broadcom GENET MDIO routines
	3	*
	4	* Copyright (c) 2014 Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
aa09677c FF	9	*/
	10
	11
	12	#include <linux/types.h>
	13	#include <linux/delay.h>
	14	#include <linux/wait.h>
	15	#include <linux/mii.h>
	16	#include <linux/ethtool.h>
	17	#include <linux/bitops.h>
	18	#include <linux/netdevice.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/phy.h>
	21	#include <linux/phy_fixed.h>
	22	#include <linux/brcmphy.h>
	23	#include <linux/of.h>
	24	#include <linux/of_net.h>
	25	#include <linux/of_mdio.h>
b0ba512e	26	#include <linux/platform_data/bcmgenet.h>
aa09677c FF	27
	28	#include "bcmgenet.h"
	29
	30	/* read a value from the MII */
	31	static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
	32	{
	33	int ret;
	34	struct net_device *dev = bus->priv;
	35	struct bcmgenet_priv *priv = netdev_priv(dev);
	36	u32 reg;
	37
	38	bcmgenet_umac_writel(priv, (MDIO_RD \| (phy_id << MDIO_PMD_SHIFT) \|
c91b7f66	39	(location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
aa09677c FF	40	/* Start MDIO transaction*/
	41	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	42	reg \|= MDIO_START_BUSY;
	43	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	44	wait_event_timeout(priv->wq,
c91b7f66 FF	45	!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
	46	& MDIO_START_BUSY),
	47	HZ / 100);
aa09677c FF	48	ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
aa09677c FF	49
9d3366e9 FF	50	/* Some broken devices are known not to release the line during
	51	* turn-around, e.g: Broadcom BCM53125 external switches, so check for
	52	* that condition here and ignore the MDIO controller read failure
	53	* indication.
	54	*/
	55	if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL))
aa09677c FF	56	return -EIO;
	57
	58	return ret & 0xffff;
	59	}
	60
	61	/* write a value to the MII */
	62	static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
c91b7f66	63	int location, u16 val)
aa09677c FF	64	{
	65	struct net_device *dev = bus->priv;
	66	struct bcmgenet_priv *priv = netdev_priv(dev);
	67	u32 reg;
	68
	69	bcmgenet_umac_writel(priv, (MDIO_WR \| (phy_id << MDIO_PMD_SHIFT) \|
c91b7f66 FF	70	(location << MDIO_REG_SHIFT) \| (0xffff & val)),
c91b7f66 FF	71	UMAC_MDIO_CMD);
aa09677c FF	72	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	73	reg \|= MDIO_START_BUSY;
	74	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	75	wait_event_timeout(priv->wq,
c91b7f66 FF	76	!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
	77	MDIO_START_BUSY),
	78	HZ / 100);
aa09677c FF	79
	80	return 0;
	81	}
	82
	83	/* setup netdev link state when PHY link status change and
	84	* update UMAC and RGMII block when link up
	85	*/
c96e731c	86	void bcmgenet_mii_setup(struct net_device *dev)
aa09677c FF	87	{
aa09677c FF	88	struct bcmgenet_priv *priv = netdev_priv(dev);
bf1a85a8	89	struct phy_device *phydev = priv->phydev;
aa09677c	90	u32 reg, cmd_bits = 0;
5ad6e6c5	91	bool status_changed = false;
aa09677c FF	92
aa09677c FF	93	if (priv->old_link != phydev->link) {
5ad6e6c5	94	status_changed = true;
aa09677c FF	95	priv->old_link = phydev->link;
	96	}
	97
	98	if (phydev->link) {
5ad6e6c5 PG	99	/* check speed/duplex/pause changes */
	100	if (priv->old_speed != phydev->speed) {
	101	status_changed = true;
	102	priv->old_speed = phydev->speed;
	103	}
	104
	105	if (priv->old_duplex != phydev->duplex) {
	106	status_changed = true;
	107	priv->old_duplex = phydev->duplex;
	108	}
	109
	110	if (priv->old_pause != phydev->pause) {
	111	status_changed = true;
	112	priv->old_pause = phydev->pause;
	113	}
	114
	115	/* done if nothing has changed */
	116	if (!status_changed)
	117	return;
aa09677c FF	118
	119	/* speed */
	120	if (phydev->speed == SPEED_1000)
	121	cmd_bits = UMAC_SPEED_1000;
	122	else if (phydev->speed == SPEED_100)
	123	cmd_bits = UMAC_SPEED_100;
	124	else
	125	cmd_bits = UMAC_SPEED_10;
	126	cmd_bits <<= CMD_SPEED_SHIFT;
	127
aa09677c FF	128	/* duplex */
	129	if (phydev->duplex != DUPLEX_FULL)
	130	cmd_bits \|= CMD_HD_EN;
	131
aa09677c FF	132	/* pause capability */
	133	if (!phydev->pause)
	134	cmd_bits \|= CMD_RX_PAUSE_IGNORE \| CMD_TX_PAUSE_IGNORE;
	135
5ad6e6c5 PG	136	/*
	137	* Program UMAC and RGMII block based on established
	138	* link speed, duplex, and pause. The speed set in
	139	* umac->cmd tell RGMII block which clock to use for
	140	* transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
	141	* Receive clock is provided by the PHY.
	142	*/
	143	reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
	144	reg &= ~OOB_DISABLE;
	145	reg \|= RGMII_LINK;
	146	bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
c677ba8b	147
aa09677c FF	148	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
	149	reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) \|
	150	CMD_HD_EN \|
	151	CMD_RX_PAUSE_IGNORE \| CMD_TX_PAUSE_IGNORE);
	152	reg \|= cmd_bits;
	153	bcmgenet_umac_writel(priv, reg, UMAC_CMD);
5ad6e6c5 PG	154	} else {
	155	/* done if nothing has changed */
	156	if (!status_changed)
	157	return;
aa09677c	158
5ad6e6c5 PG	159	/* needed for MoCA fixed PHY to reflect correct link status */
5ad6e6c5 PG	160	netif_carrier_off(dev);
24052408	161	}
c677ba8b FF	162
c677ba8b FF	163	phy_print_status(phydev);
aa09677c FF	164	}
aa09677c FF	165
5dbebbb4	166
6ac9de5f FF	167	static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
	168	struct fixed_phy_status *status)
	169	{
	170	if (dev && dev->phydev && status)
	171	status->link = dev->phydev->link;
	172
	173	return 0;
	174	}
	175
5dbebbb4 FF	176	/* Perform a voluntary PHY software reset, since the EPHY is very finicky about
	177	* not doing it and will start corrupting packets
	178	*/
	179	void bcmgenet_mii_reset(struct net_device *dev)
	180	{
	181	struct bcmgenet_priv *priv = netdev_priv(dev);
	182
	183	if (GENET_IS_V4(priv))
	184	return;
	185
bf1a85a8 FF	186	if (priv->phydev) {
	187	phy_init_hw(priv->phydev);
	188	phy_start_aneg(priv->phydev);
5dbebbb4 FF	189	}
	190	}
	191
a642c4f7	192	void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
aa09677c FF	193	{
	194	struct bcmgenet_priv *priv = netdev_priv(dev);
	195	u32 reg = 0;
	196
	197	/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
	198	if (!GENET_IS_V4(priv))
	199	return;
	200
a9d608c1	201	reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
8212c983	202	if (enable) {
0c81a8ee FF	203	reg &= ~EXT_CK25_DIS;
	204	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
	205	mdelay(1);
	206
	207	reg &= ~(EXT_CFG_IDDQ_BIAS \| EXT_CFG_PWR_DOWN);
8212c983 FF	208	reg \|= EXT_GPHY_RESET;
8212c983 FF	209	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
0c81a8ee	210	mdelay(1);
aa09677c	211
8212c983	212	reg &= ~EXT_GPHY_RESET;
a9d608c1 FF	213	} else {
a9d608c1 FF	214	reg \|= EXT_CFG_IDDQ_BIAS \| EXT_CFG_PWR_DOWN \| EXT_GPHY_RESET;
8212c983	215	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
a9d608c1 FF	216	mdelay(1);
a9d608c1 FF	217	reg \|= EXT_CK25_DIS;
8212c983	218	}
a9d608c1 FF	219	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
a9d608c1 FF	220	udelay(60);
aa09677c FF	221	}
aa09677c FF	222
aa09677c FF	223	static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
	224	{
	225	u32 reg;
	226
	227	/* Speed settings are set in bcmgenet_mii_setup() */
	228	reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
	229	reg \|= LED_ACT_SOURCE_MAC;
	230	bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
6ac9de5f FF	231
6ac9de5f FF	232	if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
bf1a85a8	233	fixed_phy_set_link_update(priv->phydev,
6ac9de5f	234	bcmgenet_fixed_phy_link_update);
aa09677c FF	235	}
aa09677c FF	236
28b45910	237	int bcmgenet_mii_config(struct net_device *dev)
aa09677c FF	238	{
aa09677c FF	239	struct bcmgenet_priv *priv = netdev_priv(dev);
bf1a85a8	240	struct phy_device *phydev = priv->phydev;
aa09677c FF	241	struct device *kdev = &priv->pdev->dev;
	242	const char *phy_name = NULL;
	243	u32 id_mode_dis = 0;
	244	u32 port_ctrl;
	245	u32 reg;
	246
c624f891	247	priv->ext_phy = !priv->internal_phy &&
aa09677c FF	248	(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
aa09677c FF	249
c624f891	250	if (priv->internal_phy)
aa09677c FF	251	priv->phy_interface = PHY_INTERFACE_MODE_NA;
	252
	253	switch (priv->phy_interface) {
	254	case PHY_INTERFACE_MODE_NA:
	255	case PHY_INTERFACE_MODE_MOCA:
	256	/* Irrespective of the actually configured PHY speed (100 or
	257	* 1000) GENETv4 only has an internal GPHY so we will just end
	258	* up masking the Gigabit features from what we support, not
	259	* switching to the EPHY
	260	*/
	261	if (GENET_IS_V4(priv))
	262	port_ctrl = PORT_MODE_INT_GPHY;
	263	else
	264	port_ctrl = PORT_MODE_INT_EPHY;
	265
	266	bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
	267
c624f891	268	if (priv->internal_phy) {
aa09677c	269	phy_name = "internal PHY";
aa09677c FF	270	} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
	271	phy_name = "MoCA";
	272	bcmgenet_moca_phy_setup(priv);
	273	}
	274	break;
	275
	276	case PHY_INTERFACE_MODE_MII:
	277	phy_name = "external MII";
	278	phydev->supported &= PHY_BASIC_FEATURES;
	279	bcmgenet_sys_writel(priv,
c91b7f66	280	PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
aa09677c FF	281	break;
	282
	283	case PHY_INTERFACE_MODE_REVMII:
	284	phy_name = "external RvMII";
	285	/* of_mdiobus_register took care of reading the 'max-speed'
	286	* PHY property for us, effectively limiting the PHY supported
	287	* capabilities, use that knowledge to also configure the
	288	* Reverse MII interface correctly.
	289	*/
bf1a85a8	290	if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
aa09677c FF	291	PHY_BASIC_FEATURES)
	292	port_ctrl = PORT_MODE_EXT_RVMII_25;
	293	else
	294	port_ctrl = PORT_MODE_EXT_RVMII_50;
	295	bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
	296	break;
	297
	298	case PHY_INTERFACE_MODE_RGMII:
	299	/* RGMII_NO_ID: TXC transitions at the same time as TXD
	300	* (requires PCB or receiver-side delay)
	301	* RGMII: Add 2ns delay on TXC (90 degree shift)
	302	*
	303	* ID is implicitly disabled for 100Mbps (RG)MII operation.
	304	*/
	305	id_mode_dis = BIT(16);
	306	/* fall through */
	307	case PHY_INTERFACE_MODE_RGMII_TXID:
	308	if (id_mode_dis)
	309	phy_name = "external RGMII (no delay)";
	310	else
	311	phy_name = "external RGMII (TX delay)";
aa09677c	312	bcmgenet_sys_writel(priv,
c91b7f66	313	PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
aa09677c FF	314	break;
	315	default:
	316	dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
	317	return -EINVAL;
	318	}
	319
afe3f907 FF	320	/* This is an external PHY (xMII), so we need to enable the RGMII
	321	* block for the interface to work
	322	*/
	323	if (priv->ext_phy) {
	324	reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
	325	reg \|= RGMII_MODE_EN \| id_mode_dis;
	326	bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
	327	}
	328
28b45910	329	dev_info_once(kdev, "configuring instance for %s\n", phy_name);
aa09677c FF	330
	331	return 0;
	332	}
	333
6cc8e6d4	334	int bcmgenet_mii_probe(struct net_device *dev)
aa09677c FF	335	{
aa09677c FF	336	struct bcmgenet_priv *priv = netdev_priv(dev);
9abf0c2b	337	struct device_node *dn = priv->pdev->dev.of_node;
aa09677c	338	struct phy_device *phydev;
487320c5	339	u32 phy_flags;
aa09677c FF	340	int ret;
aa09677c FF	341
487320c5 FF	342	/* Communicate the integrated PHY revision */
	343	phy_flags = priv->gphy_rev;
	344
5ad6e6c5 PG	345	/* Initialize link state variables that bcmgenet_mii_setup() uses */
	346	priv->old_link = -1;
	347	priv->old_speed = -1;
	348	priv->old_duplex = -1;
	349	priv->old_pause = -1;
	350
b0ba512e	351	if (dn) {
b0ba512e PG	352	phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
	353	phy_flags, priv->phy_interface);
	354	if (!phydev) {
	355	pr_err("could not attach to PHY\n");
	356	return -ENODEV;
	357	}
	358	} else {
bf1a85a8	359	phydev = priv->phydev;
b0ba512e PG	360	phydev->dev_flags = phy_flags;
	361
	362	ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
	363	priv->phy_interface);
	364	if (ret) {
	365	pr_err("could not attach to PHY\n");
	366	return -ENODEV;
	367	}
aa09677c FF	368	}
aa09677c FF	369
bf1a85a8 FF	370	priv->phydev = phydev;
bf1a85a8 FF	371
aa09677c FF	372	/* Configure port multiplexer based on what the probed PHY device since
	373	* reading the 'max-speed' property determines the maximum supported
	374	* PHY speed which is needed for bcmgenet_mii_config() to configure
	375	* things appropriately.
	376	*/
28b45910	377	ret = bcmgenet_mii_config(dev);
aa09677c	378	if (ret) {
bf1a85a8	379	phy_disconnect(priv->phydev);
aa09677c FF	380	return ret;
	381	}
	382
aa09677c FF	383	phydev->advertising = phydev->supported;
	384
	385	/* The internal PHY has its link interrupts routed to the
	386	* Ethernet MAC ISRs
	387	*/
c624f891	388	if (priv->internal_phy)
bf1a85a8	389	priv->phydev->irq = PHY_IGNORE_INTERRUPT;
aa09677c	390
aa09677c FF	391	return 0;
	392	}
	393
7b635da8 FF	394	/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
	395	* their internal MDIO management controller making them fail to successfully
	396	* be read from or written to for the first transaction. We insert a dummy
	397	* BMSR read here to make sure that phy_get_device() and get_phy_id() can
	398	* correctly read the PHY MII_PHYSID1/2 registers and successfully register a
	399	* PHY device for this peripheral.
	400	*
	401	* Once the PHY driver is registered, we can workaround subsequent reads from
	402	* there (e.g: during system-wide power management).
	403	*
	404	* bus->reset is invoked before mdiobus_scan during mdiobus_register and is
	405	* therefore the right location to stick that workaround. Since we do not want
	406	* to read from non-existing PHYs, we either use bus->phy_mask or do a manual
	407	* Device Tree scan to limit the search area.
	408	*/
	409	static int bcmgenet_mii_bus_reset(struct mii_bus *bus)
	410	{
	411	struct net_device *dev = bus->priv;
	412	struct bcmgenet_priv *priv = netdev_priv(dev);
	413	struct device_node *np = priv->mdio_dn;
	414	struct device_node *child = NULL;
	415	u32 read_mask = 0;
	416	int addr = 0;
	417
	418	if (!np) {
	419	read_mask = 1 << priv->phy_addr;
	420	} else {
	421	for_each_available_child_of_node(np, child) {
	422	addr = of_mdio_parse_addr(&dev->dev, child);
	423	if (addr < 0)
	424	continue;
	425
	426	read_mask \|= 1 << addr;
	427	}
	428	}
	429
	430	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
	431	if (read_mask & 1 << addr) {
	432	dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr);
	433	mdiobus_read(bus, addr, MII_BMSR);
	434	}
	435	}
	436
	437	return 0;
	438	}
	439
aa09677c FF	440	static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
	441	{
	442	struct mii_bus *bus;
	443
	444	if (priv->mii_bus)
	445	return 0;
	446
	447	priv->mii_bus = mdiobus_alloc();
	448	if (!priv->mii_bus) {
	449	pr_err("failed to allocate\n");
	450	return -ENOMEM;
	451	}
	452
	453	bus = priv->mii_bus;
	454	bus->priv = priv->dev;
	455	bus->name = "bcmgenet MII bus";
	456	bus->parent = &priv->pdev->dev;
	457	bus->read = bcmgenet_mii_read;
	458	bus->write = bcmgenet_mii_write;
7b635da8	459	bus->reset = bcmgenet_mii_bus_reset;
aa09677c	460	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
c91b7f66	461	priv->pdev->name, priv->pdev->id);
aa09677c	462
aa09677c FF	463	return 0;
	464	}
	465
	466	static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
	467	{
	468	struct device_node *dn = priv->pdev->dev.of_node;
	469	struct device *kdev = &priv->pdev->dev;
c624f891	470	const char *phy_mode_str = NULL;
6ac9de5f	471	struct phy_device *phydev = NULL;
aa09677c	472	char *compat;
c624f891	473	int phy_mode;
aa09677c FF	474	int ret;
	475
	476	compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
	477	if (!compat)
	478	return -ENOMEM;
	479
7b635da8	480	priv->mdio_dn = of_find_compatible_node(dn, NULL, compat);
aa09677c	481	kfree(compat);
7b635da8	482	if (!priv->mdio_dn) {
aa09677c FF	483	dev_err(kdev, "unable to find MDIO bus node\n");
	484	return -ENODEV;
	485	}
	486
7b635da8	487	ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn);
aa09677c FF	488	if (ret) {
	489	dev_err(kdev, "failed to register MDIO bus\n");
	490	return ret;
	491	}
	492
	493	/* Fetch the PHY phandle */
	494	priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
	495
6cc8e6d4 FF	496	/* In the case of a fixed PHY, the DT node associated
	497	* to the PHY is the Ethernet MAC DT node.
	498	*/
	499	if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
	500	ret = of_phy_register_fixed_link(dn);
	501	if (ret)
	502	return ret;
	503
	504	priv->phy_dn = of_node_get(dn);
	505	}
	506
aa09677c	507	/* Get the link mode */
c624f891 FF	508	phy_mode = of_get_phy_mode(dn);
	509	priv->phy_interface = phy_mode;
	510
	511	/* We need to specifically look up whether this PHY interface is internal
	512	* or not before we even try to probe the PHY driver over MDIO as we
	513	* may have shut down the internal PHY for power saving purposes.
	514	*/
	515	if (phy_mode < 0) {
	516	ret = of_property_read_string(dn, "phy-mode", &phy_mode_str);
	517	if (ret < 0) {
	518	dev_err(kdev, "invalid PHY mode property\n");
	519	return ret;
	520	}
	521
	522	priv->phy_interface = PHY_INTERFACE_MODE_NA;
	523	if (!strcasecmp(phy_mode_str, "internal"))
	524	priv->internal_phy = true;
	525	}
aa09677c	526
6ac9de5f FF	527	/* Make sure we initialize MoCA PHYs with a link down */
	528	if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
	529	phydev = of_phy_find_device(dn);
0da60541	530	if (phydev) {
6ac9de5f	531	phydev->link = 0;
0da60541 JH	532	put_device(&phydev->mdio.dev);
0da60541 JH	533	}
6ac9de5f	534	}
8d88c6eb PG	535
	536	return 0;
	537	}
	538
b0ba512e PG	539	static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
	540	{
	541	struct device *kdev = &priv->pdev->dev;
	542	struct bcmgenet_platform_data *pd = kdev->platform_data;
	543	struct mii_bus *mdio = priv->mii_bus;
	544	struct phy_device *phydev;
	545	int ret;
	546
	547	if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
	548	/*
	549	* Internal or external PHY with MDIO access
	550	*/
	551	if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
	552	mdio->phy_mask = ~(1 << pd->phy_address);
	553	else
	554	mdio->phy_mask = 0;
	555
	556	ret = mdiobus_register(mdio);
	557	if (ret) {
	558	dev_err(kdev, "failed to register MDIO bus\n");
	559	return ret;
	560	}
	561
	562	if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
7f854420	563	phydev = mdiobus_get_phy(mdio, pd->phy_address);
b0ba512e PG	564	else
	565	phydev = phy_find_first(mdio);
	566
	567	if (!phydev) {
	568	dev_err(kdev, "failed to register PHY device\n");
	569	mdiobus_unregister(mdio);
	570	return -ENODEV;
	571	}
	572	} else {
	573	/*
	574	* MoCA port or no MDIO access.
	575	* Use fixed PHY to represent the link layer.
	576	*/
	577	struct fixed_phy_status fphy_status = {
	578	.link = 1,
	579	.speed = pd->phy_speed,
	580	.duplex = pd->phy_duplex,
	581	.pause = 0,
	582	.asym_pause = 0,
	583	};
	584
a5597008	585	phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
b0ba512e PG	586	if (!phydev \|\| IS_ERR(phydev)) {
	587	dev_err(kdev, "failed to register fixed PHY device\n");
	588	return -ENODEV;
	589	}
8d88c6eb	590
6ac9de5f FF	591	/* Make sure we initialize MoCA PHYs with a link down */
	592	phydev->link = 0;
	593
b0ba512e PG	594	}
b0ba512e PG	595
bf1a85a8	596	priv->phydev = phydev;
b0ba512e PG	597	priv->phy_interface = pd->phy_interface;
	598
	599	return 0;
	600	}
	601
	602	static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
	603	{
	604	struct device_node *dn = priv->pdev->dev.of_node;
	605
	606	if (dn)
	607	return bcmgenet_mii_of_init(priv);
	608	else
	609	return bcmgenet_mii_pd_init(priv);
	610	}
	611
aa09677c FF	612	int bcmgenet_mii_init(struct net_device *dev)
	613	{
	614	struct bcmgenet_priv *priv = netdev_priv(dev);
140ca9d3	615	struct device_node *dn = priv->pdev->dev.of_node;
aa09677c FF	616	int ret;
	617
	618	ret = bcmgenet_mii_alloc(priv);
	619	if (ret)
	620	return ret;
	621
b0ba512e	622	ret = bcmgenet_mii_bus_init(priv);
aa09677c FF	623	if (ret)
	624	goto out;
	625
	626	return 0;
	627
	628	out:
140ca9d3 JH	629	if (of_phy_is_fixed_link(dn))
140ca9d3 JH	630	of_phy_deregister_fixed_link(dn);
9518259f	631	of_node_put(priv->phy_dn);
aa09677c	632	mdiobus_unregister(priv->mii_bus);
aa09677c FF	633	mdiobus_free(priv->mii_bus);
	634	return ret;
	635	}
	636
	637	void bcmgenet_mii_exit(struct net_device *dev)
	638	{
	639	struct bcmgenet_priv *priv = netdev_priv(dev);
140ca9d3	640	struct device_node *dn = priv->pdev->dev.of_node;
aa09677c	641
140ca9d3 JH	642	if (of_phy_is_fixed_link(dn))
140ca9d3 JH	643	of_phy_deregister_fixed_link(dn);
9518259f	644	of_node_put(priv->phy_dn);
aa09677c	645	mdiobus_unregister(priv->mii_bus);
aa09677c FF	646	mdiobus_free(priv->mii_bus);
aa09677c FF	647	}