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aa09677c FF |
1 | /* |
2 | * Broadcom GENET MDIO routines | |
3 | * | |
4 | * Copyright (c) 2014 Broadcom Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
aa09677c FF |
9 | */ |
10 | ||
11 | ||
12 | #include <linux/types.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/wait.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/bitops.h> | |
18 | #include <linux/netdevice.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/phy.h> | |
21 | #include <linux/phy_fixed.h> | |
22 | #include <linux/brcmphy.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/of_net.h> | |
25 | #include <linux/of_mdio.h> | |
b0ba512e | 26 | #include <linux/platform_data/bcmgenet.h> |
aa09677c FF |
27 | |
28 | #include "bcmgenet.h" | |
29 | ||
30 | /* read a value from the MII */ | |
31 | static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location) | |
32 | { | |
33 | int ret; | |
34 | struct net_device *dev = bus->priv; | |
35 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
36 | u32 reg; | |
37 | ||
38 | bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | | |
c91b7f66 | 39 | (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD); |
aa09677c FF |
40 | /* Start MDIO transaction*/ |
41 | reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); | |
42 | reg |= MDIO_START_BUSY; | |
43 | bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); | |
44 | wait_event_timeout(priv->wq, | |
c91b7f66 FF |
45 | !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) |
46 | & MDIO_START_BUSY), | |
47 | HZ / 100); | |
aa09677c FF |
48 | ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); |
49 | ||
50 | if (ret & MDIO_READ_FAIL) | |
51 | return -EIO; | |
52 | ||
53 | return ret & 0xffff; | |
54 | } | |
55 | ||
56 | /* write a value to the MII */ | |
57 | static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id, | |
c91b7f66 | 58 | int location, u16 val) |
aa09677c FF |
59 | { |
60 | struct net_device *dev = bus->priv; | |
61 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
62 | u32 reg; | |
63 | ||
64 | bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | | |
c91b7f66 FF |
65 | (location << MDIO_REG_SHIFT) | (0xffff & val)), |
66 | UMAC_MDIO_CMD); | |
aa09677c FF |
67 | reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); |
68 | reg |= MDIO_START_BUSY; | |
69 | bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); | |
70 | wait_event_timeout(priv->wq, | |
c91b7f66 FF |
71 | !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) & |
72 | MDIO_START_BUSY), | |
73 | HZ / 100); | |
aa09677c FF |
74 | |
75 | return 0; | |
76 | } | |
77 | ||
78 | /* setup netdev link state when PHY link status change and | |
79 | * update UMAC and RGMII block when link up | |
80 | */ | |
c96e731c | 81 | void bcmgenet_mii_setup(struct net_device *dev) |
aa09677c FF |
82 | { |
83 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
84 | struct phy_device *phydev = priv->phydev; | |
85 | u32 reg, cmd_bits = 0; | |
5ad6e6c5 | 86 | bool status_changed = false; |
aa09677c FF |
87 | |
88 | if (priv->old_link != phydev->link) { | |
5ad6e6c5 | 89 | status_changed = true; |
aa09677c FF |
90 | priv->old_link = phydev->link; |
91 | } | |
92 | ||
93 | if (phydev->link) { | |
5ad6e6c5 PG |
94 | /* check speed/duplex/pause changes */ |
95 | if (priv->old_speed != phydev->speed) { | |
96 | status_changed = true; | |
97 | priv->old_speed = phydev->speed; | |
98 | } | |
99 | ||
100 | if (priv->old_duplex != phydev->duplex) { | |
101 | status_changed = true; | |
102 | priv->old_duplex = phydev->duplex; | |
103 | } | |
104 | ||
105 | if (priv->old_pause != phydev->pause) { | |
106 | status_changed = true; | |
107 | priv->old_pause = phydev->pause; | |
108 | } | |
109 | ||
110 | /* done if nothing has changed */ | |
111 | if (!status_changed) | |
112 | return; | |
aa09677c FF |
113 | |
114 | /* speed */ | |
115 | if (phydev->speed == SPEED_1000) | |
116 | cmd_bits = UMAC_SPEED_1000; | |
117 | else if (phydev->speed == SPEED_100) | |
118 | cmd_bits = UMAC_SPEED_100; | |
119 | else | |
120 | cmd_bits = UMAC_SPEED_10; | |
121 | cmd_bits <<= CMD_SPEED_SHIFT; | |
122 | ||
aa09677c FF |
123 | /* duplex */ |
124 | if (phydev->duplex != DUPLEX_FULL) | |
125 | cmd_bits |= CMD_HD_EN; | |
126 | ||
aa09677c FF |
127 | /* pause capability */ |
128 | if (!phydev->pause) | |
129 | cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; | |
130 | ||
5ad6e6c5 PG |
131 | /* |
132 | * Program UMAC and RGMII block based on established | |
133 | * link speed, duplex, and pause. The speed set in | |
134 | * umac->cmd tell RGMII block which clock to use for | |
135 | * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). | |
136 | * Receive clock is provided by the PHY. | |
137 | */ | |
138 | reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); | |
139 | reg &= ~OOB_DISABLE; | |
140 | reg |= RGMII_LINK; | |
141 | bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); | |
c677ba8b | 142 | |
aa09677c FF |
143 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); |
144 | reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | | |
145 | CMD_HD_EN | | |
146 | CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); | |
147 | reg |= cmd_bits; | |
148 | bcmgenet_umac_writel(priv, reg, UMAC_CMD); | |
5ad6e6c5 PG |
149 | } else { |
150 | /* done if nothing has changed */ | |
151 | if (!status_changed) | |
152 | return; | |
aa09677c | 153 | |
5ad6e6c5 PG |
154 | /* needed for MoCA fixed PHY to reflect correct link status */ |
155 | netif_carrier_off(dev); | |
24052408 | 156 | } |
c677ba8b FF |
157 | |
158 | phy_print_status(phydev); | |
aa09677c FF |
159 | } |
160 | ||
161 | void bcmgenet_mii_reset(struct net_device *dev) | |
162 | { | |
163 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
164 | ||
165 | if (priv->phydev) { | |
166 | phy_init_hw(priv->phydev); | |
167 | phy_start_aneg(priv->phydev); | |
168 | } | |
169 | } | |
170 | ||
8212c983 | 171 | static void bcmgenet_phy_power_set(struct net_device *dev, bool enable) |
aa09677c FF |
172 | { |
173 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
174 | u32 reg = 0; | |
175 | ||
176 | /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ | |
177 | if (!GENET_IS_V4(priv)) | |
178 | return; | |
179 | ||
a9d608c1 | 180 | reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); |
8212c983 | 181 | if (enable) { |
0c81a8ee FF |
182 | reg &= ~EXT_CK25_DIS; |
183 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); | |
184 | mdelay(1); | |
185 | ||
186 | reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); | |
8212c983 FF |
187 | reg |= EXT_GPHY_RESET; |
188 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); | |
0c81a8ee | 189 | mdelay(1); |
aa09677c | 190 | |
8212c983 | 191 | reg &= ~EXT_GPHY_RESET; |
a9d608c1 FF |
192 | } else { |
193 | reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET; | |
8212c983 | 194 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); |
a9d608c1 FF |
195 | mdelay(1); |
196 | reg |= EXT_CK25_DIS; | |
8212c983 | 197 | } |
a9d608c1 FF |
198 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); |
199 | udelay(60); | |
aa09677c FF |
200 | } |
201 | ||
202 | static void bcmgenet_internal_phy_setup(struct net_device *dev) | |
203 | { | |
204 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
205 | u32 reg; | |
206 | ||
8212c983 FF |
207 | /* Power up PHY */ |
208 | bcmgenet_phy_power_set(dev, true); | |
aa09677c FF |
209 | /* enable APD */ |
210 | reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); | |
211 | reg |= EXT_PWR_DN_EN_LD; | |
212 | bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); | |
213 | bcmgenet_mii_reset(dev); | |
214 | } | |
215 | ||
216 | static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) | |
217 | { | |
218 | u32 reg; | |
219 | ||
220 | /* Speed settings are set in bcmgenet_mii_setup() */ | |
221 | reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); | |
222 | reg |= LED_ACT_SOURCE_MAC; | |
223 | bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); | |
224 | } | |
225 | ||
dbd479db | 226 | int bcmgenet_mii_config(struct net_device *dev, bool init) |
aa09677c FF |
227 | { |
228 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
229 | struct phy_device *phydev = priv->phydev; | |
230 | struct device *kdev = &priv->pdev->dev; | |
231 | const char *phy_name = NULL; | |
232 | u32 id_mode_dis = 0; | |
233 | u32 port_ctrl; | |
234 | u32 reg; | |
235 | ||
236 | priv->ext_phy = !phy_is_internal(priv->phydev) && | |
237 | (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); | |
238 | ||
239 | if (phy_is_internal(priv->phydev)) | |
240 | priv->phy_interface = PHY_INTERFACE_MODE_NA; | |
241 | ||
242 | switch (priv->phy_interface) { | |
243 | case PHY_INTERFACE_MODE_NA: | |
244 | case PHY_INTERFACE_MODE_MOCA: | |
245 | /* Irrespective of the actually configured PHY speed (100 or | |
246 | * 1000) GENETv4 only has an internal GPHY so we will just end | |
247 | * up masking the Gigabit features from what we support, not | |
248 | * switching to the EPHY | |
249 | */ | |
250 | if (GENET_IS_V4(priv)) | |
251 | port_ctrl = PORT_MODE_INT_GPHY; | |
252 | else | |
253 | port_ctrl = PORT_MODE_INT_EPHY; | |
254 | ||
255 | bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); | |
256 | ||
257 | if (phy_is_internal(priv->phydev)) { | |
258 | phy_name = "internal PHY"; | |
259 | bcmgenet_internal_phy_setup(dev); | |
260 | } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { | |
261 | phy_name = "MoCA"; | |
262 | bcmgenet_moca_phy_setup(priv); | |
263 | } | |
264 | break; | |
265 | ||
266 | case PHY_INTERFACE_MODE_MII: | |
267 | phy_name = "external MII"; | |
268 | phydev->supported &= PHY_BASIC_FEATURES; | |
269 | bcmgenet_sys_writel(priv, | |
c91b7f66 | 270 | PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); |
aa09677c FF |
271 | break; |
272 | ||
273 | case PHY_INTERFACE_MODE_REVMII: | |
274 | phy_name = "external RvMII"; | |
275 | /* of_mdiobus_register took care of reading the 'max-speed' | |
276 | * PHY property for us, effectively limiting the PHY supported | |
277 | * capabilities, use that knowledge to also configure the | |
278 | * Reverse MII interface correctly. | |
279 | */ | |
280 | if ((priv->phydev->supported & PHY_BASIC_FEATURES) == | |
281 | PHY_BASIC_FEATURES) | |
282 | port_ctrl = PORT_MODE_EXT_RVMII_25; | |
283 | else | |
284 | port_ctrl = PORT_MODE_EXT_RVMII_50; | |
285 | bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); | |
286 | break; | |
287 | ||
288 | case PHY_INTERFACE_MODE_RGMII: | |
289 | /* RGMII_NO_ID: TXC transitions at the same time as TXD | |
290 | * (requires PCB or receiver-side delay) | |
291 | * RGMII: Add 2ns delay on TXC (90 degree shift) | |
292 | * | |
293 | * ID is implicitly disabled for 100Mbps (RG)MII operation. | |
294 | */ | |
295 | id_mode_dis = BIT(16); | |
296 | /* fall through */ | |
297 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
298 | if (id_mode_dis) | |
299 | phy_name = "external RGMII (no delay)"; | |
300 | else | |
301 | phy_name = "external RGMII (TX delay)"; | |
302 | reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); | |
303 | reg |= RGMII_MODE_EN | id_mode_dis; | |
304 | bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); | |
305 | bcmgenet_sys_writel(priv, | |
c91b7f66 | 306 | PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); |
aa09677c FF |
307 | break; |
308 | default: | |
309 | dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); | |
310 | return -EINVAL; | |
311 | } | |
312 | ||
dbd479db FF |
313 | if (init) |
314 | dev_info(kdev, "configuring instance for %s\n", phy_name); | |
aa09677c FF |
315 | |
316 | return 0; | |
317 | } | |
318 | ||
319 | static int bcmgenet_mii_probe(struct net_device *dev) | |
320 | { | |
321 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
9abf0c2b | 322 | struct device_node *dn = priv->pdev->dev.of_node; |
aa09677c | 323 | struct phy_device *phydev; |
487320c5 | 324 | u32 phy_flags; |
aa09677c FF |
325 | int ret; |
326 | ||
487320c5 FF |
327 | /* Communicate the integrated PHY revision */ |
328 | phy_flags = priv->gphy_rev; | |
329 | ||
5ad6e6c5 PG |
330 | /* Initialize link state variables that bcmgenet_mii_setup() uses */ |
331 | priv->old_link = -1; | |
332 | priv->old_speed = -1; | |
333 | priv->old_duplex = -1; | |
334 | priv->old_pause = -1; | |
335 | ||
b0ba512e PG |
336 | if (dn) { |
337 | if (priv->phydev) { | |
338 | pr_info("PHY already attached\n"); | |
339 | return 0; | |
340 | } | |
341 | ||
342 | /* In the case of a fixed PHY, the DT node associated | |
343 | * to the PHY is the Ethernet MAC DT node. | |
344 | */ | |
345 | if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { | |
346 | ret = of_phy_register_fixed_link(dn); | |
347 | if (ret) | |
348 | return ret; | |
349 | ||
350 | priv->phy_dn = of_node_get(dn); | |
351 | } | |
352 | ||
353 | phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, | |
354 | phy_flags, priv->phy_interface); | |
355 | if (!phydev) { | |
356 | pr_err("could not attach to PHY\n"); | |
357 | return -ENODEV; | |
358 | } | |
359 | } else { | |
360 | phydev = priv->phydev; | |
361 | phydev->dev_flags = phy_flags; | |
362 | ||
363 | ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, | |
364 | priv->phy_interface); | |
365 | if (ret) { | |
366 | pr_err("could not attach to PHY\n"); | |
367 | return -ENODEV; | |
368 | } | |
aa09677c FF |
369 | } |
370 | ||
aa09677c FF |
371 | priv->phydev = phydev; |
372 | ||
373 | /* Configure port multiplexer based on what the probed PHY device since | |
374 | * reading the 'max-speed' property determines the maximum supported | |
375 | * PHY speed which is needed for bcmgenet_mii_config() to configure | |
376 | * things appropriately. | |
377 | */ | |
dbd479db | 378 | ret = bcmgenet_mii_config(dev, true); |
aa09677c FF |
379 | if (ret) { |
380 | phy_disconnect(priv->phydev); | |
381 | return ret; | |
382 | } | |
383 | ||
aa09677c FF |
384 | phydev->advertising = phydev->supported; |
385 | ||
386 | /* The internal PHY has its link interrupts routed to the | |
387 | * Ethernet MAC ISRs | |
388 | */ | |
389 | if (phy_is_internal(priv->phydev)) | |
390 | priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT; | |
391 | else | |
392 | priv->mii_bus->irq[phydev->addr] = PHY_POLL; | |
393 | ||
394 | pr_info("attached PHY at address %d [%s]\n", | |
c91b7f66 | 395 | phydev->addr, phydev->drv->name); |
aa09677c FF |
396 | |
397 | return 0; | |
398 | } | |
399 | ||
400 | static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv) | |
401 | { | |
402 | struct mii_bus *bus; | |
403 | ||
404 | if (priv->mii_bus) | |
405 | return 0; | |
406 | ||
407 | priv->mii_bus = mdiobus_alloc(); | |
408 | if (!priv->mii_bus) { | |
409 | pr_err("failed to allocate\n"); | |
410 | return -ENOMEM; | |
411 | } | |
412 | ||
413 | bus = priv->mii_bus; | |
414 | bus->priv = priv->dev; | |
415 | bus->name = "bcmgenet MII bus"; | |
416 | bus->parent = &priv->pdev->dev; | |
417 | bus->read = bcmgenet_mii_read; | |
418 | bus->write = bcmgenet_mii_write; | |
419 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", | |
c91b7f66 | 420 | priv->pdev->name, priv->pdev->id); |
aa09677c | 421 | |
c489be08 | 422 | bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); |
aa09677c FF |
423 | if (!bus->irq) { |
424 | mdiobus_free(priv->mii_bus); | |
425 | return -ENOMEM; | |
426 | } | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
431 | static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) | |
432 | { | |
433 | struct device_node *dn = priv->pdev->dev.of_node; | |
434 | struct device *kdev = &priv->pdev->dev; | |
435 | struct device_node *mdio_dn; | |
436 | char *compat; | |
437 | int ret; | |
438 | ||
439 | compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); | |
440 | if (!compat) | |
441 | return -ENOMEM; | |
442 | ||
443 | mdio_dn = of_find_compatible_node(dn, NULL, compat); | |
444 | kfree(compat); | |
445 | if (!mdio_dn) { | |
446 | dev_err(kdev, "unable to find MDIO bus node\n"); | |
447 | return -ENODEV; | |
448 | } | |
449 | ||
450 | ret = of_mdiobus_register(priv->mii_bus, mdio_dn); | |
451 | if (ret) { | |
452 | dev_err(kdev, "failed to register MDIO bus\n"); | |
453 | return ret; | |
454 | } | |
455 | ||
456 | /* Fetch the PHY phandle */ | |
457 | priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); | |
458 | ||
459 | /* Get the link mode */ | |
460 | priv->phy_interface = of_get_phy_mode(dn); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
b0ba512e PG |
465 | static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) |
466 | { | |
467 | struct device *kdev = &priv->pdev->dev; | |
468 | struct bcmgenet_platform_data *pd = kdev->platform_data; | |
469 | struct mii_bus *mdio = priv->mii_bus; | |
470 | struct phy_device *phydev; | |
471 | int ret; | |
472 | ||
473 | if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { | |
474 | /* | |
475 | * Internal or external PHY with MDIO access | |
476 | */ | |
477 | if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) | |
478 | mdio->phy_mask = ~(1 << pd->phy_address); | |
479 | else | |
480 | mdio->phy_mask = 0; | |
481 | ||
482 | ret = mdiobus_register(mdio); | |
483 | if (ret) { | |
484 | dev_err(kdev, "failed to register MDIO bus\n"); | |
485 | return ret; | |
486 | } | |
487 | ||
488 | if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) | |
489 | phydev = mdio->phy_map[pd->phy_address]; | |
490 | else | |
491 | phydev = phy_find_first(mdio); | |
492 | ||
493 | if (!phydev) { | |
494 | dev_err(kdev, "failed to register PHY device\n"); | |
495 | mdiobus_unregister(mdio); | |
496 | return -ENODEV; | |
497 | } | |
498 | } else { | |
499 | /* | |
500 | * MoCA port or no MDIO access. | |
501 | * Use fixed PHY to represent the link layer. | |
502 | */ | |
503 | struct fixed_phy_status fphy_status = { | |
504 | .link = 1, | |
505 | .speed = pd->phy_speed, | |
506 | .duplex = pd->phy_duplex, | |
507 | .pause = 0, | |
508 | .asym_pause = 0, | |
509 | }; | |
510 | ||
511 | phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); | |
512 | if (!phydev || IS_ERR(phydev)) { | |
513 | dev_err(kdev, "failed to register fixed PHY device\n"); | |
514 | return -ENODEV; | |
515 | } | |
516 | } | |
517 | ||
518 | priv->phydev = phydev; | |
519 | priv->phy_interface = pd->phy_interface; | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
524 | static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) | |
525 | { | |
526 | struct device_node *dn = priv->pdev->dev.of_node; | |
527 | ||
528 | if (dn) | |
529 | return bcmgenet_mii_of_init(priv); | |
530 | else | |
531 | return bcmgenet_mii_pd_init(priv); | |
532 | } | |
533 | ||
aa09677c FF |
534 | int bcmgenet_mii_init(struct net_device *dev) |
535 | { | |
536 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
537 | int ret; | |
538 | ||
539 | ret = bcmgenet_mii_alloc(priv); | |
540 | if (ret) | |
541 | return ret; | |
542 | ||
b0ba512e | 543 | ret = bcmgenet_mii_bus_init(priv); |
aa09677c FF |
544 | if (ret) |
545 | goto out_free; | |
546 | ||
547 | ret = bcmgenet_mii_probe(dev); | |
548 | if (ret) | |
549 | goto out; | |
550 | ||
551 | return 0; | |
552 | ||
553 | out: | |
9518259f | 554 | of_node_put(priv->phy_dn); |
aa09677c FF |
555 | mdiobus_unregister(priv->mii_bus); |
556 | out_free: | |
557 | kfree(priv->mii_bus->irq); | |
558 | mdiobus_free(priv->mii_bus); | |
559 | return ret; | |
560 | } | |
561 | ||
562 | void bcmgenet_mii_exit(struct net_device *dev) | |
563 | { | |
564 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
565 | ||
9518259f | 566 | of_node_put(priv->phy_dn); |
aa09677c FF |
567 | mdiobus_unregister(priv->mii_bus); |
568 | kfree(priv->mii_bus->irq); | |
569 | mdiobus_free(priv->mii_bus); | |
570 | } |