[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmmii.c

/*
 * Broadcom GENET MDIO routines
 *
 * Copyright (c) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */


#include <linux/types.h>
#include <linux/delay.h>
#include <linux/wait.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/bitops.h>
#include <linux/netdevice.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/brcmphy.h>
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>

#include "bcmgenet.h"

/* read a value from the MII */
static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
{
	int ret;
	struct net_device *dev = bus->priv;
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg;

	bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
			     (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
	/* Start MDIO transaction*/
	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	reg |= MDIO_START_BUSY;
	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	wait_event_timeout(priv->wq,
			   !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
			   & MDIO_START_BUSY),
			   HZ / 100);
	ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);

	if (ret & MDIO_READ_FAIL)
		return -EIO;

	return ret & 0xffff;
}

/* write a value to the MII */
static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
			      int location, u16 val)
{
	struct net_device *dev = bus->priv;
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg;

	bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
			     (location << MDIO_REG_SHIFT) | (0xffff & val)),
			     UMAC_MDIO_CMD);
	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	reg |= MDIO_START_BUSY;
	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	wait_event_timeout(priv->wq,
			   !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
			   MDIO_START_BUSY),
			   HZ / 100);

	return 0;
}

/* setup netdev link state when PHY link status change and
 * update UMAC and RGMII block when link up
 */
void bcmgenet_mii_setup(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct phy_device *phydev = priv->phydev;
	u32 reg, cmd_bits = 0;
	bool status_changed = false;

	if (priv->old_link != phydev->link) {
		status_changed = true;
		priv->old_link = phydev->link;
	}

	if (phydev->link) {
		/* check speed/duplex/pause changes */
		if (priv->old_speed != phydev->speed) {
			status_changed = true;
			priv->old_speed = phydev->speed;
		}

		if (priv->old_duplex != phydev->duplex) {
			status_changed = true;
			priv->old_duplex = phydev->duplex;
		}

		if (priv->old_pause != phydev->pause) {
			status_changed = true;
			priv->old_pause = phydev->pause;
		}

		/* done if nothing has changed */
		if (!status_changed)
			return;

		/* speed */
		if (phydev->speed == SPEED_1000)
			cmd_bits = UMAC_SPEED_1000;
		else if (phydev->speed == SPEED_100)
			cmd_bits = UMAC_SPEED_100;
		else
			cmd_bits = UMAC_SPEED_10;
		cmd_bits <<= CMD_SPEED_SHIFT;

		/* duplex */
		if (phydev->duplex != DUPLEX_FULL)
			cmd_bits |= CMD_HD_EN;

		/* pause capability */
		if (!phydev->pause)
			cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;

		/*
		 * Program UMAC and RGMII block based on established
		 * link speed, duplex, and pause. The speed set in
		 * umac->cmd tell RGMII block which clock to use for
		 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
		 * Receive clock is provided by the PHY.
		 */
		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
		reg &= ~OOB_DISABLE;
		reg |= RGMII_LINK;
		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);

		reg = bcmgenet_umac_readl(priv, UMAC_CMD);
		reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
			       CMD_HD_EN |
			       CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
		reg |= cmd_bits;
		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
	} else {
		/* done if nothing has changed */
		if (!status_changed)
			return;

		/* needed for MoCA fixed PHY to reflect correct link status */
		netif_carrier_off(dev);
	}

	phy_print_status(phydev);
}

void bcmgenet_mii_reset(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);

	if (priv->phydev) {
		phy_init_hw(priv->phydev);
		phy_start_aneg(priv->phydev);
	}
}

static void bcmgenet_ephy_power_up(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg = 0;

	/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
	if (!GENET_IS_V4(priv))
		return;

	reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
	reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
	reg |= EXT_GPHY_RESET;
	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
	mdelay(2);

	reg &= ~EXT_GPHY_RESET;
	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
	udelay(20);
}

static void bcmgenet_internal_phy_setup(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg;

	/* Power up EPHY */
	bcmgenet_ephy_power_up(dev);
	/* enable APD */
	reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
	reg |= EXT_PWR_DN_EN_LD;
	bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
	bcmgenet_mii_reset(dev);
}

static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
{
	u32 reg;

	/* Speed settings are set in bcmgenet_mii_setup() */
	reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
	reg |= LED_ACT_SOURCE_MAC;
	bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
}

int bcmgenet_mii_config(struct net_device *dev, bool init)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct phy_device *phydev = priv->phydev;
	struct device *kdev = &priv->pdev->dev;
	const char *phy_name = NULL;
	u32 id_mode_dis = 0;
	u32 port_ctrl;
	u32 reg;

	priv->ext_phy = !phy_is_internal(priv->phydev) &&
			(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);

	if (phy_is_internal(priv->phydev))
		priv->phy_interface = PHY_INTERFACE_MODE_NA;

	switch (priv->phy_interface) {
	case PHY_INTERFACE_MODE_NA:
	case PHY_INTERFACE_MODE_MOCA:
		/* Irrespective of the actually configured PHY speed (100 or
		 * 1000) GENETv4 only has an internal GPHY so we will just end
		 * up masking the Gigabit features from what we support, not
		 * switching to the EPHY
		 */
		if (GENET_IS_V4(priv))
			port_ctrl = PORT_MODE_INT_GPHY;
		else
			port_ctrl = PORT_MODE_INT_EPHY;

		bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);

		if (phy_is_internal(priv->phydev)) {
			phy_name = "internal PHY";
			bcmgenet_internal_phy_setup(dev);
		} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
			phy_name = "MoCA";
			bcmgenet_moca_phy_setup(priv);
		}
		break;

	case PHY_INTERFACE_MODE_MII:
		phy_name = "external MII";
		phydev->supported &= PHY_BASIC_FEATURES;
		bcmgenet_sys_writel(priv,
				    PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
		break;

	case PHY_INTERFACE_MODE_REVMII:
		phy_name = "external RvMII";
		/* of_mdiobus_register took care of reading the 'max-speed'
		 * PHY property for us, effectively limiting the PHY supported
		 * capabilities, use that knowledge to also configure the
		 * Reverse MII interface correctly.
		 */
		if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
				PHY_BASIC_FEATURES)
			port_ctrl = PORT_MODE_EXT_RVMII_25;
		else
			port_ctrl = PORT_MODE_EXT_RVMII_50;
		bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
		break;

	case PHY_INTERFACE_MODE_RGMII:
		/* RGMII_NO_ID: TXC transitions at the same time as TXD
		 *		(requires PCB or receiver-side delay)
		 * RGMII:	Add 2ns delay on TXC (90 degree shift)
		 *
		 * ID is implicitly disabled for 100Mbps (RG)MII operation.
		 */
		id_mode_dis = BIT(16);
		/* fall through */
	case PHY_INTERFACE_MODE_RGMII_TXID:
		if (id_mode_dis)
			phy_name = "external RGMII (no delay)";
		else
			phy_name = "external RGMII (TX delay)";
		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
		reg |= RGMII_MODE_EN | id_mode_dis;
		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
		bcmgenet_sys_writel(priv,
				    PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
		break;
	default:
		dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
		return -EINVAL;
	}

	if (init)
		dev_info(kdev, "configuring instance for %s\n", phy_name);

	return 0;
}

static int bcmgenet_mii_probe(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct device_node *dn = priv->pdev->dev.of_node;
	struct phy_device *phydev;
	u32 phy_flags;
	int ret;

	if (priv->phydev) {
		pr_info("PHY already attached\n");
		return 0;
	}

	/* In the case of a fixed PHY, the DT node associated
	 * to the PHY is the Ethernet MAC DT node.
	 */
	if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
		ret = of_phy_register_fixed_link(dn);
		if (ret)
			return ret;

		priv->phy_dn = of_node_get(dn);
	}

	/* Communicate the integrated PHY revision */
	phy_flags = priv->gphy_rev;

	/* Initialize link state variables that bcmgenet_mii_setup() uses */
	priv->old_link = -1;
	priv->old_speed = -1;
	priv->old_duplex = -1;
	priv->old_pause = -1;

	phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
				phy_flags, priv->phy_interface);
	if (!phydev) {
		pr_err("could not attach to PHY\n");
		return -ENODEV;
	}

	priv->phydev = phydev;

	/* Configure port multiplexer based on what the probed PHY device since
	 * reading the 'max-speed' property determines the maximum supported
	 * PHY speed which is needed for bcmgenet_mii_config() to configure
	 * things appropriately.
	 */
	ret = bcmgenet_mii_config(dev, true);
	if (ret) {
		phy_disconnect(priv->phydev);
		return ret;
	}

	phydev->advertising = phydev->supported;

	/* The internal PHY has its link interrupts routed to the
	 * Ethernet MAC ISRs
	 */
	if (phy_is_internal(priv->phydev))
		priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
	else
		priv->mii_bus->irq[phydev->addr] = PHY_POLL;

	pr_info("attached PHY at address %d [%s]\n",
		phydev->addr, phydev->drv->name);

	return 0;
}

static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
{
	struct mii_bus *bus;

	if (priv->mii_bus)
		return 0;

	priv->mii_bus = mdiobus_alloc();
	if (!priv->mii_bus) {
		pr_err("failed to allocate\n");
		return -ENOMEM;
	}

	bus = priv->mii_bus;
	bus->priv = priv->dev;
	bus->name = "bcmgenet MII bus";
	bus->parent = &priv->pdev->dev;
	bus->read = bcmgenet_mii_read;
	bus->write = bcmgenet_mii_write;
	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
		 priv->pdev->name, priv->pdev->id);

	bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
	if (!bus->irq) {
		mdiobus_free(priv->mii_bus);
		return -ENOMEM;
	}

	return 0;
}

static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
{
	struct device_node *dn = priv->pdev->dev.of_node;
	struct device *kdev = &priv->pdev->dev;
	struct device_node *mdio_dn;
	char *compat;
	int ret;

	compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
	if (!compat)
		return -ENOMEM;

	mdio_dn = of_find_compatible_node(dn, NULL, compat);
	kfree(compat);
	if (!mdio_dn) {
		dev_err(kdev, "unable to find MDIO bus node\n");
		return -ENODEV;
	}

	ret = of_mdiobus_register(priv->mii_bus, mdio_dn);
	if (ret) {
		dev_err(kdev, "failed to register MDIO bus\n");
		return ret;
	}

	/* Fetch the PHY phandle */
	priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);

	/* Get the link mode */
	priv->phy_interface = of_get_phy_mode(dn);

	return 0;
}

int bcmgenet_mii_init(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	int ret;

	ret = bcmgenet_mii_alloc(priv);
	if (ret)
		return ret;

	ret = bcmgenet_mii_of_init(priv);
	if (ret)
		goto out_free;

	ret = bcmgenet_mii_probe(dev);
	if (ret)
		goto out;

	return 0;

out:
	of_node_put(priv->phy_dn);
	mdiobus_unregister(priv->mii_bus);
out_free:
	kfree(priv->mii_bus->irq);
	mdiobus_free(priv->mii_bus);
	return ret;
}

void bcmgenet_mii_exit(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);

	of_node_put(priv->phy_dn);
	mdiobus_unregister(priv->mii_bus);
	kfree(priv->mii_bus->irq);
	mdiobus_free(priv->mii_bus);
}
Commit	Line	Data
aa09677c FF	1	/*
	2	* Broadcom GENET MDIO routines
	3	*
	4	* Copyright (c) 2014 Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
aa09677c FF	9	*/
	10
	11
	12	#include <linux/types.h>
	13	#include <linux/delay.h>
	14	#include <linux/wait.h>
	15	#include <linux/mii.h>
	16	#include <linux/ethtool.h>
	17	#include <linux/bitops.h>
	18	#include <linux/netdevice.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/phy.h>
	21	#include <linux/phy_fixed.h>
	22	#include <linux/brcmphy.h>
	23	#include <linux/of.h>
	24	#include <linux/of_net.h>
	25	#include <linux/of_mdio.h>
	26
	27	#include "bcmgenet.h"
	28
	29	/* read a value from the MII */
	30	static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
	31	{
	32	int ret;
	33	struct net_device *dev = bus->priv;
	34	struct bcmgenet_priv *priv = netdev_priv(dev);
	35	u32 reg;
	36
	37	bcmgenet_umac_writel(priv, (MDIO_RD \| (phy_id << MDIO_PMD_SHIFT) \|
c91b7f66	38	(location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
aa09677c FF	39	/* Start MDIO transaction*/
	40	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	41	reg \|= MDIO_START_BUSY;
	42	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	43	wait_event_timeout(priv->wq,
c91b7f66 FF	44	!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
	45	& MDIO_START_BUSY),
	46	HZ / 100);
aa09677c FF	47	ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	48
	49	if (ret & MDIO_READ_FAIL)
	50	return -EIO;
	51
	52	return ret & 0xffff;
	53	}
	54
	55	/* write a value to the MII */
	56	static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
c91b7f66	57	int location, u16 val)
aa09677c FF	58	{
	59	struct net_device *dev = bus->priv;
	60	struct bcmgenet_priv *priv = netdev_priv(dev);
	61	u32 reg;
	62
	63	bcmgenet_umac_writel(priv, (MDIO_WR \| (phy_id << MDIO_PMD_SHIFT) \|
c91b7f66 FF	64	(location << MDIO_REG_SHIFT) \| (0xffff & val)),
c91b7f66 FF	65	UMAC_MDIO_CMD);
aa09677c FF	66	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	67	reg \|= MDIO_START_BUSY;
	68	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	69	wait_event_timeout(priv->wq,
c91b7f66 FF	70	!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
	71	MDIO_START_BUSY),
	72	HZ / 100);
aa09677c FF	73
	74	return 0;
	75	}
	76
	77	/* setup netdev link state when PHY link status change and
	78	* update UMAC and RGMII block when link up
	79	*/
c96e731c	80	void bcmgenet_mii_setup(struct net_device *dev)
aa09677c FF	81	{
	82	struct bcmgenet_priv *priv = netdev_priv(dev);
	83	struct phy_device *phydev = priv->phydev;
	84	u32 reg, cmd_bits = 0;
5ad6e6c5	85	bool status_changed = false;
aa09677c FF	86
aa09677c FF	87	if (priv->old_link != phydev->link) {
5ad6e6c5	88	status_changed = true;
aa09677c FF	89	priv->old_link = phydev->link;
	90	}
	91
	92	if (phydev->link) {
5ad6e6c5 PG	93	/* check speed/duplex/pause changes */
	94	if (priv->old_speed != phydev->speed) {
	95	status_changed = true;
	96	priv->old_speed = phydev->speed;
	97	}
	98
	99	if (priv->old_duplex != phydev->duplex) {
	100	status_changed = true;
	101	priv->old_duplex = phydev->duplex;
	102	}
	103
	104	if (priv->old_pause != phydev->pause) {
	105	status_changed = true;
	106	priv->old_pause = phydev->pause;
	107	}
	108
	109	/* done if nothing has changed */
	110	if (!status_changed)
	111	return;
aa09677c FF	112
	113	/* speed */
	114	if (phydev->speed == SPEED_1000)
	115	cmd_bits = UMAC_SPEED_1000;
	116	else if (phydev->speed == SPEED_100)
	117	cmd_bits = UMAC_SPEED_100;
	118	else
	119	cmd_bits = UMAC_SPEED_10;
	120	cmd_bits <<= CMD_SPEED_SHIFT;
	121
aa09677c FF	122	/* duplex */
	123	if (phydev->duplex != DUPLEX_FULL)
	124	cmd_bits \|= CMD_HD_EN;
	125
aa09677c FF	126	/* pause capability */
	127	if (!phydev->pause)
	128	cmd_bits \|= CMD_RX_PAUSE_IGNORE \| CMD_TX_PAUSE_IGNORE;
	129
5ad6e6c5 PG	130	/*
	131	* Program UMAC and RGMII block based on established
	132	* link speed, duplex, and pause. The speed set in
	133	* umac->cmd tell RGMII block which clock to use for
	134	* transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
	135	* Receive clock is provided by the PHY.
	136	*/
	137	reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
	138	reg &= ~OOB_DISABLE;
	139	reg \|= RGMII_LINK;
	140	bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
c677ba8b	141
aa09677c FF	142	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
	143	reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) \|
	144	CMD_HD_EN \|
	145	CMD_RX_PAUSE_IGNORE \| CMD_TX_PAUSE_IGNORE);
	146	reg \|= cmd_bits;
	147	bcmgenet_umac_writel(priv, reg, UMAC_CMD);
5ad6e6c5 PG	148	} else {
	149	/* done if nothing has changed */
	150	if (!status_changed)
	151	return;
aa09677c	152
5ad6e6c5 PG	153	/* needed for MoCA fixed PHY to reflect correct link status */
5ad6e6c5 PG	154	netif_carrier_off(dev);
24052408	155	}
c677ba8b FF	156
c677ba8b FF	157	phy_print_status(phydev);
aa09677c FF	158	}
	159
	160	void bcmgenet_mii_reset(struct net_device *dev)
	161	{
	162	struct bcmgenet_priv *priv = netdev_priv(dev);
	163
	164	if (priv->phydev) {
	165	phy_init_hw(priv->phydev);
	166	phy_start_aneg(priv->phydev);
	167	}
	168	}
	169
	170	static void bcmgenet_ephy_power_up(struct net_device *dev)
	171	{
	172	struct bcmgenet_priv *priv = netdev_priv(dev);
	173	u32 reg = 0;
	174
	175	/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
	176	if (!GENET_IS_V4(priv))
	177	return;
	178
	179	reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
	180	reg &= ~(EXT_CFG_IDDQ_BIAS \| EXT_CFG_PWR_DOWN);
	181	reg \|= EXT_GPHY_RESET;
	182	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
	183	mdelay(2);
	184
	185	reg &= ~EXT_GPHY_RESET;
	186	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
	187	udelay(20);
	188	}
	189
	190	static void bcmgenet_internal_phy_setup(struct net_device *dev)
	191	{
	192	struct bcmgenet_priv *priv = netdev_priv(dev);
	193	u32 reg;
	194
	195	/* Power up EPHY */
	196	bcmgenet_ephy_power_up(dev);
	197	/* enable APD */
	198	reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
	199	reg \|= EXT_PWR_DN_EN_LD;
	200	bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
	201	bcmgenet_mii_reset(dev);
	202	}
	203
	204	static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
	205	{
	206	u32 reg;
	207
	208	/* Speed settings are set in bcmgenet_mii_setup() */
	209	reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
	210	reg \|= LED_ACT_SOURCE_MAC;
	211	bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
	212	}
	213
dbd479db	214	int bcmgenet_mii_config(struct net_device *dev, bool init)
aa09677c FF	215	{
	216	struct bcmgenet_priv *priv = netdev_priv(dev);
	217	struct phy_device *phydev = priv->phydev;
	218	struct device *kdev = &priv->pdev->dev;
	219	const char *phy_name = NULL;
	220	u32 id_mode_dis = 0;
	221	u32 port_ctrl;
	222	u32 reg;
	223
	224	priv->ext_phy = !phy_is_internal(priv->phydev) &&
	225	(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
	226
	227	if (phy_is_internal(priv->phydev))
	228	priv->phy_interface = PHY_INTERFACE_MODE_NA;
	229
	230	switch (priv->phy_interface) {
	231	case PHY_INTERFACE_MODE_NA:
	232	case PHY_INTERFACE_MODE_MOCA:
	233	/* Irrespective of the actually configured PHY speed (100 or
	234	* 1000) GENETv4 only has an internal GPHY so we will just end
	235	* up masking the Gigabit features from what we support, not
	236	* switching to the EPHY
	237	*/
	238	if (GENET_IS_V4(priv))
	239	port_ctrl = PORT_MODE_INT_GPHY;
	240	else
	241	port_ctrl = PORT_MODE_INT_EPHY;
	242
	243	bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
	244
	245	if (phy_is_internal(priv->phydev)) {
	246	phy_name = "internal PHY";
	247	bcmgenet_internal_phy_setup(dev);
	248	} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
	249	phy_name = "MoCA";
	250	bcmgenet_moca_phy_setup(priv);
	251	}
	252	break;
	253
	254	case PHY_INTERFACE_MODE_MII:
	255	phy_name = "external MII";
	256	phydev->supported &= PHY_BASIC_FEATURES;
	257	bcmgenet_sys_writel(priv,
c91b7f66	258	PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
aa09677c FF	259	break;
	260
	261	case PHY_INTERFACE_MODE_REVMII:
	262	phy_name = "external RvMII";
	263	/* of_mdiobus_register took care of reading the 'max-speed'
	264	* PHY property for us, effectively limiting the PHY supported
	265	* capabilities, use that knowledge to also configure the
	266	* Reverse MII interface correctly.
	267	*/
	268	if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
	269	PHY_BASIC_FEATURES)
	270	port_ctrl = PORT_MODE_EXT_RVMII_25;
	271	else
	272	port_ctrl = PORT_MODE_EXT_RVMII_50;
	273	bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
	274	break;
	275
	276	case PHY_INTERFACE_MODE_RGMII:
	277	/* RGMII_NO_ID: TXC transitions at the same time as TXD
	278	* (requires PCB or receiver-side delay)
	279	* RGMII: Add 2ns delay on TXC (90 degree shift)
	280	*
	281	* ID is implicitly disabled for 100Mbps (RG)MII operation.
	282	*/
	283	id_mode_dis = BIT(16);
	284	/* fall through */
	285	case PHY_INTERFACE_MODE_RGMII_TXID:
	286	if (id_mode_dis)
	287	phy_name = "external RGMII (no delay)";
	288	else
	289	phy_name = "external RGMII (TX delay)";
	290	reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
	291	reg \|= RGMII_MODE_EN \| id_mode_dis;
	292	bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
	293	bcmgenet_sys_writel(priv,
c91b7f66	294	PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
aa09677c FF	295	break;
	296	default:
	297	dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
	298	return -EINVAL;
	299	}
	300
dbd479db FF	301	if (init)
dbd479db FF	302	dev_info(kdev, "configuring instance for %s\n", phy_name);
aa09677c FF	303
	304	return 0;
	305	}
	306
	307	static int bcmgenet_mii_probe(struct net_device *dev)
	308	{
	309	struct bcmgenet_priv *priv = netdev_priv(dev);
9abf0c2b	310	struct device_node *dn = priv->pdev->dev.of_node;
aa09677c	311	struct phy_device *phydev;
487320c5	312	u32 phy_flags;
aa09677c FF	313	int ret;
	314
	315	if (priv->phydev) {
	316	pr_info("PHY already attached\n");
	317	return 0;
	318	}
	319
9abf0c2b FF	320	/* In the case of a fixed PHY, the DT node associated
	321	* to the PHY is the Ethernet MAC DT node.
	322	*/
9518259f	323	if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
9abf0c2b FF	324	ret = of_phy_register_fixed_link(dn);
	325	if (ret)
	326	return ret;
aa09677c	327
9518259f	328	priv->phy_dn = of_node_get(dn);
9abf0c2b FF	329	}
9abf0c2b FF	330
487320c5 FF	331	/* Communicate the integrated PHY revision */
	332	phy_flags = priv->gphy_rev;
	333
5ad6e6c5 PG	334	/* Initialize link state variables that bcmgenet_mii_setup() uses */
	335	priv->old_link = -1;
	336	priv->old_speed = -1;
	337	priv->old_duplex = -1;
	338	priv->old_pause = -1;
	339
487320c5 FF	340	phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
487320c5 FF	341	phy_flags, priv->phy_interface);
aa09677c FF	342	if (!phydev) {
	343	pr_err("could not attach to PHY\n");
	344	return -ENODEV;
	345	}
	346
aa09677c FF	347	priv->phydev = phydev;
	348
	349	/* Configure port multiplexer based on what the probed PHY device since
	350	* reading the 'max-speed' property determines the maximum supported
	351	* PHY speed which is needed for bcmgenet_mii_config() to configure
	352	* things appropriately.
	353	*/
dbd479db	354	ret = bcmgenet_mii_config(dev, true);
aa09677c FF	355	if (ret) {
	356	phy_disconnect(priv->phydev);
	357	return ret;
	358	}
	359
aa09677c FF	360	phydev->advertising = phydev->supported;
	361
	362	/* The internal PHY has its link interrupts routed to the
	363	* Ethernet MAC ISRs
	364	*/
	365	if (phy_is_internal(priv->phydev))
	366	priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
	367	else
	368	priv->mii_bus->irq[phydev->addr] = PHY_POLL;
	369
	370	pr_info("attached PHY at address %d [%s]\n",
c91b7f66	371	phydev->addr, phydev->drv->name);
aa09677c FF	372
	373	return 0;
	374	}
	375
	376	static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
	377	{
	378	struct mii_bus *bus;
	379
	380	if (priv->mii_bus)
	381	return 0;
	382
	383	priv->mii_bus = mdiobus_alloc();
	384	if (!priv->mii_bus) {
	385	pr_err("failed to allocate\n");
	386	return -ENOMEM;
	387	}
	388
	389	bus = priv->mii_bus;
	390	bus->priv = priv->dev;
	391	bus->name = "bcmgenet MII bus";
	392	bus->parent = &priv->pdev->dev;
	393	bus->read = bcmgenet_mii_read;
	394	bus->write = bcmgenet_mii_write;
	395	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
c91b7f66	396	priv->pdev->name, priv->pdev->id);
aa09677c	397
c489be08	398	bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
aa09677c FF	399	if (!bus->irq) {
	400	mdiobus_free(priv->mii_bus);
	401	return -ENOMEM;
	402	}
	403
	404	return 0;
	405	}
	406
	407	static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
	408	{
	409	struct device_node *dn = priv->pdev->dev.of_node;
	410	struct device *kdev = &priv->pdev->dev;
	411	struct device_node *mdio_dn;
	412	char *compat;
	413	int ret;
	414
	415	compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
	416	if (!compat)
	417	return -ENOMEM;
	418
	419	mdio_dn = of_find_compatible_node(dn, NULL, compat);
	420	kfree(compat);
	421	if (!mdio_dn) {
	422	dev_err(kdev, "unable to find MDIO bus node\n");
	423	return -ENODEV;
	424	}
	425
	426	ret = of_mdiobus_register(priv->mii_bus, mdio_dn);
	427	if (ret) {
	428	dev_err(kdev, "failed to register MDIO bus\n");
	429	return ret;
	430	}
	431
	432	/* Fetch the PHY phandle */
	433	priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
	434
	435	/* Get the link mode */
	436	priv->phy_interface = of_get_phy_mode(dn);
	437
	438	return 0;
	439	}
	440
	441	int bcmgenet_mii_init(struct net_device *dev)
	442	{
	443	struct bcmgenet_priv *priv = netdev_priv(dev);
	444	int ret;
	445
	446	ret = bcmgenet_mii_alloc(priv);
	447	if (ret)
	448	return ret;
	449
	450	ret = bcmgenet_mii_of_init(priv);
	451	if (ret)
	452	goto out_free;
	453
	454	ret = bcmgenet_mii_probe(dev);
	455	if (ret)
	456	goto out;
	457
	458	return 0;
	459
	460	out:
9518259f	461	of_node_put(priv->phy_dn);
aa09677c FF	462	mdiobus_unregister(priv->mii_bus);
	463	out_free:
	464	kfree(priv->mii_bus->irq);
	465	mdiobus_free(priv->mii_bus);
	466	return ret;
	467	}
	468
	469	void bcmgenet_mii_exit(struct net_device *dev)
	470	{
	471	struct bcmgenet_priv *priv = netdev_priv(dev);
	472
9518259f	473	of_node_put(priv->phy_dn);
aa09677c FF	474	mdiobus_unregister(priv->mii_bus);
	475	kfree(priv->mii_bus->irq);
	476	mdiobus_free(priv->mii_bus);
	477	}