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1da177e4 | 1 | /* |
f90fdc3c | 2 | * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation |
f5279ffd | 3 | * Copyright (c) 2006, 2007 Maciej W. Rozycki |
1da177e4 LT |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
74b0247f | 14 | * |
1da177e4 | 15 | * You should have received a copy of the GNU General Public License |
0ab75ae8 | 16 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 LT |
17 | * |
18 | * | |
19 | * This driver is designed for the Broadcom SiByte SOC built-in | |
20 | * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp. | |
f5279ffd MR |
21 | * |
22 | * Updated to the driver model and the PHY abstraction layer | |
23 | * by Maciej W. Rozycki. | |
1da177e4 | 24 | */ |
f5279ffd MR |
25 | |
26 | #include <linux/bug.h> | |
1da177e4 LT |
27 | #include <linux/module.h> |
28 | #include <linux/kernel.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/timer.h> | |
31 | #include <linux/errno.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
1da177e4 | 38 | #include <linux/bitops.h> |
f5279ffd MR |
39 | #include <linux/err.h> |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
42 | #include <linux/phy.h> | |
43 | #include <linux/platform_device.h> | |
70c71606 | 44 | #include <linux/prefetch.h> |
f5279ffd | 45 | |
1da177e4 | 46 | #include <asm/cache.h> |
f5279ffd MR |
47 | #include <asm/io.h> |
48 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
1da177e4 | 49 | |
1da177e4 LT |
50 | /* Operational parameters that usually are not changed. */ |
51 | ||
52 | #define CONFIG_SBMAC_COALESCE | |
53 | ||
1da177e4 LT |
54 | /* Time in jiffies before concluding the transmitter is hung. */ |
55 | #define TX_TIMEOUT (2*HZ) | |
56 | ||
57 | ||
58 | MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)"); | |
59 | MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver"); | |
60 | ||
61 | /* A few user-configurable values which may be modified when a driver | |
62 | module is loaded. */ | |
63 | ||
64 | /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
65 | static int debug = 1; | |
66 | module_param(debug, int, S_IRUGO); | |
67 | MODULE_PARM_DESC(debug, "Debug messages"); | |
68 | ||
1da177e4 | 69 | #ifdef CONFIG_SBMAC_COALESCE |
693aa947 MM |
70 | static int int_pktcnt_tx = 255; |
71 | module_param(int_pktcnt_tx, int, S_IRUGO); | |
72 | MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count"); | |
1da177e4 | 73 | |
693aa947 MM |
74 | static int int_timeout_tx = 255; |
75 | module_param(int_timeout_tx, int, S_IRUGO); | |
76 | MODULE_PARM_DESC(int_timeout_tx, "TX timeout value"); | |
77 | ||
78 | static int int_pktcnt_rx = 64; | |
79 | module_param(int_pktcnt_rx, int, S_IRUGO); | |
80 | MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count"); | |
81 | ||
82 | static int int_timeout_rx = 64; | |
83 | module_param(int_timeout_rx, int, S_IRUGO); | |
84 | MODULE_PARM_DESC(int_timeout_rx, "RX timeout value"); | |
1da177e4 LT |
85 | #endif |
86 | ||
f5279ffd | 87 | #include <asm/sibyte/board.h> |
1da177e4 | 88 | #include <asm/sibyte/sb1250.h> |
f90fdc3c RB |
89 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
90 | #include <asm/sibyte/bcm1480_regs.h> | |
91 | #include <asm/sibyte/bcm1480_int.h> | |
693aa947 | 92 | #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST |
f90fdc3c | 93 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) |
1da177e4 | 94 | #include <asm/sibyte/sb1250_regs.h> |
1da177e4 | 95 | #include <asm/sibyte/sb1250_int.h> |
f90fdc3c | 96 | #else |
0b1974de | 97 | #error invalid SiByte MAC configuration |
f90fdc3c | 98 | #endif |
1da177e4 | 99 | #include <asm/sibyte/sb1250_scd.h> |
f90fdc3c RB |
100 | #include <asm/sibyte/sb1250_mac.h> |
101 | #include <asm/sibyte/sb1250_dma.h> | |
1da177e4 | 102 | |
f90fdc3c RB |
103 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
104 | #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2)) | |
105 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) | |
106 | #define UNIT_INT(n) (K_INT_MAC_0 + (n)) | |
107 | #else | |
0b1974de | 108 | #error invalid SiByte MAC configuration |
f90fdc3c | 109 | #endif |
1da177e4 | 110 | |
f5279ffd MR |
111 | #ifdef K_INT_PHY |
112 | #define SBMAC_PHY_INT K_INT_PHY | |
113 | #else | |
114 | #define SBMAC_PHY_INT PHY_POLL | |
115 | #endif | |
116 | ||
1da177e4 LT |
117 | /********************************************************************** |
118 | * Simple types | |
119 | ********************************************************************* */ | |
120 | ||
f5279ffd MR |
121 | enum sbmac_speed { |
122 | sbmac_speed_none = 0, | |
123 | sbmac_speed_10 = SPEED_10, | |
124 | sbmac_speed_100 = SPEED_100, | |
125 | sbmac_speed_1000 = SPEED_1000, | |
126 | }; | |
1da177e4 | 127 | |
f5279ffd MR |
128 | enum sbmac_duplex { |
129 | sbmac_duplex_none = -1, | |
130 | sbmac_duplex_half = DUPLEX_HALF, | |
131 | sbmac_duplex_full = DUPLEX_FULL, | |
132 | }; | |
1da177e4 | 133 | |
f5279ffd MR |
134 | enum sbmac_fc { |
135 | sbmac_fc_none, | |
136 | sbmac_fc_disabled, | |
137 | sbmac_fc_frame, | |
138 | sbmac_fc_collision, | |
139 | sbmac_fc_carrier, | |
140 | }; | |
1da177e4 | 141 | |
f5279ffd MR |
142 | enum sbmac_state { |
143 | sbmac_state_uninit, | |
144 | sbmac_state_off, | |
145 | sbmac_state_on, | |
146 | sbmac_state_broken, | |
147 | }; | |
1da177e4 LT |
148 | |
149 | ||
150 | /********************************************************************** | |
151 | * Macros | |
152 | ********************************************************************* */ | |
153 | ||
154 | ||
155 | #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ | |
156 | (d)->sbdma_dscrtable : (d)->f+1) | |
157 | ||
158 | ||
159 | #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES) | |
160 | ||
693aa947 MM |
161 | #define SBMAC_MAX_TXDESCR 256 |
162 | #define SBMAC_MAX_RXDESCR 256 | |
1da177e4 | 163 | |
74b0247f RB |
164 | #define ENET_PACKET_SIZE 1518 |
165 | /*#define ENET_PACKET_SIZE 9216 */ | |
1da177e4 LT |
166 | |
167 | /********************************************************************** | |
168 | * DMA Descriptor structure | |
169 | ********************************************************************* */ | |
170 | ||
73d73969 | 171 | struct sbdmadscr { |
1da177e4 LT |
172 | uint64_t dscr_a; |
173 | uint64_t dscr_b; | |
73d73969 | 174 | }; |
1da177e4 LT |
175 | |
176 | /********************************************************************** | |
177 | * DMA Controller structure | |
178 | ********************************************************************* */ | |
179 | ||
73d73969 | 180 | struct sbmacdma { |
74b0247f RB |
181 | |
182 | /* | |
1da177e4 LT |
183 | * This stuff is used to identify the channel and the registers |
184 | * associated with it. | |
185 | */ | |
73d73969 MR |
186 | struct sbmac_softc *sbdma_eth; /* back pointer to associated |
187 | MAC */ | |
188 | int sbdma_channel; /* channel number */ | |
189 | int sbdma_txdir; /* direction (1=transmit) */ | |
190 | int sbdma_maxdescr; /* total # of descriptors | |
191 | in ring */ | |
1da177e4 | 192 | #ifdef CONFIG_SBMAC_COALESCE |
73d73969 MR |
193 | int sbdma_int_pktcnt; |
194 | /* # descriptors rx/tx | |
195 | before interrupt */ | |
196 | int sbdma_int_timeout; | |
197 | /* # usec rx/tx interrupt */ | |
1da177e4 | 198 | #endif |
73d73969 MR |
199 | void __iomem *sbdma_config0; /* DMA config register 0 */ |
200 | void __iomem *sbdma_config1; /* DMA config register 1 */ | |
201 | void __iomem *sbdma_dscrbase; | |
202 | /* descriptor base address */ | |
203 | void __iomem *sbdma_dscrcnt; /* descriptor count register */ | |
204 | void __iomem *sbdma_curdscr; /* current descriptor | |
205 | address */ | |
206 | void __iomem *sbdma_oodpktlost; | |
207 | /* pkt drop (rx only) */ | |
74b0247f | 208 | |
1da177e4 LT |
209 | /* |
210 | * This stuff is for maintenance of the ring | |
211 | */ | |
73d73969 MR |
212 | void *sbdma_dscrtable_unaligned; |
213 | struct sbdmadscr *sbdma_dscrtable; | |
214 | /* base of descriptor table */ | |
215 | struct sbdmadscr *sbdma_dscrtable_end; | |
216 | /* end of descriptor table */ | |
217 | struct sk_buff **sbdma_ctxtable; | |
218 | /* context table, one | |
219 | per descr */ | |
220 | dma_addr_t sbdma_dscrtable_phys; | |
221 | /* and also the phys addr */ | |
222 | struct sbdmadscr *sbdma_addptr; /* next dscr for sw to add */ | |
223 | struct sbdmadscr *sbdma_remptr; /* next dscr for sw | |
224 | to remove */ | |
225 | }; | |
1da177e4 LT |
226 | |
227 | ||
228 | /********************************************************************** | |
229 | * Ethernet softc structure | |
230 | ********************************************************************* */ | |
231 | ||
232 | struct sbmac_softc { | |
74b0247f | 233 | |
1da177e4 LT |
234 | /* |
235 | * Linux-specific things | |
236 | */ | |
73d73969 MR |
237 | struct net_device *sbm_dev; /* pointer to linux device */ |
238 | struct napi_struct napi; | |
f5279ffd | 239 | struct phy_device *phy_dev; /* the associated PHY device */ |
298cf9be | 240 | struct mii_bus *mii_bus; /* the MII bus */ |
73d73969 | 241 | spinlock_t sbm_lock; /* spin lock */ |
73d73969 | 242 | int sbm_devflags; /* current device flags */ |
74b0247f | 243 | |
1da177e4 LT |
244 | /* |
245 | * Controller-specific things | |
246 | */ | |
73d73969 MR |
247 | void __iomem *sbm_base; /* MAC's base address */ |
248 | enum sbmac_state sbm_state; /* current state */ | |
74b0247f | 249 | |
73d73969 MR |
250 | void __iomem *sbm_macenable; /* MAC Enable Register */ |
251 | void __iomem *sbm_maccfg; /* MAC Config Register */ | |
252 | void __iomem *sbm_fifocfg; /* FIFO Config Register */ | |
253 | void __iomem *sbm_framecfg; /* Frame Config Register */ | |
254 | void __iomem *sbm_rxfilter; /* Receive Filter Register */ | |
255 | void __iomem *sbm_isr; /* Interrupt Status Register */ | |
256 | void __iomem *sbm_imr; /* Interrupt Mask Register */ | |
257 | void __iomem *sbm_mdio; /* MDIO Register */ | |
74b0247f | 258 | |
73d73969 MR |
259 | enum sbmac_speed sbm_speed; /* current speed */ |
260 | enum sbmac_duplex sbm_duplex; /* current duplex */ | |
261 | enum sbmac_fc sbm_fc; /* cur. flow control setting */ | |
f5279ffd MR |
262 | int sbm_pause; /* current pause setting */ |
263 | int sbm_link; /* current link state */ | |
74b0247f | 264 | |
104bf3fb | 265 | unsigned char sbm_hwaddr[ETH_ALEN]; |
74b0247f | 266 | |
73d73969 MR |
267 | struct sbmacdma sbm_txdma; /* only channel 0 for now */ |
268 | struct sbmacdma sbm_rxdma; | |
269 | int rx_hw_checksum; | |
270 | int sbe_idx; | |
1da177e4 LT |
271 | }; |
272 | ||
273 | ||
274 | /********************************************************************** | |
275 | * Externs | |
276 | ********************************************************************* */ | |
277 | ||
278 | /********************************************************************** | |
279 | * Prototypes | |
280 | ********************************************************************* */ | |
281 | ||
73d73969 MR |
282 | static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, |
283 | int txrx, int maxdescr); | |
284 | static void sbdma_channel_start(struct sbmacdma *d, int rxtx); | |
789585e9 SH |
285 | static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, |
286 | struct sk_buff *m); | |
73d73969 MR |
287 | static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m); |
288 | static void sbdma_emptyring(struct sbmacdma *d); | |
789585e9 | 289 | static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d); |
73d73969 MR |
290 | static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d, |
291 | int work_to_do, int poll); | |
292 | static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d, | |
293 | int poll); | |
1da177e4 LT |
294 | static int sbmac_initctx(struct sbmac_softc *s); |
295 | static void sbmac_channel_start(struct sbmac_softc *s); | |
296 | static void sbmac_channel_stop(struct sbmac_softc *s); | |
73d73969 MR |
297 | static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *, |
298 | enum sbmac_state); | |
299 | static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); | |
1da177e4 | 300 | static uint64_t sbmac_addr2reg(unsigned char *ptr); |
73d73969 | 301 | static irqreturn_t sbmac_intr(int irq, void *dev_instance); |
1da177e4 LT |
302 | static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); |
303 | static void sbmac_setmulti(struct sbmac_softc *sc); | |
f5279ffd | 304 | static int sbmac_init(struct platform_device *pldev, long long base); |
73d73969 MR |
305 | static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed); |
306 | static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, | |
307 | enum sbmac_fc fc); | |
1da177e4 LT |
308 | |
309 | static int sbmac_open(struct net_device *dev); | |
1da177e4 | 310 | static void sbmac_tx_timeout (struct net_device *dev); |
1da177e4 LT |
311 | static void sbmac_set_rx_mode(struct net_device *dev); |
312 | static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
313 | static int sbmac_close(struct net_device *dev); | |
bea3348e | 314 | static int sbmac_poll(struct napi_struct *napi, int budget); |
693aa947 | 315 | |
f5279ffd | 316 | static void sbmac_mii_poll(struct net_device *dev); |
59b81827 | 317 | static int sbmac_mii_probe(struct net_device *dev); |
1da177e4 | 318 | |
f5279ffd MR |
319 | static void sbmac_mii_sync(void __iomem *sbm_mdio); |
320 | static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data, | |
73d73969 | 321 | int bitcnt); |
f5279ffd MR |
322 | static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx); |
323 | static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, | |
324 | u16 val); | |
1da177e4 LT |
325 | |
326 | ||
327 | /********************************************************************** | |
328 | * Globals | |
329 | ********************************************************************* */ | |
330 | ||
f5279ffd | 331 | static char sbmac_string[] = "sb1250-mac"; |
f5279ffd MR |
332 | |
333 | static char sbmac_mdio_string[] = "sb1250-mac-mdio"; | |
1da177e4 LT |
334 | |
335 | ||
336 | /********************************************************************** | |
337 | * MDIO constants | |
338 | ********************************************************************* */ | |
339 | ||
340 | #define MII_COMMAND_START 0x01 | |
341 | #define MII_COMMAND_READ 0x02 | |
342 | #define MII_COMMAND_WRITE 0x01 | |
343 | #define MII_COMMAND_ACK 0x02 | |
344 | ||
1da177e4 LT |
345 | #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ |
346 | ||
347 | #define ENABLE 1 | |
348 | #define DISABLE 0 | |
349 | ||
350 | /********************************************************************** | |
f5279ffd | 351 | * SBMAC_MII_SYNC(sbm_mdio) |
74b0247f | 352 | * |
1da177e4 LT |
353 | * Synchronize with the MII - send a pattern of bits to the MII |
354 | * that will guarantee that it is ready to accept a command. | |
74b0247f RB |
355 | * |
356 | * Input parameters: | |
f5279ffd | 357 | * sbm_mdio - address of the MAC's MDIO register |
74b0247f | 358 | * |
1da177e4 LT |
359 | * Return value: |
360 | * nothing | |
361 | ********************************************************************* */ | |
362 | ||
f5279ffd | 363 | static void sbmac_mii_sync(void __iomem *sbm_mdio) |
1da177e4 LT |
364 | { |
365 | int cnt; | |
366 | uint64_t bits; | |
367 | int mac_mdio_genc; | |
368 | ||
f5279ffd | 369 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
74b0247f | 370 | |
1da177e4 | 371 | bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; |
74b0247f | 372 | |
f5279ffd | 373 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); |
74b0247f | 374 | |
1da177e4 | 375 | for (cnt = 0; cnt < 32; cnt++) { |
f5279ffd MR |
376 | __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); |
377 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); | |
1da177e4 LT |
378 | } |
379 | } | |
380 | ||
381 | /********************************************************************** | |
f5279ffd | 382 | * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt) |
74b0247f | 383 | * |
1da177e4 LT |
384 | * Send some bits to the MII. The bits to be sent are right- |
385 | * justified in the 'data' parameter. | |
74b0247f RB |
386 | * |
387 | * Input parameters: | |
f5279ffd MR |
388 | * sbm_mdio - address of the MAC's MDIO register |
389 | * data - data to send | |
390 | * bitcnt - number of bits to send | |
1da177e4 LT |
391 | ********************************************************************* */ |
392 | ||
f5279ffd MR |
393 | static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data, |
394 | int bitcnt) | |
1da177e4 LT |
395 | { |
396 | int i; | |
397 | uint64_t bits; | |
398 | unsigned int curmask; | |
399 | int mac_mdio_genc; | |
400 | ||
f5279ffd | 401 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
74b0247f | 402 | |
1da177e4 | 403 | bits = M_MAC_MDIO_DIR_OUTPUT; |
f5279ffd | 404 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); |
74b0247f | 405 | |
1da177e4 | 406 | curmask = 1 << (bitcnt - 1); |
74b0247f | 407 | |
1da177e4 LT |
408 | for (i = 0; i < bitcnt; i++) { |
409 | if (data & curmask) | |
410 | bits |= M_MAC_MDIO_OUT; | |
411 | else bits &= ~M_MAC_MDIO_OUT; | |
f5279ffd MR |
412 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); |
413 | __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); | |
414 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); | |
1da177e4 LT |
415 | curmask >>= 1; |
416 | } | |
417 | } | |
418 | ||
419 | ||
420 | ||
421 | /********************************************************************** | |
f5279ffd | 422 | * SBMAC_MII_READ(bus, phyaddr, regidx) |
1da177e4 | 423 | * Read a PHY register. |
74b0247f RB |
424 | * |
425 | * Input parameters: | |
f5279ffd | 426 | * bus - MDIO bus handle |
1da177e4 | 427 | * phyaddr - PHY's address |
f5279ffd | 428 | * regnum - index of register to read |
74b0247f | 429 | * |
1da177e4 | 430 | * Return value: |
f5279ffd | 431 | * value read, or 0xffff if an error occurred. |
1da177e4 LT |
432 | ********************************************************************* */ |
433 | ||
f5279ffd | 434 | static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx) |
1da177e4 | 435 | { |
f5279ffd MR |
436 | struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; |
437 | void __iomem *sbm_mdio = sc->sbm_mdio; | |
1da177e4 LT |
438 | int idx; |
439 | int error; | |
440 | int regval; | |
441 | int mac_mdio_genc; | |
442 | ||
443 | /* | |
444 | * Synchronize ourselves so that the PHY knows the next | |
445 | * thing coming down is a command | |
446 | */ | |
f5279ffd | 447 | sbmac_mii_sync(sbm_mdio); |
74b0247f | 448 | |
1da177e4 LT |
449 | /* |
450 | * Send the data to the PHY. The sequence is | |
451 | * a "start" command (2 bits) | |
452 | * a "read" command (2 bits) | |
453 | * the PHY addr (5 bits) | |
454 | * the register index (5 bits) | |
455 | */ | |
f5279ffd MR |
456 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); |
457 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2); | |
458 | sbmac_mii_senddata(sbm_mdio, phyaddr, 5); | |
459 | sbmac_mii_senddata(sbm_mdio, regidx, 5); | |
74b0247f | 460 | |
f5279ffd | 461 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
74b0247f RB |
462 | |
463 | /* | |
1da177e4 LT |
464 | * Switch the port around without a clock transition. |
465 | */ | |
f5279ffd | 466 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); |
74b0247f | 467 | |
1da177e4 LT |
468 | /* |
469 | * Send out a clock pulse to signal we want the status | |
470 | */ | |
f5279ffd MR |
471 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, |
472 | sbm_mdio); | |
473 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); | |
74b0247f RB |
474 | |
475 | /* | |
1da177e4 LT |
476 | * If an error occurred, the PHY will signal '1' back |
477 | */ | |
f5279ffd | 478 | error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN; |
74b0247f RB |
479 | |
480 | /* | |
1da177e4 LT |
481 | * Issue an 'idle' clock pulse, but keep the direction |
482 | * the same. | |
483 | */ | |
f5279ffd MR |
484 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, |
485 | sbm_mdio); | |
486 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); | |
74b0247f | 487 | |
1da177e4 | 488 | regval = 0; |
74b0247f | 489 | |
1da177e4 LT |
490 | for (idx = 0; idx < 16; idx++) { |
491 | regval <<= 1; | |
74b0247f | 492 | |
1da177e4 | 493 | if (error == 0) { |
f5279ffd | 494 | if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN) |
1da177e4 LT |
495 | regval |= 1; |
496 | } | |
74b0247f | 497 | |
f5279ffd MR |
498 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, |
499 | sbm_mdio); | |
500 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); | |
1da177e4 | 501 | } |
74b0247f | 502 | |
1da177e4 | 503 | /* Switch back to output */ |
f5279ffd | 504 | __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); |
74b0247f | 505 | |
1da177e4 LT |
506 | if (error == 0) |
507 | return regval; | |
f5279ffd | 508 | return 0xffff; |
1da177e4 LT |
509 | } |
510 | ||
511 | ||
512 | /********************************************************************** | |
f5279ffd | 513 | * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval) |
74b0247f | 514 | * |
1da177e4 | 515 | * Write a value to a PHY register. |
74b0247f RB |
516 | * |
517 | * Input parameters: | |
f5279ffd | 518 | * bus - MDIO bus handle |
1da177e4 | 519 | * phyaddr - PHY to use |
f5279ffd MR |
520 | * regidx - register within the PHY |
521 | * regval - data to write to register | |
74b0247f | 522 | * |
1da177e4 | 523 | * Return value: |
f5279ffd | 524 | * 0 for success |
1da177e4 LT |
525 | ********************************************************************* */ |
526 | ||
f5279ffd MR |
527 | static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, |
528 | u16 regval) | |
1da177e4 | 529 | { |
f5279ffd MR |
530 | struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; |
531 | void __iomem *sbm_mdio = sc->sbm_mdio; | |
1da177e4 LT |
532 | int mac_mdio_genc; |
533 | ||
f5279ffd | 534 | sbmac_mii_sync(sbm_mdio); |
74b0247f | 535 | |
f5279ffd MR |
536 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); |
537 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2); | |
538 | sbmac_mii_senddata(sbm_mdio, phyaddr, 5); | |
539 | sbmac_mii_senddata(sbm_mdio, regidx, 5); | |
540 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2); | |
541 | sbmac_mii_senddata(sbm_mdio, regval, 16); | |
1da177e4 | 542 | |
f5279ffd | 543 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
1da177e4 | 544 | |
f5279ffd MR |
545 | __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); |
546 | ||
547 | return 0; | |
1da177e4 LT |
548 | } |
549 | ||
550 | ||
551 | ||
552 | /********************************************************************** | |
553 | * SBDMA_INITCTX(d,s,chan,txrx,maxdescr) | |
74b0247f | 554 | * |
1da177e4 LT |
555 | * Initialize a DMA channel context. Since there are potentially |
556 | * eight DMA channels per MAC, it's nice to do this in a standard | |
74b0247f RB |
557 | * way. |
558 | * | |
559 | * Input parameters: | |
73d73969 MR |
560 | * d - struct sbmacdma (DMA channel context) |
561 | * s - struct sbmac_softc (pointer to a MAC) | |
1da177e4 LT |
562 | * chan - channel number (0..1 right now) |
563 | * txrx - Identifies DMA_TX or DMA_RX for channel direction | |
564 | * maxdescr - number of descriptors | |
74b0247f | 565 | * |
1da177e4 LT |
566 | * Return value: |
567 | * nothing | |
568 | ********************************************************************* */ | |
569 | ||
73d73969 MR |
570 | static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, |
571 | int txrx, int maxdescr) | |
1da177e4 | 572 | { |
693aa947 MM |
573 | #ifdef CONFIG_SBMAC_COALESCE |
574 | int int_pktcnt, int_timeout; | |
575 | #endif | |
576 | ||
74b0247f RB |
577 | /* |
578 | * Save away interesting stuff in the structure | |
1da177e4 | 579 | */ |
74b0247f | 580 | |
1da177e4 LT |
581 | d->sbdma_eth = s; |
582 | d->sbdma_channel = chan; | |
583 | d->sbdma_txdir = txrx; | |
74b0247f | 584 | |
1da177e4 LT |
585 | #if 0 |
586 | /* RMON clearing */ | |
587 | s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; | |
588 | #endif | |
589 | ||
f5279ffd MR |
590 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES); |
591 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS); | |
592 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL); | |
593 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL); | |
594 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR); | |
595 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT); | |
596 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD); | |
597 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD); | |
598 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT); | |
599 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE); | |
600 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES); | |
601 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST); | |
602 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST); | |
603 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD); | |
604 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD); | |
605 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT); | |
606 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE); | |
607 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR); | |
608 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR); | |
609 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR); | |
610 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR); | |
1da177e4 | 611 | |
74b0247f RB |
612 | /* |
613 | * initialize register pointers | |
1da177e4 | 614 | */ |
74b0247f RB |
615 | |
616 | d->sbdma_config0 = | |
1da177e4 | 617 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0); |
74b0247f | 618 | d->sbdma_config1 = |
1da177e4 | 619 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1); |
74b0247f | 620 | d->sbdma_dscrbase = |
1da177e4 | 621 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE); |
74b0247f | 622 | d->sbdma_dscrcnt = |
1da177e4 | 623 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT); |
74b0247f | 624 | d->sbdma_curdscr = |
1da177e4 | 625 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR); |
693aa947 MM |
626 | if (d->sbdma_txdir) |
627 | d->sbdma_oodpktlost = NULL; | |
628 | else | |
629 | d->sbdma_oodpktlost = | |
630 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX); | |
74b0247f | 631 | |
1da177e4 LT |
632 | /* |
633 | * Allocate memory for the ring | |
634 | */ | |
74b0247f | 635 | |
1da177e4 | 636 | d->sbdma_maxdescr = maxdescr; |
74b0247f | 637 | |
73d73969 MR |
638 | d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1, |
639 | sizeof(*d->sbdma_dscrtable), | |
640 | GFP_KERNEL); | |
04115def RB |
641 | |
642 | /* | |
643 | * The descriptor table must be aligned to at least 16 bytes or the | |
644 | * MAC will corrupt it. | |
645 | */ | |
73d73969 MR |
646 | d->sbdma_dscrtable = (struct sbdmadscr *) |
647 | ALIGN((unsigned long)d->sbdma_dscrtable_unaligned, | |
648 | sizeof(*d->sbdma_dscrtable)); | |
74b0247f | 649 | |
1da177e4 | 650 | d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; |
74b0247f | 651 | |
1da177e4 | 652 | d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable); |
74b0247f | 653 | |
1da177e4 LT |
654 | /* |
655 | * And context table | |
656 | */ | |
74b0247f | 657 | |
c477f334 | 658 | d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr, |
73d73969 | 659 | sizeof(*d->sbdma_ctxtable), GFP_KERNEL); |
74b0247f | 660 | |
1da177e4 LT |
661 | #ifdef CONFIG_SBMAC_COALESCE |
662 | /* | |
663 | * Setup Rx/Tx DMA coalescing defaults | |
664 | */ | |
665 | ||
693aa947 | 666 | int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx; |
1da177e4 LT |
667 | if ( int_pktcnt ) { |
668 | d->sbdma_int_pktcnt = int_pktcnt; | |
669 | } else { | |
670 | d->sbdma_int_pktcnt = 1; | |
671 | } | |
74b0247f | 672 | |
693aa947 | 673 | int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx; |
1da177e4 LT |
674 | if ( int_timeout ) { |
675 | d->sbdma_int_timeout = int_timeout; | |
676 | } else { | |
677 | d->sbdma_int_timeout = 0; | |
678 | } | |
679 | #endif | |
680 | ||
681 | } | |
682 | ||
683 | /********************************************************************** | |
684 | * SBDMA_CHANNEL_START(d) | |
74b0247f | 685 | * |
1da177e4 | 686 | * Initialize the hardware registers for a DMA channel. |
74b0247f RB |
687 | * |
688 | * Input parameters: | |
1da177e4 LT |
689 | * d - DMA channel to init (context must be previously init'd |
690 | * rxtx - DMA_RX or DMA_TX depending on what type of channel | |
74b0247f | 691 | * |
1da177e4 LT |
692 | * Return value: |
693 | * nothing | |
694 | ********************************************************************* */ | |
695 | ||
73d73969 | 696 | static void sbdma_channel_start(struct sbmacdma *d, int rxtx) |
1da177e4 LT |
697 | { |
698 | /* | |
699 | * Turn on the DMA channel | |
700 | */ | |
74b0247f | 701 | |
1da177e4 | 702 | #ifdef CONFIG_SBMAC_COALESCE |
2039973a RB |
703 | __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) | |
704 | 0, d->sbdma_config1); | |
705 | __raw_writeq(M_DMA_EOP_INT_EN | | |
1da177e4 LT |
706 | V_DMA_RINGSZ(d->sbdma_maxdescr) | |
707 | V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) | | |
2039973a | 708 | 0, d->sbdma_config0); |
1da177e4 | 709 | #else |
2039973a RB |
710 | __raw_writeq(0, d->sbdma_config1); |
711 | __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) | | |
712 | 0, d->sbdma_config0); | |
1da177e4 LT |
713 | #endif |
714 | ||
2039973a | 715 | __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase); |
1da177e4 LT |
716 | |
717 | /* | |
718 | * Initialize ring pointers | |
719 | */ | |
720 | ||
721 | d->sbdma_addptr = d->sbdma_dscrtable; | |
722 | d->sbdma_remptr = d->sbdma_dscrtable; | |
723 | } | |
724 | ||
725 | /********************************************************************** | |
726 | * SBDMA_CHANNEL_STOP(d) | |
74b0247f | 727 | * |
1da177e4 | 728 | * Initialize the hardware registers for a DMA channel. |
74b0247f RB |
729 | * |
730 | * Input parameters: | |
1da177e4 | 731 | * d - DMA channel to init (context must be previously init'd |
74b0247f | 732 | * |
1da177e4 LT |
733 | * Return value: |
734 | * nothing | |
735 | ********************************************************************* */ | |
736 | ||
73d73969 | 737 | static void sbdma_channel_stop(struct sbmacdma *d) |
1da177e4 LT |
738 | { |
739 | /* | |
740 | * Turn off the DMA channel | |
741 | */ | |
74b0247f | 742 | |
2039973a | 743 | __raw_writeq(0, d->sbdma_config1); |
74b0247f | 744 | |
2039973a | 745 | __raw_writeq(0, d->sbdma_dscrbase); |
74b0247f | 746 | |
2039973a | 747 | __raw_writeq(0, d->sbdma_config0); |
74b0247f | 748 | |
1da177e4 LT |
749 | /* |
750 | * Zero ring pointers | |
751 | */ | |
74b0247f | 752 | |
2039973a RB |
753 | d->sbdma_addptr = NULL; |
754 | d->sbdma_remptr = NULL; | |
1da177e4 LT |
755 | } |
756 | ||
789585e9 SH |
757 | static inline void sbdma_align_skb(struct sk_buff *skb, |
758 | unsigned int power2, unsigned int offset) | |
1da177e4 | 759 | { |
789585e9 SH |
760 | unsigned char *addr = skb->data; |
761 | unsigned char *newaddr = PTR_ALIGN(addr, power2); | |
74b0247f | 762 | |
789585e9 | 763 | skb_reserve(skb, newaddr - addr + offset); |
1da177e4 LT |
764 | } |
765 | ||
766 | ||
767 | /********************************************************************** | |
768 | * SBDMA_ADD_RCVBUFFER(d,sb) | |
74b0247f | 769 | * |
1da177e4 LT |
770 | * Add a buffer to the specified DMA channel. For receive channels, |
771 | * this queues a buffer for inbound packets. | |
74b0247f RB |
772 | * |
773 | * Input parameters: | |
789585e9 SH |
774 | * sc - softc structure |
775 | * d - DMA channel descriptor | |
1da177e4 | 776 | * sb - sk_buff to add, or NULL if we should allocate one |
74b0247f | 777 | * |
1da177e4 LT |
778 | * Return value: |
779 | * 0 if buffer could not be added (ring is full) | |
780 | * 1 if buffer added successfully | |
781 | ********************************************************************* */ | |
782 | ||
783 | ||
789585e9 SH |
784 | static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, |
785 | struct sk_buff *sb) | |
1da177e4 | 786 | { |
789585e9 | 787 | struct net_device *dev = sc->sbm_dev; |
73d73969 MR |
788 | struct sbdmadscr *dsc; |
789 | struct sbdmadscr *nextdsc; | |
1da177e4 LT |
790 | struct sk_buff *sb_new = NULL; |
791 | int pktsize = ENET_PACKET_SIZE; | |
74b0247f | 792 | |
1da177e4 | 793 | /* get pointer to our current place in the ring */ |
74b0247f | 794 | |
1da177e4 LT |
795 | dsc = d->sbdma_addptr; |
796 | nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); | |
74b0247f | 797 | |
1da177e4 LT |
798 | /* |
799 | * figure out if the ring is full - if the next descriptor | |
800 | * is the same as the one that we're going to remove from | |
801 | * the ring, the ring is full | |
802 | */ | |
74b0247f | 803 | |
1da177e4 LT |
804 | if (nextdsc == d->sbdma_remptr) { |
805 | return -ENOSPC; | |
806 | } | |
807 | ||
74b0247f RB |
808 | /* |
809 | * Allocate a sk_buff if we don't already have one. | |
1da177e4 LT |
810 | * If we do have an sk_buff, reset it so that it's empty. |
811 | * | |
812 | * Note: sk_buffs don't seem to be guaranteed to have any sort | |
813 | * of alignment when they are allocated. Therefore, allocate enough | |
814 | * extra space to make sure that: | |
815 | * | |
816 | * 1. the data does not start in the middle of a cache line. | |
817 | * 2. The data does not end in the middle of a cache line | |
74b0247f | 818 | * 3. The buffer can be aligned such that the IP addresses are |
1da177e4 LT |
819 | * naturally aligned. |
820 | * | |
821 | * Remember, the SOCs MAC writes whole cache lines at a time, | |
822 | * without reading the old contents first. So, if the sk_buff's | |
823 | * data portion starts in the middle of a cache line, the SOC | |
824 | * DMA will trash the beginning (and ending) portions. | |
825 | */ | |
74b0247f | 826 | |
1da177e4 | 827 | if (sb == NULL) { |
789585e9 SH |
828 | sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE + |
829 | SMP_CACHE_BYTES * 2 + | |
830 | NET_IP_ALIGN); | |
720a43ef | 831 | if (sb_new == NULL) |
1da177e4 | 832 | return -ENOBUFS; |
1da177e4 | 833 | |
789585e9 | 834 | sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN); |
1da177e4 LT |
835 | } |
836 | else { | |
837 | sb_new = sb; | |
74b0247f | 838 | /* |
1da177e4 LT |
839 | * nothing special to reinit buffer, it's already aligned |
840 | * and sb->data already points to a good place. | |
841 | */ | |
842 | } | |
74b0247f | 843 | |
1da177e4 | 844 | /* |
74b0247f | 845 | * fill in the descriptor |
1da177e4 | 846 | */ |
74b0247f | 847 | |
1da177e4 LT |
848 | #ifdef CONFIG_SBMAC_COALESCE |
849 | /* | |
850 | * Do not interrupt per DMA transfer. | |
851 | */ | |
689be439 | 852 | dsc->dscr_a = virt_to_phys(sb_new->data) | |
789585e9 | 853 | V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0; |
1da177e4 | 854 | #else |
689be439 | 855 | dsc->dscr_a = virt_to_phys(sb_new->data) | |
789585e9 | 856 | V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | |
1da177e4 LT |
857 | M_DMA_DSCRA_INTERRUPT; |
858 | #endif | |
859 | ||
860 | /* receiving: no options */ | |
861 | dsc->dscr_b = 0; | |
74b0247f | 862 | |
1da177e4 | 863 | /* |
74b0247f | 864 | * fill in the context |
1da177e4 | 865 | */ |
74b0247f | 866 | |
1da177e4 | 867 | d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; |
74b0247f RB |
868 | |
869 | /* | |
870 | * point at next packet | |
1da177e4 | 871 | */ |
74b0247f | 872 | |
1da177e4 | 873 | d->sbdma_addptr = nextdsc; |
74b0247f RB |
874 | |
875 | /* | |
1da177e4 LT |
876 | * Give the buffer to the DMA engine. |
877 | */ | |
74b0247f | 878 | |
2039973a | 879 | __raw_writeq(1, d->sbdma_dscrcnt); |
74b0247f | 880 | |
1da177e4 LT |
881 | return 0; /* we did it */ |
882 | } | |
883 | ||
884 | /********************************************************************** | |
885 | * SBDMA_ADD_TXBUFFER(d,sb) | |
74b0247f | 886 | * |
1da177e4 LT |
887 | * Add a transmit buffer to the specified DMA channel, causing a |
888 | * transmit to start. | |
74b0247f RB |
889 | * |
890 | * Input parameters: | |
1da177e4 LT |
891 | * d - DMA channel descriptor |
892 | * sb - sk_buff to add | |
74b0247f | 893 | * |
1da177e4 LT |
894 | * Return value: |
895 | * 0 transmit queued successfully | |
896 | * otherwise error code | |
897 | ********************************************************************* */ | |
898 | ||
899 | ||
73d73969 | 900 | static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb) |
1da177e4 | 901 | { |
73d73969 MR |
902 | struct sbdmadscr *dsc; |
903 | struct sbdmadscr *nextdsc; | |
1da177e4 LT |
904 | uint64_t phys; |
905 | uint64_t ncb; | |
906 | int length; | |
74b0247f | 907 | |
1da177e4 | 908 | /* get pointer to our current place in the ring */ |
74b0247f | 909 | |
1da177e4 LT |
910 | dsc = d->sbdma_addptr; |
911 | nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); | |
74b0247f | 912 | |
1da177e4 LT |
913 | /* |
914 | * figure out if the ring is full - if the next descriptor | |
915 | * is the same as the one that we're going to remove from | |
916 | * the ring, the ring is full | |
917 | */ | |
74b0247f | 918 | |
1da177e4 LT |
919 | if (nextdsc == d->sbdma_remptr) { |
920 | return -ENOSPC; | |
921 | } | |
74b0247f | 922 | |
1da177e4 LT |
923 | /* |
924 | * Under Linux, it's not necessary to copy/coalesce buffers | |
925 | * like it is on NetBSD. We think they're all contiguous, | |
926 | * but that may not be true for GBE. | |
927 | */ | |
74b0247f | 928 | |
1da177e4 | 929 | length = sb->len; |
74b0247f | 930 | |
1da177e4 LT |
931 | /* |
932 | * fill in the descriptor. Note that the number of cache | |
933 | * blocks in the descriptor is the number of blocks | |
934 | * *spanned*, so we need to add in the offset (if any) | |
935 | * while doing the calculation. | |
936 | */ | |
74b0247f | 937 | |
1da177e4 LT |
938 | phys = virt_to_phys(sb->data); |
939 | ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1))); | |
940 | ||
74b0247f | 941 | dsc->dscr_a = phys | |
1da177e4 LT |
942 | V_DMA_DSCRA_A_SIZE(ncb) | |
943 | #ifndef CONFIG_SBMAC_COALESCE | |
944 | M_DMA_DSCRA_INTERRUPT | | |
945 | #endif | |
946 | M_DMA_ETHTX_SOP; | |
74b0247f | 947 | |
1da177e4 LT |
948 | /* transmitting: set outbound options and length */ |
949 | ||
950 | dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | | |
951 | V_DMA_DSCRB_PKT_SIZE(length); | |
74b0247f | 952 | |
1da177e4 | 953 | /* |
74b0247f | 954 | * fill in the context |
1da177e4 | 955 | */ |
74b0247f | 956 | |
1da177e4 | 957 | d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb; |
74b0247f RB |
958 | |
959 | /* | |
960 | * point at next packet | |
1da177e4 | 961 | */ |
74b0247f | 962 | |
1da177e4 | 963 | d->sbdma_addptr = nextdsc; |
74b0247f RB |
964 | |
965 | /* | |
1da177e4 LT |
966 | * Give the buffer to the DMA engine. |
967 | */ | |
74b0247f | 968 | |
2039973a | 969 | __raw_writeq(1, d->sbdma_dscrcnt); |
74b0247f | 970 | |
1da177e4 LT |
971 | return 0; /* we did it */ |
972 | } | |
973 | ||
974 | ||
975 | ||
976 | ||
977 | /********************************************************************** | |
978 | * SBDMA_EMPTYRING(d) | |
74b0247f | 979 | * |
1da177e4 | 980 | * Free all allocated sk_buffs on the specified DMA channel; |
74b0247f RB |
981 | * |
982 | * Input parameters: | |
1da177e4 | 983 | * d - DMA channel |
74b0247f | 984 | * |
1da177e4 LT |
985 | * Return value: |
986 | * nothing | |
987 | ********************************************************************* */ | |
988 | ||
73d73969 | 989 | static void sbdma_emptyring(struct sbmacdma *d) |
1da177e4 LT |
990 | { |
991 | int idx; | |
992 | struct sk_buff *sb; | |
74b0247f | 993 | |
1da177e4 LT |
994 | for (idx = 0; idx < d->sbdma_maxdescr; idx++) { |
995 | sb = d->sbdma_ctxtable[idx]; | |
996 | if (sb) { | |
997 | dev_kfree_skb(sb); | |
998 | d->sbdma_ctxtable[idx] = NULL; | |
999 | } | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | ||
1004 | /********************************************************************** | |
1005 | * SBDMA_FILLRING(d) | |
74b0247f | 1006 | * |
1da177e4 LT |
1007 | * Fill the specified DMA channel (must be receive channel) |
1008 | * with sk_buffs | |
74b0247f RB |
1009 | * |
1010 | * Input parameters: | |
789585e9 SH |
1011 | * sc - softc structure |
1012 | * d - DMA channel | |
74b0247f | 1013 | * |
1da177e4 LT |
1014 | * Return value: |
1015 | * nothing | |
1016 | ********************************************************************* */ | |
1017 | ||
789585e9 | 1018 | static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d) |
1da177e4 LT |
1019 | { |
1020 | int idx; | |
74b0247f | 1021 | |
789585e9 SH |
1022 | for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) { |
1023 | if (sbdma_add_rcvbuffer(sc, d, NULL) != 0) | |
1da177e4 LT |
1024 | break; |
1025 | } | |
1026 | } | |
1027 | ||
d6830018 DS |
1028 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1029 | static void sbmac_netpoll(struct net_device *netdev) | |
1030 | { | |
1031 | struct sbmac_softc *sc = netdev_priv(netdev); | |
1032 | int irq = sc->sbm_dev->irq; | |
1033 | ||
1034 | __raw_writeq(0, sc->sbm_imr); | |
1035 | ||
0da2f0f1 | 1036 | sbmac_intr(irq, netdev); |
d6830018 DS |
1037 | |
1038 | #ifdef CONFIG_SBMAC_COALESCE | |
1039 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | | |
1040 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), | |
1041 | sc->sbm_imr); | |
1042 | #else | |
7d2e3cb7 | 1043 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | |
d6830018 DS |
1044 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); |
1045 | #endif | |
1046 | } | |
1047 | #endif | |
1da177e4 LT |
1048 | |
1049 | /********************************************************************** | |
693aa947 | 1050 | * SBDMA_RX_PROCESS(sc,d,work_to_do,poll) |
74b0247f RB |
1051 | * |
1052 | * Process "completed" receive buffers on the specified DMA channel. | |
1da177e4 | 1053 | * |
74b0247f | 1054 | * Input parameters: |
693aa947 MM |
1055 | * sc - softc structure |
1056 | * d - DMA channel context | |
1057 | * work_to_do - no. of packets to process before enabling interrupt | |
1058 | * again (for NAPI) | |
1059 | * poll - 1: using polling (for NAPI) | |
74b0247f | 1060 | * |
1da177e4 LT |
1061 | * Return value: |
1062 | * nothing | |
1063 | ********************************************************************* */ | |
1064 | ||
73d73969 MR |
1065 | static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d, |
1066 | int work_to_do, int poll) | |
1da177e4 | 1067 | { |
09f75cd7 | 1068 | struct net_device *dev = sc->sbm_dev; |
1da177e4 LT |
1069 | int curidx; |
1070 | int hwidx; | |
73d73969 | 1071 | struct sbdmadscr *dsc; |
1da177e4 LT |
1072 | struct sk_buff *sb; |
1073 | int len; | |
693aa947 MM |
1074 | int work_done = 0; |
1075 | int dropped = 0; | |
74b0247f | 1076 | |
693aa947 MM |
1077 | prefetch(d); |
1078 | ||
1079 | again: | |
1080 | /* Check if the HW dropped any frames */ | |
09f75cd7 | 1081 | dev->stats.rx_fifo_errors |
693aa947 MM |
1082 | += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff; |
1083 | __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost); | |
1084 | ||
1085 | while (work_to_do-- > 0) { | |
74b0247f | 1086 | /* |
1da177e4 LT |
1087 | * figure out where we are (as an index) and where |
1088 | * the hardware is (also as an index) | |
1089 | * | |
74b0247f | 1090 | * This could be done faster if (for example) the |
1da177e4 LT |
1091 | * descriptor table was page-aligned and contiguous in |
1092 | * both virtual and physical memory -- you could then | |
1093 | * just compare the low-order bits of the virtual address | |
1094 | * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) | |
1095 | */ | |
74b0247f | 1096 | |
693aa947 MM |
1097 | dsc = d->sbdma_remptr; |
1098 | curidx = dsc - d->sbdma_dscrtable; | |
1099 | ||
1100 | prefetch(dsc); | |
1101 | prefetch(&d->sbdma_ctxtable[curidx]); | |
1102 | ||
73d73969 MR |
1103 | hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - |
1104 | d->sbdma_dscrtable_phys) / | |
1105 | sizeof(*d->sbdma_dscrtable); | |
74b0247f | 1106 | |
1da177e4 LT |
1107 | /* |
1108 | * If they're the same, that means we've processed all | |
1109 | * of the descriptors up to (but not including) the one that | |
1110 | * the hardware is working on right now. | |
1111 | */ | |
74b0247f | 1112 | |
1da177e4 | 1113 | if (curidx == hwidx) |
693aa947 | 1114 | goto done; |
74b0247f | 1115 | |
1da177e4 LT |
1116 | /* |
1117 | * Otherwise, get the packet's sk_buff ptr back | |
1118 | */ | |
74b0247f | 1119 | |
1da177e4 LT |
1120 | sb = d->sbdma_ctxtable[curidx]; |
1121 | d->sbdma_ctxtable[curidx] = NULL; | |
74b0247f | 1122 | |
1da177e4 | 1123 | len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; |
74b0247f | 1124 | |
1da177e4 LT |
1125 | /* |
1126 | * Check packet status. If good, process it. | |
1127 | * If not, silently drop it and put it back on the | |
1128 | * receive ring. | |
1129 | */ | |
74b0247f | 1130 | |
693aa947 | 1131 | if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) { |
74b0247f | 1132 | |
1da177e4 LT |
1133 | /* |
1134 | * Add a new buffer to replace the old one. If we fail | |
1135 | * to allocate a buffer, we're going to drop this | |
1136 | * packet and put it right back on the receive ring. | |
1137 | */ | |
74b0247f | 1138 | |
789585e9 SH |
1139 | if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) == |
1140 | -ENOBUFS)) { | |
09f75cd7 | 1141 | dev->stats.rx_dropped++; |
789585e9 SH |
1142 | /* Re-add old buffer */ |
1143 | sbdma_add_rcvbuffer(sc, d, sb); | |
693aa947 MM |
1144 | /* No point in continuing at the moment */ |
1145 | printk(KERN_ERR "dropped packet (1)\n"); | |
1146 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); | |
1147 | goto done; | |
1da177e4 LT |
1148 | } else { |
1149 | /* | |
1150 | * Set length into the packet | |
1151 | */ | |
1152 | skb_put(sb,len); | |
74b0247f | 1153 | |
1da177e4 LT |
1154 | /* |
1155 | * Buffer has been replaced on the | |
1156 | * receive ring. Pass the buffer to | |
1157 | * the kernel | |
1158 | */ | |
1da177e4 LT |
1159 | sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev); |
1160 | /* Check hw IPv4/TCP checksum if supported */ | |
1161 | if (sc->rx_hw_checksum == ENABLE) { | |
1162 | if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) && | |
1163 | !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) { | |
1164 | sb->ip_summed = CHECKSUM_UNNECESSARY; | |
1165 | /* don't need to set sb->csum */ | |
1166 | } else { | |
bc8acf2c | 1167 | skb_checksum_none_assert(sb); |
1da177e4 LT |
1168 | } |
1169 | } | |
693aa947 MM |
1170 | prefetch(sb->data); |
1171 | prefetch((const void *)(((char *)sb->data)+32)); | |
1172 | if (poll) | |
1173 | dropped = netif_receive_skb(sb); | |
1174 | else | |
1175 | dropped = netif_rx(sb); | |
1176 | ||
1177 | if (dropped == NET_RX_DROP) { | |
09f75cd7 | 1178 | dev->stats.rx_dropped++; |
693aa947 MM |
1179 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); |
1180 | goto done; | |
1181 | } | |
1182 | else { | |
09f75cd7 JG |
1183 | dev->stats.rx_bytes += len; |
1184 | dev->stats.rx_packets++; | |
693aa947 | 1185 | } |
1da177e4 LT |
1186 | } |
1187 | } else { | |
1188 | /* | |
1189 | * Packet was mangled somehow. Just drop it and | |
1190 | * put it back on the receive ring. | |
1191 | */ | |
09f75cd7 | 1192 | dev->stats.rx_errors++; |
789585e9 | 1193 | sbdma_add_rcvbuffer(sc, d, sb); |
1da177e4 | 1194 | } |
74b0247f RB |
1195 | |
1196 | ||
1197 | /* | |
1da177e4 LT |
1198 | * .. and advance to the next buffer. |
1199 | */ | |
74b0247f | 1200 | |
1da177e4 | 1201 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); |
693aa947 MM |
1202 | work_done++; |
1203 | } | |
1204 | if (!poll) { | |
1205 | work_to_do = 32; | |
1206 | goto again; /* collect fifo drop statistics again */ | |
1da177e4 | 1207 | } |
693aa947 MM |
1208 | done: |
1209 | return work_done; | |
1da177e4 LT |
1210 | } |
1211 | ||
1da177e4 LT |
1212 | /********************************************************************** |
1213 | * SBDMA_TX_PROCESS(sc,d) | |
74b0247f RB |
1214 | * |
1215 | * Process "completed" transmit buffers on the specified DMA channel. | |
1da177e4 LT |
1216 | * This is normally called within the interrupt service routine. |
1217 | * Note that this isn't really ideal for priority channels, since | |
74b0247f RB |
1218 | * it processes all of the packets on a given channel before |
1219 | * returning. | |
1da177e4 | 1220 | * |
74b0247f | 1221 | * Input parameters: |
1da177e4 | 1222 | * sc - softc structure |
693aa947 MM |
1223 | * d - DMA channel context |
1224 | * poll - 1: using polling (for NAPI) | |
74b0247f | 1225 | * |
1da177e4 LT |
1226 | * Return value: |
1227 | * nothing | |
1228 | ********************************************************************* */ | |
1229 | ||
73d73969 MR |
1230 | static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d, |
1231 | int poll) | |
1da177e4 | 1232 | { |
09f75cd7 | 1233 | struct net_device *dev = sc->sbm_dev; |
1da177e4 LT |
1234 | int curidx; |
1235 | int hwidx; | |
73d73969 | 1236 | struct sbdmadscr *dsc; |
1da177e4 LT |
1237 | struct sk_buff *sb; |
1238 | unsigned long flags; | |
693aa947 | 1239 | int packets_handled = 0; |
1da177e4 LT |
1240 | |
1241 | spin_lock_irqsave(&(sc->sbm_lock), flags); | |
74b0247f | 1242 | |
693aa947 MM |
1243 | if (d->sbdma_remptr == d->sbdma_addptr) |
1244 | goto end_unlock; | |
1245 | ||
73d73969 MR |
1246 | hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - |
1247 | d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable); | |
693aa947 | 1248 | |
1da177e4 | 1249 | for (;;) { |
74b0247f | 1250 | /* |
1da177e4 LT |
1251 | * figure out where we are (as an index) and where |
1252 | * the hardware is (also as an index) | |
1253 | * | |
74b0247f | 1254 | * This could be done faster if (for example) the |
1da177e4 LT |
1255 | * descriptor table was page-aligned and contiguous in |
1256 | * both virtual and physical memory -- you could then | |
1257 | * just compare the low-order bits of the virtual address | |
1258 | * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) | |
1259 | */ | |
74b0247f | 1260 | |
1da177e4 | 1261 | curidx = d->sbdma_remptr - d->sbdma_dscrtable; |
1da177e4 LT |
1262 | |
1263 | /* | |
1264 | * If they're the same, that means we've processed all | |
1265 | * of the descriptors up to (but not including) the one that | |
1266 | * the hardware is working on right now. | |
1267 | */ | |
74b0247f | 1268 | |
1da177e4 LT |
1269 | if (curidx == hwidx) |
1270 | break; | |
74b0247f | 1271 | |
1da177e4 LT |
1272 | /* |
1273 | * Otherwise, get the packet's sk_buff ptr back | |
1274 | */ | |
74b0247f | 1275 | |
1da177e4 LT |
1276 | dsc = &(d->sbdma_dscrtable[curidx]); |
1277 | sb = d->sbdma_ctxtable[curidx]; | |
1278 | d->sbdma_ctxtable[curidx] = NULL; | |
74b0247f | 1279 | |
1da177e4 LT |
1280 | /* |
1281 | * Stats | |
1282 | */ | |
74b0247f | 1283 | |
09f75cd7 JG |
1284 | dev->stats.tx_bytes += sb->len; |
1285 | dev->stats.tx_packets++; | |
74b0247f | 1286 | |
1da177e4 LT |
1287 | /* |
1288 | * for transmits, we just free buffers. | |
1289 | */ | |
74b0247f | 1290 | |
1da177e4 | 1291 | dev_kfree_skb_irq(sb); |
74b0247f RB |
1292 | |
1293 | /* | |
1da177e4 LT |
1294 | * .. and advance to the next buffer. |
1295 | */ | |
1296 | ||
1297 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); | |
74b0247f | 1298 | |
693aa947 MM |
1299 | packets_handled++; |
1300 | ||
1da177e4 | 1301 | } |
74b0247f | 1302 | |
1da177e4 LT |
1303 | /* |
1304 | * Decide if we should wake up the protocol or not. | |
1305 | * Other drivers seem to do this when we reach a low | |
1306 | * watermark on the transmit queue. | |
1307 | */ | |
74b0247f | 1308 | |
693aa947 MM |
1309 | if (packets_handled) |
1310 | netif_wake_queue(d->sbdma_eth->sbm_dev); | |
74b0247f | 1311 | |
693aa947 | 1312 | end_unlock: |
1da177e4 | 1313 | spin_unlock_irqrestore(&(sc->sbm_lock), flags); |
74b0247f | 1314 | |
1da177e4 LT |
1315 | } |
1316 | ||
1317 | ||
1318 | ||
1319 | /********************************************************************** | |
1320 | * SBMAC_INITCTX(s) | |
74b0247f | 1321 | * |
1da177e4 LT |
1322 | * Initialize an Ethernet context structure - this is called |
1323 | * once per MAC on the 1250. Memory is allocated here, so don't | |
1324 | * call it again from inside the ioctl routines that bring the | |
1325 | * interface up/down | |
74b0247f RB |
1326 | * |
1327 | * Input parameters: | |
1da177e4 | 1328 | * s - sbmac context structure |
74b0247f | 1329 | * |
1da177e4 LT |
1330 | * Return value: |
1331 | * 0 | |
1332 | ********************************************************************* */ | |
1333 | ||
1334 | static int sbmac_initctx(struct sbmac_softc *s) | |
1335 | { | |
74b0247f RB |
1336 | |
1337 | /* | |
1338 | * figure out the addresses of some ports | |
1da177e4 | 1339 | */ |
74b0247f | 1340 | |
1da177e4 LT |
1341 | s->sbm_macenable = s->sbm_base + R_MAC_ENABLE; |
1342 | s->sbm_maccfg = s->sbm_base + R_MAC_CFG; | |
1343 | s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG; | |
1344 | s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG; | |
1345 | s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG; | |
1346 | s->sbm_isr = s->sbm_base + R_MAC_STATUS; | |
1347 | s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; | |
1348 | s->sbm_mdio = s->sbm_base + R_MAC_MDIO; | |
1349 | ||
1da177e4 LT |
1350 | /* |
1351 | * Initialize the DMA channels. Right now, only one per MAC is used | |
1352 | * Note: Only do this _once_, as it allocates memory from the kernel! | |
1353 | */ | |
74b0247f | 1354 | |
1da177e4 LT |
1355 | sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR); |
1356 | sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR); | |
74b0247f | 1357 | |
1da177e4 LT |
1358 | /* |
1359 | * initial state is OFF | |
1360 | */ | |
74b0247f | 1361 | |
1da177e4 | 1362 | s->sbm_state = sbmac_state_off; |
74b0247f | 1363 | |
1da177e4 LT |
1364 | return 0; |
1365 | } | |
1366 | ||
1367 | ||
73d73969 | 1368 | static void sbdma_uninitctx(struct sbmacdma *d) |
1da177e4 | 1369 | { |
693aa947 MM |
1370 | if (d->sbdma_dscrtable_unaligned) { |
1371 | kfree(d->sbdma_dscrtable_unaligned); | |
1372 | d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL; | |
1da177e4 | 1373 | } |
74b0247f | 1374 | |
1da177e4 LT |
1375 | if (d->sbdma_ctxtable) { |
1376 | kfree(d->sbdma_ctxtable); | |
1377 | d->sbdma_ctxtable = NULL; | |
1378 | } | |
1379 | } | |
1380 | ||
1381 | ||
1382 | static void sbmac_uninitctx(struct sbmac_softc *sc) | |
1383 | { | |
1384 | sbdma_uninitctx(&(sc->sbm_txdma)); | |
1385 | sbdma_uninitctx(&(sc->sbm_rxdma)); | |
1386 | } | |
1387 | ||
1388 | ||
1389 | /********************************************************************** | |
1390 | * SBMAC_CHANNEL_START(s) | |
74b0247f | 1391 | * |
1da177e4 | 1392 | * Start packet processing on this MAC. |
74b0247f RB |
1393 | * |
1394 | * Input parameters: | |
1da177e4 | 1395 | * s - sbmac structure |
74b0247f | 1396 | * |
1da177e4 LT |
1397 | * Return value: |
1398 | * nothing | |
1399 | ********************************************************************* */ | |
1400 | ||
1401 | static void sbmac_channel_start(struct sbmac_softc *s) | |
1402 | { | |
1403 | uint64_t reg; | |
73d73969 | 1404 | void __iomem *port; |
1da177e4 LT |
1405 | uint64_t cfg,fifo,framecfg; |
1406 | int idx, th_value; | |
74b0247f | 1407 | |
1da177e4 LT |
1408 | /* |
1409 | * Don't do this if running | |
1410 | */ | |
1411 | ||
1412 | if (s->sbm_state == sbmac_state_on) | |
1413 | return; | |
74b0247f | 1414 | |
1da177e4 LT |
1415 | /* |
1416 | * Bring the controller out of reset, but leave it off. | |
1417 | */ | |
74b0247f | 1418 | |
2039973a | 1419 | __raw_writeq(0, s->sbm_macenable); |
74b0247f | 1420 | |
1da177e4 LT |
1421 | /* |
1422 | * Ignore all received packets | |
1423 | */ | |
74b0247f | 1424 | |
2039973a | 1425 | __raw_writeq(0, s->sbm_rxfilter); |
74b0247f RB |
1426 | |
1427 | /* | |
1da177e4 LT |
1428 | * Calculate values for various control registers. |
1429 | */ | |
74b0247f | 1430 | |
1da177e4 | 1431 | cfg = M_MAC_RETRY_EN | |
74b0247f | 1432 | M_MAC_TX_HOLD_SOP_EN | |
1da177e4 LT |
1433 | V_MAC_TX_PAUSE_CNT_16K | |
1434 | M_MAC_AP_STAT_EN | | |
1435 | M_MAC_FAST_SYNC | | |
1436 | M_MAC_SS_EN | | |
1437 | 0; | |
74b0247f RB |
1438 | |
1439 | /* | |
1da177e4 LT |
1440 | * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars |
1441 | * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above | |
1442 | * Use a larger RD_THRSH for gigabit | |
1443 | */ | |
f90fdc3c | 1444 | if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) |
1da177e4 | 1445 | th_value = 28; |
f90fdc3c RB |
1446 | else |
1447 | th_value = 64; | |
1da177e4 LT |
1448 | |
1449 | fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ | |
1450 | ((s->sbm_speed == sbmac_speed_1000) | |
1451 | ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) | | |
1452 | V_MAC_TX_RL_THRSH(4) | | |
1453 | V_MAC_RX_PL_THRSH(4) | | |
1454 | V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ | |
1da177e4 LT |
1455 | V_MAC_RX_RL_THRSH(8) | |
1456 | 0; | |
1457 | ||
1458 | framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | | |
1459 | V_MAC_MAX_FRAMESZ_DEFAULT | | |
1460 | V_MAC_BACKOFF_SEL(1); | |
1461 | ||
1462 | /* | |
74b0247f | 1463 | * Clear out the hash address map |
1da177e4 | 1464 | */ |
74b0247f | 1465 | |
1da177e4 LT |
1466 | port = s->sbm_base + R_MAC_HASH_BASE; |
1467 | for (idx = 0; idx < MAC_HASH_COUNT; idx++) { | |
2039973a | 1468 | __raw_writeq(0, port); |
1da177e4 LT |
1469 | port += sizeof(uint64_t); |
1470 | } | |
74b0247f | 1471 | |
1da177e4 LT |
1472 | /* |
1473 | * Clear out the exact-match table | |
1474 | */ | |
74b0247f | 1475 | |
1da177e4 LT |
1476 | port = s->sbm_base + R_MAC_ADDR_BASE; |
1477 | for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { | |
2039973a | 1478 | __raw_writeq(0, port); |
1da177e4 LT |
1479 | port += sizeof(uint64_t); |
1480 | } | |
74b0247f | 1481 | |
1da177e4 LT |
1482 | /* |
1483 | * Clear out the DMA Channel mapping table registers | |
1484 | */ | |
74b0247f | 1485 | |
1da177e4 LT |
1486 | port = s->sbm_base + R_MAC_CHUP0_BASE; |
1487 | for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { | |
2039973a | 1488 | __raw_writeq(0, port); |
1da177e4 LT |
1489 | port += sizeof(uint64_t); |
1490 | } | |
1491 | ||
1492 | ||
1493 | port = s->sbm_base + R_MAC_CHLO0_BASE; | |
1494 | for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { | |
2039973a | 1495 | __raw_writeq(0, port); |
1da177e4 LT |
1496 | port += sizeof(uint64_t); |
1497 | } | |
74b0247f | 1498 | |
1da177e4 LT |
1499 | /* |
1500 | * Program the hardware address. It goes into the hardware-address | |
1501 | * register as well as the first filter register. | |
1502 | */ | |
74b0247f | 1503 | |
1da177e4 | 1504 | reg = sbmac_addr2reg(s->sbm_hwaddr); |
74b0247f | 1505 | |
1da177e4 | 1506 | port = s->sbm_base + R_MAC_ADDR_BASE; |
2039973a | 1507 | __raw_writeq(reg, port); |
1da177e4 LT |
1508 | port = s->sbm_base + R_MAC_ETHERNET_ADDR; |
1509 | ||
2039973a | 1510 | __raw_writeq(reg, port); |
74b0247f | 1511 | |
1da177e4 LT |
1512 | /* |
1513 | * Set the receive filter for no packets, and write values | |
1514 | * to the various config registers | |
1515 | */ | |
74b0247f | 1516 | |
2039973a RB |
1517 | __raw_writeq(0, s->sbm_rxfilter); |
1518 | __raw_writeq(0, s->sbm_imr); | |
1519 | __raw_writeq(framecfg, s->sbm_framecfg); | |
1520 | __raw_writeq(fifo, s->sbm_fifocfg); | |
1521 | __raw_writeq(cfg, s->sbm_maccfg); | |
74b0247f | 1522 | |
1da177e4 LT |
1523 | /* |
1524 | * Initialize DMA channels (rings should be ok now) | |
1525 | */ | |
74b0247f | 1526 | |
1da177e4 LT |
1527 | sbdma_channel_start(&(s->sbm_rxdma), DMA_RX); |
1528 | sbdma_channel_start(&(s->sbm_txdma), DMA_TX); | |
74b0247f | 1529 | |
1da177e4 LT |
1530 | /* |
1531 | * Configure the speed, duplex, and flow control | |
1532 | */ | |
1533 | ||
1534 | sbmac_set_speed(s,s->sbm_speed); | |
1535 | sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc); | |
74b0247f | 1536 | |
1da177e4 LT |
1537 | /* |
1538 | * Fill the receive ring | |
1539 | */ | |
74b0247f | 1540 | |
789585e9 | 1541 | sbdma_fillring(s, &(s->sbm_rxdma)); |
74b0247f RB |
1542 | |
1543 | /* | |
1da177e4 | 1544 | * Turn on the rest of the bits in the enable register |
74b0247f RB |
1545 | */ |
1546 | ||
f90fdc3c RB |
1547 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
1548 | __raw_writeq(M_MAC_RXDMA_EN0 | | |
1549 | M_MAC_TXDMA_EN0, s->sbm_macenable); | |
1550 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) | |
2039973a | 1551 | __raw_writeq(M_MAC_RXDMA_EN0 | |
1da177e4 LT |
1552 | M_MAC_TXDMA_EN0 | |
1553 | M_MAC_RX_ENABLE | | |
2039973a | 1554 | M_MAC_TX_ENABLE, s->sbm_macenable); |
f90fdc3c | 1555 | #else |
0b1974de | 1556 | #error invalid SiByte MAC configuration |
f90fdc3c | 1557 | #endif |
1da177e4 LT |
1558 | |
1559 | #ifdef CONFIG_SBMAC_COALESCE | |
2039973a RB |
1560 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | |
1561 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr); | |
1da177e4 | 1562 | #else |
2039973a RB |
1563 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | |
1564 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr); | |
1da177e4 | 1565 | #endif |
74b0247f RB |
1566 | |
1567 | /* | |
1568 | * Enable receiving unicasts and broadcasts | |
1da177e4 | 1569 | */ |
74b0247f | 1570 | |
2039973a | 1571 | __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter); |
74b0247f | 1572 | |
1da177e4 | 1573 | /* |
74b0247f | 1574 | * we're running now. |
1da177e4 | 1575 | */ |
74b0247f | 1576 | |
1da177e4 | 1577 | s->sbm_state = sbmac_state_on; |
74b0247f RB |
1578 | |
1579 | /* | |
1580 | * Program multicast addresses | |
1da177e4 | 1581 | */ |
74b0247f | 1582 | |
1da177e4 | 1583 | sbmac_setmulti(s); |
74b0247f RB |
1584 | |
1585 | /* | |
1586 | * If channel was in promiscuous mode before, turn that on | |
1da177e4 | 1587 | */ |
74b0247f | 1588 | |
1da177e4 LT |
1589 | if (s->sbm_devflags & IFF_PROMISC) { |
1590 | sbmac_promiscuous_mode(s,1); | |
1591 | } | |
74b0247f | 1592 | |
1da177e4 LT |
1593 | } |
1594 | ||
1595 | ||
1596 | /********************************************************************** | |
1597 | * SBMAC_CHANNEL_STOP(s) | |
74b0247f | 1598 | * |
1da177e4 | 1599 | * Stop packet processing on this MAC. |
74b0247f RB |
1600 | * |
1601 | * Input parameters: | |
1da177e4 | 1602 | * s - sbmac structure |
74b0247f | 1603 | * |
1da177e4 LT |
1604 | * Return value: |
1605 | * nothing | |
1606 | ********************************************************************* */ | |
1607 | ||
1608 | static void sbmac_channel_stop(struct sbmac_softc *s) | |
1609 | { | |
1610 | /* don't do this if already stopped */ | |
74b0247f | 1611 | |
1da177e4 LT |
1612 | if (s->sbm_state == sbmac_state_off) |
1613 | return; | |
74b0247f | 1614 | |
1da177e4 | 1615 | /* don't accept any packets, disable all interrupts */ |
74b0247f | 1616 | |
2039973a RB |
1617 | __raw_writeq(0, s->sbm_rxfilter); |
1618 | __raw_writeq(0, s->sbm_imr); | |
74b0247f | 1619 | |
1da177e4 | 1620 | /* Turn off ticker */ |
74b0247f | 1621 | |
1da177e4 | 1622 | /* XXX */ |
74b0247f | 1623 | |
1da177e4 | 1624 | /* turn off receiver and transmitter */ |
74b0247f | 1625 | |
2039973a | 1626 | __raw_writeq(0, s->sbm_macenable); |
74b0247f | 1627 | |
1da177e4 | 1628 | /* We're stopped now. */ |
74b0247f | 1629 | |
1da177e4 | 1630 | s->sbm_state = sbmac_state_off; |
74b0247f | 1631 | |
1da177e4 LT |
1632 | /* |
1633 | * Stop DMA channels (rings should be ok now) | |
1634 | */ | |
74b0247f | 1635 | |
1da177e4 LT |
1636 | sbdma_channel_stop(&(s->sbm_rxdma)); |
1637 | sbdma_channel_stop(&(s->sbm_txdma)); | |
74b0247f | 1638 | |
1da177e4 | 1639 | /* Empty the receive and transmit rings */ |
74b0247f | 1640 | |
1da177e4 LT |
1641 | sbdma_emptyring(&(s->sbm_rxdma)); |
1642 | sbdma_emptyring(&(s->sbm_txdma)); | |
74b0247f | 1643 | |
1da177e4 LT |
1644 | } |
1645 | ||
1646 | /********************************************************************** | |
1647 | * SBMAC_SET_CHANNEL_STATE(state) | |
74b0247f | 1648 | * |
1da177e4 | 1649 | * Set the channel's state ON or OFF |
74b0247f RB |
1650 | * |
1651 | * Input parameters: | |
1da177e4 | 1652 | * state - new state |
74b0247f | 1653 | * |
1da177e4 LT |
1654 | * Return value: |
1655 | * old state | |
1656 | ********************************************************************* */ | |
73d73969 MR |
1657 | static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc, |
1658 | enum sbmac_state state) | |
1da177e4 | 1659 | { |
73d73969 | 1660 | enum sbmac_state oldstate = sc->sbm_state; |
74b0247f | 1661 | |
1da177e4 LT |
1662 | /* |
1663 | * If same as previous state, return | |
1664 | */ | |
74b0247f | 1665 | |
1da177e4 LT |
1666 | if (state == oldstate) { |
1667 | return oldstate; | |
1668 | } | |
74b0247f | 1669 | |
1da177e4 | 1670 | /* |
74b0247f | 1671 | * If new state is ON, turn channel on |
1da177e4 | 1672 | */ |
74b0247f | 1673 | |
1da177e4 LT |
1674 | if (state == sbmac_state_on) { |
1675 | sbmac_channel_start(sc); | |
1676 | } | |
1677 | else { | |
1678 | sbmac_channel_stop(sc); | |
1679 | } | |
74b0247f | 1680 | |
1da177e4 LT |
1681 | /* |
1682 | * Return previous state | |
1683 | */ | |
74b0247f | 1684 | |
1da177e4 LT |
1685 | return oldstate; |
1686 | } | |
1687 | ||
1688 | ||
1689 | /********************************************************************** | |
1690 | * SBMAC_PROMISCUOUS_MODE(sc,onoff) | |
74b0247f | 1691 | * |
1da177e4 | 1692 | * Turn on or off promiscuous mode |
74b0247f RB |
1693 | * |
1694 | * Input parameters: | |
1da177e4 LT |
1695 | * sc - softc |
1696 | * onoff - 1 to turn on, 0 to turn off | |
74b0247f | 1697 | * |
1da177e4 LT |
1698 | * Return value: |
1699 | * nothing | |
1700 | ********************************************************************* */ | |
1701 | ||
1702 | static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff) | |
1703 | { | |
1704 | uint64_t reg; | |
74b0247f | 1705 | |
1da177e4 LT |
1706 | if (sc->sbm_state != sbmac_state_on) |
1707 | return; | |
74b0247f | 1708 | |
1da177e4 | 1709 | if (onoff) { |
2039973a | 1710 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1711 | reg |= M_MAC_ALLPKT_EN; |
2039973a | 1712 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 1713 | } |
1da177e4 | 1714 | else { |
2039973a | 1715 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1716 | reg &= ~M_MAC_ALLPKT_EN; |
2039973a | 1717 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
1718 | } |
1719 | } | |
1720 | ||
1721 | /********************************************************************** | |
1722 | * SBMAC_SETIPHDR_OFFSET(sc,onoff) | |
74b0247f | 1723 | * |
1da177e4 | 1724 | * Set the iphdr offset as 15 assuming ethernet encapsulation |
74b0247f RB |
1725 | * |
1726 | * Input parameters: | |
1da177e4 | 1727 | * sc - softc |
74b0247f | 1728 | * |
1da177e4 LT |
1729 | * Return value: |
1730 | * nothing | |
1731 | ********************************************************************* */ | |
1732 | ||
1733 | static void sbmac_set_iphdr_offset(struct sbmac_softc *sc) | |
1734 | { | |
1735 | uint64_t reg; | |
74b0247f | 1736 | |
1da177e4 | 1737 | /* Hard code the off set to 15 for now */ |
2039973a | 1738 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1739 | reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15); |
2039973a | 1740 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 1741 | |
f90fdc3c RB |
1742 | /* BCM1250 pass1 didn't have hardware checksum. Everything |
1743 | later does. */ | |
1744 | if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) { | |
1da177e4 | 1745 | sc->rx_hw_checksum = DISABLE; |
f90fdc3c RB |
1746 | } else { |
1747 | sc->rx_hw_checksum = ENABLE; | |
1da177e4 LT |
1748 | } |
1749 | } | |
1750 | ||
1751 | ||
1752 | /********************************************************************** | |
1753 | * SBMAC_ADDR2REG(ptr) | |
74b0247f | 1754 | * |
1da177e4 LT |
1755 | * Convert six bytes into the 64-bit register value that |
1756 | * we typically write into the SBMAC's address/mcast registers | |
74b0247f RB |
1757 | * |
1758 | * Input parameters: | |
1da177e4 | 1759 | * ptr - pointer to 6 bytes |
74b0247f | 1760 | * |
1da177e4 LT |
1761 | * Return value: |
1762 | * register value | |
1763 | ********************************************************************* */ | |
1764 | ||
1765 | static uint64_t sbmac_addr2reg(unsigned char *ptr) | |
1766 | { | |
1767 | uint64_t reg = 0; | |
74b0247f | 1768 | |
1da177e4 | 1769 | ptr += 6; |
74b0247f RB |
1770 | |
1771 | reg |= (uint64_t) *(--ptr); | |
1da177e4 | 1772 | reg <<= 8; |
74b0247f | 1773 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1774 | reg <<= 8; |
74b0247f | 1775 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1776 | reg <<= 8; |
74b0247f | 1777 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1778 | reg <<= 8; |
74b0247f | 1779 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1780 | reg <<= 8; |
74b0247f RB |
1781 | reg |= (uint64_t) *(--ptr); |
1782 | ||
1da177e4 LT |
1783 | return reg; |
1784 | } | |
1785 | ||
1786 | ||
1787 | /********************************************************************** | |
1788 | * SBMAC_SET_SPEED(s,speed) | |
74b0247f | 1789 | * |
1da177e4 LT |
1790 | * Configure LAN speed for the specified MAC. |
1791 | * Warning: must be called when MAC is off! | |
74b0247f RB |
1792 | * |
1793 | * Input parameters: | |
1da177e4 | 1794 | * s - sbmac structure |
73d73969 | 1795 | * speed - speed to set MAC to (see enum sbmac_speed) |
74b0247f | 1796 | * |
1da177e4 LT |
1797 | * Return value: |
1798 | * 1 if successful | |
1799 | * 0 indicates invalid parameters | |
1800 | ********************************************************************* */ | |
1801 | ||
73d73969 | 1802 | static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed) |
1da177e4 LT |
1803 | { |
1804 | uint64_t cfg; | |
1805 | uint64_t framecfg; | |
1806 | ||
1807 | /* | |
1808 | * Save new current values | |
1809 | */ | |
74b0247f | 1810 | |
1da177e4 | 1811 | s->sbm_speed = speed; |
74b0247f | 1812 | |
1da177e4 LT |
1813 | if (s->sbm_state == sbmac_state_on) |
1814 | return 0; /* save for next restart */ | |
1815 | ||
1816 | /* | |
74b0247f | 1817 | * Read current register values |
1da177e4 | 1818 | */ |
74b0247f | 1819 | |
2039973a RB |
1820 | cfg = __raw_readq(s->sbm_maccfg); |
1821 | framecfg = __raw_readq(s->sbm_framecfg); | |
74b0247f | 1822 | |
1da177e4 LT |
1823 | /* |
1824 | * Mask out the stuff we want to change | |
1825 | */ | |
74b0247f | 1826 | |
1da177e4 LT |
1827 | cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); |
1828 | framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | | |
1829 | M_MAC_SLOT_SIZE); | |
74b0247f | 1830 | |
1da177e4 LT |
1831 | /* |
1832 | * Now add in the new bits | |
1833 | */ | |
74b0247f | 1834 | |
1da177e4 LT |
1835 | switch (speed) { |
1836 | case sbmac_speed_10: | |
1837 | framecfg |= V_MAC_IFG_RX_10 | | |
1838 | V_MAC_IFG_TX_10 | | |
1839 | K_MAC_IFG_THRSH_10 | | |
1840 | V_MAC_SLOT_SIZE_10; | |
1841 | cfg |= V_MAC_SPEED_SEL_10MBPS; | |
1842 | break; | |
74b0247f | 1843 | |
1da177e4 LT |
1844 | case sbmac_speed_100: |
1845 | framecfg |= V_MAC_IFG_RX_100 | | |
1846 | V_MAC_IFG_TX_100 | | |
1847 | V_MAC_IFG_THRSH_100 | | |
1848 | V_MAC_SLOT_SIZE_100; | |
1849 | cfg |= V_MAC_SPEED_SEL_100MBPS ; | |
1850 | break; | |
74b0247f | 1851 | |
1da177e4 LT |
1852 | case sbmac_speed_1000: |
1853 | framecfg |= V_MAC_IFG_RX_1000 | | |
1854 | V_MAC_IFG_TX_1000 | | |
1855 | V_MAC_IFG_THRSH_1000 | | |
1856 | V_MAC_SLOT_SIZE_1000; | |
1857 | cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; | |
1858 | break; | |
74b0247f | 1859 | |
1da177e4 LT |
1860 | default: |
1861 | return 0; | |
1862 | } | |
74b0247f | 1863 | |
1da177e4 | 1864 | /* |
74b0247f | 1865 | * Send the bits back to the hardware |
1da177e4 | 1866 | */ |
74b0247f | 1867 | |
2039973a RB |
1868 | __raw_writeq(framecfg, s->sbm_framecfg); |
1869 | __raw_writeq(cfg, s->sbm_maccfg); | |
74b0247f | 1870 | |
1da177e4 LT |
1871 | return 1; |
1872 | } | |
1873 | ||
1874 | /********************************************************************** | |
1875 | * SBMAC_SET_DUPLEX(s,duplex,fc) | |
74b0247f | 1876 | * |
1da177e4 LT |
1877 | * Set Ethernet duplex and flow control options for this MAC |
1878 | * Warning: must be called when MAC is off! | |
74b0247f RB |
1879 | * |
1880 | * Input parameters: | |
1da177e4 | 1881 | * s - sbmac structure |
73d73969 MR |
1882 | * duplex - duplex setting (see enum sbmac_duplex) |
1883 | * fc - flow control setting (see enum sbmac_fc) | |
74b0247f | 1884 | * |
1da177e4 LT |
1885 | * Return value: |
1886 | * 1 if ok | |
1887 | * 0 if an invalid parameter combination was specified | |
1888 | ********************************************************************* */ | |
1889 | ||
73d73969 MR |
1890 | static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, |
1891 | enum sbmac_fc fc) | |
1da177e4 LT |
1892 | { |
1893 | uint64_t cfg; | |
74b0247f | 1894 | |
1da177e4 LT |
1895 | /* |
1896 | * Save new current values | |
1897 | */ | |
74b0247f | 1898 | |
1da177e4 LT |
1899 | s->sbm_duplex = duplex; |
1900 | s->sbm_fc = fc; | |
74b0247f | 1901 | |
1da177e4 LT |
1902 | if (s->sbm_state == sbmac_state_on) |
1903 | return 0; /* save for next restart */ | |
74b0247f | 1904 | |
1da177e4 | 1905 | /* |
74b0247f | 1906 | * Read current register values |
1da177e4 | 1907 | */ |
74b0247f | 1908 | |
2039973a | 1909 | cfg = __raw_readq(s->sbm_maccfg); |
74b0247f | 1910 | |
1da177e4 LT |
1911 | /* |
1912 | * Mask off the stuff we're about to change | |
1913 | */ | |
74b0247f | 1914 | |
1da177e4 | 1915 | cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); |
74b0247f RB |
1916 | |
1917 | ||
1da177e4 LT |
1918 | switch (duplex) { |
1919 | case sbmac_duplex_half: | |
1920 | switch (fc) { | |
1921 | case sbmac_fc_disabled: | |
1922 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; | |
1923 | break; | |
74b0247f | 1924 | |
1da177e4 LT |
1925 | case sbmac_fc_collision: |
1926 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; | |
1927 | break; | |
74b0247f | 1928 | |
1da177e4 LT |
1929 | case sbmac_fc_carrier: |
1930 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; | |
1931 | break; | |
74b0247f | 1932 | |
1da177e4 LT |
1933 | case sbmac_fc_frame: /* not valid in half duplex */ |
1934 | default: /* invalid selection */ | |
1935 | return 0; | |
1936 | } | |
1937 | break; | |
74b0247f | 1938 | |
1da177e4 LT |
1939 | case sbmac_duplex_full: |
1940 | switch (fc) { | |
1941 | case sbmac_fc_disabled: | |
1942 | cfg |= V_MAC_FC_CMD_DISABLED; | |
1943 | break; | |
74b0247f | 1944 | |
1da177e4 LT |
1945 | case sbmac_fc_frame: |
1946 | cfg |= V_MAC_FC_CMD_ENABLED; | |
1947 | break; | |
74b0247f | 1948 | |
1da177e4 LT |
1949 | case sbmac_fc_collision: /* not valid in full duplex */ |
1950 | case sbmac_fc_carrier: /* not valid in full duplex */ | |
1da177e4 LT |
1951 | default: |
1952 | return 0; | |
1953 | } | |
1954 | break; | |
f5279ffd MR |
1955 | default: |
1956 | return 0; | |
1da177e4 | 1957 | } |
74b0247f | 1958 | |
1da177e4 | 1959 | /* |
74b0247f | 1960 | * Send the bits back to the hardware |
1da177e4 | 1961 | */ |
74b0247f | 1962 | |
2039973a | 1963 | __raw_writeq(cfg, s->sbm_maccfg); |
74b0247f | 1964 | |
1da177e4 LT |
1965 | return 1; |
1966 | } | |
1967 | ||
1968 | ||
1969 | ||
1970 | ||
1971 | /********************************************************************** | |
1972 | * SBMAC_INTR() | |
74b0247f | 1973 | * |
1da177e4 | 1974 | * Interrupt handler for MAC interrupts |
74b0247f RB |
1975 | * |
1976 | * Input parameters: | |
1da177e4 | 1977 | * MAC structure |
74b0247f | 1978 | * |
1da177e4 LT |
1979 | * Return value: |
1980 | * nothing | |
1981 | ********************************************************************* */ | |
7d12e780 | 1982 | static irqreturn_t sbmac_intr(int irq,void *dev_instance) |
1da177e4 LT |
1983 | { |
1984 | struct net_device *dev = (struct net_device *) dev_instance; | |
1985 | struct sbmac_softc *sc = netdev_priv(dev); | |
1986 | uint64_t isr; | |
1987 | int handled = 0; | |
1988 | ||
693aa947 MM |
1989 | /* |
1990 | * Read the ISR (this clears the bits in the real | |
1991 | * register, except for counter addr) | |
1992 | */ | |
74b0247f | 1993 | |
693aa947 | 1994 | isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR; |
1da177e4 | 1995 | |
693aa947 MM |
1996 | if (isr == 0) |
1997 | return IRQ_RETVAL(0); | |
1998 | handled = 1; | |
74b0247f | 1999 | |
693aa947 MM |
2000 | /* |
2001 | * Transmits on channel 0 | |
2002 | */ | |
74b0247f | 2003 | |
bea3348e | 2004 | if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) |
693aa947 | 2005 | sbdma_tx_process(sc,&(sc->sbm_txdma), 0); |
74b0247f | 2006 | |
693aa947 | 2007 | if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { |
288379f0 | 2008 | if (napi_schedule_prep(&sc->napi)) { |
693aa947 | 2009 | __raw_writeq(0, sc->sbm_imr); |
288379f0 | 2010 | __napi_schedule(&sc->napi); |
693aa947 MM |
2011 | /* Depend on the exit from poll to reenable intr */ |
2012 | } | |
2013 | else { | |
2014 | /* may leave some packets behind */ | |
2015 | sbdma_rx_process(sc,&(sc->sbm_rxdma), | |
2016 | SBMAC_MAX_RXDESCR * 2, 0); | |
1da177e4 LT |
2017 | } |
2018 | } | |
2019 | return IRQ_RETVAL(handled); | |
2020 | } | |
2021 | ||
1da177e4 LT |
2022 | /********************************************************************** |
2023 | * SBMAC_START_TX(skb,dev) | |
74b0247f RB |
2024 | * |
2025 | * Start output on the specified interface. Basically, we | |
1da177e4 LT |
2026 | * queue as many buffers as we can until the ring fills up, or |
2027 | * we run off the end of the queue, whichever comes first. | |
74b0247f RB |
2028 | * |
2029 | * Input parameters: | |
2030 | * | |
2031 | * | |
1da177e4 LT |
2032 | * Return value: |
2033 | * nothing | |
2034 | ********************************************************************* */ | |
2035 | static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev) | |
2036 | { | |
2037 | struct sbmac_softc *sc = netdev_priv(dev); | |
be61ea52 | 2038 | unsigned long flags; |
74b0247f | 2039 | |
1da177e4 | 2040 | /* lock eth irq */ |
be61ea52 | 2041 | spin_lock_irqsave(&sc->sbm_lock, flags); |
74b0247f | 2042 | |
1da177e4 | 2043 | /* |
74b0247f | 2044 | * Put the buffer on the transmit ring. If we |
1da177e4 LT |
2045 | * don't have room, stop the queue. |
2046 | */ | |
74b0247f | 2047 | |
1da177e4 LT |
2048 | if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) { |
2049 | /* XXX save skb that we could not send */ | |
2050 | netif_stop_queue(dev); | |
be61ea52 | 2051 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
1da177e4 | 2052 | |
5b548140 | 2053 | return NETDEV_TX_BUSY; |
1da177e4 | 2054 | } |
74b0247f | 2055 | |
be61ea52 | 2056 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
74b0247f | 2057 | |
6ed10654 | 2058 | return NETDEV_TX_OK; |
1da177e4 LT |
2059 | } |
2060 | ||
2061 | /********************************************************************** | |
2062 | * SBMAC_SETMULTI(sc) | |
74b0247f | 2063 | * |
1da177e4 LT |
2064 | * Reprogram the multicast table into the hardware, given |
2065 | * the list of multicasts associated with the interface | |
2066 | * structure. | |
74b0247f RB |
2067 | * |
2068 | * Input parameters: | |
1da177e4 | 2069 | * sc - softc |
74b0247f | 2070 | * |
1da177e4 LT |
2071 | * Return value: |
2072 | * nothing | |
2073 | ********************************************************************* */ | |
2074 | ||
2075 | static void sbmac_setmulti(struct sbmac_softc *sc) | |
2076 | { | |
2077 | uint64_t reg; | |
73d73969 | 2078 | void __iomem *port; |
1da177e4 | 2079 | int idx; |
22bedad3 | 2080 | struct netdev_hw_addr *ha; |
1da177e4 | 2081 | struct net_device *dev = sc->sbm_dev; |
74b0247f RB |
2082 | |
2083 | /* | |
1da177e4 LT |
2084 | * Clear out entire multicast table. We do this by nuking |
2085 | * the entire hash table and all the direct matches except | |
74b0247f | 2086 | * the first one, which is used for our station address |
1da177e4 | 2087 | */ |
74b0247f | 2088 | |
1da177e4 LT |
2089 | for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { |
2090 | port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)); | |
2039973a | 2091 | __raw_writeq(0, port); |
1da177e4 | 2092 | } |
74b0247f | 2093 | |
1da177e4 LT |
2094 | for (idx = 0; idx < MAC_HASH_COUNT; idx++) { |
2095 | port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t)); | |
2039973a | 2096 | __raw_writeq(0, port); |
1da177e4 | 2097 | } |
74b0247f | 2098 | |
1da177e4 LT |
2099 | /* |
2100 | * Clear the filter to say we don't want any multicasts. | |
2101 | */ | |
74b0247f | 2102 | |
2039973a | 2103 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2104 | reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); |
2039973a | 2105 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 2106 | |
1da177e4 | 2107 | if (dev->flags & IFF_ALLMULTI) { |
74b0247f RB |
2108 | /* |
2109 | * Enable ALL multicasts. Do this by inverting the | |
2110 | * multicast enable bit. | |
1da177e4 | 2111 | */ |
2039973a | 2112 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2113 | reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); |
2039973a | 2114 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
2115 | return; |
2116 | } | |
1da177e4 | 2117 | |
74b0247f RB |
2118 | |
2119 | /* | |
1da177e4 LT |
2120 | * Progam new multicast entries. For now, only use the |
2121 | * perfect filter. In the future we'll need to use the | |
2122 | * hash filter if the perfect filter overflows | |
2123 | */ | |
74b0247f | 2124 | |
1da177e4 LT |
2125 | /* XXX only using perfect filter for now, need to use hash |
2126 | * XXX if the table overflows */ | |
74b0247f | 2127 | |
1da177e4 | 2128 | idx = 1; /* skip station address */ |
22bedad3 | 2129 | netdev_for_each_mc_addr(ha, dev) { |
5508590c JP |
2130 | if (idx == MAC_ADDR_COUNT) |
2131 | break; | |
22bedad3 | 2132 | reg = sbmac_addr2reg(ha->addr); |
1da177e4 | 2133 | port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t)); |
2039973a | 2134 | __raw_writeq(reg, port); |
1da177e4 | 2135 | idx++; |
1da177e4 | 2136 | } |
74b0247f RB |
2137 | |
2138 | /* | |
1da177e4 | 2139 | * Enable the "accept multicast bits" if we programmed at least one |
74b0247f | 2140 | * multicast. |
1da177e4 | 2141 | */ |
74b0247f | 2142 | |
1da177e4 | 2143 | if (idx > 1) { |
2039973a | 2144 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2145 | reg |= M_MAC_MCAST_EN; |
2039973a | 2146 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
2147 | } |
2148 | } | |
2149 | ||
b4cf3421 AB |
2150 | static const struct net_device_ops sbmac_netdev_ops = { |
2151 | .ndo_open = sbmac_open, | |
2152 | .ndo_stop = sbmac_close, | |
2153 | .ndo_start_xmit = sbmac_start_tx, | |
afc4b13d | 2154 | .ndo_set_rx_mode = sbmac_set_rx_mode, |
b4cf3421 AB |
2155 | .ndo_tx_timeout = sbmac_tx_timeout, |
2156 | .ndo_do_ioctl = sbmac_mii_ioctl, | |
b4cf3421 AB |
2157 | .ndo_validate_addr = eth_validate_addr, |
2158 | .ndo_set_mac_address = eth_mac_addr, | |
2159 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2160 | .ndo_poll_controller = sbmac_netpoll, | |
2161 | #endif | |
2162 | }; | |
2163 | ||
1da177e4 LT |
2164 | /********************************************************************** |
2165 | * SBMAC_INIT(dev) | |
74b0247f | 2166 | * |
1da177e4 | 2167 | * Attach routine - init hardware and hook ourselves into linux |
74b0247f RB |
2168 | * |
2169 | * Input parameters: | |
1da177e4 | 2170 | * dev - net_device structure |
74b0247f | 2171 | * |
1da177e4 LT |
2172 | * Return value: |
2173 | * status | |
2174 | ********************************************************************* */ | |
2175 | ||
f5279ffd | 2176 | static int sbmac_init(struct platform_device *pldev, long long base) |
1da177e4 | 2177 | { |
8513fbd8 | 2178 | struct net_device *dev = platform_get_drvdata(pldev); |
f5279ffd MR |
2179 | int idx = pldev->id; |
2180 | struct sbmac_softc *sc = netdev_priv(dev); | |
1da177e4 LT |
2181 | unsigned char *eaddr; |
2182 | uint64_t ea_reg; | |
2183 | int i; | |
2184 | int err; | |
74b0247f | 2185 | |
1da177e4 LT |
2186 | sc->sbm_dev = dev; |
2187 | sc->sbe_idx = idx; | |
74b0247f | 2188 | |
1da177e4 | 2189 | eaddr = sc->sbm_hwaddr; |
74b0247f RB |
2190 | |
2191 | /* | |
877d0310 | 2192 | * Read the ethernet address. The firmware left this programmed |
1da177e4 LT |
2193 | * for us in the ethernet address register for each mac. |
2194 | */ | |
74b0247f | 2195 | |
2039973a RB |
2196 | ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR); |
2197 | __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR); | |
1da177e4 LT |
2198 | for (i = 0; i < 6; i++) { |
2199 | eaddr[i] = (uint8_t) (ea_reg & 0xFF); | |
2200 | ea_reg >>= 8; | |
2201 | } | |
74b0247f | 2202 | |
1da177e4 LT |
2203 | for (i = 0; i < 6; i++) { |
2204 | dev->dev_addr[i] = eaddr[i]; | |
2205 | } | |
74b0247f | 2206 | |
74b0247f | 2207 | /* |
1da177e4 LT |
2208 | * Initialize context (get pointers to registers and stuff), then |
2209 | * allocate the memory for the descriptor tables. | |
2210 | */ | |
74b0247f | 2211 | |
1da177e4 | 2212 | sbmac_initctx(sc); |
74b0247f | 2213 | |
1da177e4 LT |
2214 | /* |
2215 | * Set up Linux device callins | |
2216 | */ | |
74b0247f | 2217 | |
1da177e4 | 2218 | spin_lock_init(&(sc->sbm_lock)); |
74b0247f | 2219 | |
b4cf3421 AB |
2220 | dev->netdev_ops = &sbmac_netdev_ops; |
2221 | dev->watchdog_timeo = TX_TIMEOUT; | |
110447f8 | 2222 | dev->min_mtu = 0; |
d894be57 | 2223 | dev->max_mtu = ENET_PACKET_SIZE; |
bea3348e SH |
2224 | |
2225 | netif_napi_add(dev, &sc->napi, sbmac_poll, 16); | |
1da177e4 | 2226 | |
f5279ffd MR |
2227 | dev->irq = UNIT_INT(idx); |
2228 | ||
1da177e4 LT |
2229 | /* This is needed for PASS2 for Rx H/W checksum feature */ |
2230 | sbmac_set_iphdr_offset(sc); | |
2231 | ||
298cf9be LB |
2232 | sc->mii_bus = mdiobus_alloc(); |
2233 | if (sc->mii_bus == NULL) { | |
03f80cc3 SS |
2234 | err = -ENOMEM; |
2235 | goto uninit_ctx; | |
298cf9be LB |
2236 | } |
2237 | ||
03f80cc3 | 2238 | sc->mii_bus->name = sbmac_mdio_string; |
446bbc4b FF |
2239 | snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
2240 | pldev->name, idx); | |
03f80cc3 SS |
2241 | sc->mii_bus->priv = sc; |
2242 | sc->mii_bus->read = sbmac_mii_read; | |
2243 | sc->mii_bus->write = sbmac_mii_write; | |
03f80cc3 SS |
2244 | |
2245 | sc->mii_bus->parent = &pldev->dev; | |
2246 | /* | |
2247 | * Probe PHY address | |
2248 | */ | |
2249 | err = mdiobus_register(sc->mii_bus); | |
2250 | if (err) { | |
2251 | printk(KERN_ERR "%s: unable to register MDIO bus\n", | |
2252 | dev->name); | |
2253 | goto free_mdio; | |
2254 | } | |
8513fbd8 | 2255 | platform_set_drvdata(pldev, sc->mii_bus); |
03f80cc3 | 2256 | |
1da177e4 | 2257 | err = register_netdev(dev); |
f5279ffd MR |
2258 | if (err) { |
2259 | printk(KERN_ERR "%s.%d: unable to register netdev\n", | |
2260 | sbmac_string, idx); | |
03f80cc3 | 2261 | goto unreg_mdio; |
1da177e4 LT |
2262 | } |
2263 | ||
f5279ffd MR |
2264 | pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name); |
2265 | ||
2266 | if (sc->rx_hw_checksum == ENABLE) | |
2267 | pr_info("%s: enabling TCP rcv checksum\n", dev->name); | |
2268 | ||
1da177e4 LT |
2269 | /* |
2270 | * Display Ethernet address (this is called during the config | |
2271 | * process so we need to finish off the config message that | |
2272 | * was being displayed) | |
2273 | */ | |
e174961c JB |
2274 | pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n", |
2275 | dev->name, base, eaddr); | |
1da177e4 | 2276 | |
f5279ffd | 2277 | return 0; |
03f80cc3 SS |
2278 | unreg_mdio: |
2279 | mdiobus_unregister(sc->mii_bus); | |
03f80cc3 SS |
2280 | free_mdio: |
2281 | mdiobus_free(sc->mii_bus); | |
2282 | uninit_ctx: | |
2283 | sbmac_uninitctx(sc); | |
2284 | return err; | |
1da177e4 LT |
2285 | } |
2286 | ||
2287 | ||
2288 | static int sbmac_open(struct net_device *dev) | |
2289 | { | |
2290 | struct sbmac_softc *sc = netdev_priv(dev); | |
f5279ffd | 2291 | int err; |
74b0247f | 2292 | |
f5279ffd MR |
2293 | if (debug > 1) |
2294 | pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq); | |
74b0247f RB |
2295 | |
2296 | /* | |
1da177e4 LT |
2297 | * map/route interrupt (clear status first, in case something |
2298 | * weird is pending; we haven't initialized the mac registers | |
2299 | * yet) | |
2300 | */ | |
2301 | ||
2039973a | 2302 | __raw_readq(sc->sbm_isr); |
a0607fd3 | 2303 | err = request_irq(dev->irq, sbmac_intr, IRQF_SHARED, dev->name, dev); |
f5279ffd MR |
2304 | if (err) { |
2305 | printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name, | |
2306 | dev->irq); | |
2307 | goto out_err; | |
2308 | } | |
1da177e4 | 2309 | |
f5279ffd MR |
2310 | sc->sbm_speed = sbmac_speed_none; |
2311 | sc->sbm_duplex = sbmac_duplex_none; | |
2312 | sc->sbm_fc = sbmac_fc_none; | |
2313 | sc->sbm_pause = -1; | |
2314 | sc->sbm_link = 0; | |
bea3348e | 2315 | |
1da177e4 | 2316 | /* |
f5279ffd | 2317 | * Attach to the PHY |
1da177e4 | 2318 | */ |
f5279ffd MR |
2319 | err = sbmac_mii_probe(dev); |
2320 | if (err) | |
2321 | goto out_unregister; | |
74b0247f | 2322 | |
1da177e4 LT |
2323 | /* |
2324 | * Turn on the channel | |
2325 | */ | |
2326 | ||
2327 | sbmac_set_channel_state(sc,sbmac_state_on); | |
74b0247f | 2328 | |
1da177e4 | 2329 | netif_start_queue(dev); |
74b0247f | 2330 | |
1da177e4 | 2331 | sbmac_set_rx_mode(dev); |
74b0247f | 2332 | |
f5279ffd MR |
2333 | phy_start(sc->phy_dev); |
2334 | ||
2335 | napi_enable(&sc->napi); | |
74b0247f | 2336 | |
1da177e4 | 2337 | return 0; |
f5279ffd MR |
2338 | |
2339 | out_unregister: | |
f5279ffd | 2340 | free_irq(dev->irq, dev); |
f5279ffd MR |
2341 | out_err: |
2342 | return err; | |
1da177e4 LT |
2343 | } |
2344 | ||
59b81827 RB |
2345 | static int sbmac_mii_probe(struct net_device *dev) |
2346 | { | |
f5279ffd MR |
2347 | struct sbmac_softc *sc = netdev_priv(dev); |
2348 | struct phy_device *phy_dev; | |
1da177e4 | 2349 | |
ee64f08e | 2350 | phy_dev = phy_find_first(sc->mii_bus); |
f5279ffd MR |
2351 | if (!phy_dev) { |
2352 | printk(KERN_ERR "%s: no PHY found\n", dev->name); | |
2353 | return -ENXIO; | |
1da177e4 LT |
2354 | } |
2355 | ||
e5a03bfd AL |
2356 | phy_dev = phy_connect(dev, dev_name(&phy_dev->mdio.dev), |
2357 | &sbmac_mii_poll, PHY_INTERFACE_MODE_GMII); | |
f5279ffd MR |
2358 | if (IS_ERR(phy_dev)) { |
2359 | printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); | |
2360 | return PTR_ERR(phy_dev); | |
1da177e4 LT |
2361 | } |
2362 | ||
f5279ffd MR |
2363 | /* Remove any features not supported by the controller */ |
2364 | phy_dev->supported &= SUPPORTED_10baseT_Half | | |
2365 | SUPPORTED_10baseT_Full | | |
2366 | SUPPORTED_100baseT_Half | | |
2367 | SUPPORTED_100baseT_Full | | |
2368 | SUPPORTED_1000baseT_Half | | |
2369 | SUPPORTED_1000baseT_Full | | |
2370 | SUPPORTED_Autoneg | | |
2371 | SUPPORTED_MII | | |
2372 | SUPPORTED_Pause | | |
2373 | SUPPORTED_Asym_Pause; | |
f5279ffd | 2374 | |
ee64f08e | 2375 | phy_attached_info(phy_dev); |
2220943a AL |
2376 | |
2377 | phy_dev->advertising = phy_dev->supported; | |
f5279ffd MR |
2378 | |
2379 | sc->phy_dev = phy_dev; | |
1da177e4 | 2380 | |
f5279ffd | 2381 | return 0; |
1da177e4 LT |
2382 | } |
2383 | ||
2384 | ||
f5279ffd | 2385 | static void sbmac_mii_poll(struct net_device *dev) |
1da177e4 | 2386 | { |
1da177e4 | 2387 | struct sbmac_softc *sc = netdev_priv(dev); |
f5279ffd MR |
2388 | struct phy_device *phy_dev = sc->phy_dev; |
2389 | unsigned long flags; | |
2390 | enum sbmac_fc fc; | |
2391 | int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg; | |
2392 | ||
2393 | link_chg = (sc->sbm_link != phy_dev->link); | |
2394 | speed_chg = (sc->sbm_speed != phy_dev->speed); | |
2395 | duplex_chg = (sc->sbm_duplex != phy_dev->duplex); | |
2396 | pause_chg = (sc->sbm_pause != phy_dev->pause); | |
2397 | ||
2398 | if (!link_chg && !speed_chg && !duplex_chg && !pause_chg) | |
2399 | return; /* Hmmm... */ | |
2400 | ||
2401 | if (!phy_dev->link) { | |
2402 | if (link_chg) { | |
2403 | sc->sbm_link = phy_dev->link; | |
2404 | sc->sbm_speed = sbmac_speed_none; | |
2405 | sc->sbm_duplex = sbmac_duplex_none; | |
2406 | sc->sbm_fc = sbmac_fc_disabled; | |
2407 | sc->sbm_pause = -1; | |
2408 | pr_info("%s: link unavailable\n", dev->name); | |
2409 | } | |
2410 | return; | |
2411 | } | |
1da177e4 | 2412 | |
f5279ffd MR |
2413 | if (phy_dev->duplex == DUPLEX_FULL) { |
2414 | if (phy_dev->pause) | |
2415 | fc = sbmac_fc_frame; | |
2416 | else | |
2417 | fc = sbmac_fc_disabled; | |
2418 | } else | |
2419 | fc = sbmac_fc_collision; | |
2420 | fc_chg = (sc->sbm_fc != fc); | |
74b0247f | 2421 | |
f5279ffd MR |
2422 | pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed, |
2423 | phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H'); | |
74b0247f | 2424 | |
f5279ffd | 2425 | spin_lock_irqsave(&sc->sbm_lock, flags); |
74b0247f | 2426 | |
f5279ffd MR |
2427 | sc->sbm_speed = phy_dev->speed; |
2428 | sc->sbm_duplex = phy_dev->duplex; | |
2429 | sc->sbm_fc = fc; | |
2430 | sc->sbm_pause = phy_dev->pause; | |
2431 | sc->sbm_link = phy_dev->link; | |
1da177e4 | 2432 | |
f5279ffd MR |
2433 | if ((speed_chg || duplex_chg || fc_chg) && |
2434 | sc->sbm_state != sbmac_state_off) { | |
2435 | /* | |
2436 | * something changed, restart the channel | |
2437 | */ | |
2438 | if (debug > 1) | |
2439 | pr_debug("%s: restarting channel " | |
2440 | "because PHY state changed\n", dev->name); | |
2441 | sbmac_channel_stop(sc); | |
2442 | sbmac_channel_start(sc); | |
1da177e4 | 2443 | } |
74b0247f | 2444 | |
f5279ffd | 2445 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
1da177e4 LT |
2446 | } |
2447 | ||
2448 | ||
2449 | static void sbmac_tx_timeout (struct net_device *dev) | |
2450 | { | |
2451 | struct sbmac_softc *sc = netdev_priv(dev); | |
be61ea52 | 2452 | unsigned long flags; |
74b0247f | 2453 | |
be61ea52 | 2454 | spin_lock_irqsave(&sc->sbm_lock, flags); |
74b0247f RB |
2455 | |
2456 | ||
860e9538 | 2457 | netif_trans_update(dev); /* prevent tx timeout */ |
09f75cd7 | 2458 | dev->stats.tx_errors++; |
74b0247f | 2459 | |
be61ea52 | 2460 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
1da177e4 LT |
2461 | |
2462 | printk (KERN_WARNING "%s: Transmit timed out\n",dev->name); | |
2463 | } | |
2464 | ||
2465 | ||
2466 | ||
2467 | ||
1da177e4 LT |
2468 | static void sbmac_set_rx_mode(struct net_device *dev) |
2469 | { | |
2470 | unsigned long flags; | |
1da177e4 LT |
2471 | struct sbmac_softc *sc = netdev_priv(dev); |
2472 | ||
2473 | spin_lock_irqsave(&sc->sbm_lock, flags); | |
2474 | if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) { | |
2475 | /* | |
2476 | * Promiscuous changed. | |
2477 | */ | |
74b0247f RB |
2478 | |
2479 | if (dev->flags & IFF_PROMISC) { | |
1da177e4 LT |
2480 | sbmac_promiscuous_mode(sc,1); |
2481 | } | |
2482 | else { | |
1da177e4 LT |
2483 | sbmac_promiscuous_mode(sc,0); |
2484 | } | |
2485 | } | |
2486 | spin_unlock_irqrestore(&sc->sbm_lock, flags); | |
74b0247f | 2487 | |
1da177e4 LT |
2488 | /* |
2489 | * Program the multicasts. Do this every time. | |
2490 | */ | |
74b0247f | 2491 | |
1da177e4 | 2492 | sbmac_setmulti(sc); |
74b0247f | 2493 | |
1da177e4 LT |
2494 | } |
2495 | ||
2496 | static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2497 | { | |
2498 | struct sbmac_softc *sc = netdev_priv(dev); | |
74b0247f | 2499 | |
f5279ffd MR |
2500 | if (!netif_running(dev) || !sc->phy_dev) |
2501 | return -EINVAL; | |
74b0247f | 2502 | |
28b04113 | 2503 | return phy_mii_ioctl(sc->phy_dev, rq, cmd); |
1da177e4 LT |
2504 | } |
2505 | ||
2506 | static int sbmac_close(struct net_device *dev) | |
2507 | { | |
2508 | struct sbmac_softc *sc = netdev_priv(dev); | |
1da177e4 | 2509 | |
bea3348e SH |
2510 | napi_disable(&sc->napi); |
2511 | ||
f5279ffd | 2512 | phy_stop(sc->phy_dev); |
1da177e4 | 2513 | |
f5279ffd | 2514 | sbmac_set_channel_state(sc, sbmac_state_off); |
1da177e4 LT |
2515 | |
2516 | netif_stop_queue(dev); | |
2517 | ||
f5279ffd MR |
2518 | if (debug > 1) |
2519 | pr_debug("%s: Shutting down ethercard\n", dev->name); | |
1da177e4 | 2520 | |
f5279ffd MR |
2521 | phy_disconnect(sc->phy_dev); |
2522 | sc->phy_dev = NULL; | |
f5279ffd | 2523 | free_irq(dev->irq, dev); |
1da177e4 LT |
2524 | |
2525 | sbdma_emptyring(&(sc->sbm_txdma)); | |
2526 | sbdma_emptyring(&(sc->sbm_rxdma)); | |
74b0247f | 2527 | |
1da177e4 LT |
2528 | return 0; |
2529 | } | |
2530 | ||
bea3348e | 2531 | static int sbmac_poll(struct napi_struct *napi, int budget) |
693aa947 | 2532 | { |
bea3348e | 2533 | struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi); |
693aa947 | 2534 | int work_done; |
1da177e4 | 2535 | |
bea3348e | 2536 | work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1); |
693aa947 MM |
2537 | sbdma_tx_process(sc, &(sc->sbm_txdma), 1); |
2538 | ||
bea3348e | 2539 | if (work_done < budget) { |
6ad20165 | 2540 | napi_complete_done(napi, work_done); |
693aa947 MM |
2541 | |
2542 | #ifdef CONFIG_SBMAC_COALESCE | |
2543 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | | |
2544 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), | |
2545 | sc->sbm_imr); | |
2546 | #else | |
2547 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | | |
2548 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); | |
2549 | #endif | |
2550 | } | |
2551 | ||
bea3348e | 2552 | return work_done; |
693aa947 | 2553 | } |
1da177e4 | 2554 | |
f5279ffd | 2555 | |
047fc566 | 2556 | static int sbmac_probe(struct platform_device *pldev) |
f5279ffd MR |
2557 | { |
2558 | struct net_device *dev; | |
2559 | struct sbmac_softc *sc; | |
2560 | void __iomem *sbm_base; | |
2561 | struct resource *res; | |
2562 | u64 sbmac_orig_hwaddr; | |
2563 | int err; | |
2564 | ||
2565 | res = platform_get_resource(pldev, IORESOURCE_MEM, 0); | |
2566 | BUG_ON(!res); | |
28f65c11 | 2567 | sbm_base = ioremap_nocache(res->start, resource_size(res)); |
f5279ffd MR |
2568 | if (!sbm_base) { |
2569 | printk(KERN_ERR "%s: unable to map device registers\n", | |
db1d7bf7 | 2570 | dev_name(&pldev->dev)); |
f5279ffd MR |
2571 | err = -ENOMEM; |
2572 | goto out_out; | |
2573 | } | |
2574 | ||
2575 | /* | |
2576 | * The R_MAC_ETHERNET_ADDR register will be set to some nonzero | |
2577 | * value for us by the firmware if we're going to use this MAC. | |
2578 | * If we find a zero, skip this MAC. | |
2579 | */ | |
2580 | sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR); | |
db1d7bf7 | 2581 | pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev->dev), |
f5279ffd MR |
2582 | sbmac_orig_hwaddr ? "" : "not ", (long long)res->start); |
2583 | if (sbmac_orig_hwaddr == 0) { | |
2584 | err = 0; | |
2585 | goto out_unmap; | |
2586 | } | |
2587 | ||
2588 | /* | |
2589 | * Okay, cool. Initialize this MAC. | |
2590 | */ | |
2591 | dev = alloc_etherdev(sizeof(struct sbmac_softc)); | |
2592 | if (!dev) { | |
f5279ffd MR |
2593 | err = -ENOMEM; |
2594 | goto out_unmap; | |
2595 | } | |
2596 | ||
8513fbd8 | 2597 | platform_set_drvdata(pldev, dev); |
f5279ffd MR |
2598 | SET_NETDEV_DEV(dev, &pldev->dev); |
2599 | ||
2600 | sc = netdev_priv(dev); | |
2601 | sc->sbm_base = sbm_base; | |
2602 | ||
2603 | err = sbmac_init(pldev, res->start); | |
2604 | if (err) | |
2605 | goto out_kfree; | |
2606 | ||
2607 | return 0; | |
2608 | ||
2609 | out_kfree: | |
2610 | free_netdev(dev); | |
2611 | __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR); | |
2612 | ||
2613 | out_unmap: | |
2614 | iounmap(sbm_base); | |
2615 | ||
2616 | out_out: | |
2617 | return err; | |
2618 | } | |
2619 | ||
be12502e | 2620 | static int sbmac_remove(struct platform_device *pldev) |
f5279ffd | 2621 | { |
8513fbd8 | 2622 | struct net_device *dev = platform_get_drvdata(pldev); |
f5279ffd MR |
2623 | struct sbmac_softc *sc = netdev_priv(dev); |
2624 | ||
2625 | unregister_netdev(dev); | |
2626 | sbmac_uninitctx(sc); | |
03f80cc3 | 2627 | mdiobus_unregister(sc->mii_bus); |
298cf9be | 2628 | mdiobus_free(sc->mii_bus); |
f5279ffd MR |
2629 | iounmap(sc->sbm_base); |
2630 | free_netdev(dev); | |
2631 | ||
2632 | return 0; | |
2633 | } | |
2634 | ||
f5279ffd MR |
2635 | static struct platform_driver sbmac_driver = { |
2636 | .probe = sbmac_probe, | |
be12502e | 2637 | .remove = sbmac_remove, |
f5279ffd MR |
2638 | .driver = { |
2639 | .name = sbmac_string, | |
2640 | }, | |
2641 | }; | |
1da177e4 | 2642 | |
db62f684 | 2643 | module_platform_driver(sbmac_driver); |