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ptp: expose the programmable pins via sysfs
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / broadcom / tg3.c
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1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
b681b65d 7 * Copyright (C) 2005-2013 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
a6b7a407 28#include <linux/interrupt.h>
1da177e4
LT		 29#include <linux/ioport.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ethtool.h>
3110f5f5 35#include <linux/mdio.h>
1da177e4 36#include <linux/mii.h>
158d7abd 37#include <linux/phy.h>
a9daf367 38#include <linux/brcmphy.h>
e565eec3 39#include <linux/if.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
20170e77 97#define TG3_MIN_NUM 136
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
20170e77 100#define DRV_MODULE_RELDATE "Jan 03, 2014"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
e565eec3
MC		 211#define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212#define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
213
c6cdf436 214#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 215#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 216
077f849d 217#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 218#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 219#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
221
229b1ad1 222static char version[] =
05dbe005 223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 224
225MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227MODULE_LICENSE("GPL");
228MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 229MODULE_FIRMWARE(FIRMWARE_TG3);
230MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
232
1da177e4
LT		 233static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234module_param(tg3_debug, int, 0);
235MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
236
3d567e0e
NNS		 237#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
239
a3aa1884 240static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
68273712
NS		 343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
13185217
HK		 348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 356 {}
1da177e4
LT		 357};
358
359MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
360
50da859d 361static const struct {
1da177e4 362 const char string[ETH_GSTRING_LEN];
48fa55a0 363} ethtool_stats_keys[] = {
1da177e4
LT		 364 { "rx_octets" },
365 { "rx_fragments" },
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
369 { "rx_fcs_errors" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
376 { "rx_jabbers" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
390
391 { "tx_octets" },
392 { "tx_collisions" },
393
394 { "tx_xon_sent" },
395 { "tx_xoff_sent" },
396 { "tx_flow_control" },
397 { "tx_mac_errors" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
400 { "tx_deferred" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
421 { "tx_discards" },
422 { "tx_errors" },
423
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
426 { "rxbds_empty" },
427 { "rx_discards" },
428 { "rx_errors" },
429 { "rx_threshold_hit" },
430
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
434
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
437 { "nic_irqs" },
438 { "nic_avoided_irqs" },
4452d099
MC		 439 { "nic_tx_threshold_hit" },
440
441 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 442};
443
48fa55a0 444#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 445#define TG3_NVRAM_TEST 0
446#define TG3_LINK_TEST 1
447#define TG3_REGISTER_TEST 2
448#define TG3_MEMORY_TEST 3
449#define TG3_MAC_LOOPB_TEST 4
450#define TG3_PHY_LOOPB_TEST 5
451#define TG3_EXT_LOOPB_TEST 6
452#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 453
454
50da859d 455static const struct {
4cafd3f5 456 const char string[ETH_GSTRING_LEN];
48fa55a0 457} ethtool_test_keys[] = {
93df8b8f
NNS		 458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 466};
467
48fa55a0
MC		 468#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
469
470
b401e9e2
MC		 471static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
472{
473 writel(val, tp->regs + off);
474}
475
476static u32 tg3_read32(struct tg3 *tp, u32 off)
477{
de6f31eb 478 return readl(tp->regs + off);
b401e9e2
MC		 479}
480
0d3031d9
MC		 481static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
482{
483 writel(val, tp->aperegs + off);
484}
485
486static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
487{
de6f31eb 488 return readl(tp->aperegs + off);
0d3031d9
MC		 489}
490
1da177e4
LT		 491static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
492{
6892914f
MC		 493 unsigned long flags;
494
495 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 499}
500
501static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
502{
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
1da177e4
LT		 505}
506
6892914f 507static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 508{
6892914f
MC		 509 unsigned long flags;
510 u32 val;
511
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 return val;
517}
518
519static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
520{
521 unsigned long flags;
522
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
526 return;
527 }
66711e66 528 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
531 return;
1da177e4 532 }
6892914f
MC		 533
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
538
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
541 */
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
543 (val == 0x1)) {
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
546 }
547}
548
549static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
550{
551 unsigned long flags;
552 u32 val;
553
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 return val;
559}
560
b401e9e2
MC		 561/* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
565 */
566static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 567{
63c3a66f 568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 569 /* Non-posted methods */
570 tp->write32(tp, off, val);
571 else {
572 /* Posted method */
573 tg3_write32(tp, off, val);
574 if (usec_wait)
575 udelay(usec_wait);
576 tp->read32(tp, off);
577 }
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
580 */
581 if (usec_wait)
582 udelay(usec_wait);
1da177e4
LT		 583}
584
09ee929c
MC		 585static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
586{
587 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 591 tp->read32_mbox(tp, off);
09ee929c
MC		 592}
593
20094930 594static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 595{
596 void __iomem *mbox = tp->regs + off;
597 writel(val, mbox);
63c3a66f 598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 599 writel(val, mbox);
7e6c63f0
HM		 600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 602 readl(mbox);
603}
604
b5d3772c
MC		 605static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
606{
de6f31eb 607 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 608}
609
610static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
611{
612 writel(val, tp->regs + off + GRCMBOX_BASE);
613}
614
c6cdf436 615#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 616#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 617#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 620
c6cdf436
MC		 621#define tw32(reg, val) tp->write32(tp, reg, val)
622#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 625
626static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
627{
6892914f
MC		 628 unsigned long flags;
629
4153577a 630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
632 return;
633
6892914f 634 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 638
bbadf503
MC		 639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
641 } else {
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 644
bbadf503
MC		 645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
647 }
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 649}
650
1da177e4
LT		 651static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
652{
6892914f
MC		 653 unsigned long flags;
654
4153577a 655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
657 *val = 0;
658 return;
659 }
660
6892914f 661 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 665
bbadf503
MC		 666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
668 } else {
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
671
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
674 }
6892914f 675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 676}
677
0d3031d9
MC		 678static void tg3_ape_lock_init(struct tg3 *tp)
679{
680 int i;
6f5c8f83 681 u32 regbase, bit;
f92d9dc1 682
4153577a 683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 684 regbase = TG3_APE_LOCK_GRANT;
685 else
686 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 687
688 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
690 switch (i) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
696 break;
697 default:
698 if (!tp->pci_fn)
699 bit = APE_LOCK_GRANT_DRIVER;
700 else
701 bit = 1 << tp->pci_fn;
702 }
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 704 }
705
0d3031d9
MC		 706}
707
708static int tg3_ape_lock(struct tg3 *tp, int locknum)
709{
710 int i, off;
711 int ret = 0;
6f5c8f83 712 u32 status, req, gnt, bit;
0d3031d9 713
63c3a66f 714 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 715 return 0;
716
717 switch (locknum) {
6f5c8f83 718 case TG3_APE_LOCK_GPIO:
4153577a 719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 720 return 0;
33f401ae
MC		 721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 723 if (!tp->pci_fn)
724 bit = APE_LOCK_REQ_DRIVER;
725 else
726 bit = 1 << tp->pci_fn;
33f401ae 727 break;
8151ad57
MC		 728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
733 break;
33f401ae
MC		 734 default:
735 return -EINVAL;
0d3031d9
MC		 736 }
737
4153577a 738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
741 } else {
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
744 }
745
0d3031d9
MC		 746 off = 4 * locknum;
747
6f5c8f83 748 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 749
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
f92d9dc1 752 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 753 if (status == bit)
0d3031d9 754 break;
6d446ec3
GS		 755 if (pci_channel_offline(tp->pdev))
756 break;
757
0d3031d9
MC		 758 udelay(10);
759 }
760
6f5c8f83 761 if (status != bit) {
0d3031d9 762 /* Revoke the lock request. */
6f5c8f83 763 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 764 ret = -EBUSY;
765 }
766
767 return ret;
768}
769
770static void tg3_ape_unlock(struct tg3 *tp, int locknum)
771{
6f5c8f83 772 u32 gnt, bit;
0d3031d9 773
63c3a66f 774 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 775 return;
776
777 switch (locknum) {
6f5c8f83 778 case TG3_APE_LOCK_GPIO:
4153577a 779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 780 return;
33f401ae
MC		 781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 783 if (!tp->pci_fn)
784 bit = APE_LOCK_GRANT_DRIVER;
785 else
786 bit = 1 << tp->pci_fn;
33f401ae 787 break;
8151ad57
MC		 788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
793 break;
33f401ae
MC		 794 default:
795 return;
0d3031d9
MC		 796 }
797
4153577a 798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 799 gnt = TG3_APE_LOCK_GRANT;
800 else
801 gnt = TG3_APE_PER_LOCK_GRANT;
802
6f5c8f83 803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 804}
805
b65a372b 806static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 807{
fd6d3f0e
MC		 808 u32 apedata;
809
b65a372b
MC		 810 while (timeout_us) {
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
812 return -EBUSY;
813
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
816 break;
817
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
819
820 udelay(10);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
822 }
823
824 return timeout_us ? 0 : -EBUSY;
825}
826
cf8d55ae
MC		 827static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
828{
829 u32 i, apedata;
830
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
833
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
835 break;
836
837 udelay(10);
838 }
839
840 return i == timeout_us / 10;
841}
842
86449944
MC		 843static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
844 u32 len)
cf8d55ae
MC		 845{
846 int err;
847 u32 i, bufoff, msgoff, maxlen, apedata;
848
849 if (!tg3_flag(tp, APE_HAS_NCSI))
850 return 0;
851
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
854 return -ENODEV;
855
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
858 return -EAGAIN;
859
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
861 TG3_APE_SHMEM_BASE;
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
864
865 while (len) {
866 u32 length;
867
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
870 len -= length;
871
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
874 return -EAGAIN;
875
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
878 if (err)
879 return err;
880
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
885
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
888
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
891
892 base_off += length;
893
894 if (tg3_ape_wait_for_event(tp, 30000))
895 return -EAGAIN;
896
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
900 data++;
901 }
902 }
903
904 return 0;
905}
906
b65a372b
MC		 907static int tg3_ape_send_event(struct tg3 *tp, u32 event)
908{
909 int err;
910 u32 apedata;
fd6d3f0e
MC		 911
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 914 return -EAGAIN;
fd6d3f0e
MC		 915
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 918 return -EAGAIN;
fd6d3f0e
MC		 919
920 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 921 err = tg3_ape_event_lock(tp, 1000);
922 if (err)
923 return err;
fd6d3f0e 924
b65a372b
MC		 925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 927
b65a372b
MC		 928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 930
b65a372b 931 return 0;
fd6d3f0e
MC		 932}
933
934static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
935{
936 u32 event;
937 u32 apedata;
938
939 if (!tg3_flag(tp, ENABLE_APE))
940 return;
941
942 switch (kind) {
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
956
957 event = APE_EVENT_STATUS_STATE_START;
958 break;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
964 */
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
966
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
972 } else
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
974
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
976
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
978 break;
fd6d3f0e
MC		 979 default:
980 return;
981 }
982
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
984
985 tg3_ape_send_event(tp, event);
986}
987
1da177e4
LT		 988static void tg3_disable_ints(struct tg3 *tp)
989{
89aeb3bc
MC		 990 int i;
991
1da177e4
LT		 992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 996}
997
1da177e4
LT		 998static void tg3_enable_ints(struct tg3 *tp)
999{
89aeb3bc 1000 int i;
89aeb3bc 1001
bbe832c0
MC		 1002 tp->irq_sync = 0;
1003 wmb();
1004
1da177e4
LT		 1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 1007
f89f38b8 1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1011
898a56f8 1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1013 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1015
f89f38b8 1016 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1017 }
f19af9c2
MC		 1018
1019 /* Force an initial interrupt */
63c3a66f 1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1023 else
f89f38b8
MC		 1024 tw32(HOSTCC_MODE, tp->coal_now);
1025
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1027}
1028
17375d25 1029static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1030{
17375d25 1031 struct tg3 *tp = tnapi->tp;
898a56f8 1032 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1033 unsigned int work_exists = 0;
1034
1035 /* check for phy events */
63c3a66f 1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1037 if (sblk->status & SD_STATUS_LINK_CHG)
1038 work_exists = 1;
1039 }
f891ea16
MC		 1040
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1043 work_exists = 1;
1044
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1048 work_exists = 1;
1049
1050 return work_exists;
1051}
1052
17375d25 1053/* tg3_int_reenable
04237ddd
MC		 1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
6aa20a22 1056 * which reenables interrupts
1da177e4 1057 */
17375d25 1058static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1059{
17375d25
MC		 1060 struct tg3 *tp = tnapi->tp;
1061
898a56f8 1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1063 mmiowb();
1064
fac9b83e
DM		 1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1068 */
63c3a66f 1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1072}
1073
1da177e4
LT		 1074static void tg3_switch_clocks(struct tg3 *tp)
1075{
f6eb9b1f 1076 u32 clock_ctrl;
1da177e4
LT		 1077 u32 orig_clock_ctrl;
1078
63c3a66f 1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1080 return;
1081
f6eb9b1f
MC		 1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1083
1da177e4
LT		 1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1087 0x1f);
1088 tp->pci_clock_ctrl = clock_ctrl;
1089
63c3a66f 1090 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1094 }
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1097 clock_ctrl |
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1099 40);
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1102 40);
1da177e4 1103 }
b401e9e2 1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1105}
1106
1107#define PHY_BUSY_LOOPS 5000
1108
5c358045
HM		 1109static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1110 u32 *val)
1da177e4
LT		 1111{
1112 u32 frame_val;
1113 unsigned int loops;
1114 int ret;
1115
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1117 tw32_f(MAC_MI_MODE,
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1119 udelay(80);
1120 }
1121
8151ad57
MC		 1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1123
1da177e4
LT		 1124 *val = 0x0;
1125
5c358045 1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1131
1da177e4
LT		 1132 tw32_f(MAC_MI_COM, frame_val);
1133
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1136 udelay(10);
1137 frame_val = tr32(MAC_MI_COM);
1138
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1140 udelay(5);
1141 frame_val = tr32(MAC_MI_COM);
1142 break;
1143 }
1144 loops -= 1;
1145 }
1146
1147 ret = -EBUSY;
1148 if (loops != 0) {
1149 *val = frame_val & MI_COM_DATA_MASK;
1150 ret = 0;
1151 }
1152
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1155 udelay(80);
1156 }
1157
8151ad57
MC		 1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1159
1da177e4
LT		 1160 return ret;
1161}
1162
5c358045
HM		 1163static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1164{
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1166}
1167
1168static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1169 u32 val)
1da177e4
LT		 1170{
1171 u32 frame_val;
1172 unsigned int loops;
1173 int ret;
1174
f07e9af3 1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1177 return 0;
1178
1da177e4
LT		 1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1180 tw32_f(MAC_MI_MODE,
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1182 udelay(80);
1183 }
1184
8151ad57
MC		 1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1186
5c358045 1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1193
1da177e4
LT		 1194 tw32_f(MAC_MI_COM, frame_val);
1195
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1198 udelay(10);
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1201 udelay(5);
1202 frame_val = tr32(MAC_MI_COM);
1203 break;
1204 }
1205 loops -= 1;
1206 }
1207
1208 ret = -EBUSY;
1209 if (loops != 0)
1210 ret = 0;
1211
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1214 udelay(80);
1215 }
1216
8151ad57
MC		 1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1218
1da177e4
LT		 1219 return ret;
1220}
1221
5c358045
HM		 1222static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1223{
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1225}
1226
b0988c15
MC		 1227static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1228{
1229 int err;
1230
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1232 if (err)
1233 goto done;
1234
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1236 if (err)
1237 goto done;
1238
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1241 if (err)
1242 goto done;
1243
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1245
1246done:
1247 return err;
1248}
1249
1250static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1251{
1252 int err;
1253
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1255 if (err)
1256 goto done;
1257
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1259 if (err)
1260 goto done;
1261
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1264 if (err)
1265 goto done;
1266
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1268
1269done:
1270 return err;
1271}
1272
1273static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1274{
1275 int err;
1276
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1278 if (!err)
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1280
1281 return err;
1282}
1283
1284static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1285{
1286 int err;
1287
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1289 if (!err)
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1291
1292 return err;
1293}
1294
15ee95c3
MC		 1295static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1296{
1297 int err;
1298
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1302 if (!err)
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1304
1305 return err;
1306}
1307
b4bd2929
MC		 1308static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1309{
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1312
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1314}
1315
daf3ec68
NNS		 1316static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1317{
1318 u32 val;
1319 int err;
1d36ba45 1320
daf3ec68 1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1322
daf3ec68
NNS		 1323 if (err)
1324 return err;
daf3ec68 1325
7c10ee32 1326 if (enable)
daf3ec68
NNS		 1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1328 else
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1330
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1333
1334 return err;
1335}
1d36ba45 1336
3ab71071
NS		 1337static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1338{
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1341}
1342
95e2869a
MC		 1343static int tg3_bmcr_reset(struct tg3 *tp)
1344{
1345 u32 phy_control;
1346 int limit, err;
1347
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1350 */
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1353 if (err != 0)
1354 return -EBUSY;
1355
1356 limit = 5000;
1357 while (limit--) {
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1359 if (err != 0)
1360 return -EBUSY;
1361
1362 if ((phy_control & BMCR_RESET) == 0) {
1363 udelay(40);
1364 break;
1365 }
1366 udelay(10);
1367 }
d4675b52 1368 if (limit < 0)
95e2869a
MC		 1369 return -EBUSY;
1370
1371 return 0;
1372}
1373
158d7abd
MC		 1374static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1375{
3d16543d 1376 struct tg3 *tp = bp->priv;
158d7abd
MC		 1377 u32 val;
1378
24bb4fb6 1379 spin_lock_bh(&tp->lock);
158d7abd 1380
ead2402c 1381 if (__tg3_readphy(tp, mii_id, reg, &val))
24bb4fb6
MC		 1382 val = -EIO;
1383
1384 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1385
1386 return val;
1387}
1388
1389static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1390{
3d16543d 1391 struct tg3 *tp = bp->priv;
24bb4fb6 1392 u32 ret = 0;
158d7abd 1393
24bb4fb6 1394 spin_lock_bh(&tp->lock);
158d7abd 1395
ead2402c 1396 if (__tg3_writephy(tp, mii_id, reg, val))
24bb4fb6 1397 ret = -EIO;
158d7abd 1398
24bb4fb6
MC		 1399 spin_unlock_bh(&tp->lock);
1400
1401 return ret;
158d7abd
MC		 1402}
1403
1404static int tg3_mdio_reset(struct mii_bus *bp)
1405{
1406 return 0;
1407}
1408
9c61d6bc 1409static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1410{
1411 u32 val;
fcb389df 1412 struct phy_device *phydev;
a9daf367 1413
ead2402c 1414 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
fcb389df 1415 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1416 case PHY_ID_BCM50610:
1417 case PHY_ID_BCM50610M:
fcb389df
MC		 1418 val = MAC_PHYCFG2_50610_LED_MODES;
1419 break;
6a443a0f 1420 case PHY_ID_BCMAC131:
fcb389df
MC		 1421 val = MAC_PHYCFG2_AC131_LED_MODES;
1422 break;
6a443a0f 1423 case PHY_ID_RTL8211C:
fcb389df
MC		 1424 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1425 break;
6a443a0f 1426 case PHY_ID_RTL8201E:
fcb389df
MC		 1427 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1428 break;
1429 default:
a9daf367 1430 return;
fcb389df
MC		 1431 }
1432
1433 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1434 tw32(MAC_PHYCFG2, val);
1435
1436 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1437 val &= ~(MAC_PHYCFG1_RGMII_INT |
1438 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1439 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1440 tw32(MAC_PHYCFG1, val);
1441
1442 return;
1443 }
1444
63c3a66f 1445 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1446 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1447 MAC_PHYCFG2_FMODE_MASK_MASK |
1448 MAC_PHYCFG2_GMODE_MASK_MASK |
1449 MAC_PHYCFG2_ACT_MASK_MASK |
1450 MAC_PHYCFG2_QUAL_MASK_MASK |
1451 MAC_PHYCFG2_INBAND_ENABLE;
1452
1453 tw32(MAC_PHYCFG2, val);
a9daf367 1454
bb85fbb6
MC		 1455 val = tr32(MAC_PHYCFG1);
1456 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1457 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1458 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1459 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1460 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1461 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1462 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1463 }
bb85fbb6
MC		 1464 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1465 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1466 tw32(MAC_PHYCFG1, val);
a9daf367 1467
a9daf367
MC		 1468 val = tr32(MAC_EXT_RGMII_MODE);
1469 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1470 MAC_RGMII_MODE_RX_QUALITY |
1471 MAC_RGMII_MODE_RX_ACTIVITY |
1472 MAC_RGMII_MODE_RX_ENG_DET |
1473 MAC_RGMII_MODE_TX_ENABLE |
1474 MAC_RGMII_MODE_TX_LOWPWR |
1475 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1476 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1477 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1478 val |= MAC_RGMII_MODE_RX_INT_B |
1479 MAC_RGMII_MODE_RX_QUALITY |
1480 MAC_RGMII_MODE_RX_ACTIVITY |
1481 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1482 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1483 val |= MAC_RGMII_MODE_TX_ENABLE |
1484 MAC_RGMII_MODE_TX_LOWPWR |
1485 MAC_RGMII_MODE_TX_RESET;
1486 }
1487 tw32(MAC_EXT_RGMII_MODE, val);
1488}
1489
158d7abd
MC		 1490static void tg3_mdio_start(struct tg3 *tp)
1491{
158d7abd
MC		 1492 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1493 tw32_f(MAC_MI_MODE, tp->mi_mode);
1494 udelay(80);
a9daf367 1495
63c3a66f 1496 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1497 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1498 tg3_mdio_config_5785(tp);
1499}
1500
1501static int tg3_mdio_init(struct tg3 *tp)
1502{
1503 int i;
1504 u32 reg;
1505 struct phy_device *phydev;
1506
63c3a66f 1507 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1508 u32 is_serdes;
882e9793 1509
69f11c99 1510 tp->phy_addr = tp->pci_fn + 1;
882e9793 1511
4153577a 1512 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1513 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1514 else
1515 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1516 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1517 if (is_serdes)
1518 tp->phy_addr += 7;
ee002b64
HM		 1519 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1520 int addr;
1521
1522 addr = ssb_gige_get_phyaddr(tp->pdev);
1523 if (addr < 0)
1524 return addr;
1525 tp->phy_addr = addr;
882e9793 1526 } else
3f0e3ad7 1527 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1528
158d7abd
MC		 1529 tg3_mdio_start(tp);
1530
63c3a66f 1531 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1532 return 0;
1533
298cf9be
LB		 1534 tp->mdio_bus = mdiobus_alloc();
1535 if (tp->mdio_bus == NULL)
1536 return -ENOMEM;
158d7abd 1537
298cf9be
LB		 1538 tp->mdio_bus->name = "tg3 mdio bus";
1539 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1540 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1541 tp->mdio_bus->priv = tp;
1542 tp->mdio_bus->parent = &tp->pdev->dev;
1543 tp->mdio_bus->read = &tg3_mdio_read;
1544 tp->mdio_bus->write = &tg3_mdio_write;
1545 tp->mdio_bus->reset = &tg3_mdio_reset;
ead2402c 1546 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
298cf9be 1547 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1548
1549 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1550 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1551
1552 /* The bus registration will look for all the PHYs on the mdio bus.
1553 * Unfortunately, it does not ensure the PHY is powered up before
1554 * accessing the PHY ID registers. A chip reset is the
1555 * quickest way to bring the device back to an operational state..
1556 */
1557 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1558 tg3_bmcr_reset(tp);
1559
298cf9be 1560 i = mdiobus_register(tp->mdio_bus);
a9daf367 1561 if (i) {
ab96b241 1562 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1563 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1564 return i;
1565 }
158d7abd 1566
ead2402c 1567 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
a9daf367 1568
9c61d6bc 1569 if (!phydev || !phydev->drv) {
ab96b241 1570 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1571 mdiobus_unregister(tp->mdio_bus);
1572 mdiobus_free(tp->mdio_bus);
1573 return -ENODEV;
1574 }
1575
1576 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1577 case PHY_ID_BCM57780:
321d32a0 1578 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1579 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1580 break;
6a443a0f
MC		 1581 case PHY_ID_BCM50610:
1582 case PHY_ID_BCM50610M:
32e5a8d6 1583 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1584 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1585 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1586 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1587 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1588 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1589 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1590 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1591 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1592 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1593 /* fallthru */
6a443a0f 1594 case PHY_ID_RTL8211C:
fcb389df 1595 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1596 break;
6a443a0f
MC		 1597 case PHY_ID_RTL8201E:
1598 case PHY_ID_BCMAC131:
a9daf367 1599 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1600 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1601 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1602 break;
1603 }
1604
63c3a66f 1605 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1606
4153577a 1607 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1608 tg3_mdio_config_5785(tp);
a9daf367
MC		 1609
1610 return 0;
158d7abd
MC		 1611}
1612
1613static void tg3_mdio_fini(struct tg3 *tp)
1614{
63c3a66f
JP		 1615 if (tg3_flag(tp, MDIOBUS_INITED)) {
1616 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1617 mdiobus_unregister(tp->mdio_bus);
1618 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1619 }
1620}
1621
4ba526ce
MC		 1622/* tp->lock is held. */
1623static inline void tg3_generate_fw_event(struct tg3 *tp)
1624{
1625 u32 val;
1626
1627 val = tr32(GRC_RX_CPU_EVENT);
1628 val |= GRC_RX_CPU_DRIVER_EVENT;
1629 tw32_f(GRC_RX_CPU_EVENT, val);
1630
1631 tp->last_event_jiffies = jiffies;
1632}
1633
1634#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1635
95e2869a
MC		 1636/* tp->lock is held. */
1637static void tg3_wait_for_event_ack(struct tg3 *tp)
1638{
1639 int i;
4ba526ce
MC		 1640 unsigned int delay_cnt;
1641 long time_remain;
1642
1643 /* If enough time has passed, no wait is necessary. */
1644 time_remain = (long)(tp->last_event_jiffies + 1 +
1645 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1646 (long)jiffies;
1647 if (time_remain < 0)
1648 return;
1649
1650 /* Check if we can shorten the wait time. */
1651 delay_cnt = jiffies_to_usecs(time_remain);
1652 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1653 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1654 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1655
4ba526ce 1656 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1657 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1658 break;
6d446ec3
GS		 1659 if (pci_channel_offline(tp->pdev))
1660 break;
1661
4ba526ce 1662 udelay(8);
95e2869a
MC		 1663 }
1664}
1665
1666/* tp->lock is held. */
b28f389d 1667static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1668{
b28f389d 1669 u32 reg, val;
95e2869a
MC		 1670
1671 val = 0;
1672 if (!tg3_readphy(tp, MII_BMCR, &reg))
1673 val = reg << 16;
1674 if (!tg3_readphy(tp, MII_BMSR, &reg))
1675 val |= (reg & 0xffff);
b28f389d 1676 *data++ = val;
95e2869a
MC		 1677
1678 val = 0;
1679 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1680 val = reg << 16;
1681 if (!tg3_readphy(tp, MII_LPA, &reg))
1682 val |= (reg & 0xffff);
b28f389d 1683 *data++ = val;
95e2869a
MC		 1684
1685 val = 0;
f07e9af3 1686 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1687 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1688 val = reg << 16;
1689 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1690 val |= (reg & 0xffff);
1691 }
b28f389d 1692 *data++ = val;
95e2869a
MC		 1693
1694 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1695 val = reg << 16;
1696 else
1697 val = 0;
b28f389d
MC		 1698 *data++ = val;
1699}
1700
1701/* tp->lock is held. */
1702static void tg3_ump_link_report(struct tg3 *tp)
1703{
1704 u32 data[4];
1705
1706 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1707 return;
1708
1709 tg3_phy_gather_ump_data(tp, data);
1710
1711 tg3_wait_for_event_ack(tp);
1712
1713 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1714 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1716 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1717 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1718 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1719
4ba526ce 1720 tg3_generate_fw_event(tp);
95e2869a
MC		 1721}
1722
8d5a89b3
MC		 1723/* tp->lock is held. */
1724static void tg3_stop_fw(struct tg3 *tp)
1725{
1726 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1727 /* Wait for RX cpu to ACK the previous event. */
1728 tg3_wait_for_event_ack(tp);
1729
1730 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1731
1732 tg3_generate_fw_event(tp);
1733
1734 /* Wait for RX cpu to ACK this event. */
1735 tg3_wait_for_event_ack(tp);
1736 }
1737}
1738
fd6d3f0e
MC		 1739/* tp->lock is held. */
1740static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1741{
1742 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1743 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1744
1745 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1746 switch (kind) {
1747 case RESET_KIND_INIT:
1748 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1749 DRV_STATE_START);
1750 break;
1751
1752 case RESET_KIND_SHUTDOWN:
1753 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1754 DRV_STATE_UNLOAD);
1755 break;
1756
1757 case RESET_KIND_SUSPEND:
1758 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1759 DRV_STATE_SUSPEND);
1760 break;
1761
1762 default:
1763 break;
1764 }
1765 }
fd6d3f0e
MC		 1766}
1767
1768/* tp->lock is held. */
1769static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1770{
1771 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1772 switch (kind) {
1773 case RESET_KIND_INIT:
1774 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1775 DRV_STATE_START_DONE);
1776 break;
1777
1778 case RESET_KIND_SHUTDOWN:
1779 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1780 DRV_STATE_UNLOAD_DONE);
1781 break;
1782
1783 default:
1784 break;
1785 }
1786 }
fd6d3f0e
MC		 1787}
1788
1789/* tp->lock is held. */
1790static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1791{
1792 if (tg3_flag(tp, ENABLE_ASF)) {
1793 switch (kind) {
1794 case RESET_KIND_INIT:
1795 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1796 DRV_STATE_START);
1797 break;
1798
1799 case RESET_KIND_SHUTDOWN:
1800 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1801 DRV_STATE_UNLOAD);
1802 break;
1803
1804 case RESET_KIND_SUSPEND:
1805 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1806 DRV_STATE_SUSPEND);
1807 break;
1808
1809 default:
1810 break;
1811 }
1812 }
1813}
1814
1815static int tg3_poll_fw(struct tg3 *tp)
1816{
1817 int i;
1818 u32 val;
1819
df465abf
NS		 1820 if (tg3_flag(tp, NO_FWARE_REPORTED))
1821 return 0;
1822
7e6c63f0
HM		 1823 if (tg3_flag(tp, IS_SSB_CORE)) {
1824 /* We don't use firmware. */
1825 return 0;
1826 }
1827
4153577a 1828 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1829 /* Wait up to 20ms for init done. */
1830 for (i = 0; i < 200; i++) {
1831 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1832 return 0;
6d446ec3
GS		 1833 if (pci_channel_offline(tp->pdev))
1834 return -ENODEV;
1835
fd6d3f0e
MC		 1836 udelay(100);
1837 }
1838 return -ENODEV;
1839 }
1840
1841 /* Wait for firmware initialization to complete. */
1842 for (i = 0; i < 100000; i++) {
1843 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1844 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1845 break;
6d446ec3
GS		 1846 if (pci_channel_offline(tp->pdev)) {
1847 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1848 tg3_flag_set(tp, NO_FWARE_REPORTED);
1849 netdev_info(tp->dev, "No firmware running\n");
1850 }
1851
1852 break;
1853 }
1854
fd6d3f0e
MC		 1855 udelay(10);
1856 }
1857
1858 /* Chip might not be fitted with firmware. Some Sun onboard
1859 * parts are configured like that. So don't signal the timeout
1860 * of the above loop as an error, but do report the lack of
1861 * running firmware once.
1862 */
1863 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1864 tg3_flag_set(tp, NO_FWARE_REPORTED);
1865
1866 netdev_info(tp->dev, "No firmware running\n");
1867 }
1868
4153577a 1869 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1870 /* The 57765 A0 needs a little more
1871 * time to do some important work.
1872 */
1873 mdelay(10);
1874 }
1875
1876 return 0;
1877}
1878
95e2869a
MC		 1879static void tg3_link_report(struct tg3 *tp)
1880{
1881 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1882 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1883 tg3_ump_link_report(tp);
1884 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1885 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1886 (tp->link_config.active_speed == SPEED_1000 ?
1887 1000 :
1888 (tp->link_config.active_speed == SPEED_100 ?
1889 100 : 10)),
1890 (tp->link_config.active_duplex == DUPLEX_FULL ?
1891 "full" : "half"));
1892
1893 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1894 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1895 "on" : "off",
1896 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1897 "on" : "off");
47007831
MC		 1898
1899 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1900 netdev_info(tp->dev, "EEE is %s\n",
1901 tp->setlpicnt ? "enabled" : "disabled");
1902
95e2869a
MC		 1903 tg3_ump_link_report(tp);
1904 }
84421b99
NS		 1905
1906 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1907}
1908
fdad8de4
NS		 1909static u32 tg3_decode_flowctrl_1000T(u32 adv)
1910{
1911 u32 flowctrl = 0;
1912
1913 if (adv & ADVERTISE_PAUSE_CAP) {
1914 flowctrl |= FLOW_CTRL_RX;
1915 if (!(adv & ADVERTISE_PAUSE_ASYM))
1916 flowctrl |= FLOW_CTRL_TX;
1917 } else if (adv & ADVERTISE_PAUSE_ASYM)
1918 flowctrl |= FLOW_CTRL_TX;
1919
1920 return flowctrl;
1921}
1922
95e2869a
MC		 1923static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1924{
1925 u16 miireg;
1926
e18ce346 1927 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1928 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1929 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1930 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1931 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1932 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1933 else
1934 miireg = 0;
1935
1936 return miireg;
1937}
1938
fdad8de4
NS		 1939static u32 tg3_decode_flowctrl_1000X(u32 adv)
1940{
1941 u32 flowctrl = 0;
1942
1943 if (adv & ADVERTISE_1000XPAUSE) {
1944 flowctrl |= FLOW_CTRL_RX;
1945 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1946 flowctrl |= FLOW_CTRL_TX;
1947 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1948 flowctrl |= FLOW_CTRL_TX;
1949
1950 return flowctrl;
1951}
1952
95e2869a
MC		 1953static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1954{
1955 u8 cap = 0;
1956
f3791cdf
MC		 1957 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1958 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1959 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1960 if (lcladv & ADVERTISE_1000XPAUSE)
1961 cap = FLOW_CTRL_RX;
1962 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1963 cap = FLOW_CTRL_TX;
95e2869a
MC		 1964 }
1965
1966 return cap;
1967}
1968
f51f3562 1969static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1970{
b02fd9e3 1971 u8 autoneg;
f51f3562 1972 u8 flowctrl = 0;
95e2869a
MC		 1973 u32 old_rx_mode = tp->rx_mode;
1974 u32 old_tx_mode = tp->tx_mode;
1975
63c3a66f 1976 if (tg3_flag(tp, USE_PHYLIB))
ead2402c 1977 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
b02fd9e3
MC		 1978 else
1979 autoneg = tp->link_config.autoneg;
1980
63c3a66f 1981 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1982 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1983 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1984 else
bc02ff95 1985 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1986 } else
1987 flowctrl = tp->link_config.flowctrl;
95e2869a 1988
f51f3562 1989 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1990
e18ce346 1991 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1992 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1993 else
1994 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1995
f51f3562 1996 if (old_rx_mode != tp->rx_mode)
95e2869a 1997 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1998
e18ce346 1999 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 2000 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
2001 else
2002 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
2003
f51f3562 2004 if (old_tx_mode != tp->tx_mode)
95e2869a 2005 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 2006}
2007
b02fd9e3
MC		 2008static void tg3_adjust_link(struct net_device *dev)
2009{
2010 u8 oldflowctrl, linkmesg = 0;
2011 u32 mac_mode, lcl_adv, rmt_adv;
2012 struct tg3 *tp = netdev_priv(dev);
ead2402c 2013 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2014
24bb4fb6 2015 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 2016
2017 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2018 MAC_MODE_HALF_DUPLEX);
2019
2020 oldflowctrl = tp->link_config.active_flowctrl;
2021
2022 if (phydev->link) {
2023 lcl_adv = 0;
2024 rmt_adv = 0;
2025
2026 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2027 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2028 else if (phydev->speed == SPEED_1000 ||
4153577a 2029 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2030 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2031 else
2032 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2033
2034 if (phydev->duplex == DUPLEX_HALF)
2035 mac_mode |= MAC_MODE_HALF_DUPLEX;
2036 else {
f88788f0 2037 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2038 tp->link_config.flowctrl);
2039
2040 if (phydev->pause)
2041 rmt_adv = LPA_PAUSE_CAP;
2042 if (phydev->asym_pause)
2043 rmt_adv |= LPA_PAUSE_ASYM;
2044 }
2045
2046 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2047 } else
2048 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2049
2050 if (mac_mode != tp->mac_mode) {
2051 tp->mac_mode = mac_mode;
2052 tw32_f(MAC_MODE, tp->mac_mode);
2053 udelay(40);
2054 }
2055
4153577a 2056 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2057 if (phydev->speed == SPEED_10)
2058 tw32(MAC_MI_STAT,
2059 MAC_MI_STAT_10MBPS_MODE |
2060 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2061 else
2062 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2063 }
2064
b02fd9e3
MC		 2065 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2066 tw32(MAC_TX_LENGTHS,
2067 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2068 (6 << TX_LENGTHS_IPG_SHIFT) |
2069 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2070 else
2071 tw32(MAC_TX_LENGTHS,
2072 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2073 (6 << TX_LENGTHS_IPG_SHIFT) |
2074 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2075
34655ad6 2076 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2077 phydev->speed != tp->link_config.active_speed ||
2078 phydev->duplex != tp->link_config.active_duplex ||
2079 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2080 linkmesg = 1;
b02fd9e3 2081
34655ad6 2082 tp->old_link = phydev->link;
b02fd9e3
MC		 2083 tp->link_config.active_speed = phydev->speed;
2084 tp->link_config.active_duplex = phydev->duplex;
2085
24bb4fb6 2086 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2087
2088 if (linkmesg)
2089 tg3_link_report(tp);
2090}
2091
2092static int tg3_phy_init(struct tg3 *tp)
2093{
2094 struct phy_device *phydev;
2095
f07e9af3 2096 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2097 return 0;
2098
2099 /* Bring the PHY back to a known state. */
2100 tg3_bmcr_reset(tp);
2101
ead2402c 2102 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3
MC		 2103
2104 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2105 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2106 tg3_adjust_link, phydev->interface);
b02fd9e3 2107 if (IS_ERR(phydev)) {
ab96b241 2108 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2109 return PTR_ERR(phydev);
2110 }
2111
b02fd9e3 2112 /* Mask with MAC supported features. */
9c61d6bc
MC		 2113 switch (phydev->interface) {
2114 case PHY_INTERFACE_MODE_GMII:
2115 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2116 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2117 phydev->supported &= (PHY_GBIT_FEATURES |
2118 SUPPORTED_Pause |
2119 SUPPORTED_Asym_Pause);
2120 break;
2121 }
2122 /* fallthru */
9c61d6bc
MC		 2123 case PHY_INTERFACE_MODE_MII:
2124 phydev->supported &= (PHY_BASIC_FEATURES |
2125 SUPPORTED_Pause |
2126 SUPPORTED_Asym_Pause);
2127 break;
2128 default:
ead2402c 2129 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
9c61d6bc
MC		 2130 return -EINVAL;
2131 }
2132
f07e9af3 2133 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2134
2135 phydev->advertising = phydev->supported;
2136
b02fd9e3
MC		 2137 return 0;
2138}
2139
2140static void tg3_phy_start(struct tg3 *tp)
2141{
2142 struct phy_device *phydev;
2143
f07e9af3 2144 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2145 return;
2146
ead2402c 2147 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2148
80096068
MC		 2149 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2150 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2151 phydev->speed = tp->link_config.speed;
2152 phydev->duplex = tp->link_config.duplex;
2153 phydev->autoneg = tp->link_config.autoneg;
2154 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2155 }
2156
2157 phy_start(phydev);
2158
2159 phy_start_aneg(phydev);
2160}
2161
2162static void tg3_phy_stop(struct tg3 *tp)
2163{
f07e9af3 2164 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2165 return;
2166
ead2402c 2167 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 2168}
2169
2170static void tg3_phy_fini(struct tg3 *tp)
2171{
f07e9af3 2172 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
ead2402c 2173 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
f07e9af3 2174 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2175 }
2176}
2177
941ec90f
MC		 2178static int tg3_phy_set_extloopbk(struct tg3 *tp)
2179{
2180 int err;
2181 u32 val;
2182
2183 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2184 return 0;
2185
2186 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2187 /* Cannot do read-modify-write on 5401 */
2188 err = tg3_phy_auxctl_write(tp,
2189 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2190 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2191 0x4c20);
2192 goto done;
2193 }
2194
2195 err = tg3_phy_auxctl_read(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2197 if (err)
2198 return err;
2199
2200 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2201 err = tg3_phy_auxctl_write(tp,
2202 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2203
2204done:
2205 return err;
2206}
2207
7f97a4bd
MC		 2208static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2209{
2210 u32 phytest;
2211
2212 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2213 u32 phy;
2214
2215 tg3_writephy(tp, MII_TG3_FET_TEST,
2216 phytest | MII_TG3_FET_SHADOW_EN);
2217 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2218 if (enable)
2219 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2220 else
2221 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2222 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2223 }
2224 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2225 }
2226}
2227
6833c043
MC		 2228static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2229{
2230 u32 reg;
2231
63c3a66f
JP		 2232 if (!tg3_flag(tp, 5705_PLUS) ||
2233 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2234 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2235 return;
2236
f07e9af3 2237 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2238 tg3_phy_fet_toggle_apd(tp, enable);
2239 return;
2240 }
2241
3ab71071 2242 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
6833c043
MC		 2243 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2244 MII_TG3_MISC_SHDW_SCR5_SDTL |
2245 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2246 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2247 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2248
3ab71071 2249 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
6833c043
MC		 2250
2251
3ab71071 2252 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
6833c043
MC		 2253 if (enable)
2254 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2255
3ab71071 2256 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
6833c043
MC		 2257}
2258
953c96e0 2259static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2260{
2261 u32 phy;
2262
63c3a66f 2263 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2264 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2265 return;
2266
f07e9af3 2267 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2268 u32 ephy;
2269
535ef6e1
MC		 2270 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2271 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2272
2273 tg3_writephy(tp, MII_TG3_FET_TEST,
2274 ephy | MII_TG3_FET_SHADOW_EN);
2275 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2276 if (enable)
535ef6e1 2277 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2278 else
535ef6e1
MC		 2279 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2280 tg3_writephy(tp, reg, phy);
9ef8ca99 2281 }
535ef6e1 2282 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2283 }
2284 } else {
15ee95c3
MC		 2285 int ret;
2286
2287 ret = tg3_phy_auxctl_read(tp,
2288 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2289 if (!ret) {
9ef8ca99
MC		 2290 if (enable)
2291 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2292 else
2293 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2294 tg3_phy_auxctl_write(tp,
2295 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2296 }
2297 }
2298}
2299
1da177e4
LT		 2300static void tg3_phy_set_wirespeed(struct tg3 *tp)
2301{
15ee95c3 2302 int ret;
1da177e4
LT		 2303 u32 val;
2304
f07e9af3 2305 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2306 return;
2307
15ee95c3
MC		 2308 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2309 if (!ret)
b4bd2929
MC		 2310 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2311 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2312}
2313
b2a5c19c
MC		 2314static void tg3_phy_apply_otp(struct tg3 *tp)
2315{
2316 u32 otp, phy;
2317
2318 if (!tp->phy_otp)
2319 return;
2320
2321 otp = tp->phy_otp;
2322
daf3ec68 2323 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2324 return;
b2a5c19c
MC		 2325
2326 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2327 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2328 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2329
2330 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2331 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2332 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2333
2334 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2335 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2336 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2337
2338 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2339 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2340
2341 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2342 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2343
2344 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2345 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2346 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2347
daf3ec68 2348 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2349}
2350
400dfbaa
NS		 2351static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2352{
2353 u32 val;
2354 struct ethtool_eee *dest = &tp->eee;
2355
2356 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2357 return;
2358
2359 if (eee)
2360 dest = eee;
2361
2362 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2363 return;
2364
2365 /* Pull eee_active */
2366 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2367 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2368 dest->eee_active = 1;
2369 } else
2370 dest->eee_active = 0;
2371
2372 /* Pull lp advertised settings */
2373 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2374 return;
2375 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2376
2377 /* Pull advertised and eee_enabled settings */
2378 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2379 return;
2380 dest->eee_enabled = !!val;
2381 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2382
2383 /* Pull tx_lpi_enabled */
2384 val = tr32(TG3_CPMU_EEE_MODE);
2385 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2386
2387 /* Pull lpi timer value */
2388 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2389}
2390
953c96e0 2391static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2392{
2393 u32 val;
2394
2395 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2396 return;
2397
2398 tp->setlpicnt = 0;
2399
2400 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2401 current_link_up &&
a6b68dab
MC		 2402 tp->link_config.active_duplex == DUPLEX_FULL &&
2403 (tp->link_config.active_speed == SPEED_100 ||
2404 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2405 u32 eeectl;
2406
2407 if (tp->link_config.active_speed == SPEED_1000)
2408 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2409 else
2410 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2411
2412 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2413
400dfbaa
NS		 2414 tg3_eee_pull_config(tp, NULL);
2415 if (tp->eee.eee_active)
52b02d04
MC		 2416 tp->setlpicnt = 2;
2417 }
2418
2419 if (!tp->setlpicnt) {
953c96e0 2420 if (current_link_up &&
daf3ec68 2421 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2422 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2423 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2424 }
2425
52b02d04
MC		 2426 val = tr32(TG3_CPMU_EEE_MODE);
2427 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2428 }
2429}
2430
b0c5943f
MC		 2431static void tg3_phy_eee_enable(struct tg3 *tp)
2432{
2433 u32 val;
2434
2435 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2436 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2437 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2438 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2439 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2440 val = MII_TG3_DSP_TAP26_ALNOKO |
2441 MII_TG3_DSP_TAP26_RMRXSTO;
2442 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2443 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2444 }
2445
2446 val = tr32(TG3_CPMU_EEE_MODE);
2447 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2448}
2449
1da177e4
LT		 2450static int tg3_wait_macro_done(struct tg3 *tp)
2451{
2452 int limit = 100;
2453
2454 while (limit--) {
2455 u32 tmp32;
2456
f08aa1a8 2457 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2458 if ((tmp32 & 0x1000) == 0)
2459 break;
2460 }
2461 }
d4675b52 2462 if (limit < 0)
1da177e4
LT		 2463 return -EBUSY;
2464
2465 return 0;
2466}
2467
2468static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2469{
2470 static const u32 test_pat[4][6] = {
2471 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2472 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2473 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2474 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2475 };
2476 int chan;
2477
2478 for (chan = 0; chan < 4; chan++) {
2479 int i;
2480
2481 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2482 (chan * 0x2000) | 0x0200);
f08aa1a8 2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2484
2485 for (i = 0; i < 6; i++)
2486 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2487 test_pat[chan][i]);
2488
f08aa1a8 2489 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2490 if (tg3_wait_macro_done(tp)) {
2491 *resetp = 1;
2492 return -EBUSY;
2493 }
2494
2495 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2496 (chan * 0x2000) | 0x0200);
f08aa1a8 2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2498 if (tg3_wait_macro_done(tp)) {
2499 *resetp = 1;
2500 return -EBUSY;
2501 }
2502
f08aa1a8 2503 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2504 if (tg3_wait_macro_done(tp)) {
2505 *resetp = 1;
2506 return -EBUSY;
2507 }
2508
2509 for (i = 0; i < 6; i += 2) {
2510 u32 low, high;
2511
2512 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2513 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2514 tg3_wait_macro_done(tp)) {
2515 *resetp = 1;
2516 return -EBUSY;
2517 }
2518 low &= 0x7fff;
2519 high &= 0x000f;
2520 if (low != test_pat[chan][i] ||
2521 high != test_pat[chan][i+1]) {
2522 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2523 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2524 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2525
2526 return -EBUSY;
2527 }
2528 }
2529 }
2530
2531 return 0;
2532}
2533
2534static int tg3_phy_reset_chanpat(struct tg3 *tp)
2535{
2536 int chan;
2537
2538 for (chan = 0; chan < 4; chan++) {
2539 int i;
2540
2541 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2542 (chan * 0x2000) | 0x0200);
f08aa1a8 2543 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2544 for (i = 0; i < 6; i++)
2545 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2546 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2547 if (tg3_wait_macro_done(tp))
2548 return -EBUSY;
2549 }
2550
2551 return 0;
2552}
2553
2554static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2555{
2556 u32 reg32, phy9_orig;
2557 int retries, do_phy_reset, err;
2558
2559 retries = 10;
2560 do_phy_reset = 1;
2561 do {
2562 if (do_phy_reset) {
2563 err = tg3_bmcr_reset(tp);
2564 if (err)
2565 return err;
2566 do_phy_reset = 0;
2567 }
2568
2569 /* Disable transmitter and interrupt. */
2570 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2571 continue;
2572
2573 reg32 |= 0x3000;
2574 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2575
2576 /* Set full-duplex, 1000 mbps. */
2577 tg3_writephy(tp, MII_BMCR,
221c5637 2578 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2579
2580 /* Set to master mode. */
221c5637 2581 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2582 continue;
2583
221c5637
MC		 2584 tg3_writephy(tp, MII_CTRL1000,
2585 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2586
daf3ec68 2587 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2588 if (err)
2589 return err;
1da177e4
LT		 2590
2591 /* Block the PHY control access. */
6ee7c0a0 2592 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2593
2594 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2595 if (!err)
2596 break;
2597 } while (--retries);
2598
2599 err = tg3_phy_reset_chanpat(tp);
2600 if (err)
2601 return err;
2602
6ee7c0a0 2603 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2604
2605 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2606 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2607
daf3ec68 2608 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2609
221c5637 2610 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4 2611
c6e27f2f
DC		 2612 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
2613 if (err)
2614 return err;
1da177e4 2615
c6e27f2f
DC		 2616 reg32 &= ~0x3000;
2617 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2618
2619 return 0;
1da177e4
LT		 2620}
2621
f4a46d1f
NNS		 2622static void tg3_carrier_off(struct tg3 *tp)
2623{
2624 netif_carrier_off(tp->dev);
2625 tp->link_up = false;
2626}
2627
ce20f161
NS		 2628static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2629{
2630 if (tg3_flag(tp, ENABLE_ASF))
2631 netdev_warn(tp->dev,
2632 "Management side-band traffic will be interrupted during phy settings change\n");
2633}
2634
1da177e4
LT		 2635/* This will reset the tigon3 PHY if there is no valid
2636 * link unless the FORCE argument is non-zero.
2637 */
2638static int tg3_phy_reset(struct tg3 *tp)
2639{
f833c4c1 2640 u32 val, cpmuctrl;
1da177e4
LT		 2641 int err;
2642
4153577a 2643 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2644 val = tr32(GRC_MISC_CFG);
2645 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2646 udelay(40);
2647 }
f833c4c1
MC		 2648 err = tg3_readphy(tp, MII_BMSR, &val);
2649 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2650 if (err != 0)
2651 return -EBUSY;
2652
f4a46d1f 2653 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2654 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2655 tg3_link_report(tp);
2656 }
2657
4153577a
JP		 2658 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2659 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2660 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2661 err = tg3_phy_reset_5703_4_5(tp);
2662 if (err)
2663 return err;
2664 goto out;
2665 }
2666
b2a5c19c 2667 cpmuctrl = 0;
4153577a
JP		 2668 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2669 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2670 cpmuctrl = tr32(TG3_CPMU_CTRL);
2671 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2672 tw32(TG3_CPMU_CTRL,
2673 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2674 }
2675
1da177e4
LT		 2676 err = tg3_bmcr_reset(tp);
2677 if (err)
2678 return err;
2679
b2a5c19c 2680 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2681 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2683
2684 tw32(TG3_CPMU_CTRL, cpmuctrl);
2685 }
2686
4153577a
JP		 2687 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2688 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2689 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2690 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2691 CPMU_LSPD_1000MB_MACCLK_12_5) {
2692 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2693 udelay(40);
2694 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2695 }
2696 }
2697
63c3a66f 2698 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2699 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2700 return 0;
2701
b2a5c19c
MC		 2702 tg3_phy_apply_otp(tp);
2703
f07e9af3 2704 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2705 tg3_phy_toggle_apd(tp, true);
2706 else
2707 tg3_phy_toggle_apd(tp, false);
2708
1da177e4 2709out:
1d36ba45 2710 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2711 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2712 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2713 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2714 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2715 }
1d36ba45 2716
f07e9af3 2717 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2718 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2719 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2720 }
1d36ba45 2721
f07e9af3 2722 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2723 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2724 tg3_phydsp_write(tp, 0x000a, 0x310b);
2725 tg3_phydsp_write(tp, 0x201f, 0x9506);
2726 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2727 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2728 }
f07e9af3 2729 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2730 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2731 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2732 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2734 tg3_writephy(tp, MII_TG3_TEST1,
2735 MII_TG3_TEST1_TRIM_EN | 0x4);
2736 } else
2737 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2738
daf3ec68 2739 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2740 }
c424cb24 2741 }
1d36ba45 2742
1da177e4
LT		 2743 /* Set Extended packet length bit (bit 14) on all chips that */
2744 /* support jumbo frames */
79eb6904 2745 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2746 /* Cannot do read-modify-write on 5401 */
b4bd2929 2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2748 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2749 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2750 err = tg3_phy_auxctl_read(tp,
2751 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2752 if (!err)
b4bd2929
MC		 2753 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2754 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2755 }
2756
2757 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2758 * jumbo frames transmission.
2759 */
63c3a66f 2760 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2761 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2762 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2763 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2764 }
2765
4153577a 2766 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2767 /* adjust output voltage */
535ef6e1 2768 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2769 }
2770
4153577a 2771 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2772 tg3_phydsp_write(tp, 0xffb, 0x4000);
2773
953c96e0 2774 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2775 tg3_phy_set_wirespeed(tp);
2776 return 0;
2777}
2778
3a1e19d3
MC		 2779#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2780#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2781#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2782 TG3_GPIO_MSG_NEED_VAUX)
2783#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2784 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2785 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2786 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2787 (TG3_GPIO_MSG_DRVR_PRES << 12))
2788
2789#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2790 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2791 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2792 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2793 (TG3_GPIO_MSG_NEED_VAUX << 12))
2794
2795static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2796{
2797 u32 status, shift;
2798
4153577a
JP		 2799 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2800 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2801 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2802 else
2803 status = tr32(TG3_CPMU_DRV_STATUS);
2804
2805 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2806 status &= ~(TG3_GPIO_MSG_MASK << shift);
2807 status |= (newstat << shift);
2808
4153577a
JP		 2809 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2810 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2811 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2812 else
2813 tw32(TG3_CPMU_DRV_STATUS, status);
2814
2815 return status >> TG3_APE_GPIO_MSG_SHIFT;
2816}
2817
520b2756
MC		 2818static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2819{
2820 if (!tg3_flag(tp, IS_NIC))
2821 return 0;
2822
4153577a
JP		 2823 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2824 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2825 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2826 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2827 return -EIO;
520b2756 2828
3a1e19d3
MC		 2829 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2830
2831 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2832 TG3_GRC_LCLCTL_PWRSW_DELAY);
2833
2834 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2835 } else {
2836 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2837 TG3_GRC_LCLCTL_PWRSW_DELAY);
2838 }
6f5c8f83 2839
520b2756
MC		 2840 return 0;
2841}
2842
2843static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2844{
2845 u32 grc_local_ctrl;
2846
2847 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2848 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2849 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2850 return;
2851
2852 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2853
2854 tw32_wait_f(GRC_LOCAL_CTRL,
2855 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2856 TG3_GRC_LCLCTL_PWRSW_DELAY);
2857
2858 tw32_wait_f(GRC_LOCAL_CTRL,
2859 grc_local_ctrl,
2860 TG3_GRC_LCLCTL_PWRSW_DELAY);
2861
2862 tw32_wait_f(GRC_LOCAL_CTRL,
2863 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2864 TG3_GRC_LCLCTL_PWRSW_DELAY);
2865}
2866
2867static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2868{
2869 if (!tg3_flag(tp, IS_NIC))
2870 return;
2871
4153577a
JP		 2872 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2873 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2874 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2875 (GRC_LCLCTRL_GPIO_OE0 |
2876 GRC_LCLCTRL_GPIO_OE1 |
2877 GRC_LCLCTRL_GPIO_OE2 |
2878 GRC_LCLCTRL_GPIO_OUTPUT0 |
2879 GRC_LCLCTRL_GPIO_OUTPUT1),
2880 TG3_GRC_LCLCTL_PWRSW_DELAY);
2881 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2882 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2883 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2884 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2885 GRC_LCLCTRL_GPIO_OE1 |
2886 GRC_LCLCTRL_GPIO_OE2 |
2887 GRC_LCLCTRL_GPIO_OUTPUT0 |
2888 GRC_LCLCTRL_GPIO_OUTPUT1 |
2889 tp->grc_local_ctrl;
2890 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2891 TG3_GRC_LCLCTL_PWRSW_DELAY);
2892
2893 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2894 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2895 TG3_GRC_LCLCTL_PWRSW_DELAY);
2896
2897 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2898 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2899 TG3_GRC_LCLCTL_PWRSW_DELAY);
2900 } else {
2901 u32 no_gpio2;
2902 u32 grc_local_ctrl = 0;
2903
2904 /* Workaround to prevent overdrawing Amps. */
4153577a 2905 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2906 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2907 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2908 grc_local_ctrl,
2909 TG3_GRC_LCLCTL_PWRSW_DELAY);
2910 }
2911
2912 /* On 5753 and variants, GPIO2 cannot be used. */
2913 no_gpio2 = tp->nic_sram_data_cfg &
2914 NIC_SRAM_DATA_CFG_NO_GPIO2;
2915
2916 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2917 GRC_LCLCTRL_GPIO_OE1 |
2918 GRC_LCLCTRL_GPIO_OE2 |
2919 GRC_LCLCTRL_GPIO_OUTPUT1 |
2920 GRC_LCLCTRL_GPIO_OUTPUT2;
2921 if (no_gpio2) {
2922 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2923 GRC_LCLCTRL_GPIO_OUTPUT2);
2924 }
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2928
2929 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2930
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2934
2935 if (!no_gpio2) {
2936 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2937 tw32_wait_f(GRC_LOCAL_CTRL,
2938 tp->grc_local_ctrl | grc_local_ctrl,
2939 TG3_GRC_LCLCTL_PWRSW_DELAY);
2940 }
2941 }
3a1e19d3
MC		 2942}
2943
cd0d7228 2944static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2945{
2946 u32 msg = 0;
2947
2948 /* Serialize power state transitions */
2949 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2950 return;
2951
cd0d7228 2952 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2953 msg = TG3_GPIO_MSG_NEED_VAUX;
2954
2955 msg = tg3_set_function_status(tp, msg);
2956
2957 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2958 goto done;
6f5c8f83 2959
3a1e19d3
MC		 2960 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2961 tg3_pwrsrc_switch_to_vaux(tp);
2962 else
2963 tg3_pwrsrc_die_with_vmain(tp);
2964
2965done:
6f5c8f83 2966 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2967}
2968
cd0d7228 2969static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2970{
683644b7 2971 bool need_vaux = false;
1da177e4 2972
334355aa 2973 /* The GPIOs do something completely different on 57765. */
55086ad9 2974 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2975 return;
2976
4153577a
JP		 2977 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2978 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2979 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2980 tg3_frob_aux_power_5717(tp, include_wol ?
2981 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2982 return;
2983 }
2984
2985 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2986 struct net_device *dev_peer;
2987
2988 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2989
bc1c7567 2990 /* remove_one() may have been run on the peer. */
683644b7
MC		 2991 if (dev_peer) {
2992 struct tg3 *tp_peer = netdev_priv(dev_peer);
2993
63c3a66f 2994 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2995 return;
2996
cd0d7228 2997 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2998 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2999 need_vaux = true;
3000 }
1da177e4
LT		 3001 }
3002
cd0d7228
MC		 3003 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
3004 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 3005 need_vaux = true;
3006
520b2756
MC		 3007 if (need_vaux)
3008 tg3_pwrsrc_switch_to_vaux(tp);
3009 else
3010 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 3011}
3012
e8f3f6ca
MC		 3013static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3014{
3015 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3016 return 1;
79eb6904 3017 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3018 if (speed != SPEED_10)
3019 return 1;
3020 } else if (speed == SPEED_10)
3021 return 1;
3022
3023 return 0;
3024}
3025
44f3b503
NS		 3026static bool tg3_phy_power_bug(struct tg3 *tp)
3027{
3028 switch (tg3_asic_rev(tp)) {
3029 case ASIC_REV_5700:
3030 case ASIC_REV_5704:
3031 return true;
3032 case ASIC_REV_5780:
3033 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3034 return true;
3035 return false;
3036 case ASIC_REV_5717:
3037 if (!tp->pci_fn)
3038 return true;
3039 return false;
3040 case ASIC_REV_5719:
3041 case ASIC_REV_5720:
3042 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3043 !tp->pci_fn)
3044 return true;
3045 return false;
3046 }
3047
3048 return false;
3049}
3050
989038e2
NS		 3051static bool tg3_phy_led_bug(struct tg3 *tp)
3052{
3053 switch (tg3_asic_rev(tp)) {
3054 case ASIC_REV_5719:
300cf9b9 3055 case ASIC_REV_5720:
989038e2
NS		 3056 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3057 !tp->pci_fn)
3058 return true;
3059 return false;
3060 }
3061
3062 return false;
3063}
3064
0a459aac 3065static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3066{
ce057f01
MC		 3067 u32 val;
3068
942d1af0
NS		 3069 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3070 return;
3071
f07e9af3 3072 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3073 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3074 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3075 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3076
3077 sg_dig_ctrl |=
3078 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3079 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3080 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3081 }
3f7045c1 3082 return;
5129724a 3083 }
3f7045c1 3084
4153577a 3085 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3086 tg3_bmcr_reset(tp);
3087 val = tr32(GRC_MISC_CFG);
3088 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3089 udelay(40);
3090 return;
f07e9af3 3091 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3092 u32 phytest;
3093 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3094 u32 phy;
3095
3096 tg3_writephy(tp, MII_ADVERTISE, 0);
3097 tg3_writephy(tp, MII_BMCR,
3098 BMCR_ANENABLE | BMCR_ANRESTART);
3099
3100 tg3_writephy(tp, MII_TG3_FET_TEST,
3101 phytest | MII_TG3_FET_SHADOW_EN);
3102 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3103 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3104 tg3_writephy(tp,
3105 MII_TG3_FET_SHDW_AUXMODE4,
3106 phy);
3107 }
3108 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3109 }
3110 return;
0a459aac 3111 } else if (do_low_power) {
989038e2
NS		 3112 if (!tg3_phy_led_bug(tp))
3113 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3115
b4bd2929
MC		 3116 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3117 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3118 MII_TG3_AUXCTL_PCTL_VREG_11V;
3119 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3120 }
3f7045c1 3121
15c3b696
MC		 3122 /* The PHY should not be powered down on some chips because
3123 * of bugs.
3124 */
44f3b503 3125 if (tg3_phy_power_bug(tp))
15c3b696 3126 return;
ce057f01 3127
4153577a
JP		 3128 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3129 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3130 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3131 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3132 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3133 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3134 }
3135
15c3b696
MC		 3136 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3137}
3138
ffbcfed4
MC		 3139/* tp->lock is held. */
3140static int tg3_nvram_lock(struct tg3 *tp)
3141{
63c3a66f 3142 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3143 int i;
3144
3145 if (tp->nvram_lock_cnt == 0) {
3146 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3147 for (i = 0; i < 8000; i++) {
3148 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3149 break;
3150 udelay(20);
3151 }
3152 if (i == 8000) {
3153 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3154 return -ENODEV;
3155 }
3156 }
3157 tp->nvram_lock_cnt++;
3158 }
3159 return 0;
3160}
3161
3162/* tp->lock is held. */
3163static void tg3_nvram_unlock(struct tg3 *tp)
3164{
63c3a66f 3165 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3166 if (tp->nvram_lock_cnt > 0)
3167 tp->nvram_lock_cnt--;
3168 if (tp->nvram_lock_cnt == 0)
3169 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3170 }
3171}
3172
3173/* tp->lock is held. */
3174static void tg3_enable_nvram_access(struct tg3 *tp)
3175{
63c3a66f 3176 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3177 u32 nvaccess = tr32(NVRAM_ACCESS);
3178
3179 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3180 }
3181}
3182
3183/* tp->lock is held. */
3184static void tg3_disable_nvram_access(struct tg3 *tp)
3185{
63c3a66f 3186 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3187 u32 nvaccess = tr32(NVRAM_ACCESS);
3188
3189 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3190 }
3191}
3192
3193static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3194 u32 offset, u32 *val)
3195{
3196 u32 tmp;
3197 int i;
3198
3199 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3200 return -EINVAL;
3201
3202 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3203 EEPROM_ADDR_DEVID_MASK |
3204 EEPROM_ADDR_READ);
3205 tw32(GRC_EEPROM_ADDR,
3206 tmp |
3207 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3208 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3209 EEPROM_ADDR_ADDR_MASK) |
3210 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3211
3212 for (i = 0; i < 1000; i++) {
3213 tmp = tr32(GRC_EEPROM_ADDR);
3214
3215 if (tmp & EEPROM_ADDR_COMPLETE)
3216 break;
3217 msleep(1);
3218 }
3219 if (!(tmp & EEPROM_ADDR_COMPLETE))
3220 return -EBUSY;
3221
62cedd11
MC		 3222 tmp = tr32(GRC_EEPROM_DATA);
3223
3224 /*
3225 * The data will always be opposite the native endian
3226 * format. Perform a blind byteswap to compensate.
3227 */
3228 *val = swab32(tmp);
3229
ffbcfed4
MC		 3230 return 0;
3231}
3232
3233#define NVRAM_CMD_TIMEOUT 10000
3234
3235static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3236{
3237 int i;
3238
3239 tw32(NVRAM_CMD, nvram_cmd);
3240 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3241 udelay(10);
3242 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3243 udelay(10);
3244 break;
3245 }
3246 }
3247
3248 if (i == NVRAM_CMD_TIMEOUT)
3249 return -EBUSY;
3250
3251 return 0;
3252}
3253
3254static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3255{
63c3a66f
JP		 3256 if (tg3_flag(tp, NVRAM) &&
3257 tg3_flag(tp, NVRAM_BUFFERED) &&
3258 tg3_flag(tp, FLASH) &&
3259 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3260 (tp->nvram_jedecnum == JEDEC_ATMEL))
3261
3262 addr = ((addr / tp->nvram_pagesize) <<
3263 ATMEL_AT45DB0X1B_PAGE_POS) +
3264 (addr % tp->nvram_pagesize);
3265
3266 return addr;
3267}
3268
3269static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3270{
63c3a66f
JP		 3271 if (tg3_flag(tp, NVRAM) &&
3272 tg3_flag(tp, NVRAM_BUFFERED) &&
3273 tg3_flag(tp, FLASH) &&
3274 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3275 (tp->nvram_jedecnum == JEDEC_ATMEL))
3276
3277 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3278 tp->nvram_pagesize) +
3279 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3280
3281 return addr;
3282}
3283
e4f34110
MC		 3284/* NOTE: Data read in from NVRAM is byteswapped according to
3285 * the byteswapping settings for all other register accesses.
3286 * tg3 devices are BE devices, so on a BE machine, the data
3287 * returned will be exactly as it is seen in NVRAM. On a LE
3288 * machine, the 32-bit value will be byteswapped.
3289 */
ffbcfed4
MC		 3290static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3291{
3292 int ret;
3293
63c3a66f 3294 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3295 return tg3_nvram_read_using_eeprom(tp, offset, val);
3296
3297 offset = tg3_nvram_phys_addr(tp, offset);
3298
3299 if (offset > NVRAM_ADDR_MSK)
3300 return -EINVAL;
3301
3302 ret = tg3_nvram_lock(tp);
3303 if (ret)
3304 return ret;
3305
3306 tg3_enable_nvram_access(tp);
3307
3308 tw32(NVRAM_ADDR, offset);
3309 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3310 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3311
3312 if (ret == 0)
e4f34110 3313 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3314
3315 tg3_disable_nvram_access(tp);
3316
3317 tg3_nvram_unlock(tp);
3318
3319 return ret;
3320}
3321
a9dc529d
MC		 3322/* Ensures NVRAM data is in bytestream format. */
3323static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3324{
3325 u32 v;
a9dc529d 3326 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3327 if (!res)
a9dc529d 3328 *val = cpu_to_be32(v);
ffbcfed4
MC		 3329 return res;
3330}
3331
dbe9b92a
MC		 3332static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3333 u32 offset, u32 len, u8 *buf)
3334{
3335 int i, j, rc = 0;
3336 u32 val;
3337
3338 for (i = 0; i < len; i += 4) {
3339 u32 addr;
3340 __be32 data;
3341
3342 addr = offset + i;
3343
3344 memcpy(&data, buf + i, 4);
3345
3346 /*
3347 * The SEEPROM interface expects the data to always be opposite
3348 * the native endian format. We accomplish this by reversing
3349 * all the operations that would have been performed on the
3350 * data from a call to tg3_nvram_read_be32().
3351 */
3352 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3353
3354 val = tr32(GRC_EEPROM_ADDR);
3355 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3356
3357 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3358 EEPROM_ADDR_READ);
3359 tw32(GRC_EEPROM_ADDR, val |
3360 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3361 (addr & EEPROM_ADDR_ADDR_MASK) |
3362 EEPROM_ADDR_START |
3363 EEPROM_ADDR_WRITE);
3364
3365 for (j = 0; j < 1000; j++) {
3366 val = tr32(GRC_EEPROM_ADDR);
3367
3368 if (val & EEPROM_ADDR_COMPLETE)
3369 break;
3370 msleep(1);
3371 }
3372 if (!(val & EEPROM_ADDR_COMPLETE)) {
3373 rc = -EBUSY;
3374 break;
3375 }
3376 }
3377
3378 return rc;
3379}
3380
3381/* offset and length are dword aligned */
3382static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3383 u8 *buf)
3384{
3385 int ret = 0;
3386 u32 pagesize = tp->nvram_pagesize;
3387 u32 pagemask = pagesize - 1;
3388 u32 nvram_cmd;
3389 u8 *tmp;
3390
3391 tmp = kmalloc(pagesize, GFP_KERNEL);
3392 if (tmp == NULL)
3393 return -ENOMEM;
3394
3395 while (len) {
3396 int j;
3397 u32 phy_addr, page_off, size;
3398
3399 phy_addr = offset & ~pagemask;
3400
3401 for (j = 0; j < pagesize; j += 4) {
3402 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3403 (__be32 *) (tmp + j));
3404 if (ret)
3405 break;
3406 }
3407 if (ret)
3408 break;
3409
3410 page_off = offset & pagemask;
3411 size = pagesize;
3412 if (len < size)
3413 size = len;
3414
3415 len -= size;
3416
3417 memcpy(tmp + page_off, buf, size);
3418
3419 offset = offset + (pagesize - page_off);
3420
3421 tg3_enable_nvram_access(tp);
3422
3423 /*
3424 * Before we can erase the flash page, we need
3425 * to issue a special "write enable" command.
3426 */
3427 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3428
3429 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3430 break;
3431
3432 /* Erase the target page */
3433 tw32(NVRAM_ADDR, phy_addr);
3434
3435 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3436 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3437
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3439 break;
3440
3441 /* Issue another write enable to start the write. */
3442 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3443
3444 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3445 break;
3446
3447 for (j = 0; j < pagesize; j += 4) {
3448 __be32 data;
3449
3450 data = *((__be32 *) (tmp + j));
3451
3452 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3453
3454 tw32(NVRAM_ADDR, phy_addr + j);
3455
3456 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3457 NVRAM_CMD_WR;
3458
3459 if (j == 0)
3460 nvram_cmd |= NVRAM_CMD_FIRST;
3461 else if (j == (pagesize - 4))
3462 nvram_cmd |= NVRAM_CMD_LAST;
3463
3464 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3465 if (ret)
3466 break;
3467 }
3468 if (ret)
3469 break;
3470 }
3471
3472 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3473 tg3_nvram_exec_cmd(tp, nvram_cmd);
3474
3475 kfree(tmp);
3476
3477 return ret;
3478}
3479
3480/* offset and length are dword aligned */
3481static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3482 u8 *buf)
3483{
3484 int i, ret = 0;
3485
3486 for (i = 0; i < len; i += 4, offset += 4) {
3487 u32 page_off, phy_addr, nvram_cmd;
3488 __be32 data;
3489
3490 memcpy(&data, buf + i, 4);
3491 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3492
3493 page_off = offset % tp->nvram_pagesize;
3494
3495 phy_addr = tg3_nvram_phys_addr(tp, offset);
3496
dbe9b92a
MC		 3497 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3498
3499 if (page_off == 0 || i == 0)
3500 nvram_cmd |= NVRAM_CMD_FIRST;
3501 if (page_off == (tp->nvram_pagesize - 4))
3502 nvram_cmd |= NVRAM_CMD_LAST;
3503
3504 if (i == (len - 4))
3505 nvram_cmd |= NVRAM_CMD_LAST;
3506
42278224
MC		 3507 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3508 !tg3_flag(tp, FLASH) ||
3509 !tg3_flag(tp, 57765_PLUS))
3510 tw32(NVRAM_ADDR, phy_addr);
3511
4153577a 3512 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3513 !tg3_flag(tp, 5755_PLUS) &&
3514 (tp->nvram_jedecnum == JEDEC_ST) &&
3515 (nvram_cmd & NVRAM_CMD_FIRST)) {
3516 u32 cmd;
3517
3518 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3519 ret = tg3_nvram_exec_cmd(tp, cmd);
3520 if (ret)
3521 break;
3522 }
3523 if (!tg3_flag(tp, FLASH)) {
3524 /* We always do complete word writes to eeprom. */
3525 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3526 }
3527
3528 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3529 if (ret)
3530 break;
3531 }
3532 return ret;
3533}
3534
3535/* offset and length are dword aligned */
3536static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3537{
3538 int ret;
3539
3540 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3541 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3542 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3543 udelay(40);
3544 }
3545
3546 if (!tg3_flag(tp, NVRAM)) {
3547 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3548 } else {
3549 u32 grc_mode;
3550
3551 ret = tg3_nvram_lock(tp);
3552 if (ret)
3553 return ret;
3554
3555 tg3_enable_nvram_access(tp);
3556 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3557 tw32(NVRAM_WRITE1, 0x406);
3558
3559 grc_mode = tr32(GRC_MODE);
3560 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3561
3562 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3563 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3564 buf);
3565 } else {
3566 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3567 buf);
3568 }
3569
3570 grc_mode = tr32(GRC_MODE);
3571 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3572
3573 tg3_disable_nvram_access(tp);
3574 tg3_nvram_unlock(tp);
3575 }
3576
3577 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3578 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3579 udelay(40);
3580 }
3581
3582 return ret;
3583}
3584
997b4f13
MC		 3585#define RX_CPU_SCRATCH_BASE 0x30000
3586#define RX_CPU_SCRATCH_SIZE 0x04000
3587#define TX_CPU_SCRATCH_BASE 0x34000
3588#define TX_CPU_SCRATCH_SIZE 0x04000
3589
3590/* tp->lock is held. */
837c45bb 3591static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3592{
3593 int i;
837c45bb 3594 const int iters = 10000;
997b4f13 3595
837c45bb
NS		 3596 for (i = 0; i < iters; i++) {
3597 tw32(cpu_base + CPU_STATE, 0xffffffff);
3598 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3599 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3600 break;
6d446ec3
GS		 3601 if (pci_channel_offline(tp->pdev))
3602 return -EBUSY;
837c45bb
NS		 3603 }
3604
3605 return (i == iters) ? -EBUSY : 0;
3606}
3607
3608/* tp->lock is held. */
3609static int tg3_rxcpu_pause(struct tg3 *tp)
3610{
3611 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3612
3613 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3614 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3615 udelay(10);
3616
3617 return rc;
3618}
3619
3620/* tp->lock is held. */
3621static int tg3_txcpu_pause(struct tg3 *tp)
3622{
3623 return tg3_pause_cpu(tp, TX_CPU_BASE);
3624}
3625
3626/* tp->lock is held. */
3627static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3628{
3629 tw32(cpu_base + CPU_STATE, 0xffffffff);
3630 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3631}
3632
3633/* tp->lock is held. */
3634static void tg3_rxcpu_resume(struct tg3 *tp)
3635{
3636 tg3_resume_cpu(tp, RX_CPU_BASE);
3637}
3638
3639/* tp->lock is held. */
3640static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3641{
3642 int rc;
3643
3644 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3645
4153577a 3646 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3647 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3648
3649 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3650 return 0;
3651 }
837c45bb
NS		 3652 if (cpu_base == RX_CPU_BASE) {
3653 rc = tg3_rxcpu_pause(tp);
997b4f13 3654 } else {
7e6c63f0
HM		 3655 /*
3656 * There is only an Rx CPU for the 5750 derivative in the
3657 * BCM4785.
3658 */
3659 if (tg3_flag(tp, IS_SSB_CORE))
3660 return 0;
3661
837c45bb 3662 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3663 }
3664
837c45bb 3665 if (rc) {
997b4f13 3666 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3667 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3668 return -ENODEV;
3669 }
3670
3671 /* Clear firmware's nvram arbitration. */
3672 if (tg3_flag(tp, NVRAM))
3673 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3674 return 0;
3675}
3676
31f11a95
NS		 3677static int tg3_fw_data_len(struct tg3 *tp,
3678 const struct tg3_firmware_hdr *fw_hdr)
3679{
3680 int fw_len;
3681
3682 /* Non fragmented firmware have one firmware header followed by a
3683 * contiguous chunk of data to be written. The length field in that
3684 * header is not the length of data to be written but the complete
3685 * length of the bss. The data length is determined based on
3686 * tp->fw->size minus headers.
3687 *
3688 * Fragmented firmware have a main header followed by multiple
3689 * fragments. Each fragment is identical to non fragmented firmware
3690 * with a firmware header followed by a contiguous chunk of data. In
3691 * the main header, the length field is unused and set to 0xffffffff.
3692 * In each fragment header the length is the entire size of that
3693 * fragment i.e. fragment data + header length. Data length is
3694 * therefore length field in the header minus TG3_FW_HDR_LEN.
3695 */
3696 if (tp->fw_len == 0xffffffff)
3697 fw_len = be32_to_cpu(fw_hdr->len);
3698 else
3699 fw_len = tp->fw->size;
3700
3701 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3702}
3703
997b4f13
MC		 3704/* tp->lock is held. */
3705static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3706 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3707 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3708{
c4dab506 3709 int err, i;
997b4f13 3710 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3711 int total_len = tp->fw->size;
997b4f13
MC		 3712
3713 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3714 netdev_err(tp->dev,
3715 "%s: Trying to load TX cpu firmware which is 5705\n",
3716 __func__);
3717 return -EINVAL;
3718 }
3719
c4dab506 3720 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3721 write_op = tg3_write_mem;
3722 else
3723 write_op = tg3_write_indirect_reg32;
3724
c4dab506
NS		 3725 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3726 /* It is possible that bootcode is still loading at this point.
3727 * Get the nvram lock first before halting the cpu.
3728 */
3729 int lock_err = tg3_nvram_lock(tp);
3730 err = tg3_halt_cpu(tp, cpu_base);
3731 if (!lock_err)
3732 tg3_nvram_unlock(tp);
3733 if (err)
3734 goto out;
997b4f13 3735
c4dab506
NS		 3736 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3737 write_op(tp, cpu_scratch_base + i, 0);
3738 tw32(cpu_base + CPU_STATE, 0xffffffff);
3739 tw32(cpu_base + CPU_MODE,
3740 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3741 } else {
3742 /* Subtract additional main header for fragmented firmware and
3743 * advance to the first fragment
3744 */
3745 total_len -= TG3_FW_HDR_LEN;
3746 fw_hdr++;
3747 }
77997ea3 3748
31f11a95
NS		 3749 do {
3750 u32 *fw_data = (u32 *)(fw_hdr + 1);
3751 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3752 write_op(tp, cpu_scratch_base +
3753 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3754 (i * sizeof(u32)),
3755 be32_to_cpu(fw_data[i]));
3756
3757 total_len -= be32_to_cpu(fw_hdr->len);
3758
3759 /* Advance to next fragment */
3760 fw_hdr = (struct tg3_firmware_hdr *)
3761 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3762 } while (total_len > 0);
997b4f13
MC		 3763
3764 err = 0;
3765
3766out:
3767 return err;
3768}
3769
f4bffb28
NS		 3770/* tp->lock is held. */
3771static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3772{
3773 int i;
3774 const int iters = 5;
3775
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32_f(cpu_base + CPU_PC, pc);
3778
3779 for (i = 0; i < iters; i++) {
3780 if (tr32(cpu_base + CPU_PC) == pc)
3781 break;
3782 tw32(cpu_base + CPU_STATE, 0xffffffff);
3783 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3784 tw32_f(cpu_base + CPU_PC, pc);
3785 udelay(1000);
3786 }
3787
3788 return (i == iters) ? -EBUSY : 0;
3789}
3790
997b4f13
MC		 3791/* tp->lock is held. */
3792static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3793{
77997ea3 3794 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3795 int err;
997b4f13 3796
77997ea3 3797 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3798
3799 /* Firmware blob starts with version numbers, followed by
3800 start address and length. We are setting complete length.
3801 length = end_address_of_bss - start_address_of_text.
3802 Remainder is the blob to be loaded contiguously
3803 from start address. */
3804
997b4f13
MC		 3805 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3806 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3807 fw_hdr);
997b4f13
MC		 3808 if (err)
3809 return err;
3810
3811 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3812 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3813 fw_hdr);
997b4f13
MC		 3814 if (err)
3815 return err;
3816
3817 /* Now startup only the RX cpu. */
77997ea3
NS		 3818 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3819 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3820 if (err) {
997b4f13
MC		 3821 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3822 "should be %08x\n", __func__,
77997ea3
NS		 3823 tr32(RX_CPU_BASE + CPU_PC),
3824 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3825 return -ENODEV;
3826 }
837c45bb
NS		 3827
3828 tg3_rxcpu_resume(tp);
997b4f13
MC		 3829
3830 return 0;
3831}
3832
c4dab506
NS		 3833static int tg3_validate_rxcpu_state(struct tg3 *tp)
3834{
3835 const int iters = 1000;
3836 int i;
3837 u32 val;
3838
3839 /* Wait for boot code to complete initialization and enter service
3840 * loop. It is then safe to download service patches
3841 */
3842 for (i = 0; i < iters; i++) {
3843 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3844 break;
3845
3846 udelay(10);
3847 }
3848
3849 if (i == iters) {
3850 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3851 return -EBUSY;
3852 }
3853
3854 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3855 if (val & 0xff) {
3856 netdev_warn(tp->dev,
3857 "Other patches exist. Not downloading EEE patch\n");
3858 return -EEXIST;
3859 }
3860
3861 return 0;
3862}
3863
3864/* tp->lock is held. */
3865static void tg3_load_57766_firmware(struct tg3 *tp)
3866{
3867 struct tg3_firmware_hdr *fw_hdr;
3868
3869 if (!tg3_flag(tp, NO_NVRAM))
3870 return;
3871
3872 if (tg3_validate_rxcpu_state(tp))
3873 return;
3874
3875 if (!tp->fw)
3876 return;
3877
3878 /* This firmware blob has a different format than older firmware
3879 * releases as given below. The main difference is we have fragmented
3880 * data to be written to non-contiguous locations.
3881 *
3882 * In the beginning we have a firmware header identical to other
3883 * firmware which consists of version, base addr and length. The length
3884 * here is unused and set to 0xffffffff.
3885 *
3886 * This is followed by a series of firmware fragments which are
3887 * individually identical to previous firmware. i.e. they have the
3888 * firmware header and followed by data for that fragment. The version
3889 * field of the individual fragment header is unused.
3890 */
3891
3892 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3893 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3894 return;
3895
3896 if (tg3_rxcpu_pause(tp))
3897 return;
3898
3899 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3900 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3901
3902 tg3_rxcpu_resume(tp);
3903}
3904
997b4f13
MC		 3905/* tp->lock is held. */
3906static int tg3_load_tso_firmware(struct tg3 *tp)
3907{
77997ea3 3908 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3909 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3910 int err;
997b4f13 3911
1caf13eb 3912 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3913 return 0;
3914
77997ea3 3915 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3916
3917 /* Firmware blob starts with version numbers, followed by
3918 start address and length. We are setting complete length.
3919 length = end_address_of_bss - start_address_of_text.
3920 Remainder is the blob to be loaded contiguously
3921 from start address. */
3922
997b4f13 3923 cpu_scratch_size = tp->fw_len;
997b4f13 3924
4153577a 3925 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3926 cpu_base = RX_CPU_BASE;
3927 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3928 } else {
3929 cpu_base = TX_CPU_BASE;
3930 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3931 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3932 }
3933
3934 err = tg3_load_firmware_cpu(tp, cpu_base,
3935 cpu_scratch_base, cpu_scratch_size,
77997ea3 3936 fw_hdr);
997b4f13
MC		 3937 if (err)
3938 return err;
3939
3940 /* Now startup the cpu. */
77997ea3
NS		 3941 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3942 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3943 if (err) {
997b4f13
MC		 3944 netdev_err(tp->dev,
3945 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3946 __func__, tr32(cpu_base + CPU_PC),
3947 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3948 return -ENODEV;
3949 }
837c45bb
NS		 3950
3951 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3952 return 0;
3953}
3954
f022ae62
MC		 3955/* tp->lock is held. */
3956static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3957{
3958 u32 addr_high, addr_low;
3959
3960 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3961 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3962 (mac_addr[4] << 8) | mac_addr[5]);
3963
3964 if (index < 4) {
3965 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3966 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3967 } else {
3968 index -= 4;
3969 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3970 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3971 }
3972}
997b4f13 3973
3f007891 3974/* tp->lock is held. */
953c96e0 3975static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891 3976{
f022ae62 3977 u32 addr_high;
3f007891
MC		 3978 int i;
3979
3f007891
MC		 3980 for (i = 0; i < 4; i++) {
3981 if (i == 1 && skip_mac_1)
3982 continue;
f022ae62 3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3984 }
3985
4153577a
JP		 3986 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3987 tg3_asic_rev(tp) == ASIC_REV_5704) {
f022ae62
MC		 3988 for (i = 4; i < 16; i++)
3989 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3990 }
3991
3992 addr_high = (tp->dev->dev_addr[0] +
3993 tp->dev->dev_addr[1] +
3994 tp->dev->dev_addr[2] +
3995 tp->dev->dev_addr[3] +
3996 tp->dev->dev_addr[4] +
3997 tp->dev->dev_addr[5]) &
3998 TX_BACKOFF_SEED_MASK;
3999 tw32(MAC_TX_BACKOFF_SEED, addr_high);
4000}
4001
c866b7ea 4002static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 4003{
c866b7ea
RW		 4004 /*
4005 * Make sure register accesses (indirect or otherwise) will function
4006 * correctly.
1da177e4
LT		 4007 */
4008 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 4009 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4010}
1da177e4 4011
c866b7ea
RW		 4012static int tg3_power_up(struct tg3 *tp)
4013{
bed9829f 4014 int err;
8c6bda1a 4015
bed9829f 4016 tg3_enable_register_access(tp);
1da177e4 4017
bed9829f
MC		 4018 err = pci_set_power_state(tp->pdev, PCI_D0);
4019 if (!err) {
4020 /* Switch out of Vaux if it is a NIC */
4021 tg3_pwrsrc_switch_to_vmain(tp);
4022 } else {
4023 netdev_err(tp->dev, "Transition to D0 failed\n");
4024 }
1da177e4 4025
bed9829f 4026 return err;
c866b7ea 4027}
1da177e4 4028
953c96e0 4029static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4030
c866b7ea
RW		 4031static int tg3_power_down_prepare(struct tg3 *tp)
4032{
4033 u32 misc_host_ctrl;
4034 bool device_should_wake, do_low_power;
4035
4036 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4037
4038 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4039 if (tg3_flag(tp, CLKREQ_BUG))
4040 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4041 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4042
1da177e4
LT		 4043 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4044 tw32(TG3PCI_MISC_HOST_CTRL,
4045 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4046
c866b7ea 4047 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4048 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4049
63c3a66f 4050 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4051 do_low_power = false;
f07e9af3 4052 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4053 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4054 struct phy_device *phydev;
0a459aac 4055 u32 phyid, advertising;
b02fd9e3 4056
ead2402c 4057 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 4058
80096068 4059 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4060
c6700ce2
MC		 4061 tp->link_config.speed = phydev->speed;
4062 tp->link_config.duplex = phydev->duplex;
4063 tp->link_config.autoneg = phydev->autoneg;
4064 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4065
4066 advertising = ADVERTISED_TP |
4067 ADVERTISED_Pause |
4068 ADVERTISED_Autoneg |
4069 ADVERTISED_10baseT_Half;
4070
63c3a66f
JP		 4071 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4072 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4073 advertising |=
4074 ADVERTISED_100baseT_Half |
4075 ADVERTISED_100baseT_Full |
4076 ADVERTISED_10baseT_Full;
4077 else
4078 advertising |= ADVERTISED_10baseT_Full;
4079 }
4080
4081 phydev->advertising = advertising;
4082
4083 phy_start_aneg(phydev);
0a459aac
MC		 4084
4085 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4086 if (phyid != PHY_ID_BCMAC131) {
4087 phyid &= PHY_BCM_OUI_MASK;
4088 if (phyid == PHY_BCM_OUI_1 ||
4089 phyid == PHY_BCM_OUI_2 ||
4090 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4091 do_low_power = true;
4092 }
b02fd9e3 4093 }
dd477003 4094 } else {
2023276e 4095 do_low_power = true;
0a459aac 4096
c6700ce2 4097 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4098 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4099
2855b9fe 4100 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4101 tg3_setup_phy(tp, false);
1da177e4
LT		 4102 }
4103
4153577a 4104 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4105 u32 val;
4106
4107 val = tr32(GRC_VCPU_EXT_CTRL);
4108 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4109 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4110 int i;
4111 u32 val;
4112
4113 for (i = 0; i < 200; i++) {
4114 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4115 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4116 break;
4117 msleep(1);
4118 }
4119 }
63c3a66f 4120 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4121 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4122 WOL_DRV_STATE_SHUTDOWN |
4123 WOL_DRV_WOL |
4124 WOL_SET_MAGIC_PKT);
6921d201 4125
05ac4cb7 4126 if (device_should_wake) {
1da177e4
LT		 4127 u32 mac_mode;
4128
f07e9af3 4129 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4130 if (do_low_power &&
4131 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4132 tg3_phy_auxctl_write(tp,
4133 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4134 MII_TG3_AUXCTL_PCTL_WOL_EN |
4135 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4136 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4137 udelay(40);
4138 }
1da177e4 4139
f07e9af3 4140 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4141 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4142 else if (tp->phy_flags &
4143 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4144 if (tp->link_config.active_speed == SPEED_1000)
4145 mac_mode = MAC_MODE_PORT_MODE_GMII;
4146 else
4147 mac_mode = MAC_MODE_PORT_MODE_MII;
4148 } else
3f7045c1 4149 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4150
e8f3f6ca 4151 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4152 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4153 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4154 SPEED_100 : SPEED_10;
4155 if (tg3_5700_link_polarity(tp, speed))
4156 mac_mode |= MAC_MODE_LINK_POLARITY;
4157 else
4158 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4159 }
1da177e4
LT		 4160 } else {
4161 mac_mode = MAC_MODE_PORT_MODE_TBI;
4162 }
4163
63c3a66f 4164 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4165 tw32(MAC_LED_CTRL, tp->led_ctrl);
4166
05ac4cb7 4167 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4168 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4169 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4170 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4171
63c3a66f 4172 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4173 mac_mode |= MAC_MODE_APE_TX_EN |
4174 MAC_MODE_APE_RX_EN |
4175 MAC_MODE_TDE_ENABLE;
3bda1258 4176
1da177e4
LT		 4177 tw32_f(MAC_MODE, mac_mode);
4178 udelay(100);
4179
4180 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4181 udelay(10);
4182 }
4183
63c3a66f 4184 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4185 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4186 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4187 u32 base_val;
4188
4189 base_val = tp->pci_clock_ctrl;
4190 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4191 CLOCK_CTRL_TXCLK_DISABLE);
4192
b401e9e2
MC		 4193 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4194 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4195 } else if (tg3_flag(tp, 5780_CLASS) ||
4196 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4197 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4198 /* do nothing */
63c3a66f 4199 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4200 u32 newbits1, newbits2;
4201
4153577a
JP		 4202 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4203 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4204 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4205 CLOCK_CTRL_TXCLK_DISABLE |
4206 CLOCK_CTRL_ALTCLK);
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4208 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4209 newbits1 = CLOCK_CTRL_625_CORE;
4210 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4211 } else {
4212 newbits1 = CLOCK_CTRL_ALTCLK;
4213 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4214 }
4215
b401e9e2
MC		 4216 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4217 40);
1da177e4 4218
b401e9e2
MC		 4219 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4220 40);
1da177e4 4221
63c3a66f 4222 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4223 u32 newbits3;
4224
4153577a
JP		 4225 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4226 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4227 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4228 CLOCK_CTRL_TXCLK_DISABLE |
4229 CLOCK_CTRL_44MHZ_CORE);
4230 } else {
4231 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4232 }
4233
b401e9e2
MC		 4234 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4235 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4236 }
4237 }
4238
63c3a66f 4239 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4240 tg3_power_down_phy(tp, do_low_power);
6921d201 4241
cd0d7228 4242 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4243
4244 /* Workaround for unstable PLL clock */
7e6c63f0 4245 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4246 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4247 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4248 u32 val = tr32(0x7d00);
4249
4250 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4251 tw32(0x7d00, val);
63c3a66f 4252 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4253 int err;
4254
4255 err = tg3_nvram_lock(tp);
1da177e4 4256 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4257 if (!err)
4258 tg3_nvram_unlock(tp);
6921d201 4259 }
1da177e4
LT		 4260 }
4261
bbadf503
MC		 4262 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4263
2e460fc0
NS		 4264 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4265
c866b7ea
RW		 4266 return 0;
4267}
12dac075 4268
c866b7ea
RW		 4269static void tg3_power_down(struct tg3 *tp)
4270{
63c3a66f 4271 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4272 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4273}
4274
1da177e4
LT		 4275static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4276{
4277 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4278 case MII_TG3_AUX_STAT_10HALF:
4279 *speed = SPEED_10;
4280 *duplex = DUPLEX_HALF;
4281 break;
4282
4283 case MII_TG3_AUX_STAT_10FULL:
4284 *speed = SPEED_10;
4285 *duplex = DUPLEX_FULL;
4286 break;
4287
4288 case MII_TG3_AUX_STAT_100HALF:
4289 *speed = SPEED_100;
4290 *duplex = DUPLEX_HALF;
4291 break;
4292
4293 case MII_TG3_AUX_STAT_100FULL:
4294 *speed = SPEED_100;
4295 *duplex = DUPLEX_FULL;
4296 break;
4297
4298 case MII_TG3_AUX_STAT_1000HALF:
4299 *speed = SPEED_1000;
4300 *duplex = DUPLEX_HALF;
4301 break;
4302
4303 case MII_TG3_AUX_STAT_1000FULL:
4304 *speed = SPEED_1000;
4305 *duplex = DUPLEX_FULL;
4306 break;
4307
4308 default:
f07e9af3 4309 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4310 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4311 SPEED_10;
4312 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4313 DUPLEX_HALF;
4314 break;
4315 }
e740522e
MC		 4316 *speed = SPEED_UNKNOWN;
4317 *duplex = DUPLEX_UNKNOWN;
1da177e4 4318 break;
855e1111 4319 }
1da177e4
LT		 4320}
4321
42b64a45 4322static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4323{
42b64a45
MC		 4324 int err = 0;
4325 u32 val, new_adv;
1da177e4 4326
42b64a45 4327 new_adv = ADVERTISE_CSMA;
202ff1c2 4328 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4329 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4330
42b64a45
MC		 4331 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4332 if (err)
4333 goto done;
ba4d07a8 4334
4f272096
MC		 4335 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4336 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4337
4153577a
JP		 4338 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4339 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4340 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4341
4f272096
MC		 4342 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4343 if (err)
4344 goto done;
4345 }
1da177e4 4346
42b64a45
MC		 4347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4348 goto done;
52b02d04 4349
42b64a45
MC		 4350 tw32(TG3_CPMU_EEE_MODE,
4351 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4352
daf3ec68 4353 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4354 if (!err) {
4355 u32 err2;
52b02d04 4356
b715ce94
MC		 4357 val = 0;
4358 /* Advertise 100-BaseTX EEE ability */
4359 if (advertise & ADVERTISED_100baseT_Full)
4360 val |= MDIO_AN_EEE_ADV_100TX;
4361 /* Advertise 1000-BaseT EEE ability */
4362 if (advertise & ADVERTISED_1000baseT_Full)
4363 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4364
4365 if (!tp->eee.eee_enabled) {
4366 val = 0;
4367 tp->eee.advertised = 0;
4368 } else {
4369 tp->eee.advertised = advertise &
4370 (ADVERTISED_100baseT_Full |
4371 ADVERTISED_1000baseT_Full);
4372 }
4373
b715ce94
MC		 4374 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4375 if (err)
4376 val = 0;
4377
4153577a 4378 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4379 case ASIC_REV_5717:
4380 case ASIC_REV_57765:
55086ad9 4381 case ASIC_REV_57766:
21a00ab2 4382 case ASIC_REV_5719:
b715ce94
MC		 4383 /* If we advertised any eee advertisements above... */
4384 if (val)
4385 val = MII_TG3_DSP_TAP26_ALNOKO |
4386 MII_TG3_DSP_TAP26_RMRXSTO |
4387 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4388 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4389 /* Fall through */
4390 case ASIC_REV_5720:
c65a17f4 4391 case ASIC_REV_5762:
be671947
MC		 4392 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4393 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4394 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4395 }
52b02d04 4396
daf3ec68 4397 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4398 if (!err)
4399 err = err2;
4400 }
4401
4402done:
4403 return err;
4404}
4405
4406static void tg3_phy_copper_begin(struct tg3 *tp)
4407{
d13ba512
MC		 4408 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4409 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4410 u32 adv, fc;
4411
942d1af0
NS		 4412 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4413 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4414 adv = ADVERTISED_10baseT_Half |
4415 ADVERTISED_10baseT_Full;
4416 if (tg3_flag(tp, WOL_SPEED_100MB))
4417 adv |= ADVERTISED_100baseT_Half |
4418 ADVERTISED_100baseT_Full;
7c786065
NS		 4419 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4420 if (!(tp->phy_flags &
4421 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4422 adv |= ADVERTISED_1000baseT_Half;
4423 adv |= ADVERTISED_1000baseT_Full;
4424 }
d13ba512
MC		 4425
4426 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4427 } else {
d13ba512
MC		 4428 adv = tp->link_config.advertising;
4429 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4430 adv &= ~(ADVERTISED_1000baseT_Half |
4431 ADVERTISED_1000baseT_Full);
4432
4433 fc = tp->link_config.flowctrl;
52b02d04 4434 }
52b02d04 4435
d13ba512 4436 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4437
942d1af0
NS		 4438 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4439 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4440 /* Normally during power down we want to autonegotiate
4441 * the lowest possible speed for WOL. However, to avoid
4442 * link flap, we leave it untouched.
4443 */
4444 return;
4445 }
4446
d13ba512
MC		 4447 tg3_writephy(tp, MII_BMCR,
4448 BMCR_ANENABLE | BMCR_ANRESTART);
4449 } else {
4450 int i;
1da177e4
LT		 4451 u32 bmcr, orig_bmcr;
4452
4453 tp->link_config.active_speed = tp->link_config.speed;
4454 tp->link_config.active_duplex = tp->link_config.duplex;
4455
7c6cdead
NS		 4456 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4457 /* With autoneg disabled, 5715 only links up when the
4458 * advertisement register has the configured speed
4459 * enabled.
4460 */
4461 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4462 }
4463
1da177e4
LT		 4464 bmcr = 0;
4465 switch (tp->link_config.speed) {
4466 default:
4467 case SPEED_10:
4468 break;
4469
4470 case SPEED_100:
4471 bmcr |= BMCR_SPEED100;
4472 break;
4473
4474 case SPEED_1000:
221c5637 4475 bmcr |= BMCR_SPEED1000;
1da177e4 4476 break;
855e1111 4477 }
1da177e4
LT		 4478
4479 if (tp->link_config.duplex == DUPLEX_FULL)
4480 bmcr |= BMCR_FULLDPLX;
4481
4482 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4483 (bmcr != orig_bmcr)) {
4484 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4485 for (i = 0; i < 1500; i++) {
4486 u32 tmp;
4487
4488 udelay(10);
4489 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4490 tg3_readphy(tp, MII_BMSR, &tmp))
4491 continue;
4492 if (!(tmp & BMSR_LSTATUS)) {
4493 udelay(40);
4494 break;
4495 }
4496 }
4497 tg3_writephy(tp, MII_BMCR, bmcr);
4498 udelay(40);
4499 }
1da177e4
LT		 4500 }
4501}
4502
fdad8de4
NS		 4503static int tg3_phy_pull_config(struct tg3 *tp)
4504{
4505 int err;
4506 u32 val;
4507
4508 err = tg3_readphy(tp, MII_BMCR, &val);
4509 if (err)
4510 goto done;
4511
4512 if (!(val & BMCR_ANENABLE)) {
4513 tp->link_config.autoneg = AUTONEG_DISABLE;
4514 tp->link_config.advertising = 0;
4515 tg3_flag_clear(tp, PAUSE_AUTONEG);
4516
4517 err = -EIO;
4518
4519 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4520 case 0:
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4522 goto done;
4523
4524 tp->link_config.speed = SPEED_10;
4525 break;
4526 case BMCR_SPEED100:
4527 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4528 goto done;
4529
4530 tp->link_config.speed = SPEED_100;
4531 break;
4532 case BMCR_SPEED1000:
4533 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4534 tp->link_config.speed = SPEED_1000;
4535 break;
4536 }
4537 /* Fall through */
4538 default:
4539 goto done;
4540 }
4541
4542 if (val & BMCR_FULLDPLX)
4543 tp->link_config.duplex = DUPLEX_FULL;
4544 else
4545 tp->link_config.duplex = DUPLEX_HALF;
4546
4547 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4548
4549 err = 0;
4550 goto done;
4551 }
4552
4553 tp->link_config.autoneg = AUTONEG_ENABLE;
4554 tp->link_config.advertising = ADVERTISED_Autoneg;
4555 tg3_flag_set(tp, PAUSE_AUTONEG);
4556
4557 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4558 u32 adv;
4559
4560 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4561 if (err)
4562 goto done;
4563
4564 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4565 tp->link_config.advertising |= adv | ADVERTISED_TP;
4566
4567 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4568 } else {
4569 tp->link_config.advertising |= ADVERTISED_FIBRE;
4570 }
4571
4572 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4573 u32 adv;
4574
4575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4576 err = tg3_readphy(tp, MII_CTRL1000, &val);
4577 if (err)
4578 goto done;
4579
4580 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4581 } else {
4582 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4583 if (err)
4584 goto done;
4585
4586 adv = tg3_decode_flowctrl_1000X(val);
4587 tp->link_config.flowctrl = adv;
4588
4589 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4590 adv = mii_adv_to_ethtool_adv_x(val);
4591 }
4592
4593 tp->link_config.advertising |= adv;
4594 }
4595
4596done:
4597 return err;
4598}
4599
1da177e4
LT		 4600static int tg3_init_5401phy_dsp(struct tg3 *tp)
4601{
4602 int err;
4603
4604 /* Turn off tap power management. */
4605 /* Set Extended packet length bit */
b4bd2929 4606 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4607
6ee7c0a0
MC		 4608 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4609 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4610 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4611 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4612 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4613
4614 udelay(40);
4615
4616 return err;
4617}
4618
ed1ff5c3
NS		 4619static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4620{
5b6c273a 4621 struct ethtool_eee eee;
ed1ff5c3
NS		 4622
4623 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4624 return true;
4625
5b6c273a 4626 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4627
5b6c273a
NS		 4628 if (tp->eee.eee_enabled) {
4629 if (tp->eee.advertised != eee.advertised ||
4630 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4631 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4632 return false;
4633 } else {
4634 /* EEE is disabled but we're advertising */
4635 if (eee.advertised)
4636 return false;
4637 }
ed1ff5c3
NS		 4638
4639 return true;
4640}
4641
e2bf73e7 4642static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4643{
e2bf73e7 4644 u32 advmsk, tgtadv, advertising;
3600d918 4645
e2bf73e7
MC		 4646 advertising = tp->link_config.advertising;
4647 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4648
e2bf73e7
MC		 4649 advmsk = ADVERTISE_ALL;
4650 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4651 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4652 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4653 }
1da177e4 4654
e2bf73e7
MC		 4655 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4656 return false;
4657
4658 if ((*lcladv & advmsk) != tgtadv)
4659 return false;
b99d2a57 4660
f07e9af3 4661 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4662 u32 tg3_ctrl;
4663
e2bf73e7 4664 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4665
221c5637 4666 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4667 return false;
1da177e4 4668
3198e07f 4669 if (tgtadv &&
4153577a
JP		 4670 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4671 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4672 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4673 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4674 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4675 } else {
4676 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4677 }
4678
e2bf73e7
MC		 4679 if (tg3_ctrl != tgtadv)
4680 return false;
ef167e27
MC		 4681 }
4682
e2bf73e7 4683 return true;
ef167e27
MC		 4684}
4685
859edb26
MC		 4686static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4687{
4688 u32 lpeth = 0;
4689
4690 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4691 u32 val;
4692
4693 if (tg3_readphy(tp, MII_STAT1000, &val))
4694 return false;
4695
4696 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4697 }
4698
4699 if (tg3_readphy(tp, MII_LPA, rmtadv))
4700 return false;
4701
4702 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4703 tp->link_config.rmt_adv = lpeth;
4704
4705 return true;
4706}
4707
953c96e0 4708static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4709{
4710 if (curr_link_up != tp->link_up) {
4711 if (curr_link_up) {
84421b99 4712 netif_carrier_on(tp->dev);
f4a46d1f 4713 } else {
84421b99 4714 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4715 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4716 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4717 }
4718
4719 tg3_link_report(tp);
4720 return true;
4721 }
4722
4723 return false;
4724}
4725
3310e248
MC		 4726static void tg3_clear_mac_status(struct tg3 *tp)
4727{
4728 tw32(MAC_EVENT, 0);
4729
4730 tw32_f(MAC_STATUS,
4731 MAC_STATUS_SYNC_CHANGED |
4732 MAC_STATUS_CFG_CHANGED |
4733 MAC_STATUS_MI_COMPLETION |
4734 MAC_STATUS_LNKSTATE_CHANGED);
4735 udelay(40);
4736}
4737
9e2ecbeb
NS		 4738static void tg3_setup_eee(struct tg3 *tp)
4739{
4740 u32 val;
4741
4742 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4743 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4744 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4745 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4746
4747 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4748
4749 tw32_f(TG3_CPMU_EEE_CTRL,
4750 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4751
4752 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4753 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4754 TG3_CPMU_EEEMD_LPI_IN_RX |
4755 TG3_CPMU_EEEMD_EEE_ENABLE;
4756
4757 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4758 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4759
4760 if (tg3_flag(tp, ENABLE_APE))
4761 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4762
4763 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4764
4765 tw32_f(TG3_CPMU_EEE_DBTMR1,
4766 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4767 (tp->eee.tx_lpi_timer & 0xffff));
4768
4769 tw32_f(TG3_CPMU_EEE_DBTMR2,
4770 TG3_CPMU_DBTMR2_APE_TX_2047US |
4771 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4772}
4773
953c96e0 4774static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4775{
953c96e0 4776 bool current_link_up;
f833c4c1 4777 u32 bmsr, val;
ef167e27 4778 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4779 u16 current_speed;
4780 u8 current_duplex;
4781 int i, err;
4782
3310e248 4783 tg3_clear_mac_status(tp);
1da177e4 4784
8ef21428
MC		 4785 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4786 tw32_f(MAC_MI_MODE,
4787 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4788 udelay(80);
4789 }
1da177e4 4790
b4bd2929 4791 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4792
4793 /* Some third-party PHYs need to be reset on link going
4794 * down.
4795 */
4153577a
JP		 4796 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4797 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4798 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4799 tp->link_up) {
1da177e4
LT		 4800 tg3_readphy(tp, MII_BMSR, &bmsr);
4801 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4802 !(bmsr & BMSR_LSTATUS))
953c96e0 4803 force_reset = true;
1da177e4
LT		 4804 }
4805 if (force_reset)
4806 tg3_phy_reset(tp);
4807
79eb6904 4808 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4809 tg3_readphy(tp, MII_BMSR, &bmsr);
4810 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4811 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4812 bmsr = 0;
4813
4814 if (!(bmsr & BMSR_LSTATUS)) {
4815 err = tg3_init_5401phy_dsp(tp);
4816 if (err)
4817 return err;
4818
4819 tg3_readphy(tp, MII_BMSR, &bmsr);
4820 for (i = 0; i < 1000; i++) {
4821 udelay(10);
4822 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4823 (bmsr & BMSR_LSTATUS)) {
4824 udelay(40);
4825 break;
4826 }
4827 }
4828
79eb6904
MC		 4829 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4830 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4831 !(bmsr & BMSR_LSTATUS) &&
4832 tp->link_config.active_speed == SPEED_1000) {
4833 err = tg3_phy_reset(tp);
4834 if (!err)
4835 err = tg3_init_5401phy_dsp(tp);
4836 if (err)
4837 return err;
4838 }
4839 }
4153577a
JP		 4840 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4841 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4842 /* 5701 {A0,B0} CRC bug workaround */
4843 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4844 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4846 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4847 }
4848
4849 /* Clear pending interrupts... */
f833c4c1
MC		 4850 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4851 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4852
f07e9af3 4853 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4855 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4856 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4857
4153577a
JP		 4858 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4859 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4862 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4863 else
4864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4865 }
4866
953c96e0 4867 current_link_up = false;
e740522e
MC		 4868 current_speed = SPEED_UNKNOWN;
4869 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4870 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4871 tp->link_config.rmt_adv = 0;
1da177e4 4872
f07e9af3 4873 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4874 err = tg3_phy_auxctl_read(tp,
4875 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4876 &val);
4877 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4878 tg3_phy_auxctl_write(tp,
4879 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4880 val | (1 << 10));
1da177e4
LT		 4881 goto relink;
4882 }
4883 }
4884
4885 bmsr = 0;
4886 for (i = 0; i < 100; i++) {
4887 tg3_readphy(tp, MII_BMSR, &bmsr);
4888 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4889 (bmsr & BMSR_LSTATUS))
4890 break;
4891 udelay(40);
4892 }
4893
4894 if (bmsr & BMSR_LSTATUS) {
4895 u32 aux_stat, bmcr;
4896
4897 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4898 for (i = 0; i < 2000; i++) {
4899 udelay(10);
4900 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4901 aux_stat)
4902 break;
4903 }
4904
4905 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4906 &current_speed,
4907 &current_duplex);
4908
4909 bmcr = 0;
4910 for (i = 0; i < 200; i++) {
4911 tg3_readphy(tp, MII_BMCR, &bmcr);
4912 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4913 continue;
4914 if (bmcr && bmcr != 0x7fff)
4915 break;
4916 udelay(10);
4917 }
4918
ef167e27
MC		 4919 lcl_adv = 0;
4920 rmt_adv = 0;
1da177e4 4921
ef167e27
MC		 4922 tp->link_config.active_speed = current_speed;
4923 tp->link_config.active_duplex = current_duplex;
4924
4925 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4926 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4927
ef167e27 4928 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4929 eee_config_ok &&
e2bf73e7 4930 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4931 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4932 current_link_up = true;
ed1ff5c3
NS		 4933
4934 /* EEE settings changes take effect only after a phy
4935 * reset. If we have skipped a reset due to Link Flap
4936 * Avoidance being enabled, do it now.
4937 */
4938 if (!eee_config_ok &&
4939 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4940 !force_reset) {
4941 tg3_setup_eee(tp);
ed1ff5c3 4942 tg3_phy_reset(tp);
5b6c273a 4943 }
1da177e4
LT		 4944 } else {
4945 if (!(bmcr & BMCR_ANENABLE) &&
4946 tp->link_config.speed == current_speed &&
f0fcd7a9 4947 tp->link_config.duplex == current_duplex) {
953c96e0 4948 current_link_up = true;
1da177e4
LT		 4949 }
4950 }
4951
953c96e0 4952 if (current_link_up &&
e348c5e7
MC		 4953 tp->link_config.active_duplex == DUPLEX_FULL) {
4954 u32 reg, bit;
4955
4956 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4957 reg = MII_TG3_FET_GEN_STAT;
4958 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4959 } else {
4960 reg = MII_TG3_EXT_STAT;
4961 bit = MII_TG3_EXT_STAT_MDIX;
4962 }
4963
4964 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4965 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4966
ef167e27 4967 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4968 }
1da177e4
LT		 4969 }
4970
1da177e4 4971relink:
953c96e0 4972 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4973 tg3_phy_copper_begin(tp);
4974
7e6c63f0 4975 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4976 current_link_up = true;
7e6c63f0
HM		 4977 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4978 current_speed = SPEED_1000;
4979 current_duplex = DUPLEX_FULL;
4980 tp->link_config.active_speed = current_speed;
4981 tp->link_config.active_duplex = current_duplex;
4982 }
4983
f833c4c1 4984 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4985 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4986 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4987 current_link_up = true;
1da177e4
LT		 4988 }
4989
4990 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4991 if (current_link_up) {
1da177e4
LT		 4992 if (tp->link_config.active_speed == SPEED_100 ||
4993 tp->link_config.active_speed == SPEED_10)
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4995 else
4996 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4997 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4998 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4999 else
1da177e4
LT		 5000 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5001
7e6c63f0
HM		 5002 /* In order for the 5750 core in BCM4785 chip to work properly
5003 * in RGMII mode, the Led Control Register must be set up.
5004 */
5005 if (tg3_flag(tp, RGMII_MODE)) {
5006 u32 led_ctrl = tr32(MAC_LED_CTRL);
5007 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5008
5009 if (tp->link_config.active_speed == SPEED_10)
5010 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5011 else if (tp->link_config.active_speed == SPEED_100)
5012 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5013 LED_CTRL_100MBPS_ON);
5014 else if (tp->link_config.active_speed == SPEED_1000)
5015 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5016 LED_CTRL_1000MBPS_ON);
5017
5018 tw32(MAC_LED_CTRL, led_ctrl);
5019 udelay(40);
5020 }
5021
1da177e4
LT		 5022 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5023 if (tp->link_config.active_duplex == DUPLEX_HALF)
5024 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5025
4153577a 5026 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 5027 if (current_link_up &&
e8f3f6ca 5028 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 5029 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5030 else
5031 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5032 }
5033
5034 /* ??? Without this setting Netgear GA302T PHY does not
5035 * ??? send/receive packets...
5036 */
79eb6904 5037 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5038 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5039 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5040 tw32_f(MAC_MI_MODE, tp->mi_mode);
5041 udelay(80);
5042 }
5043
5044 tw32_f(MAC_MODE, tp->mac_mode);
5045 udelay(40);
5046
52b02d04
MC		 5047 tg3_phy_eee_adjust(tp, current_link_up);
5048
63c3a66f 5049 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5050 /* Polled via timer. */
5051 tw32_f(MAC_EVENT, 0);
5052 } else {
5053 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5054 }
5055 udelay(40);
5056
4153577a 5057 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5058 current_link_up &&
1da177e4 5059 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5060 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5061 udelay(120);
5062 tw32_f(MAC_STATUS,
5063 (MAC_STATUS_SYNC_CHANGED |
5064 MAC_STATUS_CFG_CHANGED));
5065 udelay(40);
5066 tg3_write_mem(tp,
5067 NIC_SRAM_FIRMWARE_MBOX,
5068 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5069 }
5070
5e7dfd0f 5071 /* Prevent send BD corruption. */
63c3a66f 5072 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5073 if (tp->link_config.active_speed == SPEED_100 ||
5074 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5075 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5076 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5077 else
0f49bfbd
JL		 5078 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5079 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5080 }
5081
f4a46d1f 5082 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5083
5084 return 0;
5085}
5086
5087struct tg3_fiber_aneginfo {
5088 int state;
5089#define ANEG_STATE_UNKNOWN 0
5090#define ANEG_STATE_AN_ENABLE 1
5091#define ANEG_STATE_RESTART_INIT 2
5092#define ANEG_STATE_RESTART 3
5093#define ANEG_STATE_DISABLE_LINK_OK 4
5094#define ANEG_STATE_ABILITY_DETECT_INIT 5
5095#define ANEG_STATE_ABILITY_DETECT 6
5096#define ANEG_STATE_ACK_DETECT_INIT 7
5097#define ANEG_STATE_ACK_DETECT 8
5098#define ANEG_STATE_COMPLETE_ACK_INIT 9
5099#define ANEG_STATE_COMPLETE_ACK 10
5100#define ANEG_STATE_IDLE_DETECT_INIT 11
5101#define ANEG_STATE_IDLE_DETECT 12
5102#define ANEG_STATE_LINK_OK 13
5103#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5104#define ANEG_STATE_NEXT_PAGE_WAIT 15
5105
5106 u32 flags;
5107#define MR_AN_ENABLE 0x00000001
5108#define MR_RESTART_AN 0x00000002
5109#define MR_AN_COMPLETE 0x00000004
5110#define MR_PAGE_RX 0x00000008
5111#define MR_NP_LOADED 0x00000010
5112#define MR_TOGGLE_TX 0x00000020
5113#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5114#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5115#define MR_LP_ADV_SYM_PAUSE 0x00000100
5116#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5117#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5118#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5119#define MR_LP_ADV_NEXT_PAGE 0x00001000
5120#define MR_TOGGLE_RX 0x00002000
5121#define MR_NP_RX 0x00004000
5122
5123#define MR_LINK_OK 0x80000000
5124
5125 unsigned long link_time, cur_time;
5126
5127 u32 ability_match_cfg;
5128 int ability_match_count;
5129
5130 char ability_match, idle_match, ack_match;
5131
5132 u32 txconfig, rxconfig;
5133#define ANEG_CFG_NP 0x00000080
5134#define ANEG_CFG_ACK 0x00000040
5135#define ANEG_CFG_RF2 0x00000020
5136#define ANEG_CFG_RF1 0x00000010
5137#define ANEG_CFG_PS2 0x00000001
5138#define ANEG_CFG_PS1 0x00008000
5139#define ANEG_CFG_HD 0x00004000
5140#define ANEG_CFG_FD 0x00002000
5141#define ANEG_CFG_INVAL 0x00001f06
5142
5143};
5144#define ANEG_OK 0
5145#define ANEG_DONE 1
5146#define ANEG_TIMER_ENAB 2
5147#define ANEG_FAILED -1
5148
5149#define ANEG_STATE_SETTLE_TIME 10000
5150
5151static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5152 struct tg3_fiber_aneginfo *ap)
5153{
5be73b47 5154 u16 flowctrl;
1da177e4
LT		 5155 unsigned long delta;
5156 u32 rx_cfg_reg;
5157 int ret;
5158
5159 if (ap->state == ANEG_STATE_UNKNOWN) {
5160 ap->rxconfig = 0;
5161 ap->link_time = 0;
5162 ap->cur_time = 0;
5163 ap->ability_match_cfg = 0;
5164 ap->ability_match_count = 0;
5165 ap->ability_match = 0;
5166 ap->idle_match = 0;
5167 ap->ack_match = 0;
5168 }
5169 ap->cur_time++;
5170
5171 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5172 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5173
5174 if (rx_cfg_reg != ap->ability_match_cfg) {
5175 ap->ability_match_cfg = rx_cfg_reg;
5176 ap->ability_match = 0;
5177 ap->ability_match_count = 0;
5178 } else {
5179 if (++ap->ability_match_count > 1) {
5180 ap->ability_match = 1;
5181 ap->ability_match_cfg = rx_cfg_reg;
5182 }
5183 }
5184 if (rx_cfg_reg & ANEG_CFG_ACK)
5185 ap->ack_match = 1;
5186 else
5187 ap->ack_match = 0;
5188
5189 ap->idle_match = 0;
5190 } else {
5191 ap->idle_match = 1;
5192 ap->ability_match_cfg = 0;
5193 ap->ability_match_count = 0;
5194 ap->ability_match = 0;
5195 ap->ack_match = 0;
5196
5197 rx_cfg_reg = 0;
5198 }
5199
5200 ap->rxconfig = rx_cfg_reg;
5201 ret = ANEG_OK;
5202
33f401ae 5203 switch (ap->state) {
1da177e4
LT		 5204 case ANEG_STATE_UNKNOWN:
5205 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5206 ap->state = ANEG_STATE_AN_ENABLE;
5207
5208 /* fallthru */
5209 case ANEG_STATE_AN_ENABLE:
5210 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5211 if (ap->flags & MR_AN_ENABLE) {
5212 ap->link_time = 0;
5213 ap->cur_time = 0;
5214 ap->ability_match_cfg = 0;
5215 ap->ability_match_count = 0;
5216 ap->ability_match = 0;
5217 ap->idle_match = 0;
5218 ap->ack_match = 0;
5219
5220 ap->state = ANEG_STATE_RESTART_INIT;
5221 } else {
5222 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5223 }
5224 break;
5225
5226 case ANEG_STATE_RESTART_INIT:
5227 ap->link_time = ap->cur_time;
5228 ap->flags &= ~(MR_NP_LOADED);
5229 ap->txconfig = 0;
5230 tw32(MAC_TX_AUTO_NEG, 0);
5231 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5232 tw32_f(MAC_MODE, tp->mac_mode);
5233 udelay(40);
5234
5235 ret = ANEG_TIMER_ENAB;
5236 ap->state = ANEG_STATE_RESTART;
5237
5238 /* fallthru */
5239 case ANEG_STATE_RESTART:
5240 delta = ap->cur_time - ap->link_time;
859a5887 5241 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5242 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5243 else
1da177e4 5244 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5245 break;
5246
5247 case ANEG_STATE_DISABLE_LINK_OK:
5248 ret = ANEG_DONE;
5249 break;
5250
5251 case ANEG_STATE_ABILITY_DETECT_INIT:
5252 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5253 ap->txconfig = ANEG_CFG_FD;
5254 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5255 if (flowctrl & ADVERTISE_1000XPAUSE)
5256 ap->txconfig |= ANEG_CFG_PS1;
5257 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5258 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5259 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5260 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5261 tw32_f(MAC_MODE, tp->mac_mode);
5262 udelay(40);
5263
5264 ap->state = ANEG_STATE_ABILITY_DETECT;
5265 break;
5266
5267 case ANEG_STATE_ABILITY_DETECT:
859a5887 5268 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5269 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5270 break;
5271
5272 case ANEG_STATE_ACK_DETECT_INIT:
5273 ap->txconfig |= ANEG_CFG_ACK;
5274 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5275 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5276 tw32_f(MAC_MODE, tp->mac_mode);
5277 udelay(40);
5278
5279 ap->state = ANEG_STATE_ACK_DETECT;
5280
5281 /* fallthru */
5282 case ANEG_STATE_ACK_DETECT:
5283 if (ap->ack_match != 0) {
5284 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5285 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5286 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5287 } else {
5288 ap->state = ANEG_STATE_AN_ENABLE;
5289 }
5290 } else if (ap->ability_match != 0 &&
5291 ap->rxconfig == 0) {
5292 ap->state = ANEG_STATE_AN_ENABLE;
5293 }
5294 break;
5295
5296 case ANEG_STATE_COMPLETE_ACK_INIT:
5297 if (ap->rxconfig & ANEG_CFG_INVAL) {
5298 ret = ANEG_FAILED;
5299 break;
5300 }
5301 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5302 MR_LP_ADV_HALF_DUPLEX |
5303 MR_LP_ADV_SYM_PAUSE |
5304 MR_LP_ADV_ASYM_PAUSE |
5305 MR_LP_ADV_REMOTE_FAULT1 |
5306 MR_LP_ADV_REMOTE_FAULT2 |
5307 MR_LP_ADV_NEXT_PAGE |
5308 MR_TOGGLE_RX |
5309 MR_NP_RX);
5310 if (ap->rxconfig & ANEG_CFG_FD)
5311 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5312 if (ap->rxconfig & ANEG_CFG_HD)
5313 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5314 if (ap->rxconfig & ANEG_CFG_PS1)
5315 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5316 if (ap->rxconfig & ANEG_CFG_PS2)
5317 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5318 if (ap->rxconfig & ANEG_CFG_RF1)
5319 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5320 if (ap->rxconfig & ANEG_CFG_RF2)
5321 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5322 if (ap->rxconfig & ANEG_CFG_NP)
5323 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5324
5325 ap->link_time = ap->cur_time;
5326
5327 ap->flags ^= (MR_TOGGLE_TX);
5328 if (ap->rxconfig & 0x0008)
5329 ap->flags |= MR_TOGGLE_RX;
5330 if (ap->rxconfig & ANEG_CFG_NP)
5331 ap->flags |= MR_NP_RX;
5332 ap->flags |= MR_PAGE_RX;
5333
5334 ap->state = ANEG_STATE_COMPLETE_ACK;
5335 ret = ANEG_TIMER_ENAB;
5336 break;
5337
5338 case ANEG_STATE_COMPLETE_ACK:
5339 if (ap->ability_match != 0 &&
5340 ap->rxconfig == 0) {
5341 ap->state = ANEG_STATE_AN_ENABLE;
5342 break;
5343 }
5344 delta = ap->cur_time - ap->link_time;
5345 if (delta > ANEG_STATE_SETTLE_TIME) {
5346 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5347 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5348 } else {
5349 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5350 !(ap->flags & MR_NP_RX)) {
5351 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5352 } else {
5353 ret = ANEG_FAILED;
5354 }
5355 }
5356 }
5357 break;
5358
5359 case ANEG_STATE_IDLE_DETECT_INIT:
5360 ap->link_time = ap->cur_time;
5361 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5362 tw32_f(MAC_MODE, tp->mac_mode);
5363 udelay(40);
5364
5365 ap->state = ANEG_STATE_IDLE_DETECT;
5366 ret = ANEG_TIMER_ENAB;
5367 break;
5368
5369 case ANEG_STATE_IDLE_DETECT:
5370 if (ap->ability_match != 0 &&
5371 ap->rxconfig == 0) {
5372 ap->state = ANEG_STATE_AN_ENABLE;
5373 break;
5374 }
5375 delta = ap->cur_time - ap->link_time;
5376 if (delta > ANEG_STATE_SETTLE_TIME) {
5377 /* XXX another gem from the Broadcom driver :( */
5378 ap->state = ANEG_STATE_LINK_OK;
5379 }
5380 break;
5381
5382 case ANEG_STATE_LINK_OK:
5383 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5384 ret = ANEG_DONE;
5385 break;
5386
5387 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5388 /* ??? unimplemented */
5389 break;
5390
5391 case ANEG_STATE_NEXT_PAGE_WAIT:
5392 /* ??? unimplemented */
5393 break;
5394
5395 default:
5396 ret = ANEG_FAILED;
5397 break;
855e1111 5398 }
1da177e4
LT		 5399
5400 return ret;
5401}
5402
5be73b47 5403static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5404{
5405 int res = 0;
5406 struct tg3_fiber_aneginfo aninfo;
5407 int status = ANEG_FAILED;
5408 unsigned int tick;
5409 u32 tmp;
5410
5411 tw32_f(MAC_TX_AUTO_NEG, 0);
5412
5413 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5414 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5415 udelay(40);
5416
5417 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5418 udelay(40);
5419
5420 memset(&aninfo, 0, sizeof(aninfo));
5421 aninfo.flags |= MR_AN_ENABLE;
5422 aninfo.state = ANEG_STATE_UNKNOWN;
5423 aninfo.cur_time = 0;
5424 tick = 0;
5425 while (++tick < 195000) {
5426 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5427 if (status == ANEG_DONE || status == ANEG_FAILED)
5428 break;
5429
5430 udelay(1);
5431 }
5432
5433 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5434 tw32_f(MAC_MODE, tp->mac_mode);
5435 udelay(40);
5436
5be73b47
MC		 5437 *txflags = aninfo.txconfig;
5438 *rxflags = aninfo.flags;
1da177e4
LT		 5439
5440 if (status == ANEG_DONE &&
5441 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5442 MR_LP_ADV_FULL_DUPLEX)))
5443 res = 1;
5444
5445 return res;
5446}
5447
5448static void tg3_init_bcm8002(struct tg3 *tp)
5449{
5450 u32 mac_status = tr32(MAC_STATUS);
5451 int i;
5452
5453 /* Reset when initting first time or we have a link. */
63c3a66f 5454 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5455 !(mac_status & MAC_STATUS_PCS_SYNCED))
5456 return;
5457
5458 /* Set PLL lock range. */
5459 tg3_writephy(tp, 0x16, 0x8007);
5460
5461 /* SW reset */
5462 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5463
5464 /* Wait for reset to complete. */
5465 /* XXX schedule_timeout() ... */
5466 for (i = 0; i < 500; i++)
5467 udelay(10);
5468
5469 /* Config mode; select PMA/Ch 1 regs. */
5470 tg3_writephy(tp, 0x10, 0x8411);
5471
5472 /* Enable auto-lock and comdet, select txclk for tx. */
5473 tg3_writephy(tp, 0x11, 0x0a10);
5474
5475 tg3_writephy(tp, 0x18, 0x00a0);
5476 tg3_writephy(tp, 0x16, 0x41ff);
5477
5478 /* Assert and deassert POR. */
5479 tg3_writephy(tp, 0x13, 0x0400);
5480 udelay(40);
5481 tg3_writephy(tp, 0x13, 0x0000);
5482
5483 tg3_writephy(tp, 0x11, 0x0a50);
5484 udelay(40);
5485 tg3_writephy(tp, 0x11, 0x0a10);
5486
5487 /* Wait for signal to stabilize */
5488 /* XXX schedule_timeout() ... */
5489 for (i = 0; i < 15000; i++)
5490 udelay(10);
5491
5492 /* Deselect the channel register so we can read the PHYID
5493 * later.
5494 */
5495 tg3_writephy(tp, 0x10, 0x8011);
5496}
5497
953c96e0 5498static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5499{
82cd3d11 5500 u16 flowctrl;
953c96e0 5501 bool current_link_up;
1da177e4
LT		 5502 u32 sg_dig_ctrl, sg_dig_status;
5503 u32 serdes_cfg, expected_sg_dig_ctrl;
5504 int workaround, port_a;
1da177e4
LT		 5505
5506 serdes_cfg = 0;
5507 expected_sg_dig_ctrl = 0;
5508 workaround = 0;
5509 port_a = 1;
953c96e0 5510 current_link_up = false;
1da177e4 5511
4153577a
JP		 5512 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5513 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5514 workaround = 1;
5515 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5516 port_a = 0;
5517
5518 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5519 /* preserve bits 20-23 for voltage regulator */
5520 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5521 }
5522
5523 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5524
5525 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5526 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5527 if (workaround) {
5528 u32 val = serdes_cfg;
5529
5530 if (port_a)
5531 val |= 0xc010000;
5532 else
5533 val |= 0x4010000;
5534 tw32_f(MAC_SERDES_CFG, val);
5535 }
c98f6e3b
MC		 5536
5537 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5538 }
5539 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5540 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5541 current_link_up = true;
1da177e4
LT		 5542 }
5543 goto out;
5544 }
5545
5546 /* Want auto-negotiation. */
c98f6e3b 5547 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5548
82cd3d11
MC		 5549 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5550 if (flowctrl & ADVERTISE_1000XPAUSE)
5551 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5552 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5553 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5554
5555 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5556 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5557 tp->serdes_counter &&
5558 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5559 MAC_STATUS_RCVD_CFG)) ==
5560 MAC_STATUS_PCS_SYNCED)) {
5561 tp->serdes_counter--;
953c96e0 5562 current_link_up = true;
3d3ebe74
MC		 5563 goto out;
5564 }
5565restart_autoneg:
1da177e4
LT		 5566 if (workaround)
5567 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5568 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5569 udelay(5);
5570 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5571
3d3ebe74 5572 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5573 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5574 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5575 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5576 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5577 mac_status = tr32(MAC_STATUS);
5578
c98f6e3b 5579 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5580 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5581 u32 local_adv = 0, remote_adv = 0;
5582
5583 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5584 local_adv |= ADVERTISE_1000XPAUSE;
5585 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5586 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5587
c98f6e3b 5588 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5589 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5590 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5591 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5592
859edb26
MC		 5593 tp->link_config.rmt_adv =
5594 mii_adv_to_ethtool_adv_x(remote_adv);
5595
1da177e4 5596 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5597 current_link_up = true;
3d3ebe74 5598 tp->serdes_counter = 0;
f07e9af3 5599 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5600 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5601 if (tp->serdes_counter)
5602 tp->serdes_counter--;
1da177e4
LT		 5603 else {
5604 if (workaround) {
5605 u32 val = serdes_cfg;
5606
5607 if (port_a)
5608 val |= 0xc010000;
5609 else
5610 val |= 0x4010000;
5611
5612 tw32_f(MAC_SERDES_CFG, val);
5613 }
5614
c98f6e3b 5615 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5616 udelay(40);
5617
5618 /* Link parallel detection - link is up */
5619 /* only if we have PCS_SYNC and not */
5620 /* receiving config code words */
5621 mac_status = tr32(MAC_STATUS);
5622 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5623 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5624 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5625 current_link_up = true;
f07e9af3
MC		 5626 tp->phy_flags |=
5627 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5628 tp->serdes_counter =
5629 SERDES_PARALLEL_DET_TIMEOUT;
5630 } else
5631 goto restart_autoneg;
1da177e4
LT		 5632 }
5633 }
3d3ebe74
MC		 5634 } else {
5635 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5636 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5637 }
5638
5639out:
5640 return current_link_up;
5641}
5642
953c96e0 5643static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5644{
953c96e0 5645 bool current_link_up = false;
1da177e4 5646
5cf64b8a 5647 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5648 goto out;
1da177e4
LT		 5649
5650 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5651 u32 txflags, rxflags;
1da177e4 5652 int i;
6aa20a22 5653
5be73b47
MC		 5654 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5655 u32 local_adv = 0, remote_adv = 0;
1da177e4 5656
5be73b47
MC		 5657 if (txflags & ANEG_CFG_PS1)
5658 local_adv |= ADVERTISE_1000XPAUSE;
5659 if (txflags & ANEG_CFG_PS2)
5660 local_adv |= ADVERTISE_1000XPSE_ASYM;
5661
5662 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5663 remote_adv |= LPA_1000XPAUSE;
5664 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5665 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5666
859edb26
MC		 5667 tp->link_config.rmt_adv =
5668 mii_adv_to_ethtool_adv_x(remote_adv);
5669
1da177e4
LT		 5670 tg3_setup_flow_control(tp, local_adv, remote_adv);
5671
953c96e0 5672 current_link_up = true;
1da177e4
LT		 5673 }
5674 for (i = 0; i < 30; i++) {
5675 udelay(20);
5676 tw32_f(MAC_STATUS,
5677 (MAC_STATUS_SYNC_CHANGED |
5678 MAC_STATUS_CFG_CHANGED));
5679 udelay(40);
5680 if ((tr32(MAC_STATUS) &
5681 (MAC_STATUS_SYNC_CHANGED |
5682 MAC_STATUS_CFG_CHANGED)) == 0)
5683 break;
5684 }
5685
5686 mac_status = tr32(MAC_STATUS);
953c96e0 5687 if (!current_link_up &&
1da177e4
LT		 5688 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5689 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5690 current_link_up = true;
1da177e4 5691 } else {
5be73b47
MC		 5692 tg3_setup_flow_control(tp, 0, 0);
5693
1da177e4 5694 /* Forcing 1000FD link up. */
953c96e0 5695 current_link_up = true;
1da177e4
LT		 5696
5697 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5698 udelay(40);
e8f3f6ca
MC		 5699
5700 tw32_f(MAC_MODE, tp->mac_mode);
5701 udelay(40);
1da177e4
LT		 5702 }
5703
5704out:
5705 return current_link_up;
5706}
5707
953c96e0 5708static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5709{
5710 u32 orig_pause_cfg;
5711 u16 orig_active_speed;
5712 u8 orig_active_duplex;
5713 u32 mac_status;
953c96e0 5714 bool current_link_up;
1da177e4
LT		 5715 int i;
5716
8d018621 5717 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5718 orig_active_speed = tp->link_config.active_speed;
5719 orig_active_duplex = tp->link_config.active_duplex;
5720
63c3a66f 5721 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5722 tp->link_up &&
63c3a66f 5723 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5724 mac_status = tr32(MAC_STATUS);
5725 mac_status &= (MAC_STATUS_PCS_SYNCED |
5726 MAC_STATUS_SIGNAL_DET |
5727 MAC_STATUS_CFG_CHANGED |
5728 MAC_STATUS_RCVD_CFG);
5729 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5730 MAC_STATUS_SIGNAL_DET)) {
5731 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5732 MAC_STATUS_CFG_CHANGED));
5733 return 0;
5734 }
5735 }
5736
5737 tw32_f(MAC_TX_AUTO_NEG, 0);
5738
5739 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5740 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5741 tw32_f(MAC_MODE, tp->mac_mode);
5742 udelay(40);
5743
79eb6904 5744 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5745 tg3_init_bcm8002(tp);
5746
5747 /* Enable link change event even when serdes polling. */
5748 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5749 udelay(40);
5750
953c96e0 5751 current_link_up = false;
859edb26 5752 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5753 mac_status = tr32(MAC_STATUS);
5754
63c3a66f 5755 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5756 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5757 else
5758 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5759
898a56f8 5760 tp->napi[0].hw_status->status =
1da177e4 5761 (SD_STATUS_UPDATED |
898a56f8 5762 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5763
5764 for (i = 0; i < 100; i++) {
5765 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5766 MAC_STATUS_CFG_CHANGED));
5767 udelay(5);
5768 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5769 MAC_STATUS_CFG_CHANGED |
5770 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5771 break;
5772 }
5773
5774 mac_status = tr32(MAC_STATUS);
5775 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5776 current_link_up = false;
3d3ebe74
MC		 5777 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5778 tp->serdes_counter == 0) {
1da177e4
LT		 5779 tw32_f(MAC_MODE, (tp->mac_mode |
5780 MAC_MODE_SEND_CONFIGS));
5781 udelay(1);
5782 tw32_f(MAC_MODE, tp->mac_mode);
5783 }
5784 }
5785
953c96e0 5786 if (current_link_up) {
1da177e4
LT		 5787 tp->link_config.active_speed = SPEED_1000;
5788 tp->link_config.active_duplex = DUPLEX_FULL;
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_1000MBPS_ON));
5792 } else {
e740522e
MC		 5793 tp->link_config.active_speed = SPEED_UNKNOWN;
5794 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5795 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5796 LED_CTRL_LNKLED_OVERRIDE |
5797 LED_CTRL_TRAFFIC_OVERRIDE));
5798 }
5799
f4a46d1f 5800 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5801 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5802 if (orig_pause_cfg != now_pause_cfg ||
5803 orig_active_speed != tp->link_config.active_speed ||
5804 orig_active_duplex != tp->link_config.active_duplex)
5805 tg3_link_report(tp);
5806 }
5807
5808 return 0;
5809}
5810
953c96e0 5811static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5812{
953c96e0 5813 int err = 0;
747e8f8b 5814 u32 bmsr, bmcr;
85730a63
MC		 5815 u16 current_speed = SPEED_UNKNOWN;
5816 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5817 bool current_link_up = false;
85730a63
MC		 5818 u32 local_adv, remote_adv, sgsr;
5819
5820 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5821 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5822 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5823 (sgsr & SERDES_TG3_SGMII_MODE)) {
5824
5825 if (force_reset)
5826 tg3_phy_reset(tp);
5827
5828 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5829
5830 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5831 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5832 } else {
953c96e0 5833 current_link_up = true;
85730a63
MC		 5834 if (sgsr & SERDES_TG3_SPEED_1000) {
5835 current_speed = SPEED_1000;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5837 } else if (sgsr & SERDES_TG3_SPEED_100) {
5838 current_speed = SPEED_100;
5839 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5840 } else {
5841 current_speed = SPEED_10;
5842 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5843 }
5844
5845 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5846 current_duplex = DUPLEX_FULL;
5847 else
5848 current_duplex = DUPLEX_HALF;
5849 }
5850
5851 tw32_f(MAC_MODE, tp->mac_mode);
5852 udelay(40);
5853
5854 tg3_clear_mac_status(tp);
5855
5856 goto fiber_setup_done;
5857 }
747e8f8b
MC		 5858
5859 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5860 tw32_f(MAC_MODE, tp->mac_mode);
5861 udelay(40);
5862
3310e248 5863 tg3_clear_mac_status(tp);
747e8f8b
MC		 5864
5865 if (force_reset)
5866 tg3_phy_reset(tp);
5867
859edb26 5868 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5869
5870 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5871 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5872 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5873 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5874 bmsr |= BMSR_LSTATUS;
5875 else
5876 bmsr &= ~BMSR_LSTATUS;
5877 }
747e8f8b
MC		 5878
5879 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5880
5881 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5882 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5883 /* do nothing, just check for link up at the end */
5884 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5885 u32 adv, newadv;
747e8f8b
MC		 5886
5887 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5888 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5889 ADVERTISE_1000XPAUSE |
5890 ADVERTISE_1000XPSE_ASYM |
5891 ADVERTISE_SLCT);
747e8f8b 5892
28011cf1 5893 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5894 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5895
28011cf1
MC		 5896 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5897 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5898 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5899 tg3_writephy(tp, MII_BMCR, bmcr);
5900
5901 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5902 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5903 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5904
5905 return err;
5906 }
5907 } else {
5908 u32 new_bmcr;
5909
5910 bmcr &= ~BMCR_SPEED1000;
5911 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5912
5913 if (tp->link_config.duplex == DUPLEX_FULL)
5914 new_bmcr |= BMCR_FULLDPLX;
5915
5916 if (new_bmcr != bmcr) {
5917 /* BMCR_SPEED1000 is a reserved bit that needs
5918 * to be set on write.
5919 */
5920 new_bmcr |= BMCR_SPEED1000;
5921
5922 /* Force a linkdown */
f4a46d1f 5923 if (tp->link_up) {
747e8f8b
MC		 5924 u32 adv;
5925
5926 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5927 adv &= ~(ADVERTISE_1000XFULL |
5928 ADVERTISE_1000XHALF |
5929 ADVERTISE_SLCT);
5930 tg3_writephy(tp, MII_ADVERTISE, adv);
5931 tg3_writephy(tp, MII_BMCR, bmcr |
5932 BMCR_ANRESTART |
5933 BMCR_ANENABLE);
5934 udelay(10);
f4a46d1f 5935 tg3_carrier_off(tp);
747e8f8b
MC		 5936 }
5937 tg3_writephy(tp, MII_BMCR, new_bmcr);
5938 bmcr = new_bmcr;
5939 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5940 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5941 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5942 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5943 bmsr |= BMSR_LSTATUS;
5944 else
5945 bmsr &= ~BMSR_LSTATUS;
5946 }
f07e9af3 5947 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5948 }
5949 }
5950
5951 if (bmsr & BMSR_LSTATUS) {
5952 current_speed = SPEED_1000;
953c96e0 5953 current_link_up = true;
747e8f8b
MC		 5954 if (bmcr & BMCR_FULLDPLX)
5955 current_duplex = DUPLEX_FULL;
5956 else
5957 current_duplex = DUPLEX_HALF;
5958
ef167e27
MC		 5959 local_adv = 0;
5960 remote_adv = 0;
5961
747e8f8b 5962 if (bmcr & BMCR_ANENABLE) {
ef167e27 5963 u32 common;
747e8f8b
MC		 5964
5965 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5966 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5967 common = local_adv & remote_adv;
5968 if (common & (ADVERTISE_1000XHALF |
5969 ADVERTISE_1000XFULL)) {
5970 if (common & ADVERTISE_1000XFULL)
5971 current_duplex = DUPLEX_FULL;
5972 else
5973 current_duplex = DUPLEX_HALF;
859edb26
MC		 5974
5975 tp->link_config.rmt_adv =
5976 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5977 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5978 /* Link is up via parallel detect */
859a5887 5979 } else {
953c96e0 5980 current_link_up = false;
859a5887 5981 }
747e8f8b
MC		 5982 }
5983 }
5984
85730a63 5985fiber_setup_done:
953c96e0 5986 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5987 tg3_setup_flow_control(tp, local_adv, remote_adv);
5988
747e8f8b
MC		 5989 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5990 if (tp->link_config.active_duplex == DUPLEX_HALF)
5991 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5992
5993 tw32_f(MAC_MODE, tp->mac_mode);
5994 udelay(40);
5995
5996 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5997
5998 tp->link_config.active_speed = current_speed;
5999 tp->link_config.active_duplex = current_duplex;
6000
f4a46d1f 6001 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 6002 return err;
6003}
6004
6005static void tg3_serdes_parallel_detect(struct tg3 *tp)
6006{
3d3ebe74 6007 if (tp->serdes_counter) {
747e8f8b 6008 /* Give autoneg time to complete. */
3d3ebe74 6009 tp->serdes_counter--;
747e8f8b
MC		 6010 return;
6011 }
c6cdf436 6012
f4a46d1f 6013 if (!tp->link_up &&
747e8f8b
MC		 6014 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6015 u32 bmcr;
6016
6017 tg3_readphy(tp, MII_BMCR, &bmcr);
6018 if (bmcr & BMCR_ANENABLE) {
6019 u32 phy1, phy2;
6020
6021 /* Select shadow register 0x1f */
f08aa1a8
MC		 6022 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6023 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 6024
6025 /* Select expansion interrupt status register */
f08aa1a8
MC		 6026 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6027 MII_TG3_DSP_EXP1_INT_STAT);
6028 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6029 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6030
6031 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6032 /* We have signal detect and not receiving
6033 * config code words, link is up by parallel
6034 * detection.
6035 */
6036
6037 bmcr &= ~BMCR_ANENABLE;
6038 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6039 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6040 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6041 }
6042 }
f4a46d1f 6043 } else if (tp->link_up &&
859a5887 6044 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6045 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6046 u32 phy2;
6047
6048 /* Select expansion interrupt status register */
f08aa1a8
MC		 6049 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6050 MII_TG3_DSP_EXP1_INT_STAT);
6051 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6052 if (phy2 & 0x20) {
6053 u32 bmcr;
6054
6055 /* Config code words received, turn on autoneg. */
6056 tg3_readphy(tp, MII_BMCR, &bmcr);
6057 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6058
f07e9af3 6059 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6060
6061 }
6062 }
6063}
6064
953c96e0 6065static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6066{
f2096f94 6067 u32 val;
1da177e4
LT		 6068 int err;
6069
f07e9af3 6070 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6071 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6072 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6073 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6074 else
1da177e4 6075 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6076
4153577a 6077 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6078 u32 scale;
aa6c91fe
MC		 6079
6080 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6081 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6082 scale = 65;
6083 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6084 scale = 6;
6085 else
6086 scale = 12;
6087
6088 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6089 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6090 tw32(GRC_MISC_CFG, val);
6091 }
6092
f2096f94
MC		 6093 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6094 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6095 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6096 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6097 val |= tr32(MAC_TX_LENGTHS) &
6098 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6099 TX_LENGTHS_CNT_DWN_VAL_MSK);
6100
1da177e4
LT		 6101 if (tp->link_config.active_speed == SPEED_1000 &&
6102 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6103 tw32(MAC_TX_LENGTHS, val |
6104 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6105 else
f2096f94
MC		 6106 tw32(MAC_TX_LENGTHS, val |
6107 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6108
63c3a66f 6109 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6110 if (tp->link_up) {
1da177e4 6111 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6112 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6113 } else {
6114 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6115 }
6116 }
6117
63c3a66f 6118 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6119 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6120 if (!tp->link_up)
8ed5d97e
MC		 6121 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6122 tp->pwrmgmt_thresh;
6123 else
6124 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6125 tw32(PCIE_PWR_MGMT_THRESH, val);
6126 }
6127
1da177e4
LT		 6128 return err;
6129}
6130
7d41e49a
MC		 6131/* tp->lock must be held */
6132static u64 tg3_refclk_read(struct tg3 *tp)
6133{
6134 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6135 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6136}
6137
be947307
MC		 6138/* tp->lock must be held */
6139static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6140{
92e6457d
NS		 6141 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6142
6143 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6144 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6145 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6146 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6147}
6148
7d41e49a
MC		 6149static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6150static inline void tg3_full_unlock(struct tg3 *tp);
6151static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6152{
6153 struct tg3 *tp = netdev_priv(dev);
6154
6155 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6156 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6157 SOF_TIMESTAMPING_SOFTWARE;
6158
6159 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6160 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6161 SOF_TIMESTAMPING_RX_HARDWARE |
6162 SOF_TIMESTAMPING_RAW_HARDWARE;
6163 }
7d41e49a
MC		 6164
6165 if (tp->ptp_clock)
6166 info->phc_index = ptp_clock_index(tp->ptp_clock);
6167 else
6168 info->phc_index = -1;
6169
6170 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6171
6172 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6173 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6174 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6175 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6176 return 0;
6177}
6178
6179static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6180{
6181 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6182 bool neg_adj = false;
6183 u32 correction = 0;
6184
6185 if (ppb < 0) {
6186 neg_adj = true;
6187 ppb = -ppb;
6188 }
6189
6190 /* Frequency adjustment is performed using hardware with a 24 bit
6191 * accumulator and a programmable correction value. On each clk, the
6192 * correction value gets added to the accumulator and when it
6193 * overflows, the time counter is incremented/decremented.
6194 *
6195 * So conversion from ppb to correction value is
6196 * ppb * (1 << 24) / 1000000000
6197 */
6198 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6199 TG3_EAV_REF_CLK_CORRECT_MASK;
6200
6201 tg3_full_lock(tp, 0);
6202
6203 if (correction)
6204 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6205 TG3_EAV_REF_CLK_CORRECT_EN |
6206 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6207 else
6208 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6209
6210 tg3_full_unlock(tp);
6211
6212 return 0;
6213}
6214
6215static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6216{
6217 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6218
6219 tg3_full_lock(tp, 0);
6220 tp->ptp_adjust += delta;
6221 tg3_full_unlock(tp);
6222
6223 return 0;
6224}
6225
6226static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6227{
6228 u64 ns;
6229 u32 remainder;
6230 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6231
6232 tg3_full_lock(tp, 0);
6233 ns = tg3_refclk_read(tp);
6234 ns += tp->ptp_adjust;
6235 tg3_full_unlock(tp);
6236
6237 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6238 ts->tv_nsec = remainder;
6239
6240 return 0;
6241}
6242
6243static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6244 const struct timespec *ts)
6245{
6246 u64 ns;
6247 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6248
6249 ns = timespec_to_ns(ts);
6250
6251 tg3_full_lock(tp, 0);
6252 tg3_refclk_write(tp, ns);
6253 tp->ptp_adjust = 0;
6254 tg3_full_unlock(tp);
6255
6256 return 0;
6257}
6258
6259static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6260 struct ptp_clock_request *rq, int on)
6261{
92e6457d
NS		 6262 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6263 u32 clock_ctl;
6264 int rval = 0;
6265
6266 switch (rq->type) {
6267 case PTP_CLK_REQ_PEROUT:
6268 if (rq->perout.index != 0)
6269 return -EINVAL;
6270
6271 tg3_full_lock(tp, 0);
6272 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6273 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6274
6275 if (on) {
6276 u64 nsec;
6277
6278 nsec = rq->perout.start.sec * 1000000000ULL +
6279 rq->perout.start.nsec;
6280
6281 if (rq->perout.period.sec || rq->perout.period.nsec) {
6282 netdev_warn(tp->dev,
6283 "Device supports only a one-shot timesync output, period must be 0\n");
6284 rval = -EINVAL;
6285 goto err_out;
6286 }
6287
6288 if (nsec & (1ULL << 63)) {
6289 netdev_warn(tp->dev,
6290 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6291 rval = -EINVAL;
6292 goto err_out;
6293 }
6294
6295 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6296 tw32(TG3_EAV_WATCHDOG0_MSB,
6297 TG3_EAV_WATCHDOG0_EN |
6298 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6299
6300 tw32(TG3_EAV_REF_CLCK_CTL,
6301 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6302 } else {
6303 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6304 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6305 }
6306
6307err_out:
6308 tg3_full_unlock(tp);
6309 return rval;
6310
6311 default:
6312 break;
6313 }
6314
7d41e49a
MC		 6315 return -EOPNOTSUPP;
6316}
6317
6318static const struct ptp_clock_info tg3_ptp_caps = {
6319 .owner = THIS_MODULE,
6320 .name = "tg3 clock",
6321 .max_adj = 250000000,
6322 .n_alarm = 0,
6323 .n_ext_ts = 0,
92e6457d 6324 .n_per_out = 1,
7d41e49a
MC		 6325 .pps = 0,
6326 .adjfreq = tg3_ptp_adjfreq,
6327 .adjtime = tg3_ptp_adjtime,
6328 .gettime = tg3_ptp_gettime,
6329 .settime = tg3_ptp_settime,
6330 .enable = tg3_ptp_enable,
6331};
6332
fb4ce8ad
MC		 6333static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6334 struct skb_shared_hwtstamps *timestamp)
6335{
6336 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6337 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6338 tp->ptp_adjust);
6339}
6340
be947307
MC		 6341/* tp->lock must be held */
6342static void tg3_ptp_init(struct tg3 *tp)
6343{
6344 if (!tg3_flag(tp, PTP_CAPABLE))
6345 return;
6346
6347 /* Initialize the hardware clock to the system time. */
6348 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6349 tp->ptp_adjust = 0;
7d41e49a 6350 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6351}
6352
6353/* tp->lock must be held */
6354static void tg3_ptp_resume(struct tg3 *tp)
6355{
6356 if (!tg3_flag(tp, PTP_CAPABLE))
6357 return;
6358
6359 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6360 tp->ptp_adjust = 0;
6361}
6362
6363static void tg3_ptp_fini(struct tg3 *tp)
6364{
6365 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6366 return;
6367
7d41e49a 6368 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6369 tp->ptp_clock = NULL;
6370 tp->ptp_adjust = 0;
6371}
6372
66cfd1bd
MC		 6373static inline int tg3_irq_sync(struct tg3 *tp)
6374{
6375 return tp->irq_sync;
6376}
6377
97bd8e49
MC		 6378static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6379{
6380 int i;
6381
6382 dst = (u32 *)((u8 *)dst + off);
6383 for (i = 0; i < len; i += sizeof(u32))
6384 *dst++ = tr32(off + i);
6385}
6386
6387static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6388{
6389 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6390 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6391 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6392 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6393 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6394 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6395 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6396 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6397 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6398 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6399 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6400 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6401 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6402 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6403 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6404 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6405 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6406 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6407 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6408
63c3a66f 6409 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6410 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6411
6412 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6413 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6414 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6415 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6416 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6417 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6418 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6419 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6420
63c3a66f 6421 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6422 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6423 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6424 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6425 }
6426
6427 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6428 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6429 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6430 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6431 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6432
63c3a66f 6433 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6434 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6435}
6436
6437static void tg3_dump_state(struct tg3 *tp)
6438{
6439 int i;
6440 u32 *regs;
6441
6442 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6443 if (!regs)
97bd8e49 6444 return;
97bd8e49 6445
63c3a66f 6446 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6447 /* Read up to but not including private PCI registers */
6448 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6449 regs[i / sizeof(u32)] = tr32(i);
6450 } else
6451 tg3_dump_legacy_regs(tp, regs);
6452
6453 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6454 if (!regs[i + 0] && !regs[i + 1] &&
6455 !regs[i + 2] && !regs[i + 3])
6456 continue;
6457
6458 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6459 i * 4,
6460 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6461 }
6462
6463 kfree(regs);
6464
6465 for (i = 0; i < tp->irq_cnt; i++) {
6466 struct tg3_napi *tnapi = &tp->napi[i];
6467
6468 /* SW status block */
6469 netdev_err(tp->dev,
6470 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6471 i,
6472 tnapi->hw_status->status,
6473 tnapi->hw_status->status_tag,
6474 tnapi->hw_status->rx_jumbo_consumer,
6475 tnapi->hw_status->rx_consumer,
6476 tnapi->hw_status->rx_mini_consumer,
6477 tnapi->hw_status->idx[0].rx_producer,
6478 tnapi->hw_status->idx[0].tx_consumer);
6479
6480 netdev_err(tp->dev,
6481 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6482 i,
6483 tnapi->last_tag, tnapi->last_irq_tag,
6484 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6485 tnapi->rx_rcb_ptr,
6486 tnapi->prodring.rx_std_prod_idx,
6487 tnapi->prodring.rx_std_cons_idx,
6488 tnapi->prodring.rx_jmb_prod_idx,
6489 tnapi->prodring.rx_jmb_cons_idx);
6490 }
6491}
6492
df3e6548
MC		 6493/* This is called whenever we suspect that the system chipset is re-
6494 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6495 * is bogus tx completions. We try to recover by setting the
6496 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6497 * in the workqueue.
6498 */
6499static void tg3_tx_recover(struct tg3 *tp)
6500{
63c3a66f 6501 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6502 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6503
5129c3a3
MC		 6504 netdev_warn(tp->dev,
6505 "The system may be re-ordering memory-mapped I/O "
6506 "cycles to the network device, attempting to recover. "
6507 "Please report the problem to the driver maintainer "
6508 "and include system chipset information.\n");
df3e6548 6509
63c3a66f 6510 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6511}
6512
f3f3f27e 6513static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6514{
f65aac16
MC		 6515 /* Tell compiler to fetch tx indices from memory. */
6516 barrier();
f3f3f27e
MC		 6517 return tnapi->tx_pending -
6518 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6519}
6520
1da177e4
LT		 6521/* Tigon3 never reports partial packet sends. So we do not
6522 * need special logic to handle SKBs that have not had all
6523 * of their frags sent yet, like SunGEM does.
6524 */
17375d25 6525static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6526{
17375d25 6527 struct tg3 *tp = tnapi->tp;
898a56f8 6528 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6529 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6530 struct netdev_queue *txq;
6531 int index = tnapi - tp->napi;
298376d3 6532 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6533
63c3a66f 6534 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6535 index--;
6536
6537 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6538
6539 while (sw_idx != hw_idx) {
df8944cf 6540 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6541 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6542 int i, tx_bug = 0;
6543
6544 if (unlikely(skb == NULL)) {
6545 tg3_tx_recover(tp);
6546 return;
6547 }
1da177e4 6548
fb4ce8ad
MC		 6549 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6550 struct skb_shared_hwtstamps timestamp;
6551 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6552 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6553
6554 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6555
6556 skb_tstamp_tx(skb, &timestamp);
6557 }
6558
f4188d8a 6559 pci_unmap_single(tp->pdev,
4e5e4f0d 6560 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6561 skb_headlen(skb),
6562 PCI_DMA_TODEVICE);
1da177e4
LT		 6563
6564 ri->skb = NULL;
6565
e01ee14d
MC		 6566 while (ri->fragmented) {
6567 ri->fragmented = false;
6568 sw_idx = NEXT_TX(sw_idx);
6569 ri = &tnapi->tx_buffers[sw_idx];
6570 }
6571
1da177e4
LT		 6572 sw_idx = NEXT_TX(sw_idx);
6573
6574 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6575 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6576 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6577 tx_bug = 1;
f4188d8a
AD		 6578
6579 pci_unmap_page(tp->pdev,
4e5e4f0d 6580 dma_unmap_addr(ri, mapping),
9e903e08 6581 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6582 PCI_DMA_TODEVICE);
e01ee14d
MC		 6583
6584 while (ri->fragmented) {
6585 ri->fragmented = false;
6586 sw_idx = NEXT_TX(sw_idx);
6587 ri = &tnapi->tx_buffers[sw_idx];
6588 }
6589
1da177e4
LT		 6590 sw_idx = NEXT_TX(sw_idx);
6591 }
6592
298376d3
TH		 6593 pkts_compl++;
6594 bytes_compl += skb->len;
6595
497a27b9 6596 dev_kfree_skb_any(skb);
df3e6548
MC		 6597
6598 if (unlikely(tx_bug)) {
6599 tg3_tx_recover(tp);
6600 return;
6601 }
1da177e4
LT		 6602 }
6603
5cb917bc 6604 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6605
f3f3f27e 6606 tnapi->tx_cons = sw_idx;
1da177e4 6607
1b2a7205
MC		 6608 /* Need to make the tx_cons update visible to tg3_start_xmit()
6609 * before checking for netif_queue_stopped(). Without the
6610 * memory barrier, there is a small possibility that tg3_start_xmit()
6611 * will miss it and cause the queue to be stopped forever.
6612 */
6613 smp_mb();
6614
fe5f5787 6615 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6616 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6617 __netif_tx_lock(txq, smp_processor_id());
6618 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6619 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6620 netif_tx_wake_queue(txq);
6621 __netif_tx_unlock(txq);
51b91468 6622 }
1da177e4
LT		 6623}
6624
8d4057a9
ED		 6625static void tg3_frag_free(bool is_frag, void *data)
6626{
6627 if (is_frag)
6628 put_page(virt_to_head_page(data));
6629 else
6630 kfree(data);
6631}
6632
9205fd9c 6633static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6634{
8d4057a9
ED		 6635 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6636 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6637
9205fd9c 6638 if (!ri->data)
2b2cdb65
MC		 6639 return;
6640
4e5e4f0d 6641 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6642 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6643 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6644 ri->data = NULL;
2b2cdb65
MC		 6645}
6646
8d4057a9 6647
1da177e4
LT		 6648/* Returns size of skb allocated or < 0 on error.
6649 *
6650 * We only need to fill in the address because the other members
6651 * of the RX descriptor are invariant, see tg3_init_rings.
6652 *
6653 * Note the purposeful assymetry of cpu vs. chip accesses. For
6654 * posting buffers we only dirty the first cache line of the RX
6655 * descriptor (containing the address). Whereas for the RX status
6656 * buffers the cpu only reads the last cacheline of the RX descriptor
6657 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6658 */
9205fd9c 6659static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6660 u32 opaque_key, u32 dest_idx_unmasked,
6661 unsigned int *frag_size)
1da177e4
LT		 6662{
6663 struct tg3_rx_buffer_desc *desc;
f94e290e 6664 struct ring_info *map;
9205fd9c 6665 u8 *data;
1da177e4 6666 dma_addr_t mapping;
9205fd9c 6667 int skb_size, data_size, dest_idx;
1da177e4 6668
1da177e4
LT		 6669 switch (opaque_key) {
6670 case RXD_OPAQUE_RING_STD:
2c49a44d 6671 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6672 desc = &tpr->rx_std[dest_idx];
6673 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6674 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6675 break;
6676
6677 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6678 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6679 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6680 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6681 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6682 break;
6683
6684 default:
6685 return -EINVAL;
855e1111 6686 }
1da177e4
LT		 6687
6688 /* Do not overwrite any of the map or rp information
6689 * until we are sure we can commit to a new buffer.
6690 *
6691 * Callers depend upon this behavior and assume that
6692 * we leave everything unchanged if we fail.
6693 */
9205fd9c
ED		 6694 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6695 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6696 if (skb_size <= PAGE_SIZE) {
6697 data = netdev_alloc_frag(skb_size);
6698 *frag_size = skb_size;
8d4057a9
ED		 6699 } else {
6700 data = kmalloc(skb_size, GFP_ATOMIC);
6701 *frag_size = 0;
6702 }
9205fd9c 6703 if (!data)
1da177e4
LT		 6704 return -ENOMEM;
6705
9205fd9c
ED		 6706 mapping = pci_map_single(tp->pdev,
6707 data + TG3_RX_OFFSET(tp),
6708 data_size,
1da177e4 6709 PCI_DMA_FROMDEVICE);
8d4057a9 6710 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6711 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6712 return -EIO;
6713 }
1da177e4 6714
9205fd9c 6715 map->data = data;
4e5e4f0d 6716 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6717
1da177e4
LT		 6718 desc->addr_hi = ((u64)mapping >> 32);
6719 desc->addr_lo = ((u64)mapping & 0xffffffff);
6720
9205fd9c 6721 return data_size;
1da177e4
LT		 6722}
6723
6724/* We only need to move over in the address because the other
6725 * members of the RX descriptor are invariant. See notes above
9205fd9c 6726 * tg3_alloc_rx_data for full details.
1da177e4 6727 */
a3896167
MC		 6728static void tg3_recycle_rx(struct tg3_napi *tnapi,
6729 struct tg3_rx_prodring_set *dpr,
6730 u32 opaque_key, int src_idx,
6731 u32 dest_idx_unmasked)
1da177e4 6732{
17375d25 6733 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6734 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6735 struct ring_info *src_map, *dest_map;
8fea32b9 6736 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6737 int dest_idx;
1da177e4
LT		 6738
6739 switch (opaque_key) {
6740 case RXD_OPAQUE_RING_STD:
2c49a44d 6741 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6742 dest_desc = &dpr->rx_std[dest_idx];
6743 dest_map = &dpr->rx_std_buffers[dest_idx];
6744 src_desc = &spr->rx_std[src_idx];
6745 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6746 break;
6747
6748 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6749 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6750 dest_desc = &dpr->rx_jmb[dest_idx].std;
6751 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6752 src_desc = &spr->rx_jmb[src_idx].std;
6753 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6754 break;
6755
6756 default:
6757 return;
855e1111 6758 }
1da177e4 6759
9205fd9c 6760 dest_map->data = src_map->data;
4e5e4f0d
FT		 6761 dma_unmap_addr_set(dest_map, mapping,
6762 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6763 dest_desc->addr_hi = src_desc->addr_hi;
6764 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6765
6766 /* Ensure that the update to the skb happens after the physical
6767 * addresses have been transferred to the new BD location.
6768 */
6769 smp_wmb();
6770
9205fd9c 6771 src_map->data = NULL;
1da177e4
LT		 6772}
6773
1da177e4
LT		 6774/* The RX ring scheme is composed of multiple rings which post fresh
6775 * buffers to the chip, and one special ring the chip uses to report
6776 * status back to the host.
6777 *
6778 * The special ring reports the status of received packets to the
6779 * host. The chip does not write into the original descriptor the
6780 * RX buffer was obtained from. The chip simply takes the original
6781 * descriptor as provided by the host, updates the status and length
6782 * field, then writes this into the next status ring entry.
6783 *
6784 * Each ring the host uses to post buffers to the chip is described
6785 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6786 * it is first placed into the on-chip ram. When the packet's length
6787 * is known, it walks down the TG3_BDINFO entries to select the ring.
6788 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6789 * which is within the range of the new packet's length is chosen.
6790 *
6791 * The "separate ring for rx status" scheme may sound queer, but it makes
6792 * sense from a cache coherency perspective. If only the host writes
6793 * to the buffer post rings, and only the chip writes to the rx status
6794 * rings, then cache lines never move beyond shared-modified state.
6795 * If both the host and chip were to write into the same ring, cache line
6796 * eviction could occur since both entities want it in an exclusive state.
6797 */
17375d25 6798static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6799{
17375d25 6800 struct tg3 *tp = tnapi->tp;
f92905de 6801 u32 work_mask, rx_std_posted = 0;
4361935a 6802 u32 std_prod_idx, jmb_prod_idx;
72334482 6803 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6804 u16 hw_idx;
1da177e4 6805 int received;
8fea32b9 6806 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6807
8d9d7cfc 6808 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6809 /*
6810 * We need to order the read of hw_idx and the read of
6811 * the opaque cookie.
6812 */
6813 rmb();
1da177e4
LT		 6814 work_mask = 0;
6815 received = 0;
4361935a
MC		 6816 std_prod_idx = tpr->rx_std_prod_idx;
6817 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6818 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6819 struct ring_info *ri;
72334482 6820 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6821 unsigned int len;
6822 struct sk_buff *skb;
6823 dma_addr_t dma_addr;
6824 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6825 u8 *data;
fb4ce8ad 6826 u64 tstamp = 0;
1da177e4
LT		 6827
6828 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6829 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6830 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6831 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6832 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6833 data = ri->data;
4361935a 6834 post_ptr = &std_prod_idx;
f92905de 6835 rx_std_posted++;
1da177e4 6836 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6837 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6838 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6839 data = ri->data;
4361935a 6840 post_ptr = &jmb_prod_idx;
21f581a5 6841 } else
1da177e4 6842 goto next_pkt_nopost;
1da177e4
LT		 6843
6844 work_mask |= opaque_key;
6845
d7b95315 6846 if (desc->err_vlan & RXD_ERR_MASK) {
1da177e4 6847 drop_it:
a3896167 6848 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6849 desc_idx, *post_ptr);
6850 drop_it_no_recycle:
6851 /* Other statistics kept track of by card. */
b0057c51 6852 tp->rx_dropped++;
1da177e4
LT		 6853 goto next_pkt;
6854 }
6855
9205fd9c 6856 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6857 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6858 ETH_FCS_LEN;
1da177e4 6859
fb4ce8ad
MC		 6860 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6861 RXD_FLAG_PTPSTAT_PTPV1 ||
6862 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6863 RXD_FLAG_PTPSTAT_PTPV2) {
6864 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6865 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6866 }
6867
d2757fc4 6868 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6869 int skb_size;
8d4057a9 6870 unsigned int frag_size;
1da177e4 6871
9205fd9c 6872 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6873 *post_ptr, &frag_size);
1da177e4
LT		 6874 if (skb_size < 0)
6875 goto drop_it;
6876
287be12e 6877 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6878 PCI_DMA_FROMDEVICE);
6879
9205fd9c 6880 /* Ensure that the update to the data happens
61e800cf
MC		 6881 * after the usage of the old DMA mapping.
6882 */
6883 smp_wmb();
6884
9205fd9c 6885 ri->data = NULL;
61e800cf 6886
85aec73d
IV		 6887 skb = build_skb(data, frag_size);
6888 if (!skb) {
6889 tg3_frag_free(frag_size != 0, data);
6890 goto drop_it_no_recycle;
6891 }
6892 skb_reserve(skb, TG3_RX_OFFSET(tp));
1da177e4 6893 } else {
a3896167 6894 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6895 desc_idx, *post_ptr);
6896
9205fd9c
ED		 6897 skb = netdev_alloc_skb(tp->dev,
6898 len + TG3_RAW_IP_ALIGN);
6899 if (skb == NULL)
1da177e4
LT		 6900 goto drop_it_no_recycle;
6901
9205fd9c 6902 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6903 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6904 memcpy(skb->data,
6905 data + TG3_RX_OFFSET(tp),
6906 len);
1da177e4 6907 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6908 }
6909
9205fd9c 6910 skb_put(skb, len);
fb4ce8ad
MC		 6911 if (tstamp)
6912 tg3_hwclock_to_timestamp(tp, tstamp,
6913 skb_hwtstamps(skb));
6914
dc668910 6915 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6916 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6917 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6918 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6919 skb->ip_summed = CHECKSUM_UNNECESSARY;
6920 else
bc8acf2c 6921 skb_checksum_none_assert(skb);
1da177e4
LT		 6922
6923 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6924
6925 if (len > (tp->dev->mtu + ETH_HLEN) &&
6926 skb->protocol != htons(ETH_P_8021Q)) {
497a27b9 6927 dev_kfree_skb_any(skb);
b0057c51 6928 goto drop_it_no_recycle;
f7b493e0
MC		 6929 }
6930
9dc7a113 6931 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6932 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6933 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6934 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6935
bf933c80 6936 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6937
1da177e4
LT		 6938 received++;
6939 budget--;
6940
6941next_pkt:
6942 (*post_ptr)++;
f92905de
MC		 6943
6944 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6945 tpr->rx_std_prod_idx = std_prod_idx &
6946 tp->rx_std_ring_mask;
86cfe4ff
MC		 6947 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6948 tpr->rx_std_prod_idx);
f92905de
MC		 6949 work_mask &= ~RXD_OPAQUE_RING_STD;
6950 rx_std_posted = 0;
6951 }
1da177e4 6952next_pkt_nopost:
483ba50b 6953 sw_idx++;
7cb32cf2 6954 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6955
6956 /* Refresh hw_idx to see if there is new work */
6957 if (sw_idx == hw_idx) {
8d9d7cfc 6958 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6959 rmb();
6960 }
1da177e4
LT		 6961 }
6962
6963 /* ACK the status ring. */
72334482
MC		 6964 tnapi->rx_rcb_ptr = sw_idx;
6965 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6966
6967 /* Refill RX ring(s). */
63c3a66f 6968 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6969 /* Sync BD data before updating mailbox */
6970 wmb();
6971
b196c7e4 6972 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6973 tpr->rx_std_prod_idx = std_prod_idx &
6974 tp->rx_std_ring_mask;
b196c7e4
MC		 6975 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6976 tpr->rx_std_prod_idx);
6977 }
6978 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6979 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6980 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6981 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6982 tpr->rx_jmb_prod_idx);
6983 }
6984 mmiowb();
6985 } else if (work_mask) {
6986 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6987 * updated before the producer indices can be updated.
6988 */
6989 smp_wmb();
6990
2c49a44d
MC		 6991 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6992 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6993
7ae52890
MC		 6994 if (tnapi != &tp->napi[1]) {
6995 tp->rx_refill = true;
e4af1af9 6996 napi_schedule(&tp->napi[1].napi);
7ae52890 6997 }
1da177e4 6998 }
1da177e4
LT		 6999
7000 return received;
7001}
7002
35f2d7d0 7003static void tg3_poll_link(struct tg3 *tp)
1da177e4 7004{
1da177e4 7005 /* handle link change and other phy events */
63c3a66f 7006 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 7007 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7008
1da177e4
LT		 7009 if (sblk->status & SD_STATUS_LINK_CHG) {
7010 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 7011 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 7012 spin_lock(&tp->lock);
63c3a66f 7013 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 7014 tw32_f(MAC_STATUS,
7015 (MAC_STATUS_SYNC_CHANGED |
7016 MAC_STATUS_CFG_CHANGED |
7017 MAC_STATUS_MI_COMPLETION |
7018 MAC_STATUS_LNKSTATE_CHANGED));
7019 udelay(40);
7020 } else
953c96e0 7021 tg3_setup_phy(tp, false);
f47c11ee 7022 spin_unlock(&tp->lock);
1da177e4
LT		 7023 }
7024 }
35f2d7d0
MC		 7025}
7026
f89f38b8
MC		 7027static int tg3_rx_prodring_xfer(struct tg3 *tp,
7028 struct tg3_rx_prodring_set *dpr,
7029 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7030{
7031 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7032 int i, err = 0;
b196c7e4
MC		 7033
7034 while (1) {
7035 src_prod_idx = spr->rx_std_prod_idx;
7036
7037 /* Make sure updates to the rx_std_buffers[] entries and the
7038 * standard producer index are seen in the correct order.
7039 */
7040 smp_rmb();
7041
7042 if (spr->rx_std_cons_idx == src_prod_idx)
7043 break;
7044
7045 if (spr->rx_std_cons_idx < src_prod_idx)
7046 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7047 else
2c49a44d
MC		 7048 cpycnt = tp->rx_std_ring_mask + 1 -
7049 spr->rx_std_cons_idx;
b196c7e4 7050
2c49a44d
MC		 7051 cpycnt = min(cpycnt,
7052 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7053
7054 si = spr->rx_std_cons_idx;
7055 di = dpr->rx_std_prod_idx;
7056
e92967bf 7057 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7058 if (dpr->rx_std_buffers[i].data) {
e92967bf 7059 cpycnt = i - di;
f89f38b8 7060 err = -ENOSPC;
e92967bf
MC		 7061 break;
7062 }
7063 }
7064
7065 if (!cpycnt)
7066 break;
7067
7068 /* Ensure that updates to the rx_std_buffers ring and the
7069 * shadowed hardware producer ring from tg3_recycle_skb() are
7070 * ordered correctly WRT the skb check above.
7071 */
7072 smp_rmb();
7073
b196c7e4
MC		 7074 memcpy(&dpr->rx_std_buffers[di],
7075 &spr->rx_std_buffers[si],
7076 cpycnt * sizeof(struct ring_info));
7077
7078 for (i = 0; i < cpycnt; i++, di++, si++) {
7079 struct tg3_rx_buffer_desc *sbd, *dbd;
7080 sbd = &spr->rx_std[si];
7081 dbd = &dpr->rx_std[di];
7082 dbd->addr_hi = sbd->addr_hi;
7083 dbd->addr_lo = sbd->addr_lo;
7084 }
7085
2c49a44d
MC		 7086 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7087 tp->rx_std_ring_mask;
7088 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7089 tp->rx_std_ring_mask;
b196c7e4
MC		 7090 }
7091
7092 while (1) {
7093 src_prod_idx = spr->rx_jmb_prod_idx;
7094
7095 /* Make sure updates to the rx_jmb_buffers[] entries and
7096 * the jumbo producer index are seen in the correct order.
7097 */
7098 smp_rmb();
7099
7100 if (spr->rx_jmb_cons_idx == src_prod_idx)
7101 break;
7102
7103 if (spr->rx_jmb_cons_idx < src_prod_idx)
7104 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7105 else
2c49a44d
MC		 7106 cpycnt = tp->rx_jmb_ring_mask + 1 -
7107 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7108
7109 cpycnt = min(cpycnt,
2c49a44d 7110 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7111
7112 si = spr->rx_jmb_cons_idx;
7113 di = dpr->rx_jmb_prod_idx;
7114
e92967bf 7115 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7116 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7117 cpycnt = i - di;
f89f38b8 7118 err = -ENOSPC;
e92967bf
MC		 7119 break;
7120 }
7121 }
7122
7123 if (!cpycnt)
7124 break;
7125
7126 /* Ensure that updates to the rx_jmb_buffers ring and the
7127 * shadowed hardware producer ring from tg3_recycle_skb() are
7128 * ordered correctly WRT the skb check above.
7129 */
7130 smp_rmb();
7131
b196c7e4
MC		 7132 memcpy(&dpr->rx_jmb_buffers[di],
7133 &spr->rx_jmb_buffers[si],
7134 cpycnt * sizeof(struct ring_info));
7135
7136 for (i = 0; i < cpycnt; i++, di++, si++) {
7137 struct tg3_rx_buffer_desc *sbd, *dbd;
7138 sbd = &spr->rx_jmb[si].std;
7139 dbd = &dpr->rx_jmb[di].std;
7140 dbd->addr_hi = sbd->addr_hi;
7141 dbd->addr_lo = sbd->addr_lo;
7142 }
7143
2c49a44d
MC		 7144 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7145 tp->rx_jmb_ring_mask;
7146 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7147 tp->rx_jmb_ring_mask;
b196c7e4 7148 }
f89f38b8
MC		 7149
7150 return err;
b196c7e4
MC		 7151}
7152
35f2d7d0
MC		 7153static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7154{
7155 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7156
7157 /* run TX completion thread */
f3f3f27e 7158 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7159 tg3_tx(tnapi);
63c3a66f 7160 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7161 return work_done;
1da177e4
LT		 7162 }
7163
f891ea16
MC		 7164 if (!tnapi->rx_rcb_prod_idx)
7165 return work_done;
7166
1da177e4
LT		 7167 /* run RX thread, within the bounds set by NAPI.
7168 * All RX "locking" is done by ensuring outside
bea3348e 7169 * code synchronizes with tg3->napi.poll()
1da177e4 7170 */
8d9d7cfc 7171 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7172 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7173
63c3a66f 7174 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7175 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7176 int i, err = 0;
e4af1af9
MC		 7177 u32 std_prod_idx = dpr->rx_std_prod_idx;
7178 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7179
7ae52890 7180 tp->rx_refill = false;
9102426a 7181 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7182 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7183 &tp->napi[i].prodring);
b196c7e4
MC		 7184
7185 wmb();
7186
e4af1af9
MC		 7187 if (std_prod_idx != dpr->rx_std_prod_idx)
7188 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7189 dpr->rx_std_prod_idx);
b196c7e4 7190
e4af1af9
MC		 7191 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7192 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7193 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7194
7195 mmiowb();
f89f38b8
MC		 7196
7197 if (err)
7198 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7199 }
7200
6f535763
DM		 7201 return work_done;
7202}
7203
db219973
MC		 7204static inline void tg3_reset_task_schedule(struct tg3 *tp)
7205{
7206 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7207 schedule_work(&tp->reset_task);
7208}
7209
7210static inline void tg3_reset_task_cancel(struct tg3 *tp)
7211{
7212 cancel_work_sync(&tp->reset_task);
7213 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7214 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7215}
7216
35f2d7d0
MC		 7217static int tg3_poll_msix(struct napi_struct *napi, int budget)
7218{
7219 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7220 struct tg3 *tp = tnapi->tp;
7221 int work_done = 0;
7222 struct tg3_hw_status *sblk = tnapi->hw_status;
7223
7224 while (1) {
7225 work_done = tg3_poll_work(tnapi, work_done, budget);
7226
63c3a66f 7227 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7228 goto tx_recovery;
7229
7230 if (unlikely(work_done >= budget))
7231 break;
7232
c6cdf436 7233 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7234 * to tell the hw how much work has been processed,
7235 * so we must read it before checking for more work.
7236 */
7237 tnapi->last_tag = sblk->status_tag;
7238 tnapi->last_irq_tag = tnapi->last_tag;
7239 rmb();
7240
7241 /* check for RX/TX work to do */
6d40db7b
MC		 7242 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7243 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7244
7245 /* This test here is not race free, but will reduce
7246 * the number of interrupts by looping again.
7247 */
7248 if (tnapi == &tp->napi[1] && tp->rx_refill)
7249 continue;
7250
35f2d7d0
MC		 7251 napi_complete(napi);
7252 /* Reenable interrupts. */
7253 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7254
7255 /* This test here is synchronized by napi_schedule()
7256 * and napi_complete() to close the race condition.
7257 */
7258 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7259 tw32(HOSTCC_MODE, tp->coalesce_mode |
7260 HOSTCC_MODE_ENABLE |
7261 tnapi->coal_now);
7262 }
35f2d7d0
MC		 7263 mmiowb();
7264 break;
7265 }
7266 }
7267
7268 return work_done;
7269
7270tx_recovery:
7271 /* work_done is guaranteed to be less than budget. */
7272 napi_complete(napi);
db219973 7273 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7274 return work_done;
7275}
7276
e64de4e6
MC		 7277static void tg3_process_error(struct tg3 *tp)
7278{
7279 u32 val;
7280 bool real_error = false;
7281
63c3a66f 7282 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7283 return;
7284
7285 /* Check Flow Attention register */
7286 val = tr32(HOSTCC_FLOW_ATTN);
7287 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7288 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7289 real_error = true;
7290 }
7291
7292 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7293 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7294 real_error = true;
7295 }
7296
7297 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7298 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7299 real_error = true;
7300 }
7301
7302 if (!real_error)
7303 return;
7304
7305 tg3_dump_state(tp);
7306
63c3a66f 7307 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7308 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7309}
7310
6f535763
DM		 7311static int tg3_poll(struct napi_struct *napi, int budget)
7312{
8ef0442f
MC		 7313 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7314 struct tg3 *tp = tnapi->tp;
6f535763 7315 int work_done = 0;
898a56f8 7316 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7317
7318 while (1) {
e64de4e6
MC		 7319 if (sblk->status & SD_STATUS_ERROR)
7320 tg3_process_error(tp);
7321
35f2d7d0
MC		 7322 tg3_poll_link(tp);
7323
17375d25 7324 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7325
63c3a66f 7326 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7327 goto tx_recovery;
7328
7329 if (unlikely(work_done >= budget))
7330 break;
7331
63c3a66f 7332 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7333 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7334 * to tell the hw how much work has been processed,
7335 * so we must read it before checking for more work.
7336 */
898a56f8
MC		 7337 tnapi->last_tag = sblk->status_tag;
7338 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7339 rmb();
7340 } else
7341 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7342
17375d25 7343 if (likely(!tg3_has_work(tnapi))) {
288379f0 7344 napi_complete(napi);
17375d25 7345 tg3_int_reenable(tnapi);
6f535763
DM		 7346 break;
7347 }
1da177e4
LT		 7348 }
7349
bea3348e 7350 return work_done;
6f535763
DM		 7351
7352tx_recovery:
4fd7ab59 7353 /* work_done is guaranteed to be less than budget. */
288379f0 7354 napi_complete(napi);
db219973 7355 tg3_reset_task_schedule(tp);
4fd7ab59 7356 return work_done;
1da177e4
LT		 7357}
7358
66cfd1bd
MC		 7359static void tg3_napi_disable(struct tg3 *tp)
7360{
7361 int i;
7362
7363 for (i = tp->irq_cnt - 1; i >= 0; i--)
7364 napi_disable(&tp->napi[i].napi);
7365}
7366
7367static void tg3_napi_enable(struct tg3 *tp)
7368{
7369 int i;
7370
7371 for (i = 0; i < tp->irq_cnt; i++)
7372 napi_enable(&tp->napi[i].napi);
7373}
7374
7375static void tg3_napi_init(struct tg3 *tp)
7376{
7377 int i;
7378
7379 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7380 for (i = 1; i < tp->irq_cnt; i++)
7381 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7382}
7383
7384static void tg3_napi_fini(struct tg3 *tp)
7385{
7386 int i;
7387
7388 for (i = 0; i < tp->irq_cnt; i++)
7389 netif_napi_del(&tp->napi[i].napi);
7390}
7391
7392static inline void tg3_netif_stop(struct tg3 *tp)
7393{
7394 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7395 tg3_napi_disable(tp);
f4a46d1f 7396 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7397 netif_tx_disable(tp->dev);
7398}
7399
35763066 7400/* tp->lock must be held */
66cfd1bd
MC		 7401static inline void tg3_netif_start(struct tg3 *tp)
7402{
be947307
MC		 7403 tg3_ptp_resume(tp);
7404
66cfd1bd
MC		 7405 /* NOTE: unconditional netif_tx_wake_all_queues is only
7406 * appropriate so long as all callers are assured to
7407 * have free tx slots (such as after tg3_init_hw)
7408 */
7409 netif_tx_wake_all_queues(tp->dev);
7410
f4a46d1f
NNS		 7411 if (tp->link_up)
7412 netif_carrier_on(tp->dev);
7413
66cfd1bd
MC		 7414 tg3_napi_enable(tp);
7415 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7416 tg3_enable_ints(tp);
7417}
7418
f47c11ee
DM		 7419static void tg3_irq_quiesce(struct tg3 *tp)
7420{
4f125f42
MC		 7421 int i;
7422
f47c11ee
DM		 7423 BUG_ON(tp->irq_sync);
7424
7425 tp->irq_sync = 1;
7426 smp_mb();
7427
4f125f42
MC		 7428 for (i = 0; i < tp->irq_cnt; i++)
7429 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7430}
7431
f47c11ee
DM		 7432/* Fully shutdown all tg3 driver activity elsewhere in the system.
7433 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7434 * with as well. Most of the time, this is not necessary except when
7435 * shutting down the device.
7436 */
7437static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7438{
46966545 7439 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7440 if (irq_sync)
7441 tg3_irq_quiesce(tp);
f47c11ee
DM		 7442}
7443
7444static inline void tg3_full_unlock(struct tg3 *tp)
7445{
f47c11ee
DM		 7446 spin_unlock_bh(&tp->lock);
7447}
7448
fcfa0a32
MC		 7449/* One-shot MSI handler - Chip automatically disables interrupt
7450 * after sending MSI so driver doesn't have to do it.
7451 */
7d12e780 7452static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7453{
09943a18
MC		 7454 struct tg3_napi *tnapi = dev_id;
7455 struct tg3 *tp = tnapi->tp;
fcfa0a32 7456
898a56f8 7457 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7458 if (tnapi->rx_rcb)
7459 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7460
7461 if (likely(!tg3_irq_sync(tp)))
09943a18 7462 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7463
7464 return IRQ_HANDLED;
7465}
7466
88b06bc2
MC		 7467/* MSI ISR - No need to check for interrupt sharing and no need to
7468 * flush status block and interrupt mailbox. PCI ordering rules
7469 * guarantee that MSI will arrive after the status block.
7470 */
7d12e780 7471static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7472{
09943a18
MC		 7473 struct tg3_napi *tnapi = dev_id;
7474 struct tg3 *tp = tnapi->tp;
88b06bc2 7475
898a56f8 7476 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7477 if (tnapi->rx_rcb)
7478 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7479 /*
fac9b83e 7480 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7481 * chip-internal interrupt pending events.
fac9b83e 7482 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7483 * NIC to stop sending us irqs, engaging "in-intr-handler"
7484 * event coalescing.
7485 */
5b39de91 7486 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7487 if (likely(!tg3_irq_sync(tp)))
09943a18 7488 napi_schedule(&tnapi->napi);
61487480 7489
88b06bc2
MC		 7490 return IRQ_RETVAL(1);
7491}
7492
7d12e780 7493static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7494{
09943a18
MC		 7495 struct tg3_napi *tnapi = dev_id;
7496 struct tg3 *tp = tnapi->tp;
898a56f8 7497 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7498 unsigned int handled = 1;
7499
1da177e4
LT		 7500 /* In INTx mode, it is possible for the interrupt to arrive at
7501 * the CPU before the status block posted prior to the interrupt.
7502 * Reading the PCI State register will confirm whether the
7503 * interrupt is ours and will flush the status block.
7504 */
d18edcb2 7505 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7506 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7507 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7508 handled = 0;
f47c11ee 7509 goto out;
fac9b83e 7510 }
d18edcb2
MC		 7511 }
7512
7513 /*
7514 * Writing any value to intr-mbox-0 clears PCI INTA# and
7515 * chip-internal interrupt pending events.
7516 * Writing non-zero to intr-mbox-0 additional tells the
7517 * NIC to stop sending us irqs, engaging "in-intr-handler"
7518 * event coalescing.
c04cb347
MC		 7519 *
7520 * Flush the mailbox to de-assert the IRQ immediately to prevent
7521 * spurious interrupts. The flush impacts performance but
7522 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7523 */
c04cb347 7524 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7525 if (tg3_irq_sync(tp))
7526 goto out;
7527 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7528 if (likely(tg3_has_work(tnapi))) {
72334482 7529 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7530 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7531 } else {
7532 /* No work, shared interrupt perhaps? re-enable
7533 * interrupts, and flush that PCI write
7534 */
7535 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7536 0x00000000);
fac9b83e 7537 }
f47c11ee 7538out:
fac9b83e
DM		 7539 return IRQ_RETVAL(handled);
7540}
7541
7d12e780 7542static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7543{
09943a18
MC		 7544 struct tg3_napi *tnapi = dev_id;
7545 struct tg3 *tp = tnapi->tp;
898a56f8 7546 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7547 unsigned int handled = 1;
7548
fac9b83e
DM		 7549 /* In INTx mode, it is possible for the interrupt to arrive at
7550 * the CPU before the status block posted prior to the interrupt.
7551 * Reading the PCI State register will confirm whether the
7552 * interrupt is ours and will flush the status block.
7553 */
898a56f8 7554 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7555 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7556 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7557 handled = 0;
f47c11ee 7558 goto out;
1da177e4 7559 }
d18edcb2
MC		 7560 }
7561
7562 /*
7563 * writing any value to intr-mbox-0 clears PCI INTA# and
7564 * chip-internal interrupt pending events.
7565 * writing non-zero to intr-mbox-0 additional tells the
7566 * NIC to stop sending us irqs, engaging "in-intr-handler"
7567 * event coalescing.
c04cb347
MC		 7568 *
7569 * Flush the mailbox to de-assert the IRQ immediately to prevent
7570 * spurious interrupts. The flush impacts performance but
7571 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7572 */
c04cb347 7573 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7574
7575 /*
7576 * In a shared interrupt configuration, sometimes other devices'
7577 * interrupts will scream. We record the current status tag here
7578 * so that the above check can report that the screaming interrupts
7579 * are unhandled. Eventually they will be silenced.
7580 */
898a56f8 7581 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7582
d18edcb2
MC		 7583 if (tg3_irq_sync(tp))
7584 goto out;
624f8e50 7585
72334482 7586 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7587
09943a18 7588 napi_schedule(&tnapi->napi);
624f8e50 7589
f47c11ee 7590out:
1da177e4
LT		 7591 return IRQ_RETVAL(handled);
7592}
7593
7938109f 7594/* ISR for interrupt test */
7d12e780 7595static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7596{
09943a18
MC		 7597 struct tg3_napi *tnapi = dev_id;
7598 struct tg3 *tp = tnapi->tp;
898a56f8 7599 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7600
f9804ddb
MC		 7601 if ((sblk->status & SD_STATUS_UPDATED) ||
7602 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7603 tg3_disable_ints(tp);
7938109f
MC		 7604 return IRQ_RETVAL(1);
7605 }
7606 return IRQ_RETVAL(0);
7607}
7608
1da177e4
LT		 7609#ifdef CONFIG_NET_POLL_CONTROLLER
7610static void tg3_poll_controller(struct net_device *dev)
7611{
4f125f42 7612 int i;
88b06bc2
MC		 7613 struct tg3 *tp = netdev_priv(dev);
7614
9c13cb8b
NNS		 7615 if (tg3_irq_sync(tp))
7616 return;
7617
4f125f42 7618 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7619 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7620}
7621#endif
7622
1da177e4
LT		 7623static void tg3_tx_timeout(struct net_device *dev)
7624{
7625 struct tg3 *tp = netdev_priv(dev);
7626
b0408751 7627 if (netif_msg_tx_err(tp)) {
05dbe005 7628 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7629 tg3_dump_state(tp);
b0408751 7630 }
1da177e4 7631
db219973 7632 tg3_reset_task_schedule(tp);
1da177e4
LT		 7633}
7634
c58ec932
MC		 7635/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7636static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7637{
7638 u32 base = (u32) mapping & 0xffffffff;
7639
37567910 7640 return base + len + 8 < base;
c58ec932
MC		 7641}
7642
0f0d1510
MC		 7643/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7644 * of any 4GB boundaries: 4G, 8G, etc
7645 */
7646static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7647 u32 len, u32 mss)
7648{
7649 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7650 u32 base = (u32) mapping & 0xffffffff;
7651
7652 return ((base + len + (mss & 0x3fff)) < base);
7653 }
7654 return 0;
7655}
7656
72f2afb8
MC		 7657/* Test for DMA addresses > 40-bit */
7658static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7659 int len)
7660{
7661#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7662 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7663 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7664 return 0;
7665#else
7666 return 0;
7667#endif
7668}
7669
d1a3b737 7670static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7671 dma_addr_t mapping, u32 len, u32 flags,
7672 u32 mss, u32 vlan)
2ffcc981 7673{
92cd3a17
MC		 7674 txbd->addr_hi = ((u64) mapping >> 32);
7675 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7676 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7677 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7678}
1da177e4 7679
84b67b27 7680static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7681 dma_addr_t map, u32 len, u32 flags,
7682 u32 mss, u32 vlan)
7683{
7684 struct tg3 *tp = tnapi->tp;
7685 bool hwbug = false;
7686
7687 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7688 hwbug = true;
d1a3b737
MC		 7689
7690 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7691 hwbug = true;
d1a3b737 7692
0f0d1510
MC		 7693 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7694 hwbug = true;
7695
d1a3b737 7696 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7697 hwbug = true;
d1a3b737 7698
a4cb428d 7699 if (tp->dma_limit) {
b9e45482 7700 u32 prvidx = *entry;
e31aa987 7701 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7702 while (len > tp->dma_limit && *budget) {
7703 u32 frag_len = tp->dma_limit;
7704 len -= tp->dma_limit;
e31aa987 7705
b9e45482
MC		 7706 /* Avoid the 8byte DMA problem */
7707 if (len <= 8) {
a4cb428d
MC		 7708 len += tp->dma_limit / 2;
7709 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7710 }
7711
b9e45482
MC		 7712 tnapi->tx_buffers[*entry].fragmented = true;
7713
7714 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7715 frag_len, tmp_flag, mss, vlan);
7716 *budget -= 1;
7717 prvidx = *entry;
7718 *entry = NEXT_TX(*entry);
7719
e31aa987
MC		 7720 map += frag_len;
7721 }
7722
7723 if (len) {
7724 if (*budget) {
7725 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7726 len, flags, mss, vlan);
b9e45482 7727 *budget -= 1;
e31aa987
MC		 7728 *entry = NEXT_TX(*entry);
7729 } else {
3db1cd5c 7730 hwbug = true;
b9e45482 7731 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7732 }
7733 }
7734 } else {
84b67b27
MC		 7735 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7736 len, flags, mss, vlan);
e31aa987
MC		 7737 *entry = NEXT_TX(*entry);
7738 }
d1a3b737
MC		 7739
7740 return hwbug;
7741}
7742
0d681b27 7743static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7744{
7745 int i;
0d681b27 7746 struct sk_buff *skb;
df8944cf 7747 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7748
0d681b27
MC		 7749 skb = txb->skb;
7750 txb->skb = NULL;
7751
432aa7ed
MC		 7752 pci_unmap_single(tnapi->tp->pdev,
7753 dma_unmap_addr(txb, mapping),
7754 skb_headlen(skb),
7755 PCI_DMA_TODEVICE);
e01ee14d
MC		 7756
7757 while (txb->fragmented) {
7758 txb->fragmented = false;
7759 entry = NEXT_TX(entry);
7760 txb = &tnapi->tx_buffers[entry];
7761 }
7762
ba1142e4 7763 for (i = 0; i <= last; i++) {
9e903e08 7764 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7765
7766 entry = NEXT_TX(entry);
7767 txb = &tnapi->tx_buffers[entry];
7768
7769 pci_unmap_page(tnapi->tp->pdev,
7770 dma_unmap_addr(txb, mapping),
9e903e08 7771 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7772
7773 while (txb->fragmented) {
7774 txb->fragmented = false;
7775 entry = NEXT_TX(entry);
7776 txb = &tnapi->tx_buffers[entry];
7777 }
432aa7ed
MC		 7778 }
7779}
7780
72f2afb8 7781/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7782static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7783 struct sk_buff **pskb,
84b67b27 7784 u32 *entry, u32 *budget,
92cd3a17 7785 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7786{
24f4efd4 7787 struct tg3 *tp = tnapi->tp;
f7ff1987 7788 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7789 dma_addr_t new_addr = 0;
432aa7ed 7790 int ret = 0;
1da177e4 7791
4153577a 7792 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7793 new_skb = skb_copy(skb, GFP_ATOMIC);
7794 else {
7795 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7796
7797 new_skb = skb_copy_expand(skb,
7798 skb_headroom(skb) + more_headroom,
7799 skb_tailroom(skb), GFP_ATOMIC);
7800 }
7801
1da177e4 7802 if (!new_skb) {
c58ec932
MC		 7803 ret = -1;
7804 } else {
7805 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7806 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7807 PCI_DMA_TODEVICE);
7808 /* Make sure the mapping succeeded */
7809 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
497a27b9 7810 dev_kfree_skb_any(new_skb);
c58ec932 7811 ret = -1;
c58ec932 7812 } else {
b9e45482
MC		 7813 u32 save_entry = *entry;
7814
92cd3a17
MC		 7815 base_flags |= TXD_FLAG_END;
7816
84b67b27
MC		 7817 tnapi->tx_buffers[*entry].skb = new_skb;
7818 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7819 mapping, new_addr);
7820
84b67b27 7821 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7822 new_skb->len, base_flags,
7823 mss, vlan)) {
ba1142e4 7824 tg3_tx_skb_unmap(tnapi, save_entry, -1);
497a27b9 7825 dev_kfree_skb_any(new_skb);
d1a3b737
MC		 7826 ret = -1;
7827 }
f4188d8a 7828 }
1da177e4
LT		 7829 }
7830
497a27b9 7831 dev_kfree_skb_any(skb);
f7ff1987 7832 *pskb = new_skb;
c58ec932 7833 return ret;
1da177e4
LT		 7834}
7835
2ffcc981 7836static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83
MC		 7837
7838/* Use GSO to workaround a rare TSO bug that may be triggered when the
7839 * TSO header is greater than 80 bytes.
7840 */
7841static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7842{
7843 struct sk_buff *segs, *nskb;
f3f3f27e 7844 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7845
7846 /* Estimate the number of fragments in the worst case */
f3f3f27e 7847 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 7848 netif_stop_queue(tp->dev);
f65aac16
MC		 7849
7850 /* netif_tx_stop_queue() must be done before checking
7851 * checking tx index in tg3_tx_avail() below, because in
7852 * tg3_tx(), we update tx index before checking for
7853 * netif_tx_queue_stopped().
7854 */
7855 smp_mb();
f3f3f27e 7856 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 7857 return NETDEV_TX_BUSY;
7858
7859 netif_wake_queue(tp->dev);
52c0fd83
MC		 7860 }
7861
7862 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 7863 if (IS_ERR(segs))
52c0fd83
MC		 7864 goto tg3_tso_bug_end;
7865
7866 do {
7867 nskb = segs;
7868 segs = segs->next;
7869 nskb->next = NULL;
2ffcc981 7870 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7871 } while (segs);
7872
7873tg3_tso_bug_end:
497a27b9 7874 dev_kfree_skb_any(skb);
52c0fd83
MC		 7875
7876 return NETDEV_TX_OK;
7877}
52c0fd83 7878
5a6f3074 7879/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
63c3a66f 7880 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5a6f3074 7881 */
2ffcc981 7882static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7883{
7884 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7885 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7886 u32 budget;
432aa7ed 7887 int i = -1, would_hit_hwbug;
90079ce8 7888 dma_addr_t mapping;
24f4efd4
MC		 7889 struct tg3_napi *tnapi;
7890 struct netdev_queue *txq;
432aa7ed 7891 unsigned int last;
f4188d8a 7892
24f4efd4
MC		 7893 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7894 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7895 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7896 tnapi++;
1da177e4 7897
84b67b27
MC		 7898 budget = tg3_tx_avail(tnapi);
7899
00b70504 7900 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7901 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7902 * interrupt. Furthermore, IRQ processing runs lockless so we have
7903 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7904 */
84b67b27 7905 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7906 if (!netif_tx_queue_stopped(txq)) {
7907 netif_tx_stop_queue(txq);
1f064a87
SH		 7908
7909 /* This is a hard error, log it. */
5129c3a3
MC		 7910 netdev_err(dev,
7911 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7912 }
1da177e4
LT		 7913 return NETDEV_TX_BUSY;
7914 }
7915
f3f3f27e 7916 entry = tnapi->tx_prod;
1da177e4 7917 base_flags = 0;
84fa7933 7918 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 7919 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 7920
be98da6a
MC		 7921 mss = skb_shinfo(skb)->gso_size;
7922 if (mss) {
eddc9ec5 7923 struct iphdr *iph;
34195c3d 7924 u32 tcp_opt_len, hdr_len;
1da177e4
LT		 7925
7926 if (skb_header_cloned(skb) &&
48855432
ED		 7927 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7928 goto drop;
1da177e4 7929
34195c3d 7930 iph = ip_hdr(skb);
ab6a5bb6 7931 tcp_opt_len = tcp_optlen(skb);
1da177e4 7932
a5a11955 7933 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7934
a5a11955 7935 if (!skb_is_gso_v6(skb)) {
34195c3d
MC		 7936 iph->check = 0;
7937 iph->tot_len = htons(mss + hdr_len);
7938 }
7939
52c0fd83 7940 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
63c3a66f 7941 tg3_flag(tp, TSO_BUG))
de6f31eb 7942 return tg3_tso_bug(tp, skb);
52c0fd83 7943
1da177e4
LT		 7944 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7945 TXD_FLAG_CPU_POST_DMA);
7946
63c3a66f
JP		 7947 if (tg3_flag(tp, HW_TSO_1) ||
7948 tg3_flag(tp, HW_TSO_2) ||
7949 tg3_flag(tp, HW_TSO_3)) {
aa8223c7 7950 tcp_hdr(skb)->check = 0;
1da177e4 7951 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 7952 } else
7953 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7954 iph->daddr, 0,
7955 IPPROTO_TCP,
7956 0);
1da177e4 7957
63c3a66f 7958 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7959 mss |= (hdr_len & 0xc) << 12;
7960 if (hdr_len & 0x10)
7961 base_flags |= 0x00000010;
7962 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7963 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7964 mss |= hdr_len << 9;
63c3a66f 7965 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7966 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7967 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7968 int tsflags;
7969
eddc9ec5 7970 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7971 mss |= (tsflags << 11);
7972 }
7973 } else {
eddc9ec5 7974 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7975 int tsflags;
7976
eddc9ec5 7977 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7978 base_flags |= tsflags << 12;
7979 }
7980 }
7981 }
bf933c80 7982
93a700a9
MC		 7983 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7984 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7985 base_flags |= TXD_FLAG_JMB_PKT;
7986
92cd3a17
MC		 7987 if (vlan_tx_tag_present(skb)) {
7988 base_flags |= TXD_FLAG_VLAN;
7989 vlan = vlan_tx_tag_get(skb);
7990 }
1da177e4 7991
fb4ce8ad
MC		 7992 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7993 tg3_flag(tp, TX_TSTAMP_EN)) {
7994 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7995 base_flags |= TXD_FLAG_HWTSTAMP;
7996 }
7997
f4188d8a
AD		 7998 len = skb_headlen(skb);
7999
8000 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 8001 if (pci_dma_mapping_error(tp->pdev, mapping))
8002 goto drop;
8003
90079ce8 8004
f3f3f27e 8005 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 8006 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 8007
8008 would_hit_hwbug = 0;
8009
63c3a66f 8010 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 8011 would_hit_hwbug = 1;
1da177e4 8012
84b67b27 8013 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 8014 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 8015 mss, vlan)) {
d1a3b737 8016 would_hit_hwbug = 1;
ba1142e4 8017 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 8018 u32 tmp_mss = mss;
8019
8020 if (!tg3_flag(tp, HW_TSO_1) &&
8021 !tg3_flag(tp, HW_TSO_2) &&
8022 !tg3_flag(tp, HW_TSO_3))
8023 tmp_mss = 0;
8024
c5665a53
MC		 8025 /* Now loop through additional data
8026 * fragments, and queue them.
8027 */
1da177e4
LT		 8028 last = skb_shinfo(skb)->nr_frags - 1;
8029 for (i = 0; i <= last; i++) {
8030 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8031
9e903e08 8032 len = skb_frag_size(frag);
dc234d0b 8033 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8034 len, DMA_TO_DEVICE);
1da177e4 8035
f3f3f27e 8036 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8037 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8038 mapping);
5d6bcdfe 8039 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8040 goto dma_error;
1da177e4 8041
b9e45482
MC		 8042 if (!budget ||
8043 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8044 len, base_flags |
8045 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8046 tmp_mss, vlan)) {
72f2afb8 8047 would_hit_hwbug = 1;
b9e45482
MC		 8048 break;
8049 }
1da177e4
LT		 8050 }
8051 }
8052
8053 if (would_hit_hwbug) {
0d681b27 8054 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4
LT		 8055
8056 /* If the workaround fails due to memory/mapping
8057 * failure, silently drop this packet.
8058 */
84b67b27
MC		 8059 entry = tnapi->tx_prod;
8060 budget = tg3_tx_avail(tnapi);
f7ff1987 8061 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8062 base_flags, mss, vlan))
48855432 8063 goto drop_nofree;
1da177e4
LT		 8064 }
8065
d515b450 8066 skb_tx_timestamp(skb);
5cb917bc 8067 netdev_tx_sent_queue(txq, skb->len);
d515b450 8068
6541b806
MC		 8069 /* Sync BD data before updating mailbox */
8070 wmb();
8071
1da177e4 8072 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 8073 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 8074
f3f3f27e
MC		 8075 tnapi->tx_prod = entry;
8076 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8077 netif_tx_stop_queue(txq);
f65aac16
MC		 8078
8079 /* netif_tx_stop_queue() must be done before checking
8080 * checking tx index in tg3_tx_avail() below, because in
8081 * tg3_tx(), we update tx index before checking for
8082 * netif_tx_queue_stopped().
8083 */
8084 smp_mb();
f3f3f27e 8085 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8086 netif_tx_wake_queue(txq);
51b91468 8087 }
1da177e4 8088
cdd0db05 8089 mmiowb();
1da177e4 8090 return NETDEV_TX_OK;
f4188d8a
AD		 8091
8092dma_error:
ba1142e4 8093 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8094 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432 8095drop:
497a27b9 8096 dev_kfree_skb_any(skb);
48855432
ED		 8097drop_nofree:
8098 tp->tx_dropped++;
f4188d8a 8099 return NETDEV_TX_OK;
1da177e4
LT		 8100}
8101
6e01b20b
MC		 8102static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8103{
8104 if (enable) {
8105 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8106 MAC_MODE_PORT_MODE_MASK);
8107
8108 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8109
8110 if (!tg3_flag(tp, 5705_PLUS))
8111 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8112
8113 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8114 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8115 else
8116 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8117 } else {
8118 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8119
8120 if (tg3_flag(tp, 5705_PLUS) ||
8121 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8122 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8123 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8124 }
8125
8126 tw32(MAC_MODE, tp->mac_mode);
8127 udelay(40);
8128}
8129
941ec90f 8130static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8131{
941ec90f 8132 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8133
8134 tg3_phy_toggle_apd(tp, false);
953c96e0 8135 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8136
941ec90f
MC		 8137 if (extlpbk && tg3_phy_set_extloopbk(tp))
8138 return -EIO;
8139
8140 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8141 switch (speed) {
8142 case SPEED_10:
8143 break;
8144 case SPEED_100:
8145 bmcr |= BMCR_SPEED100;
8146 break;
8147 case SPEED_1000:
8148 default:
8149 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8150 speed = SPEED_100;
8151 bmcr |= BMCR_SPEED100;
8152 } else {
8153 speed = SPEED_1000;
8154 bmcr |= BMCR_SPEED1000;
8155 }
8156 }
8157
941ec90f
MC		 8158 if (extlpbk) {
8159 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8160 tg3_readphy(tp, MII_CTRL1000, &val);
8161 val |= CTL1000_AS_MASTER |
8162 CTL1000_ENABLE_MASTER;
8163 tg3_writephy(tp, MII_CTRL1000, val);
8164 } else {
8165 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8166 MII_TG3_FET_PTEST_TRIM_2;
8167 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8168 }
8169 } else
8170 bmcr |= BMCR_LOOPBACK;
8171
5e5a7f37
MC		 8172 tg3_writephy(tp, MII_BMCR, bmcr);
8173
8174 /* The write needs to be flushed for the FETs */
8175 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8176 tg3_readphy(tp, MII_BMCR, &bmcr);
8177
8178 udelay(40);
8179
8180 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8181 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8182 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8183 MII_TG3_FET_PTEST_FRC_TX_LINK |
8184 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8185
8186 /* The write needs to be flushed for the AC131 */
8187 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8188 }
8189
8190 /* Reset to prevent losing 1st rx packet intermittently */
8191 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8192 tg3_flag(tp, 5780_CLASS)) {
8193 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8194 udelay(10);
8195 tw32_f(MAC_RX_MODE, tp->rx_mode);
8196 }
8197
8198 mac_mode = tp->mac_mode &
8199 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8200 if (speed == SPEED_1000)
8201 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8202 else
8203 mac_mode |= MAC_MODE_PORT_MODE_MII;
8204
4153577a 8205 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8206 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8207
8208 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8209 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8210 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8211 mac_mode |= MAC_MODE_LINK_POLARITY;
8212
8213 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8214 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8215 }
8216
8217 tw32(MAC_MODE, mac_mode);
8218 udelay(40);
941ec90f
MC		 8219
8220 return 0;
5e5a7f37
MC		 8221}
8222
c8f44aff 8223static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8224{
8225 struct tg3 *tp = netdev_priv(dev);
8226
8227 if (features & NETIF_F_LOOPBACK) {
8228 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8229 return;
8230
06c03c02 8231 spin_lock_bh(&tp->lock);
6e01b20b 8232 tg3_mac_loopback(tp, true);
06c03c02
MB		 8233 netif_carrier_on(tp->dev);
8234 spin_unlock_bh(&tp->lock);
8235 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8236 } else {
8237 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8238 return;
8239
06c03c02 8240 spin_lock_bh(&tp->lock);
6e01b20b 8241 tg3_mac_loopback(tp, false);
06c03c02 8242 /* Force link status check */
953c96e0 8243 tg3_setup_phy(tp, true);
06c03c02
MB		 8244 spin_unlock_bh(&tp->lock);
8245 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8246 }
8247}
8248
c8f44aff
MM		 8249static netdev_features_t tg3_fix_features(struct net_device *dev,
8250 netdev_features_t features)
dc668910
MM		 8251{
8252 struct tg3 *tp = netdev_priv(dev);
8253
63c3a66f 8254 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8255 features &= ~NETIF_F_ALL_TSO;
8256
8257 return features;
8258}
8259
c8f44aff 8260static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8261{
c8f44aff 8262 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8263
8264 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8265 tg3_set_loopback(dev, features);
8266
8267 return 0;
8268}
8269
21f581a5
MC		 8270static void tg3_rx_prodring_free(struct tg3 *tp,
8271 struct tg3_rx_prodring_set *tpr)
1da177e4 8272{
1da177e4
LT		 8273 int i;
8274
8fea32b9 8275 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8276 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8277 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8278 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8279 tp->rx_pkt_map_sz);
8280
63c3a66f 8281 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8282 for (i = tpr->rx_jmb_cons_idx;
8283 i != tpr->rx_jmb_prod_idx;
2c49a44d 8284 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8285 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8286 TG3_RX_JMB_MAP_SZ);
8287 }
8288 }
8289
2b2cdb65 8290 return;
b196c7e4 8291 }
1da177e4 8292
2c49a44d 8293 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8294 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8295 tp->rx_pkt_map_sz);
1da177e4 8296
63c3a66f 8297 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8298 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8299 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8300 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8301 }
8302}
8303
c6cdf436 8304/* Initialize rx rings for packet processing.
1da177e4
LT		 8305 *
8306 * The chip has been shut down and the driver detached from
8307 * the networking, so no interrupts or new tx packets will
8308 * end up in the driver. tp->{tx,}lock are held and thus
8309 * we may not sleep.
8310 */
21f581a5
MC		 8311static int tg3_rx_prodring_alloc(struct tg3 *tp,
8312 struct tg3_rx_prodring_set *tpr)
1da177e4 8313{
287be12e 8314 u32 i, rx_pkt_dma_sz;
1da177e4 8315
b196c7e4
MC		 8316 tpr->rx_std_cons_idx = 0;
8317 tpr->rx_std_prod_idx = 0;
8318 tpr->rx_jmb_cons_idx = 0;
8319 tpr->rx_jmb_prod_idx = 0;
8320
8fea32b9 8321 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8322 memset(&tpr->rx_std_buffers[0], 0,
8323 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8324 if (tpr->rx_jmb_buffers)
2b2cdb65 8325 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8326 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8327 goto done;
8328 }
8329
1da177e4 8330 /* Zero out all descriptors. */
2c49a44d 8331 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8332
287be12e 8333 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8334 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8335 tp->dev->mtu > ETH_DATA_LEN)
8336 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8337 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8338
1da177e4
LT		 8339 /* Initialize invariants of the rings, we only set this
8340 * stuff once. This works because the card does not
8341 * write into the rx buffer posting rings.
8342 */
2c49a44d 8343 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8344 struct tg3_rx_buffer_desc *rxd;
8345
21f581a5 8346 rxd = &tpr->rx_std[i];
287be12e 8347 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8348 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8349 rxd->opaque = (RXD_OPAQUE_RING_STD |
8350 (i << RXD_OPAQUE_INDEX_SHIFT));
8351 }
8352
1da177e4
LT		 8353 /* Now allocate fresh SKBs for each rx ring. */
8354 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8355 unsigned int frag_size;
8356
8357 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8358 &frag_size) < 0) {
5129c3a3
MC		 8359 netdev_warn(tp->dev,
8360 "Using a smaller RX standard ring. Only "
8361 "%d out of %d buffers were allocated "
8362 "successfully\n", i, tp->rx_pending);
32d8c572 8363 if (i == 0)
cf7a7298 8364 goto initfail;
32d8c572 8365 tp->rx_pending = i;
1da177e4 8366 break;
32d8c572 8367 }
1da177e4
LT		 8368 }
8369
63c3a66f 8370 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8371 goto done;
8372
2c49a44d 8373 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8374
63c3a66f 8375 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8376 goto done;
cf7a7298 8377
2c49a44d 8378 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8379 struct tg3_rx_buffer_desc *rxd;
8380
8381 rxd = &tpr->rx_jmb[i].std;
8382 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8383 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8384 RXD_FLAG_JUMBO;
8385 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8386 (i << RXD_OPAQUE_INDEX_SHIFT));
8387 }
8388
8389 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8390 unsigned int frag_size;
8391
8392 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8393 &frag_size) < 0) {
5129c3a3
MC		 8394 netdev_warn(tp->dev,
8395 "Using a smaller RX jumbo ring. Only %d "
8396 "out of %d buffers were allocated "
8397 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8398 if (i == 0)
8399 goto initfail;
8400 tp->rx_jumbo_pending = i;
8401 break;
1da177e4
LT		 8402 }
8403 }
cf7a7298
MC		 8404
8405done:
32d8c572 8406 return 0;
cf7a7298
MC		 8407
8408initfail:
21f581a5 8409 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8410 return -ENOMEM;
1da177e4
LT		 8411}
8412
21f581a5
MC		 8413static void tg3_rx_prodring_fini(struct tg3 *tp,
8414 struct tg3_rx_prodring_set *tpr)
1da177e4 8415{
21f581a5
MC		 8416 kfree(tpr->rx_std_buffers);
8417 tpr->rx_std_buffers = NULL;
8418 kfree(tpr->rx_jmb_buffers);
8419 tpr->rx_jmb_buffers = NULL;
8420 if (tpr->rx_std) {
4bae65c8
MC		 8421 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8422 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8423 tpr->rx_std = NULL;
1da177e4 8424 }
21f581a5 8425 if (tpr->rx_jmb) {
4bae65c8
MC		 8426 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8427 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8428 tpr->rx_jmb = NULL;
1da177e4 8429 }
cf7a7298
MC		 8430}
8431
21f581a5
MC		 8432static int tg3_rx_prodring_init(struct tg3 *tp,
8433 struct tg3_rx_prodring_set *tpr)
cf7a7298 8434{
2c49a44d
MC		 8435 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8436 GFP_KERNEL);
21f581a5 8437 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8438 return -ENOMEM;
8439
4bae65c8
MC		 8440 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8441 TG3_RX_STD_RING_BYTES(tp),
8442 &tpr->rx_std_mapping,
8443 GFP_KERNEL);
21f581a5 8444 if (!tpr->rx_std)
cf7a7298
MC		 8445 goto err_out;
8446
63c3a66f 8447 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8448 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8449 GFP_KERNEL);
8450 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8451 goto err_out;
8452
4bae65c8
MC		 8453 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8454 TG3_RX_JMB_RING_BYTES(tp),
8455 &tpr->rx_jmb_mapping,
8456 GFP_KERNEL);
21f581a5 8457 if (!tpr->rx_jmb)
cf7a7298
MC		 8458 goto err_out;
8459 }
8460
8461 return 0;
8462
8463err_out:
21f581a5 8464 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8465 return -ENOMEM;
8466}
8467
8468/* Free up pending packets in all rx/tx rings.
8469 *
8470 * The chip has been shut down and the driver detached from
8471 * the networking, so no interrupts or new tx packets will
8472 * end up in the driver. tp->{tx,}lock is not held and we are not
8473 * in an interrupt context and thus may sleep.
8474 */
8475static void tg3_free_rings(struct tg3 *tp)
8476{
f77a6a8e 8477 int i, j;
cf7a7298 8478
f77a6a8e
MC		 8479 for (j = 0; j < tp->irq_cnt; j++) {
8480 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8481
8fea32b9 8482 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8483
0c1d0e2b
MC		 8484 if (!tnapi->tx_buffers)
8485 continue;
8486
0d681b27
MC		 8487 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8488 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8489
0d681b27 8490 if (!skb)
f77a6a8e 8491 continue;
cf7a7298 8492
ba1142e4
MC		 8493 tg3_tx_skb_unmap(tnapi, i,
8494 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8495
8496 dev_kfree_skb_any(skb);
8497 }
5cb917bc 8498 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8499 }
cf7a7298
MC		 8500}
8501
8502/* Initialize tx/rx rings for packet processing.
8503 *
8504 * The chip has been shut down and the driver detached from
8505 * the networking, so no interrupts or new tx packets will
8506 * end up in the driver. tp->{tx,}lock are held and thus
8507 * we may not sleep.
8508 */
8509static int tg3_init_rings(struct tg3 *tp)
8510{
f77a6a8e 8511 int i;
72334482 8512
cf7a7298
MC		 8513 /* Free up all the SKBs. */
8514 tg3_free_rings(tp);
8515
f77a6a8e
MC		 8516 for (i = 0; i < tp->irq_cnt; i++) {
8517 struct tg3_napi *tnapi = &tp->napi[i];
8518
8519 tnapi->last_tag = 0;
8520 tnapi->last_irq_tag = 0;
8521 tnapi->hw_status->status = 0;
8522 tnapi->hw_status->status_tag = 0;
8523 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8524
f77a6a8e
MC		 8525 tnapi->tx_prod = 0;
8526 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8527 if (tnapi->tx_ring)
8528 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8529
8530 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8531 if (tnapi->rx_rcb)
8532 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8533
8fea32b9 8534 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8535 tg3_free_rings(tp);
2b2cdb65 8536 return -ENOMEM;
e4af1af9 8537 }
f77a6a8e 8538 }
72334482 8539
2b2cdb65 8540 return 0;
cf7a7298
MC		 8541}
8542
49a359e3 8543static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8544{
f77a6a8e 8545 int i;
898a56f8 8546
49a359e3 8547 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8548 struct tg3_napi *tnapi = &tp->napi[i];
8549
8550 if (tnapi->tx_ring) {
4bae65c8 8551 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8552 tnapi->tx_ring, tnapi->tx_desc_mapping);
8553 tnapi->tx_ring = NULL;
8554 }
8555
8556 kfree(tnapi->tx_buffers);
8557 tnapi->tx_buffers = NULL;
49a359e3
MC		 8558 }
8559}
f77a6a8e 8560
49a359e3
MC		 8561static int tg3_mem_tx_acquire(struct tg3 *tp)
8562{
8563 int i;
8564 struct tg3_napi *tnapi = &tp->napi[0];
8565
8566 /* If multivector TSS is enabled, vector 0 does not handle
8567 * tx interrupts. Don't allocate any resources for it.
8568 */
8569 if (tg3_flag(tp, ENABLE_TSS))
8570 tnapi++;
8571
8572 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8573 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8574 TG3_TX_RING_SIZE, GFP_KERNEL);
8575 if (!tnapi->tx_buffers)
8576 goto err_out;
8577
8578 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8579 TG3_TX_RING_BYTES,
8580 &tnapi->tx_desc_mapping,
8581 GFP_KERNEL);
8582 if (!tnapi->tx_ring)
8583 goto err_out;
8584 }
8585
8586 return 0;
8587
8588err_out:
8589 tg3_mem_tx_release(tp);
8590 return -ENOMEM;
8591}
8592
8593static void tg3_mem_rx_release(struct tg3 *tp)
8594{
8595 int i;
8596
8597 for (i = 0; i < tp->irq_max; i++) {
8598 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8599
8fea32b9
MC		 8600 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8601
49a359e3
MC		 8602 if (!tnapi->rx_rcb)
8603 continue;
8604
8605 dma_free_coherent(&tp->pdev->dev,
8606 TG3_RX_RCB_RING_BYTES(tp),
8607 tnapi->rx_rcb,
8608 tnapi->rx_rcb_mapping);
8609 tnapi->rx_rcb = NULL;
8610 }
8611}
8612
8613static int tg3_mem_rx_acquire(struct tg3 *tp)
8614{
8615 unsigned int i, limit;
8616
8617 limit = tp->rxq_cnt;
8618
8619 /* If RSS is enabled, we need a (dummy) producer ring
8620 * set on vector zero. This is the true hw prodring.
8621 */
8622 if (tg3_flag(tp, ENABLE_RSS))
8623 limit++;
8624
8625 for (i = 0; i < limit; i++) {
8626 struct tg3_napi *tnapi = &tp->napi[i];
8627
8628 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8629 goto err_out;
8630
8631 /* If multivector RSS is enabled, vector 0
8632 * does not handle rx or tx interrupts.
8633 * Don't allocate any resources for it.
8634 */
8635 if (!i && tg3_flag(tp, ENABLE_RSS))
8636 continue;
8637
ede23fa8
JP		 8638 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8639 TG3_RX_RCB_RING_BYTES(tp),
8640 &tnapi->rx_rcb_mapping,
8641 GFP_KERNEL);
49a359e3
MC		 8642 if (!tnapi->rx_rcb)
8643 goto err_out;
49a359e3
MC		 8644 }
8645
8646 return 0;
8647
8648err_out:
8649 tg3_mem_rx_release(tp);
8650 return -ENOMEM;
8651}
8652
8653/*
8654 * Must not be invoked with interrupt sources disabled and
8655 * the hardware shutdown down.
8656 */
8657static void tg3_free_consistent(struct tg3 *tp)
8658{
8659 int i;
8660
8661 for (i = 0; i < tp->irq_cnt; i++) {
8662 struct tg3_napi *tnapi = &tp->napi[i];
8663
f77a6a8e 8664 if (tnapi->hw_status) {
4bae65c8
MC		 8665 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8666 tnapi->hw_status,
8667 tnapi->status_mapping);
f77a6a8e
MC		 8668 tnapi->hw_status = NULL;
8669 }
1da177e4 8670 }
f77a6a8e 8671
49a359e3
MC		 8672 tg3_mem_rx_release(tp);
8673 tg3_mem_tx_release(tp);
8674
1da177e4 8675 if (tp->hw_stats) {
4bae65c8
MC		 8676 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8677 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8678 tp->hw_stats = NULL;
8679 }
8680}
8681
8682/*
8683 * Must not be invoked with interrupt sources disabled and
8684 * the hardware shutdown down. Can sleep.
8685 */
8686static int tg3_alloc_consistent(struct tg3 *tp)
8687{
f77a6a8e 8688 int i;
898a56f8 8689
ede23fa8
JP		 8690 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8691 sizeof(struct tg3_hw_stats),
8692 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8693 if (!tp->hw_stats)
1da177e4
LT		 8694 goto err_out;
8695
f77a6a8e
MC		 8696 for (i = 0; i < tp->irq_cnt; i++) {
8697 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8698 struct tg3_hw_status *sblk;
1da177e4 8699
ede23fa8
JP		 8700 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8701 TG3_HW_STATUS_SIZE,
8702 &tnapi->status_mapping,
8703 GFP_KERNEL);
f77a6a8e
MC		 8704 if (!tnapi->hw_status)
8705 goto err_out;
898a56f8 8706
8d9d7cfc
MC		 8707 sblk = tnapi->hw_status;
8708
49a359e3 8709 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8710 u16 *prodptr = NULL;
8fea32b9 8711
49a359e3
MC		 8712 /*
8713 * When RSS is enabled, the status block format changes
8714 * slightly. The "rx_jumbo_consumer", "reserved",
8715 * and "rx_mini_consumer" members get mapped to the
8716 * other three rx return ring producer indexes.
8717 */
8718 switch (i) {
8719 case 1:
8720 prodptr = &sblk->idx[0].rx_producer;
8721 break;
8722 case 2:
8723 prodptr = &sblk->rx_jumbo_consumer;
8724 break;
8725 case 3:
8726 prodptr = &sblk->reserved;
8727 break;
8728 case 4:
8729 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8730 break;
8731 }
49a359e3
MC		 8732 tnapi->rx_rcb_prod_idx = prodptr;
8733 } else {
8d9d7cfc 8734 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8735 }
f77a6a8e 8736 }
1da177e4 8737
49a359e3
MC		 8738 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8739 goto err_out;
8740
1da177e4
LT		 8741 return 0;
8742
8743err_out:
8744 tg3_free_consistent(tp);
8745 return -ENOMEM;
8746}
8747
8748#define MAX_WAIT_CNT 1000
8749
8750/* To stop a block, clear the enable bit and poll till it
8751 * clears. tp->lock is held.
8752 */
953c96e0 8753static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8754{
8755 unsigned int i;
8756 u32 val;
8757
63c3a66f 8758 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8759 switch (ofs) {
8760 case RCVLSC_MODE:
8761 case DMAC_MODE:
8762 case MBFREE_MODE:
8763 case BUFMGR_MODE:
8764 case MEMARB_MODE:
8765 /* We can't enable/disable these bits of the
8766 * 5705/5750, just say success.
8767 */
8768 return 0;
8769
8770 default:
8771 break;
855e1111 8772 }
1da177e4
LT		 8773 }
8774
8775 val = tr32(ofs);
8776 val &= ~enable_bit;
8777 tw32_f(ofs, val);
8778
8779 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8780 if (pci_channel_offline(tp->pdev)) {
8781 dev_err(&tp->pdev->dev,
8782 "tg3_stop_block device offline, "
8783 "ofs=%lx enable_bit=%x\n",
8784 ofs, enable_bit);
8785 return -ENODEV;
8786 }
8787
1da177e4
LT		 8788 udelay(100);
8789 val = tr32(ofs);
8790 if ((val & enable_bit) == 0)
8791 break;
8792 }
8793
b3b7d6be 8794 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8795 dev_err(&tp->pdev->dev,
8796 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8797 ofs, enable_bit);
1da177e4
LT		 8798 return -ENODEV;
8799 }
8800
8801 return 0;
8802}
8803
8804/* tp->lock is held. */
953c96e0 8805static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8806{
8807 int i, err;
8808
8809 tg3_disable_ints(tp);
8810
6d446ec3
GS		 8811 if (pci_channel_offline(tp->pdev)) {
8812 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8813 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8814 err = -ENODEV;
8815 goto err_no_dev;
8816 }
8817
1da177e4
LT		 8818 tp->rx_mode &= ~RX_MODE_ENABLE;
8819 tw32_f(MAC_RX_MODE, tp->rx_mode);
8820 udelay(10);
8821
b3b7d6be
DM		 8822 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8823 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8824 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8825 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8826 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8827 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8828
8829 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8830 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8831 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8832 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8833 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8834 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8835 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8836
8837 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8838 tw32_f(MAC_MODE, tp->mac_mode);
8839 udelay(40);
8840
8841 tp->tx_mode &= ~TX_MODE_ENABLE;
8842 tw32_f(MAC_TX_MODE, tp->tx_mode);
8843
8844 for (i = 0; i < MAX_WAIT_CNT; i++) {
8845 udelay(100);
8846 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8847 break;
8848 }
8849 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8850 dev_err(&tp->pdev->dev,
8851 "%s timed out, TX_MODE_ENABLE will not clear "
8852 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8853 err |= -ENODEV;
1da177e4
LT		 8854 }
8855
e6de8ad1 8856 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8857 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8858 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8859
8860 tw32(FTQ_RESET, 0xffffffff);
8861 tw32(FTQ_RESET, 0x00000000);
8862
b3b7d6be
DM		 8863 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8864 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8865
6d446ec3 8866err_no_dev:
f77a6a8e
MC		 8867 for (i = 0; i < tp->irq_cnt; i++) {
8868 struct tg3_napi *tnapi = &tp->napi[i];
8869 if (tnapi->hw_status)
8870 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8871 }
1da177e4 8872
1da177e4
LT		 8873 return err;
8874}
8875
ee6a99b5
MC		 8876/* Save PCI command register before chip reset */
8877static void tg3_save_pci_state(struct tg3 *tp)
8878{
8a6eac90 8879 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8880}
8881
8882/* Restore PCI state after chip reset */
8883static void tg3_restore_pci_state(struct tg3 *tp)
8884{
8885 u32 val;
8886
8887 /* Re-enable indirect register accesses. */
8888 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8889 tp->misc_host_ctrl);
8890
8891 /* Set MAX PCI retry to zero. */
8892 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8893 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8894 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8895 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8896 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8897 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8898 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8899 PCISTATE_ALLOW_APE_SHMEM_WR |
8900 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8901 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8902
8a6eac90 8903 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8904
2c55a3d0
MC		 8905 if (!tg3_flag(tp, PCI_EXPRESS)) {
8906 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8907 tp->pci_cacheline_sz);
8908 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8909 tp->pci_lat_timer);
114342f2 8910 }
5f5c51e3 8911
ee6a99b5 8912 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8913 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8914 u16 pcix_cmd;
8915
8916 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8917 &pcix_cmd);
8918 pcix_cmd &= ~PCI_X_CMD_ERO;
8919 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8920 pcix_cmd);
8921 }
ee6a99b5 8922
63c3a66f 8923 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8924
8925 /* Chip reset on 5780 will reset MSI enable bit,
8926 * so need to restore it.
8927 */
63c3a66f 8928 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8929 u16 ctrl;
8930
8931 pci_read_config_word(tp->pdev,
8932 tp->msi_cap + PCI_MSI_FLAGS,
8933 &ctrl);
8934 pci_write_config_word(tp->pdev,
8935 tp->msi_cap + PCI_MSI_FLAGS,
8936 ctrl | PCI_MSI_FLAGS_ENABLE);
8937 val = tr32(MSGINT_MODE);
8938 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8939 }
8940 }
8941}
8942
f82995b6
NS		 8943static void tg3_override_clk(struct tg3 *tp)
8944{
8945 u32 val;
8946
8947 switch (tg3_asic_rev(tp)) {
8948 case ASIC_REV_5717:
8949 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8950 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8951 TG3_CPMU_MAC_ORIDE_ENABLE);
8952 break;
8953
8954 case ASIC_REV_5719:
8955 case ASIC_REV_5720:
8956 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8957 break;
8958
8959 default:
8960 return;
8961 }
8962}
8963
8964static void tg3_restore_clk(struct tg3 *tp)
8965{
8966 u32 val;
8967
8968 switch (tg3_asic_rev(tp)) {
8969 case ASIC_REV_5717:
8970 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8971 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
8972 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
8973 break;
8974
8975 case ASIC_REV_5719:
8976 case ASIC_REV_5720:
8977 val = tr32(TG3_CPMU_CLCK_ORIDE);
8978 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8979 break;
8980
8981 default:
8982 return;
8983 }
8984}
8985
1da177e4
LT		 8986/* tp->lock is held. */
8987static int tg3_chip_reset(struct tg3 *tp)
8988{
8989 u32 val;
1ee582d8 8990 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 8991 int i, err;
1da177e4 8992
8496e85c
RW		 8993 if (!pci_device_is_present(tp->pdev))
8994 return -ENODEV;
8995
f49639e6
DM		 8996 tg3_nvram_lock(tp);
8997
77b483f1
MC		 8998 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8999
f49639e6
DM		 9000 /* No matching tg3_nvram_unlock() after this because
9001 * chip reset below will undo the nvram lock.
9002 */
9003 tp->nvram_lock_cnt = 0;
1da177e4 9004
ee6a99b5
MC		 9005 /* GRC_MISC_CFG core clock reset will clear the memory
9006 * enable bit in PCI register 4 and the MSI enable bit
9007 * on some chips, so we save relevant registers here.
9008 */
9009 tg3_save_pci_state(tp);
9010
4153577a 9011 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 9012 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 9013 tw32(GRC_FASTBOOT_PC, 0);
9014
1da177e4
LT		 9015 /*
9016 * We must avoid the readl() that normally takes place.
9017 * It locks machines, causes machine checks, and other
9018 * fun things. So, temporarily disable the 5701
9019 * hardware workaround, while we do the reset.
9020 */
1ee582d8
MC		 9021 write_op = tp->write32;
9022 if (write_op == tg3_write_flush_reg32)
9023 tp->write32 = tg3_write32;
1da177e4 9024
d18edcb2
MC		 9025 /* Prevent the irq handler from reading or writing PCI registers
9026 * during chip reset when the memory enable bit in the PCI command
9027 * register may be cleared. The chip does not generate interrupt
9028 * at this time, but the irq handler may still be called due to irq
9029 * sharing or irqpoll.
9030 */
63c3a66f 9031 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 9032 for (i = 0; i < tp->irq_cnt; i++) {
9033 struct tg3_napi *tnapi = &tp->napi[i];
9034 if (tnapi->hw_status) {
9035 tnapi->hw_status->status = 0;
9036 tnapi->hw_status->status_tag = 0;
9037 }
9038 tnapi->last_tag = 0;
9039 tnapi->last_irq_tag = 0;
b8fa2f3a 9040 }
d18edcb2 9041 smp_mb();
4f125f42
MC		 9042
9043 for (i = 0; i < tp->irq_cnt; i++)
9044 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 9045
4153577a 9046 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 9047 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9048 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9049 }
9050
1da177e4
LT		 9051 /* do the reset */
9052 val = GRC_MISC_CFG_CORECLK_RESET;
9053
63c3a66f 9054 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 9055 /* Force PCIe 1.0a mode */
4153577a 9056 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9057 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 9058 tr32(TG3_PCIE_PHY_TSTCTL) ==
9059 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9060 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9061
4153577a 9062 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 9063 tw32(GRC_MISC_CFG, (1 << 29));
9064 val |= (1 << 29);
9065 }
9066 }
9067
4153577a 9068 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 9069 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9070 tw32(GRC_VCPU_EXT_CTRL,
9071 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9072 }
9073
f82995b6
NS		 9074 /* Set the clock to the highest frequency to avoid timeouts. With link
9075 * aware mode, the clock speed could be slow and bootcode does not
9076 * complete within the expected time. Override the clock to allow the
9077 * bootcode to finish sooner and then restore it.
9078 */
9079 tg3_override_clk(tp);
9080
f37500d3 9081 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9082 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9083 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9084
1da177e4
LT		 9085 tw32(GRC_MISC_CFG, val);
9086
1ee582d8
MC		 9087 /* restore 5701 hardware bug workaround write method */
9088 tp->write32 = write_op;
1da177e4
LT		 9089
9090 /* Unfortunately, we have to delay before the PCI read back.
9091 * Some 575X chips even will not respond to a PCI cfg access
9092 * when the reset command is given to the chip.
9093 *
9094 * How do these hardware designers expect things to work
9095 * properly if the PCI write is posted for a long period
9096 * of time? It is always necessary to have some method by
9097 * which a register read back can occur to push the write
9098 * out which does the reset.
9099 *
9100 * For most tg3 variants the trick below was working.
9101 * Ho hum...
9102 */
9103 udelay(120);
9104
9105 /* Flush PCI posted writes. The normal MMIO registers
9106 * are inaccessible at this time so this is the only
9107 * way to make this reliably (actually, this is no longer
9108 * the case, see above). I tried to use indirect
9109 * register read/write but this upset some 5701 variants.
9110 */
9111 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9112
9113 udelay(120);
9114
0f49bfbd 9115 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9116 u16 val16;
9117
4153577a 9118 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9119 int j;
1da177e4
LT		 9120 u32 cfg_val;
9121
9122 /* Wait for link training to complete. */
86449944 9123 for (j = 0; j < 5000; j++)
1da177e4
LT		 9124 udelay(100);
9125
9126 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9127 pci_write_config_dword(tp->pdev, 0xc4,
9128 cfg_val | (1 << 15));
9129 }
5e7dfd0f 9130
e7126997 9131 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9132 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9133 /*
9134 * Older PCIe devices only support the 128 byte
9135 * MPS setting. Enforce the restriction.
5e7dfd0f 9136 */
63c3a66f 9137 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9138 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9139 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9140
5e7dfd0f 9141 /* Clear error status */
0f49bfbd 9142 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9143 PCI_EXP_DEVSTA_CED |
9144 PCI_EXP_DEVSTA_NFED |
9145 PCI_EXP_DEVSTA_FED |
9146 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9147 }
9148
ee6a99b5 9149 tg3_restore_pci_state(tp);
1da177e4 9150
63c3a66f
JP		 9151 tg3_flag_clear(tp, CHIP_RESETTING);
9152 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9153
ee6a99b5 9154 val = 0;
63c3a66f 9155 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9156 val = tr32(MEMARB_MODE);
ee6a99b5 9157 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9158
4153577a 9159 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9160 tg3_stop_fw(tp);
9161 tw32(0x5000, 0x400);
9162 }
9163
7e6c63f0
HM		 9164 if (tg3_flag(tp, IS_SSB_CORE)) {
9165 /*
9166 * BCM4785: In order to avoid repercussions from using
9167 * potentially defective internal ROM, stop the Rx RISC CPU,
9168 * which is not required.
9169 */
9170 tg3_stop_fw(tp);
9171 tg3_halt_cpu(tp, RX_CPU_BASE);
9172 }
9173
fb03a43f
NS		 9174 err = tg3_poll_fw(tp);
9175 if (err)
9176 return err;
9177
1da177e4
LT		 9178 tw32(GRC_MODE, tp->grc_mode);
9179
4153577a 9180 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9181 val = tr32(0xc4);
1da177e4
LT		 9182
9183 tw32(0xc4, val | (1 << 15));
9184 }
9185
9186 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9187 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9188 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9189 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9190 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9191 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9192 }
9193
f07e9af3 9194 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9195 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9196 val = tp->mac_mode;
f07e9af3 9197 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9198 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9199 val = tp->mac_mode;
1da177e4 9200 } else
d2394e6b
MC		 9201 val = 0;
9202
9203 tw32_f(MAC_MODE, val);
1da177e4
LT		 9204 udelay(40);
9205
77b483f1
MC		 9206 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9207
0a9140cf
MC		 9208 tg3_mdio_start(tp);
9209
63c3a66f 9210 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9211 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9212 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9213 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9214 val = tr32(0x7c00);
1da177e4
LT		 9215
9216 tw32(0x7c00, val | (1 << 25));
9217 }
9218
f82995b6 9219 tg3_restore_clk(tp);
d78b59f5 9220
1da177e4 9221 /* Reprobe ASF enable state. */
63c3a66f 9222 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9223 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9224 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9225
63c3a66f 9226 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9227 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9228 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9229 u32 nic_cfg;
9230
9231 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9232 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9233 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9234 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9235 if (tg3_flag(tp, 5750_PLUS))
9236 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9237
9238 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9239 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9240 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9241 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9242 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9243 }
9244 }
9245
9246 return 0;
9247}
9248
65ec698d
MC		 9249static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9250static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
e565eec3 9251static void __tg3_set_rx_mode(struct net_device *);
92feeabf 9252
1da177e4 9253/* tp->lock is held. */
953c96e0 9254static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9255{
9256 int err;
9257
9258 tg3_stop_fw(tp);
9259
944d980e 9260 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9261
b3b7d6be 9262 tg3_abort_hw(tp, silent);
1da177e4
LT		 9263 err = tg3_chip_reset(tp);
9264
953c96e0 9265 __tg3_set_mac_addr(tp, false);
daba2a63 9266
944d980e
MC		 9267 tg3_write_sig_legacy(tp, kind);
9268 tg3_write_sig_post_reset(tp, kind);
1da177e4 9269
92feeabf
MC		 9270 if (tp->hw_stats) {
9271 /* Save the stats across chip resets... */
b4017c53 9272 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9273 tg3_get_estats(tp, &tp->estats_prev);
9274
9275 /* And make sure the next sample is new data */
9276 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9277 }
9278
4bc814ab 9279 return err;
1da177e4
LT		 9280}
9281
1da177e4
LT		 9282static int tg3_set_mac_addr(struct net_device *dev, void *p)
9283{
9284 struct tg3 *tp = netdev_priv(dev);
9285 struct sockaddr *addr = p;
953c96e0
JP		 9286 int err = 0;
9287 bool skip_mac_1 = false;
1da177e4 9288
f9804ddb 9289 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9290 return -EADDRNOTAVAIL;
f9804ddb 9291
1da177e4
LT		 9292 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9293
e75f7c90
MC		 9294 if (!netif_running(dev))
9295 return 0;
9296
63c3a66f 9297 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9298 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9299
986e0aeb
MC		 9300 addr0_high = tr32(MAC_ADDR_0_HIGH);
9301 addr0_low = tr32(MAC_ADDR_0_LOW);
9302 addr1_high = tr32(MAC_ADDR_1_HIGH);
9303 addr1_low = tr32(MAC_ADDR_1_LOW);
9304
9305 /* Skip MAC addr 1 if ASF is using it. */
9306 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9307 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9308 skip_mac_1 = true;
58712ef9 9309 }
986e0aeb
MC		 9310 spin_lock_bh(&tp->lock);
9311 __tg3_set_mac_addr(tp, skip_mac_1);
e565eec3 9312 __tg3_set_rx_mode(dev);
986e0aeb 9313 spin_unlock_bh(&tp->lock);
1da177e4 9314
b9ec6c1b 9315 return err;
1da177e4
LT		 9316}
9317
9318/* tp->lock is held. */
9319static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9320 dma_addr_t mapping, u32 maxlen_flags,
9321 u32 nic_addr)
9322{
9323 tg3_write_mem(tp,
9324 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9325 ((u64) mapping >> 32));
9326 tg3_write_mem(tp,
9327 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9328 ((u64) mapping & 0xffffffff));
9329 tg3_write_mem(tp,
9330 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9331 maxlen_flags);
9332
63c3a66f 9333 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9334 tg3_write_mem(tp,
9335 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9336 nic_addr);
9337}
9338
a489b6d9
MC		 9339
9340static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9341{
a489b6d9 9342 int i = 0;
b6080e12 9343
63c3a66f 9344 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9345 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9346 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9347 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9348 } else {
9349 tw32(HOSTCC_TXCOL_TICKS, 0);
9350 tw32(HOSTCC_TXMAX_FRAMES, 0);
9351 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9352
9353 for (; i < tp->txq_cnt; i++) {
9354 u32 reg;
9355
9356 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9357 tw32(reg, ec->tx_coalesce_usecs);
9358 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9359 tw32(reg, ec->tx_max_coalesced_frames);
9360 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9361 tw32(reg, ec->tx_max_coalesced_frames_irq);
9362 }
19cfaecc 9363 }
b6080e12 9364
a489b6d9
MC		 9365 for (; i < tp->irq_max - 1; i++) {
9366 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9367 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9368 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9369 }
9370}
9371
9372static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9373{
9374 int i = 0;
9375 u32 limit = tp->rxq_cnt;
9376
63c3a66f 9377 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9378 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9379 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9380 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9381 limit--;
19cfaecc 9382 } else {
b6080e12
MC		 9383 tw32(HOSTCC_RXCOL_TICKS, 0);
9384 tw32(HOSTCC_RXMAX_FRAMES, 0);
9385 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9386 }
b6080e12 9387
a489b6d9 9388 for (; i < limit; i++) {
b6080e12
MC		 9389 u32 reg;
9390
9391 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9392 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9393 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9394 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9395 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9396 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9397 }
9398
9399 for (; i < tp->irq_max - 1; i++) {
9400 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9401 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9402 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9403 }
9404}
19cfaecc 9405
a489b6d9
MC		 9406static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9407{
9408 tg3_coal_tx_init(tp, ec);
9409 tg3_coal_rx_init(tp, ec);
9410
9411 if (!tg3_flag(tp, 5705_PLUS)) {
9412 u32 val = ec->stats_block_coalesce_usecs;
9413
9414 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9415 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9416
f4a46d1f 9417 if (!tp->link_up)
a489b6d9
MC		 9418 val = 0;
9419
9420 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9421 }
15f9850d 9422}
1da177e4 9423
328947ff
NS		 9424/* tp->lock is held. */
9425static void tg3_tx_rcbs_disable(struct tg3 *tp)
9426{
9427 u32 txrcb, limit;
9428
9429 /* Disable all transmit rings but the first. */
9430 if (!tg3_flag(tp, 5705_PLUS))
9431 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9432 else if (tg3_flag(tp, 5717_PLUS))
9433 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9434 else if (tg3_flag(tp, 57765_CLASS) ||
9435 tg3_asic_rev(tp) == ASIC_REV_5762)
9436 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9437 else
9438 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9439
9440 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9441 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9442 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9443 BDINFO_FLAGS_DISABLED);
9444}
9445
32ba19ef
NS		 9446/* tp->lock is held. */
9447static void tg3_tx_rcbs_init(struct tg3 *tp)
9448{
9449 int i = 0;
9450 u32 txrcb = NIC_SRAM_SEND_RCB;
9451
9452 if (tg3_flag(tp, ENABLE_TSS))
9453 i++;
9454
9455 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9456 struct tg3_napi *tnapi = &tp->napi[i];
9457
9458 if (!tnapi->tx_ring)
9459 continue;
9460
9461 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9462 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9463 NIC_SRAM_TX_BUFFER_DESC);
9464 }
9465}
9466
328947ff
NS		 9467/* tp->lock is held. */
9468static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9469{
9470 u32 rxrcb, limit;
9471
9472 /* Disable all receive return rings but the first. */
9473 if (tg3_flag(tp, 5717_PLUS))
9474 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9475 else if (!tg3_flag(tp, 5705_PLUS))
9476 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9477 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9478 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9479 tg3_flag(tp, 57765_CLASS))
9480 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9481 else
9482 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9483
9484 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9485 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9486 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9487 BDINFO_FLAGS_DISABLED);
9488}
9489
32ba19ef
NS		 9490/* tp->lock is held. */
9491static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9492{
9493 int i = 0;
9494 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9495
9496 if (tg3_flag(tp, ENABLE_RSS))
9497 i++;
9498
9499 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9500 struct tg3_napi *tnapi = &tp->napi[i];
9501
9502 if (!tnapi->rx_rcb)
9503 continue;
9504
9505 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9506 (tp->rx_ret_ring_mask + 1) <<
9507 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9508 }
9509}
9510
2d31ecaf
MC		 9511/* tp->lock is held. */
9512static void tg3_rings_reset(struct tg3 *tp)
9513{
9514 int i;
328947ff 9515 u32 stblk;
2d31ecaf
MC		 9516 struct tg3_napi *tnapi = &tp->napi[0];
9517
328947ff 9518 tg3_tx_rcbs_disable(tp);
2d31ecaf 9519
328947ff 9520 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9521
9522 /* Disable interrupts */
9523 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9524 tp->napi[0].chk_msi_cnt = 0;
9525 tp->napi[0].last_rx_cons = 0;
9526 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9527
9528 /* Zero mailbox registers. */
63c3a66f 9529 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9530 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9531 tp->napi[i].tx_prod = 0;
9532 tp->napi[i].tx_cons = 0;
63c3a66f 9533 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9534 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9535 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9536 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9537 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9538 tp->napi[i].last_rx_cons = 0;
9539 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9540 }
63c3a66f 9541 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9542 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9543 } else {
9544 tp->napi[0].tx_prod = 0;
9545 tp->napi[0].tx_cons = 0;
9546 tw32_mailbox(tp->napi[0].prodmbox, 0);
9547 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9548 }
2d31ecaf
MC		 9549
9550 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9551 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9552 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9553 for (i = 0; i < 16; i++)
9554 tw32_tx_mbox(mbox + i * 8, 0);
9555 }
9556
2d31ecaf
MC		 9557 /* Clear status block in ram. */
9558 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9559
9560 /* Set status block DMA address */
9561 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9562 ((u64) tnapi->status_mapping >> 32));
9563 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9564 ((u64) tnapi->status_mapping & 0xffffffff));
9565
f77a6a8e 9566 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9567
f77a6a8e
MC		 9568 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9569 u64 mapping = (u64)tnapi->status_mapping;
9570 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9571 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9572 stblk += 8;
f77a6a8e
MC		 9573
9574 /* Clear status block in ram. */
9575 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9576 }
32ba19ef
NS		 9577
9578 tg3_tx_rcbs_init(tp);
9579 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9580}
9581
eb07a940
MC		 9582static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9583{
9584 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9585
63c3a66f
JP		 9586 if (!tg3_flag(tp, 5750_PLUS) ||
9587 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9588 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9589 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9590 tg3_flag(tp, 57765_PLUS))
eb07a940 9591 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9592 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9593 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9594 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9595 else
9596 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9597
9598 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9599 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9600
9601 val = min(nic_rep_thresh, host_rep_thresh);
9602 tw32(RCVBDI_STD_THRESH, val);
9603
63c3a66f 9604 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9605 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9606
63c3a66f 9607 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9608 return;
9609
513aa6ea 9610 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9611
9612 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9613
9614 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9615 tw32(RCVBDI_JUMBO_THRESH, val);
9616
63c3a66f 9617 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9618 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9619}
9620
ccd5ba9d
MC		 9621static inline u32 calc_crc(unsigned char *buf, int len)
9622{
9623 u32 reg;
9624 u32 tmp;
9625 int j, k;
9626
9627 reg = 0xffffffff;
9628
9629 for (j = 0; j < len; j++) {
9630 reg ^= buf[j];
9631
9632 for (k = 0; k < 8; k++) {
9633 tmp = reg & 0x01;
9634
9635 reg >>= 1;
9636
9637 if (tmp)
9638 reg ^= 0xedb88320;
9639 }
9640 }
9641
9642 return ~reg;
9643}
9644
9645static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9646{
9647 /* accept or reject all multicast frames */
9648 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9649 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9650 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9651 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9652}
9653
9654static void __tg3_set_rx_mode(struct net_device *dev)
9655{
9656 struct tg3 *tp = netdev_priv(dev);
9657 u32 rx_mode;
9658
9659 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9660 RX_MODE_KEEP_VLAN_TAG);
9661
9662#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9663 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9664 * flag clear.
9665 */
9666 if (!tg3_flag(tp, ENABLE_ASF))
9667 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9668#endif
9669
9670 if (dev->flags & IFF_PROMISC) {
9671 /* Promiscuous mode. */
9672 rx_mode |= RX_MODE_PROMISC;
9673 } else if (dev->flags & IFF_ALLMULTI) {
9674 /* Accept all multicast. */
9675 tg3_set_multi(tp, 1);
9676 } else if (netdev_mc_empty(dev)) {
9677 /* Reject all multicast. */
9678 tg3_set_multi(tp, 0);
9679 } else {
9680 /* Accept one or more multicast(s). */
9681 struct netdev_hw_addr *ha;
9682 u32 mc_filter[4] = { 0, };
9683 u32 regidx;
9684 u32 bit;
9685 u32 crc;
9686
9687 netdev_for_each_mc_addr(ha, dev) {
9688 crc = calc_crc(ha->addr, ETH_ALEN);
9689 bit = ~crc & 0x7f;
9690 regidx = (bit & 0x60) >> 5;
9691 bit &= 0x1f;
9692 mc_filter[regidx] |= (1 << bit);
9693 }
9694
9695 tw32(MAC_HASH_REG_0, mc_filter[0]);
9696 tw32(MAC_HASH_REG_1, mc_filter[1]);
9697 tw32(MAC_HASH_REG_2, mc_filter[2]);
9698 tw32(MAC_HASH_REG_3, mc_filter[3]);
9699 }
9700
e565eec3
MC		 9701 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9702 rx_mode |= RX_MODE_PROMISC;
9703 } else if (!(dev->flags & IFF_PROMISC)) {
9704 /* Add all entries into to the mac addr filter list */
9705 int i = 0;
9706 struct netdev_hw_addr *ha;
9707
9708 netdev_for_each_uc_addr(ha, dev) {
9709 __tg3_set_one_mac_addr(tp, ha->addr,
9710 i + TG3_UCAST_ADDR_IDX(tp));
9711 i++;
9712 }
9713 }
9714
ccd5ba9d
MC		 9715 if (rx_mode != tp->rx_mode) {
9716 tp->rx_mode = rx_mode;
9717 tw32_f(MAC_RX_MODE, rx_mode);
9718 udelay(10);
9719 }
9720}
9721
9102426a 9722static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9723{
9724 int i;
9725
9726 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9727 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9728}
9729
9730static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9731{
9732 int i;
9733
9734 if (!tg3_flag(tp, SUPPORT_MSIX))
9735 return;
9736
0b3ba055 9737 if (tp->rxq_cnt == 1) {
bcebcc46 9738 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9739 return;
9740 }
9741
9742 /* Validate table against current IRQ count */
9743 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9744 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9745 break;
9746 }
9747
9748 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9749 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9750}
9751
90415477 9752static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9753{
9754 int i = 0;
9755 u32 reg = MAC_RSS_INDIR_TBL_0;
9756
9757 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9758 u32 val = tp->rss_ind_tbl[i];
9759 i++;
9760 for (; i % 8; i++) {
9761 val <<= 4;
9762 val |= tp->rss_ind_tbl[i];
9763 }
9764 tw32(reg, val);
9765 reg += 4;
9766 }
9767}
9768
9bc297ea
NS		 9769static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9770{
9771 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9772 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9773 else
9774 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9775}
9776
1da177e4 9777/* tp->lock is held. */
953c96e0 9778static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9779{
9780 u32 val, rdmac_mode;
9781 int i, err, limit;
8fea32b9 9782 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9783
9784 tg3_disable_ints(tp);
9785
9786 tg3_stop_fw(tp);
9787
9788 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9789
63c3a66f 9790 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9791 tg3_abort_hw(tp, 1);
1da177e4 9792
fdad8de4
NS		 9793 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9794 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9795 tg3_phy_pull_config(tp);
400dfbaa 9796 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9797 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9798 }
9799
400dfbaa
NS		 9800 /* Enable MAC control of LPI */
9801 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9802 tg3_setup_eee(tp);
9803
603f1173 9804 if (reset_phy)
d4d2c558
MC		 9805 tg3_phy_reset(tp);
9806
1da177e4
LT		 9807 err = tg3_chip_reset(tp);
9808 if (err)
9809 return err;
9810
9811 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9812
4153577a 9813 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9814 val = tr32(TG3_CPMU_CTRL);
9815 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9816 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9817
9818 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9819 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9820 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9821 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9822
9823 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9824 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9825 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9826 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9827
9828 val = tr32(TG3_CPMU_HST_ACC);
9829 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9830 val |= CPMU_HST_ACC_MACCLK_6_25;
9831 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9832 }
9833
4153577a 9834 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9835 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9836 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9837 PCIE_PWR_MGMT_L1_THRESH_4MS;
9838 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9839
9840 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9841 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9842
9843 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9844
f40386c8
MC		 9845 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9846 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9847 }
9848
63c3a66f 9849 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9850 u32 grc_mode = tr32(GRC_MODE);
9851
9852 /* Access the lower 1K of PL PCIE block registers. */
9853 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9854 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9855
9856 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9857 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9858 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9859
9860 tw32(GRC_MODE, grc_mode);
9861 }
9862
55086ad9 9863 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9864 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9865 u32 grc_mode = tr32(GRC_MODE);
cea46462 9866
5093eedc
MC		 9867 /* Access the lower 1K of PL PCIE block registers. */
9868 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9869 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9870
5093eedc
MC		 9871 val = tr32(TG3_PCIE_TLDLPL_PORT +
9872 TG3_PCIE_PL_LO_PHYCTL5);
9873 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9874 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9875
5093eedc
MC		 9876 tw32(GRC_MODE, grc_mode);
9877 }
a977dbe8 9878
4153577a 9879 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9880 u32 grc_mode;
9881
9882 /* Fix transmit hangs */
9883 val = tr32(TG3_CPMU_PADRNG_CTL);
9884 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9885 tw32(TG3_CPMU_PADRNG_CTL, val);
9886
9887 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9888
9889 /* Access the lower 1K of DL PCIE block registers. */
9890 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9891 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9892
9893 val = tr32(TG3_PCIE_TLDLPL_PORT +
9894 TG3_PCIE_DL_LO_FTSMAX);
9895 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9896 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9897 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9898
9899 tw32(GRC_MODE, grc_mode);
9900 }
9901
a977dbe8
MC		 9902 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9903 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9904 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9905 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9906 }
9907
1da177e4
LT		 9908 /* This works around an issue with Athlon chipsets on
9909 * B3 tigon3 silicon. This bit has no effect on any
9910 * other revision. But do not set this on PCI Express
795d01c5 9911 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9912 */
63c3a66f
JP		 9913 if (!tg3_flag(tp, CPMU_PRESENT)) {
9914 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9915 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9916 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9917 }
1da177e4 9918
4153577a 9919 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9920 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9921 val = tr32(TG3PCI_PCISTATE);
9922 val |= PCISTATE_RETRY_SAME_DMA;
9923 tw32(TG3PCI_PCISTATE, val);
9924 }
9925
63c3a66f 9926 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9927 /* Allow reads and writes to the
9928 * APE register and memory space.
9929 */
9930 val = tr32(TG3PCI_PCISTATE);
9931 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9932 PCISTATE_ALLOW_APE_SHMEM_WR |
9933 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9934 tw32(TG3PCI_PCISTATE, val);
9935 }
9936
4153577a 9937 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9938 /* Enable some hw fixes. */
9939 val = tr32(TG3PCI_MSI_DATA);
9940 val |= (1 << 26) | (1 << 28) | (1 << 29);
9941 tw32(TG3PCI_MSI_DATA, val);
9942 }
9943
9944 /* Descriptor ring init may make accesses to the
9945 * NIC SRAM area to setup the TX descriptors, so we
9946 * can only do this after the hardware has been
9947 * successfully reset.
9948 */
32d8c572
MC		 9949 err = tg3_init_rings(tp);
9950 if (err)
9951 return err;
1da177e4 9952
63c3a66f 9953 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9954 val = tr32(TG3PCI_DMA_RW_CTRL) &
9955 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9956 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9957 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9958 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9959 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9960 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9961 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9962 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9963 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9964 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9965 /* This value is determined during the probe time DMA
9966 * engine test, tg3_test_dma.
9967 */
9968 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9969 }
1da177e4
LT		 9970
9971 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9972 GRC_MODE_4X_NIC_SEND_RINGS |
9973 GRC_MODE_NO_TX_PHDR_CSUM |
9974 GRC_MODE_NO_RX_PHDR_CSUM);
9975 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 9976
9977 /* Pseudo-header checksum is done by hardware logic and not
9978 * the offload processers, so make the chip do the pseudo-
9979 * header checksums on receive. For transmit it is more
9980 * convenient to do the pseudo-header checksum in software
9981 * as Linux does that on transmit for us in all cases.
9982 */
9983 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 9984
fb4ce8ad
MC		 9985 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9986 if (tp->rxptpctl)
9987 tw32(TG3_RX_PTP_CTL,
9988 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9989
9990 if (tg3_flag(tp, PTP_CAPABLE))
9991 val |= GRC_MODE_TIME_SYNC_ENABLE;
9992
9993 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 9994
9995 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9996 val = tr32(GRC_MISC_CFG);
9997 val &= ~0xff;
9998 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9999 tw32(GRC_MISC_CFG, val);
10000
10001 /* Initialize MBUF/DESC pool. */
63c3a66f 10002 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 10003 /* Do nothing. */
4153577a 10004 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 10005 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 10006 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 10007 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10008 else
10009 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10010 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10011 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 10012 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10013 int fw_len;
10014
077f849d 10015 fw_len = tp->fw_len;
1da177e4
LT		 10016 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10017 tw32(BUFMGR_MB_POOL_ADDR,
10018 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10019 tw32(BUFMGR_MB_POOL_SIZE,
10020 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10021 }
1da177e4 10022
0f893dc6 10023 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 10024 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10025 tp->bufmgr_config.mbuf_read_dma_low_water);
10026 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10027 tp->bufmgr_config.mbuf_mac_rx_low_water);
10028 tw32(BUFMGR_MB_HIGH_WATER,
10029 tp->bufmgr_config.mbuf_high_water);
10030 } else {
10031 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10032 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10033 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10034 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10035 tw32(BUFMGR_MB_HIGH_WATER,
10036 tp->bufmgr_config.mbuf_high_water_jumbo);
10037 }
10038 tw32(BUFMGR_DMA_LOW_WATER,
10039 tp->bufmgr_config.dma_low_water);
10040 tw32(BUFMGR_DMA_HIGH_WATER,
10041 tp->bufmgr_config.dma_high_water);
10042
d309a46e 10043 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 10044 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 10045 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a 10046 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 10047 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 10048 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10049 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 10050 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 10051 tw32(BUFMGR_MODE, val);
1da177e4
LT		 10052 for (i = 0; i < 2000; i++) {
10053 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10054 break;
10055 udelay(10);
10056 }
10057 if (i >= 2000) {
05dbe005 10058 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 10059 return -ENODEV;
10060 }
10061
4153577a 10062 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 10063 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 10064
eb07a940 10065 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 10066
10067 /* Initialize TG3_BDINFO's at:
10068 * RCVDBDI_STD_BD: standard eth size rx ring
10069 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10070 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10071 *
10072 * like so:
10073 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10074 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10075 * ring attribute flags
10076 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10077 *
10078 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10079 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10080 *
10081 * The size of each ring is fixed in the firmware, but the location is
10082 * configurable.
10083 */
10084 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10085 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 10086 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10087 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 10088 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 10089 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10090 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 10091
fdb72b38 10092 /* Disable the mini ring */
63c3a66f 10093 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10094 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10095 BDINFO_FLAGS_DISABLED);
10096
fdb72b38
MC		 10097 /* Program the jumbo buffer descriptor ring control
10098 * blocks on those devices that have them.
10099 */
4153577a 10100 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10101 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10102
63c3a66f 10103 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10104 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10105 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10106 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10107 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10108 val = TG3_RX_JMB_RING_SIZE(tp) <<
10109 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10110 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10111 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10112 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10113 tg3_flag(tp, 57765_CLASS) ||
4153577a 10114 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10115 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10116 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10117 } else {
10118 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10119 BDINFO_FLAGS_DISABLED);
10120 }
10121
63c3a66f 10122 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10123 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10124 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10125 val |= (TG3_RX_STD_DMA_SZ << 2);
10126 } else
04380d40 10127 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10128 } else
de9f5230 10129 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10130
10131 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10132
411da640 10133 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10134 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10135
63c3a66f
JP		 10136 tpr->rx_jmb_prod_idx =
10137 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10138 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10139
2d31ecaf
MC		 10140 tg3_rings_reset(tp);
10141
1da177e4 10142 /* Initialize MAC address and backoff seed. */
953c96e0 10143 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10144
10145 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10146 tw32(MAC_RX_MTU_SIZE,
10147 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10148
10149 /* The slot time is changed by tg3_setup_phy if we
10150 * run at gigabit with half duplex.
10151 */
f2096f94
MC		 10152 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10153 (6 << TX_LENGTHS_IPG_SHIFT) |
10154 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10155
4153577a
JP		 10156 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10157 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10158 val |= tr32(MAC_TX_LENGTHS) &
10159 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10160 TX_LENGTHS_CNT_DWN_VAL_MSK);
10161
10162 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10163
10164 /* Receive rules. */
10165 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10166 tw32(RCVLPC_CONFIG, 0x0181);
10167
10168 /* Calculate RDMAC_MODE setting early, we need it to determine
10169 * the RCVLPC_STATE_ENABLE mask.
10170 */
10171 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10172 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10173 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10174 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10175 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10176
4153577a 10177 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10178 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10179
4153577a
JP		 10180 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10181 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10182 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10183 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10184 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10185 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10186
4153577a
JP		 10187 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10188 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10189 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10190 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10191 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10192 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10193 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10194 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10195 }
10196 }
10197
63c3a66f 10198 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10199 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10200
4153577a 10201 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10202 tp->dma_limit = 0;
10203 if (tp->dev->mtu <= ETH_DATA_LEN) {
10204 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10205 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10206 }
10207 }
10208
63c3a66f
JP		 10209 if (tg3_flag(tp, HW_TSO_1) ||
10210 tg3_flag(tp, HW_TSO_2) ||
10211 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10212 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10213
108a6c16 10214 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10215 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10216 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10217 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10218
4153577a
JP		 10219 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10220 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10221 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10222
4153577a
JP		 10223 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10224 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10225 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10226 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10227 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10228 u32 tgtreg;
10229
4153577a 10230 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10231 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10232 else
10233 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10234
10235 val = tr32(tgtreg);
4153577a
JP		 10236 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10237 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10238 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10239 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10240 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10241 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10242 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10243 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10244 }
c65a17f4 10245 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10246 }
10247
4153577a
JP		 10248 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10249 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10250 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10251 u32 tgtreg;
10252
4153577a 10253 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10254 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10255 else
10256 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10257
10258 val = tr32(tgtreg);
10259 tw32(tgtreg, val |
d309a46e
MC		 10260 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10261 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10262 }
10263
1da177e4 10264 /* Receive/send statistics. */
63c3a66f 10265 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10266 val = tr32(RCVLPC_STATS_ENABLE);
10267 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10268 tw32(RCVLPC_STATS_ENABLE, val);
10269 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10270 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10271 val = tr32(RCVLPC_STATS_ENABLE);
10272 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10273 tw32(RCVLPC_STATS_ENABLE, val);
10274 } else {
10275 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10276 }
10277 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10278 tw32(SNDDATAI_STATSENAB, 0xffffff);
10279 tw32(SNDDATAI_STATSCTRL,
10280 (SNDDATAI_SCTRL_ENABLE |
10281 SNDDATAI_SCTRL_FASTUPD));
10282
10283 /* Setup host coalescing engine. */
10284 tw32(HOSTCC_MODE, 0);
10285 for (i = 0; i < 2000; i++) {
10286 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10287 break;
10288 udelay(10);
10289 }
10290
d244c892 10291 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10292
63c3a66f 10293 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10294 /* Status/statistics block address. See tg3_timer,
10295 * the tg3_periodic_fetch_stats call there, and
10296 * tg3_get_stats to see how this works for 5705/5750 chips.
10297 */
1da177e4
LT		 10298 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10299 ((u64) tp->stats_mapping >> 32));
10300 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10301 ((u64) tp->stats_mapping & 0xffffffff));
10302 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10303
1da177e4 10304 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10305
10306 /* Clear statistics and status block memory areas */
10307 for (i = NIC_SRAM_STATS_BLK;
10308 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10309 i += sizeof(u32)) {
10310 tg3_write_mem(tp, i, 0);
10311 udelay(40);
10312 }
1da177e4
LT		 10313 }
10314
10315 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10316
10317 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10318 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10319 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10320 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10321
f07e9af3
MC		 10322 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10323 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10324 /* reset to prevent losing 1st rx packet intermittently */
10325 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10326 udelay(10);
10327 }
10328
3bda1258 10329 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10330 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10331 MAC_MODE_FHDE_ENABLE;
10332 if (tg3_flag(tp, ENABLE_APE))
10333 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10334 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10335 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10336 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10337 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10338 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10339 udelay(40);
10340
314fba34 10341 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10342 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10343 * register to preserve the GPIO settings for LOMs. The GPIOs,
10344 * whether used as inputs or outputs, are set by boot code after
10345 * reset.
10346 */
63c3a66f 10347 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10348 u32 gpio_mask;
10349
9d26e213
MC		 10350 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10351 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10352 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10353
4153577a 10354 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10355 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10356 GRC_LCLCTRL_GPIO_OUTPUT3;
10357
4153577a 10358 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10359 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10360
aaf84465 10361 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10362 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10363
10364 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10365 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10366 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10367 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10368 }
1da177e4
LT		 10369 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10370 udelay(100);
10371
c3b5003b 10372 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10373 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10374 val |= MSGINT_MODE_ENABLE;
10375 if (tp->irq_cnt > 1)
10376 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10377 if (!tg3_flag(tp, 1SHOT_MSI))
10378 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10379 tw32(MSGINT_MODE, val);
10380 }
10381
63c3a66f 10382 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10383 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10384 udelay(40);
10385 }
10386
10387 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10388 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10389 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10390 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10391 WDMAC_MODE_LNGREAD_ENAB);
10392
4153577a
JP		 10393 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10394 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10395 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10396 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10397 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10398 /* nothing */
10399 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10400 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10401 val |= WDMAC_MODE_RX_ACCEL;
10402 }
10403 }
10404
d9ab5ad1 10405 /* Enable host coalescing bug fix */
63c3a66f 10406 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10407 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10408
4153577a 10409 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10410 val |= WDMAC_MODE_BURST_ALL_DATA;
10411
1da177e4
LT		 10412 tw32_f(WDMAC_MODE, val);
10413 udelay(40);
10414
63c3a66f 10415 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10416 u16 pcix_cmd;
10417
10418 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10419 &pcix_cmd);
4153577a 10420 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10421 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10422 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10423 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10424 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10425 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10426 }
9974a356
MC		 10427 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10428 pcix_cmd);
1da177e4
LT		 10429 }
10430
10431 tw32_f(RDMAC_MODE, rdmac_mode);
10432 udelay(40);
10433
9bc297ea
NS		 10434 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10435 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10436 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10437 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10438 break;
10439 }
10440 if (i < TG3_NUM_RDMA_CHANNELS) {
10441 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10442 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10443 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10444 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10445 }
10446 }
10447
1da177e4 10448 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10449 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10450 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10451
4153577a 10452 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10453 tw32(SNDDATAC_MODE,
10454 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10455 else
10456 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10457
1da177e4
LT		 10458 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10459 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10460 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10461 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10462 val |= RCVDBDI_MODE_LRG_RING_SZ;
10463 tw32(RCVDBDI_MODE, val);
1da177e4 10464 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10465 if (tg3_flag(tp, HW_TSO_1) ||
10466 tg3_flag(tp, HW_TSO_2) ||
10467 tg3_flag(tp, HW_TSO_3))
1da177e4 10468 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10469 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10470 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10471 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10472 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10473 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10474
4153577a 10475 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10476 err = tg3_load_5701_a0_firmware_fix(tp);
10477 if (err)
10478 return err;
10479 }
10480
c4dab506
NS		 10481 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10482 /* Ignore any errors for the firmware download. If download
10483 * fails, the device will operate with EEE disabled
10484 */
10485 tg3_load_57766_firmware(tp);
10486 }
10487
63c3a66f 10488 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10489 err = tg3_load_tso_firmware(tp);
10490 if (err)
10491 return err;
10492 }
1da177e4
LT		 10493
10494 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10495
63c3a66f 10496 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10497 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10498 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10499
4153577a
JP		 10500 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10501 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10502 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10503 tp->tx_mode &= ~val;
10504 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10505 }
10506
1da177e4
LT		 10507 tw32_f(MAC_TX_MODE, tp->tx_mode);
10508 udelay(100);
10509
63c3a66f 10510 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10511 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10512
10513 /* Setup the "secret" hash key. */
10514 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10515 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10516 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10517 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10518 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10519 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10520 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10521 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10522 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10523 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10524 }
10525
1da177e4 10526 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10527 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10528 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10529
378b72c8
NS		 10530 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10531 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10532
63c3a66f 10533 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10534 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10535 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10536 RX_MODE_RSS_IPV6_HASH_EN |
10537 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10538 RX_MODE_RSS_IPV4_HASH_EN |
10539 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10540
1da177e4
LT		 10541 tw32_f(MAC_RX_MODE, tp->rx_mode);
10542 udelay(10);
10543
1da177e4
LT		 10544 tw32(MAC_LED_CTRL, tp->led_ctrl);
10545
10546 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10547 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10548 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10549 udelay(10);
10550 }
10551 tw32_f(MAC_RX_MODE, tp->rx_mode);
10552 udelay(10);
10553
f07e9af3 10554 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10555 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10556 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10557 /* Set drive transmission level to 1.2V */
10558 /* only if the signal pre-emphasis bit is not set */
10559 val = tr32(MAC_SERDES_CFG);
10560 val &= 0xfffff000;
10561 val |= 0x880;
10562 tw32(MAC_SERDES_CFG, val);
10563 }
4153577a 10564 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10565 tw32(MAC_SERDES_CFG, 0x616000);
10566 }
10567
10568 /* Prevent chip from dropping frames when flow control
10569 * is enabled.
10570 */
55086ad9 10571 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10572 val = 1;
10573 else
10574 val = 2;
10575 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10576
4153577a 10577 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10578 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10579 /* Use hardware link auto-negotiation */
63c3a66f 10580 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10581 }
10582
f07e9af3 10583 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10584 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10585 u32 tmp;
10586
10587 tmp = tr32(SERDES_RX_CTRL);
10588 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10589 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10590 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10591 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10592 }
10593
63c3a66f 10594 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10595 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10596 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10597
953c96e0 10598 err = tg3_setup_phy(tp, false);
dd477003
MC		 10599 if (err)
10600 return err;
1da177e4 10601
f07e9af3
MC		 10602 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10603 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10604 u32 tmp;
10605
10606 /* Clear CRC stats. */
10607 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10608 tg3_writephy(tp, MII_TG3_TEST1,
10609 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10610 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10611 }
1da177e4
LT		 10612 }
10613 }
10614
10615 __tg3_set_rx_mode(tp->dev);
10616
10617 /* Initialize receive rules. */
10618 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10619 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10620 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10621 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10622
63c3a66f 10623 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10624 limit = 8;
10625 else
10626 limit = 16;
63c3a66f 10627 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10628 limit -= 4;
10629 switch (limit) {
10630 case 16:
10631 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10632 case 15:
10633 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10634 case 14:
10635 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10636 case 13:
10637 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10638 case 12:
10639 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10640 case 11:
10641 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10642 case 10:
10643 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10644 case 9:
10645 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10646 case 8:
10647 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10648 case 7:
10649 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10650 case 6:
10651 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10652 case 5:
10653 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10654 case 4:
10655 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10656 case 3:
10657 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10658 case 2:
10659 case 1:
10660
10661 default:
10662 break;
855e1111 10663 }
1da177e4 10664
63c3a66f 10665 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10666 /* Write our heartbeat update interval to APE. */
10667 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10668 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10669
1da177e4
LT		 10670 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10671
1da177e4
LT		 10672 return 0;
10673}
10674
10675/* Called at device open time to get the chip ready for
10676 * packet processing. Invoked with tp->lock held.
10677 */
953c96e0 10678static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10679{
df465abf
NS		 10680 /* Chip may have been just powered on. If so, the boot code may still
10681 * be running initialization. Wait for it to finish to avoid races in
10682 * accessing the hardware.
10683 */
10684 tg3_enable_register_access(tp);
10685 tg3_poll_fw(tp);
10686
1da177e4
LT		 10687 tg3_switch_clocks(tp);
10688
10689 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10690
2f751b67 10691 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10692}
10693
aed93e0b
MC		 10694static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10695{
10696 int i;
10697
10698 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10699 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10700
10701 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10702 off += len;
10703
10704 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10705 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10706 memset(ocir, 0, TG3_OCIR_LEN);
10707 }
10708}
10709
10710/* sysfs attributes for hwmon */
10711static ssize_t tg3_show_temp(struct device *dev,
10712 struct device_attribute *devattr, char *buf)
10713{
aed93e0b 10714 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
a2f4dfba 10715 struct tg3 *tp = dev_get_drvdata(dev);
aed93e0b
MC		 10716 u32 temperature;
10717
10718 spin_lock_bh(&tp->lock);
10719 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10720 sizeof(temperature));
10721 spin_unlock_bh(&tp->lock);
10722 return sprintf(buf, "%u\n", temperature);
10723}
10724
10725
10726static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10727 TG3_TEMP_SENSOR_OFFSET);
10728static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10729 TG3_TEMP_CAUTION_OFFSET);
10730static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10731 TG3_TEMP_MAX_OFFSET);
10732
a2f4dfba 10733static struct attribute *tg3_attrs[] = {
aed93e0b
MC		 10734 &sensor_dev_attr_temp1_input.dev_attr.attr,
10735 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10736 &sensor_dev_attr_temp1_max.dev_attr.attr,
10737 NULL
10738};
a2f4dfba 10739ATTRIBUTE_GROUPS(tg3);
aed93e0b 10740
aed93e0b
MC		 10741static void tg3_hwmon_close(struct tg3 *tp)
10742{
aed93e0b
MC		 10743 if (tp->hwmon_dev) {
10744 hwmon_device_unregister(tp->hwmon_dev);
10745 tp->hwmon_dev = NULL;
aed93e0b 10746 }
aed93e0b
MC		 10747}
10748
10749static void tg3_hwmon_open(struct tg3 *tp)
10750{
a2f4dfba 10751 int i;
aed93e0b
MC		 10752 u32 size = 0;
10753 struct pci_dev *pdev = tp->pdev;
10754 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10755
10756 tg3_sd_scan_scratchpad(tp, ocirs);
10757
10758 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10759 if (!ocirs[i].src_data_length)
10760 continue;
10761
10762 size += ocirs[i].src_hdr_length;
10763 size += ocirs[i].src_data_length;
10764 }
10765
10766 if (!size)
10767 return;
10768
a2f4dfba
GR		 10769 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10770 tp, tg3_groups);
aed93e0b
MC		 10771 if (IS_ERR(tp->hwmon_dev)) {
10772 tp->hwmon_dev = NULL;
10773 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
aed93e0b 10774 }
aed93e0b
MC		 10775}
10776
10777
1da177e4
LT		 10778#define TG3_STAT_ADD32(PSTAT, REG) \
10779do { u32 __val = tr32(REG); \
10780 (PSTAT)->low += __val; \
10781 if ((PSTAT)->low < __val) \
10782 (PSTAT)->high += 1; \
10783} while (0)
10784
10785static void tg3_periodic_fetch_stats(struct tg3 *tp)
10786{
10787 struct tg3_hw_stats *sp = tp->hw_stats;
10788
f4a46d1f 10789 if (!tp->link_up)
1da177e4
LT		 10790 return;
10791
10792 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10793 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10794 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10795 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10796 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10797 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10798 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10799 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10800 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10801 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10802 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10803 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10804 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10805 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10806 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10807 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10808 u32 val;
10809
10810 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10811 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10812 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10813 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10814 }
1da177e4
LT		 10815
10816 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10817 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10818 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10819 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10820 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10821 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10822 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10823 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10824 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10825 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10826 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10827 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10828 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10829 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10830
10831 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a 10832 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
94962f7f 10833 tg3_asic_rev(tp) != ASIC_REV_5762 &&
4153577a
JP		 10834 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10835 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10836 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10837 } else {
10838 u32 val = tr32(HOSTCC_FLOW_ATTN);
10839 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10840 if (val) {
10841 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10842 sp->rx_discards.low += val;
10843 if (sp->rx_discards.low < val)
10844 sp->rx_discards.high += 1;
10845 }
10846 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10847 }
463d305b 10848 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10849}
10850
0e6cf6a9
MC		 10851static void tg3_chk_missed_msi(struct tg3 *tp)
10852{
10853 u32 i;
10854
10855 for (i = 0; i < tp->irq_cnt; i++) {
10856 struct tg3_napi *tnapi = &tp->napi[i];
10857
10858 if (tg3_has_work(tnapi)) {
10859 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10860 tnapi->last_tx_cons == tnapi->tx_cons) {
10861 if (tnapi->chk_msi_cnt < 1) {
10862 tnapi->chk_msi_cnt++;
10863 return;
10864 }
7f230735 10865 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10866 }
10867 }
10868 tnapi->chk_msi_cnt = 0;
10869 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10870 tnapi->last_tx_cons = tnapi->tx_cons;
10871 }
10872}
10873
1da177e4
LT		 10874static void tg3_timer(unsigned long __opaque)
10875{
10876 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10877
5b190624 10878 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10879 goto restart_timer;
10880
f47c11ee 10881 spin_lock(&tp->lock);
1da177e4 10882
4153577a 10883 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10884 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10885 tg3_chk_missed_msi(tp);
10886
7e6c63f0
HM		 10887 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10888 /* BCM4785: Flush posted writes from GbE to host memory. */
10889 tr32(HOSTCC_MODE);
10890 }
10891
63c3a66f 10892 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10893 /* All of this garbage is because when using non-tagged
10894 * IRQ status the mailbox/status_block protocol the chip
10895 * uses with the cpu is race prone.
10896 */
898a56f8 10897 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10898 tw32(GRC_LOCAL_CTRL,
10899 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10900 } else {
10901 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10902 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10903 }
1da177e4 10904
fac9b83e 10905 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10906 spin_unlock(&tp->lock);
db219973 10907 tg3_reset_task_schedule(tp);
5b190624 10908 goto restart_timer;
fac9b83e 10909 }
1da177e4
LT		 10910 }
10911
1da177e4
LT		 10912 /* This part only runs once per second. */
10913 if (!--tp->timer_counter) {
63c3a66f 10914 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10915 tg3_periodic_fetch_stats(tp);
10916
b0c5943f
MC		 10917 if (tp->setlpicnt && !--tp->setlpicnt)
10918 tg3_phy_eee_enable(tp);
52b02d04 10919
63c3a66f 10920 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10921 u32 mac_stat;
10922 int phy_event;
10923
10924 mac_stat = tr32(MAC_STATUS);
10925
10926 phy_event = 0;
f07e9af3 10927 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10928 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10929 phy_event = 1;
10930 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10931 phy_event = 1;
10932
10933 if (phy_event)
953c96e0 10934 tg3_setup_phy(tp, false);
63c3a66f 10935 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10936 u32 mac_stat = tr32(MAC_STATUS);
10937 int need_setup = 0;
10938
f4a46d1f 10939 if (tp->link_up &&
1da177e4
LT		 10940 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10941 need_setup = 1;
10942 }
f4a46d1f 10943 if (!tp->link_up &&
1da177e4
LT		 10944 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10945 MAC_STATUS_SIGNAL_DET))) {
10946 need_setup = 1;
10947 }
10948 if (need_setup) {
3d3ebe74
MC		 10949 if (!tp->serdes_counter) {
10950 tw32_f(MAC_MODE,
10951 (tp->mac_mode &
10952 ~MAC_MODE_PORT_MODE_MASK));
10953 udelay(40);
10954 tw32_f(MAC_MODE, tp->mac_mode);
10955 udelay(40);
10956 }
953c96e0 10957 tg3_setup_phy(tp, false);
1da177e4 10958 }
f07e9af3 10959 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10960 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10961 tg3_serdes_parallel_detect(tp);
1743b83c
NS		 10962 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10963 u32 cpmu = tr32(TG3_CPMU_STATUS);
10964 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10965 TG3_CPMU_STATUS_LINK_MASK);
10966
10967 if (link_up != tp->link_up)
10968 tg3_setup_phy(tp, false);
57d8b880 10969 }
1da177e4
LT		 10970
10971 tp->timer_counter = tp->timer_multiplier;
10972 }
10973
130b8e4d
MC		 10974 /* Heartbeat is only sent once every 2 seconds.
10975 *
10976 * The heartbeat is to tell the ASF firmware that the host
10977 * driver is still alive. In the event that the OS crashes,
10978 * ASF needs to reset the hardware to free up the FIFO space
10979 * that may be filled with rx packets destined for the host.
10980 * If the FIFO is full, ASF will no longer function properly.
10981 *
10982 * Unintended resets have been reported on real time kernels
10983 * where the timer doesn't run on time. Netpoll will also have
10984 * same problem.
10985 *
10986 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10987 * to check the ring condition when the heartbeat is expiring
10988 * before doing the reset. This will prevent most unintended
10989 * resets.
10990 */
1da177e4 10991 if (!--tp->asf_counter) {
63c3a66f 10992 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 10993 tg3_wait_for_event_ack(tp);
10994
bbadf503 10995 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 10996 FWCMD_NICDRV_ALIVE3);
bbadf503 10997 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 10998 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10999 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 11000
11001 tg3_generate_fw_event(tp);
1da177e4
LT		 11002 }
11003 tp->asf_counter = tp->asf_multiplier;
11004 }
11005
f47c11ee 11006 spin_unlock(&tp->lock);
1da177e4 11007
f475f163 11008restart_timer:
1da177e4
LT		 11009 tp->timer.expires = jiffies + tp->timer_offset;
11010 add_timer(&tp->timer);
11011}
11012
229b1ad1 11013static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 11014{
11015 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 11016 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 11017 !tg3_flag(tp, 57765_CLASS))
11018 tp->timer_offset = HZ;
11019 else
11020 tp->timer_offset = HZ / 10;
11021
11022 BUG_ON(tp->timer_offset > HZ);
11023
11024 tp->timer_multiplier = (HZ / tp->timer_offset);
11025 tp->asf_multiplier = (HZ / tp->timer_offset) *
11026 TG3_FW_UPDATE_FREQ_SEC;
11027
11028 init_timer(&tp->timer);
11029 tp->timer.data = (unsigned long) tp;
11030 tp->timer.function = tg3_timer;
11031}
11032
11033static void tg3_timer_start(struct tg3 *tp)
11034{
11035 tp->asf_counter = tp->asf_multiplier;
11036 tp->timer_counter = tp->timer_multiplier;
11037
11038 tp->timer.expires = jiffies + tp->timer_offset;
11039 add_timer(&tp->timer);
11040}
11041
11042static void tg3_timer_stop(struct tg3 *tp)
11043{
11044 del_timer_sync(&tp->timer);
11045}
11046
11047/* Restart hardware after configuration changes, self-test, etc.
11048 * Invoked with tp->lock held.
11049 */
953c96e0 11050static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 11051 __releases(tp->lock)
11052 __acquires(tp->lock)
11053{
11054 int err;
11055
11056 err = tg3_init_hw(tp, reset_phy);
11057 if (err) {
11058 netdev_err(tp->dev,
11059 "Failed to re-initialize device, aborting\n");
11060 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11061 tg3_full_unlock(tp);
11062 tg3_timer_stop(tp);
11063 tp->irq_sync = 0;
11064 tg3_napi_enable(tp);
11065 dev_close(tp->dev);
11066 tg3_full_lock(tp, 0);
11067 }
11068 return err;
11069}
11070
11071static void tg3_reset_task(struct work_struct *work)
11072{
11073 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11074 int err;
11075
11076 tg3_full_lock(tp, 0);
11077
11078 if (!netif_running(tp->dev)) {
11079 tg3_flag_clear(tp, RESET_TASK_PENDING);
11080 tg3_full_unlock(tp);
11081 return;
11082 }
11083
11084 tg3_full_unlock(tp);
11085
11086 tg3_phy_stop(tp);
11087
11088 tg3_netif_stop(tp);
11089
11090 tg3_full_lock(tp, 1);
11091
11092 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11093 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11094 tp->write32_rx_mbox = tg3_write_flush_reg32;
11095 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11096 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11097 }
11098
11099 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11100 err = tg3_init_hw(tp, true);
21f7638e
MC		 11101 if (err)
11102 goto out;
11103
11104 tg3_netif_start(tp);
11105
11106out:
11107 tg3_full_unlock(tp);
11108
11109 if (!err)
11110 tg3_phy_start(tp);
11111
11112 tg3_flag_clear(tp, RESET_TASK_PENDING);
11113}
11114
4f125f42 11115static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11116{
7d12e780 11117 irq_handler_t fn;
fcfa0a32 11118 unsigned long flags;
4f125f42
MC		 11119 char *name;
11120 struct tg3_napi *tnapi = &tp->napi[irq_num];
11121
11122 if (tp->irq_cnt == 1)
11123 name = tp->dev->name;
11124 else {
11125 name = &tnapi->irq_lbl[0];
21e315e1
NS		 11126 if (tnapi->tx_buffers && tnapi->rx_rcb)
11127 snprintf(name, IFNAMSIZ,
11128 "%s-txrx-%d", tp->dev->name, irq_num);
11129 else if (tnapi->tx_buffers)
11130 snprintf(name, IFNAMSIZ,
11131 "%s-tx-%d", tp->dev->name, irq_num);
11132 else if (tnapi->rx_rcb)
11133 snprintf(name, IFNAMSIZ,
11134 "%s-rx-%d", tp->dev->name, irq_num);
11135 else
11136 snprintf(name, IFNAMSIZ,
11137 "%s-%d", tp->dev->name, irq_num);
4f125f42
MC		 11138 name[IFNAMSIZ-1] = 0;
11139 }
fcfa0a32 11140
63c3a66f 11141 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11142 fn = tg3_msi;
63c3a66f 11143 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11144 fn = tg3_msi_1shot;
ab392d2d 11145 flags = 0;
fcfa0a32
MC		 11146 } else {
11147 fn = tg3_interrupt;
63c3a66f 11148 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11149 fn = tg3_interrupt_tagged;
ab392d2d 11150 flags = IRQF_SHARED;
fcfa0a32 11151 }
4f125f42
MC		 11152
11153 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11154}
11155
7938109f
MC		 11156static int tg3_test_interrupt(struct tg3 *tp)
11157{
09943a18 11158 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11159 struct net_device *dev = tp->dev;
b16250e3 11160 int err, i, intr_ok = 0;
f6eb9b1f 11161 u32 val;
7938109f 11162
d4bc3927
MC		 11163 if (!netif_running(dev))
11164 return -ENODEV;
11165
7938109f
MC		 11166 tg3_disable_ints(tp);
11167
4f125f42 11168 free_irq(tnapi->irq_vec, tnapi);
7938109f 11169
f6eb9b1f
MC		 11170 /*
11171 * Turn off MSI one shot mode. Otherwise this test has no
11172 * observable way to know whether the interrupt was delivered.
11173 */
3aa1cdf8 11174 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11175 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11176 tw32(MSGINT_MODE, val);
11177 }
11178
4f125f42 11179 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11180 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11181 if (err)
11182 return err;
11183
898a56f8 11184 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11185 tg3_enable_ints(tp);
11186
11187 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11188 tnapi->coal_now);
7938109f
MC		 11189
11190 for (i = 0; i < 5; i++) {
b16250e3
MC		 11191 u32 int_mbox, misc_host_ctrl;
11192
898a56f8 11193 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11194 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11195
11196 if ((int_mbox != 0) ||
11197 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11198 intr_ok = 1;
7938109f 11199 break;
b16250e3
MC		 11200 }
11201
3aa1cdf8
MC		 11202 if (tg3_flag(tp, 57765_PLUS) &&
11203 tnapi->hw_status->status_tag != tnapi->last_tag)
11204 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11205
7938109f
MC		 11206 msleep(10);
11207 }
11208
11209 tg3_disable_ints(tp);
11210
4f125f42 11211 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11212
4f125f42 11213 err = tg3_request_irq(tp, 0);
7938109f
MC		 11214
11215 if (err)
11216 return err;
11217
f6eb9b1f
MC		 11218 if (intr_ok) {
11219 /* Reenable MSI one shot mode. */
5b39de91 11220 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11221 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11222 tw32(MSGINT_MODE, val);
11223 }
7938109f 11224 return 0;
f6eb9b1f 11225 }
7938109f
MC		 11226
11227 return -EIO;
11228}
11229
11230/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11231 * successfully restored
11232 */
11233static int tg3_test_msi(struct tg3 *tp)
11234{
7938109f
MC		 11235 int err;
11236 u16 pci_cmd;
11237
63c3a66f 11238 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11239 return 0;
11240
11241 /* Turn off SERR reporting in case MSI terminates with Master
11242 * Abort.
11243 */
11244 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11245 pci_write_config_word(tp->pdev, PCI_COMMAND,
11246 pci_cmd & ~PCI_COMMAND_SERR);
11247
11248 err = tg3_test_interrupt(tp);
11249
11250 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11251
11252 if (!err)
11253 return 0;
11254
11255 /* other failures */
11256 if (err != -EIO)
11257 return err;
11258
11259 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11260 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11261 "to INTx mode. Please report this failure to the PCI "
11262 "maintainer and include system chipset information\n");
7938109f 11263
4f125f42 11264 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11265
7938109f
MC		 11266 pci_disable_msi(tp->pdev);
11267
63c3a66f 11268 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11269 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11270
4f125f42 11271 err = tg3_request_irq(tp, 0);
7938109f
MC		 11272 if (err)
11273 return err;
11274
11275 /* Need to reset the chip because the MSI cycle may have terminated
11276 * with Master Abort.
11277 */
f47c11ee 11278 tg3_full_lock(tp, 1);
7938109f 11279
944d980e 11280 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11281 err = tg3_init_hw(tp, true);
7938109f 11282
f47c11ee 11283 tg3_full_unlock(tp);
7938109f
MC		 11284
11285 if (err)
4f125f42 11286 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11287
11288 return err;
11289}
11290
9e9fd12d
MC		 11291static int tg3_request_firmware(struct tg3 *tp)
11292{
77997ea3 11293 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11294
11295 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11296 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11297 tp->fw_needed);
9e9fd12d
MC		 11298 return -ENOENT;
11299 }
11300
77997ea3 11301 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11302
11303 /* Firmware blob starts with version numbers, followed by
11304 * start address and _full_ length including BSS sections
11305 * (which must be longer than the actual data, of course
11306 */
11307
77997ea3
NS		 11308 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11309 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11310 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11311 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11312 release_firmware(tp->fw);
11313 tp->fw = NULL;
11314 return -EINVAL;
11315 }
11316
11317 /* We no longer need firmware; we have it. */
11318 tp->fw_needed = NULL;
11319 return 0;
11320}
11321
9102426a 11322static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11323{
9102426a 11324 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11325
9102426a 11326 if (irq_cnt > 1) {
c3b5003b
MC		 11327 /* We want as many rx rings enabled as there are cpus.
11328 * In multiqueue MSI-X mode, the first MSI-X vector
11329 * only deals with link interrupts, etc, so we add
11330 * one to the number of vectors we are requesting.
11331 */
9102426a 11332 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11333 }
679563f4 11334
9102426a
MC		 11335 return irq_cnt;
11336}
11337
11338static bool tg3_enable_msix(struct tg3 *tp)
11339{
11340 int i, rc;
86449944 11341 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11342
0968169c
MC		 11343 tp->txq_cnt = tp->txq_req;
11344 tp->rxq_cnt = tp->rxq_req;
11345 if (!tp->rxq_cnt)
11346 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11347 if (tp->rxq_cnt > tp->rxq_max)
11348 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11349
11350 /* Disable multiple TX rings by default. Simple round-robin hardware
11351 * scheduling of the TX rings can cause starvation of rings with
11352 * small packets when other rings have TSO or jumbo packets.
11353 */
11354 if (!tp->txq_req)
11355 tp->txq_cnt = 1;
9102426a
MC		 11356
11357 tp->irq_cnt = tg3_irq_count(tp);
11358
679563f4
MC		 11359 for (i = 0; i < tp->irq_max; i++) {
11360 msix_ent[i].entry = i;
11361 msix_ent[i].vector = 0;
11362 }
11363
6f1f411a 11364 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
2430b031
MC		 11365 if (rc < 0) {
11366 return false;
6f1f411a 11367 } else if (rc < tp->irq_cnt) {
05dbe005
JP		 11368 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11369 tp->irq_cnt, rc);
679563f4 11370 tp->irq_cnt = rc;
49a359e3 11371 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11372 if (tp->txq_cnt)
11373 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11374 }
11375
11376 for (i = 0; i < tp->irq_max; i++)
11377 tp->napi[i].irq_vec = msix_ent[i].vector;
11378
49a359e3 11379 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11380 pci_disable_msix(tp->pdev);
11381 return false;
11382 }
b92b9040 11383
9102426a
MC		 11384 if (tp->irq_cnt == 1)
11385 return true;
d78b59f5 11386
9102426a
MC		 11387 tg3_flag_set(tp, ENABLE_RSS);
11388
11389 if (tp->txq_cnt > 1)
11390 tg3_flag_set(tp, ENABLE_TSS);
11391
11392 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11393
679563f4
MC		 11394 return true;
11395}
11396
07b0173c
MC		 11397static void tg3_ints_init(struct tg3 *tp)
11398{
63c3a66f
JP		 11399 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11400 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11401 /* All MSI supporting chips should support tagged
11402 * status. Assert that this is the case.
11403 */
5129c3a3
MC		 11404 netdev_warn(tp->dev,
11405 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11406 goto defcfg;
07b0173c 11407 }
4f125f42 11408
63c3a66f
JP		 11409 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11410 tg3_flag_set(tp, USING_MSIX);
11411 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11412 tg3_flag_set(tp, USING_MSI);
679563f4 11413
63c3a66f 11414 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11415 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11416 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11417 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11418 if (!tg3_flag(tp, 1SHOT_MSI))
11419 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11420 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11421 }
11422defcfg:
63c3a66f 11423 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11424 tp->irq_cnt = 1;
11425 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11426 }
11427
11428 if (tp->irq_cnt == 1) {
11429 tp->txq_cnt = 1;
11430 tp->rxq_cnt = 1;
2ddaad39 11431 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11432 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11433 }
07b0173c
MC		 11434}
11435
11436static void tg3_ints_fini(struct tg3 *tp)
11437{
63c3a66f 11438 if (tg3_flag(tp, USING_MSIX))
679563f4 11439 pci_disable_msix(tp->pdev);
63c3a66f 11440 else if (tg3_flag(tp, USING_MSI))
679563f4 11441 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11442 tg3_flag_clear(tp, USING_MSI);
11443 tg3_flag_clear(tp, USING_MSIX);
11444 tg3_flag_clear(tp, ENABLE_RSS);
11445 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11446}
11447
be947307
MC		 11448static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11449 bool init)
1da177e4 11450{
d8f4cd38 11451 struct net_device *dev = tp->dev;
4f125f42 11452 int i, err;
1da177e4 11453
679563f4
MC		 11454 /*
11455 * Setup interrupts first so we know how
11456 * many NAPI resources to allocate
11457 */
11458 tg3_ints_init(tp);
11459
90415477 11460 tg3_rss_check_indir_tbl(tp);
bcebcc46 11461
1da177e4
LT		 11462 /* The placement of this call is tied
11463 * to the setup and use of Host TX descriptors.
11464 */
11465 err = tg3_alloc_consistent(tp);
11466 if (err)
4a5f46f2 11467 goto out_ints_fini;
88b06bc2 11468
66cfd1bd
MC		 11469 tg3_napi_init(tp);
11470
fed97810 11471 tg3_napi_enable(tp);
1da177e4 11472
4f125f42
MC		 11473 for (i = 0; i < tp->irq_cnt; i++) {
11474 struct tg3_napi *tnapi = &tp->napi[i];
11475 err = tg3_request_irq(tp, i);
11476 if (err) {
5bc09186
MC		 11477 for (i--; i >= 0; i--) {
11478 tnapi = &tp->napi[i];
4f125f42 11479 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11480 }
4a5f46f2 11481 goto out_napi_fini;
4f125f42
MC		 11482 }
11483 }
1da177e4 11484
f47c11ee 11485 tg3_full_lock(tp, 0);
1da177e4 11486
2e460fc0
NS		 11487 if (init)
11488 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11489
d8f4cd38 11490 err = tg3_init_hw(tp, reset_phy);
1da177e4 11491 if (err) {
944d980e 11492 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11493 tg3_free_rings(tp);
1da177e4
LT		 11494 }
11495
f47c11ee 11496 tg3_full_unlock(tp);
1da177e4 11497
07b0173c 11498 if (err)
4a5f46f2 11499 goto out_free_irq;
1da177e4 11500
d8f4cd38 11501 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11502 err = tg3_test_msi(tp);
fac9b83e 11503
7938109f 11504 if (err) {
f47c11ee 11505 tg3_full_lock(tp, 0);
944d980e 11506 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11507 tg3_free_rings(tp);
f47c11ee 11508 tg3_full_unlock(tp);
7938109f 11509
4a5f46f2 11510 goto out_napi_fini;
7938109f 11511 }
fcfa0a32 11512
63c3a66f 11513 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11514 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11515
f6eb9b1f
MC		 11516 tw32(PCIE_TRANSACTION_CFG,
11517 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11518 }
7938109f
MC		 11519 }
11520
b02fd9e3
MC		 11521 tg3_phy_start(tp);
11522
aed93e0b
MC		 11523 tg3_hwmon_open(tp);
11524
f47c11ee 11525 tg3_full_lock(tp, 0);
1da177e4 11526
21f7638e 11527 tg3_timer_start(tp);
63c3a66f 11528 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11529 tg3_enable_ints(tp);
11530
be947307
MC		 11531 if (init)
11532 tg3_ptp_init(tp);
11533 else
11534 tg3_ptp_resume(tp);
11535
11536
f47c11ee 11537 tg3_full_unlock(tp);
1da177e4 11538
fe5f5787 11539 netif_tx_start_all_queues(dev);
1da177e4 11540
06c03c02
MB		 11541 /*
11542 * Reset loopback feature if it was turned on while the device was down
11543 * make sure that it's installed properly now.
11544 */
11545 if (dev->features & NETIF_F_LOOPBACK)
11546 tg3_set_loopback(dev, dev->features);
11547
1da177e4 11548 return 0;
07b0173c 11549
4a5f46f2 11550out_free_irq:
4f125f42
MC		 11551 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11552 struct tg3_napi *tnapi = &tp->napi[i];
11553 free_irq(tnapi->irq_vec, tnapi);
11554 }
07b0173c 11555
4a5f46f2 11556out_napi_fini:
fed97810 11557 tg3_napi_disable(tp);
66cfd1bd 11558 tg3_napi_fini(tp);
07b0173c 11559 tg3_free_consistent(tp);
679563f4 11560
4a5f46f2 11561out_ints_fini:
679563f4 11562 tg3_ints_fini(tp);
d8f4cd38 11563
07b0173c 11564 return err;
1da177e4
LT		 11565}
11566
65138594 11567static void tg3_stop(struct tg3 *tp)
1da177e4 11568{
4f125f42 11569 int i;
1da177e4 11570
db219973 11571 tg3_reset_task_cancel(tp);
bd473da3 11572 tg3_netif_stop(tp);
1da177e4 11573
21f7638e 11574 tg3_timer_stop(tp);
1da177e4 11575
aed93e0b
MC		 11576 tg3_hwmon_close(tp);
11577
24bb4fb6
MC		 11578 tg3_phy_stop(tp);
11579
f47c11ee 11580 tg3_full_lock(tp, 1);
1da177e4
LT		 11581
11582 tg3_disable_ints(tp);
11583
944d980e 11584 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11585 tg3_free_rings(tp);
63c3a66f 11586 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11587
f47c11ee 11588 tg3_full_unlock(tp);
1da177e4 11589
4f125f42
MC		 11590 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11591 struct tg3_napi *tnapi = &tp->napi[i];
11592 free_irq(tnapi->irq_vec, tnapi);
11593 }
07b0173c
MC		 11594
11595 tg3_ints_fini(tp);
1da177e4 11596
66cfd1bd
MC		 11597 tg3_napi_fini(tp);
11598
1da177e4 11599 tg3_free_consistent(tp);
65138594
MC		 11600}
11601
d8f4cd38
MC		 11602static int tg3_open(struct net_device *dev)
11603{
11604 struct tg3 *tp = netdev_priv(dev);
11605 int err;
11606
11607 if (tp->fw_needed) {
11608 err = tg3_request_firmware(tp);
c4dab506
NS		 11609 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11610 if (err) {
11611 netdev_warn(tp->dev, "EEE capability disabled\n");
11612 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11613 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11614 netdev_warn(tp->dev, "EEE capability restored\n");
11615 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11616 }
11617 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11618 if (err)
11619 return err;
11620 } else if (err) {
11621 netdev_warn(tp->dev, "TSO capability disabled\n");
11622 tg3_flag_clear(tp, TSO_CAPABLE);
11623 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11624 netdev_notice(tp->dev, "TSO capability restored\n");
11625 tg3_flag_set(tp, TSO_CAPABLE);
11626 }
11627 }
11628
f4a46d1f 11629 tg3_carrier_off(tp);
d8f4cd38
MC		 11630
11631 err = tg3_power_up(tp);
11632 if (err)
11633 return err;
11634
11635 tg3_full_lock(tp, 0);
11636
11637 tg3_disable_ints(tp);
11638 tg3_flag_clear(tp, INIT_COMPLETE);
11639
11640 tg3_full_unlock(tp);
11641
942d1af0
NS		 11642 err = tg3_start(tp,
11643 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11644 true, true);
d8f4cd38
MC		 11645 if (err) {
11646 tg3_frob_aux_power(tp, false);
11647 pci_set_power_state(tp->pdev, PCI_D3hot);
11648 }
be947307 11649
7d41e49a
MC		 11650 if (tg3_flag(tp, PTP_CAPABLE)) {
11651 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11652 &tp->pdev->dev);
11653 if (IS_ERR(tp->ptp_clock))
11654 tp->ptp_clock = NULL;
11655 }
11656
07b0173c 11657 return err;
1da177e4
LT		 11658}
11659
1da177e4
LT		 11660static int tg3_close(struct net_device *dev)
11661{
11662 struct tg3 *tp = netdev_priv(dev);
11663
be947307
MC		 11664 tg3_ptp_fini(tp);
11665
65138594 11666 tg3_stop(tp);
1da177e4 11667
92feeabf
MC		 11668 /* Clear stats across close / open calls */
11669 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11670 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11671
8496e85c
RW		 11672 if (pci_device_is_present(tp->pdev)) {
11673 tg3_power_down_prepare(tp);
bc1c7567 11674
8496e85c
RW		 11675 tg3_carrier_off(tp);
11676 }
1da177e4
LT		 11677 return 0;
11678}
11679
511d2224 11680static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11681{
11682 return ((u64)val->high << 32) | ((u64)val->low);
11683}
11684
65ec698d 11685static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11686{
11687 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11688
f07e9af3 11689 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11690 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11691 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11692 u32 val;
11693
569a5df8
MC		 11694 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11695 tg3_writephy(tp, MII_TG3_TEST1,
11696 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11697 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11698 } else
11699 val = 0;
1da177e4
LT		 11700
11701 tp->phy_crc_errors += val;
11702
11703 return tp->phy_crc_errors;
11704 }
11705
11706 return get_stat64(&hw_stats->rx_fcs_errors);
11707}
11708
11709#define ESTAT_ADD(member) \
11710 estats->member = old_estats->member + \
511d2224 11711 get_stat64(&hw_stats->member)
1da177e4 11712
65ec698d 11713static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11714{
1da177e4
LT		 11715 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11716 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11717
1da177e4
LT		 11718 ESTAT_ADD(rx_octets);
11719 ESTAT_ADD(rx_fragments);
11720 ESTAT_ADD(rx_ucast_packets);
11721 ESTAT_ADD(rx_mcast_packets);
11722 ESTAT_ADD(rx_bcast_packets);
11723 ESTAT_ADD(rx_fcs_errors);
11724 ESTAT_ADD(rx_align_errors);
11725 ESTAT_ADD(rx_xon_pause_rcvd);
11726 ESTAT_ADD(rx_xoff_pause_rcvd);
11727 ESTAT_ADD(rx_mac_ctrl_rcvd);
11728 ESTAT_ADD(rx_xoff_entered);
11729 ESTAT_ADD(rx_frame_too_long_errors);
11730 ESTAT_ADD(rx_jabbers);
11731 ESTAT_ADD(rx_undersize_packets);
11732 ESTAT_ADD(rx_in_length_errors);
11733 ESTAT_ADD(rx_out_length_errors);
11734 ESTAT_ADD(rx_64_or_less_octet_packets);
11735 ESTAT_ADD(rx_65_to_127_octet_packets);
11736 ESTAT_ADD(rx_128_to_255_octet_packets);
11737 ESTAT_ADD(rx_256_to_511_octet_packets);
11738 ESTAT_ADD(rx_512_to_1023_octet_packets);
11739 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11740 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11741 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11742 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11743 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11744
11745 ESTAT_ADD(tx_octets);
11746 ESTAT_ADD(tx_collisions);
11747 ESTAT_ADD(tx_xon_sent);
11748 ESTAT_ADD(tx_xoff_sent);
11749 ESTAT_ADD(tx_flow_control);
11750 ESTAT_ADD(tx_mac_errors);
11751 ESTAT_ADD(tx_single_collisions);
11752 ESTAT_ADD(tx_mult_collisions);
11753 ESTAT_ADD(tx_deferred);
11754 ESTAT_ADD(tx_excessive_collisions);
11755 ESTAT_ADD(tx_late_collisions);
11756 ESTAT_ADD(tx_collide_2times);
11757 ESTAT_ADD(tx_collide_3times);
11758 ESTAT_ADD(tx_collide_4times);
11759 ESTAT_ADD(tx_collide_5times);
11760 ESTAT_ADD(tx_collide_6times);
11761 ESTAT_ADD(tx_collide_7times);
11762 ESTAT_ADD(tx_collide_8times);
11763 ESTAT_ADD(tx_collide_9times);
11764 ESTAT_ADD(tx_collide_10times);
11765 ESTAT_ADD(tx_collide_11times);
11766 ESTAT_ADD(tx_collide_12times);
11767 ESTAT_ADD(tx_collide_13times);
11768 ESTAT_ADD(tx_collide_14times);
11769 ESTAT_ADD(tx_collide_15times);
11770 ESTAT_ADD(tx_ucast_packets);
11771 ESTAT_ADD(tx_mcast_packets);
11772 ESTAT_ADD(tx_bcast_packets);
11773 ESTAT_ADD(tx_carrier_sense_errors);
11774 ESTAT_ADD(tx_discards);
11775 ESTAT_ADD(tx_errors);
11776
11777 ESTAT_ADD(dma_writeq_full);
11778 ESTAT_ADD(dma_write_prioq_full);
11779 ESTAT_ADD(rxbds_empty);
11780 ESTAT_ADD(rx_discards);
11781 ESTAT_ADD(rx_errors);
11782 ESTAT_ADD(rx_threshold_hit);
11783
11784 ESTAT_ADD(dma_readq_full);
11785 ESTAT_ADD(dma_read_prioq_full);
11786 ESTAT_ADD(tx_comp_queue_full);
11787
11788 ESTAT_ADD(ring_set_send_prod_index);
11789 ESTAT_ADD(ring_status_update);
11790 ESTAT_ADD(nic_irqs);
11791 ESTAT_ADD(nic_avoided_irqs);
11792 ESTAT_ADD(nic_tx_threshold_hit);
11793
4452d099 11794 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11795}
11796
65ec698d 11797static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11798{
511d2224 11799 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11800 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11801
1da177e4
LT		 11802 stats->rx_packets = old_stats->rx_packets +
11803 get_stat64(&hw_stats->rx_ucast_packets) +
11804 get_stat64(&hw_stats->rx_mcast_packets) +
11805 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11806
1da177e4
LT		 11807 stats->tx_packets = old_stats->tx_packets +
11808 get_stat64(&hw_stats->tx_ucast_packets) +
11809 get_stat64(&hw_stats->tx_mcast_packets) +
11810 get_stat64(&hw_stats->tx_bcast_packets);
11811
11812 stats->rx_bytes = old_stats->rx_bytes +
11813 get_stat64(&hw_stats->rx_octets);
11814 stats->tx_bytes = old_stats->tx_bytes +
11815 get_stat64(&hw_stats->tx_octets);
11816
11817 stats->rx_errors = old_stats->rx_errors +
4f63b877 11818 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11819 stats->tx_errors = old_stats->tx_errors +
11820 get_stat64(&hw_stats->tx_errors) +
11821 get_stat64(&hw_stats->tx_mac_errors) +
11822 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11823 get_stat64(&hw_stats->tx_discards);
11824
11825 stats->multicast = old_stats->multicast +
11826 get_stat64(&hw_stats->rx_mcast_packets);
11827 stats->collisions = old_stats->collisions +
11828 get_stat64(&hw_stats->tx_collisions);
11829
11830 stats->rx_length_errors = old_stats->rx_length_errors +
11831 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11832 get_stat64(&hw_stats->rx_undersize_packets);
11833
1da177e4
LT		 11834 stats->rx_frame_errors = old_stats->rx_frame_errors +
11835 get_stat64(&hw_stats->rx_align_errors);
11836 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11837 get_stat64(&hw_stats->tx_discards);
11838 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11839 get_stat64(&hw_stats->tx_carrier_sense_errors);
11840
11841 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11842 tg3_calc_crc_errors(tp);
1da177e4 11843
4f63b877
JL		 11844 stats->rx_missed_errors = old_stats->rx_missed_errors +
11845 get_stat64(&hw_stats->rx_discards);
11846
b0057c51 11847 stats->rx_dropped = tp->rx_dropped;
48855432 11848 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11849}
11850
1da177e4
LT		 11851static int tg3_get_regs_len(struct net_device *dev)
11852{
97bd8e49 11853 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11854}
11855
11856static void tg3_get_regs(struct net_device *dev,
11857 struct ethtool_regs *regs, void *_p)
11858{
1da177e4 11859 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11860
11861 regs->version = 0;
11862
97bd8e49 11863 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11864
80096068 11865 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11866 return;
11867
f47c11ee 11868 tg3_full_lock(tp, 0);
1da177e4 11869
97bd8e49 11870 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11871
f47c11ee 11872 tg3_full_unlock(tp);
1da177e4
LT		 11873}
11874
11875static int tg3_get_eeprom_len(struct net_device *dev)
11876{
11877 struct tg3 *tp = netdev_priv(dev);
11878
11879 return tp->nvram_size;
11880}
11881
1da177e4
LT		 11882static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11883{
11884 struct tg3 *tp = netdev_priv(dev);
11885 int ret;
11886 u8 *pd;
b9fc7dc5 11887 u32 i, offset, len, b_offset, b_count;
a9dc529d 11888 __be32 val;
1da177e4 11889
63c3a66f 11890 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11891 return -EINVAL;
11892
1da177e4
LT		 11893 offset = eeprom->offset;
11894 len = eeprom->len;
11895 eeprom->len = 0;
11896
11897 eeprom->magic = TG3_EEPROM_MAGIC;
11898
11899 if (offset & 3) {
11900 /* adjustments to start on required 4 byte boundary */
11901 b_offset = offset & 3;
11902 b_count = 4 - b_offset;
11903 if (b_count > len) {
11904 /* i.e. offset=1 len=2 */
11905 b_count = len;
11906 }
a9dc529d 11907 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 11908 if (ret)
11909 return ret;
be98da6a 11910 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11911 len -= b_count;
11912 offset += b_count;
c6cdf436 11913 eeprom->len += b_count;
1da177e4
LT		 11914 }
11915
25985edc 11916 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11917 pd = &data[eeprom->len];
11918 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11919 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 11920 if (ret) {
11921 eeprom->len += i;
11922 return ret;
11923 }
1da177e4
LT		 11924 memcpy(pd + i, &val, 4);
11925 }
11926 eeprom->len += i;
11927
11928 if (len & 3) {
11929 /* read last bytes not ending on 4 byte boundary */
11930 pd = &data[eeprom->len];
11931 b_count = len & 3;
11932 b_offset = offset + len - b_count;
a9dc529d 11933 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 11934 if (ret)
11935 return ret;
b9fc7dc5 11936 memcpy(pd, &val, b_count);
1da177e4
LT		 11937 eeprom->len += b_count;
11938 }
11939 return 0;
11940}
11941
1da177e4
LT		 11942static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11943{
11944 struct tg3 *tp = netdev_priv(dev);
11945 int ret;
b9fc7dc5 11946 u32 offset, len, b_offset, odd_len;
1da177e4 11947 u8 *buf;
a9dc529d 11948 __be32 start, end;
1da177e4 11949
63c3a66f 11950 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 11951 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 11952 return -EINVAL;
11953
11954 offset = eeprom->offset;
11955 len = eeprom->len;
11956
11957 if ((b_offset = (offset & 3))) {
11958 /* adjustments to start on required 4 byte boundary */
a9dc529d 11959 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 11960 if (ret)
11961 return ret;
1da177e4
LT		 11962 len += b_offset;
11963 offset &= ~3;
1c8594b4
MC		 11964 if (len < 4)
11965 len = 4;
1da177e4
LT		 11966 }
11967
11968 odd_len = 0;
1c8594b4 11969 if (len & 3) {
1da177e4
LT		 11970 /* adjustments to end on required 4 byte boundary */
11971 odd_len = 1;
11972 len = (len + 3) & ~3;
a9dc529d 11973 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 11974 if (ret)
11975 return ret;
1da177e4
LT		 11976 }
11977
11978 buf = data;
11979 if (b_offset || odd_len) {
11980 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 11981 if (!buf)
1da177e4
LT		 11982 return -ENOMEM;
11983 if (b_offset)
11984 memcpy(buf, &start, 4);
11985 if (odd_len)
11986 memcpy(buf+len-4, &end, 4);
11987 memcpy(buf + b_offset, data, eeprom->len);
11988 }
11989
11990 ret = tg3_nvram_write_block(tp, offset, len, buf);
11991
11992 if (buf != data)
11993 kfree(buf);
11994
11995 return ret;
11996}
11997
11998static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11999{
b02fd9e3
MC		 12000 struct tg3 *tp = netdev_priv(dev);
12001
63c3a66f 12002 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12003 struct phy_device *phydev;
f07e9af3 12004 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12005 return -EAGAIN;
ead2402c 12006 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12007 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 12008 }
6aa20a22 12009
1da177e4
LT		 12010 cmd->supported = (SUPPORTED_Autoneg);
12011
f07e9af3 12012 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 12013 cmd->supported |= (SUPPORTED_1000baseT_Half |
12014 SUPPORTED_1000baseT_Full);
12015
f07e9af3 12016 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 12017 cmd->supported |= (SUPPORTED_100baseT_Half |
12018 SUPPORTED_100baseT_Full |
12019 SUPPORTED_10baseT_Half |
12020 SUPPORTED_10baseT_Full |
3bebab59 12021 SUPPORTED_TP);
ef348144
KK		 12022 cmd->port = PORT_TP;
12023 } else {
1da177e4 12024 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 12025 cmd->port = PORT_FIBRE;
12026 }
6aa20a22 12027
1da177e4 12028 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 12029 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12030 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12031 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12032 cmd->advertising |= ADVERTISED_Pause;
12033 } else {
12034 cmd->advertising |= ADVERTISED_Pause |
12035 ADVERTISED_Asym_Pause;
12036 }
12037 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12038 cmd->advertising |= ADVERTISED_Asym_Pause;
12039 }
12040 }
f4a46d1f 12041 if (netif_running(dev) && tp->link_up) {
70739497 12042 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 12043 cmd->duplex = tp->link_config.active_duplex;
859edb26 12044 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 12045 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12046 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12047 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12048 else
12049 cmd->eth_tp_mdix = ETH_TP_MDI;
12050 }
64c22182 12051 } else {
e740522e
MC		 12052 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12053 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 12054 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 12055 }
882e9793 12056 cmd->phy_address = tp->phy_addr;
7e5856bd 12057 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 12058 cmd->autoneg = tp->link_config.autoneg;
12059 cmd->maxtxpkt = 0;
12060 cmd->maxrxpkt = 0;
12061 return 0;
12062}
6aa20a22 12063
1da177e4
LT		 12064static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12065{
12066 struct tg3 *tp = netdev_priv(dev);
25db0338 12067 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 12068
63c3a66f 12069 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12070 struct phy_device *phydev;
f07e9af3 12071 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12072 return -EAGAIN;
ead2402c 12073 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12074 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 12075 }
12076
7e5856bd
MC		 12077 if (cmd->autoneg != AUTONEG_ENABLE &&
12078 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 12079 return -EINVAL;
7e5856bd
MC		 12080
12081 if (cmd->autoneg == AUTONEG_DISABLE &&
12082 cmd->duplex != DUPLEX_FULL &&
12083 cmd->duplex != DUPLEX_HALF)
37ff238d 12084 return -EINVAL;
1da177e4 12085
7e5856bd
MC		 12086 if (cmd->autoneg == AUTONEG_ENABLE) {
12087 u32 mask = ADVERTISED_Autoneg |
12088 ADVERTISED_Pause |
12089 ADVERTISED_Asym_Pause;
12090
f07e9af3 12091 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 12092 mask |= ADVERTISED_1000baseT_Half |
12093 ADVERTISED_1000baseT_Full;
12094
f07e9af3 12095 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12096 mask |= ADVERTISED_100baseT_Half |
12097 ADVERTISED_100baseT_Full |
12098 ADVERTISED_10baseT_Half |
12099 ADVERTISED_10baseT_Full |
12100 ADVERTISED_TP;
12101 else
12102 mask |= ADVERTISED_FIBRE;
12103
12104 if (cmd->advertising & ~mask)
12105 return -EINVAL;
12106
12107 mask &= (ADVERTISED_1000baseT_Half |
12108 ADVERTISED_1000baseT_Full |
12109 ADVERTISED_100baseT_Half |
12110 ADVERTISED_100baseT_Full |
12111 ADVERTISED_10baseT_Half |
12112 ADVERTISED_10baseT_Full);
12113
12114 cmd->advertising &= mask;
12115 } else {
f07e9af3 12116 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12117 if (speed != SPEED_1000)
7e5856bd
MC		 12118 return -EINVAL;
12119
12120 if (cmd->duplex != DUPLEX_FULL)
12121 return -EINVAL;
12122 } else {
25db0338
DD		 12123 if (speed != SPEED_100 &&
12124 speed != SPEED_10)
7e5856bd
MC		 12125 return -EINVAL;
12126 }
12127 }
12128
f47c11ee 12129 tg3_full_lock(tp, 0);
1da177e4
LT		 12130
12131 tp->link_config.autoneg = cmd->autoneg;
12132 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12133 tp->link_config.advertising = (cmd->advertising |
12134 ADVERTISED_Autoneg);
e740522e
MC		 12135 tp->link_config.speed = SPEED_UNKNOWN;
12136 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12137 } else {
12138 tp->link_config.advertising = 0;
25db0338 12139 tp->link_config.speed = speed;
1da177e4 12140 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12141 }
6aa20a22 12142
fdad8de4
NS		 12143 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12144
ce20f161
NS		 12145 tg3_warn_mgmt_link_flap(tp);
12146
1da177e4 12147 if (netif_running(dev))
953c96e0 12148 tg3_setup_phy(tp, true);
1da177e4 12149
f47c11ee 12150 tg3_full_unlock(tp);
6aa20a22 12151
1da177e4
LT		 12152 return 0;
12153}
6aa20a22 12154
1da177e4
LT		 12155static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12156{
12157 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12158
68aad78c
RJ		 12159 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12160 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12161 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12162 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12163}
6aa20a22 12164
1da177e4
LT		 12165static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12166{
12167 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12168
63c3a66f 12169 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12170 wol->supported = WAKE_MAGIC;
12171 else
12172 wol->supported = 0;
1da177e4 12173 wol->wolopts = 0;
63c3a66f 12174 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12175 wol->wolopts = WAKE_MAGIC;
12176 memset(&wol->sopass, 0, sizeof(wol->sopass));
12177}
6aa20a22 12178
1da177e4
LT		 12179static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12180{
12181 struct tg3 *tp = netdev_priv(dev);
12dac075 12182 struct device *dp = &tp->pdev->dev;
6aa20a22 12183
1da177e4
LT		 12184 if (wol->wolopts & ~WAKE_MAGIC)
12185 return -EINVAL;
12186 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12187 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12188 return -EINVAL;
6aa20a22 12189
f2dc0d18
RW		 12190 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12191
f2dc0d18 12192 if (device_may_wakeup(dp))
63c3a66f 12193 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12194 else
63c3a66f 12195 tg3_flag_clear(tp, WOL_ENABLE);
6aa20a22 12196
1da177e4
LT		 12197 return 0;
12198}
6aa20a22 12199
1da177e4
LT		 12200static u32 tg3_get_msglevel(struct net_device *dev)
12201{
12202 struct tg3 *tp = netdev_priv(dev);
12203 return tp->msg_enable;
12204}
6aa20a22 12205
1da177e4
LT		 12206static void tg3_set_msglevel(struct net_device *dev, u32 value)
12207{
12208 struct tg3 *tp = netdev_priv(dev);
12209 tp->msg_enable = value;
12210}
6aa20a22 12211
1da177e4
LT		 12212static int tg3_nway_reset(struct net_device *dev)
12213{
12214 struct tg3 *tp = netdev_priv(dev);
1da177e4 12215 int r;
6aa20a22 12216
1da177e4
LT		 12217 if (!netif_running(dev))
12218 return -EAGAIN;
12219
f07e9af3 12220 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12221 return -EINVAL;
12222
ce20f161
NS		 12223 tg3_warn_mgmt_link_flap(tp);
12224
63c3a66f 12225 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12226 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12227 return -EAGAIN;
ead2402c 12228 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 12229 } else {
12230 u32 bmcr;
12231
12232 spin_lock_bh(&tp->lock);
12233 r = -EINVAL;
12234 tg3_readphy(tp, MII_BMCR, &bmcr);
12235 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12236 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12237 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12238 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12239 BMCR_ANENABLE);
12240 r = 0;
12241 }
12242 spin_unlock_bh(&tp->lock);
1da177e4 12243 }
6aa20a22 12244
1da177e4
LT		 12245 return r;
12246}
6aa20a22 12247
1da177e4
LT		 12248static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12249{
12250 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12251
2c49a44d 12252 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12253 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12254 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12255 else
12256 ering->rx_jumbo_max_pending = 0;
12257
12258 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12259
12260 ering->rx_pending = tp->rx_pending;
63c3a66f 12261 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12262 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12263 else
12264 ering->rx_jumbo_pending = 0;
12265
f3f3f27e 12266 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12267}
6aa20a22 12268
1da177e4
LT		 12269static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12270{
12271 struct tg3 *tp = netdev_priv(dev);
646c9edd 12272 int i, irq_sync = 0, err = 0;
6aa20a22 12273
2c49a44d
MC		 12274 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12275 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12276 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12277 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12278 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12279 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12280 return -EINVAL;
6aa20a22 12281
bbe832c0 12282 if (netif_running(dev)) {
b02fd9e3 12283 tg3_phy_stop(tp);
1da177e4 12284 tg3_netif_stop(tp);
bbe832c0
MC		 12285 irq_sync = 1;
12286 }
1da177e4 12287
bbe832c0 12288 tg3_full_lock(tp, irq_sync);
6aa20a22 12289
1da177e4
LT		 12290 tp->rx_pending = ering->rx_pending;
12291
63c3a66f 12292 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12293 tp->rx_pending > 63)
12294 tp->rx_pending = 63;
12295 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12296
6fd45cb8 12297 for (i = 0; i < tp->irq_max; i++)
646c9edd 12298 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12299
12300 if (netif_running(dev)) {
944d980e 12301 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12302 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12303 if (!err)
12304 tg3_netif_start(tp);
1da177e4
LT		 12305 }
12306
f47c11ee 12307 tg3_full_unlock(tp);
6aa20a22 12308
b02fd9e3
MC		 12309 if (irq_sync && !err)
12310 tg3_phy_start(tp);
12311
b9ec6c1b 12312 return err;
1da177e4 12313}
6aa20a22 12314
1da177e4
LT		 12315static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12316{
12317 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12318
63c3a66f 12319 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12320
4a2db503 12321 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12322 epause->rx_pause = 1;
12323 else
12324 epause->rx_pause = 0;
12325
4a2db503 12326 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12327 epause->tx_pause = 1;
12328 else
12329 epause->tx_pause = 0;
1da177e4 12330}
6aa20a22 12331
1da177e4
LT		 12332static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12333{
12334 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12335 int err = 0;
6aa20a22 12336
ce20f161
NS		 12337 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12338 tg3_warn_mgmt_link_flap(tp);
12339
63c3a66f 12340 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12341 u32 newadv;
12342 struct phy_device *phydev;
1da177e4 12343
ead2402c 12344 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
f47c11ee 12345
2712168f
MC		 12346 if (!(phydev->supported & SUPPORTED_Pause) ||
12347 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12348 (epause->rx_pause != epause->tx_pause)))
2712168f 12349 return -EINVAL;
1da177e4 12350
2712168f
MC		 12351 tp->link_config.flowctrl = 0;
12352 if (epause->rx_pause) {
12353 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12354
12355 if (epause->tx_pause) {
12356 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12357 newadv = ADVERTISED_Pause;
b02fd9e3 12358 } else
2712168f
MC		 12359 newadv = ADVERTISED_Pause |
12360 ADVERTISED_Asym_Pause;
12361 } else if (epause->tx_pause) {
12362 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12363 newadv = ADVERTISED_Asym_Pause;
12364 } else
12365 newadv = 0;
12366
12367 if (epause->autoneg)
63c3a66f 12368 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12369 else
63c3a66f 12370 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12371
f07e9af3 12372 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12373 u32 oldadv = phydev->advertising &
12374 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12375 if (oldadv != newadv) {
12376 phydev->advertising &=
12377 ~(ADVERTISED_Pause |
12378 ADVERTISED_Asym_Pause);
12379 phydev->advertising |= newadv;
12380 if (phydev->autoneg) {
12381 /*
12382 * Always renegotiate the link to
12383 * inform our link partner of our
12384 * flow control settings, even if the
12385 * flow control is forced. Let
12386 * tg3_adjust_link() do the final
12387 * flow control setup.
12388 */
12389 return phy_start_aneg(phydev);
b02fd9e3 12390 }
b02fd9e3 12391 }
b02fd9e3 12392
2712168f 12393 if (!epause->autoneg)
b02fd9e3 12394 tg3_setup_flow_control(tp, 0, 0);
2712168f 12395 } else {
c6700ce2 12396 tp->link_config.advertising &=
2712168f
MC		 12397 ~(ADVERTISED_Pause |
12398 ADVERTISED_Asym_Pause);
c6700ce2 12399 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12400 }
12401 } else {
12402 int irq_sync = 0;
12403
12404 if (netif_running(dev)) {
12405 tg3_netif_stop(tp);
12406 irq_sync = 1;
12407 }
12408
12409 tg3_full_lock(tp, irq_sync);
12410
12411 if (epause->autoneg)
63c3a66f 12412 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12413 else
63c3a66f 12414 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12415 if (epause->rx_pause)
e18ce346 12416 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12417 else
e18ce346 12418 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12419 if (epause->tx_pause)
e18ce346 12420 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12421 else
e18ce346 12422 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12423
12424 if (netif_running(dev)) {
12425 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12426 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12427 if (!err)
12428 tg3_netif_start(tp);
12429 }
12430
12431 tg3_full_unlock(tp);
12432 }
6aa20a22 12433
fdad8de4
NS		 12434 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12435
b9ec6c1b 12436 return err;
1da177e4 12437}
6aa20a22 12438
de6f31eb 12439static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12440{
b9f2c044
JG		 12441 switch (sset) {
12442 case ETH_SS_TEST:
12443 return TG3_NUM_TEST;
12444 case ETH_SS_STATS:
12445 return TG3_NUM_STATS;
12446 default:
12447 return -EOPNOTSUPP;
12448 }
4cafd3f5
MC		 12449}
12450
90415477
MC		 12451static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12452 u32 *rules __always_unused)
12453{
12454 struct tg3 *tp = netdev_priv(dev);
12455
12456 if (!tg3_flag(tp, SUPPORT_MSIX))
12457 return -EOPNOTSUPP;
12458
12459 switch (info->cmd) {
12460 case ETHTOOL_GRXRINGS:
12461 if (netif_running(tp->dev))
9102426a 12462 info->data = tp->rxq_cnt;
90415477
MC		 12463 else {
12464 info->data = num_online_cpus();
9102426a
MC		 12465 if (info->data > TG3_RSS_MAX_NUM_QS)
12466 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12467 }
12468
12469 /* The first interrupt vector only
12470 * handles link interrupts.
12471 */
12472 info->data -= 1;
12473 return 0;
12474
12475 default:
12476 return -EOPNOTSUPP;
12477 }
12478}
12479
12480static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12481{
12482 u32 size = 0;
12483 struct tg3 *tp = netdev_priv(dev);
12484
12485 if (tg3_flag(tp, SUPPORT_MSIX))
12486 size = TG3_RSS_INDIR_TBL_SIZE;
12487
12488 return size;
12489}
12490
12491static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12492{
12493 struct tg3 *tp = netdev_priv(dev);
12494 int i;
12495
12496 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12497 indir[i] = tp->rss_ind_tbl[i];
12498
12499 return 0;
12500}
12501
12502static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12503{
12504 struct tg3 *tp = netdev_priv(dev);
12505 size_t i;
12506
12507 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12508 tp->rss_ind_tbl[i] = indir[i];
12509
12510 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12511 return 0;
12512
12513 /* It is legal to write the indirection
12514 * table while the device is running.
12515 */
12516 tg3_full_lock(tp, 0);
12517 tg3_rss_write_indir_tbl(tp);
12518 tg3_full_unlock(tp);
12519
12520 return 0;
12521}
12522
0968169c
MC		 12523static void tg3_get_channels(struct net_device *dev,
12524 struct ethtool_channels *channel)
12525{
12526 struct tg3 *tp = netdev_priv(dev);
12527 u32 deflt_qs = netif_get_num_default_rss_queues();
12528
12529 channel->max_rx = tp->rxq_max;
12530 channel->max_tx = tp->txq_max;
12531
12532 if (netif_running(dev)) {
12533 channel->rx_count = tp->rxq_cnt;
12534 channel->tx_count = tp->txq_cnt;
12535 } else {
12536 if (tp->rxq_req)
12537 channel->rx_count = tp->rxq_req;
12538 else
12539 channel->rx_count = min(deflt_qs, tp->rxq_max);
12540
12541 if (tp->txq_req)
12542 channel->tx_count = tp->txq_req;
12543 else
12544 channel->tx_count = min(deflt_qs, tp->txq_max);
12545 }
12546}
12547
12548static int tg3_set_channels(struct net_device *dev,
12549 struct ethtool_channels *channel)
12550{
12551 struct tg3 *tp = netdev_priv(dev);
12552
12553 if (!tg3_flag(tp, SUPPORT_MSIX))
12554 return -EOPNOTSUPP;
12555
12556 if (channel->rx_count > tp->rxq_max ||
12557 channel->tx_count > tp->txq_max)
12558 return -EINVAL;
12559
12560 tp->rxq_req = channel->rx_count;
12561 tp->txq_req = channel->tx_count;
12562
12563 if (!netif_running(dev))
12564 return 0;
12565
12566 tg3_stop(tp);
12567
f4a46d1f 12568 tg3_carrier_off(tp);
0968169c 12569
be947307 12570 tg3_start(tp, true, false, false);
0968169c
MC		 12571
12572 return 0;
12573}
12574
de6f31eb 12575static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12576{
12577 switch (stringset) {
12578 case ETH_SS_STATS:
12579 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12580 break;
4cafd3f5
MC		 12581 case ETH_SS_TEST:
12582 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12583 break;
1da177e4
LT		 12584 default:
12585 WARN_ON(1); /* we need a WARN() */
12586 break;
12587 }
12588}
12589
81b8709c 12590static int tg3_set_phys_id(struct net_device *dev,
12591 enum ethtool_phys_id_state state)
4009a93d
MC		 12592{
12593 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12594
12595 if (!netif_running(tp->dev))
12596 return -EAGAIN;
12597
81b8709c 12598 switch (state) {
12599 case ETHTOOL_ID_ACTIVE:
fce55922 12600 return 1; /* cycle on/off once per second */
4009a93d 12601
81b8709c 12602 case ETHTOOL_ID_ON:
12603 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12604 LED_CTRL_1000MBPS_ON |
12605 LED_CTRL_100MBPS_ON |
12606 LED_CTRL_10MBPS_ON |
12607 LED_CTRL_TRAFFIC_OVERRIDE |
12608 LED_CTRL_TRAFFIC_BLINK |
12609 LED_CTRL_TRAFFIC_LED);
12610 break;
6aa20a22 12611
81b8709c 12612 case ETHTOOL_ID_OFF:
12613 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12614 LED_CTRL_TRAFFIC_OVERRIDE);
12615 break;
4009a93d 12616
81b8709c 12617 case ETHTOOL_ID_INACTIVE:
12618 tw32(MAC_LED_CTRL, tp->led_ctrl);
12619 break;
4009a93d 12620 }
81b8709c 12621
4009a93d
MC		 12622 return 0;
12623}
12624
de6f31eb 12625static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12626 struct ethtool_stats *estats, u64 *tmp_stats)
12627{
12628 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12629
b546e46f
MC		 12630 if (tp->hw_stats)
12631 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12632 else
12633 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12634}
12635
535a490e 12636static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12637{
12638 int i;
12639 __be32 *buf;
12640 u32 offset = 0, len = 0;
12641 u32 magic, val;
12642
63c3a66f 12643 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12644 return NULL;
12645
12646 if (magic == TG3_EEPROM_MAGIC) {
12647 for (offset = TG3_NVM_DIR_START;
12648 offset < TG3_NVM_DIR_END;
12649 offset += TG3_NVM_DIRENT_SIZE) {
12650 if (tg3_nvram_read(tp, offset, &val))
12651 return NULL;
12652
12653 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12654 TG3_NVM_DIRTYPE_EXTVPD)
12655 break;
12656 }
12657
12658 if (offset != TG3_NVM_DIR_END) {
12659 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12660 if (tg3_nvram_read(tp, offset + 4, &offset))
12661 return NULL;
12662
12663 offset = tg3_nvram_logical_addr(tp, offset);
12664 }
12665 }
12666
12667 if (!offset || !len) {
12668 offset = TG3_NVM_VPD_OFF;
12669 len = TG3_NVM_VPD_LEN;
12670 }
12671
12672 buf = kmalloc(len, GFP_KERNEL);
12673 if (buf == NULL)
12674 return NULL;
12675
12676 if (magic == TG3_EEPROM_MAGIC) {
12677 for (i = 0; i < len; i += 4) {
12678 /* The data is in little-endian format in NVRAM.
12679 * Use the big-endian read routines to preserve
12680 * the byte order as it exists in NVRAM.
12681 */
12682 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12683 goto error;
12684 }
12685 } else {
12686 u8 *ptr;
12687 ssize_t cnt;
12688 unsigned int pos = 0;
12689
12690 ptr = (u8 *)&buf[0];
12691 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12692 cnt = pci_read_vpd(tp->pdev, pos,
12693 len - pos, ptr);
12694 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12695 cnt = 0;
12696 else if (cnt < 0)
12697 goto error;
12698 }
12699 if (pos != len)
12700 goto error;
12701 }
12702
535a490e
MC		 12703 *vpdlen = len;
12704
c3e94500
MC		 12705 return buf;
12706
12707error:
12708 kfree(buf);
12709 return NULL;
12710}
12711
566f86ad 12712#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12713#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12714#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12715#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12716#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12717#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12718#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12719#define NVRAM_SELFBOOT_HW_SIZE 0x20
12720#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12721
12722static int tg3_test_nvram(struct tg3 *tp)
12723{
535a490e 12724 u32 csum, magic, len;
a9dc529d 12725 __be32 *buf;
ab0049b4 12726 int i, j, k, err = 0, size;
566f86ad 12727
63c3a66f 12728 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12729 return 0;
12730
e4f34110 12731 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12732 return -EIO;
12733
1b27777a
MC		 12734 if (magic == TG3_EEPROM_MAGIC)
12735 size = NVRAM_TEST_SIZE;
b16250e3 12736 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12737 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12738 TG3_EEPROM_SB_FORMAT_1) {
12739 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12740 case TG3_EEPROM_SB_REVISION_0:
12741 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12742 break;
12743 case TG3_EEPROM_SB_REVISION_2:
12744 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12745 break;
12746 case TG3_EEPROM_SB_REVISION_3:
12747 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12748 break;
727a6d9f
MC		 12749 case TG3_EEPROM_SB_REVISION_4:
12750 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12751 break;
12752 case TG3_EEPROM_SB_REVISION_5:
12753 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12754 break;
12755 case TG3_EEPROM_SB_REVISION_6:
12756 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12757 break;
a5767dec 12758 default:
727a6d9f 12759 return -EIO;
a5767dec
MC		 12760 }
12761 } else
1b27777a 12762 return 0;
b16250e3
MC		 12763 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12764 size = NVRAM_SELFBOOT_HW_SIZE;
12765 else
1b27777a
MC		 12766 return -EIO;
12767
12768 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12769 if (buf == NULL)
12770 return -ENOMEM;
12771
1b27777a
MC		 12772 err = -EIO;
12773 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12774 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12775 if (err)
566f86ad 12776 break;
566f86ad 12777 }
1b27777a 12778 if (i < size)
566f86ad
MC		 12779 goto out;
12780
1b27777a 12781 /* Selfboot format */
a9dc529d 12782 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12783 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12784 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12785 u8 *buf8 = (u8 *) buf, csum8 = 0;
12786
b9fc7dc5 12787 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12788 TG3_EEPROM_SB_REVISION_2) {
12789 /* For rev 2, the csum doesn't include the MBA. */
12790 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12791 csum8 += buf8[i];
12792 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12793 csum8 += buf8[i];
12794 } else {
12795 for (i = 0; i < size; i++)
12796 csum8 += buf8[i];
12797 }
1b27777a 12798
ad96b485
AB		 12799 if (csum8 == 0) {
12800 err = 0;
12801 goto out;
12802 }
12803
12804 err = -EIO;
12805 goto out;
1b27777a 12806 }
566f86ad 12807
b9fc7dc5 12808 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12809 TG3_EEPROM_MAGIC_HW) {
12810 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12811 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12812 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12813
12814 /* Separate the parity bits and the data bytes. */
12815 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12816 if ((i == 0) || (i == 8)) {
12817 int l;
12818 u8 msk;
12819
12820 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12821 parity[k++] = buf8[i] & msk;
12822 i++;
859a5887 12823 } else if (i == 16) {
b16250e3
MC		 12824 int l;
12825 u8 msk;
12826
12827 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12828 parity[k++] = buf8[i] & msk;
12829 i++;
12830
12831 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12832 parity[k++] = buf8[i] & msk;
12833 i++;
12834 }
12835 data[j++] = buf8[i];
12836 }
12837
12838 err = -EIO;
12839 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12840 u8 hw8 = hweight8(data[i]);
12841
12842 if ((hw8 & 0x1) && parity[i])
12843 goto out;
12844 else if (!(hw8 & 0x1) && !parity[i])
12845 goto out;
12846 }
12847 err = 0;
12848 goto out;
12849 }
12850
01c3a392
MC		 12851 err = -EIO;
12852
566f86ad
MC		 12853 /* Bootstrap checksum at offset 0x10 */
12854 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12855 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12856 goto out;
12857
12858 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12859 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12860 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12861 goto out;
566f86ad 12862
c3e94500
MC		 12863 kfree(buf);
12864
535a490e 12865 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12866 if (!buf)
12867 return -ENOMEM;
d4894f3e 12868
535a490e 12869 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12870 if (i > 0) {
12871 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12872 if (j < 0)
12873 goto out;
12874
535a490e 12875 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12876 goto out;
12877
12878 i += PCI_VPD_LRDT_TAG_SIZE;
12879 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12880 PCI_VPD_RO_KEYWORD_CHKSUM);
12881 if (j > 0) {
12882 u8 csum8 = 0;
12883
12884 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12885
12886 for (i = 0; i <= j; i++)
12887 csum8 += ((u8 *)buf)[i];
12888
12889 if (csum8)
12890 goto out;
12891 }
12892 }
12893
566f86ad
MC		 12894 err = 0;
12895
12896out:
12897 kfree(buf);
12898 return err;
12899}
12900
ca43007a
MC		 12901#define TG3_SERDES_TIMEOUT_SEC 2
12902#define TG3_COPPER_TIMEOUT_SEC 6
12903
12904static int tg3_test_link(struct tg3 *tp)
12905{
12906 int i, max;
12907
12908 if (!netif_running(tp->dev))
12909 return -ENODEV;
12910
f07e9af3 12911 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12912 max = TG3_SERDES_TIMEOUT_SEC;
12913 else
12914 max = TG3_COPPER_TIMEOUT_SEC;
12915
12916 for (i = 0; i < max; i++) {
f4a46d1f 12917 if (tp->link_up)
ca43007a
MC		 12918 return 0;
12919
12920 if (msleep_interruptible(1000))
12921 break;
12922 }
12923
12924 return -EIO;
12925}
12926
a71116d1 12927/* Only test the commonly used registers */
30ca3e37 12928static int tg3_test_registers(struct tg3 *tp)
a71116d1 12929{
b16250e3 12930 int i, is_5705, is_5750;
a71116d1
MC		 12931 u32 offset, read_mask, write_mask, val, save_val, read_val;
12932 static struct {
12933 u16 offset;
12934 u16 flags;
12935#define TG3_FL_5705 0x1
12936#define TG3_FL_NOT_5705 0x2
12937#define TG3_FL_NOT_5788 0x4
b16250e3 12938#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 12939 u32 read_mask;
12940 u32 write_mask;
12941 } reg_tbl[] = {
12942 /* MAC Control Registers */
12943 { MAC_MODE, TG3_FL_NOT_5705,
12944 0x00000000, 0x00ef6f8c },
12945 { MAC_MODE, TG3_FL_5705,
12946 0x00000000, 0x01ef6b8c },
12947 { MAC_STATUS, TG3_FL_NOT_5705,
12948 0x03800107, 0x00000000 },
12949 { MAC_STATUS, TG3_FL_5705,
12950 0x03800100, 0x00000000 },
12951 { MAC_ADDR_0_HIGH, 0x0000,
12952 0x00000000, 0x0000ffff },
12953 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 12954 0x00000000, 0xffffffff },
a71116d1
MC		 12955 { MAC_RX_MTU_SIZE, 0x0000,
12956 0x00000000, 0x0000ffff },
12957 { MAC_TX_MODE, 0x0000,
12958 0x00000000, 0x00000070 },
12959 { MAC_TX_LENGTHS, 0x0000,
12960 0x00000000, 0x00003fff },
12961 { MAC_RX_MODE, TG3_FL_NOT_5705,
12962 0x00000000, 0x000007fc },
12963 { MAC_RX_MODE, TG3_FL_5705,
12964 0x00000000, 0x000007dc },
12965 { MAC_HASH_REG_0, 0x0000,
12966 0x00000000, 0xffffffff },
12967 { MAC_HASH_REG_1, 0x0000,
12968 0x00000000, 0xffffffff },
12969 { MAC_HASH_REG_2, 0x0000,
12970 0x00000000, 0xffffffff },
12971 { MAC_HASH_REG_3, 0x0000,
12972 0x00000000, 0xffffffff },
12973
12974 /* Receive Data and Receive BD Initiator Control Registers. */
12975 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12976 0x00000000, 0xffffffff },
12977 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12978 0x00000000, 0xffffffff },
12979 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12980 0x00000000, 0x00000003 },
12981 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12982 0x00000000, 0xffffffff },
12983 { RCVDBDI_STD_BD+0, 0x0000,
12984 0x00000000, 0xffffffff },
12985 { RCVDBDI_STD_BD+4, 0x0000,
12986 0x00000000, 0xffffffff },
12987 { RCVDBDI_STD_BD+8, 0x0000,
12988 0x00000000, 0xffff0002 },
12989 { RCVDBDI_STD_BD+0xc, 0x0000,
12990 0x00000000, 0xffffffff },
6aa20a22 12991
a71116d1
MC		 12992 /* Receive BD Initiator Control Registers. */
12993 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12994 0x00000000, 0xffffffff },
12995 { RCVBDI_STD_THRESH, TG3_FL_5705,
12996 0x00000000, 0x000003ff },
12997 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12998 0x00000000, 0xffffffff },
6aa20a22 12999
a71116d1
MC		 13000 /* Host Coalescing Control Registers. */
13001 { HOSTCC_MODE, TG3_FL_NOT_5705,
13002 0x00000000, 0x00000004 },
13003 { HOSTCC_MODE, TG3_FL_5705,
13004 0x00000000, 0x000000f6 },
13005 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13006 0x00000000, 0xffffffff },
13007 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13008 0x00000000, 0x000003ff },
13009 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13010 0x00000000, 0xffffffff },
13011 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13012 0x00000000, 0x000003ff },
13013 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13014 0x00000000, 0xffffffff },
13015 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13016 0x00000000, 0x000000ff },
13017 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13018 0x00000000, 0xffffffff },
13019 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13020 0x00000000, 0x000000ff },
13021 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13022 0x00000000, 0xffffffff },
13023 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13024 0x00000000, 0xffffffff },
13025 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13026 0x00000000, 0xffffffff },
13027 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13028 0x00000000, 0x000000ff },
13029 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13030 0x00000000, 0xffffffff },
13031 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13032 0x00000000, 0x000000ff },
13033 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13034 0x00000000, 0xffffffff },
13035 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13036 0x00000000, 0xffffffff },
13037 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13038 0x00000000, 0xffffffff },
13039 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13040 0x00000000, 0xffffffff },
13041 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13042 0x00000000, 0xffffffff },
13043 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13044 0xffffffff, 0x00000000 },
13045 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13046 0xffffffff, 0x00000000 },
13047
13048 /* Buffer Manager Control Registers. */
b16250e3 13049 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 13050 0x00000000, 0x007fff80 },
b16250e3 13051 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 13052 0x00000000, 0x007fffff },
13053 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13054 0x00000000, 0x0000003f },
13055 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13056 0x00000000, 0x000001ff },
13057 { BUFMGR_MB_HIGH_WATER, 0x0000,
13058 0x00000000, 0x000001ff },
13059 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13060 0xffffffff, 0x00000000 },
13061 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13062 0xffffffff, 0x00000000 },
6aa20a22 13063
a71116d1
MC		 13064 /* Mailbox Registers */
13065 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13066 0x00000000, 0x000001ff },
13067 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13068 0x00000000, 0x000001ff },
13069 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13070 0x00000000, 0x000007ff },
13071 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13072 0x00000000, 0x000001ff },
13073
13074 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13075 };
13076
b16250e3 13077 is_5705 = is_5750 = 0;
63c3a66f 13078 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 13079 is_5705 = 1;
63c3a66f 13080 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 13081 is_5750 = 1;
13082 }
a71116d1
MC		 13083
13084 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13085 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13086 continue;
13087
13088 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13089 continue;
13090
63c3a66f 13091 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 13092 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13093 continue;
13094
b16250e3
MC		 13095 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13096 continue;
13097
a71116d1
MC		 13098 offset = (u32) reg_tbl[i].offset;
13099 read_mask = reg_tbl[i].read_mask;
13100 write_mask = reg_tbl[i].write_mask;
13101
13102 /* Save the original register content */
13103 save_val = tr32(offset);
13104
13105 /* Determine the read-only value. */
13106 read_val = save_val & read_mask;
13107
13108 /* Write zero to the register, then make sure the read-only bits
13109 * are not changed and the read/write bits are all zeros.
13110 */
13111 tw32(offset, 0);
13112
13113 val = tr32(offset);
13114
13115 /* Test the read-only and read/write bits. */
13116 if (((val & read_mask) != read_val) || (val & write_mask))
13117 goto out;
13118
13119 /* Write ones to all the bits defined by RdMask and WrMask, then
13120 * make sure the read-only bits are not changed and the
13121 * read/write bits are all ones.
13122 */
13123 tw32(offset, read_mask | write_mask);
13124
13125 val = tr32(offset);
13126
13127 /* Test the read-only bits. */
13128 if ((val & read_mask) != read_val)
13129 goto out;
13130
13131 /* Test the read/write bits. */
13132 if ((val & write_mask) != write_mask)
13133 goto out;
13134
13135 tw32(offset, save_val);
13136 }
13137
13138 return 0;
13139
13140out:
9f88f29f 13141 if (netif_msg_hw(tp))
2445e461
MC		 13142 netdev_err(tp->dev,
13143 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13144 tw32(offset, save_val);
13145 return -EIO;
13146}
13147
7942e1db
MC		 13148static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13149{
f71e1309 13150 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13151 int i;
13152 u32 j;
13153
e9edda69 13154 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13155 for (j = 0; j < len; j += 4) {
13156 u32 val;
13157
13158 tg3_write_mem(tp, offset + j, test_pattern[i]);
13159 tg3_read_mem(tp, offset + j, &val);
13160 if (val != test_pattern[i])
13161 return -EIO;
13162 }
13163 }
13164 return 0;
13165}
13166
13167static int tg3_test_memory(struct tg3 *tp)
13168{
13169 static struct mem_entry {
13170 u32 offset;
13171 u32 len;
13172 } mem_tbl_570x[] = {
38690194 13173 { 0x00000000, 0x00b50},
7942e1db
MC		 13174 { 0x00002000, 0x1c000},
13175 { 0xffffffff, 0x00000}
13176 }, mem_tbl_5705[] = {
13177 { 0x00000100, 0x0000c},
13178 { 0x00000200, 0x00008},
7942e1db
MC		 13179 { 0x00004000, 0x00800},
13180 { 0x00006000, 0x01000},
13181 { 0x00008000, 0x02000},
13182 { 0x00010000, 0x0e000},
13183 { 0xffffffff, 0x00000}
79f4d13a
MC		 13184 }, mem_tbl_5755[] = {
13185 { 0x00000200, 0x00008},
13186 { 0x00004000, 0x00800},
13187 { 0x00006000, 0x00800},
13188 { 0x00008000, 0x02000},
13189 { 0x00010000, 0x0c000},
13190 { 0xffffffff, 0x00000}
b16250e3
MC		 13191 }, mem_tbl_5906[] = {
13192 { 0x00000200, 0x00008},
13193 { 0x00004000, 0x00400},
13194 { 0x00006000, 0x00400},
13195 { 0x00008000, 0x01000},
13196 { 0x00010000, 0x01000},
13197 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13198 }, mem_tbl_5717[] = {
13199 { 0x00000200, 0x00008},
13200 { 0x00010000, 0x0a000},
13201 { 0x00020000, 0x13c00},
13202 { 0xffffffff, 0x00000}
13203 }, mem_tbl_57765[] = {
13204 { 0x00000200, 0x00008},
13205 { 0x00004000, 0x00800},
13206 { 0x00006000, 0x09800},
13207 { 0x00010000, 0x0a000},
13208 { 0xffffffff, 0x00000}
7942e1db
MC		 13209 };
13210 struct mem_entry *mem_tbl;
13211 int err = 0;
13212 int i;
13213
63c3a66f 13214 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13215 mem_tbl = mem_tbl_5717;
c65a17f4 13216 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13217 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13218 mem_tbl = mem_tbl_57765;
63c3a66f 13219 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13220 mem_tbl = mem_tbl_5755;
4153577a 13221 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13222 mem_tbl = mem_tbl_5906;
63c3a66f 13223 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13224 mem_tbl = mem_tbl_5705;
13225 else
7942e1db
MC		 13226 mem_tbl = mem_tbl_570x;
13227
13228 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13229 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13230 if (err)
7942e1db
MC		 13231 break;
13232 }
6aa20a22 13233
7942e1db
MC		 13234 return err;
13235}
13236
bb158d69
MC		 13237#define TG3_TSO_MSS 500
13238
13239#define TG3_TSO_IP_HDR_LEN 20
13240#define TG3_TSO_TCP_HDR_LEN 20
13241#define TG3_TSO_TCP_OPT_LEN 12
13242
13243static const u8 tg3_tso_header[] = {
132440x08, 0x00,
132450x45, 0x00, 0x00, 0x00,
132460x00, 0x00, 0x40, 0x00,
132470x40, 0x06, 0x00, 0x00,
132480x0a, 0x00, 0x00, 0x01,
132490x0a, 0x00, 0x00, 0x02,
132500x0d, 0x00, 0xe0, 0x00,
132510x00, 0x00, 0x01, 0x00,
132520x00, 0x00, 0x02, 0x00,
132530x80, 0x10, 0x10, 0x00,
132540x14, 0x09, 0x00, 0x00,
132550x01, 0x01, 0x08, 0x0a,
132560x11, 0x11, 0x11, 0x11,
132570x11, 0x11, 0x11, 0x11,
13258};
9f40dead 13259
28a45957 13260static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13261{
5e5a7f37 13262 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13263 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13264 u32 budget;
9205fd9c
ED		 13265 struct sk_buff *skb;
13266 u8 *tx_data, *rx_data;
c76949a6
MC		 13267 dma_addr_t map;
13268 int num_pkts, tx_len, rx_len, i, err;
13269 struct tg3_rx_buffer_desc *desc;
898a56f8 13270 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13271 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13272
c8873405
MC		 13273 tnapi = &tp->napi[0];
13274 rnapi = &tp->napi[0];
0c1d0e2b 13275 if (tp->irq_cnt > 1) {
63c3a66f 13276 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13277 rnapi = &tp->napi[1];
63c3a66f 13278 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13279 tnapi = &tp->napi[1];
0c1d0e2b 13280 }
fd2ce37f 13281 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13282
c76949a6
MC		 13283 err = -EIO;
13284
4852a861 13285 tx_len = pktsz;
a20e9c62 13286 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13287 if (!skb)
13288 return -ENOMEM;
13289
c76949a6 13290 tx_data = skb_put(skb, tx_len);
d458cdf7
JP		 13291 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13292 memset(tx_data + ETH_ALEN, 0x0, 8);
c76949a6 13293
4852a861 13294 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13295
28a45957 13296 if (tso_loopback) {
bb158d69
MC		 13297 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13298
13299 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13300 TG3_TSO_TCP_OPT_LEN;
13301
13302 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13303 sizeof(tg3_tso_header));
13304 mss = TG3_TSO_MSS;
13305
13306 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13307 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13308
13309 /* Set the total length field in the IP header */
13310 iph->tot_len = htons((u16)(mss + hdr_len));
13311
13312 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13313 TXD_FLAG_CPU_POST_DMA);
13314
63c3a66f
JP		 13315 if (tg3_flag(tp, HW_TSO_1) ||
13316 tg3_flag(tp, HW_TSO_2) ||
13317 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13318 struct tcphdr *th;
13319 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13320 th = (struct tcphdr *)&tx_data[val];
13321 th->check = 0;
13322 } else
13323 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13324
63c3a66f 13325 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13326 mss |= (hdr_len & 0xc) << 12;
13327 if (hdr_len & 0x10)
13328 base_flags |= 0x00000010;
13329 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13330 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13331 mss |= hdr_len << 9;
63c3a66f 13332 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13333 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13334 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13335 } else {
13336 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13337 }
13338
13339 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13340 } else {
13341 num_pkts = 1;
13342 data_off = ETH_HLEN;
c441b456
MC		 13343
13344 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13345 tx_len > VLAN_ETH_FRAME_LEN)
13346 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13347 }
13348
13349 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13350 tx_data[i] = (u8) (i & 0xff);
13351
f4188d8a
AD		 13352 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13353 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13354 dev_kfree_skb(skb);
13355 return -EIO;
13356 }
c76949a6 13357
0d681b27
MC		 13358 val = tnapi->tx_prod;
13359 tnapi->tx_buffers[val].skb = skb;
13360 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13361
c76949a6 13362 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13363 rnapi->coal_now);
c76949a6
MC		 13364
13365 udelay(10);
13366
898a56f8 13367 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13368
84b67b27
MC		 13369 budget = tg3_tx_avail(tnapi);
13370 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13371 base_flags | TXD_FLAG_END, mss, 0)) {
13372 tnapi->tx_buffers[val].skb = NULL;
13373 dev_kfree_skb(skb);
13374 return -EIO;
13375 }
c76949a6 13376
f3f3f27e 13377 tnapi->tx_prod++;
c76949a6 13378
6541b806
MC		 13379 /* Sync BD data before updating mailbox */
13380 wmb();
13381
f3f3f27e
MC		 13382 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13383 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13384
13385 udelay(10);
13386
303fc921
MC		 13387 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13388 for (i = 0; i < 35; i++) {
c76949a6 13389 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13390 coal_now);
c76949a6
MC		 13391
13392 udelay(10);
13393
898a56f8
MC		 13394 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13395 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13396 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13397 (rx_idx == (rx_start_idx + num_pkts)))
13398 break;
13399 }
13400
ba1142e4 13401 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13402 dev_kfree_skb(skb);
13403
f3f3f27e 13404 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13405 goto out;
13406
13407 if (rx_idx != rx_start_idx + num_pkts)
13408 goto out;
13409
bb158d69
MC		 13410 val = data_off;
13411 while (rx_idx != rx_start_idx) {
13412 desc = &rnapi->rx_rcb[rx_start_idx++];
13413 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13414 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13415
bb158d69
MC		 13416 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13417 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13418 goto out;
c76949a6 13419
bb158d69
MC		 13420 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13421 - ETH_FCS_LEN;
c76949a6 13422
28a45957 13423 if (!tso_loopback) {
bb158d69
MC		 13424 if (rx_len != tx_len)
13425 goto out;
4852a861 13426
bb158d69
MC		 13427 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13428 if (opaque_key != RXD_OPAQUE_RING_STD)
13429 goto out;
13430 } else {
13431 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13432 goto out;
13433 }
13434 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13435 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13436 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13437 goto out;
bb158d69 13438 }
4852a861 13439
bb158d69 13440 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13441 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13442 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13443 mapping);
13444 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13445 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13446 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13447 mapping);
13448 } else
13449 goto out;
c76949a6 13450
bb158d69
MC		 13451 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13452 PCI_DMA_FROMDEVICE);
c76949a6 13453
9205fd9c 13454 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13455 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13456 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13457 goto out;
13458 }
c76949a6 13459 }
bb158d69 13460
c76949a6 13461 err = 0;
6aa20a22 13462
9205fd9c 13463 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13464out:
13465 return err;
13466}
13467
00c266b7
MC		 13468#define TG3_STD_LOOPBACK_FAILED 1
13469#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13470#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13471#define TG3_LOOPBACK_FAILED \
13472 (TG3_STD_LOOPBACK_FAILED | \
13473 TG3_JMB_LOOPBACK_FAILED | \
13474 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13475
941ec90f 13476static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13477{
28a45957 13478 int err = -EIO;
2215e24c 13479 u32 eee_cap;
c441b456
MC		 13480 u32 jmb_pkt_sz = 9000;
13481
13482 if (tp->dma_limit)
13483 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13484
ab789046
MC		 13485 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13486 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13487
28a45957 13488 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13489 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13490 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13491 if (do_extlpbk)
93df8b8f 13492 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13493 goto done;
13494 }
13495
953c96e0 13496 err = tg3_reset_hw(tp, true);
ab789046 13497 if (err) {
93df8b8f
NNS		 13498 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13499 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13500 if (do_extlpbk)
93df8b8f 13501 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13502 goto done;
13503 }
9f40dead 13504
63c3a66f 13505 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13506 int i;
13507
13508 /* Reroute all rx packets to the 1st queue */
13509 for (i = MAC_RSS_INDIR_TBL_0;
13510 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13511 tw32(i, 0x0);
13512 }
13513
6e01b20b
MC		 13514 /* HW errata - mac loopback fails in some cases on 5780.
13515 * Normal traffic and PHY loopback are not affected by
13516 * errata. Also, the MAC loopback test is deprecated for
13517 * all newer ASIC revisions.
13518 */
4153577a 13519 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13520 !tg3_flag(tp, CPMU_PRESENT)) {
13521 tg3_mac_loopback(tp, true);
9936bcf6 13522
28a45957 13523 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13524 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13525
13526 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13527 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13528 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13529
13530 tg3_mac_loopback(tp, false);
13531 }
4852a861 13532
f07e9af3 13533 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13534 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13535 int i;
13536
941ec90f 13537 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13538
13539 /* Wait for link */
13540 for (i = 0; i < 100; i++) {
13541 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13542 break;
13543 mdelay(1);
13544 }
13545
28a45957 13546 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13547 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13548 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13549 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13550 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13551 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13552 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13553 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13554
941ec90f
MC		 13555 if (do_extlpbk) {
13556 tg3_phy_lpbk_set(tp, 0, true);
13557
13558 /* All link indications report up, but the hardware
13559 * isn't really ready for about 20 msec. Double it
13560 * to be sure.
13561 */
13562 mdelay(40);
13563
13564 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13565 data[TG3_EXT_LOOPB_TEST] |=
13566 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13567 if (tg3_flag(tp, TSO_CAPABLE) &&
13568 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13569 data[TG3_EXT_LOOPB_TEST] |=
13570 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13571 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13572 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13573 data[TG3_EXT_LOOPB_TEST] |=
13574 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13575 }
13576
5e5a7f37
MC		 13577 /* Re-enable gphy autopowerdown. */
13578 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13579 tg3_phy_toggle_apd(tp, true);
13580 }
6833c043 13581
93df8b8f
NNS		 13582 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13583 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13584
ab789046
MC		 13585done:
13586 tp->phy_flags |= eee_cap;
13587
9f40dead
MC		 13588 return err;
13589}
13590
4cafd3f5
MC		 13591static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13592 u64 *data)
13593{
566f86ad 13594 struct tg3 *tp = netdev_priv(dev);
941ec90f 13595 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13596
2e460fc0
NS		 13597 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13598 if (tg3_power_up(tp)) {
13599 etest->flags |= ETH_TEST_FL_FAILED;
13600 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13601 return;
13602 }
13603 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13604 }
bc1c7567 13605
566f86ad
MC		 13606 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13607
13608 if (tg3_test_nvram(tp) != 0) {
13609 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13610 data[TG3_NVRAM_TEST] = 1;
566f86ad 13611 }
941ec90f 13612 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13613 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13614 data[TG3_LINK_TEST] = 1;
ca43007a 13615 }
a71116d1 13616 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13617 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13618
13619 if (netif_running(dev)) {
b02fd9e3 13620 tg3_phy_stop(tp);
a71116d1 13621 tg3_netif_stop(tp);
bbe832c0
MC		 13622 irq_sync = 1;
13623 }
a71116d1 13624
bbe832c0 13625 tg3_full_lock(tp, irq_sync);
a71116d1 13626 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13627 err = tg3_nvram_lock(tp);
a71116d1 13628 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13629 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13630 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13631 if (!err)
13632 tg3_nvram_unlock(tp);
a71116d1 13633
f07e9af3 13634 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13635 tg3_phy_reset(tp);
13636
a71116d1
MC		 13637 if (tg3_test_registers(tp) != 0) {
13638 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13639 data[TG3_REGISTER_TEST] = 1;
a71116d1 13640 }
28a45957 13641
7942e1db
MC		 13642 if (tg3_test_memory(tp) != 0) {
13643 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13644 data[TG3_MEMORY_TEST] = 1;
7942e1db 13645 }
28a45957 13646
941ec90f
MC		 13647 if (doextlpbk)
13648 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13649
93df8b8f 13650 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13651 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13652
f47c11ee
DM		 13653 tg3_full_unlock(tp);
13654
d4bc3927
MC		 13655 if (tg3_test_interrupt(tp) != 0) {
13656 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13657 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13658 }
f47c11ee
DM		 13659
13660 tg3_full_lock(tp, 0);
d4bc3927 13661
a71116d1
MC		 13662 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13663 if (netif_running(dev)) {
63c3a66f 13664 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13665 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13666 if (!err2)
b9ec6c1b 13667 tg3_netif_start(tp);
a71116d1 13668 }
f47c11ee
DM		 13669
13670 tg3_full_unlock(tp);
b02fd9e3
MC		 13671
13672 if (irq_sync && !err2)
13673 tg3_phy_start(tp);
a71116d1 13674 }
80096068 13675 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13676 tg3_power_down_prepare(tp);
bc1c7567 13677
4cafd3f5
MC		 13678}
13679
7260899b 13680static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
0a633ac2
MC		 13681{
13682 struct tg3 *tp = netdev_priv(dev);
13683 struct hwtstamp_config stmpconf;
13684
13685 if (!tg3_flag(tp, PTP_CAPABLE))
7260899b 13686 return -EOPNOTSUPP;
0a633ac2
MC		 13687
13688 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13689 return -EFAULT;
13690
13691 if (stmpconf.flags)
13692 return -EINVAL;
13693
58b187c6
BH		 13694 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13695 stmpconf.tx_type != HWTSTAMP_TX_OFF)
0a633ac2 13696 return -ERANGE;
0a633ac2
MC		 13697
13698 switch (stmpconf.rx_filter) {
13699 case HWTSTAMP_FILTER_NONE:
13700 tp->rxptpctl = 0;
13701 break;
13702 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13703 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13704 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13705 break;
13706 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13707 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13708 TG3_RX_PTP_CTL_SYNC_EVNT;
13709 break;
13710 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13711 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13712 TG3_RX_PTP_CTL_DELAY_REQ;
13713 break;
13714 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13715 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13716 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13717 break;
13718 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13719 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13720 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13721 break;
13722 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13723 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13724 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13725 break;
13726 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13727 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13728 TG3_RX_PTP_CTL_SYNC_EVNT;
13729 break;
13730 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13731 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13732 TG3_RX_PTP_CTL_SYNC_EVNT;
13733 break;
13734 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13735 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13736 TG3_RX_PTP_CTL_SYNC_EVNT;
13737 break;
13738 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13739 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13740 TG3_RX_PTP_CTL_DELAY_REQ;
13741 break;
13742 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13743 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13744 TG3_RX_PTP_CTL_DELAY_REQ;
13745 break;
13746 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13747 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13748 TG3_RX_PTP_CTL_DELAY_REQ;
13749 break;
13750 default:
13751 return -ERANGE;
13752 }
13753
13754 if (netif_running(dev) && tp->rxptpctl)
13755 tw32(TG3_RX_PTP_CTL,
13756 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13757
58b187c6
BH		 13758 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13759 tg3_flag_set(tp, TX_TSTAMP_EN);
13760 else
13761 tg3_flag_clear(tp, TX_TSTAMP_EN);
13762
0a633ac2
MC		 13763 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13764 -EFAULT : 0;
13765}
13766
7260899b
BH		 13767static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13768{
13769 struct tg3 *tp = netdev_priv(dev);
13770 struct hwtstamp_config stmpconf;
13771
13772 if (!tg3_flag(tp, PTP_CAPABLE))
13773 return -EOPNOTSUPP;
13774
13775 stmpconf.flags = 0;
13776 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13777 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13778
13779 switch (tp->rxptpctl) {
13780 case 0:
13781 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13782 break;
13783 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13784 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13785 break;
13786 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13787 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13788 break;
13789 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13790 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13791 break;
13792 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13793 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13794 break;
13795 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13796 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13797 break;
13798 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13799 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13800 break;
13801 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13802 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13803 break;
13804 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13805 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13806 break;
13807 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13808 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13809 break;
13810 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13811 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13812 break;
13813 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13814 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13815 break;
13816 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13817 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13818 break;
13819 default:
13820 WARN_ON_ONCE(1);
13821 return -ERANGE;
13822 }
13823
13824 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13825 -EFAULT : 0;
13826}
13827
1da177e4
LT		 13828static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13829{
13830 struct mii_ioctl_data *data = if_mii(ifr);
13831 struct tg3 *tp = netdev_priv(dev);
13832 int err;
13833
63c3a66f 13834 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13835 struct phy_device *phydev;
f07e9af3 13836 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13837 return -EAGAIN;
ead2402c 13838 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
28b04113 13839 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13840 }
13841
33f401ae 13842 switch (cmd) {
1da177e4 13843 case SIOCGMIIPHY:
882e9793 13844 data->phy_id = tp->phy_addr;
1da177e4
LT		 13845
13846 /* fallthru */
13847 case SIOCGMIIREG: {
13848 u32 mii_regval;
13849
f07e9af3 13850 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13851 break; /* We have no PHY */
13852
34eea5ac 13853 if (!netif_running(dev))
bc1c7567
MC		 13854 return -EAGAIN;
13855
f47c11ee 13856 spin_lock_bh(&tp->lock);
5c358045
HM		 13857 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13858 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13859 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13860
13861 data->val_out = mii_regval;
13862
13863 return err;
13864 }
13865
13866 case SIOCSMIIREG:
f07e9af3 13867 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13868 break; /* We have no PHY */
13869
34eea5ac 13870 if (!netif_running(dev))
bc1c7567
MC		 13871 return -EAGAIN;
13872
f47c11ee 13873 spin_lock_bh(&tp->lock);
5c358045
HM		 13874 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13875 data->reg_num & 0x1f, data->val_in);
f47c11ee 13876 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13877
13878 return err;
13879
0a633ac2 13880 case SIOCSHWTSTAMP:
7260899b
BH		 13881 return tg3_hwtstamp_set(dev, ifr);
13882
13883 case SIOCGHWTSTAMP:
13884 return tg3_hwtstamp_get(dev, ifr);
0a633ac2 13885
1da177e4
LT		 13886 default:
13887 /* do nothing */
13888 break;
13889 }
13890 return -EOPNOTSUPP;
13891}
13892
15f9850d
DM		 13893static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13894{
13895 struct tg3 *tp = netdev_priv(dev);
13896
13897 memcpy(ec, &tp->coal, sizeof(*ec));
13898 return 0;
13899}
13900
d244c892
MC		 13901static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13902{
13903 struct tg3 *tp = netdev_priv(dev);
13904 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13905 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13906
63c3a66f 13907 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13908 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13909 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13910 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13911 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13912 }
13913
13914 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13915 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13916 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13917 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13918 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13919 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13920 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13921 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13922 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13923 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13924 return -EINVAL;
13925
13926 /* No rx interrupts will be generated if both are zero */
13927 if ((ec->rx_coalesce_usecs == 0) &&
13928 (ec->rx_max_coalesced_frames == 0))
13929 return -EINVAL;
13930
13931 /* No tx interrupts will be generated if both are zero */
13932 if ((ec->tx_coalesce_usecs == 0) &&
13933 (ec->tx_max_coalesced_frames == 0))
13934 return -EINVAL;
13935
13936 /* Only copy relevant parameters, ignore all others. */
13937 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13938 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13939 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13940 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13941 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13942 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13943 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13944 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13945 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13946
13947 if (netif_running(dev)) {
13948 tg3_full_lock(tp, 0);
13949 __tg3_set_coalesce(tp, &tp->coal);
13950 tg3_full_unlock(tp);
13951 }
13952 return 0;
13953}
13954
1cbf9eb8
NS		 13955static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13956{
13957 struct tg3 *tp = netdev_priv(dev);
13958
13959 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13960 netdev_warn(tp->dev, "Board does not support EEE!\n");
13961 return -EOPNOTSUPP;
13962 }
13963
13964 if (edata->advertised != tp->eee.advertised) {
13965 netdev_warn(tp->dev,
13966 "Direct manipulation of EEE advertisement is not supported\n");
13967 return -EINVAL;
13968 }
13969
13970 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13971 netdev_warn(tp->dev,
13972 "Maximal Tx Lpi timer supported is %#x(u)\n",
13973 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13974 return -EINVAL;
13975 }
13976
13977 tp->eee = *edata;
13978
13979 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13980 tg3_warn_mgmt_link_flap(tp);
13981
13982 if (netif_running(tp->dev)) {
13983 tg3_full_lock(tp, 0);
13984 tg3_setup_eee(tp);
13985 tg3_phy_reset(tp);
13986 tg3_full_unlock(tp);
13987 }
13988
13989 return 0;
13990}
13991
13992static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13993{
13994 struct tg3 *tp = netdev_priv(dev);
13995
13996 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13997 netdev_warn(tp->dev,
13998 "Board does not support EEE!\n");
13999 return -EOPNOTSUPP;
14000 }
14001
14002 *edata = tp->eee;
14003 return 0;
14004}
14005
7282d491 14006static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 14007 .get_settings = tg3_get_settings,
14008 .set_settings = tg3_set_settings,
14009 .get_drvinfo = tg3_get_drvinfo,
14010 .get_regs_len = tg3_get_regs_len,
14011 .get_regs = tg3_get_regs,
14012 .get_wol = tg3_get_wol,
14013 .set_wol = tg3_set_wol,
14014 .get_msglevel = tg3_get_msglevel,
14015 .set_msglevel = tg3_set_msglevel,
14016 .nway_reset = tg3_nway_reset,
14017 .get_link = ethtool_op_get_link,
14018 .get_eeprom_len = tg3_get_eeprom_len,
14019 .get_eeprom = tg3_get_eeprom,
14020 .set_eeprom = tg3_set_eeprom,
14021 .get_ringparam = tg3_get_ringparam,
14022 .set_ringparam = tg3_set_ringparam,
14023 .get_pauseparam = tg3_get_pauseparam,
14024 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 14025 .self_test = tg3_self_test,
1da177e4 14026 .get_strings = tg3_get_strings,
81b8709c 14027 .set_phys_id = tg3_set_phys_id,
1da177e4 14028 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 14029 .get_coalesce = tg3_get_coalesce,
d244c892 14030 .set_coalesce = tg3_set_coalesce,
b9f2c044 14031 .get_sset_count = tg3_get_sset_count,
90415477
MC		 14032 .get_rxnfc = tg3_get_rxnfc,
14033 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14034 .get_rxfh_indir = tg3_get_rxfh_indir,
14035 .set_rxfh_indir = tg3_set_rxfh_indir,
0968169c
MC		 14036 .get_channels = tg3_get_channels,
14037 .set_channels = tg3_set_channels,
7d41e49a 14038 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 14039 .get_eee = tg3_get_eee,
14040 .set_eee = tg3_set_eee,
1da177e4
LT		 14041};
14042
b4017c53
DM		 14043static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14044 struct rtnl_link_stats64 *stats)
14045{
14046 struct tg3 *tp = netdev_priv(dev);
14047
0f566b20
MC		 14048 spin_lock_bh(&tp->lock);
14049 if (!tp->hw_stats) {
14050 spin_unlock_bh(&tp->lock);
b4017c53 14051 return &tp->net_stats_prev;
0f566b20 14052 }
b4017c53 14053
b4017c53
DM		 14054 tg3_get_nstats(tp, stats);
14055 spin_unlock_bh(&tp->lock);
14056
14057 return stats;
14058}
14059
ccd5ba9d
MC		 14060static void tg3_set_rx_mode(struct net_device *dev)
14061{
14062 struct tg3 *tp = netdev_priv(dev);
14063
14064 if (!netif_running(dev))
14065 return;
14066
14067 tg3_full_lock(tp, 0);
14068 __tg3_set_rx_mode(dev);
14069 tg3_full_unlock(tp);
14070}
14071
faf1627a
MC		 14072static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14073 int new_mtu)
14074{
14075 dev->mtu = new_mtu;
14076
14077 if (new_mtu > ETH_DATA_LEN) {
14078 if (tg3_flag(tp, 5780_CLASS)) {
14079 netdev_update_features(dev);
14080 tg3_flag_clear(tp, TSO_CAPABLE);
14081 } else {
14082 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14083 }
14084 } else {
14085 if (tg3_flag(tp, 5780_CLASS)) {
14086 tg3_flag_set(tp, TSO_CAPABLE);
14087 netdev_update_features(dev);
14088 }
14089 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14090 }
14091}
14092
14093static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14094{
14095 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 14096 int err;
14097 bool reset_phy = false;
faf1627a
MC		 14098
14099 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14100 return -EINVAL;
14101
14102 if (!netif_running(dev)) {
14103 /* We'll just catch it later when the
14104 * device is up'd.
14105 */
14106 tg3_set_mtu(dev, tp, new_mtu);
14107 return 0;
14108 }
14109
14110 tg3_phy_stop(tp);
14111
14112 tg3_netif_stop(tp);
14113
c6993dfd
NS		 14114 tg3_set_mtu(dev, tp, new_mtu);
14115
faf1627a
MC		 14116 tg3_full_lock(tp, 1);
14117
14118 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14119
2fae5e36
MC		 14120 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14121 * breaks all requests to 256 bytes.
14122 */
4153577a 14123 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 14124 reset_phy = true;
2fae5e36
MC		 14125
14126 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 14127
14128 if (!err)
14129 tg3_netif_start(tp);
14130
14131 tg3_full_unlock(tp);
14132
14133 if (!err)
14134 tg3_phy_start(tp);
14135
14136 return err;
14137}
14138
14139static const struct net_device_ops tg3_netdev_ops = {
14140 .ndo_open = tg3_open,
14141 .ndo_stop = tg3_close,
14142 .ndo_start_xmit = tg3_start_xmit,
14143 .ndo_get_stats64 = tg3_get_stats64,
14144 .ndo_validate_addr = eth_validate_addr,
14145 .ndo_set_rx_mode = tg3_set_rx_mode,
14146 .ndo_set_mac_address = tg3_set_mac_addr,
14147 .ndo_do_ioctl = tg3_ioctl,
14148 .ndo_tx_timeout = tg3_tx_timeout,
14149 .ndo_change_mtu = tg3_change_mtu,
14150 .ndo_fix_features = tg3_fix_features,
14151 .ndo_set_features = tg3_set_features,
14152#ifdef CONFIG_NET_POLL_CONTROLLER
14153 .ndo_poll_controller = tg3_poll_controller,
14154#endif
14155};
14156
229b1ad1 14157static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14158{
1b27777a 14159 u32 cursize, val, magic;
1da177e4
LT		 14160
14161 tp->nvram_size = EEPROM_CHIP_SIZE;
14162
e4f34110 14163 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14164 return;
14165
b16250e3
MC		 14166 if ((magic != TG3_EEPROM_MAGIC) &&
14167 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14168 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14169 return;
14170
14171 /*
14172 * Size the chip by reading offsets at increasing powers of two.
14173 * When we encounter our validation signature, we know the addressing
14174 * has wrapped around, and thus have our chip size.
14175 */
1b27777a 14176 cursize = 0x10;
1da177e4
LT		 14177
14178 while (cursize < tp->nvram_size) {
e4f34110 14179 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14180 return;
14181
1820180b 14182 if (val == magic)
1da177e4
LT		 14183 break;
14184
14185 cursize <<= 1;
14186 }
14187
14188 tp->nvram_size = cursize;
14189}
6aa20a22 14190
229b1ad1 14191static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14192{
14193 u32 val;
14194
63c3a66f 14195 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14196 return;
14197
14198 /* Selfboot format */
1820180b 14199 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14200 tg3_get_eeprom_size(tp);
14201 return;
14202 }
14203
6d348f2c 14204 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14205 if (val != 0) {
6d348f2c
MC		 14206 /* This is confusing. We want to operate on the
14207 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14208 * call will read from NVRAM and byteswap the data
14209 * according to the byteswapping settings for all
14210 * other register accesses. This ensures the data we
14211 * want will always reside in the lower 16-bits.
14212 * However, the data in NVRAM is in LE format, which
14213 * means the data from the NVRAM read will always be
14214 * opposite the endianness of the CPU. The 16-bit
14215 * byteswap then brings the data to CPU endianness.
14216 */
14217 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14218 return;
14219 }
14220 }
fd1122a2 14221 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14222}
14223
229b1ad1 14224static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14225{
14226 u32 nvcfg1;
14227
14228 nvcfg1 = tr32(NVRAM_CFG1);
14229 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14230 tg3_flag_set(tp, FLASH);
8590a603 14231 } else {
1da177e4
LT		 14232 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14233 tw32(NVRAM_CFG1, nvcfg1);
14234 }
14235
4153577a 14236 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14237 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14238 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14239 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14240 tp->nvram_jedecnum = JEDEC_ATMEL;
14241 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14242 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14243 break;
14244 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14245 tp->nvram_jedecnum = JEDEC_ATMEL;
14246 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14247 break;
14248 case FLASH_VENDOR_ATMEL_EEPROM:
14249 tp->nvram_jedecnum = JEDEC_ATMEL;
14250 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14251 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14252 break;
14253 case FLASH_VENDOR_ST:
14254 tp->nvram_jedecnum = JEDEC_ST;
14255 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14256 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14257 break;
14258 case FLASH_VENDOR_SAIFUN:
14259 tp->nvram_jedecnum = JEDEC_SAIFUN;
14260 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14261 break;
14262 case FLASH_VENDOR_SST_SMALL:
14263 case FLASH_VENDOR_SST_LARGE:
14264 tp->nvram_jedecnum = JEDEC_SST;
14265 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14266 break;
1da177e4 14267 }
8590a603 14268 } else {
1da177e4
LT		 14269 tp->nvram_jedecnum = JEDEC_ATMEL;
14270 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14271 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14272 }
14273}
14274
229b1ad1 14275static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14276{
14277 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14278 case FLASH_5752PAGE_SIZE_256:
14279 tp->nvram_pagesize = 256;
14280 break;
14281 case FLASH_5752PAGE_SIZE_512:
14282 tp->nvram_pagesize = 512;
14283 break;
14284 case FLASH_5752PAGE_SIZE_1K:
14285 tp->nvram_pagesize = 1024;
14286 break;
14287 case FLASH_5752PAGE_SIZE_2K:
14288 tp->nvram_pagesize = 2048;
14289 break;
14290 case FLASH_5752PAGE_SIZE_4K:
14291 tp->nvram_pagesize = 4096;
14292 break;
14293 case FLASH_5752PAGE_SIZE_264:
14294 tp->nvram_pagesize = 264;
14295 break;
14296 case FLASH_5752PAGE_SIZE_528:
14297 tp->nvram_pagesize = 528;
14298 break;
14299 }
14300}
14301
229b1ad1 14302static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14303{
14304 u32 nvcfg1;
14305
14306 nvcfg1 = tr32(NVRAM_CFG1);
14307
e6af301b
MC		 14308 /* NVRAM protection for TPM */
14309 if (nvcfg1 & (1 << 27))
63c3a66f 14310 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14311
361b4ac2 14312 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14313 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14314 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14315 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14316 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14317 break;
14318 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14319 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14320 tg3_flag_set(tp, NVRAM_BUFFERED);
14321 tg3_flag_set(tp, FLASH);
8590a603
MC		 14322 break;
14323 case FLASH_5752VENDOR_ST_M45PE10:
14324 case FLASH_5752VENDOR_ST_M45PE20:
14325 case FLASH_5752VENDOR_ST_M45PE40:
14326 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14327 tg3_flag_set(tp, NVRAM_BUFFERED);
14328 tg3_flag_set(tp, FLASH);
8590a603 14329 break;
361b4ac2
MC		 14330 }
14331
63c3a66f 14332 if (tg3_flag(tp, FLASH)) {
a1b950d5 14333 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14334 } else {
361b4ac2
MC		 14335 /* For eeprom, set pagesize to maximum eeprom size */
14336 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14337
14338 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14339 tw32(NVRAM_CFG1, nvcfg1);
14340 }
14341}
14342
229b1ad1 14343static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14344{
989a9d23 14345 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14346
14347 nvcfg1 = tr32(NVRAM_CFG1);
14348
14349 /* NVRAM protection for TPM */
989a9d23 14350 if (nvcfg1 & (1 << 27)) {
63c3a66f 14351 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14352 protect = 1;
14353 }
d3c7b886 14354
989a9d23
MC		 14355 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14356 switch (nvcfg1) {
8590a603
MC		 14357 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14358 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14359 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14360 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14361 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14362 tg3_flag_set(tp, NVRAM_BUFFERED);
14363 tg3_flag_set(tp, FLASH);
8590a603
MC		 14364 tp->nvram_pagesize = 264;
14365 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14366 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14367 tp->nvram_size = (protect ? 0x3e200 :
14368 TG3_NVRAM_SIZE_512KB);
14369 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14370 tp->nvram_size = (protect ? 0x1f200 :
14371 TG3_NVRAM_SIZE_256KB);
14372 else
14373 tp->nvram_size = (protect ? 0x1f200 :
14374 TG3_NVRAM_SIZE_128KB);
14375 break;
14376 case FLASH_5752VENDOR_ST_M45PE10:
14377 case FLASH_5752VENDOR_ST_M45PE20:
14378 case FLASH_5752VENDOR_ST_M45PE40:
14379 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14380 tg3_flag_set(tp, NVRAM_BUFFERED);
14381 tg3_flag_set(tp, FLASH);
8590a603
MC		 14382 tp->nvram_pagesize = 256;
14383 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14384 tp->nvram_size = (protect ?
14385 TG3_NVRAM_SIZE_64KB :
14386 TG3_NVRAM_SIZE_128KB);
14387 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14388 tp->nvram_size = (protect ?
14389 TG3_NVRAM_SIZE_64KB :
14390 TG3_NVRAM_SIZE_256KB);
14391 else
14392 tp->nvram_size = (protect ?
14393 TG3_NVRAM_SIZE_128KB :
14394 TG3_NVRAM_SIZE_512KB);
14395 break;
d3c7b886
MC		 14396 }
14397}
14398
229b1ad1 14399static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14400{
14401 u32 nvcfg1;
14402
14403 nvcfg1 = tr32(NVRAM_CFG1);
14404
14405 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14406 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14407 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14408 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14409 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14410 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14411 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14412 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14413
8590a603
MC		 14414 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14415 tw32(NVRAM_CFG1, nvcfg1);
14416 break;
14417 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14418 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14419 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14420 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14421 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14422 tg3_flag_set(tp, NVRAM_BUFFERED);
14423 tg3_flag_set(tp, FLASH);
8590a603
MC		 14424 tp->nvram_pagesize = 264;
14425 break;
14426 case FLASH_5752VENDOR_ST_M45PE10:
14427 case FLASH_5752VENDOR_ST_M45PE20:
14428 case FLASH_5752VENDOR_ST_M45PE40:
14429 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14430 tg3_flag_set(tp, NVRAM_BUFFERED);
14431 tg3_flag_set(tp, FLASH);
8590a603
MC		 14432 tp->nvram_pagesize = 256;
14433 break;
1b27777a
MC		 14434 }
14435}
14436
229b1ad1 14437static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14438{
14439 u32 nvcfg1, protect = 0;
14440
14441 nvcfg1 = tr32(NVRAM_CFG1);
14442
14443 /* NVRAM protection for TPM */
14444 if (nvcfg1 & (1 << 27)) {
63c3a66f 14445 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14446 protect = 1;
14447 }
14448
14449 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14450 switch (nvcfg1) {
8590a603
MC		 14451 case FLASH_5761VENDOR_ATMEL_ADB021D:
14452 case FLASH_5761VENDOR_ATMEL_ADB041D:
14453 case FLASH_5761VENDOR_ATMEL_ADB081D:
14454 case FLASH_5761VENDOR_ATMEL_ADB161D:
14455 case FLASH_5761VENDOR_ATMEL_MDB021D:
14456 case FLASH_5761VENDOR_ATMEL_MDB041D:
14457 case FLASH_5761VENDOR_ATMEL_MDB081D:
14458 case FLASH_5761VENDOR_ATMEL_MDB161D:
14459 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14460 tg3_flag_set(tp, NVRAM_BUFFERED);
14461 tg3_flag_set(tp, FLASH);
14462 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14463 tp->nvram_pagesize = 256;
14464 break;
14465 case FLASH_5761VENDOR_ST_A_M45PE20:
14466 case FLASH_5761VENDOR_ST_A_M45PE40:
14467 case FLASH_5761VENDOR_ST_A_M45PE80:
14468 case FLASH_5761VENDOR_ST_A_M45PE16:
14469 case FLASH_5761VENDOR_ST_M_M45PE20:
14470 case FLASH_5761VENDOR_ST_M_M45PE40:
14471 case FLASH_5761VENDOR_ST_M_M45PE80:
14472 case FLASH_5761VENDOR_ST_M_M45PE16:
14473 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14474 tg3_flag_set(tp, NVRAM_BUFFERED);
14475 tg3_flag_set(tp, FLASH);
8590a603
MC		 14476 tp->nvram_pagesize = 256;
14477 break;
6b91fa02
MC		 14478 }
14479
14480 if (protect) {
14481 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14482 } else {
14483 switch (nvcfg1) {
8590a603
MC		 14484 case FLASH_5761VENDOR_ATMEL_ADB161D:
14485 case FLASH_5761VENDOR_ATMEL_MDB161D:
14486 case FLASH_5761VENDOR_ST_A_M45PE16:
14487 case FLASH_5761VENDOR_ST_M_M45PE16:
14488 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14489 break;
14490 case FLASH_5761VENDOR_ATMEL_ADB081D:
14491 case FLASH_5761VENDOR_ATMEL_MDB081D:
14492 case FLASH_5761VENDOR_ST_A_M45PE80:
14493 case FLASH_5761VENDOR_ST_M_M45PE80:
14494 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14495 break;
14496 case FLASH_5761VENDOR_ATMEL_ADB041D:
14497 case FLASH_5761VENDOR_ATMEL_MDB041D:
14498 case FLASH_5761VENDOR_ST_A_M45PE40:
14499 case FLASH_5761VENDOR_ST_M_M45PE40:
14500 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14501 break;
14502 case FLASH_5761VENDOR_ATMEL_ADB021D:
14503 case FLASH_5761VENDOR_ATMEL_MDB021D:
14504 case FLASH_5761VENDOR_ST_A_M45PE20:
14505 case FLASH_5761VENDOR_ST_M_M45PE20:
14506 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14507 break;
6b91fa02
MC		 14508 }
14509 }
14510}
14511
229b1ad1 14512static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14513{
14514 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14515 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14516 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14517}
14518
229b1ad1 14519static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14520{
14521 u32 nvcfg1;
14522
14523 nvcfg1 = tr32(NVRAM_CFG1);
14524
14525 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14526 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14527 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14528 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14529 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14530 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14531
14532 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14533 tw32(NVRAM_CFG1, nvcfg1);
14534 return;
14535 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14536 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14537 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14538 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14539 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14540 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14541 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14542 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14543 tg3_flag_set(tp, NVRAM_BUFFERED);
14544 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14545
14546 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14547 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14548 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14549 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14550 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14551 break;
14552 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14553 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14554 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14555 break;
14556 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14557 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14558 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14559 break;
14560 }
14561 break;
14562 case FLASH_5752VENDOR_ST_M45PE10:
14563 case FLASH_5752VENDOR_ST_M45PE20:
14564 case FLASH_5752VENDOR_ST_M45PE40:
14565 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14566 tg3_flag_set(tp, NVRAM_BUFFERED);
14567 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14568
14569 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14570 case FLASH_5752VENDOR_ST_M45PE10:
14571 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14572 break;
14573 case FLASH_5752VENDOR_ST_M45PE20:
14574 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14575 break;
14576 case FLASH_5752VENDOR_ST_M45PE40:
14577 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14578 break;
14579 }
14580 break;
14581 default:
63c3a66f 14582 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14583 return;
14584 }
14585
a1b950d5
MC		 14586 tg3_nvram_get_pagesize(tp, nvcfg1);
14587 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14588 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14589}
14590
14591
229b1ad1 14592static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14593{
14594 u32 nvcfg1;
14595
14596 nvcfg1 = tr32(NVRAM_CFG1);
14597
14598 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14599 case FLASH_5717VENDOR_ATMEL_EEPROM:
14600 case FLASH_5717VENDOR_MICRO_EEPROM:
14601 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14602 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14603 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14604
14605 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14606 tw32(NVRAM_CFG1, nvcfg1);
14607 return;
14608 case FLASH_5717VENDOR_ATMEL_MDB011D:
14609 case FLASH_5717VENDOR_ATMEL_ADB011B:
14610 case FLASH_5717VENDOR_ATMEL_ADB011D:
14611 case FLASH_5717VENDOR_ATMEL_MDB021D:
14612 case FLASH_5717VENDOR_ATMEL_ADB021B:
14613 case FLASH_5717VENDOR_ATMEL_ADB021D:
14614 case FLASH_5717VENDOR_ATMEL_45USPT:
14615 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14616 tg3_flag_set(tp, NVRAM_BUFFERED);
14617 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14618
14619 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14620 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14621 /* Detect size with tg3_nvram_get_size() */
14622 break;
a1b950d5
MC		 14623 case FLASH_5717VENDOR_ATMEL_ADB021B:
14624 case FLASH_5717VENDOR_ATMEL_ADB021D:
14625 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14626 break;
14627 default:
14628 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14629 break;
14630 }
321d32a0 14631 break;
a1b950d5
MC		 14632 case FLASH_5717VENDOR_ST_M_M25PE10:
14633 case FLASH_5717VENDOR_ST_A_M25PE10:
14634 case FLASH_5717VENDOR_ST_M_M45PE10:
14635 case FLASH_5717VENDOR_ST_A_M45PE10:
14636 case FLASH_5717VENDOR_ST_M_M25PE20:
14637 case FLASH_5717VENDOR_ST_A_M25PE20:
14638 case FLASH_5717VENDOR_ST_M_M45PE20:
14639 case FLASH_5717VENDOR_ST_A_M45PE20:
14640 case FLASH_5717VENDOR_ST_25USPT:
14641 case FLASH_5717VENDOR_ST_45USPT:
14642 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14643 tg3_flag_set(tp, NVRAM_BUFFERED);
14644 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14645
14646 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14647 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14648 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14649 /* Detect size with tg3_nvram_get_size() */
14650 break;
14651 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14652 case FLASH_5717VENDOR_ST_A_M45PE20:
14653 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14654 break;
14655 default:
14656 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14657 break;
14658 }
321d32a0 14659 break;
a1b950d5 14660 default:
63c3a66f 14661 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14662 return;
321d32a0 14663 }
a1b950d5
MC		 14664
14665 tg3_nvram_get_pagesize(tp, nvcfg1);
14666 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14667 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14668}
14669
229b1ad1 14670static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14671{
14672 u32 nvcfg1, nvmpinstrp;
14673
14674 nvcfg1 = tr32(NVRAM_CFG1);
14675 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14676
4153577a 14677 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14678 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14679 tg3_flag_set(tp, NO_NVRAM);
14680 return;
14681 }
14682
14683 switch (nvmpinstrp) {
14684 case FLASH_5762_EEPROM_HD:
14685 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14686 break;
c86a8560
MC		 14687 case FLASH_5762_EEPROM_LD:
14688 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14689 break;
f6334bb8
MC		 14690 case FLASH_5720VENDOR_M_ST_M45PE20:
14691 /* This pinstrap supports multiple sizes, so force it
14692 * to read the actual size from location 0xf0.
14693 */
14694 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14695 break;
c86a8560
MC		 14696 }
14697 }
14698
9b91b5f1
MC		 14699 switch (nvmpinstrp) {
14700 case FLASH_5720_EEPROM_HD:
14701 case FLASH_5720_EEPROM_LD:
14702 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14703 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14704
14705 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14706 tw32(NVRAM_CFG1, nvcfg1);
14707 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14708 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14709 else
14710 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14711 return;
14712 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14713 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14714 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14715 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14716 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14717 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14718 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14719 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14720 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14721 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14722 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14723 case FLASH_5720VENDOR_ATMEL_45USPT:
14724 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14725 tg3_flag_set(tp, NVRAM_BUFFERED);
14726 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14727
14728 switch (nvmpinstrp) {
14729 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14730 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14731 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14732 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14733 break;
14734 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14735 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14736 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14737 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14738 break;
14739 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14740 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14741 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14742 break;
14743 default:
4153577a 14744 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14745 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14746 break;
14747 }
14748 break;
14749 case FLASH_5720VENDOR_M_ST_M25PE10:
14750 case FLASH_5720VENDOR_M_ST_M45PE10:
14751 case FLASH_5720VENDOR_A_ST_M25PE10:
14752 case FLASH_5720VENDOR_A_ST_M45PE10:
14753 case FLASH_5720VENDOR_M_ST_M25PE20:
14754 case FLASH_5720VENDOR_M_ST_M45PE20:
14755 case FLASH_5720VENDOR_A_ST_M25PE20:
14756 case FLASH_5720VENDOR_A_ST_M45PE20:
14757 case FLASH_5720VENDOR_M_ST_M25PE40:
14758 case FLASH_5720VENDOR_M_ST_M45PE40:
14759 case FLASH_5720VENDOR_A_ST_M25PE40:
14760 case FLASH_5720VENDOR_A_ST_M45PE40:
14761 case FLASH_5720VENDOR_M_ST_M25PE80:
14762 case FLASH_5720VENDOR_M_ST_M45PE80:
14763 case FLASH_5720VENDOR_A_ST_M25PE80:
14764 case FLASH_5720VENDOR_A_ST_M45PE80:
14765 case FLASH_5720VENDOR_ST_25USPT:
14766 case FLASH_5720VENDOR_ST_45USPT:
14767 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14768 tg3_flag_set(tp, NVRAM_BUFFERED);
14769 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14770
14771 switch (nvmpinstrp) {
14772 case FLASH_5720VENDOR_M_ST_M25PE20:
14773 case FLASH_5720VENDOR_M_ST_M45PE20:
14774 case FLASH_5720VENDOR_A_ST_M25PE20:
14775 case FLASH_5720VENDOR_A_ST_M45PE20:
14776 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14777 break;
14778 case FLASH_5720VENDOR_M_ST_M25PE40:
14779 case FLASH_5720VENDOR_M_ST_M45PE40:
14780 case FLASH_5720VENDOR_A_ST_M25PE40:
14781 case FLASH_5720VENDOR_A_ST_M45PE40:
14782 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14783 break;
14784 case FLASH_5720VENDOR_M_ST_M25PE80:
14785 case FLASH_5720VENDOR_M_ST_M45PE80:
14786 case FLASH_5720VENDOR_A_ST_M25PE80:
14787 case FLASH_5720VENDOR_A_ST_M45PE80:
14788 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14789 break;
14790 default:
4153577a 14791 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14792 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14793 break;
14794 }
14795 break;
14796 default:
63c3a66f 14797 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14798 return;
14799 }
14800
14801 tg3_nvram_get_pagesize(tp, nvcfg1);
14802 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14803 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14804
4153577a 14805 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14806 u32 val;
14807
14808 if (tg3_nvram_read(tp, 0, &val))
14809 return;
14810
14811 if (val != TG3_EEPROM_MAGIC &&
14812 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14813 tg3_flag_set(tp, NO_NVRAM);
14814 }
9b91b5f1
MC		 14815}
14816
1da177e4 14817/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14818static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14819{
7e6c63f0
HM		 14820 if (tg3_flag(tp, IS_SSB_CORE)) {
14821 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14822 tg3_flag_clear(tp, NVRAM);
14823 tg3_flag_clear(tp, NVRAM_BUFFERED);
14824 tg3_flag_set(tp, NO_NVRAM);
14825 return;
14826 }
14827
1da177e4
LT		 14828 tw32_f(GRC_EEPROM_ADDR,
14829 (EEPROM_ADDR_FSM_RESET |
14830 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14831 EEPROM_ADDR_CLKPERD_SHIFT)));
14832
9d57f01c 14833 msleep(1);
1da177e4
LT		 14834
14835 /* Enable seeprom accesses. */
14836 tw32_f(GRC_LOCAL_CTRL,
14837 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14838 udelay(100);
14839
4153577a
JP		 14840 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14841 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14842 tg3_flag_set(tp, NVRAM);
1da177e4 14843
ec41c7df 14844 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14845 netdev_warn(tp->dev,
14846 "Cannot get nvram lock, %s failed\n",
05dbe005 14847 __func__);
ec41c7df
MC		 14848 return;
14849 }
e6af301b 14850 tg3_enable_nvram_access(tp);
1da177e4 14851
989a9d23
MC		 14852 tp->nvram_size = 0;
14853
4153577a 14854 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14855 tg3_get_5752_nvram_info(tp);
4153577a 14856 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14857 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14858 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14859 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14860 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14861 tg3_get_5787_nvram_info(tp);
4153577a 14862 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14863 tg3_get_5761_nvram_info(tp);
4153577a 14864 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14865 tg3_get_5906_nvram_info(tp);
4153577a 14866 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14867 tg3_flag(tp, 57765_CLASS))
321d32a0 14868 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14869 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14870 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14871 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14872 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14873 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14874 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14875 else
14876 tg3_get_nvram_info(tp);
14877
989a9d23
MC		 14878 if (tp->nvram_size == 0)
14879 tg3_get_nvram_size(tp);
1da177e4 14880
e6af301b 14881 tg3_disable_nvram_access(tp);
381291b7 14882 tg3_nvram_unlock(tp);
1da177e4
LT		 14883
14884 } else {
63c3a66f
JP		 14885 tg3_flag_clear(tp, NVRAM);
14886 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14887
14888 tg3_get_eeprom_size(tp);
14889 }
14890}
14891
1da177e4
LT		 14892struct subsys_tbl_ent {
14893 u16 subsys_vendor, subsys_devid;
14894 u32 phy_id;
14895};
14896
229b1ad1 14897static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14898 /* Broadcom boards. */
24daf2b0 14899 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14900 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14901 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14902 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14903 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14904 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14905 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14906 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14907 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14908 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14909 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14910 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14911 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14912 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14913 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14914 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14915 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14916 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14917 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14918 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14919 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14920 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14921
14922 /* 3com boards. */
24daf2b0 14923 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14924 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 14925 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14926 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14927 { TG3PCI_SUBVENDOR_ID_3COM,
14928 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14929 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14930 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 14931 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14932 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14933
14934 /* DELL boards. */
24daf2b0 14935 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14936 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 14937 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14938 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 14939 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14940 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 14941 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14942 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 14943
14944 /* Compaq boards. */
24daf2b0 14945 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14946 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 14947 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14948 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14949 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14950 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14951 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14952 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 14953 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14954 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14955
14956 /* IBM boards. */
24daf2b0
MC		 14957 { TG3PCI_SUBVENDOR_ID_IBM,
14958 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 14959};
14960
229b1ad1 14961static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 14962{
14963 int i;
14964
14965 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14966 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14967 tp->pdev->subsystem_vendor) &&
14968 (subsys_id_to_phy_id[i].subsys_devid ==
14969 tp->pdev->subsystem_device))
14970 return &subsys_id_to_phy_id[i];
14971 }
14972 return NULL;
14973}
14974
229b1ad1 14975static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 14976{
1da177e4 14977 u32 val;
f49639e6 14978
79eb6904 14979 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 14980 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14981
a85feb8c 14982 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 14983 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14984 tg3_flag_set(tp, WOL_CAP);
72b845e0 14985
4153577a 14986 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 14987 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 14988 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14989 tg3_flag_set(tp, IS_NIC);
9d26e213 14990 }
0527ba35
MC		 14991 val = tr32(VCPU_CFGSHDW);
14992 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 14993 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 14994 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 14995 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 14996 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14997 device_set_wakeup_enable(&tp->pdev->dev, true);
14998 }
05ac4cb7 14999 goto done;
b5d3772c
MC		 15000 }
15001
1da177e4
LT		 15002 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15003 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15004 u32 nic_cfg, led_cfg;
7c786065
NS		 15005 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15006 u32 nic_phy_id, ver, eeprom_phy_id;
7d0c41ef 15007 int eeprom_phy_serdes = 0;
1da177e4
LT		 15008
15009 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15010 tp->nic_sram_data_cfg = nic_cfg;
15011
15012 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15013 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 15014 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15015 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15016 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 15017 (ver > 0) && (ver < 0x100))
15018 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15019
4153577a 15020 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 15021 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15022
7c786065
NS		 15023 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15024 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15025 tg3_asic_rev(tp) == ASIC_REV_5720)
15026 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15027
1da177e4
LT		 15028 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15029 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15030 eeprom_phy_serdes = 1;
15031
15032 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15033 if (nic_phy_id != 0) {
15034 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15035 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15036
15037 eeprom_phy_id = (id1 >> 16) << 10;
15038 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15039 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15040 } else
15041 eeprom_phy_id = 0;
15042
7d0c41ef 15043 tp->phy_id = eeprom_phy_id;
747e8f8b 15044 if (eeprom_phy_serdes) {
63c3a66f 15045 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 15046 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 15047 else
f07e9af3 15048 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 15049 }
7d0c41ef 15050
63c3a66f 15051 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 15052 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15053 SHASTA_EXT_LED_MODE_MASK);
cbf46853 15054 else
1da177e4
LT		 15055 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15056
15057 switch (led_cfg) {
15058 default:
15059 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15060 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15061 break;
15062
15063 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15064 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15065 break;
15066
15067 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15068 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 15069
15070 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15071 * read on some older 5700/5701 bootcode.
15072 */
4153577a
JP		 15073 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15074 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 15075 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15076
1da177e4
LT		 15077 break;
15078
15079 case SHASTA_EXT_LED_SHARED:
15080 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 15081 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15082 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 15083 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15084 LED_CTRL_MODE_PHY_2);
89f67978
NS		 15085
15086 if (tg3_flag(tp, 5717_PLUS) ||
15087 tg3_asic_rev(tp) == ASIC_REV_5762)
15088 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15089 LED_CTRL_BLINK_RATE_MASK;
15090
1da177e4
LT		 15091 break;
15092
15093 case SHASTA_EXT_LED_MAC:
15094 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15095 break;
15096
15097 case SHASTA_EXT_LED_COMBO:
15098 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 15099 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 15100 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15101 LED_CTRL_MODE_PHY_2);
15102 break;
15103
855e1111 15104 }
1da177e4 15105
4153577a
JP		 15106 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15107 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 15108 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15109 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15110
4153577a 15111 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 15112 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 15113
9d26e213 15114 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 15115 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 15116 if ((tp->pdev->subsystem_vendor ==
15117 PCI_VENDOR_ID_ARIMA) &&
15118 (tp->pdev->subsystem_device == 0x205a ||
15119 tp->pdev->subsystem_device == 0x2063))
63c3a66f 15120 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 15121 } else {
63c3a66f
JP		 15122 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15123 tg3_flag_set(tp, IS_NIC);
9d26e213 15124 }
1da177e4
LT		 15125
15126 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 15127 tg3_flag_set(tp, ENABLE_ASF);
15128 if (tg3_flag(tp, 5750_PLUS))
15129 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 15130 }
b2b98d4a
MC		 15131
15132 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 15133 tg3_flag(tp, 5750_PLUS))
15134 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 15135
f07e9af3 15136 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 15137 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 15138 tg3_flag_clear(tp, WOL_CAP);
1da177e4 15139
63c3a66f 15140 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 15141 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 15142 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15143 device_set_wakeup_enable(&tp->pdev->dev, true);
15144 }
0527ba35 15145
1da177e4 15146 if (cfg2 & (1 << 17))
f07e9af3 15147 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 15148
15149 /* serdes signal pre-emphasis in register 0x590 set by */
15150 /* bootcode if bit 18 is set */
15151 if (cfg2 & (1 << 18))
f07e9af3 15152 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 15153
63c3a66f 15154 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 15155 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15156 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 15157 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 15158 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 15159
942d1af0 15160 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 15161 u32 cfg3;
15162
15163 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 15164 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15165 !tg3_flag(tp, 57765_PLUS) &&
15166 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15167 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15168 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15169 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15170 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15171 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15172 }
a9daf367 15173
14417063 15174 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15175 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15176 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15177 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15178 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15179 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
7c786065
NS		 15180
15181 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15182 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
1da177e4 15183 }
05ac4cb7 15184done:
63c3a66f 15185 if (tg3_flag(tp, WOL_CAP))
43067ed8 15186 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15187 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15188 else
15189 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15190}
15191
c86a8560
MC		 15192static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15193{
15194 int i, err;
15195 u32 val2, off = offset * 8;
15196
15197 err = tg3_nvram_lock(tp);
15198 if (err)
15199 return err;
15200
15201 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15202 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15203 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15204 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15205 udelay(10);
15206
15207 for (i = 0; i < 100; i++) {
15208 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15209 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15210 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15211 break;
15212 }
15213 udelay(10);
15214 }
15215
15216 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15217
15218 tg3_nvram_unlock(tp);
15219 if (val2 & APE_OTP_STATUS_CMD_DONE)
15220 return 0;
15221
15222 return -EBUSY;
15223}
15224
229b1ad1 15225static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15226{
15227 int i;
15228 u32 val;
15229
15230 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15231 tw32(OTP_CTRL, cmd);
15232
15233 /* Wait for up to 1 ms for command to execute. */
15234 for (i = 0; i < 100; i++) {
15235 val = tr32(OTP_STATUS);
15236 if (val & OTP_STATUS_CMD_DONE)
15237 break;
15238 udelay(10);
15239 }
15240
15241 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15242}
15243
15244/* Read the gphy configuration from the OTP region of the chip. The gphy
15245 * configuration is a 32-bit value that straddles the alignment boundary.
15246 * We do two 32-bit reads and then shift and merge the results.
15247 */
229b1ad1 15248static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15249{
15250 u32 bhalf_otp, thalf_otp;
15251
15252 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15253
15254 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15255 return 0;
15256
15257 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15258
15259 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15260 return 0;
15261
15262 thalf_otp = tr32(OTP_READ_DATA);
15263
15264 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15265
15266 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15267 return 0;
15268
15269 bhalf_otp = tr32(OTP_READ_DATA);
15270
15271 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15272}
15273
229b1ad1 15274static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15275{
202ff1c2 15276 u32 adv = ADVERTISED_Autoneg;
e256f8a3 15277
7c786065
NS		 15278 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15279 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15280 adv |= ADVERTISED_1000baseT_Half;
15281 adv |= ADVERTISED_1000baseT_Full;
15282 }
e256f8a3
MC		 15283
15284 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15285 adv |= ADVERTISED_100baseT_Half |
15286 ADVERTISED_100baseT_Full |
15287 ADVERTISED_10baseT_Half |
15288 ADVERTISED_10baseT_Full |
15289 ADVERTISED_TP;
15290 else
15291 adv |= ADVERTISED_FIBRE;
15292
15293 tp->link_config.advertising = adv;
e740522e
MC		 15294 tp->link_config.speed = SPEED_UNKNOWN;
15295 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15296 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15297 tp->link_config.active_speed = SPEED_UNKNOWN;
15298 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15299
15300 tp->old_link = -1;
e256f8a3
MC		 15301}
15302
229b1ad1 15303static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15304{
15305 u32 hw_phy_id_1, hw_phy_id_2;
15306 u32 hw_phy_id, hw_phy_id_masked;
15307 int err;
1da177e4 15308
e256f8a3 15309 /* flow control autonegotiation is default behavior */
63c3a66f 15310 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15311 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15312
8151ad57
MC		 15313 if (tg3_flag(tp, ENABLE_APE)) {
15314 switch (tp->pci_fn) {
15315 case 0:
15316 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15317 break;
15318 case 1:
15319 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15320 break;
15321 case 2:
15322 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15323 break;
15324 case 3:
15325 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15326 break;
15327 }
15328 }
15329
942d1af0
NS		 15330 if (!tg3_flag(tp, ENABLE_ASF) &&
15331 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15332 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15333 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15334 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15335
63c3a66f 15336 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15337 return tg3_phy_init(tp);
15338
1da177e4 15339 /* Reading the PHY ID register can conflict with ASF
877d0310 15340 * firmware access to the PHY hardware.
1da177e4
LT		 15341 */
15342 err = 0;
63c3a66f 15343 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15344 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15345 } else {
15346 /* Now read the physical PHY_ID from the chip and verify
15347 * that it is sane. If it doesn't look good, we fall back
15348 * to either the hard-coded table based PHY_ID and failing
15349 * that the value found in the eeprom area.
15350 */
15351 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15352 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15353
15354 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15355 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15356 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15357
79eb6904 15358 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15359 }
15360
79eb6904 15361 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15362 tp->phy_id = hw_phy_id;
79eb6904 15363 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15364 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15365 else
f07e9af3 15366 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15367 } else {
79eb6904 15368 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15369 /* Do nothing, phy ID already set up in
15370 * tg3_get_eeprom_hw_cfg().
15371 */
1da177e4
LT		 15372 } else {
15373 struct subsys_tbl_ent *p;
15374
15375 /* No eeprom signature? Try the hardcoded
15376 * subsys device table.
15377 */
24daf2b0 15378 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15379 if (p) {
15380 tp->phy_id = p->phy_id;
15381 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15382 /* For now we saw the IDs 0xbc050cd0,
15383 * 0xbc050f80 and 0xbc050c30 on devices
15384 * connected to an BCM4785 and there are
15385 * probably more. Just assume that the phy is
15386 * supported when it is connected to a SSB core
15387 * for now.
15388 */
1da177e4 15389 return -ENODEV;
7e6c63f0 15390 }
1da177e4 15391
1da177e4 15392 if (!tp->phy_id ||
79eb6904 15393 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15394 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15395 }
15396 }
15397
a6b68dab 15398 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15399 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15400 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15401 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15402 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15403 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15404 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15405 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15406 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15407 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15408
9e2ecbeb
NS		 15409 tp->eee.supported = SUPPORTED_100baseT_Full |
15410 SUPPORTED_1000baseT_Full;
15411 tp->eee.advertised = ADVERTISED_100baseT_Full |
15412 ADVERTISED_1000baseT_Full;
15413 tp->eee.eee_enabled = 1;
15414 tp->eee.tx_lpi_enabled = 1;
15415 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15416 }
15417
e256f8a3
MC		 15418 tg3_phy_init_link_config(tp);
15419
942d1af0
NS		 15420 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15421 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15422 !tg3_flag(tp, ENABLE_APE) &&
15423 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15424 u32 bmsr, dummy;
1da177e4
LT		 15425
15426 tg3_readphy(tp, MII_BMSR, &bmsr);
15427 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15428 (bmsr & BMSR_LSTATUS))
15429 goto skip_phy_reset;
6aa20a22 15430
1da177e4
LT		 15431 err = tg3_phy_reset(tp);
15432 if (err)
15433 return err;
15434
42b64a45 15435 tg3_phy_set_wirespeed(tp);
1da177e4 15436
e2bf73e7 15437 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15438 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15439 tp->link_config.flowctrl);
1da177e4
LT		 15440
15441 tg3_writephy(tp, MII_BMCR,
15442 BMCR_ANENABLE | BMCR_ANRESTART);
15443 }
1da177e4
LT		 15444 }
15445
15446skip_phy_reset:
79eb6904 15447 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15448 err = tg3_init_5401phy_dsp(tp);
15449 if (err)
15450 return err;
1da177e4 15451
1da177e4
LT		 15452 err = tg3_init_5401phy_dsp(tp);
15453 }
15454
1da177e4
LT		 15455 return err;
15456}
15457
229b1ad1 15458static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15459{
a4a8bb15 15460 u8 *vpd_data;
4181b2c8 15461 unsigned int block_end, rosize, len;
535a490e 15462 u32 vpdlen;
184b8904 15463 int j, i = 0;
a4a8bb15 15464
535a490e 15465 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15466 if (!vpd_data)
15467 goto out_no_vpd;
1da177e4 15468
535a490e 15469 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15470 if (i < 0)
15471 goto out_not_found;
1da177e4 15472
4181b2c8
MC		 15473 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15474 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15475 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15476
535a490e 15477 if (block_end > vpdlen)
4181b2c8 15478 goto out_not_found;
af2c6a4a 15479
184b8904
MC		 15480 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15481 PCI_VPD_RO_KEYWORD_MFR_ID);
15482 if (j > 0) {
15483 len = pci_vpd_info_field_size(&vpd_data[j]);
15484
15485 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15486 if (j + len > block_end || len != 4 ||
15487 memcmp(&vpd_data[j], "1028", 4))
15488 goto partno;
15489
15490 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15491 PCI_VPD_RO_KEYWORD_VENDOR0);
15492 if (j < 0)
15493 goto partno;
15494
15495 len = pci_vpd_info_field_size(&vpd_data[j]);
15496
15497 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15498 if (j + len > block_end)
15499 goto partno;
15500
715230a4
KC		 15501 if (len >= sizeof(tp->fw_ver))
15502 len = sizeof(tp->fw_ver) - 1;
15503 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15504 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15505 &vpd_data[j]);
184b8904
MC		 15506 }
15507
15508partno:
4181b2c8
MC		 15509 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15510 PCI_VPD_RO_KEYWORD_PARTNO);
15511 if (i < 0)
15512 goto out_not_found;
af2c6a4a 15513
4181b2c8 15514 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15515
4181b2c8
MC		 15516 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15517 if (len > TG3_BPN_SIZE ||
535a490e 15518 (len + i) > vpdlen)
4181b2c8 15519 goto out_not_found;
1da177e4 15520
4181b2c8 15521 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15522
1da177e4 15523out_not_found:
a4a8bb15 15524 kfree(vpd_data);
37a949c5 15525 if (tp->board_part_number[0])
a4a8bb15
MC		 15526 return;
15527
15528out_no_vpd:
4153577a 15529 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15530 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15531 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15532 strcpy(tp->board_part_number, "BCM5717");
15533 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15534 strcpy(tp->board_part_number, "BCM5718");
15535 else
15536 goto nomatch;
4153577a 15537 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15538 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15539 strcpy(tp->board_part_number, "BCM57780");
15540 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15541 strcpy(tp->board_part_number, "BCM57760");
15542 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15543 strcpy(tp->board_part_number, "BCM57790");
15544 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15545 strcpy(tp->board_part_number, "BCM57788");
15546 else
15547 goto nomatch;
4153577a 15548 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15549 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15550 strcpy(tp->board_part_number, "BCM57761");
15551 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15552 strcpy(tp->board_part_number, "BCM57765");
15553 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15554 strcpy(tp->board_part_number, "BCM57781");
15555 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15556 strcpy(tp->board_part_number, "BCM57785");
15557 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15558 strcpy(tp->board_part_number, "BCM57791");
15559 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15560 strcpy(tp->board_part_number, "BCM57795");
15561 else
15562 goto nomatch;
4153577a 15563 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15564 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15565 strcpy(tp->board_part_number, "BCM57762");
15566 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15567 strcpy(tp->board_part_number, "BCM57766");
15568 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15569 strcpy(tp->board_part_number, "BCM57782");
15570 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15571 strcpy(tp->board_part_number, "BCM57786");
15572 else
15573 goto nomatch;
4153577a 15574 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15575 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15576 } else {
15577nomatch:
b5d3772c 15578 strcpy(tp->board_part_number, "none");
37a949c5 15579 }
1da177e4
LT		 15580}
15581
229b1ad1 15582static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15583{
15584 u32 val;
15585
e4f34110 15586 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15587 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15588 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15589 val != 0)
15590 return 0;
15591
15592 return 1;
15593}
15594
229b1ad1 15595static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15596{
ff3a7cb2 15597 u32 val, offset, start, ver_offset;
75f9936e 15598 int i, dst_off;
ff3a7cb2 15599 bool newver = false;
acd9c119
MC		 15600
15601 if (tg3_nvram_read(tp, 0xc, &offset) ||
15602 tg3_nvram_read(tp, 0x4, &start))
15603 return;
15604
15605 offset = tg3_nvram_logical_addr(tp, offset);
15606
ff3a7cb2 15607 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15608 return;
15609
ff3a7cb2
MC		 15610 if ((val & 0xfc000000) == 0x0c000000) {
15611 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15612 return;
15613
ff3a7cb2
MC		 15614 if (val == 0)
15615 newver = true;
15616 }
15617
75f9936e
MC		 15618 dst_off = strlen(tp->fw_ver);
15619
ff3a7cb2 15620 if (newver) {
75f9936e
MC		 15621 if (TG3_VER_SIZE - dst_off < 16 ||
15622 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15623 return;
15624
15625 offset = offset + ver_offset - start;
15626 for (i = 0; i < 16; i += 4) {
15627 __be32 v;
15628 if (tg3_nvram_read_be32(tp, offset + i, &v))
15629 return;
15630
75f9936e 15631 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15632 }
15633 } else {
15634 u32 major, minor;
15635
15636 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15637 return;
15638
15639 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15640 TG3_NVM_BCVER_MAJSFT;
15641 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15642 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15643 "v%d.%02d", major, minor);
acd9c119
MC		 15644 }
15645}
15646
229b1ad1 15647static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15648{
15649 u32 val, major, minor;
15650
15651 /* Use native endian representation */
15652 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15653 return;
15654
15655 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15656 TG3_NVM_HWSB_CFG1_MAJSFT;
15657 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15658 TG3_NVM_HWSB_CFG1_MINSFT;
15659
15660 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15661}
15662
229b1ad1 15663static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15664{
15665 u32 offset, major, minor, build;
15666
75f9936e 15667 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15668
15669 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15670 return;
15671
15672 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15673 case TG3_EEPROM_SB_REVISION_0:
15674 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15675 break;
15676 case TG3_EEPROM_SB_REVISION_2:
15677 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15678 break;
15679 case TG3_EEPROM_SB_REVISION_3:
15680 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15681 break;
a4153d40
MC		 15682 case TG3_EEPROM_SB_REVISION_4:
15683 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15684 break;
15685 case TG3_EEPROM_SB_REVISION_5:
15686 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15687 break;
bba226ac
MC		 15688 case TG3_EEPROM_SB_REVISION_6:
15689 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15690 break;
dfe00d7d
MC		 15691 default:
15692 return;
15693 }
15694
e4f34110 15695 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15696 return;
15697
15698 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15699 TG3_EEPROM_SB_EDH_BLD_SHFT;
15700 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15701 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15702 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15703
15704 if (minor > 99 || build > 26)
15705 return;
15706
75f9936e
MC		 15707 offset = strlen(tp->fw_ver);
15708 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15709 " v%d.%02d", major, minor);
dfe00d7d
MC		 15710
15711 if (build > 0) {
75f9936e
MC		 15712 offset = strlen(tp->fw_ver);
15713 if (offset < TG3_VER_SIZE - 1)
15714 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15715 }
15716}
15717
229b1ad1 15718static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15719{
15720 u32 val, offset, start;
acd9c119 15721 int i, vlen;
9c8a620e
MC		 15722
15723 for (offset = TG3_NVM_DIR_START;
15724 offset < TG3_NVM_DIR_END;
15725 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15726 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15727 return;
15728
9c8a620e
MC		 15729 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15730 break;
15731 }
15732
15733 if (offset == TG3_NVM_DIR_END)
15734 return;
15735
63c3a66f 15736 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15737 start = 0x08000000;
e4f34110 15738 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15739 return;
15740
e4f34110 15741 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15742 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15743 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15744 return;
15745
15746 offset += val - start;
15747
acd9c119 15748 vlen = strlen(tp->fw_ver);
9c8a620e 15749
acd9c119
MC		 15750 tp->fw_ver[vlen++] = ',';
15751 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15752
15753 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15754 __be32 v;
15755 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15756 return;
15757
b9fc7dc5 15758 offset += sizeof(v);
c4e6575c 15759
acd9c119
MC		 15760 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15761 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15762 break;
c4e6575c 15763 }
9c8a620e 15764
acd9c119
MC		 15765 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15766 vlen += sizeof(v);
c4e6575c 15767 }
acd9c119
MC		 15768}
15769
229b1ad1 15770static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15771{
7fd76445 15772 u32 apedata;
7fd76445
MC		 15773
15774 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15775 if (apedata != APE_SEG_SIG_MAGIC)
15776 return;
15777
15778 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15779 if (!(apedata & APE_FW_STATUS_READY))
15780 return;
15781
165f4d1c
MC		 15782 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15783 tg3_flag_set(tp, APE_HAS_NCSI);
15784}
15785
229b1ad1 15786static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15787{
15788 int vlen;
15789 u32 apedata;
15790 char *fwtype;
15791
7fd76445
MC		 15792 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15793
165f4d1c 15794 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15795 fwtype = "NCSI";
c86a8560
MC		 15796 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15797 fwtype = "SMASH";
165f4d1c 15798 else
ecc79648
MC		 15799 fwtype = "DASH";
15800
7fd76445
MC		 15801 vlen = strlen(tp->fw_ver);
15802
ecc79648
MC		 15803 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15804 fwtype,
7fd76445
MC		 15805 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15806 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15807 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15808 (apedata & APE_FW_VERSION_BLDMSK));
15809}
15810
c86a8560
MC		 15811static void tg3_read_otp_ver(struct tg3 *tp)
15812{
15813 u32 val, val2;
15814
4153577a 15815 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15816 return;
15817
15818 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15819 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15820 TG3_OTP_MAGIC0_VALID(val)) {
15821 u64 val64 = (u64) val << 32 | val2;
15822 u32 ver = 0;
15823 int i, vlen;
15824
15825 for (i = 0; i < 7; i++) {
15826 if ((val64 & 0xff) == 0)
15827 break;
15828 ver = val64 & 0xff;
15829 val64 >>= 8;
15830 }
15831 vlen = strlen(tp->fw_ver);
15832 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15833 }
15834}
15835
229b1ad1 15836static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15837{
15838 u32 val;
75f9936e 15839 bool vpd_vers = false;
acd9c119 15840
75f9936e
MC		 15841 if (tp->fw_ver[0] != 0)
15842 vpd_vers = true;
df259d8c 15843
63c3a66f 15844 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15845 strcat(tp->fw_ver, "sb");
c86a8560 15846 tg3_read_otp_ver(tp);
df259d8c
MC		 15847 return;
15848 }
15849
acd9c119
MC		 15850 if (tg3_nvram_read(tp, 0, &val))
15851 return;
15852
15853 if (val == TG3_EEPROM_MAGIC)
15854 tg3_read_bc_ver(tp);
15855 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15856 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15857 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15858 tg3_read_hwsb_ver(tp);
acd9c119 15859
165f4d1c
MC		 15860 if (tg3_flag(tp, ENABLE_ASF)) {
15861 if (tg3_flag(tp, ENABLE_APE)) {
15862 tg3_probe_ncsi(tp);
15863 if (!vpd_vers)
15864 tg3_read_dash_ver(tp);
15865 } else if (!vpd_vers) {
15866 tg3_read_mgmtfw_ver(tp);
15867 }
c9cab24e 15868 }
9c8a620e
MC		 15869
15870 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15871}
15872
7cb32cf2
MC		 15873static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15874{
63c3a66f 15875 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15876 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15877 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15878 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15879 else
de9f5230 15880 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15881}
15882
4143470c 15883static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
895950c2
JP		 15884 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15885 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15886 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15887 { },
15888};
15889
229b1ad1 15890static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15891{
15892 struct pci_dev *peer;
15893 unsigned int func, devnr = tp->pdev->devfn & ~7;
15894
15895 for (func = 0; func < 8; func++) {
15896 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15897 if (peer && peer != tp->pdev)
15898 break;
15899 pci_dev_put(peer);
15900 }
15901 /* 5704 can be configured in single-port mode, set peer to
15902 * tp->pdev in that case.
15903 */
15904 if (!peer) {
15905 peer = tp->pdev;
15906 return peer;
15907 }
15908
15909 /*
15910 * We don't need to keep the refcount elevated; there's no way
15911 * to remove one half of this device without removing the other
15912 */
15913 pci_dev_put(peer);
15914
15915 return peer;
15916}
15917
229b1ad1 15918static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15919{
15920 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15921 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15922 u32 reg;
15923
15924 /* All devices that use the alternate
15925 * ASIC REV location have a CPMU.
15926 */
15927 tg3_flag_set(tp, CPMU_PRESENT);
15928
15929 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 15930 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 15931 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15932 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 15933 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 15934 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15935 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 15936 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15937 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 15938 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15939 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
42b123b1
MC		 15940 reg = TG3PCI_GEN2_PRODID_ASICREV;
15941 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15942 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15943 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15944 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15945 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15946 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15947 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15948 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15949 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15950 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15951 reg = TG3PCI_GEN15_PRODID_ASICREV;
15952 else
15953 reg = TG3PCI_PRODID_ASICREV;
15954
15955 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15956 }
15957
15958 /* Wrong chip ID in 5752 A0. This code can be removed later
15959 * as A0 is not in production.
15960 */
4153577a 15961 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 15962 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15963
4153577a 15964 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 15965 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15966
4153577a
JP		 15967 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15968 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15969 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 15970 tg3_flag_set(tp, 5717_PLUS);
15971
4153577a
JP		 15972 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15973 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 15974 tg3_flag_set(tp, 57765_CLASS);
15975
c65a17f4 15976 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 15977 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 15978 tg3_flag_set(tp, 57765_PLUS);
15979
15980 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 15981 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15982 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15983 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15984 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15985 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15986 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 15987 tg3_flag(tp, 57765_PLUS))
15988 tg3_flag_set(tp, 5755_PLUS);
15989
4153577a
JP		 15990 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15991 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 15992 tg3_flag_set(tp, 5780_CLASS);
15993
4153577a
JP		 15994 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15995 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15996 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 15997 tg3_flag(tp, 5755_PLUS) ||
15998 tg3_flag(tp, 5780_CLASS))
15999 tg3_flag_set(tp, 5750_PLUS);
16000
4153577a 16001 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 16002 tg3_flag(tp, 5750_PLUS))
16003 tg3_flag_set(tp, 5705_PLUS);
16004}
16005
3d567e0e
NNS		 16006static bool tg3_10_100_only_device(struct tg3 *tp,
16007 const struct pci_device_id *ent)
16008{
16009 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16010
4153577a
JP		 16011 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16012 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 16013 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16014 return true;
16015
16016 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 16017 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 16018 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16019 return true;
16020 } else {
16021 return true;
16022 }
16023 }
16024
16025 return false;
16026}
16027
1dd06ae8 16028static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 16029{
1da177e4 16030 u32 misc_ctrl_reg;
1da177e4
LT		 16031 u32 pci_state_reg, grc_misc_cfg;
16032 u32 val;
16033 u16 pci_cmd;
5e7dfd0f 16034 int err;
1da177e4 16035
1da177e4
LT		 16036 /* Force memory write invalidate off. If we leave it on,
16037 * then on 5700_BX chips we have to enable a workaround.
16038 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16039 * to match the cacheline size. The Broadcom driver have this
16040 * workaround but turns MWI off all the times so never uses
16041 * it. This seems to suggest that the workaround is insufficient.
16042 */
16043 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16044 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16045 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16046
16821285
MC		 16047 /* Important! -- Make sure register accesses are byteswapped
16048 * correctly. Also, for those chips that require it, make
16049 * sure that indirect register accesses are enabled before
16050 * the first operation.
1da177e4
LT		 16051 */
16052 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16053 &misc_ctrl_reg);
16821285
MC		 16054 tp->misc_host_ctrl |= (misc_ctrl_reg &
16055 MISC_HOST_CTRL_CHIPREV);
16056 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16057 tp->misc_host_ctrl);
1da177e4 16058
42b123b1 16059 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 16060
6892914f
MC		 16061 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16062 * we need to disable memory and use config. cycles
16063 * only to access all registers. The 5702/03 chips
16064 * can mistakenly decode the special cycles from the
16065 * ICH chipsets as memory write cycles, causing corruption
16066 * of register and memory space. Only certain ICH bridges
16067 * will drive special cycles with non-zero data during the
16068 * address phase which can fall within the 5703's address
16069 * range. This is not an ICH bug as the PCI spec allows
16070 * non-zero address during special cycles. However, only
16071 * these ICH bridges are known to drive non-zero addresses
16072 * during special cycles.
16073 *
16074 * Since special cycles do not cross PCI bridges, we only
16075 * enable this workaround if the 5703 is on the secondary
16076 * bus of these ICH bridges.
16077 */
4153577a
JP		 16078 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16079 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 16080 static struct tg3_dev_id {
16081 u32 vendor;
16082 u32 device;
16083 u32 rev;
16084 } ich_chipsets[] = {
16085 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16086 PCI_ANY_ID },
16087 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16088 PCI_ANY_ID },
16089 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16090 0xa },
16091 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16092 PCI_ANY_ID },
16093 { },
16094 };
16095 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16096 struct pci_dev *bridge = NULL;
16097
16098 while (pci_id->vendor != 0) {
16099 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16100 bridge);
16101 if (!bridge) {
16102 pci_id++;
16103 continue;
16104 }
16105 if (pci_id->rev != PCI_ANY_ID) {
44c10138 16106 if (bridge->revision > pci_id->rev)
6892914f
MC		 16107 continue;
16108 }
16109 if (bridge->subordinate &&
16110 (bridge->subordinate->number ==
16111 tp->pdev->bus->number)) {
63c3a66f 16112 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 16113 pci_dev_put(bridge);
16114 break;
16115 }
16116 }
16117 }
16118
4153577a 16119 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 16120 static struct tg3_dev_id {
16121 u32 vendor;
16122 u32 device;
16123 } bridge_chipsets[] = {
16124 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16125 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16126 { },
16127 };
16128 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16129 struct pci_dev *bridge = NULL;
16130
16131 while (pci_id->vendor != 0) {
16132 bridge = pci_get_device(pci_id->vendor,
16133 pci_id->device,
16134 bridge);
16135 if (!bridge) {
16136 pci_id++;
16137 continue;
16138 }
16139 if (bridge->subordinate &&
16140 (bridge->subordinate->number <=
16141 tp->pdev->bus->number) &&
b918c62e 16142 (bridge->subordinate->busn_res.end >=
41588ba1 16143 tp->pdev->bus->number)) {
63c3a66f 16144 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 16145 pci_dev_put(bridge);
16146 break;
16147 }
16148 }
16149 }
16150
4a29cc2e
MC		 16151 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16152 * DMA addresses > 40-bit. This bridge may have other additional
16153 * 57xx devices behind it in some 4-port NIC designs for example.
16154 * Any tg3 device found behind the bridge will also need the 40-bit
16155 * DMA workaround.
16156 */
42b123b1 16157 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 16158 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 16159 tp->msi_cap = tp->pdev->msi_cap;
859a5887 16160 } else {
4a29cc2e
MC		 16161 struct pci_dev *bridge = NULL;
16162
16163 do {
16164 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16165 PCI_DEVICE_ID_SERVERWORKS_EPB,
16166 bridge);
16167 if (bridge && bridge->subordinate &&
16168 (bridge->subordinate->number <=
16169 tp->pdev->bus->number) &&
b918c62e 16170 (bridge->subordinate->busn_res.end >=
4a29cc2e 16171 tp->pdev->bus->number)) {
63c3a66f 16172 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 16173 pci_dev_put(bridge);
16174 break;
16175 }
16176 } while (bridge);
16177 }
4cf78e4f 16178
4153577a
JP		 16179 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16180 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16181 tp->pdev_peer = tg3_find_peer(tp);
16182
507399f1 16183 /* Determine TSO capabilities */
4153577a 16184 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16185 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16186 else if (tg3_flag(tp, 57765_PLUS))
16187 tg3_flag_set(tp, HW_TSO_3);
16188 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16189 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16190 tg3_flag_set(tp, HW_TSO_2);
16191 else if (tg3_flag(tp, 5750_PLUS)) {
16192 tg3_flag_set(tp, HW_TSO_1);
16193 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16194 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16195 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16196 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16197 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16198 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16199 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16200 tg3_flag_set(tp, FW_TSO);
16201 tg3_flag_set(tp, TSO_BUG);
4153577a 16202 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16203 tp->fw_needed = FIRMWARE_TG3TSO5;
16204 else
16205 tp->fw_needed = FIRMWARE_TG3TSO;
16206 }
16207
dabc5c67 16208 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16209 if (tg3_flag(tp, HW_TSO_1) ||
16210 tg3_flag(tp, HW_TSO_2) ||
16211 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16212 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16213 /* For firmware TSO, assume ASF is disabled.
16214 * We'll disable TSO later if we discover ASF
16215 * is enabled in tg3_get_eeprom_hw_cfg().
16216 */
dabc5c67 16217 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16218 } else {
dabc5c67
MC		 16219 tg3_flag_clear(tp, TSO_CAPABLE);
16220 tg3_flag_clear(tp, TSO_BUG);
16221 tp->fw_needed = NULL;
16222 }
16223
4153577a 16224 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16225 tp->fw_needed = FIRMWARE_TG3;
16226
c4dab506
NS		 16227 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16228 tp->fw_needed = FIRMWARE_TG357766;
16229
507399f1
MC		 16230 tp->irq_max = 1;
16231
63c3a66f
JP		 16232 if (tg3_flag(tp, 5750_PLUS)) {
16233 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16234 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16235 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16236 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16237 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16238 tp->pdev_peer == tp->pdev))
63c3a66f 16239 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16240
63c3a66f 16241 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16242 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16243 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16244 }
4f125f42 16245
63c3a66f
JP		 16246 if (tg3_flag(tp, 57765_PLUS)) {
16247 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16248 tp->irq_max = TG3_IRQ_MAX_VECS;
16249 }
f6eb9b1f 16250 }
0e1406dd 16251
9102426a
MC		 16252 tp->txq_max = 1;
16253 tp->rxq_max = 1;
16254 if (tp->irq_max > 1) {
16255 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16256 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16257
4153577a
JP		 16258 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16259 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16260 tp->txq_max = tp->irq_max - 1;
16261 }
16262
b7abee6e 16263 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16264 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16265 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16266
4153577a 16267 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16268 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16269
4153577a
JP		 16270 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16271 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16272 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16273 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16274 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16275
63c3a66f 16276 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16277 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16278 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16279
63c3a66f
JP		 16280 if (!tg3_flag(tp, 5705_PLUS) ||
16281 tg3_flag(tp, 5780_CLASS) ||
16282 tg3_flag(tp, USE_JUMBO_BDFLAG))
16283 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16284
52f4490c
MC		 16285 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16286 &pci_state_reg);
16287
708ebb3a 16288 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16289 u16 lnkctl;
16290
63c3a66f 16291 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16292
0f49bfbd 16293 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16294 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16295 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16296 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16297 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16298 }
4153577a
JP		 16299 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16300 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16301 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16302 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16303 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16304 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16305 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16306 }
4153577a 16307 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16308 /* BCM5785 devices are effectively PCIe devices, and should
16309 * follow PCIe codepaths, but do not have a PCIe capabilities
16310 * section.
93a700a9 16311 */
63c3a66f
JP		 16312 tg3_flag_set(tp, PCI_EXPRESS);
16313 } else if (!tg3_flag(tp, 5705_PLUS) ||
16314 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16315 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16316 if (!tp->pcix_cap) {
2445e461
MC		 16317 dev_err(&tp->pdev->dev,
16318 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16319 return -EIO;
16320 }
16321
16322 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16323 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16324 }
1da177e4 16325
399de50b
MC		 16326 /* If we have an AMD 762 or VIA K8T800 chipset, write
16327 * reordering to the mailbox registers done by the host
16328 * controller can cause major troubles. We read back from
16329 * every mailbox register write to force the writes to be
16330 * posted to the chip in order.
16331 */
4143470c 16332 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16333 !tg3_flag(tp, PCI_EXPRESS))
16334 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16335
69fc4053
MC		 16336 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16337 &tp->pci_cacheline_sz);
16338 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16339 &tp->pci_lat_timer);
4153577a 16340 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16341 tp->pci_lat_timer < 64) {
16342 tp->pci_lat_timer = 64;
69fc4053
MC		 16343 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16344 tp->pci_lat_timer);
1da177e4
LT		 16345 }
16346
16821285
MC		 16347 /* Important! -- It is critical that the PCI-X hw workaround
16348 * situation is decided before the first MMIO register access.
16349 */
4153577a 16350 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16351 /* 5700 BX chips need to have their TX producer index
16352 * mailboxes written twice to workaround a bug.
16353 */
63c3a66f 16354 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16355
52f4490c 16356 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16357 *
16358 * The workaround is to use indirect register accesses
16359 * for all chip writes not to mailbox registers.
16360 */
63c3a66f 16361 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16362 u32 pm_reg;
1da177e4 16363
63c3a66f 16364 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16365
16366 /* The chip can have it's power management PCI config
16367 * space registers clobbered due to this bug.
16368 * So explicitly force the chip into D0 here.
16369 */
9974a356 16370 pci_read_config_dword(tp->pdev,
0319f30e 16371 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16372 &pm_reg);
16373 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16374 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16375 pci_write_config_dword(tp->pdev,
0319f30e 16376 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16377 pm_reg);
16378
16379 /* Also, force SERR#/PERR# in PCI command. */
16380 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16381 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16382 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16383 }
16384 }
16385
1da177e4 16386 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16387 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16388 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16389 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16390
16391 /* Chip-specific fixup from Broadcom driver */
4153577a 16392 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16393 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16394 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16395 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16396 }
16397
1ee582d8 16398 /* Default fast path register access methods */
20094930 16399 tp->read32 = tg3_read32;
1ee582d8 16400 tp->write32 = tg3_write32;
09ee929c 16401 tp->read32_mbox = tg3_read32;
20094930 16402 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16403 tp->write32_tx_mbox = tg3_write32;
16404 tp->write32_rx_mbox = tg3_write32;
16405
16406 /* Various workaround register access methods */
63c3a66f 16407 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16408 tp->write32 = tg3_write_indirect_reg32;
4153577a 16409 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16410 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16411 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16412 /*
16413 * Back to back register writes can cause problems on these
16414 * chips, the workaround is to read back all reg writes
16415 * except those to mailbox regs.
16416 *
16417 * See tg3_write_indirect_reg32().
16418 */
1ee582d8 16419 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16420 }
16421
63c3a66f 16422 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16423 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16424 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16425 tp->write32_rx_mbox = tg3_write_flush_reg32;
16426 }
20094930 16427
63c3a66f 16428 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16429 tp->read32 = tg3_read_indirect_reg32;
16430 tp->write32 = tg3_write_indirect_reg32;
16431 tp->read32_mbox = tg3_read_indirect_mbox;
16432 tp->write32_mbox = tg3_write_indirect_mbox;
16433 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16434 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16435
16436 iounmap(tp->regs);
22abe310 16437 tp->regs = NULL;
6892914f
MC		 16438
16439 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16440 pci_cmd &= ~PCI_COMMAND_MEMORY;
16441 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16442 }
4153577a 16443 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16444 tp->read32_mbox = tg3_read32_mbox_5906;
16445 tp->write32_mbox = tg3_write32_mbox_5906;
16446 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16447 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16448 }
6892914f 16449
bbadf503 16450 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16451 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16452 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16453 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16454 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16455
16821285
MC		 16456 /* The memory arbiter has to be enabled in order for SRAM accesses
16457 * to succeed. Normally on powerup the tg3 chip firmware will make
16458 * sure it is enabled, but other entities such as system netboot
16459 * code might disable it.
16460 */
16461 val = tr32(MEMARB_MODE);
16462 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16463
9dc5e342 16464 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16465 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16466 tg3_flag(tp, 5780_CLASS)) {
16467 if (tg3_flag(tp, PCIX_MODE)) {
16468 pci_read_config_dword(tp->pdev,
16469 tp->pcix_cap + PCI_X_STATUS,
16470 &val);
16471 tp->pci_fn = val & 0x7;
16472 }
4153577a
JP		 16473 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16474 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16475 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16476 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16477 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16478 val = tr32(TG3_CPMU_STATUS);
16479
4153577a 16480 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16481 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16482 else
9dc5e342
MC		 16483 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16484 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16485 }
16486
7e6c63f0
HM		 16487 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16488 tp->write32_tx_mbox = tg3_write_flush_reg32;
16489 tp->write32_rx_mbox = tg3_write_flush_reg32;
16490 }
16491
7d0c41ef 16492 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16493 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16494 * determined before calling tg3_set_power_state() so that
16495 * we know whether or not to switch out of Vaux power.
16496 * When the flag is set, it means that GPIO1 is used for eeprom
16497 * write protect and also implies that it is a LOM where GPIOs
16498 * are not used to switch power.
6aa20a22 16499 */
7d0c41ef
MC		 16500 tg3_get_eeprom_hw_cfg(tp);
16501
1caf13eb 16502 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16503 tg3_flag_clear(tp, TSO_CAPABLE);
16504 tg3_flag_clear(tp, TSO_BUG);
16505 tp->fw_needed = NULL;
16506 }
16507
63c3a66f 16508 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16509 /* Allow reads and writes to the
16510 * APE register and memory space.
16511 */
16512 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16513 PCISTATE_ALLOW_APE_SHMEM_WR |
16514 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16515 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16516 pci_state_reg);
c9cab24e
MC		 16517
16518 tg3_ape_lock_init(tp);
0d3031d9
MC		 16519 }
16520
16821285
MC		 16521 /* Set up tp->grc_local_ctrl before calling
16522 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16523 * will bring 5700's external PHY out of reset.
314fba34
MC		 16524 * It is also used as eeprom write protect on LOMs.
16525 */
16526 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16527 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16528 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16529 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16530 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16531 /* Unused GPIO3 must be driven as output on 5752 because there
16532 * are no pull-up resistors on unused GPIO pins.
16533 */
4153577a 16534 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16535 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16536
4153577a
JP		 16537 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16538 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16539 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16540 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16541
8d519ab2
MC		 16542 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16543 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16544 /* Turn off the debug UART. */
16545 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16546 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16547 /* Keep VMain power. */
16548 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16549 GRC_LCLCTRL_GPIO_OUTPUT0;
16550 }
16551
4153577a 16552 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16553 tp->grc_local_ctrl |=
16554 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16555
16821285
MC		 16556 /* Switch out of Vaux if it is a NIC */
16557 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16558
1da177e4
LT		 16559 /* Derive initial jumbo mode from MTU assigned in
16560 * ether_setup() via the alloc_etherdev() call
16561 */
63c3a66f
JP		 16562 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16563 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16564
16565 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16566 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16567 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16568 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16569 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16570 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16571 } else {
63c3a66f 16572 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16573 }
16574
4153577a 16575 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16576 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16577
1da177e4 16578 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16579 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16580 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16581 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16582 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16583 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16584 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16585 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16586
4153577a
JP		 16587 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16588 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16589 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16590 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16591 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16592
63c3a66f 16593 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16594 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16595 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16596 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16597 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16598 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16599 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16600 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16601 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16602 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16603 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16604 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16605 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16606 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16607 } else
f07e9af3 16608 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16609 }
1da177e4 16610
4153577a
JP		 16611 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16612 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16613 tp->phy_otp = tg3_read_otp_phycfg(tp);
16614 if (tp->phy_otp == 0)
16615 tp->phy_otp = TG3_OTP_DEFAULT;
16616 }
16617
63c3a66f 16618 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16619 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16620 else
16621 tp->mi_mode = MAC_MI_MODE_BASE;
16622
1da177e4 16623 tp->coalesce_mode = 0;
4153577a
JP		 16624 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16625 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16626 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16627
4d958473 16628 /* Set these bits to enable statistics workaround. */
4153577a 16629 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 16630 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 16631 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16632 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16633 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16634 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16635 }
16636
4153577a
JP		 16637 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16638 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16639 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16640
158d7abd
MC		 16641 err = tg3_mdio_init(tp);
16642 if (err)
16643 return err;
1da177e4
LT		 16644
16645 /* Initialize data/descriptor byte/word swapping. */
16646 val = tr32(GRC_MODE);
4153577a
JP		 16647 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16648 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16649 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16650 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16651 GRC_MODE_B2HRX_ENABLE |
16652 GRC_MODE_HTX2B_ENABLE |
16653 GRC_MODE_HOST_STACKUP);
16654 else
16655 val &= GRC_MODE_HOST_STACKUP;
16656
1da177e4
LT		 16657 tw32(GRC_MODE, val | tp->grc_mode);
16658
16659 tg3_switch_clocks(tp);
16660
16661 /* Clear this out for sanity. */
16662 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16663
388d3335
NG		 16664 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16665 tw32(TG3PCI_REG_BASE_ADDR, 0);
16666
1da177e4
LT		 16667 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16668 &pci_state_reg);
16669 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16670 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16671 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16672 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16673 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16674 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16675 void __iomem *sram_base;
16676
16677 /* Write some dummy words into the SRAM status block
16678 * area, see if it reads back correctly. If the return
16679 * value is bad, force enable the PCIX workaround.
16680 */
16681 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16682
16683 writel(0x00000000, sram_base);
16684 writel(0x00000000, sram_base + 4);
16685 writel(0xffffffff, sram_base + 4);
16686 if (readl(sram_base) != 0x00000000)
63c3a66f 16687 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16688 }
16689 }
16690
16691 udelay(50);
16692 tg3_nvram_init(tp);
16693
c4dab506
NS		 16694 /* If the device has an NVRAM, no need to load patch firmware */
16695 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16696 !tg3_flag(tp, NO_NVRAM))
16697 tp->fw_needed = NULL;
16698
1da177e4
LT		 16699 grc_misc_cfg = tr32(GRC_MISC_CFG);
16700 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16701
4153577a 16702 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16703 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16704 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16705 tg3_flag_set(tp, IS_5788);
1da177e4 16706
63c3a66f 16707 if (!tg3_flag(tp, IS_5788) &&
4153577a 16708 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16709 tg3_flag_set(tp, TAGGED_STATUS);
16710 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16711 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16712 HOSTCC_MODE_CLRTICK_TXBD);
16713
16714 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16715 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16716 tp->misc_host_ctrl);
16717 }
16718
3bda1258 16719 /* Preserve the APE MAC_MODE bits */
63c3a66f 16720 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16721 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16722 else
6e01b20b 16723 tp->mac_mode = 0;
3bda1258 16724
3d567e0e 16725 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16726 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16727
16728 err = tg3_phy_probe(tp);
16729 if (err) {
2445e461 16730 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16731 /* ... but do not return immediately ... */
b02fd9e3 16732 tg3_mdio_fini(tp);
1da177e4
LT		 16733 }
16734
184b8904 16735 tg3_read_vpd(tp);
c4e6575c 16736 tg3_read_fw_ver(tp);
1da177e4 16737
f07e9af3
MC		 16738 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16739 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16740 } else {
4153577a 16741 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16742 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16743 else
f07e9af3 16744 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16745 }
16746
16747 /* 5700 {AX,BX} chips have a broken status block link
16748 * change bit implementation, so we must use the
16749 * status register in those cases.
16750 */
4153577a 16751 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16752 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16753 else
63c3a66f 16754 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16755
16756 /* The led_ctrl is set during tg3_phy_probe, here we might
16757 * have to force the link status polling mechanism based
16758 * upon subsystem IDs.
16759 */
16760 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16761 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16762 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16763 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16764 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16765 }
16766
16767 /* For all SERDES we poll the MAC status register. */
f07e9af3 16768 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16769 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16770 else
63c3a66f 16771 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16772
1743b83c
NS		 16773 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16774 tg3_flag_set(tp, POLL_CPMU_LINK);
16775
9205fd9c 16776 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16777 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16778 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16779 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16780 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16781#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16782 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16783#endif
16784 }
1da177e4 16785
2c49a44d
MC		 16786 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16787 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16788 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16789
2c49a44d 16790 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16791
16792 /* Increment the rx prod index on the rx std ring by at most
16793 * 8 for these chips to workaround hw errata.
16794 */
4153577a
JP		 16795 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16796 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16797 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16798 tp->rx_std_max_post = 8;
16799
63c3a66f 16800 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16801 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16802 PCIE_PWR_MGMT_L1_THRESH_MSK;
16803
1da177e4
LT		 16804 return err;
16805}
16806
49b6e95f 16807#ifdef CONFIG_SPARC
229b1ad1 16808static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16809{
16810 struct net_device *dev = tp->dev;
16811 struct pci_dev *pdev = tp->pdev;
49b6e95f 16812 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16813 const unsigned char *addr;
49b6e95f
DM		 16814 int len;
16815
16816 addr = of_get_property(dp, "local-mac-address", &len);
d458cdf7
JP		 16817 if (addr && len == ETH_ALEN) {
16818 memcpy(dev->dev_addr, addr, ETH_ALEN);
49b6e95f 16819 return 0;
1da177e4
LT		 16820 }
16821 return -ENODEV;
16822}
16823
229b1ad1 16824static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16825{
16826 struct net_device *dev = tp->dev;
16827
d458cdf7 16828 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
1da177e4
LT		 16829 return 0;
16830}
16831#endif
16832
229b1ad1 16833static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16834{
16835 struct net_device *dev = tp->dev;
16836 u32 hi, lo, mac_offset;
008652b3 16837 int addr_ok = 0;
7e6c63f0 16838 int err;
1da177e4 16839
49b6e95f 16840#ifdef CONFIG_SPARC
1da177e4
LT		 16841 if (!tg3_get_macaddr_sparc(tp))
16842 return 0;
16843#endif
16844
7e6c63f0
HM		 16845 if (tg3_flag(tp, IS_SSB_CORE)) {
16846 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16847 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16848 return 0;
16849 }
16850
1da177e4 16851 mac_offset = 0x7c;
4153577a 16852 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16853 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16854 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16855 mac_offset = 0xcc;
16856 if (tg3_nvram_lock(tp))
16857 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16858 else
16859 tg3_nvram_unlock(tp);
63c3a66f 16860 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16861 if (tp->pci_fn & 1)
a1b950d5 16862 mac_offset = 0xcc;
69f11c99 16863 if (tp->pci_fn > 1)
a50d0796 16864 mac_offset += 0x18c;
4153577a 16865 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16866 mac_offset = 0x10;
1da177e4
LT		 16867
16868 /* First try to get it from MAC address mailbox. */
16869 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16870 if ((hi >> 16) == 0x484b) {
16871 dev->dev_addr[0] = (hi >> 8) & 0xff;
16872 dev->dev_addr[1] = (hi >> 0) & 0xff;
16873
16874 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16875 dev->dev_addr[2] = (lo >> 24) & 0xff;
16876 dev->dev_addr[3] = (lo >> 16) & 0xff;
16877 dev->dev_addr[4] = (lo >> 8) & 0xff;
16878 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16879
008652b3
MC		 16880 /* Some old bootcode may report a 0 MAC address in SRAM */
16881 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16882 }
16883 if (!addr_ok) {
16884 /* Next, try NVRAM. */
63c3a66f 16885 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16886 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16887 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16888 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16889 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16890 }
16891 /* Finally just fetch it out of the MAC control regs. */
16892 else {
16893 hi = tr32(MAC_ADDR_0_HIGH);
16894 lo = tr32(MAC_ADDR_0_LOW);
16895
16896 dev->dev_addr[5] = lo & 0xff;
16897 dev->dev_addr[4] = (lo >> 8) & 0xff;
16898 dev->dev_addr[3] = (lo >> 16) & 0xff;
16899 dev->dev_addr[2] = (lo >> 24) & 0xff;
16900 dev->dev_addr[1] = hi & 0xff;
16901 dev->dev_addr[0] = (hi >> 8) & 0xff;
16902 }
1da177e4
LT		 16903 }
16904
16905 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16906#ifdef CONFIG_SPARC
1da177e4
LT		 16907 if (!tg3_get_default_macaddr_sparc(tp))
16908 return 0;
16909#endif
16910 return -EINVAL;
16911 }
16912 return 0;
16913}
16914
59e6b434
DM		 16915#define BOUNDARY_SINGLE_CACHELINE 1
16916#define BOUNDARY_MULTI_CACHELINE 2
16917
229b1ad1 16918static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16919{
16920 int cacheline_size;
16921 u8 byte;
16922 int goal;
16923
16924 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16925 if (byte == 0)
16926 cacheline_size = 1024;
16927 else
16928 cacheline_size = (int) byte * 4;
16929
16930 /* On 5703 and later chips, the boundary bits have no
16931 * effect.
16932 */
4153577a
JP		 16933 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16934 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 16935 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 16936 goto out;
16937
16938#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16939 goal = BOUNDARY_MULTI_CACHELINE;
16940#else
16941#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16942 goal = BOUNDARY_SINGLE_CACHELINE;
16943#else
16944 goal = 0;
16945#endif
16946#endif
16947
63c3a66f 16948 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 16949 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16950 goto out;
16951 }
16952
59e6b434
DM		 16953 if (!goal)
16954 goto out;
16955
16956 /* PCI controllers on most RISC systems tend to disconnect
16957 * when a device tries to burst across a cache-line boundary.
16958 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16959 *
16960 * Unfortunately, for PCI-E there are only limited
16961 * write-side controls for this, and thus for reads
16962 * we will still get the disconnects. We'll also waste
16963 * these PCI cycles for both read and write for chips
16964 * other than 5700 and 5701 which do not implement the
16965 * boundary bits.
16966 */
63c3a66f 16967 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16968 switch (cacheline_size) {
16969 case 16:
16970 case 32:
16971 case 64:
16972 case 128:
16973 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16974 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16975 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16976 } else {
16977 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16978 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16979 }
16980 break;
16981
16982 case 256:
16983 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16984 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16985 break;
16986
16987 default:
16988 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16989 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16990 break;
855e1111 16991 }
63c3a66f 16992 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16993 switch (cacheline_size) {
16994 case 16:
16995 case 32:
16996 case 64:
16997 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16998 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16999 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17000 break;
17001 }
17002 /* fallthrough */
17003 case 128:
17004 default:
17005 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17006 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17007 break;
855e1111 17008 }
59e6b434
DM		 17009 } else {
17010 switch (cacheline_size) {
17011 case 16:
17012 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17013 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17014 DMA_RWCTRL_WRITE_BNDRY_16);
17015 break;
17016 }
17017 /* fallthrough */
17018 case 32:
17019 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17020 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17021 DMA_RWCTRL_WRITE_BNDRY_32);
17022 break;
17023 }
17024 /* fallthrough */
17025 case 64:
17026 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17027 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17028 DMA_RWCTRL_WRITE_BNDRY_64);
17029 break;
17030 }
17031 /* fallthrough */
17032 case 128:
17033 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17034 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17035 DMA_RWCTRL_WRITE_BNDRY_128);
17036 break;
17037 }
17038 /* fallthrough */
17039 case 256:
17040 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17041 DMA_RWCTRL_WRITE_BNDRY_256);
17042 break;
17043 case 512:
17044 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17045 DMA_RWCTRL_WRITE_BNDRY_512);
17046 break;
17047 case 1024:
17048 default:
17049 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17050 DMA_RWCTRL_WRITE_BNDRY_1024);
17051 break;
855e1111 17052 }
59e6b434
DM		 17053 }
17054
17055out:
17056 return val;
17057}
17058
229b1ad1 17059static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 17060 int size, bool to_device)
1da177e4
LT		 17061{
17062 struct tg3_internal_buffer_desc test_desc;
17063 u32 sram_dma_descs;
17064 int i, ret;
17065
17066 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17067
17068 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17069 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17070 tw32(RDMAC_STATUS, 0);
17071 tw32(WDMAC_STATUS, 0);
17072
17073 tw32(BUFMGR_MODE, 0);
17074 tw32(FTQ_RESET, 0);
17075
17076 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17077 test_desc.addr_lo = buf_dma & 0xffffffff;
17078 test_desc.nic_mbuf = 0x00002100;
17079 test_desc.len = size;
17080
17081 /*
17082 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17083 * the *second* time the tg3 driver was getting loaded after an
17084 * initial scan.
17085 *
17086 * Broadcom tells me:
17087 * ...the DMA engine is connected to the GRC block and a DMA
17088 * reset may affect the GRC block in some unpredictable way...
17089 * The behavior of resets to individual blocks has not been tested.
17090 *
17091 * Broadcom noted the GRC reset will also reset all sub-components.
17092 */
17093 if (to_device) {
17094 test_desc.cqid_sqid = (13 << 8) | 2;
17095
17096 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17097 udelay(40);
17098 } else {
17099 test_desc.cqid_sqid = (16 << 8) | 7;
17100
17101 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17102 udelay(40);
17103 }
17104 test_desc.flags = 0x00000005;
17105
17106 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17107 u32 val;
17108
17109 val = *(((u32 *)&test_desc) + i);
17110 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17111 sram_dma_descs + (i * sizeof(u32)));
17112 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17113 }
17114 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17115
859a5887 17116 if (to_device)
1da177e4 17117 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 17118 else
1da177e4 17119 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 17120
17121 ret = -ENODEV;
17122 for (i = 0; i < 40; i++) {
17123 u32 val;
17124
17125 if (to_device)
17126 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17127 else
17128 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17129 if ((val & 0xffff) == sram_dma_descs) {
17130 ret = 0;
17131 break;
17132 }
17133
17134 udelay(100);
17135 }
17136
17137 return ret;
17138}
17139
ded7340d 17140#define TEST_BUFFER_SIZE 0x2000
1da177e4 17141
4143470c 17142static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
895950c2
JP		 17143 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17144 { },
17145};
17146
229b1ad1 17147static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 17148{
17149 dma_addr_t buf_dma;
59e6b434 17150 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 17151 int ret = 0;
1da177e4 17152
4bae65c8
MC		 17153 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17154 &buf_dma, GFP_KERNEL);
1da177e4
LT		 17155 if (!buf) {
17156 ret = -ENOMEM;
17157 goto out_nofree;
17158 }
17159
17160 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17161 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17162
59e6b434 17163 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 17164
63c3a66f 17165 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 17166 goto out;
17167
63c3a66f 17168 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 17169 /* DMA read watermark not used on PCIE */
17170 tp->dma_rwctrl |= 0x00180000;
63c3a66f 17171 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 17172 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17173 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 17174 tp->dma_rwctrl |= 0x003f0000;
17175 else
17176 tp->dma_rwctrl |= 0x003f000f;
17177 } else {
4153577a
JP		 17178 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17179 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 17180 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 17181 u32 read_water = 0x7;
1da177e4 17182
4a29cc2e
MC		 17183 /* If the 5704 is behind the EPB bridge, we can
17184 * do the less restrictive ONE_DMA workaround for
17185 * better performance.
17186 */
63c3a66f 17187 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17188 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17189 tp->dma_rwctrl |= 0x8000;
17190 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17191 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17192
4153577a 17193 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17194 read_water = 4;
59e6b434 17195 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17196 tp->dma_rwctrl |=
17197 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17198 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17199 (1 << 23);
4153577a 17200 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17201 /* 5780 always in PCIX mode */
17202 tp->dma_rwctrl |= 0x00144000;
4153577a 17203 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17204 /* 5714 always in PCIX mode */
17205 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17206 } else {
17207 tp->dma_rwctrl |= 0x001b000f;
17208 }
17209 }
7e6c63f0
HM		 17210 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17211 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17212
4153577a
JP		 17213 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17214 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17215 tp->dma_rwctrl &= 0xfffffff0;
17216
4153577a
JP		 17217 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17218 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17219 /* Remove this if it causes problems for some boards. */
17220 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17221
17222 /* On 5700/5701 chips, we need to set this bit.
17223 * Otherwise the chip will issue cacheline transactions
17224 * to streamable DMA memory with not all the byte
17225 * enables turned on. This is an error on several
17226 * RISC PCI controllers, in particular sparc64.
17227 *
17228 * On 5703/5704 chips, this bit has been reassigned
17229 * a different meaning. In particular, it is used
17230 * on those chips to enable a PCI-X workaround.
17231 */
17232 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17233 }
17234
17235 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17236
1da177e4 17237
4153577a
JP		 17238 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17239 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17240 goto out;
17241
59e6b434
DM		 17242 /* It is best to perform DMA test with maximum write burst size
17243 * to expose the 5700/5701 write DMA bug.
17244 */
17245 saved_dma_rwctrl = tp->dma_rwctrl;
17246 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17247 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17248
1da177e4
LT		 17249 while (1) {
17250 u32 *p = buf, i;
17251
17252 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17253 p[i] = i;
17254
17255 /* Send the buffer to the chip. */
953c96e0 17256 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17257 if (ret) {
2445e461
MC		 17258 dev_err(&tp->pdev->dev,
17259 "%s: Buffer write failed. err = %d\n",
17260 __func__, ret);
1da177e4
LT		 17261 break;
17262 }
17263
1da177e4 17264 /* Now read it back. */
953c96e0 17265 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17266 if (ret) {
5129c3a3
MC		 17267 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17268 "err = %d\n", __func__, ret);
1da177e4
LT		 17269 break;
17270 }
17271
17272 /* Verify it. */
17273 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17274 if (p[i] == i)
17275 continue;
17276
59e6b434
DM		 17277 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17278 DMA_RWCTRL_WRITE_BNDRY_16) {
17279 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17280 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17281 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17282 break;
17283 } else {
2445e461
MC		 17284 dev_err(&tp->pdev->dev,
17285 "%s: Buffer corrupted on read back! "
17286 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17287 ret = -ENODEV;
17288 goto out;
17289 }
17290 }
17291
17292 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17293 /* Success. */
17294 ret = 0;
17295 break;
17296 }
17297 }
59e6b434
DM		 17298 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17299 DMA_RWCTRL_WRITE_BNDRY_16) {
17300 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17301 * now look for chipsets that are known to expose the
17302 * DMA bug without failing the test.
59e6b434 17303 */
4143470c 17304 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17305 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17306 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17307 } else {
6d1cfbab
MC		 17308 /* Safe to use the calculated DMA boundary. */
17309 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17310 }
6d1cfbab 17311
59e6b434
DM		 17312 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17313 }
1da177e4
LT		 17314
17315out:
4bae65c8 17316 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17317out_nofree:
17318 return ret;
17319}
17320
229b1ad1 17321static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17322{
63c3a66f 17323 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17324 tp->bufmgr_config.mbuf_read_dma_low_water =
17325 DEFAULT_MB_RDMA_LOW_WATER_5705;
17326 tp->bufmgr_config.mbuf_mac_rx_low_water =
17327 DEFAULT_MB_MACRX_LOW_WATER_57765;
17328 tp->bufmgr_config.mbuf_high_water =
17329 DEFAULT_MB_HIGH_WATER_57765;
17330
17331 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17332 DEFAULT_MB_RDMA_LOW_WATER_5705;
17333 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17334 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17335 tp->bufmgr_config.mbuf_high_water_jumbo =
17336 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17337 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17338 tp->bufmgr_config.mbuf_read_dma_low_water =
17339 DEFAULT_MB_RDMA_LOW_WATER_5705;
17340 tp->bufmgr_config.mbuf_mac_rx_low_water =
17341 DEFAULT_MB_MACRX_LOW_WATER_5705;
17342 tp->bufmgr_config.mbuf_high_water =
17343 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17344 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17345 tp->bufmgr_config.mbuf_mac_rx_low_water =
17346 DEFAULT_MB_MACRX_LOW_WATER_5906;
17347 tp->bufmgr_config.mbuf_high_water =
17348 DEFAULT_MB_HIGH_WATER_5906;
17349 }
fdfec172
MC		 17350
17351 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17352 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17353 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17354 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17355 tp->bufmgr_config.mbuf_high_water_jumbo =
17356 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17357 } else {
17358 tp->bufmgr_config.mbuf_read_dma_low_water =
17359 DEFAULT_MB_RDMA_LOW_WATER;
17360 tp->bufmgr_config.mbuf_mac_rx_low_water =
17361 DEFAULT_MB_MACRX_LOW_WATER;
17362 tp->bufmgr_config.mbuf_high_water =
17363 DEFAULT_MB_HIGH_WATER;
17364
17365 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17366 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17367 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17368 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17369 tp->bufmgr_config.mbuf_high_water_jumbo =
17370 DEFAULT_MB_HIGH_WATER_JUMBO;
17371 }
1da177e4
LT		 17372
17373 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17374 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17375}
17376
229b1ad1 17377static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17378{
79eb6904
MC		 17379 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17380 case TG3_PHY_ID_BCM5400: return "5400";
17381 case TG3_PHY_ID_BCM5401: return "5401";
17382 case TG3_PHY_ID_BCM5411: return "5411";
17383 case TG3_PHY_ID_BCM5701: return "5701";
17384 case TG3_PHY_ID_BCM5703: return "5703";
17385 case TG3_PHY_ID_BCM5704: return "5704";
17386 case TG3_PHY_ID_BCM5705: return "5705";
17387 case TG3_PHY_ID_BCM5750: return "5750";
17388 case TG3_PHY_ID_BCM5752: return "5752";
17389 case TG3_PHY_ID_BCM5714: return "5714";
17390 case TG3_PHY_ID_BCM5780: return "5780";
17391 case TG3_PHY_ID_BCM5755: return "5755";
17392 case TG3_PHY_ID_BCM5787: return "5787";
17393 case TG3_PHY_ID_BCM5784: return "5784";
17394 case TG3_PHY_ID_BCM5756: return "5722/5756";
17395 case TG3_PHY_ID_BCM5906: return "5906";
17396 case TG3_PHY_ID_BCM5761: return "5761";
17397 case TG3_PHY_ID_BCM5718C: return "5718C";
17398 case TG3_PHY_ID_BCM5718S: return "5718S";
17399 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17400 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17401 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17402 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17403 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17404 case 0: return "serdes";
17405 default: return "unknown";
855e1111 17406 }
1da177e4
LT		 17407}
17408
229b1ad1 17409static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17410{
63c3a66f 17411 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17412 strcpy(str, "PCI Express");
17413 return str;
63c3a66f 17414 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17415 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17416
17417 strcpy(str, "PCIX:");
17418
17419 if ((clock_ctrl == 7) ||
17420 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17421 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17422 strcat(str, "133MHz");
17423 else if (clock_ctrl == 0)
17424 strcat(str, "33MHz");
17425 else if (clock_ctrl == 2)
17426 strcat(str, "50MHz");
17427 else if (clock_ctrl == 4)
17428 strcat(str, "66MHz");
17429 else if (clock_ctrl == 6)
17430 strcat(str, "100MHz");
f9804ddb
MC		 17431 } else {
17432 strcpy(str, "PCI:");
63c3a66f 17433 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17434 strcat(str, "66MHz");
17435 else
17436 strcat(str, "33MHz");
17437 }
63c3a66f 17438 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17439 strcat(str, ":32-bit");
17440 else
17441 strcat(str, ":64-bit");
17442 return str;
17443}
17444
229b1ad1 17445static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17446{
17447 struct ethtool_coalesce *ec = &tp->coal;
17448
17449 memset(ec, 0, sizeof(*ec));
17450 ec->cmd = ETHTOOL_GCOALESCE;
17451 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17452 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17453 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17454 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17455 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17456 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17457 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17458 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17459 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17460
17461 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17462 HOSTCC_MODE_CLRTICK_TXBD)) {
17463 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17464 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17465 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17466 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17467 }
d244c892 17468
63c3a66f 17469 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17470 ec->rx_coalesce_usecs_irq = 0;
17471 ec->tx_coalesce_usecs_irq = 0;
17472 ec->stats_block_coalesce_usecs = 0;
17473 }
15f9850d
DM		 17474}
17475
229b1ad1 17476static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17477 const struct pci_device_id *ent)
17478{
1da177e4
LT		 17479 struct net_device *dev;
17480 struct tg3 *tp;
5865fc1b 17481 int i, err;
646c9edd 17482 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17483 char str[40];
72f2afb8 17484 u64 dma_mask, persist_dma_mask;
c8f44aff 17485 netdev_features_t features = 0;
1da177e4 17486
05dbe005 17487 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17488
17489 err = pci_enable_device(pdev);
17490 if (err) {
2445e461 17491 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17492 return err;
17493 }
17494
1da177e4
LT		 17495 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17496 if (err) {
2445e461 17497 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17498 goto err_out_disable_pdev;
17499 }
17500
17501 pci_set_master(pdev);
17502
fe5f5787 17503 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17504 if (!dev) {
1da177e4 17505 err = -ENOMEM;
5865fc1b 17506 goto err_out_free_res;
1da177e4
LT		 17507 }
17508
1da177e4
LT		 17509 SET_NETDEV_DEV(dev, &pdev->dev);
17510
1da177e4
LT		 17511 tp = netdev_priv(dev);
17512 tp->pdev = pdev;
17513 tp->dev = dev;
1da177e4
LT		 17514 tp->rx_mode = TG3_DEF_RX_MODE;
17515 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17516 tp->irq_sync = 1;
8ef21428 17517
1da177e4
LT		 17518 if (tg3_debug > 0)
17519 tp->msg_enable = tg3_debug;
17520 else
17521 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17522
7e6c63f0
HM		 17523 if (pdev_is_ssb_gige_core(pdev)) {
17524 tg3_flag_set(tp, IS_SSB_CORE);
17525 if (ssb_gige_must_flush_posted_writes(pdev))
17526 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17527 if (ssb_gige_one_dma_at_once(pdev))
17528 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
ee002b64
HM		 17529 if (ssb_gige_have_roboswitch(pdev)) {
17530 tg3_flag_set(tp, USE_PHYLIB);
7e6c63f0 17531 tg3_flag_set(tp, ROBOSWITCH);
ee002b64 17532 }
7e6c63f0
HM		 17533 if (ssb_gige_is_rgmii(pdev))
17534 tg3_flag_set(tp, RGMII_MODE);
17535 }
17536
1da177e4
LT		 17537 /* The word/byte swap controls here control register access byte
17538 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17539 * setting below.
17540 */
17541 tp->misc_host_ctrl =
17542 MISC_HOST_CTRL_MASK_PCI_INT |
17543 MISC_HOST_CTRL_WORD_SWAP |
17544 MISC_HOST_CTRL_INDIR_ACCESS |
17545 MISC_HOST_CTRL_PCISTATE_RW;
17546
17547 /* The NONFRM (non-frame) byte/word swap controls take effect
17548 * on descriptor entries, anything which isn't packet data.
17549 *
17550 * The StrongARM chips on the board (one for tx, one for rx)
17551 * are running in big-endian mode.
17552 */
17553 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17554 GRC_MODE_WSWAP_NONFRM_DATA);
17555#ifdef __BIG_ENDIAN
17556 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17557#endif
17558 spin_lock_init(&tp->lock);
1da177e4 17559 spin_lock_init(&tp->indirect_lock);
c4028958 17560 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17561
d5fe488a 17562 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17563 if (!tp->regs) {
ab96b241 17564 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17565 err = -ENOMEM;
17566 goto err_out_free_dev;
17567 }
17568
c9cab24e
MC		 17569 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17570 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17571 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17572 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17573 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17574 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17575 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17576 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 17577 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 17578 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17579 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 17580 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17581 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 17582 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17583 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
c9cab24e
MC		 17584 tg3_flag_set(tp, ENABLE_APE);
17585 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17586 if (!tp->aperegs) {
17587 dev_err(&pdev->dev,
17588 "Cannot map APE registers, aborting\n");
17589 err = -ENOMEM;
17590 goto err_out_iounmap;
17591 }
17592 }
17593
1da177e4
LT		 17594 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17595 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17596
1da177e4 17597 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17598 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17599 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17600 dev->irq = pdev->irq;
1da177e4 17601
3d567e0e 17602 err = tg3_get_invariants(tp, ent);
1da177e4 17603 if (err) {
ab96b241
MC		 17604 dev_err(&pdev->dev,
17605 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17606 goto err_out_apeunmap;
1da177e4
LT		 17607 }
17608
4a29cc2e
MC		 17609 /* The EPB bridge inside 5714, 5715, and 5780 and any
17610 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17611 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17612 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17613 * do DMA address check in tg3_start_xmit().
17614 */
63c3a66f 17615 if (tg3_flag(tp, IS_5788))
284901a9 17616 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17617 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17618 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17619#ifdef CONFIG_HIGHMEM
6a35528a 17620 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17621#endif
4a29cc2e 17622 } else
6a35528a 17623 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17624
17625 /* Configure DMA attributes. */
284901a9 17626 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17627 err = pci_set_dma_mask(pdev, dma_mask);
17628 if (!err) {
0da0606f 17629 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17630 err = pci_set_consistent_dma_mask(pdev,
17631 persist_dma_mask);
17632 if (err < 0) {
ab96b241
MC		 17633 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17634 "DMA for consistent allocations\n");
c9cab24e 17635 goto err_out_apeunmap;
72f2afb8
MC		 17636 }
17637 }
17638 }
284901a9
YH		 17639 if (err || dma_mask == DMA_BIT_MASK(32)) {
17640 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17641 if (err) {
ab96b241
MC		 17642 dev_err(&pdev->dev,
17643 "No usable DMA configuration, aborting\n");
c9cab24e 17644 goto err_out_apeunmap;
72f2afb8
MC		 17645 }
17646 }
17647
fdfec172 17648 tg3_init_bufmgr_config(tp);
1da177e4 17649
f646968f 17650 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
0da0606f
MC		 17651
17652 /* 5700 B0 chips do not support checksumming correctly due
17653 * to hardware bugs.
17654 */
4153577a 17655 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17656 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17657
17658 if (tg3_flag(tp, 5755_PLUS))
17659 features |= NETIF_F_IPV6_CSUM;
17660 }
17661
4e3a7aaa
MC		 17662 /* TSO is on by default on chips that support hardware TSO.
17663 * Firmware TSO on older chips gives lower performance, so it
17664 * is off by default, but can be enabled using ethtool.
17665 */
63c3a66f
JP		 17666 if ((tg3_flag(tp, HW_TSO_1) ||
17667 tg3_flag(tp, HW_TSO_2) ||
17668 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17669 (features & NETIF_F_IP_CSUM))
17670 features |= NETIF_F_TSO;
63c3a66f 17671 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17672 if (features & NETIF_F_IPV6_CSUM)
17673 features |= NETIF_F_TSO6;
63c3a66f 17674 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17675 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17676 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17677 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17678 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17679 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17680 features |= NETIF_F_TSO_ECN;
b0026624 17681 }
1da177e4 17682
d542fe27
MC		 17683 dev->features |= features;
17684 dev->vlan_features |= features;
17685
06c03c02
MB		 17686 /*
17687 * Add loopback capability only for a subset of devices that support
17688 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17689 * loopback for the remaining devices.
17690 */
4153577a 17691 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17692 !tg3_flag(tp, CPMU_PRESENT))
17693 /* Add the loopback capability */
0da0606f
MC		 17694 features |= NETIF_F_LOOPBACK;
17695
0da0606f 17696 dev->hw_features |= features;
e565eec3 17697 dev->priv_flags |= IFF_UNICAST_FLT;
06c03c02 17698
4153577a 17699 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17700 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17701 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17702 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17703 tp->rx_pending = 63;
17704 }
17705
1da177e4
LT		 17706 err = tg3_get_device_address(tp);
17707 if (err) {
ab96b241
MC		 17708 dev_err(&pdev->dev,
17709 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17710 goto err_out_apeunmap;
c88864df
MC		 17711 }
17712
1da177e4
LT		 17713 /*
17714 * Reset chip in case UNDI or EFI driver did not shutdown
17715 * DMA self test will enable WDMAC and we'll see (spurious)
17716 * pending DMA on the PCI bus at that point.
17717 */
17718 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17719 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17720 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17721 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17722 }
17723
17724 err = tg3_test_dma(tp);
17725 if (err) {
ab96b241 17726 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17727 goto err_out_apeunmap;
1da177e4
LT		 17728 }
17729
78f90dcf
MC		 17730 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17731 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17732 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17733 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17734 struct tg3_napi *tnapi = &tp->napi[i];
17735
17736 tnapi->tp = tp;
17737 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17738
17739 tnapi->int_mbox = intmbx;
93a700a9 17740 if (i <= 4)
78f90dcf
MC		 17741 intmbx += 0x8;
17742 else
17743 intmbx += 0x4;
17744
17745 tnapi->consmbox = rcvmbx;
17746 tnapi->prodmbox = sndmbx;
17747
66cfd1bd 17748 if (i)
78f90dcf 17749 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17750 else
78f90dcf 17751 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17752
63c3a66f 17753 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17754 break;
17755
17756 /*
17757 * If we support MSIX, we'll be using RSS. If we're using
17758 * RSS, the first vector only handles link interrupts and the
17759 * remaining vectors handle rx and tx interrupts. Reuse the
17760 * mailbox values for the next iteration. The values we setup
17761 * above are still useful for the single vectored mode.
17762 */
17763 if (!i)
17764 continue;
17765
17766 rcvmbx += 0x8;
17767
17768 if (sndmbx & 0x4)
17769 sndmbx -= 0x4;
17770 else
17771 sndmbx += 0xc;
17772 }
17773
15f9850d
DM		 17774 tg3_init_coal(tp);
17775
c49a1561
MC		 17776 pci_set_drvdata(pdev, dev);
17777
4153577a
JP		 17778 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17779 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17780 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17781 tg3_flag_set(tp, PTP_CAPABLE);
17782
21f7638e
MC		 17783 tg3_timer_init(tp);
17784
402e1398
MC		 17785 tg3_carrier_off(tp);
17786
1da177e4
LT		 17787 err = register_netdev(dev);
17788 if (err) {
ab96b241 17789 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17790 goto err_out_apeunmap;
1da177e4
LT		 17791 }
17792
05dbe005
JP		 17793 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17794 tp->board_part_number,
4153577a 17795 tg3_chip_rev_id(tp),
05dbe005
JP		 17796 tg3_bus_string(tp, str),
17797 dev->dev_addr);
1da177e4 17798
f07e9af3 17799 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 17800 struct phy_device *phydev;
ead2402c 17801 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
5129c3a3
MC		 17802 netdev_info(dev,
17803 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17804 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17805 } else {
17806 char *ethtype;
17807
17808 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17809 ethtype = "10/100Base-TX";
17810 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17811 ethtype = "1000Base-SX";
17812 else
17813 ethtype = "10/100/1000Base-T";
17814
5129c3a3 17815 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17816 "(WireSpeed[%d], EEE[%d])\n",
17817 tg3_phy_string(tp), ethtype,
17818 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17819 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17820 }
05dbe005
JP		 17821
17822 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17823 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17824 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17825 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17826 tg3_flag(tp, ENABLE_ASF) != 0,
17827 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17828 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17829 tp->dma_rwctrl,
17830 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17831 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17832
b45aa2f6
MC		 17833 pci_save_state(pdev);
17834
1da177e4
LT		 17835 return 0;
17836
0d3031d9
MC		 17837err_out_apeunmap:
17838 if (tp->aperegs) {
17839 iounmap(tp->aperegs);
17840 tp->aperegs = NULL;
17841 }
17842
1da177e4 17843err_out_iounmap:
6892914f
MC		 17844 if (tp->regs) {
17845 iounmap(tp->regs);
22abe310 17846 tp->regs = NULL;
6892914f 17847 }
1da177e4
LT		 17848
17849err_out_free_dev:
17850 free_netdev(dev);
17851
17852err_out_free_res:
17853 pci_release_regions(pdev);
17854
17855err_out_disable_pdev:
c80dc13d
GS		 17856 if (pci_is_enabled(pdev))
17857 pci_disable_device(pdev);
1da177e4
LT		 17858 return err;
17859}
17860
229b1ad1 17861static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17862{
17863 struct net_device *dev = pci_get_drvdata(pdev);
17864
17865 if (dev) {
17866 struct tg3 *tp = netdev_priv(dev);
17867
e3c5530b 17868 release_firmware(tp->fw);
077f849d 17869
db219973 17870 tg3_reset_task_cancel(tp);
158d7abd 17871
e730c823 17872 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17873 tg3_phy_fini(tp);
158d7abd 17874 tg3_mdio_fini(tp);
b02fd9e3 17875 }
158d7abd 17876
1da177e4 17877 unregister_netdev(dev);
0d3031d9
MC		 17878 if (tp->aperegs) {
17879 iounmap(tp->aperegs);
17880 tp->aperegs = NULL;
17881 }
6892914f
MC		 17882 if (tp->regs) {
17883 iounmap(tp->regs);
22abe310 17884 tp->regs = NULL;
6892914f 17885 }
1da177e4
LT		 17886 free_netdev(dev);
17887 pci_release_regions(pdev);
17888 pci_disable_device(pdev);
1da177e4
LT		 17889 }
17890}
17891
aa6027ca 17892#ifdef CONFIG_PM_SLEEP
c866b7ea 17893static int tg3_suspend(struct device *device)
1da177e4 17894{
c866b7ea 17895 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17896 struct net_device *dev = pci_get_drvdata(pdev);
17897 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17898 int err = 0;
17899
17900 rtnl_lock();
1da177e4
LT		 17901
17902 if (!netif_running(dev))
8496e85c 17903 goto unlock;
1da177e4 17904
db219973 17905 tg3_reset_task_cancel(tp);
b02fd9e3 17906 tg3_phy_stop(tp);
1da177e4
LT		 17907 tg3_netif_stop(tp);
17908
21f7638e 17909 tg3_timer_stop(tp);
1da177e4 17910
f47c11ee 17911 tg3_full_lock(tp, 1);
1da177e4 17912 tg3_disable_ints(tp);
f47c11ee 17913 tg3_full_unlock(tp);
1da177e4
LT		 17914
17915 netif_device_detach(dev);
17916
f47c11ee 17917 tg3_full_lock(tp, 0);
944d980e 17918 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17919 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17920 tg3_full_unlock(tp);
1da177e4 17921
c866b7ea 17922 err = tg3_power_down_prepare(tp);
1da177e4 17923 if (err) {
b02fd9e3
MC		 17924 int err2;
17925
f47c11ee 17926 tg3_full_lock(tp, 0);
1da177e4 17927
63c3a66f 17928 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17929 err2 = tg3_restart_hw(tp, true);
b02fd9e3 17930 if (err2)
b9ec6c1b 17931 goto out;
1da177e4 17932
21f7638e 17933 tg3_timer_start(tp);
1da177e4
LT		 17934
17935 netif_device_attach(dev);
17936 tg3_netif_start(tp);
17937
b9ec6c1b 17938out:
f47c11ee 17939 tg3_full_unlock(tp);
b02fd9e3
MC		 17940
17941 if (!err2)
17942 tg3_phy_start(tp);
1da177e4
LT		 17943 }
17944
8496e85c
RW		 17945unlock:
17946 rtnl_unlock();
1da177e4
LT		 17947 return err;
17948}
17949
c866b7ea 17950static int tg3_resume(struct device *device)
1da177e4 17951{
c866b7ea 17952 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17953 struct net_device *dev = pci_get_drvdata(pdev);
17954 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17955 int err = 0;
17956
17957 rtnl_lock();
1da177e4
LT		 17958
17959 if (!netif_running(dev))
8496e85c 17960 goto unlock;
1da177e4 17961
1da177e4
LT		 17962 netif_device_attach(dev);
17963
f47c11ee 17964 tg3_full_lock(tp, 0);
1da177e4 17965
2e460fc0
NS		 17966 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17967
63c3a66f 17968 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 17969 err = tg3_restart_hw(tp,
17970 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 17971 if (err)
17972 goto out;
1da177e4 17973
21f7638e 17974 tg3_timer_start(tp);
1da177e4 17975
1da177e4
LT		 17976 tg3_netif_start(tp);
17977
b9ec6c1b 17978out:
f47c11ee 17979 tg3_full_unlock(tp);
1da177e4 17980
b02fd9e3
MC		 17981 if (!err)
17982 tg3_phy_start(tp);
17983
8496e85c
RW		 17984unlock:
17985 rtnl_unlock();
b9ec6c1b 17986 return err;
1da177e4 17987}
42df36a6 17988#endif /* CONFIG_PM_SLEEP */
1da177e4 17989
c866b7ea
RW		 17990static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17991
4c305fa2
NS		 17992static void tg3_shutdown(struct pci_dev *pdev)
17993{
17994 struct net_device *dev = pci_get_drvdata(pdev);
17995 struct tg3 *tp = netdev_priv(dev);
17996
17997 rtnl_lock();
17998 netif_device_detach(dev);
17999
18000 if (netif_running(dev))
18001 dev_close(dev);
18002
18003 if (system_state == SYSTEM_POWER_OFF)
18004 tg3_power_down(tp);
18005
18006 rtnl_unlock();
18007}
18008
b45aa2f6
MC		 18009/**
18010 * tg3_io_error_detected - called when PCI error is detected
18011 * @pdev: Pointer to PCI device
18012 * @state: The current pci connection state
18013 *
18014 * This function is called after a PCI bus error affecting
18015 * this device has been detected.
18016 */
18017static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18018 pci_channel_state_t state)
18019{
18020 struct net_device *netdev = pci_get_drvdata(pdev);
18021 struct tg3 *tp = netdev_priv(netdev);
18022 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18023
18024 netdev_info(netdev, "PCI I/O error detected\n");
18025
18026 rtnl_lock();
18027
d8af4dfd
GS		 18028 /* We probably don't have netdev yet */
18029 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 18030 goto done;
18031
18032 tg3_phy_stop(tp);
18033
18034 tg3_netif_stop(tp);
18035
21f7638e 18036 tg3_timer_stop(tp);
b45aa2f6
MC		 18037
18038 /* Want to make sure that the reset task doesn't run */
db219973 18039 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 18040
18041 netif_device_detach(netdev);
18042
18043 /* Clean up software state, even if MMIO is blocked */
18044 tg3_full_lock(tp, 0);
18045 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18046 tg3_full_unlock(tp);
18047
18048done:
72bb72b0 18049 if (state == pci_channel_io_perm_failure) {
68293099
DB		 18050 if (netdev) {
18051 tg3_napi_enable(tp);
18052 dev_close(netdev);
18053 }
b45aa2f6 18054 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 18055 } else {
b45aa2f6 18056 pci_disable_device(pdev);
72bb72b0 18057 }
b45aa2f6
MC		 18058
18059 rtnl_unlock();
18060
18061 return err;
18062}
18063
18064/**
18065 * tg3_io_slot_reset - called after the pci bus has been reset.
18066 * @pdev: Pointer to PCI device
18067 *
18068 * Restart the card from scratch, as if from a cold-boot.
18069 * At this point, the card has exprienced a hard reset,
18070 * followed by fixups by BIOS, and has its config space
18071 * set up identically to what it was at cold boot.
18072 */
18073static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18074{
18075 struct net_device *netdev = pci_get_drvdata(pdev);
18076 struct tg3 *tp = netdev_priv(netdev);
18077 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18078 int err;
18079
18080 rtnl_lock();
18081
18082 if (pci_enable_device(pdev)) {
68293099
DB		 18083 dev_err(&pdev->dev,
18084 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 18085 goto done;
18086 }
18087
18088 pci_set_master(pdev);
18089 pci_restore_state(pdev);
18090 pci_save_state(pdev);
18091
68293099 18092 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 18093 rc = PCI_ERS_RESULT_RECOVERED;
18094 goto done;
18095 }
18096
18097 err = tg3_power_up(tp);
bed9829f 18098 if (err)
b45aa2f6 18099 goto done;
b45aa2f6
MC		 18100
18101 rc = PCI_ERS_RESULT_RECOVERED;
18102
18103done:
68293099 18104 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 18105 tg3_napi_enable(tp);
18106 dev_close(netdev);
18107 }
b45aa2f6
MC		 18108 rtnl_unlock();
18109
18110 return rc;
18111}
18112
18113/**
18114 * tg3_io_resume - called when traffic can start flowing again.
18115 * @pdev: Pointer to PCI device
18116 *
18117 * This callback is called when the error recovery driver tells
18118 * us that its OK to resume normal operation.
18119 */
18120static void tg3_io_resume(struct pci_dev *pdev)
18121{
18122 struct net_device *netdev = pci_get_drvdata(pdev);
18123 struct tg3 *tp = netdev_priv(netdev);
18124 int err;
18125
18126 rtnl_lock();
18127
18128 if (!netif_running(netdev))
18129 goto done;
18130
18131 tg3_full_lock(tp, 0);
2e460fc0 18132 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 18133 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 18134 err = tg3_restart_hw(tp, true);
b45aa2f6 18135 if (err) {
35763066 18136 tg3_full_unlock(tp);
b45aa2f6
MC		 18137 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18138 goto done;
18139 }
18140
18141 netif_device_attach(netdev);
18142
21f7638e 18143 tg3_timer_start(tp);
b45aa2f6
MC		 18144
18145 tg3_netif_start(tp);
18146
35763066
NNS		 18147 tg3_full_unlock(tp);
18148
b45aa2f6
MC		 18149 tg3_phy_start(tp);
18150
18151done:
18152 rtnl_unlock();
18153}
18154
3646f0e5 18155static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 18156 .error_detected = tg3_io_error_detected,
18157 .slot_reset = tg3_io_slot_reset,
18158 .resume = tg3_io_resume
18159};
18160
1da177e4
LT		 18161static struct pci_driver tg3_driver = {
18162 .name = DRV_MODULE_NAME,
18163 .id_table = tg3_pci_tbl,
18164 .probe = tg3_init_one,
229b1ad1 18165 .remove = tg3_remove_one,
b45aa2f6 18166 .err_handler = &tg3_err_handler,
42df36a6 18167 .driver.pm = &tg3_pm_ops,
4c305fa2 18168 .shutdown = tg3_shutdown,
1da177e4
LT		 18169};
18170
8dbb0dc2 18171module_pci_driver(tg3_driver);
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