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tg3: Add support for new 577xx device ids
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
b681b65d 7 * Copyright (C) 2005-2013 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
1da177e4 28#include <linux/init.h>
a6b7a407 29#include <linux/interrupt.h>
1da177e4
LT		 30#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ethtool.h>
3110f5f5 36#include <linux/mdio.h>
1da177e4 37#include <linux/mii.h>
158d7abd 38#include <linux/phy.h>
a9daf367 39#include <linux/brcmphy.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
cd77b2eb 97#define TG3_MIN_NUM 133
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
cd77b2eb 100#define DRV_MODULE_RELDATE "Jul 29, 2013"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
c6cdf436 211#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 212#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 213
077f849d 214#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 215#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 216#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
217#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
218
229b1ad1 219static char version[] =
05dbe005 220 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 221
222MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
223MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 226MODULE_FIRMWARE(FIRMWARE_TG3);
227MODULE_FIRMWARE(FIRMWARE_TG3TSO);
228MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
229
1da177e4
LT		 230static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
231module_param(tg3_debug, int, 0);
232MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
233
3d567e0e
NNS		 234#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
235#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
236
a3aa1884 237static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
257 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
258 TG3_DRV_DATA_FLAG_5705_10_100},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
264 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
272 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
278 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 286 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
287 PCI_VENDOR_ID_LENOVO,
288 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
289 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
313 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
330 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
332 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
68273712
NS		 340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
13185217
HK		 345 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
346 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
347 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
348 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
349 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
351 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 352 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 353 {}
1da177e4
LT		 354};
355
356MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
357
50da859d 358static const struct {
1da177e4 359 const char string[ETH_GSTRING_LEN];
48fa55a0 360} ethtool_stats_keys[] = {
1da177e4
LT		 361 { "rx_octets" },
362 { "rx_fragments" },
363 { "rx_ucast_packets" },
364 { "rx_mcast_packets" },
365 { "rx_bcast_packets" },
366 { "rx_fcs_errors" },
367 { "rx_align_errors" },
368 { "rx_xon_pause_rcvd" },
369 { "rx_xoff_pause_rcvd" },
370 { "rx_mac_ctrl_rcvd" },
371 { "rx_xoff_entered" },
372 { "rx_frame_too_long_errors" },
373 { "rx_jabbers" },
374 { "rx_undersize_packets" },
375 { "rx_in_length_errors" },
376 { "rx_out_length_errors" },
377 { "rx_64_or_less_octet_packets" },
378 { "rx_65_to_127_octet_packets" },
379 { "rx_128_to_255_octet_packets" },
380 { "rx_256_to_511_octet_packets" },
381 { "rx_512_to_1023_octet_packets" },
382 { "rx_1024_to_1522_octet_packets" },
383 { "rx_1523_to_2047_octet_packets" },
384 { "rx_2048_to_4095_octet_packets" },
385 { "rx_4096_to_8191_octet_packets" },
386 { "rx_8192_to_9022_octet_packets" },
387
388 { "tx_octets" },
389 { "tx_collisions" },
390
391 { "tx_xon_sent" },
392 { "tx_xoff_sent" },
393 { "tx_flow_control" },
394 { "tx_mac_errors" },
395 { "tx_single_collisions" },
396 { "tx_mult_collisions" },
397 { "tx_deferred" },
398 { "tx_excessive_collisions" },
399 { "tx_late_collisions" },
400 { "tx_collide_2times" },
401 { "tx_collide_3times" },
402 { "tx_collide_4times" },
403 { "tx_collide_5times" },
404 { "tx_collide_6times" },
405 { "tx_collide_7times" },
406 { "tx_collide_8times" },
407 { "tx_collide_9times" },
408 { "tx_collide_10times" },
409 { "tx_collide_11times" },
410 { "tx_collide_12times" },
411 { "tx_collide_13times" },
412 { "tx_collide_14times" },
413 { "tx_collide_15times" },
414 { "tx_ucast_packets" },
415 { "tx_mcast_packets" },
416 { "tx_bcast_packets" },
417 { "tx_carrier_sense_errors" },
418 { "tx_discards" },
419 { "tx_errors" },
420
421 { "dma_writeq_full" },
422 { "dma_write_prioq_full" },
423 { "rxbds_empty" },
424 { "rx_discards" },
425 { "rx_errors" },
426 { "rx_threshold_hit" },
427
428 { "dma_readq_full" },
429 { "dma_read_prioq_full" },
430 { "tx_comp_queue_full" },
431
432 { "ring_set_send_prod_index" },
433 { "ring_status_update" },
434 { "nic_irqs" },
435 { "nic_avoided_irqs" },
4452d099
MC		 436 { "nic_tx_threshold_hit" },
437
438 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 439};
440
48fa55a0 441#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 442#define TG3_NVRAM_TEST 0
443#define TG3_LINK_TEST 1
444#define TG3_REGISTER_TEST 2
445#define TG3_MEMORY_TEST 3
446#define TG3_MAC_LOOPB_TEST 4
447#define TG3_PHY_LOOPB_TEST 5
448#define TG3_EXT_LOOPB_TEST 6
449#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 450
451
50da859d 452static const struct {
4cafd3f5 453 const char string[ETH_GSTRING_LEN];
48fa55a0 454} ethtool_test_keys[] = {
93df8b8f
NNS		 455 [TG3_NVRAM_TEST] = { "nvram test (online) " },
456 [TG3_LINK_TEST] = { "link test (online) " },
457 [TG3_REGISTER_TEST] = { "register test (offline)" },
458 [TG3_MEMORY_TEST] = { "memory test (offline)" },
459 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
460 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
461 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
462 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 463};
464
48fa55a0
MC		 465#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
466
467
b401e9e2
MC		 468static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
469{
470 writel(val, tp->regs + off);
471}
472
473static u32 tg3_read32(struct tg3 *tp, u32 off)
474{
de6f31eb 475 return readl(tp->regs + off);
b401e9e2
MC		 476}
477
0d3031d9
MC		 478static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
479{
480 writel(val, tp->aperegs + off);
481}
482
483static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
484{
de6f31eb 485 return readl(tp->aperegs + off);
0d3031d9
MC		 486}
487
1da177e4
LT		 488static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
489{
6892914f
MC		 490 unsigned long flags;
491
492 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 493 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
494 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 495 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 496}
497
498static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
499{
500 writel(val, tp->regs + off);
501 readl(tp->regs + off);
1da177e4
LT		 502}
503
6892914f 504static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 505{
6892914f
MC		 506 unsigned long flags;
507 u32 val;
508
509 spin_lock_irqsave(&tp->indirect_lock, flags);
510 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
511 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
512 spin_unlock_irqrestore(&tp->indirect_lock, flags);
513 return val;
514}
515
516static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
517{
518 unsigned long flags;
519
520 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
521 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
522 TG3_64BIT_REG_LOW, val);
523 return;
524 }
66711e66 525 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 526 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
527 TG3_64BIT_REG_LOW, val);
528 return;
1da177e4 529 }
6892914f
MC		 530
531 spin_lock_irqsave(&tp->indirect_lock, flags);
532 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
533 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
535
536 /* In indirect mode when disabling interrupts, we also need
537 * to clear the interrupt bit in the GRC local ctrl register.
538 */
539 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
540 (val == 0x1)) {
541 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
542 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
543 }
544}
545
546static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
547{
548 unsigned long flags;
549 u32 val;
550
551 spin_lock_irqsave(&tp->indirect_lock, flags);
552 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
553 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
555 return val;
556}
557
b401e9e2
MC		 558/* usec_wait specifies the wait time in usec when writing to certain registers
559 * where it is unsafe to read back the register without some delay.
560 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
561 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
562 */
563static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 564{
63c3a66f 565 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 566 /* Non-posted methods */
567 tp->write32(tp, off, val);
568 else {
569 /* Posted method */
570 tg3_write32(tp, off, val);
571 if (usec_wait)
572 udelay(usec_wait);
573 tp->read32(tp, off);
574 }
575 /* Wait again after the read for the posted method to guarantee that
576 * the wait time is met.
577 */
578 if (usec_wait)
579 udelay(usec_wait);
1da177e4
LT		 580}
581
09ee929c
MC		 582static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
583{
584 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 585 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
586 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
587 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 588 tp->read32_mbox(tp, off);
09ee929c
MC		 589}
590
20094930 591static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 592{
593 void __iomem *mbox = tp->regs + off;
594 writel(val, mbox);
63c3a66f 595 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 596 writel(val, mbox);
7e6c63f0
HM		 597 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
598 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 599 readl(mbox);
600}
601
b5d3772c
MC		 602static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
603{
de6f31eb 604 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 605}
606
607static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
608{
609 writel(val, tp->regs + off + GRCMBOX_BASE);
610}
611
c6cdf436 612#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 613#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 614#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
615#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
616#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 617
c6cdf436
MC		 618#define tw32(reg, val) tp->write32(tp, reg, val)
619#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
620#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
621#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 622
623static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
624{
6892914f
MC		 625 unsigned long flags;
626
4153577a 627 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 628 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
629 return;
630
6892914f 631 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 632 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 633 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
634 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 635
bbadf503
MC		 636 /* Always leave this as zero. */
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
638 } else {
639 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
640 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 641
bbadf503
MC		 642 /* Always leave this as zero. */
643 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
644 }
645 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 646}
647
1da177e4
LT		 648static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
649{
6892914f
MC		 650 unsigned long flags;
651
4153577a 652 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 653 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
654 *val = 0;
655 return;
656 }
657
6892914f 658 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 659 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 660 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
661 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 662
bbadf503
MC		 663 /* Always leave this as zero. */
664 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
665 } else {
666 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
667 *val = tr32(TG3PCI_MEM_WIN_DATA);
668
669 /* Always leave this as zero. */
670 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
671 }
6892914f 672 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 673}
674
0d3031d9
MC		 675static void tg3_ape_lock_init(struct tg3 *tp)
676{
677 int i;
6f5c8f83 678 u32 regbase, bit;
f92d9dc1 679
4153577a 680 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 681 regbase = TG3_APE_LOCK_GRANT;
682 else
683 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 684
685 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 686 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
687 switch (i) {
688 case TG3_APE_LOCK_PHY0:
689 case TG3_APE_LOCK_PHY1:
690 case TG3_APE_LOCK_PHY2:
691 case TG3_APE_LOCK_PHY3:
692 bit = APE_LOCK_GRANT_DRIVER;
693 break;
694 default:
695 if (!tp->pci_fn)
696 bit = APE_LOCK_GRANT_DRIVER;
697 else
698 bit = 1 << tp->pci_fn;
699 }
700 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 701 }
702
0d3031d9
MC		 703}
704
705static int tg3_ape_lock(struct tg3 *tp, int locknum)
706{
707 int i, off;
708 int ret = 0;
6f5c8f83 709 u32 status, req, gnt, bit;
0d3031d9 710
63c3a66f 711 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 712 return 0;
713
714 switch (locknum) {
6f5c8f83 715 case TG3_APE_LOCK_GPIO:
4153577a 716 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 717 return 0;
33f401ae
MC		 718 case TG3_APE_LOCK_GRC:
719 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 720 if (!tp->pci_fn)
721 bit = APE_LOCK_REQ_DRIVER;
722 else
723 bit = 1 << tp->pci_fn;
33f401ae 724 break;
8151ad57
MC		 725 case TG3_APE_LOCK_PHY0:
726 case TG3_APE_LOCK_PHY1:
727 case TG3_APE_LOCK_PHY2:
728 case TG3_APE_LOCK_PHY3:
729 bit = APE_LOCK_REQ_DRIVER;
730 break;
33f401ae
MC		 731 default:
732 return -EINVAL;
0d3031d9
MC		 733 }
734
4153577a 735 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 736 req = TG3_APE_LOCK_REQ;
737 gnt = TG3_APE_LOCK_GRANT;
738 } else {
739 req = TG3_APE_PER_LOCK_REQ;
740 gnt = TG3_APE_PER_LOCK_GRANT;
741 }
742
0d3031d9
MC		 743 off = 4 * locknum;
744
6f5c8f83 745 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 746
747 /* Wait for up to 1 millisecond to acquire lock. */
748 for (i = 0; i < 100; i++) {
f92d9dc1 749 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 750 if (status == bit)
0d3031d9 751 break;
6d446ec3
GS		 752 if (pci_channel_offline(tp->pdev))
753 break;
754
0d3031d9
MC		 755 udelay(10);
756 }
757
6f5c8f83 758 if (status != bit) {
0d3031d9 759 /* Revoke the lock request. */
6f5c8f83 760 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 761 ret = -EBUSY;
762 }
763
764 return ret;
765}
766
767static void tg3_ape_unlock(struct tg3 *tp, int locknum)
768{
6f5c8f83 769 u32 gnt, bit;
0d3031d9 770
63c3a66f 771 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 772 return;
773
774 switch (locknum) {
6f5c8f83 775 case TG3_APE_LOCK_GPIO:
4153577a 776 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 777 return;
33f401ae
MC		 778 case TG3_APE_LOCK_GRC:
779 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 780 if (!tp->pci_fn)
781 bit = APE_LOCK_GRANT_DRIVER;
782 else
783 bit = 1 << tp->pci_fn;
33f401ae 784 break;
8151ad57
MC		 785 case TG3_APE_LOCK_PHY0:
786 case TG3_APE_LOCK_PHY1:
787 case TG3_APE_LOCK_PHY2:
788 case TG3_APE_LOCK_PHY3:
789 bit = APE_LOCK_GRANT_DRIVER;
790 break;
33f401ae
MC		 791 default:
792 return;
0d3031d9
MC		 793 }
794
4153577a 795 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 796 gnt = TG3_APE_LOCK_GRANT;
797 else
798 gnt = TG3_APE_PER_LOCK_GRANT;
799
6f5c8f83 800 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 801}
802
b65a372b 803static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 804{
fd6d3f0e
MC		 805 u32 apedata;
806
b65a372b
MC		 807 while (timeout_us) {
808 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
809 return -EBUSY;
810
811 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
812 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
813 break;
814
815 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
816
817 udelay(10);
818 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
819 }
820
821 return timeout_us ? 0 : -EBUSY;
822}
823
cf8d55ae
MC		 824static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
825{
826 u32 i, apedata;
827
828 for (i = 0; i < timeout_us / 10; i++) {
829 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
830
831 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
832 break;
833
834 udelay(10);
835 }
836
837 return i == timeout_us / 10;
838}
839
86449944
MC		 840static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
841 u32 len)
cf8d55ae
MC		 842{
843 int err;
844 u32 i, bufoff, msgoff, maxlen, apedata;
845
846 if (!tg3_flag(tp, APE_HAS_NCSI))
847 return 0;
848
849 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
850 if (apedata != APE_SEG_SIG_MAGIC)
851 return -ENODEV;
852
853 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
854 if (!(apedata & APE_FW_STATUS_READY))
855 return -EAGAIN;
856
857 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
858 TG3_APE_SHMEM_BASE;
859 msgoff = bufoff + 2 * sizeof(u32);
860 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
861
862 while (len) {
863 u32 length;
864
865 /* Cap xfer sizes to scratchpad limits. */
866 length = (len > maxlen) ? maxlen : len;
867 len -= length;
868
869 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
870 if (!(apedata & APE_FW_STATUS_READY))
871 return -EAGAIN;
872
873 /* Wait for up to 1 msec for APE to service previous event. */
874 err = tg3_ape_event_lock(tp, 1000);
875 if (err)
876 return err;
877
878 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
879 APE_EVENT_STATUS_SCRTCHPD_READ |
880 APE_EVENT_STATUS_EVENT_PENDING;
881 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
882
883 tg3_ape_write32(tp, bufoff, base_off);
884 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
885
886 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
887 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
888
889 base_off += length;
890
891 if (tg3_ape_wait_for_event(tp, 30000))
892 return -EAGAIN;
893
894 for (i = 0; length; i += 4, length -= 4) {
895 u32 val = tg3_ape_read32(tp, msgoff + i);
896 memcpy(data, &val, sizeof(u32));
897 data++;
898 }
899 }
900
901 return 0;
902}
903
b65a372b
MC		 904static int tg3_ape_send_event(struct tg3 *tp, u32 event)
905{
906 int err;
907 u32 apedata;
fd6d3f0e
MC		 908
909 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
910 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 911 return -EAGAIN;
fd6d3f0e
MC		 912
913 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
914 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 915 return -EAGAIN;
fd6d3f0e
MC		 916
917 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 918 err = tg3_ape_event_lock(tp, 1000);
919 if (err)
920 return err;
fd6d3f0e 921
b65a372b
MC		 922 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
923 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 924
b65a372b
MC		 925 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
926 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 927
b65a372b 928 return 0;
fd6d3f0e
MC		 929}
930
931static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
932{
933 u32 event;
934 u32 apedata;
935
936 if (!tg3_flag(tp, ENABLE_APE))
937 return;
938
939 switch (kind) {
940 case RESET_KIND_INIT:
941 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
942 APE_HOST_SEG_SIG_MAGIC);
943 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
944 APE_HOST_SEG_LEN_MAGIC);
945 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
946 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
947 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
948 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
949 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
950 APE_HOST_BEHAV_NO_PHYLOCK);
951 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
952 TG3_APE_HOST_DRVR_STATE_START);
953
954 event = APE_EVENT_STATUS_STATE_START;
955 break;
956 case RESET_KIND_SHUTDOWN:
957 /* With the interface we are currently using,
958 * APE does not track driver state. Wiping
959 * out the HOST SEGMENT SIGNATURE forces
960 * the APE to assume OS absent status.
961 */
962 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
963
964 if (device_may_wakeup(&tp->pdev->dev) &&
965 tg3_flag(tp, WOL_ENABLE)) {
966 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
967 TG3_APE_HOST_WOL_SPEED_AUTO);
968 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
969 } else
970 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
971
972 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
973
974 event = APE_EVENT_STATUS_STATE_UNLOAD;
975 break;
fd6d3f0e
MC		 976 default:
977 return;
978 }
979
980 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
981
982 tg3_ape_send_event(tp, event);
983}
984
1da177e4
LT		 985static void tg3_disable_ints(struct tg3 *tp)
986{
89aeb3bc
MC		 987 int i;
988
1da177e4
LT		 989 tw32(TG3PCI_MISC_HOST_CTRL,
990 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 991 for (i = 0; i < tp->irq_max; i++)
992 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 993}
994
1da177e4
LT		 995static void tg3_enable_ints(struct tg3 *tp)
996{
89aeb3bc 997 int i;
89aeb3bc 998
bbe832c0
MC		 999 tp->irq_sync = 0;
1000 wmb();
1001
1da177e4
LT		 1002 tw32(TG3PCI_MISC_HOST_CTRL,
1003 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 1004
f89f38b8 1005 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1006 for (i = 0; i < tp->irq_cnt; i++) {
1007 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1008
898a56f8 1009 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1010 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1011 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1012
f89f38b8 1013 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1014 }
f19af9c2
MC		 1015
1016 /* Force an initial interrupt */
63c3a66f 1017 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1018 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1019 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1020 else
f89f38b8
MC		 1021 tw32(HOSTCC_MODE, tp->coal_now);
1022
1023 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1024}
1025
17375d25 1026static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1027{
17375d25 1028 struct tg3 *tp = tnapi->tp;
898a56f8 1029 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1030 unsigned int work_exists = 0;
1031
1032 /* check for phy events */
63c3a66f 1033 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1034 if (sblk->status & SD_STATUS_LINK_CHG)
1035 work_exists = 1;
1036 }
f891ea16
MC		 1037
1038 /* check for TX work to do */
1039 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1040 work_exists = 1;
1041
1042 /* check for RX work to do */
1043 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1044 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1045 work_exists = 1;
1046
1047 return work_exists;
1048}
1049
17375d25 1050/* tg3_int_reenable
04237ddd
MC		 1051 * similar to tg3_enable_ints, but it accurately determines whether there
1052 * is new work pending and can return without flushing the PIO write
6aa20a22 1053 * which reenables interrupts
1da177e4 1054 */
17375d25 1055static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1056{
17375d25
MC		 1057 struct tg3 *tp = tnapi->tp;
1058
898a56f8 1059 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1060 mmiowb();
1061
fac9b83e
DM		 1062 /* When doing tagged status, this work check is unnecessary.
1063 * The last_tag we write above tells the chip which piece of
1064 * work we've completed.
1065 */
63c3a66f 1066 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1067 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1068 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1069}
1070
1da177e4
LT		 1071static void tg3_switch_clocks(struct tg3 *tp)
1072{
f6eb9b1f 1073 u32 clock_ctrl;
1da177e4
LT		 1074 u32 orig_clock_ctrl;
1075
63c3a66f 1076 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1077 return;
1078
f6eb9b1f
MC		 1079 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1080
1da177e4
LT		 1081 orig_clock_ctrl = clock_ctrl;
1082 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1083 CLOCK_CTRL_CLKRUN_OENABLE |
1084 0x1f);
1085 tp->pci_clock_ctrl = clock_ctrl;
1086
63c3a66f 1087 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1088 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1089 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1090 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1091 }
1092 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1093 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1094 clock_ctrl |
1095 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1096 40);
1097 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1099 40);
1da177e4 1100 }
b401e9e2 1101 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1102}
1103
1104#define PHY_BUSY_LOOPS 5000
1105
5c358045
HM		 1106static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1107 u32 *val)
1da177e4
LT		 1108{
1109 u32 frame_val;
1110 unsigned int loops;
1111 int ret;
1112
1113 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1114 tw32_f(MAC_MI_MODE,
1115 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1116 udelay(80);
1117 }
1118
8151ad57
MC		 1119 tg3_ape_lock(tp, tp->phy_ape_lock);
1120
1da177e4
LT		 1121 *val = 0x0;
1122
5c358045 1123 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1124 MI_COM_PHY_ADDR_MASK);
1125 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1126 MI_COM_REG_ADDR_MASK);
1127 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1128
1da177e4
LT		 1129 tw32_f(MAC_MI_COM, frame_val);
1130
1131 loops = PHY_BUSY_LOOPS;
1132 while (loops != 0) {
1133 udelay(10);
1134 frame_val = tr32(MAC_MI_COM);
1135
1136 if ((frame_val & MI_COM_BUSY) == 0) {
1137 udelay(5);
1138 frame_val = tr32(MAC_MI_COM);
1139 break;
1140 }
1141 loops -= 1;
1142 }
1143
1144 ret = -EBUSY;
1145 if (loops != 0) {
1146 *val = frame_val & MI_COM_DATA_MASK;
1147 ret = 0;
1148 }
1149
1150 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1151 tw32_f(MAC_MI_MODE, tp->mi_mode);
1152 udelay(80);
1153 }
1154
8151ad57
MC		 1155 tg3_ape_unlock(tp, tp->phy_ape_lock);
1156
1da177e4
LT		 1157 return ret;
1158}
1159
5c358045
HM		 1160static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1161{
1162 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1163}
1164
1165static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1166 u32 val)
1da177e4
LT		 1167{
1168 u32 frame_val;
1169 unsigned int loops;
1170 int ret;
1171
f07e9af3 1172 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1173 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1174 return 0;
1175
1da177e4
LT		 1176 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1177 tw32_f(MAC_MI_MODE,
1178 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1179 udelay(80);
1180 }
1181
8151ad57
MC		 1182 tg3_ape_lock(tp, tp->phy_ape_lock);
1183
5c358045 1184 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1185 MI_COM_PHY_ADDR_MASK);
1186 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1187 MI_COM_REG_ADDR_MASK);
1188 frame_val |= (val & MI_COM_DATA_MASK);
1189 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1190
1da177e4
LT		 1191 tw32_f(MAC_MI_COM, frame_val);
1192
1193 loops = PHY_BUSY_LOOPS;
1194 while (loops != 0) {
1195 udelay(10);
1196 frame_val = tr32(MAC_MI_COM);
1197 if ((frame_val & MI_COM_BUSY) == 0) {
1198 udelay(5);
1199 frame_val = tr32(MAC_MI_COM);
1200 break;
1201 }
1202 loops -= 1;
1203 }
1204
1205 ret = -EBUSY;
1206 if (loops != 0)
1207 ret = 0;
1208
1209 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1210 tw32_f(MAC_MI_MODE, tp->mi_mode);
1211 udelay(80);
1212 }
1213
8151ad57
MC		 1214 tg3_ape_unlock(tp, tp->phy_ape_lock);
1215
1da177e4
LT		 1216 return ret;
1217}
1218
5c358045
HM		 1219static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1220{
1221 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1222}
1223
b0988c15
MC		 1224static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1225{
1226 int err;
1227
1228 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1229 if (err)
1230 goto done;
1231
1232 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1233 if (err)
1234 goto done;
1235
1236 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1237 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1238 if (err)
1239 goto done;
1240
1241 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1242
1243done:
1244 return err;
1245}
1246
1247static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1248{
1249 int err;
1250
1251 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1252 if (err)
1253 goto done;
1254
1255 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1256 if (err)
1257 goto done;
1258
1259 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1260 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1261 if (err)
1262 goto done;
1263
1264 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1265
1266done:
1267 return err;
1268}
1269
1270static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1271{
1272 int err;
1273
1274 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1275 if (!err)
1276 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1277
1278 return err;
1279}
1280
1281static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1282{
1283 int err;
1284
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1286 if (!err)
1287 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1288
1289 return err;
1290}
1291
15ee95c3
MC		 1292static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1293{
1294 int err;
1295
1296 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1297 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1298 MII_TG3_AUXCTL_SHDWSEL_MISC);
1299 if (!err)
1300 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1301
1302 return err;
1303}
1304
b4bd2929
MC		 1305static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1306{
1307 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1308 set |= MII_TG3_AUXCTL_MISC_WREN;
1309
1310 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1311}
1312
daf3ec68
NNS		 1313static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1314{
1315 u32 val;
1316 int err;
1d36ba45 1317
daf3ec68 1318 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1319
daf3ec68
NNS		 1320 if (err)
1321 return err;
daf3ec68 1322
7c10ee32 1323 if (enable)
daf3ec68
NNS		 1324 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1325 else
1326 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1327
1328 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1329 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1330
1331 return err;
1332}
1d36ba45 1333
3ab71071
NS		 1334static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1335{
1336 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1337 reg | val | MII_TG3_MISC_SHDW_WREN);
1338}
1339
95e2869a
MC		 1340static int tg3_bmcr_reset(struct tg3 *tp)
1341{
1342 u32 phy_control;
1343 int limit, err;
1344
1345 /* OK, reset it, and poll the BMCR_RESET bit until it
1346 * clears or we time out.
1347 */
1348 phy_control = BMCR_RESET;
1349 err = tg3_writephy(tp, MII_BMCR, phy_control);
1350 if (err != 0)
1351 return -EBUSY;
1352
1353 limit = 5000;
1354 while (limit--) {
1355 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1356 if (err != 0)
1357 return -EBUSY;
1358
1359 if ((phy_control & BMCR_RESET) == 0) {
1360 udelay(40);
1361 break;
1362 }
1363 udelay(10);
1364 }
d4675b52 1365 if (limit < 0)
95e2869a
MC		 1366 return -EBUSY;
1367
1368 return 0;
1369}
1370
158d7abd
MC		 1371static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1372{
3d16543d 1373 struct tg3 *tp = bp->priv;
158d7abd
MC		 1374 u32 val;
1375
24bb4fb6 1376 spin_lock_bh(&tp->lock);
158d7abd
MC		 1377
1378 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 1379 val = -EIO;
1380
1381 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1382
1383 return val;
1384}
1385
1386static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1387{
3d16543d 1388 struct tg3 *tp = bp->priv;
24bb4fb6 1389 u32 ret = 0;
158d7abd 1390
24bb4fb6 1391 spin_lock_bh(&tp->lock);
158d7abd
MC		 1392
1393 if (tg3_writephy(tp, reg, val))
24bb4fb6 1394 ret = -EIO;
158d7abd 1395
24bb4fb6
MC		 1396 spin_unlock_bh(&tp->lock);
1397
1398 return ret;
158d7abd
MC		 1399}
1400
1401static int tg3_mdio_reset(struct mii_bus *bp)
1402{
1403 return 0;
1404}
1405
9c61d6bc 1406static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1407{
1408 u32 val;
fcb389df 1409 struct phy_device *phydev;
a9daf367 1410
3f0e3ad7 1411 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 1412 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1413 case PHY_ID_BCM50610:
1414 case PHY_ID_BCM50610M:
fcb389df
MC		 1415 val = MAC_PHYCFG2_50610_LED_MODES;
1416 break;
6a443a0f 1417 case PHY_ID_BCMAC131:
fcb389df
MC		 1418 val = MAC_PHYCFG2_AC131_LED_MODES;
1419 break;
6a443a0f 1420 case PHY_ID_RTL8211C:
fcb389df
MC		 1421 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1422 break;
6a443a0f 1423 case PHY_ID_RTL8201E:
fcb389df
MC		 1424 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1425 break;
1426 default:
a9daf367 1427 return;
fcb389df
MC		 1428 }
1429
1430 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1431 tw32(MAC_PHYCFG2, val);
1432
1433 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1434 val &= ~(MAC_PHYCFG1_RGMII_INT |
1435 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1436 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1437 tw32(MAC_PHYCFG1, val);
1438
1439 return;
1440 }
1441
63c3a66f 1442 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1443 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1444 MAC_PHYCFG2_FMODE_MASK_MASK |
1445 MAC_PHYCFG2_GMODE_MASK_MASK |
1446 MAC_PHYCFG2_ACT_MASK_MASK |
1447 MAC_PHYCFG2_QUAL_MASK_MASK |
1448 MAC_PHYCFG2_INBAND_ENABLE;
1449
1450 tw32(MAC_PHYCFG2, val);
a9daf367 1451
bb85fbb6
MC		 1452 val = tr32(MAC_PHYCFG1);
1453 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1454 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1455 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1456 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1457 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1458 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1459 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1460 }
bb85fbb6
MC		 1461 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1462 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1463 tw32(MAC_PHYCFG1, val);
a9daf367 1464
a9daf367
MC		 1465 val = tr32(MAC_EXT_RGMII_MODE);
1466 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1467 MAC_RGMII_MODE_RX_QUALITY |
1468 MAC_RGMII_MODE_RX_ACTIVITY |
1469 MAC_RGMII_MODE_RX_ENG_DET |
1470 MAC_RGMII_MODE_TX_ENABLE |
1471 MAC_RGMII_MODE_TX_LOWPWR |
1472 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1473 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1474 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1475 val |= MAC_RGMII_MODE_RX_INT_B |
1476 MAC_RGMII_MODE_RX_QUALITY |
1477 MAC_RGMII_MODE_RX_ACTIVITY |
1478 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1479 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1480 val |= MAC_RGMII_MODE_TX_ENABLE |
1481 MAC_RGMII_MODE_TX_LOWPWR |
1482 MAC_RGMII_MODE_TX_RESET;
1483 }
1484 tw32(MAC_EXT_RGMII_MODE, val);
1485}
1486
158d7abd
MC		 1487static void tg3_mdio_start(struct tg3 *tp)
1488{
158d7abd
MC		 1489 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1490 tw32_f(MAC_MI_MODE, tp->mi_mode);
1491 udelay(80);
a9daf367 1492
63c3a66f 1493 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1494 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1495 tg3_mdio_config_5785(tp);
1496}
1497
1498static int tg3_mdio_init(struct tg3 *tp)
1499{
1500 int i;
1501 u32 reg;
1502 struct phy_device *phydev;
1503
63c3a66f 1504 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1505 u32 is_serdes;
882e9793 1506
69f11c99 1507 tp->phy_addr = tp->pci_fn + 1;
882e9793 1508
4153577a 1509 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1510 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1511 else
1512 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1513 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1514 if (is_serdes)
1515 tp->phy_addr += 7;
1516 } else
3f0e3ad7 1517 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1518
158d7abd
MC		 1519 tg3_mdio_start(tp);
1520
63c3a66f 1521 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1522 return 0;
1523
298cf9be
LB		 1524 tp->mdio_bus = mdiobus_alloc();
1525 if (tp->mdio_bus == NULL)
1526 return -ENOMEM;
158d7abd 1527
298cf9be
LB		 1528 tp->mdio_bus->name = "tg3 mdio bus";
1529 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1530 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1531 tp->mdio_bus->priv = tp;
1532 tp->mdio_bus->parent = &tp->pdev->dev;
1533 tp->mdio_bus->read = &tg3_mdio_read;
1534 tp->mdio_bus->write = &tg3_mdio_write;
1535 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1536 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1537 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1538
1539 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1540 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1541
1542 /* The bus registration will look for all the PHYs on the mdio bus.
1543 * Unfortunately, it does not ensure the PHY is powered up before
1544 * accessing the PHY ID registers. A chip reset is the
1545 * quickest way to bring the device back to an operational state..
1546 */
1547 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1548 tg3_bmcr_reset(tp);
1549
298cf9be 1550 i = mdiobus_register(tp->mdio_bus);
a9daf367 1551 if (i) {
ab96b241 1552 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1553 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1554 return i;
1555 }
158d7abd 1556
3f0e3ad7 1557 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1558
9c61d6bc 1559 if (!phydev || !phydev->drv) {
ab96b241 1560 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1561 mdiobus_unregister(tp->mdio_bus);
1562 mdiobus_free(tp->mdio_bus);
1563 return -ENODEV;
1564 }
1565
1566 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1567 case PHY_ID_BCM57780:
321d32a0 1568 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1569 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1570 break;
6a443a0f
MC		 1571 case PHY_ID_BCM50610:
1572 case PHY_ID_BCM50610M:
32e5a8d6 1573 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1574 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1575 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1576 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1577 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1578 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1579 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1580 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1581 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1582 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1583 /* fallthru */
6a443a0f 1584 case PHY_ID_RTL8211C:
fcb389df 1585 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1586 break;
6a443a0f
MC		 1587 case PHY_ID_RTL8201E:
1588 case PHY_ID_BCMAC131:
a9daf367 1589 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1590 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1591 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1592 break;
1593 }
1594
63c3a66f 1595 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1596
4153577a 1597 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1598 tg3_mdio_config_5785(tp);
a9daf367
MC		 1599
1600 return 0;
158d7abd
MC		 1601}
1602
1603static void tg3_mdio_fini(struct tg3 *tp)
1604{
63c3a66f
JP		 1605 if (tg3_flag(tp, MDIOBUS_INITED)) {
1606 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1607 mdiobus_unregister(tp->mdio_bus);
1608 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1609 }
1610}
1611
4ba526ce
MC		 1612/* tp->lock is held. */
1613static inline void tg3_generate_fw_event(struct tg3 *tp)
1614{
1615 u32 val;
1616
1617 val = tr32(GRC_RX_CPU_EVENT);
1618 val |= GRC_RX_CPU_DRIVER_EVENT;
1619 tw32_f(GRC_RX_CPU_EVENT, val);
1620
1621 tp->last_event_jiffies = jiffies;
1622}
1623
1624#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1625
95e2869a
MC		 1626/* tp->lock is held. */
1627static void tg3_wait_for_event_ack(struct tg3 *tp)
1628{
1629 int i;
4ba526ce
MC		 1630 unsigned int delay_cnt;
1631 long time_remain;
1632
1633 /* If enough time has passed, no wait is necessary. */
1634 time_remain = (long)(tp->last_event_jiffies + 1 +
1635 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1636 (long)jiffies;
1637 if (time_remain < 0)
1638 return;
1639
1640 /* Check if we can shorten the wait time. */
1641 delay_cnt = jiffies_to_usecs(time_remain);
1642 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1643 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1644 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1645
4ba526ce 1646 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1647 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1648 break;
6d446ec3
GS		 1649 if (pci_channel_offline(tp->pdev))
1650 break;
1651
4ba526ce 1652 udelay(8);
95e2869a
MC		 1653 }
1654}
1655
1656/* tp->lock is held. */
b28f389d 1657static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1658{
b28f389d 1659 u32 reg, val;
95e2869a
MC		 1660
1661 val = 0;
1662 if (!tg3_readphy(tp, MII_BMCR, &reg))
1663 val = reg << 16;
1664 if (!tg3_readphy(tp, MII_BMSR, &reg))
1665 val |= (reg & 0xffff);
b28f389d 1666 *data++ = val;
95e2869a
MC		 1667
1668 val = 0;
1669 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1670 val = reg << 16;
1671 if (!tg3_readphy(tp, MII_LPA, &reg))
1672 val |= (reg & 0xffff);
b28f389d 1673 *data++ = val;
95e2869a
MC		 1674
1675 val = 0;
f07e9af3 1676 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1677 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1678 val = reg << 16;
1679 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1680 val |= (reg & 0xffff);
1681 }
b28f389d 1682 *data++ = val;
95e2869a
MC		 1683
1684 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1685 val = reg << 16;
1686 else
1687 val = 0;
b28f389d
MC		 1688 *data++ = val;
1689}
1690
1691/* tp->lock is held. */
1692static void tg3_ump_link_report(struct tg3 *tp)
1693{
1694 u32 data[4];
1695
1696 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1697 return;
1698
1699 tg3_phy_gather_ump_data(tp, data);
1700
1701 tg3_wait_for_event_ack(tp);
1702
1703 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1704 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1705 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1706 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1709
4ba526ce 1710 tg3_generate_fw_event(tp);
95e2869a
MC		 1711}
1712
8d5a89b3
MC		 1713/* tp->lock is held. */
1714static void tg3_stop_fw(struct tg3 *tp)
1715{
1716 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1717 /* Wait for RX cpu to ACK the previous event. */
1718 tg3_wait_for_event_ack(tp);
1719
1720 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1721
1722 tg3_generate_fw_event(tp);
1723
1724 /* Wait for RX cpu to ACK this event. */
1725 tg3_wait_for_event_ack(tp);
1726 }
1727}
1728
fd6d3f0e
MC		 1729/* tp->lock is held. */
1730static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1731{
1732 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1733 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1734
1735 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1736 switch (kind) {
1737 case RESET_KIND_INIT:
1738 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1739 DRV_STATE_START);
1740 break;
1741
1742 case RESET_KIND_SHUTDOWN:
1743 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1744 DRV_STATE_UNLOAD);
1745 break;
1746
1747 case RESET_KIND_SUSPEND:
1748 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1749 DRV_STATE_SUSPEND);
1750 break;
1751
1752 default:
1753 break;
1754 }
1755 }
fd6d3f0e
MC		 1756}
1757
1758/* tp->lock is held. */
1759static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1760{
1761 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1762 switch (kind) {
1763 case RESET_KIND_INIT:
1764 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1765 DRV_STATE_START_DONE);
1766 break;
1767
1768 case RESET_KIND_SHUTDOWN:
1769 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1770 DRV_STATE_UNLOAD_DONE);
1771 break;
1772
1773 default:
1774 break;
1775 }
1776 }
fd6d3f0e
MC		 1777}
1778
1779/* tp->lock is held. */
1780static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1781{
1782 if (tg3_flag(tp, ENABLE_ASF)) {
1783 switch (kind) {
1784 case RESET_KIND_INIT:
1785 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1786 DRV_STATE_START);
1787 break;
1788
1789 case RESET_KIND_SHUTDOWN:
1790 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1791 DRV_STATE_UNLOAD);
1792 break;
1793
1794 case RESET_KIND_SUSPEND:
1795 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1796 DRV_STATE_SUSPEND);
1797 break;
1798
1799 default:
1800 break;
1801 }
1802 }
1803}
1804
1805static int tg3_poll_fw(struct tg3 *tp)
1806{
1807 int i;
1808 u32 val;
1809
df465abf
NS		 1810 if (tg3_flag(tp, NO_FWARE_REPORTED))
1811 return 0;
1812
7e6c63f0
HM		 1813 if (tg3_flag(tp, IS_SSB_CORE)) {
1814 /* We don't use firmware. */
1815 return 0;
1816 }
1817
4153577a 1818 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1819 /* Wait up to 20ms for init done. */
1820 for (i = 0; i < 200; i++) {
1821 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1822 return 0;
6d446ec3
GS		 1823 if (pci_channel_offline(tp->pdev))
1824 return -ENODEV;
1825
fd6d3f0e
MC		 1826 udelay(100);
1827 }
1828 return -ENODEV;
1829 }
1830
1831 /* Wait for firmware initialization to complete. */
1832 for (i = 0; i < 100000; i++) {
1833 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1834 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1835 break;
6d446ec3
GS		 1836 if (pci_channel_offline(tp->pdev)) {
1837 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1838 tg3_flag_set(tp, NO_FWARE_REPORTED);
1839 netdev_info(tp->dev, "No firmware running\n");
1840 }
1841
1842 break;
1843 }
1844
fd6d3f0e
MC		 1845 udelay(10);
1846 }
1847
1848 /* Chip might not be fitted with firmware. Some Sun onboard
1849 * parts are configured like that. So don't signal the timeout
1850 * of the above loop as an error, but do report the lack of
1851 * running firmware once.
1852 */
1853 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1854 tg3_flag_set(tp, NO_FWARE_REPORTED);
1855
1856 netdev_info(tp->dev, "No firmware running\n");
1857 }
1858
4153577a 1859 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1860 /* The 57765 A0 needs a little more
1861 * time to do some important work.
1862 */
1863 mdelay(10);
1864 }
1865
1866 return 0;
1867}
1868
95e2869a
MC		 1869static void tg3_link_report(struct tg3 *tp)
1870{
1871 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1872 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1873 tg3_ump_link_report(tp);
1874 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1875 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1876 (tp->link_config.active_speed == SPEED_1000 ?
1877 1000 :
1878 (tp->link_config.active_speed == SPEED_100 ?
1879 100 : 10)),
1880 (tp->link_config.active_duplex == DUPLEX_FULL ?
1881 "full" : "half"));
1882
1883 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1884 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1885 "on" : "off",
1886 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1887 "on" : "off");
47007831
MC		 1888
1889 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1890 netdev_info(tp->dev, "EEE is %s\n",
1891 tp->setlpicnt ? "enabled" : "disabled");
1892
95e2869a
MC		 1893 tg3_ump_link_report(tp);
1894 }
84421b99
NS		 1895
1896 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1897}
1898
fdad8de4
NS		 1899static u32 tg3_decode_flowctrl_1000T(u32 adv)
1900{
1901 u32 flowctrl = 0;
1902
1903 if (adv & ADVERTISE_PAUSE_CAP) {
1904 flowctrl |= FLOW_CTRL_RX;
1905 if (!(adv & ADVERTISE_PAUSE_ASYM))
1906 flowctrl |= FLOW_CTRL_TX;
1907 } else if (adv & ADVERTISE_PAUSE_ASYM)
1908 flowctrl |= FLOW_CTRL_TX;
1909
1910 return flowctrl;
1911}
1912
95e2869a
MC		 1913static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1914{
1915 u16 miireg;
1916
e18ce346 1917 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1918 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1919 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1920 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1921 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1922 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1923 else
1924 miireg = 0;
1925
1926 return miireg;
1927}
1928
fdad8de4
NS		 1929static u32 tg3_decode_flowctrl_1000X(u32 adv)
1930{
1931 u32 flowctrl = 0;
1932
1933 if (adv & ADVERTISE_1000XPAUSE) {
1934 flowctrl |= FLOW_CTRL_RX;
1935 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1936 flowctrl |= FLOW_CTRL_TX;
1937 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1938 flowctrl |= FLOW_CTRL_TX;
1939
1940 return flowctrl;
1941}
1942
95e2869a
MC		 1943static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1944{
1945 u8 cap = 0;
1946
f3791cdf
MC		 1947 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1948 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1949 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1950 if (lcladv & ADVERTISE_1000XPAUSE)
1951 cap = FLOW_CTRL_RX;
1952 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1953 cap = FLOW_CTRL_TX;
95e2869a
MC		 1954 }
1955
1956 return cap;
1957}
1958
f51f3562 1959static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1960{
b02fd9e3 1961 u8 autoneg;
f51f3562 1962 u8 flowctrl = 0;
95e2869a
MC		 1963 u32 old_rx_mode = tp->rx_mode;
1964 u32 old_tx_mode = tp->tx_mode;
1965
63c3a66f 1966 if (tg3_flag(tp, USE_PHYLIB))
3f0e3ad7 1967 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1968 else
1969 autoneg = tp->link_config.autoneg;
1970
63c3a66f 1971 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1972 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1973 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1974 else
bc02ff95 1975 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1976 } else
1977 flowctrl = tp->link_config.flowctrl;
95e2869a 1978
f51f3562 1979 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1980
e18ce346 1981 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1982 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1983 else
1984 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1985
f51f3562 1986 if (old_rx_mode != tp->rx_mode)
95e2869a 1987 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1988
e18ce346 1989 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1990 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1991 else
1992 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1993
f51f3562 1994 if (old_tx_mode != tp->tx_mode)
95e2869a 1995 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1996}
1997
b02fd9e3
MC		 1998static void tg3_adjust_link(struct net_device *dev)
1999{
2000 u8 oldflowctrl, linkmesg = 0;
2001 u32 mac_mode, lcl_adv, rmt_adv;
2002 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 2003 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 2004
24bb4fb6 2005 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 2006
2007 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2008 MAC_MODE_HALF_DUPLEX);
2009
2010 oldflowctrl = tp->link_config.active_flowctrl;
2011
2012 if (phydev->link) {
2013 lcl_adv = 0;
2014 rmt_adv = 0;
2015
2016 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2017 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2018 else if (phydev->speed == SPEED_1000 ||
4153577a 2019 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2020 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2021 else
2022 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2023
2024 if (phydev->duplex == DUPLEX_HALF)
2025 mac_mode |= MAC_MODE_HALF_DUPLEX;
2026 else {
f88788f0 2027 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2028 tp->link_config.flowctrl);
2029
2030 if (phydev->pause)
2031 rmt_adv = LPA_PAUSE_CAP;
2032 if (phydev->asym_pause)
2033 rmt_adv |= LPA_PAUSE_ASYM;
2034 }
2035
2036 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2037 } else
2038 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2039
2040 if (mac_mode != tp->mac_mode) {
2041 tp->mac_mode = mac_mode;
2042 tw32_f(MAC_MODE, tp->mac_mode);
2043 udelay(40);
2044 }
2045
4153577a 2046 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2047 if (phydev->speed == SPEED_10)
2048 tw32(MAC_MI_STAT,
2049 MAC_MI_STAT_10MBPS_MODE |
2050 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2051 else
2052 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2053 }
2054
b02fd9e3
MC		 2055 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2056 tw32(MAC_TX_LENGTHS,
2057 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2058 (6 << TX_LENGTHS_IPG_SHIFT) |
2059 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2060 else
2061 tw32(MAC_TX_LENGTHS,
2062 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2063 (6 << TX_LENGTHS_IPG_SHIFT) |
2064 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2065
34655ad6 2066 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2067 phydev->speed != tp->link_config.active_speed ||
2068 phydev->duplex != tp->link_config.active_duplex ||
2069 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2070 linkmesg = 1;
b02fd9e3 2071
34655ad6 2072 tp->old_link = phydev->link;
b02fd9e3
MC		 2073 tp->link_config.active_speed = phydev->speed;
2074 tp->link_config.active_duplex = phydev->duplex;
2075
24bb4fb6 2076 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2077
2078 if (linkmesg)
2079 tg3_link_report(tp);
2080}
2081
2082static int tg3_phy_init(struct tg3 *tp)
2083{
2084 struct phy_device *phydev;
2085
f07e9af3 2086 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2087 return 0;
2088
2089 /* Bring the PHY back to a known state. */
2090 tg3_bmcr_reset(tp);
2091
3f0e3ad7 2092 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2093
2094 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2095 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2096 tg3_adjust_link, phydev->interface);
b02fd9e3 2097 if (IS_ERR(phydev)) {
ab96b241 2098 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2099 return PTR_ERR(phydev);
2100 }
2101
b02fd9e3 2102 /* Mask with MAC supported features. */
9c61d6bc
MC		 2103 switch (phydev->interface) {
2104 case PHY_INTERFACE_MODE_GMII:
2105 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2106 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2107 phydev->supported &= (PHY_GBIT_FEATURES |
2108 SUPPORTED_Pause |
2109 SUPPORTED_Asym_Pause);
2110 break;
2111 }
2112 /* fallthru */
9c61d6bc
MC		 2113 case PHY_INTERFACE_MODE_MII:
2114 phydev->supported &= (PHY_BASIC_FEATURES |
2115 SUPPORTED_Pause |
2116 SUPPORTED_Asym_Pause);
2117 break;
2118 default:
3f0e3ad7 2119 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 2120 return -EINVAL;
2121 }
2122
f07e9af3 2123 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2124
2125 phydev->advertising = phydev->supported;
2126
b02fd9e3
MC		 2127 return 0;
2128}
2129
2130static void tg3_phy_start(struct tg3 *tp)
2131{
2132 struct phy_device *phydev;
2133
f07e9af3 2134 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2135 return;
2136
3f0e3ad7 2137 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 2138
80096068
MC		 2139 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2140 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2141 phydev->speed = tp->link_config.speed;
2142 phydev->duplex = tp->link_config.duplex;
2143 phydev->autoneg = tp->link_config.autoneg;
2144 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2145 }
2146
2147 phy_start(phydev);
2148
2149 phy_start_aneg(phydev);
2150}
2151
2152static void tg3_phy_stop(struct tg3 *tp)
2153{
f07e9af3 2154 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2155 return;
2156
3f0e3ad7 2157 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 2158}
2159
2160static void tg3_phy_fini(struct tg3 *tp)
2161{
f07e9af3 2162 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 2163 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
f07e9af3 2164 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2165 }
2166}
2167
941ec90f
MC		 2168static int tg3_phy_set_extloopbk(struct tg3 *tp)
2169{
2170 int err;
2171 u32 val;
2172
2173 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2174 return 0;
2175
2176 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2177 /* Cannot do read-modify-write on 5401 */
2178 err = tg3_phy_auxctl_write(tp,
2179 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2180 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2181 0x4c20);
2182 goto done;
2183 }
2184
2185 err = tg3_phy_auxctl_read(tp,
2186 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2187 if (err)
2188 return err;
2189
2190 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2191 err = tg3_phy_auxctl_write(tp,
2192 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2193
2194done:
2195 return err;
2196}
2197
7f97a4bd
MC		 2198static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2199{
2200 u32 phytest;
2201
2202 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2203 u32 phy;
2204
2205 tg3_writephy(tp, MII_TG3_FET_TEST,
2206 phytest | MII_TG3_FET_SHADOW_EN);
2207 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2208 if (enable)
2209 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2210 else
2211 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2212 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2213 }
2214 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2215 }
2216}
2217
6833c043
MC		 2218static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2219{
2220 u32 reg;
2221
63c3a66f
JP		 2222 if (!tg3_flag(tp, 5705_PLUS) ||
2223 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2224 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2225 return;
2226
f07e9af3 2227 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2228 tg3_phy_fet_toggle_apd(tp, enable);
2229 return;
2230 }
2231
3ab71071 2232 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
6833c043
MC		 2233 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2234 MII_TG3_MISC_SHDW_SCR5_SDTL |
2235 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2236 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2237 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2238
3ab71071 2239 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
6833c043
MC		 2240
2241
3ab71071 2242 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
6833c043
MC		 2243 if (enable)
2244 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2245
3ab71071 2246 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
6833c043
MC		 2247}
2248
953c96e0 2249static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2250{
2251 u32 phy;
2252
63c3a66f 2253 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2254 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2255 return;
2256
f07e9af3 2257 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2258 u32 ephy;
2259
535ef6e1
MC		 2260 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2261 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2262
2263 tg3_writephy(tp, MII_TG3_FET_TEST,
2264 ephy | MII_TG3_FET_SHADOW_EN);
2265 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2266 if (enable)
535ef6e1 2267 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2268 else
535ef6e1
MC		 2269 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2270 tg3_writephy(tp, reg, phy);
9ef8ca99 2271 }
535ef6e1 2272 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2273 }
2274 } else {
15ee95c3
MC		 2275 int ret;
2276
2277 ret = tg3_phy_auxctl_read(tp,
2278 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2279 if (!ret) {
9ef8ca99
MC		 2280 if (enable)
2281 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2282 else
2283 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2284 tg3_phy_auxctl_write(tp,
2285 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2286 }
2287 }
2288}
2289
1da177e4
LT		 2290static void tg3_phy_set_wirespeed(struct tg3 *tp)
2291{
15ee95c3 2292 int ret;
1da177e4
LT		 2293 u32 val;
2294
f07e9af3 2295 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2296 return;
2297
15ee95c3
MC		 2298 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2299 if (!ret)
b4bd2929
MC		 2300 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2301 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2302}
2303
b2a5c19c
MC		 2304static void tg3_phy_apply_otp(struct tg3 *tp)
2305{
2306 u32 otp, phy;
2307
2308 if (!tp->phy_otp)
2309 return;
2310
2311 otp = tp->phy_otp;
2312
daf3ec68 2313 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2314 return;
b2a5c19c
MC		 2315
2316 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2317 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2318 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2319
2320 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2321 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2322 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2323
2324 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2325 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2327
2328 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2329 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2330
2331 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2332 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2333
2334 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2335 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2337
daf3ec68 2338 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2339}
2340
400dfbaa
NS		 2341static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2342{
2343 u32 val;
2344 struct ethtool_eee *dest = &tp->eee;
2345
2346 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2347 return;
2348
2349 if (eee)
2350 dest = eee;
2351
2352 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2353 return;
2354
2355 /* Pull eee_active */
2356 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2357 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2358 dest->eee_active = 1;
2359 } else
2360 dest->eee_active = 0;
2361
2362 /* Pull lp advertised settings */
2363 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2364 return;
2365 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2366
2367 /* Pull advertised and eee_enabled settings */
2368 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2369 return;
2370 dest->eee_enabled = !!val;
2371 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2372
2373 /* Pull tx_lpi_enabled */
2374 val = tr32(TG3_CPMU_EEE_MODE);
2375 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2376
2377 /* Pull lpi timer value */
2378 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2379}
2380
953c96e0 2381static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2382{
2383 u32 val;
2384
2385 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2386 return;
2387
2388 tp->setlpicnt = 0;
2389
2390 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2391 current_link_up &&
a6b68dab
MC		 2392 tp->link_config.active_duplex == DUPLEX_FULL &&
2393 (tp->link_config.active_speed == SPEED_100 ||
2394 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2395 u32 eeectl;
2396
2397 if (tp->link_config.active_speed == SPEED_1000)
2398 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2399 else
2400 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2401
2402 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2403
400dfbaa
NS		 2404 tg3_eee_pull_config(tp, NULL);
2405 if (tp->eee.eee_active)
52b02d04
MC		 2406 tp->setlpicnt = 2;
2407 }
2408
2409 if (!tp->setlpicnt) {
953c96e0 2410 if (current_link_up &&
daf3ec68 2411 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2412 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2413 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2414 }
2415
52b02d04
MC		 2416 val = tr32(TG3_CPMU_EEE_MODE);
2417 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2418 }
2419}
2420
b0c5943f
MC		 2421static void tg3_phy_eee_enable(struct tg3 *tp)
2422{
2423 u32 val;
2424
2425 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2426 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2427 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2428 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2429 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2430 val = MII_TG3_DSP_TAP26_ALNOKO |
2431 MII_TG3_DSP_TAP26_RMRXSTO;
2432 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2433 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2434 }
2435
2436 val = tr32(TG3_CPMU_EEE_MODE);
2437 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2438}
2439
1da177e4
LT		 2440static int tg3_wait_macro_done(struct tg3 *tp)
2441{
2442 int limit = 100;
2443
2444 while (limit--) {
2445 u32 tmp32;
2446
f08aa1a8 2447 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2448 if ((tmp32 & 0x1000) == 0)
2449 break;
2450 }
2451 }
d4675b52 2452 if (limit < 0)
1da177e4
LT		 2453 return -EBUSY;
2454
2455 return 0;
2456}
2457
2458static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2459{
2460 static const u32 test_pat[4][6] = {
2461 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2462 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2463 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2464 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2465 };
2466 int chan;
2467
2468 for (chan = 0; chan < 4; chan++) {
2469 int i;
2470
2471 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2472 (chan * 0x2000) | 0x0200);
f08aa1a8 2473 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2474
2475 for (i = 0; i < 6; i++)
2476 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2477 test_pat[chan][i]);
2478
f08aa1a8 2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2480 if (tg3_wait_macro_done(tp)) {
2481 *resetp = 1;
2482 return -EBUSY;
2483 }
2484
2485 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2486 (chan * 0x2000) | 0x0200);
f08aa1a8 2487 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2488 if (tg3_wait_macro_done(tp)) {
2489 *resetp = 1;
2490 return -EBUSY;
2491 }
2492
f08aa1a8 2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2494 if (tg3_wait_macro_done(tp)) {
2495 *resetp = 1;
2496 return -EBUSY;
2497 }
2498
2499 for (i = 0; i < 6; i += 2) {
2500 u32 low, high;
2501
2502 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2503 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2504 tg3_wait_macro_done(tp)) {
2505 *resetp = 1;
2506 return -EBUSY;
2507 }
2508 low &= 0x7fff;
2509 high &= 0x000f;
2510 if (low != test_pat[chan][i] ||
2511 high != test_pat[chan][i+1]) {
2512 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2513 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2515
2516 return -EBUSY;
2517 }
2518 }
2519 }
2520
2521 return 0;
2522}
2523
2524static int tg3_phy_reset_chanpat(struct tg3 *tp)
2525{
2526 int chan;
2527
2528 for (chan = 0; chan < 4; chan++) {
2529 int i;
2530
2531 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2532 (chan * 0x2000) | 0x0200);
f08aa1a8 2533 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2534 for (i = 0; i < 6; i++)
2535 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2536 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2537 if (tg3_wait_macro_done(tp))
2538 return -EBUSY;
2539 }
2540
2541 return 0;
2542}
2543
2544static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2545{
2546 u32 reg32, phy9_orig;
2547 int retries, do_phy_reset, err;
2548
2549 retries = 10;
2550 do_phy_reset = 1;
2551 do {
2552 if (do_phy_reset) {
2553 err = tg3_bmcr_reset(tp);
2554 if (err)
2555 return err;
2556 do_phy_reset = 0;
2557 }
2558
2559 /* Disable transmitter and interrupt. */
2560 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2561 continue;
2562
2563 reg32 |= 0x3000;
2564 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2565
2566 /* Set full-duplex, 1000 mbps. */
2567 tg3_writephy(tp, MII_BMCR,
221c5637 2568 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2569
2570 /* Set to master mode. */
221c5637 2571 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2572 continue;
2573
221c5637
MC		 2574 tg3_writephy(tp, MII_CTRL1000,
2575 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2576
daf3ec68 2577 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2578 if (err)
2579 return err;
1da177e4
LT		 2580
2581 /* Block the PHY control access. */
6ee7c0a0 2582 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2583
2584 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2585 if (!err)
2586 break;
2587 } while (--retries);
2588
2589 err = tg3_phy_reset_chanpat(tp);
2590 if (err)
2591 return err;
2592
6ee7c0a0 2593 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2594
2595 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2596 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2597
daf3ec68 2598 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2599
221c5637 2600 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4
LT		 2601
2602 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2603 reg32 &= ~0x3000;
2604 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2605 } else if (!err)
2606 err = -EBUSY;
2607
2608 return err;
2609}
2610
f4a46d1f
NNS		 2611static void tg3_carrier_off(struct tg3 *tp)
2612{
2613 netif_carrier_off(tp->dev);
2614 tp->link_up = false;
2615}
2616
ce20f161
NS		 2617static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2618{
2619 if (tg3_flag(tp, ENABLE_ASF))
2620 netdev_warn(tp->dev,
2621 "Management side-band traffic will be interrupted during phy settings change\n");
2622}
2623
1da177e4
LT		 2624/* This will reset the tigon3 PHY if there is no valid
2625 * link unless the FORCE argument is non-zero.
2626 */
2627static int tg3_phy_reset(struct tg3 *tp)
2628{
f833c4c1 2629 u32 val, cpmuctrl;
1da177e4
LT		 2630 int err;
2631
4153577a 2632 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2633 val = tr32(GRC_MISC_CFG);
2634 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2635 udelay(40);
2636 }
f833c4c1
MC		 2637 err = tg3_readphy(tp, MII_BMSR, &val);
2638 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2639 if (err != 0)
2640 return -EBUSY;
2641
f4a46d1f 2642 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2643 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2644 tg3_link_report(tp);
2645 }
2646
4153577a
JP		 2647 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2648 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2649 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2650 err = tg3_phy_reset_5703_4_5(tp);
2651 if (err)
2652 return err;
2653 goto out;
2654 }
2655
b2a5c19c 2656 cpmuctrl = 0;
4153577a
JP		 2657 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2658 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2659 cpmuctrl = tr32(TG3_CPMU_CTRL);
2660 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2661 tw32(TG3_CPMU_CTRL,
2662 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2663 }
2664
1da177e4
LT		 2665 err = tg3_bmcr_reset(tp);
2666 if (err)
2667 return err;
2668
b2a5c19c 2669 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2670 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2671 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2672
2673 tw32(TG3_CPMU_CTRL, cpmuctrl);
2674 }
2675
4153577a
JP		 2676 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2677 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2678 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2679 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2680 CPMU_LSPD_1000MB_MACCLK_12_5) {
2681 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2682 udelay(40);
2683 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2684 }
2685 }
2686
63c3a66f 2687 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2688 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2689 return 0;
2690
b2a5c19c
MC		 2691 tg3_phy_apply_otp(tp);
2692
f07e9af3 2693 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2694 tg3_phy_toggle_apd(tp, true);
2695 else
2696 tg3_phy_toggle_apd(tp, false);
2697
1da177e4 2698out:
1d36ba45 2699 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2700 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2701 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2702 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2703 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2704 }
1d36ba45 2705
f07e9af3 2706 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2707 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2708 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2709 }
1d36ba45 2710
f07e9af3 2711 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2712 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2713 tg3_phydsp_write(tp, 0x000a, 0x310b);
2714 tg3_phydsp_write(tp, 0x201f, 0x9506);
2715 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2716 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2717 }
f07e9af3 2718 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2719 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2720 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2721 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2722 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2723 tg3_writephy(tp, MII_TG3_TEST1,
2724 MII_TG3_TEST1_TRIM_EN | 0x4);
2725 } else
2726 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2727
daf3ec68 2728 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2729 }
c424cb24 2730 }
1d36ba45 2731
1da177e4
LT		 2732 /* Set Extended packet length bit (bit 14) on all chips that */
2733 /* support jumbo frames */
79eb6904 2734 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2735 /* Cannot do read-modify-write on 5401 */
b4bd2929 2736 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2737 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2738 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2739 err = tg3_phy_auxctl_read(tp,
2740 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2741 if (!err)
b4bd2929
MC		 2742 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2743 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2744 }
2745
2746 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2747 * jumbo frames transmission.
2748 */
63c3a66f 2749 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2750 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2751 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2752 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2753 }
2754
4153577a 2755 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2756 /* adjust output voltage */
535ef6e1 2757 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2758 }
2759
4153577a 2760 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2761 tg3_phydsp_write(tp, 0xffb, 0x4000);
2762
953c96e0 2763 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2764 tg3_phy_set_wirespeed(tp);
2765 return 0;
2766}
2767
3a1e19d3
MC		 2768#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2769#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2770#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2771 TG3_GPIO_MSG_NEED_VAUX)
2772#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2773 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2774 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2775 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2776 (TG3_GPIO_MSG_DRVR_PRES << 12))
2777
2778#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2779 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2780 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2781 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2782 (TG3_GPIO_MSG_NEED_VAUX << 12))
2783
2784static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2785{
2786 u32 status, shift;
2787
4153577a
JP		 2788 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2789 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2790 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2791 else
2792 status = tr32(TG3_CPMU_DRV_STATUS);
2793
2794 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2795 status &= ~(TG3_GPIO_MSG_MASK << shift);
2796 status |= (newstat << shift);
2797
4153577a
JP		 2798 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2799 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2800 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2801 else
2802 tw32(TG3_CPMU_DRV_STATUS, status);
2803
2804 return status >> TG3_APE_GPIO_MSG_SHIFT;
2805}
2806
520b2756
MC		 2807static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2808{
2809 if (!tg3_flag(tp, IS_NIC))
2810 return 0;
2811
4153577a
JP		 2812 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2813 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2814 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2815 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2816 return -EIO;
520b2756 2817
3a1e19d3
MC		 2818 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2819
2820 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2821 TG3_GRC_LCLCTL_PWRSW_DELAY);
2822
2823 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2824 } else {
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2827 }
6f5c8f83 2828
520b2756
MC		 2829 return 0;
2830}
2831
2832static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2833{
2834 u32 grc_local_ctrl;
2835
2836 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2837 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2838 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2839 return;
2840
2841 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2842
2843 tw32_wait_f(GRC_LOCAL_CTRL,
2844 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2845 TG3_GRC_LCLCTL_PWRSW_DELAY);
2846
2847 tw32_wait_f(GRC_LOCAL_CTRL,
2848 grc_local_ctrl,
2849 TG3_GRC_LCLCTL_PWRSW_DELAY);
2850
2851 tw32_wait_f(GRC_LOCAL_CTRL,
2852 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2853 TG3_GRC_LCLCTL_PWRSW_DELAY);
2854}
2855
2856static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2857{
2858 if (!tg3_flag(tp, IS_NIC))
2859 return;
2860
4153577a
JP		 2861 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2862 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2863 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2864 (GRC_LCLCTRL_GPIO_OE0 |
2865 GRC_LCLCTRL_GPIO_OE1 |
2866 GRC_LCLCTRL_GPIO_OE2 |
2867 GRC_LCLCTRL_GPIO_OUTPUT0 |
2868 GRC_LCLCTRL_GPIO_OUTPUT1),
2869 TG3_GRC_LCLCTL_PWRSW_DELAY);
2870 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2871 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2872 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2873 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2874 GRC_LCLCTRL_GPIO_OE1 |
2875 GRC_LCLCTRL_GPIO_OE2 |
2876 GRC_LCLCTRL_GPIO_OUTPUT0 |
2877 GRC_LCLCTRL_GPIO_OUTPUT1 |
2878 tp->grc_local_ctrl;
2879 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2880 TG3_GRC_LCLCTL_PWRSW_DELAY);
2881
2882 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2883 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2884 TG3_GRC_LCLCTL_PWRSW_DELAY);
2885
2886 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2887 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2888 TG3_GRC_LCLCTL_PWRSW_DELAY);
2889 } else {
2890 u32 no_gpio2;
2891 u32 grc_local_ctrl = 0;
2892
2893 /* Workaround to prevent overdrawing Amps. */
4153577a 2894 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2895 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2896 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2897 grc_local_ctrl,
2898 TG3_GRC_LCLCTL_PWRSW_DELAY);
2899 }
2900
2901 /* On 5753 and variants, GPIO2 cannot be used. */
2902 no_gpio2 = tp->nic_sram_data_cfg &
2903 NIC_SRAM_DATA_CFG_NO_GPIO2;
2904
2905 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2906 GRC_LCLCTRL_GPIO_OE1 |
2907 GRC_LCLCTRL_GPIO_OE2 |
2908 GRC_LCLCTRL_GPIO_OUTPUT1 |
2909 GRC_LCLCTRL_GPIO_OUTPUT2;
2910 if (no_gpio2) {
2911 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2912 GRC_LCLCTRL_GPIO_OUTPUT2);
2913 }
2914 tw32_wait_f(GRC_LOCAL_CTRL,
2915 tp->grc_local_ctrl | grc_local_ctrl,
2916 TG3_GRC_LCLCTL_PWRSW_DELAY);
2917
2918 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2919
2920 tw32_wait_f(GRC_LOCAL_CTRL,
2921 tp->grc_local_ctrl | grc_local_ctrl,
2922 TG3_GRC_LCLCTL_PWRSW_DELAY);
2923
2924 if (!no_gpio2) {
2925 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2926 tw32_wait_f(GRC_LOCAL_CTRL,
2927 tp->grc_local_ctrl | grc_local_ctrl,
2928 TG3_GRC_LCLCTL_PWRSW_DELAY);
2929 }
2930 }
3a1e19d3
MC		 2931}
2932
cd0d7228 2933static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2934{
2935 u32 msg = 0;
2936
2937 /* Serialize power state transitions */
2938 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2939 return;
2940
cd0d7228 2941 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2942 msg = TG3_GPIO_MSG_NEED_VAUX;
2943
2944 msg = tg3_set_function_status(tp, msg);
2945
2946 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2947 goto done;
6f5c8f83 2948
3a1e19d3
MC		 2949 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2950 tg3_pwrsrc_switch_to_vaux(tp);
2951 else
2952 tg3_pwrsrc_die_with_vmain(tp);
2953
2954done:
6f5c8f83 2955 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2956}
2957
cd0d7228 2958static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2959{
683644b7 2960 bool need_vaux = false;
1da177e4 2961
334355aa 2962 /* The GPIOs do something completely different on 57765. */
55086ad9 2963 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2964 return;
2965
4153577a
JP		 2966 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2967 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2968 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2969 tg3_frob_aux_power_5717(tp, include_wol ?
2970 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2971 return;
2972 }
2973
2974 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2975 struct net_device *dev_peer;
2976
2977 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2978
bc1c7567 2979 /* remove_one() may have been run on the peer. */
683644b7
MC		 2980 if (dev_peer) {
2981 struct tg3 *tp_peer = netdev_priv(dev_peer);
2982
63c3a66f 2983 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2984 return;
2985
cd0d7228 2986 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2987 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2988 need_vaux = true;
2989 }
1da177e4
LT		 2990 }
2991
cd0d7228
MC		 2992 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2993 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 2994 need_vaux = true;
2995
520b2756
MC		 2996 if (need_vaux)
2997 tg3_pwrsrc_switch_to_vaux(tp);
2998 else
2999 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 3000}
3001
e8f3f6ca
MC		 3002static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3003{
3004 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3005 return 1;
79eb6904 3006 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3007 if (speed != SPEED_10)
3008 return 1;
3009 } else if (speed == SPEED_10)
3010 return 1;
3011
3012 return 0;
3013}
3014
44f3b503
NS		 3015static bool tg3_phy_power_bug(struct tg3 *tp)
3016{
3017 switch (tg3_asic_rev(tp)) {
3018 case ASIC_REV_5700:
3019 case ASIC_REV_5704:
3020 return true;
3021 case ASIC_REV_5780:
3022 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3023 return true;
3024 return false;
3025 case ASIC_REV_5717:
3026 if (!tp->pci_fn)
3027 return true;
3028 return false;
3029 case ASIC_REV_5719:
3030 case ASIC_REV_5720:
3031 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3032 !tp->pci_fn)
3033 return true;
3034 return false;
3035 }
3036
3037 return false;
3038}
3039
989038e2
NS		 3040static bool tg3_phy_led_bug(struct tg3 *tp)
3041{
3042 switch (tg3_asic_rev(tp)) {
3043 case ASIC_REV_5719:
300cf9b9 3044 case ASIC_REV_5720:
989038e2
NS		 3045 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3046 !tp->pci_fn)
3047 return true;
3048 return false;
3049 }
3050
3051 return false;
3052}
3053
0a459aac 3054static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3055{
ce057f01
MC		 3056 u32 val;
3057
942d1af0
NS		 3058 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3059 return;
3060
f07e9af3 3061 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3062 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3063 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3064 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3065
3066 sg_dig_ctrl |=
3067 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3068 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3069 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3070 }
3f7045c1 3071 return;
5129724a 3072 }
3f7045c1 3073
4153577a 3074 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3075 tg3_bmcr_reset(tp);
3076 val = tr32(GRC_MISC_CFG);
3077 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3078 udelay(40);
3079 return;
f07e9af3 3080 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3081 u32 phytest;
3082 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3083 u32 phy;
3084
3085 tg3_writephy(tp, MII_ADVERTISE, 0);
3086 tg3_writephy(tp, MII_BMCR,
3087 BMCR_ANENABLE | BMCR_ANRESTART);
3088
3089 tg3_writephy(tp, MII_TG3_FET_TEST,
3090 phytest | MII_TG3_FET_SHADOW_EN);
3091 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3092 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3093 tg3_writephy(tp,
3094 MII_TG3_FET_SHDW_AUXMODE4,
3095 phy);
3096 }
3097 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3098 }
3099 return;
0a459aac 3100 } else if (do_low_power) {
989038e2
NS		 3101 if (!tg3_phy_led_bug(tp))
3102 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3103 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3104
b4bd2929
MC		 3105 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3106 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3107 MII_TG3_AUXCTL_PCTL_VREG_11V;
3108 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3109 }
3f7045c1 3110
15c3b696
MC		 3111 /* The PHY should not be powered down on some chips because
3112 * of bugs.
3113 */
44f3b503 3114 if (tg3_phy_power_bug(tp))
15c3b696 3115 return;
ce057f01 3116
4153577a
JP		 3117 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3118 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3119 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3120 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3121 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3122 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3123 }
3124
15c3b696
MC		 3125 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3126}
3127
ffbcfed4
MC		 3128/* tp->lock is held. */
3129static int tg3_nvram_lock(struct tg3 *tp)
3130{
63c3a66f 3131 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3132 int i;
3133
3134 if (tp->nvram_lock_cnt == 0) {
3135 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3136 for (i = 0; i < 8000; i++) {
3137 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3138 break;
3139 udelay(20);
3140 }
3141 if (i == 8000) {
3142 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3143 return -ENODEV;
3144 }
3145 }
3146 tp->nvram_lock_cnt++;
3147 }
3148 return 0;
3149}
3150
3151/* tp->lock is held. */
3152static void tg3_nvram_unlock(struct tg3 *tp)
3153{
63c3a66f 3154 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3155 if (tp->nvram_lock_cnt > 0)
3156 tp->nvram_lock_cnt--;
3157 if (tp->nvram_lock_cnt == 0)
3158 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3159 }
3160}
3161
3162/* tp->lock is held. */
3163static void tg3_enable_nvram_access(struct tg3 *tp)
3164{
63c3a66f 3165 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3166 u32 nvaccess = tr32(NVRAM_ACCESS);
3167
3168 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3169 }
3170}
3171
3172/* tp->lock is held. */
3173static void tg3_disable_nvram_access(struct tg3 *tp)
3174{
63c3a66f 3175 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3176 u32 nvaccess = tr32(NVRAM_ACCESS);
3177
3178 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3179 }
3180}
3181
3182static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3183 u32 offset, u32 *val)
3184{
3185 u32 tmp;
3186 int i;
3187
3188 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3189 return -EINVAL;
3190
3191 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3192 EEPROM_ADDR_DEVID_MASK |
3193 EEPROM_ADDR_READ);
3194 tw32(GRC_EEPROM_ADDR,
3195 tmp |
3196 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3197 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3198 EEPROM_ADDR_ADDR_MASK) |
3199 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3200
3201 for (i = 0; i < 1000; i++) {
3202 tmp = tr32(GRC_EEPROM_ADDR);
3203
3204 if (tmp & EEPROM_ADDR_COMPLETE)
3205 break;
3206 msleep(1);
3207 }
3208 if (!(tmp & EEPROM_ADDR_COMPLETE))
3209 return -EBUSY;
3210
62cedd11
MC		 3211 tmp = tr32(GRC_EEPROM_DATA);
3212
3213 /*
3214 * The data will always be opposite the native endian
3215 * format. Perform a blind byteswap to compensate.
3216 */
3217 *val = swab32(tmp);
3218
ffbcfed4
MC		 3219 return 0;
3220}
3221
3222#define NVRAM_CMD_TIMEOUT 10000
3223
3224static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3225{
3226 int i;
3227
3228 tw32(NVRAM_CMD, nvram_cmd);
3229 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3230 udelay(10);
3231 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3232 udelay(10);
3233 break;
3234 }
3235 }
3236
3237 if (i == NVRAM_CMD_TIMEOUT)
3238 return -EBUSY;
3239
3240 return 0;
3241}
3242
3243static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3244{
63c3a66f
JP		 3245 if (tg3_flag(tp, NVRAM) &&
3246 tg3_flag(tp, NVRAM_BUFFERED) &&
3247 tg3_flag(tp, FLASH) &&
3248 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3249 (tp->nvram_jedecnum == JEDEC_ATMEL))
3250
3251 addr = ((addr / tp->nvram_pagesize) <<
3252 ATMEL_AT45DB0X1B_PAGE_POS) +
3253 (addr % tp->nvram_pagesize);
3254
3255 return addr;
3256}
3257
3258static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3259{
63c3a66f
JP		 3260 if (tg3_flag(tp, NVRAM) &&
3261 tg3_flag(tp, NVRAM_BUFFERED) &&
3262 tg3_flag(tp, FLASH) &&
3263 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3264 (tp->nvram_jedecnum == JEDEC_ATMEL))
3265
3266 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3267 tp->nvram_pagesize) +
3268 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3269
3270 return addr;
3271}
3272
e4f34110
MC		 3273/* NOTE: Data read in from NVRAM is byteswapped according to
3274 * the byteswapping settings for all other register accesses.
3275 * tg3 devices are BE devices, so on a BE machine, the data
3276 * returned will be exactly as it is seen in NVRAM. On a LE
3277 * machine, the 32-bit value will be byteswapped.
3278 */
ffbcfed4
MC		 3279static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3280{
3281 int ret;
3282
63c3a66f 3283 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3284 return tg3_nvram_read_using_eeprom(tp, offset, val);
3285
3286 offset = tg3_nvram_phys_addr(tp, offset);
3287
3288 if (offset > NVRAM_ADDR_MSK)
3289 return -EINVAL;
3290
3291 ret = tg3_nvram_lock(tp);
3292 if (ret)
3293 return ret;
3294
3295 tg3_enable_nvram_access(tp);
3296
3297 tw32(NVRAM_ADDR, offset);
3298 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3299 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3300
3301 if (ret == 0)
e4f34110 3302 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3303
3304 tg3_disable_nvram_access(tp);
3305
3306 tg3_nvram_unlock(tp);
3307
3308 return ret;
3309}
3310
a9dc529d
MC		 3311/* Ensures NVRAM data is in bytestream format. */
3312static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3313{
3314 u32 v;
a9dc529d 3315 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3316 if (!res)
a9dc529d 3317 *val = cpu_to_be32(v);
ffbcfed4
MC		 3318 return res;
3319}
3320
dbe9b92a
MC		 3321static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3322 u32 offset, u32 len, u8 *buf)
3323{
3324 int i, j, rc = 0;
3325 u32 val;
3326
3327 for (i = 0; i < len; i += 4) {
3328 u32 addr;
3329 __be32 data;
3330
3331 addr = offset + i;
3332
3333 memcpy(&data, buf + i, 4);
3334
3335 /*
3336 * The SEEPROM interface expects the data to always be opposite
3337 * the native endian format. We accomplish this by reversing
3338 * all the operations that would have been performed on the
3339 * data from a call to tg3_nvram_read_be32().
3340 */
3341 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3342
3343 val = tr32(GRC_EEPROM_ADDR);
3344 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3345
3346 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3347 EEPROM_ADDR_READ);
3348 tw32(GRC_EEPROM_ADDR, val |
3349 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3350 (addr & EEPROM_ADDR_ADDR_MASK) |
3351 EEPROM_ADDR_START |
3352 EEPROM_ADDR_WRITE);
3353
3354 for (j = 0; j < 1000; j++) {
3355 val = tr32(GRC_EEPROM_ADDR);
3356
3357 if (val & EEPROM_ADDR_COMPLETE)
3358 break;
3359 msleep(1);
3360 }
3361 if (!(val & EEPROM_ADDR_COMPLETE)) {
3362 rc = -EBUSY;
3363 break;
3364 }
3365 }
3366
3367 return rc;
3368}
3369
3370/* offset and length are dword aligned */
3371static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3372 u8 *buf)
3373{
3374 int ret = 0;
3375 u32 pagesize = tp->nvram_pagesize;
3376 u32 pagemask = pagesize - 1;
3377 u32 nvram_cmd;
3378 u8 *tmp;
3379
3380 tmp = kmalloc(pagesize, GFP_KERNEL);
3381 if (tmp == NULL)
3382 return -ENOMEM;
3383
3384 while (len) {
3385 int j;
3386 u32 phy_addr, page_off, size;
3387
3388 phy_addr = offset & ~pagemask;
3389
3390 for (j = 0; j < pagesize; j += 4) {
3391 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3392 (__be32 *) (tmp + j));
3393 if (ret)
3394 break;
3395 }
3396 if (ret)
3397 break;
3398
3399 page_off = offset & pagemask;
3400 size = pagesize;
3401 if (len < size)
3402 size = len;
3403
3404 len -= size;
3405
3406 memcpy(tmp + page_off, buf, size);
3407
3408 offset = offset + (pagesize - page_off);
3409
3410 tg3_enable_nvram_access(tp);
3411
3412 /*
3413 * Before we can erase the flash page, we need
3414 * to issue a special "write enable" command.
3415 */
3416 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3417
3418 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3419 break;
3420
3421 /* Erase the target page */
3422 tw32(NVRAM_ADDR, phy_addr);
3423
3424 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3425 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3426
3427 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3428 break;
3429
3430 /* Issue another write enable to start the write. */
3431 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3432
3433 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3434 break;
3435
3436 for (j = 0; j < pagesize; j += 4) {
3437 __be32 data;
3438
3439 data = *((__be32 *) (tmp + j));
3440
3441 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3442
3443 tw32(NVRAM_ADDR, phy_addr + j);
3444
3445 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3446 NVRAM_CMD_WR;
3447
3448 if (j == 0)
3449 nvram_cmd |= NVRAM_CMD_FIRST;
3450 else if (j == (pagesize - 4))
3451 nvram_cmd |= NVRAM_CMD_LAST;
3452
3453 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3454 if (ret)
3455 break;
3456 }
3457 if (ret)
3458 break;
3459 }
3460
3461 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3462 tg3_nvram_exec_cmd(tp, nvram_cmd);
3463
3464 kfree(tmp);
3465
3466 return ret;
3467}
3468
3469/* offset and length are dword aligned */
3470static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3471 u8 *buf)
3472{
3473 int i, ret = 0;
3474
3475 for (i = 0; i < len; i += 4, offset += 4) {
3476 u32 page_off, phy_addr, nvram_cmd;
3477 __be32 data;
3478
3479 memcpy(&data, buf + i, 4);
3480 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3481
3482 page_off = offset % tp->nvram_pagesize;
3483
3484 phy_addr = tg3_nvram_phys_addr(tp, offset);
3485
dbe9b92a
MC		 3486 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3487
3488 if (page_off == 0 || i == 0)
3489 nvram_cmd |= NVRAM_CMD_FIRST;
3490 if (page_off == (tp->nvram_pagesize - 4))
3491 nvram_cmd |= NVRAM_CMD_LAST;
3492
3493 if (i == (len - 4))
3494 nvram_cmd |= NVRAM_CMD_LAST;
3495
42278224
MC		 3496 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3497 !tg3_flag(tp, FLASH) ||
3498 !tg3_flag(tp, 57765_PLUS))
3499 tw32(NVRAM_ADDR, phy_addr);
3500
4153577a 3501 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3502 !tg3_flag(tp, 5755_PLUS) &&
3503 (tp->nvram_jedecnum == JEDEC_ST) &&
3504 (nvram_cmd & NVRAM_CMD_FIRST)) {
3505 u32 cmd;
3506
3507 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3508 ret = tg3_nvram_exec_cmd(tp, cmd);
3509 if (ret)
3510 break;
3511 }
3512 if (!tg3_flag(tp, FLASH)) {
3513 /* We always do complete word writes to eeprom. */
3514 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3515 }
3516
3517 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3518 if (ret)
3519 break;
3520 }
3521 return ret;
3522}
3523
3524/* offset and length are dword aligned */
3525static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3526{
3527 int ret;
3528
3529 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3530 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3531 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3532 udelay(40);
3533 }
3534
3535 if (!tg3_flag(tp, NVRAM)) {
3536 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3537 } else {
3538 u32 grc_mode;
3539
3540 ret = tg3_nvram_lock(tp);
3541 if (ret)
3542 return ret;
3543
3544 tg3_enable_nvram_access(tp);
3545 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3546 tw32(NVRAM_WRITE1, 0x406);
3547
3548 grc_mode = tr32(GRC_MODE);
3549 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3550
3551 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3552 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3553 buf);
3554 } else {
3555 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3556 buf);
3557 }
3558
3559 grc_mode = tr32(GRC_MODE);
3560 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3561
3562 tg3_disable_nvram_access(tp);
3563 tg3_nvram_unlock(tp);
3564 }
3565
3566 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3567 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3568 udelay(40);
3569 }
3570
3571 return ret;
3572}
3573
997b4f13
MC		 3574#define RX_CPU_SCRATCH_BASE 0x30000
3575#define RX_CPU_SCRATCH_SIZE 0x04000
3576#define TX_CPU_SCRATCH_BASE 0x34000
3577#define TX_CPU_SCRATCH_SIZE 0x04000
3578
3579/* tp->lock is held. */
837c45bb 3580static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3581{
3582 int i;
837c45bb 3583 const int iters = 10000;
997b4f13 3584
837c45bb
NS		 3585 for (i = 0; i < iters; i++) {
3586 tw32(cpu_base + CPU_STATE, 0xffffffff);
3587 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3588 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3589 break;
6d446ec3
GS		 3590 if (pci_channel_offline(tp->pdev))
3591 return -EBUSY;
837c45bb
NS		 3592 }
3593
3594 return (i == iters) ? -EBUSY : 0;
3595}
3596
3597/* tp->lock is held. */
3598static int tg3_rxcpu_pause(struct tg3 *tp)
3599{
3600 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3601
3602 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3603 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3604 udelay(10);
3605
3606 return rc;
3607}
3608
3609/* tp->lock is held. */
3610static int tg3_txcpu_pause(struct tg3 *tp)
3611{
3612 return tg3_pause_cpu(tp, TX_CPU_BASE);
3613}
3614
3615/* tp->lock is held. */
3616static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3617{
3618 tw32(cpu_base + CPU_STATE, 0xffffffff);
3619 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3620}
3621
3622/* tp->lock is held. */
3623static void tg3_rxcpu_resume(struct tg3 *tp)
3624{
3625 tg3_resume_cpu(tp, RX_CPU_BASE);
3626}
3627
3628/* tp->lock is held. */
3629static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3630{
3631 int rc;
3632
3633 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3634
4153577a 3635 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3636 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3637
3638 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3639 return 0;
3640 }
837c45bb
NS		 3641 if (cpu_base == RX_CPU_BASE) {
3642 rc = tg3_rxcpu_pause(tp);
997b4f13 3643 } else {
7e6c63f0
HM		 3644 /*
3645 * There is only an Rx CPU for the 5750 derivative in the
3646 * BCM4785.
3647 */
3648 if (tg3_flag(tp, IS_SSB_CORE))
3649 return 0;
3650
837c45bb 3651 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3652 }
3653
837c45bb 3654 if (rc) {
997b4f13 3655 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3656 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3657 return -ENODEV;
3658 }
3659
3660 /* Clear firmware's nvram arbitration. */
3661 if (tg3_flag(tp, NVRAM))
3662 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3663 return 0;
3664}
3665
31f11a95
NS		 3666static int tg3_fw_data_len(struct tg3 *tp,
3667 const struct tg3_firmware_hdr *fw_hdr)
3668{
3669 int fw_len;
3670
3671 /* Non fragmented firmware have one firmware header followed by a
3672 * contiguous chunk of data to be written. The length field in that
3673 * header is not the length of data to be written but the complete
3674 * length of the bss. The data length is determined based on
3675 * tp->fw->size minus headers.
3676 *
3677 * Fragmented firmware have a main header followed by multiple
3678 * fragments. Each fragment is identical to non fragmented firmware
3679 * with a firmware header followed by a contiguous chunk of data. In
3680 * the main header, the length field is unused and set to 0xffffffff.
3681 * In each fragment header the length is the entire size of that
3682 * fragment i.e. fragment data + header length. Data length is
3683 * therefore length field in the header minus TG3_FW_HDR_LEN.
3684 */
3685 if (tp->fw_len == 0xffffffff)
3686 fw_len = be32_to_cpu(fw_hdr->len);
3687 else
3688 fw_len = tp->fw->size;
3689
3690 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3691}
3692
997b4f13
MC		 3693/* tp->lock is held. */
3694static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3695 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3696 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3697{
c4dab506 3698 int err, i;
997b4f13 3699 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3700 int total_len = tp->fw->size;
997b4f13
MC		 3701
3702 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3703 netdev_err(tp->dev,
3704 "%s: Trying to load TX cpu firmware which is 5705\n",
3705 __func__);
3706 return -EINVAL;
3707 }
3708
c4dab506 3709 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3710 write_op = tg3_write_mem;
3711 else
3712 write_op = tg3_write_indirect_reg32;
3713
c4dab506
NS		 3714 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3715 /* It is possible that bootcode is still loading at this point.
3716 * Get the nvram lock first before halting the cpu.
3717 */
3718 int lock_err = tg3_nvram_lock(tp);
3719 err = tg3_halt_cpu(tp, cpu_base);
3720 if (!lock_err)
3721 tg3_nvram_unlock(tp);
3722 if (err)
3723 goto out;
997b4f13 3724
c4dab506
NS		 3725 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3726 write_op(tp, cpu_scratch_base + i, 0);
3727 tw32(cpu_base + CPU_STATE, 0xffffffff);
3728 tw32(cpu_base + CPU_MODE,
3729 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3730 } else {
3731 /* Subtract additional main header for fragmented firmware and
3732 * advance to the first fragment
3733 */
3734 total_len -= TG3_FW_HDR_LEN;
3735 fw_hdr++;
3736 }
77997ea3 3737
31f11a95
NS		 3738 do {
3739 u32 *fw_data = (u32 *)(fw_hdr + 1);
3740 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3741 write_op(tp, cpu_scratch_base +
3742 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3743 (i * sizeof(u32)),
3744 be32_to_cpu(fw_data[i]));
3745
3746 total_len -= be32_to_cpu(fw_hdr->len);
3747
3748 /* Advance to next fragment */
3749 fw_hdr = (struct tg3_firmware_hdr *)
3750 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3751 } while (total_len > 0);
997b4f13
MC		 3752
3753 err = 0;
3754
3755out:
3756 return err;
3757}
3758
f4bffb28
NS		 3759/* tp->lock is held. */
3760static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3761{
3762 int i;
3763 const int iters = 5;
3764
3765 tw32(cpu_base + CPU_STATE, 0xffffffff);
3766 tw32_f(cpu_base + CPU_PC, pc);
3767
3768 for (i = 0; i < iters; i++) {
3769 if (tr32(cpu_base + CPU_PC) == pc)
3770 break;
3771 tw32(cpu_base + CPU_STATE, 0xffffffff);
3772 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3773 tw32_f(cpu_base + CPU_PC, pc);
3774 udelay(1000);
3775 }
3776
3777 return (i == iters) ? -EBUSY : 0;
3778}
3779
997b4f13
MC		 3780/* tp->lock is held. */
3781static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3782{
77997ea3 3783 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3784 int err;
997b4f13 3785
77997ea3 3786 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3787
3788 /* Firmware blob starts with version numbers, followed by
3789 start address and length. We are setting complete length.
3790 length = end_address_of_bss - start_address_of_text.
3791 Remainder is the blob to be loaded contiguously
3792 from start address. */
3793
997b4f13
MC		 3794 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3795 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3796 fw_hdr);
997b4f13
MC		 3797 if (err)
3798 return err;
3799
3800 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3801 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3802 fw_hdr);
997b4f13
MC		 3803 if (err)
3804 return err;
3805
3806 /* Now startup only the RX cpu. */
77997ea3
NS		 3807 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3808 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3809 if (err) {
997b4f13
MC		 3810 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3811 "should be %08x\n", __func__,
77997ea3
NS		 3812 tr32(RX_CPU_BASE + CPU_PC),
3813 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3814 return -ENODEV;
3815 }
837c45bb
NS		 3816
3817 tg3_rxcpu_resume(tp);
997b4f13
MC		 3818
3819 return 0;
3820}
3821
c4dab506
NS		 3822static int tg3_validate_rxcpu_state(struct tg3 *tp)
3823{
3824 const int iters = 1000;
3825 int i;
3826 u32 val;
3827
3828 /* Wait for boot code to complete initialization and enter service
3829 * loop. It is then safe to download service patches
3830 */
3831 for (i = 0; i < iters; i++) {
3832 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3833 break;
3834
3835 udelay(10);
3836 }
3837
3838 if (i == iters) {
3839 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3840 return -EBUSY;
3841 }
3842
3843 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3844 if (val & 0xff) {
3845 netdev_warn(tp->dev,
3846 "Other patches exist. Not downloading EEE patch\n");
3847 return -EEXIST;
3848 }
3849
3850 return 0;
3851}
3852
3853/* tp->lock is held. */
3854static void tg3_load_57766_firmware(struct tg3 *tp)
3855{
3856 struct tg3_firmware_hdr *fw_hdr;
3857
3858 if (!tg3_flag(tp, NO_NVRAM))
3859 return;
3860
3861 if (tg3_validate_rxcpu_state(tp))
3862 return;
3863
3864 if (!tp->fw)
3865 return;
3866
3867 /* This firmware blob has a different format than older firmware
3868 * releases as given below. The main difference is we have fragmented
3869 * data to be written to non-contiguous locations.
3870 *
3871 * In the beginning we have a firmware header identical to other
3872 * firmware which consists of version, base addr and length. The length
3873 * here is unused and set to 0xffffffff.
3874 *
3875 * This is followed by a series of firmware fragments which are
3876 * individually identical to previous firmware. i.e. they have the
3877 * firmware header and followed by data for that fragment. The version
3878 * field of the individual fragment header is unused.
3879 */
3880
3881 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3882 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3883 return;
3884
3885 if (tg3_rxcpu_pause(tp))
3886 return;
3887
3888 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3889 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3890
3891 tg3_rxcpu_resume(tp);
3892}
3893
997b4f13
MC		 3894/* tp->lock is held. */
3895static int tg3_load_tso_firmware(struct tg3 *tp)
3896{
77997ea3 3897 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3898 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3899 int err;
997b4f13 3900
1caf13eb 3901 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3902 return 0;
3903
77997ea3 3904 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3905
3906 /* Firmware blob starts with version numbers, followed by
3907 start address and length. We are setting complete length.
3908 length = end_address_of_bss - start_address_of_text.
3909 Remainder is the blob to be loaded contiguously
3910 from start address. */
3911
997b4f13 3912 cpu_scratch_size = tp->fw_len;
997b4f13 3913
4153577a 3914 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3915 cpu_base = RX_CPU_BASE;
3916 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3917 } else {
3918 cpu_base = TX_CPU_BASE;
3919 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3920 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3921 }
3922
3923 err = tg3_load_firmware_cpu(tp, cpu_base,
3924 cpu_scratch_base, cpu_scratch_size,
77997ea3 3925 fw_hdr);
997b4f13
MC		 3926 if (err)
3927 return err;
3928
3929 /* Now startup the cpu. */
77997ea3
NS		 3930 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3931 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3932 if (err) {
997b4f13
MC		 3933 netdev_err(tp->dev,
3934 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3935 __func__, tr32(cpu_base + CPU_PC),
3936 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3937 return -ENODEV;
3938 }
837c45bb
NS		 3939
3940 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3941 return 0;
3942}
3943
3944
3f007891 3945/* tp->lock is held. */
953c96e0 3946static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891
MC		 3947{
3948 u32 addr_high, addr_low;
3949 int i;
3950
3951 addr_high = ((tp->dev->dev_addr[0] << 8) |
3952 tp->dev->dev_addr[1]);
3953 addr_low = ((tp->dev->dev_addr[2] << 24) |
3954 (tp->dev->dev_addr[3] << 16) |
3955 (tp->dev->dev_addr[4] << 8) |
3956 (tp->dev->dev_addr[5] << 0));
3957 for (i = 0; i < 4; i++) {
3958 if (i == 1 && skip_mac_1)
3959 continue;
3960 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3961 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3962 }
3963
4153577a
JP		 3964 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3965 tg3_asic_rev(tp) == ASIC_REV_5704) {
3f007891
MC		 3966 for (i = 0; i < 12; i++) {
3967 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3968 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3969 }
3970 }
3971
3972 addr_high = (tp->dev->dev_addr[0] +
3973 tp->dev->dev_addr[1] +
3974 tp->dev->dev_addr[2] +
3975 tp->dev->dev_addr[3] +
3976 tp->dev->dev_addr[4] +
3977 tp->dev->dev_addr[5]) &
3978 TX_BACKOFF_SEED_MASK;
3979 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3980}
3981
c866b7ea 3982static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 3983{
c866b7ea
RW		 3984 /*
3985 * Make sure register accesses (indirect or otherwise) will function
3986 * correctly.
1da177e4
LT		 3987 */
3988 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 3989 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3990}
1da177e4 3991
c866b7ea
RW		 3992static int tg3_power_up(struct tg3 *tp)
3993{
bed9829f 3994 int err;
8c6bda1a 3995
bed9829f 3996 tg3_enable_register_access(tp);
1da177e4 3997
bed9829f
MC		 3998 err = pci_set_power_state(tp->pdev, PCI_D0);
3999 if (!err) {
4000 /* Switch out of Vaux if it is a NIC */
4001 tg3_pwrsrc_switch_to_vmain(tp);
4002 } else {
4003 netdev_err(tp->dev, "Transition to D0 failed\n");
4004 }
1da177e4 4005
bed9829f 4006 return err;
c866b7ea 4007}
1da177e4 4008
953c96e0 4009static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4010
c866b7ea
RW		 4011static int tg3_power_down_prepare(struct tg3 *tp)
4012{
4013 u32 misc_host_ctrl;
4014 bool device_should_wake, do_low_power;
4015
4016 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4017
4018 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4019 if (tg3_flag(tp, CLKREQ_BUG))
4020 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4021 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4022
1da177e4
LT		 4023 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4024 tw32(TG3PCI_MISC_HOST_CTRL,
4025 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4026
c866b7ea 4027 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4028 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4029
63c3a66f 4030 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4031 do_low_power = false;
f07e9af3 4032 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4033 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4034 struct phy_device *phydev;
0a459aac 4035 u32 phyid, advertising;
b02fd9e3 4036
3f0e3ad7 4037 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 4038
80096068 4039 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4040
c6700ce2
MC		 4041 tp->link_config.speed = phydev->speed;
4042 tp->link_config.duplex = phydev->duplex;
4043 tp->link_config.autoneg = phydev->autoneg;
4044 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4045
4046 advertising = ADVERTISED_TP |
4047 ADVERTISED_Pause |
4048 ADVERTISED_Autoneg |
4049 ADVERTISED_10baseT_Half;
4050
63c3a66f
JP		 4051 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4052 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4053 advertising |=
4054 ADVERTISED_100baseT_Half |
4055 ADVERTISED_100baseT_Full |
4056 ADVERTISED_10baseT_Full;
4057 else
4058 advertising |= ADVERTISED_10baseT_Full;
4059 }
4060
4061 phydev->advertising = advertising;
4062
4063 phy_start_aneg(phydev);
0a459aac
MC		 4064
4065 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4066 if (phyid != PHY_ID_BCMAC131) {
4067 phyid &= PHY_BCM_OUI_MASK;
4068 if (phyid == PHY_BCM_OUI_1 ||
4069 phyid == PHY_BCM_OUI_2 ||
4070 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4071 do_low_power = true;
4072 }
b02fd9e3 4073 }
dd477003 4074 } else {
2023276e 4075 do_low_power = true;
0a459aac 4076
c6700ce2 4077 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4078 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4079
2855b9fe 4080 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4081 tg3_setup_phy(tp, false);
1da177e4
LT		 4082 }
4083
4153577a 4084 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4085 u32 val;
4086
4087 val = tr32(GRC_VCPU_EXT_CTRL);
4088 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4089 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4090 int i;
4091 u32 val;
4092
4093 for (i = 0; i < 200; i++) {
4094 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4095 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4096 break;
4097 msleep(1);
4098 }
4099 }
63c3a66f 4100 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4101 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4102 WOL_DRV_STATE_SHUTDOWN |
4103 WOL_DRV_WOL |
4104 WOL_SET_MAGIC_PKT);
6921d201 4105
05ac4cb7 4106 if (device_should_wake) {
1da177e4
LT		 4107 u32 mac_mode;
4108
f07e9af3 4109 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4110 if (do_low_power &&
4111 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4112 tg3_phy_auxctl_write(tp,
4113 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4114 MII_TG3_AUXCTL_PCTL_WOL_EN |
4115 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4116 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4117 udelay(40);
4118 }
1da177e4 4119
f07e9af3 4120 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4121 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4122 else if (tp->phy_flags &
4123 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4124 if (tp->link_config.active_speed == SPEED_1000)
4125 mac_mode = MAC_MODE_PORT_MODE_GMII;
4126 else
4127 mac_mode = MAC_MODE_PORT_MODE_MII;
4128 } else
3f7045c1 4129 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4130
e8f3f6ca 4131 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4132 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4133 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4134 SPEED_100 : SPEED_10;
4135 if (tg3_5700_link_polarity(tp, speed))
4136 mac_mode |= MAC_MODE_LINK_POLARITY;
4137 else
4138 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4139 }
1da177e4
LT		 4140 } else {
4141 mac_mode = MAC_MODE_PORT_MODE_TBI;
4142 }
4143
63c3a66f 4144 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4145 tw32(MAC_LED_CTRL, tp->led_ctrl);
4146
05ac4cb7 4147 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4148 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4149 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4150 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4151
63c3a66f 4152 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4153 mac_mode |= MAC_MODE_APE_TX_EN |
4154 MAC_MODE_APE_RX_EN |
4155 MAC_MODE_TDE_ENABLE;
3bda1258 4156
1da177e4
LT		 4157 tw32_f(MAC_MODE, mac_mode);
4158 udelay(100);
4159
4160 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4161 udelay(10);
4162 }
4163
63c3a66f 4164 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4165 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4166 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4167 u32 base_val;
4168
4169 base_val = tp->pci_clock_ctrl;
4170 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4171 CLOCK_CTRL_TXCLK_DISABLE);
4172
b401e9e2
MC		 4173 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4174 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4175 } else if (tg3_flag(tp, 5780_CLASS) ||
4176 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4177 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4178 /* do nothing */
63c3a66f 4179 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4180 u32 newbits1, newbits2;
4181
4153577a
JP		 4182 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4183 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4184 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE |
4186 CLOCK_CTRL_ALTCLK);
4187 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4188 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4189 newbits1 = CLOCK_CTRL_625_CORE;
4190 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4191 } else {
4192 newbits1 = CLOCK_CTRL_ALTCLK;
4193 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4194 }
4195
b401e9e2
MC		 4196 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4197 40);
1da177e4 4198
b401e9e2
MC		 4199 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4200 40);
1da177e4 4201
63c3a66f 4202 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4203 u32 newbits3;
4204
4153577a
JP		 4205 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4206 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4207 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4208 CLOCK_CTRL_TXCLK_DISABLE |
4209 CLOCK_CTRL_44MHZ_CORE);
4210 } else {
4211 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4212 }
4213
b401e9e2
MC		 4214 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4215 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4216 }
4217 }
4218
63c3a66f 4219 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4220 tg3_power_down_phy(tp, do_low_power);
6921d201 4221
cd0d7228 4222 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4223
4224 /* Workaround for unstable PLL clock */
7e6c63f0 4225 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4226 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4227 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4228 u32 val = tr32(0x7d00);
4229
4230 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4231 tw32(0x7d00, val);
63c3a66f 4232 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4233 int err;
4234
4235 err = tg3_nvram_lock(tp);
1da177e4 4236 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4237 if (!err)
4238 tg3_nvram_unlock(tp);
6921d201 4239 }
1da177e4
LT		 4240 }
4241
bbadf503
MC		 4242 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4243
2e460fc0
NS		 4244 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4245
c866b7ea
RW		 4246 return 0;
4247}
12dac075 4248
c866b7ea
RW		 4249static void tg3_power_down(struct tg3 *tp)
4250{
63c3a66f 4251 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4252 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4253}
4254
1da177e4
LT		 4255static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4256{
4257 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4258 case MII_TG3_AUX_STAT_10HALF:
4259 *speed = SPEED_10;
4260 *duplex = DUPLEX_HALF;
4261 break;
4262
4263 case MII_TG3_AUX_STAT_10FULL:
4264 *speed = SPEED_10;
4265 *duplex = DUPLEX_FULL;
4266 break;
4267
4268 case MII_TG3_AUX_STAT_100HALF:
4269 *speed = SPEED_100;
4270 *duplex = DUPLEX_HALF;
4271 break;
4272
4273 case MII_TG3_AUX_STAT_100FULL:
4274 *speed = SPEED_100;
4275 *duplex = DUPLEX_FULL;
4276 break;
4277
4278 case MII_TG3_AUX_STAT_1000HALF:
4279 *speed = SPEED_1000;
4280 *duplex = DUPLEX_HALF;
4281 break;
4282
4283 case MII_TG3_AUX_STAT_1000FULL:
4284 *speed = SPEED_1000;
4285 *duplex = DUPLEX_FULL;
4286 break;
4287
4288 default:
f07e9af3 4289 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4290 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4291 SPEED_10;
4292 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4293 DUPLEX_HALF;
4294 break;
4295 }
e740522e
MC		 4296 *speed = SPEED_UNKNOWN;
4297 *duplex = DUPLEX_UNKNOWN;
1da177e4 4298 break;
855e1111 4299 }
1da177e4
LT		 4300}
4301
42b64a45 4302static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4303{
42b64a45
MC		 4304 int err = 0;
4305 u32 val, new_adv;
1da177e4 4306
42b64a45 4307 new_adv = ADVERTISE_CSMA;
202ff1c2 4308 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4309 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4310
42b64a45
MC		 4311 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4312 if (err)
4313 goto done;
ba4d07a8 4314
4f272096
MC		 4315 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4316 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4317
4153577a
JP		 4318 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4319 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4320 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4321
4f272096
MC		 4322 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4323 if (err)
4324 goto done;
4325 }
1da177e4 4326
42b64a45
MC		 4327 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4328 goto done;
52b02d04 4329
42b64a45
MC		 4330 tw32(TG3_CPMU_EEE_MODE,
4331 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4332
daf3ec68 4333 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4334 if (!err) {
4335 u32 err2;
52b02d04 4336
b715ce94
MC		 4337 val = 0;
4338 /* Advertise 100-BaseTX EEE ability */
4339 if (advertise & ADVERTISED_100baseT_Full)
4340 val |= MDIO_AN_EEE_ADV_100TX;
4341 /* Advertise 1000-BaseT EEE ability */
4342 if (advertise & ADVERTISED_1000baseT_Full)
4343 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4344
4345 if (!tp->eee.eee_enabled) {
4346 val = 0;
4347 tp->eee.advertised = 0;
4348 } else {
4349 tp->eee.advertised = advertise &
4350 (ADVERTISED_100baseT_Full |
4351 ADVERTISED_1000baseT_Full);
4352 }
4353
b715ce94
MC		 4354 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4355 if (err)
4356 val = 0;
4357
4153577a 4358 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4359 case ASIC_REV_5717:
4360 case ASIC_REV_57765:
55086ad9 4361 case ASIC_REV_57766:
21a00ab2 4362 case ASIC_REV_5719:
b715ce94
MC		 4363 /* If we advertised any eee advertisements above... */
4364 if (val)
4365 val = MII_TG3_DSP_TAP26_ALNOKO |
4366 MII_TG3_DSP_TAP26_RMRXSTO |
4367 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4368 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4369 /* Fall through */
4370 case ASIC_REV_5720:
c65a17f4 4371 case ASIC_REV_5762:
be671947
MC		 4372 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4373 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4374 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4375 }
52b02d04 4376
daf3ec68 4377 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4378 if (!err)
4379 err = err2;
4380 }
4381
4382done:
4383 return err;
4384}
4385
4386static void tg3_phy_copper_begin(struct tg3 *tp)
4387{
d13ba512
MC		 4388 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4389 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4390 u32 adv, fc;
4391
942d1af0
NS		 4392 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4393 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4394 adv = ADVERTISED_10baseT_Half |
4395 ADVERTISED_10baseT_Full;
4396 if (tg3_flag(tp, WOL_SPEED_100MB))
4397 adv |= ADVERTISED_100baseT_Half |
4398 ADVERTISED_100baseT_Full;
942d1af0
NS		 4399 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
4400 adv |= ADVERTISED_1000baseT_Half |
4401 ADVERTISED_1000baseT_Full;
d13ba512
MC		 4402
4403 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4404 } else {
d13ba512
MC		 4405 adv = tp->link_config.advertising;
4406 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4407 adv &= ~(ADVERTISED_1000baseT_Half |
4408 ADVERTISED_1000baseT_Full);
4409
4410 fc = tp->link_config.flowctrl;
52b02d04 4411 }
52b02d04 4412
d13ba512 4413 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4414
942d1af0
NS		 4415 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4416 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4417 /* Normally during power down we want to autonegotiate
4418 * the lowest possible speed for WOL. However, to avoid
4419 * link flap, we leave it untouched.
4420 */
4421 return;
4422 }
4423
d13ba512
MC		 4424 tg3_writephy(tp, MII_BMCR,
4425 BMCR_ANENABLE | BMCR_ANRESTART);
4426 } else {
4427 int i;
1da177e4
LT		 4428 u32 bmcr, orig_bmcr;
4429
4430 tp->link_config.active_speed = tp->link_config.speed;
4431 tp->link_config.active_duplex = tp->link_config.duplex;
4432
7c6cdead
NS		 4433 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4434 /* With autoneg disabled, 5715 only links up when the
4435 * advertisement register has the configured speed
4436 * enabled.
4437 */
4438 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4439 }
4440
1da177e4
LT		 4441 bmcr = 0;
4442 switch (tp->link_config.speed) {
4443 default:
4444 case SPEED_10:
4445 break;
4446
4447 case SPEED_100:
4448 bmcr |= BMCR_SPEED100;
4449 break;
4450
4451 case SPEED_1000:
221c5637 4452 bmcr |= BMCR_SPEED1000;
1da177e4 4453 break;
855e1111 4454 }
1da177e4
LT		 4455
4456 if (tp->link_config.duplex == DUPLEX_FULL)
4457 bmcr |= BMCR_FULLDPLX;
4458
4459 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4460 (bmcr != orig_bmcr)) {
4461 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4462 for (i = 0; i < 1500; i++) {
4463 u32 tmp;
4464
4465 udelay(10);
4466 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4467 tg3_readphy(tp, MII_BMSR, &tmp))
4468 continue;
4469 if (!(tmp & BMSR_LSTATUS)) {
4470 udelay(40);
4471 break;
4472 }
4473 }
4474 tg3_writephy(tp, MII_BMCR, bmcr);
4475 udelay(40);
4476 }
1da177e4
LT		 4477 }
4478}
4479
fdad8de4
NS		 4480static int tg3_phy_pull_config(struct tg3 *tp)
4481{
4482 int err;
4483 u32 val;
4484
4485 err = tg3_readphy(tp, MII_BMCR, &val);
4486 if (err)
4487 goto done;
4488
4489 if (!(val & BMCR_ANENABLE)) {
4490 tp->link_config.autoneg = AUTONEG_DISABLE;
4491 tp->link_config.advertising = 0;
4492 tg3_flag_clear(tp, PAUSE_AUTONEG);
4493
4494 err = -EIO;
4495
4496 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4497 case 0:
4498 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4499 goto done;
4500
4501 tp->link_config.speed = SPEED_10;
4502 break;
4503 case BMCR_SPEED100:
4504 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4505 goto done;
4506
4507 tp->link_config.speed = SPEED_100;
4508 break;
4509 case BMCR_SPEED1000:
4510 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4511 tp->link_config.speed = SPEED_1000;
4512 break;
4513 }
4514 /* Fall through */
4515 default:
4516 goto done;
4517 }
4518
4519 if (val & BMCR_FULLDPLX)
4520 tp->link_config.duplex = DUPLEX_FULL;
4521 else
4522 tp->link_config.duplex = DUPLEX_HALF;
4523
4524 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4525
4526 err = 0;
4527 goto done;
4528 }
4529
4530 tp->link_config.autoneg = AUTONEG_ENABLE;
4531 tp->link_config.advertising = ADVERTISED_Autoneg;
4532 tg3_flag_set(tp, PAUSE_AUTONEG);
4533
4534 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4535 u32 adv;
4536
4537 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4538 if (err)
4539 goto done;
4540
4541 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4542 tp->link_config.advertising |= adv | ADVERTISED_TP;
4543
4544 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4545 } else {
4546 tp->link_config.advertising |= ADVERTISED_FIBRE;
4547 }
4548
4549 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4550 u32 adv;
4551
4552 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4553 err = tg3_readphy(tp, MII_CTRL1000, &val);
4554 if (err)
4555 goto done;
4556
4557 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4558 } else {
4559 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4560 if (err)
4561 goto done;
4562
4563 adv = tg3_decode_flowctrl_1000X(val);
4564 tp->link_config.flowctrl = adv;
4565
4566 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4567 adv = mii_adv_to_ethtool_adv_x(val);
4568 }
4569
4570 tp->link_config.advertising |= adv;
4571 }
4572
4573done:
4574 return err;
4575}
4576
1da177e4
LT		 4577static int tg3_init_5401phy_dsp(struct tg3 *tp)
4578{
4579 int err;
4580
4581 /* Turn off tap power management. */
4582 /* Set Extended packet length bit */
b4bd2929 4583 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4584
6ee7c0a0
MC		 4585 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4586 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4587 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4588 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4589 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4590
4591 udelay(40);
4592
4593 return err;
4594}
4595
ed1ff5c3
NS		 4596static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4597{
5b6c273a 4598 struct ethtool_eee eee;
ed1ff5c3
NS		 4599
4600 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4601 return true;
4602
5b6c273a 4603 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4604
5b6c273a
NS		 4605 if (tp->eee.eee_enabled) {
4606 if (tp->eee.advertised != eee.advertised ||
4607 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4608 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4609 return false;
4610 } else {
4611 /* EEE is disabled but we're advertising */
4612 if (eee.advertised)
4613 return false;
4614 }
ed1ff5c3
NS		 4615
4616 return true;
4617}
4618
e2bf73e7 4619static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4620{
e2bf73e7 4621 u32 advmsk, tgtadv, advertising;
3600d918 4622
e2bf73e7
MC		 4623 advertising = tp->link_config.advertising;
4624 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4625
e2bf73e7
MC		 4626 advmsk = ADVERTISE_ALL;
4627 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4628 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4629 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4630 }
1da177e4 4631
e2bf73e7
MC		 4632 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4633 return false;
4634
4635 if ((*lcladv & advmsk) != tgtadv)
4636 return false;
b99d2a57 4637
f07e9af3 4638 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4639 u32 tg3_ctrl;
4640
e2bf73e7 4641 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4642
221c5637 4643 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4644 return false;
1da177e4 4645
3198e07f 4646 if (tgtadv &&
4153577a
JP		 4647 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4648 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4649 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4650 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4651 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4652 } else {
4653 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4654 }
4655
e2bf73e7
MC		 4656 if (tg3_ctrl != tgtadv)
4657 return false;
ef167e27
MC		 4658 }
4659
e2bf73e7 4660 return true;
ef167e27
MC		 4661}
4662
859edb26
MC		 4663static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4664{
4665 u32 lpeth = 0;
4666
4667 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4668 u32 val;
4669
4670 if (tg3_readphy(tp, MII_STAT1000, &val))
4671 return false;
4672
4673 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4674 }
4675
4676 if (tg3_readphy(tp, MII_LPA, rmtadv))
4677 return false;
4678
4679 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4680 tp->link_config.rmt_adv = lpeth;
4681
4682 return true;
4683}
4684
953c96e0 4685static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4686{
4687 if (curr_link_up != tp->link_up) {
4688 if (curr_link_up) {
84421b99 4689 netif_carrier_on(tp->dev);
f4a46d1f 4690 } else {
84421b99 4691 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4692 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4693 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4694 }
4695
4696 tg3_link_report(tp);
4697 return true;
4698 }
4699
4700 return false;
4701}
4702
3310e248
MC		 4703static void tg3_clear_mac_status(struct tg3 *tp)
4704{
4705 tw32(MAC_EVENT, 0);
4706
4707 tw32_f(MAC_STATUS,
4708 MAC_STATUS_SYNC_CHANGED |
4709 MAC_STATUS_CFG_CHANGED |
4710 MAC_STATUS_MI_COMPLETION |
4711 MAC_STATUS_LNKSTATE_CHANGED);
4712 udelay(40);
4713}
4714
9e2ecbeb
NS		 4715static void tg3_setup_eee(struct tg3 *tp)
4716{
4717 u32 val;
4718
4719 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4720 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4721 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4722 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4723
4724 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4725
4726 tw32_f(TG3_CPMU_EEE_CTRL,
4727 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4728
4729 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4730 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4731 TG3_CPMU_EEEMD_LPI_IN_RX |
4732 TG3_CPMU_EEEMD_EEE_ENABLE;
4733
4734 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4735 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4736
4737 if (tg3_flag(tp, ENABLE_APE))
4738 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4739
4740 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4741
4742 tw32_f(TG3_CPMU_EEE_DBTMR1,
4743 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4744 (tp->eee.tx_lpi_timer & 0xffff));
4745
4746 tw32_f(TG3_CPMU_EEE_DBTMR2,
4747 TG3_CPMU_DBTMR2_APE_TX_2047US |
4748 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4749}
4750
953c96e0 4751static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4752{
953c96e0 4753 bool current_link_up;
f833c4c1 4754 u32 bmsr, val;
ef167e27 4755 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4756 u16 current_speed;
4757 u8 current_duplex;
4758 int i, err;
4759
3310e248 4760 tg3_clear_mac_status(tp);
1da177e4 4761
8ef21428
MC		 4762 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4763 tw32_f(MAC_MI_MODE,
4764 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4765 udelay(80);
4766 }
1da177e4 4767
b4bd2929 4768 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4769
4770 /* Some third-party PHYs need to be reset on link going
4771 * down.
4772 */
4153577a
JP		 4773 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4774 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4775 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4776 tp->link_up) {
1da177e4
LT		 4777 tg3_readphy(tp, MII_BMSR, &bmsr);
4778 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4779 !(bmsr & BMSR_LSTATUS))
953c96e0 4780 force_reset = true;
1da177e4
LT		 4781 }
4782 if (force_reset)
4783 tg3_phy_reset(tp);
4784
79eb6904 4785 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4786 tg3_readphy(tp, MII_BMSR, &bmsr);
4787 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4788 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4789 bmsr = 0;
4790
4791 if (!(bmsr & BMSR_LSTATUS)) {
4792 err = tg3_init_5401phy_dsp(tp);
4793 if (err)
4794 return err;
4795
4796 tg3_readphy(tp, MII_BMSR, &bmsr);
4797 for (i = 0; i < 1000; i++) {
4798 udelay(10);
4799 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4800 (bmsr & BMSR_LSTATUS)) {
4801 udelay(40);
4802 break;
4803 }
4804 }
4805
79eb6904
MC		 4806 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4807 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4808 !(bmsr & BMSR_LSTATUS) &&
4809 tp->link_config.active_speed == SPEED_1000) {
4810 err = tg3_phy_reset(tp);
4811 if (!err)
4812 err = tg3_init_5401phy_dsp(tp);
4813 if (err)
4814 return err;
4815 }
4816 }
4153577a
JP		 4817 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4818 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4819 /* 5701 {A0,B0} CRC bug workaround */
4820 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4821 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4822 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4823 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4824 }
4825
4826 /* Clear pending interrupts... */
f833c4c1
MC		 4827 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4828 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4829
f07e9af3 4830 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4831 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4832 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4833 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4834
4153577a
JP		 4835 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4836 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4837 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4838 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4839 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4840 else
4841 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4842 }
4843
953c96e0 4844 current_link_up = false;
e740522e
MC		 4845 current_speed = SPEED_UNKNOWN;
4846 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4847 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4848 tp->link_config.rmt_adv = 0;
1da177e4 4849
f07e9af3 4850 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4851 err = tg3_phy_auxctl_read(tp,
4852 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4853 &val);
4854 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4855 tg3_phy_auxctl_write(tp,
4856 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4857 val | (1 << 10));
1da177e4
LT		 4858 goto relink;
4859 }
4860 }
4861
4862 bmsr = 0;
4863 for (i = 0; i < 100; i++) {
4864 tg3_readphy(tp, MII_BMSR, &bmsr);
4865 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4866 (bmsr & BMSR_LSTATUS))
4867 break;
4868 udelay(40);
4869 }
4870
4871 if (bmsr & BMSR_LSTATUS) {
4872 u32 aux_stat, bmcr;
4873
4874 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4875 for (i = 0; i < 2000; i++) {
4876 udelay(10);
4877 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4878 aux_stat)
4879 break;
4880 }
4881
4882 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4883 &current_speed,
4884 &current_duplex);
4885
4886 bmcr = 0;
4887 for (i = 0; i < 200; i++) {
4888 tg3_readphy(tp, MII_BMCR, &bmcr);
4889 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4890 continue;
4891 if (bmcr && bmcr != 0x7fff)
4892 break;
4893 udelay(10);
4894 }
4895
ef167e27
MC		 4896 lcl_adv = 0;
4897 rmt_adv = 0;
1da177e4 4898
ef167e27
MC		 4899 tp->link_config.active_speed = current_speed;
4900 tp->link_config.active_duplex = current_duplex;
4901
4902 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4903 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4904
ef167e27 4905 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4906 eee_config_ok &&
e2bf73e7 4907 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4908 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4909 current_link_up = true;
ed1ff5c3
NS		 4910
4911 /* EEE settings changes take effect only after a phy
4912 * reset. If we have skipped a reset due to Link Flap
4913 * Avoidance being enabled, do it now.
4914 */
4915 if (!eee_config_ok &&
4916 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4917 !force_reset) {
4918 tg3_setup_eee(tp);
ed1ff5c3 4919 tg3_phy_reset(tp);
5b6c273a 4920 }
1da177e4
LT		 4921 } else {
4922 if (!(bmcr & BMCR_ANENABLE) &&
4923 tp->link_config.speed == current_speed &&
f0fcd7a9 4924 tp->link_config.duplex == current_duplex) {
953c96e0 4925 current_link_up = true;
1da177e4
LT		 4926 }
4927 }
4928
953c96e0 4929 if (current_link_up &&
e348c5e7
MC		 4930 tp->link_config.active_duplex == DUPLEX_FULL) {
4931 u32 reg, bit;
4932
4933 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4934 reg = MII_TG3_FET_GEN_STAT;
4935 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4936 } else {
4937 reg = MII_TG3_EXT_STAT;
4938 bit = MII_TG3_EXT_STAT_MDIX;
4939 }
4940
4941 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4942 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4943
ef167e27 4944 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4945 }
1da177e4
LT		 4946 }
4947
1da177e4 4948relink:
953c96e0 4949 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4950 tg3_phy_copper_begin(tp);
4951
7e6c63f0 4952 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4953 current_link_up = true;
7e6c63f0
HM		 4954 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4955 current_speed = SPEED_1000;
4956 current_duplex = DUPLEX_FULL;
4957 tp->link_config.active_speed = current_speed;
4958 tp->link_config.active_duplex = current_duplex;
4959 }
4960
f833c4c1 4961 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4962 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4963 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4964 current_link_up = true;
1da177e4
LT		 4965 }
4966
4967 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4968 if (current_link_up) {
1da177e4
LT		 4969 if (tp->link_config.active_speed == SPEED_100 ||
4970 tp->link_config.active_speed == SPEED_10)
4971 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4972 else
4973 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4974 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4975 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4976 else
1da177e4
LT		 4977 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4978
7e6c63f0
HM		 4979 /* In order for the 5750 core in BCM4785 chip to work properly
4980 * in RGMII mode, the Led Control Register must be set up.
4981 */
4982 if (tg3_flag(tp, RGMII_MODE)) {
4983 u32 led_ctrl = tr32(MAC_LED_CTRL);
4984 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
4985
4986 if (tp->link_config.active_speed == SPEED_10)
4987 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
4988 else if (tp->link_config.active_speed == SPEED_100)
4989 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4990 LED_CTRL_100MBPS_ON);
4991 else if (tp->link_config.active_speed == SPEED_1000)
4992 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4993 LED_CTRL_1000MBPS_ON);
4994
4995 tw32(MAC_LED_CTRL, led_ctrl);
4996 udelay(40);
4997 }
4998
1da177e4
LT		 4999 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5000 if (tp->link_config.active_duplex == DUPLEX_HALF)
5001 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5002
4153577a 5003 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 5004 if (current_link_up &&
e8f3f6ca 5005 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 5006 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5007 else
5008 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5009 }
5010
5011 /* ??? Without this setting Netgear GA302T PHY does not
5012 * ??? send/receive packets...
5013 */
79eb6904 5014 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5015 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5016 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5017 tw32_f(MAC_MI_MODE, tp->mi_mode);
5018 udelay(80);
5019 }
5020
5021 tw32_f(MAC_MODE, tp->mac_mode);
5022 udelay(40);
5023
52b02d04
MC		 5024 tg3_phy_eee_adjust(tp, current_link_up);
5025
63c3a66f 5026 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5027 /* Polled via timer. */
5028 tw32_f(MAC_EVENT, 0);
5029 } else {
5030 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5031 }
5032 udelay(40);
5033
4153577a 5034 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5035 current_link_up &&
1da177e4 5036 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5037 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5038 udelay(120);
5039 tw32_f(MAC_STATUS,
5040 (MAC_STATUS_SYNC_CHANGED |
5041 MAC_STATUS_CFG_CHANGED));
5042 udelay(40);
5043 tg3_write_mem(tp,
5044 NIC_SRAM_FIRMWARE_MBOX,
5045 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5046 }
5047
5e7dfd0f 5048 /* Prevent send BD corruption. */
63c3a66f 5049 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5050 if (tp->link_config.active_speed == SPEED_100 ||
5051 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5052 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5053 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5054 else
0f49bfbd
JL		 5055 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5056 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5057 }
5058
f4a46d1f 5059 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5060
5061 return 0;
5062}
5063
5064struct tg3_fiber_aneginfo {
5065 int state;
5066#define ANEG_STATE_UNKNOWN 0
5067#define ANEG_STATE_AN_ENABLE 1
5068#define ANEG_STATE_RESTART_INIT 2
5069#define ANEG_STATE_RESTART 3
5070#define ANEG_STATE_DISABLE_LINK_OK 4
5071#define ANEG_STATE_ABILITY_DETECT_INIT 5
5072#define ANEG_STATE_ABILITY_DETECT 6
5073#define ANEG_STATE_ACK_DETECT_INIT 7
5074#define ANEG_STATE_ACK_DETECT 8
5075#define ANEG_STATE_COMPLETE_ACK_INIT 9
5076#define ANEG_STATE_COMPLETE_ACK 10
5077#define ANEG_STATE_IDLE_DETECT_INIT 11
5078#define ANEG_STATE_IDLE_DETECT 12
5079#define ANEG_STATE_LINK_OK 13
5080#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5081#define ANEG_STATE_NEXT_PAGE_WAIT 15
5082
5083 u32 flags;
5084#define MR_AN_ENABLE 0x00000001
5085#define MR_RESTART_AN 0x00000002
5086#define MR_AN_COMPLETE 0x00000004
5087#define MR_PAGE_RX 0x00000008
5088#define MR_NP_LOADED 0x00000010
5089#define MR_TOGGLE_TX 0x00000020
5090#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5091#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5092#define MR_LP_ADV_SYM_PAUSE 0x00000100
5093#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5094#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5095#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5096#define MR_LP_ADV_NEXT_PAGE 0x00001000
5097#define MR_TOGGLE_RX 0x00002000
5098#define MR_NP_RX 0x00004000
5099
5100#define MR_LINK_OK 0x80000000
5101
5102 unsigned long link_time, cur_time;
5103
5104 u32 ability_match_cfg;
5105 int ability_match_count;
5106
5107 char ability_match, idle_match, ack_match;
5108
5109 u32 txconfig, rxconfig;
5110#define ANEG_CFG_NP 0x00000080
5111#define ANEG_CFG_ACK 0x00000040
5112#define ANEG_CFG_RF2 0x00000020
5113#define ANEG_CFG_RF1 0x00000010
5114#define ANEG_CFG_PS2 0x00000001
5115#define ANEG_CFG_PS1 0x00008000
5116#define ANEG_CFG_HD 0x00004000
5117#define ANEG_CFG_FD 0x00002000
5118#define ANEG_CFG_INVAL 0x00001f06
5119
5120};
5121#define ANEG_OK 0
5122#define ANEG_DONE 1
5123#define ANEG_TIMER_ENAB 2
5124#define ANEG_FAILED -1
5125
5126#define ANEG_STATE_SETTLE_TIME 10000
5127
5128static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5129 struct tg3_fiber_aneginfo *ap)
5130{
5be73b47 5131 u16 flowctrl;
1da177e4
LT		 5132 unsigned long delta;
5133 u32 rx_cfg_reg;
5134 int ret;
5135
5136 if (ap->state == ANEG_STATE_UNKNOWN) {
5137 ap->rxconfig = 0;
5138 ap->link_time = 0;
5139 ap->cur_time = 0;
5140 ap->ability_match_cfg = 0;
5141 ap->ability_match_count = 0;
5142 ap->ability_match = 0;
5143 ap->idle_match = 0;
5144 ap->ack_match = 0;
5145 }
5146 ap->cur_time++;
5147
5148 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5149 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5150
5151 if (rx_cfg_reg != ap->ability_match_cfg) {
5152 ap->ability_match_cfg = rx_cfg_reg;
5153 ap->ability_match = 0;
5154 ap->ability_match_count = 0;
5155 } else {
5156 if (++ap->ability_match_count > 1) {
5157 ap->ability_match = 1;
5158 ap->ability_match_cfg = rx_cfg_reg;
5159 }
5160 }
5161 if (rx_cfg_reg & ANEG_CFG_ACK)
5162 ap->ack_match = 1;
5163 else
5164 ap->ack_match = 0;
5165
5166 ap->idle_match = 0;
5167 } else {
5168 ap->idle_match = 1;
5169 ap->ability_match_cfg = 0;
5170 ap->ability_match_count = 0;
5171 ap->ability_match = 0;
5172 ap->ack_match = 0;
5173
5174 rx_cfg_reg = 0;
5175 }
5176
5177 ap->rxconfig = rx_cfg_reg;
5178 ret = ANEG_OK;
5179
33f401ae 5180 switch (ap->state) {
1da177e4
LT		 5181 case ANEG_STATE_UNKNOWN:
5182 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5183 ap->state = ANEG_STATE_AN_ENABLE;
5184
5185 /* fallthru */
5186 case ANEG_STATE_AN_ENABLE:
5187 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5188 if (ap->flags & MR_AN_ENABLE) {
5189 ap->link_time = 0;
5190 ap->cur_time = 0;
5191 ap->ability_match_cfg = 0;
5192 ap->ability_match_count = 0;
5193 ap->ability_match = 0;
5194 ap->idle_match = 0;
5195 ap->ack_match = 0;
5196
5197 ap->state = ANEG_STATE_RESTART_INIT;
5198 } else {
5199 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5200 }
5201 break;
5202
5203 case ANEG_STATE_RESTART_INIT:
5204 ap->link_time = ap->cur_time;
5205 ap->flags &= ~(MR_NP_LOADED);
5206 ap->txconfig = 0;
5207 tw32(MAC_TX_AUTO_NEG, 0);
5208 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5209 tw32_f(MAC_MODE, tp->mac_mode);
5210 udelay(40);
5211
5212 ret = ANEG_TIMER_ENAB;
5213 ap->state = ANEG_STATE_RESTART;
5214
5215 /* fallthru */
5216 case ANEG_STATE_RESTART:
5217 delta = ap->cur_time - ap->link_time;
859a5887 5218 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5219 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5220 else
1da177e4 5221 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5222 break;
5223
5224 case ANEG_STATE_DISABLE_LINK_OK:
5225 ret = ANEG_DONE;
5226 break;
5227
5228 case ANEG_STATE_ABILITY_DETECT_INIT:
5229 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5230 ap->txconfig = ANEG_CFG_FD;
5231 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5232 if (flowctrl & ADVERTISE_1000XPAUSE)
5233 ap->txconfig |= ANEG_CFG_PS1;
5234 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5235 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5236 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5237 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5238 tw32_f(MAC_MODE, tp->mac_mode);
5239 udelay(40);
5240
5241 ap->state = ANEG_STATE_ABILITY_DETECT;
5242 break;
5243
5244 case ANEG_STATE_ABILITY_DETECT:
859a5887 5245 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5246 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5247 break;
5248
5249 case ANEG_STATE_ACK_DETECT_INIT:
5250 ap->txconfig |= ANEG_CFG_ACK;
5251 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5252 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5253 tw32_f(MAC_MODE, tp->mac_mode);
5254 udelay(40);
5255
5256 ap->state = ANEG_STATE_ACK_DETECT;
5257
5258 /* fallthru */
5259 case ANEG_STATE_ACK_DETECT:
5260 if (ap->ack_match != 0) {
5261 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5262 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5263 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5264 } else {
5265 ap->state = ANEG_STATE_AN_ENABLE;
5266 }
5267 } else if (ap->ability_match != 0 &&
5268 ap->rxconfig == 0) {
5269 ap->state = ANEG_STATE_AN_ENABLE;
5270 }
5271 break;
5272
5273 case ANEG_STATE_COMPLETE_ACK_INIT:
5274 if (ap->rxconfig & ANEG_CFG_INVAL) {
5275 ret = ANEG_FAILED;
5276 break;
5277 }
5278 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5279 MR_LP_ADV_HALF_DUPLEX |
5280 MR_LP_ADV_SYM_PAUSE |
5281 MR_LP_ADV_ASYM_PAUSE |
5282 MR_LP_ADV_REMOTE_FAULT1 |
5283 MR_LP_ADV_REMOTE_FAULT2 |
5284 MR_LP_ADV_NEXT_PAGE |
5285 MR_TOGGLE_RX |
5286 MR_NP_RX);
5287 if (ap->rxconfig & ANEG_CFG_FD)
5288 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5289 if (ap->rxconfig & ANEG_CFG_HD)
5290 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5291 if (ap->rxconfig & ANEG_CFG_PS1)
5292 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5293 if (ap->rxconfig & ANEG_CFG_PS2)
5294 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5295 if (ap->rxconfig & ANEG_CFG_RF1)
5296 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5297 if (ap->rxconfig & ANEG_CFG_RF2)
5298 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5299 if (ap->rxconfig & ANEG_CFG_NP)
5300 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5301
5302 ap->link_time = ap->cur_time;
5303
5304 ap->flags ^= (MR_TOGGLE_TX);
5305 if (ap->rxconfig & 0x0008)
5306 ap->flags |= MR_TOGGLE_RX;
5307 if (ap->rxconfig & ANEG_CFG_NP)
5308 ap->flags |= MR_NP_RX;
5309 ap->flags |= MR_PAGE_RX;
5310
5311 ap->state = ANEG_STATE_COMPLETE_ACK;
5312 ret = ANEG_TIMER_ENAB;
5313 break;
5314
5315 case ANEG_STATE_COMPLETE_ACK:
5316 if (ap->ability_match != 0 &&
5317 ap->rxconfig == 0) {
5318 ap->state = ANEG_STATE_AN_ENABLE;
5319 break;
5320 }
5321 delta = ap->cur_time - ap->link_time;
5322 if (delta > ANEG_STATE_SETTLE_TIME) {
5323 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5324 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5325 } else {
5326 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5327 !(ap->flags & MR_NP_RX)) {
5328 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5329 } else {
5330 ret = ANEG_FAILED;
5331 }
5332 }
5333 }
5334 break;
5335
5336 case ANEG_STATE_IDLE_DETECT_INIT:
5337 ap->link_time = ap->cur_time;
5338 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5339 tw32_f(MAC_MODE, tp->mac_mode);
5340 udelay(40);
5341
5342 ap->state = ANEG_STATE_IDLE_DETECT;
5343 ret = ANEG_TIMER_ENAB;
5344 break;
5345
5346 case ANEG_STATE_IDLE_DETECT:
5347 if (ap->ability_match != 0 &&
5348 ap->rxconfig == 0) {
5349 ap->state = ANEG_STATE_AN_ENABLE;
5350 break;
5351 }
5352 delta = ap->cur_time - ap->link_time;
5353 if (delta > ANEG_STATE_SETTLE_TIME) {
5354 /* XXX another gem from the Broadcom driver :( */
5355 ap->state = ANEG_STATE_LINK_OK;
5356 }
5357 break;
5358
5359 case ANEG_STATE_LINK_OK:
5360 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5361 ret = ANEG_DONE;
5362 break;
5363
5364 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5365 /* ??? unimplemented */
5366 break;
5367
5368 case ANEG_STATE_NEXT_PAGE_WAIT:
5369 /* ??? unimplemented */
5370 break;
5371
5372 default:
5373 ret = ANEG_FAILED;
5374 break;
855e1111 5375 }
1da177e4
LT		 5376
5377 return ret;
5378}
5379
5be73b47 5380static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5381{
5382 int res = 0;
5383 struct tg3_fiber_aneginfo aninfo;
5384 int status = ANEG_FAILED;
5385 unsigned int tick;
5386 u32 tmp;
5387
5388 tw32_f(MAC_TX_AUTO_NEG, 0);
5389
5390 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5391 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5392 udelay(40);
5393
5394 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5395 udelay(40);
5396
5397 memset(&aninfo, 0, sizeof(aninfo));
5398 aninfo.flags |= MR_AN_ENABLE;
5399 aninfo.state = ANEG_STATE_UNKNOWN;
5400 aninfo.cur_time = 0;
5401 tick = 0;
5402 while (++tick < 195000) {
5403 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5404 if (status == ANEG_DONE || status == ANEG_FAILED)
5405 break;
5406
5407 udelay(1);
5408 }
5409
5410 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5411 tw32_f(MAC_MODE, tp->mac_mode);
5412 udelay(40);
5413
5be73b47
MC		 5414 *txflags = aninfo.txconfig;
5415 *rxflags = aninfo.flags;
1da177e4
LT		 5416
5417 if (status == ANEG_DONE &&
5418 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5419 MR_LP_ADV_FULL_DUPLEX)))
5420 res = 1;
5421
5422 return res;
5423}
5424
5425static void tg3_init_bcm8002(struct tg3 *tp)
5426{
5427 u32 mac_status = tr32(MAC_STATUS);
5428 int i;
5429
5430 /* Reset when initting first time or we have a link. */
63c3a66f 5431 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5432 !(mac_status & MAC_STATUS_PCS_SYNCED))
5433 return;
5434
5435 /* Set PLL lock range. */
5436 tg3_writephy(tp, 0x16, 0x8007);
5437
5438 /* SW reset */
5439 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5440
5441 /* Wait for reset to complete. */
5442 /* XXX schedule_timeout() ... */
5443 for (i = 0; i < 500; i++)
5444 udelay(10);
5445
5446 /* Config mode; select PMA/Ch 1 regs. */
5447 tg3_writephy(tp, 0x10, 0x8411);
5448
5449 /* Enable auto-lock and comdet, select txclk for tx. */
5450 tg3_writephy(tp, 0x11, 0x0a10);
5451
5452 tg3_writephy(tp, 0x18, 0x00a0);
5453 tg3_writephy(tp, 0x16, 0x41ff);
5454
5455 /* Assert and deassert POR. */
5456 tg3_writephy(tp, 0x13, 0x0400);
5457 udelay(40);
5458 tg3_writephy(tp, 0x13, 0x0000);
5459
5460 tg3_writephy(tp, 0x11, 0x0a50);
5461 udelay(40);
5462 tg3_writephy(tp, 0x11, 0x0a10);
5463
5464 /* Wait for signal to stabilize */
5465 /* XXX schedule_timeout() ... */
5466 for (i = 0; i < 15000; i++)
5467 udelay(10);
5468
5469 /* Deselect the channel register so we can read the PHYID
5470 * later.
5471 */
5472 tg3_writephy(tp, 0x10, 0x8011);
5473}
5474
953c96e0 5475static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5476{
82cd3d11 5477 u16 flowctrl;
953c96e0 5478 bool current_link_up;
1da177e4
LT		 5479 u32 sg_dig_ctrl, sg_dig_status;
5480 u32 serdes_cfg, expected_sg_dig_ctrl;
5481 int workaround, port_a;
1da177e4
LT		 5482
5483 serdes_cfg = 0;
5484 expected_sg_dig_ctrl = 0;
5485 workaround = 0;
5486 port_a = 1;
953c96e0 5487 current_link_up = false;
1da177e4 5488
4153577a
JP		 5489 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5490 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5491 workaround = 1;
5492 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5493 port_a = 0;
5494
5495 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5496 /* preserve bits 20-23 for voltage regulator */
5497 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5498 }
5499
5500 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5501
5502 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5503 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5504 if (workaround) {
5505 u32 val = serdes_cfg;
5506
5507 if (port_a)
5508 val |= 0xc010000;
5509 else
5510 val |= 0x4010000;
5511 tw32_f(MAC_SERDES_CFG, val);
5512 }
c98f6e3b
MC		 5513
5514 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5515 }
5516 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5517 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5518 current_link_up = true;
1da177e4
LT		 5519 }
5520 goto out;
5521 }
5522
5523 /* Want auto-negotiation. */
c98f6e3b 5524 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5525
82cd3d11
MC		 5526 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5527 if (flowctrl & ADVERTISE_1000XPAUSE)
5528 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5529 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5530 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5531
5532 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5533 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5534 tp->serdes_counter &&
5535 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5536 MAC_STATUS_RCVD_CFG)) ==
5537 MAC_STATUS_PCS_SYNCED)) {
5538 tp->serdes_counter--;
953c96e0 5539 current_link_up = true;
3d3ebe74
MC		 5540 goto out;
5541 }
5542restart_autoneg:
1da177e4
LT		 5543 if (workaround)
5544 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5545 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5546 udelay(5);
5547 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5548
3d3ebe74 5549 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5550 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5551 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5552 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5553 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5554 mac_status = tr32(MAC_STATUS);
5555
c98f6e3b 5556 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5557 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5558 u32 local_adv = 0, remote_adv = 0;
5559
5560 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5561 local_adv |= ADVERTISE_1000XPAUSE;
5562 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5563 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5564
c98f6e3b 5565 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5566 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5567 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5568 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5569
859edb26
MC		 5570 tp->link_config.rmt_adv =
5571 mii_adv_to_ethtool_adv_x(remote_adv);
5572
1da177e4 5573 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5574 current_link_up = true;
3d3ebe74 5575 tp->serdes_counter = 0;
f07e9af3 5576 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5577 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5578 if (tp->serdes_counter)
5579 tp->serdes_counter--;
1da177e4
LT		 5580 else {
5581 if (workaround) {
5582 u32 val = serdes_cfg;
5583
5584 if (port_a)
5585 val |= 0xc010000;
5586 else
5587 val |= 0x4010000;
5588
5589 tw32_f(MAC_SERDES_CFG, val);
5590 }
5591
c98f6e3b 5592 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5593 udelay(40);
5594
5595 /* Link parallel detection - link is up */
5596 /* only if we have PCS_SYNC and not */
5597 /* receiving config code words */
5598 mac_status = tr32(MAC_STATUS);
5599 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5600 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5601 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5602 current_link_up = true;
f07e9af3
MC		 5603 tp->phy_flags |=
5604 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5605 tp->serdes_counter =
5606 SERDES_PARALLEL_DET_TIMEOUT;
5607 } else
5608 goto restart_autoneg;
1da177e4
LT		 5609 }
5610 }
3d3ebe74
MC		 5611 } else {
5612 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5613 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5614 }
5615
5616out:
5617 return current_link_up;
5618}
5619
953c96e0 5620static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5621{
953c96e0 5622 bool current_link_up = false;
1da177e4 5623
5cf64b8a 5624 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5625 goto out;
1da177e4
LT		 5626
5627 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5628 u32 txflags, rxflags;
1da177e4 5629 int i;
6aa20a22 5630
5be73b47
MC		 5631 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5632 u32 local_adv = 0, remote_adv = 0;
1da177e4 5633
5be73b47
MC		 5634 if (txflags & ANEG_CFG_PS1)
5635 local_adv |= ADVERTISE_1000XPAUSE;
5636 if (txflags & ANEG_CFG_PS2)
5637 local_adv |= ADVERTISE_1000XPSE_ASYM;
5638
5639 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5640 remote_adv |= LPA_1000XPAUSE;
5641 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5642 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5643
859edb26
MC		 5644 tp->link_config.rmt_adv =
5645 mii_adv_to_ethtool_adv_x(remote_adv);
5646
1da177e4
LT		 5647 tg3_setup_flow_control(tp, local_adv, remote_adv);
5648
953c96e0 5649 current_link_up = true;
1da177e4
LT		 5650 }
5651 for (i = 0; i < 30; i++) {
5652 udelay(20);
5653 tw32_f(MAC_STATUS,
5654 (MAC_STATUS_SYNC_CHANGED |
5655 MAC_STATUS_CFG_CHANGED));
5656 udelay(40);
5657 if ((tr32(MAC_STATUS) &
5658 (MAC_STATUS_SYNC_CHANGED |
5659 MAC_STATUS_CFG_CHANGED)) == 0)
5660 break;
5661 }
5662
5663 mac_status = tr32(MAC_STATUS);
953c96e0 5664 if (!current_link_up &&
1da177e4
LT		 5665 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5666 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5667 current_link_up = true;
1da177e4 5668 } else {
5be73b47
MC		 5669 tg3_setup_flow_control(tp, 0, 0);
5670
1da177e4 5671 /* Forcing 1000FD link up. */
953c96e0 5672 current_link_up = true;
1da177e4
LT		 5673
5674 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5675 udelay(40);
e8f3f6ca
MC		 5676
5677 tw32_f(MAC_MODE, tp->mac_mode);
5678 udelay(40);
1da177e4
LT		 5679 }
5680
5681out:
5682 return current_link_up;
5683}
5684
953c96e0 5685static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5686{
5687 u32 orig_pause_cfg;
5688 u16 orig_active_speed;
5689 u8 orig_active_duplex;
5690 u32 mac_status;
953c96e0 5691 bool current_link_up;
1da177e4
LT		 5692 int i;
5693
8d018621 5694 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5695 orig_active_speed = tp->link_config.active_speed;
5696 orig_active_duplex = tp->link_config.active_duplex;
5697
63c3a66f 5698 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5699 tp->link_up &&
63c3a66f 5700 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5701 mac_status = tr32(MAC_STATUS);
5702 mac_status &= (MAC_STATUS_PCS_SYNCED |
5703 MAC_STATUS_SIGNAL_DET |
5704 MAC_STATUS_CFG_CHANGED |
5705 MAC_STATUS_RCVD_CFG);
5706 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5707 MAC_STATUS_SIGNAL_DET)) {
5708 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5709 MAC_STATUS_CFG_CHANGED));
5710 return 0;
5711 }
5712 }
5713
5714 tw32_f(MAC_TX_AUTO_NEG, 0);
5715
5716 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5717 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5718 tw32_f(MAC_MODE, tp->mac_mode);
5719 udelay(40);
5720
79eb6904 5721 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5722 tg3_init_bcm8002(tp);
5723
5724 /* Enable link change event even when serdes polling. */
5725 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5726 udelay(40);
5727
953c96e0 5728 current_link_up = false;
859edb26 5729 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5730 mac_status = tr32(MAC_STATUS);
5731
63c3a66f 5732 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5733 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5734 else
5735 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5736
898a56f8 5737 tp->napi[0].hw_status->status =
1da177e4 5738 (SD_STATUS_UPDATED |
898a56f8 5739 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5740
5741 for (i = 0; i < 100; i++) {
5742 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5743 MAC_STATUS_CFG_CHANGED));
5744 udelay(5);
5745 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5746 MAC_STATUS_CFG_CHANGED |
5747 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5748 break;
5749 }
5750
5751 mac_status = tr32(MAC_STATUS);
5752 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5753 current_link_up = false;
3d3ebe74
MC		 5754 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5755 tp->serdes_counter == 0) {
1da177e4
LT		 5756 tw32_f(MAC_MODE, (tp->mac_mode |
5757 MAC_MODE_SEND_CONFIGS));
5758 udelay(1);
5759 tw32_f(MAC_MODE, tp->mac_mode);
5760 }
5761 }
5762
953c96e0 5763 if (current_link_up) {
1da177e4
LT		 5764 tp->link_config.active_speed = SPEED_1000;
5765 tp->link_config.active_duplex = DUPLEX_FULL;
5766 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5767 LED_CTRL_LNKLED_OVERRIDE |
5768 LED_CTRL_1000MBPS_ON));
5769 } else {
e740522e
MC		 5770 tp->link_config.active_speed = SPEED_UNKNOWN;
5771 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5772 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5773 LED_CTRL_LNKLED_OVERRIDE |
5774 LED_CTRL_TRAFFIC_OVERRIDE));
5775 }
5776
f4a46d1f 5777 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5778 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5779 if (orig_pause_cfg != now_pause_cfg ||
5780 orig_active_speed != tp->link_config.active_speed ||
5781 orig_active_duplex != tp->link_config.active_duplex)
5782 tg3_link_report(tp);
5783 }
5784
5785 return 0;
5786}
5787
953c96e0 5788static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5789{
953c96e0 5790 int err = 0;
747e8f8b 5791 u32 bmsr, bmcr;
85730a63
MC		 5792 u16 current_speed = SPEED_UNKNOWN;
5793 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5794 bool current_link_up = false;
85730a63
MC		 5795 u32 local_adv, remote_adv, sgsr;
5796
5797 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5798 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5799 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5800 (sgsr & SERDES_TG3_SGMII_MODE)) {
5801
5802 if (force_reset)
5803 tg3_phy_reset(tp);
5804
5805 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5806
5807 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5808 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5809 } else {
953c96e0 5810 current_link_up = true;
85730a63
MC		 5811 if (sgsr & SERDES_TG3_SPEED_1000) {
5812 current_speed = SPEED_1000;
5813 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5814 } else if (sgsr & SERDES_TG3_SPEED_100) {
5815 current_speed = SPEED_100;
5816 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5817 } else {
5818 current_speed = SPEED_10;
5819 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5820 }
5821
5822 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5823 current_duplex = DUPLEX_FULL;
5824 else
5825 current_duplex = DUPLEX_HALF;
5826 }
5827
5828 tw32_f(MAC_MODE, tp->mac_mode);
5829 udelay(40);
5830
5831 tg3_clear_mac_status(tp);
5832
5833 goto fiber_setup_done;
5834 }
747e8f8b
MC		 5835
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5837 tw32_f(MAC_MODE, tp->mac_mode);
5838 udelay(40);
5839
3310e248 5840 tg3_clear_mac_status(tp);
747e8f8b
MC		 5841
5842 if (force_reset)
5843 tg3_phy_reset(tp);
5844
859edb26 5845 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5846
5847 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5848 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5849 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5850 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5851 bmsr |= BMSR_LSTATUS;
5852 else
5853 bmsr &= ~BMSR_LSTATUS;
5854 }
747e8f8b
MC		 5855
5856 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5857
5858 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5859 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5860 /* do nothing, just check for link up at the end */
5861 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5862 u32 adv, newadv;
747e8f8b
MC		 5863
5864 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5865 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5866 ADVERTISE_1000XPAUSE |
5867 ADVERTISE_1000XPSE_ASYM |
5868 ADVERTISE_SLCT);
747e8f8b 5869
28011cf1 5870 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5871 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5872
28011cf1
MC		 5873 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5874 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5875 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5876 tg3_writephy(tp, MII_BMCR, bmcr);
5877
5878 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5879 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5880 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5881
5882 return err;
5883 }
5884 } else {
5885 u32 new_bmcr;
5886
5887 bmcr &= ~BMCR_SPEED1000;
5888 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5889
5890 if (tp->link_config.duplex == DUPLEX_FULL)
5891 new_bmcr |= BMCR_FULLDPLX;
5892
5893 if (new_bmcr != bmcr) {
5894 /* BMCR_SPEED1000 is a reserved bit that needs
5895 * to be set on write.
5896 */
5897 new_bmcr |= BMCR_SPEED1000;
5898
5899 /* Force a linkdown */
f4a46d1f 5900 if (tp->link_up) {
747e8f8b
MC		 5901 u32 adv;
5902
5903 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5904 adv &= ~(ADVERTISE_1000XFULL |
5905 ADVERTISE_1000XHALF |
5906 ADVERTISE_SLCT);
5907 tg3_writephy(tp, MII_ADVERTISE, adv);
5908 tg3_writephy(tp, MII_BMCR, bmcr |
5909 BMCR_ANRESTART |
5910 BMCR_ANENABLE);
5911 udelay(10);
f4a46d1f 5912 tg3_carrier_off(tp);
747e8f8b
MC		 5913 }
5914 tg3_writephy(tp, MII_BMCR, new_bmcr);
5915 bmcr = new_bmcr;
5916 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5917 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5918 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5919 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5920 bmsr |= BMSR_LSTATUS;
5921 else
5922 bmsr &= ~BMSR_LSTATUS;
5923 }
f07e9af3 5924 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5925 }
5926 }
5927
5928 if (bmsr & BMSR_LSTATUS) {
5929 current_speed = SPEED_1000;
953c96e0 5930 current_link_up = true;
747e8f8b
MC		 5931 if (bmcr & BMCR_FULLDPLX)
5932 current_duplex = DUPLEX_FULL;
5933 else
5934 current_duplex = DUPLEX_HALF;
5935
ef167e27
MC		 5936 local_adv = 0;
5937 remote_adv = 0;
5938
747e8f8b 5939 if (bmcr & BMCR_ANENABLE) {
ef167e27 5940 u32 common;
747e8f8b
MC		 5941
5942 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5943 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5944 common = local_adv & remote_adv;
5945 if (common & (ADVERTISE_1000XHALF |
5946 ADVERTISE_1000XFULL)) {
5947 if (common & ADVERTISE_1000XFULL)
5948 current_duplex = DUPLEX_FULL;
5949 else
5950 current_duplex = DUPLEX_HALF;
859edb26
MC		 5951
5952 tp->link_config.rmt_adv =
5953 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5954 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5955 /* Link is up via parallel detect */
859a5887 5956 } else {
953c96e0 5957 current_link_up = false;
859a5887 5958 }
747e8f8b
MC		 5959 }
5960 }
5961
85730a63 5962fiber_setup_done:
953c96e0 5963 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5964 tg3_setup_flow_control(tp, local_adv, remote_adv);
5965
747e8f8b
MC		 5966 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5967 if (tp->link_config.active_duplex == DUPLEX_HALF)
5968 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5969
5970 tw32_f(MAC_MODE, tp->mac_mode);
5971 udelay(40);
5972
5973 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5974
5975 tp->link_config.active_speed = current_speed;
5976 tp->link_config.active_duplex = current_duplex;
5977
f4a46d1f 5978 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 5979 return err;
5980}
5981
5982static void tg3_serdes_parallel_detect(struct tg3 *tp)
5983{
3d3ebe74 5984 if (tp->serdes_counter) {
747e8f8b 5985 /* Give autoneg time to complete. */
3d3ebe74 5986 tp->serdes_counter--;
747e8f8b
MC		 5987 return;
5988 }
c6cdf436 5989
f4a46d1f 5990 if (!tp->link_up &&
747e8f8b
MC		 5991 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5992 u32 bmcr;
5993
5994 tg3_readphy(tp, MII_BMCR, &bmcr);
5995 if (bmcr & BMCR_ANENABLE) {
5996 u32 phy1, phy2;
5997
5998 /* Select shadow register 0x1f */
f08aa1a8
MC		 5999 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6000 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 6001
6002 /* Select expansion interrupt status register */
f08aa1a8
MC		 6003 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6004 MII_TG3_DSP_EXP1_INT_STAT);
6005 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6006 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6007
6008 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6009 /* We have signal detect and not receiving
6010 * config code words, link is up by parallel
6011 * detection.
6012 */
6013
6014 bmcr &= ~BMCR_ANENABLE;
6015 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6016 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6017 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6018 }
6019 }
f4a46d1f 6020 } else if (tp->link_up &&
859a5887 6021 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6022 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6023 u32 phy2;
6024
6025 /* Select expansion interrupt status register */
f08aa1a8
MC		 6026 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6027 MII_TG3_DSP_EXP1_INT_STAT);
6028 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6029 if (phy2 & 0x20) {
6030 u32 bmcr;
6031
6032 /* Config code words received, turn on autoneg. */
6033 tg3_readphy(tp, MII_BMCR, &bmcr);
6034 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6035
f07e9af3 6036 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6037
6038 }
6039 }
6040}
6041
953c96e0 6042static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6043{
f2096f94 6044 u32 val;
1da177e4
LT		 6045 int err;
6046
f07e9af3 6047 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6048 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6049 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6050 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6051 else
1da177e4 6052 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6053
4153577a 6054 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6055 u32 scale;
aa6c91fe
MC		 6056
6057 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6058 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6059 scale = 65;
6060 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6061 scale = 6;
6062 else
6063 scale = 12;
6064
6065 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6066 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6067 tw32(GRC_MISC_CFG, val);
6068 }
6069
f2096f94
MC		 6070 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6071 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6072 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6073 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6074 val |= tr32(MAC_TX_LENGTHS) &
6075 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6076 TX_LENGTHS_CNT_DWN_VAL_MSK);
6077
1da177e4
LT		 6078 if (tp->link_config.active_speed == SPEED_1000 &&
6079 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6080 tw32(MAC_TX_LENGTHS, val |
6081 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6082 else
f2096f94
MC		 6083 tw32(MAC_TX_LENGTHS, val |
6084 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6085
63c3a66f 6086 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6087 if (tp->link_up) {
1da177e4 6088 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6089 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6090 } else {
6091 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6092 }
6093 }
6094
63c3a66f 6095 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6096 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6097 if (!tp->link_up)
8ed5d97e
MC		 6098 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6099 tp->pwrmgmt_thresh;
6100 else
6101 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6102 tw32(PCIE_PWR_MGMT_THRESH, val);
6103 }
6104
1da177e4
LT		 6105 return err;
6106}
6107
7d41e49a
MC		 6108/* tp->lock must be held */
6109static u64 tg3_refclk_read(struct tg3 *tp)
6110{
6111 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6112 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6113}
6114
be947307
MC		 6115/* tp->lock must be held */
6116static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6117{
92e6457d
NS		 6118 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6119
6120 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6121 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6122 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6123 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6124}
6125
7d41e49a
MC		 6126static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6127static inline void tg3_full_unlock(struct tg3 *tp);
6128static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6129{
6130 struct tg3 *tp = netdev_priv(dev);
6131
6132 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6133 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6134 SOF_TIMESTAMPING_SOFTWARE;
6135
6136 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6137 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6138 SOF_TIMESTAMPING_RX_HARDWARE |
6139 SOF_TIMESTAMPING_RAW_HARDWARE;
6140 }
7d41e49a
MC		 6141
6142 if (tp->ptp_clock)
6143 info->phc_index = ptp_clock_index(tp->ptp_clock);
6144 else
6145 info->phc_index = -1;
6146
6147 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6148
6149 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6150 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6151 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6152 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6153 return 0;
6154}
6155
6156static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6157{
6158 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6159 bool neg_adj = false;
6160 u32 correction = 0;
6161
6162 if (ppb < 0) {
6163 neg_adj = true;
6164 ppb = -ppb;
6165 }
6166
6167 /* Frequency adjustment is performed using hardware with a 24 bit
6168 * accumulator and a programmable correction value. On each clk, the
6169 * correction value gets added to the accumulator and when it
6170 * overflows, the time counter is incremented/decremented.
6171 *
6172 * So conversion from ppb to correction value is
6173 * ppb * (1 << 24) / 1000000000
6174 */
6175 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6176 TG3_EAV_REF_CLK_CORRECT_MASK;
6177
6178 tg3_full_lock(tp, 0);
6179
6180 if (correction)
6181 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6182 TG3_EAV_REF_CLK_CORRECT_EN |
6183 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6184 else
6185 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6186
6187 tg3_full_unlock(tp);
6188
6189 return 0;
6190}
6191
6192static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6193{
6194 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6195
6196 tg3_full_lock(tp, 0);
6197 tp->ptp_adjust += delta;
6198 tg3_full_unlock(tp);
6199
6200 return 0;
6201}
6202
6203static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6204{
6205 u64 ns;
6206 u32 remainder;
6207 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6208
6209 tg3_full_lock(tp, 0);
6210 ns = tg3_refclk_read(tp);
6211 ns += tp->ptp_adjust;
6212 tg3_full_unlock(tp);
6213
6214 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6215 ts->tv_nsec = remainder;
6216
6217 return 0;
6218}
6219
6220static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6221 const struct timespec *ts)
6222{
6223 u64 ns;
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6225
6226 ns = timespec_to_ns(ts);
6227
6228 tg3_full_lock(tp, 0);
6229 tg3_refclk_write(tp, ns);
6230 tp->ptp_adjust = 0;
6231 tg3_full_unlock(tp);
6232
6233 return 0;
6234}
6235
6236static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6237 struct ptp_clock_request *rq, int on)
6238{
92e6457d
NS		 6239 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6240 u32 clock_ctl;
6241 int rval = 0;
6242
6243 switch (rq->type) {
6244 case PTP_CLK_REQ_PEROUT:
6245 if (rq->perout.index != 0)
6246 return -EINVAL;
6247
6248 tg3_full_lock(tp, 0);
6249 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6250 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6251
6252 if (on) {
6253 u64 nsec;
6254
6255 nsec = rq->perout.start.sec * 1000000000ULL +
6256 rq->perout.start.nsec;
6257
6258 if (rq->perout.period.sec || rq->perout.period.nsec) {
6259 netdev_warn(tp->dev,
6260 "Device supports only a one-shot timesync output, period must be 0\n");
6261 rval = -EINVAL;
6262 goto err_out;
6263 }
6264
6265 if (nsec & (1ULL << 63)) {
6266 netdev_warn(tp->dev,
6267 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6268 rval = -EINVAL;
6269 goto err_out;
6270 }
6271
6272 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6273 tw32(TG3_EAV_WATCHDOG0_MSB,
6274 TG3_EAV_WATCHDOG0_EN |
6275 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6276
6277 tw32(TG3_EAV_REF_CLCK_CTL,
6278 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6279 } else {
6280 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6281 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6282 }
6283
6284err_out:
6285 tg3_full_unlock(tp);
6286 return rval;
6287
6288 default:
6289 break;
6290 }
6291
7d41e49a
MC		 6292 return -EOPNOTSUPP;
6293}
6294
6295static const struct ptp_clock_info tg3_ptp_caps = {
6296 .owner = THIS_MODULE,
6297 .name = "tg3 clock",
6298 .max_adj = 250000000,
6299 .n_alarm = 0,
6300 .n_ext_ts = 0,
92e6457d 6301 .n_per_out = 1,
7d41e49a
MC		 6302 .pps = 0,
6303 .adjfreq = tg3_ptp_adjfreq,
6304 .adjtime = tg3_ptp_adjtime,
6305 .gettime = tg3_ptp_gettime,
6306 .settime = tg3_ptp_settime,
6307 .enable = tg3_ptp_enable,
6308};
6309
fb4ce8ad
MC		 6310static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6311 struct skb_shared_hwtstamps *timestamp)
6312{
6313 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6314 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6315 tp->ptp_adjust);
6316}
6317
be947307
MC		 6318/* tp->lock must be held */
6319static void tg3_ptp_init(struct tg3 *tp)
6320{
6321 if (!tg3_flag(tp, PTP_CAPABLE))
6322 return;
6323
6324 /* Initialize the hardware clock to the system time. */
6325 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6326 tp->ptp_adjust = 0;
7d41e49a 6327 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6328}
6329
6330/* tp->lock must be held */
6331static void tg3_ptp_resume(struct tg3 *tp)
6332{
6333 if (!tg3_flag(tp, PTP_CAPABLE))
6334 return;
6335
6336 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6337 tp->ptp_adjust = 0;
6338}
6339
6340static void tg3_ptp_fini(struct tg3 *tp)
6341{
6342 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6343 return;
6344
7d41e49a 6345 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6346 tp->ptp_clock = NULL;
6347 tp->ptp_adjust = 0;
6348}
6349
66cfd1bd
MC		 6350static inline int tg3_irq_sync(struct tg3 *tp)
6351{
6352 return tp->irq_sync;
6353}
6354
97bd8e49
MC		 6355static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6356{
6357 int i;
6358
6359 dst = (u32 *)((u8 *)dst + off);
6360 for (i = 0; i < len; i += sizeof(u32))
6361 *dst++ = tr32(off + i);
6362}
6363
6364static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6365{
6366 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6367 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6368 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6369 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6370 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6371 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6372 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6373 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6374 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6375 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6376 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6377 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6378 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6379 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6380 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6381 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6382 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6383 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6384 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6385
63c3a66f 6386 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6387 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6388
6389 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6390 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6391 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6392 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6393 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6394 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6395 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6396 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6397
63c3a66f 6398 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6399 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6400 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6401 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6402 }
6403
6404 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6405 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6406 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6407 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6408 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6409
63c3a66f 6410 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6411 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6412}
6413
6414static void tg3_dump_state(struct tg3 *tp)
6415{
6416 int i;
6417 u32 *regs;
6418
6419 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6420 if (!regs)
97bd8e49 6421 return;
97bd8e49 6422
63c3a66f 6423 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6424 /* Read up to but not including private PCI registers */
6425 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6426 regs[i / sizeof(u32)] = tr32(i);
6427 } else
6428 tg3_dump_legacy_regs(tp, regs);
6429
6430 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6431 if (!regs[i + 0] && !regs[i + 1] &&
6432 !regs[i + 2] && !regs[i + 3])
6433 continue;
6434
6435 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6436 i * 4,
6437 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6438 }
6439
6440 kfree(regs);
6441
6442 for (i = 0; i < tp->irq_cnt; i++) {
6443 struct tg3_napi *tnapi = &tp->napi[i];
6444
6445 /* SW status block */
6446 netdev_err(tp->dev,
6447 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6448 i,
6449 tnapi->hw_status->status,
6450 tnapi->hw_status->status_tag,
6451 tnapi->hw_status->rx_jumbo_consumer,
6452 tnapi->hw_status->rx_consumer,
6453 tnapi->hw_status->rx_mini_consumer,
6454 tnapi->hw_status->idx[0].rx_producer,
6455 tnapi->hw_status->idx[0].tx_consumer);
6456
6457 netdev_err(tp->dev,
6458 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6459 i,
6460 tnapi->last_tag, tnapi->last_irq_tag,
6461 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6462 tnapi->rx_rcb_ptr,
6463 tnapi->prodring.rx_std_prod_idx,
6464 tnapi->prodring.rx_std_cons_idx,
6465 tnapi->prodring.rx_jmb_prod_idx,
6466 tnapi->prodring.rx_jmb_cons_idx);
6467 }
6468}
6469
df3e6548
MC		 6470/* This is called whenever we suspect that the system chipset is re-
6471 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6472 * is bogus tx completions. We try to recover by setting the
6473 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6474 * in the workqueue.
6475 */
6476static void tg3_tx_recover(struct tg3 *tp)
6477{
63c3a66f 6478 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6479 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6480
5129c3a3
MC		 6481 netdev_warn(tp->dev,
6482 "The system may be re-ordering memory-mapped I/O "
6483 "cycles to the network device, attempting to recover. "
6484 "Please report the problem to the driver maintainer "
6485 "and include system chipset information.\n");
df3e6548 6486
63c3a66f 6487 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6488}
6489
f3f3f27e 6490static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6491{
f65aac16
MC		 6492 /* Tell compiler to fetch tx indices from memory. */
6493 barrier();
f3f3f27e
MC		 6494 return tnapi->tx_pending -
6495 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6496}
6497
1da177e4
LT		 6498/* Tigon3 never reports partial packet sends. So we do not
6499 * need special logic to handle SKBs that have not had all
6500 * of their frags sent yet, like SunGEM does.
6501 */
17375d25 6502static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6503{
17375d25 6504 struct tg3 *tp = tnapi->tp;
898a56f8 6505 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6506 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6507 struct netdev_queue *txq;
6508 int index = tnapi - tp->napi;
298376d3 6509 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6510
63c3a66f 6511 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6512 index--;
6513
6514 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6515
6516 while (sw_idx != hw_idx) {
df8944cf 6517 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6518 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6519 int i, tx_bug = 0;
6520
6521 if (unlikely(skb == NULL)) {
6522 tg3_tx_recover(tp);
6523 return;
6524 }
1da177e4 6525
fb4ce8ad
MC		 6526 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6527 struct skb_shared_hwtstamps timestamp;
6528 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6529 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6530
6531 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6532
6533 skb_tstamp_tx(skb, &timestamp);
6534 }
6535
f4188d8a 6536 pci_unmap_single(tp->pdev,
4e5e4f0d 6537 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6538 skb_headlen(skb),
6539 PCI_DMA_TODEVICE);
1da177e4
LT		 6540
6541 ri->skb = NULL;
6542
e01ee14d
MC		 6543 while (ri->fragmented) {
6544 ri->fragmented = false;
6545 sw_idx = NEXT_TX(sw_idx);
6546 ri = &tnapi->tx_buffers[sw_idx];
6547 }
6548
1da177e4
LT		 6549 sw_idx = NEXT_TX(sw_idx);
6550
6551 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6552 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6553 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6554 tx_bug = 1;
f4188d8a
AD		 6555
6556 pci_unmap_page(tp->pdev,
4e5e4f0d 6557 dma_unmap_addr(ri, mapping),
9e903e08 6558 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6559 PCI_DMA_TODEVICE);
e01ee14d
MC		 6560
6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6565 }
6566
1da177e4
LT		 6567 sw_idx = NEXT_TX(sw_idx);
6568 }
6569
298376d3
TH		 6570 pkts_compl++;
6571 bytes_compl += skb->len;
6572
f47c11ee 6573 dev_kfree_skb(skb);
df3e6548
MC		 6574
6575 if (unlikely(tx_bug)) {
6576 tg3_tx_recover(tp);
6577 return;
6578 }
1da177e4
LT		 6579 }
6580
5cb917bc 6581 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6582
f3f3f27e 6583 tnapi->tx_cons = sw_idx;
1da177e4 6584
1b2a7205
MC		 6585 /* Need to make the tx_cons update visible to tg3_start_xmit()
6586 * before checking for netif_queue_stopped(). Without the
6587 * memory barrier, there is a small possibility that tg3_start_xmit()
6588 * will miss it and cause the queue to be stopped forever.
6589 */
6590 smp_mb();
6591
fe5f5787 6592 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6593 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6594 __netif_tx_lock(txq, smp_processor_id());
6595 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6596 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6597 netif_tx_wake_queue(txq);
6598 __netif_tx_unlock(txq);
51b91468 6599 }
1da177e4
LT		 6600}
6601
8d4057a9
ED		 6602static void tg3_frag_free(bool is_frag, void *data)
6603{
6604 if (is_frag)
6605 put_page(virt_to_head_page(data));
6606 else
6607 kfree(data);
6608}
6609
9205fd9c 6610static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6611{
8d4057a9
ED		 6612 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6613 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6614
9205fd9c 6615 if (!ri->data)
2b2cdb65
MC		 6616 return;
6617
4e5e4f0d 6618 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6619 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6620 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6621 ri->data = NULL;
2b2cdb65
MC		 6622}
6623
8d4057a9 6624
1da177e4
LT		 6625/* Returns size of skb allocated or < 0 on error.
6626 *
6627 * We only need to fill in the address because the other members
6628 * of the RX descriptor are invariant, see tg3_init_rings.
6629 *
6630 * Note the purposeful assymetry of cpu vs. chip accesses. For
6631 * posting buffers we only dirty the first cache line of the RX
6632 * descriptor (containing the address). Whereas for the RX status
6633 * buffers the cpu only reads the last cacheline of the RX descriptor
6634 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6635 */
9205fd9c 6636static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6637 u32 opaque_key, u32 dest_idx_unmasked,
6638 unsigned int *frag_size)
1da177e4
LT		 6639{
6640 struct tg3_rx_buffer_desc *desc;
f94e290e 6641 struct ring_info *map;
9205fd9c 6642 u8 *data;
1da177e4 6643 dma_addr_t mapping;
9205fd9c 6644 int skb_size, data_size, dest_idx;
1da177e4 6645
1da177e4
LT		 6646 switch (opaque_key) {
6647 case RXD_OPAQUE_RING_STD:
2c49a44d 6648 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6649 desc = &tpr->rx_std[dest_idx];
6650 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6651 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6652 break;
6653
6654 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6655 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6656 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6657 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6658 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6659 break;
6660
6661 default:
6662 return -EINVAL;
855e1111 6663 }
1da177e4
LT		 6664
6665 /* Do not overwrite any of the map or rp information
6666 * until we are sure we can commit to a new buffer.
6667 *
6668 * Callers depend upon this behavior and assume that
6669 * we leave everything unchanged if we fail.
6670 */
9205fd9c
ED		 6671 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6672 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6673 if (skb_size <= PAGE_SIZE) {
6674 data = netdev_alloc_frag(skb_size);
6675 *frag_size = skb_size;
8d4057a9
ED		 6676 } else {
6677 data = kmalloc(skb_size, GFP_ATOMIC);
6678 *frag_size = 0;
6679 }
9205fd9c 6680 if (!data)
1da177e4
LT		 6681 return -ENOMEM;
6682
9205fd9c
ED		 6683 mapping = pci_map_single(tp->pdev,
6684 data + TG3_RX_OFFSET(tp),
6685 data_size,
1da177e4 6686 PCI_DMA_FROMDEVICE);
8d4057a9 6687 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6688 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6689 return -EIO;
6690 }
1da177e4 6691
9205fd9c 6692 map->data = data;
4e5e4f0d 6693 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6694
1da177e4
LT		 6695 desc->addr_hi = ((u64)mapping >> 32);
6696 desc->addr_lo = ((u64)mapping & 0xffffffff);
6697
9205fd9c 6698 return data_size;
1da177e4
LT		 6699}
6700
6701/* We only need to move over in the address because the other
6702 * members of the RX descriptor are invariant. See notes above
9205fd9c 6703 * tg3_alloc_rx_data for full details.
1da177e4 6704 */
a3896167
MC		 6705static void tg3_recycle_rx(struct tg3_napi *tnapi,
6706 struct tg3_rx_prodring_set *dpr,
6707 u32 opaque_key, int src_idx,
6708 u32 dest_idx_unmasked)
1da177e4 6709{
17375d25 6710 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6711 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6712 struct ring_info *src_map, *dest_map;
8fea32b9 6713 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6714 int dest_idx;
1da177e4
LT		 6715
6716 switch (opaque_key) {
6717 case RXD_OPAQUE_RING_STD:
2c49a44d 6718 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6719 dest_desc = &dpr->rx_std[dest_idx];
6720 dest_map = &dpr->rx_std_buffers[dest_idx];
6721 src_desc = &spr->rx_std[src_idx];
6722 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6723 break;
6724
6725 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6726 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6727 dest_desc = &dpr->rx_jmb[dest_idx].std;
6728 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6729 src_desc = &spr->rx_jmb[src_idx].std;
6730 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6731 break;
6732
6733 default:
6734 return;
855e1111 6735 }
1da177e4 6736
9205fd9c 6737 dest_map->data = src_map->data;
4e5e4f0d
FT		 6738 dma_unmap_addr_set(dest_map, mapping,
6739 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6740 dest_desc->addr_hi = src_desc->addr_hi;
6741 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6742
6743 /* Ensure that the update to the skb happens after the physical
6744 * addresses have been transferred to the new BD location.
6745 */
6746 smp_wmb();
6747
9205fd9c 6748 src_map->data = NULL;
1da177e4
LT		 6749}
6750
1da177e4
LT		 6751/* The RX ring scheme is composed of multiple rings which post fresh
6752 * buffers to the chip, and one special ring the chip uses to report
6753 * status back to the host.
6754 *
6755 * The special ring reports the status of received packets to the
6756 * host. The chip does not write into the original descriptor the
6757 * RX buffer was obtained from. The chip simply takes the original
6758 * descriptor as provided by the host, updates the status and length
6759 * field, then writes this into the next status ring entry.
6760 *
6761 * Each ring the host uses to post buffers to the chip is described
6762 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6763 * it is first placed into the on-chip ram. When the packet's length
6764 * is known, it walks down the TG3_BDINFO entries to select the ring.
6765 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6766 * which is within the range of the new packet's length is chosen.
6767 *
6768 * The "separate ring for rx status" scheme may sound queer, but it makes
6769 * sense from a cache coherency perspective. If only the host writes
6770 * to the buffer post rings, and only the chip writes to the rx status
6771 * rings, then cache lines never move beyond shared-modified state.
6772 * If both the host and chip were to write into the same ring, cache line
6773 * eviction could occur since both entities want it in an exclusive state.
6774 */
17375d25 6775static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6776{
17375d25 6777 struct tg3 *tp = tnapi->tp;
f92905de 6778 u32 work_mask, rx_std_posted = 0;
4361935a 6779 u32 std_prod_idx, jmb_prod_idx;
72334482 6780 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6781 u16 hw_idx;
1da177e4 6782 int received;
8fea32b9 6783 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6784
8d9d7cfc 6785 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6786 /*
6787 * We need to order the read of hw_idx and the read of
6788 * the opaque cookie.
6789 */
6790 rmb();
1da177e4
LT		 6791 work_mask = 0;
6792 received = 0;
4361935a
MC		 6793 std_prod_idx = tpr->rx_std_prod_idx;
6794 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6795 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6796 struct ring_info *ri;
72334482 6797 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6798 unsigned int len;
6799 struct sk_buff *skb;
6800 dma_addr_t dma_addr;
6801 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6802 u8 *data;
fb4ce8ad 6803 u64 tstamp = 0;
1da177e4
LT		 6804
6805 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6806 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6807 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6808 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6809 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6810 data = ri->data;
4361935a 6811 post_ptr = &std_prod_idx;
f92905de 6812 rx_std_posted++;
1da177e4 6813 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6814 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6815 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6816 data = ri->data;
4361935a 6817 post_ptr = &jmb_prod_idx;
21f581a5 6818 } else
1da177e4 6819 goto next_pkt_nopost;
1da177e4
LT		 6820
6821 work_mask |= opaque_key;
6822
6823 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6824 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6825 drop_it:
a3896167 6826 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6827 desc_idx, *post_ptr);
6828 drop_it_no_recycle:
6829 /* Other statistics kept track of by card. */
b0057c51 6830 tp->rx_dropped++;
1da177e4
LT		 6831 goto next_pkt;
6832 }
6833
9205fd9c 6834 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6835 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6836 ETH_FCS_LEN;
1da177e4 6837
fb4ce8ad
MC		 6838 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6839 RXD_FLAG_PTPSTAT_PTPV1 ||
6840 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6841 RXD_FLAG_PTPSTAT_PTPV2) {
6842 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6843 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6844 }
6845
d2757fc4 6846 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6847 int skb_size;
8d4057a9 6848 unsigned int frag_size;
1da177e4 6849
9205fd9c 6850 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6851 *post_ptr, &frag_size);
1da177e4
LT		 6852 if (skb_size < 0)
6853 goto drop_it;
6854
287be12e 6855 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6856 PCI_DMA_FROMDEVICE);
6857
8d4057a9 6858 skb = build_skb(data, frag_size);
9205fd9c 6859 if (!skb) {
8d4057a9 6860 tg3_frag_free(frag_size != 0, data);
9205fd9c
ED		 6861 goto drop_it_no_recycle;
6862 }
6863 skb_reserve(skb, TG3_RX_OFFSET(tp));
6864 /* Ensure that the update to the data happens
61e800cf
MC		 6865 * after the usage of the old DMA mapping.
6866 */
6867 smp_wmb();
6868
9205fd9c 6869 ri->data = NULL;
61e800cf 6870
1da177e4 6871 } else {
a3896167 6872 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6873 desc_idx, *post_ptr);
6874
9205fd9c
ED		 6875 skb = netdev_alloc_skb(tp->dev,
6876 len + TG3_RAW_IP_ALIGN);
6877 if (skb == NULL)
1da177e4
LT		 6878 goto drop_it_no_recycle;
6879
9205fd9c 6880 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6881 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6882 memcpy(skb->data,
6883 data + TG3_RX_OFFSET(tp),
6884 len);
1da177e4 6885 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6886 }
6887
9205fd9c 6888 skb_put(skb, len);
fb4ce8ad
MC		 6889 if (tstamp)
6890 tg3_hwclock_to_timestamp(tp, tstamp,
6891 skb_hwtstamps(skb));
6892
dc668910 6893 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6894 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6895 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6896 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6897 skb->ip_summed = CHECKSUM_UNNECESSARY;
6898 else
bc8acf2c 6899 skb_checksum_none_assert(skb);
1da177e4
LT		 6900
6901 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6902
6903 if (len > (tp->dev->mtu + ETH_HLEN) &&
6904 skb->protocol != htons(ETH_P_8021Q)) {
6905 dev_kfree_skb(skb);
b0057c51 6906 goto drop_it_no_recycle;
f7b493e0
MC		 6907 }
6908
9dc7a113 6909 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6910 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6911 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6912 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6913
bf933c80 6914 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6915
1da177e4
LT		 6916 received++;
6917 budget--;
6918
6919next_pkt:
6920 (*post_ptr)++;
f92905de
MC		 6921
6922 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6923 tpr->rx_std_prod_idx = std_prod_idx &
6924 tp->rx_std_ring_mask;
86cfe4ff
MC		 6925 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6926 tpr->rx_std_prod_idx);
f92905de
MC		 6927 work_mask &= ~RXD_OPAQUE_RING_STD;
6928 rx_std_posted = 0;
6929 }
1da177e4 6930next_pkt_nopost:
483ba50b 6931 sw_idx++;
7cb32cf2 6932 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6933
6934 /* Refresh hw_idx to see if there is new work */
6935 if (sw_idx == hw_idx) {
8d9d7cfc 6936 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6937 rmb();
6938 }
1da177e4
LT		 6939 }
6940
6941 /* ACK the status ring. */
72334482
MC		 6942 tnapi->rx_rcb_ptr = sw_idx;
6943 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6944
6945 /* Refill RX ring(s). */
63c3a66f 6946 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6947 /* Sync BD data before updating mailbox */
6948 wmb();
6949
b196c7e4 6950 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6951 tpr->rx_std_prod_idx = std_prod_idx &
6952 tp->rx_std_ring_mask;
b196c7e4
MC		 6953 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6954 tpr->rx_std_prod_idx);
6955 }
6956 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6957 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6958 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6959 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6960 tpr->rx_jmb_prod_idx);
6961 }
6962 mmiowb();
6963 } else if (work_mask) {
6964 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6965 * updated before the producer indices can be updated.
6966 */
6967 smp_wmb();
6968
2c49a44d
MC		 6969 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6970 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6971
7ae52890
MC		 6972 if (tnapi != &tp->napi[1]) {
6973 tp->rx_refill = true;
e4af1af9 6974 napi_schedule(&tp->napi[1].napi);
7ae52890 6975 }
1da177e4 6976 }
1da177e4
LT		 6977
6978 return received;
6979}
6980
35f2d7d0 6981static void tg3_poll_link(struct tg3 *tp)
1da177e4 6982{
1da177e4 6983 /* handle link change and other phy events */
63c3a66f 6984 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 6985 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6986
1da177e4
LT		 6987 if (sblk->status & SD_STATUS_LINK_CHG) {
6988 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 6989 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 6990 spin_lock(&tp->lock);
63c3a66f 6991 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 6992 tw32_f(MAC_STATUS,
6993 (MAC_STATUS_SYNC_CHANGED |
6994 MAC_STATUS_CFG_CHANGED |
6995 MAC_STATUS_MI_COMPLETION |
6996 MAC_STATUS_LNKSTATE_CHANGED));
6997 udelay(40);
6998 } else
953c96e0 6999 tg3_setup_phy(tp, false);
f47c11ee 7000 spin_unlock(&tp->lock);
1da177e4
LT		 7001 }
7002 }
35f2d7d0
MC		 7003}
7004
f89f38b8
MC		 7005static int tg3_rx_prodring_xfer(struct tg3 *tp,
7006 struct tg3_rx_prodring_set *dpr,
7007 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7008{
7009 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7010 int i, err = 0;
b196c7e4
MC		 7011
7012 while (1) {
7013 src_prod_idx = spr->rx_std_prod_idx;
7014
7015 /* Make sure updates to the rx_std_buffers[] entries and the
7016 * standard producer index are seen in the correct order.
7017 */
7018 smp_rmb();
7019
7020 if (spr->rx_std_cons_idx == src_prod_idx)
7021 break;
7022
7023 if (spr->rx_std_cons_idx < src_prod_idx)
7024 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7025 else
2c49a44d
MC		 7026 cpycnt = tp->rx_std_ring_mask + 1 -
7027 spr->rx_std_cons_idx;
b196c7e4 7028
2c49a44d
MC		 7029 cpycnt = min(cpycnt,
7030 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7031
7032 si = spr->rx_std_cons_idx;
7033 di = dpr->rx_std_prod_idx;
7034
e92967bf 7035 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7036 if (dpr->rx_std_buffers[i].data) {
e92967bf 7037 cpycnt = i - di;
f89f38b8 7038 err = -ENOSPC;
e92967bf
MC		 7039 break;
7040 }
7041 }
7042
7043 if (!cpycnt)
7044 break;
7045
7046 /* Ensure that updates to the rx_std_buffers ring and the
7047 * shadowed hardware producer ring from tg3_recycle_skb() are
7048 * ordered correctly WRT the skb check above.
7049 */
7050 smp_rmb();
7051
b196c7e4
MC		 7052 memcpy(&dpr->rx_std_buffers[di],
7053 &spr->rx_std_buffers[si],
7054 cpycnt * sizeof(struct ring_info));
7055
7056 for (i = 0; i < cpycnt; i++, di++, si++) {
7057 struct tg3_rx_buffer_desc *sbd, *dbd;
7058 sbd = &spr->rx_std[si];
7059 dbd = &dpr->rx_std[di];
7060 dbd->addr_hi = sbd->addr_hi;
7061 dbd->addr_lo = sbd->addr_lo;
7062 }
7063
2c49a44d
MC		 7064 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7065 tp->rx_std_ring_mask;
7066 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7067 tp->rx_std_ring_mask;
b196c7e4
MC		 7068 }
7069
7070 while (1) {
7071 src_prod_idx = spr->rx_jmb_prod_idx;
7072
7073 /* Make sure updates to the rx_jmb_buffers[] entries and
7074 * the jumbo producer index are seen in the correct order.
7075 */
7076 smp_rmb();
7077
7078 if (spr->rx_jmb_cons_idx == src_prod_idx)
7079 break;
7080
7081 if (spr->rx_jmb_cons_idx < src_prod_idx)
7082 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7083 else
2c49a44d
MC		 7084 cpycnt = tp->rx_jmb_ring_mask + 1 -
7085 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7086
7087 cpycnt = min(cpycnt,
2c49a44d 7088 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7089
7090 si = spr->rx_jmb_cons_idx;
7091 di = dpr->rx_jmb_prod_idx;
7092
e92967bf 7093 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7094 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7095 cpycnt = i - di;
f89f38b8 7096 err = -ENOSPC;
e92967bf
MC		 7097 break;
7098 }
7099 }
7100
7101 if (!cpycnt)
7102 break;
7103
7104 /* Ensure that updates to the rx_jmb_buffers ring and the
7105 * shadowed hardware producer ring from tg3_recycle_skb() are
7106 * ordered correctly WRT the skb check above.
7107 */
7108 smp_rmb();
7109
b196c7e4
MC		 7110 memcpy(&dpr->rx_jmb_buffers[di],
7111 &spr->rx_jmb_buffers[si],
7112 cpycnt * sizeof(struct ring_info));
7113
7114 for (i = 0; i < cpycnt; i++, di++, si++) {
7115 struct tg3_rx_buffer_desc *sbd, *dbd;
7116 sbd = &spr->rx_jmb[si].std;
7117 dbd = &dpr->rx_jmb[di].std;
7118 dbd->addr_hi = sbd->addr_hi;
7119 dbd->addr_lo = sbd->addr_lo;
7120 }
7121
2c49a44d
MC		 7122 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7123 tp->rx_jmb_ring_mask;
7124 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7125 tp->rx_jmb_ring_mask;
b196c7e4 7126 }
f89f38b8
MC		 7127
7128 return err;
b196c7e4
MC		 7129}
7130
35f2d7d0
MC		 7131static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7132{
7133 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7134
7135 /* run TX completion thread */
f3f3f27e 7136 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7137 tg3_tx(tnapi);
63c3a66f 7138 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7139 return work_done;
1da177e4
LT		 7140 }
7141
f891ea16
MC		 7142 if (!tnapi->rx_rcb_prod_idx)
7143 return work_done;
7144
1da177e4
LT		 7145 /* run RX thread, within the bounds set by NAPI.
7146 * All RX "locking" is done by ensuring outside
bea3348e 7147 * code synchronizes with tg3->napi.poll()
1da177e4 7148 */
8d9d7cfc 7149 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7150 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7151
63c3a66f 7152 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7153 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7154 int i, err = 0;
e4af1af9
MC		 7155 u32 std_prod_idx = dpr->rx_std_prod_idx;
7156 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7157
7ae52890 7158 tp->rx_refill = false;
9102426a 7159 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7160 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7161 &tp->napi[i].prodring);
b196c7e4
MC		 7162
7163 wmb();
7164
e4af1af9
MC		 7165 if (std_prod_idx != dpr->rx_std_prod_idx)
7166 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7167 dpr->rx_std_prod_idx);
b196c7e4 7168
e4af1af9
MC		 7169 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7170 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7171 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7172
7173 mmiowb();
f89f38b8
MC		 7174
7175 if (err)
7176 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7177 }
7178
6f535763
DM		 7179 return work_done;
7180}
7181
db219973
MC		 7182static inline void tg3_reset_task_schedule(struct tg3 *tp)
7183{
7184 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7185 schedule_work(&tp->reset_task);
7186}
7187
7188static inline void tg3_reset_task_cancel(struct tg3 *tp)
7189{
7190 cancel_work_sync(&tp->reset_task);
7191 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7192 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7193}
7194
35f2d7d0
MC		 7195static int tg3_poll_msix(struct napi_struct *napi, int budget)
7196{
7197 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7198 struct tg3 *tp = tnapi->tp;
7199 int work_done = 0;
7200 struct tg3_hw_status *sblk = tnapi->hw_status;
7201
7202 while (1) {
7203 work_done = tg3_poll_work(tnapi, work_done, budget);
7204
63c3a66f 7205 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7206 goto tx_recovery;
7207
7208 if (unlikely(work_done >= budget))
7209 break;
7210
c6cdf436 7211 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7212 * to tell the hw how much work has been processed,
7213 * so we must read it before checking for more work.
7214 */
7215 tnapi->last_tag = sblk->status_tag;
7216 tnapi->last_irq_tag = tnapi->last_tag;
7217 rmb();
7218
7219 /* check for RX/TX work to do */
6d40db7b
MC		 7220 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7221 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7222
7223 /* This test here is not race free, but will reduce
7224 * the number of interrupts by looping again.
7225 */
7226 if (tnapi == &tp->napi[1] && tp->rx_refill)
7227 continue;
7228
35f2d7d0
MC		 7229 napi_complete(napi);
7230 /* Reenable interrupts. */
7231 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7232
7233 /* This test here is synchronized by napi_schedule()
7234 * and napi_complete() to close the race condition.
7235 */
7236 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7237 tw32(HOSTCC_MODE, tp->coalesce_mode |
7238 HOSTCC_MODE_ENABLE |
7239 tnapi->coal_now);
7240 }
35f2d7d0
MC		 7241 mmiowb();
7242 break;
7243 }
7244 }
7245
7246 return work_done;
7247
7248tx_recovery:
7249 /* work_done is guaranteed to be less than budget. */
7250 napi_complete(napi);
db219973 7251 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7252 return work_done;
7253}
7254
e64de4e6
MC		 7255static void tg3_process_error(struct tg3 *tp)
7256{
7257 u32 val;
7258 bool real_error = false;
7259
63c3a66f 7260 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7261 return;
7262
7263 /* Check Flow Attention register */
7264 val = tr32(HOSTCC_FLOW_ATTN);
7265 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7266 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7267 real_error = true;
7268 }
7269
7270 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7271 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7272 real_error = true;
7273 }
7274
7275 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7276 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7277 real_error = true;
7278 }
7279
7280 if (!real_error)
7281 return;
7282
7283 tg3_dump_state(tp);
7284
63c3a66f 7285 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7286 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7287}
7288
6f535763
DM		 7289static int tg3_poll(struct napi_struct *napi, int budget)
7290{
8ef0442f
MC		 7291 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7292 struct tg3 *tp = tnapi->tp;
6f535763 7293 int work_done = 0;
898a56f8 7294 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7295
7296 while (1) {
e64de4e6
MC		 7297 if (sblk->status & SD_STATUS_ERROR)
7298 tg3_process_error(tp);
7299
35f2d7d0
MC		 7300 tg3_poll_link(tp);
7301
17375d25 7302 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7303
63c3a66f 7304 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7305 goto tx_recovery;
7306
7307 if (unlikely(work_done >= budget))
7308 break;
7309
63c3a66f 7310 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7311 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7312 * to tell the hw how much work has been processed,
7313 * so we must read it before checking for more work.
7314 */
898a56f8
MC		 7315 tnapi->last_tag = sblk->status_tag;
7316 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7317 rmb();
7318 } else
7319 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7320
17375d25 7321 if (likely(!tg3_has_work(tnapi))) {
288379f0 7322 napi_complete(napi);
17375d25 7323 tg3_int_reenable(tnapi);
6f535763
DM		 7324 break;
7325 }
1da177e4
LT		 7326 }
7327
bea3348e 7328 return work_done;
6f535763
DM		 7329
7330tx_recovery:
4fd7ab59 7331 /* work_done is guaranteed to be less than budget. */
288379f0 7332 napi_complete(napi);
db219973 7333 tg3_reset_task_schedule(tp);
4fd7ab59 7334 return work_done;
1da177e4
LT		 7335}
7336
66cfd1bd
MC		 7337static void tg3_napi_disable(struct tg3 *tp)
7338{
7339 int i;
7340
7341 for (i = tp->irq_cnt - 1; i >= 0; i--)
7342 napi_disable(&tp->napi[i].napi);
7343}
7344
7345static void tg3_napi_enable(struct tg3 *tp)
7346{
7347 int i;
7348
7349 for (i = 0; i < tp->irq_cnt; i++)
7350 napi_enable(&tp->napi[i].napi);
7351}
7352
7353static void tg3_napi_init(struct tg3 *tp)
7354{
7355 int i;
7356
7357 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7358 for (i = 1; i < tp->irq_cnt; i++)
7359 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7360}
7361
7362static void tg3_napi_fini(struct tg3 *tp)
7363{
7364 int i;
7365
7366 for (i = 0; i < tp->irq_cnt; i++)
7367 netif_napi_del(&tp->napi[i].napi);
7368}
7369
7370static inline void tg3_netif_stop(struct tg3 *tp)
7371{
7372 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7373 tg3_napi_disable(tp);
f4a46d1f 7374 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7375 netif_tx_disable(tp->dev);
7376}
7377
35763066 7378/* tp->lock must be held */
66cfd1bd
MC		 7379static inline void tg3_netif_start(struct tg3 *tp)
7380{
be947307
MC		 7381 tg3_ptp_resume(tp);
7382
66cfd1bd
MC		 7383 /* NOTE: unconditional netif_tx_wake_all_queues is only
7384 * appropriate so long as all callers are assured to
7385 * have free tx slots (such as after tg3_init_hw)
7386 */
7387 netif_tx_wake_all_queues(tp->dev);
7388
f4a46d1f
NNS		 7389 if (tp->link_up)
7390 netif_carrier_on(tp->dev);
7391
66cfd1bd
MC		 7392 tg3_napi_enable(tp);
7393 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7394 tg3_enable_ints(tp);
7395}
7396
f47c11ee
DM		 7397static void tg3_irq_quiesce(struct tg3 *tp)
7398{
4f125f42
MC		 7399 int i;
7400
f47c11ee
DM		 7401 BUG_ON(tp->irq_sync);
7402
7403 tp->irq_sync = 1;
7404 smp_mb();
7405
4f125f42
MC		 7406 for (i = 0; i < tp->irq_cnt; i++)
7407 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7408}
7409
f47c11ee
DM		 7410/* Fully shutdown all tg3 driver activity elsewhere in the system.
7411 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7412 * with as well. Most of the time, this is not necessary except when
7413 * shutting down the device.
7414 */
7415static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7416{
46966545 7417 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7418 if (irq_sync)
7419 tg3_irq_quiesce(tp);
f47c11ee
DM		 7420}
7421
7422static inline void tg3_full_unlock(struct tg3 *tp)
7423{
f47c11ee
DM		 7424 spin_unlock_bh(&tp->lock);
7425}
7426
fcfa0a32
MC		 7427/* One-shot MSI handler - Chip automatically disables interrupt
7428 * after sending MSI so driver doesn't have to do it.
7429 */
7d12e780 7430static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7431{
09943a18
MC		 7432 struct tg3_napi *tnapi = dev_id;
7433 struct tg3 *tp = tnapi->tp;
fcfa0a32 7434
898a56f8 7435 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7436 if (tnapi->rx_rcb)
7437 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7438
7439 if (likely(!tg3_irq_sync(tp)))
09943a18 7440 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7441
7442 return IRQ_HANDLED;
7443}
7444
88b06bc2
MC		 7445/* MSI ISR - No need to check for interrupt sharing and no need to
7446 * flush status block and interrupt mailbox. PCI ordering rules
7447 * guarantee that MSI will arrive after the status block.
7448 */
7d12e780 7449static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7450{
09943a18
MC		 7451 struct tg3_napi *tnapi = dev_id;
7452 struct tg3 *tp = tnapi->tp;
88b06bc2 7453
898a56f8 7454 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7455 if (tnapi->rx_rcb)
7456 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7457 /*
fac9b83e 7458 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7459 * chip-internal interrupt pending events.
fac9b83e 7460 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7461 * NIC to stop sending us irqs, engaging "in-intr-handler"
7462 * event coalescing.
7463 */
5b39de91 7464 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7465 if (likely(!tg3_irq_sync(tp)))
09943a18 7466 napi_schedule(&tnapi->napi);
61487480 7467
88b06bc2
MC		 7468 return IRQ_RETVAL(1);
7469}
7470
7d12e780 7471static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7472{
09943a18
MC		 7473 struct tg3_napi *tnapi = dev_id;
7474 struct tg3 *tp = tnapi->tp;
898a56f8 7475 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7476 unsigned int handled = 1;
7477
1da177e4
LT		 7478 /* In INTx mode, it is possible for the interrupt to arrive at
7479 * the CPU before the status block posted prior to the interrupt.
7480 * Reading the PCI State register will confirm whether the
7481 * interrupt is ours and will flush the status block.
7482 */
d18edcb2 7483 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7484 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7485 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7486 handled = 0;
f47c11ee 7487 goto out;
fac9b83e 7488 }
d18edcb2
MC		 7489 }
7490
7491 /*
7492 * Writing any value to intr-mbox-0 clears PCI INTA# and
7493 * chip-internal interrupt pending events.
7494 * Writing non-zero to intr-mbox-0 additional tells the
7495 * NIC to stop sending us irqs, engaging "in-intr-handler"
7496 * event coalescing.
c04cb347
MC		 7497 *
7498 * Flush the mailbox to de-assert the IRQ immediately to prevent
7499 * spurious interrupts. The flush impacts performance but
7500 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7501 */
c04cb347 7502 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7503 if (tg3_irq_sync(tp))
7504 goto out;
7505 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7506 if (likely(tg3_has_work(tnapi))) {
72334482 7507 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7508 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7509 } else {
7510 /* No work, shared interrupt perhaps? re-enable
7511 * interrupts, and flush that PCI write
7512 */
7513 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7514 0x00000000);
fac9b83e 7515 }
f47c11ee 7516out:
fac9b83e
DM		 7517 return IRQ_RETVAL(handled);
7518}
7519
7d12e780 7520static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7521{
09943a18
MC		 7522 struct tg3_napi *tnapi = dev_id;
7523 struct tg3 *tp = tnapi->tp;
898a56f8 7524 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7525 unsigned int handled = 1;
7526
fac9b83e
DM		 7527 /* In INTx mode, it is possible for the interrupt to arrive at
7528 * the CPU before the status block posted prior to the interrupt.
7529 * Reading the PCI State register will confirm whether the
7530 * interrupt is ours and will flush the status block.
7531 */
898a56f8 7532 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7533 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7534 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7535 handled = 0;
f47c11ee 7536 goto out;
1da177e4 7537 }
d18edcb2
MC		 7538 }
7539
7540 /*
7541 * writing any value to intr-mbox-0 clears PCI INTA# and
7542 * chip-internal interrupt pending events.
7543 * writing non-zero to intr-mbox-0 additional tells the
7544 * NIC to stop sending us irqs, engaging "in-intr-handler"
7545 * event coalescing.
c04cb347
MC		 7546 *
7547 * Flush the mailbox to de-assert the IRQ immediately to prevent
7548 * spurious interrupts. The flush impacts performance but
7549 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7550 */
c04cb347 7551 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7552
7553 /*
7554 * In a shared interrupt configuration, sometimes other devices'
7555 * interrupts will scream. We record the current status tag here
7556 * so that the above check can report that the screaming interrupts
7557 * are unhandled. Eventually they will be silenced.
7558 */
898a56f8 7559 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7560
d18edcb2
MC		 7561 if (tg3_irq_sync(tp))
7562 goto out;
624f8e50 7563
72334482 7564 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7565
09943a18 7566 napi_schedule(&tnapi->napi);
624f8e50 7567
f47c11ee 7568out:
1da177e4
LT		 7569 return IRQ_RETVAL(handled);
7570}
7571
7938109f 7572/* ISR for interrupt test */
7d12e780 7573static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7574{
09943a18
MC		 7575 struct tg3_napi *tnapi = dev_id;
7576 struct tg3 *tp = tnapi->tp;
898a56f8 7577 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7578
f9804ddb
MC		 7579 if ((sblk->status & SD_STATUS_UPDATED) ||
7580 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7581 tg3_disable_ints(tp);
7938109f
MC		 7582 return IRQ_RETVAL(1);
7583 }
7584 return IRQ_RETVAL(0);
7585}
7586
1da177e4
LT		 7587#ifdef CONFIG_NET_POLL_CONTROLLER
7588static void tg3_poll_controller(struct net_device *dev)
7589{
4f125f42 7590 int i;
88b06bc2
MC		 7591 struct tg3 *tp = netdev_priv(dev);
7592
9c13cb8b
NNS		 7593 if (tg3_irq_sync(tp))
7594 return;
7595
4f125f42 7596 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7597 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7598}
7599#endif
7600
1da177e4
LT		 7601static void tg3_tx_timeout(struct net_device *dev)
7602{
7603 struct tg3 *tp = netdev_priv(dev);
7604
b0408751 7605 if (netif_msg_tx_err(tp)) {
05dbe005 7606 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7607 tg3_dump_state(tp);
b0408751 7608 }
1da177e4 7609
db219973 7610 tg3_reset_task_schedule(tp);
1da177e4
LT		 7611}
7612
c58ec932
MC		 7613/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7614static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7615{
7616 u32 base = (u32) mapping & 0xffffffff;
7617
807540ba 7618 return (base > 0xffffdcc0) && (base + len + 8 < base);
c58ec932
MC		 7619}
7620
0f0d1510
MC		 7621/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7622 * of any 4GB boundaries: 4G, 8G, etc
7623 */
7624static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7625 u32 len, u32 mss)
7626{
7627 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7628 u32 base = (u32) mapping & 0xffffffff;
7629
7630 return ((base + len + (mss & 0x3fff)) < base);
7631 }
7632 return 0;
7633}
7634
72f2afb8
MC		 7635/* Test for DMA addresses > 40-bit */
7636static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7637 int len)
7638{
7639#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7640 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7641 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7642 return 0;
7643#else
7644 return 0;
7645#endif
7646}
7647
d1a3b737 7648static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7649 dma_addr_t mapping, u32 len, u32 flags,
7650 u32 mss, u32 vlan)
2ffcc981 7651{
92cd3a17
MC		 7652 txbd->addr_hi = ((u64) mapping >> 32);
7653 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7654 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7655 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7656}
1da177e4 7657
84b67b27 7658static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7659 dma_addr_t map, u32 len, u32 flags,
7660 u32 mss, u32 vlan)
7661{
7662 struct tg3 *tp = tnapi->tp;
7663 bool hwbug = false;
7664
7665 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7666 hwbug = true;
d1a3b737
MC		 7667
7668 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7669 hwbug = true;
d1a3b737 7670
0f0d1510
MC		 7671 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7672 hwbug = true;
7673
d1a3b737 7674 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7675 hwbug = true;
d1a3b737 7676
a4cb428d 7677 if (tp->dma_limit) {
b9e45482 7678 u32 prvidx = *entry;
e31aa987 7679 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7680 while (len > tp->dma_limit && *budget) {
7681 u32 frag_len = tp->dma_limit;
7682 len -= tp->dma_limit;
e31aa987 7683
b9e45482
MC		 7684 /* Avoid the 8byte DMA problem */
7685 if (len <= 8) {
a4cb428d
MC		 7686 len += tp->dma_limit / 2;
7687 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7688 }
7689
b9e45482
MC		 7690 tnapi->tx_buffers[*entry].fragmented = true;
7691
7692 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7693 frag_len, tmp_flag, mss, vlan);
7694 *budget -= 1;
7695 prvidx = *entry;
7696 *entry = NEXT_TX(*entry);
7697
e31aa987
MC		 7698 map += frag_len;
7699 }
7700
7701 if (len) {
7702 if (*budget) {
7703 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7704 len, flags, mss, vlan);
b9e45482 7705 *budget -= 1;
e31aa987
MC		 7706 *entry = NEXT_TX(*entry);
7707 } else {
3db1cd5c 7708 hwbug = true;
b9e45482 7709 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7710 }
7711 }
7712 } else {
84b67b27
MC		 7713 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7714 len, flags, mss, vlan);
e31aa987
MC		 7715 *entry = NEXT_TX(*entry);
7716 }
d1a3b737
MC		 7717
7718 return hwbug;
7719}
7720
0d681b27 7721static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7722{
7723 int i;
0d681b27 7724 struct sk_buff *skb;
df8944cf 7725 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7726
0d681b27
MC		 7727 skb = txb->skb;
7728 txb->skb = NULL;
7729
432aa7ed
MC		 7730 pci_unmap_single(tnapi->tp->pdev,
7731 dma_unmap_addr(txb, mapping),
7732 skb_headlen(skb),
7733 PCI_DMA_TODEVICE);
e01ee14d
MC		 7734
7735 while (txb->fragmented) {
7736 txb->fragmented = false;
7737 entry = NEXT_TX(entry);
7738 txb = &tnapi->tx_buffers[entry];
7739 }
7740
ba1142e4 7741 for (i = 0; i <= last; i++) {
9e903e08 7742 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7743
7744 entry = NEXT_TX(entry);
7745 txb = &tnapi->tx_buffers[entry];
7746
7747 pci_unmap_page(tnapi->tp->pdev,
7748 dma_unmap_addr(txb, mapping),
9e903e08 7749 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7750
7751 while (txb->fragmented) {
7752 txb->fragmented = false;
7753 entry = NEXT_TX(entry);
7754 txb = &tnapi->tx_buffers[entry];
7755 }
432aa7ed
MC		 7756 }
7757}
7758
72f2afb8 7759/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7760static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7761 struct sk_buff **pskb,
84b67b27 7762 u32 *entry, u32 *budget,
92cd3a17 7763 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7764{
24f4efd4 7765 struct tg3 *tp = tnapi->tp;
f7ff1987 7766 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7767 dma_addr_t new_addr = 0;
432aa7ed 7768 int ret = 0;
1da177e4 7769
4153577a 7770 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7771 new_skb = skb_copy(skb, GFP_ATOMIC);
7772 else {
7773 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7774
7775 new_skb = skb_copy_expand(skb,
7776 skb_headroom(skb) + more_headroom,
7777 skb_tailroom(skb), GFP_ATOMIC);
7778 }
7779
1da177e4 7780 if (!new_skb) {
c58ec932
MC		 7781 ret = -1;
7782 } else {
7783 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7784 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7785 PCI_DMA_TODEVICE);
7786 /* Make sure the mapping succeeded */
7787 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
f4188d8a 7788 dev_kfree_skb(new_skb);
c58ec932 7789 ret = -1;
c58ec932 7790 } else {
b9e45482
MC		 7791 u32 save_entry = *entry;
7792
92cd3a17
MC		 7793 base_flags |= TXD_FLAG_END;
7794
84b67b27
MC		 7795 tnapi->tx_buffers[*entry].skb = new_skb;
7796 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7797 mapping, new_addr);
7798
84b67b27 7799 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7800 new_skb->len, base_flags,
7801 mss, vlan)) {
ba1142e4 7802 tg3_tx_skb_unmap(tnapi, save_entry, -1);
d1a3b737
MC		 7803 dev_kfree_skb(new_skb);
7804 ret = -1;
7805 }
f4188d8a 7806 }
1da177e4
LT		 7807 }
7808
7809 dev_kfree_skb(skb);
f7ff1987 7810 *pskb = new_skb;
c58ec932 7811 return ret;
1da177e4
LT		 7812}
7813
2ffcc981 7814static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83
MC		 7815
7816/* Use GSO to workaround a rare TSO bug that may be triggered when the
7817 * TSO header is greater than 80 bytes.
7818 */
7819static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7820{
7821 struct sk_buff *segs, *nskb;
f3f3f27e 7822 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7823
7824 /* Estimate the number of fragments in the worst case */
f3f3f27e 7825 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 7826 netif_stop_queue(tp->dev);
f65aac16
MC		 7827
7828 /* netif_tx_stop_queue() must be done before checking
7829 * checking tx index in tg3_tx_avail() below, because in
7830 * tg3_tx(), we update tx index before checking for
7831 * netif_tx_queue_stopped().
7832 */
7833 smp_mb();
f3f3f27e 7834 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 7835 return NETDEV_TX_BUSY;
7836
7837 netif_wake_queue(tp->dev);
52c0fd83
MC		 7838 }
7839
7840 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 7841 if (IS_ERR(segs))
52c0fd83
MC		 7842 goto tg3_tso_bug_end;
7843
7844 do {
7845 nskb = segs;
7846 segs = segs->next;
7847 nskb->next = NULL;
2ffcc981 7848 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7849 } while (segs);
7850
7851tg3_tso_bug_end:
7852 dev_kfree_skb(skb);
7853
7854 return NETDEV_TX_OK;
7855}
52c0fd83 7856
5a6f3074 7857/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
63c3a66f 7858 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5a6f3074 7859 */
2ffcc981 7860static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7861{
7862 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7863 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7864 u32 budget;
432aa7ed 7865 int i = -1, would_hit_hwbug;
90079ce8 7866 dma_addr_t mapping;
24f4efd4
MC		 7867 struct tg3_napi *tnapi;
7868 struct netdev_queue *txq;
432aa7ed 7869 unsigned int last;
f4188d8a 7870
24f4efd4
MC		 7871 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7872 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7873 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7874 tnapi++;
1da177e4 7875
84b67b27
MC		 7876 budget = tg3_tx_avail(tnapi);
7877
00b70504 7878 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7879 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7880 * interrupt. Furthermore, IRQ processing runs lockless so we have
7881 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7882 */
84b67b27 7883 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7884 if (!netif_tx_queue_stopped(txq)) {
7885 netif_tx_stop_queue(txq);
1f064a87
SH		 7886
7887 /* This is a hard error, log it. */
5129c3a3
MC		 7888 netdev_err(dev,
7889 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7890 }
1da177e4
LT		 7891 return NETDEV_TX_BUSY;
7892 }
7893
f3f3f27e 7894 entry = tnapi->tx_prod;
1da177e4 7895 base_flags = 0;
84fa7933 7896 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 7897 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 7898
be98da6a
MC		 7899 mss = skb_shinfo(skb)->gso_size;
7900 if (mss) {
eddc9ec5 7901 struct iphdr *iph;
34195c3d 7902 u32 tcp_opt_len, hdr_len;
1da177e4
LT		 7903
7904 if (skb_header_cloned(skb) &&
48855432
ED		 7905 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7906 goto drop;
1da177e4 7907
34195c3d 7908 iph = ip_hdr(skb);
ab6a5bb6 7909 tcp_opt_len = tcp_optlen(skb);
1da177e4 7910
a5a11955 7911 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7912
a5a11955 7913 if (!skb_is_gso_v6(skb)) {
34195c3d
MC		 7914 iph->check = 0;
7915 iph->tot_len = htons(mss + hdr_len);
7916 }
7917
52c0fd83 7918 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
63c3a66f 7919 tg3_flag(tp, TSO_BUG))
de6f31eb 7920 return tg3_tso_bug(tp, skb);
52c0fd83 7921
1da177e4
LT		 7922 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7923 TXD_FLAG_CPU_POST_DMA);
7924
63c3a66f
JP		 7925 if (tg3_flag(tp, HW_TSO_1) ||
7926 tg3_flag(tp, HW_TSO_2) ||
7927 tg3_flag(tp, HW_TSO_3)) {
aa8223c7 7928 tcp_hdr(skb)->check = 0;
1da177e4 7929 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 7930 } else
7931 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7932 iph->daddr, 0,
7933 IPPROTO_TCP,
7934 0);
1da177e4 7935
63c3a66f 7936 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7937 mss |= (hdr_len & 0xc) << 12;
7938 if (hdr_len & 0x10)
7939 base_flags |= 0x00000010;
7940 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7941 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7942 mss |= hdr_len << 9;
63c3a66f 7943 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7944 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7945 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7946 int tsflags;
7947
eddc9ec5 7948 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7949 mss |= (tsflags << 11);
7950 }
7951 } else {
eddc9ec5 7952 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7953 int tsflags;
7954
eddc9ec5 7955 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7956 base_flags |= tsflags << 12;
7957 }
7958 }
7959 }
bf933c80 7960
93a700a9
MC		 7961 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7962 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7963 base_flags |= TXD_FLAG_JMB_PKT;
7964
92cd3a17
MC		 7965 if (vlan_tx_tag_present(skb)) {
7966 base_flags |= TXD_FLAG_VLAN;
7967 vlan = vlan_tx_tag_get(skb);
7968 }
1da177e4 7969
fb4ce8ad
MC		 7970 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7971 tg3_flag(tp, TX_TSTAMP_EN)) {
7972 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7973 base_flags |= TXD_FLAG_HWTSTAMP;
7974 }
7975
f4188d8a
AD		 7976 len = skb_headlen(skb);
7977
7978 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 7979 if (pci_dma_mapping_error(tp->pdev, mapping))
7980 goto drop;
7981
90079ce8 7982
f3f3f27e 7983 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 7984 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 7985
7986 would_hit_hwbug = 0;
7987
63c3a66f 7988 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 7989 would_hit_hwbug = 1;
1da177e4 7990
84b67b27 7991 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 7992 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 7993 mss, vlan)) {
d1a3b737 7994 would_hit_hwbug = 1;
ba1142e4 7995 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 7996 u32 tmp_mss = mss;
7997
7998 if (!tg3_flag(tp, HW_TSO_1) &&
7999 !tg3_flag(tp, HW_TSO_2) &&
8000 !tg3_flag(tp, HW_TSO_3))
8001 tmp_mss = 0;
8002
c5665a53
MC		 8003 /* Now loop through additional data
8004 * fragments, and queue them.
8005 */
1da177e4
LT		 8006 last = skb_shinfo(skb)->nr_frags - 1;
8007 for (i = 0; i <= last; i++) {
8008 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8009
9e903e08 8010 len = skb_frag_size(frag);
dc234d0b 8011 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8012 len, DMA_TO_DEVICE);
1da177e4 8013
f3f3f27e 8014 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8015 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8016 mapping);
5d6bcdfe 8017 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8018 goto dma_error;
1da177e4 8019
b9e45482
MC		 8020 if (!budget ||
8021 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8022 len, base_flags |
8023 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8024 tmp_mss, vlan)) {
72f2afb8 8025 would_hit_hwbug = 1;
b9e45482
MC		 8026 break;
8027 }
1da177e4
LT		 8028 }
8029 }
8030
8031 if (would_hit_hwbug) {
0d681b27 8032 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4
LT		 8033
8034 /* If the workaround fails due to memory/mapping
8035 * failure, silently drop this packet.
8036 */
84b67b27
MC		 8037 entry = tnapi->tx_prod;
8038 budget = tg3_tx_avail(tnapi);
f7ff1987 8039 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8040 base_flags, mss, vlan))
48855432 8041 goto drop_nofree;
1da177e4
LT		 8042 }
8043
d515b450 8044 skb_tx_timestamp(skb);
5cb917bc 8045 netdev_tx_sent_queue(txq, skb->len);
d515b450 8046
6541b806
MC		 8047 /* Sync BD data before updating mailbox */
8048 wmb();
8049
1da177e4 8050 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 8051 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 8052
f3f3f27e
MC		 8053 tnapi->tx_prod = entry;
8054 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8055 netif_tx_stop_queue(txq);
f65aac16
MC		 8056
8057 /* netif_tx_stop_queue() must be done before checking
8058 * checking tx index in tg3_tx_avail() below, because in
8059 * tg3_tx(), we update tx index before checking for
8060 * netif_tx_queue_stopped().
8061 */
8062 smp_mb();
f3f3f27e 8063 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8064 netif_tx_wake_queue(txq);
51b91468 8065 }
1da177e4 8066
cdd0db05 8067 mmiowb();
1da177e4 8068 return NETDEV_TX_OK;
f4188d8a
AD		 8069
8070dma_error:
ba1142e4 8071 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8072 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432
ED		 8073drop:
8074 dev_kfree_skb(skb);
8075drop_nofree:
8076 tp->tx_dropped++;
f4188d8a 8077 return NETDEV_TX_OK;
1da177e4
LT		 8078}
8079
6e01b20b
MC		 8080static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8081{
8082 if (enable) {
8083 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8084 MAC_MODE_PORT_MODE_MASK);
8085
8086 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8087
8088 if (!tg3_flag(tp, 5705_PLUS))
8089 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8090
8091 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8092 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8093 else
8094 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8095 } else {
8096 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8097
8098 if (tg3_flag(tp, 5705_PLUS) ||
8099 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8100 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8101 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8102 }
8103
8104 tw32(MAC_MODE, tp->mac_mode);
8105 udelay(40);
8106}
8107
941ec90f 8108static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8109{
941ec90f 8110 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8111
8112 tg3_phy_toggle_apd(tp, false);
953c96e0 8113 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8114
941ec90f
MC		 8115 if (extlpbk && tg3_phy_set_extloopbk(tp))
8116 return -EIO;
8117
8118 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8119 switch (speed) {
8120 case SPEED_10:
8121 break;
8122 case SPEED_100:
8123 bmcr |= BMCR_SPEED100;
8124 break;
8125 case SPEED_1000:
8126 default:
8127 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8128 speed = SPEED_100;
8129 bmcr |= BMCR_SPEED100;
8130 } else {
8131 speed = SPEED_1000;
8132 bmcr |= BMCR_SPEED1000;
8133 }
8134 }
8135
941ec90f
MC		 8136 if (extlpbk) {
8137 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8138 tg3_readphy(tp, MII_CTRL1000, &val);
8139 val |= CTL1000_AS_MASTER |
8140 CTL1000_ENABLE_MASTER;
8141 tg3_writephy(tp, MII_CTRL1000, val);
8142 } else {
8143 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8144 MII_TG3_FET_PTEST_TRIM_2;
8145 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8146 }
8147 } else
8148 bmcr |= BMCR_LOOPBACK;
8149
5e5a7f37
MC		 8150 tg3_writephy(tp, MII_BMCR, bmcr);
8151
8152 /* The write needs to be flushed for the FETs */
8153 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8154 tg3_readphy(tp, MII_BMCR, &bmcr);
8155
8156 udelay(40);
8157
8158 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8159 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8160 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8161 MII_TG3_FET_PTEST_FRC_TX_LINK |
8162 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8163
8164 /* The write needs to be flushed for the AC131 */
8165 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8166 }
8167
8168 /* Reset to prevent losing 1st rx packet intermittently */
8169 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8170 tg3_flag(tp, 5780_CLASS)) {
8171 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8172 udelay(10);
8173 tw32_f(MAC_RX_MODE, tp->rx_mode);
8174 }
8175
8176 mac_mode = tp->mac_mode &
8177 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8178 if (speed == SPEED_1000)
8179 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8180 else
8181 mac_mode |= MAC_MODE_PORT_MODE_MII;
8182
4153577a 8183 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8184 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8185
8186 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8187 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8188 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8189 mac_mode |= MAC_MODE_LINK_POLARITY;
8190
8191 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8192 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8193 }
8194
8195 tw32(MAC_MODE, mac_mode);
8196 udelay(40);
941ec90f
MC		 8197
8198 return 0;
5e5a7f37
MC		 8199}
8200
c8f44aff 8201static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8202{
8203 struct tg3 *tp = netdev_priv(dev);
8204
8205 if (features & NETIF_F_LOOPBACK) {
8206 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8207 return;
8208
06c03c02 8209 spin_lock_bh(&tp->lock);
6e01b20b 8210 tg3_mac_loopback(tp, true);
06c03c02
MB		 8211 netif_carrier_on(tp->dev);
8212 spin_unlock_bh(&tp->lock);
8213 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8214 } else {
8215 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8216 return;
8217
06c03c02 8218 spin_lock_bh(&tp->lock);
6e01b20b 8219 tg3_mac_loopback(tp, false);
06c03c02 8220 /* Force link status check */
953c96e0 8221 tg3_setup_phy(tp, true);
06c03c02
MB		 8222 spin_unlock_bh(&tp->lock);
8223 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8224 }
8225}
8226
c8f44aff
MM		 8227static netdev_features_t tg3_fix_features(struct net_device *dev,
8228 netdev_features_t features)
dc668910
MM		 8229{
8230 struct tg3 *tp = netdev_priv(dev);
8231
63c3a66f 8232 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8233 features &= ~NETIF_F_ALL_TSO;
8234
8235 return features;
8236}
8237
c8f44aff 8238static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8239{
c8f44aff 8240 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8241
8242 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8243 tg3_set_loopback(dev, features);
8244
8245 return 0;
8246}
8247
21f581a5
MC		 8248static void tg3_rx_prodring_free(struct tg3 *tp,
8249 struct tg3_rx_prodring_set *tpr)
1da177e4 8250{
1da177e4
LT		 8251 int i;
8252
8fea32b9 8253 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8254 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8255 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8256 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8257 tp->rx_pkt_map_sz);
8258
63c3a66f 8259 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8260 for (i = tpr->rx_jmb_cons_idx;
8261 i != tpr->rx_jmb_prod_idx;
2c49a44d 8262 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8263 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8264 TG3_RX_JMB_MAP_SZ);
8265 }
8266 }
8267
2b2cdb65 8268 return;
b196c7e4 8269 }
1da177e4 8270
2c49a44d 8271 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8272 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8273 tp->rx_pkt_map_sz);
1da177e4 8274
63c3a66f 8275 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8276 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8277 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8278 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8279 }
8280}
8281
c6cdf436 8282/* Initialize rx rings for packet processing.
1da177e4
LT		 8283 *
8284 * The chip has been shut down and the driver detached from
8285 * the networking, so no interrupts or new tx packets will
8286 * end up in the driver. tp->{tx,}lock are held and thus
8287 * we may not sleep.
8288 */
21f581a5
MC		 8289static int tg3_rx_prodring_alloc(struct tg3 *tp,
8290 struct tg3_rx_prodring_set *tpr)
1da177e4 8291{
287be12e 8292 u32 i, rx_pkt_dma_sz;
1da177e4 8293
b196c7e4
MC		 8294 tpr->rx_std_cons_idx = 0;
8295 tpr->rx_std_prod_idx = 0;
8296 tpr->rx_jmb_cons_idx = 0;
8297 tpr->rx_jmb_prod_idx = 0;
8298
8fea32b9 8299 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8300 memset(&tpr->rx_std_buffers[0], 0,
8301 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8302 if (tpr->rx_jmb_buffers)
2b2cdb65 8303 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8304 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8305 goto done;
8306 }
8307
1da177e4 8308 /* Zero out all descriptors. */
2c49a44d 8309 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8310
287be12e 8311 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8312 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8313 tp->dev->mtu > ETH_DATA_LEN)
8314 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8315 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8316
1da177e4
LT		 8317 /* Initialize invariants of the rings, we only set this
8318 * stuff once. This works because the card does not
8319 * write into the rx buffer posting rings.
8320 */
2c49a44d 8321 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8322 struct tg3_rx_buffer_desc *rxd;
8323
21f581a5 8324 rxd = &tpr->rx_std[i];
287be12e 8325 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8326 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8327 rxd->opaque = (RXD_OPAQUE_RING_STD |
8328 (i << RXD_OPAQUE_INDEX_SHIFT));
8329 }
8330
1da177e4
LT		 8331 /* Now allocate fresh SKBs for each rx ring. */
8332 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8333 unsigned int frag_size;
8334
8335 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8336 &frag_size) < 0) {
5129c3a3
MC		 8337 netdev_warn(tp->dev,
8338 "Using a smaller RX standard ring. Only "
8339 "%d out of %d buffers were allocated "
8340 "successfully\n", i, tp->rx_pending);
32d8c572 8341 if (i == 0)
cf7a7298 8342 goto initfail;
32d8c572 8343 tp->rx_pending = i;
1da177e4 8344 break;
32d8c572 8345 }
1da177e4
LT		 8346 }
8347
63c3a66f 8348 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8349 goto done;
8350
2c49a44d 8351 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8352
63c3a66f 8353 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8354 goto done;
cf7a7298 8355
2c49a44d 8356 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8357 struct tg3_rx_buffer_desc *rxd;
8358
8359 rxd = &tpr->rx_jmb[i].std;
8360 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8361 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8362 RXD_FLAG_JUMBO;
8363 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8364 (i << RXD_OPAQUE_INDEX_SHIFT));
8365 }
8366
8367 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8368 unsigned int frag_size;
8369
8370 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8371 &frag_size) < 0) {
5129c3a3
MC		 8372 netdev_warn(tp->dev,
8373 "Using a smaller RX jumbo ring. Only %d "
8374 "out of %d buffers were allocated "
8375 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8376 if (i == 0)
8377 goto initfail;
8378 tp->rx_jumbo_pending = i;
8379 break;
1da177e4
LT		 8380 }
8381 }
cf7a7298
MC		 8382
8383done:
32d8c572 8384 return 0;
cf7a7298
MC		 8385
8386initfail:
21f581a5 8387 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8388 return -ENOMEM;
1da177e4
LT		 8389}
8390
21f581a5
MC		 8391static void tg3_rx_prodring_fini(struct tg3 *tp,
8392 struct tg3_rx_prodring_set *tpr)
1da177e4 8393{
21f581a5
MC		 8394 kfree(tpr->rx_std_buffers);
8395 tpr->rx_std_buffers = NULL;
8396 kfree(tpr->rx_jmb_buffers);
8397 tpr->rx_jmb_buffers = NULL;
8398 if (tpr->rx_std) {
4bae65c8
MC		 8399 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8400 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8401 tpr->rx_std = NULL;
1da177e4 8402 }
21f581a5 8403 if (tpr->rx_jmb) {
4bae65c8
MC		 8404 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8405 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8406 tpr->rx_jmb = NULL;
1da177e4 8407 }
cf7a7298
MC		 8408}
8409
21f581a5
MC		 8410static int tg3_rx_prodring_init(struct tg3 *tp,
8411 struct tg3_rx_prodring_set *tpr)
cf7a7298 8412{
2c49a44d
MC		 8413 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8414 GFP_KERNEL);
21f581a5 8415 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8416 return -ENOMEM;
8417
4bae65c8
MC		 8418 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8419 TG3_RX_STD_RING_BYTES(tp),
8420 &tpr->rx_std_mapping,
8421 GFP_KERNEL);
21f581a5 8422 if (!tpr->rx_std)
cf7a7298
MC		 8423 goto err_out;
8424
63c3a66f 8425 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8426 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8427 GFP_KERNEL);
8428 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8429 goto err_out;
8430
4bae65c8
MC		 8431 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8432 TG3_RX_JMB_RING_BYTES(tp),
8433 &tpr->rx_jmb_mapping,
8434 GFP_KERNEL);
21f581a5 8435 if (!tpr->rx_jmb)
cf7a7298
MC		 8436 goto err_out;
8437 }
8438
8439 return 0;
8440
8441err_out:
21f581a5 8442 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8443 return -ENOMEM;
8444}
8445
8446/* Free up pending packets in all rx/tx rings.
8447 *
8448 * The chip has been shut down and the driver detached from
8449 * the networking, so no interrupts or new tx packets will
8450 * end up in the driver. tp->{tx,}lock is not held and we are not
8451 * in an interrupt context and thus may sleep.
8452 */
8453static void tg3_free_rings(struct tg3 *tp)
8454{
f77a6a8e 8455 int i, j;
cf7a7298 8456
f77a6a8e
MC		 8457 for (j = 0; j < tp->irq_cnt; j++) {
8458 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8459
8fea32b9 8460 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8461
0c1d0e2b
MC		 8462 if (!tnapi->tx_buffers)
8463 continue;
8464
0d681b27
MC		 8465 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8466 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8467
0d681b27 8468 if (!skb)
f77a6a8e 8469 continue;
cf7a7298 8470
ba1142e4
MC		 8471 tg3_tx_skb_unmap(tnapi, i,
8472 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8473
8474 dev_kfree_skb_any(skb);
8475 }
5cb917bc 8476 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8477 }
cf7a7298
MC		 8478}
8479
8480/* Initialize tx/rx rings for packet processing.
8481 *
8482 * The chip has been shut down and the driver detached from
8483 * the networking, so no interrupts or new tx packets will
8484 * end up in the driver. tp->{tx,}lock are held and thus
8485 * we may not sleep.
8486 */
8487static int tg3_init_rings(struct tg3 *tp)
8488{
f77a6a8e 8489 int i;
72334482 8490
cf7a7298
MC		 8491 /* Free up all the SKBs. */
8492 tg3_free_rings(tp);
8493
f77a6a8e
MC		 8494 for (i = 0; i < tp->irq_cnt; i++) {
8495 struct tg3_napi *tnapi = &tp->napi[i];
8496
8497 tnapi->last_tag = 0;
8498 tnapi->last_irq_tag = 0;
8499 tnapi->hw_status->status = 0;
8500 tnapi->hw_status->status_tag = 0;
8501 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8502
f77a6a8e
MC		 8503 tnapi->tx_prod = 0;
8504 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8505 if (tnapi->tx_ring)
8506 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8507
8508 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8509 if (tnapi->rx_rcb)
8510 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8511
8fea32b9 8512 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8513 tg3_free_rings(tp);
2b2cdb65 8514 return -ENOMEM;
e4af1af9 8515 }
f77a6a8e 8516 }
72334482 8517
2b2cdb65 8518 return 0;
cf7a7298
MC		 8519}
8520
49a359e3 8521static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8522{
f77a6a8e 8523 int i;
898a56f8 8524
49a359e3 8525 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8526 struct tg3_napi *tnapi = &tp->napi[i];
8527
8528 if (tnapi->tx_ring) {
4bae65c8 8529 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8530 tnapi->tx_ring, tnapi->tx_desc_mapping);
8531 tnapi->tx_ring = NULL;
8532 }
8533
8534 kfree(tnapi->tx_buffers);
8535 tnapi->tx_buffers = NULL;
49a359e3
MC		 8536 }
8537}
f77a6a8e 8538
49a359e3
MC		 8539static int tg3_mem_tx_acquire(struct tg3 *tp)
8540{
8541 int i;
8542 struct tg3_napi *tnapi = &tp->napi[0];
8543
8544 /* If multivector TSS is enabled, vector 0 does not handle
8545 * tx interrupts. Don't allocate any resources for it.
8546 */
8547 if (tg3_flag(tp, ENABLE_TSS))
8548 tnapi++;
8549
8550 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8551 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8552 TG3_TX_RING_SIZE, GFP_KERNEL);
8553 if (!tnapi->tx_buffers)
8554 goto err_out;
8555
8556 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8557 TG3_TX_RING_BYTES,
8558 &tnapi->tx_desc_mapping,
8559 GFP_KERNEL);
8560 if (!tnapi->tx_ring)
8561 goto err_out;
8562 }
8563
8564 return 0;
8565
8566err_out:
8567 tg3_mem_tx_release(tp);
8568 return -ENOMEM;
8569}
8570
8571static void tg3_mem_rx_release(struct tg3 *tp)
8572{
8573 int i;
8574
8575 for (i = 0; i < tp->irq_max; i++) {
8576 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8577
8fea32b9
MC		 8578 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8579
49a359e3
MC		 8580 if (!tnapi->rx_rcb)
8581 continue;
8582
8583 dma_free_coherent(&tp->pdev->dev,
8584 TG3_RX_RCB_RING_BYTES(tp),
8585 tnapi->rx_rcb,
8586 tnapi->rx_rcb_mapping);
8587 tnapi->rx_rcb = NULL;
8588 }
8589}
8590
8591static int tg3_mem_rx_acquire(struct tg3 *tp)
8592{
8593 unsigned int i, limit;
8594
8595 limit = tp->rxq_cnt;
8596
8597 /* If RSS is enabled, we need a (dummy) producer ring
8598 * set on vector zero. This is the true hw prodring.
8599 */
8600 if (tg3_flag(tp, ENABLE_RSS))
8601 limit++;
8602
8603 for (i = 0; i < limit; i++) {
8604 struct tg3_napi *tnapi = &tp->napi[i];
8605
8606 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8607 goto err_out;
8608
8609 /* If multivector RSS is enabled, vector 0
8610 * does not handle rx or tx interrupts.
8611 * Don't allocate any resources for it.
8612 */
8613 if (!i && tg3_flag(tp, ENABLE_RSS))
8614 continue;
8615
ede23fa8
JP		 8616 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8617 TG3_RX_RCB_RING_BYTES(tp),
8618 &tnapi->rx_rcb_mapping,
8619 GFP_KERNEL);
49a359e3
MC		 8620 if (!tnapi->rx_rcb)
8621 goto err_out;
49a359e3
MC		 8622 }
8623
8624 return 0;
8625
8626err_out:
8627 tg3_mem_rx_release(tp);
8628 return -ENOMEM;
8629}
8630
8631/*
8632 * Must not be invoked with interrupt sources disabled and
8633 * the hardware shutdown down.
8634 */
8635static void tg3_free_consistent(struct tg3 *tp)
8636{
8637 int i;
8638
8639 for (i = 0; i < tp->irq_cnt; i++) {
8640 struct tg3_napi *tnapi = &tp->napi[i];
8641
f77a6a8e 8642 if (tnapi->hw_status) {
4bae65c8
MC		 8643 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8644 tnapi->hw_status,
8645 tnapi->status_mapping);
f77a6a8e
MC		 8646 tnapi->hw_status = NULL;
8647 }
1da177e4 8648 }
f77a6a8e 8649
49a359e3
MC		 8650 tg3_mem_rx_release(tp);
8651 tg3_mem_tx_release(tp);
8652
1da177e4 8653 if (tp->hw_stats) {
4bae65c8
MC		 8654 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8655 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8656 tp->hw_stats = NULL;
8657 }
8658}
8659
8660/*
8661 * Must not be invoked with interrupt sources disabled and
8662 * the hardware shutdown down. Can sleep.
8663 */
8664static int tg3_alloc_consistent(struct tg3 *tp)
8665{
f77a6a8e 8666 int i;
898a56f8 8667
ede23fa8
JP		 8668 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8669 sizeof(struct tg3_hw_stats),
8670 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8671 if (!tp->hw_stats)
1da177e4
LT		 8672 goto err_out;
8673
f77a6a8e
MC		 8674 for (i = 0; i < tp->irq_cnt; i++) {
8675 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8676 struct tg3_hw_status *sblk;
1da177e4 8677
ede23fa8
JP		 8678 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8679 TG3_HW_STATUS_SIZE,
8680 &tnapi->status_mapping,
8681 GFP_KERNEL);
f77a6a8e
MC		 8682 if (!tnapi->hw_status)
8683 goto err_out;
898a56f8 8684
8d9d7cfc
MC		 8685 sblk = tnapi->hw_status;
8686
49a359e3 8687 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8688 u16 *prodptr = NULL;
8fea32b9 8689
49a359e3
MC		 8690 /*
8691 * When RSS is enabled, the status block format changes
8692 * slightly. The "rx_jumbo_consumer", "reserved",
8693 * and "rx_mini_consumer" members get mapped to the
8694 * other three rx return ring producer indexes.
8695 */
8696 switch (i) {
8697 case 1:
8698 prodptr = &sblk->idx[0].rx_producer;
8699 break;
8700 case 2:
8701 prodptr = &sblk->rx_jumbo_consumer;
8702 break;
8703 case 3:
8704 prodptr = &sblk->reserved;
8705 break;
8706 case 4:
8707 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8708 break;
8709 }
49a359e3
MC		 8710 tnapi->rx_rcb_prod_idx = prodptr;
8711 } else {
8d9d7cfc 8712 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8713 }
f77a6a8e 8714 }
1da177e4 8715
49a359e3
MC		 8716 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8717 goto err_out;
8718
1da177e4
LT		 8719 return 0;
8720
8721err_out:
8722 tg3_free_consistent(tp);
8723 return -ENOMEM;
8724}
8725
8726#define MAX_WAIT_CNT 1000
8727
8728/* To stop a block, clear the enable bit and poll till it
8729 * clears. tp->lock is held.
8730 */
953c96e0 8731static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8732{
8733 unsigned int i;
8734 u32 val;
8735
63c3a66f 8736 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8737 switch (ofs) {
8738 case RCVLSC_MODE:
8739 case DMAC_MODE:
8740 case MBFREE_MODE:
8741 case BUFMGR_MODE:
8742 case MEMARB_MODE:
8743 /* We can't enable/disable these bits of the
8744 * 5705/5750, just say success.
8745 */
8746 return 0;
8747
8748 default:
8749 break;
855e1111 8750 }
1da177e4
LT		 8751 }
8752
8753 val = tr32(ofs);
8754 val &= ~enable_bit;
8755 tw32_f(ofs, val);
8756
8757 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8758 if (pci_channel_offline(tp->pdev)) {
8759 dev_err(&tp->pdev->dev,
8760 "tg3_stop_block device offline, "
8761 "ofs=%lx enable_bit=%x\n",
8762 ofs, enable_bit);
8763 return -ENODEV;
8764 }
8765
1da177e4
LT		 8766 udelay(100);
8767 val = tr32(ofs);
8768 if ((val & enable_bit) == 0)
8769 break;
8770 }
8771
b3b7d6be 8772 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8773 dev_err(&tp->pdev->dev,
8774 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8775 ofs, enable_bit);
1da177e4
LT		 8776 return -ENODEV;
8777 }
8778
8779 return 0;
8780}
8781
8782/* tp->lock is held. */
953c96e0 8783static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8784{
8785 int i, err;
8786
8787 tg3_disable_ints(tp);
8788
6d446ec3
GS		 8789 if (pci_channel_offline(tp->pdev)) {
8790 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8791 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8792 err = -ENODEV;
8793 goto err_no_dev;
8794 }
8795
1da177e4
LT		 8796 tp->rx_mode &= ~RX_MODE_ENABLE;
8797 tw32_f(MAC_RX_MODE, tp->rx_mode);
8798 udelay(10);
8799
b3b7d6be
DM		 8800 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8801 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8802 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8803 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8804 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8805 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8806
8807 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8808 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8809 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8810 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8811 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8812 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8813 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8814
8815 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8816 tw32_f(MAC_MODE, tp->mac_mode);
8817 udelay(40);
8818
8819 tp->tx_mode &= ~TX_MODE_ENABLE;
8820 tw32_f(MAC_TX_MODE, tp->tx_mode);
8821
8822 for (i = 0; i < MAX_WAIT_CNT; i++) {
8823 udelay(100);
8824 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8825 break;
8826 }
8827 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8828 dev_err(&tp->pdev->dev,
8829 "%s timed out, TX_MODE_ENABLE will not clear "
8830 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8831 err |= -ENODEV;
1da177e4
LT		 8832 }
8833
e6de8ad1 8834 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8835 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8836 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8837
8838 tw32(FTQ_RESET, 0xffffffff);
8839 tw32(FTQ_RESET, 0x00000000);
8840
b3b7d6be
DM		 8841 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8842 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8843
6d446ec3 8844err_no_dev:
f77a6a8e
MC		 8845 for (i = 0; i < tp->irq_cnt; i++) {
8846 struct tg3_napi *tnapi = &tp->napi[i];
8847 if (tnapi->hw_status)
8848 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8849 }
1da177e4 8850
1da177e4
LT		 8851 return err;
8852}
8853
ee6a99b5
MC		 8854/* Save PCI command register before chip reset */
8855static void tg3_save_pci_state(struct tg3 *tp)
8856{
8a6eac90 8857 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8858}
8859
8860/* Restore PCI state after chip reset */
8861static void tg3_restore_pci_state(struct tg3 *tp)
8862{
8863 u32 val;
8864
8865 /* Re-enable indirect register accesses. */
8866 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8867 tp->misc_host_ctrl);
8868
8869 /* Set MAX PCI retry to zero. */
8870 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8871 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8872 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8873 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8874 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8875 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8876 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8877 PCISTATE_ALLOW_APE_SHMEM_WR |
8878 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8879 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8880
8a6eac90 8881 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8882
2c55a3d0
MC		 8883 if (!tg3_flag(tp, PCI_EXPRESS)) {
8884 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8885 tp->pci_cacheline_sz);
8886 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8887 tp->pci_lat_timer);
114342f2 8888 }
5f5c51e3 8889
ee6a99b5 8890 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8891 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8892 u16 pcix_cmd;
8893
8894 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8895 &pcix_cmd);
8896 pcix_cmd &= ~PCI_X_CMD_ERO;
8897 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8898 pcix_cmd);
8899 }
ee6a99b5 8900
63c3a66f 8901 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8902
8903 /* Chip reset on 5780 will reset MSI enable bit,
8904 * so need to restore it.
8905 */
63c3a66f 8906 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8907 u16 ctrl;
8908
8909 pci_read_config_word(tp->pdev,
8910 tp->msi_cap + PCI_MSI_FLAGS,
8911 &ctrl);
8912 pci_write_config_word(tp->pdev,
8913 tp->msi_cap + PCI_MSI_FLAGS,
8914 ctrl | PCI_MSI_FLAGS_ENABLE);
8915 val = tr32(MSGINT_MODE);
8916 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8917 }
8918 }
8919}
8920
1da177e4
LT		 8921/* tp->lock is held. */
8922static int tg3_chip_reset(struct tg3 *tp)
8923{
8924 u32 val;
1ee582d8 8925 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 8926 int i, err;
1da177e4 8927
f49639e6
DM		 8928 tg3_nvram_lock(tp);
8929
77b483f1
MC		 8930 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8931
f49639e6
DM		 8932 /* No matching tg3_nvram_unlock() after this because
8933 * chip reset below will undo the nvram lock.
8934 */
8935 tp->nvram_lock_cnt = 0;
1da177e4 8936
ee6a99b5
MC		 8937 /* GRC_MISC_CFG core clock reset will clear the memory
8938 * enable bit in PCI register 4 and the MSI enable bit
8939 * on some chips, so we save relevant registers here.
8940 */
8941 tg3_save_pci_state(tp);
8942
4153577a 8943 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 8944 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 8945 tw32(GRC_FASTBOOT_PC, 0);
8946
1da177e4
LT		 8947 /*
8948 * We must avoid the readl() that normally takes place.
8949 * It locks machines, causes machine checks, and other
8950 * fun things. So, temporarily disable the 5701
8951 * hardware workaround, while we do the reset.
8952 */
1ee582d8
MC		 8953 write_op = tp->write32;
8954 if (write_op == tg3_write_flush_reg32)
8955 tp->write32 = tg3_write32;
1da177e4 8956
d18edcb2
MC		 8957 /* Prevent the irq handler from reading or writing PCI registers
8958 * during chip reset when the memory enable bit in the PCI command
8959 * register may be cleared. The chip does not generate interrupt
8960 * at this time, but the irq handler may still be called due to irq
8961 * sharing or irqpoll.
8962 */
63c3a66f 8963 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 8964 for (i = 0; i < tp->irq_cnt; i++) {
8965 struct tg3_napi *tnapi = &tp->napi[i];
8966 if (tnapi->hw_status) {
8967 tnapi->hw_status->status = 0;
8968 tnapi->hw_status->status_tag = 0;
8969 }
8970 tnapi->last_tag = 0;
8971 tnapi->last_irq_tag = 0;
b8fa2f3a 8972 }
d18edcb2 8973 smp_mb();
4f125f42
MC		 8974
8975 for (i = 0; i < tp->irq_cnt; i++)
8976 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 8977
4153577a 8978 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 8979 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8980 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8981 }
8982
1da177e4
LT		 8983 /* do the reset */
8984 val = GRC_MISC_CFG_CORECLK_RESET;
8985
63c3a66f 8986 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 8987 /* Force PCIe 1.0a mode */
4153577a 8988 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 8989 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 8990 tr32(TG3_PCIE_PHY_TSTCTL) ==
8991 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8992 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
8993
4153577a 8994 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 8995 tw32(GRC_MISC_CFG, (1 << 29));
8996 val |= (1 << 29);
8997 }
8998 }
8999
4153577a 9000 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 9001 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9002 tw32(GRC_VCPU_EXT_CTRL,
9003 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9004 }
9005
f37500d3 9006 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9007 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9008 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9009
1da177e4
LT		 9010 tw32(GRC_MISC_CFG, val);
9011
1ee582d8
MC		 9012 /* restore 5701 hardware bug workaround write method */
9013 tp->write32 = write_op;
1da177e4
LT		 9014
9015 /* Unfortunately, we have to delay before the PCI read back.
9016 * Some 575X chips even will not respond to a PCI cfg access
9017 * when the reset command is given to the chip.
9018 *
9019 * How do these hardware designers expect things to work
9020 * properly if the PCI write is posted for a long period
9021 * of time? It is always necessary to have some method by
9022 * which a register read back can occur to push the write
9023 * out which does the reset.
9024 *
9025 * For most tg3 variants the trick below was working.
9026 * Ho hum...
9027 */
9028 udelay(120);
9029
9030 /* Flush PCI posted writes. The normal MMIO registers
9031 * are inaccessible at this time so this is the only
9032 * way to make this reliably (actually, this is no longer
9033 * the case, see above). I tried to use indirect
9034 * register read/write but this upset some 5701 variants.
9035 */
9036 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9037
9038 udelay(120);
9039
0f49bfbd 9040 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9041 u16 val16;
9042
4153577a 9043 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9044 int j;
1da177e4
LT		 9045 u32 cfg_val;
9046
9047 /* Wait for link training to complete. */
86449944 9048 for (j = 0; j < 5000; j++)
1da177e4
LT		 9049 udelay(100);
9050
9051 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9052 pci_write_config_dword(tp->pdev, 0xc4,
9053 cfg_val | (1 << 15));
9054 }
5e7dfd0f 9055
e7126997 9056 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9057 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9058 /*
9059 * Older PCIe devices only support the 128 byte
9060 * MPS setting. Enforce the restriction.
5e7dfd0f 9061 */
63c3a66f 9062 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9063 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9064 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9065
5e7dfd0f 9066 /* Clear error status */
0f49bfbd 9067 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9068 PCI_EXP_DEVSTA_CED |
9069 PCI_EXP_DEVSTA_NFED |
9070 PCI_EXP_DEVSTA_FED |
9071 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9072 }
9073
ee6a99b5 9074 tg3_restore_pci_state(tp);
1da177e4 9075
63c3a66f
JP		 9076 tg3_flag_clear(tp, CHIP_RESETTING);
9077 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9078
ee6a99b5 9079 val = 0;
63c3a66f 9080 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9081 val = tr32(MEMARB_MODE);
ee6a99b5 9082 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9083
4153577a 9084 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9085 tg3_stop_fw(tp);
9086 tw32(0x5000, 0x400);
9087 }
9088
7e6c63f0
HM		 9089 if (tg3_flag(tp, IS_SSB_CORE)) {
9090 /*
9091 * BCM4785: In order to avoid repercussions from using
9092 * potentially defective internal ROM, stop the Rx RISC CPU,
9093 * which is not required.
9094 */
9095 tg3_stop_fw(tp);
9096 tg3_halt_cpu(tp, RX_CPU_BASE);
9097 }
9098
fb03a43f
NS		 9099 err = tg3_poll_fw(tp);
9100 if (err)
9101 return err;
9102
1da177e4
LT		 9103 tw32(GRC_MODE, tp->grc_mode);
9104
4153577a 9105 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9106 val = tr32(0xc4);
1da177e4
LT		 9107
9108 tw32(0xc4, val | (1 << 15));
9109 }
9110
9111 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9112 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9113 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9114 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9115 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9116 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9117 }
9118
f07e9af3 9119 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9120 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9121 val = tp->mac_mode;
f07e9af3 9122 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9123 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9124 val = tp->mac_mode;
1da177e4 9125 } else
d2394e6b
MC		 9126 val = 0;
9127
9128 tw32_f(MAC_MODE, val);
1da177e4
LT		 9129 udelay(40);
9130
77b483f1
MC		 9131 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9132
0a9140cf
MC		 9133 tg3_mdio_start(tp);
9134
63c3a66f 9135 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9136 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9137 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9138 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9139 val = tr32(0x7c00);
1da177e4
LT		 9140
9141 tw32(0x7c00, val | (1 << 25));
9142 }
9143
4153577a 9144 if (tg3_asic_rev(tp) == ASIC_REV_5720) {
d78b59f5
MC		 9145 val = tr32(TG3_CPMU_CLCK_ORIDE);
9146 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9147 }
9148
1da177e4 9149 /* Reprobe ASF enable state. */
63c3a66f 9150 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9151 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9152 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9153
63c3a66f 9154 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9155 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9156 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9157 u32 nic_cfg;
9158
9159 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9160 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9161 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9162 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9163 if (tg3_flag(tp, 5750_PLUS))
9164 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9165
9166 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9167 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9168 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9169 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9170 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9171 }
9172 }
9173
9174 return 0;
9175}
9176
65ec698d
MC		 9177static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9178static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
92feeabf 9179
1da177e4 9180/* tp->lock is held. */
953c96e0 9181static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9182{
9183 int err;
9184
9185 tg3_stop_fw(tp);
9186
944d980e 9187 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9188
b3b7d6be 9189 tg3_abort_hw(tp, silent);
1da177e4
LT		 9190 err = tg3_chip_reset(tp);
9191
953c96e0 9192 __tg3_set_mac_addr(tp, false);
daba2a63 9193
944d980e
MC		 9194 tg3_write_sig_legacy(tp, kind);
9195 tg3_write_sig_post_reset(tp, kind);
1da177e4 9196
92feeabf
MC		 9197 if (tp->hw_stats) {
9198 /* Save the stats across chip resets... */
b4017c53 9199 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9200 tg3_get_estats(tp, &tp->estats_prev);
9201
9202 /* And make sure the next sample is new data */
9203 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9204 }
9205
1da177e4
LT		 9206 if (err)
9207 return err;
9208
9209 return 0;
9210}
9211
1da177e4
LT		 9212static int tg3_set_mac_addr(struct net_device *dev, void *p)
9213{
9214 struct tg3 *tp = netdev_priv(dev);
9215 struct sockaddr *addr = p;
953c96e0
JP		 9216 int err = 0;
9217 bool skip_mac_1 = false;
1da177e4 9218
f9804ddb 9219 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9220 return -EADDRNOTAVAIL;
f9804ddb 9221
1da177e4
LT		 9222 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9223
e75f7c90
MC		 9224 if (!netif_running(dev))
9225 return 0;
9226
63c3a66f 9227 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9228 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9229
986e0aeb
MC		 9230 addr0_high = tr32(MAC_ADDR_0_HIGH);
9231 addr0_low = tr32(MAC_ADDR_0_LOW);
9232 addr1_high = tr32(MAC_ADDR_1_HIGH);
9233 addr1_low = tr32(MAC_ADDR_1_LOW);
9234
9235 /* Skip MAC addr 1 if ASF is using it. */
9236 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9237 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9238 skip_mac_1 = true;
58712ef9 9239 }
986e0aeb
MC		 9240 spin_lock_bh(&tp->lock);
9241 __tg3_set_mac_addr(tp, skip_mac_1);
9242 spin_unlock_bh(&tp->lock);
1da177e4 9243
b9ec6c1b 9244 return err;
1da177e4
LT		 9245}
9246
9247/* tp->lock is held. */
9248static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9249 dma_addr_t mapping, u32 maxlen_flags,
9250 u32 nic_addr)
9251{
9252 tg3_write_mem(tp,
9253 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9254 ((u64) mapping >> 32));
9255 tg3_write_mem(tp,
9256 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9257 ((u64) mapping & 0xffffffff));
9258 tg3_write_mem(tp,
9259 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9260 maxlen_flags);
9261
63c3a66f 9262 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9263 tg3_write_mem(tp,
9264 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9265 nic_addr);
9266}
9267
a489b6d9
MC		 9268
9269static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9270{
a489b6d9 9271 int i = 0;
b6080e12 9272
63c3a66f 9273 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9274 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9275 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9276 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9277 } else {
9278 tw32(HOSTCC_TXCOL_TICKS, 0);
9279 tw32(HOSTCC_TXMAX_FRAMES, 0);
9280 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9281
9282 for (; i < tp->txq_cnt; i++) {
9283 u32 reg;
9284
9285 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9286 tw32(reg, ec->tx_coalesce_usecs);
9287 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9288 tw32(reg, ec->tx_max_coalesced_frames);
9289 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9290 tw32(reg, ec->tx_max_coalesced_frames_irq);
9291 }
19cfaecc 9292 }
b6080e12 9293
a489b6d9
MC		 9294 for (; i < tp->irq_max - 1; i++) {
9295 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9296 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9297 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9298 }
9299}
9300
9301static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9302{
9303 int i = 0;
9304 u32 limit = tp->rxq_cnt;
9305
63c3a66f 9306 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9307 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9308 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9309 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9310 limit--;
19cfaecc 9311 } else {
b6080e12
MC		 9312 tw32(HOSTCC_RXCOL_TICKS, 0);
9313 tw32(HOSTCC_RXMAX_FRAMES, 0);
9314 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9315 }
b6080e12 9316
a489b6d9 9317 for (; i < limit; i++) {
b6080e12
MC		 9318 u32 reg;
9319
9320 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9321 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9322 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9323 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9324 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9325 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9326 }
9327
9328 for (; i < tp->irq_max - 1; i++) {
9329 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9330 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9331 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9332 }
9333}
19cfaecc 9334
a489b6d9
MC		 9335static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9336{
9337 tg3_coal_tx_init(tp, ec);
9338 tg3_coal_rx_init(tp, ec);
9339
9340 if (!tg3_flag(tp, 5705_PLUS)) {
9341 u32 val = ec->stats_block_coalesce_usecs;
9342
9343 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9344 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9345
f4a46d1f 9346 if (!tp->link_up)
a489b6d9
MC		 9347 val = 0;
9348
9349 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9350 }
15f9850d 9351}
1da177e4 9352
328947ff
NS		 9353/* tp->lock is held. */
9354static void tg3_tx_rcbs_disable(struct tg3 *tp)
9355{
9356 u32 txrcb, limit;
9357
9358 /* Disable all transmit rings but the first. */
9359 if (!tg3_flag(tp, 5705_PLUS))
9360 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9361 else if (tg3_flag(tp, 5717_PLUS))
9362 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9363 else if (tg3_flag(tp, 57765_CLASS) ||
9364 tg3_asic_rev(tp) == ASIC_REV_5762)
9365 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9366 else
9367 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9368
9369 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9370 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9371 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9372 BDINFO_FLAGS_DISABLED);
9373}
9374
32ba19ef
NS		 9375/* tp->lock is held. */
9376static void tg3_tx_rcbs_init(struct tg3 *tp)
9377{
9378 int i = 0;
9379 u32 txrcb = NIC_SRAM_SEND_RCB;
9380
9381 if (tg3_flag(tp, ENABLE_TSS))
9382 i++;
9383
9384 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9385 struct tg3_napi *tnapi = &tp->napi[i];
9386
9387 if (!tnapi->tx_ring)
9388 continue;
9389
9390 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9391 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9392 NIC_SRAM_TX_BUFFER_DESC);
9393 }
9394}
9395
328947ff
NS		 9396/* tp->lock is held. */
9397static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9398{
9399 u32 rxrcb, limit;
9400
9401 /* Disable all receive return rings but the first. */
9402 if (tg3_flag(tp, 5717_PLUS))
9403 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9404 else if (!tg3_flag(tp, 5705_PLUS))
9405 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9406 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9407 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9408 tg3_flag(tp, 57765_CLASS))
9409 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9410 else
9411 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9412
9413 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9414 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9415 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9416 BDINFO_FLAGS_DISABLED);
9417}
9418
32ba19ef
NS		 9419/* tp->lock is held. */
9420static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9421{
9422 int i = 0;
9423 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9424
9425 if (tg3_flag(tp, ENABLE_RSS))
9426 i++;
9427
9428 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9429 struct tg3_napi *tnapi = &tp->napi[i];
9430
9431 if (!tnapi->rx_rcb)
9432 continue;
9433
9434 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9435 (tp->rx_ret_ring_mask + 1) <<
9436 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9437 }
9438}
9439
2d31ecaf
MC		 9440/* tp->lock is held. */
9441static void tg3_rings_reset(struct tg3 *tp)
9442{
9443 int i;
328947ff 9444 u32 stblk;
2d31ecaf
MC		 9445 struct tg3_napi *tnapi = &tp->napi[0];
9446
328947ff 9447 tg3_tx_rcbs_disable(tp);
2d31ecaf 9448
328947ff 9449 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9450
9451 /* Disable interrupts */
9452 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9453 tp->napi[0].chk_msi_cnt = 0;
9454 tp->napi[0].last_rx_cons = 0;
9455 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9456
9457 /* Zero mailbox registers. */
63c3a66f 9458 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9459 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9460 tp->napi[i].tx_prod = 0;
9461 tp->napi[i].tx_cons = 0;
63c3a66f 9462 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9463 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9464 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9465 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9466 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9467 tp->napi[i].last_rx_cons = 0;
9468 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9469 }
63c3a66f 9470 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9471 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9472 } else {
9473 tp->napi[0].tx_prod = 0;
9474 tp->napi[0].tx_cons = 0;
9475 tw32_mailbox(tp->napi[0].prodmbox, 0);
9476 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9477 }
2d31ecaf
MC		 9478
9479 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9480 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9481 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9482 for (i = 0; i < 16; i++)
9483 tw32_tx_mbox(mbox + i * 8, 0);
9484 }
9485
2d31ecaf
MC		 9486 /* Clear status block in ram. */
9487 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9488
9489 /* Set status block DMA address */
9490 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9491 ((u64) tnapi->status_mapping >> 32));
9492 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9493 ((u64) tnapi->status_mapping & 0xffffffff));
9494
f77a6a8e 9495 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9496
f77a6a8e
MC		 9497 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9498 u64 mapping = (u64)tnapi->status_mapping;
9499 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9500 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9501 stblk += 8;
f77a6a8e
MC		 9502
9503 /* Clear status block in ram. */
9504 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9505 }
32ba19ef
NS		 9506
9507 tg3_tx_rcbs_init(tp);
9508 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9509}
9510
eb07a940
MC		 9511static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9512{
9513 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9514
63c3a66f
JP		 9515 if (!tg3_flag(tp, 5750_PLUS) ||
9516 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9517 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9518 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9519 tg3_flag(tp, 57765_PLUS))
eb07a940 9520 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9521 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9522 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9523 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9524 else
9525 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9526
9527 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9528 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9529
9530 val = min(nic_rep_thresh, host_rep_thresh);
9531 tw32(RCVBDI_STD_THRESH, val);
9532
63c3a66f 9533 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9534 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9535
63c3a66f 9536 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9537 return;
9538
513aa6ea 9539 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9540
9541 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9542
9543 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9544 tw32(RCVBDI_JUMBO_THRESH, val);
9545
63c3a66f 9546 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9547 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9548}
9549
ccd5ba9d
MC		 9550static inline u32 calc_crc(unsigned char *buf, int len)
9551{
9552 u32 reg;
9553 u32 tmp;
9554 int j, k;
9555
9556 reg = 0xffffffff;
9557
9558 for (j = 0; j < len; j++) {
9559 reg ^= buf[j];
9560
9561 for (k = 0; k < 8; k++) {
9562 tmp = reg & 0x01;
9563
9564 reg >>= 1;
9565
9566 if (tmp)
9567 reg ^= 0xedb88320;
9568 }
9569 }
9570
9571 return ~reg;
9572}
9573
9574static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9575{
9576 /* accept or reject all multicast frames */
9577 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9578 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9579 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9580 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9581}
9582
9583static void __tg3_set_rx_mode(struct net_device *dev)
9584{
9585 struct tg3 *tp = netdev_priv(dev);
9586 u32 rx_mode;
9587
9588 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9589 RX_MODE_KEEP_VLAN_TAG);
9590
9591#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9592 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9593 * flag clear.
9594 */
9595 if (!tg3_flag(tp, ENABLE_ASF))
9596 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9597#endif
9598
9599 if (dev->flags & IFF_PROMISC) {
9600 /* Promiscuous mode. */
9601 rx_mode |= RX_MODE_PROMISC;
9602 } else if (dev->flags & IFF_ALLMULTI) {
9603 /* Accept all multicast. */
9604 tg3_set_multi(tp, 1);
9605 } else if (netdev_mc_empty(dev)) {
9606 /* Reject all multicast. */
9607 tg3_set_multi(tp, 0);
9608 } else {
9609 /* Accept one or more multicast(s). */
9610 struct netdev_hw_addr *ha;
9611 u32 mc_filter[4] = { 0, };
9612 u32 regidx;
9613 u32 bit;
9614 u32 crc;
9615
9616 netdev_for_each_mc_addr(ha, dev) {
9617 crc = calc_crc(ha->addr, ETH_ALEN);
9618 bit = ~crc & 0x7f;
9619 regidx = (bit & 0x60) >> 5;
9620 bit &= 0x1f;
9621 mc_filter[regidx] |= (1 << bit);
9622 }
9623
9624 tw32(MAC_HASH_REG_0, mc_filter[0]);
9625 tw32(MAC_HASH_REG_1, mc_filter[1]);
9626 tw32(MAC_HASH_REG_2, mc_filter[2]);
9627 tw32(MAC_HASH_REG_3, mc_filter[3]);
9628 }
9629
9630 if (rx_mode != tp->rx_mode) {
9631 tp->rx_mode = rx_mode;
9632 tw32_f(MAC_RX_MODE, rx_mode);
9633 udelay(10);
9634 }
9635}
9636
9102426a 9637static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9638{
9639 int i;
9640
9641 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9642 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9643}
9644
9645static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9646{
9647 int i;
9648
9649 if (!tg3_flag(tp, SUPPORT_MSIX))
9650 return;
9651
0b3ba055 9652 if (tp->rxq_cnt == 1) {
bcebcc46 9653 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9654 return;
9655 }
9656
9657 /* Validate table against current IRQ count */
9658 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9659 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9660 break;
9661 }
9662
9663 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9664 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9665}
9666
90415477 9667static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9668{
9669 int i = 0;
9670 u32 reg = MAC_RSS_INDIR_TBL_0;
9671
9672 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9673 u32 val = tp->rss_ind_tbl[i];
9674 i++;
9675 for (; i % 8; i++) {
9676 val <<= 4;
9677 val |= tp->rss_ind_tbl[i];
9678 }
9679 tw32(reg, val);
9680 reg += 4;
9681 }
9682}
9683
9bc297ea
NS		 9684static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9685{
9686 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9687 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9688 else
9689 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9690}
9691
1da177e4 9692/* tp->lock is held. */
953c96e0 9693static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9694{
9695 u32 val, rdmac_mode;
9696 int i, err, limit;
8fea32b9 9697 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9698
9699 tg3_disable_ints(tp);
9700
9701 tg3_stop_fw(tp);
9702
9703 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9704
63c3a66f 9705 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9706 tg3_abort_hw(tp, 1);
1da177e4 9707
fdad8de4
NS		 9708 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9709 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9710 tg3_phy_pull_config(tp);
400dfbaa 9711 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9712 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9713 }
9714
400dfbaa
NS		 9715 /* Enable MAC control of LPI */
9716 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9717 tg3_setup_eee(tp);
9718
603f1173 9719 if (reset_phy)
d4d2c558
MC		 9720 tg3_phy_reset(tp);
9721
1da177e4
LT		 9722 err = tg3_chip_reset(tp);
9723 if (err)
9724 return err;
9725
9726 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9727
4153577a 9728 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9729 val = tr32(TG3_CPMU_CTRL);
9730 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9731 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9732
9733 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9734 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9735 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9736 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9737
9738 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9739 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9740 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9741 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9742
9743 val = tr32(TG3_CPMU_HST_ACC);
9744 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9745 val |= CPMU_HST_ACC_MACCLK_6_25;
9746 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9747 }
9748
4153577a 9749 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9750 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9751 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9752 PCIE_PWR_MGMT_L1_THRESH_4MS;
9753 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9754
9755 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9756 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9757
9758 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9759
f40386c8
MC		 9760 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9761 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9762 }
9763
63c3a66f 9764 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9765 u32 grc_mode = tr32(GRC_MODE);
9766
9767 /* Access the lower 1K of PL PCIE block registers. */
9768 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9769 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9770
9771 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9772 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9773 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9774
9775 tw32(GRC_MODE, grc_mode);
9776 }
9777
55086ad9 9778 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9779 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9780 u32 grc_mode = tr32(GRC_MODE);
cea46462 9781
5093eedc
MC		 9782 /* Access the lower 1K of PL PCIE block registers. */
9783 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9784 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9785
5093eedc
MC		 9786 val = tr32(TG3_PCIE_TLDLPL_PORT +
9787 TG3_PCIE_PL_LO_PHYCTL5);
9788 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9789 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9790
5093eedc
MC		 9791 tw32(GRC_MODE, grc_mode);
9792 }
a977dbe8 9793
4153577a 9794 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9795 u32 grc_mode;
9796
9797 /* Fix transmit hangs */
9798 val = tr32(TG3_CPMU_PADRNG_CTL);
9799 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9800 tw32(TG3_CPMU_PADRNG_CTL, val);
9801
9802 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9803
9804 /* Access the lower 1K of DL PCIE block registers. */
9805 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9806 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9807
9808 val = tr32(TG3_PCIE_TLDLPL_PORT +
9809 TG3_PCIE_DL_LO_FTSMAX);
9810 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9811 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9812 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9813
9814 tw32(GRC_MODE, grc_mode);
9815 }
9816
a977dbe8
MC		 9817 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9818 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9819 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9820 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9821 }
9822
1da177e4
LT		 9823 /* This works around an issue with Athlon chipsets on
9824 * B3 tigon3 silicon. This bit has no effect on any
9825 * other revision. But do not set this on PCI Express
795d01c5 9826 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9827 */
63c3a66f
JP		 9828 if (!tg3_flag(tp, CPMU_PRESENT)) {
9829 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9830 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9831 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9832 }
1da177e4 9833
4153577a 9834 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9835 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9836 val = tr32(TG3PCI_PCISTATE);
9837 val |= PCISTATE_RETRY_SAME_DMA;
9838 tw32(TG3PCI_PCISTATE, val);
9839 }
9840
63c3a66f 9841 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9842 /* Allow reads and writes to the
9843 * APE register and memory space.
9844 */
9845 val = tr32(TG3PCI_PCISTATE);
9846 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9847 PCISTATE_ALLOW_APE_SHMEM_WR |
9848 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9849 tw32(TG3PCI_PCISTATE, val);
9850 }
9851
4153577a 9852 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9853 /* Enable some hw fixes. */
9854 val = tr32(TG3PCI_MSI_DATA);
9855 val |= (1 << 26) | (1 << 28) | (1 << 29);
9856 tw32(TG3PCI_MSI_DATA, val);
9857 }
9858
9859 /* Descriptor ring init may make accesses to the
9860 * NIC SRAM area to setup the TX descriptors, so we
9861 * can only do this after the hardware has been
9862 * successfully reset.
9863 */
32d8c572
MC		 9864 err = tg3_init_rings(tp);
9865 if (err)
9866 return err;
1da177e4 9867
63c3a66f 9868 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9869 val = tr32(TG3PCI_DMA_RW_CTRL) &
9870 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9871 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9872 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9873 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9874 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9875 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9876 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9877 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9878 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9879 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9880 /* This value is determined during the probe time DMA
9881 * engine test, tg3_test_dma.
9882 */
9883 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9884 }
1da177e4
LT		 9885
9886 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9887 GRC_MODE_4X_NIC_SEND_RINGS |
9888 GRC_MODE_NO_TX_PHDR_CSUM |
9889 GRC_MODE_NO_RX_PHDR_CSUM);
9890 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 9891
9892 /* Pseudo-header checksum is done by hardware logic and not
9893 * the offload processers, so make the chip do the pseudo-
9894 * header checksums on receive. For transmit it is more
9895 * convenient to do the pseudo-header checksum in software
9896 * as Linux does that on transmit for us in all cases.
9897 */
9898 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 9899
fb4ce8ad
MC		 9900 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9901 if (tp->rxptpctl)
9902 tw32(TG3_RX_PTP_CTL,
9903 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9904
9905 if (tg3_flag(tp, PTP_CAPABLE))
9906 val |= GRC_MODE_TIME_SYNC_ENABLE;
9907
9908 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 9909
9910 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9911 val = tr32(GRC_MISC_CFG);
9912 val &= ~0xff;
9913 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9914 tw32(GRC_MISC_CFG, val);
9915
9916 /* Initialize MBUF/DESC pool. */
63c3a66f 9917 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 9918 /* Do nothing. */
4153577a 9919 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 9920 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 9921 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 9922 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
9923 else
9924 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
9925 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
9926 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 9927 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 9928 int fw_len;
9929
077f849d 9930 fw_len = tp->fw_len;
1da177e4
LT		 9931 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
9932 tw32(BUFMGR_MB_POOL_ADDR,
9933 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
9934 tw32(BUFMGR_MB_POOL_SIZE,
9935 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
9936 }
1da177e4 9937
0f893dc6 9938 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 9939 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9940 tp->bufmgr_config.mbuf_read_dma_low_water);
9941 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9942 tp->bufmgr_config.mbuf_mac_rx_low_water);
9943 tw32(BUFMGR_MB_HIGH_WATER,
9944 tp->bufmgr_config.mbuf_high_water);
9945 } else {
9946 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9947 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
9948 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9949 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
9950 tw32(BUFMGR_MB_HIGH_WATER,
9951 tp->bufmgr_config.mbuf_high_water_jumbo);
9952 }
9953 tw32(BUFMGR_DMA_LOW_WATER,
9954 tp->bufmgr_config.dma_low_water);
9955 tw32(BUFMGR_DMA_HIGH_WATER,
9956 tp->bufmgr_config.dma_high_water);
9957
d309a46e 9958 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 9959 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 9960 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a
JP		 9961 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
9962 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
9963 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 9964 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 9965 tw32(BUFMGR_MODE, val);
1da177e4
LT		 9966 for (i = 0; i < 2000; i++) {
9967 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
9968 break;
9969 udelay(10);
9970 }
9971 if (i >= 2000) {
05dbe005 9972 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 9973 return -ENODEV;
9974 }
9975
4153577a 9976 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 9977 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 9978
eb07a940 9979 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 9980
9981 /* Initialize TG3_BDINFO's at:
9982 * RCVDBDI_STD_BD: standard eth size rx ring
9983 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9984 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9985 *
9986 * like so:
9987 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9988 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9989 * ring attribute flags
9990 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9991 *
9992 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9993 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9994 *
9995 * The size of each ring is fixed in the firmware, but the location is
9996 * configurable.
9997 */
9998 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 9999 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 10000 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10001 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 10002 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 10003 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10004 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 10005
fdb72b38 10006 /* Disable the mini ring */
63c3a66f 10007 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10008 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10009 BDINFO_FLAGS_DISABLED);
10010
fdb72b38
MC		 10011 /* Program the jumbo buffer descriptor ring control
10012 * blocks on those devices that have them.
10013 */
4153577a 10014 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10015 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10016
63c3a66f 10017 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10018 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10019 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10020 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10021 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10022 val = TG3_RX_JMB_RING_SIZE(tp) <<
10023 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10024 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10025 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10026 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10027 tg3_flag(tp, 57765_CLASS) ||
4153577a 10028 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10029 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10030 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10031 } else {
10032 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10033 BDINFO_FLAGS_DISABLED);
10034 }
10035
63c3a66f 10036 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10037 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10038 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10039 val |= (TG3_RX_STD_DMA_SZ << 2);
10040 } else
04380d40 10041 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10042 } else
de9f5230 10043 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10044
10045 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10046
411da640 10047 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10048 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10049
63c3a66f
JP		 10050 tpr->rx_jmb_prod_idx =
10051 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10052 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10053
2d31ecaf
MC		 10054 tg3_rings_reset(tp);
10055
1da177e4 10056 /* Initialize MAC address and backoff seed. */
953c96e0 10057 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10058
10059 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10060 tw32(MAC_RX_MTU_SIZE,
10061 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10062
10063 /* The slot time is changed by tg3_setup_phy if we
10064 * run at gigabit with half duplex.
10065 */
f2096f94
MC		 10066 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10067 (6 << TX_LENGTHS_IPG_SHIFT) |
10068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10069
4153577a
JP		 10070 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10071 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10072 val |= tr32(MAC_TX_LENGTHS) &
10073 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10074 TX_LENGTHS_CNT_DWN_VAL_MSK);
10075
10076 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10077
10078 /* Receive rules. */
10079 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10080 tw32(RCVLPC_CONFIG, 0x0181);
10081
10082 /* Calculate RDMAC_MODE setting early, we need it to determine
10083 * the RCVLPC_STATE_ENABLE mask.
10084 */
10085 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10086 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10087 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10088 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10089 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10090
4153577a 10091 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10092 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10093
4153577a
JP		 10094 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10095 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10096 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10097 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10098 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10099 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10100
4153577a
JP		 10101 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10102 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10103 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10104 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10105 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10106 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10107 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10108 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10109 }
10110 }
10111
63c3a66f 10112 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10113 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10114
4153577a 10115 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10116 tp->dma_limit = 0;
10117 if (tp->dev->mtu <= ETH_DATA_LEN) {
10118 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10119 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10120 }
10121 }
10122
63c3a66f
JP		 10123 if (tg3_flag(tp, HW_TSO_1) ||
10124 tg3_flag(tp, HW_TSO_2) ||
10125 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10126 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10127
108a6c16 10128 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10129 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10130 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10131 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10132
4153577a
JP		 10133 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10134 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10135 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10136
4153577a
JP		 10137 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10138 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10139 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10140 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10141 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10142 u32 tgtreg;
10143
4153577a 10144 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10145 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10146 else
10147 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10148
10149 val = tr32(tgtreg);
4153577a
JP		 10150 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10151 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10152 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10153 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10154 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10155 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10156 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10157 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10158 }
c65a17f4 10159 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10160 }
10161
4153577a
JP		 10162 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10163 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10164 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10165 u32 tgtreg;
10166
4153577a 10167 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10168 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10169 else
10170 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10171
10172 val = tr32(tgtreg);
10173 tw32(tgtreg, val |
d309a46e
MC		 10174 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10175 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10176 }
10177
1da177e4 10178 /* Receive/send statistics. */
63c3a66f 10179 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10180 val = tr32(RCVLPC_STATS_ENABLE);
10181 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10182 tw32(RCVLPC_STATS_ENABLE, val);
10183 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10184 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10185 val = tr32(RCVLPC_STATS_ENABLE);
10186 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10187 tw32(RCVLPC_STATS_ENABLE, val);
10188 } else {
10189 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10190 }
10191 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10192 tw32(SNDDATAI_STATSENAB, 0xffffff);
10193 tw32(SNDDATAI_STATSCTRL,
10194 (SNDDATAI_SCTRL_ENABLE |
10195 SNDDATAI_SCTRL_FASTUPD));
10196
10197 /* Setup host coalescing engine. */
10198 tw32(HOSTCC_MODE, 0);
10199 for (i = 0; i < 2000; i++) {
10200 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10201 break;
10202 udelay(10);
10203 }
10204
d244c892 10205 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10206
63c3a66f 10207 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10208 /* Status/statistics block address. See tg3_timer,
10209 * the tg3_periodic_fetch_stats call there, and
10210 * tg3_get_stats to see how this works for 5705/5750 chips.
10211 */
1da177e4
LT		 10212 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10213 ((u64) tp->stats_mapping >> 32));
10214 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10215 ((u64) tp->stats_mapping & 0xffffffff));
10216 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10217
1da177e4 10218 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10219
10220 /* Clear statistics and status block memory areas */
10221 for (i = NIC_SRAM_STATS_BLK;
10222 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10223 i += sizeof(u32)) {
10224 tg3_write_mem(tp, i, 0);
10225 udelay(40);
10226 }
1da177e4
LT		 10227 }
10228
10229 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10230
10231 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10232 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10233 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10234 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10235
f07e9af3
MC		 10236 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10237 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10238 /* reset to prevent losing 1st rx packet intermittently */
10239 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10240 udelay(10);
10241 }
10242
3bda1258 10243 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10244 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10245 MAC_MODE_FHDE_ENABLE;
10246 if (tg3_flag(tp, ENABLE_APE))
10247 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10248 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10249 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10250 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10251 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10252 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10253 udelay(40);
10254
314fba34 10255 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10256 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10257 * register to preserve the GPIO settings for LOMs. The GPIOs,
10258 * whether used as inputs or outputs, are set by boot code after
10259 * reset.
10260 */
63c3a66f 10261 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10262 u32 gpio_mask;
10263
9d26e213
MC		 10264 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10265 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10266 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10267
4153577a 10268 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10269 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10270 GRC_LCLCTRL_GPIO_OUTPUT3;
10271
4153577a 10272 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10273 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10274
aaf84465 10275 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10276 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10277
10278 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10279 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10280 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10281 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10282 }
1da177e4
LT		 10283 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10284 udelay(100);
10285
c3b5003b 10286 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10287 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10288 val |= MSGINT_MODE_ENABLE;
10289 if (tp->irq_cnt > 1)
10290 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10291 if (!tg3_flag(tp, 1SHOT_MSI))
10292 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10293 tw32(MSGINT_MODE, val);
10294 }
10295
63c3a66f 10296 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10297 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10298 udelay(40);
10299 }
10300
10301 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10302 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10303 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10304 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10305 WDMAC_MODE_LNGREAD_ENAB);
10306
4153577a
JP		 10307 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10308 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10309 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10310 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10311 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10312 /* nothing */
10313 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10314 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10315 val |= WDMAC_MODE_RX_ACCEL;
10316 }
10317 }
10318
d9ab5ad1 10319 /* Enable host coalescing bug fix */
63c3a66f 10320 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10321 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10322
4153577a 10323 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10324 val |= WDMAC_MODE_BURST_ALL_DATA;
10325
1da177e4
LT		 10326 tw32_f(WDMAC_MODE, val);
10327 udelay(40);
10328
63c3a66f 10329 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10330 u16 pcix_cmd;
10331
10332 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10333 &pcix_cmd);
4153577a 10334 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10335 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10336 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10337 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10338 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10339 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10340 }
9974a356
MC		 10341 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10342 pcix_cmd);
1da177e4
LT		 10343 }
10344
10345 tw32_f(RDMAC_MODE, rdmac_mode);
10346 udelay(40);
10347
9bc297ea
NS		 10348 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10349 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10350 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10351 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10352 break;
10353 }
10354 if (i < TG3_NUM_RDMA_CHANNELS) {
10355 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10356 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10357 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10358 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10359 }
10360 }
10361
1da177e4 10362 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10363 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10364 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10365
4153577a 10366 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10367 tw32(SNDDATAC_MODE,
10368 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10369 else
10370 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10371
1da177e4
LT		 10372 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10373 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10374 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10375 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10376 val |= RCVDBDI_MODE_LRG_RING_SZ;
10377 tw32(RCVDBDI_MODE, val);
1da177e4 10378 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10379 if (tg3_flag(tp, HW_TSO_1) ||
10380 tg3_flag(tp, HW_TSO_2) ||
10381 tg3_flag(tp, HW_TSO_3))
1da177e4 10382 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10383 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10384 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10385 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10386 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10387 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10388
4153577a 10389 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10390 err = tg3_load_5701_a0_firmware_fix(tp);
10391 if (err)
10392 return err;
10393 }
10394
c4dab506
NS		 10395 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10396 /* Ignore any errors for the firmware download. If download
10397 * fails, the device will operate with EEE disabled
10398 */
10399 tg3_load_57766_firmware(tp);
10400 }
10401
63c3a66f 10402 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10403 err = tg3_load_tso_firmware(tp);
10404 if (err)
10405 return err;
10406 }
1da177e4
LT		 10407
10408 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10409
63c3a66f 10410 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10411 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10412 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10413
4153577a
JP		 10414 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10415 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10416 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10417 tp->tx_mode &= ~val;
10418 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10419 }
10420
1da177e4
LT		 10421 tw32_f(MAC_TX_MODE, tp->tx_mode);
10422 udelay(100);
10423
63c3a66f 10424 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10425 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10426
10427 /* Setup the "secret" hash key. */
10428 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10429 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10430 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10431 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10432 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10433 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10434 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10435 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10436 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10437 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10438 }
10439
1da177e4 10440 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10441 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10442 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10443
378b72c8
NS		 10444 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10445 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10446
63c3a66f 10447 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10448 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10449 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10450 RX_MODE_RSS_IPV6_HASH_EN |
10451 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10452 RX_MODE_RSS_IPV4_HASH_EN |
10453 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10454
1da177e4
LT		 10455 tw32_f(MAC_RX_MODE, tp->rx_mode);
10456 udelay(10);
10457
1da177e4
LT		 10458 tw32(MAC_LED_CTRL, tp->led_ctrl);
10459
10460 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10461 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10462 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10463 udelay(10);
10464 }
10465 tw32_f(MAC_RX_MODE, tp->rx_mode);
10466 udelay(10);
10467
f07e9af3 10468 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10469 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10470 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10471 /* Set drive transmission level to 1.2V */
10472 /* only if the signal pre-emphasis bit is not set */
10473 val = tr32(MAC_SERDES_CFG);
10474 val &= 0xfffff000;
10475 val |= 0x880;
10476 tw32(MAC_SERDES_CFG, val);
10477 }
4153577a 10478 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10479 tw32(MAC_SERDES_CFG, 0x616000);
10480 }
10481
10482 /* Prevent chip from dropping frames when flow control
10483 * is enabled.
10484 */
55086ad9 10485 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10486 val = 1;
10487 else
10488 val = 2;
10489 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10490
4153577a 10491 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10492 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10493 /* Use hardware link auto-negotiation */
63c3a66f 10494 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10495 }
10496
f07e9af3 10497 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10498 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10499 u32 tmp;
10500
10501 tmp = tr32(SERDES_RX_CTRL);
10502 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10503 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10504 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10505 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10506 }
10507
63c3a66f 10508 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10509 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10510 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10511
953c96e0 10512 err = tg3_setup_phy(tp, false);
dd477003
MC		 10513 if (err)
10514 return err;
1da177e4 10515
f07e9af3
MC		 10516 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10517 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10518 u32 tmp;
10519
10520 /* Clear CRC stats. */
10521 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10522 tg3_writephy(tp, MII_TG3_TEST1,
10523 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10524 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10525 }
1da177e4
LT		 10526 }
10527 }
10528
10529 __tg3_set_rx_mode(tp->dev);
10530
10531 /* Initialize receive rules. */
10532 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10533 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10534 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10535 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10536
63c3a66f 10537 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10538 limit = 8;
10539 else
10540 limit = 16;
63c3a66f 10541 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10542 limit -= 4;
10543 switch (limit) {
10544 case 16:
10545 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10546 case 15:
10547 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10548 case 14:
10549 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10550 case 13:
10551 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10552 case 12:
10553 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10554 case 11:
10555 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10556 case 10:
10557 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10558 case 9:
10559 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10560 case 8:
10561 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10562 case 7:
10563 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10564 case 6:
10565 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10566 case 5:
10567 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10568 case 4:
10569 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10570 case 3:
10571 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10572 case 2:
10573 case 1:
10574
10575 default:
10576 break;
855e1111 10577 }
1da177e4 10578
63c3a66f 10579 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10580 /* Write our heartbeat update interval to APE. */
10581 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10582 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10583
1da177e4
LT		 10584 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10585
1da177e4
LT		 10586 return 0;
10587}
10588
10589/* Called at device open time to get the chip ready for
10590 * packet processing. Invoked with tp->lock held.
10591 */
953c96e0 10592static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10593{
df465abf
NS		 10594 /* Chip may have been just powered on. If so, the boot code may still
10595 * be running initialization. Wait for it to finish to avoid races in
10596 * accessing the hardware.
10597 */
10598 tg3_enable_register_access(tp);
10599 tg3_poll_fw(tp);
10600
1da177e4
LT		 10601 tg3_switch_clocks(tp);
10602
10603 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10604
2f751b67 10605 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10606}
10607
aed93e0b
MC		 10608static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10609{
10610 int i;
10611
10612 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10613 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10614
10615 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10616 off += len;
10617
10618 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10619 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10620 memset(ocir, 0, TG3_OCIR_LEN);
10621 }
10622}
10623
10624/* sysfs attributes for hwmon */
10625static ssize_t tg3_show_temp(struct device *dev,
10626 struct device_attribute *devattr, char *buf)
10627{
10628 struct pci_dev *pdev = to_pci_dev(dev);
10629 struct net_device *netdev = pci_get_drvdata(pdev);
10630 struct tg3 *tp = netdev_priv(netdev);
10631 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10632 u32 temperature;
10633
10634 spin_lock_bh(&tp->lock);
10635 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10636 sizeof(temperature));
10637 spin_unlock_bh(&tp->lock);
10638 return sprintf(buf, "%u\n", temperature);
10639}
10640
10641
10642static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10643 TG3_TEMP_SENSOR_OFFSET);
10644static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10645 TG3_TEMP_CAUTION_OFFSET);
10646static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10647 TG3_TEMP_MAX_OFFSET);
10648
10649static struct attribute *tg3_attributes[] = {
10650 &sensor_dev_attr_temp1_input.dev_attr.attr,
10651 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10652 &sensor_dev_attr_temp1_max.dev_attr.attr,
10653 NULL
10654};
10655
10656static const struct attribute_group tg3_group = {
10657 .attrs = tg3_attributes,
10658};
10659
aed93e0b
MC		 10660static void tg3_hwmon_close(struct tg3 *tp)
10661{
aed93e0b
MC		 10662 if (tp->hwmon_dev) {
10663 hwmon_device_unregister(tp->hwmon_dev);
10664 tp->hwmon_dev = NULL;
10665 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
10666 }
aed93e0b
MC		 10667}
10668
10669static void tg3_hwmon_open(struct tg3 *tp)
10670{
aed93e0b
MC		 10671 int i, err;
10672 u32 size = 0;
10673 struct pci_dev *pdev = tp->pdev;
10674 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10675
10676 tg3_sd_scan_scratchpad(tp, ocirs);
10677
10678 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10679 if (!ocirs[i].src_data_length)
10680 continue;
10681
10682 size += ocirs[i].src_hdr_length;
10683 size += ocirs[i].src_data_length;
10684 }
10685
10686 if (!size)
10687 return;
10688
10689 /* Register hwmon sysfs hooks */
10690 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
10691 if (err) {
10692 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
10693 return;
10694 }
10695
10696 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
10697 if (IS_ERR(tp->hwmon_dev)) {
10698 tp->hwmon_dev = NULL;
10699 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10700 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
10701 }
aed93e0b
MC		 10702}
10703
10704
1da177e4
LT		 10705#define TG3_STAT_ADD32(PSTAT, REG) \
10706do { u32 __val = tr32(REG); \
10707 (PSTAT)->low += __val; \
10708 if ((PSTAT)->low < __val) \
10709 (PSTAT)->high += 1; \
10710} while (0)
10711
10712static void tg3_periodic_fetch_stats(struct tg3 *tp)
10713{
10714 struct tg3_hw_stats *sp = tp->hw_stats;
10715
f4a46d1f 10716 if (!tp->link_up)
1da177e4
LT		 10717 return;
10718
10719 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10720 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10721 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10722 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10723 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10724 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10725 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10726 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10727 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10728 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10729 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10730 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10731 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10732 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10733 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10734 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10735 u32 val;
10736
10737 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10738 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10739 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10740 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10741 }
1da177e4
LT		 10742
10743 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10744 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10745 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10746 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10747 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10748 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10749 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10750 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10751 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10752 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10753 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10754 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10755 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10756 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10757
10758 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a
JP		 10759 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10760 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10761 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10762 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10763 } else {
10764 u32 val = tr32(HOSTCC_FLOW_ATTN);
10765 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10766 if (val) {
10767 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10768 sp->rx_discards.low += val;
10769 if (sp->rx_discards.low < val)
10770 sp->rx_discards.high += 1;
10771 }
10772 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10773 }
463d305b 10774 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10775}
10776
0e6cf6a9
MC		 10777static void tg3_chk_missed_msi(struct tg3 *tp)
10778{
10779 u32 i;
10780
10781 for (i = 0; i < tp->irq_cnt; i++) {
10782 struct tg3_napi *tnapi = &tp->napi[i];
10783
10784 if (tg3_has_work(tnapi)) {
10785 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10786 tnapi->last_tx_cons == tnapi->tx_cons) {
10787 if (tnapi->chk_msi_cnt < 1) {
10788 tnapi->chk_msi_cnt++;
10789 return;
10790 }
7f230735 10791 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10792 }
10793 }
10794 tnapi->chk_msi_cnt = 0;
10795 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10796 tnapi->last_tx_cons = tnapi->tx_cons;
10797 }
10798}
10799
1da177e4
LT		 10800static void tg3_timer(unsigned long __opaque)
10801{
10802 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10803
5b190624 10804 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10805 goto restart_timer;
10806
f47c11ee 10807 spin_lock(&tp->lock);
1da177e4 10808
4153577a 10809 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10810 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10811 tg3_chk_missed_msi(tp);
10812
7e6c63f0
HM		 10813 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10814 /* BCM4785: Flush posted writes from GbE to host memory. */
10815 tr32(HOSTCC_MODE);
10816 }
10817
63c3a66f 10818 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10819 /* All of this garbage is because when using non-tagged
10820 * IRQ status the mailbox/status_block protocol the chip
10821 * uses with the cpu is race prone.
10822 */
898a56f8 10823 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10824 tw32(GRC_LOCAL_CTRL,
10825 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10826 } else {
10827 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10828 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10829 }
1da177e4 10830
fac9b83e 10831 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10832 spin_unlock(&tp->lock);
db219973 10833 tg3_reset_task_schedule(tp);
5b190624 10834 goto restart_timer;
fac9b83e 10835 }
1da177e4
LT		 10836 }
10837
1da177e4
LT		 10838 /* This part only runs once per second. */
10839 if (!--tp->timer_counter) {
63c3a66f 10840 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10841 tg3_periodic_fetch_stats(tp);
10842
b0c5943f
MC		 10843 if (tp->setlpicnt && !--tp->setlpicnt)
10844 tg3_phy_eee_enable(tp);
52b02d04 10845
63c3a66f 10846 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10847 u32 mac_stat;
10848 int phy_event;
10849
10850 mac_stat = tr32(MAC_STATUS);
10851
10852 phy_event = 0;
f07e9af3 10853 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10854 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10855 phy_event = 1;
10856 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10857 phy_event = 1;
10858
10859 if (phy_event)
953c96e0 10860 tg3_setup_phy(tp, false);
63c3a66f 10861 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10862 u32 mac_stat = tr32(MAC_STATUS);
10863 int need_setup = 0;
10864
f4a46d1f 10865 if (tp->link_up &&
1da177e4
LT		 10866 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10867 need_setup = 1;
10868 }
f4a46d1f 10869 if (!tp->link_up &&
1da177e4
LT		 10870 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10871 MAC_STATUS_SIGNAL_DET))) {
10872 need_setup = 1;
10873 }
10874 if (need_setup) {
3d3ebe74
MC		 10875 if (!tp->serdes_counter) {
10876 tw32_f(MAC_MODE,
10877 (tp->mac_mode &
10878 ~MAC_MODE_PORT_MODE_MASK));
10879 udelay(40);
10880 tw32_f(MAC_MODE, tp->mac_mode);
10881 udelay(40);
10882 }
953c96e0 10883 tg3_setup_phy(tp, false);
1da177e4 10884 }
f07e9af3 10885 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10886 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10887 tg3_serdes_parallel_detect(tp);
57d8b880 10888 }
1da177e4
LT		 10889
10890 tp->timer_counter = tp->timer_multiplier;
10891 }
10892
130b8e4d
MC		 10893 /* Heartbeat is only sent once every 2 seconds.
10894 *
10895 * The heartbeat is to tell the ASF firmware that the host
10896 * driver is still alive. In the event that the OS crashes,
10897 * ASF needs to reset the hardware to free up the FIFO space
10898 * that may be filled with rx packets destined for the host.
10899 * If the FIFO is full, ASF will no longer function properly.
10900 *
10901 * Unintended resets have been reported on real time kernels
10902 * where the timer doesn't run on time. Netpoll will also have
10903 * same problem.
10904 *
10905 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10906 * to check the ring condition when the heartbeat is expiring
10907 * before doing the reset. This will prevent most unintended
10908 * resets.
10909 */
1da177e4 10910 if (!--tp->asf_counter) {
63c3a66f 10911 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 10912 tg3_wait_for_event_ack(tp);
10913
bbadf503 10914 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 10915 FWCMD_NICDRV_ALIVE3);
bbadf503 10916 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 10917 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10918 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 10919
10920 tg3_generate_fw_event(tp);
1da177e4
LT		 10921 }
10922 tp->asf_counter = tp->asf_multiplier;
10923 }
10924
f47c11ee 10925 spin_unlock(&tp->lock);
1da177e4 10926
f475f163 10927restart_timer:
1da177e4
LT		 10928 tp->timer.expires = jiffies + tp->timer_offset;
10929 add_timer(&tp->timer);
10930}
10931
229b1ad1 10932static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 10933{
10934 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 10935 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 10936 !tg3_flag(tp, 57765_CLASS))
10937 tp->timer_offset = HZ;
10938 else
10939 tp->timer_offset = HZ / 10;
10940
10941 BUG_ON(tp->timer_offset > HZ);
10942
10943 tp->timer_multiplier = (HZ / tp->timer_offset);
10944 tp->asf_multiplier = (HZ / tp->timer_offset) *
10945 TG3_FW_UPDATE_FREQ_SEC;
10946
10947 init_timer(&tp->timer);
10948 tp->timer.data = (unsigned long) tp;
10949 tp->timer.function = tg3_timer;
10950}
10951
10952static void tg3_timer_start(struct tg3 *tp)
10953{
10954 tp->asf_counter = tp->asf_multiplier;
10955 tp->timer_counter = tp->timer_multiplier;
10956
10957 tp->timer.expires = jiffies + tp->timer_offset;
10958 add_timer(&tp->timer);
10959}
10960
10961static void tg3_timer_stop(struct tg3 *tp)
10962{
10963 del_timer_sync(&tp->timer);
10964}
10965
10966/* Restart hardware after configuration changes, self-test, etc.
10967 * Invoked with tp->lock held.
10968 */
953c96e0 10969static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 10970 __releases(tp->lock)
10971 __acquires(tp->lock)
10972{
10973 int err;
10974
10975 err = tg3_init_hw(tp, reset_phy);
10976 if (err) {
10977 netdev_err(tp->dev,
10978 "Failed to re-initialize device, aborting\n");
10979 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10980 tg3_full_unlock(tp);
10981 tg3_timer_stop(tp);
10982 tp->irq_sync = 0;
10983 tg3_napi_enable(tp);
10984 dev_close(tp->dev);
10985 tg3_full_lock(tp, 0);
10986 }
10987 return err;
10988}
10989
10990static void tg3_reset_task(struct work_struct *work)
10991{
10992 struct tg3 *tp = container_of(work, struct tg3, reset_task);
10993 int err;
10994
10995 tg3_full_lock(tp, 0);
10996
10997 if (!netif_running(tp->dev)) {
10998 tg3_flag_clear(tp, RESET_TASK_PENDING);
10999 tg3_full_unlock(tp);
11000 return;
11001 }
11002
11003 tg3_full_unlock(tp);
11004
11005 tg3_phy_stop(tp);
11006
11007 tg3_netif_stop(tp);
11008
11009 tg3_full_lock(tp, 1);
11010
11011 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11012 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11013 tp->write32_rx_mbox = tg3_write_flush_reg32;
11014 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11015 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11016 }
11017
11018 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11019 err = tg3_init_hw(tp, true);
21f7638e
MC		 11020 if (err)
11021 goto out;
11022
11023 tg3_netif_start(tp);
11024
11025out:
11026 tg3_full_unlock(tp);
11027
11028 if (!err)
11029 tg3_phy_start(tp);
11030
11031 tg3_flag_clear(tp, RESET_TASK_PENDING);
11032}
11033
4f125f42 11034static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11035{
7d12e780 11036 irq_handler_t fn;
fcfa0a32 11037 unsigned long flags;
4f125f42
MC		 11038 char *name;
11039 struct tg3_napi *tnapi = &tp->napi[irq_num];
11040
11041 if (tp->irq_cnt == 1)
11042 name = tp->dev->name;
11043 else {
11044 name = &tnapi->irq_lbl[0];
11045 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
11046 name[IFNAMSIZ-1] = 0;
11047 }
fcfa0a32 11048
63c3a66f 11049 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11050 fn = tg3_msi;
63c3a66f 11051 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11052 fn = tg3_msi_1shot;
ab392d2d 11053 flags = 0;
fcfa0a32
MC		 11054 } else {
11055 fn = tg3_interrupt;
63c3a66f 11056 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11057 fn = tg3_interrupt_tagged;
ab392d2d 11058 flags = IRQF_SHARED;
fcfa0a32 11059 }
4f125f42
MC		 11060
11061 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11062}
11063
7938109f
MC		 11064static int tg3_test_interrupt(struct tg3 *tp)
11065{
09943a18 11066 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11067 struct net_device *dev = tp->dev;
b16250e3 11068 int err, i, intr_ok = 0;
f6eb9b1f 11069 u32 val;
7938109f 11070
d4bc3927
MC		 11071 if (!netif_running(dev))
11072 return -ENODEV;
11073
7938109f
MC		 11074 tg3_disable_ints(tp);
11075
4f125f42 11076 free_irq(tnapi->irq_vec, tnapi);
7938109f 11077
f6eb9b1f
MC		 11078 /*
11079 * Turn off MSI one shot mode. Otherwise this test has no
11080 * observable way to know whether the interrupt was delivered.
11081 */
3aa1cdf8 11082 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11083 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11084 tw32(MSGINT_MODE, val);
11085 }
11086
4f125f42 11087 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11088 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11089 if (err)
11090 return err;
11091
898a56f8 11092 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11093 tg3_enable_ints(tp);
11094
11095 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11096 tnapi->coal_now);
7938109f
MC		 11097
11098 for (i = 0; i < 5; i++) {
b16250e3
MC		 11099 u32 int_mbox, misc_host_ctrl;
11100
898a56f8 11101 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11102 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11103
11104 if ((int_mbox != 0) ||
11105 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11106 intr_ok = 1;
7938109f 11107 break;
b16250e3
MC		 11108 }
11109
3aa1cdf8
MC		 11110 if (tg3_flag(tp, 57765_PLUS) &&
11111 tnapi->hw_status->status_tag != tnapi->last_tag)
11112 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11113
7938109f
MC		 11114 msleep(10);
11115 }
11116
11117 tg3_disable_ints(tp);
11118
4f125f42 11119 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11120
4f125f42 11121 err = tg3_request_irq(tp, 0);
7938109f
MC		 11122
11123 if (err)
11124 return err;
11125
f6eb9b1f
MC		 11126 if (intr_ok) {
11127 /* Reenable MSI one shot mode. */
5b39de91 11128 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11129 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11130 tw32(MSGINT_MODE, val);
11131 }
7938109f 11132 return 0;
f6eb9b1f 11133 }
7938109f
MC		 11134
11135 return -EIO;
11136}
11137
11138/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11139 * successfully restored
11140 */
11141static int tg3_test_msi(struct tg3 *tp)
11142{
7938109f
MC		 11143 int err;
11144 u16 pci_cmd;
11145
63c3a66f 11146 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11147 return 0;
11148
11149 /* Turn off SERR reporting in case MSI terminates with Master
11150 * Abort.
11151 */
11152 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11153 pci_write_config_word(tp->pdev, PCI_COMMAND,
11154 pci_cmd & ~PCI_COMMAND_SERR);
11155
11156 err = tg3_test_interrupt(tp);
11157
11158 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11159
11160 if (!err)
11161 return 0;
11162
11163 /* other failures */
11164 if (err != -EIO)
11165 return err;
11166
11167 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11168 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11169 "to INTx mode. Please report this failure to the PCI "
11170 "maintainer and include system chipset information\n");
7938109f 11171
4f125f42 11172 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11173
7938109f
MC		 11174 pci_disable_msi(tp->pdev);
11175
63c3a66f 11176 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11177 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11178
4f125f42 11179 err = tg3_request_irq(tp, 0);
7938109f
MC		 11180 if (err)
11181 return err;
11182
11183 /* Need to reset the chip because the MSI cycle may have terminated
11184 * with Master Abort.
11185 */
f47c11ee 11186 tg3_full_lock(tp, 1);
7938109f 11187
944d980e 11188 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11189 err = tg3_init_hw(tp, true);
7938109f 11190
f47c11ee 11191 tg3_full_unlock(tp);
7938109f
MC		 11192
11193 if (err)
4f125f42 11194 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11195
11196 return err;
11197}
11198
9e9fd12d
MC		 11199static int tg3_request_firmware(struct tg3 *tp)
11200{
77997ea3 11201 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11202
11203 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11204 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11205 tp->fw_needed);
9e9fd12d
MC		 11206 return -ENOENT;
11207 }
11208
77997ea3 11209 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11210
11211 /* Firmware blob starts with version numbers, followed by
11212 * start address and _full_ length including BSS sections
11213 * (which must be longer than the actual data, of course
11214 */
11215
77997ea3
NS		 11216 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11217 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11218 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11219 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11220 release_firmware(tp->fw);
11221 tp->fw = NULL;
11222 return -EINVAL;
11223 }
11224
11225 /* We no longer need firmware; we have it. */
11226 tp->fw_needed = NULL;
11227 return 0;
11228}
11229
9102426a 11230static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11231{
9102426a 11232 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11233
9102426a 11234 if (irq_cnt > 1) {
c3b5003b
MC		 11235 /* We want as many rx rings enabled as there are cpus.
11236 * In multiqueue MSI-X mode, the first MSI-X vector
11237 * only deals with link interrupts, etc, so we add
11238 * one to the number of vectors we are requesting.
11239 */
9102426a 11240 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11241 }
679563f4 11242
9102426a
MC		 11243 return irq_cnt;
11244}
11245
11246static bool tg3_enable_msix(struct tg3 *tp)
11247{
11248 int i, rc;
86449944 11249 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11250
0968169c
MC		 11251 tp->txq_cnt = tp->txq_req;
11252 tp->rxq_cnt = tp->rxq_req;
11253 if (!tp->rxq_cnt)
11254 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11255 if (tp->rxq_cnt > tp->rxq_max)
11256 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11257
11258 /* Disable multiple TX rings by default. Simple round-robin hardware
11259 * scheduling of the TX rings can cause starvation of rings with
11260 * small packets when other rings have TSO or jumbo packets.
11261 */
11262 if (!tp->txq_req)
11263 tp->txq_cnt = 1;
9102426a
MC		 11264
11265 tp->irq_cnt = tg3_irq_count(tp);
11266
679563f4
MC		 11267 for (i = 0; i < tp->irq_max; i++) {
11268 msix_ent[i].entry = i;
11269 msix_ent[i].vector = 0;
11270 }
11271
11272 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
2430b031
MC		 11273 if (rc < 0) {
11274 return false;
11275 } else if (rc != 0) {
679563f4
MC		 11276 if (pci_enable_msix(tp->pdev, msix_ent, rc))
11277 return false;
05dbe005
JP		 11278 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11279 tp->irq_cnt, rc);
679563f4 11280 tp->irq_cnt = rc;
49a359e3 11281 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11282 if (tp->txq_cnt)
11283 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11284 }
11285
11286 for (i = 0; i < tp->irq_max; i++)
11287 tp->napi[i].irq_vec = msix_ent[i].vector;
11288
49a359e3 11289 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11290 pci_disable_msix(tp->pdev);
11291 return false;
11292 }
b92b9040 11293
9102426a
MC		 11294 if (tp->irq_cnt == 1)
11295 return true;
d78b59f5 11296
9102426a
MC		 11297 tg3_flag_set(tp, ENABLE_RSS);
11298
11299 if (tp->txq_cnt > 1)
11300 tg3_flag_set(tp, ENABLE_TSS);
11301
11302 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11303
679563f4
MC		 11304 return true;
11305}
11306
07b0173c
MC		 11307static void tg3_ints_init(struct tg3 *tp)
11308{
63c3a66f
JP		 11309 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11310 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11311 /* All MSI supporting chips should support tagged
11312 * status. Assert that this is the case.
11313 */
5129c3a3
MC		 11314 netdev_warn(tp->dev,
11315 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11316 goto defcfg;
07b0173c 11317 }
4f125f42 11318
63c3a66f
JP		 11319 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11320 tg3_flag_set(tp, USING_MSIX);
11321 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11322 tg3_flag_set(tp, USING_MSI);
679563f4 11323
63c3a66f 11324 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11325 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11326 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11327 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11328 if (!tg3_flag(tp, 1SHOT_MSI))
11329 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11330 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11331 }
11332defcfg:
63c3a66f 11333 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11334 tp->irq_cnt = 1;
11335 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11336 }
11337
11338 if (tp->irq_cnt == 1) {
11339 tp->txq_cnt = 1;
11340 tp->rxq_cnt = 1;
2ddaad39 11341 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11342 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11343 }
07b0173c
MC		 11344}
11345
11346static void tg3_ints_fini(struct tg3 *tp)
11347{
63c3a66f 11348 if (tg3_flag(tp, USING_MSIX))
679563f4 11349 pci_disable_msix(tp->pdev);
63c3a66f 11350 else if (tg3_flag(tp, USING_MSI))
679563f4 11351 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11352 tg3_flag_clear(tp, USING_MSI);
11353 tg3_flag_clear(tp, USING_MSIX);
11354 tg3_flag_clear(tp, ENABLE_RSS);
11355 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11356}
11357
be947307
MC		 11358static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11359 bool init)
1da177e4 11360{
d8f4cd38 11361 struct net_device *dev = tp->dev;
4f125f42 11362 int i, err;
1da177e4 11363
679563f4
MC		 11364 /*
11365 * Setup interrupts first so we know how
11366 * many NAPI resources to allocate
11367 */
11368 tg3_ints_init(tp);
11369
90415477 11370 tg3_rss_check_indir_tbl(tp);
bcebcc46 11371
1da177e4
LT		 11372 /* The placement of this call is tied
11373 * to the setup and use of Host TX descriptors.
11374 */
11375 err = tg3_alloc_consistent(tp);
11376 if (err)
4a5f46f2 11377 goto out_ints_fini;
88b06bc2 11378
66cfd1bd
MC		 11379 tg3_napi_init(tp);
11380
fed97810 11381 tg3_napi_enable(tp);
1da177e4 11382
4f125f42
MC		 11383 for (i = 0; i < tp->irq_cnt; i++) {
11384 struct tg3_napi *tnapi = &tp->napi[i];
11385 err = tg3_request_irq(tp, i);
11386 if (err) {
5bc09186
MC		 11387 for (i--; i >= 0; i--) {
11388 tnapi = &tp->napi[i];
4f125f42 11389 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11390 }
4a5f46f2 11391 goto out_napi_fini;
4f125f42
MC		 11392 }
11393 }
1da177e4 11394
f47c11ee 11395 tg3_full_lock(tp, 0);
1da177e4 11396
2e460fc0
NS		 11397 if (init)
11398 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11399
d8f4cd38 11400 err = tg3_init_hw(tp, reset_phy);
1da177e4 11401 if (err) {
944d980e 11402 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11403 tg3_free_rings(tp);
1da177e4
LT		 11404 }
11405
f47c11ee 11406 tg3_full_unlock(tp);
1da177e4 11407
07b0173c 11408 if (err)
4a5f46f2 11409 goto out_free_irq;
1da177e4 11410
d8f4cd38 11411 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11412 err = tg3_test_msi(tp);
fac9b83e 11413
7938109f 11414 if (err) {
f47c11ee 11415 tg3_full_lock(tp, 0);
944d980e 11416 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11417 tg3_free_rings(tp);
f47c11ee 11418 tg3_full_unlock(tp);
7938109f 11419
4a5f46f2 11420 goto out_napi_fini;
7938109f 11421 }
fcfa0a32 11422
63c3a66f 11423 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11424 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11425
f6eb9b1f
MC		 11426 tw32(PCIE_TRANSACTION_CFG,
11427 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11428 }
7938109f
MC		 11429 }
11430
b02fd9e3
MC		 11431 tg3_phy_start(tp);
11432
aed93e0b
MC		 11433 tg3_hwmon_open(tp);
11434
f47c11ee 11435 tg3_full_lock(tp, 0);
1da177e4 11436
21f7638e 11437 tg3_timer_start(tp);
63c3a66f 11438 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11439 tg3_enable_ints(tp);
11440
be947307
MC		 11441 if (init)
11442 tg3_ptp_init(tp);
11443 else
11444 tg3_ptp_resume(tp);
11445
11446
f47c11ee 11447 tg3_full_unlock(tp);
1da177e4 11448
fe5f5787 11449 netif_tx_start_all_queues(dev);
1da177e4 11450
06c03c02
MB		 11451 /*
11452 * Reset loopback feature if it was turned on while the device was down
11453 * make sure that it's installed properly now.
11454 */
11455 if (dev->features & NETIF_F_LOOPBACK)
11456 tg3_set_loopback(dev, dev->features);
11457
1da177e4 11458 return 0;
07b0173c 11459
4a5f46f2 11460out_free_irq:
4f125f42
MC		 11461 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11462 struct tg3_napi *tnapi = &tp->napi[i];
11463 free_irq(tnapi->irq_vec, tnapi);
11464 }
07b0173c 11465
4a5f46f2 11466out_napi_fini:
fed97810 11467 tg3_napi_disable(tp);
66cfd1bd 11468 tg3_napi_fini(tp);
07b0173c 11469 tg3_free_consistent(tp);
679563f4 11470
4a5f46f2 11471out_ints_fini:
679563f4 11472 tg3_ints_fini(tp);
d8f4cd38 11473
07b0173c 11474 return err;
1da177e4
LT		 11475}
11476
65138594 11477static void tg3_stop(struct tg3 *tp)
1da177e4 11478{
4f125f42 11479 int i;
1da177e4 11480
db219973 11481 tg3_reset_task_cancel(tp);
bd473da3 11482 tg3_netif_stop(tp);
1da177e4 11483
21f7638e 11484 tg3_timer_stop(tp);
1da177e4 11485
aed93e0b
MC		 11486 tg3_hwmon_close(tp);
11487
24bb4fb6
MC		 11488 tg3_phy_stop(tp);
11489
f47c11ee 11490 tg3_full_lock(tp, 1);
1da177e4
LT		 11491
11492 tg3_disable_ints(tp);
11493
944d980e 11494 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11495 tg3_free_rings(tp);
63c3a66f 11496 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11497
f47c11ee 11498 tg3_full_unlock(tp);
1da177e4 11499
4f125f42
MC		 11500 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11501 struct tg3_napi *tnapi = &tp->napi[i];
11502 free_irq(tnapi->irq_vec, tnapi);
11503 }
07b0173c
MC		 11504
11505 tg3_ints_fini(tp);
1da177e4 11506
66cfd1bd
MC		 11507 tg3_napi_fini(tp);
11508
1da177e4 11509 tg3_free_consistent(tp);
65138594
MC		 11510}
11511
d8f4cd38
MC		 11512static int tg3_open(struct net_device *dev)
11513{
11514 struct tg3 *tp = netdev_priv(dev);
11515 int err;
11516
11517 if (tp->fw_needed) {
11518 err = tg3_request_firmware(tp);
c4dab506
NS		 11519 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11520 if (err) {
11521 netdev_warn(tp->dev, "EEE capability disabled\n");
11522 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11523 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11524 netdev_warn(tp->dev, "EEE capability restored\n");
11525 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11526 }
11527 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11528 if (err)
11529 return err;
11530 } else if (err) {
11531 netdev_warn(tp->dev, "TSO capability disabled\n");
11532 tg3_flag_clear(tp, TSO_CAPABLE);
11533 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11534 netdev_notice(tp->dev, "TSO capability restored\n");
11535 tg3_flag_set(tp, TSO_CAPABLE);
11536 }
11537 }
11538
f4a46d1f 11539 tg3_carrier_off(tp);
d8f4cd38
MC		 11540
11541 err = tg3_power_up(tp);
11542 if (err)
11543 return err;
11544
11545 tg3_full_lock(tp, 0);
11546
11547 tg3_disable_ints(tp);
11548 tg3_flag_clear(tp, INIT_COMPLETE);
11549
11550 tg3_full_unlock(tp);
11551
942d1af0
NS		 11552 err = tg3_start(tp,
11553 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11554 true, true);
d8f4cd38
MC		 11555 if (err) {
11556 tg3_frob_aux_power(tp, false);
11557 pci_set_power_state(tp->pdev, PCI_D3hot);
11558 }
be947307 11559
7d41e49a
MC		 11560 if (tg3_flag(tp, PTP_CAPABLE)) {
11561 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11562 &tp->pdev->dev);
11563 if (IS_ERR(tp->ptp_clock))
11564 tp->ptp_clock = NULL;
11565 }
11566
07b0173c 11567 return err;
1da177e4
LT		 11568}
11569
1da177e4
LT		 11570static int tg3_close(struct net_device *dev)
11571{
11572 struct tg3 *tp = netdev_priv(dev);
11573
be947307
MC		 11574 tg3_ptp_fini(tp);
11575
65138594 11576 tg3_stop(tp);
1da177e4 11577
92feeabf
MC		 11578 /* Clear stats across close / open calls */
11579 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11580 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11581
5137a2ee 11582 tg3_power_down_prepare(tp);
bc1c7567 11583
f4a46d1f 11584 tg3_carrier_off(tp);
bc1c7567 11585
1da177e4
LT		 11586 return 0;
11587}
11588
511d2224 11589static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11590{
11591 return ((u64)val->high << 32) | ((u64)val->low);
11592}
11593
65ec698d 11594static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11595{
11596 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11597
f07e9af3 11598 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11599 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11600 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11601 u32 val;
11602
569a5df8
MC		 11603 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11604 tg3_writephy(tp, MII_TG3_TEST1,
11605 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11606 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11607 } else
11608 val = 0;
1da177e4
LT		 11609
11610 tp->phy_crc_errors += val;
11611
11612 return tp->phy_crc_errors;
11613 }
11614
11615 return get_stat64(&hw_stats->rx_fcs_errors);
11616}
11617
11618#define ESTAT_ADD(member) \
11619 estats->member = old_estats->member + \
511d2224 11620 get_stat64(&hw_stats->member)
1da177e4 11621
65ec698d 11622static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11623{
1da177e4
LT		 11624 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11625 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11626
1da177e4
LT		 11627 ESTAT_ADD(rx_octets);
11628 ESTAT_ADD(rx_fragments);
11629 ESTAT_ADD(rx_ucast_packets);
11630 ESTAT_ADD(rx_mcast_packets);
11631 ESTAT_ADD(rx_bcast_packets);
11632 ESTAT_ADD(rx_fcs_errors);
11633 ESTAT_ADD(rx_align_errors);
11634 ESTAT_ADD(rx_xon_pause_rcvd);
11635 ESTAT_ADD(rx_xoff_pause_rcvd);
11636 ESTAT_ADD(rx_mac_ctrl_rcvd);
11637 ESTAT_ADD(rx_xoff_entered);
11638 ESTAT_ADD(rx_frame_too_long_errors);
11639 ESTAT_ADD(rx_jabbers);
11640 ESTAT_ADD(rx_undersize_packets);
11641 ESTAT_ADD(rx_in_length_errors);
11642 ESTAT_ADD(rx_out_length_errors);
11643 ESTAT_ADD(rx_64_or_less_octet_packets);
11644 ESTAT_ADD(rx_65_to_127_octet_packets);
11645 ESTAT_ADD(rx_128_to_255_octet_packets);
11646 ESTAT_ADD(rx_256_to_511_octet_packets);
11647 ESTAT_ADD(rx_512_to_1023_octet_packets);
11648 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11649 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11650 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11651 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11652 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11653
11654 ESTAT_ADD(tx_octets);
11655 ESTAT_ADD(tx_collisions);
11656 ESTAT_ADD(tx_xon_sent);
11657 ESTAT_ADD(tx_xoff_sent);
11658 ESTAT_ADD(tx_flow_control);
11659 ESTAT_ADD(tx_mac_errors);
11660 ESTAT_ADD(tx_single_collisions);
11661 ESTAT_ADD(tx_mult_collisions);
11662 ESTAT_ADD(tx_deferred);
11663 ESTAT_ADD(tx_excessive_collisions);
11664 ESTAT_ADD(tx_late_collisions);
11665 ESTAT_ADD(tx_collide_2times);
11666 ESTAT_ADD(tx_collide_3times);
11667 ESTAT_ADD(tx_collide_4times);
11668 ESTAT_ADD(tx_collide_5times);
11669 ESTAT_ADD(tx_collide_6times);
11670 ESTAT_ADD(tx_collide_7times);
11671 ESTAT_ADD(tx_collide_8times);
11672 ESTAT_ADD(tx_collide_9times);
11673 ESTAT_ADD(tx_collide_10times);
11674 ESTAT_ADD(tx_collide_11times);
11675 ESTAT_ADD(tx_collide_12times);
11676 ESTAT_ADD(tx_collide_13times);
11677 ESTAT_ADD(tx_collide_14times);
11678 ESTAT_ADD(tx_collide_15times);
11679 ESTAT_ADD(tx_ucast_packets);
11680 ESTAT_ADD(tx_mcast_packets);
11681 ESTAT_ADD(tx_bcast_packets);
11682 ESTAT_ADD(tx_carrier_sense_errors);
11683 ESTAT_ADD(tx_discards);
11684 ESTAT_ADD(tx_errors);
11685
11686 ESTAT_ADD(dma_writeq_full);
11687 ESTAT_ADD(dma_write_prioq_full);
11688 ESTAT_ADD(rxbds_empty);
11689 ESTAT_ADD(rx_discards);
11690 ESTAT_ADD(rx_errors);
11691 ESTAT_ADD(rx_threshold_hit);
11692
11693 ESTAT_ADD(dma_readq_full);
11694 ESTAT_ADD(dma_read_prioq_full);
11695 ESTAT_ADD(tx_comp_queue_full);
11696
11697 ESTAT_ADD(ring_set_send_prod_index);
11698 ESTAT_ADD(ring_status_update);
11699 ESTAT_ADD(nic_irqs);
11700 ESTAT_ADD(nic_avoided_irqs);
11701 ESTAT_ADD(nic_tx_threshold_hit);
11702
4452d099 11703 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11704}
11705
65ec698d 11706static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11707{
511d2224 11708 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11709 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11710
1da177e4
LT		 11711 stats->rx_packets = old_stats->rx_packets +
11712 get_stat64(&hw_stats->rx_ucast_packets) +
11713 get_stat64(&hw_stats->rx_mcast_packets) +
11714 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11715
1da177e4
LT		 11716 stats->tx_packets = old_stats->tx_packets +
11717 get_stat64(&hw_stats->tx_ucast_packets) +
11718 get_stat64(&hw_stats->tx_mcast_packets) +
11719 get_stat64(&hw_stats->tx_bcast_packets);
11720
11721 stats->rx_bytes = old_stats->rx_bytes +
11722 get_stat64(&hw_stats->rx_octets);
11723 stats->tx_bytes = old_stats->tx_bytes +
11724 get_stat64(&hw_stats->tx_octets);
11725
11726 stats->rx_errors = old_stats->rx_errors +
4f63b877 11727 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11728 stats->tx_errors = old_stats->tx_errors +
11729 get_stat64(&hw_stats->tx_errors) +
11730 get_stat64(&hw_stats->tx_mac_errors) +
11731 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11732 get_stat64(&hw_stats->tx_discards);
11733
11734 stats->multicast = old_stats->multicast +
11735 get_stat64(&hw_stats->rx_mcast_packets);
11736 stats->collisions = old_stats->collisions +
11737 get_stat64(&hw_stats->tx_collisions);
11738
11739 stats->rx_length_errors = old_stats->rx_length_errors +
11740 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11741 get_stat64(&hw_stats->rx_undersize_packets);
11742
11743 stats->rx_over_errors = old_stats->rx_over_errors +
11744 get_stat64(&hw_stats->rxbds_empty);
11745 stats->rx_frame_errors = old_stats->rx_frame_errors +
11746 get_stat64(&hw_stats->rx_align_errors);
11747 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11748 get_stat64(&hw_stats->tx_discards);
11749 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11750 get_stat64(&hw_stats->tx_carrier_sense_errors);
11751
11752 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11753 tg3_calc_crc_errors(tp);
1da177e4 11754
4f63b877
JL		 11755 stats->rx_missed_errors = old_stats->rx_missed_errors +
11756 get_stat64(&hw_stats->rx_discards);
11757
b0057c51 11758 stats->rx_dropped = tp->rx_dropped;
48855432 11759 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11760}
11761
1da177e4
LT		 11762static int tg3_get_regs_len(struct net_device *dev)
11763{
97bd8e49 11764 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11765}
11766
11767static void tg3_get_regs(struct net_device *dev,
11768 struct ethtool_regs *regs, void *_p)
11769{
1da177e4 11770 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11771
11772 regs->version = 0;
11773
97bd8e49 11774 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11775
80096068 11776 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11777 return;
11778
f47c11ee 11779 tg3_full_lock(tp, 0);
1da177e4 11780
97bd8e49 11781 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11782
f47c11ee 11783 tg3_full_unlock(tp);
1da177e4
LT		 11784}
11785
11786static int tg3_get_eeprom_len(struct net_device *dev)
11787{
11788 struct tg3 *tp = netdev_priv(dev);
11789
11790 return tp->nvram_size;
11791}
11792
1da177e4
LT		 11793static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11794{
11795 struct tg3 *tp = netdev_priv(dev);
11796 int ret;
11797 u8 *pd;
b9fc7dc5 11798 u32 i, offset, len, b_offset, b_count;
a9dc529d 11799 __be32 val;
1da177e4 11800
63c3a66f 11801 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11802 return -EINVAL;
11803
1da177e4
LT		 11804 offset = eeprom->offset;
11805 len = eeprom->len;
11806 eeprom->len = 0;
11807
11808 eeprom->magic = TG3_EEPROM_MAGIC;
11809
11810 if (offset & 3) {
11811 /* adjustments to start on required 4 byte boundary */
11812 b_offset = offset & 3;
11813 b_count = 4 - b_offset;
11814 if (b_count > len) {
11815 /* i.e. offset=1 len=2 */
11816 b_count = len;
11817 }
a9dc529d 11818 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 11819 if (ret)
11820 return ret;
be98da6a 11821 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11822 len -= b_count;
11823 offset += b_count;
c6cdf436 11824 eeprom->len += b_count;
1da177e4
LT		 11825 }
11826
25985edc 11827 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11828 pd = &data[eeprom->len];
11829 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11830 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 11831 if (ret) {
11832 eeprom->len += i;
11833 return ret;
11834 }
1da177e4
LT		 11835 memcpy(pd + i, &val, 4);
11836 }
11837 eeprom->len += i;
11838
11839 if (len & 3) {
11840 /* read last bytes not ending on 4 byte boundary */
11841 pd = &data[eeprom->len];
11842 b_count = len & 3;
11843 b_offset = offset + len - b_count;
a9dc529d 11844 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 11845 if (ret)
11846 return ret;
b9fc7dc5 11847 memcpy(pd, &val, b_count);
1da177e4
LT		 11848 eeprom->len += b_count;
11849 }
11850 return 0;
11851}
11852
1da177e4
LT		 11853static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11854{
11855 struct tg3 *tp = netdev_priv(dev);
11856 int ret;
b9fc7dc5 11857 u32 offset, len, b_offset, odd_len;
1da177e4 11858 u8 *buf;
a9dc529d 11859 __be32 start, end;
1da177e4 11860
63c3a66f 11861 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 11862 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 11863 return -EINVAL;
11864
11865 offset = eeprom->offset;
11866 len = eeprom->len;
11867
11868 if ((b_offset = (offset & 3))) {
11869 /* adjustments to start on required 4 byte boundary */
a9dc529d 11870 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 11871 if (ret)
11872 return ret;
1da177e4
LT		 11873 len += b_offset;
11874 offset &= ~3;
1c8594b4
MC		 11875 if (len < 4)
11876 len = 4;
1da177e4
LT		 11877 }
11878
11879 odd_len = 0;
1c8594b4 11880 if (len & 3) {
1da177e4
LT		 11881 /* adjustments to end on required 4 byte boundary */
11882 odd_len = 1;
11883 len = (len + 3) & ~3;
a9dc529d 11884 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 11885 if (ret)
11886 return ret;
1da177e4
LT		 11887 }
11888
11889 buf = data;
11890 if (b_offset || odd_len) {
11891 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 11892 if (!buf)
1da177e4
LT		 11893 return -ENOMEM;
11894 if (b_offset)
11895 memcpy(buf, &start, 4);
11896 if (odd_len)
11897 memcpy(buf+len-4, &end, 4);
11898 memcpy(buf + b_offset, data, eeprom->len);
11899 }
11900
11901 ret = tg3_nvram_write_block(tp, offset, len, buf);
11902
11903 if (buf != data)
11904 kfree(buf);
11905
11906 return ret;
11907}
11908
11909static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11910{
b02fd9e3
MC		 11911 struct tg3 *tp = netdev_priv(dev);
11912
63c3a66f 11913 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11914 struct phy_device *phydev;
f07e9af3 11915 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11916 return -EAGAIN;
3f0e3ad7
MC		 11917 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11918 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 11919 }
6aa20a22 11920
1da177e4
LT		 11921 cmd->supported = (SUPPORTED_Autoneg);
11922
f07e9af3 11923 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 11924 cmd->supported |= (SUPPORTED_1000baseT_Half |
11925 SUPPORTED_1000baseT_Full);
11926
f07e9af3 11927 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 11928 cmd->supported |= (SUPPORTED_100baseT_Half |
11929 SUPPORTED_100baseT_Full |
11930 SUPPORTED_10baseT_Half |
11931 SUPPORTED_10baseT_Full |
3bebab59 11932 SUPPORTED_TP);
ef348144
KK		 11933 cmd->port = PORT_TP;
11934 } else {
1da177e4 11935 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 11936 cmd->port = PORT_FIBRE;
11937 }
6aa20a22 11938
1da177e4 11939 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 11940 if (tg3_flag(tp, PAUSE_AUTONEG)) {
11941 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
11942 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11943 cmd->advertising |= ADVERTISED_Pause;
11944 } else {
11945 cmd->advertising |= ADVERTISED_Pause |
11946 ADVERTISED_Asym_Pause;
11947 }
11948 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11949 cmd->advertising |= ADVERTISED_Asym_Pause;
11950 }
11951 }
f4a46d1f 11952 if (netif_running(dev) && tp->link_up) {
70739497 11953 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 11954 cmd->duplex = tp->link_config.active_duplex;
859edb26 11955 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 11956 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11957 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
11958 cmd->eth_tp_mdix = ETH_TP_MDI_X;
11959 else
11960 cmd->eth_tp_mdix = ETH_TP_MDI;
11961 }
64c22182 11962 } else {
e740522e
MC		 11963 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
11964 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 11965 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 11966 }
882e9793 11967 cmd->phy_address = tp->phy_addr;
7e5856bd 11968 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 11969 cmd->autoneg = tp->link_config.autoneg;
11970 cmd->maxtxpkt = 0;
11971 cmd->maxrxpkt = 0;
11972 return 0;
11973}
6aa20a22 11974
1da177e4
LT		 11975static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11976{
11977 struct tg3 *tp = netdev_priv(dev);
25db0338 11978 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 11979
63c3a66f 11980 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11981 struct phy_device *phydev;
f07e9af3 11982 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11983 return -EAGAIN;
3f0e3ad7
MC		 11984 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11985 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 11986 }
11987
7e5856bd
MC		 11988 if (cmd->autoneg != AUTONEG_ENABLE &&
11989 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 11990 return -EINVAL;
7e5856bd
MC		 11991
11992 if (cmd->autoneg == AUTONEG_DISABLE &&
11993 cmd->duplex != DUPLEX_FULL &&
11994 cmd->duplex != DUPLEX_HALF)
37ff238d 11995 return -EINVAL;
1da177e4 11996
7e5856bd
MC		 11997 if (cmd->autoneg == AUTONEG_ENABLE) {
11998 u32 mask = ADVERTISED_Autoneg |
11999 ADVERTISED_Pause |
12000 ADVERTISED_Asym_Pause;
12001
f07e9af3 12002 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 12003 mask |= ADVERTISED_1000baseT_Half |
12004 ADVERTISED_1000baseT_Full;
12005
f07e9af3 12006 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12007 mask |= ADVERTISED_100baseT_Half |
12008 ADVERTISED_100baseT_Full |
12009 ADVERTISED_10baseT_Half |
12010 ADVERTISED_10baseT_Full |
12011 ADVERTISED_TP;
12012 else
12013 mask |= ADVERTISED_FIBRE;
12014
12015 if (cmd->advertising & ~mask)
12016 return -EINVAL;
12017
12018 mask &= (ADVERTISED_1000baseT_Half |
12019 ADVERTISED_1000baseT_Full |
12020 ADVERTISED_100baseT_Half |
12021 ADVERTISED_100baseT_Full |
12022 ADVERTISED_10baseT_Half |
12023 ADVERTISED_10baseT_Full);
12024
12025 cmd->advertising &= mask;
12026 } else {
f07e9af3 12027 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12028 if (speed != SPEED_1000)
7e5856bd
MC		 12029 return -EINVAL;
12030
12031 if (cmd->duplex != DUPLEX_FULL)
12032 return -EINVAL;
12033 } else {
25db0338
DD		 12034 if (speed != SPEED_100 &&
12035 speed != SPEED_10)
7e5856bd
MC		 12036 return -EINVAL;
12037 }
12038 }
12039
f47c11ee 12040 tg3_full_lock(tp, 0);
1da177e4
LT		 12041
12042 tp->link_config.autoneg = cmd->autoneg;
12043 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12044 tp->link_config.advertising = (cmd->advertising |
12045 ADVERTISED_Autoneg);
e740522e
MC		 12046 tp->link_config.speed = SPEED_UNKNOWN;
12047 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12048 } else {
12049 tp->link_config.advertising = 0;
25db0338 12050 tp->link_config.speed = speed;
1da177e4 12051 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12052 }
6aa20a22 12053
fdad8de4
NS		 12054 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12055
ce20f161
NS		 12056 tg3_warn_mgmt_link_flap(tp);
12057
1da177e4 12058 if (netif_running(dev))
953c96e0 12059 tg3_setup_phy(tp, true);
1da177e4 12060
f47c11ee 12061 tg3_full_unlock(tp);
6aa20a22 12062
1da177e4
LT		 12063 return 0;
12064}
6aa20a22 12065
1da177e4
LT		 12066static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12067{
12068 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12069
68aad78c
RJ		 12070 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12071 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12072 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12073 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12074}
6aa20a22 12075
1da177e4
LT		 12076static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12077{
12078 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12079
63c3a66f 12080 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12081 wol->supported = WAKE_MAGIC;
12082 else
12083 wol->supported = 0;
1da177e4 12084 wol->wolopts = 0;
63c3a66f 12085 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12086 wol->wolopts = WAKE_MAGIC;
12087 memset(&wol->sopass, 0, sizeof(wol->sopass));
12088}
6aa20a22 12089
1da177e4
LT		 12090static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12091{
12092 struct tg3 *tp = netdev_priv(dev);
12dac075 12093 struct device *dp = &tp->pdev->dev;
6aa20a22 12094
1da177e4
LT		 12095 if (wol->wolopts & ~WAKE_MAGIC)
12096 return -EINVAL;
12097 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12098 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12099 return -EINVAL;
6aa20a22 12100
f2dc0d18
RW		 12101 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12102
f47c11ee 12103 spin_lock_bh(&tp->lock);
f2dc0d18 12104 if (device_may_wakeup(dp))
63c3a66f 12105 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12106 else
63c3a66f 12107 tg3_flag_clear(tp, WOL_ENABLE);
f47c11ee 12108 spin_unlock_bh(&tp->lock);
6aa20a22 12109
1da177e4
LT		 12110 return 0;
12111}
6aa20a22 12112
1da177e4
LT		 12113static u32 tg3_get_msglevel(struct net_device *dev)
12114{
12115 struct tg3 *tp = netdev_priv(dev);
12116 return tp->msg_enable;
12117}
6aa20a22 12118
1da177e4
LT		 12119static void tg3_set_msglevel(struct net_device *dev, u32 value)
12120{
12121 struct tg3 *tp = netdev_priv(dev);
12122 tp->msg_enable = value;
12123}
6aa20a22 12124
1da177e4
LT		 12125static int tg3_nway_reset(struct net_device *dev)
12126{
12127 struct tg3 *tp = netdev_priv(dev);
1da177e4 12128 int r;
6aa20a22 12129
1da177e4
LT		 12130 if (!netif_running(dev))
12131 return -EAGAIN;
12132
f07e9af3 12133 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12134 return -EINVAL;
12135
ce20f161
NS		 12136 tg3_warn_mgmt_link_flap(tp);
12137
63c3a66f 12138 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12139 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12140 return -EAGAIN;
3f0e3ad7 12141 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 12142 } else {
12143 u32 bmcr;
12144
12145 spin_lock_bh(&tp->lock);
12146 r = -EINVAL;
12147 tg3_readphy(tp, MII_BMCR, &bmcr);
12148 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12149 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12150 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12151 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12152 BMCR_ANENABLE);
12153 r = 0;
12154 }
12155 spin_unlock_bh(&tp->lock);
1da177e4 12156 }
6aa20a22 12157
1da177e4
LT		 12158 return r;
12159}
6aa20a22 12160
1da177e4
LT		 12161static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12162{
12163 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12164
2c49a44d 12165 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12166 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12167 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12168 else
12169 ering->rx_jumbo_max_pending = 0;
12170
12171 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12172
12173 ering->rx_pending = tp->rx_pending;
63c3a66f 12174 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12175 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12176 else
12177 ering->rx_jumbo_pending = 0;
12178
f3f3f27e 12179 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12180}
6aa20a22 12181
1da177e4
LT		 12182static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12183{
12184 struct tg3 *tp = netdev_priv(dev);
646c9edd 12185 int i, irq_sync = 0, err = 0;
6aa20a22 12186
2c49a44d
MC		 12187 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12188 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12189 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12190 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12191 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12192 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12193 return -EINVAL;
6aa20a22 12194
bbe832c0 12195 if (netif_running(dev)) {
b02fd9e3 12196 tg3_phy_stop(tp);
1da177e4 12197 tg3_netif_stop(tp);
bbe832c0
MC		 12198 irq_sync = 1;
12199 }
1da177e4 12200
bbe832c0 12201 tg3_full_lock(tp, irq_sync);
6aa20a22 12202
1da177e4
LT		 12203 tp->rx_pending = ering->rx_pending;
12204
63c3a66f 12205 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12206 tp->rx_pending > 63)
12207 tp->rx_pending = 63;
12208 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12209
6fd45cb8 12210 for (i = 0; i < tp->irq_max; i++)
646c9edd 12211 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12212
12213 if (netif_running(dev)) {
944d980e 12214 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12215 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12216 if (!err)
12217 tg3_netif_start(tp);
1da177e4
LT		 12218 }
12219
f47c11ee 12220 tg3_full_unlock(tp);
6aa20a22 12221
b02fd9e3
MC		 12222 if (irq_sync && !err)
12223 tg3_phy_start(tp);
12224
b9ec6c1b 12225 return err;
1da177e4 12226}
6aa20a22 12227
1da177e4
LT		 12228static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12229{
12230 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12231
63c3a66f 12232 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12233
4a2db503 12234 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12235 epause->rx_pause = 1;
12236 else
12237 epause->rx_pause = 0;
12238
4a2db503 12239 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12240 epause->tx_pause = 1;
12241 else
12242 epause->tx_pause = 0;
1da177e4 12243}
6aa20a22 12244
1da177e4
LT		 12245static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12246{
12247 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12248 int err = 0;
6aa20a22 12249
ce20f161
NS		 12250 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12251 tg3_warn_mgmt_link_flap(tp);
12252
63c3a66f 12253 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12254 u32 newadv;
12255 struct phy_device *phydev;
1da177e4 12256
2712168f 12257 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 12258
2712168f
MC		 12259 if (!(phydev->supported & SUPPORTED_Pause) ||
12260 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12261 (epause->rx_pause != epause->tx_pause)))
2712168f 12262 return -EINVAL;
1da177e4 12263
2712168f
MC		 12264 tp->link_config.flowctrl = 0;
12265 if (epause->rx_pause) {
12266 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12267
12268 if (epause->tx_pause) {
12269 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12270 newadv = ADVERTISED_Pause;
b02fd9e3 12271 } else
2712168f
MC		 12272 newadv = ADVERTISED_Pause |
12273 ADVERTISED_Asym_Pause;
12274 } else if (epause->tx_pause) {
12275 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12276 newadv = ADVERTISED_Asym_Pause;
12277 } else
12278 newadv = 0;
12279
12280 if (epause->autoneg)
63c3a66f 12281 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12282 else
63c3a66f 12283 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12284
f07e9af3 12285 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12286 u32 oldadv = phydev->advertising &
12287 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12288 if (oldadv != newadv) {
12289 phydev->advertising &=
12290 ~(ADVERTISED_Pause |
12291 ADVERTISED_Asym_Pause);
12292 phydev->advertising |= newadv;
12293 if (phydev->autoneg) {
12294 /*
12295 * Always renegotiate the link to
12296 * inform our link partner of our
12297 * flow control settings, even if the
12298 * flow control is forced. Let
12299 * tg3_adjust_link() do the final
12300 * flow control setup.
12301 */
12302 return phy_start_aneg(phydev);
b02fd9e3 12303 }
b02fd9e3 12304 }
b02fd9e3 12305
2712168f 12306 if (!epause->autoneg)
b02fd9e3 12307 tg3_setup_flow_control(tp, 0, 0);
2712168f 12308 } else {
c6700ce2 12309 tp->link_config.advertising &=
2712168f
MC		 12310 ~(ADVERTISED_Pause |
12311 ADVERTISED_Asym_Pause);
c6700ce2 12312 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12313 }
12314 } else {
12315 int irq_sync = 0;
12316
12317 if (netif_running(dev)) {
12318 tg3_netif_stop(tp);
12319 irq_sync = 1;
12320 }
12321
12322 tg3_full_lock(tp, irq_sync);
12323
12324 if (epause->autoneg)
63c3a66f 12325 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12326 else
63c3a66f 12327 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12328 if (epause->rx_pause)
e18ce346 12329 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12330 else
e18ce346 12331 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12332 if (epause->tx_pause)
e18ce346 12333 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12334 else
e18ce346 12335 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12336
12337 if (netif_running(dev)) {
12338 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12339 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12340 if (!err)
12341 tg3_netif_start(tp);
12342 }
12343
12344 tg3_full_unlock(tp);
12345 }
6aa20a22 12346
fdad8de4
NS		 12347 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12348
b9ec6c1b 12349 return err;
1da177e4 12350}
6aa20a22 12351
de6f31eb 12352static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12353{
b9f2c044
JG		 12354 switch (sset) {
12355 case ETH_SS_TEST:
12356 return TG3_NUM_TEST;
12357 case ETH_SS_STATS:
12358 return TG3_NUM_STATS;
12359 default:
12360 return -EOPNOTSUPP;
12361 }
4cafd3f5
MC		 12362}
12363
90415477
MC		 12364static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12365 u32 *rules __always_unused)
12366{
12367 struct tg3 *tp = netdev_priv(dev);
12368
12369 if (!tg3_flag(tp, SUPPORT_MSIX))
12370 return -EOPNOTSUPP;
12371
12372 switch (info->cmd) {
12373 case ETHTOOL_GRXRINGS:
12374 if (netif_running(tp->dev))
9102426a 12375 info->data = tp->rxq_cnt;
90415477
MC		 12376 else {
12377 info->data = num_online_cpus();
9102426a
MC		 12378 if (info->data > TG3_RSS_MAX_NUM_QS)
12379 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12380 }
12381
12382 /* The first interrupt vector only
12383 * handles link interrupts.
12384 */
12385 info->data -= 1;
12386 return 0;
12387
12388 default:
12389 return -EOPNOTSUPP;
12390 }
12391}
12392
12393static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12394{
12395 u32 size = 0;
12396 struct tg3 *tp = netdev_priv(dev);
12397
12398 if (tg3_flag(tp, SUPPORT_MSIX))
12399 size = TG3_RSS_INDIR_TBL_SIZE;
12400
12401 return size;
12402}
12403
12404static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12405{
12406 struct tg3 *tp = netdev_priv(dev);
12407 int i;
12408
12409 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12410 indir[i] = tp->rss_ind_tbl[i];
12411
12412 return 0;
12413}
12414
12415static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12416{
12417 struct tg3 *tp = netdev_priv(dev);
12418 size_t i;
12419
12420 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12421 tp->rss_ind_tbl[i] = indir[i];
12422
12423 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12424 return 0;
12425
12426 /* It is legal to write the indirection
12427 * table while the device is running.
12428 */
12429 tg3_full_lock(tp, 0);
12430 tg3_rss_write_indir_tbl(tp);
12431 tg3_full_unlock(tp);
12432
12433 return 0;
12434}
12435
0968169c
MC		 12436static void tg3_get_channels(struct net_device *dev,
12437 struct ethtool_channels *channel)
12438{
12439 struct tg3 *tp = netdev_priv(dev);
12440 u32 deflt_qs = netif_get_num_default_rss_queues();
12441
12442 channel->max_rx = tp->rxq_max;
12443 channel->max_tx = tp->txq_max;
12444
12445 if (netif_running(dev)) {
12446 channel->rx_count = tp->rxq_cnt;
12447 channel->tx_count = tp->txq_cnt;
12448 } else {
12449 if (tp->rxq_req)
12450 channel->rx_count = tp->rxq_req;
12451 else
12452 channel->rx_count = min(deflt_qs, tp->rxq_max);
12453
12454 if (tp->txq_req)
12455 channel->tx_count = tp->txq_req;
12456 else
12457 channel->tx_count = min(deflt_qs, tp->txq_max);
12458 }
12459}
12460
12461static int tg3_set_channels(struct net_device *dev,
12462 struct ethtool_channels *channel)
12463{
12464 struct tg3 *tp = netdev_priv(dev);
12465
12466 if (!tg3_flag(tp, SUPPORT_MSIX))
12467 return -EOPNOTSUPP;
12468
12469 if (channel->rx_count > tp->rxq_max ||
12470 channel->tx_count > tp->txq_max)
12471 return -EINVAL;
12472
12473 tp->rxq_req = channel->rx_count;
12474 tp->txq_req = channel->tx_count;
12475
12476 if (!netif_running(dev))
12477 return 0;
12478
12479 tg3_stop(tp);
12480
f4a46d1f 12481 tg3_carrier_off(tp);
0968169c 12482
be947307 12483 tg3_start(tp, true, false, false);
0968169c
MC		 12484
12485 return 0;
12486}
12487
de6f31eb 12488static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12489{
12490 switch (stringset) {
12491 case ETH_SS_STATS:
12492 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12493 break;
4cafd3f5
MC		 12494 case ETH_SS_TEST:
12495 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12496 break;
1da177e4
LT		 12497 default:
12498 WARN_ON(1); /* we need a WARN() */
12499 break;
12500 }
12501}
12502
81b8709c 12503static int tg3_set_phys_id(struct net_device *dev,
12504 enum ethtool_phys_id_state state)
4009a93d
MC		 12505{
12506 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12507
12508 if (!netif_running(tp->dev))
12509 return -EAGAIN;
12510
81b8709c 12511 switch (state) {
12512 case ETHTOOL_ID_ACTIVE:
fce55922 12513 return 1; /* cycle on/off once per second */
4009a93d 12514
81b8709c 12515 case ETHTOOL_ID_ON:
12516 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12517 LED_CTRL_1000MBPS_ON |
12518 LED_CTRL_100MBPS_ON |
12519 LED_CTRL_10MBPS_ON |
12520 LED_CTRL_TRAFFIC_OVERRIDE |
12521 LED_CTRL_TRAFFIC_BLINK |
12522 LED_CTRL_TRAFFIC_LED);
12523 break;
6aa20a22 12524
81b8709c 12525 case ETHTOOL_ID_OFF:
12526 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12527 LED_CTRL_TRAFFIC_OVERRIDE);
12528 break;
4009a93d 12529
81b8709c 12530 case ETHTOOL_ID_INACTIVE:
12531 tw32(MAC_LED_CTRL, tp->led_ctrl);
12532 break;
4009a93d 12533 }
81b8709c 12534
4009a93d
MC		 12535 return 0;
12536}
12537
de6f31eb 12538static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12539 struct ethtool_stats *estats, u64 *tmp_stats)
12540{
12541 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12542
b546e46f
MC		 12543 if (tp->hw_stats)
12544 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12545 else
12546 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12547}
12548
535a490e 12549static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12550{
12551 int i;
12552 __be32 *buf;
12553 u32 offset = 0, len = 0;
12554 u32 magic, val;
12555
63c3a66f 12556 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12557 return NULL;
12558
12559 if (magic == TG3_EEPROM_MAGIC) {
12560 for (offset = TG3_NVM_DIR_START;
12561 offset < TG3_NVM_DIR_END;
12562 offset += TG3_NVM_DIRENT_SIZE) {
12563 if (tg3_nvram_read(tp, offset, &val))
12564 return NULL;
12565
12566 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12567 TG3_NVM_DIRTYPE_EXTVPD)
12568 break;
12569 }
12570
12571 if (offset != TG3_NVM_DIR_END) {
12572 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12573 if (tg3_nvram_read(tp, offset + 4, &offset))
12574 return NULL;
12575
12576 offset = tg3_nvram_logical_addr(tp, offset);
12577 }
12578 }
12579
12580 if (!offset || !len) {
12581 offset = TG3_NVM_VPD_OFF;
12582 len = TG3_NVM_VPD_LEN;
12583 }
12584
12585 buf = kmalloc(len, GFP_KERNEL);
12586 if (buf == NULL)
12587 return NULL;
12588
12589 if (magic == TG3_EEPROM_MAGIC) {
12590 for (i = 0; i < len; i += 4) {
12591 /* The data is in little-endian format in NVRAM.
12592 * Use the big-endian read routines to preserve
12593 * the byte order as it exists in NVRAM.
12594 */
12595 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12596 goto error;
12597 }
12598 } else {
12599 u8 *ptr;
12600 ssize_t cnt;
12601 unsigned int pos = 0;
12602
12603 ptr = (u8 *)&buf[0];
12604 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12605 cnt = pci_read_vpd(tp->pdev, pos,
12606 len - pos, ptr);
12607 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12608 cnt = 0;
12609 else if (cnt < 0)
12610 goto error;
12611 }
12612 if (pos != len)
12613 goto error;
12614 }
12615
535a490e
MC		 12616 *vpdlen = len;
12617
c3e94500
MC		 12618 return buf;
12619
12620error:
12621 kfree(buf);
12622 return NULL;
12623}
12624
566f86ad 12625#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12626#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12627#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12628#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12629#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12630#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12631#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12632#define NVRAM_SELFBOOT_HW_SIZE 0x20
12633#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12634
12635static int tg3_test_nvram(struct tg3 *tp)
12636{
535a490e 12637 u32 csum, magic, len;
a9dc529d 12638 __be32 *buf;
ab0049b4 12639 int i, j, k, err = 0, size;
566f86ad 12640
63c3a66f 12641 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12642 return 0;
12643
e4f34110 12644 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12645 return -EIO;
12646
1b27777a
MC		 12647 if (magic == TG3_EEPROM_MAGIC)
12648 size = NVRAM_TEST_SIZE;
b16250e3 12649 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12650 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12651 TG3_EEPROM_SB_FORMAT_1) {
12652 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12653 case TG3_EEPROM_SB_REVISION_0:
12654 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12655 break;
12656 case TG3_EEPROM_SB_REVISION_2:
12657 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12658 break;
12659 case TG3_EEPROM_SB_REVISION_3:
12660 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12661 break;
727a6d9f
MC		 12662 case TG3_EEPROM_SB_REVISION_4:
12663 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12664 break;
12665 case TG3_EEPROM_SB_REVISION_5:
12666 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12667 break;
12668 case TG3_EEPROM_SB_REVISION_6:
12669 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12670 break;
a5767dec 12671 default:
727a6d9f 12672 return -EIO;
a5767dec
MC		 12673 }
12674 } else
1b27777a 12675 return 0;
b16250e3
MC		 12676 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12677 size = NVRAM_SELFBOOT_HW_SIZE;
12678 else
1b27777a
MC		 12679 return -EIO;
12680
12681 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12682 if (buf == NULL)
12683 return -ENOMEM;
12684
1b27777a
MC		 12685 err = -EIO;
12686 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12687 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12688 if (err)
566f86ad 12689 break;
566f86ad 12690 }
1b27777a 12691 if (i < size)
566f86ad
MC		 12692 goto out;
12693
1b27777a 12694 /* Selfboot format */
a9dc529d 12695 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12696 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12697 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12698 u8 *buf8 = (u8 *) buf, csum8 = 0;
12699
b9fc7dc5 12700 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12701 TG3_EEPROM_SB_REVISION_2) {
12702 /* For rev 2, the csum doesn't include the MBA. */
12703 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12704 csum8 += buf8[i];
12705 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12706 csum8 += buf8[i];
12707 } else {
12708 for (i = 0; i < size; i++)
12709 csum8 += buf8[i];
12710 }
1b27777a 12711
ad96b485
AB		 12712 if (csum8 == 0) {
12713 err = 0;
12714 goto out;
12715 }
12716
12717 err = -EIO;
12718 goto out;
1b27777a 12719 }
566f86ad 12720
b9fc7dc5 12721 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12722 TG3_EEPROM_MAGIC_HW) {
12723 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12724 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12725 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12726
12727 /* Separate the parity bits and the data bytes. */
12728 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12729 if ((i == 0) || (i == 8)) {
12730 int l;
12731 u8 msk;
12732
12733 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12734 parity[k++] = buf8[i] & msk;
12735 i++;
859a5887 12736 } else if (i == 16) {
b16250e3
MC		 12737 int l;
12738 u8 msk;
12739
12740 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12741 parity[k++] = buf8[i] & msk;
12742 i++;
12743
12744 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12745 parity[k++] = buf8[i] & msk;
12746 i++;
12747 }
12748 data[j++] = buf8[i];
12749 }
12750
12751 err = -EIO;
12752 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12753 u8 hw8 = hweight8(data[i]);
12754
12755 if ((hw8 & 0x1) && parity[i])
12756 goto out;
12757 else if (!(hw8 & 0x1) && !parity[i])
12758 goto out;
12759 }
12760 err = 0;
12761 goto out;
12762 }
12763
01c3a392
MC		 12764 err = -EIO;
12765
566f86ad
MC		 12766 /* Bootstrap checksum at offset 0x10 */
12767 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12768 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12769 goto out;
12770
12771 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12772 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12773 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12774 goto out;
566f86ad 12775
c3e94500
MC		 12776 kfree(buf);
12777
535a490e 12778 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12779 if (!buf)
12780 return -ENOMEM;
d4894f3e 12781
535a490e 12782 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12783 if (i > 0) {
12784 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12785 if (j < 0)
12786 goto out;
12787
535a490e 12788 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12789 goto out;
12790
12791 i += PCI_VPD_LRDT_TAG_SIZE;
12792 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12793 PCI_VPD_RO_KEYWORD_CHKSUM);
12794 if (j > 0) {
12795 u8 csum8 = 0;
12796
12797 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12798
12799 for (i = 0; i <= j; i++)
12800 csum8 += ((u8 *)buf)[i];
12801
12802 if (csum8)
12803 goto out;
12804 }
12805 }
12806
566f86ad
MC		 12807 err = 0;
12808
12809out:
12810 kfree(buf);
12811 return err;
12812}
12813
ca43007a
MC		 12814#define TG3_SERDES_TIMEOUT_SEC 2
12815#define TG3_COPPER_TIMEOUT_SEC 6
12816
12817static int tg3_test_link(struct tg3 *tp)
12818{
12819 int i, max;
12820
12821 if (!netif_running(tp->dev))
12822 return -ENODEV;
12823
f07e9af3 12824 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12825 max = TG3_SERDES_TIMEOUT_SEC;
12826 else
12827 max = TG3_COPPER_TIMEOUT_SEC;
12828
12829 for (i = 0; i < max; i++) {
f4a46d1f 12830 if (tp->link_up)
ca43007a
MC		 12831 return 0;
12832
12833 if (msleep_interruptible(1000))
12834 break;
12835 }
12836
12837 return -EIO;
12838}
12839
a71116d1 12840/* Only test the commonly used registers */
30ca3e37 12841static int tg3_test_registers(struct tg3 *tp)
a71116d1 12842{
b16250e3 12843 int i, is_5705, is_5750;
a71116d1
MC		 12844 u32 offset, read_mask, write_mask, val, save_val, read_val;
12845 static struct {
12846 u16 offset;
12847 u16 flags;
12848#define TG3_FL_5705 0x1
12849#define TG3_FL_NOT_5705 0x2
12850#define TG3_FL_NOT_5788 0x4
b16250e3 12851#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 12852 u32 read_mask;
12853 u32 write_mask;
12854 } reg_tbl[] = {
12855 /* MAC Control Registers */
12856 { MAC_MODE, TG3_FL_NOT_5705,
12857 0x00000000, 0x00ef6f8c },
12858 { MAC_MODE, TG3_FL_5705,
12859 0x00000000, 0x01ef6b8c },
12860 { MAC_STATUS, TG3_FL_NOT_5705,
12861 0x03800107, 0x00000000 },
12862 { MAC_STATUS, TG3_FL_5705,
12863 0x03800100, 0x00000000 },
12864 { MAC_ADDR_0_HIGH, 0x0000,
12865 0x00000000, 0x0000ffff },
12866 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 12867 0x00000000, 0xffffffff },
a71116d1
MC		 12868 { MAC_RX_MTU_SIZE, 0x0000,
12869 0x00000000, 0x0000ffff },
12870 { MAC_TX_MODE, 0x0000,
12871 0x00000000, 0x00000070 },
12872 { MAC_TX_LENGTHS, 0x0000,
12873 0x00000000, 0x00003fff },
12874 { MAC_RX_MODE, TG3_FL_NOT_5705,
12875 0x00000000, 0x000007fc },
12876 { MAC_RX_MODE, TG3_FL_5705,
12877 0x00000000, 0x000007dc },
12878 { MAC_HASH_REG_0, 0x0000,
12879 0x00000000, 0xffffffff },
12880 { MAC_HASH_REG_1, 0x0000,
12881 0x00000000, 0xffffffff },
12882 { MAC_HASH_REG_2, 0x0000,
12883 0x00000000, 0xffffffff },
12884 { MAC_HASH_REG_3, 0x0000,
12885 0x00000000, 0xffffffff },
12886
12887 /* Receive Data and Receive BD Initiator Control Registers. */
12888 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12889 0x00000000, 0xffffffff },
12890 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12891 0x00000000, 0xffffffff },
12892 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12893 0x00000000, 0x00000003 },
12894 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12895 0x00000000, 0xffffffff },
12896 { RCVDBDI_STD_BD+0, 0x0000,
12897 0x00000000, 0xffffffff },
12898 { RCVDBDI_STD_BD+4, 0x0000,
12899 0x00000000, 0xffffffff },
12900 { RCVDBDI_STD_BD+8, 0x0000,
12901 0x00000000, 0xffff0002 },
12902 { RCVDBDI_STD_BD+0xc, 0x0000,
12903 0x00000000, 0xffffffff },
6aa20a22 12904
a71116d1
MC		 12905 /* Receive BD Initiator Control Registers. */
12906 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12907 0x00000000, 0xffffffff },
12908 { RCVBDI_STD_THRESH, TG3_FL_5705,
12909 0x00000000, 0x000003ff },
12910 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12911 0x00000000, 0xffffffff },
6aa20a22 12912
a71116d1
MC		 12913 /* Host Coalescing Control Registers. */
12914 { HOSTCC_MODE, TG3_FL_NOT_5705,
12915 0x00000000, 0x00000004 },
12916 { HOSTCC_MODE, TG3_FL_5705,
12917 0x00000000, 0x000000f6 },
12918 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
12919 0x00000000, 0xffffffff },
12920 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
12921 0x00000000, 0x000003ff },
12922 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
12923 0x00000000, 0xffffffff },
12924 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
12925 0x00000000, 0x000003ff },
12926 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
12927 0x00000000, 0xffffffff },
12928 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12929 0x00000000, 0x000000ff },
12930 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
12931 0x00000000, 0xffffffff },
12932 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12933 0x00000000, 0x000000ff },
12934 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
12935 0x00000000, 0xffffffff },
12936 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
12937 0x00000000, 0xffffffff },
12938 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12939 0x00000000, 0xffffffff },
12940 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12941 0x00000000, 0x000000ff },
12942 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12943 0x00000000, 0xffffffff },
12944 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12945 0x00000000, 0x000000ff },
12946 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
12947 0x00000000, 0xffffffff },
12948 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
12949 0x00000000, 0xffffffff },
12950 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
12951 0x00000000, 0xffffffff },
12952 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
12953 0x00000000, 0xffffffff },
12954 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
12955 0x00000000, 0xffffffff },
12956 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
12957 0xffffffff, 0x00000000 },
12958 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
12959 0xffffffff, 0x00000000 },
12960
12961 /* Buffer Manager Control Registers. */
b16250e3 12962 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 12963 0x00000000, 0x007fff80 },
b16250e3 12964 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 12965 0x00000000, 0x007fffff },
12966 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
12967 0x00000000, 0x0000003f },
12968 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
12969 0x00000000, 0x000001ff },
12970 { BUFMGR_MB_HIGH_WATER, 0x0000,
12971 0x00000000, 0x000001ff },
12972 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
12973 0xffffffff, 0x00000000 },
12974 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
12975 0xffffffff, 0x00000000 },
6aa20a22 12976
a71116d1
MC		 12977 /* Mailbox Registers */
12978 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
12979 0x00000000, 0x000001ff },
12980 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
12981 0x00000000, 0x000001ff },
12982 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
12983 0x00000000, 0x000007ff },
12984 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
12985 0x00000000, 0x000001ff },
12986
12987 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
12988 };
12989
b16250e3 12990 is_5705 = is_5750 = 0;
63c3a66f 12991 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 12992 is_5705 = 1;
63c3a66f 12993 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 12994 is_5750 = 1;
12995 }
a71116d1
MC		 12996
12997 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
12998 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
12999 continue;
13000
13001 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13002 continue;
13003
63c3a66f 13004 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 13005 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13006 continue;
13007
b16250e3
MC		 13008 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13009 continue;
13010
a71116d1
MC		 13011 offset = (u32) reg_tbl[i].offset;
13012 read_mask = reg_tbl[i].read_mask;
13013 write_mask = reg_tbl[i].write_mask;
13014
13015 /* Save the original register content */
13016 save_val = tr32(offset);
13017
13018 /* Determine the read-only value. */
13019 read_val = save_val & read_mask;
13020
13021 /* Write zero to the register, then make sure the read-only bits
13022 * are not changed and the read/write bits are all zeros.
13023 */
13024 tw32(offset, 0);
13025
13026 val = tr32(offset);
13027
13028 /* Test the read-only and read/write bits. */
13029 if (((val & read_mask) != read_val) || (val & write_mask))
13030 goto out;
13031
13032 /* Write ones to all the bits defined by RdMask and WrMask, then
13033 * make sure the read-only bits are not changed and the
13034 * read/write bits are all ones.
13035 */
13036 tw32(offset, read_mask | write_mask);
13037
13038 val = tr32(offset);
13039
13040 /* Test the read-only bits. */
13041 if ((val & read_mask) != read_val)
13042 goto out;
13043
13044 /* Test the read/write bits. */
13045 if ((val & write_mask) != write_mask)
13046 goto out;
13047
13048 tw32(offset, save_val);
13049 }
13050
13051 return 0;
13052
13053out:
9f88f29f 13054 if (netif_msg_hw(tp))
2445e461
MC		 13055 netdev_err(tp->dev,
13056 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13057 tw32(offset, save_val);
13058 return -EIO;
13059}
13060
7942e1db
MC		 13061static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13062{
f71e1309 13063 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13064 int i;
13065 u32 j;
13066
e9edda69 13067 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13068 for (j = 0; j < len; j += 4) {
13069 u32 val;
13070
13071 tg3_write_mem(tp, offset + j, test_pattern[i]);
13072 tg3_read_mem(tp, offset + j, &val);
13073 if (val != test_pattern[i])
13074 return -EIO;
13075 }
13076 }
13077 return 0;
13078}
13079
13080static int tg3_test_memory(struct tg3 *tp)
13081{
13082 static struct mem_entry {
13083 u32 offset;
13084 u32 len;
13085 } mem_tbl_570x[] = {
38690194 13086 { 0x00000000, 0x00b50},
7942e1db
MC		 13087 { 0x00002000, 0x1c000},
13088 { 0xffffffff, 0x00000}
13089 }, mem_tbl_5705[] = {
13090 { 0x00000100, 0x0000c},
13091 { 0x00000200, 0x00008},
7942e1db
MC		 13092 { 0x00004000, 0x00800},
13093 { 0x00006000, 0x01000},
13094 { 0x00008000, 0x02000},
13095 { 0x00010000, 0x0e000},
13096 { 0xffffffff, 0x00000}
79f4d13a
MC		 13097 }, mem_tbl_5755[] = {
13098 { 0x00000200, 0x00008},
13099 { 0x00004000, 0x00800},
13100 { 0x00006000, 0x00800},
13101 { 0x00008000, 0x02000},
13102 { 0x00010000, 0x0c000},
13103 { 0xffffffff, 0x00000}
b16250e3
MC		 13104 }, mem_tbl_5906[] = {
13105 { 0x00000200, 0x00008},
13106 { 0x00004000, 0x00400},
13107 { 0x00006000, 0x00400},
13108 { 0x00008000, 0x01000},
13109 { 0x00010000, 0x01000},
13110 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13111 }, mem_tbl_5717[] = {
13112 { 0x00000200, 0x00008},
13113 { 0x00010000, 0x0a000},
13114 { 0x00020000, 0x13c00},
13115 { 0xffffffff, 0x00000}
13116 }, mem_tbl_57765[] = {
13117 { 0x00000200, 0x00008},
13118 { 0x00004000, 0x00800},
13119 { 0x00006000, 0x09800},
13120 { 0x00010000, 0x0a000},
13121 { 0xffffffff, 0x00000}
7942e1db
MC		 13122 };
13123 struct mem_entry *mem_tbl;
13124 int err = 0;
13125 int i;
13126
63c3a66f 13127 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13128 mem_tbl = mem_tbl_5717;
c65a17f4 13129 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13130 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13131 mem_tbl = mem_tbl_57765;
63c3a66f 13132 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13133 mem_tbl = mem_tbl_5755;
4153577a 13134 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13135 mem_tbl = mem_tbl_5906;
63c3a66f 13136 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13137 mem_tbl = mem_tbl_5705;
13138 else
7942e1db
MC		 13139 mem_tbl = mem_tbl_570x;
13140
13141 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13142 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13143 if (err)
7942e1db
MC		 13144 break;
13145 }
6aa20a22 13146
7942e1db
MC		 13147 return err;
13148}
13149
bb158d69
MC		 13150#define TG3_TSO_MSS 500
13151
13152#define TG3_TSO_IP_HDR_LEN 20
13153#define TG3_TSO_TCP_HDR_LEN 20
13154#define TG3_TSO_TCP_OPT_LEN 12
13155
13156static const u8 tg3_tso_header[] = {
131570x08, 0x00,
131580x45, 0x00, 0x00, 0x00,
131590x00, 0x00, 0x40, 0x00,
131600x40, 0x06, 0x00, 0x00,
131610x0a, 0x00, 0x00, 0x01,
131620x0a, 0x00, 0x00, 0x02,
131630x0d, 0x00, 0xe0, 0x00,
131640x00, 0x00, 0x01, 0x00,
131650x00, 0x00, 0x02, 0x00,
131660x80, 0x10, 0x10, 0x00,
131670x14, 0x09, 0x00, 0x00,
131680x01, 0x01, 0x08, 0x0a,
131690x11, 0x11, 0x11, 0x11,
131700x11, 0x11, 0x11, 0x11,
13171};
9f40dead 13172
28a45957 13173static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13174{
5e5a7f37 13175 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13176 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13177 u32 budget;
9205fd9c
ED		 13178 struct sk_buff *skb;
13179 u8 *tx_data, *rx_data;
c76949a6
MC		 13180 dma_addr_t map;
13181 int num_pkts, tx_len, rx_len, i, err;
13182 struct tg3_rx_buffer_desc *desc;
898a56f8 13183 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13184 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13185
c8873405
MC		 13186 tnapi = &tp->napi[0];
13187 rnapi = &tp->napi[0];
0c1d0e2b 13188 if (tp->irq_cnt > 1) {
63c3a66f 13189 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13190 rnapi = &tp->napi[1];
63c3a66f 13191 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13192 tnapi = &tp->napi[1];
0c1d0e2b 13193 }
fd2ce37f 13194 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13195
c76949a6
MC		 13196 err = -EIO;
13197
4852a861 13198 tx_len = pktsz;
a20e9c62 13199 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13200 if (!skb)
13201 return -ENOMEM;
13202
c76949a6
MC		 13203 tx_data = skb_put(skb, tx_len);
13204 memcpy(tx_data, tp->dev->dev_addr, 6);
13205 memset(tx_data + 6, 0x0, 8);
13206
4852a861 13207 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13208
28a45957 13209 if (tso_loopback) {
bb158d69
MC		 13210 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13211
13212 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13213 TG3_TSO_TCP_OPT_LEN;
13214
13215 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13216 sizeof(tg3_tso_header));
13217 mss = TG3_TSO_MSS;
13218
13219 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13220 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13221
13222 /* Set the total length field in the IP header */
13223 iph->tot_len = htons((u16)(mss + hdr_len));
13224
13225 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13226 TXD_FLAG_CPU_POST_DMA);
13227
63c3a66f
JP		 13228 if (tg3_flag(tp, HW_TSO_1) ||
13229 tg3_flag(tp, HW_TSO_2) ||
13230 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13231 struct tcphdr *th;
13232 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13233 th = (struct tcphdr *)&tx_data[val];
13234 th->check = 0;
13235 } else
13236 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13237
63c3a66f 13238 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13239 mss |= (hdr_len & 0xc) << 12;
13240 if (hdr_len & 0x10)
13241 base_flags |= 0x00000010;
13242 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13243 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13244 mss |= hdr_len << 9;
63c3a66f 13245 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13246 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13247 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13248 } else {
13249 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13250 }
13251
13252 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13253 } else {
13254 num_pkts = 1;
13255 data_off = ETH_HLEN;
c441b456
MC		 13256
13257 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13258 tx_len > VLAN_ETH_FRAME_LEN)
13259 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13260 }
13261
13262 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13263 tx_data[i] = (u8) (i & 0xff);
13264
f4188d8a
AD		 13265 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13266 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13267 dev_kfree_skb(skb);
13268 return -EIO;
13269 }
c76949a6 13270
0d681b27
MC		 13271 val = tnapi->tx_prod;
13272 tnapi->tx_buffers[val].skb = skb;
13273 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13274
c76949a6 13275 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13276 rnapi->coal_now);
c76949a6
MC		 13277
13278 udelay(10);
13279
898a56f8 13280 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13281
84b67b27
MC		 13282 budget = tg3_tx_avail(tnapi);
13283 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13284 base_flags | TXD_FLAG_END, mss, 0)) {
13285 tnapi->tx_buffers[val].skb = NULL;
13286 dev_kfree_skb(skb);
13287 return -EIO;
13288 }
c76949a6 13289
f3f3f27e 13290 tnapi->tx_prod++;
c76949a6 13291
6541b806
MC		 13292 /* Sync BD data before updating mailbox */
13293 wmb();
13294
f3f3f27e
MC		 13295 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13296 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13297
13298 udelay(10);
13299
303fc921
MC		 13300 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13301 for (i = 0; i < 35; i++) {
c76949a6 13302 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13303 coal_now);
c76949a6
MC		 13304
13305 udelay(10);
13306
898a56f8
MC		 13307 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13308 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13309 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13310 (rx_idx == (rx_start_idx + num_pkts)))
13311 break;
13312 }
13313
ba1142e4 13314 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13315 dev_kfree_skb(skb);
13316
f3f3f27e 13317 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13318 goto out;
13319
13320 if (rx_idx != rx_start_idx + num_pkts)
13321 goto out;
13322
bb158d69
MC		 13323 val = data_off;
13324 while (rx_idx != rx_start_idx) {
13325 desc = &rnapi->rx_rcb[rx_start_idx++];
13326 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13327 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13328
bb158d69
MC		 13329 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13330 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13331 goto out;
c76949a6 13332
bb158d69
MC		 13333 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13334 - ETH_FCS_LEN;
c76949a6 13335
28a45957 13336 if (!tso_loopback) {
bb158d69
MC		 13337 if (rx_len != tx_len)
13338 goto out;
4852a861 13339
bb158d69
MC		 13340 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13341 if (opaque_key != RXD_OPAQUE_RING_STD)
13342 goto out;
13343 } else {
13344 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13345 goto out;
13346 }
13347 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13348 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13349 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13350 goto out;
bb158d69 13351 }
4852a861 13352
bb158d69 13353 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13354 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13355 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13356 mapping);
13357 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13358 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13359 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13360 mapping);
13361 } else
13362 goto out;
c76949a6 13363
bb158d69
MC		 13364 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13365 PCI_DMA_FROMDEVICE);
c76949a6 13366
9205fd9c 13367 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13368 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13369 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13370 goto out;
13371 }
c76949a6 13372 }
bb158d69 13373
c76949a6 13374 err = 0;
6aa20a22 13375
9205fd9c 13376 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13377out:
13378 return err;
13379}
13380
00c266b7
MC		 13381#define TG3_STD_LOOPBACK_FAILED 1
13382#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13383#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13384#define TG3_LOOPBACK_FAILED \
13385 (TG3_STD_LOOPBACK_FAILED | \
13386 TG3_JMB_LOOPBACK_FAILED | \
13387 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13388
941ec90f 13389static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13390{
28a45957 13391 int err = -EIO;
2215e24c 13392 u32 eee_cap;
c441b456
MC		 13393 u32 jmb_pkt_sz = 9000;
13394
13395 if (tp->dma_limit)
13396 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13397
ab789046
MC		 13398 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13399 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13400
28a45957 13401 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13402 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13403 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13404 if (do_extlpbk)
93df8b8f 13405 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13406 goto done;
13407 }
13408
953c96e0 13409 err = tg3_reset_hw(tp, true);
ab789046 13410 if (err) {
93df8b8f
NNS		 13411 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13412 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13413 if (do_extlpbk)
93df8b8f 13414 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13415 goto done;
13416 }
9f40dead 13417
63c3a66f 13418 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13419 int i;
13420
13421 /* Reroute all rx packets to the 1st queue */
13422 for (i = MAC_RSS_INDIR_TBL_0;
13423 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13424 tw32(i, 0x0);
13425 }
13426
6e01b20b
MC		 13427 /* HW errata - mac loopback fails in some cases on 5780.
13428 * Normal traffic and PHY loopback are not affected by
13429 * errata. Also, the MAC loopback test is deprecated for
13430 * all newer ASIC revisions.
13431 */
4153577a 13432 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13433 !tg3_flag(tp, CPMU_PRESENT)) {
13434 tg3_mac_loopback(tp, true);
9936bcf6 13435
28a45957 13436 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13437 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13438
13439 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13440 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13441 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13442
13443 tg3_mac_loopback(tp, false);
13444 }
4852a861 13445
f07e9af3 13446 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13447 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13448 int i;
13449
941ec90f 13450 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13451
13452 /* Wait for link */
13453 for (i = 0; i < 100; i++) {
13454 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13455 break;
13456 mdelay(1);
13457 }
13458
28a45957 13459 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13460 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13461 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13462 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13463 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13464 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13465 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13466 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13467
941ec90f
MC		 13468 if (do_extlpbk) {
13469 tg3_phy_lpbk_set(tp, 0, true);
13470
13471 /* All link indications report up, but the hardware
13472 * isn't really ready for about 20 msec. Double it
13473 * to be sure.
13474 */
13475 mdelay(40);
13476
13477 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13478 data[TG3_EXT_LOOPB_TEST] |=
13479 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13480 if (tg3_flag(tp, TSO_CAPABLE) &&
13481 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13482 data[TG3_EXT_LOOPB_TEST] |=
13483 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13484 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13485 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13486 data[TG3_EXT_LOOPB_TEST] |=
13487 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13488 }
13489
5e5a7f37
MC		 13490 /* Re-enable gphy autopowerdown. */
13491 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13492 tg3_phy_toggle_apd(tp, true);
13493 }
6833c043 13494
93df8b8f
NNS		 13495 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13496 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13497
ab789046
MC		 13498done:
13499 tp->phy_flags |= eee_cap;
13500
9f40dead
MC		 13501 return err;
13502}
13503
4cafd3f5
MC		 13504static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13505 u64 *data)
13506{
566f86ad 13507 struct tg3 *tp = netdev_priv(dev);
941ec90f 13508 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13509
2e460fc0
NS		 13510 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13511 if (tg3_power_up(tp)) {
13512 etest->flags |= ETH_TEST_FL_FAILED;
13513 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13514 return;
13515 }
13516 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13517 }
bc1c7567 13518
566f86ad
MC		 13519 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13520
13521 if (tg3_test_nvram(tp) != 0) {
13522 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13523 data[TG3_NVRAM_TEST] = 1;
566f86ad 13524 }
941ec90f 13525 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13526 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13527 data[TG3_LINK_TEST] = 1;
ca43007a 13528 }
a71116d1 13529 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13530 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13531
13532 if (netif_running(dev)) {
b02fd9e3 13533 tg3_phy_stop(tp);
a71116d1 13534 tg3_netif_stop(tp);
bbe832c0
MC		 13535 irq_sync = 1;
13536 }
a71116d1 13537
bbe832c0 13538 tg3_full_lock(tp, irq_sync);
a71116d1 13539 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13540 err = tg3_nvram_lock(tp);
a71116d1 13541 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13542 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13543 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13544 if (!err)
13545 tg3_nvram_unlock(tp);
a71116d1 13546
f07e9af3 13547 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13548 tg3_phy_reset(tp);
13549
a71116d1
MC		 13550 if (tg3_test_registers(tp) != 0) {
13551 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13552 data[TG3_REGISTER_TEST] = 1;
a71116d1 13553 }
28a45957 13554
7942e1db
MC		 13555 if (tg3_test_memory(tp) != 0) {
13556 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13557 data[TG3_MEMORY_TEST] = 1;
7942e1db 13558 }
28a45957 13559
941ec90f
MC		 13560 if (doextlpbk)
13561 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13562
93df8b8f 13563 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13564 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13565
f47c11ee
DM		 13566 tg3_full_unlock(tp);
13567
d4bc3927
MC		 13568 if (tg3_test_interrupt(tp) != 0) {
13569 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13570 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13571 }
f47c11ee
DM		 13572
13573 tg3_full_lock(tp, 0);
d4bc3927 13574
a71116d1
MC		 13575 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13576 if (netif_running(dev)) {
63c3a66f 13577 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13578 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13579 if (!err2)
b9ec6c1b 13580 tg3_netif_start(tp);
a71116d1 13581 }
f47c11ee
DM		 13582
13583 tg3_full_unlock(tp);
b02fd9e3
MC		 13584
13585 if (irq_sync && !err2)
13586 tg3_phy_start(tp);
a71116d1 13587 }
80096068 13588 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13589 tg3_power_down_prepare(tp);
bc1c7567 13590
4cafd3f5
MC		 13591}
13592
0a633ac2
MC		 13593static int tg3_hwtstamp_ioctl(struct net_device *dev,
13594 struct ifreq *ifr, int cmd)
13595{
13596 struct tg3 *tp = netdev_priv(dev);
13597 struct hwtstamp_config stmpconf;
13598
13599 if (!tg3_flag(tp, PTP_CAPABLE))
13600 return -EINVAL;
13601
13602 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13603 return -EFAULT;
13604
13605 if (stmpconf.flags)
13606 return -EINVAL;
13607
13608 switch (stmpconf.tx_type) {
13609 case HWTSTAMP_TX_ON:
13610 tg3_flag_set(tp, TX_TSTAMP_EN);
13611 break;
13612 case HWTSTAMP_TX_OFF:
13613 tg3_flag_clear(tp, TX_TSTAMP_EN);
13614 break;
13615 default:
13616 return -ERANGE;
13617 }
13618
13619 switch (stmpconf.rx_filter) {
13620 case HWTSTAMP_FILTER_NONE:
13621 tp->rxptpctl = 0;
13622 break;
13623 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13624 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13625 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13626 break;
13627 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13628 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13629 TG3_RX_PTP_CTL_SYNC_EVNT;
13630 break;
13631 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13632 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13633 TG3_RX_PTP_CTL_DELAY_REQ;
13634 break;
13635 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13636 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13637 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13638 break;
13639 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13640 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13641 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13642 break;
13643 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13644 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13645 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13646 break;
13647 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13648 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13649 TG3_RX_PTP_CTL_SYNC_EVNT;
13650 break;
13651 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13652 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13653 TG3_RX_PTP_CTL_SYNC_EVNT;
13654 break;
13655 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13656 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13657 TG3_RX_PTP_CTL_SYNC_EVNT;
13658 break;
13659 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13660 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13661 TG3_RX_PTP_CTL_DELAY_REQ;
13662 break;
13663 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13664 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13665 TG3_RX_PTP_CTL_DELAY_REQ;
13666 break;
13667 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13668 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13669 TG3_RX_PTP_CTL_DELAY_REQ;
13670 break;
13671 default:
13672 return -ERANGE;
13673 }
13674
13675 if (netif_running(dev) && tp->rxptpctl)
13676 tw32(TG3_RX_PTP_CTL,
13677 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13678
13679 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13680 -EFAULT : 0;
13681}
13682
1da177e4
LT		 13683static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13684{
13685 struct mii_ioctl_data *data = if_mii(ifr);
13686 struct tg3 *tp = netdev_priv(dev);
13687 int err;
13688
63c3a66f 13689 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13690 struct phy_device *phydev;
f07e9af3 13691 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13692 return -EAGAIN;
3f0e3ad7 13693 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
28b04113 13694 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13695 }
13696
33f401ae 13697 switch (cmd) {
1da177e4 13698 case SIOCGMIIPHY:
882e9793 13699 data->phy_id = tp->phy_addr;
1da177e4
LT		 13700
13701 /* fallthru */
13702 case SIOCGMIIREG: {
13703 u32 mii_regval;
13704
f07e9af3 13705 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13706 break; /* We have no PHY */
13707
34eea5ac 13708 if (!netif_running(dev))
bc1c7567
MC		 13709 return -EAGAIN;
13710
f47c11ee 13711 spin_lock_bh(&tp->lock);
5c358045
HM		 13712 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13713 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13714 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13715
13716 data->val_out = mii_regval;
13717
13718 return err;
13719 }
13720
13721 case SIOCSMIIREG:
f07e9af3 13722 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13723 break; /* We have no PHY */
13724
34eea5ac 13725 if (!netif_running(dev))
bc1c7567
MC		 13726 return -EAGAIN;
13727
f47c11ee 13728 spin_lock_bh(&tp->lock);
5c358045
HM		 13729 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13730 data->reg_num & 0x1f, data->val_in);
f47c11ee 13731 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13732
13733 return err;
13734
0a633ac2
MC		 13735 case SIOCSHWTSTAMP:
13736 return tg3_hwtstamp_ioctl(dev, ifr, cmd);
13737
1da177e4
LT		 13738 default:
13739 /* do nothing */
13740 break;
13741 }
13742 return -EOPNOTSUPP;
13743}
13744
15f9850d
DM		 13745static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13746{
13747 struct tg3 *tp = netdev_priv(dev);
13748
13749 memcpy(ec, &tp->coal, sizeof(*ec));
13750 return 0;
13751}
13752
d244c892
MC		 13753static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13754{
13755 struct tg3 *tp = netdev_priv(dev);
13756 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13757 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13758
63c3a66f 13759 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13760 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13761 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13762 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13763 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13764 }
13765
13766 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13767 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13768 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13769 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13770 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13771 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13772 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13773 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13774 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13775 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13776 return -EINVAL;
13777
13778 /* No rx interrupts will be generated if both are zero */
13779 if ((ec->rx_coalesce_usecs == 0) &&
13780 (ec->rx_max_coalesced_frames == 0))
13781 return -EINVAL;
13782
13783 /* No tx interrupts will be generated if both are zero */
13784 if ((ec->tx_coalesce_usecs == 0) &&
13785 (ec->tx_max_coalesced_frames == 0))
13786 return -EINVAL;
13787
13788 /* Only copy relevant parameters, ignore all others. */
13789 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13790 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13791 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13792 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13793 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13794 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13795 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13796 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13797 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13798
13799 if (netif_running(dev)) {
13800 tg3_full_lock(tp, 0);
13801 __tg3_set_coalesce(tp, &tp->coal);
13802 tg3_full_unlock(tp);
13803 }
13804 return 0;
13805}
13806
1cbf9eb8
NS		 13807static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13808{
13809 struct tg3 *tp = netdev_priv(dev);
13810
13811 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13812 netdev_warn(tp->dev, "Board does not support EEE!\n");
13813 return -EOPNOTSUPP;
13814 }
13815
13816 if (edata->advertised != tp->eee.advertised) {
13817 netdev_warn(tp->dev,
13818 "Direct manipulation of EEE advertisement is not supported\n");
13819 return -EINVAL;
13820 }
13821
13822 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13823 netdev_warn(tp->dev,
13824 "Maximal Tx Lpi timer supported is %#x(u)\n",
13825 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13826 return -EINVAL;
13827 }
13828
13829 tp->eee = *edata;
13830
13831 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13832 tg3_warn_mgmt_link_flap(tp);
13833
13834 if (netif_running(tp->dev)) {
13835 tg3_full_lock(tp, 0);
13836 tg3_setup_eee(tp);
13837 tg3_phy_reset(tp);
13838 tg3_full_unlock(tp);
13839 }
13840
13841 return 0;
13842}
13843
13844static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13845{
13846 struct tg3 *tp = netdev_priv(dev);
13847
13848 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13849 netdev_warn(tp->dev,
13850 "Board does not support EEE!\n");
13851 return -EOPNOTSUPP;
13852 }
13853
13854 *edata = tp->eee;
13855 return 0;
13856}
13857
7282d491 13858static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 13859 .get_settings = tg3_get_settings,
13860 .set_settings = tg3_set_settings,
13861 .get_drvinfo = tg3_get_drvinfo,
13862 .get_regs_len = tg3_get_regs_len,
13863 .get_regs = tg3_get_regs,
13864 .get_wol = tg3_get_wol,
13865 .set_wol = tg3_set_wol,
13866 .get_msglevel = tg3_get_msglevel,
13867 .set_msglevel = tg3_set_msglevel,
13868 .nway_reset = tg3_nway_reset,
13869 .get_link = ethtool_op_get_link,
13870 .get_eeprom_len = tg3_get_eeprom_len,
13871 .get_eeprom = tg3_get_eeprom,
13872 .set_eeprom = tg3_set_eeprom,
13873 .get_ringparam = tg3_get_ringparam,
13874 .set_ringparam = tg3_set_ringparam,
13875 .get_pauseparam = tg3_get_pauseparam,
13876 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 13877 .self_test = tg3_self_test,
1da177e4 13878 .get_strings = tg3_get_strings,
81b8709c 13879 .set_phys_id = tg3_set_phys_id,
1da177e4 13880 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 13881 .get_coalesce = tg3_get_coalesce,
d244c892 13882 .set_coalesce = tg3_set_coalesce,
b9f2c044 13883 .get_sset_count = tg3_get_sset_count,
90415477
MC		 13884 .get_rxnfc = tg3_get_rxnfc,
13885 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
13886 .get_rxfh_indir = tg3_get_rxfh_indir,
13887 .set_rxfh_indir = tg3_set_rxfh_indir,
0968169c
MC		 13888 .get_channels = tg3_get_channels,
13889 .set_channels = tg3_set_channels,
7d41e49a 13890 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 13891 .get_eee = tg3_get_eee,
13892 .set_eee = tg3_set_eee,
1da177e4
LT		 13893};
13894
b4017c53
DM		 13895static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
13896 struct rtnl_link_stats64 *stats)
13897{
13898 struct tg3 *tp = netdev_priv(dev);
13899
0f566b20
MC		 13900 spin_lock_bh(&tp->lock);
13901 if (!tp->hw_stats) {
13902 spin_unlock_bh(&tp->lock);
b4017c53 13903 return &tp->net_stats_prev;
0f566b20 13904 }
b4017c53 13905
b4017c53
DM		 13906 tg3_get_nstats(tp, stats);
13907 spin_unlock_bh(&tp->lock);
13908
13909 return stats;
13910}
13911
ccd5ba9d
MC		 13912static void tg3_set_rx_mode(struct net_device *dev)
13913{
13914 struct tg3 *tp = netdev_priv(dev);
13915
13916 if (!netif_running(dev))
13917 return;
13918
13919 tg3_full_lock(tp, 0);
13920 __tg3_set_rx_mode(dev);
13921 tg3_full_unlock(tp);
13922}
13923
faf1627a
MC		 13924static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
13925 int new_mtu)
13926{
13927 dev->mtu = new_mtu;
13928
13929 if (new_mtu > ETH_DATA_LEN) {
13930 if (tg3_flag(tp, 5780_CLASS)) {
13931 netdev_update_features(dev);
13932 tg3_flag_clear(tp, TSO_CAPABLE);
13933 } else {
13934 tg3_flag_set(tp, JUMBO_RING_ENABLE);
13935 }
13936 } else {
13937 if (tg3_flag(tp, 5780_CLASS)) {
13938 tg3_flag_set(tp, TSO_CAPABLE);
13939 netdev_update_features(dev);
13940 }
13941 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
13942 }
13943}
13944
13945static int tg3_change_mtu(struct net_device *dev, int new_mtu)
13946{
13947 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 13948 int err;
13949 bool reset_phy = false;
faf1627a
MC		 13950
13951 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
13952 return -EINVAL;
13953
13954 if (!netif_running(dev)) {
13955 /* We'll just catch it later when the
13956 * device is up'd.
13957 */
13958 tg3_set_mtu(dev, tp, new_mtu);
13959 return 0;
13960 }
13961
13962 tg3_phy_stop(tp);
13963
13964 tg3_netif_stop(tp);
13965
13966 tg3_full_lock(tp, 1);
13967
13968 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13969
13970 tg3_set_mtu(dev, tp, new_mtu);
13971
2fae5e36
MC		 13972 /* Reset PHY, otherwise the read DMA engine will be in a mode that
13973 * breaks all requests to 256 bytes.
13974 */
4153577a 13975 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 13976 reset_phy = true;
2fae5e36
MC		 13977
13978 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 13979
13980 if (!err)
13981 tg3_netif_start(tp);
13982
13983 tg3_full_unlock(tp);
13984
13985 if (!err)
13986 tg3_phy_start(tp);
13987
13988 return err;
13989}
13990
13991static const struct net_device_ops tg3_netdev_ops = {
13992 .ndo_open = tg3_open,
13993 .ndo_stop = tg3_close,
13994 .ndo_start_xmit = tg3_start_xmit,
13995 .ndo_get_stats64 = tg3_get_stats64,
13996 .ndo_validate_addr = eth_validate_addr,
13997 .ndo_set_rx_mode = tg3_set_rx_mode,
13998 .ndo_set_mac_address = tg3_set_mac_addr,
13999 .ndo_do_ioctl = tg3_ioctl,
14000 .ndo_tx_timeout = tg3_tx_timeout,
14001 .ndo_change_mtu = tg3_change_mtu,
14002 .ndo_fix_features = tg3_fix_features,
14003 .ndo_set_features = tg3_set_features,
14004#ifdef CONFIG_NET_POLL_CONTROLLER
14005 .ndo_poll_controller = tg3_poll_controller,
14006#endif
14007};
14008
229b1ad1 14009static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14010{
1b27777a 14011 u32 cursize, val, magic;
1da177e4
LT		 14012
14013 tp->nvram_size = EEPROM_CHIP_SIZE;
14014
e4f34110 14015 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14016 return;
14017
b16250e3
MC		 14018 if ((magic != TG3_EEPROM_MAGIC) &&
14019 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14020 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14021 return;
14022
14023 /*
14024 * Size the chip by reading offsets at increasing powers of two.
14025 * When we encounter our validation signature, we know the addressing
14026 * has wrapped around, and thus have our chip size.
14027 */
1b27777a 14028 cursize = 0x10;
1da177e4
LT		 14029
14030 while (cursize < tp->nvram_size) {
e4f34110 14031 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14032 return;
14033
1820180b 14034 if (val == magic)
1da177e4
LT		 14035 break;
14036
14037 cursize <<= 1;
14038 }
14039
14040 tp->nvram_size = cursize;
14041}
6aa20a22 14042
229b1ad1 14043static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14044{
14045 u32 val;
14046
63c3a66f 14047 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14048 return;
14049
14050 /* Selfboot format */
1820180b 14051 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14052 tg3_get_eeprom_size(tp);
14053 return;
14054 }
14055
6d348f2c 14056 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14057 if (val != 0) {
6d348f2c
MC		 14058 /* This is confusing. We want to operate on the
14059 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14060 * call will read from NVRAM and byteswap the data
14061 * according to the byteswapping settings for all
14062 * other register accesses. This ensures the data we
14063 * want will always reside in the lower 16-bits.
14064 * However, the data in NVRAM is in LE format, which
14065 * means the data from the NVRAM read will always be
14066 * opposite the endianness of the CPU. The 16-bit
14067 * byteswap then brings the data to CPU endianness.
14068 */
14069 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14070 return;
14071 }
14072 }
fd1122a2 14073 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14074}
14075
229b1ad1 14076static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14077{
14078 u32 nvcfg1;
14079
14080 nvcfg1 = tr32(NVRAM_CFG1);
14081 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14082 tg3_flag_set(tp, FLASH);
8590a603 14083 } else {
1da177e4
LT		 14084 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14085 tw32(NVRAM_CFG1, nvcfg1);
14086 }
14087
4153577a 14088 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14089 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14090 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14091 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14092 tp->nvram_jedecnum = JEDEC_ATMEL;
14093 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14094 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14095 break;
14096 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14097 tp->nvram_jedecnum = JEDEC_ATMEL;
14098 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14099 break;
14100 case FLASH_VENDOR_ATMEL_EEPROM:
14101 tp->nvram_jedecnum = JEDEC_ATMEL;
14102 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14103 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14104 break;
14105 case FLASH_VENDOR_ST:
14106 tp->nvram_jedecnum = JEDEC_ST;
14107 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14108 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14109 break;
14110 case FLASH_VENDOR_SAIFUN:
14111 tp->nvram_jedecnum = JEDEC_SAIFUN;
14112 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14113 break;
14114 case FLASH_VENDOR_SST_SMALL:
14115 case FLASH_VENDOR_SST_LARGE:
14116 tp->nvram_jedecnum = JEDEC_SST;
14117 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14118 break;
1da177e4 14119 }
8590a603 14120 } else {
1da177e4
LT		 14121 tp->nvram_jedecnum = JEDEC_ATMEL;
14122 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14123 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14124 }
14125}
14126
229b1ad1 14127static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14128{
14129 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14130 case FLASH_5752PAGE_SIZE_256:
14131 tp->nvram_pagesize = 256;
14132 break;
14133 case FLASH_5752PAGE_SIZE_512:
14134 tp->nvram_pagesize = 512;
14135 break;
14136 case FLASH_5752PAGE_SIZE_1K:
14137 tp->nvram_pagesize = 1024;
14138 break;
14139 case FLASH_5752PAGE_SIZE_2K:
14140 tp->nvram_pagesize = 2048;
14141 break;
14142 case FLASH_5752PAGE_SIZE_4K:
14143 tp->nvram_pagesize = 4096;
14144 break;
14145 case FLASH_5752PAGE_SIZE_264:
14146 tp->nvram_pagesize = 264;
14147 break;
14148 case FLASH_5752PAGE_SIZE_528:
14149 tp->nvram_pagesize = 528;
14150 break;
14151 }
14152}
14153
229b1ad1 14154static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14155{
14156 u32 nvcfg1;
14157
14158 nvcfg1 = tr32(NVRAM_CFG1);
14159
e6af301b
MC		 14160 /* NVRAM protection for TPM */
14161 if (nvcfg1 & (1 << 27))
63c3a66f 14162 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14163
361b4ac2 14164 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14165 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14166 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14167 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14168 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14169 break;
14170 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14171 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14172 tg3_flag_set(tp, NVRAM_BUFFERED);
14173 tg3_flag_set(tp, FLASH);
8590a603
MC		 14174 break;
14175 case FLASH_5752VENDOR_ST_M45PE10:
14176 case FLASH_5752VENDOR_ST_M45PE20:
14177 case FLASH_5752VENDOR_ST_M45PE40:
14178 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14179 tg3_flag_set(tp, NVRAM_BUFFERED);
14180 tg3_flag_set(tp, FLASH);
8590a603 14181 break;
361b4ac2
MC		 14182 }
14183
63c3a66f 14184 if (tg3_flag(tp, FLASH)) {
a1b950d5 14185 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14186 } else {
361b4ac2
MC		 14187 /* For eeprom, set pagesize to maximum eeprom size */
14188 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14189
14190 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14191 tw32(NVRAM_CFG1, nvcfg1);
14192 }
14193}
14194
229b1ad1 14195static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14196{
989a9d23 14197 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14198
14199 nvcfg1 = tr32(NVRAM_CFG1);
14200
14201 /* NVRAM protection for TPM */
989a9d23 14202 if (nvcfg1 & (1 << 27)) {
63c3a66f 14203 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14204 protect = 1;
14205 }
d3c7b886 14206
989a9d23
MC		 14207 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14208 switch (nvcfg1) {
8590a603
MC		 14209 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14210 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14211 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14212 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14213 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14214 tg3_flag_set(tp, NVRAM_BUFFERED);
14215 tg3_flag_set(tp, FLASH);
8590a603
MC		 14216 tp->nvram_pagesize = 264;
14217 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14218 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14219 tp->nvram_size = (protect ? 0x3e200 :
14220 TG3_NVRAM_SIZE_512KB);
14221 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14222 tp->nvram_size = (protect ? 0x1f200 :
14223 TG3_NVRAM_SIZE_256KB);
14224 else
14225 tp->nvram_size = (protect ? 0x1f200 :
14226 TG3_NVRAM_SIZE_128KB);
14227 break;
14228 case FLASH_5752VENDOR_ST_M45PE10:
14229 case FLASH_5752VENDOR_ST_M45PE20:
14230 case FLASH_5752VENDOR_ST_M45PE40:
14231 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14232 tg3_flag_set(tp, NVRAM_BUFFERED);
14233 tg3_flag_set(tp, FLASH);
8590a603
MC		 14234 tp->nvram_pagesize = 256;
14235 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14236 tp->nvram_size = (protect ?
14237 TG3_NVRAM_SIZE_64KB :
14238 TG3_NVRAM_SIZE_128KB);
14239 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14240 tp->nvram_size = (protect ?
14241 TG3_NVRAM_SIZE_64KB :
14242 TG3_NVRAM_SIZE_256KB);
14243 else
14244 tp->nvram_size = (protect ?
14245 TG3_NVRAM_SIZE_128KB :
14246 TG3_NVRAM_SIZE_512KB);
14247 break;
d3c7b886
MC		 14248 }
14249}
14250
229b1ad1 14251static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14252{
14253 u32 nvcfg1;
14254
14255 nvcfg1 = tr32(NVRAM_CFG1);
14256
14257 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14258 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14259 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14260 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14261 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14262 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14263 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14264 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14265
8590a603
MC		 14266 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14267 tw32(NVRAM_CFG1, nvcfg1);
14268 break;
14269 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14270 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14271 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14272 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14273 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14274 tg3_flag_set(tp, NVRAM_BUFFERED);
14275 tg3_flag_set(tp, FLASH);
8590a603
MC		 14276 tp->nvram_pagesize = 264;
14277 break;
14278 case FLASH_5752VENDOR_ST_M45PE10:
14279 case FLASH_5752VENDOR_ST_M45PE20:
14280 case FLASH_5752VENDOR_ST_M45PE40:
14281 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14282 tg3_flag_set(tp, NVRAM_BUFFERED);
14283 tg3_flag_set(tp, FLASH);
8590a603
MC		 14284 tp->nvram_pagesize = 256;
14285 break;
1b27777a
MC		 14286 }
14287}
14288
229b1ad1 14289static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14290{
14291 u32 nvcfg1, protect = 0;
14292
14293 nvcfg1 = tr32(NVRAM_CFG1);
14294
14295 /* NVRAM protection for TPM */
14296 if (nvcfg1 & (1 << 27)) {
63c3a66f 14297 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14298 protect = 1;
14299 }
14300
14301 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14302 switch (nvcfg1) {
8590a603
MC		 14303 case FLASH_5761VENDOR_ATMEL_ADB021D:
14304 case FLASH_5761VENDOR_ATMEL_ADB041D:
14305 case FLASH_5761VENDOR_ATMEL_ADB081D:
14306 case FLASH_5761VENDOR_ATMEL_ADB161D:
14307 case FLASH_5761VENDOR_ATMEL_MDB021D:
14308 case FLASH_5761VENDOR_ATMEL_MDB041D:
14309 case FLASH_5761VENDOR_ATMEL_MDB081D:
14310 case FLASH_5761VENDOR_ATMEL_MDB161D:
14311 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14312 tg3_flag_set(tp, NVRAM_BUFFERED);
14313 tg3_flag_set(tp, FLASH);
14314 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14315 tp->nvram_pagesize = 256;
14316 break;
14317 case FLASH_5761VENDOR_ST_A_M45PE20:
14318 case FLASH_5761VENDOR_ST_A_M45PE40:
14319 case FLASH_5761VENDOR_ST_A_M45PE80:
14320 case FLASH_5761VENDOR_ST_A_M45PE16:
14321 case FLASH_5761VENDOR_ST_M_M45PE20:
14322 case FLASH_5761VENDOR_ST_M_M45PE40:
14323 case FLASH_5761VENDOR_ST_M_M45PE80:
14324 case FLASH_5761VENDOR_ST_M_M45PE16:
14325 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14326 tg3_flag_set(tp, NVRAM_BUFFERED);
14327 tg3_flag_set(tp, FLASH);
8590a603
MC		 14328 tp->nvram_pagesize = 256;
14329 break;
6b91fa02
MC		 14330 }
14331
14332 if (protect) {
14333 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14334 } else {
14335 switch (nvcfg1) {
8590a603
MC		 14336 case FLASH_5761VENDOR_ATMEL_ADB161D:
14337 case FLASH_5761VENDOR_ATMEL_MDB161D:
14338 case FLASH_5761VENDOR_ST_A_M45PE16:
14339 case FLASH_5761VENDOR_ST_M_M45PE16:
14340 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14341 break;
14342 case FLASH_5761VENDOR_ATMEL_ADB081D:
14343 case FLASH_5761VENDOR_ATMEL_MDB081D:
14344 case FLASH_5761VENDOR_ST_A_M45PE80:
14345 case FLASH_5761VENDOR_ST_M_M45PE80:
14346 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14347 break;
14348 case FLASH_5761VENDOR_ATMEL_ADB041D:
14349 case FLASH_5761VENDOR_ATMEL_MDB041D:
14350 case FLASH_5761VENDOR_ST_A_M45PE40:
14351 case FLASH_5761VENDOR_ST_M_M45PE40:
14352 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14353 break;
14354 case FLASH_5761VENDOR_ATMEL_ADB021D:
14355 case FLASH_5761VENDOR_ATMEL_MDB021D:
14356 case FLASH_5761VENDOR_ST_A_M45PE20:
14357 case FLASH_5761VENDOR_ST_M_M45PE20:
14358 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14359 break;
6b91fa02
MC		 14360 }
14361 }
14362}
14363
229b1ad1 14364static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14365{
14366 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14367 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14368 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14369}
14370
229b1ad1 14371static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14372{
14373 u32 nvcfg1;
14374
14375 nvcfg1 = tr32(NVRAM_CFG1);
14376
14377 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14378 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14379 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14380 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14381 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14382 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14383
14384 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14385 tw32(NVRAM_CFG1, nvcfg1);
14386 return;
14387 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14388 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14389 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14390 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14391 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14392 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14393 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14394 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14395 tg3_flag_set(tp, NVRAM_BUFFERED);
14396 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14397
14398 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14399 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14400 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14401 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14402 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14403 break;
14404 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14405 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14406 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14407 break;
14408 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14409 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14410 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14411 break;
14412 }
14413 break;
14414 case FLASH_5752VENDOR_ST_M45PE10:
14415 case FLASH_5752VENDOR_ST_M45PE20:
14416 case FLASH_5752VENDOR_ST_M45PE40:
14417 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14418 tg3_flag_set(tp, NVRAM_BUFFERED);
14419 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14420
14421 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14422 case FLASH_5752VENDOR_ST_M45PE10:
14423 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14424 break;
14425 case FLASH_5752VENDOR_ST_M45PE20:
14426 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14427 break;
14428 case FLASH_5752VENDOR_ST_M45PE40:
14429 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14430 break;
14431 }
14432 break;
14433 default:
63c3a66f 14434 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14435 return;
14436 }
14437
a1b950d5
MC		 14438 tg3_nvram_get_pagesize(tp, nvcfg1);
14439 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14440 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14441}
14442
14443
229b1ad1 14444static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14445{
14446 u32 nvcfg1;
14447
14448 nvcfg1 = tr32(NVRAM_CFG1);
14449
14450 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14451 case FLASH_5717VENDOR_ATMEL_EEPROM:
14452 case FLASH_5717VENDOR_MICRO_EEPROM:
14453 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14454 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14455 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14456
14457 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14458 tw32(NVRAM_CFG1, nvcfg1);
14459 return;
14460 case FLASH_5717VENDOR_ATMEL_MDB011D:
14461 case FLASH_5717VENDOR_ATMEL_ADB011B:
14462 case FLASH_5717VENDOR_ATMEL_ADB011D:
14463 case FLASH_5717VENDOR_ATMEL_MDB021D:
14464 case FLASH_5717VENDOR_ATMEL_ADB021B:
14465 case FLASH_5717VENDOR_ATMEL_ADB021D:
14466 case FLASH_5717VENDOR_ATMEL_45USPT:
14467 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14468 tg3_flag_set(tp, NVRAM_BUFFERED);
14469 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14470
14471 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14472 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14473 /* Detect size with tg3_nvram_get_size() */
14474 break;
a1b950d5
MC		 14475 case FLASH_5717VENDOR_ATMEL_ADB021B:
14476 case FLASH_5717VENDOR_ATMEL_ADB021D:
14477 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14478 break;
14479 default:
14480 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14481 break;
14482 }
321d32a0 14483 break;
a1b950d5
MC		 14484 case FLASH_5717VENDOR_ST_M_M25PE10:
14485 case FLASH_5717VENDOR_ST_A_M25PE10:
14486 case FLASH_5717VENDOR_ST_M_M45PE10:
14487 case FLASH_5717VENDOR_ST_A_M45PE10:
14488 case FLASH_5717VENDOR_ST_M_M25PE20:
14489 case FLASH_5717VENDOR_ST_A_M25PE20:
14490 case FLASH_5717VENDOR_ST_M_M45PE20:
14491 case FLASH_5717VENDOR_ST_A_M45PE20:
14492 case FLASH_5717VENDOR_ST_25USPT:
14493 case FLASH_5717VENDOR_ST_45USPT:
14494 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14495 tg3_flag_set(tp, NVRAM_BUFFERED);
14496 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14497
14498 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14499 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14500 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14501 /* Detect size with tg3_nvram_get_size() */
14502 break;
14503 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14504 case FLASH_5717VENDOR_ST_A_M45PE20:
14505 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14506 break;
14507 default:
14508 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14509 break;
14510 }
321d32a0 14511 break;
a1b950d5 14512 default:
63c3a66f 14513 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14514 return;
321d32a0 14515 }
a1b950d5
MC		 14516
14517 tg3_nvram_get_pagesize(tp, nvcfg1);
14518 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14519 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14520}
14521
229b1ad1 14522static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14523{
14524 u32 nvcfg1, nvmpinstrp;
14525
14526 nvcfg1 = tr32(NVRAM_CFG1);
14527 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14528
4153577a 14529 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14530 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14531 tg3_flag_set(tp, NO_NVRAM);
14532 return;
14533 }
14534
14535 switch (nvmpinstrp) {
14536 case FLASH_5762_EEPROM_HD:
14537 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14538 break;
c86a8560
MC		 14539 case FLASH_5762_EEPROM_LD:
14540 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14541 break;
f6334bb8
MC		 14542 case FLASH_5720VENDOR_M_ST_M45PE20:
14543 /* This pinstrap supports multiple sizes, so force it
14544 * to read the actual size from location 0xf0.
14545 */
14546 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14547 break;
c86a8560
MC		 14548 }
14549 }
14550
9b91b5f1
MC		 14551 switch (nvmpinstrp) {
14552 case FLASH_5720_EEPROM_HD:
14553 case FLASH_5720_EEPROM_LD:
14554 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14555 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14556
14557 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14558 tw32(NVRAM_CFG1, nvcfg1);
14559 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14560 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14561 else
14562 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14563 return;
14564 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14565 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14566 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14567 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14568 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14569 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14570 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14571 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14572 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14573 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14574 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14575 case FLASH_5720VENDOR_ATMEL_45USPT:
14576 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14577 tg3_flag_set(tp, NVRAM_BUFFERED);
14578 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14579
14580 switch (nvmpinstrp) {
14581 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14582 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14583 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14584 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14585 break;
14586 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14587 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14588 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14589 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14590 break;
14591 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14592 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14593 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14594 break;
14595 default:
4153577a 14596 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14597 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14598 break;
14599 }
14600 break;
14601 case FLASH_5720VENDOR_M_ST_M25PE10:
14602 case FLASH_5720VENDOR_M_ST_M45PE10:
14603 case FLASH_5720VENDOR_A_ST_M25PE10:
14604 case FLASH_5720VENDOR_A_ST_M45PE10:
14605 case FLASH_5720VENDOR_M_ST_M25PE20:
14606 case FLASH_5720VENDOR_M_ST_M45PE20:
14607 case FLASH_5720VENDOR_A_ST_M25PE20:
14608 case FLASH_5720VENDOR_A_ST_M45PE20:
14609 case FLASH_5720VENDOR_M_ST_M25PE40:
14610 case FLASH_5720VENDOR_M_ST_M45PE40:
14611 case FLASH_5720VENDOR_A_ST_M25PE40:
14612 case FLASH_5720VENDOR_A_ST_M45PE40:
14613 case FLASH_5720VENDOR_M_ST_M25PE80:
14614 case FLASH_5720VENDOR_M_ST_M45PE80:
14615 case FLASH_5720VENDOR_A_ST_M25PE80:
14616 case FLASH_5720VENDOR_A_ST_M45PE80:
14617 case FLASH_5720VENDOR_ST_25USPT:
14618 case FLASH_5720VENDOR_ST_45USPT:
14619 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14620 tg3_flag_set(tp, NVRAM_BUFFERED);
14621 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14622
14623 switch (nvmpinstrp) {
14624 case FLASH_5720VENDOR_M_ST_M25PE20:
14625 case FLASH_5720VENDOR_M_ST_M45PE20:
14626 case FLASH_5720VENDOR_A_ST_M25PE20:
14627 case FLASH_5720VENDOR_A_ST_M45PE20:
14628 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14629 break;
14630 case FLASH_5720VENDOR_M_ST_M25PE40:
14631 case FLASH_5720VENDOR_M_ST_M45PE40:
14632 case FLASH_5720VENDOR_A_ST_M25PE40:
14633 case FLASH_5720VENDOR_A_ST_M45PE40:
14634 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14635 break;
14636 case FLASH_5720VENDOR_M_ST_M25PE80:
14637 case FLASH_5720VENDOR_M_ST_M45PE80:
14638 case FLASH_5720VENDOR_A_ST_M25PE80:
14639 case FLASH_5720VENDOR_A_ST_M45PE80:
14640 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14641 break;
14642 default:
4153577a 14643 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14644 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14645 break;
14646 }
14647 break;
14648 default:
63c3a66f 14649 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14650 return;
14651 }
14652
14653 tg3_nvram_get_pagesize(tp, nvcfg1);
14654 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14655 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14656
4153577a 14657 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14658 u32 val;
14659
14660 if (tg3_nvram_read(tp, 0, &val))
14661 return;
14662
14663 if (val != TG3_EEPROM_MAGIC &&
14664 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14665 tg3_flag_set(tp, NO_NVRAM);
14666 }
9b91b5f1
MC		 14667}
14668
1da177e4 14669/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14670static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14671{
7e6c63f0
HM		 14672 if (tg3_flag(tp, IS_SSB_CORE)) {
14673 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14674 tg3_flag_clear(tp, NVRAM);
14675 tg3_flag_clear(tp, NVRAM_BUFFERED);
14676 tg3_flag_set(tp, NO_NVRAM);
14677 return;
14678 }
14679
1da177e4
LT		 14680 tw32_f(GRC_EEPROM_ADDR,
14681 (EEPROM_ADDR_FSM_RESET |
14682 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14683 EEPROM_ADDR_CLKPERD_SHIFT)));
14684
9d57f01c 14685 msleep(1);
1da177e4
LT		 14686
14687 /* Enable seeprom accesses. */
14688 tw32_f(GRC_LOCAL_CTRL,
14689 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14690 udelay(100);
14691
4153577a
JP		 14692 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14693 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14694 tg3_flag_set(tp, NVRAM);
1da177e4 14695
ec41c7df 14696 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14697 netdev_warn(tp->dev,
14698 "Cannot get nvram lock, %s failed\n",
05dbe005 14699 __func__);
ec41c7df
MC		 14700 return;
14701 }
e6af301b 14702 tg3_enable_nvram_access(tp);
1da177e4 14703
989a9d23
MC		 14704 tp->nvram_size = 0;
14705
4153577a 14706 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14707 tg3_get_5752_nvram_info(tp);
4153577a 14708 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14709 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14710 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14711 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14712 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14713 tg3_get_5787_nvram_info(tp);
4153577a 14714 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14715 tg3_get_5761_nvram_info(tp);
4153577a 14716 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14717 tg3_get_5906_nvram_info(tp);
4153577a 14718 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14719 tg3_flag(tp, 57765_CLASS))
321d32a0 14720 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14721 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14722 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14723 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14724 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14725 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14726 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14727 else
14728 tg3_get_nvram_info(tp);
14729
989a9d23
MC		 14730 if (tp->nvram_size == 0)
14731 tg3_get_nvram_size(tp);
1da177e4 14732
e6af301b 14733 tg3_disable_nvram_access(tp);
381291b7 14734 tg3_nvram_unlock(tp);
1da177e4
LT		 14735
14736 } else {
63c3a66f
JP		 14737 tg3_flag_clear(tp, NVRAM);
14738 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14739
14740 tg3_get_eeprom_size(tp);
14741 }
14742}
14743
1da177e4
LT		 14744struct subsys_tbl_ent {
14745 u16 subsys_vendor, subsys_devid;
14746 u32 phy_id;
14747};
14748
229b1ad1 14749static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14750 /* Broadcom boards. */
24daf2b0 14751 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14752 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14753 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14754 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14755 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14756 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14757 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14758 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14759 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14760 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14761 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14762 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14763 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14764 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14765 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14766 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14767 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14768 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14769 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14770 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14771 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14772 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14773
14774 /* 3com boards. */
24daf2b0 14775 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14776 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 14777 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14778 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14779 { TG3PCI_SUBVENDOR_ID_3COM,
14780 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14781 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14782 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 14783 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14784 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14785
14786 /* DELL boards. */
24daf2b0 14787 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14788 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 14789 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14790 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 14791 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14792 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 14793 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14794 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 14795
14796 /* Compaq boards. */
24daf2b0 14797 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14798 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 14799 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14800 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14801 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14802 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14803 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14804 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 14805 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14806 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14807
14808 /* IBM boards. */
24daf2b0
MC		 14809 { TG3PCI_SUBVENDOR_ID_IBM,
14810 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 14811};
14812
229b1ad1 14813static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 14814{
14815 int i;
14816
14817 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14818 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14819 tp->pdev->subsystem_vendor) &&
14820 (subsys_id_to_phy_id[i].subsys_devid ==
14821 tp->pdev->subsystem_device))
14822 return &subsys_id_to_phy_id[i];
14823 }
14824 return NULL;
14825}
14826
229b1ad1 14827static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 14828{
1da177e4 14829 u32 val;
f49639e6 14830
79eb6904 14831 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 14832 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14833
a85feb8c 14834 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 14835 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14836 tg3_flag_set(tp, WOL_CAP);
72b845e0 14837
4153577a 14838 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 14839 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 14840 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14841 tg3_flag_set(tp, IS_NIC);
9d26e213 14842 }
0527ba35
MC		 14843 val = tr32(VCPU_CFGSHDW);
14844 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 14845 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 14846 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 14847 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 14848 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14849 device_set_wakeup_enable(&tp->pdev->dev, true);
14850 }
05ac4cb7 14851 goto done;
b5d3772c
MC		 14852 }
14853
1da177e4
LT		 14854 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14855 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14856 u32 nic_cfg, led_cfg;
a9daf367 14857 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 14858 int eeprom_phy_serdes = 0;
1da177e4
LT		 14859
14860 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
14861 tp->nic_sram_data_cfg = nic_cfg;
14862
14863 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
14864 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 14865 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14866 tg3_asic_rev(tp) != ASIC_REV_5701 &&
14867 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 14868 (ver > 0) && (ver < 0x100))
14869 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
14870
4153577a 14871 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 14872 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
14873
1da177e4
LT		 14874 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
14875 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
14876 eeprom_phy_serdes = 1;
14877
14878 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
14879 if (nic_phy_id != 0) {
14880 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
14881 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
14882
14883 eeprom_phy_id = (id1 >> 16) << 10;
14884 eeprom_phy_id |= (id2 & 0xfc00) << 16;
14885 eeprom_phy_id |= (id2 & 0x03ff) << 0;
14886 } else
14887 eeprom_phy_id = 0;
14888
7d0c41ef 14889 tp->phy_id = eeprom_phy_id;
747e8f8b 14890 if (eeprom_phy_serdes) {
63c3a66f 14891 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 14892 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 14893 else
f07e9af3 14894 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 14895 }
7d0c41ef 14896
63c3a66f 14897 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 14898 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
14899 SHASTA_EXT_LED_MODE_MASK);
cbf46853 14900 else
1da177e4
LT		 14901 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
14902
14903 switch (led_cfg) {
14904 default:
14905 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
14906 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14907 break;
14908
14909 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
14910 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14911 break;
14912
14913 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
14914 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 14915
14916 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
14917 * read on some older 5700/5701 bootcode.
14918 */
4153577a
JP		 14919 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
14920 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 14921 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14922
1da177e4
LT		 14923 break;
14924
14925 case SHASTA_EXT_LED_SHARED:
14926 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 14927 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
14928 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 14929 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14930 LED_CTRL_MODE_PHY_2);
14931 break;
14932
14933 case SHASTA_EXT_LED_MAC:
14934 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
14935 break;
14936
14937 case SHASTA_EXT_LED_COMBO:
14938 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 14939 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 14940 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14941 LED_CTRL_MODE_PHY_2);
14942 break;
14943
855e1111 14944 }
1da177e4 14945
4153577a
JP		 14946 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
14947 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 14948 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
14949 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14950
4153577a 14951 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 14952 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 14953
9d26e213 14954 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 14955 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 14956 if ((tp->pdev->subsystem_vendor ==
14957 PCI_VENDOR_ID_ARIMA) &&
14958 (tp->pdev->subsystem_device == 0x205a ||
14959 tp->pdev->subsystem_device == 0x2063))
63c3a66f 14960 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 14961 } else {
63c3a66f
JP		 14962 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14963 tg3_flag_set(tp, IS_NIC);
9d26e213 14964 }
1da177e4
LT		 14965
14966 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 14967 tg3_flag_set(tp, ENABLE_ASF);
14968 if (tg3_flag(tp, 5750_PLUS))
14969 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 14970 }
b2b98d4a
MC		 14971
14972 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 14973 tg3_flag(tp, 5750_PLUS))
14974 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 14975
f07e9af3 14976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 14977 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 14978 tg3_flag_clear(tp, WOL_CAP);
1da177e4 14979
63c3a66f 14980 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 14981 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 14982 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14983 device_set_wakeup_enable(&tp->pdev->dev, true);
14984 }
0527ba35 14985
1da177e4 14986 if (cfg2 & (1 << 17))
f07e9af3 14987 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 14988
14989 /* serdes signal pre-emphasis in register 0x590 set by */
14990 /* bootcode if bit 18 is set */
14991 if (cfg2 & (1 << 18))
f07e9af3 14992 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 14993
63c3a66f 14994 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 14995 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
14996 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 14997 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 14998 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 14999
942d1af0 15000 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 15001 u32 cfg3;
15002
15003 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 15004 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15005 !tg3_flag(tp, 57765_PLUS) &&
15006 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15007 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15008 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15009 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15010 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15011 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15012 }
a9daf367 15013
14417063 15014 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15015 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15016 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15017 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15018 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15019 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
1da177e4 15020 }
05ac4cb7 15021done:
63c3a66f 15022 if (tg3_flag(tp, WOL_CAP))
43067ed8 15023 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15024 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15025 else
15026 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15027}
15028
c86a8560
MC		 15029static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15030{
15031 int i, err;
15032 u32 val2, off = offset * 8;
15033
15034 err = tg3_nvram_lock(tp);
15035 if (err)
15036 return err;
15037
15038 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15039 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15040 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15041 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15042 udelay(10);
15043
15044 for (i = 0; i < 100; i++) {
15045 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15046 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15047 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15048 break;
15049 }
15050 udelay(10);
15051 }
15052
15053 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15054
15055 tg3_nvram_unlock(tp);
15056 if (val2 & APE_OTP_STATUS_CMD_DONE)
15057 return 0;
15058
15059 return -EBUSY;
15060}
15061
229b1ad1 15062static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15063{
15064 int i;
15065 u32 val;
15066
15067 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15068 tw32(OTP_CTRL, cmd);
15069
15070 /* Wait for up to 1 ms for command to execute. */
15071 for (i = 0; i < 100; i++) {
15072 val = tr32(OTP_STATUS);
15073 if (val & OTP_STATUS_CMD_DONE)
15074 break;
15075 udelay(10);
15076 }
15077
15078 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15079}
15080
15081/* Read the gphy configuration from the OTP region of the chip. The gphy
15082 * configuration is a 32-bit value that straddles the alignment boundary.
15083 * We do two 32-bit reads and then shift and merge the results.
15084 */
229b1ad1 15085static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15086{
15087 u32 bhalf_otp, thalf_otp;
15088
15089 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15090
15091 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15092 return 0;
15093
15094 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15095
15096 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15097 return 0;
15098
15099 thalf_otp = tr32(OTP_READ_DATA);
15100
15101 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15102
15103 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15104 return 0;
15105
15106 bhalf_otp = tr32(OTP_READ_DATA);
15107
15108 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15109}
15110
229b1ad1 15111static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15112{
202ff1c2 15113 u32 adv = ADVERTISED_Autoneg;
e256f8a3
MC		 15114
15115 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15116 adv |= ADVERTISED_1000baseT_Half |
15117 ADVERTISED_1000baseT_Full;
15118
15119 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15120 adv |= ADVERTISED_100baseT_Half |
15121 ADVERTISED_100baseT_Full |
15122 ADVERTISED_10baseT_Half |
15123 ADVERTISED_10baseT_Full |
15124 ADVERTISED_TP;
15125 else
15126 adv |= ADVERTISED_FIBRE;
15127
15128 tp->link_config.advertising = adv;
e740522e
MC		 15129 tp->link_config.speed = SPEED_UNKNOWN;
15130 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15131 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15132 tp->link_config.active_speed = SPEED_UNKNOWN;
15133 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15134
15135 tp->old_link = -1;
e256f8a3
MC		 15136}
15137
229b1ad1 15138static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15139{
15140 u32 hw_phy_id_1, hw_phy_id_2;
15141 u32 hw_phy_id, hw_phy_id_masked;
15142 int err;
1da177e4 15143
e256f8a3 15144 /* flow control autonegotiation is default behavior */
63c3a66f 15145 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15146 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15147
8151ad57
MC		 15148 if (tg3_flag(tp, ENABLE_APE)) {
15149 switch (tp->pci_fn) {
15150 case 0:
15151 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15152 break;
15153 case 1:
15154 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15155 break;
15156 case 2:
15157 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15158 break;
15159 case 3:
15160 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15161 break;
15162 }
15163 }
15164
942d1af0
NS		 15165 if (!tg3_flag(tp, ENABLE_ASF) &&
15166 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15167 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15168 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15169 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15170
63c3a66f 15171 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15172 return tg3_phy_init(tp);
15173
1da177e4 15174 /* Reading the PHY ID register can conflict with ASF
877d0310 15175 * firmware access to the PHY hardware.
1da177e4
LT		 15176 */
15177 err = 0;
63c3a66f 15178 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15179 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15180 } else {
15181 /* Now read the physical PHY_ID from the chip and verify
15182 * that it is sane. If it doesn't look good, we fall back
15183 * to either the hard-coded table based PHY_ID and failing
15184 * that the value found in the eeprom area.
15185 */
15186 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15187 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15188
15189 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15190 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15191 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15192
79eb6904 15193 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15194 }
15195
79eb6904 15196 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15197 tp->phy_id = hw_phy_id;
79eb6904 15198 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15199 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15200 else
f07e9af3 15201 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15202 } else {
79eb6904 15203 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15204 /* Do nothing, phy ID already set up in
15205 * tg3_get_eeprom_hw_cfg().
15206 */
1da177e4
LT		 15207 } else {
15208 struct subsys_tbl_ent *p;
15209
15210 /* No eeprom signature? Try the hardcoded
15211 * subsys device table.
15212 */
24daf2b0 15213 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15214 if (p) {
15215 tp->phy_id = p->phy_id;
15216 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15217 /* For now we saw the IDs 0xbc050cd0,
15218 * 0xbc050f80 and 0xbc050c30 on devices
15219 * connected to an BCM4785 and there are
15220 * probably more. Just assume that the phy is
15221 * supported when it is connected to a SSB core
15222 * for now.
15223 */
1da177e4 15224 return -ENODEV;
7e6c63f0 15225 }
1da177e4 15226
1da177e4 15227 if (!tp->phy_id ||
79eb6904 15228 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15229 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15230 }
15231 }
15232
a6b68dab 15233 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15234 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15235 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15236 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15237 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15238 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15239 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15240 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15241 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15242 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15243
9e2ecbeb
NS		 15244 tp->eee.supported = SUPPORTED_100baseT_Full |
15245 SUPPORTED_1000baseT_Full;
15246 tp->eee.advertised = ADVERTISED_100baseT_Full |
15247 ADVERTISED_1000baseT_Full;
15248 tp->eee.eee_enabled = 1;
15249 tp->eee.tx_lpi_enabled = 1;
15250 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15251 }
15252
e256f8a3
MC		 15253 tg3_phy_init_link_config(tp);
15254
942d1af0
NS		 15255 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15256 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15257 !tg3_flag(tp, ENABLE_APE) &&
15258 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15259 u32 bmsr, dummy;
1da177e4
LT		 15260
15261 tg3_readphy(tp, MII_BMSR, &bmsr);
15262 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15263 (bmsr & BMSR_LSTATUS))
15264 goto skip_phy_reset;
6aa20a22 15265
1da177e4
LT		 15266 err = tg3_phy_reset(tp);
15267 if (err)
15268 return err;
15269
42b64a45 15270 tg3_phy_set_wirespeed(tp);
1da177e4 15271
e2bf73e7 15272 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15273 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15274 tp->link_config.flowctrl);
1da177e4
LT		 15275
15276 tg3_writephy(tp, MII_BMCR,
15277 BMCR_ANENABLE | BMCR_ANRESTART);
15278 }
1da177e4
LT		 15279 }
15280
15281skip_phy_reset:
79eb6904 15282 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15283 err = tg3_init_5401phy_dsp(tp);
15284 if (err)
15285 return err;
1da177e4 15286
1da177e4
LT		 15287 err = tg3_init_5401phy_dsp(tp);
15288 }
15289
1da177e4
LT		 15290 return err;
15291}
15292
229b1ad1 15293static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15294{
a4a8bb15 15295 u8 *vpd_data;
4181b2c8 15296 unsigned int block_end, rosize, len;
535a490e 15297 u32 vpdlen;
184b8904 15298 int j, i = 0;
a4a8bb15 15299
535a490e 15300 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15301 if (!vpd_data)
15302 goto out_no_vpd;
1da177e4 15303
535a490e 15304 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15305 if (i < 0)
15306 goto out_not_found;
1da177e4 15307
4181b2c8
MC		 15308 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15309 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15310 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15311
535a490e 15312 if (block_end > vpdlen)
4181b2c8 15313 goto out_not_found;
af2c6a4a 15314
184b8904
MC		 15315 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15316 PCI_VPD_RO_KEYWORD_MFR_ID);
15317 if (j > 0) {
15318 len = pci_vpd_info_field_size(&vpd_data[j]);
15319
15320 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15321 if (j + len > block_end || len != 4 ||
15322 memcmp(&vpd_data[j], "1028", 4))
15323 goto partno;
15324
15325 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15326 PCI_VPD_RO_KEYWORD_VENDOR0);
15327 if (j < 0)
15328 goto partno;
15329
15330 len = pci_vpd_info_field_size(&vpd_data[j]);
15331
15332 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15333 if (j + len > block_end)
15334 goto partno;
15335
715230a4
KC		 15336 if (len >= sizeof(tp->fw_ver))
15337 len = sizeof(tp->fw_ver) - 1;
15338 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15339 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15340 &vpd_data[j]);
184b8904
MC		 15341 }
15342
15343partno:
4181b2c8
MC		 15344 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15345 PCI_VPD_RO_KEYWORD_PARTNO);
15346 if (i < 0)
15347 goto out_not_found;
af2c6a4a 15348
4181b2c8 15349 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15350
4181b2c8
MC		 15351 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15352 if (len > TG3_BPN_SIZE ||
535a490e 15353 (len + i) > vpdlen)
4181b2c8 15354 goto out_not_found;
1da177e4 15355
4181b2c8 15356 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15357
1da177e4 15358out_not_found:
a4a8bb15 15359 kfree(vpd_data);
37a949c5 15360 if (tp->board_part_number[0])
a4a8bb15
MC		 15361 return;
15362
15363out_no_vpd:
4153577a 15364 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15365 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15366 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15367 strcpy(tp->board_part_number, "BCM5717");
15368 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15369 strcpy(tp->board_part_number, "BCM5718");
15370 else
15371 goto nomatch;
4153577a 15372 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15373 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15374 strcpy(tp->board_part_number, "BCM57780");
15375 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15376 strcpy(tp->board_part_number, "BCM57760");
15377 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15378 strcpy(tp->board_part_number, "BCM57790");
15379 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15380 strcpy(tp->board_part_number, "BCM57788");
15381 else
15382 goto nomatch;
4153577a 15383 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15384 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15385 strcpy(tp->board_part_number, "BCM57761");
15386 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15387 strcpy(tp->board_part_number, "BCM57765");
15388 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15389 strcpy(tp->board_part_number, "BCM57781");
15390 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15391 strcpy(tp->board_part_number, "BCM57785");
15392 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15393 strcpy(tp->board_part_number, "BCM57791");
15394 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15395 strcpy(tp->board_part_number, "BCM57795");
15396 else
15397 goto nomatch;
4153577a 15398 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15399 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15400 strcpy(tp->board_part_number, "BCM57762");
15401 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15402 strcpy(tp->board_part_number, "BCM57766");
15403 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15404 strcpy(tp->board_part_number, "BCM57782");
15405 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15406 strcpy(tp->board_part_number, "BCM57786");
15407 else
15408 goto nomatch;
4153577a 15409 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15410 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15411 } else {
15412nomatch:
b5d3772c 15413 strcpy(tp->board_part_number, "none");
37a949c5 15414 }
1da177e4
LT		 15415}
15416
229b1ad1 15417static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15418{
15419 u32 val;
15420
e4f34110 15421 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15422 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15423 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15424 val != 0)
15425 return 0;
15426
15427 return 1;
15428}
15429
229b1ad1 15430static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15431{
ff3a7cb2 15432 u32 val, offset, start, ver_offset;
75f9936e 15433 int i, dst_off;
ff3a7cb2 15434 bool newver = false;
acd9c119
MC		 15435
15436 if (tg3_nvram_read(tp, 0xc, &offset) ||
15437 tg3_nvram_read(tp, 0x4, &start))
15438 return;
15439
15440 offset = tg3_nvram_logical_addr(tp, offset);
15441
ff3a7cb2 15442 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15443 return;
15444
ff3a7cb2
MC		 15445 if ((val & 0xfc000000) == 0x0c000000) {
15446 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15447 return;
15448
ff3a7cb2
MC		 15449 if (val == 0)
15450 newver = true;
15451 }
15452
75f9936e
MC		 15453 dst_off = strlen(tp->fw_ver);
15454
ff3a7cb2 15455 if (newver) {
75f9936e
MC		 15456 if (TG3_VER_SIZE - dst_off < 16 ||
15457 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15458 return;
15459
15460 offset = offset + ver_offset - start;
15461 for (i = 0; i < 16; i += 4) {
15462 __be32 v;
15463 if (tg3_nvram_read_be32(tp, offset + i, &v))
15464 return;
15465
75f9936e 15466 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15467 }
15468 } else {
15469 u32 major, minor;
15470
15471 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15472 return;
15473
15474 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15475 TG3_NVM_BCVER_MAJSFT;
15476 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15477 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15478 "v%d.%02d", major, minor);
acd9c119
MC		 15479 }
15480}
15481
229b1ad1 15482static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15483{
15484 u32 val, major, minor;
15485
15486 /* Use native endian representation */
15487 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15488 return;
15489
15490 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15491 TG3_NVM_HWSB_CFG1_MAJSFT;
15492 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15493 TG3_NVM_HWSB_CFG1_MINSFT;
15494
15495 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15496}
15497
229b1ad1 15498static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15499{
15500 u32 offset, major, minor, build;
15501
75f9936e 15502 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15503
15504 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15505 return;
15506
15507 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15508 case TG3_EEPROM_SB_REVISION_0:
15509 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15510 break;
15511 case TG3_EEPROM_SB_REVISION_2:
15512 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15513 break;
15514 case TG3_EEPROM_SB_REVISION_3:
15515 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15516 break;
a4153d40
MC		 15517 case TG3_EEPROM_SB_REVISION_4:
15518 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15519 break;
15520 case TG3_EEPROM_SB_REVISION_5:
15521 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15522 break;
bba226ac
MC		 15523 case TG3_EEPROM_SB_REVISION_6:
15524 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15525 break;
dfe00d7d
MC		 15526 default:
15527 return;
15528 }
15529
e4f34110 15530 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15531 return;
15532
15533 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15534 TG3_EEPROM_SB_EDH_BLD_SHFT;
15535 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15536 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15537 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15538
15539 if (minor > 99 || build > 26)
15540 return;
15541
75f9936e
MC		 15542 offset = strlen(tp->fw_ver);
15543 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15544 " v%d.%02d", major, minor);
dfe00d7d
MC		 15545
15546 if (build > 0) {
75f9936e
MC		 15547 offset = strlen(tp->fw_ver);
15548 if (offset < TG3_VER_SIZE - 1)
15549 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15550 }
15551}
15552
229b1ad1 15553static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15554{
15555 u32 val, offset, start;
acd9c119 15556 int i, vlen;
9c8a620e
MC		 15557
15558 for (offset = TG3_NVM_DIR_START;
15559 offset < TG3_NVM_DIR_END;
15560 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15561 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15562 return;
15563
9c8a620e
MC		 15564 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15565 break;
15566 }
15567
15568 if (offset == TG3_NVM_DIR_END)
15569 return;
15570
63c3a66f 15571 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15572 start = 0x08000000;
e4f34110 15573 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15574 return;
15575
e4f34110 15576 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15577 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15578 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15579 return;
15580
15581 offset += val - start;
15582
acd9c119 15583 vlen = strlen(tp->fw_ver);
9c8a620e 15584
acd9c119
MC		 15585 tp->fw_ver[vlen++] = ',';
15586 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15587
15588 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15589 __be32 v;
15590 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15591 return;
15592
b9fc7dc5 15593 offset += sizeof(v);
c4e6575c 15594
acd9c119
MC		 15595 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15596 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15597 break;
c4e6575c 15598 }
9c8a620e 15599
acd9c119
MC		 15600 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15601 vlen += sizeof(v);
c4e6575c 15602 }
acd9c119
MC		 15603}
15604
229b1ad1 15605static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15606{
7fd76445 15607 u32 apedata;
7fd76445
MC		 15608
15609 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15610 if (apedata != APE_SEG_SIG_MAGIC)
15611 return;
15612
15613 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15614 if (!(apedata & APE_FW_STATUS_READY))
15615 return;
15616
165f4d1c
MC		 15617 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15618 tg3_flag_set(tp, APE_HAS_NCSI);
15619}
15620
229b1ad1 15621static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15622{
15623 int vlen;
15624 u32 apedata;
15625 char *fwtype;
15626
7fd76445
MC		 15627 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15628
165f4d1c 15629 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15630 fwtype = "NCSI";
c86a8560
MC		 15631 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15632 fwtype = "SMASH";
165f4d1c 15633 else
ecc79648
MC		 15634 fwtype = "DASH";
15635
7fd76445
MC		 15636 vlen = strlen(tp->fw_ver);
15637
ecc79648
MC		 15638 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15639 fwtype,
7fd76445
MC		 15640 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15641 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15642 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15643 (apedata & APE_FW_VERSION_BLDMSK));
15644}
15645
c86a8560
MC		 15646static void tg3_read_otp_ver(struct tg3 *tp)
15647{
15648 u32 val, val2;
15649
4153577a 15650 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15651 return;
15652
15653 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15654 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15655 TG3_OTP_MAGIC0_VALID(val)) {
15656 u64 val64 = (u64) val << 32 | val2;
15657 u32 ver = 0;
15658 int i, vlen;
15659
15660 for (i = 0; i < 7; i++) {
15661 if ((val64 & 0xff) == 0)
15662 break;
15663 ver = val64 & 0xff;
15664 val64 >>= 8;
15665 }
15666 vlen = strlen(tp->fw_ver);
15667 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15668 }
15669}
15670
229b1ad1 15671static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15672{
15673 u32 val;
75f9936e 15674 bool vpd_vers = false;
acd9c119 15675
75f9936e
MC		 15676 if (tp->fw_ver[0] != 0)
15677 vpd_vers = true;
df259d8c 15678
63c3a66f 15679 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15680 strcat(tp->fw_ver, "sb");
c86a8560 15681 tg3_read_otp_ver(tp);
df259d8c
MC		 15682 return;
15683 }
15684
acd9c119
MC		 15685 if (tg3_nvram_read(tp, 0, &val))
15686 return;
15687
15688 if (val == TG3_EEPROM_MAGIC)
15689 tg3_read_bc_ver(tp);
15690 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15691 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15692 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15693 tg3_read_hwsb_ver(tp);
acd9c119 15694
165f4d1c
MC		 15695 if (tg3_flag(tp, ENABLE_ASF)) {
15696 if (tg3_flag(tp, ENABLE_APE)) {
15697 tg3_probe_ncsi(tp);
15698 if (!vpd_vers)
15699 tg3_read_dash_ver(tp);
15700 } else if (!vpd_vers) {
15701 tg3_read_mgmtfw_ver(tp);
15702 }
c9cab24e 15703 }
9c8a620e
MC		 15704
15705 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15706}
15707
7cb32cf2
MC		 15708static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15709{
63c3a66f 15710 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15711 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15712 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15713 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15714 else
de9f5230 15715 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15716}
15717
4143470c 15718static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
895950c2
JP		 15719 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15720 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15721 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15722 { },
15723};
15724
229b1ad1 15725static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15726{
15727 struct pci_dev *peer;
15728 unsigned int func, devnr = tp->pdev->devfn & ~7;
15729
15730 for (func = 0; func < 8; func++) {
15731 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15732 if (peer && peer != tp->pdev)
15733 break;
15734 pci_dev_put(peer);
15735 }
15736 /* 5704 can be configured in single-port mode, set peer to
15737 * tp->pdev in that case.
15738 */
15739 if (!peer) {
15740 peer = tp->pdev;
15741 return peer;
15742 }
15743
15744 /*
15745 * We don't need to keep the refcount elevated; there's no way
15746 * to remove one half of this device without removing the other
15747 */
15748 pci_dev_put(peer);
15749
15750 return peer;
15751}
15752
229b1ad1 15753static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15754{
15755 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15756 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15757 u32 reg;
15758
15759 /* All devices that use the alternate
15760 * ASIC REV location have a CPMU.
15761 */
15762 tg3_flag_set(tp, CPMU_PRESENT);
15763
15764 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 15765 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 15766 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15767 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 15768 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 15769 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15770 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 15771 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15772 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 15773 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15774 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
42b123b1
MC		 15775 reg = TG3PCI_GEN2_PRODID_ASICREV;
15776 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15777 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15778 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15779 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15780 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15781 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15782 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15783 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15784 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15785 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15786 reg = TG3PCI_GEN15_PRODID_ASICREV;
15787 else
15788 reg = TG3PCI_PRODID_ASICREV;
15789
15790 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15791 }
15792
15793 /* Wrong chip ID in 5752 A0. This code can be removed later
15794 * as A0 is not in production.
15795 */
4153577a 15796 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 15797 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15798
4153577a 15799 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 15800 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15801
4153577a
JP		 15802 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15803 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15804 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 15805 tg3_flag_set(tp, 5717_PLUS);
15806
4153577a
JP		 15807 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15808 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 15809 tg3_flag_set(tp, 57765_CLASS);
15810
c65a17f4 15811 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 15812 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 15813 tg3_flag_set(tp, 57765_PLUS);
15814
15815 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 15816 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15817 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15818 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15819 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15820 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15821 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 15822 tg3_flag(tp, 57765_PLUS))
15823 tg3_flag_set(tp, 5755_PLUS);
15824
4153577a
JP		 15825 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15826 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 15827 tg3_flag_set(tp, 5780_CLASS);
15828
4153577a
JP		 15829 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15830 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15831 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 15832 tg3_flag(tp, 5755_PLUS) ||
15833 tg3_flag(tp, 5780_CLASS))
15834 tg3_flag_set(tp, 5750_PLUS);
15835
4153577a 15836 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 15837 tg3_flag(tp, 5750_PLUS))
15838 tg3_flag_set(tp, 5705_PLUS);
15839}
15840
3d567e0e
NNS		 15841static bool tg3_10_100_only_device(struct tg3 *tp,
15842 const struct pci_device_id *ent)
15843{
15844 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
15845
4153577a
JP		 15846 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
15847 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 15848 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15849 return true;
15850
15851 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 15852 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 15853 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
15854 return true;
15855 } else {
15856 return true;
15857 }
15858 }
15859
15860 return false;
15861}
15862
1dd06ae8 15863static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 15864{
1da177e4 15865 u32 misc_ctrl_reg;
1da177e4
LT		 15866 u32 pci_state_reg, grc_misc_cfg;
15867 u32 val;
15868 u16 pci_cmd;
5e7dfd0f 15869 int err;
1da177e4 15870
1da177e4
LT		 15871 /* Force memory write invalidate off. If we leave it on,
15872 * then on 5700_BX chips we have to enable a workaround.
15873 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15874 * to match the cacheline size. The Broadcom driver have this
15875 * workaround but turns MWI off all the times so never uses
15876 * it. This seems to suggest that the workaround is insufficient.
15877 */
15878 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15879 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
15880 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15881
16821285
MC		 15882 /* Important! -- Make sure register accesses are byteswapped
15883 * correctly. Also, for those chips that require it, make
15884 * sure that indirect register accesses are enabled before
15885 * the first operation.
1da177e4
LT		 15886 */
15887 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15888 &misc_ctrl_reg);
16821285
MC		 15889 tp->misc_host_ctrl |= (misc_ctrl_reg &
15890 MISC_HOST_CTRL_CHIPREV);
15891 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15892 tp->misc_host_ctrl);
1da177e4 15893
42b123b1 15894 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 15895
6892914f
MC		 15896 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
15897 * we need to disable memory and use config. cycles
15898 * only to access all registers. The 5702/03 chips
15899 * can mistakenly decode the special cycles from the
15900 * ICH chipsets as memory write cycles, causing corruption
15901 * of register and memory space. Only certain ICH bridges
15902 * will drive special cycles with non-zero data during the
15903 * address phase which can fall within the 5703's address
15904 * range. This is not an ICH bug as the PCI spec allows
15905 * non-zero address during special cycles. However, only
15906 * these ICH bridges are known to drive non-zero addresses
15907 * during special cycles.
15908 *
15909 * Since special cycles do not cross PCI bridges, we only
15910 * enable this workaround if the 5703 is on the secondary
15911 * bus of these ICH bridges.
15912 */
4153577a
JP		 15913 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
15914 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 15915 static struct tg3_dev_id {
15916 u32 vendor;
15917 u32 device;
15918 u32 rev;
15919 } ich_chipsets[] = {
15920 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
15921 PCI_ANY_ID },
15922 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
15923 PCI_ANY_ID },
15924 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
15925 0xa },
15926 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
15927 PCI_ANY_ID },
15928 { },
15929 };
15930 struct tg3_dev_id *pci_id = &ich_chipsets[0];
15931 struct pci_dev *bridge = NULL;
15932
15933 while (pci_id->vendor != 0) {
15934 bridge = pci_get_device(pci_id->vendor, pci_id->device,
15935 bridge);
15936 if (!bridge) {
15937 pci_id++;
15938 continue;
15939 }
15940 if (pci_id->rev != PCI_ANY_ID) {
44c10138 15941 if (bridge->revision > pci_id->rev)
6892914f
MC		 15942 continue;
15943 }
15944 if (bridge->subordinate &&
15945 (bridge->subordinate->number ==
15946 tp->pdev->bus->number)) {
63c3a66f 15947 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 15948 pci_dev_put(bridge);
15949 break;
15950 }
15951 }
15952 }
15953
4153577a 15954 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 15955 static struct tg3_dev_id {
15956 u32 vendor;
15957 u32 device;
15958 } bridge_chipsets[] = {
15959 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
15960 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
15961 { },
15962 };
15963 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
15964 struct pci_dev *bridge = NULL;
15965
15966 while (pci_id->vendor != 0) {
15967 bridge = pci_get_device(pci_id->vendor,
15968 pci_id->device,
15969 bridge);
15970 if (!bridge) {
15971 pci_id++;
15972 continue;
15973 }
15974 if (bridge->subordinate &&
15975 (bridge->subordinate->number <=
15976 tp->pdev->bus->number) &&
b918c62e 15977 (bridge->subordinate->busn_res.end >=
41588ba1 15978 tp->pdev->bus->number)) {
63c3a66f 15979 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 15980 pci_dev_put(bridge);
15981 break;
15982 }
15983 }
15984 }
15985
4a29cc2e
MC		 15986 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
15987 * DMA addresses > 40-bit. This bridge may have other additional
15988 * 57xx devices behind it in some 4-port NIC designs for example.
15989 * Any tg3 device found behind the bridge will also need the 40-bit
15990 * DMA workaround.
15991 */
42b123b1 15992 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 15993 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 15994 tp->msi_cap = tp->pdev->msi_cap;
859a5887 15995 } else {
4a29cc2e
MC		 15996 struct pci_dev *bridge = NULL;
15997
15998 do {
15999 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16000 PCI_DEVICE_ID_SERVERWORKS_EPB,
16001 bridge);
16002 if (bridge && bridge->subordinate &&
16003 (bridge->subordinate->number <=
16004 tp->pdev->bus->number) &&
b918c62e 16005 (bridge->subordinate->busn_res.end >=
4a29cc2e 16006 tp->pdev->bus->number)) {
63c3a66f 16007 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 16008 pci_dev_put(bridge);
16009 break;
16010 }
16011 } while (bridge);
16012 }
4cf78e4f 16013
4153577a
JP		 16014 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16015 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16016 tp->pdev_peer = tg3_find_peer(tp);
16017
507399f1 16018 /* Determine TSO capabilities */
4153577a 16019 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16020 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16021 else if (tg3_flag(tp, 57765_PLUS))
16022 tg3_flag_set(tp, HW_TSO_3);
16023 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16024 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16025 tg3_flag_set(tp, HW_TSO_2);
16026 else if (tg3_flag(tp, 5750_PLUS)) {
16027 tg3_flag_set(tp, HW_TSO_1);
16028 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16029 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16030 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16031 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16032 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16033 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16034 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16035 tg3_flag_set(tp, FW_TSO);
16036 tg3_flag_set(tp, TSO_BUG);
4153577a 16037 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16038 tp->fw_needed = FIRMWARE_TG3TSO5;
16039 else
16040 tp->fw_needed = FIRMWARE_TG3TSO;
16041 }
16042
dabc5c67 16043 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16044 if (tg3_flag(tp, HW_TSO_1) ||
16045 tg3_flag(tp, HW_TSO_2) ||
16046 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16047 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16048 /* For firmware TSO, assume ASF is disabled.
16049 * We'll disable TSO later if we discover ASF
16050 * is enabled in tg3_get_eeprom_hw_cfg().
16051 */
dabc5c67 16052 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16053 } else {
dabc5c67
MC		 16054 tg3_flag_clear(tp, TSO_CAPABLE);
16055 tg3_flag_clear(tp, TSO_BUG);
16056 tp->fw_needed = NULL;
16057 }
16058
4153577a 16059 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16060 tp->fw_needed = FIRMWARE_TG3;
16061
c4dab506
NS		 16062 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16063 tp->fw_needed = FIRMWARE_TG357766;
16064
507399f1
MC		 16065 tp->irq_max = 1;
16066
63c3a66f
JP		 16067 if (tg3_flag(tp, 5750_PLUS)) {
16068 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16069 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16070 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16071 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16072 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16073 tp->pdev_peer == tp->pdev))
63c3a66f 16074 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16075
63c3a66f 16076 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16077 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16078 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16079 }
4f125f42 16080
63c3a66f
JP		 16081 if (tg3_flag(tp, 57765_PLUS)) {
16082 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16083 tp->irq_max = TG3_IRQ_MAX_VECS;
16084 }
f6eb9b1f 16085 }
0e1406dd 16086
9102426a
MC		 16087 tp->txq_max = 1;
16088 tp->rxq_max = 1;
16089 if (tp->irq_max > 1) {
16090 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16091 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16092
4153577a
JP		 16093 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16094 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16095 tp->txq_max = tp->irq_max - 1;
16096 }
16097
b7abee6e 16098 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16099 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16100 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16101
4153577a 16102 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16103 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16104
4153577a
JP		 16105 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16106 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16107 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16108 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16109 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16110
63c3a66f 16111 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16112 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16113 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16114
63c3a66f
JP		 16115 if (!tg3_flag(tp, 5705_PLUS) ||
16116 tg3_flag(tp, 5780_CLASS) ||
16117 tg3_flag(tp, USE_JUMBO_BDFLAG))
16118 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16119
52f4490c
MC		 16120 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16121 &pci_state_reg);
16122
708ebb3a 16123 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16124 u16 lnkctl;
16125
63c3a66f 16126 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16127
0f49bfbd 16128 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16129 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16130 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16131 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16132 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16133 }
4153577a
JP		 16134 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16135 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16136 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16137 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16138 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16139 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16140 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16141 }
4153577a 16142 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16143 /* BCM5785 devices are effectively PCIe devices, and should
16144 * follow PCIe codepaths, but do not have a PCIe capabilities
16145 * section.
93a700a9 16146 */
63c3a66f
JP		 16147 tg3_flag_set(tp, PCI_EXPRESS);
16148 } else if (!tg3_flag(tp, 5705_PLUS) ||
16149 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16150 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16151 if (!tp->pcix_cap) {
2445e461
MC		 16152 dev_err(&tp->pdev->dev,
16153 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16154 return -EIO;
16155 }
16156
16157 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16158 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16159 }
1da177e4 16160
399de50b
MC		 16161 /* If we have an AMD 762 or VIA K8T800 chipset, write
16162 * reordering to the mailbox registers done by the host
16163 * controller can cause major troubles. We read back from
16164 * every mailbox register write to force the writes to be
16165 * posted to the chip in order.
16166 */
4143470c 16167 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16168 !tg3_flag(tp, PCI_EXPRESS))
16169 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16170
69fc4053
MC		 16171 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16172 &tp->pci_cacheline_sz);
16173 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16174 &tp->pci_lat_timer);
4153577a 16175 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16176 tp->pci_lat_timer < 64) {
16177 tp->pci_lat_timer = 64;
69fc4053
MC		 16178 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16179 tp->pci_lat_timer);
1da177e4
LT		 16180 }
16181
16821285
MC		 16182 /* Important! -- It is critical that the PCI-X hw workaround
16183 * situation is decided before the first MMIO register access.
16184 */
4153577a 16185 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16186 /* 5700 BX chips need to have their TX producer index
16187 * mailboxes written twice to workaround a bug.
16188 */
63c3a66f 16189 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16190
52f4490c 16191 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16192 *
16193 * The workaround is to use indirect register accesses
16194 * for all chip writes not to mailbox registers.
16195 */
63c3a66f 16196 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16197 u32 pm_reg;
1da177e4 16198
63c3a66f 16199 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16200
16201 /* The chip can have it's power management PCI config
16202 * space registers clobbered due to this bug.
16203 * So explicitly force the chip into D0 here.
16204 */
9974a356 16205 pci_read_config_dword(tp->pdev,
0319f30e 16206 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16207 &pm_reg);
16208 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16209 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16210 pci_write_config_dword(tp->pdev,
0319f30e 16211 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16212 pm_reg);
16213
16214 /* Also, force SERR#/PERR# in PCI command. */
16215 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16216 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16217 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16218 }
16219 }
16220
1da177e4 16221 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16222 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16223 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16224 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16225
16226 /* Chip-specific fixup from Broadcom driver */
4153577a 16227 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16228 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16229 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16230 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16231 }
16232
1ee582d8 16233 /* Default fast path register access methods */
20094930 16234 tp->read32 = tg3_read32;
1ee582d8 16235 tp->write32 = tg3_write32;
09ee929c 16236 tp->read32_mbox = tg3_read32;
20094930 16237 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16238 tp->write32_tx_mbox = tg3_write32;
16239 tp->write32_rx_mbox = tg3_write32;
16240
16241 /* Various workaround register access methods */
63c3a66f 16242 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16243 tp->write32 = tg3_write_indirect_reg32;
4153577a 16244 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16245 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16246 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16247 /*
16248 * Back to back register writes can cause problems on these
16249 * chips, the workaround is to read back all reg writes
16250 * except those to mailbox regs.
16251 *
16252 * See tg3_write_indirect_reg32().
16253 */
1ee582d8 16254 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16255 }
16256
63c3a66f 16257 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16258 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16259 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16260 tp->write32_rx_mbox = tg3_write_flush_reg32;
16261 }
20094930 16262
63c3a66f 16263 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16264 tp->read32 = tg3_read_indirect_reg32;
16265 tp->write32 = tg3_write_indirect_reg32;
16266 tp->read32_mbox = tg3_read_indirect_mbox;
16267 tp->write32_mbox = tg3_write_indirect_mbox;
16268 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16269 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16270
16271 iounmap(tp->regs);
22abe310 16272 tp->regs = NULL;
6892914f
MC		 16273
16274 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16275 pci_cmd &= ~PCI_COMMAND_MEMORY;
16276 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16277 }
4153577a 16278 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16279 tp->read32_mbox = tg3_read32_mbox_5906;
16280 tp->write32_mbox = tg3_write32_mbox_5906;
16281 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16282 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16283 }
6892914f 16284
bbadf503 16285 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16286 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16287 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16288 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16289 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16290
16821285
MC		 16291 /* The memory arbiter has to be enabled in order for SRAM accesses
16292 * to succeed. Normally on powerup the tg3 chip firmware will make
16293 * sure it is enabled, but other entities such as system netboot
16294 * code might disable it.
16295 */
16296 val = tr32(MEMARB_MODE);
16297 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16298
9dc5e342 16299 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16300 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16301 tg3_flag(tp, 5780_CLASS)) {
16302 if (tg3_flag(tp, PCIX_MODE)) {
16303 pci_read_config_dword(tp->pdev,
16304 tp->pcix_cap + PCI_X_STATUS,
16305 &val);
16306 tp->pci_fn = val & 0x7;
16307 }
4153577a
JP		 16308 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16309 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16310 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16311 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16312 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16313 val = tr32(TG3_CPMU_STATUS);
16314
4153577a 16315 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16316 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16317 else
9dc5e342
MC		 16318 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16319 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16320 }
16321
7e6c63f0
HM		 16322 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16323 tp->write32_tx_mbox = tg3_write_flush_reg32;
16324 tp->write32_rx_mbox = tg3_write_flush_reg32;
16325 }
16326
7d0c41ef 16327 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16328 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16329 * determined before calling tg3_set_power_state() so that
16330 * we know whether or not to switch out of Vaux power.
16331 * When the flag is set, it means that GPIO1 is used for eeprom
16332 * write protect and also implies that it is a LOM where GPIOs
16333 * are not used to switch power.
6aa20a22 16334 */
7d0c41ef
MC		 16335 tg3_get_eeprom_hw_cfg(tp);
16336
1caf13eb 16337 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16338 tg3_flag_clear(tp, TSO_CAPABLE);
16339 tg3_flag_clear(tp, TSO_BUG);
16340 tp->fw_needed = NULL;
16341 }
16342
63c3a66f 16343 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16344 /* Allow reads and writes to the
16345 * APE register and memory space.
16346 */
16347 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16348 PCISTATE_ALLOW_APE_SHMEM_WR |
16349 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16350 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16351 pci_state_reg);
c9cab24e
MC		 16352
16353 tg3_ape_lock_init(tp);
0d3031d9
MC		 16354 }
16355
16821285
MC		 16356 /* Set up tp->grc_local_ctrl before calling
16357 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16358 * will bring 5700's external PHY out of reset.
314fba34
MC		 16359 * It is also used as eeprom write protect on LOMs.
16360 */
16361 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16362 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16363 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16364 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16365 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16366 /* Unused GPIO3 must be driven as output on 5752 because there
16367 * are no pull-up resistors on unused GPIO pins.
16368 */
4153577a 16369 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16370 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16371
4153577a
JP		 16372 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16373 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16374 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16375 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16376
8d519ab2
MC		 16377 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16378 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16379 /* Turn off the debug UART. */
16380 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16381 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16382 /* Keep VMain power. */
16383 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16384 GRC_LCLCTRL_GPIO_OUTPUT0;
16385 }
16386
4153577a 16387 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16388 tp->grc_local_ctrl |=
16389 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16390
16821285
MC		 16391 /* Switch out of Vaux if it is a NIC */
16392 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16393
1da177e4
LT		 16394 /* Derive initial jumbo mode from MTU assigned in
16395 * ether_setup() via the alloc_etherdev() call
16396 */
63c3a66f
JP		 16397 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16398 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16399
16400 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16401 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16402 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16403 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16404 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16405 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16406 } else {
63c3a66f 16407 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16408 }
16409
4153577a 16410 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16411 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16412
1da177e4 16413 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16414 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16415 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16416 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16417 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16418 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16419 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16420 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16421
4153577a
JP		 16422 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16423 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16424 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16425 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16426 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16427
63c3a66f 16428 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16429 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16430 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16431 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16432 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16433 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16434 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16435 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16436 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16437 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16438 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16439 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16440 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16441 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16442 } else
f07e9af3 16443 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16444 }
1da177e4 16445
4153577a
JP		 16446 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16447 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16448 tp->phy_otp = tg3_read_otp_phycfg(tp);
16449 if (tp->phy_otp == 0)
16450 tp->phy_otp = TG3_OTP_DEFAULT;
16451 }
16452
63c3a66f 16453 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16454 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16455 else
16456 tp->mi_mode = MAC_MI_MODE_BASE;
16457
1da177e4 16458 tp->coalesce_mode = 0;
4153577a
JP		 16459 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16460 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16461 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16462
4d958473 16463 /* Set these bits to enable statistics workaround. */
4153577a
JP		 16464 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16465 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16466 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16467 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16468 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16469 }
16470
4153577a
JP		 16471 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16472 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16473 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16474
158d7abd
MC		 16475 err = tg3_mdio_init(tp);
16476 if (err)
16477 return err;
1da177e4
LT		 16478
16479 /* Initialize data/descriptor byte/word swapping. */
16480 val = tr32(GRC_MODE);
4153577a
JP		 16481 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16482 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16483 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16484 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16485 GRC_MODE_B2HRX_ENABLE |
16486 GRC_MODE_HTX2B_ENABLE |
16487 GRC_MODE_HOST_STACKUP);
16488 else
16489 val &= GRC_MODE_HOST_STACKUP;
16490
1da177e4
LT		 16491 tw32(GRC_MODE, val | tp->grc_mode);
16492
16493 tg3_switch_clocks(tp);
16494
16495 /* Clear this out for sanity. */
16496 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16497
16498 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16499 &pci_state_reg);
16500 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16501 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16502 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16503 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16504 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16505 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16506 void __iomem *sram_base;
16507
16508 /* Write some dummy words into the SRAM status block
16509 * area, see if it reads back correctly. If the return
16510 * value is bad, force enable the PCIX workaround.
16511 */
16512 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16513
16514 writel(0x00000000, sram_base);
16515 writel(0x00000000, sram_base + 4);
16516 writel(0xffffffff, sram_base + 4);
16517 if (readl(sram_base) != 0x00000000)
63c3a66f 16518 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16519 }
16520 }
16521
16522 udelay(50);
16523 tg3_nvram_init(tp);
16524
c4dab506
NS		 16525 /* If the device has an NVRAM, no need to load patch firmware */
16526 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16527 !tg3_flag(tp, NO_NVRAM))
16528 tp->fw_needed = NULL;
16529
1da177e4
LT		 16530 grc_misc_cfg = tr32(GRC_MISC_CFG);
16531 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16532
4153577a 16533 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16534 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16535 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16536 tg3_flag_set(tp, IS_5788);
1da177e4 16537
63c3a66f 16538 if (!tg3_flag(tp, IS_5788) &&
4153577a 16539 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16540 tg3_flag_set(tp, TAGGED_STATUS);
16541 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16542 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16543 HOSTCC_MODE_CLRTICK_TXBD);
16544
16545 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16546 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16547 tp->misc_host_ctrl);
16548 }
16549
3bda1258 16550 /* Preserve the APE MAC_MODE bits */
63c3a66f 16551 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16552 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16553 else
6e01b20b 16554 tp->mac_mode = 0;
3bda1258 16555
3d567e0e 16556 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16557 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16558
16559 err = tg3_phy_probe(tp);
16560 if (err) {
2445e461 16561 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16562 /* ... but do not return immediately ... */
b02fd9e3 16563 tg3_mdio_fini(tp);
1da177e4
LT		 16564 }
16565
184b8904 16566 tg3_read_vpd(tp);
c4e6575c 16567 tg3_read_fw_ver(tp);
1da177e4 16568
f07e9af3
MC		 16569 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16570 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16571 } else {
4153577a 16572 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16573 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16574 else
f07e9af3 16575 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16576 }
16577
16578 /* 5700 {AX,BX} chips have a broken status block link
16579 * change bit implementation, so we must use the
16580 * status register in those cases.
16581 */
4153577a 16582 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16583 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16584 else
63c3a66f 16585 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16586
16587 /* The led_ctrl is set during tg3_phy_probe, here we might
16588 * have to force the link status polling mechanism based
16589 * upon subsystem IDs.
16590 */
16591 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16592 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16593 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16594 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16595 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16596 }
16597
16598 /* For all SERDES we poll the MAC status register. */
f07e9af3 16599 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16600 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16601 else
63c3a66f 16602 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16603
9205fd9c 16604 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16605 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16606 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16607 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16608 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16609#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16610 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16611#endif
16612 }
1da177e4 16613
2c49a44d
MC		 16614 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16615 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16616 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16617
2c49a44d 16618 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16619
16620 /* Increment the rx prod index on the rx std ring by at most
16621 * 8 for these chips to workaround hw errata.
16622 */
4153577a
JP		 16623 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16624 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16625 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16626 tp->rx_std_max_post = 8;
16627
63c3a66f 16628 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16629 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16630 PCIE_PWR_MGMT_L1_THRESH_MSK;
16631
1da177e4
LT		 16632 return err;
16633}
16634
49b6e95f 16635#ifdef CONFIG_SPARC
229b1ad1 16636static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16637{
16638 struct net_device *dev = tp->dev;
16639 struct pci_dev *pdev = tp->pdev;
49b6e95f 16640 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16641 const unsigned char *addr;
49b6e95f
DM		 16642 int len;
16643
16644 addr = of_get_property(dp, "local-mac-address", &len);
16645 if (addr && len == 6) {
16646 memcpy(dev->dev_addr, addr, 6);
49b6e95f 16647 return 0;
1da177e4
LT		 16648 }
16649 return -ENODEV;
16650}
16651
229b1ad1 16652static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16653{
16654 struct net_device *dev = tp->dev;
16655
16656 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
16657 return 0;
16658}
16659#endif
16660
229b1ad1 16661static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16662{
16663 struct net_device *dev = tp->dev;
16664 u32 hi, lo, mac_offset;
008652b3 16665 int addr_ok = 0;
7e6c63f0 16666 int err;
1da177e4 16667
49b6e95f 16668#ifdef CONFIG_SPARC
1da177e4
LT		 16669 if (!tg3_get_macaddr_sparc(tp))
16670 return 0;
16671#endif
16672
7e6c63f0
HM		 16673 if (tg3_flag(tp, IS_SSB_CORE)) {
16674 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16675 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16676 return 0;
16677 }
16678
1da177e4 16679 mac_offset = 0x7c;
4153577a 16680 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16681 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16682 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16683 mac_offset = 0xcc;
16684 if (tg3_nvram_lock(tp))
16685 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16686 else
16687 tg3_nvram_unlock(tp);
63c3a66f 16688 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16689 if (tp->pci_fn & 1)
a1b950d5 16690 mac_offset = 0xcc;
69f11c99 16691 if (tp->pci_fn > 1)
a50d0796 16692 mac_offset += 0x18c;
4153577a 16693 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16694 mac_offset = 0x10;
1da177e4
LT		 16695
16696 /* First try to get it from MAC address mailbox. */
16697 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16698 if ((hi >> 16) == 0x484b) {
16699 dev->dev_addr[0] = (hi >> 8) & 0xff;
16700 dev->dev_addr[1] = (hi >> 0) & 0xff;
16701
16702 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16703 dev->dev_addr[2] = (lo >> 24) & 0xff;
16704 dev->dev_addr[3] = (lo >> 16) & 0xff;
16705 dev->dev_addr[4] = (lo >> 8) & 0xff;
16706 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16707
008652b3
MC		 16708 /* Some old bootcode may report a 0 MAC address in SRAM */
16709 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16710 }
16711 if (!addr_ok) {
16712 /* Next, try NVRAM. */
63c3a66f 16713 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16714 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16715 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16716 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16717 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16718 }
16719 /* Finally just fetch it out of the MAC control regs. */
16720 else {
16721 hi = tr32(MAC_ADDR_0_HIGH);
16722 lo = tr32(MAC_ADDR_0_LOW);
16723
16724 dev->dev_addr[5] = lo & 0xff;
16725 dev->dev_addr[4] = (lo >> 8) & 0xff;
16726 dev->dev_addr[3] = (lo >> 16) & 0xff;
16727 dev->dev_addr[2] = (lo >> 24) & 0xff;
16728 dev->dev_addr[1] = hi & 0xff;
16729 dev->dev_addr[0] = (hi >> 8) & 0xff;
16730 }
1da177e4
LT		 16731 }
16732
16733 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16734#ifdef CONFIG_SPARC
1da177e4
LT		 16735 if (!tg3_get_default_macaddr_sparc(tp))
16736 return 0;
16737#endif
16738 return -EINVAL;
16739 }
16740 return 0;
16741}
16742
59e6b434
DM		 16743#define BOUNDARY_SINGLE_CACHELINE 1
16744#define BOUNDARY_MULTI_CACHELINE 2
16745
229b1ad1 16746static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16747{
16748 int cacheline_size;
16749 u8 byte;
16750 int goal;
16751
16752 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16753 if (byte == 0)
16754 cacheline_size = 1024;
16755 else
16756 cacheline_size = (int) byte * 4;
16757
16758 /* On 5703 and later chips, the boundary bits have no
16759 * effect.
16760 */
4153577a
JP		 16761 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16762 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 16763 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 16764 goto out;
16765
16766#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16767 goal = BOUNDARY_MULTI_CACHELINE;
16768#else
16769#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16770 goal = BOUNDARY_SINGLE_CACHELINE;
16771#else
16772 goal = 0;
16773#endif
16774#endif
16775
63c3a66f 16776 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 16777 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16778 goto out;
16779 }
16780
59e6b434
DM		 16781 if (!goal)
16782 goto out;
16783
16784 /* PCI controllers on most RISC systems tend to disconnect
16785 * when a device tries to burst across a cache-line boundary.
16786 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16787 *
16788 * Unfortunately, for PCI-E there are only limited
16789 * write-side controls for this, and thus for reads
16790 * we will still get the disconnects. We'll also waste
16791 * these PCI cycles for both read and write for chips
16792 * other than 5700 and 5701 which do not implement the
16793 * boundary bits.
16794 */
63c3a66f 16795 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16796 switch (cacheline_size) {
16797 case 16:
16798 case 32:
16799 case 64:
16800 case 128:
16801 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16802 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16803 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16804 } else {
16805 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16806 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16807 }
16808 break;
16809
16810 case 256:
16811 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16812 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16813 break;
16814
16815 default:
16816 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16817 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16818 break;
855e1111 16819 }
63c3a66f 16820 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16821 switch (cacheline_size) {
16822 case 16:
16823 case 32:
16824 case 64:
16825 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16826 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16827 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
16828 break;
16829 }
16830 /* fallthrough */
16831 case 128:
16832 default:
16833 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16834 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
16835 break;
855e1111 16836 }
59e6b434
DM		 16837 } else {
16838 switch (cacheline_size) {
16839 case 16:
16840 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16841 val |= (DMA_RWCTRL_READ_BNDRY_16 |
16842 DMA_RWCTRL_WRITE_BNDRY_16);
16843 break;
16844 }
16845 /* fallthrough */
16846 case 32:
16847 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16848 val |= (DMA_RWCTRL_READ_BNDRY_32 |
16849 DMA_RWCTRL_WRITE_BNDRY_32);
16850 break;
16851 }
16852 /* fallthrough */
16853 case 64:
16854 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16855 val |= (DMA_RWCTRL_READ_BNDRY_64 |
16856 DMA_RWCTRL_WRITE_BNDRY_64);
16857 break;
16858 }
16859 /* fallthrough */
16860 case 128:
16861 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16862 val |= (DMA_RWCTRL_READ_BNDRY_128 |
16863 DMA_RWCTRL_WRITE_BNDRY_128);
16864 break;
16865 }
16866 /* fallthrough */
16867 case 256:
16868 val |= (DMA_RWCTRL_READ_BNDRY_256 |
16869 DMA_RWCTRL_WRITE_BNDRY_256);
16870 break;
16871 case 512:
16872 val |= (DMA_RWCTRL_READ_BNDRY_512 |
16873 DMA_RWCTRL_WRITE_BNDRY_512);
16874 break;
16875 case 1024:
16876 default:
16877 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
16878 DMA_RWCTRL_WRITE_BNDRY_1024);
16879 break;
855e1111 16880 }
59e6b434
DM		 16881 }
16882
16883out:
16884 return val;
16885}
16886
229b1ad1 16887static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 16888 int size, bool to_device)
1da177e4
LT		 16889{
16890 struct tg3_internal_buffer_desc test_desc;
16891 u32 sram_dma_descs;
16892 int i, ret;
16893
16894 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
16895
16896 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
16897 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
16898 tw32(RDMAC_STATUS, 0);
16899 tw32(WDMAC_STATUS, 0);
16900
16901 tw32(BUFMGR_MODE, 0);
16902 tw32(FTQ_RESET, 0);
16903
16904 test_desc.addr_hi = ((u64) buf_dma) >> 32;
16905 test_desc.addr_lo = buf_dma & 0xffffffff;
16906 test_desc.nic_mbuf = 0x00002100;
16907 test_desc.len = size;
16908
16909 /*
16910 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
16911 * the *second* time the tg3 driver was getting loaded after an
16912 * initial scan.
16913 *
16914 * Broadcom tells me:
16915 * ...the DMA engine is connected to the GRC block and a DMA
16916 * reset may affect the GRC block in some unpredictable way...
16917 * The behavior of resets to individual blocks has not been tested.
16918 *
16919 * Broadcom noted the GRC reset will also reset all sub-components.
16920 */
16921 if (to_device) {
16922 test_desc.cqid_sqid = (13 << 8) | 2;
16923
16924 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
16925 udelay(40);
16926 } else {
16927 test_desc.cqid_sqid = (16 << 8) | 7;
16928
16929 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
16930 udelay(40);
16931 }
16932 test_desc.flags = 0x00000005;
16933
16934 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
16935 u32 val;
16936
16937 val = *(((u32 *)&test_desc) + i);
16938 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
16939 sram_dma_descs + (i * sizeof(u32)));
16940 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
16941 }
16942 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
16943
859a5887 16944 if (to_device)
1da177e4 16945 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 16946 else
1da177e4 16947 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 16948
16949 ret = -ENODEV;
16950 for (i = 0; i < 40; i++) {
16951 u32 val;
16952
16953 if (to_device)
16954 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
16955 else
16956 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
16957 if ((val & 0xffff) == sram_dma_descs) {
16958 ret = 0;
16959 break;
16960 }
16961
16962 udelay(100);
16963 }
16964
16965 return ret;
16966}
16967
ded7340d 16968#define TEST_BUFFER_SIZE 0x2000
1da177e4 16969
4143470c 16970static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
895950c2
JP		 16971 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
16972 { },
16973};
16974
229b1ad1 16975static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 16976{
16977 dma_addr_t buf_dma;
59e6b434 16978 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 16979 int ret = 0;
1da177e4 16980
4bae65c8
MC		 16981 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
16982 &buf_dma, GFP_KERNEL);
1da177e4
LT		 16983 if (!buf) {
16984 ret = -ENOMEM;
16985 goto out_nofree;
16986 }
16987
16988 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
16989 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
16990
59e6b434 16991 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 16992
63c3a66f 16993 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 16994 goto out;
16995
63c3a66f 16996 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 16997 /* DMA read watermark not used on PCIE */
16998 tp->dma_rwctrl |= 0x00180000;
63c3a66f 16999 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 17000 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17001 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 17002 tp->dma_rwctrl |= 0x003f0000;
17003 else
17004 tp->dma_rwctrl |= 0x003f000f;
17005 } else {
4153577a
JP		 17006 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17007 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 17008 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 17009 u32 read_water = 0x7;
1da177e4 17010
4a29cc2e
MC		 17011 /* If the 5704 is behind the EPB bridge, we can
17012 * do the less restrictive ONE_DMA workaround for
17013 * better performance.
17014 */
63c3a66f 17015 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17016 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17017 tp->dma_rwctrl |= 0x8000;
17018 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17019 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17020
4153577a 17021 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17022 read_water = 4;
59e6b434 17023 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17024 tp->dma_rwctrl |=
17025 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17026 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17027 (1 << 23);
4153577a 17028 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17029 /* 5780 always in PCIX mode */
17030 tp->dma_rwctrl |= 0x00144000;
4153577a 17031 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17032 /* 5714 always in PCIX mode */
17033 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17034 } else {
17035 tp->dma_rwctrl |= 0x001b000f;
17036 }
17037 }
7e6c63f0
HM		 17038 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17039 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17040
4153577a
JP		 17041 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17042 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17043 tp->dma_rwctrl &= 0xfffffff0;
17044
4153577a
JP		 17045 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17046 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17047 /* Remove this if it causes problems for some boards. */
17048 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17049
17050 /* On 5700/5701 chips, we need to set this bit.
17051 * Otherwise the chip will issue cacheline transactions
17052 * to streamable DMA memory with not all the byte
17053 * enables turned on. This is an error on several
17054 * RISC PCI controllers, in particular sparc64.
17055 *
17056 * On 5703/5704 chips, this bit has been reassigned
17057 * a different meaning. In particular, it is used
17058 * on those chips to enable a PCI-X workaround.
17059 */
17060 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17061 }
17062
17063 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17064
17065#if 0
17066 /* Unneeded, already done by tg3_get_invariants. */
17067 tg3_switch_clocks(tp);
17068#endif
17069
4153577a
JP		 17070 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17071 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17072 goto out;
17073
59e6b434
DM		 17074 /* It is best to perform DMA test with maximum write burst size
17075 * to expose the 5700/5701 write DMA bug.
17076 */
17077 saved_dma_rwctrl = tp->dma_rwctrl;
17078 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17079 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17080
1da177e4
LT		 17081 while (1) {
17082 u32 *p = buf, i;
17083
17084 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17085 p[i] = i;
17086
17087 /* Send the buffer to the chip. */
953c96e0 17088 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17089 if (ret) {
2445e461
MC		 17090 dev_err(&tp->pdev->dev,
17091 "%s: Buffer write failed. err = %d\n",
17092 __func__, ret);
1da177e4
LT		 17093 break;
17094 }
17095
17096#if 0
17097 /* validate data reached card RAM correctly. */
17098 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17099 u32 val;
17100 tg3_read_mem(tp, 0x2100 + (i*4), &val);
17101 if (le32_to_cpu(val) != p[i]) {
2445e461
MC		 17102 dev_err(&tp->pdev->dev,
17103 "%s: Buffer corrupted on device! "
17104 "(%d != %d)\n", __func__, val, i);
1da177e4
LT		 17105 /* ret = -ENODEV here? */
17106 }
17107 p[i] = 0;
17108 }
17109#endif
17110 /* Now read it back. */
953c96e0 17111 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17112 if (ret) {
5129c3a3
MC		 17113 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17114 "err = %d\n", __func__, ret);
1da177e4
LT		 17115 break;
17116 }
17117
17118 /* Verify it. */
17119 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17120 if (p[i] == i)
17121 continue;
17122
59e6b434
DM		 17123 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17124 DMA_RWCTRL_WRITE_BNDRY_16) {
17125 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17126 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17127 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17128 break;
17129 } else {
2445e461
MC		 17130 dev_err(&tp->pdev->dev,
17131 "%s: Buffer corrupted on read back! "
17132 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17133 ret = -ENODEV;
17134 goto out;
17135 }
17136 }
17137
17138 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17139 /* Success. */
17140 ret = 0;
17141 break;
17142 }
17143 }
59e6b434
DM		 17144 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17145 DMA_RWCTRL_WRITE_BNDRY_16) {
17146 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17147 * now look for chipsets that are known to expose the
17148 * DMA bug without failing the test.
59e6b434 17149 */
4143470c 17150 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17151 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17152 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17153 } else {
6d1cfbab
MC		 17154 /* Safe to use the calculated DMA boundary. */
17155 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17156 }
6d1cfbab 17157
59e6b434
DM		 17158 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17159 }
1da177e4
LT		 17160
17161out:
4bae65c8 17162 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17163out_nofree:
17164 return ret;
17165}
17166
229b1ad1 17167static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17168{
63c3a66f 17169 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17170 tp->bufmgr_config.mbuf_read_dma_low_water =
17171 DEFAULT_MB_RDMA_LOW_WATER_5705;
17172 tp->bufmgr_config.mbuf_mac_rx_low_water =
17173 DEFAULT_MB_MACRX_LOW_WATER_57765;
17174 tp->bufmgr_config.mbuf_high_water =
17175 DEFAULT_MB_HIGH_WATER_57765;
17176
17177 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17178 DEFAULT_MB_RDMA_LOW_WATER_5705;
17179 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17180 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17181 tp->bufmgr_config.mbuf_high_water_jumbo =
17182 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17183 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17184 tp->bufmgr_config.mbuf_read_dma_low_water =
17185 DEFAULT_MB_RDMA_LOW_WATER_5705;
17186 tp->bufmgr_config.mbuf_mac_rx_low_water =
17187 DEFAULT_MB_MACRX_LOW_WATER_5705;
17188 tp->bufmgr_config.mbuf_high_water =
17189 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17190 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17191 tp->bufmgr_config.mbuf_mac_rx_low_water =
17192 DEFAULT_MB_MACRX_LOW_WATER_5906;
17193 tp->bufmgr_config.mbuf_high_water =
17194 DEFAULT_MB_HIGH_WATER_5906;
17195 }
fdfec172
MC		 17196
17197 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17198 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17199 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17200 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17201 tp->bufmgr_config.mbuf_high_water_jumbo =
17202 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17203 } else {
17204 tp->bufmgr_config.mbuf_read_dma_low_water =
17205 DEFAULT_MB_RDMA_LOW_WATER;
17206 tp->bufmgr_config.mbuf_mac_rx_low_water =
17207 DEFAULT_MB_MACRX_LOW_WATER;
17208 tp->bufmgr_config.mbuf_high_water =
17209 DEFAULT_MB_HIGH_WATER;
17210
17211 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17212 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17213 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17214 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17215 tp->bufmgr_config.mbuf_high_water_jumbo =
17216 DEFAULT_MB_HIGH_WATER_JUMBO;
17217 }
1da177e4
LT		 17218
17219 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17220 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17221}
17222
229b1ad1 17223static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17224{
79eb6904
MC		 17225 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17226 case TG3_PHY_ID_BCM5400: return "5400";
17227 case TG3_PHY_ID_BCM5401: return "5401";
17228 case TG3_PHY_ID_BCM5411: return "5411";
17229 case TG3_PHY_ID_BCM5701: return "5701";
17230 case TG3_PHY_ID_BCM5703: return "5703";
17231 case TG3_PHY_ID_BCM5704: return "5704";
17232 case TG3_PHY_ID_BCM5705: return "5705";
17233 case TG3_PHY_ID_BCM5750: return "5750";
17234 case TG3_PHY_ID_BCM5752: return "5752";
17235 case TG3_PHY_ID_BCM5714: return "5714";
17236 case TG3_PHY_ID_BCM5780: return "5780";
17237 case TG3_PHY_ID_BCM5755: return "5755";
17238 case TG3_PHY_ID_BCM5787: return "5787";
17239 case TG3_PHY_ID_BCM5784: return "5784";
17240 case TG3_PHY_ID_BCM5756: return "5722/5756";
17241 case TG3_PHY_ID_BCM5906: return "5906";
17242 case TG3_PHY_ID_BCM5761: return "5761";
17243 case TG3_PHY_ID_BCM5718C: return "5718C";
17244 case TG3_PHY_ID_BCM5718S: return "5718S";
17245 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17246 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17247 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17248 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17249 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17250 case 0: return "serdes";
17251 default: return "unknown";
855e1111 17252 }
1da177e4
LT		 17253}
17254
229b1ad1 17255static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17256{
63c3a66f 17257 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17258 strcpy(str, "PCI Express");
17259 return str;
63c3a66f 17260 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17261 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17262
17263 strcpy(str, "PCIX:");
17264
17265 if ((clock_ctrl == 7) ||
17266 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17267 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17268 strcat(str, "133MHz");
17269 else if (clock_ctrl == 0)
17270 strcat(str, "33MHz");
17271 else if (clock_ctrl == 2)
17272 strcat(str, "50MHz");
17273 else if (clock_ctrl == 4)
17274 strcat(str, "66MHz");
17275 else if (clock_ctrl == 6)
17276 strcat(str, "100MHz");
f9804ddb
MC		 17277 } else {
17278 strcpy(str, "PCI:");
63c3a66f 17279 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17280 strcat(str, "66MHz");
17281 else
17282 strcat(str, "33MHz");
17283 }
63c3a66f 17284 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17285 strcat(str, ":32-bit");
17286 else
17287 strcat(str, ":64-bit");
17288 return str;
17289}
17290
229b1ad1 17291static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17292{
17293 struct ethtool_coalesce *ec = &tp->coal;
17294
17295 memset(ec, 0, sizeof(*ec));
17296 ec->cmd = ETHTOOL_GCOALESCE;
17297 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17298 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17299 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17300 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17301 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17302 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17303 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17304 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17305 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17306
17307 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17308 HOSTCC_MODE_CLRTICK_TXBD)) {
17309 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17310 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17311 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17312 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17313 }
d244c892 17314
63c3a66f 17315 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17316 ec->rx_coalesce_usecs_irq = 0;
17317 ec->tx_coalesce_usecs_irq = 0;
17318 ec->stats_block_coalesce_usecs = 0;
17319 }
15f9850d
DM		 17320}
17321
229b1ad1 17322static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17323 const struct pci_device_id *ent)
17324{
1da177e4
LT		 17325 struct net_device *dev;
17326 struct tg3 *tp;
5865fc1b 17327 int i, err;
646c9edd 17328 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17329 char str[40];
72f2afb8 17330 u64 dma_mask, persist_dma_mask;
c8f44aff 17331 netdev_features_t features = 0;
1da177e4 17332
05dbe005 17333 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17334
17335 err = pci_enable_device(pdev);
17336 if (err) {
2445e461 17337 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17338 return err;
17339 }
17340
1da177e4
LT		 17341 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17342 if (err) {
2445e461 17343 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17344 goto err_out_disable_pdev;
17345 }
17346
17347 pci_set_master(pdev);
17348
fe5f5787 17349 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17350 if (!dev) {
1da177e4 17351 err = -ENOMEM;
5865fc1b 17352 goto err_out_free_res;
1da177e4
LT		 17353 }
17354
1da177e4
LT		 17355 SET_NETDEV_DEV(dev, &pdev->dev);
17356
1da177e4
LT		 17357 tp = netdev_priv(dev);
17358 tp->pdev = pdev;
17359 tp->dev = dev;
1da177e4
LT		 17360 tp->rx_mode = TG3_DEF_RX_MODE;
17361 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17362 tp->irq_sync = 1;
8ef21428 17363
1da177e4
LT		 17364 if (tg3_debug > 0)
17365 tp->msg_enable = tg3_debug;
17366 else
17367 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17368
7e6c63f0
HM		 17369 if (pdev_is_ssb_gige_core(pdev)) {
17370 tg3_flag_set(tp, IS_SSB_CORE);
17371 if (ssb_gige_must_flush_posted_writes(pdev))
17372 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17373 if (ssb_gige_one_dma_at_once(pdev))
17374 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17375 if (ssb_gige_have_roboswitch(pdev))
17376 tg3_flag_set(tp, ROBOSWITCH);
17377 if (ssb_gige_is_rgmii(pdev))
17378 tg3_flag_set(tp, RGMII_MODE);
17379 }
17380
1da177e4
LT		 17381 /* The word/byte swap controls here control register access byte
17382 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17383 * setting below.
17384 */
17385 tp->misc_host_ctrl =
17386 MISC_HOST_CTRL_MASK_PCI_INT |
17387 MISC_HOST_CTRL_WORD_SWAP |
17388 MISC_HOST_CTRL_INDIR_ACCESS |
17389 MISC_HOST_CTRL_PCISTATE_RW;
17390
17391 /* The NONFRM (non-frame) byte/word swap controls take effect
17392 * on descriptor entries, anything which isn't packet data.
17393 *
17394 * The StrongARM chips on the board (one for tx, one for rx)
17395 * are running in big-endian mode.
17396 */
17397 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17398 GRC_MODE_WSWAP_NONFRM_DATA);
17399#ifdef __BIG_ENDIAN
17400 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17401#endif
17402 spin_lock_init(&tp->lock);
1da177e4 17403 spin_lock_init(&tp->indirect_lock);
c4028958 17404 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17405
d5fe488a 17406 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17407 if (!tp->regs) {
ab96b241 17408 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17409 err = -ENOMEM;
17410 goto err_out_free_dev;
17411 }
17412
c9cab24e
MC		 17413 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17414 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17415 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17416 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17417 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17418 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17419 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17420 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 17421 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 17422 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17423 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 17424 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17425 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 17426 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17427 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
c9cab24e
MC		 17428 tg3_flag_set(tp, ENABLE_APE);
17429 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17430 if (!tp->aperegs) {
17431 dev_err(&pdev->dev,
17432 "Cannot map APE registers, aborting\n");
17433 err = -ENOMEM;
17434 goto err_out_iounmap;
17435 }
17436 }
17437
1da177e4
LT		 17438 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17439 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17440
1da177e4 17441 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17442 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17443 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17444 dev->irq = pdev->irq;
1da177e4 17445
3d567e0e 17446 err = tg3_get_invariants(tp, ent);
1da177e4 17447 if (err) {
ab96b241
MC		 17448 dev_err(&pdev->dev,
17449 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17450 goto err_out_apeunmap;
1da177e4
LT		 17451 }
17452
4a29cc2e
MC		 17453 /* The EPB bridge inside 5714, 5715, and 5780 and any
17454 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17455 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17456 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17457 * do DMA address check in tg3_start_xmit().
17458 */
63c3a66f 17459 if (tg3_flag(tp, IS_5788))
284901a9 17460 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17461 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17462 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17463#ifdef CONFIG_HIGHMEM
6a35528a 17464 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17465#endif
4a29cc2e 17466 } else
6a35528a 17467 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17468
17469 /* Configure DMA attributes. */
284901a9 17470 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17471 err = pci_set_dma_mask(pdev, dma_mask);
17472 if (!err) {
0da0606f 17473 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17474 err = pci_set_consistent_dma_mask(pdev,
17475 persist_dma_mask);
17476 if (err < 0) {
ab96b241
MC		 17477 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17478 "DMA for consistent allocations\n");
c9cab24e 17479 goto err_out_apeunmap;
72f2afb8
MC		 17480 }
17481 }
17482 }
284901a9
YH		 17483 if (err || dma_mask == DMA_BIT_MASK(32)) {
17484 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17485 if (err) {
ab96b241
MC		 17486 dev_err(&pdev->dev,
17487 "No usable DMA configuration, aborting\n");
c9cab24e 17488 goto err_out_apeunmap;
72f2afb8
MC		 17489 }
17490 }
17491
fdfec172 17492 tg3_init_bufmgr_config(tp);
1da177e4 17493
f646968f 17494 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
0da0606f
MC		 17495
17496 /* 5700 B0 chips do not support checksumming correctly due
17497 * to hardware bugs.
17498 */
4153577a 17499 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17500 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17501
17502 if (tg3_flag(tp, 5755_PLUS))
17503 features |= NETIF_F_IPV6_CSUM;
17504 }
17505
4e3a7aaa
MC		 17506 /* TSO is on by default on chips that support hardware TSO.
17507 * Firmware TSO on older chips gives lower performance, so it
17508 * is off by default, but can be enabled using ethtool.
17509 */
63c3a66f
JP		 17510 if ((tg3_flag(tp, HW_TSO_1) ||
17511 tg3_flag(tp, HW_TSO_2) ||
17512 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17513 (features & NETIF_F_IP_CSUM))
17514 features |= NETIF_F_TSO;
63c3a66f 17515 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17516 if (features & NETIF_F_IPV6_CSUM)
17517 features |= NETIF_F_TSO6;
63c3a66f 17518 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17519 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17520 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17521 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17522 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17523 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17524 features |= NETIF_F_TSO_ECN;
b0026624 17525 }
1da177e4 17526
d542fe27
MC		 17527 dev->features |= features;
17528 dev->vlan_features |= features;
17529
06c03c02
MB		 17530 /*
17531 * Add loopback capability only for a subset of devices that support
17532 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17533 * loopback for the remaining devices.
17534 */
4153577a 17535 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17536 !tg3_flag(tp, CPMU_PRESENT))
17537 /* Add the loopback capability */
0da0606f
MC		 17538 features |= NETIF_F_LOOPBACK;
17539
0da0606f 17540 dev->hw_features |= features;
06c03c02 17541
4153577a 17542 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17543 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17544 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17545 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17546 tp->rx_pending = 63;
17547 }
17548
1da177e4
LT		 17549 err = tg3_get_device_address(tp);
17550 if (err) {
ab96b241
MC		 17551 dev_err(&pdev->dev,
17552 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17553 goto err_out_apeunmap;
c88864df
MC		 17554 }
17555
1da177e4
LT		 17556 /*
17557 * Reset chip in case UNDI or EFI driver did not shutdown
17558 * DMA self test will enable WDMAC and we'll see (spurious)
17559 * pending DMA on the PCI bus at that point.
17560 */
17561 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17562 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17563 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17564 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17565 }
17566
17567 err = tg3_test_dma(tp);
17568 if (err) {
ab96b241 17569 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17570 goto err_out_apeunmap;
1da177e4
LT		 17571 }
17572
78f90dcf
MC		 17573 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17574 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17575 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17576 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17577 struct tg3_napi *tnapi = &tp->napi[i];
17578
17579 tnapi->tp = tp;
17580 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17581
17582 tnapi->int_mbox = intmbx;
93a700a9 17583 if (i <= 4)
78f90dcf
MC		 17584 intmbx += 0x8;
17585 else
17586 intmbx += 0x4;
17587
17588 tnapi->consmbox = rcvmbx;
17589 tnapi->prodmbox = sndmbx;
17590
66cfd1bd 17591 if (i)
78f90dcf 17592 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17593 else
78f90dcf 17594 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17595
63c3a66f 17596 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17597 break;
17598
17599 /*
17600 * If we support MSIX, we'll be using RSS. If we're using
17601 * RSS, the first vector only handles link interrupts and the
17602 * remaining vectors handle rx and tx interrupts. Reuse the
17603 * mailbox values for the next iteration. The values we setup
17604 * above are still useful for the single vectored mode.
17605 */
17606 if (!i)
17607 continue;
17608
17609 rcvmbx += 0x8;
17610
17611 if (sndmbx & 0x4)
17612 sndmbx -= 0x4;
17613 else
17614 sndmbx += 0xc;
17615 }
17616
15f9850d
DM		 17617 tg3_init_coal(tp);
17618
c49a1561
MC		 17619 pci_set_drvdata(pdev, dev);
17620
4153577a
JP		 17621 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17622 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17623 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17624 tg3_flag_set(tp, PTP_CAPABLE);
17625
21f7638e
MC		 17626 tg3_timer_init(tp);
17627
402e1398
MC		 17628 tg3_carrier_off(tp);
17629
1da177e4
LT		 17630 err = register_netdev(dev);
17631 if (err) {
ab96b241 17632 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17633 goto err_out_apeunmap;
1da177e4
LT		 17634 }
17635
05dbe005
JP		 17636 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17637 tp->board_part_number,
4153577a 17638 tg3_chip_rev_id(tp),
05dbe005
JP		 17639 tg3_bus_string(tp, str),
17640 dev->dev_addr);
1da177e4 17641
f07e9af3 17642 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7
MC		 17643 struct phy_device *phydev;
17644 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
5129c3a3
MC		 17645 netdev_info(dev,
17646 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17647 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17648 } else {
17649 char *ethtype;
17650
17651 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17652 ethtype = "10/100Base-TX";
17653 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17654 ethtype = "1000Base-SX";
17655 else
17656 ethtype = "10/100/1000Base-T";
17657
5129c3a3 17658 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17659 "(WireSpeed[%d], EEE[%d])\n",
17660 tg3_phy_string(tp), ethtype,
17661 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17662 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17663 }
05dbe005
JP		 17664
17665 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17666 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17667 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17668 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17669 tg3_flag(tp, ENABLE_ASF) != 0,
17670 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17671 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17672 tp->dma_rwctrl,
17673 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17674 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17675
b45aa2f6
MC		 17676 pci_save_state(pdev);
17677
1da177e4
LT		 17678 return 0;
17679
0d3031d9
MC		 17680err_out_apeunmap:
17681 if (tp->aperegs) {
17682 iounmap(tp->aperegs);
17683 tp->aperegs = NULL;
17684 }
17685
1da177e4 17686err_out_iounmap:
6892914f
MC		 17687 if (tp->regs) {
17688 iounmap(tp->regs);
22abe310 17689 tp->regs = NULL;
6892914f 17690 }
1da177e4
LT		 17691
17692err_out_free_dev:
17693 free_netdev(dev);
17694
17695err_out_free_res:
17696 pci_release_regions(pdev);
17697
17698err_out_disable_pdev:
c80dc13d
GS		 17699 if (pci_is_enabled(pdev))
17700 pci_disable_device(pdev);
1da177e4
LT		 17701 pci_set_drvdata(pdev, NULL);
17702 return err;
17703}
17704
229b1ad1 17705static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17706{
17707 struct net_device *dev = pci_get_drvdata(pdev);
17708
17709 if (dev) {
17710 struct tg3 *tp = netdev_priv(dev);
17711
e3c5530b 17712 release_firmware(tp->fw);
077f849d 17713
db219973 17714 tg3_reset_task_cancel(tp);
158d7abd 17715
e730c823 17716 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17717 tg3_phy_fini(tp);
158d7abd 17718 tg3_mdio_fini(tp);
b02fd9e3 17719 }
158d7abd 17720
1da177e4 17721 unregister_netdev(dev);
0d3031d9
MC		 17722 if (tp->aperegs) {
17723 iounmap(tp->aperegs);
17724 tp->aperegs = NULL;
17725 }
6892914f
MC		 17726 if (tp->regs) {
17727 iounmap(tp->regs);
22abe310 17728 tp->regs = NULL;
6892914f 17729 }
1da177e4
LT		 17730 free_netdev(dev);
17731 pci_release_regions(pdev);
17732 pci_disable_device(pdev);
17733 pci_set_drvdata(pdev, NULL);
17734 }
17735}
17736
aa6027ca 17737#ifdef CONFIG_PM_SLEEP
c866b7ea 17738static int tg3_suspend(struct device *device)
1da177e4 17739{
c866b7ea 17740 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17741 struct net_device *dev = pci_get_drvdata(pdev);
17742 struct tg3 *tp = netdev_priv(dev);
17743 int err;
17744
17745 if (!netif_running(dev))
17746 return 0;
17747
db219973 17748 tg3_reset_task_cancel(tp);
b02fd9e3 17749 tg3_phy_stop(tp);
1da177e4
LT		 17750 tg3_netif_stop(tp);
17751
21f7638e 17752 tg3_timer_stop(tp);
1da177e4 17753
f47c11ee 17754 tg3_full_lock(tp, 1);
1da177e4 17755 tg3_disable_ints(tp);
f47c11ee 17756 tg3_full_unlock(tp);
1da177e4
LT		 17757
17758 netif_device_detach(dev);
17759
f47c11ee 17760 tg3_full_lock(tp, 0);
944d980e 17761 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17762 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17763 tg3_full_unlock(tp);
1da177e4 17764
c866b7ea 17765 err = tg3_power_down_prepare(tp);
1da177e4 17766 if (err) {
b02fd9e3
MC		 17767 int err2;
17768
f47c11ee 17769 tg3_full_lock(tp, 0);
1da177e4 17770
63c3a66f 17771 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17772 err2 = tg3_restart_hw(tp, true);
b02fd9e3 17773 if (err2)
b9ec6c1b 17774 goto out;
1da177e4 17775
21f7638e 17776 tg3_timer_start(tp);
1da177e4
LT		 17777
17778 netif_device_attach(dev);
17779 tg3_netif_start(tp);
17780
b9ec6c1b 17781out:
f47c11ee 17782 tg3_full_unlock(tp);
b02fd9e3
MC		 17783
17784 if (!err2)
17785 tg3_phy_start(tp);
1da177e4
LT		 17786 }
17787
17788 return err;
17789}
17790
c866b7ea 17791static int tg3_resume(struct device *device)
1da177e4 17792{
c866b7ea 17793 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17794 struct net_device *dev = pci_get_drvdata(pdev);
17795 struct tg3 *tp = netdev_priv(dev);
17796 int err;
17797
17798 if (!netif_running(dev))
17799 return 0;
17800
1da177e4
LT		 17801 netif_device_attach(dev);
17802
f47c11ee 17803 tg3_full_lock(tp, 0);
1da177e4 17804
2e460fc0
NS		 17805 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17806
63c3a66f 17807 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 17808 err = tg3_restart_hw(tp,
17809 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 17810 if (err)
17811 goto out;
1da177e4 17812
21f7638e 17813 tg3_timer_start(tp);
1da177e4 17814
1da177e4
LT		 17815 tg3_netif_start(tp);
17816
b9ec6c1b 17817out:
f47c11ee 17818 tg3_full_unlock(tp);
1da177e4 17819
b02fd9e3
MC		 17820 if (!err)
17821 tg3_phy_start(tp);
17822
b9ec6c1b 17823 return err;
1da177e4 17824}
42df36a6 17825#endif /* CONFIG_PM_SLEEP */
1da177e4 17826
c866b7ea
RW		 17827static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17828
4c305fa2
NS		 17829static void tg3_shutdown(struct pci_dev *pdev)
17830{
17831 struct net_device *dev = pci_get_drvdata(pdev);
17832 struct tg3 *tp = netdev_priv(dev);
17833
17834 rtnl_lock();
17835 netif_device_detach(dev);
17836
17837 if (netif_running(dev))
17838 dev_close(dev);
17839
17840 if (system_state == SYSTEM_POWER_OFF)
17841 tg3_power_down(tp);
17842
17843 rtnl_unlock();
17844}
17845
b45aa2f6
MC		 17846/**
17847 * tg3_io_error_detected - called when PCI error is detected
17848 * @pdev: Pointer to PCI device
17849 * @state: The current pci connection state
17850 *
17851 * This function is called after a PCI bus error affecting
17852 * this device has been detected.
17853 */
17854static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
17855 pci_channel_state_t state)
17856{
17857 struct net_device *netdev = pci_get_drvdata(pdev);
17858 struct tg3 *tp = netdev_priv(netdev);
17859 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
17860
17861 netdev_info(netdev, "PCI I/O error detected\n");
17862
17863 rtnl_lock();
17864
d8af4dfd
GS		 17865 /* We probably don't have netdev yet */
17866 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 17867 goto done;
17868
17869 tg3_phy_stop(tp);
17870
17871 tg3_netif_stop(tp);
17872
21f7638e 17873 tg3_timer_stop(tp);
b45aa2f6
MC		 17874
17875 /* Want to make sure that the reset task doesn't run */
db219973 17876 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 17877
17878 netif_device_detach(netdev);
17879
17880 /* Clean up software state, even if MMIO is blocked */
17881 tg3_full_lock(tp, 0);
17882 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
17883 tg3_full_unlock(tp);
17884
17885done:
72bb72b0 17886 if (state == pci_channel_io_perm_failure) {
68293099
DB		 17887 if (netdev) {
17888 tg3_napi_enable(tp);
17889 dev_close(netdev);
17890 }
b45aa2f6 17891 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 17892 } else {
b45aa2f6 17893 pci_disable_device(pdev);
72bb72b0 17894 }
b45aa2f6
MC		 17895
17896 rtnl_unlock();
17897
17898 return err;
17899}
17900
17901/**
17902 * tg3_io_slot_reset - called after the pci bus has been reset.
17903 * @pdev: Pointer to PCI device
17904 *
17905 * Restart the card from scratch, as if from a cold-boot.
17906 * At this point, the card has exprienced a hard reset,
17907 * followed by fixups by BIOS, and has its config space
17908 * set up identically to what it was at cold boot.
17909 */
17910static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
17911{
17912 struct net_device *netdev = pci_get_drvdata(pdev);
17913 struct tg3 *tp = netdev_priv(netdev);
17914 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
17915 int err;
17916
17917 rtnl_lock();
17918
17919 if (pci_enable_device(pdev)) {
68293099
DB		 17920 dev_err(&pdev->dev,
17921 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 17922 goto done;
17923 }
17924
17925 pci_set_master(pdev);
17926 pci_restore_state(pdev);
17927 pci_save_state(pdev);
17928
68293099 17929 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 17930 rc = PCI_ERS_RESULT_RECOVERED;
17931 goto done;
17932 }
17933
17934 err = tg3_power_up(tp);
bed9829f 17935 if (err)
b45aa2f6 17936 goto done;
b45aa2f6
MC		 17937
17938 rc = PCI_ERS_RESULT_RECOVERED;
17939
17940done:
68293099 17941 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 17942 tg3_napi_enable(tp);
17943 dev_close(netdev);
17944 }
b45aa2f6
MC		 17945 rtnl_unlock();
17946
17947 return rc;
17948}
17949
17950/**
17951 * tg3_io_resume - called when traffic can start flowing again.
17952 * @pdev: Pointer to PCI device
17953 *
17954 * This callback is called when the error recovery driver tells
17955 * us that its OK to resume normal operation.
17956 */
17957static void tg3_io_resume(struct pci_dev *pdev)
17958{
17959 struct net_device *netdev = pci_get_drvdata(pdev);
17960 struct tg3 *tp = netdev_priv(netdev);
17961 int err;
17962
17963 rtnl_lock();
17964
17965 if (!netif_running(netdev))
17966 goto done;
17967
17968 tg3_full_lock(tp, 0);
2e460fc0 17969 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 17970 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17971 err = tg3_restart_hw(tp, true);
b45aa2f6 17972 if (err) {
35763066 17973 tg3_full_unlock(tp);
b45aa2f6
MC		 17974 netdev_err(netdev, "Cannot restart hardware after reset.\n");
17975 goto done;
17976 }
17977
17978 netif_device_attach(netdev);
17979
21f7638e 17980 tg3_timer_start(tp);
b45aa2f6
MC		 17981
17982 tg3_netif_start(tp);
17983
35763066
NNS		 17984 tg3_full_unlock(tp);
17985
b45aa2f6
MC		 17986 tg3_phy_start(tp);
17987
17988done:
17989 rtnl_unlock();
17990}
17991
3646f0e5 17992static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 17993 .error_detected = tg3_io_error_detected,
17994 .slot_reset = tg3_io_slot_reset,
17995 .resume = tg3_io_resume
17996};
17997
1da177e4
LT		 17998static struct pci_driver tg3_driver = {
17999 .name = DRV_MODULE_NAME,
18000 .id_table = tg3_pci_tbl,
18001 .probe = tg3_init_one,
229b1ad1 18002 .remove = tg3_remove_one,
b45aa2f6 18003 .err_handler = &tg3_err_handler,
42df36a6 18004 .driver.pm = &tg3_pm_ops,
4c305fa2 18005 .shutdown = tg3_shutdown,
1da177e4
LT		 18006};
18007
8dbb0dc2 18008module_pci_driver(tg3_driver);
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