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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
9e056c03 | 7 | * Copyright (C) 2005-2012 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 | 28 | #include <linux/init.h> |
a6b7a407 | 29 | #include <linux/interrupt.h> |
1da177e4 LT |
30 | #include <linux/ioport.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/ethtool.h> | |
3110f5f5 | 36 | #include <linux/mdio.h> |
1da177e4 | 37 | #include <linux/mii.h> |
158d7abd | 38 | #include <linux/phy.h> |
a9daf367 | 39 | #include <linux/brcmphy.h> |
1da177e4 LT |
40 | #include <linux/if_vlan.h> |
41 | #include <linux/ip.h> | |
42 | #include <linux/tcp.h> | |
43 | #include <linux/workqueue.h> | |
61487480 | 44 | #include <linux/prefetch.h> |
f9a5f7d3 | 45 | #include <linux/dma-mapping.h> |
077f849d | 46 | #include <linux/firmware.h> |
aed93e0b MC |
47 | #include <linux/hwmon.h> |
48 | #include <linux/hwmon-sysfs.h> | |
1da177e4 LT |
49 | |
50 | #include <net/checksum.h> | |
c9bdd4b5 | 51 | #include <net/ip.h> |
1da177e4 | 52 | |
27fd9de8 | 53 | #include <linux/io.h> |
1da177e4 | 54 | #include <asm/byteorder.h> |
27fd9de8 | 55 | #include <linux/uaccess.h> |
1da177e4 | 56 | |
be947307 MC |
57 | #include <uapi/linux/net_tstamp.h> |
58 | #include <linux/ptp_clock_kernel.h> | |
59 | ||
49b6e95f | 60 | #ifdef CONFIG_SPARC |
1da177e4 | 61 | #include <asm/idprom.h> |
49b6e95f | 62 | #include <asm/prom.h> |
1da177e4 LT |
63 | #endif |
64 | ||
63532394 MC |
65 | #define BAR_0 0 |
66 | #define BAR_2 2 | |
67 | ||
1da177e4 LT |
68 | #include "tg3.h" |
69 | ||
63c3a66f JP |
70 | /* Functions & macros to verify TG3_FLAGS types */ |
71 | ||
72 | static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) | |
73 | { | |
74 | return test_bit(flag, bits); | |
75 | } | |
76 | ||
77 | static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) | |
78 | { | |
79 | set_bit(flag, bits); | |
80 | } | |
81 | ||
82 | static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) | |
83 | { | |
84 | clear_bit(flag, bits); | |
85 | } | |
86 | ||
87 | #define tg3_flag(tp, flag) \ | |
88 | _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) | |
89 | #define tg3_flag_set(tp, flag) \ | |
90 | _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) | |
91 | #define tg3_flag_clear(tp, flag) \ | |
92 | _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) | |
93 | ||
1da177e4 | 94 | #define DRV_MODULE_NAME "tg3" |
6867c843 | 95 | #define TG3_MAJ_NUM 3 |
0b3ba055 | 96 | #define TG3_MIN_NUM 127 |
6867c843 MC |
97 | #define DRV_MODULE_VERSION \ |
98 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
0b3ba055 | 99 | #define DRV_MODULE_RELDATE "November 14, 2012" |
1da177e4 | 100 | |
fd6d3f0e MC |
101 | #define RESET_KIND_SHUTDOWN 0 |
102 | #define RESET_KIND_INIT 1 | |
103 | #define RESET_KIND_SUSPEND 2 | |
104 | ||
1da177e4 LT |
105 | #define TG3_DEF_RX_MODE 0 |
106 | #define TG3_DEF_TX_MODE 0 | |
107 | #define TG3_DEF_MSG_ENABLE \ | |
108 | (NETIF_MSG_DRV | \ | |
109 | NETIF_MSG_PROBE | \ | |
110 | NETIF_MSG_LINK | \ | |
111 | NETIF_MSG_TIMER | \ | |
112 | NETIF_MSG_IFDOWN | \ | |
113 | NETIF_MSG_IFUP | \ | |
114 | NETIF_MSG_RX_ERR | \ | |
115 | NETIF_MSG_TX_ERR) | |
116 | ||
520b2756 MC |
117 | #define TG3_GRC_LCLCTL_PWRSW_DELAY 100 |
118 | ||
1da177e4 LT |
119 | /* length of time before we decide the hardware is borked, |
120 | * and dev->tx_timeout() should be called to fix the problem | |
121 | */ | |
63c3a66f | 122 | |
1da177e4 LT |
123 | #define TG3_TX_TIMEOUT (5 * HZ) |
124 | ||
125 | /* hardware minimum and maximum for a single frame's data payload */ | |
126 | #define TG3_MIN_MTU 60 | |
127 | #define TG3_MAX_MTU(tp) \ | |
63c3a66f | 128 | (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
129 | |
130 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
131 | * You can't change the ring sizes, but you can change where you place | |
132 | * them in the NIC onboard memory. | |
133 | */ | |
7cb32cf2 | 134 | #define TG3_RX_STD_RING_SIZE(tp) \ |
63c3a66f | 135 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 136 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) |
1da177e4 | 137 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 138 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
63c3a66f | 139 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 140 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) |
1da177e4 LT |
141 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
142 | ||
143 | /* Do not place this n-ring entries value into the tp struct itself, | |
144 | * we really want to expose these constants to GCC so that modulo et | |
145 | * al. operations are done with shifts and masks instead of with | |
146 | * hw multiply/modulo instructions. Another solution would be to | |
147 | * replace things like '% foo' with '& (foo - 1)'. | |
148 | */ | |
1da177e4 LT |
149 | |
150 | #define TG3_TX_RING_SIZE 512 | |
151 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
152 | ||
2c49a44d MC |
153 | #define TG3_RX_STD_RING_BYTES(tp) \ |
154 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
155 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
156 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
157 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 158 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
159 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
160 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
161 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
162 | ||
287be12e MC |
163 | #define TG3_DMA_BYTE_ENAB 64 |
164 | ||
165 | #define TG3_RX_STD_DMA_SZ 1536 | |
166 | #define TG3_RX_JMB_DMA_SZ 9046 | |
167 | ||
168 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
169 | ||
170 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
171 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 172 | |
2c49a44d MC |
173 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
174 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 175 | |
2c49a44d MC |
176 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
177 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 178 | |
d2757fc4 MC |
179 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
180 | * that are at least dword aligned when used in PCIX mode. The driver | |
181 | * works around this bug by double copying the packet. This workaround | |
182 | * is built into the normal double copy length check for efficiency. | |
183 | * | |
184 | * However, the double copy is only necessary on those architectures | |
185 | * where unaligned memory accesses are inefficient. For those architectures | |
186 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
187 | * the 5701 in the normal rx path. Doing so saves a device structure | |
188 | * dereference by hardcoding the double copy threshold in place. | |
189 | */ | |
190 | #define TG3_RX_COPY_THRESHOLD 256 | |
191 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
192 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
193 | #else | |
194 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
195 | #endif | |
196 | ||
81389f57 MC |
197 | #if (NET_IP_ALIGN != 0) |
198 | #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) | |
199 | #else | |
9205fd9c | 200 | #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) |
81389f57 MC |
201 | #endif |
202 | ||
1da177e4 | 203 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 204 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
55086ad9 | 205 | #define TG3_TX_BD_DMA_MAX_2K 2048 |
a4cb428d | 206 | #define TG3_TX_BD_DMA_MAX_4K 4096 |
1da177e4 | 207 | |
ad829268 MC |
208 | #define TG3_RAW_IP_ALIGN 2 |
209 | ||
c6cdf436 | 210 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
21f7638e | 211 | #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2) |
c6cdf436 | 212 | |
077f849d JSR |
213 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
214 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
215 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
216 | ||
229b1ad1 | 217 | static char version[] = |
05dbe005 | 218 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
219 | |
220 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
221 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
222 | MODULE_LICENSE("GPL"); | |
223 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
224 | MODULE_FIRMWARE(FIRMWARE_TG3); |
225 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
226 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
227 | ||
1da177e4 LT |
228 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
229 | module_param(tg3_debug, int, 0); | |
230 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
231 | ||
3d567e0e NNS |
232 | #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001 |
233 | #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002 | |
234 | ||
a3aa1884 | 235 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
3d567e0e NNS |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901), |
255 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY | | |
256 | TG3_DRV_DATA_FLAG_5705_10_100}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2), | |
258 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY | | |
259 | TG3_DRV_DATA_FLAG_5705_10_100}, | |
13185217 | 260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, |
3d567e0e NNS |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F), |
262 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY | | |
263 | TG3_DRV_DATA_FLAG_5705_10_100}, | |
13185217 | 264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 | 267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
3d567e0e NNS |
268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F), |
269 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
13185217 HK |
270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, |
271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
272 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
3d567e0e NNS |
274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F), |
275 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
13185217 HK |
276 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, |
277 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
278 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
279 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 280 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
281 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
282 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
3d567e0e NNS |
283 | {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M, |
284 | PCI_VENDOR_ID_LENOVO, | |
285 | TG3PCI_SUBDEVICE_ID_LENOVO_5787M), | |
286 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
13185217 | 287 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, |
3d567e0e NNS |
288 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F), |
289 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
13185217 HK |
290 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
291 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
292 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
293 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
294 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
295 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
296 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
297 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
298 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
299 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
300 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 301 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
302 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
303 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
304 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
305 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
306 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
307 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
3d567e0e NNS |
308 | {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780, |
309 | PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A), | |
310 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
311 | {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780, | |
312 | PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B), | |
313 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
321d32a0 MC |
314 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
315 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
3d567e0e NNS |
316 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790), |
317 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
5e7ccf20 | 318 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 | 319 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
79d49695 | 320 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)}, |
5001e2f6 | 321 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, |
b0f75221 MC |
322 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
323 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
324 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
325 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
3d567e0e NNS |
326 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791), |
327 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
328 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795), | |
329 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
302b500b | 330 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
ba1f3c76 | 331 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
02eca3f5 | 332 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)}, |
13185217 HK |
333 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
334 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
335 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
336 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
337 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
338 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
339 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
1dcb14d9 | 340 | {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */ |
13185217 | 341 | {} |
1da177e4 LT |
342 | }; |
343 | ||
344 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
345 | ||
50da859d | 346 | static const struct { |
1da177e4 | 347 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 348 | } ethtool_stats_keys[] = { |
1da177e4 LT |
349 | { "rx_octets" }, |
350 | { "rx_fragments" }, | |
351 | { "rx_ucast_packets" }, | |
352 | { "rx_mcast_packets" }, | |
353 | { "rx_bcast_packets" }, | |
354 | { "rx_fcs_errors" }, | |
355 | { "rx_align_errors" }, | |
356 | { "rx_xon_pause_rcvd" }, | |
357 | { "rx_xoff_pause_rcvd" }, | |
358 | { "rx_mac_ctrl_rcvd" }, | |
359 | { "rx_xoff_entered" }, | |
360 | { "rx_frame_too_long_errors" }, | |
361 | { "rx_jabbers" }, | |
362 | { "rx_undersize_packets" }, | |
363 | { "rx_in_length_errors" }, | |
364 | { "rx_out_length_errors" }, | |
365 | { "rx_64_or_less_octet_packets" }, | |
366 | { "rx_65_to_127_octet_packets" }, | |
367 | { "rx_128_to_255_octet_packets" }, | |
368 | { "rx_256_to_511_octet_packets" }, | |
369 | { "rx_512_to_1023_octet_packets" }, | |
370 | { "rx_1024_to_1522_octet_packets" }, | |
371 | { "rx_1523_to_2047_octet_packets" }, | |
372 | { "rx_2048_to_4095_octet_packets" }, | |
373 | { "rx_4096_to_8191_octet_packets" }, | |
374 | { "rx_8192_to_9022_octet_packets" }, | |
375 | ||
376 | { "tx_octets" }, | |
377 | { "tx_collisions" }, | |
378 | ||
379 | { "tx_xon_sent" }, | |
380 | { "tx_xoff_sent" }, | |
381 | { "tx_flow_control" }, | |
382 | { "tx_mac_errors" }, | |
383 | { "tx_single_collisions" }, | |
384 | { "tx_mult_collisions" }, | |
385 | { "tx_deferred" }, | |
386 | { "tx_excessive_collisions" }, | |
387 | { "tx_late_collisions" }, | |
388 | { "tx_collide_2times" }, | |
389 | { "tx_collide_3times" }, | |
390 | { "tx_collide_4times" }, | |
391 | { "tx_collide_5times" }, | |
392 | { "tx_collide_6times" }, | |
393 | { "tx_collide_7times" }, | |
394 | { "tx_collide_8times" }, | |
395 | { "tx_collide_9times" }, | |
396 | { "tx_collide_10times" }, | |
397 | { "tx_collide_11times" }, | |
398 | { "tx_collide_12times" }, | |
399 | { "tx_collide_13times" }, | |
400 | { "tx_collide_14times" }, | |
401 | { "tx_collide_15times" }, | |
402 | { "tx_ucast_packets" }, | |
403 | { "tx_mcast_packets" }, | |
404 | { "tx_bcast_packets" }, | |
405 | { "tx_carrier_sense_errors" }, | |
406 | { "tx_discards" }, | |
407 | { "tx_errors" }, | |
408 | ||
409 | { "dma_writeq_full" }, | |
410 | { "dma_write_prioq_full" }, | |
411 | { "rxbds_empty" }, | |
412 | { "rx_discards" }, | |
413 | { "rx_errors" }, | |
414 | { "rx_threshold_hit" }, | |
415 | ||
416 | { "dma_readq_full" }, | |
417 | { "dma_read_prioq_full" }, | |
418 | { "tx_comp_queue_full" }, | |
419 | ||
420 | { "ring_set_send_prod_index" }, | |
421 | { "ring_status_update" }, | |
422 | { "nic_irqs" }, | |
423 | { "nic_avoided_irqs" }, | |
4452d099 MC |
424 | { "nic_tx_threshold_hit" }, |
425 | ||
426 | { "mbuf_lwm_thresh_hit" }, | |
1da177e4 LT |
427 | }; |
428 | ||
48fa55a0 | 429 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
93df8b8f NNS |
430 | #define TG3_NVRAM_TEST 0 |
431 | #define TG3_LINK_TEST 1 | |
432 | #define TG3_REGISTER_TEST 2 | |
433 | #define TG3_MEMORY_TEST 3 | |
434 | #define TG3_MAC_LOOPB_TEST 4 | |
435 | #define TG3_PHY_LOOPB_TEST 5 | |
436 | #define TG3_EXT_LOOPB_TEST 6 | |
437 | #define TG3_INTERRUPT_TEST 7 | |
48fa55a0 MC |
438 | |
439 | ||
50da859d | 440 | static const struct { |
4cafd3f5 | 441 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 442 | } ethtool_test_keys[] = { |
93df8b8f NNS |
443 | [TG3_NVRAM_TEST] = { "nvram test (online) " }, |
444 | [TG3_LINK_TEST] = { "link test (online) " }, | |
445 | [TG3_REGISTER_TEST] = { "register test (offline)" }, | |
446 | [TG3_MEMORY_TEST] = { "memory test (offline)" }, | |
447 | [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" }, | |
448 | [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" }, | |
449 | [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" }, | |
450 | [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" }, | |
4cafd3f5 MC |
451 | }; |
452 | ||
48fa55a0 MC |
453 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
454 | ||
455 | ||
b401e9e2 MC |
456 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
457 | { | |
458 | writel(val, tp->regs + off); | |
459 | } | |
460 | ||
461 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
462 | { | |
de6f31eb | 463 | return readl(tp->regs + off); |
b401e9e2 MC |
464 | } |
465 | ||
0d3031d9 MC |
466 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
467 | { | |
468 | writel(val, tp->aperegs + off); | |
469 | } | |
470 | ||
471 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
472 | { | |
de6f31eb | 473 | return readl(tp->aperegs + off); |
0d3031d9 MC |
474 | } |
475 | ||
1da177e4 LT |
476 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
477 | { | |
6892914f MC |
478 | unsigned long flags; |
479 | ||
480 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
481 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
482 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 483 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
484 | } |
485 | ||
486 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
487 | { | |
488 | writel(val, tp->regs + off); | |
489 | readl(tp->regs + off); | |
1da177e4 LT |
490 | } |
491 | ||
6892914f | 492 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 493 | { |
6892914f MC |
494 | unsigned long flags; |
495 | u32 val; | |
496 | ||
497 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
498 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
499 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
500 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
501 | return val; | |
502 | } | |
503 | ||
504 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
505 | { | |
506 | unsigned long flags; | |
507 | ||
508 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
509 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
510 | TG3_64BIT_REG_LOW, val); | |
511 | return; | |
512 | } | |
66711e66 | 513 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
514 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
515 | TG3_64BIT_REG_LOW, val); | |
516 | return; | |
1da177e4 | 517 | } |
6892914f MC |
518 | |
519 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
520 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
521 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
522 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
523 | ||
524 | /* In indirect mode when disabling interrupts, we also need | |
525 | * to clear the interrupt bit in the GRC local ctrl register. | |
526 | */ | |
527 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
528 | (val == 0x1)) { | |
529 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
530 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
531 | } | |
532 | } | |
533 | ||
534 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
535 | { | |
536 | unsigned long flags; | |
537 | u32 val; | |
538 | ||
539 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
540 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
541 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
542 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
543 | return val; | |
544 | } | |
545 | ||
b401e9e2 MC |
546 | /* usec_wait specifies the wait time in usec when writing to certain registers |
547 | * where it is unsafe to read back the register without some delay. | |
548 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
549 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
550 | */ | |
551 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 552 | { |
63c3a66f | 553 | if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) |
b401e9e2 MC |
554 | /* Non-posted methods */ |
555 | tp->write32(tp, off, val); | |
556 | else { | |
557 | /* Posted method */ | |
558 | tg3_write32(tp, off, val); | |
559 | if (usec_wait) | |
560 | udelay(usec_wait); | |
561 | tp->read32(tp, off); | |
562 | } | |
563 | /* Wait again after the read for the posted method to guarantee that | |
564 | * the wait time is met. | |
565 | */ | |
566 | if (usec_wait) | |
567 | udelay(usec_wait); | |
1da177e4 LT |
568 | } |
569 | ||
09ee929c MC |
570 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
571 | { | |
572 | tp->write32_mbox(tp, off, val); | |
63c3a66f | 573 | if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) |
6892914f | 574 | tp->read32_mbox(tp, off); |
09ee929c MC |
575 | } |
576 | ||
20094930 | 577 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
578 | { |
579 | void __iomem *mbox = tp->regs + off; | |
580 | writel(val, mbox); | |
63c3a66f | 581 | if (tg3_flag(tp, TXD_MBOX_HWBUG)) |
1da177e4 | 582 | writel(val, mbox); |
63c3a66f | 583 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1da177e4 LT |
584 | readl(mbox); |
585 | } | |
586 | ||
b5d3772c MC |
587 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
588 | { | |
de6f31eb | 589 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
590 | } |
591 | ||
592 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
593 | { | |
594 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
595 | } | |
596 | ||
c6cdf436 | 597 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 598 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
599 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
600 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
601 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 602 | |
c6cdf436 MC |
603 | #define tw32(reg, val) tp->write32(tp, reg, val) |
604 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
605 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
606 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
607 | |
608 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
609 | { | |
6892914f MC |
610 | unsigned long flags; |
611 | ||
6ff6f81d | 612 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
613 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) |
614 | return; | |
615 | ||
6892914f | 616 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 617 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
618 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
619 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 620 | |
bbadf503 MC |
621 | /* Always leave this as zero. */ |
622 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
623 | } else { | |
624 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
625 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 626 | |
bbadf503 MC |
627 | /* Always leave this as zero. */ |
628 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
629 | } | |
630 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
631 | } |
632 | ||
1da177e4 LT |
633 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
634 | { | |
6892914f MC |
635 | unsigned long flags; |
636 | ||
6ff6f81d | 637 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
638 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { |
639 | *val = 0; | |
640 | return; | |
641 | } | |
642 | ||
6892914f | 643 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 644 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
645 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
646 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 647 | |
bbadf503 MC |
648 | /* Always leave this as zero. */ |
649 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
650 | } else { | |
651 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
652 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
653 | ||
654 | /* Always leave this as zero. */ | |
655 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
656 | } | |
6892914f | 657 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
658 | } |
659 | ||
0d3031d9 MC |
660 | static void tg3_ape_lock_init(struct tg3 *tp) |
661 | { | |
662 | int i; | |
6f5c8f83 | 663 | u32 regbase, bit; |
f92d9dc1 MC |
664 | |
665 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
666 | regbase = TG3_APE_LOCK_GRANT; | |
667 | else | |
668 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
669 | |
670 | /* Make sure the driver hasn't any stale locks. */ | |
78f94dc7 MC |
671 | for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) { |
672 | switch (i) { | |
673 | case TG3_APE_LOCK_PHY0: | |
674 | case TG3_APE_LOCK_PHY1: | |
675 | case TG3_APE_LOCK_PHY2: | |
676 | case TG3_APE_LOCK_PHY3: | |
677 | bit = APE_LOCK_GRANT_DRIVER; | |
678 | break; | |
679 | default: | |
680 | if (!tp->pci_fn) | |
681 | bit = APE_LOCK_GRANT_DRIVER; | |
682 | else | |
683 | bit = 1 << tp->pci_fn; | |
684 | } | |
685 | tg3_ape_write32(tp, regbase + 4 * i, bit); | |
6f5c8f83 MC |
686 | } |
687 | ||
0d3031d9 MC |
688 | } |
689 | ||
690 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
691 | { | |
692 | int i, off; | |
693 | int ret = 0; | |
6f5c8f83 | 694 | u32 status, req, gnt, bit; |
0d3031d9 | 695 | |
63c3a66f | 696 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
697 | return 0; |
698 | ||
699 | switch (locknum) { | |
6f5c8f83 MC |
700 | case TG3_APE_LOCK_GPIO: |
701 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
702 | return 0; | |
33f401ae MC |
703 | case TG3_APE_LOCK_GRC: |
704 | case TG3_APE_LOCK_MEM: | |
78f94dc7 MC |
705 | if (!tp->pci_fn) |
706 | bit = APE_LOCK_REQ_DRIVER; | |
707 | else | |
708 | bit = 1 << tp->pci_fn; | |
33f401ae | 709 | break; |
8151ad57 MC |
710 | case TG3_APE_LOCK_PHY0: |
711 | case TG3_APE_LOCK_PHY1: | |
712 | case TG3_APE_LOCK_PHY2: | |
713 | case TG3_APE_LOCK_PHY3: | |
714 | bit = APE_LOCK_REQ_DRIVER; | |
715 | break; | |
33f401ae MC |
716 | default: |
717 | return -EINVAL; | |
0d3031d9 MC |
718 | } |
719 | ||
f92d9dc1 MC |
720 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
721 | req = TG3_APE_LOCK_REQ; | |
722 | gnt = TG3_APE_LOCK_GRANT; | |
723 | } else { | |
724 | req = TG3_APE_PER_LOCK_REQ; | |
725 | gnt = TG3_APE_PER_LOCK_GRANT; | |
726 | } | |
727 | ||
0d3031d9 MC |
728 | off = 4 * locknum; |
729 | ||
6f5c8f83 | 730 | tg3_ape_write32(tp, req + off, bit); |
0d3031d9 MC |
731 | |
732 | /* Wait for up to 1 millisecond to acquire lock. */ | |
733 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 734 | status = tg3_ape_read32(tp, gnt + off); |
6f5c8f83 | 735 | if (status == bit) |
0d3031d9 MC |
736 | break; |
737 | udelay(10); | |
738 | } | |
739 | ||
6f5c8f83 | 740 | if (status != bit) { |
0d3031d9 | 741 | /* Revoke the lock request. */ |
6f5c8f83 | 742 | tg3_ape_write32(tp, gnt + off, bit); |
0d3031d9 MC |
743 | ret = -EBUSY; |
744 | } | |
745 | ||
746 | return ret; | |
747 | } | |
748 | ||
749 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
750 | { | |
6f5c8f83 | 751 | u32 gnt, bit; |
0d3031d9 | 752 | |
63c3a66f | 753 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
754 | return; |
755 | ||
756 | switch (locknum) { | |
6f5c8f83 MC |
757 | case TG3_APE_LOCK_GPIO: |
758 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
759 | return; | |
33f401ae MC |
760 | case TG3_APE_LOCK_GRC: |
761 | case TG3_APE_LOCK_MEM: | |
78f94dc7 MC |
762 | if (!tp->pci_fn) |
763 | bit = APE_LOCK_GRANT_DRIVER; | |
764 | else | |
765 | bit = 1 << tp->pci_fn; | |
33f401ae | 766 | break; |
8151ad57 MC |
767 | case TG3_APE_LOCK_PHY0: |
768 | case TG3_APE_LOCK_PHY1: | |
769 | case TG3_APE_LOCK_PHY2: | |
770 | case TG3_APE_LOCK_PHY3: | |
771 | bit = APE_LOCK_GRANT_DRIVER; | |
772 | break; | |
33f401ae MC |
773 | default: |
774 | return; | |
0d3031d9 MC |
775 | } |
776 | ||
f92d9dc1 MC |
777 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
778 | gnt = TG3_APE_LOCK_GRANT; | |
779 | else | |
780 | gnt = TG3_APE_PER_LOCK_GRANT; | |
781 | ||
6f5c8f83 | 782 | tg3_ape_write32(tp, gnt + 4 * locknum, bit); |
0d3031d9 MC |
783 | } |
784 | ||
b65a372b | 785 | static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us) |
fd6d3f0e | 786 | { |
fd6d3f0e MC |
787 | u32 apedata; |
788 | ||
b65a372b MC |
789 | while (timeout_us) { |
790 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
791 | return -EBUSY; | |
792 | ||
793 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
794 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
795 | break; | |
796 | ||
797 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
798 | ||
799 | udelay(10); | |
800 | timeout_us -= (timeout_us > 10) ? 10 : timeout_us; | |
801 | } | |
802 | ||
803 | return timeout_us ? 0 : -EBUSY; | |
804 | } | |
805 | ||
cf8d55ae MC |
806 | static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us) |
807 | { | |
808 | u32 i, apedata; | |
809 | ||
810 | for (i = 0; i < timeout_us / 10; i++) { | |
811 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
812 | ||
813 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
814 | break; | |
815 | ||
816 | udelay(10); | |
817 | } | |
818 | ||
819 | return i == timeout_us / 10; | |
820 | } | |
821 | ||
86449944 MC |
822 | static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, |
823 | u32 len) | |
cf8d55ae MC |
824 | { |
825 | int err; | |
826 | u32 i, bufoff, msgoff, maxlen, apedata; | |
827 | ||
828 | if (!tg3_flag(tp, APE_HAS_NCSI)) | |
829 | return 0; | |
830 | ||
831 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
832 | if (apedata != APE_SEG_SIG_MAGIC) | |
833 | return -ENODEV; | |
834 | ||
835 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
836 | if (!(apedata & APE_FW_STATUS_READY)) | |
837 | return -EAGAIN; | |
838 | ||
839 | bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) + | |
840 | TG3_APE_SHMEM_BASE; | |
841 | msgoff = bufoff + 2 * sizeof(u32); | |
842 | maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN); | |
843 | ||
844 | while (len) { | |
845 | u32 length; | |
846 | ||
847 | /* Cap xfer sizes to scratchpad limits. */ | |
848 | length = (len > maxlen) ? maxlen : len; | |
849 | len -= length; | |
850 | ||
851 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
852 | if (!(apedata & APE_FW_STATUS_READY)) | |
853 | return -EAGAIN; | |
854 | ||
855 | /* Wait for up to 1 msec for APE to service previous event. */ | |
856 | err = tg3_ape_event_lock(tp, 1000); | |
857 | if (err) | |
858 | return err; | |
859 | ||
860 | apedata = APE_EVENT_STATUS_DRIVER_EVNT | | |
861 | APE_EVENT_STATUS_SCRTCHPD_READ | | |
862 | APE_EVENT_STATUS_EVENT_PENDING; | |
863 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata); | |
864 | ||
865 | tg3_ape_write32(tp, bufoff, base_off); | |
866 | tg3_ape_write32(tp, bufoff + sizeof(u32), length); | |
867 | ||
868 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
869 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
870 | ||
871 | base_off += length; | |
872 | ||
873 | if (tg3_ape_wait_for_event(tp, 30000)) | |
874 | return -EAGAIN; | |
875 | ||
876 | for (i = 0; length; i += 4, length -= 4) { | |
877 | u32 val = tg3_ape_read32(tp, msgoff + i); | |
878 | memcpy(data, &val, sizeof(u32)); | |
879 | data++; | |
880 | } | |
881 | } | |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
b65a372b MC |
886 | static int tg3_ape_send_event(struct tg3 *tp, u32 event) |
887 | { | |
888 | int err; | |
889 | u32 apedata; | |
fd6d3f0e MC |
890 | |
891 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
892 | if (apedata != APE_SEG_SIG_MAGIC) | |
b65a372b | 893 | return -EAGAIN; |
fd6d3f0e MC |
894 | |
895 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
896 | if (!(apedata & APE_FW_STATUS_READY)) | |
b65a372b | 897 | return -EAGAIN; |
fd6d3f0e MC |
898 | |
899 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
b65a372b MC |
900 | err = tg3_ape_event_lock(tp, 1000); |
901 | if (err) | |
902 | return err; | |
fd6d3f0e | 903 | |
b65a372b MC |
904 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, |
905 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
fd6d3f0e | 906 | |
b65a372b MC |
907 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); |
908 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
fd6d3f0e | 909 | |
b65a372b | 910 | return 0; |
fd6d3f0e MC |
911 | } |
912 | ||
913 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
914 | { | |
915 | u32 event; | |
916 | u32 apedata; | |
917 | ||
918 | if (!tg3_flag(tp, ENABLE_APE)) | |
919 | return; | |
920 | ||
921 | switch (kind) { | |
922 | case RESET_KIND_INIT: | |
923 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
924 | APE_HOST_SEG_SIG_MAGIC); | |
925 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
926 | APE_HOST_SEG_LEN_MAGIC); | |
927 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
928 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
929 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
930 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); | |
931 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
932 | APE_HOST_BEHAV_NO_PHYLOCK); | |
933 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, | |
934 | TG3_APE_HOST_DRVR_STATE_START); | |
935 | ||
936 | event = APE_EVENT_STATUS_STATE_START; | |
937 | break; | |
938 | case RESET_KIND_SHUTDOWN: | |
939 | /* With the interface we are currently using, | |
940 | * APE does not track driver state. Wiping | |
941 | * out the HOST SEGMENT SIGNATURE forces | |
942 | * the APE to assume OS absent status. | |
943 | */ | |
944 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
945 | ||
946 | if (device_may_wakeup(&tp->pdev->dev) && | |
947 | tg3_flag(tp, WOL_ENABLE)) { | |
948 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, | |
949 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
950 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
951 | } else | |
952 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
953 | ||
954 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
955 | ||
956 | event = APE_EVENT_STATUS_STATE_UNLOAD; | |
957 | break; | |
958 | case RESET_KIND_SUSPEND: | |
959 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
960 | break; | |
961 | default: | |
962 | return; | |
963 | } | |
964 | ||
965 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
966 | ||
967 | tg3_ape_send_event(tp, event); | |
968 | } | |
969 | ||
1da177e4 LT |
970 | static void tg3_disable_ints(struct tg3 *tp) |
971 | { | |
89aeb3bc MC |
972 | int i; |
973 | ||
1da177e4 LT |
974 | tw32(TG3PCI_MISC_HOST_CTRL, |
975 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
976 | for (i = 0; i < tp->irq_max; i++) |
977 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
978 | } |
979 | ||
1da177e4 LT |
980 | static void tg3_enable_ints(struct tg3 *tp) |
981 | { | |
89aeb3bc | 982 | int i; |
89aeb3bc | 983 | |
bbe832c0 MC |
984 | tp->irq_sync = 0; |
985 | wmb(); | |
986 | ||
1da177e4 LT |
987 | tw32(TG3PCI_MISC_HOST_CTRL, |
988 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 989 | |
f89f38b8 | 990 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
991 | for (i = 0; i < tp->irq_cnt; i++) { |
992 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 993 | |
898a56f8 | 994 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
63c3a66f | 995 | if (tg3_flag(tp, 1SHOT_MSI)) |
89aeb3bc | 996 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
f19af9c2 | 997 | |
f89f38b8 | 998 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 999 | } |
f19af9c2 MC |
1000 | |
1001 | /* Force an initial interrupt */ | |
63c3a66f | 1002 | if (!tg3_flag(tp, TAGGED_STATUS) && |
f19af9c2 MC |
1003 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) |
1004 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
1005 | else | |
f89f38b8 MC |
1006 | tw32(HOSTCC_MODE, tp->coal_now); |
1007 | ||
1008 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
1009 | } |
1010 | ||
17375d25 | 1011 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 1012 | { |
17375d25 | 1013 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 1014 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
1015 | unsigned int work_exists = 0; |
1016 | ||
1017 | /* check for phy events */ | |
63c3a66f | 1018 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
04237ddd MC |
1019 | if (sblk->status & SD_STATUS_LINK_CHG) |
1020 | work_exists = 1; | |
1021 | } | |
f891ea16 MC |
1022 | |
1023 | /* check for TX work to do */ | |
1024 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons) | |
1025 | work_exists = 1; | |
1026 | ||
1027 | /* check for RX work to do */ | |
1028 | if (tnapi->rx_rcb_prod_idx && | |
8d9d7cfc | 1029 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
1030 | work_exists = 1; |
1031 | ||
1032 | return work_exists; | |
1033 | } | |
1034 | ||
17375d25 | 1035 | /* tg3_int_reenable |
04237ddd MC |
1036 | * similar to tg3_enable_ints, but it accurately determines whether there |
1037 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 1038 | * which reenables interrupts |
1da177e4 | 1039 | */ |
17375d25 | 1040 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 1041 | { |
17375d25 MC |
1042 | struct tg3 *tp = tnapi->tp; |
1043 | ||
898a56f8 | 1044 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
1045 | mmiowb(); |
1046 | ||
fac9b83e DM |
1047 | /* When doing tagged status, this work check is unnecessary. |
1048 | * The last_tag we write above tells the chip which piece of | |
1049 | * work we've completed. | |
1050 | */ | |
63c3a66f | 1051 | if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) |
04237ddd | 1052 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 1053 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
1054 | } |
1055 | ||
1da177e4 LT |
1056 | static void tg3_switch_clocks(struct tg3 *tp) |
1057 | { | |
f6eb9b1f | 1058 | u32 clock_ctrl; |
1da177e4 LT |
1059 | u32 orig_clock_ctrl; |
1060 | ||
63c3a66f | 1061 | if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) |
4cf78e4f MC |
1062 | return; |
1063 | ||
f6eb9b1f MC |
1064 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
1065 | ||
1da177e4 LT |
1066 | orig_clock_ctrl = clock_ctrl; |
1067 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
1068 | CLOCK_CTRL_CLKRUN_OENABLE | | |
1069 | 0x1f); | |
1070 | tp->pci_clock_ctrl = clock_ctrl; | |
1071 | ||
63c3a66f | 1072 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 | 1073 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { |
b401e9e2 MC |
1074 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
1075 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
1076 | } |
1077 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
1078 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
1079 | clock_ctrl | | |
1080 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
1081 | 40); | |
1082 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
1083 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
1084 | 40); | |
1da177e4 | 1085 | } |
b401e9e2 | 1086 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
1087 | } |
1088 | ||
1089 | #define PHY_BUSY_LOOPS 5000 | |
1090 | ||
1091 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
1092 | { | |
1093 | u32 frame_val; | |
1094 | unsigned int loops; | |
1095 | int ret; | |
1096 | ||
1097 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
1098 | tw32_f(MAC_MI_MODE, | |
1099 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
1100 | udelay(80); | |
1101 | } | |
1102 | ||
8151ad57 MC |
1103 | tg3_ape_lock(tp, tp->phy_ape_lock); |
1104 | ||
1da177e4 LT |
1105 | *val = 0x0; |
1106 | ||
882e9793 | 1107 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
1108 | MI_COM_PHY_ADDR_MASK); |
1109 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
1110 | MI_COM_REG_ADDR_MASK); | |
1111 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 1112 | |
1da177e4 LT |
1113 | tw32_f(MAC_MI_COM, frame_val); |
1114 | ||
1115 | loops = PHY_BUSY_LOOPS; | |
1116 | while (loops != 0) { | |
1117 | udelay(10); | |
1118 | frame_val = tr32(MAC_MI_COM); | |
1119 | ||
1120 | if ((frame_val & MI_COM_BUSY) == 0) { | |
1121 | udelay(5); | |
1122 | frame_val = tr32(MAC_MI_COM); | |
1123 | break; | |
1124 | } | |
1125 | loops -= 1; | |
1126 | } | |
1127 | ||
1128 | ret = -EBUSY; | |
1129 | if (loops != 0) { | |
1130 | *val = frame_val & MI_COM_DATA_MASK; | |
1131 | ret = 0; | |
1132 | } | |
1133 | ||
1134 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
1135 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1136 | udelay(80); | |
1137 | } | |
1138 | ||
8151ad57 MC |
1139 | tg3_ape_unlock(tp, tp->phy_ape_lock); |
1140 | ||
1da177e4 LT |
1141 | return ret; |
1142 | } | |
1143 | ||
1144 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
1145 | { | |
1146 | u32 frame_val; | |
1147 | unsigned int loops; | |
1148 | int ret; | |
1149 | ||
f07e9af3 | 1150 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
221c5637 | 1151 | (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) |
b5d3772c MC |
1152 | return 0; |
1153 | ||
1da177e4 LT |
1154 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
1155 | tw32_f(MAC_MI_MODE, | |
1156 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
1157 | udelay(80); | |
1158 | } | |
1159 | ||
8151ad57 MC |
1160 | tg3_ape_lock(tp, tp->phy_ape_lock); |
1161 | ||
882e9793 | 1162 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
1163 | MI_COM_PHY_ADDR_MASK); |
1164 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
1165 | MI_COM_REG_ADDR_MASK); | |
1166 | frame_val |= (val & MI_COM_DATA_MASK); | |
1167 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 1168 | |
1da177e4 LT |
1169 | tw32_f(MAC_MI_COM, frame_val); |
1170 | ||
1171 | loops = PHY_BUSY_LOOPS; | |
1172 | while (loops != 0) { | |
1173 | udelay(10); | |
1174 | frame_val = tr32(MAC_MI_COM); | |
1175 | if ((frame_val & MI_COM_BUSY) == 0) { | |
1176 | udelay(5); | |
1177 | frame_val = tr32(MAC_MI_COM); | |
1178 | break; | |
1179 | } | |
1180 | loops -= 1; | |
1181 | } | |
1182 | ||
1183 | ret = -EBUSY; | |
1184 | if (loops != 0) | |
1185 | ret = 0; | |
1186 | ||
1187 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
1188 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1189 | udelay(80); | |
1190 | } | |
1191 | ||
8151ad57 MC |
1192 | tg3_ape_unlock(tp, tp->phy_ape_lock); |
1193 | ||
1da177e4 LT |
1194 | return ret; |
1195 | } | |
1196 | ||
b0988c15 MC |
1197 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
1198 | { | |
1199 | int err; | |
1200 | ||
1201 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1202 | if (err) | |
1203 | goto done; | |
1204 | ||
1205 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1206 | if (err) | |
1207 | goto done; | |
1208 | ||
1209 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1210 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1211 | if (err) | |
1212 | goto done; | |
1213 | ||
1214 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
1215 | ||
1216 | done: | |
1217 | return err; | |
1218 | } | |
1219 | ||
1220 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
1221 | { | |
1222 | int err; | |
1223 | ||
1224 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1225 | if (err) | |
1226 | goto done; | |
1227 | ||
1228 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1229 | if (err) | |
1230 | goto done; | |
1231 | ||
1232 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1233 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1234 | if (err) | |
1235 | goto done; | |
1236 | ||
1237 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
1238 | ||
1239 | done: | |
1240 | return err; | |
1241 | } | |
1242 | ||
1243 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) | |
1244 | { | |
1245 | int err; | |
1246 | ||
1247 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1248 | if (!err) | |
1249 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
1250 | ||
1251 | return err; | |
1252 | } | |
1253 | ||
1254 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
1255 | { | |
1256 | int err; | |
1257 | ||
1258 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1259 | if (!err) | |
1260 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1261 | ||
1262 | return err; | |
1263 | } | |
1264 | ||
15ee95c3 MC |
1265 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) |
1266 | { | |
1267 | int err; | |
1268 | ||
1269 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1270 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | | |
1271 | MII_TG3_AUXCTL_SHDWSEL_MISC); | |
1272 | if (!err) | |
1273 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); | |
1274 | ||
1275 | return err; | |
1276 | } | |
1277 | ||
b4bd2929 MC |
1278 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) |
1279 | { | |
1280 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) | |
1281 | set |= MII_TG3_AUXCTL_MISC_WREN; | |
1282 | ||
1283 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); | |
1284 | } | |
1285 | ||
1d36ba45 MC |
1286 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ |
1287 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1288 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ | |
1289 | MII_TG3_AUXCTL_ACTL_TX_6DB) | |
1290 | ||
1291 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ | |
1292 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1293 | MII_TG3_AUXCTL_ACTL_TX_6DB); | |
1294 | ||
95e2869a MC |
1295 | static int tg3_bmcr_reset(struct tg3 *tp) |
1296 | { | |
1297 | u32 phy_control; | |
1298 | int limit, err; | |
1299 | ||
1300 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
1301 | * clears or we time out. | |
1302 | */ | |
1303 | phy_control = BMCR_RESET; | |
1304 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
1305 | if (err != 0) | |
1306 | return -EBUSY; | |
1307 | ||
1308 | limit = 5000; | |
1309 | while (limit--) { | |
1310 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
1311 | if (err != 0) | |
1312 | return -EBUSY; | |
1313 | ||
1314 | if ((phy_control & BMCR_RESET) == 0) { | |
1315 | udelay(40); | |
1316 | break; | |
1317 | } | |
1318 | udelay(10); | |
1319 | } | |
d4675b52 | 1320 | if (limit < 0) |
95e2869a MC |
1321 | return -EBUSY; |
1322 | ||
1323 | return 0; | |
1324 | } | |
1325 | ||
158d7abd MC |
1326 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
1327 | { | |
3d16543d | 1328 | struct tg3 *tp = bp->priv; |
158d7abd MC |
1329 | u32 val; |
1330 | ||
24bb4fb6 | 1331 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1332 | |
1333 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
1334 | val = -EIO; |
1335 | ||
1336 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
1337 | |
1338 | return val; | |
1339 | } | |
1340 | ||
1341 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
1342 | { | |
3d16543d | 1343 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 1344 | u32 ret = 0; |
158d7abd | 1345 | |
24bb4fb6 | 1346 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1347 | |
1348 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 1349 | ret = -EIO; |
158d7abd | 1350 | |
24bb4fb6 MC |
1351 | spin_unlock_bh(&tp->lock); |
1352 | ||
1353 | return ret; | |
158d7abd MC |
1354 | } |
1355 | ||
1356 | static int tg3_mdio_reset(struct mii_bus *bp) | |
1357 | { | |
1358 | return 0; | |
1359 | } | |
1360 | ||
9c61d6bc | 1361 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
1362 | { |
1363 | u32 val; | |
fcb389df | 1364 | struct phy_device *phydev; |
a9daf367 | 1365 | |
3f0e3ad7 | 1366 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 1367 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
1368 | case PHY_ID_BCM50610: |
1369 | case PHY_ID_BCM50610M: | |
fcb389df MC |
1370 | val = MAC_PHYCFG2_50610_LED_MODES; |
1371 | break; | |
6a443a0f | 1372 | case PHY_ID_BCMAC131: |
fcb389df MC |
1373 | val = MAC_PHYCFG2_AC131_LED_MODES; |
1374 | break; | |
6a443a0f | 1375 | case PHY_ID_RTL8211C: |
fcb389df MC |
1376 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
1377 | break; | |
6a443a0f | 1378 | case PHY_ID_RTL8201E: |
fcb389df MC |
1379 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
1380 | break; | |
1381 | default: | |
a9daf367 | 1382 | return; |
fcb389df MC |
1383 | } |
1384 | ||
1385 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
1386 | tw32(MAC_PHYCFG2, val); | |
1387 | ||
1388 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
1389 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
1390 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1391 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
1392 | tw32(MAC_PHYCFG1, val); |
1393 | ||
1394 | return; | |
1395 | } | |
1396 | ||
63c3a66f | 1397 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) |
fcb389df MC |
1398 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
1399 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1400 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1401 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1402 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1403 | MAC_PHYCFG2_INBAND_ENABLE; | |
1404 | ||
1405 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 1406 | |
bb85fbb6 MC |
1407 | val = tr32(MAC_PHYCFG1); |
1408 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1409 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
63c3a66f JP |
1410 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1411 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 | 1412 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; |
63c3a66f | 1413 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1414 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; |
1415 | } | |
bb85fbb6 MC |
1416 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1417 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1418 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1419 | |
a9daf367 MC |
1420 | val = tr32(MAC_EXT_RGMII_MODE); |
1421 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1422 | MAC_RGMII_MODE_RX_QUALITY | | |
1423 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1424 | MAC_RGMII_MODE_RX_ENG_DET | | |
1425 | MAC_RGMII_MODE_TX_ENABLE | | |
1426 | MAC_RGMII_MODE_TX_LOWPWR | | |
1427 | MAC_RGMII_MODE_TX_RESET); | |
63c3a66f JP |
1428 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1429 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 MC |
1430 | val |= MAC_RGMII_MODE_RX_INT_B | |
1431 | MAC_RGMII_MODE_RX_QUALITY | | |
1432 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1433 | MAC_RGMII_MODE_RX_ENG_DET; | |
63c3a66f | 1434 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1435 | val |= MAC_RGMII_MODE_TX_ENABLE | |
1436 | MAC_RGMII_MODE_TX_LOWPWR | | |
1437 | MAC_RGMII_MODE_TX_RESET; | |
1438 | } | |
1439 | tw32(MAC_EXT_RGMII_MODE, val); | |
1440 | } | |
1441 | ||
158d7abd MC |
1442 | static void tg3_mdio_start(struct tg3 *tp) |
1443 | { | |
158d7abd MC |
1444 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1445 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1446 | udelay(80); | |
a9daf367 | 1447 | |
63c3a66f | 1448 | if (tg3_flag(tp, MDIOBUS_INITED) && |
9ea4818d MC |
1449 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
1450 | tg3_mdio_config_5785(tp); | |
1451 | } | |
1452 | ||
1453 | static int tg3_mdio_init(struct tg3 *tp) | |
1454 | { | |
1455 | int i; | |
1456 | u32 reg; | |
1457 | struct phy_device *phydev; | |
1458 | ||
63c3a66f | 1459 | if (tg3_flag(tp, 5717_PLUS)) { |
9c7df915 | 1460 | u32 is_serdes; |
882e9793 | 1461 | |
69f11c99 | 1462 | tp->phy_addr = tp->pci_fn + 1; |
882e9793 | 1463 | |
d1ec96af MC |
1464 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1465 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1466 | else | |
1467 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1468 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1469 | if (is_serdes) |
1470 | tp->phy_addr += 7; | |
1471 | } else | |
3f0e3ad7 | 1472 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1473 | |
158d7abd MC |
1474 | tg3_mdio_start(tp); |
1475 | ||
63c3a66f | 1476 | if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) |
158d7abd MC |
1477 | return 0; |
1478 | ||
298cf9be LB |
1479 | tp->mdio_bus = mdiobus_alloc(); |
1480 | if (tp->mdio_bus == NULL) | |
1481 | return -ENOMEM; | |
158d7abd | 1482 | |
298cf9be LB |
1483 | tp->mdio_bus->name = "tg3 mdio bus"; |
1484 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1485 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1486 | tp->mdio_bus->priv = tp; |
1487 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1488 | tp->mdio_bus->read = &tg3_mdio_read; | |
1489 | tp->mdio_bus->write = &tg3_mdio_write; | |
1490 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1491 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1492 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1493 | |
1494 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1495 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1496 | |
1497 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1498 | * Unfortunately, it does not ensure the PHY is powered up before | |
1499 | * accessing the PHY ID registers. A chip reset is the | |
1500 | * quickest way to bring the device back to an operational state.. | |
1501 | */ | |
1502 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1503 | tg3_bmcr_reset(tp); | |
1504 | ||
298cf9be | 1505 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1506 | if (i) { |
ab96b241 | 1507 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1508 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1509 | return i; |
1510 | } | |
158d7abd | 1511 | |
3f0e3ad7 | 1512 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1513 | |
9c61d6bc | 1514 | if (!phydev || !phydev->drv) { |
ab96b241 | 1515 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1516 | mdiobus_unregister(tp->mdio_bus); |
1517 | mdiobus_free(tp->mdio_bus); | |
1518 | return -ENODEV; | |
1519 | } | |
1520 | ||
1521 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1522 | case PHY_ID_BCM57780: |
321d32a0 | 1523 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1524 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1525 | break; |
6a443a0f MC |
1526 | case PHY_ID_BCM50610: |
1527 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1528 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1529 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1530 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1531 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
63c3a66f | 1532 | if (tg3_flag(tp, RGMII_INBAND_DISABLE)) |
a9daf367 | 1533 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
63c3a66f | 1534 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
a9daf367 | 1535 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; |
63c3a66f | 1536 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 | 1537 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; |
fcb389df | 1538 | /* fallthru */ |
6a443a0f | 1539 | case PHY_ID_RTL8211C: |
fcb389df | 1540 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1541 | break; |
6a443a0f MC |
1542 | case PHY_ID_RTL8201E: |
1543 | case PHY_ID_BCMAC131: | |
a9daf367 | 1544 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1545 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1546 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1547 | break; |
1548 | } | |
1549 | ||
63c3a66f | 1550 | tg3_flag_set(tp, MDIOBUS_INITED); |
9c61d6bc MC |
1551 | |
1552 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1553 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1554 | |
1555 | return 0; | |
158d7abd MC |
1556 | } |
1557 | ||
1558 | static void tg3_mdio_fini(struct tg3 *tp) | |
1559 | { | |
63c3a66f JP |
1560 | if (tg3_flag(tp, MDIOBUS_INITED)) { |
1561 | tg3_flag_clear(tp, MDIOBUS_INITED); | |
298cf9be LB |
1562 | mdiobus_unregister(tp->mdio_bus); |
1563 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1564 | } |
1565 | } | |
1566 | ||
4ba526ce MC |
1567 | /* tp->lock is held. */ |
1568 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1569 | { | |
1570 | u32 val; | |
1571 | ||
1572 | val = tr32(GRC_RX_CPU_EVENT); | |
1573 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1574 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1575 | ||
1576 | tp->last_event_jiffies = jiffies; | |
1577 | } | |
1578 | ||
1579 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1580 | ||
95e2869a MC |
1581 | /* tp->lock is held. */ |
1582 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1583 | { | |
1584 | int i; | |
4ba526ce MC |
1585 | unsigned int delay_cnt; |
1586 | long time_remain; | |
1587 | ||
1588 | /* If enough time has passed, no wait is necessary. */ | |
1589 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1590 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1591 | (long)jiffies; | |
1592 | if (time_remain < 0) | |
1593 | return; | |
1594 | ||
1595 | /* Check if we can shorten the wait time. */ | |
1596 | delay_cnt = jiffies_to_usecs(time_remain); | |
1597 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1598 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1599 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1600 | |
4ba526ce | 1601 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1602 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1603 | break; | |
4ba526ce | 1604 | udelay(8); |
95e2869a MC |
1605 | } |
1606 | } | |
1607 | ||
1608 | /* tp->lock is held. */ | |
b28f389d | 1609 | static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data) |
95e2869a | 1610 | { |
b28f389d | 1611 | u32 reg, val; |
95e2869a MC |
1612 | |
1613 | val = 0; | |
1614 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1615 | val = reg << 16; | |
1616 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1617 | val |= (reg & 0xffff); | |
b28f389d | 1618 | *data++ = val; |
95e2869a MC |
1619 | |
1620 | val = 0; | |
1621 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1622 | val = reg << 16; | |
1623 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1624 | val |= (reg & 0xffff); | |
b28f389d | 1625 | *data++ = val; |
95e2869a MC |
1626 | |
1627 | val = 0; | |
f07e9af3 | 1628 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1629 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1630 | val = reg << 16; | |
1631 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1632 | val |= (reg & 0xffff); | |
1633 | } | |
b28f389d | 1634 | *data++ = val; |
95e2869a MC |
1635 | |
1636 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1637 | val = reg << 16; | |
1638 | else | |
1639 | val = 0; | |
b28f389d MC |
1640 | *data++ = val; |
1641 | } | |
1642 | ||
1643 | /* tp->lock is held. */ | |
1644 | static void tg3_ump_link_report(struct tg3 *tp) | |
1645 | { | |
1646 | u32 data[4]; | |
1647 | ||
1648 | if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) | |
1649 | return; | |
1650 | ||
1651 | tg3_phy_gather_ump_data(tp, data); | |
1652 | ||
1653 | tg3_wait_for_event_ack(tp); | |
1654 | ||
1655 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1656 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1657 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]); | |
1658 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]); | |
1659 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]); | |
1660 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]); | |
95e2869a | 1661 | |
4ba526ce | 1662 | tg3_generate_fw_event(tp); |
95e2869a MC |
1663 | } |
1664 | ||
8d5a89b3 MC |
1665 | /* tp->lock is held. */ |
1666 | static void tg3_stop_fw(struct tg3 *tp) | |
1667 | { | |
1668 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { | |
1669 | /* Wait for RX cpu to ACK the previous event. */ | |
1670 | tg3_wait_for_event_ack(tp); | |
1671 | ||
1672 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
1673 | ||
1674 | tg3_generate_fw_event(tp); | |
1675 | ||
1676 | /* Wait for RX cpu to ACK this event. */ | |
1677 | tg3_wait_for_event_ack(tp); | |
1678 | } | |
1679 | } | |
1680 | ||
fd6d3f0e MC |
1681 | /* tp->lock is held. */ |
1682 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
1683 | { | |
1684 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, | |
1685 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1686 | ||
1687 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
1688 | switch (kind) { | |
1689 | case RESET_KIND_INIT: | |
1690 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1691 | DRV_STATE_START); | |
1692 | break; | |
1693 | ||
1694 | case RESET_KIND_SHUTDOWN: | |
1695 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1696 | DRV_STATE_UNLOAD); | |
1697 | break; | |
1698 | ||
1699 | case RESET_KIND_SUSPEND: | |
1700 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1701 | DRV_STATE_SUSPEND); | |
1702 | break; | |
1703 | ||
1704 | default: | |
1705 | break; | |
1706 | } | |
1707 | } | |
1708 | ||
1709 | if (kind == RESET_KIND_INIT || | |
1710 | kind == RESET_KIND_SUSPEND) | |
1711 | tg3_ape_driver_state_change(tp, kind); | |
1712 | } | |
1713 | ||
1714 | /* tp->lock is held. */ | |
1715 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
1716 | { | |
1717 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
1718 | switch (kind) { | |
1719 | case RESET_KIND_INIT: | |
1720 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1721 | DRV_STATE_START_DONE); | |
1722 | break; | |
1723 | ||
1724 | case RESET_KIND_SHUTDOWN: | |
1725 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1726 | DRV_STATE_UNLOAD_DONE); | |
1727 | break; | |
1728 | ||
1729 | default: | |
1730 | break; | |
1731 | } | |
1732 | } | |
1733 | ||
1734 | if (kind == RESET_KIND_SHUTDOWN) | |
1735 | tg3_ape_driver_state_change(tp, kind); | |
1736 | } | |
1737 | ||
1738 | /* tp->lock is held. */ | |
1739 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
1740 | { | |
1741 | if (tg3_flag(tp, ENABLE_ASF)) { | |
1742 | switch (kind) { | |
1743 | case RESET_KIND_INIT: | |
1744 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1745 | DRV_STATE_START); | |
1746 | break; | |
1747 | ||
1748 | case RESET_KIND_SHUTDOWN: | |
1749 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1750 | DRV_STATE_UNLOAD); | |
1751 | break; | |
1752 | ||
1753 | case RESET_KIND_SUSPEND: | |
1754 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1755 | DRV_STATE_SUSPEND); | |
1756 | break; | |
1757 | ||
1758 | default: | |
1759 | break; | |
1760 | } | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | static int tg3_poll_fw(struct tg3 *tp) | |
1765 | { | |
1766 | int i; | |
1767 | u32 val; | |
1768 | ||
1769 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
1770 | /* Wait up to 20ms for init done. */ | |
1771 | for (i = 0; i < 200; i++) { | |
1772 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) | |
1773 | return 0; | |
1774 | udelay(100); | |
1775 | } | |
1776 | return -ENODEV; | |
1777 | } | |
1778 | ||
1779 | /* Wait for firmware initialization to complete. */ | |
1780 | for (i = 0; i < 100000; i++) { | |
1781 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
1782 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
1783 | break; | |
1784 | udelay(10); | |
1785 | } | |
1786 | ||
1787 | /* Chip might not be fitted with firmware. Some Sun onboard | |
1788 | * parts are configured like that. So don't signal the timeout | |
1789 | * of the above loop as an error, but do report the lack of | |
1790 | * running firmware once. | |
1791 | */ | |
1792 | if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { | |
1793 | tg3_flag_set(tp, NO_FWARE_REPORTED); | |
1794 | ||
1795 | netdev_info(tp->dev, "No firmware running\n"); | |
1796 | } | |
1797 | ||
1798 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
1799 | /* The 57765 A0 needs a little more | |
1800 | * time to do some important work. | |
1801 | */ | |
1802 | mdelay(10); | |
1803 | } | |
1804 | ||
1805 | return 0; | |
1806 | } | |
1807 | ||
95e2869a MC |
1808 | static void tg3_link_report(struct tg3 *tp) |
1809 | { | |
1810 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1811 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1812 | tg3_ump_link_report(tp); |
1813 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1814 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1815 | (tp->link_config.active_speed == SPEED_1000 ? | |
1816 | 1000 : | |
1817 | (tp->link_config.active_speed == SPEED_100 ? | |
1818 | 100 : 10)), | |
1819 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1820 | "full" : "half")); | |
1821 | ||
1822 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1823 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1824 | "on" : "off", | |
1825 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1826 | "on" : "off"); | |
47007831 MC |
1827 | |
1828 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) | |
1829 | netdev_info(tp->dev, "EEE is %s\n", | |
1830 | tp->setlpicnt ? "enabled" : "disabled"); | |
1831 | ||
95e2869a MC |
1832 | tg3_ump_link_report(tp); |
1833 | } | |
1834 | } | |
1835 | ||
95e2869a MC |
1836 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) |
1837 | { | |
1838 | u16 miireg; | |
1839 | ||
e18ce346 | 1840 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1841 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1842 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1843 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1844 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1845 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1846 | else | |
1847 | miireg = 0; | |
1848 | ||
1849 | return miireg; | |
1850 | } | |
1851 | ||
95e2869a MC |
1852 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1853 | { | |
1854 | u8 cap = 0; | |
1855 | ||
f3791cdf MC |
1856 | if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) { |
1857 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1858 | } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) { | |
1859 | if (lcladv & ADVERTISE_1000XPAUSE) | |
1860 | cap = FLOW_CTRL_RX; | |
1861 | if (rmtadv & ADVERTISE_1000XPAUSE) | |
e18ce346 | 1862 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1863 | } |
1864 | ||
1865 | return cap; | |
1866 | } | |
1867 | ||
f51f3562 | 1868 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1869 | { |
b02fd9e3 | 1870 | u8 autoneg; |
f51f3562 | 1871 | u8 flowctrl = 0; |
95e2869a MC |
1872 | u32 old_rx_mode = tp->rx_mode; |
1873 | u32 old_tx_mode = tp->tx_mode; | |
1874 | ||
63c3a66f | 1875 | if (tg3_flag(tp, USE_PHYLIB)) |
3f0e3ad7 | 1876 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1877 | else |
1878 | autoneg = tp->link_config.autoneg; | |
1879 | ||
63c3a66f | 1880 | if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { |
f07e9af3 | 1881 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1882 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1883 | else |
bc02ff95 | 1884 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1885 | } else |
1886 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1887 | |
f51f3562 | 1888 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1889 | |
e18ce346 | 1890 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1891 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1892 | else | |
1893 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1894 | ||
f51f3562 | 1895 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1896 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1897 | |
e18ce346 | 1898 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1899 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1900 | else | |
1901 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1902 | ||
f51f3562 | 1903 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1904 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1905 | } |
1906 | ||
b02fd9e3 MC |
1907 | static void tg3_adjust_link(struct net_device *dev) |
1908 | { | |
1909 | u8 oldflowctrl, linkmesg = 0; | |
1910 | u32 mac_mode, lcl_adv, rmt_adv; | |
1911 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1912 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1913 | |
24bb4fb6 | 1914 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1915 | |
1916 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1917 | MAC_MODE_HALF_DUPLEX); | |
1918 | ||
1919 | oldflowctrl = tp->link_config.active_flowctrl; | |
1920 | ||
1921 | if (phydev->link) { | |
1922 | lcl_adv = 0; | |
1923 | rmt_adv = 0; | |
1924 | ||
1925 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1926 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1927 | else if (phydev->speed == SPEED_1000 || |
1928 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1929 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1930 | else |
1931 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1932 | |
1933 | if (phydev->duplex == DUPLEX_HALF) | |
1934 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1935 | else { | |
f88788f0 | 1936 | lcl_adv = mii_advertise_flowctrl( |
b02fd9e3 MC |
1937 | tp->link_config.flowctrl); |
1938 | ||
1939 | if (phydev->pause) | |
1940 | rmt_adv = LPA_PAUSE_CAP; | |
1941 | if (phydev->asym_pause) | |
1942 | rmt_adv |= LPA_PAUSE_ASYM; | |
1943 | } | |
1944 | ||
1945 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1946 | } else | |
1947 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1948 | ||
1949 | if (mac_mode != tp->mac_mode) { | |
1950 | tp->mac_mode = mac_mode; | |
1951 | tw32_f(MAC_MODE, tp->mac_mode); | |
1952 | udelay(40); | |
1953 | } | |
1954 | ||
fcb389df MC |
1955 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1956 | if (phydev->speed == SPEED_10) | |
1957 | tw32(MAC_MI_STAT, | |
1958 | MAC_MI_STAT_10MBPS_MODE | | |
1959 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1960 | else | |
1961 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1962 | } | |
1963 | ||
b02fd9e3 MC |
1964 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1965 | tw32(MAC_TX_LENGTHS, | |
1966 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1967 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1968 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1969 | else | |
1970 | tw32(MAC_TX_LENGTHS, | |
1971 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1972 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1973 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1974 | ||
34655ad6 | 1975 | if (phydev->link != tp->old_link || |
b02fd9e3 MC |
1976 | phydev->speed != tp->link_config.active_speed || |
1977 | phydev->duplex != tp->link_config.active_duplex || | |
1978 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1979 | linkmesg = 1; |
b02fd9e3 | 1980 | |
34655ad6 | 1981 | tp->old_link = phydev->link; |
b02fd9e3 MC |
1982 | tp->link_config.active_speed = phydev->speed; |
1983 | tp->link_config.active_duplex = phydev->duplex; | |
1984 | ||
24bb4fb6 | 1985 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1986 | |
1987 | if (linkmesg) | |
1988 | tg3_link_report(tp); | |
1989 | } | |
1990 | ||
1991 | static int tg3_phy_init(struct tg3 *tp) | |
1992 | { | |
1993 | struct phy_device *phydev; | |
1994 | ||
f07e9af3 | 1995 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1996 | return 0; |
1997 | ||
1998 | /* Bring the PHY back to a known state. */ | |
1999 | tg3_bmcr_reset(tp); | |
2000 | ||
3f0e3ad7 | 2001 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
2002 | |
2003 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 2004 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 2005 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 2006 | if (IS_ERR(phydev)) { |
ab96b241 | 2007 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
2008 | return PTR_ERR(phydev); |
2009 | } | |
2010 | ||
b02fd9e3 | 2011 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
2012 | switch (phydev->interface) { |
2013 | case PHY_INTERFACE_MODE_GMII: | |
2014 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 2015 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
2016 | phydev->supported &= (PHY_GBIT_FEATURES | |
2017 | SUPPORTED_Pause | | |
2018 | SUPPORTED_Asym_Pause); | |
2019 | break; | |
2020 | } | |
2021 | /* fallthru */ | |
9c61d6bc MC |
2022 | case PHY_INTERFACE_MODE_MII: |
2023 | phydev->supported &= (PHY_BASIC_FEATURES | | |
2024 | SUPPORTED_Pause | | |
2025 | SUPPORTED_Asym_Pause); | |
2026 | break; | |
2027 | default: | |
3f0e3ad7 | 2028 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
2029 | return -EINVAL; |
2030 | } | |
2031 | ||
f07e9af3 | 2032 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
2033 | |
2034 | phydev->advertising = phydev->supported; | |
2035 | ||
b02fd9e3 MC |
2036 | return 0; |
2037 | } | |
2038 | ||
2039 | static void tg3_phy_start(struct tg3 *tp) | |
2040 | { | |
2041 | struct phy_device *phydev; | |
2042 | ||
f07e9af3 | 2043 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
2044 | return; |
2045 | ||
3f0e3ad7 | 2046 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 2047 | |
80096068 MC |
2048 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
2049 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
c6700ce2 MC |
2050 | phydev->speed = tp->link_config.speed; |
2051 | phydev->duplex = tp->link_config.duplex; | |
2052 | phydev->autoneg = tp->link_config.autoneg; | |
2053 | phydev->advertising = tp->link_config.advertising; | |
b02fd9e3 MC |
2054 | } |
2055 | ||
2056 | phy_start(phydev); | |
2057 | ||
2058 | phy_start_aneg(phydev); | |
2059 | } | |
2060 | ||
2061 | static void tg3_phy_stop(struct tg3 *tp) | |
2062 | { | |
f07e9af3 | 2063 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
2064 | return; |
2065 | ||
3f0e3ad7 | 2066 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
2067 | } |
2068 | ||
2069 | static void tg3_phy_fini(struct tg3 *tp) | |
2070 | { | |
f07e9af3 | 2071 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 2072 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 2073 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
2074 | } |
2075 | } | |
2076 | ||
941ec90f MC |
2077 | static int tg3_phy_set_extloopbk(struct tg3 *tp) |
2078 | { | |
2079 | int err; | |
2080 | u32 val; | |
2081 | ||
2082 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
2083 | return 0; | |
2084 | ||
2085 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { | |
2086 | /* Cannot do read-modify-write on 5401 */ | |
2087 | err = tg3_phy_auxctl_write(tp, | |
2088 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, | |
2089 | MII_TG3_AUXCTL_ACTL_EXTLOOPBK | | |
2090 | 0x4c20); | |
2091 | goto done; | |
2092 | } | |
2093 | ||
2094 | err = tg3_phy_auxctl_read(tp, | |
2095 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2096 | if (err) | |
2097 | return err; | |
2098 | ||
2099 | val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK; | |
2100 | err = tg3_phy_auxctl_write(tp, | |
2101 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val); | |
2102 | ||
2103 | done: | |
2104 | return err; | |
2105 | } | |
2106 | ||
7f97a4bd MC |
2107 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
2108 | { | |
2109 | u32 phytest; | |
2110 | ||
2111 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2112 | u32 phy; | |
2113 | ||
2114 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2115 | phytest | MII_TG3_FET_SHADOW_EN); | |
2116 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
2117 | if (enable) | |
2118 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
2119 | else | |
2120 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
2121 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
2122 | } | |
2123 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2124 | } | |
2125 | } | |
2126 | ||
6833c043 MC |
2127 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
2128 | { | |
2129 | u32 reg; | |
2130 | ||
63c3a66f JP |
2131 | if (!tg3_flag(tp, 5705_PLUS) || |
2132 | (tg3_flag(tp, 5717_PLUS) && | |
f07e9af3 | 2133 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
2134 | return; |
2135 | ||
f07e9af3 | 2136 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
2137 | tg3_phy_fet_toggle_apd(tp, enable); |
2138 | return; | |
2139 | } | |
2140 | ||
6833c043 MC |
2141 | reg = MII_TG3_MISC_SHDW_WREN | |
2142 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
2143 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
2144 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
2145 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
2146 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
2147 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
2148 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
2149 | ||
2150 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
2151 | ||
2152 | ||
2153 | reg = MII_TG3_MISC_SHDW_WREN | | |
2154 | MII_TG3_MISC_SHDW_APD_SEL | | |
2155 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
2156 | if (enable) | |
2157 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
2158 | ||
2159 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
2160 | } | |
2161 | ||
9ef8ca99 MC |
2162 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
2163 | { | |
2164 | u32 phy; | |
2165 | ||
63c3a66f | 2166 | if (!tg3_flag(tp, 5705_PLUS) || |
f07e9af3 | 2167 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
2168 | return; |
2169 | ||
f07e9af3 | 2170 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
2171 | u32 ephy; |
2172 | ||
535ef6e1 MC |
2173 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
2174 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
2175 | ||
2176 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2177 | ephy | MII_TG3_FET_SHADOW_EN); | |
2178 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 2179 | if (enable) |
535ef6e1 | 2180 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 2181 | else |
535ef6e1 MC |
2182 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
2183 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 2184 | } |
535ef6e1 | 2185 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
2186 | } |
2187 | } else { | |
15ee95c3 MC |
2188 | int ret; |
2189 | ||
2190 | ret = tg3_phy_auxctl_read(tp, | |
2191 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); | |
2192 | if (!ret) { | |
9ef8ca99 MC |
2193 | if (enable) |
2194 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
2195 | else | |
2196 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
b4bd2929 MC |
2197 | tg3_phy_auxctl_write(tp, |
2198 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); | |
9ef8ca99 MC |
2199 | } |
2200 | } | |
2201 | } | |
2202 | ||
1da177e4 LT |
2203 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
2204 | { | |
15ee95c3 | 2205 | int ret; |
1da177e4 LT |
2206 | u32 val; |
2207 | ||
f07e9af3 | 2208 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
2209 | return; |
2210 | ||
15ee95c3 MC |
2211 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); |
2212 | if (!ret) | |
b4bd2929 MC |
2213 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, |
2214 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); | |
1da177e4 LT |
2215 | } |
2216 | ||
b2a5c19c MC |
2217 | static void tg3_phy_apply_otp(struct tg3 *tp) |
2218 | { | |
2219 | u32 otp, phy; | |
2220 | ||
2221 | if (!tp->phy_otp) | |
2222 | return; | |
2223 | ||
2224 | otp = tp->phy_otp; | |
2225 | ||
1d36ba45 MC |
2226 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) |
2227 | return; | |
b2a5c19c MC |
2228 | |
2229 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
2230 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
2231 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
2232 | ||
2233 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
2234 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
2235 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
2236 | ||
2237 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
2238 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
2239 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
2240 | ||
2241 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
2242 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
2243 | ||
2244 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
2245 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
2246 | ||
2247 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
2248 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
2249 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
2250 | ||
1d36ba45 | 2251 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
b2a5c19c MC |
2252 | } |
2253 | ||
52b02d04 MC |
2254 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
2255 | { | |
2256 | u32 val; | |
2257 | ||
2258 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
2259 | return; | |
2260 | ||
2261 | tp->setlpicnt = 0; | |
2262 | ||
2263 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
2264 | current_link_up == 1 && | |
a6b68dab MC |
2265 | tp->link_config.active_duplex == DUPLEX_FULL && |
2266 | (tp->link_config.active_speed == SPEED_100 || | |
2267 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
2268 | u32 eeectl; |
2269 | ||
2270 | if (tp->link_config.active_speed == SPEED_1000) | |
2271 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
2272 | else | |
2273 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
2274 | ||
2275 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
2276 | ||
3110f5f5 MC |
2277 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
2278 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 2279 | |
b0c5943f MC |
2280 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || |
2281 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) | |
52b02d04 MC |
2282 | tp->setlpicnt = 2; |
2283 | } | |
2284 | ||
2285 | if (!tp->setlpicnt) { | |
b715ce94 MC |
2286 | if (current_link_up == 1 && |
2287 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
2288 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | |
2289 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2290 | } | |
2291 | ||
52b02d04 MC |
2292 | val = tr32(TG3_CPMU_EEE_MODE); |
2293 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
2294 | } | |
2295 | } | |
2296 | ||
b0c5943f MC |
2297 | static void tg3_phy_eee_enable(struct tg3 *tp) |
2298 | { | |
2299 | u32 val; | |
2300 | ||
2301 | if (tp->link_config.active_speed == SPEED_1000 && | |
2302 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2303 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
55086ad9 | 2304 | tg3_flag(tp, 57765_CLASS)) && |
b0c5943f | 2305 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
b715ce94 MC |
2306 | val = MII_TG3_DSP_TAP26_ALNOKO | |
2307 | MII_TG3_DSP_TAP26_RMRXSTO; | |
2308 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
b0c5943f MC |
2309 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
2310 | } | |
2311 | ||
2312 | val = tr32(TG3_CPMU_EEE_MODE); | |
2313 | tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
2314 | } | |
2315 | ||
1da177e4 LT |
2316 | static int tg3_wait_macro_done(struct tg3 *tp) |
2317 | { | |
2318 | int limit = 100; | |
2319 | ||
2320 | while (limit--) { | |
2321 | u32 tmp32; | |
2322 | ||
f08aa1a8 | 2323 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
2324 | if ((tmp32 & 0x1000) == 0) |
2325 | break; | |
2326 | } | |
2327 | } | |
d4675b52 | 2328 | if (limit < 0) |
1da177e4 LT |
2329 | return -EBUSY; |
2330 | ||
2331 | return 0; | |
2332 | } | |
2333 | ||
2334 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
2335 | { | |
2336 | static const u32 test_pat[4][6] = { | |
2337 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
2338 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
2339 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
2340 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
2341 | }; | |
2342 | int chan; | |
2343 | ||
2344 | for (chan = 0; chan < 4; chan++) { | |
2345 | int i; | |
2346 | ||
2347 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2348 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2349 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
2350 | |
2351 | for (i = 0; i < 6; i++) | |
2352 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
2353 | test_pat[chan][i]); | |
2354 | ||
f08aa1a8 | 2355 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
2356 | if (tg3_wait_macro_done(tp)) { |
2357 | *resetp = 1; | |
2358 | return -EBUSY; | |
2359 | } | |
2360 | ||
2361 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2362 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2363 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
2364 | if (tg3_wait_macro_done(tp)) { |
2365 | *resetp = 1; | |
2366 | return -EBUSY; | |
2367 | } | |
2368 | ||
f08aa1a8 | 2369 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
2370 | if (tg3_wait_macro_done(tp)) { |
2371 | *resetp = 1; | |
2372 | return -EBUSY; | |
2373 | } | |
2374 | ||
2375 | for (i = 0; i < 6; i += 2) { | |
2376 | u32 low, high; | |
2377 | ||
2378 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
2379 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
2380 | tg3_wait_macro_done(tp)) { | |
2381 | *resetp = 1; | |
2382 | return -EBUSY; | |
2383 | } | |
2384 | low &= 0x7fff; | |
2385 | high &= 0x000f; | |
2386 | if (low != test_pat[chan][i] || | |
2387 | high != test_pat[chan][i+1]) { | |
2388 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
2389 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
2390 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
2391 | ||
2392 | return -EBUSY; | |
2393 | } | |
2394 | } | |
2395 | } | |
2396 | ||
2397 | return 0; | |
2398 | } | |
2399 | ||
2400 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
2401 | { | |
2402 | int chan; | |
2403 | ||
2404 | for (chan = 0; chan < 4; chan++) { | |
2405 | int i; | |
2406 | ||
2407 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2408 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2409 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
2410 | for (i = 0; i < 6; i++) |
2411 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 2412 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
2413 | if (tg3_wait_macro_done(tp)) |
2414 | return -EBUSY; | |
2415 | } | |
2416 | ||
2417 | return 0; | |
2418 | } | |
2419 | ||
2420 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
2421 | { | |
2422 | u32 reg32, phy9_orig; | |
2423 | int retries, do_phy_reset, err; | |
2424 | ||
2425 | retries = 10; | |
2426 | do_phy_reset = 1; | |
2427 | do { | |
2428 | if (do_phy_reset) { | |
2429 | err = tg3_bmcr_reset(tp); | |
2430 | if (err) | |
2431 | return err; | |
2432 | do_phy_reset = 0; | |
2433 | } | |
2434 | ||
2435 | /* Disable transmitter and interrupt. */ | |
2436 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
2437 | continue; | |
2438 | ||
2439 | reg32 |= 0x3000; | |
2440 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2441 | ||
2442 | /* Set full-duplex, 1000 mbps. */ | |
2443 | tg3_writephy(tp, MII_BMCR, | |
221c5637 | 2444 | BMCR_FULLDPLX | BMCR_SPEED1000); |
1da177e4 LT |
2445 | |
2446 | /* Set to master mode. */ | |
221c5637 | 2447 | if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) |
1da177e4 LT |
2448 | continue; |
2449 | ||
221c5637 MC |
2450 | tg3_writephy(tp, MII_CTRL1000, |
2451 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
1da177e4 | 2452 | |
1d36ba45 MC |
2453 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
2454 | if (err) | |
2455 | return err; | |
1da177e4 LT |
2456 | |
2457 | /* Block the PHY control access. */ | |
6ee7c0a0 | 2458 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
2459 | |
2460 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
2461 | if (!err) | |
2462 | break; | |
2463 | } while (--retries); | |
2464 | ||
2465 | err = tg3_phy_reset_chanpat(tp); | |
2466 | if (err) | |
2467 | return err; | |
2468 | ||
6ee7c0a0 | 2469 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
2470 | |
2471 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 2472 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 | 2473 | |
1d36ba45 | 2474 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2475 | |
221c5637 | 2476 | tg3_writephy(tp, MII_CTRL1000, phy9_orig); |
1da177e4 LT |
2477 | |
2478 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
2479 | reg32 &= ~0x3000; | |
2480 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2481 | } else if (!err) | |
2482 | err = -EBUSY; | |
2483 | ||
2484 | return err; | |
2485 | } | |
2486 | ||
f4a46d1f NNS |
2487 | static void tg3_carrier_on(struct tg3 *tp) |
2488 | { | |
2489 | netif_carrier_on(tp->dev); | |
2490 | tp->link_up = true; | |
2491 | } | |
2492 | ||
2493 | static void tg3_carrier_off(struct tg3 *tp) | |
2494 | { | |
2495 | netif_carrier_off(tp->dev); | |
2496 | tp->link_up = false; | |
2497 | } | |
2498 | ||
1da177e4 LT |
2499 | /* This will reset the tigon3 PHY if there is no valid |
2500 | * link unless the FORCE argument is non-zero. | |
2501 | */ | |
2502 | static int tg3_phy_reset(struct tg3 *tp) | |
2503 | { | |
f833c4c1 | 2504 | u32 val, cpmuctrl; |
1da177e4 LT |
2505 | int err; |
2506 | ||
60189ddf | 2507 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2508 | val = tr32(GRC_MISC_CFG); |
2509 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
2510 | udelay(40); | |
2511 | } | |
f833c4c1 MC |
2512 | err = tg3_readphy(tp, MII_BMSR, &val); |
2513 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
2514 | if (err != 0) |
2515 | return -EBUSY; | |
2516 | ||
f4a46d1f NNS |
2517 | if (netif_running(tp->dev) && tp->link_up) { |
2518 | tg3_carrier_off(tp); | |
c8e1e82b MC |
2519 | tg3_link_report(tp); |
2520 | } | |
2521 | ||
1da177e4 LT |
2522 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2523 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2524 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2525 | err = tg3_phy_reset_5703_4_5(tp); | |
2526 | if (err) | |
2527 | return err; | |
2528 | goto out; | |
2529 | } | |
2530 | ||
b2a5c19c MC |
2531 | cpmuctrl = 0; |
2532 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2533 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2534 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2535 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2536 | tw32(TG3_CPMU_CTRL, | |
2537 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2538 | } | |
2539 | ||
1da177e4 LT |
2540 | err = tg3_bmcr_reset(tp); |
2541 | if (err) | |
2542 | return err; | |
2543 | ||
b2a5c19c | 2544 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2545 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2546 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2547 | |
2548 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2549 | } | |
2550 | ||
bcb37f6c MC |
2551 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2552 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2553 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2554 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2555 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2556 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2557 | udelay(40); | |
2558 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2559 | } | |
2560 | } | |
2561 | ||
63c3a66f | 2562 | if (tg3_flag(tp, 5717_PLUS) && |
f07e9af3 | 2563 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2564 | return 0; |
2565 | ||
b2a5c19c MC |
2566 | tg3_phy_apply_otp(tp); |
2567 | ||
f07e9af3 | 2568 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2569 | tg3_phy_toggle_apd(tp, true); |
2570 | else | |
2571 | tg3_phy_toggle_apd(tp, false); | |
2572 | ||
1da177e4 | 2573 | out: |
1d36ba45 MC |
2574 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && |
2575 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
6ee7c0a0 MC |
2576 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2577 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1d36ba45 | 2578 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2579 | } |
1d36ba45 | 2580 | |
f07e9af3 | 2581 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2582 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2583 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2584 | } |
1d36ba45 | 2585 | |
f07e9af3 | 2586 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1d36ba45 MC |
2587 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2588 | tg3_phydsp_write(tp, 0x000a, 0x310b); | |
2589 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2590 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
2591 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2592 | } | |
f07e9af3 | 2593 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
1d36ba45 MC |
2594 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2595 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
2596 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { | |
2597 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2598 | tg3_writephy(tp, MII_TG3_TEST1, | |
2599 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2600 | } else | |
2601 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
2602 | ||
2603 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2604 | } | |
c424cb24 | 2605 | } |
1d36ba45 | 2606 | |
1da177e4 LT |
2607 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2608 | /* support jumbo frames */ | |
79eb6904 | 2609 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 | 2610 | /* Cannot do read-modify-write on 5401 */ |
b4bd2929 | 2611 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
63c3a66f | 2612 | } else if (tg3_flag(tp, JUMBO_CAPABLE)) { |
1da177e4 | 2613 | /* Set bit 14 with read-modify-write to preserve other bits */ |
15ee95c3 MC |
2614 | err = tg3_phy_auxctl_read(tp, |
2615 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2616 | if (!err) | |
b4bd2929 MC |
2617 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
2618 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); | |
1da177e4 LT |
2619 | } |
2620 | ||
2621 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2622 | * jumbo frames transmission. | |
2623 | */ | |
63c3a66f | 2624 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
f833c4c1 | 2625 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2626 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2627 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2628 | } |
2629 | ||
715116a1 | 2630 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2631 | /* adjust output voltage */ |
535ef6e1 | 2632 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2633 | } |
2634 | ||
9ef8ca99 | 2635 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2636 | tg3_phy_set_wirespeed(tp); |
2637 | return 0; | |
2638 | } | |
2639 | ||
3a1e19d3 MC |
2640 | #define TG3_GPIO_MSG_DRVR_PRES 0x00000001 |
2641 | #define TG3_GPIO_MSG_NEED_VAUX 0x00000002 | |
2642 | #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \ | |
2643 | TG3_GPIO_MSG_NEED_VAUX) | |
2644 | #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \ | |
2645 | ((TG3_GPIO_MSG_DRVR_PRES << 0) | \ | |
2646 | (TG3_GPIO_MSG_DRVR_PRES << 4) | \ | |
2647 | (TG3_GPIO_MSG_DRVR_PRES << 8) | \ | |
2648 | (TG3_GPIO_MSG_DRVR_PRES << 12)) | |
2649 | ||
2650 | #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \ | |
2651 | ((TG3_GPIO_MSG_NEED_VAUX << 0) | \ | |
2652 | (TG3_GPIO_MSG_NEED_VAUX << 4) | \ | |
2653 | (TG3_GPIO_MSG_NEED_VAUX << 8) | \ | |
2654 | (TG3_GPIO_MSG_NEED_VAUX << 12)) | |
2655 | ||
2656 | static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) | |
2657 | { | |
2658 | u32 status, shift; | |
2659 | ||
2660 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2661 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2662 | status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); | |
2663 | else | |
2664 | status = tr32(TG3_CPMU_DRV_STATUS); | |
2665 | ||
2666 | shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; | |
2667 | status &= ~(TG3_GPIO_MSG_MASK << shift); | |
2668 | status |= (newstat << shift); | |
2669 | ||
2670 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2671 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2672 | tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); | |
2673 | else | |
2674 | tw32(TG3_CPMU_DRV_STATUS, status); | |
2675 | ||
2676 | return status >> TG3_APE_GPIO_MSG_SHIFT; | |
2677 | } | |
2678 | ||
520b2756 MC |
2679 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) |
2680 | { | |
2681 | if (!tg3_flag(tp, IS_NIC)) | |
2682 | return 0; | |
2683 | ||
3a1e19d3 MC |
2684 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2685 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2686 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
2687 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2688 | return -EIO; | |
520b2756 | 2689 | |
3a1e19d3 MC |
2690 | tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); |
2691 | ||
2692 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2693 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2694 | ||
2695 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); | |
2696 | } else { | |
2697 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2698 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2699 | } | |
6f5c8f83 | 2700 | |
520b2756 MC |
2701 | return 0; |
2702 | } | |
2703 | ||
2704 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) | |
2705 | { | |
2706 | u32 grc_local_ctrl; | |
2707 | ||
2708 | if (!tg3_flag(tp, IS_NIC) || | |
2709 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2710 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) | |
2711 | return; | |
2712 | ||
2713 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; | |
2714 | ||
2715 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2716 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2717 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2718 | ||
2719 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2720 | grc_local_ctrl, | |
2721 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2722 | ||
2723 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2724 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2725 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2726 | } | |
2727 | ||
2728 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) | |
2729 | { | |
2730 | if (!tg3_flag(tp, IS_NIC)) | |
2731 | return; | |
2732 | ||
2733 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2734 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2735 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2736 | (GRC_LCLCTRL_GPIO_OE0 | | |
2737 | GRC_LCLCTRL_GPIO_OE1 | | |
2738 | GRC_LCLCTRL_GPIO_OE2 | | |
2739 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2740 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2741 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2742 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
2743 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
2744 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
2745 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2746 | GRC_LCLCTRL_GPIO_OE1 | | |
2747 | GRC_LCLCTRL_GPIO_OE2 | | |
2748 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2749 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2750 | tp->grc_local_ctrl; | |
2751 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2752 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2753 | ||
2754 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2755 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2756 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2757 | ||
2758 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2759 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2760 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2761 | } else { | |
2762 | u32 no_gpio2; | |
2763 | u32 grc_local_ctrl = 0; | |
2764 | ||
2765 | /* Workaround to prevent overdrawing Amps. */ | |
2766 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
2767 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
2768 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2769 | grc_local_ctrl, | |
2770 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2771 | } | |
2772 | ||
2773 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
2774 | no_gpio2 = tp->nic_sram_data_cfg & | |
2775 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2776 | ||
2777 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
2778 | GRC_LCLCTRL_GPIO_OE1 | | |
2779 | GRC_LCLCTRL_GPIO_OE2 | | |
2780 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2781 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2782 | if (no_gpio2) { | |
2783 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2784 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2785 | } | |
2786 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2787 | tp->grc_local_ctrl | grc_local_ctrl, | |
2788 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2789 | ||
2790 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2791 | ||
2792 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2793 | tp->grc_local_ctrl | grc_local_ctrl, | |
2794 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2795 | ||
2796 | if (!no_gpio2) { | |
2797 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2798 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2799 | tp->grc_local_ctrl | grc_local_ctrl, | |
2800 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2801 | } | |
2802 | } | |
3a1e19d3 MC |
2803 | } |
2804 | ||
cd0d7228 | 2805 | static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) |
3a1e19d3 MC |
2806 | { |
2807 | u32 msg = 0; | |
2808 | ||
2809 | /* Serialize power state transitions */ | |
2810 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2811 | return; | |
2812 | ||
cd0d7228 | 2813 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) |
3a1e19d3 MC |
2814 | msg = TG3_GPIO_MSG_NEED_VAUX; |
2815 | ||
2816 | msg = tg3_set_function_status(tp, msg); | |
2817 | ||
2818 | if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK) | |
2819 | goto done; | |
6f5c8f83 | 2820 | |
3a1e19d3 MC |
2821 | if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK) |
2822 | tg3_pwrsrc_switch_to_vaux(tp); | |
2823 | else | |
2824 | tg3_pwrsrc_die_with_vmain(tp); | |
2825 | ||
2826 | done: | |
6f5c8f83 | 2827 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); |
520b2756 MC |
2828 | } |
2829 | ||
cd0d7228 | 2830 | static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) |
1da177e4 | 2831 | { |
683644b7 | 2832 | bool need_vaux = false; |
1da177e4 | 2833 | |
334355aa | 2834 | /* The GPIOs do something completely different on 57765. */ |
55086ad9 | 2835 | if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) |
1da177e4 LT |
2836 | return; |
2837 | ||
3a1e19d3 MC |
2838 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2839 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2840 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
cd0d7228 MC |
2841 | tg3_frob_aux_power_5717(tp, include_wol ? |
2842 | tg3_flag(tp, WOL_ENABLE) != 0 : 0); | |
3a1e19d3 MC |
2843 | return; |
2844 | } | |
2845 | ||
2846 | if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { | |
8c2dc7e1 MC |
2847 | struct net_device *dev_peer; |
2848 | ||
2849 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2850 | |
bc1c7567 | 2851 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2852 | if (dev_peer) { |
2853 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2854 | ||
63c3a66f | 2855 | if (tg3_flag(tp_peer, INIT_COMPLETE)) |
683644b7 MC |
2856 | return; |
2857 | ||
cd0d7228 | 2858 | if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) || |
63c3a66f | 2859 | tg3_flag(tp_peer, ENABLE_ASF)) |
683644b7 MC |
2860 | need_vaux = true; |
2861 | } | |
1da177e4 LT |
2862 | } |
2863 | ||
cd0d7228 MC |
2864 | if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || |
2865 | tg3_flag(tp, ENABLE_ASF)) | |
683644b7 MC |
2866 | need_vaux = true; |
2867 | ||
520b2756 MC |
2868 | if (need_vaux) |
2869 | tg3_pwrsrc_switch_to_vaux(tp); | |
2870 | else | |
2871 | tg3_pwrsrc_die_with_vmain(tp); | |
1da177e4 LT |
2872 | } |
2873 | ||
e8f3f6ca MC |
2874 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2875 | { | |
2876 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2877 | return 1; | |
79eb6904 | 2878 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2879 | if (speed != SPEED_10) |
2880 | return 1; | |
2881 | } else if (speed == SPEED_10) | |
2882 | return 1; | |
2883 | ||
2884 | return 0; | |
2885 | } | |
2886 | ||
0a459aac | 2887 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2888 | { |
ce057f01 MC |
2889 | u32 val; |
2890 | ||
f07e9af3 | 2891 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2892 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2893 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2894 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2895 | ||
2896 | sg_dig_ctrl |= | |
2897 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2898 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2899 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2900 | } | |
3f7045c1 | 2901 | return; |
5129724a | 2902 | } |
3f7045c1 | 2903 | |
60189ddf | 2904 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2905 | tg3_bmcr_reset(tp); |
2906 | val = tr32(GRC_MISC_CFG); | |
2907 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2908 | udelay(40); | |
2909 | return; | |
f07e9af3 | 2910 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2911 | u32 phytest; |
2912 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2913 | u32 phy; | |
2914 | ||
2915 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2916 | tg3_writephy(tp, MII_BMCR, | |
2917 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2918 | ||
2919 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2920 | phytest | MII_TG3_FET_SHADOW_EN); | |
2921 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2922 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2923 | tg3_writephy(tp, | |
2924 | MII_TG3_FET_SHDW_AUXMODE4, | |
2925 | phy); | |
2926 | } | |
2927 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2928 | } | |
2929 | return; | |
0a459aac | 2930 | } else if (do_low_power) { |
715116a1 MC |
2931 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2932 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac | 2933 | |
b4bd2929 MC |
2934 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
2935 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2936 | MII_TG3_AUXCTL_PCTL_VREG_11V; | |
2937 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); | |
715116a1 | 2938 | } |
3f7045c1 | 2939 | |
15c3b696 MC |
2940 | /* The PHY should not be powered down on some chips because |
2941 | * of bugs. | |
2942 | */ | |
2943 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2944 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2945 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
085f1afc MC |
2946 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) || |
2947 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | |
2948 | !tp->pci_fn)) | |
15c3b696 | 2949 | return; |
ce057f01 | 2950 | |
bcb37f6c MC |
2951 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2952 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2953 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2954 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2955 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2956 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2957 | } | |
2958 | ||
15c3b696 MC |
2959 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2960 | } | |
2961 | ||
ffbcfed4 MC |
2962 | /* tp->lock is held. */ |
2963 | static int tg3_nvram_lock(struct tg3 *tp) | |
2964 | { | |
63c3a66f | 2965 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2966 | int i; |
2967 | ||
2968 | if (tp->nvram_lock_cnt == 0) { | |
2969 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2970 | for (i = 0; i < 8000; i++) { | |
2971 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2972 | break; | |
2973 | udelay(20); | |
2974 | } | |
2975 | if (i == 8000) { | |
2976 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2977 | return -ENODEV; | |
2978 | } | |
2979 | } | |
2980 | tp->nvram_lock_cnt++; | |
2981 | } | |
2982 | return 0; | |
2983 | } | |
2984 | ||
2985 | /* tp->lock is held. */ | |
2986 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2987 | { | |
63c3a66f | 2988 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2989 | if (tp->nvram_lock_cnt > 0) |
2990 | tp->nvram_lock_cnt--; | |
2991 | if (tp->nvram_lock_cnt == 0) | |
2992 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2993 | } | |
2994 | } | |
2995 | ||
2996 | /* tp->lock is held. */ | |
2997 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2998 | { | |
63c3a66f | 2999 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
3000 | u32 nvaccess = tr32(NVRAM_ACCESS); |
3001 | ||
3002 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
3003 | } | |
3004 | } | |
3005 | ||
3006 | /* tp->lock is held. */ | |
3007 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
3008 | { | |
63c3a66f | 3009 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
3010 | u32 nvaccess = tr32(NVRAM_ACCESS); |
3011 | ||
3012 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
3013 | } | |
3014 | } | |
3015 | ||
3016 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
3017 | u32 offset, u32 *val) | |
3018 | { | |
3019 | u32 tmp; | |
3020 | int i; | |
3021 | ||
3022 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
3023 | return -EINVAL; | |
3024 | ||
3025 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
3026 | EEPROM_ADDR_DEVID_MASK | | |
3027 | EEPROM_ADDR_READ); | |
3028 | tw32(GRC_EEPROM_ADDR, | |
3029 | tmp | | |
3030 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
3031 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
3032 | EEPROM_ADDR_ADDR_MASK) | | |
3033 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
3034 | ||
3035 | for (i = 0; i < 1000; i++) { | |
3036 | tmp = tr32(GRC_EEPROM_ADDR); | |
3037 | ||
3038 | if (tmp & EEPROM_ADDR_COMPLETE) | |
3039 | break; | |
3040 | msleep(1); | |
3041 | } | |
3042 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
3043 | return -EBUSY; | |
3044 | ||
62cedd11 MC |
3045 | tmp = tr32(GRC_EEPROM_DATA); |
3046 | ||
3047 | /* | |
3048 | * The data will always be opposite the native endian | |
3049 | * format. Perform a blind byteswap to compensate. | |
3050 | */ | |
3051 | *val = swab32(tmp); | |
3052 | ||
ffbcfed4 MC |
3053 | return 0; |
3054 | } | |
3055 | ||
3056 | #define NVRAM_CMD_TIMEOUT 10000 | |
3057 | ||
3058 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
3059 | { | |
3060 | int i; | |
3061 | ||
3062 | tw32(NVRAM_CMD, nvram_cmd); | |
3063 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
3064 | udelay(10); | |
3065 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
3066 | udelay(10); | |
3067 | break; | |
3068 | } | |
3069 | } | |
3070 | ||
3071 | if (i == NVRAM_CMD_TIMEOUT) | |
3072 | return -EBUSY; | |
3073 | ||
3074 | return 0; | |
3075 | } | |
3076 | ||
3077 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
3078 | { | |
63c3a66f JP |
3079 | if (tg3_flag(tp, NVRAM) && |
3080 | tg3_flag(tp, NVRAM_BUFFERED) && | |
3081 | tg3_flag(tp, FLASH) && | |
3082 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
3083 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
3084 | ||
3085 | addr = ((addr / tp->nvram_pagesize) << | |
3086 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
3087 | (addr % tp->nvram_pagesize); | |
3088 | ||
3089 | return addr; | |
3090 | } | |
3091 | ||
3092 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
3093 | { | |
63c3a66f JP |
3094 | if (tg3_flag(tp, NVRAM) && |
3095 | tg3_flag(tp, NVRAM_BUFFERED) && | |
3096 | tg3_flag(tp, FLASH) && | |
3097 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
3098 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
3099 | ||
3100 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
3101 | tp->nvram_pagesize) + | |
3102 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
3103 | ||
3104 | return addr; | |
3105 | } | |
3106 | ||
e4f34110 MC |
3107 | /* NOTE: Data read in from NVRAM is byteswapped according to |
3108 | * the byteswapping settings for all other register accesses. | |
3109 | * tg3 devices are BE devices, so on a BE machine, the data | |
3110 | * returned will be exactly as it is seen in NVRAM. On a LE | |
3111 | * machine, the 32-bit value will be byteswapped. | |
3112 | */ | |
ffbcfed4 MC |
3113 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
3114 | { | |
3115 | int ret; | |
3116 | ||
63c3a66f | 3117 | if (!tg3_flag(tp, NVRAM)) |
ffbcfed4 MC |
3118 | return tg3_nvram_read_using_eeprom(tp, offset, val); |
3119 | ||
3120 | offset = tg3_nvram_phys_addr(tp, offset); | |
3121 | ||
3122 | if (offset > NVRAM_ADDR_MSK) | |
3123 | return -EINVAL; | |
3124 | ||
3125 | ret = tg3_nvram_lock(tp); | |
3126 | if (ret) | |
3127 | return ret; | |
3128 | ||
3129 | tg3_enable_nvram_access(tp); | |
3130 | ||
3131 | tw32(NVRAM_ADDR, offset); | |
3132 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
3133 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
3134 | ||
3135 | if (ret == 0) | |
e4f34110 | 3136 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
3137 | |
3138 | tg3_disable_nvram_access(tp); | |
3139 | ||
3140 | tg3_nvram_unlock(tp); | |
3141 | ||
3142 | return ret; | |
3143 | } | |
3144 | ||
a9dc529d MC |
3145 | /* Ensures NVRAM data is in bytestream format. */ |
3146 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
3147 | { |
3148 | u32 v; | |
a9dc529d | 3149 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 3150 | if (!res) |
a9dc529d | 3151 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
3152 | return res; |
3153 | } | |
3154 | ||
dbe9b92a MC |
3155 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
3156 | u32 offset, u32 len, u8 *buf) | |
3157 | { | |
3158 | int i, j, rc = 0; | |
3159 | u32 val; | |
3160 | ||
3161 | for (i = 0; i < len; i += 4) { | |
3162 | u32 addr; | |
3163 | __be32 data; | |
3164 | ||
3165 | addr = offset + i; | |
3166 | ||
3167 | memcpy(&data, buf + i, 4); | |
3168 | ||
3169 | /* | |
3170 | * The SEEPROM interface expects the data to always be opposite | |
3171 | * the native endian format. We accomplish this by reversing | |
3172 | * all the operations that would have been performed on the | |
3173 | * data from a call to tg3_nvram_read_be32(). | |
3174 | */ | |
3175 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
3176 | ||
3177 | val = tr32(GRC_EEPROM_ADDR); | |
3178 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
3179 | ||
3180 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
3181 | EEPROM_ADDR_READ); | |
3182 | tw32(GRC_EEPROM_ADDR, val | | |
3183 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
3184 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
3185 | EEPROM_ADDR_START | | |
3186 | EEPROM_ADDR_WRITE); | |
3187 | ||
3188 | for (j = 0; j < 1000; j++) { | |
3189 | val = tr32(GRC_EEPROM_ADDR); | |
3190 | ||
3191 | if (val & EEPROM_ADDR_COMPLETE) | |
3192 | break; | |
3193 | msleep(1); | |
3194 | } | |
3195 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
3196 | rc = -EBUSY; | |
3197 | break; | |
3198 | } | |
3199 | } | |
3200 | ||
3201 | return rc; | |
3202 | } | |
3203 | ||
3204 | /* offset and length are dword aligned */ | |
3205 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
3206 | u8 *buf) | |
3207 | { | |
3208 | int ret = 0; | |
3209 | u32 pagesize = tp->nvram_pagesize; | |
3210 | u32 pagemask = pagesize - 1; | |
3211 | u32 nvram_cmd; | |
3212 | u8 *tmp; | |
3213 | ||
3214 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
3215 | if (tmp == NULL) | |
3216 | return -ENOMEM; | |
3217 | ||
3218 | while (len) { | |
3219 | int j; | |
3220 | u32 phy_addr, page_off, size; | |
3221 | ||
3222 | phy_addr = offset & ~pagemask; | |
3223 | ||
3224 | for (j = 0; j < pagesize; j += 4) { | |
3225 | ret = tg3_nvram_read_be32(tp, phy_addr + j, | |
3226 | (__be32 *) (tmp + j)); | |
3227 | if (ret) | |
3228 | break; | |
3229 | } | |
3230 | if (ret) | |
3231 | break; | |
3232 | ||
3233 | page_off = offset & pagemask; | |
3234 | size = pagesize; | |
3235 | if (len < size) | |
3236 | size = len; | |
3237 | ||
3238 | len -= size; | |
3239 | ||
3240 | memcpy(tmp + page_off, buf, size); | |
3241 | ||
3242 | offset = offset + (pagesize - page_off); | |
3243 | ||
3244 | tg3_enable_nvram_access(tp); | |
3245 | ||
3246 | /* | |
3247 | * Before we can erase the flash page, we need | |
3248 | * to issue a special "write enable" command. | |
3249 | */ | |
3250 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3251 | ||
3252 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
3253 | break; | |
3254 | ||
3255 | /* Erase the target page */ | |
3256 | tw32(NVRAM_ADDR, phy_addr); | |
3257 | ||
3258 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
3259 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
3260 | ||
3261 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
3262 | break; | |
3263 | ||
3264 | /* Issue another write enable to start the write. */ | |
3265 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3266 | ||
3267 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
3268 | break; | |
3269 | ||
3270 | for (j = 0; j < pagesize; j += 4) { | |
3271 | __be32 data; | |
3272 | ||
3273 | data = *((__be32 *) (tmp + j)); | |
3274 | ||
3275 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
3276 | ||
3277 | tw32(NVRAM_ADDR, phy_addr + j); | |
3278 | ||
3279 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
3280 | NVRAM_CMD_WR; | |
3281 | ||
3282 | if (j == 0) | |
3283 | nvram_cmd |= NVRAM_CMD_FIRST; | |
3284 | else if (j == (pagesize - 4)) | |
3285 | nvram_cmd |= NVRAM_CMD_LAST; | |
3286 | ||
3287 | ret = tg3_nvram_exec_cmd(tp, nvram_cmd); | |
3288 | if (ret) | |
3289 | break; | |
3290 | } | |
3291 | if (ret) | |
3292 | break; | |
3293 | } | |
3294 | ||
3295 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3296 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
3297 | ||
3298 | kfree(tmp); | |
3299 | ||
3300 | return ret; | |
3301 | } | |
3302 | ||
3303 | /* offset and length are dword aligned */ | |
3304 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
3305 | u8 *buf) | |
3306 | { | |
3307 | int i, ret = 0; | |
3308 | ||
3309 | for (i = 0; i < len; i += 4, offset += 4) { | |
3310 | u32 page_off, phy_addr, nvram_cmd; | |
3311 | __be32 data; | |
3312 | ||
3313 | memcpy(&data, buf + i, 4); | |
3314 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
3315 | ||
3316 | page_off = offset % tp->nvram_pagesize; | |
3317 | ||
3318 | phy_addr = tg3_nvram_phys_addr(tp, offset); | |
3319 | ||
dbe9b92a MC |
3320 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; |
3321 | ||
3322 | if (page_off == 0 || i == 0) | |
3323 | nvram_cmd |= NVRAM_CMD_FIRST; | |
3324 | if (page_off == (tp->nvram_pagesize - 4)) | |
3325 | nvram_cmd |= NVRAM_CMD_LAST; | |
3326 | ||
3327 | if (i == (len - 4)) | |
3328 | nvram_cmd |= NVRAM_CMD_LAST; | |
3329 | ||
42278224 MC |
3330 | if ((nvram_cmd & NVRAM_CMD_FIRST) || |
3331 | !tg3_flag(tp, FLASH) || | |
3332 | !tg3_flag(tp, 57765_PLUS)) | |
3333 | tw32(NVRAM_ADDR, phy_addr); | |
3334 | ||
dbe9b92a MC |
3335 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
3336 | !tg3_flag(tp, 5755_PLUS) && | |
3337 | (tp->nvram_jedecnum == JEDEC_ST) && | |
3338 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
3339 | u32 cmd; | |
3340 | ||
3341 | cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3342 | ret = tg3_nvram_exec_cmd(tp, cmd); | |
3343 | if (ret) | |
3344 | break; | |
3345 | } | |
3346 | if (!tg3_flag(tp, FLASH)) { | |
3347 | /* We always do complete word writes to eeprom. */ | |
3348 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
3349 | } | |
3350 | ||
3351 | ret = tg3_nvram_exec_cmd(tp, nvram_cmd); | |
3352 | if (ret) | |
3353 | break; | |
3354 | } | |
3355 | return ret; | |
3356 | } | |
3357 | ||
3358 | /* offset and length are dword aligned */ | |
3359 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
3360 | { | |
3361 | int ret; | |
3362 | ||
3363 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { | |
3364 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & | |
3365 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
3366 | udelay(40); | |
3367 | } | |
3368 | ||
3369 | if (!tg3_flag(tp, NVRAM)) { | |
3370 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
3371 | } else { | |
3372 | u32 grc_mode; | |
3373 | ||
3374 | ret = tg3_nvram_lock(tp); | |
3375 | if (ret) | |
3376 | return ret; | |
3377 | ||
3378 | tg3_enable_nvram_access(tp); | |
3379 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) | |
3380 | tw32(NVRAM_WRITE1, 0x406); | |
3381 | ||
3382 | grc_mode = tr32(GRC_MODE); | |
3383 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
3384 | ||
3385 | if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { | |
3386 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
3387 | buf); | |
3388 | } else { | |
3389 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, | |
3390 | buf); | |
3391 | } | |
3392 | ||
3393 | grc_mode = tr32(GRC_MODE); | |
3394 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
3395 | ||
3396 | tg3_disable_nvram_access(tp); | |
3397 | tg3_nvram_unlock(tp); | |
3398 | } | |
3399 | ||
3400 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { | |
3401 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
3402 | udelay(40); | |
3403 | } | |
3404 | ||
3405 | return ret; | |
3406 | } | |
3407 | ||
997b4f13 MC |
3408 | #define RX_CPU_SCRATCH_BASE 0x30000 |
3409 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
3410 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
3411 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
3412 | ||
3413 | /* tp->lock is held. */ | |
3414 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
3415 | { | |
3416 | int i; | |
3417 | ||
3418 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); | |
3419 | ||
3420 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
3421 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
3422 | ||
3423 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
3424 | return 0; | |
3425 | } | |
3426 | if (offset == RX_CPU_BASE) { | |
3427 | for (i = 0; i < 10000; i++) { | |
3428 | tw32(offset + CPU_STATE, 0xffffffff); | |
3429 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
3430 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
3431 | break; | |
3432 | } | |
3433 | ||
3434 | tw32(offset + CPU_STATE, 0xffffffff); | |
3435 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
3436 | udelay(10); | |
3437 | } else { | |
3438 | for (i = 0; i < 10000; i++) { | |
3439 | tw32(offset + CPU_STATE, 0xffffffff); | |
3440 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
3441 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
3442 | break; | |
3443 | } | |
3444 | } | |
3445 | ||
3446 | if (i >= 10000) { | |
3447 | netdev_err(tp->dev, "%s timed out, %s CPU\n", | |
3448 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
3449 | return -ENODEV; | |
3450 | } | |
3451 | ||
3452 | /* Clear firmware's nvram arbitration. */ | |
3453 | if (tg3_flag(tp, NVRAM)) | |
3454 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
3455 | return 0; | |
3456 | } | |
3457 | ||
3458 | struct fw_info { | |
3459 | unsigned int fw_base; | |
3460 | unsigned int fw_len; | |
3461 | const __be32 *fw_data; | |
3462 | }; | |
3463 | ||
3464 | /* tp->lock is held. */ | |
3465 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, | |
3466 | u32 cpu_scratch_base, int cpu_scratch_size, | |
3467 | struct fw_info *info) | |
3468 | { | |
3469 | int err, lock_err, i; | |
3470 | void (*write_op)(struct tg3 *, u32, u32); | |
3471 | ||
3472 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { | |
3473 | netdev_err(tp->dev, | |
3474 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
3475 | __func__); | |
3476 | return -EINVAL; | |
3477 | } | |
3478 | ||
3479 | if (tg3_flag(tp, 5705_PLUS)) | |
3480 | write_op = tg3_write_mem; | |
3481 | else | |
3482 | write_op = tg3_write_indirect_reg32; | |
3483 | ||
3484 | /* It is possible that bootcode is still loading at this point. | |
3485 | * Get the nvram lock first before halting the cpu. | |
3486 | */ | |
3487 | lock_err = tg3_nvram_lock(tp); | |
3488 | err = tg3_halt_cpu(tp, cpu_base); | |
3489 | if (!lock_err) | |
3490 | tg3_nvram_unlock(tp); | |
3491 | if (err) | |
3492 | goto out; | |
3493 | ||
3494 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
3495 | write_op(tp, cpu_scratch_base + i, 0); | |
3496 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3497 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
3498 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) | |
3499 | write_op(tp, (cpu_scratch_base + | |
3500 | (info->fw_base & 0xffff) + | |
3501 | (i * sizeof(u32))), | |
3502 | be32_to_cpu(info->fw_data[i])); | |
3503 | ||
3504 | err = 0; | |
3505 | ||
3506 | out: | |
3507 | return err; | |
3508 | } | |
3509 | ||
3510 | /* tp->lock is held. */ | |
3511 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
3512 | { | |
3513 | struct fw_info info; | |
3514 | const __be32 *fw_data; | |
3515 | int err, i; | |
3516 | ||
3517 | fw_data = (void *)tp->fw->data; | |
3518 | ||
3519 | /* Firmware blob starts with version numbers, followed by | |
3520 | start address and length. We are setting complete length. | |
3521 | length = end_address_of_bss - start_address_of_text. | |
3522 | Remainder is the blob to be loaded contiguously | |
3523 | from start address. */ | |
3524 | ||
3525 | info.fw_base = be32_to_cpu(fw_data[1]); | |
3526 | info.fw_len = tp->fw->size - 12; | |
3527 | info.fw_data = &fw_data[3]; | |
3528 | ||
3529 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
3530 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
3531 | &info); | |
3532 | if (err) | |
3533 | return err; | |
3534 | ||
3535 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
3536 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
3537 | &info); | |
3538 | if (err) | |
3539 | return err; | |
3540 | ||
3541 | /* Now startup only the RX cpu. */ | |
3542 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3543 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
3544 | ||
3545 | for (i = 0; i < 5; i++) { | |
3546 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) | |
3547 | break; | |
3548 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3549 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
3550 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
3551 | udelay(1000); | |
3552 | } | |
3553 | if (i >= 5) { | |
3554 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " | |
3555 | "should be %08x\n", __func__, | |
3556 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); | |
3557 | return -ENODEV; | |
3558 | } | |
3559 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3560 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
3561 | ||
3562 | return 0; | |
3563 | } | |
3564 | ||
3565 | /* tp->lock is held. */ | |
3566 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
3567 | { | |
3568 | struct fw_info info; | |
3569 | const __be32 *fw_data; | |
3570 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; | |
3571 | int err, i; | |
3572 | ||
3573 | if (tg3_flag(tp, HW_TSO_1) || | |
3574 | tg3_flag(tp, HW_TSO_2) || | |
3575 | tg3_flag(tp, HW_TSO_3)) | |
3576 | return 0; | |
3577 | ||
3578 | fw_data = (void *)tp->fw->data; | |
3579 | ||
3580 | /* Firmware blob starts with version numbers, followed by | |
3581 | start address and length. We are setting complete length. | |
3582 | length = end_address_of_bss - start_address_of_text. | |
3583 | Remainder is the blob to be loaded contiguously | |
3584 | from start address. */ | |
3585 | ||
3586 | info.fw_base = be32_to_cpu(fw_data[1]); | |
3587 | cpu_scratch_size = tp->fw_len; | |
3588 | info.fw_len = tp->fw->size - 12; | |
3589 | info.fw_data = &fw_data[3]; | |
3590 | ||
3591 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
3592 | cpu_base = RX_CPU_BASE; | |
3593 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
3594 | } else { | |
3595 | cpu_base = TX_CPU_BASE; | |
3596 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
3597 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
3598 | } | |
3599 | ||
3600 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
3601 | cpu_scratch_base, cpu_scratch_size, | |
3602 | &info); | |
3603 | if (err) | |
3604 | return err; | |
3605 | ||
3606 | /* Now startup the cpu. */ | |
3607 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3608 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
3609 | ||
3610 | for (i = 0; i < 5; i++) { | |
3611 | if (tr32(cpu_base + CPU_PC) == info.fw_base) | |
3612 | break; | |
3613 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3614 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
3615 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
3616 | udelay(1000); | |
3617 | } | |
3618 | if (i >= 5) { | |
3619 | netdev_err(tp->dev, | |
3620 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
3621 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); | |
3622 | return -ENODEV; | |
3623 | } | |
3624 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3625 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
3626 | return 0; | |
3627 | } | |
3628 | ||
3629 | ||
3f007891 MC |
3630 | /* tp->lock is held. */ |
3631 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
3632 | { | |
3633 | u32 addr_high, addr_low; | |
3634 | int i; | |
3635 | ||
3636 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
3637 | tp->dev->dev_addr[1]); | |
3638 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
3639 | (tp->dev->dev_addr[3] << 16) | | |
3640 | (tp->dev->dev_addr[4] << 8) | | |
3641 | (tp->dev->dev_addr[5] << 0)); | |
3642 | for (i = 0; i < 4; i++) { | |
3643 | if (i == 1 && skip_mac_1) | |
3644 | continue; | |
3645 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
3646 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
3647 | } | |
3648 | ||
3649 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3650 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
3651 | for (i = 0; i < 12; i++) { | |
3652 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
3653 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
3654 | } | |
3655 | } | |
3656 | ||
3657 | addr_high = (tp->dev->dev_addr[0] + | |
3658 | tp->dev->dev_addr[1] + | |
3659 | tp->dev->dev_addr[2] + | |
3660 | tp->dev->dev_addr[3] + | |
3661 | tp->dev->dev_addr[4] + | |
3662 | tp->dev->dev_addr[5]) & | |
3663 | TX_BACKOFF_SEED_MASK; | |
3664 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
3665 | } | |
3666 | ||
c866b7ea | 3667 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 3668 | { |
c866b7ea RW |
3669 | /* |
3670 | * Make sure register accesses (indirect or otherwise) will function | |
3671 | * correctly. | |
1da177e4 LT |
3672 | */ |
3673 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
3674 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
3675 | } | |
1da177e4 | 3676 | |
c866b7ea RW |
3677 | static int tg3_power_up(struct tg3 *tp) |
3678 | { | |
bed9829f | 3679 | int err; |
8c6bda1a | 3680 | |
bed9829f | 3681 | tg3_enable_register_access(tp); |
1da177e4 | 3682 | |
bed9829f MC |
3683 | err = pci_set_power_state(tp->pdev, PCI_D0); |
3684 | if (!err) { | |
3685 | /* Switch out of Vaux if it is a NIC */ | |
3686 | tg3_pwrsrc_switch_to_vmain(tp); | |
3687 | } else { | |
3688 | netdev_err(tp->dev, "Transition to D0 failed\n"); | |
3689 | } | |
1da177e4 | 3690 | |
bed9829f | 3691 | return err; |
c866b7ea | 3692 | } |
1da177e4 | 3693 | |
4b409522 MC |
3694 | static int tg3_setup_phy(struct tg3 *, int); |
3695 | ||
c866b7ea RW |
3696 | static int tg3_power_down_prepare(struct tg3 *tp) |
3697 | { | |
3698 | u32 misc_host_ctrl; | |
3699 | bool device_should_wake, do_low_power; | |
3700 | ||
3701 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
3702 | |
3703 | /* Restore the CLKREQ setting. */ | |
0f49bfbd JL |
3704 | if (tg3_flag(tp, CLKREQ_BUG)) |
3705 | pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, | |
3706 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
5e7dfd0f | 3707 | |
1da177e4 LT |
3708 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
3709 | tw32(TG3PCI_MISC_HOST_CTRL, | |
3710 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
3711 | ||
c866b7ea | 3712 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 3713 | tg3_flag(tp, WOL_ENABLE); |
05ac4cb7 | 3714 | |
63c3a66f | 3715 | if (tg3_flag(tp, USE_PHYLIB)) { |
0a459aac | 3716 | do_low_power = false; |
f07e9af3 | 3717 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 3718 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 3719 | struct phy_device *phydev; |
0a459aac | 3720 | u32 phyid, advertising; |
b02fd9e3 | 3721 | |
3f0e3ad7 | 3722 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 3723 | |
80096068 | 3724 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 | 3725 | |
c6700ce2 MC |
3726 | tp->link_config.speed = phydev->speed; |
3727 | tp->link_config.duplex = phydev->duplex; | |
3728 | tp->link_config.autoneg = phydev->autoneg; | |
3729 | tp->link_config.advertising = phydev->advertising; | |
b02fd9e3 MC |
3730 | |
3731 | advertising = ADVERTISED_TP | | |
3732 | ADVERTISED_Pause | | |
3733 | ADVERTISED_Autoneg | | |
3734 | ADVERTISED_10baseT_Half; | |
3735 | ||
63c3a66f JP |
3736 | if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { |
3737 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
b02fd9e3 MC |
3738 | advertising |= |
3739 | ADVERTISED_100baseT_Half | | |
3740 | ADVERTISED_100baseT_Full | | |
3741 | ADVERTISED_10baseT_Full; | |
3742 | else | |
3743 | advertising |= ADVERTISED_10baseT_Full; | |
3744 | } | |
3745 | ||
3746 | phydev->advertising = advertising; | |
3747 | ||
3748 | phy_start_aneg(phydev); | |
0a459aac MC |
3749 | |
3750 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
3751 | if (phyid != PHY_ID_BCMAC131) { |
3752 | phyid &= PHY_BCM_OUI_MASK; | |
3753 | if (phyid == PHY_BCM_OUI_1 || | |
3754 | phyid == PHY_BCM_OUI_2 || | |
3755 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
3756 | do_low_power = true; |
3757 | } | |
b02fd9e3 | 3758 | } |
dd477003 | 3759 | } else { |
2023276e | 3760 | do_low_power = true; |
0a459aac | 3761 | |
c6700ce2 | 3762 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) |
80096068 | 3763 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
1da177e4 | 3764 | |
2855b9fe | 3765 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
dd477003 | 3766 | tg3_setup_phy(tp, 0); |
1da177e4 LT |
3767 | } |
3768 | ||
b5d3772c MC |
3769 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
3770 | u32 val; | |
3771 | ||
3772 | val = tr32(GRC_VCPU_EXT_CTRL); | |
3773 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
63c3a66f | 3774 | } else if (!tg3_flag(tp, ENABLE_ASF)) { |
6921d201 MC |
3775 | int i; |
3776 | u32 val; | |
3777 | ||
3778 | for (i = 0; i < 200; i++) { | |
3779 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
3780 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
3781 | break; | |
3782 | msleep(1); | |
3783 | } | |
3784 | } | |
63c3a66f | 3785 | if (tg3_flag(tp, WOL_CAP)) |
a85feb8c GZ |
3786 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | |
3787 | WOL_DRV_STATE_SHUTDOWN | | |
3788 | WOL_DRV_WOL | | |
3789 | WOL_SET_MAGIC_PKT); | |
6921d201 | 3790 | |
05ac4cb7 | 3791 | if (device_should_wake) { |
1da177e4 LT |
3792 | u32 mac_mode; |
3793 | ||
f07e9af3 | 3794 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
b4bd2929 MC |
3795 | if (do_low_power && |
3796 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
3797 | tg3_phy_auxctl_write(tp, | |
3798 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, | |
3799 | MII_TG3_AUXCTL_PCTL_WOL_EN | | |
3800 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
3801 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); | |
dd477003 MC |
3802 | udelay(40); |
3803 | } | |
1da177e4 | 3804 | |
f07e9af3 | 3805 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
3806 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
3807 | else | |
3808 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 3809 | |
e8f3f6ca MC |
3810 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
3811 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
3812 | ASIC_REV_5700) { | |
63c3a66f | 3813 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? |
e8f3f6ca MC |
3814 | SPEED_100 : SPEED_10; |
3815 | if (tg3_5700_link_polarity(tp, speed)) | |
3816 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
3817 | else | |
3818 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
3819 | } | |
1da177e4 LT |
3820 | } else { |
3821 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
3822 | } | |
3823 | ||
63c3a66f | 3824 | if (!tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
3825 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
3826 | ||
05ac4cb7 | 3827 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
63c3a66f JP |
3828 | if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && |
3829 | (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) | |
05ac4cb7 | 3830 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; |
1da177e4 | 3831 | |
63c3a66f | 3832 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b MC |
3833 | mac_mode |= MAC_MODE_APE_TX_EN | |
3834 | MAC_MODE_APE_RX_EN | | |
3835 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 3836 | |
1da177e4 LT |
3837 | tw32_f(MAC_MODE, mac_mode); |
3838 | udelay(100); | |
3839 | ||
3840 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
3841 | udelay(10); | |
3842 | } | |
3843 | ||
63c3a66f | 3844 | if (!tg3_flag(tp, WOL_SPEED_100MB) && |
1da177e4 LT |
3845 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
3846 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
3847 | u32 base_val; | |
3848 | ||
3849 | base_val = tp->pci_clock_ctrl; | |
3850 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
3851 | CLOCK_CTRL_TXCLK_DISABLE); | |
3852 | ||
b401e9e2 MC |
3853 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
3854 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
63c3a66f JP |
3855 | } else if (tg3_flag(tp, 5780_CLASS) || |
3856 | tg3_flag(tp, CPMU_PRESENT) || | |
6ff6f81d | 3857 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
4cf78e4f | 3858 | /* do nothing */ |
63c3a66f | 3859 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { |
1da177e4 LT |
3860 | u32 newbits1, newbits2; |
3861 | ||
3862 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3863 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3864 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
3865 | CLOCK_CTRL_TXCLK_DISABLE | | |
3866 | CLOCK_CTRL_ALTCLK); | |
3867 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
63c3a66f | 3868 | } else if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
3869 | newbits1 = CLOCK_CTRL_625_CORE; |
3870 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
3871 | } else { | |
3872 | newbits1 = CLOCK_CTRL_ALTCLK; | |
3873 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
3874 | } | |
3875 | ||
b401e9e2 MC |
3876 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
3877 | 40); | |
1da177e4 | 3878 | |
b401e9e2 MC |
3879 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
3880 | 40); | |
1da177e4 | 3881 | |
63c3a66f | 3882 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
3883 | u32 newbits3; |
3884 | ||
3885 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3886 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3887 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
3888 | CLOCK_CTRL_TXCLK_DISABLE | | |
3889 | CLOCK_CTRL_44MHZ_CORE); | |
3890 | } else { | |
3891 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
3892 | } | |
3893 | ||
b401e9e2 MC |
3894 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
3895 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
3896 | } |
3897 | } | |
3898 | ||
63c3a66f | 3899 | if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) |
0a459aac | 3900 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 3901 | |
cd0d7228 | 3902 | tg3_frob_aux_power(tp, true); |
1da177e4 LT |
3903 | |
3904 | /* Workaround for unstable PLL clock */ | |
3905 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
3906 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
3907 | u32 val = tr32(0x7d00); | |
3908 | ||
3909 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
3910 | tw32(0x7d00, val); | |
63c3a66f | 3911 | if (!tg3_flag(tp, ENABLE_ASF)) { |
ec41c7df MC |
3912 | int err; |
3913 | ||
3914 | err = tg3_nvram_lock(tp); | |
1da177e4 | 3915 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
3916 | if (!err) |
3917 | tg3_nvram_unlock(tp); | |
6921d201 | 3918 | } |
1da177e4 LT |
3919 | } |
3920 | ||
bbadf503 MC |
3921 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
3922 | ||
c866b7ea RW |
3923 | return 0; |
3924 | } | |
12dac075 | 3925 | |
c866b7ea RW |
3926 | static void tg3_power_down(struct tg3 *tp) |
3927 | { | |
3928 | tg3_power_down_prepare(tp); | |
1da177e4 | 3929 | |
63c3a66f | 3930 | pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); |
c866b7ea | 3931 | pci_set_power_state(tp->pdev, PCI_D3hot); |
1da177e4 LT |
3932 | } |
3933 | ||
1da177e4 LT |
3934 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
3935 | { | |
3936 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
3937 | case MII_TG3_AUX_STAT_10HALF: | |
3938 | *speed = SPEED_10; | |
3939 | *duplex = DUPLEX_HALF; | |
3940 | break; | |
3941 | ||
3942 | case MII_TG3_AUX_STAT_10FULL: | |
3943 | *speed = SPEED_10; | |
3944 | *duplex = DUPLEX_FULL; | |
3945 | break; | |
3946 | ||
3947 | case MII_TG3_AUX_STAT_100HALF: | |
3948 | *speed = SPEED_100; | |
3949 | *duplex = DUPLEX_HALF; | |
3950 | break; | |
3951 | ||
3952 | case MII_TG3_AUX_STAT_100FULL: | |
3953 | *speed = SPEED_100; | |
3954 | *duplex = DUPLEX_FULL; | |
3955 | break; | |
3956 | ||
3957 | case MII_TG3_AUX_STAT_1000HALF: | |
3958 | *speed = SPEED_1000; | |
3959 | *duplex = DUPLEX_HALF; | |
3960 | break; | |
3961 | ||
3962 | case MII_TG3_AUX_STAT_1000FULL: | |
3963 | *speed = SPEED_1000; | |
3964 | *duplex = DUPLEX_FULL; | |
3965 | break; | |
3966 | ||
3967 | default: | |
f07e9af3 | 3968 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
3969 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
3970 | SPEED_10; | |
3971 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
3972 | DUPLEX_HALF; | |
3973 | break; | |
3974 | } | |
e740522e MC |
3975 | *speed = SPEED_UNKNOWN; |
3976 | *duplex = DUPLEX_UNKNOWN; | |
1da177e4 | 3977 | break; |
855e1111 | 3978 | } |
1da177e4 LT |
3979 | } |
3980 | ||
42b64a45 | 3981 | static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) |
1da177e4 | 3982 | { |
42b64a45 MC |
3983 | int err = 0; |
3984 | u32 val, new_adv; | |
1da177e4 | 3985 | |
42b64a45 | 3986 | new_adv = ADVERTISE_CSMA; |
202ff1c2 | 3987 | new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL; |
f88788f0 | 3988 | new_adv |= mii_advertise_flowctrl(flowctrl); |
1da177e4 | 3989 | |
42b64a45 MC |
3990 | err = tg3_writephy(tp, MII_ADVERTISE, new_adv); |
3991 | if (err) | |
3992 | goto done; | |
ba4d07a8 | 3993 | |
4f272096 MC |
3994 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
3995 | new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise); | |
ba4d07a8 | 3996 | |
4f272096 MC |
3997 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
3998 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
3999 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; | |
ba4d07a8 | 4000 | |
4f272096 MC |
4001 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
4002 | if (err) | |
4003 | goto done; | |
4004 | } | |
1da177e4 | 4005 | |
42b64a45 MC |
4006 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) |
4007 | goto done; | |
52b02d04 | 4008 | |
42b64a45 MC |
4009 | tw32(TG3_CPMU_EEE_MODE, |
4010 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
52b02d04 | 4011 | |
42b64a45 MC |
4012 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
4013 | if (!err) { | |
4014 | u32 err2; | |
52b02d04 | 4015 | |
b715ce94 MC |
4016 | val = 0; |
4017 | /* Advertise 100-BaseTX EEE ability */ | |
4018 | if (advertise & ADVERTISED_100baseT_Full) | |
4019 | val |= MDIO_AN_EEE_ADV_100TX; | |
4020 | /* Advertise 1000-BaseT EEE ability */ | |
4021 | if (advertise & ADVERTISED_1000baseT_Full) | |
4022 | val |= MDIO_AN_EEE_ADV_1000T; | |
4023 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
4024 | if (err) | |
4025 | val = 0; | |
4026 | ||
21a00ab2 MC |
4027 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
4028 | case ASIC_REV_5717: | |
4029 | case ASIC_REV_57765: | |
55086ad9 | 4030 | case ASIC_REV_57766: |
21a00ab2 | 4031 | case ASIC_REV_5719: |
b715ce94 MC |
4032 | /* If we advertised any eee advertisements above... */ |
4033 | if (val) | |
4034 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
4035 | MII_TG3_DSP_TAP26_RMRXSTO | | |
4036 | MII_TG3_DSP_TAP26_OPCSINPT; | |
21a00ab2 | 4037 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); |
be671947 MC |
4038 | /* Fall through */ |
4039 | case ASIC_REV_5720: | |
4040 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
4041 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
4042 | MII_TG3_DSP_CH34TP2_HIBW01); | |
21a00ab2 | 4043 | } |
52b02d04 | 4044 | |
42b64a45 MC |
4045 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
4046 | if (!err) | |
4047 | err = err2; | |
4048 | } | |
4049 | ||
4050 | done: | |
4051 | return err; | |
4052 | } | |
4053 | ||
4054 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
4055 | { | |
d13ba512 MC |
4056 | if (tp->link_config.autoneg == AUTONEG_ENABLE || |
4057 | (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { | |
4058 | u32 adv, fc; | |
4059 | ||
4060 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
4061 | adv = ADVERTISED_10baseT_Half | | |
4062 | ADVERTISED_10baseT_Full; | |
4063 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
4064 | adv |= ADVERTISED_100baseT_Half | | |
4065 | ADVERTISED_100baseT_Full; | |
4066 | ||
4067 | fc = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
42b64a45 | 4068 | } else { |
d13ba512 MC |
4069 | adv = tp->link_config.advertising; |
4070 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
4071 | adv &= ~(ADVERTISED_1000baseT_Half | | |
4072 | ADVERTISED_1000baseT_Full); | |
4073 | ||
4074 | fc = tp->link_config.flowctrl; | |
52b02d04 | 4075 | } |
52b02d04 | 4076 | |
d13ba512 | 4077 | tg3_phy_autoneg_cfg(tp, adv, fc); |
52b02d04 | 4078 | |
d13ba512 MC |
4079 | tg3_writephy(tp, MII_BMCR, |
4080 | BMCR_ANENABLE | BMCR_ANRESTART); | |
4081 | } else { | |
4082 | int i; | |
1da177e4 LT |
4083 | u32 bmcr, orig_bmcr; |
4084 | ||
4085 | tp->link_config.active_speed = tp->link_config.speed; | |
4086 | tp->link_config.active_duplex = tp->link_config.duplex; | |
4087 | ||
4088 | bmcr = 0; | |
4089 | switch (tp->link_config.speed) { | |
4090 | default: | |
4091 | case SPEED_10: | |
4092 | break; | |
4093 | ||
4094 | case SPEED_100: | |
4095 | bmcr |= BMCR_SPEED100; | |
4096 | break; | |
4097 | ||
4098 | case SPEED_1000: | |
221c5637 | 4099 | bmcr |= BMCR_SPEED1000; |
1da177e4 | 4100 | break; |
855e1111 | 4101 | } |
1da177e4 LT |
4102 | |
4103 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4104 | bmcr |= BMCR_FULLDPLX; | |
4105 | ||
4106 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
4107 | (bmcr != orig_bmcr)) { | |
4108 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
4109 | for (i = 0; i < 1500; i++) { | |
4110 | u32 tmp; | |
4111 | ||
4112 | udelay(10); | |
4113 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
4114 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
4115 | continue; | |
4116 | if (!(tmp & BMSR_LSTATUS)) { | |
4117 | udelay(40); | |
4118 | break; | |
4119 | } | |
4120 | } | |
4121 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4122 | udelay(40); | |
4123 | } | |
1da177e4 LT |
4124 | } |
4125 | } | |
4126 | ||
4127 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
4128 | { | |
4129 | int err; | |
4130 | ||
4131 | /* Turn off tap power management. */ | |
4132 | /* Set Extended packet length bit */ | |
b4bd2929 | 4133 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
1da177e4 | 4134 | |
6ee7c0a0 MC |
4135 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
4136 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
4137 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
4138 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
4139 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
4140 | |
4141 | udelay(40); | |
4142 | ||
4143 | return err; | |
4144 | } | |
4145 | ||
e2bf73e7 | 4146 | static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) |
1da177e4 | 4147 | { |
e2bf73e7 | 4148 | u32 advmsk, tgtadv, advertising; |
3600d918 | 4149 | |
e2bf73e7 MC |
4150 | advertising = tp->link_config.advertising; |
4151 | tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL; | |
1da177e4 | 4152 | |
e2bf73e7 MC |
4153 | advmsk = ADVERTISE_ALL; |
4154 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
f88788f0 | 4155 | tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); |
e2bf73e7 MC |
4156 | advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4157 | } | |
1da177e4 | 4158 | |
e2bf73e7 MC |
4159 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) |
4160 | return false; | |
4161 | ||
4162 | if ((*lcladv & advmsk) != tgtadv) | |
4163 | return false; | |
b99d2a57 | 4164 | |
f07e9af3 | 4165 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
4166 | u32 tg3_ctrl; |
4167 | ||
e2bf73e7 | 4168 | tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising); |
3600d918 | 4169 | |
221c5637 | 4170 | if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) |
e2bf73e7 | 4171 | return false; |
1da177e4 | 4172 | |
3198e07f MC |
4173 | if (tgtadv && |
4174 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
4175 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) { | |
4176 | tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; | |
4177 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL | | |
4178 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
4179 | } else { | |
4180 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL); | |
4181 | } | |
4182 | ||
e2bf73e7 MC |
4183 | if (tg3_ctrl != tgtadv) |
4184 | return false; | |
ef167e27 MC |
4185 | } |
4186 | ||
e2bf73e7 | 4187 | return true; |
ef167e27 MC |
4188 | } |
4189 | ||
859edb26 MC |
4190 | static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) |
4191 | { | |
4192 | u32 lpeth = 0; | |
4193 | ||
4194 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { | |
4195 | u32 val; | |
4196 | ||
4197 | if (tg3_readphy(tp, MII_STAT1000, &val)) | |
4198 | return false; | |
4199 | ||
4200 | lpeth = mii_stat1000_to_ethtool_lpa_t(val); | |
4201 | } | |
4202 | ||
4203 | if (tg3_readphy(tp, MII_LPA, rmtadv)) | |
4204 | return false; | |
4205 | ||
4206 | lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv); | |
4207 | tp->link_config.rmt_adv = lpeth; | |
4208 | ||
4209 | return true; | |
4210 | } | |
4211 | ||
f4a46d1f NNS |
4212 | static bool tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up) |
4213 | { | |
4214 | if (curr_link_up != tp->link_up) { | |
4215 | if (curr_link_up) { | |
4216 | tg3_carrier_on(tp); | |
4217 | } else { | |
4218 | tg3_carrier_off(tp); | |
4219 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) | |
4220 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
4221 | } | |
4222 | ||
4223 | tg3_link_report(tp); | |
4224 | return true; | |
4225 | } | |
4226 | ||
4227 | return false; | |
4228 | } | |
4229 | ||
1da177e4 LT |
4230 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
4231 | { | |
4232 | int current_link_up; | |
f833c4c1 | 4233 | u32 bmsr, val; |
ef167e27 | 4234 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
4235 | u16 current_speed; |
4236 | u8 current_duplex; | |
4237 | int i, err; | |
4238 | ||
4239 | tw32(MAC_EVENT, 0); | |
4240 | ||
4241 | tw32_f(MAC_STATUS, | |
4242 | (MAC_STATUS_SYNC_CHANGED | | |
4243 | MAC_STATUS_CFG_CHANGED | | |
4244 | MAC_STATUS_MI_COMPLETION | | |
4245 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4246 | udelay(40); | |
4247 | ||
8ef21428 MC |
4248 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
4249 | tw32_f(MAC_MI_MODE, | |
4250 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
4251 | udelay(80); | |
4252 | } | |
1da177e4 | 4253 | |
b4bd2929 | 4254 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); |
1da177e4 LT |
4255 | |
4256 | /* Some third-party PHYs need to be reset on link going | |
4257 | * down. | |
4258 | */ | |
4259 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
4260 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
4261 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
f4a46d1f | 4262 | tp->link_up) { |
1da177e4 LT |
4263 | tg3_readphy(tp, MII_BMSR, &bmsr); |
4264 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
4265 | !(bmsr & BMSR_LSTATUS)) | |
4266 | force_reset = 1; | |
4267 | } | |
4268 | if (force_reset) | |
4269 | tg3_phy_reset(tp); | |
4270 | ||
79eb6904 | 4271 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
4272 | tg3_readphy(tp, MII_BMSR, &bmsr); |
4273 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
63c3a66f | 4274 | !tg3_flag(tp, INIT_COMPLETE)) |
1da177e4 LT |
4275 | bmsr = 0; |
4276 | ||
4277 | if (!(bmsr & BMSR_LSTATUS)) { | |
4278 | err = tg3_init_5401phy_dsp(tp); | |
4279 | if (err) | |
4280 | return err; | |
4281 | ||
4282 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
4283 | for (i = 0; i < 1000; i++) { | |
4284 | udelay(10); | |
4285 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
4286 | (bmsr & BMSR_LSTATUS)) { | |
4287 | udelay(40); | |
4288 | break; | |
4289 | } | |
4290 | } | |
4291 | ||
79eb6904 MC |
4292 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
4293 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
4294 | !(bmsr & BMSR_LSTATUS) && |
4295 | tp->link_config.active_speed == SPEED_1000) { | |
4296 | err = tg3_phy_reset(tp); | |
4297 | if (!err) | |
4298 | err = tg3_init_5401phy_dsp(tp); | |
4299 | if (err) | |
4300 | return err; | |
4301 | } | |
4302 | } | |
4303 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
4304 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
4305 | /* 5701 {A0,B0} CRC bug workaround */ | |
4306 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
4307 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
4308 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
4309 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
4310 | } |
4311 | ||
4312 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
4313 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
4314 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 4315 | |
f07e9af3 | 4316 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 4317 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 4318 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
4319 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
4320 | ||
4321 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
4322 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
4323 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
4324 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
4325 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
4326 | else | |
4327 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
4328 | } | |
4329 | ||
4330 | current_link_up = 0; | |
e740522e MC |
4331 | current_speed = SPEED_UNKNOWN; |
4332 | current_duplex = DUPLEX_UNKNOWN; | |
e348c5e7 | 4333 | tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; |
859edb26 | 4334 | tp->link_config.rmt_adv = 0; |
1da177e4 | 4335 | |
f07e9af3 | 4336 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
15ee95c3 MC |
4337 | err = tg3_phy_auxctl_read(tp, |
4338 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
4339 | &val); | |
4340 | if (!err && !(val & (1 << 10))) { | |
b4bd2929 MC |
4341 | tg3_phy_auxctl_write(tp, |
4342 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
4343 | val | (1 << 10)); | |
1da177e4 LT |
4344 | goto relink; |
4345 | } | |
4346 | } | |
4347 | ||
4348 | bmsr = 0; | |
4349 | for (i = 0; i < 100; i++) { | |
4350 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
4351 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
4352 | (bmsr & BMSR_LSTATUS)) | |
4353 | break; | |
4354 | udelay(40); | |
4355 | } | |
4356 | ||
4357 | if (bmsr & BMSR_LSTATUS) { | |
4358 | u32 aux_stat, bmcr; | |
4359 | ||
4360 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
4361 | for (i = 0; i < 2000; i++) { | |
4362 | udelay(10); | |
4363 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
4364 | aux_stat) | |
4365 | break; | |
4366 | } | |
4367 | ||
4368 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
4369 | ¤t_speed, | |
4370 | ¤t_duplex); | |
4371 | ||
4372 | bmcr = 0; | |
4373 | for (i = 0; i < 200; i++) { | |
4374 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4375 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
4376 | continue; | |
4377 | if (bmcr && bmcr != 0x7fff) | |
4378 | break; | |
4379 | udelay(10); | |
4380 | } | |
4381 | ||
ef167e27 MC |
4382 | lcl_adv = 0; |
4383 | rmt_adv = 0; | |
1da177e4 | 4384 | |
ef167e27 MC |
4385 | tp->link_config.active_speed = current_speed; |
4386 | tp->link_config.active_duplex = current_duplex; | |
4387 | ||
4388 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4389 | if ((bmcr & BMCR_ANENABLE) && | |
e2bf73e7 | 4390 | tg3_phy_copper_an_config_ok(tp, &lcl_adv) && |
859edb26 | 4391 | tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) |
e2bf73e7 | 4392 | current_link_up = 1; |
1da177e4 LT |
4393 | } else { |
4394 | if (!(bmcr & BMCR_ANENABLE) && | |
4395 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
4396 | tp->link_config.duplex == current_duplex && |
4397 | tp->link_config.flowctrl == | |
4398 | tp->link_config.active_flowctrl) { | |
1da177e4 | 4399 | current_link_up = 1; |
1da177e4 LT |
4400 | } |
4401 | } | |
4402 | ||
ef167e27 | 4403 | if (current_link_up == 1 && |
e348c5e7 MC |
4404 | tp->link_config.active_duplex == DUPLEX_FULL) { |
4405 | u32 reg, bit; | |
4406 | ||
4407 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
4408 | reg = MII_TG3_FET_GEN_STAT; | |
4409 | bit = MII_TG3_FET_GEN_STAT_MDIXSTAT; | |
4410 | } else { | |
4411 | reg = MII_TG3_EXT_STAT; | |
4412 | bit = MII_TG3_EXT_STAT_MDIX; | |
4413 | } | |
4414 | ||
4415 | if (!tg3_readphy(tp, reg, &val) && (val & bit)) | |
4416 | tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; | |
4417 | ||
ef167e27 | 4418 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); |
e348c5e7 | 4419 | } |
1da177e4 LT |
4420 | } |
4421 | ||
1da177e4 | 4422 | relink: |
80096068 | 4423 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
4424 | tg3_phy_copper_begin(tp); |
4425 | ||
f833c4c1 | 4426 | tg3_readphy(tp, MII_BMSR, &bmsr); |
06c03c02 MB |
4427 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
4428 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
1da177e4 LT |
4429 | current_link_up = 1; |
4430 | } | |
4431 | ||
4432 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
4433 | if (current_link_up == 1) { | |
4434 | if (tp->link_config.active_speed == SPEED_100 || | |
4435 | tp->link_config.active_speed == SPEED_10) | |
4436 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
4437 | else | |
4438 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 4439 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
4440 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
4441 | else | |
1da177e4 LT |
4442 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
4443 | ||
4444 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
4445 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4446 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4447 | ||
1da177e4 | 4448 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
4449 | if (current_link_up == 1 && |
4450 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 4451 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
4452 | else |
4453 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
4454 | } |
4455 | ||
4456 | /* ??? Without this setting Netgear GA302T PHY does not | |
4457 | * ??? send/receive packets... | |
4458 | */ | |
79eb6904 | 4459 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
4460 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
4461 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
4462 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
4463 | udelay(80); | |
4464 | } | |
4465 | ||
4466 | tw32_f(MAC_MODE, tp->mac_mode); | |
4467 | udelay(40); | |
4468 | ||
52b02d04 MC |
4469 | tg3_phy_eee_adjust(tp, current_link_up); |
4470 | ||
63c3a66f | 4471 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
4472 | /* Polled via timer. */ |
4473 | tw32_f(MAC_EVENT, 0); | |
4474 | } else { | |
4475 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4476 | } | |
4477 | udelay(40); | |
4478 | ||
4479 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
4480 | current_link_up == 1 && | |
4481 | tp->link_config.active_speed == SPEED_1000 && | |
63c3a66f | 4482 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
1da177e4 LT |
4483 | udelay(120); |
4484 | tw32_f(MAC_STATUS, | |
4485 | (MAC_STATUS_SYNC_CHANGED | | |
4486 | MAC_STATUS_CFG_CHANGED)); | |
4487 | udelay(40); | |
4488 | tg3_write_mem(tp, | |
4489 | NIC_SRAM_FIRMWARE_MBOX, | |
4490 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
4491 | } | |
4492 | ||
5e7dfd0f | 4493 | /* Prevent send BD corruption. */ |
63c3a66f | 4494 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
4495 | if (tp->link_config.active_speed == SPEED_100 || |
4496 | tp->link_config.active_speed == SPEED_10) | |
0f49bfbd JL |
4497 | pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, |
4498 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
5e7dfd0f | 4499 | else |
0f49bfbd JL |
4500 | pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, |
4501 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
5e7dfd0f MC |
4502 | } |
4503 | ||
f4a46d1f | 4504 | tg3_test_and_report_link_chg(tp, current_link_up); |
1da177e4 LT |
4505 | |
4506 | return 0; | |
4507 | } | |
4508 | ||
4509 | struct tg3_fiber_aneginfo { | |
4510 | int state; | |
4511 | #define ANEG_STATE_UNKNOWN 0 | |
4512 | #define ANEG_STATE_AN_ENABLE 1 | |
4513 | #define ANEG_STATE_RESTART_INIT 2 | |
4514 | #define ANEG_STATE_RESTART 3 | |
4515 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
4516 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
4517 | #define ANEG_STATE_ABILITY_DETECT 6 | |
4518 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
4519 | #define ANEG_STATE_ACK_DETECT 8 | |
4520 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
4521 | #define ANEG_STATE_COMPLETE_ACK 10 | |
4522 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
4523 | #define ANEG_STATE_IDLE_DETECT 12 | |
4524 | #define ANEG_STATE_LINK_OK 13 | |
4525 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
4526 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
4527 | ||
4528 | u32 flags; | |
4529 | #define MR_AN_ENABLE 0x00000001 | |
4530 | #define MR_RESTART_AN 0x00000002 | |
4531 | #define MR_AN_COMPLETE 0x00000004 | |
4532 | #define MR_PAGE_RX 0x00000008 | |
4533 | #define MR_NP_LOADED 0x00000010 | |
4534 | #define MR_TOGGLE_TX 0x00000020 | |
4535 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
4536 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
4537 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
4538 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
4539 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
4540 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
4541 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
4542 | #define MR_TOGGLE_RX 0x00002000 | |
4543 | #define MR_NP_RX 0x00004000 | |
4544 | ||
4545 | #define MR_LINK_OK 0x80000000 | |
4546 | ||
4547 | unsigned long link_time, cur_time; | |
4548 | ||
4549 | u32 ability_match_cfg; | |
4550 | int ability_match_count; | |
4551 | ||
4552 | char ability_match, idle_match, ack_match; | |
4553 | ||
4554 | u32 txconfig, rxconfig; | |
4555 | #define ANEG_CFG_NP 0x00000080 | |
4556 | #define ANEG_CFG_ACK 0x00000040 | |
4557 | #define ANEG_CFG_RF2 0x00000020 | |
4558 | #define ANEG_CFG_RF1 0x00000010 | |
4559 | #define ANEG_CFG_PS2 0x00000001 | |
4560 | #define ANEG_CFG_PS1 0x00008000 | |
4561 | #define ANEG_CFG_HD 0x00004000 | |
4562 | #define ANEG_CFG_FD 0x00002000 | |
4563 | #define ANEG_CFG_INVAL 0x00001f06 | |
4564 | ||
4565 | }; | |
4566 | #define ANEG_OK 0 | |
4567 | #define ANEG_DONE 1 | |
4568 | #define ANEG_TIMER_ENAB 2 | |
4569 | #define ANEG_FAILED -1 | |
4570 | ||
4571 | #define ANEG_STATE_SETTLE_TIME 10000 | |
4572 | ||
4573 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
4574 | struct tg3_fiber_aneginfo *ap) | |
4575 | { | |
5be73b47 | 4576 | u16 flowctrl; |
1da177e4 LT |
4577 | unsigned long delta; |
4578 | u32 rx_cfg_reg; | |
4579 | int ret; | |
4580 | ||
4581 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
4582 | ap->rxconfig = 0; | |
4583 | ap->link_time = 0; | |
4584 | ap->cur_time = 0; | |
4585 | ap->ability_match_cfg = 0; | |
4586 | ap->ability_match_count = 0; | |
4587 | ap->ability_match = 0; | |
4588 | ap->idle_match = 0; | |
4589 | ap->ack_match = 0; | |
4590 | } | |
4591 | ap->cur_time++; | |
4592 | ||
4593 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
4594 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
4595 | ||
4596 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
4597 | ap->ability_match_cfg = rx_cfg_reg; | |
4598 | ap->ability_match = 0; | |
4599 | ap->ability_match_count = 0; | |
4600 | } else { | |
4601 | if (++ap->ability_match_count > 1) { | |
4602 | ap->ability_match = 1; | |
4603 | ap->ability_match_cfg = rx_cfg_reg; | |
4604 | } | |
4605 | } | |
4606 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
4607 | ap->ack_match = 1; | |
4608 | else | |
4609 | ap->ack_match = 0; | |
4610 | ||
4611 | ap->idle_match = 0; | |
4612 | } else { | |
4613 | ap->idle_match = 1; | |
4614 | ap->ability_match_cfg = 0; | |
4615 | ap->ability_match_count = 0; | |
4616 | ap->ability_match = 0; | |
4617 | ap->ack_match = 0; | |
4618 | ||
4619 | rx_cfg_reg = 0; | |
4620 | } | |
4621 | ||
4622 | ap->rxconfig = rx_cfg_reg; | |
4623 | ret = ANEG_OK; | |
4624 | ||
33f401ae | 4625 | switch (ap->state) { |
1da177e4 LT |
4626 | case ANEG_STATE_UNKNOWN: |
4627 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
4628 | ap->state = ANEG_STATE_AN_ENABLE; | |
4629 | ||
4630 | /* fallthru */ | |
4631 | case ANEG_STATE_AN_ENABLE: | |
4632 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
4633 | if (ap->flags & MR_AN_ENABLE) { | |
4634 | ap->link_time = 0; | |
4635 | ap->cur_time = 0; | |
4636 | ap->ability_match_cfg = 0; | |
4637 | ap->ability_match_count = 0; | |
4638 | ap->ability_match = 0; | |
4639 | ap->idle_match = 0; | |
4640 | ap->ack_match = 0; | |
4641 | ||
4642 | ap->state = ANEG_STATE_RESTART_INIT; | |
4643 | } else { | |
4644 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
4645 | } | |
4646 | break; | |
4647 | ||
4648 | case ANEG_STATE_RESTART_INIT: | |
4649 | ap->link_time = ap->cur_time; | |
4650 | ap->flags &= ~(MR_NP_LOADED); | |
4651 | ap->txconfig = 0; | |
4652 | tw32(MAC_TX_AUTO_NEG, 0); | |
4653 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4654 | tw32_f(MAC_MODE, tp->mac_mode); | |
4655 | udelay(40); | |
4656 | ||
4657 | ret = ANEG_TIMER_ENAB; | |
4658 | ap->state = ANEG_STATE_RESTART; | |
4659 | ||
4660 | /* fallthru */ | |
4661 | case ANEG_STATE_RESTART: | |
4662 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 4663 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 4664 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 4665 | else |
1da177e4 | 4666 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
4667 | break; |
4668 | ||
4669 | case ANEG_STATE_DISABLE_LINK_OK: | |
4670 | ret = ANEG_DONE; | |
4671 | break; | |
4672 | ||
4673 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
4674 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
4675 | ap->txconfig = ANEG_CFG_FD; |
4676 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
4677 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4678 | ap->txconfig |= ANEG_CFG_PS1; | |
4679 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4680 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
4681 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
4682 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4683 | tw32_f(MAC_MODE, tp->mac_mode); | |
4684 | udelay(40); | |
4685 | ||
4686 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
4687 | break; | |
4688 | ||
4689 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 4690 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 4691 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
4692 | break; |
4693 | ||
4694 | case ANEG_STATE_ACK_DETECT_INIT: | |
4695 | ap->txconfig |= ANEG_CFG_ACK; | |
4696 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
4697 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4698 | tw32_f(MAC_MODE, tp->mac_mode); | |
4699 | udelay(40); | |
4700 | ||
4701 | ap->state = ANEG_STATE_ACK_DETECT; | |
4702 | ||
4703 | /* fallthru */ | |
4704 | case ANEG_STATE_ACK_DETECT: | |
4705 | if (ap->ack_match != 0) { | |
4706 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
4707 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
4708 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
4709 | } else { | |
4710 | ap->state = ANEG_STATE_AN_ENABLE; | |
4711 | } | |
4712 | } else if (ap->ability_match != 0 && | |
4713 | ap->rxconfig == 0) { | |
4714 | ap->state = ANEG_STATE_AN_ENABLE; | |
4715 | } | |
4716 | break; | |
4717 | ||
4718 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
4719 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
4720 | ret = ANEG_FAILED; | |
4721 | break; | |
4722 | } | |
4723 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
4724 | MR_LP_ADV_HALF_DUPLEX | | |
4725 | MR_LP_ADV_SYM_PAUSE | | |
4726 | MR_LP_ADV_ASYM_PAUSE | | |
4727 | MR_LP_ADV_REMOTE_FAULT1 | | |
4728 | MR_LP_ADV_REMOTE_FAULT2 | | |
4729 | MR_LP_ADV_NEXT_PAGE | | |
4730 | MR_TOGGLE_RX | | |
4731 | MR_NP_RX); | |
4732 | if (ap->rxconfig & ANEG_CFG_FD) | |
4733 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
4734 | if (ap->rxconfig & ANEG_CFG_HD) | |
4735 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
4736 | if (ap->rxconfig & ANEG_CFG_PS1) | |
4737 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
4738 | if (ap->rxconfig & ANEG_CFG_PS2) | |
4739 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
4740 | if (ap->rxconfig & ANEG_CFG_RF1) | |
4741 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
4742 | if (ap->rxconfig & ANEG_CFG_RF2) | |
4743 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
4744 | if (ap->rxconfig & ANEG_CFG_NP) | |
4745 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
4746 | ||
4747 | ap->link_time = ap->cur_time; | |
4748 | ||
4749 | ap->flags ^= (MR_TOGGLE_TX); | |
4750 | if (ap->rxconfig & 0x0008) | |
4751 | ap->flags |= MR_TOGGLE_RX; | |
4752 | if (ap->rxconfig & ANEG_CFG_NP) | |
4753 | ap->flags |= MR_NP_RX; | |
4754 | ap->flags |= MR_PAGE_RX; | |
4755 | ||
4756 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
4757 | ret = ANEG_TIMER_ENAB; | |
4758 | break; | |
4759 | ||
4760 | case ANEG_STATE_COMPLETE_ACK: | |
4761 | if (ap->ability_match != 0 && | |
4762 | ap->rxconfig == 0) { | |
4763 | ap->state = ANEG_STATE_AN_ENABLE; | |
4764 | break; | |
4765 | } | |
4766 | delta = ap->cur_time - ap->link_time; | |
4767 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
4768 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
4769 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
4770 | } else { | |
4771 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
4772 | !(ap->flags & MR_NP_RX)) { | |
4773 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
4774 | } else { | |
4775 | ret = ANEG_FAILED; | |
4776 | } | |
4777 | } | |
4778 | } | |
4779 | break; | |
4780 | ||
4781 | case ANEG_STATE_IDLE_DETECT_INIT: | |
4782 | ap->link_time = ap->cur_time; | |
4783 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
4784 | tw32_f(MAC_MODE, tp->mac_mode); | |
4785 | udelay(40); | |
4786 | ||
4787 | ap->state = ANEG_STATE_IDLE_DETECT; | |
4788 | ret = ANEG_TIMER_ENAB; | |
4789 | break; | |
4790 | ||
4791 | case ANEG_STATE_IDLE_DETECT: | |
4792 | if (ap->ability_match != 0 && | |
4793 | ap->rxconfig == 0) { | |
4794 | ap->state = ANEG_STATE_AN_ENABLE; | |
4795 | break; | |
4796 | } | |
4797 | delta = ap->cur_time - ap->link_time; | |
4798 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
4799 | /* XXX another gem from the Broadcom driver :( */ | |
4800 | ap->state = ANEG_STATE_LINK_OK; | |
4801 | } | |
4802 | break; | |
4803 | ||
4804 | case ANEG_STATE_LINK_OK: | |
4805 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
4806 | ret = ANEG_DONE; | |
4807 | break; | |
4808 | ||
4809 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
4810 | /* ??? unimplemented */ | |
4811 | break; | |
4812 | ||
4813 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
4814 | /* ??? unimplemented */ | |
4815 | break; | |
4816 | ||
4817 | default: | |
4818 | ret = ANEG_FAILED; | |
4819 | break; | |
855e1111 | 4820 | } |
1da177e4 LT |
4821 | |
4822 | return ret; | |
4823 | } | |
4824 | ||
5be73b47 | 4825 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
4826 | { |
4827 | int res = 0; | |
4828 | struct tg3_fiber_aneginfo aninfo; | |
4829 | int status = ANEG_FAILED; | |
4830 | unsigned int tick; | |
4831 | u32 tmp; | |
4832 | ||
4833 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4834 | ||
4835 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
4836 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
4837 | udelay(40); | |
4838 | ||
4839 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
4840 | udelay(40); | |
4841 | ||
4842 | memset(&aninfo, 0, sizeof(aninfo)); | |
4843 | aninfo.flags |= MR_AN_ENABLE; | |
4844 | aninfo.state = ANEG_STATE_UNKNOWN; | |
4845 | aninfo.cur_time = 0; | |
4846 | tick = 0; | |
4847 | while (++tick < 195000) { | |
4848 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
4849 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
4850 | break; | |
4851 | ||
4852 | udelay(1); | |
4853 | } | |
4854 | ||
4855 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
4856 | tw32_f(MAC_MODE, tp->mac_mode); | |
4857 | udelay(40); | |
4858 | ||
5be73b47 MC |
4859 | *txflags = aninfo.txconfig; |
4860 | *rxflags = aninfo.flags; | |
1da177e4 LT |
4861 | |
4862 | if (status == ANEG_DONE && | |
4863 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
4864 | MR_LP_ADV_FULL_DUPLEX))) | |
4865 | res = 1; | |
4866 | ||
4867 | return res; | |
4868 | } | |
4869 | ||
4870 | static void tg3_init_bcm8002(struct tg3 *tp) | |
4871 | { | |
4872 | u32 mac_status = tr32(MAC_STATUS); | |
4873 | int i; | |
4874 | ||
4875 | /* Reset when initting first time or we have a link. */ | |
63c3a66f | 4876 | if (tg3_flag(tp, INIT_COMPLETE) && |
1da177e4 LT |
4877 | !(mac_status & MAC_STATUS_PCS_SYNCED)) |
4878 | return; | |
4879 | ||
4880 | /* Set PLL lock range. */ | |
4881 | tg3_writephy(tp, 0x16, 0x8007); | |
4882 | ||
4883 | /* SW reset */ | |
4884 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
4885 | ||
4886 | /* Wait for reset to complete. */ | |
4887 | /* XXX schedule_timeout() ... */ | |
4888 | for (i = 0; i < 500; i++) | |
4889 | udelay(10); | |
4890 | ||
4891 | /* Config mode; select PMA/Ch 1 regs. */ | |
4892 | tg3_writephy(tp, 0x10, 0x8411); | |
4893 | ||
4894 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
4895 | tg3_writephy(tp, 0x11, 0x0a10); | |
4896 | ||
4897 | tg3_writephy(tp, 0x18, 0x00a0); | |
4898 | tg3_writephy(tp, 0x16, 0x41ff); | |
4899 | ||
4900 | /* Assert and deassert POR. */ | |
4901 | tg3_writephy(tp, 0x13, 0x0400); | |
4902 | udelay(40); | |
4903 | tg3_writephy(tp, 0x13, 0x0000); | |
4904 | ||
4905 | tg3_writephy(tp, 0x11, 0x0a50); | |
4906 | udelay(40); | |
4907 | tg3_writephy(tp, 0x11, 0x0a10); | |
4908 | ||
4909 | /* Wait for signal to stabilize */ | |
4910 | /* XXX schedule_timeout() ... */ | |
4911 | for (i = 0; i < 15000; i++) | |
4912 | udelay(10); | |
4913 | ||
4914 | /* Deselect the channel register so we can read the PHYID | |
4915 | * later. | |
4916 | */ | |
4917 | tg3_writephy(tp, 0x10, 0x8011); | |
4918 | } | |
4919 | ||
4920 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
4921 | { | |
82cd3d11 | 4922 | u16 flowctrl; |
1da177e4 LT |
4923 | u32 sg_dig_ctrl, sg_dig_status; |
4924 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
4925 | int workaround, port_a; | |
4926 | int current_link_up; | |
4927 | ||
4928 | serdes_cfg = 0; | |
4929 | expected_sg_dig_ctrl = 0; | |
4930 | workaround = 0; | |
4931 | port_a = 1; | |
4932 | current_link_up = 0; | |
4933 | ||
4934 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
4935 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
4936 | workaround = 1; | |
4937 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
4938 | port_a = 0; | |
4939 | ||
4940 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
4941 | /* preserve bits 20-23 for voltage regulator */ | |
4942 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
4943 | } | |
4944 | ||
4945 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
4946 | ||
4947 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 4948 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
4949 | if (workaround) { |
4950 | u32 val = serdes_cfg; | |
4951 | ||
4952 | if (port_a) | |
4953 | val |= 0xc010000; | |
4954 | else | |
4955 | val |= 0x4010000; | |
4956 | tw32_f(MAC_SERDES_CFG, val); | |
4957 | } | |
c98f6e3b MC |
4958 | |
4959 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
4960 | } |
4961 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
4962 | tg3_setup_flow_control(tp, 0, 0); | |
4963 | current_link_up = 1; | |
4964 | } | |
4965 | goto out; | |
4966 | } | |
4967 | ||
4968 | /* Want auto-negotiation. */ | |
c98f6e3b | 4969 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 4970 | |
82cd3d11 MC |
4971 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
4972 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4973 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
4974 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4975 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
4976 | |
4977 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 4978 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
4979 | tp->serdes_counter && |
4980 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
4981 | MAC_STATUS_RCVD_CFG)) == | |
4982 | MAC_STATUS_PCS_SYNCED)) { | |
4983 | tp->serdes_counter--; | |
4984 | current_link_up = 1; | |
4985 | goto out; | |
4986 | } | |
4987 | restart_autoneg: | |
1da177e4 LT |
4988 | if (workaround) |
4989 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 4990 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
4991 | udelay(5); |
4992 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
4993 | ||
3d3ebe74 | 4994 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 4995 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4996 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
4997 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 4998 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
4999 | mac_status = tr32(MAC_STATUS); |
5000 | ||
c98f6e3b | 5001 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 5002 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
5003 | u32 local_adv = 0, remote_adv = 0; |
5004 | ||
5005 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
5006 | local_adv |= ADVERTISE_1000XPAUSE; | |
5007 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
5008 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 5009 | |
c98f6e3b | 5010 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 5011 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 5012 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 5013 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 | 5014 | |
859edb26 MC |
5015 | tp->link_config.rmt_adv = |
5016 | mii_adv_to_ethtool_adv_x(remote_adv); | |
5017 | ||
1da177e4 LT |
5018 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
5019 | current_link_up = 1; | |
3d3ebe74 | 5020 | tp->serdes_counter = 0; |
f07e9af3 | 5021 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 5022 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
5023 | if (tp->serdes_counter) |
5024 | tp->serdes_counter--; | |
1da177e4 LT |
5025 | else { |
5026 | if (workaround) { | |
5027 | u32 val = serdes_cfg; | |
5028 | ||
5029 | if (port_a) | |
5030 | val |= 0xc010000; | |
5031 | else | |
5032 | val |= 0x4010000; | |
5033 | ||
5034 | tw32_f(MAC_SERDES_CFG, val); | |
5035 | } | |
5036 | ||
c98f6e3b | 5037 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
5038 | udelay(40); |
5039 | ||
5040 | /* Link parallel detection - link is up */ | |
5041 | /* only if we have PCS_SYNC and not */ | |
5042 | /* receiving config code words */ | |
5043 | mac_status = tr32(MAC_STATUS); | |
5044 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
5045 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
5046 | tg3_setup_flow_control(tp, 0, 0); | |
5047 | current_link_up = 1; | |
f07e9af3 MC |
5048 | tp->phy_flags |= |
5049 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
5050 | tp->serdes_counter = |
5051 | SERDES_PARALLEL_DET_TIMEOUT; | |
5052 | } else | |
5053 | goto restart_autoneg; | |
1da177e4 LT |
5054 | } |
5055 | } | |
3d3ebe74 MC |
5056 | } else { |
5057 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 5058 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
5059 | } |
5060 | ||
5061 | out: | |
5062 | return current_link_up; | |
5063 | } | |
5064 | ||
5065 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
5066 | { | |
5067 | int current_link_up = 0; | |
5068 | ||
5cf64b8a | 5069 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 5070 | goto out; |
1da177e4 LT |
5071 | |
5072 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 5073 | u32 txflags, rxflags; |
1da177e4 | 5074 | int i; |
6aa20a22 | 5075 | |
5be73b47 MC |
5076 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
5077 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 5078 | |
5be73b47 MC |
5079 | if (txflags & ANEG_CFG_PS1) |
5080 | local_adv |= ADVERTISE_1000XPAUSE; | |
5081 | if (txflags & ANEG_CFG_PS2) | |
5082 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
5083 | ||
5084 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
5085 | remote_adv |= LPA_1000XPAUSE; | |
5086 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
5087 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 | 5088 | |
859edb26 MC |
5089 | tp->link_config.rmt_adv = |
5090 | mii_adv_to_ethtool_adv_x(remote_adv); | |
5091 | ||
1da177e4 LT |
5092 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
5093 | ||
1da177e4 LT |
5094 | current_link_up = 1; |
5095 | } | |
5096 | for (i = 0; i < 30; i++) { | |
5097 | udelay(20); | |
5098 | tw32_f(MAC_STATUS, | |
5099 | (MAC_STATUS_SYNC_CHANGED | | |
5100 | MAC_STATUS_CFG_CHANGED)); | |
5101 | udelay(40); | |
5102 | if ((tr32(MAC_STATUS) & | |
5103 | (MAC_STATUS_SYNC_CHANGED | | |
5104 | MAC_STATUS_CFG_CHANGED)) == 0) | |
5105 | break; | |
5106 | } | |
5107 | ||
5108 | mac_status = tr32(MAC_STATUS); | |
5109 | if (current_link_up == 0 && | |
5110 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
5111 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
5112 | current_link_up = 1; | |
5113 | } else { | |
5be73b47 MC |
5114 | tg3_setup_flow_control(tp, 0, 0); |
5115 | ||
1da177e4 LT |
5116 | /* Forcing 1000FD link up. */ |
5117 | current_link_up = 1; | |
1da177e4 LT |
5118 | |
5119 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
5120 | udelay(40); | |
e8f3f6ca MC |
5121 | |
5122 | tw32_f(MAC_MODE, tp->mac_mode); | |
5123 | udelay(40); | |
1da177e4 LT |
5124 | } |
5125 | ||
5126 | out: | |
5127 | return current_link_up; | |
5128 | } | |
5129 | ||
5130 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
5131 | { | |
5132 | u32 orig_pause_cfg; | |
5133 | u16 orig_active_speed; | |
5134 | u8 orig_active_duplex; | |
5135 | u32 mac_status; | |
5136 | int current_link_up; | |
5137 | int i; | |
5138 | ||
8d018621 | 5139 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
5140 | orig_active_speed = tp->link_config.active_speed; |
5141 | orig_active_duplex = tp->link_config.active_duplex; | |
5142 | ||
63c3a66f | 5143 | if (!tg3_flag(tp, HW_AUTONEG) && |
f4a46d1f | 5144 | tp->link_up && |
63c3a66f | 5145 | tg3_flag(tp, INIT_COMPLETE)) { |
1da177e4 LT |
5146 | mac_status = tr32(MAC_STATUS); |
5147 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
5148 | MAC_STATUS_SIGNAL_DET | | |
5149 | MAC_STATUS_CFG_CHANGED | | |
5150 | MAC_STATUS_RCVD_CFG); | |
5151 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
5152 | MAC_STATUS_SIGNAL_DET)) { | |
5153 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
5154 | MAC_STATUS_CFG_CHANGED)); | |
5155 | return 0; | |
5156 | } | |
5157 | } | |
5158 | ||
5159 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
5160 | ||
5161 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
5162 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
5163 | tw32_f(MAC_MODE, tp->mac_mode); | |
5164 | udelay(40); | |
5165 | ||
79eb6904 | 5166 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
5167 | tg3_init_bcm8002(tp); |
5168 | ||
5169 | /* Enable link change event even when serdes polling. */ | |
5170 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
5171 | udelay(40); | |
5172 | ||
5173 | current_link_up = 0; | |
859edb26 | 5174 | tp->link_config.rmt_adv = 0; |
1da177e4 LT |
5175 | mac_status = tr32(MAC_STATUS); |
5176 | ||
63c3a66f | 5177 | if (tg3_flag(tp, HW_AUTONEG)) |
1da177e4 LT |
5178 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); |
5179 | else | |
5180 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
5181 | ||
898a56f8 | 5182 | tp->napi[0].hw_status->status = |
1da177e4 | 5183 | (SD_STATUS_UPDATED | |
898a56f8 | 5184 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
5185 | |
5186 | for (i = 0; i < 100; i++) { | |
5187 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
5188 | MAC_STATUS_CFG_CHANGED)); | |
5189 | udelay(5); | |
5190 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
5191 | MAC_STATUS_CFG_CHANGED | |
5192 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
5193 | break; |
5194 | } | |
5195 | ||
5196 | mac_status = tr32(MAC_STATUS); | |
5197 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
5198 | current_link_up = 0; | |
3d3ebe74 MC |
5199 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
5200 | tp->serdes_counter == 0) { | |
1da177e4 LT |
5201 | tw32_f(MAC_MODE, (tp->mac_mode | |
5202 | MAC_MODE_SEND_CONFIGS)); | |
5203 | udelay(1); | |
5204 | tw32_f(MAC_MODE, tp->mac_mode); | |
5205 | } | |
5206 | } | |
5207 | ||
5208 | if (current_link_up == 1) { | |
5209 | tp->link_config.active_speed = SPEED_1000; | |
5210 | tp->link_config.active_duplex = DUPLEX_FULL; | |
5211 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
5212 | LED_CTRL_LNKLED_OVERRIDE | | |
5213 | LED_CTRL_1000MBPS_ON)); | |
5214 | } else { | |
e740522e MC |
5215 | tp->link_config.active_speed = SPEED_UNKNOWN; |
5216 | tp->link_config.active_duplex = DUPLEX_UNKNOWN; | |
1da177e4 LT |
5217 | tw32(MAC_LED_CTRL, (tp->led_ctrl | |
5218 | LED_CTRL_LNKLED_OVERRIDE | | |
5219 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
5220 | } | |
5221 | ||
f4a46d1f | 5222 | if (!tg3_test_and_report_link_chg(tp, current_link_up)) { |
8d018621 | 5223 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
5224 | if (orig_pause_cfg != now_pause_cfg || |
5225 | orig_active_speed != tp->link_config.active_speed || | |
5226 | orig_active_duplex != tp->link_config.active_duplex) | |
5227 | tg3_link_report(tp); | |
5228 | } | |
5229 | ||
5230 | return 0; | |
5231 | } | |
5232 | ||
747e8f8b MC |
5233 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
5234 | { | |
5235 | int current_link_up, err = 0; | |
5236 | u32 bmsr, bmcr; | |
5237 | u16 current_speed; | |
5238 | u8 current_duplex; | |
ef167e27 | 5239 | u32 local_adv, remote_adv; |
747e8f8b MC |
5240 | |
5241 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
5242 | tw32_f(MAC_MODE, tp->mac_mode); | |
5243 | udelay(40); | |
5244 | ||
5245 | tw32(MAC_EVENT, 0); | |
5246 | ||
5247 | tw32_f(MAC_STATUS, | |
5248 | (MAC_STATUS_SYNC_CHANGED | | |
5249 | MAC_STATUS_CFG_CHANGED | | |
5250 | MAC_STATUS_MI_COMPLETION | | |
5251 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5252 | udelay(40); | |
5253 | ||
5254 | if (force_reset) | |
5255 | tg3_phy_reset(tp); | |
5256 | ||
5257 | current_link_up = 0; | |
e740522e MC |
5258 | current_speed = SPEED_UNKNOWN; |
5259 | current_duplex = DUPLEX_UNKNOWN; | |
859edb26 | 5260 | tp->link_config.rmt_adv = 0; |
747e8f8b MC |
5261 | |
5262 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
5263 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
5264 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
5265 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
5266 | bmsr |= BMSR_LSTATUS; | |
5267 | else | |
5268 | bmsr &= ~BMSR_LSTATUS; | |
5269 | } | |
747e8f8b MC |
5270 | |
5271 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
5272 | ||
5273 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 5274 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
5275 | /* do nothing, just check for link up at the end */ |
5276 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
28011cf1 | 5277 | u32 adv, newadv; |
747e8f8b MC |
5278 | |
5279 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
28011cf1 MC |
5280 | newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | |
5281 | ADVERTISE_1000XPAUSE | | |
5282 | ADVERTISE_1000XPSE_ASYM | | |
5283 | ADVERTISE_SLCT); | |
747e8f8b | 5284 | |
28011cf1 | 5285 | newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
37f07023 | 5286 | newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); |
747e8f8b | 5287 | |
28011cf1 MC |
5288 | if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) { |
5289 | tg3_writephy(tp, MII_ADVERTISE, newadv); | |
747e8f8b MC |
5290 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; |
5291 | tg3_writephy(tp, MII_BMCR, bmcr); | |
5292 | ||
5293 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 5294 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 5295 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5296 | |
5297 | return err; | |
5298 | } | |
5299 | } else { | |
5300 | u32 new_bmcr; | |
5301 | ||
5302 | bmcr &= ~BMCR_SPEED1000; | |
5303 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
5304 | ||
5305 | if (tp->link_config.duplex == DUPLEX_FULL) | |
5306 | new_bmcr |= BMCR_FULLDPLX; | |
5307 | ||
5308 | if (new_bmcr != bmcr) { | |
5309 | /* BMCR_SPEED1000 is a reserved bit that needs | |
5310 | * to be set on write. | |
5311 | */ | |
5312 | new_bmcr |= BMCR_SPEED1000; | |
5313 | ||
5314 | /* Force a linkdown */ | |
f4a46d1f | 5315 | if (tp->link_up) { |
747e8f8b MC |
5316 | u32 adv; |
5317 | ||
5318 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
5319 | adv &= ~(ADVERTISE_1000XFULL | | |
5320 | ADVERTISE_1000XHALF | | |
5321 | ADVERTISE_SLCT); | |
5322 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
5323 | tg3_writephy(tp, MII_BMCR, bmcr | | |
5324 | BMCR_ANRESTART | | |
5325 | BMCR_ANENABLE); | |
5326 | udelay(10); | |
f4a46d1f | 5327 | tg3_carrier_off(tp); |
747e8f8b MC |
5328 | } |
5329 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
5330 | bmcr = new_bmcr; | |
5331 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
5332 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
5333 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
5334 | ASIC_REV_5714) { | |
5335 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
5336 | bmsr |= BMSR_LSTATUS; | |
5337 | else | |
5338 | bmsr &= ~BMSR_LSTATUS; | |
5339 | } | |
f07e9af3 | 5340 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5341 | } |
5342 | } | |
5343 | ||
5344 | if (bmsr & BMSR_LSTATUS) { | |
5345 | current_speed = SPEED_1000; | |
5346 | current_link_up = 1; | |
5347 | if (bmcr & BMCR_FULLDPLX) | |
5348 | current_duplex = DUPLEX_FULL; | |
5349 | else | |
5350 | current_duplex = DUPLEX_HALF; | |
5351 | ||
ef167e27 MC |
5352 | local_adv = 0; |
5353 | remote_adv = 0; | |
5354 | ||
747e8f8b | 5355 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 5356 | u32 common; |
747e8f8b MC |
5357 | |
5358 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
5359 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
5360 | common = local_adv & remote_adv; | |
5361 | if (common & (ADVERTISE_1000XHALF | | |
5362 | ADVERTISE_1000XFULL)) { | |
5363 | if (common & ADVERTISE_1000XFULL) | |
5364 | current_duplex = DUPLEX_FULL; | |
5365 | else | |
5366 | current_duplex = DUPLEX_HALF; | |
859edb26 MC |
5367 | |
5368 | tp->link_config.rmt_adv = | |
5369 | mii_adv_to_ethtool_adv_x(remote_adv); | |
63c3a66f | 5370 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
57d8b880 | 5371 | /* Link is up via parallel detect */ |
859a5887 | 5372 | } else { |
747e8f8b | 5373 | current_link_up = 0; |
859a5887 | 5374 | } |
747e8f8b MC |
5375 | } |
5376 | } | |
5377 | ||
ef167e27 MC |
5378 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
5379 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
5380 | ||
747e8f8b MC |
5381 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
5382 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
5383 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
5384 | ||
5385 | tw32_f(MAC_MODE, tp->mac_mode); | |
5386 | udelay(40); | |
5387 | ||
5388 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
5389 | ||
5390 | tp->link_config.active_speed = current_speed; | |
5391 | tp->link_config.active_duplex = current_duplex; | |
5392 | ||
f4a46d1f | 5393 | tg3_test_and_report_link_chg(tp, current_link_up); |
747e8f8b MC |
5394 | return err; |
5395 | } | |
5396 | ||
5397 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
5398 | { | |
3d3ebe74 | 5399 | if (tp->serdes_counter) { |
747e8f8b | 5400 | /* Give autoneg time to complete. */ |
3d3ebe74 | 5401 | tp->serdes_counter--; |
747e8f8b MC |
5402 | return; |
5403 | } | |
c6cdf436 | 5404 | |
f4a46d1f | 5405 | if (!tp->link_up && |
747e8f8b MC |
5406 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { |
5407 | u32 bmcr; | |
5408 | ||
5409 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
5410 | if (bmcr & BMCR_ANENABLE) { | |
5411 | u32 phy1, phy2; | |
5412 | ||
5413 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
5414 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
5415 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
5416 | |
5417 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
5418 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
5419 | MII_TG3_DSP_EXP1_INT_STAT); | |
5420 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
5421 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
5422 | |
5423 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
5424 | /* We have signal detect and not receiving | |
5425 | * config code words, link is up by parallel | |
5426 | * detection. | |
5427 | */ | |
5428 | ||
5429 | bmcr &= ~BMCR_ANENABLE; | |
5430 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
5431 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 5432 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5433 | } |
5434 | } | |
f4a46d1f | 5435 | } else if (tp->link_up && |
859a5887 | 5436 | (tp->link_config.autoneg == AUTONEG_ENABLE) && |
f07e9af3 | 5437 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
5438 | u32 phy2; |
5439 | ||
5440 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
5441 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
5442 | MII_TG3_DSP_EXP1_INT_STAT); | |
5443 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
5444 | if (phy2 & 0x20) { |
5445 | u32 bmcr; | |
5446 | ||
5447 | /* Config code words received, turn on autoneg. */ | |
5448 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
5449 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
5450 | ||
f07e9af3 | 5451 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5452 | |
5453 | } | |
5454 | } | |
5455 | } | |
5456 | ||
1da177e4 LT |
5457 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
5458 | { | |
f2096f94 | 5459 | u32 val; |
1da177e4 LT |
5460 | int err; |
5461 | ||
f07e9af3 | 5462 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 5463 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 5464 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 5465 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 5466 | else |
1da177e4 | 5467 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 5468 | |
bcb37f6c | 5469 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
f2096f94 | 5470 | u32 scale; |
aa6c91fe MC |
5471 | |
5472 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
5473 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
5474 | scale = 65; | |
5475 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
5476 | scale = 6; | |
5477 | else | |
5478 | scale = 12; | |
5479 | ||
5480 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
5481 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
5482 | tw32(GRC_MISC_CFG, val); | |
5483 | } | |
5484 | ||
f2096f94 MC |
5485 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
5486 | (6 << TX_LENGTHS_IPG_SHIFT); | |
5487 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
5488 | val |= tr32(MAC_TX_LENGTHS) & | |
5489 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
5490 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
5491 | ||
1da177e4 LT |
5492 | if (tp->link_config.active_speed == SPEED_1000 && |
5493 | tp->link_config.active_duplex == DUPLEX_HALF) | |
f2096f94 MC |
5494 | tw32(MAC_TX_LENGTHS, val | |
5495 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 5496 | else |
f2096f94 MC |
5497 | tw32(MAC_TX_LENGTHS, val | |
5498 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 5499 | |
63c3a66f | 5500 | if (!tg3_flag(tp, 5705_PLUS)) { |
f4a46d1f | 5501 | if (tp->link_up) { |
1da177e4 | 5502 | tw32(HOSTCC_STAT_COAL_TICKS, |
15f9850d | 5503 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
5504 | } else { |
5505 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
5506 | } | |
5507 | } | |
5508 | ||
63c3a66f | 5509 | if (tg3_flag(tp, ASPM_WORKAROUND)) { |
f2096f94 | 5510 | val = tr32(PCIE_PWR_MGMT_THRESH); |
f4a46d1f | 5511 | if (!tp->link_up) |
8ed5d97e MC |
5512 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | |
5513 | tp->pwrmgmt_thresh; | |
5514 | else | |
5515 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
5516 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
5517 | } | |
5518 | ||
1da177e4 LT |
5519 | return err; |
5520 | } | |
5521 | ||
7d41e49a MC |
5522 | /* tp->lock must be held */ |
5523 | static u64 tg3_refclk_read(struct tg3 *tp) | |
5524 | { | |
5525 | u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB); | |
5526 | return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32; | |
5527 | } | |
5528 | ||
be947307 MC |
5529 | /* tp->lock must be held */ |
5530 | static void tg3_refclk_write(struct tg3 *tp, u64 newval) | |
5531 | { | |
5532 | tw32(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_STOP); | |
5533 | tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff); | |
5534 | tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32); | |
5535 | tw32_f(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_RESUME); | |
5536 | } | |
5537 | ||
7d41e49a MC |
5538 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync); |
5539 | static inline void tg3_full_unlock(struct tg3 *tp); | |
5540 | static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info) | |
5541 | { | |
5542 | struct tg3 *tp = netdev_priv(dev); | |
5543 | ||
5544 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
5545 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
5546 | SOF_TIMESTAMPING_SOFTWARE | | |
5547 | SOF_TIMESTAMPING_TX_HARDWARE | | |
5548 | SOF_TIMESTAMPING_RX_HARDWARE | | |
5549 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
5550 | ||
5551 | if (tp->ptp_clock) | |
5552 | info->phc_index = ptp_clock_index(tp->ptp_clock); | |
5553 | else | |
5554 | info->phc_index = -1; | |
5555 | ||
5556 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); | |
5557 | ||
5558 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
5559 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | | |
5560 | (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | | |
5561 | (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); | |
5562 | return 0; | |
5563 | } | |
5564 | ||
5565 | static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) | |
5566 | { | |
5567 | struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); | |
5568 | bool neg_adj = false; | |
5569 | u32 correction = 0; | |
5570 | ||
5571 | if (ppb < 0) { | |
5572 | neg_adj = true; | |
5573 | ppb = -ppb; | |
5574 | } | |
5575 | ||
5576 | /* Frequency adjustment is performed using hardware with a 24 bit | |
5577 | * accumulator and a programmable correction value. On each clk, the | |
5578 | * correction value gets added to the accumulator and when it | |
5579 | * overflows, the time counter is incremented/decremented. | |
5580 | * | |
5581 | * So conversion from ppb to correction value is | |
5582 | * ppb * (1 << 24) / 1000000000 | |
5583 | */ | |
5584 | correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) & | |
5585 | TG3_EAV_REF_CLK_CORRECT_MASK; | |
5586 | ||
5587 | tg3_full_lock(tp, 0); | |
5588 | ||
5589 | if (correction) | |
5590 | tw32(TG3_EAV_REF_CLK_CORRECT_CTL, | |
5591 | TG3_EAV_REF_CLK_CORRECT_EN | | |
5592 | (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction); | |
5593 | else | |
5594 | tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0); | |
5595 | ||
5596 | tg3_full_unlock(tp); | |
5597 | ||
5598 | return 0; | |
5599 | } | |
5600 | ||
5601 | static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
5602 | { | |
5603 | struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); | |
5604 | ||
5605 | tg3_full_lock(tp, 0); | |
5606 | tp->ptp_adjust += delta; | |
5607 | tg3_full_unlock(tp); | |
5608 | ||
5609 | return 0; | |
5610 | } | |
5611 | ||
5612 | static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts) | |
5613 | { | |
5614 | u64 ns; | |
5615 | u32 remainder; | |
5616 | struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); | |
5617 | ||
5618 | tg3_full_lock(tp, 0); | |
5619 | ns = tg3_refclk_read(tp); | |
5620 | ns += tp->ptp_adjust; | |
5621 | tg3_full_unlock(tp); | |
5622 | ||
5623 | ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); | |
5624 | ts->tv_nsec = remainder; | |
5625 | ||
5626 | return 0; | |
5627 | } | |
5628 | ||
5629 | static int tg3_ptp_settime(struct ptp_clock_info *ptp, | |
5630 | const struct timespec *ts) | |
5631 | { | |
5632 | u64 ns; | |
5633 | struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); | |
5634 | ||
5635 | ns = timespec_to_ns(ts); | |
5636 | ||
5637 | tg3_full_lock(tp, 0); | |
5638 | tg3_refclk_write(tp, ns); | |
5639 | tp->ptp_adjust = 0; | |
5640 | tg3_full_unlock(tp); | |
5641 | ||
5642 | return 0; | |
5643 | } | |
5644 | ||
5645 | static int tg3_ptp_enable(struct ptp_clock_info *ptp, | |
5646 | struct ptp_clock_request *rq, int on) | |
5647 | { | |
5648 | return -EOPNOTSUPP; | |
5649 | } | |
5650 | ||
5651 | static const struct ptp_clock_info tg3_ptp_caps = { | |
5652 | .owner = THIS_MODULE, | |
5653 | .name = "tg3 clock", | |
5654 | .max_adj = 250000000, | |
5655 | .n_alarm = 0, | |
5656 | .n_ext_ts = 0, | |
5657 | .n_per_out = 0, | |
5658 | .pps = 0, | |
5659 | .adjfreq = tg3_ptp_adjfreq, | |
5660 | .adjtime = tg3_ptp_adjtime, | |
5661 | .gettime = tg3_ptp_gettime, | |
5662 | .settime = tg3_ptp_settime, | |
5663 | .enable = tg3_ptp_enable, | |
5664 | }; | |
5665 | ||
be947307 MC |
5666 | /* tp->lock must be held */ |
5667 | static void tg3_ptp_init(struct tg3 *tp) | |
5668 | { | |
5669 | if (!tg3_flag(tp, PTP_CAPABLE)) | |
5670 | return; | |
5671 | ||
5672 | /* Initialize the hardware clock to the system time. */ | |
5673 | tg3_refclk_write(tp, ktime_to_ns(ktime_get_real())); | |
5674 | tp->ptp_adjust = 0; | |
7d41e49a | 5675 | tp->ptp_info = tg3_ptp_caps; |
be947307 MC |
5676 | } |
5677 | ||
5678 | /* tp->lock must be held */ | |
5679 | static void tg3_ptp_resume(struct tg3 *tp) | |
5680 | { | |
5681 | if (!tg3_flag(tp, PTP_CAPABLE)) | |
5682 | return; | |
5683 | ||
5684 | tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); | |
5685 | tp->ptp_adjust = 0; | |
5686 | } | |
5687 | ||
5688 | static void tg3_ptp_fini(struct tg3 *tp) | |
5689 | { | |
5690 | if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) | |
5691 | return; | |
5692 | ||
7d41e49a | 5693 | ptp_clock_unregister(tp->ptp_clock); |
be947307 MC |
5694 | tp->ptp_clock = NULL; |
5695 | tp->ptp_adjust = 0; | |
5696 | } | |
5697 | ||
66cfd1bd MC |
5698 | static inline int tg3_irq_sync(struct tg3 *tp) |
5699 | { | |
5700 | return tp->irq_sync; | |
5701 | } | |
5702 | ||
97bd8e49 MC |
5703 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
5704 | { | |
5705 | int i; | |
5706 | ||
5707 | dst = (u32 *)((u8 *)dst + off); | |
5708 | for (i = 0; i < len; i += sizeof(u32)) | |
5709 | *dst++ = tr32(off + i); | |
5710 | } | |
5711 | ||
5712 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
5713 | { | |
5714 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
5715 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
5716 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
5717 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
5718 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
5719 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
5720 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
5721 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
5722 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
5723 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
5724 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
5725 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
5726 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
5727 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
5728 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
5729 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
5730 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
5731 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
5732 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
5733 | ||
63c3a66f | 5734 | if (tg3_flag(tp, SUPPORT_MSIX)) |
97bd8e49 MC |
5735 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); |
5736 | ||
5737 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
5738 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
5739 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
5740 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
5741 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
5742 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
5743 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
5744 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
5745 | ||
63c3a66f | 5746 | if (!tg3_flag(tp, 5705_PLUS)) { |
97bd8e49 MC |
5747 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); |
5748 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
5749 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
5750 | } | |
5751 | ||
5752 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
5753 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
5754 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
5755 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
5756 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
5757 | ||
63c3a66f | 5758 | if (tg3_flag(tp, NVRAM)) |
97bd8e49 MC |
5759 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); |
5760 | } | |
5761 | ||
5762 | static void tg3_dump_state(struct tg3 *tp) | |
5763 | { | |
5764 | int i; | |
5765 | u32 *regs; | |
5766 | ||
5767 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
5768 | if (!regs) { | |
5769 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
5770 | return; | |
5771 | } | |
5772 | ||
63c3a66f | 5773 | if (tg3_flag(tp, PCI_EXPRESS)) { |
97bd8e49 MC |
5774 | /* Read up to but not including private PCI registers */ |
5775 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
5776 | regs[i / sizeof(u32)] = tr32(i); | |
5777 | } else | |
5778 | tg3_dump_legacy_regs(tp, regs); | |
5779 | ||
5780 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
5781 | if (!regs[i + 0] && !regs[i + 1] && | |
5782 | !regs[i + 2] && !regs[i + 3]) | |
5783 | continue; | |
5784 | ||
5785 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
5786 | i * 4, | |
5787 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
5788 | } | |
5789 | ||
5790 | kfree(regs); | |
5791 | ||
5792 | for (i = 0; i < tp->irq_cnt; i++) { | |
5793 | struct tg3_napi *tnapi = &tp->napi[i]; | |
5794 | ||
5795 | /* SW status block */ | |
5796 | netdev_err(tp->dev, | |
5797 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
5798 | i, | |
5799 | tnapi->hw_status->status, | |
5800 | tnapi->hw_status->status_tag, | |
5801 | tnapi->hw_status->rx_jumbo_consumer, | |
5802 | tnapi->hw_status->rx_consumer, | |
5803 | tnapi->hw_status->rx_mini_consumer, | |
5804 | tnapi->hw_status->idx[0].rx_producer, | |
5805 | tnapi->hw_status->idx[0].tx_consumer); | |
5806 | ||
5807 | netdev_err(tp->dev, | |
5808 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
5809 | i, | |
5810 | tnapi->last_tag, tnapi->last_irq_tag, | |
5811 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
5812 | tnapi->rx_rcb_ptr, | |
5813 | tnapi->prodring.rx_std_prod_idx, | |
5814 | tnapi->prodring.rx_std_cons_idx, | |
5815 | tnapi->prodring.rx_jmb_prod_idx, | |
5816 | tnapi->prodring.rx_jmb_cons_idx); | |
5817 | } | |
5818 | } | |
5819 | ||
df3e6548 MC |
5820 | /* This is called whenever we suspect that the system chipset is re- |
5821 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
5822 | * is bogus tx completions. We try to recover by setting the | |
5823 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
5824 | * in the workqueue. | |
5825 | */ | |
5826 | static void tg3_tx_recover(struct tg3 *tp) | |
5827 | { | |
63c3a66f | 5828 | BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || |
df3e6548 MC |
5829 | tp->write32_tx_mbox == tg3_write_indirect_mbox); |
5830 | ||
5129c3a3 MC |
5831 | netdev_warn(tp->dev, |
5832 | "The system may be re-ordering memory-mapped I/O " | |
5833 | "cycles to the network device, attempting to recover. " | |
5834 | "Please report the problem to the driver maintainer " | |
5835 | "and include system chipset information.\n"); | |
df3e6548 MC |
5836 | |
5837 | spin_lock(&tp->lock); | |
63c3a66f | 5838 | tg3_flag_set(tp, TX_RECOVERY_PENDING); |
df3e6548 MC |
5839 | spin_unlock(&tp->lock); |
5840 | } | |
5841 | ||
f3f3f27e | 5842 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 5843 | { |
f65aac16 MC |
5844 | /* Tell compiler to fetch tx indices from memory. */ |
5845 | barrier(); | |
f3f3f27e MC |
5846 | return tnapi->tx_pending - |
5847 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
5848 | } |
5849 | ||
1da177e4 LT |
5850 | /* Tigon3 never reports partial packet sends. So we do not |
5851 | * need special logic to handle SKBs that have not had all | |
5852 | * of their frags sent yet, like SunGEM does. | |
5853 | */ | |
17375d25 | 5854 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 5855 | { |
17375d25 | 5856 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 5857 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 5858 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
5859 | struct netdev_queue *txq; |
5860 | int index = tnapi - tp->napi; | |
298376d3 | 5861 | unsigned int pkts_compl = 0, bytes_compl = 0; |
fe5f5787 | 5862 | |
63c3a66f | 5863 | if (tg3_flag(tp, ENABLE_TSS)) |
fe5f5787 MC |
5864 | index--; |
5865 | ||
5866 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
5867 | |
5868 | while (sw_idx != hw_idx) { | |
df8944cf | 5869 | struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 5870 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
5871 | int i, tx_bug = 0; |
5872 | ||
5873 | if (unlikely(skb == NULL)) { | |
5874 | tg3_tx_recover(tp); | |
5875 | return; | |
5876 | } | |
1da177e4 | 5877 | |
f4188d8a | 5878 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 5879 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
5880 | skb_headlen(skb), |
5881 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
5882 | |
5883 | ri->skb = NULL; | |
5884 | ||
e01ee14d MC |
5885 | while (ri->fragmented) { |
5886 | ri->fragmented = false; | |
5887 | sw_idx = NEXT_TX(sw_idx); | |
5888 | ri = &tnapi->tx_buffers[sw_idx]; | |
5889 | } | |
5890 | ||
1da177e4 LT |
5891 | sw_idx = NEXT_TX(sw_idx); |
5892 | ||
5893 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 5894 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
5895 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
5896 | tx_bug = 1; | |
f4188d8a AD |
5897 | |
5898 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 5899 | dma_unmap_addr(ri, mapping), |
9e903e08 | 5900 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
f4188d8a | 5901 | PCI_DMA_TODEVICE); |
e01ee14d MC |
5902 | |
5903 | while (ri->fragmented) { | |
5904 | ri->fragmented = false; | |
5905 | sw_idx = NEXT_TX(sw_idx); | |
5906 | ri = &tnapi->tx_buffers[sw_idx]; | |
5907 | } | |
5908 | ||
1da177e4 LT |
5909 | sw_idx = NEXT_TX(sw_idx); |
5910 | } | |
5911 | ||
298376d3 TH |
5912 | pkts_compl++; |
5913 | bytes_compl += skb->len; | |
5914 | ||
f47c11ee | 5915 | dev_kfree_skb(skb); |
df3e6548 MC |
5916 | |
5917 | if (unlikely(tx_bug)) { | |
5918 | tg3_tx_recover(tp); | |
5919 | return; | |
5920 | } | |
1da177e4 LT |
5921 | } |
5922 | ||
5cb917bc | 5923 | netdev_tx_completed_queue(txq, pkts_compl, bytes_compl); |
298376d3 | 5924 | |
f3f3f27e | 5925 | tnapi->tx_cons = sw_idx; |
1da177e4 | 5926 | |
1b2a7205 MC |
5927 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
5928 | * before checking for netif_queue_stopped(). Without the | |
5929 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
5930 | * will miss it and cause the queue to be stopped forever. | |
5931 | */ | |
5932 | smp_mb(); | |
5933 | ||
fe5f5787 | 5934 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 5935 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
5936 | __netif_tx_lock(txq, smp_processor_id()); |
5937 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 5938 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
5939 | netif_tx_wake_queue(txq); |
5940 | __netif_tx_unlock(txq); | |
51b91468 | 5941 | } |
1da177e4 LT |
5942 | } |
5943 | ||
8d4057a9 ED |
5944 | static void tg3_frag_free(bool is_frag, void *data) |
5945 | { | |
5946 | if (is_frag) | |
5947 | put_page(virt_to_head_page(data)); | |
5948 | else | |
5949 | kfree(data); | |
5950 | } | |
5951 | ||
9205fd9c | 5952 | static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
2b2cdb65 | 5953 | { |
8d4057a9 ED |
5954 | unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) + |
5955 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
5956 | ||
9205fd9c | 5957 | if (!ri->data) |
2b2cdb65 MC |
5958 | return; |
5959 | ||
4e5e4f0d | 5960 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 | 5961 | map_sz, PCI_DMA_FROMDEVICE); |
a1e8b307 | 5962 | tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); |
9205fd9c | 5963 | ri->data = NULL; |
2b2cdb65 MC |
5964 | } |
5965 | ||
8d4057a9 | 5966 | |
1da177e4 LT |
5967 | /* Returns size of skb allocated or < 0 on error. |
5968 | * | |
5969 | * We only need to fill in the address because the other members | |
5970 | * of the RX descriptor are invariant, see tg3_init_rings. | |
5971 | * | |
5972 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
5973 | * posting buffers we only dirty the first cache line of the RX | |
5974 | * descriptor (containing the address). Whereas for the RX status | |
5975 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
5976 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
5977 | */ | |
9205fd9c | 5978 | static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
8d4057a9 ED |
5979 | u32 opaque_key, u32 dest_idx_unmasked, |
5980 | unsigned int *frag_size) | |
1da177e4 LT |
5981 | { |
5982 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 5983 | struct ring_info *map; |
9205fd9c | 5984 | u8 *data; |
1da177e4 | 5985 | dma_addr_t mapping; |
9205fd9c | 5986 | int skb_size, data_size, dest_idx; |
1da177e4 | 5987 | |
1da177e4 LT |
5988 | switch (opaque_key) { |
5989 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 5990 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
5991 | desc = &tpr->rx_std[dest_idx]; |
5992 | map = &tpr->rx_std_buffers[dest_idx]; | |
9205fd9c | 5993 | data_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
5994 | break; |
5995 | ||
5996 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 5997 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 5998 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 5999 | map = &tpr->rx_jmb_buffers[dest_idx]; |
9205fd9c | 6000 | data_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
6001 | break; |
6002 | ||
6003 | default: | |
6004 | return -EINVAL; | |
855e1111 | 6005 | } |
1da177e4 LT |
6006 | |
6007 | /* Do not overwrite any of the map or rp information | |
6008 | * until we are sure we can commit to a new buffer. | |
6009 | * | |
6010 | * Callers depend upon this behavior and assume that | |
6011 | * we leave everything unchanged if we fail. | |
6012 | */ | |
9205fd9c ED |
6013 | skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + |
6014 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
a1e8b307 ED |
6015 | if (skb_size <= PAGE_SIZE) { |
6016 | data = netdev_alloc_frag(skb_size); | |
6017 | *frag_size = skb_size; | |
8d4057a9 ED |
6018 | } else { |
6019 | data = kmalloc(skb_size, GFP_ATOMIC); | |
6020 | *frag_size = 0; | |
6021 | } | |
9205fd9c | 6022 | if (!data) |
1da177e4 LT |
6023 | return -ENOMEM; |
6024 | ||
9205fd9c ED |
6025 | mapping = pci_map_single(tp->pdev, |
6026 | data + TG3_RX_OFFSET(tp), | |
6027 | data_size, | |
1da177e4 | 6028 | PCI_DMA_FROMDEVICE); |
8d4057a9 | 6029 | if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) { |
a1e8b307 | 6030 | tg3_frag_free(skb_size <= PAGE_SIZE, data); |
a21771dd MC |
6031 | return -EIO; |
6032 | } | |
1da177e4 | 6033 | |
9205fd9c | 6034 | map->data = data; |
4e5e4f0d | 6035 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 6036 | |
1da177e4 LT |
6037 | desc->addr_hi = ((u64)mapping >> 32); |
6038 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
6039 | ||
9205fd9c | 6040 | return data_size; |
1da177e4 LT |
6041 | } |
6042 | ||
6043 | /* We only need to move over in the address because the other | |
6044 | * members of the RX descriptor are invariant. See notes above | |
9205fd9c | 6045 | * tg3_alloc_rx_data for full details. |
1da177e4 | 6046 | */ |
a3896167 MC |
6047 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
6048 | struct tg3_rx_prodring_set *dpr, | |
6049 | u32 opaque_key, int src_idx, | |
6050 | u32 dest_idx_unmasked) | |
1da177e4 | 6051 | { |
17375d25 | 6052 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
6053 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
6054 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 6055 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 6056 | int dest_idx; |
1da177e4 LT |
6057 | |
6058 | switch (opaque_key) { | |
6059 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 6060 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
6061 | dest_desc = &dpr->rx_std[dest_idx]; |
6062 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
6063 | src_desc = &spr->rx_std[src_idx]; | |
6064 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
6065 | break; |
6066 | ||
6067 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 6068 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
6069 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
6070 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
6071 | src_desc = &spr->rx_jmb[src_idx].std; | |
6072 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
6073 | break; |
6074 | ||
6075 | default: | |
6076 | return; | |
855e1111 | 6077 | } |
1da177e4 | 6078 | |
9205fd9c | 6079 | dest_map->data = src_map->data; |
4e5e4f0d FT |
6080 | dma_unmap_addr_set(dest_map, mapping, |
6081 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
6082 | dest_desc->addr_hi = src_desc->addr_hi; |
6083 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
6084 | |
6085 | /* Ensure that the update to the skb happens after the physical | |
6086 | * addresses have been transferred to the new BD location. | |
6087 | */ | |
6088 | smp_wmb(); | |
6089 | ||
9205fd9c | 6090 | src_map->data = NULL; |
1da177e4 LT |
6091 | } |
6092 | ||
1da177e4 LT |
6093 | /* The RX ring scheme is composed of multiple rings which post fresh |
6094 | * buffers to the chip, and one special ring the chip uses to report | |
6095 | * status back to the host. | |
6096 | * | |
6097 | * The special ring reports the status of received packets to the | |
6098 | * host. The chip does not write into the original descriptor the | |
6099 | * RX buffer was obtained from. The chip simply takes the original | |
6100 | * descriptor as provided by the host, updates the status and length | |
6101 | * field, then writes this into the next status ring entry. | |
6102 | * | |
6103 | * Each ring the host uses to post buffers to the chip is described | |
6104 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
6105 | * it is first placed into the on-chip ram. When the packet's length | |
6106 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
6107 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
6108 | * which is within the range of the new packet's length is chosen. | |
6109 | * | |
6110 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
6111 | * sense from a cache coherency perspective. If only the host writes | |
6112 | * to the buffer post rings, and only the chip writes to the rx status | |
6113 | * rings, then cache lines never move beyond shared-modified state. | |
6114 | * If both the host and chip were to write into the same ring, cache line | |
6115 | * eviction could occur since both entities want it in an exclusive state. | |
6116 | */ | |
17375d25 | 6117 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 6118 | { |
17375d25 | 6119 | struct tg3 *tp = tnapi->tp; |
f92905de | 6120 | u32 work_mask, rx_std_posted = 0; |
4361935a | 6121 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 6122 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 6123 | u16 hw_idx; |
1da177e4 | 6124 | int received; |
8fea32b9 | 6125 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 6126 | |
8d9d7cfc | 6127 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
6128 | /* |
6129 | * We need to order the read of hw_idx and the read of | |
6130 | * the opaque cookie. | |
6131 | */ | |
6132 | rmb(); | |
1da177e4 LT |
6133 | work_mask = 0; |
6134 | received = 0; | |
4361935a MC |
6135 | std_prod_idx = tpr->rx_std_prod_idx; |
6136 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 6137 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 6138 | struct ring_info *ri; |
72334482 | 6139 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
6140 | unsigned int len; |
6141 | struct sk_buff *skb; | |
6142 | dma_addr_t dma_addr; | |
6143 | u32 opaque_key, desc_idx, *post_ptr; | |
9205fd9c | 6144 | u8 *data; |
1da177e4 LT |
6145 | |
6146 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
6147 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
6148 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 6149 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 6150 | dma_addr = dma_unmap_addr(ri, mapping); |
9205fd9c | 6151 | data = ri->data; |
4361935a | 6152 | post_ptr = &std_prod_idx; |
f92905de | 6153 | rx_std_posted++; |
1da177e4 | 6154 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 6155 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 6156 | dma_addr = dma_unmap_addr(ri, mapping); |
9205fd9c | 6157 | data = ri->data; |
4361935a | 6158 | post_ptr = &jmb_prod_idx; |
21f581a5 | 6159 | } else |
1da177e4 | 6160 | goto next_pkt_nopost; |
1da177e4 LT |
6161 | |
6162 | work_mask |= opaque_key; | |
6163 | ||
6164 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
6165 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
6166 | drop_it: | |
a3896167 | 6167 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
6168 | desc_idx, *post_ptr); |
6169 | drop_it_no_recycle: | |
6170 | /* Other statistics kept track of by card. */ | |
b0057c51 | 6171 | tp->rx_dropped++; |
1da177e4 LT |
6172 | goto next_pkt; |
6173 | } | |
6174 | ||
9205fd9c | 6175 | prefetch(data + TG3_RX_OFFSET(tp)); |
ad829268 MC |
6176 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
6177 | ETH_FCS_LEN; | |
1da177e4 | 6178 | |
d2757fc4 | 6179 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 | 6180 | int skb_size; |
8d4057a9 | 6181 | unsigned int frag_size; |
1da177e4 | 6182 | |
9205fd9c | 6183 | skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, |
8d4057a9 | 6184 | *post_ptr, &frag_size); |
1da177e4 LT |
6185 | if (skb_size < 0) |
6186 | goto drop_it; | |
6187 | ||
287be12e | 6188 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
6189 | PCI_DMA_FROMDEVICE); |
6190 | ||
8d4057a9 | 6191 | skb = build_skb(data, frag_size); |
9205fd9c | 6192 | if (!skb) { |
8d4057a9 | 6193 | tg3_frag_free(frag_size != 0, data); |
9205fd9c ED |
6194 | goto drop_it_no_recycle; |
6195 | } | |
6196 | skb_reserve(skb, TG3_RX_OFFSET(tp)); | |
6197 | /* Ensure that the update to the data happens | |
61e800cf MC |
6198 | * after the usage of the old DMA mapping. |
6199 | */ | |
6200 | smp_wmb(); | |
6201 | ||
9205fd9c | 6202 | ri->data = NULL; |
61e800cf | 6203 | |
1da177e4 | 6204 | } else { |
a3896167 | 6205 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
6206 | desc_idx, *post_ptr); |
6207 | ||
9205fd9c ED |
6208 | skb = netdev_alloc_skb(tp->dev, |
6209 | len + TG3_RAW_IP_ALIGN); | |
6210 | if (skb == NULL) | |
1da177e4 LT |
6211 | goto drop_it_no_recycle; |
6212 | ||
9205fd9c | 6213 | skb_reserve(skb, TG3_RAW_IP_ALIGN); |
1da177e4 | 6214 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
9205fd9c ED |
6215 | memcpy(skb->data, |
6216 | data + TG3_RX_OFFSET(tp), | |
6217 | len); | |
1da177e4 | 6218 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
6219 | } |
6220 | ||
9205fd9c | 6221 | skb_put(skb, len); |
dc668910 | 6222 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
1da177e4 LT |
6223 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
6224 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
6225 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
6226 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
6227 | else | |
bc8acf2c | 6228 | skb_checksum_none_assert(skb); |
1da177e4 LT |
6229 | |
6230 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
6231 | |
6232 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
6233 | skb->protocol != htons(ETH_P_8021Q)) { | |
6234 | dev_kfree_skb(skb); | |
b0057c51 | 6235 | goto drop_it_no_recycle; |
f7b493e0 MC |
6236 | } |
6237 | ||
9dc7a113 | 6238 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
6239 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
6240 | __vlan_hwaccel_put_tag(skb, | |
6241 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 6242 | |
bf933c80 | 6243 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 6244 | |
1da177e4 LT |
6245 | received++; |
6246 | budget--; | |
6247 | ||
6248 | next_pkt: | |
6249 | (*post_ptr)++; | |
f92905de MC |
6250 | |
6251 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
6252 | tpr->rx_std_prod_idx = std_prod_idx & |
6253 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
6254 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
6255 | tpr->rx_std_prod_idx); | |
f92905de MC |
6256 | work_mask &= ~RXD_OPAQUE_RING_STD; |
6257 | rx_std_posted = 0; | |
6258 | } | |
1da177e4 | 6259 | next_pkt_nopost: |
483ba50b | 6260 | sw_idx++; |
7cb32cf2 | 6261 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
6262 | |
6263 | /* Refresh hw_idx to see if there is new work */ | |
6264 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 6265 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
6266 | rmb(); |
6267 | } | |
1da177e4 LT |
6268 | } |
6269 | ||
6270 | /* ACK the status ring. */ | |
72334482 MC |
6271 | tnapi->rx_rcb_ptr = sw_idx; |
6272 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
6273 | |
6274 | /* Refill RX ring(s). */ | |
63c3a66f | 6275 | if (!tg3_flag(tp, ENABLE_RSS)) { |
6541b806 MC |
6276 | /* Sync BD data before updating mailbox */ |
6277 | wmb(); | |
6278 | ||
b196c7e4 | 6279 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
6280 | tpr->rx_std_prod_idx = std_prod_idx & |
6281 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
6282 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
6283 | tpr->rx_std_prod_idx); | |
6284 | } | |
6285 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
6286 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
6287 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
6288 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
6289 | tpr->rx_jmb_prod_idx); | |
6290 | } | |
6291 | mmiowb(); | |
6292 | } else if (work_mask) { | |
6293 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
6294 | * updated before the producer indices can be updated. | |
6295 | */ | |
6296 | smp_wmb(); | |
6297 | ||
2c49a44d MC |
6298 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
6299 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 6300 | |
7ae52890 MC |
6301 | if (tnapi != &tp->napi[1]) { |
6302 | tp->rx_refill = true; | |
e4af1af9 | 6303 | napi_schedule(&tp->napi[1].napi); |
7ae52890 | 6304 | } |
1da177e4 | 6305 | } |
1da177e4 LT |
6306 | |
6307 | return received; | |
6308 | } | |
6309 | ||
35f2d7d0 | 6310 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 6311 | { |
1da177e4 | 6312 | /* handle link change and other phy events */ |
63c3a66f | 6313 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
35f2d7d0 MC |
6314 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
6315 | ||
1da177e4 LT |
6316 | if (sblk->status & SD_STATUS_LINK_CHG) { |
6317 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 6318 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 6319 | spin_lock(&tp->lock); |
63c3a66f | 6320 | if (tg3_flag(tp, USE_PHYLIB)) { |
dd477003 MC |
6321 | tw32_f(MAC_STATUS, |
6322 | (MAC_STATUS_SYNC_CHANGED | | |
6323 | MAC_STATUS_CFG_CHANGED | | |
6324 | MAC_STATUS_MI_COMPLETION | | |
6325 | MAC_STATUS_LNKSTATE_CHANGED)); | |
6326 | udelay(40); | |
6327 | } else | |
6328 | tg3_setup_phy(tp, 0); | |
f47c11ee | 6329 | spin_unlock(&tp->lock); |
1da177e4 LT |
6330 | } |
6331 | } | |
35f2d7d0 MC |
6332 | } |
6333 | ||
f89f38b8 MC |
6334 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
6335 | struct tg3_rx_prodring_set *dpr, | |
6336 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
6337 | { |
6338 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 6339 | int i, err = 0; |
b196c7e4 MC |
6340 | |
6341 | while (1) { | |
6342 | src_prod_idx = spr->rx_std_prod_idx; | |
6343 | ||
6344 | /* Make sure updates to the rx_std_buffers[] entries and the | |
6345 | * standard producer index are seen in the correct order. | |
6346 | */ | |
6347 | smp_rmb(); | |
6348 | ||
6349 | if (spr->rx_std_cons_idx == src_prod_idx) | |
6350 | break; | |
6351 | ||
6352 | if (spr->rx_std_cons_idx < src_prod_idx) | |
6353 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
6354 | else | |
2c49a44d MC |
6355 | cpycnt = tp->rx_std_ring_mask + 1 - |
6356 | spr->rx_std_cons_idx; | |
b196c7e4 | 6357 | |
2c49a44d MC |
6358 | cpycnt = min(cpycnt, |
6359 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
6360 | |
6361 | si = spr->rx_std_cons_idx; | |
6362 | di = dpr->rx_std_prod_idx; | |
6363 | ||
e92967bf | 6364 | for (i = di; i < di + cpycnt; i++) { |
9205fd9c | 6365 | if (dpr->rx_std_buffers[i].data) { |
e92967bf | 6366 | cpycnt = i - di; |
f89f38b8 | 6367 | err = -ENOSPC; |
e92967bf MC |
6368 | break; |
6369 | } | |
6370 | } | |
6371 | ||
6372 | if (!cpycnt) | |
6373 | break; | |
6374 | ||
6375 | /* Ensure that updates to the rx_std_buffers ring and the | |
6376 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
6377 | * ordered correctly WRT the skb check above. | |
6378 | */ | |
6379 | smp_rmb(); | |
6380 | ||
b196c7e4 MC |
6381 | memcpy(&dpr->rx_std_buffers[di], |
6382 | &spr->rx_std_buffers[si], | |
6383 | cpycnt * sizeof(struct ring_info)); | |
6384 | ||
6385 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
6386 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
6387 | sbd = &spr->rx_std[si]; | |
6388 | dbd = &dpr->rx_std[di]; | |
6389 | dbd->addr_hi = sbd->addr_hi; | |
6390 | dbd->addr_lo = sbd->addr_lo; | |
6391 | } | |
6392 | ||
2c49a44d MC |
6393 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
6394 | tp->rx_std_ring_mask; | |
6395 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
6396 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
6397 | } |
6398 | ||
6399 | while (1) { | |
6400 | src_prod_idx = spr->rx_jmb_prod_idx; | |
6401 | ||
6402 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
6403 | * the jumbo producer index are seen in the correct order. | |
6404 | */ | |
6405 | smp_rmb(); | |
6406 | ||
6407 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
6408 | break; | |
6409 | ||
6410 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
6411 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
6412 | else | |
2c49a44d MC |
6413 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
6414 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
6415 | |
6416 | cpycnt = min(cpycnt, | |
2c49a44d | 6417 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
6418 | |
6419 | si = spr->rx_jmb_cons_idx; | |
6420 | di = dpr->rx_jmb_prod_idx; | |
6421 | ||
e92967bf | 6422 | for (i = di; i < di + cpycnt; i++) { |
9205fd9c | 6423 | if (dpr->rx_jmb_buffers[i].data) { |
e92967bf | 6424 | cpycnt = i - di; |
f89f38b8 | 6425 | err = -ENOSPC; |
e92967bf MC |
6426 | break; |
6427 | } | |
6428 | } | |
6429 | ||
6430 | if (!cpycnt) | |
6431 | break; | |
6432 | ||
6433 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
6434 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
6435 | * ordered correctly WRT the skb check above. | |
6436 | */ | |
6437 | smp_rmb(); | |
6438 | ||
b196c7e4 MC |
6439 | memcpy(&dpr->rx_jmb_buffers[di], |
6440 | &spr->rx_jmb_buffers[si], | |
6441 | cpycnt * sizeof(struct ring_info)); | |
6442 | ||
6443 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
6444 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
6445 | sbd = &spr->rx_jmb[si].std; | |
6446 | dbd = &dpr->rx_jmb[di].std; | |
6447 | dbd->addr_hi = sbd->addr_hi; | |
6448 | dbd->addr_lo = sbd->addr_lo; | |
6449 | } | |
6450 | ||
2c49a44d MC |
6451 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
6452 | tp->rx_jmb_ring_mask; | |
6453 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
6454 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 6455 | } |
f89f38b8 MC |
6456 | |
6457 | return err; | |
b196c7e4 MC |
6458 | } |
6459 | ||
35f2d7d0 MC |
6460 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
6461 | { | |
6462 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
6463 | |
6464 | /* run TX completion thread */ | |
f3f3f27e | 6465 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 6466 | tg3_tx(tnapi); |
63c3a66f | 6467 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
4fd7ab59 | 6468 | return work_done; |
1da177e4 LT |
6469 | } |
6470 | ||
f891ea16 MC |
6471 | if (!tnapi->rx_rcb_prod_idx) |
6472 | return work_done; | |
6473 | ||
1da177e4 LT |
6474 | /* run RX thread, within the bounds set by NAPI. |
6475 | * All RX "locking" is done by ensuring outside | |
bea3348e | 6476 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 6477 | */ |
8d9d7cfc | 6478 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 6479 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 6480 | |
63c3a66f | 6481 | if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 6482 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 6483 | int i, err = 0; |
e4af1af9 MC |
6484 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
6485 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 6486 | |
7ae52890 | 6487 | tp->rx_refill = false; |
9102426a | 6488 | for (i = 1; i <= tp->rxq_cnt; i++) |
f89f38b8 | 6489 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 6490 | &tp->napi[i].prodring); |
b196c7e4 MC |
6491 | |
6492 | wmb(); | |
6493 | ||
e4af1af9 MC |
6494 | if (std_prod_idx != dpr->rx_std_prod_idx) |
6495 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
6496 | dpr->rx_std_prod_idx); | |
b196c7e4 | 6497 | |
e4af1af9 MC |
6498 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
6499 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
6500 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
6501 | |
6502 | mmiowb(); | |
f89f38b8 MC |
6503 | |
6504 | if (err) | |
6505 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
6506 | } |
6507 | ||
6f535763 DM |
6508 | return work_done; |
6509 | } | |
6510 | ||
db219973 MC |
6511 | static inline void tg3_reset_task_schedule(struct tg3 *tp) |
6512 | { | |
6513 | if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) | |
6514 | schedule_work(&tp->reset_task); | |
6515 | } | |
6516 | ||
6517 | static inline void tg3_reset_task_cancel(struct tg3 *tp) | |
6518 | { | |
6519 | cancel_work_sync(&tp->reset_task); | |
6520 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
c7101359 | 6521 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); |
db219973 MC |
6522 | } |
6523 | ||
35f2d7d0 MC |
6524 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
6525 | { | |
6526 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
6527 | struct tg3 *tp = tnapi->tp; | |
6528 | int work_done = 0; | |
6529 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
6530 | ||
6531 | while (1) { | |
6532 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
6533 | ||
63c3a66f | 6534 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
35f2d7d0 MC |
6535 | goto tx_recovery; |
6536 | ||
6537 | if (unlikely(work_done >= budget)) | |
6538 | break; | |
6539 | ||
c6cdf436 | 6540 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
6541 | * to tell the hw how much work has been processed, |
6542 | * so we must read it before checking for more work. | |
6543 | */ | |
6544 | tnapi->last_tag = sblk->status_tag; | |
6545 | tnapi->last_irq_tag = tnapi->last_tag; | |
6546 | rmb(); | |
6547 | ||
6548 | /* check for RX/TX work to do */ | |
6d40db7b MC |
6549 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
6550 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
7ae52890 MC |
6551 | |
6552 | /* This test here is not race free, but will reduce | |
6553 | * the number of interrupts by looping again. | |
6554 | */ | |
6555 | if (tnapi == &tp->napi[1] && tp->rx_refill) | |
6556 | continue; | |
6557 | ||
35f2d7d0 MC |
6558 | napi_complete(napi); |
6559 | /* Reenable interrupts. */ | |
6560 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
7ae52890 MC |
6561 | |
6562 | /* This test here is synchronized by napi_schedule() | |
6563 | * and napi_complete() to close the race condition. | |
6564 | */ | |
6565 | if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { | |
6566 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
6567 | HOSTCC_MODE_ENABLE | | |
6568 | tnapi->coal_now); | |
6569 | } | |
35f2d7d0 MC |
6570 | mmiowb(); |
6571 | break; | |
6572 | } | |
6573 | } | |
6574 | ||
6575 | return work_done; | |
6576 | ||
6577 | tx_recovery: | |
6578 | /* work_done is guaranteed to be less than budget. */ | |
6579 | napi_complete(napi); | |
db219973 | 6580 | tg3_reset_task_schedule(tp); |
35f2d7d0 MC |
6581 | return work_done; |
6582 | } | |
6583 | ||
e64de4e6 MC |
6584 | static void tg3_process_error(struct tg3 *tp) |
6585 | { | |
6586 | u32 val; | |
6587 | bool real_error = false; | |
6588 | ||
63c3a66f | 6589 | if (tg3_flag(tp, ERROR_PROCESSED)) |
e64de4e6 MC |
6590 | return; |
6591 | ||
6592 | /* Check Flow Attention register */ | |
6593 | val = tr32(HOSTCC_FLOW_ATTN); | |
6594 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
6595 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
6596 | real_error = true; | |
6597 | } | |
6598 | ||
6599 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
6600 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
6601 | real_error = true; | |
6602 | } | |
6603 | ||
6604 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
6605 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
6606 | real_error = true; | |
6607 | } | |
6608 | ||
6609 | if (!real_error) | |
6610 | return; | |
6611 | ||
6612 | tg3_dump_state(tp); | |
6613 | ||
63c3a66f | 6614 | tg3_flag_set(tp, ERROR_PROCESSED); |
db219973 | 6615 | tg3_reset_task_schedule(tp); |
e64de4e6 MC |
6616 | } |
6617 | ||
6f535763 DM |
6618 | static int tg3_poll(struct napi_struct *napi, int budget) |
6619 | { | |
8ef0442f MC |
6620 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
6621 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 6622 | int work_done = 0; |
898a56f8 | 6623 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
6624 | |
6625 | while (1) { | |
e64de4e6 MC |
6626 | if (sblk->status & SD_STATUS_ERROR) |
6627 | tg3_process_error(tp); | |
6628 | ||
35f2d7d0 MC |
6629 | tg3_poll_link(tp); |
6630 | ||
17375d25 | 6631 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 | 6632 | |
63c3a66f | 6633 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
6f535763 DM |
6634 | goto tx_recovery; |
6635 | ||
6636 | if (unlikely(work_done >= budget)) | |
6637 | break; | |
6638 | ||
63c3a66f | 6639 | if (tg3_flag(tp, TAGGED_STATUS)) { |
17375d25 | 6640 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
6641 | * to tell the hw how much work has been processed, |
6642 | * so we must read it before checking for more work. | |
6643 | */ | |
898a56f8 MC |
6644 | tnapi->last_tag = sblk->status_tag; |
6645 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
6646 | rmb(); |
6647 | } else | |
6648 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 6649 | |
17375d25 | 6650 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 6651 | napi_complete(napi); |
17375d25 | 6652 | tg3_int_reenable(tnapi); |
6f535763 DM |
6653 | break; |
6654 | } | |
1da177e4 LT |
6655 | } |
6656 | ||
bea3348e | 6657 | return work_done; |
6f535763 DM |
6658 | |
6659 | tx_recovery: | |
4fd7ab59 | 6660 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 6661 | napi_complete(napi); |
db219973 | 6662 | tg3_reset_task_schedule(tp); |
4fd7ab59 | 6663 | return work_done; |
1da177e4 LT |
6664 | } |
6665 | ||
66cfd1bd MC |
6666 | static void tg3_napi_disable(struct tg3 *tp) |
6667 | { | |
6668 | int i; | |
6669 | ||
6670 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
6671 | napi_disable(&tp->napi[i].napi); | |
6672 | } | |
6673 | ||
6674 | static void tg3_napi_enable(struct tg3 *tp) | |
6675 | { | |
6676 | int i; | |
6677 | ||
6678 | for (i = 0; i < tp->irq_cnt; i++) | |
6679 | napi_enable(&tp->napi[i].napi); | |
6680 | } | |
6681 | ||
6682 | static void tg3_napi_init(struct tg3 *tp) | |
6683 | { | |
6684 | int i; | |
6685 | ||
6686 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
6687 | for (i = 1; i < tp->irq_cnt; i++) | |
6688 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
6689 | } | |
6690 | ||
6691 | static void tg3_napi_fini(struct tg3 *tp) | |
6692 | { | |
6693 | int i; | |
6694 | ||
6695 | for (i = 0; i < tp->irq_cnt; i++) | |
6696 | netif_napi_del(&tp->napi[i].napi); | |
6697 | } | |
6698 | ||
6699 | static inline void tg3_netif_stop(struct tg3 *tp) | |
6700 | { | |
6701 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
6702 | tg3_napi_disable(tp); | |
f4a46d1f | 6703 | netif_carrier_off(tp->dev); |
66cfd1bd MC |
6704 | netif_tx_disable(tp->dev); |
6705 | } | |
6706 | ||
35763066 | 6707 | /* tp->lock must be held */ |
66cfd1bd MC |
6708 | static inline void tg3_netif_start(struct tg3 *tp) |
6709 | { | |
be947307 MC |
6710 | tg3_ptp_resume(tp); |
6711 | ||
66cfd1bd MC |
6712 | /* NOTE: unconditional netif_tx_wake_all_queues is only |
6713 | * appropriate so long as all callers are assured to | |
6714 | * have free tx slots (such as after tg3_init_hw) | |
6715 | */ | |
6716 | netif_tx_wake_all_queues(tp->dev); | |
6717 | ||
f4a46d1f NNS |
6718 | if (tp->link_up) |
6719 | netif_carrier_on(tp->dev); | |
6720 | ||
66cfd1bd MC |
6721 | tg3_napi_enable(tp); |
6722 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
6723 | tg3_enable_ints(tp); | |
6724 | } | |
6725 | ||
f47c11ee DM |
6726 | static void tg3_irq_quiesce(struct tg3 *tp) |
6727 | { | |
4f125f42 MC |
6728 | int i; |
6729 | ||
f47c11ee DM |
6730 | BUG_ON(tp->irq_sync); |
6731 | ||
6732 | tp->irq_sync = 1; | |
6733 | smp_mb(); | |
6734 | ||
4f125f42 MC |
6735 | for (i = 0; i < tp->irq_cnt; i++) |
6736 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
6737 | } |
6738 | ||
f47c11ee DM |
6739 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
6740 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
6741 | * with as well. Most of the time, this is not necessary except when | |
6742 | * shutting down the device. | |
6743 | */ | |
6744 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
6745 | { | |
46966545 | 6746 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
6747 | if (irq_sync) |
6748 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
6749 | } |
6750 | ||
6751 | static inline void tg3_full_unlock(struct tg3 *tp) | |
6752 | { | |
f47c11ee DM |
6753 | spin_unlock_bh(&tp->lock); |
6754 | } | |
6755 | ||
fcfa0a32 MC |
6756 | /* One-shot MSI handler - Chip automatically disables interrupt |
6757 | * after sending MSI so driver doesn't have to do it. | |
6758 | */ | |
7d12e780 | 6759 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 6760 | { |
09943a18 MC |
6761 | struct tg3_napi *tnapi = dev_id; |
6762 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 6763 | |
898a56f8 | 6764 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
6765 | if (tnapi->rx_rcb) |
6766 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
6767 | |
6768 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 6769 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
6770 | |
6771 | return IRQ_HANDLED; | |
6772 | } | |
6773 | ||
88b06bc2 MC |
6774 | /* MSI ISR - No need to check for interrupt sharing and no need to |
6775 | * flush status block and interrupt mailbox. PCI ordering rules | |
6776 | * guarantee that MSI will arrive after the status block. | |
6777 | */ | |
7d12e780 | 6778 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 6779 | { |
09943a18 MC |
6780 | struct tg3_napi *tnapi = dev_id; |
6781 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 6782 | |
898a56f8 | 6783 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
6784 | if (tnapi->rx_rcb) |
6785 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 6786 | /* |
fac9b83e | 6787 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 6788 | * chip-internal interrupt pending events. |
fac9b83e | 6789 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
6790 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
6791 | * event coalescing. | |
6792 | */ | |
5b39de91 | 6793 | tw32_mailbox(tnapi->int_mbox, 0x00000001); |
61487480 | 6794 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 6795 | napi_schedule(&tnapi->napi); |
61487480 | 6796 | |
88b06bc2 MC |
6797 | return IRQ_RETVAL(1); |
6798 | } | |
6799 | ||
7d12e780 | 6800 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 6801 | { |
09943a18 MC |
6802 | struct tg3_napi *tnapi = dev_id; |
6803 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6804 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
6805 | unsigned int handled = 1; |
6806 | ||
1da177e4 LT |
6807 | /* In INTx mode, it is possible for the interrupt to arrive at |
6808 | * the CPU before the status block posted prior to the interrupt. | |
6809 | * Reading the PCI State register will confirm whether the | |
6810 | * interrupt is ours and will flush the status block. | |
6811 | */ | |
d18edcb2 | 6812 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
63c3a66f | 6813 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
6814 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
6815 | handled = 0; | |
f47c11ee | 6816 | goto out; |
fac9b83e | 6817 | } |
d18edcb2 MC |
6818 | } |
6819 | ||
6820 | /* | |
6821 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
6822 | * chip-internal interrupt pending events. | |
6823 | * Writing non-zero to intr-mbox-0 additional tells the | |
6824 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
6825 | * event coalescing. | |
c04cb347 MC |
6826 | * |
6827 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
6828 | * spurious interrupts. The flush impacts performance but | |
6829 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 6830 | */ |
c04cb347 | 6831 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
6832 | if (tg3_irq_sync(tp)) |
6833 | goto out; | |
6834 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 6835 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 6836 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 6837 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
6838 | } else { |
6839 | /* No work, shared interrupt perhaps? re-enable | |
6840 | * interrupts, and flush that PCI write | |
6841 | */ | |
6842 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
6843 | 0x00000000); | |
fac9b83e | 6844 | } |
f47c11ee | 6845 | out: |
fac9b83e DM |
6846 | return IRQ_RETVAL(handled); |
6847 | } | |
6848 | ||
7d12e780 | 6849 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 6850 | { |
09943a18 MC |
6851 | struct tg3_napi *tnapi = dev_id; |
6852 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6853 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
6854 | unsigned int handled = 1; |
6855 | ||
fac9b83e DM |
6856 | /* In INTx mode, it is possible for the interrupt to arrive at |
6857 | * the CPU before the status block posted prior to the interrupt. | |
6858 | * Reading the PCI State register will confirm whether the | |
6859 | * interrupt is ours and will flush the status block. | |
6860 | */ | |
898a56f8 | 6861 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
63c3a66f | 6862 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
6863 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
6864 | handled = 0; | |
f47c11ee | 6865 | goto out; |
1da177e4 | 6866 | } |
d18edcb2 MC |
6867 | } |
6868 | ||
6869 | /* | |
6870 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
6871 | * chip-internal interrupt pending events. | |
6872 | * writing non-zero to intr-mbox-0 additional tells the | |
6873 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
6874 | * event coalescing. | |
c04cb347 MC |
6875 | * |
6876 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
6877 | * spurious interrupts. The flush impacts performance but | |
6878 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 6879 | */ |
c04cb347 | 6880 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
6881 | |
6882 | /* | |
6883 | * In a shared interrupt configuration, sometimes other devices' | |
6884 | * interrupts will scream. We record the current status tag here | |
6885 | * so that the above check can report that the screaming interrupts | |
6886 | * are unhandled. Eventually they will be silenced. | |
6887 | */ | |
898a56f8 | 6888 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 6889 | |
d18edcb2 MC |
6890 | if (tg3_irq_sync(tp)) |
6891 | goto out; | |
624f8e50 | 6892 | |
72334482 | 6893 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 6894 | |
09943a18 | 6895 | napi_schedule(&tnapi->napi); |
624f8e50 | 6896 | |
f47c11ee | 6897 | out: |
1da177e4 LT |
6898 | return IRQ_RETVAL(handled); |
6899 | } | |
6900 | ||
7938109f | 6901 | /* ISR for interrupt test */ |
7d12e780 | 6902 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 6903 | { |
09943a18 MC |
6904 | struct tg3_napi *tnapi = dev_id; |
6905 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6906 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 6907 | |
f9804ddb MC |
6908 | if ((sblk->status & SD_STATUS_UPDATED) || |
6909 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 6910 | tg3_disable_ints(tp); |
7938109f MC |
6911 | return IRQ_RETVAL(1); |
6912 | } | |
6913 | return IRQ_RETVAL(0); | |
6914 | } | |
6915 | ||
1da177e4 LT |
6916 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6917 | static void tg3_poll_controller(struct net_device *dev) | |
6918 | { | |
4f125f42 | 6919 | int i; |
88b06bc2 MC |
6920 | struct tg3 *tp = netdev_priv(dev); |
6921 | ||
4f125f42 | 6922 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 6923 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
6924 | } |
6925 | #endif | |
6926 | ||
1da177e4 LT |
6927 | static void tg3_tx_timeout(struct net_device *dev) |
6928 | { | |
6929 | struct tg3 *tp = netdev_priv(dev); | |
6930 | ||
b0408751 | 6931 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 6932 | netdev_err(dev, "transmit timed out, resetting\n"); |
97bd8e49 | 6933 | tg3_dump_state(tp); |
b0408751 | 6934 | } |
1da177e4 | 6935 | |
db219973 | 6936 | tg3_reset_task_schedule(tp); |
1da177e4 LT |
6937 | } |
6938 | ||
c58ec932 MC |
6939 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
6940 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
6941 | { | |
6942 | u32 base = (u32) mapping & 0xffffffff; | |
6943 | ||
807540ba | 6944 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
6945 | } |
6946 | ||
72f2afb8 MC |
6947 | /* Test for DMA addresses > 40-bit */ |
6948 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
6949 | int len) | |
6950 | { | |
6951 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
63c3a66f | 6952 | if (tg3_flag(tp, 40BIT_DMA_BUG)) |
807540ba | 6953 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
6954 | return 0; |
6955 | #else | |
6956 | return 0; | |
6957 | #endif | |
6958 | } | |
6959 | ||
d1a3b737 | 6960 | static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd, |
92cd3a17 MC |
6961 | dma_addr_t mapping, u32 len, u32 flags, |
6962 | u32 mss, u32 vlan) | |
2ffcc981 | 6963 | { |
92cd3a17 MC |
6964 | txbd->addr_hi = ((u64) mapping >> 32); |
6965 | txbd->addr_lo = ((u64) mapping & 0xffffffff); | |
6966 | txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); | |
6967 | txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); | |
2ffcc981 | 6968 | } |
1da177e4 | 6969 | |
84b67b27 | 6970 | static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget, |
d1a3b737 MC |
6971 | dma_addr_t map, u32 len, u32 flags, |
6972 | u32 mss, u32 vlan) | |
6973 | { | |
6974 | struct tg3 *tp = tnapi->tp; | |
6975 | bool hwbug = false; | |
6976 | ||
6977 | if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) | |
3db1cd5c | 6978 | hwbug = true; |
d1a3b737 MC |
6979 | |
6980 | if (tg3_4g_overflow_test(map, len)) | |
3db1cd5c | 6981 | hwbug = true; |
d1a3b737 MC |
6982 | |
6983 | if (tg3_40bit_overflow_test(tp, map, len)) | |
3db1cd5c | 6984 | hwbug = true; |
d1a3b737 | 6985 | |
a4cb428d | 6986 | if (tp->dma_limit) { |
b9e45482 | 6987 | u32 prvidx = *entry; |
e31aa987 | 6988 | u32 tmp_flag = flags & ~TXD_FLAG_END; |
a4cb428d MC |
6989 | while (len > tp->dma_limit && *budget) { |
6990 | u32 frag_len = tp->dma_limit; | |
6991 | len -= tp->dma_limit; | |
e31aa987 | 6992 | |
b9e45482 MC |
6993 | /* Avoid the 8byte DMA problem */ |
6994 | if (len <= 8) { | |
a4cb428d MC |
6995 | len += tp->dma_limit / 2; |
6996 | frag_len = tp->dma_limit / 2; | |
e31aa987 MC |
6997 | } |
6998 | ||
b9e45482 MC |
6999 | tnapi->tx_buffers[*entry].fragmented = true; |
7000 | ||
7001 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
7002 | frag_len, tmp_flag, mss, vlan); | |
7003 | *budget -= 1; | |
7004 | prvidx = *entry; | |
7005 | *entry = NEXT_TX(*entry); | |
7006 | ||
e31aa987 MC |
7007 | map += frag_len; |
7008 | } | |
7009 | ||
7010 | if (len) { | |
7011 | if (*budget) { | |
7012 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
7013 | len, flags, mss, vlan); | |
b9e45482 | 7014 | *budget -= 1; |
e31aa987 MC |
7015 | *entry = NEXT_TX(*entry); |
7016 | } else { | |
3db1cd5c | 7017 | hwbug = true; |
b9e45482 | 7018 | tnapi->tx_buffers[prvidx].fragmented = false; |
e31aa987 MC |
7019 | } |
7020 | } | |
7021 | } else { | |
84b67b27 MC |
7022 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, |
7023 | len, flags, mss, vlan); | |
e31aa987 MC |
7024 | *entry = NEXT_TX(*entry); |
7025 | } | |
d1a3b737 MC |
7026 | |
7027 | return hwbug; | |
7028 | } | |
7029 | ||
0d681b27 | 7030 | static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last) |
432aa7ed MC |
7031 | { |
7032 | int i; | |
0d681b27 | 7033 | struct sk_buff *skb; |
df8944cf | 7034 | struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; |
432aa7ed | 7035 | |
0d681b27 MC |
7036 | skb = txb->skb; |
7037 | txb->skb = NULL; | |
7038 | ||
432aa7ed MC |
7039 | pci_unmap_single(tnapi->tp->pdev, |
7040 | dma_unmap_addr(txb, mapping), | |
7041 | skb_headlen(skb), | |
7042 | PCI_DMA_TODEVICE); | |
e01ee14d MC |
7043 | |
7044 | while (txb->fragmented) { | |
7045 | txb->fragmented = false; | |
7046 | entry = NEXT_TX(entry); | |
7047 | txb = &tnapi->tx_buffers[entry]; | |
7048 | } | |
7049 | ||
ba1142e4 | 7050 | for (i = 0; i <= last; i++) { |
9e903e08 | 7051 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
432aa7ed MC |
7052 | |
7053 | entry = NEXT_TX(entry); | |
7054 | txb = &tnapi->tx_buffers[entry]; | |
7055 | ||
7056 | pci_unmap_page(tnapi->tp->pdev, | |
7057 | dma_unmap_addr(txb, mapping), | |
9e903e08 | 7058 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
e01ee14d MC |
7059 | |
7060 | while (txb->fragmented) { | |
7061 | txb->fragmented = false; | |
7062 | entry = NEXT_TX(entry); | |
7063 | txb = &tnapi->tx_buffers[entry]; | |
7064 | } | |
432aa7ed MC |
7065 | } |
7066 | } | |
7067 | ||
72f2afb8 | 7068 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 | 7069 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
f7ff1987 | 7070 | struct sk_buff **pskb, |
84b67b27 | 7071 | u32 *entry, u32 *budget, |
92cd3a17 | 7072 | u32 base_flags, u32 mss, u32 vlan) |
1da177e4 | 7073 | { |
24f4efd4 | 7074 | struct tg3 *tp = tnapi->tp; |
f7ff1987 | 7075 | struct sk_buff *new_skb, *skb = *pskb; |
c58ec932 | 7076 | dma_addr_t new_addr = 0; |
432aa7ed | 7077 | int ret = 0; |
1da177e4 | 7078 | |
41588ba1 MC |
7079 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
7080 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
7081 | else { | |
7082 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
7083 | ||
7084 | new_skb = skb_copy_expand(skb, | |
7085 | skb_headroom(skb) + more_headroom, | |
7086 | skb_tailroom(skb), GFP_ATOMIC); | |
7087 | } | |
7088 | ||
1da177e4 | 7089 | if (!new_skb) { |
c58ec932 MC |
7090 | ret = -1; |
7091 | } else { | |
7092 | /* New SKB is guaranteed to be linear. */ | |
f4188d8a AD |
7093 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
7094 | PCI_DMA_TODEVICE); | |
7095 | /* Make sure the mapping succeeded */ | |
7096 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
f4188d8a | 7097 | dev_kfree_skb(new_skb); |
c58ec932 | 7098 | ret = -1; |
c58ec932 | 7099 | } else { |
b9e45482 MC |
7100 | u32 save_entry = *entry; |
7101 | ||
92cd3a17 MC |
7102 | base_flags |= TXD_FLAG_END; |
7103 | ||
84b67b27 MC |
7104 | tnapi->tx_buffers[*entry].skb = new_skb; |
7105 | dma_unmap_addr_set(&tnapi->tx_buffers[*entry], | |
432aa7ed MC |
7106 | mapping, new_addr); |
7107 | ||
84b67b27 | 7108 | if (tg3_tx_frag_set(tnapi, entry, budget, new_addr, |
d1a3b737 MC |
7109 | new_skb->len, base_flags, |
7110 | mss, vlan)) { | |
ba1142e4 | 7111 | tg3_tx_skb_unmap(tnapi, save_entry, -1); |
d1a3b737 MC |
7112 | dev_kfree_skb(new_skb); |
7113 | ret = -1; | |
7114 | } | |
f4188d8a | 7115 | } |
1da177e4 LT |
7116 | } |
7117 | ||
7118 | dev_kfree_skb(skb); | |
f7ff1987 | 7119 | *pskb = new_skb; |
c58ec932 | 7120 | return ret; |
1da177e4 LT |
7121 | } |
7122 | ||
2ffcc981 | 7123 | static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *); |
52c0fd83 MC |
7124 | |
7125 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
7126 | * TSO header is greater than 80 bytes. | |
7127 | */ | |
7128 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
7129 | { | |
7130 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 7131 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
7132 | |
7133 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 7134 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 7135 | netif_stop_queue(tp->dev); |
f65aac16 MC |
7136 | |
7137 | /* netif_tx_stop_queue() must be done before checking | |
7138 | * checking tx index in tg3_tx_avail() below, because in | |
7139 | * tg3_tx(), we update tx index before checking for | |
7140 | * netif_tx_queue_stopped(). | |
7141 | */ | |
7142 | smp_mb(); | |
f3f3f27e | 7143 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
7144 | return NETDEV_TX_BUSY; |
7145 | ||
7146 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
7147 | } |
7148 | ||
7149 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 7150 | if (IS_ERR(segs)) |
52c0fd83 MC |
7151 | goto tg3_tso_bug_end; |
7152 | ||
7153 | do { | |
7154 | nskb = segs; | |
7155 | segs = segs->next; | |
7156 | nskb->next = NULL; | |
2ffcc981 | 7157 | tg3_start_xmit(nskb, tp->dev); |
52c0fd83 MC |
7158 | } while (segs); |
7159 | ||
7160 | tg3_tso_bug_end: | |
7161 | dev_kfree_skb(skb); | |
7162 | ||
7163 | return NETDEV_TX_OK; | |
7164 | } | |
52c0fd83 | 7165 | |
5a6f3074 | 7166 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
63c3a66f | 7167 | * support TG3_FLAG_HW_TSO_1 or firmware TSO only. |
5a6f3074 | 7168 | */ |
2ffcc981 | 7169 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
7170 | { |
7171 | struct tg3 *tp = netdev_priv(dev); | |
92cd3a17 | 7172 | u32 len, entry, base_flags, mss, vlan = 0; |
84b67b27 | 7173 | u32 budget; |
432aa7ed | 7174 | int i = -1, would_hit_hwbug; |
90079ce8 | 7175 | dma_addr_t mapping; |
24f4efd4 MC |
7176 | struct tg3_napi *tnapi; |
7177 | struct netdev_queue *txq; | |
432aa7ed | 7178 | unsigned int last; |
f4188d8a | 7179 | |
24f4efd4 MC |
7180 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
7181 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
63c3a66f | 7182 | if (tg3_flag(tp, ENABLE_TSS)) |
24f4efd4 | 7183 | tnapi++; |
1da177e4 | 7184 | |
84b67b27 MC |
7185 | budget = tg3_tx_avail(tnapi); |
7186 | ||
00b70504 | 7187 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 7188 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
7189 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
7190 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 7191 | */ |
84b67b27 | 7192 | if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
7193 | if (!netif_tx_queue_stopped(txq)) { |
7194 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
7195 | |
7196 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
7197 | netdev_err(dev, |
7198 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 7199 | } |
1da177e4 LT |
7200 | return NETDEV_TX_BUSY; |
7201 | } | |
7202 | ||
f3f3f27e | 7203 | entry = tnapi->tx_prod; |
1da177e4 | 7204 | base_flags = 0; |
84fa7933 | 7205 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 7206 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 7207 | |
be98da6a MC |
7208 | mss = skb_shinfo(skb)->gso_size; |
7209 | if (mss) { | |
eddc9ec5 | 7210 | struct iphdr *iph; |
34195c3d | 7211 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
7212 | |
7213 | if (skb_header_cloned(skb) && | |
48855432 ED |
7214 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) |
7215 | goto drop; | |
1da177e4 | 7216 | |
34195c3d | 7217 | iph = ip_hdr(skb); |
ab6a5bb6 | 7218 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 7219 | |
a5a11955 | 7220 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN; |
34195c3d | 7221 | |
a5a11955 | 7222 | if (!skb_is_gso_v6(skb)) { |
34195c3d MC |
7223 | iph->check = 0; |
7224 | iph->tot_len = htons(mss + hdr_len); | |
7225 | } | |
7226 | ||
52c0fd83 | 7227 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
63c3a66f | 7228 | tg3_flag(tp, TSO_BUG)) |
de6f31eb | 7229 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 7230 | |
1da177e4 LT |
7231 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
7232 | TXD_FLAG_CPU_POST_DMA); | |
7233 | ||
63c3a66f JP |
7234 | if (tg3_flag(tp, HW_TSO_1) || |
7235 | tg3_flag(tp, HW_TSO_2) || | |
7236 | tg3_flag(tp, HW_TSO_3)) { | |
aa8223c7 | 7237 | tcp_hdr(skb)->check = 0; |
1da177e4 | 7238 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
7239 | } else |
7240 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
7241 | iph->daddr, 0, | |
7242 | IPPROTO_TCP, | |
7243 | 0); | |
1da177e4 | 7244 | |
63c3a66f | 7245 | if (tg3_flag(tp, HW_TSO_3)) { |
615774fe MC |
7246 | mss |= (hdr_len & 0xc) << 12; |
7247 | if (hdr_len & 0x10) | |
7248 | base_flags |= 0x00000010; | |
7249 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 7250 | } else if (tg3_flag(tp, HW_TSO_2)) |
92c6b8d1 | 7251 | mss |= hdr_len << 9; |
63c3a66f | 7252 | else if (tg3_flag(tp, HW_TSO_1) || |
92c6b8d1 | 7253 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
eddc9ec5 | 7254 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
7255 | int tsflags; |
7256 | ||
eddc9ec5 | 7257 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
7258 | mss |= (tsflags << 11); |
7259 | } | |
7260 | } else { | |
eddc9ec5 | 7261 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
7262 | int tsflags; |
7263 | ||
eddc9ec5 | 7264 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
7265 | base_flags |= tsflags << 12; |
7266 | } | |
7267 | } | |
7268 | } | |
bf933c80 | 7269 | |
93a700a9 MC |
7270 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && |
7271 | !mss && skb->len > VLAN_ETH_FRAME_LEN) | |
7272 | base_flags |= TXD_FLAG_JMB_PKT; | |
7273 | ||
92cd3a17 MC |
7274 | if (vlan_tx_tag_present(skb)) { |
7275 | base_flags |= TXD_FLAG_VLAN; | |
7276 | vlan = vlan_tx_tag_get(skb); | |
7277 | } | |
1da177e4 | 7278 | |
f4188d8a AD |
7279 | len = skb_headlen(skb); |
7280 | ||
7281 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
48855432 ED |
7282 | if (pci_dma_mapping_error(tp->pdev, mapping)) |
7283 | goto drop; | |
7284 | ||
90079ce8 | 7285 | |
f3f3f27e | 7286 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 7287 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
7288 | |
7289 | would_hit_hwbug = 0; | |
7290 | ||
63c3a66f | 7291 | if (tg3_flag(tp, 5701_DMA_BUG)) |
c58ec932 | 7292 | would_hit_hwbug = 1; |
1da177e4 | 7293 | |
84b67b27 | 7294 | if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags | |
d1a3b737 | 7295 | ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), |
ba1142e4 | 7296 | mss, vlan)) { |
d1a3b737 | 7297 | would_hit_hwbug = 1; |
ba1142e4 | 7298 | } else if (skb_shinfo(skb)->nr_frags > 0) { |
92cd3a17 MC |
7299 | u32 tmp_mss = mss; |
7300 | ||
7301 | if (!tg3_flag(tp, HW_TSO_1) && | |
7302 | !tg3_flag(tp, HW_TSO_2) && | |
7303 | !tg3_flag(tp, HW_TSO_3)) | |
7304 | tmp_mss = 0; | |
7305 | ||
c5665a53 MC |
7306 | /* Now loop through additional data |
7307 | * fragments, and queue them. | |
7308 | */ | |
1da177e4 LT |
7309 | last = skb_shinfo(skb)->nr_frags - 1; |
7310 | for (i = 0; i <= last; i++) { | |
7311 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
7312 | ||
9e903e08 | 7313 | len = skb_frag_size(frag); |
dc234d0b | 7314 | mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, |
5d6bcdfe | 7315 | len, DMA_TO_DEVICE); |
1da177e4 | 7316 | |
f3f3f27e | 7317 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 7318 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a | 7319 | mapping); |
5d6bcdfe | 7320 | if (dma_mapping_error(&tp->pdev->dev, mapping)) |
f4188d8a | 7321 | goto dma_error; |
1da177e4 | 7322 | |
b9e45482 MC |
7323 | if (!budget || |
7324 | tg3_tx_frag_set(tnapi, &entry, &budget, mapping, | |
84b67b27 MC |
7325 | len, base_flags | |
7326 | ((i == last) ? TXD_FLAG_END : 0), | |
b9e45482 | 7327 | tmp_mss, vlan)) { |
72f2afb8 | 7328 | would_hit_hwbug = 1; |
b9e45482 MC |
7329 | break; |
7330 | } | |
1da177e4 LT |
7331 | } |
7332 | } | |
7333 | ||
7334 | if (would_hit_hwbug) { | |
0d681b27 | 7335 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); |
1da177e4 LT |
7336 | |
7337 | /* If the workaround fails due to memory/mapping | |
7338 | * failure, silently drop this packet. | |
7339 | */ | |
84b67b27 MC |
7340 | entry = tnapi->tx_prod; |
7341 | budget = tg3_tx_avail(tnapi); | |
f7ff1987 | 7342 | if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget, |
84b67b27 | 7343 | base_flags, mss, vlan)) |
48855432 | 7344 | goto drop_nofree; |
1da177e4 LT |
7345 | } |
7346 | ||
d515b450 | 7347 | skb_tx_timestamp(skb); |
5cb917bc | 7348 | netdev_tx_sent_queue(txq, skb->len); |
d515b450 | 7349 | |
6541b806 MC |
7350 | /* Sync BD data before updating mailbox */ |
7351 | wmb(); | |
7352 | ||
1da177e4 | 7353 | /* Packets are ready, update Tx producer idx local and on card. */ |
24f4efd4 | 7354 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 7355 | |
f3f3f27e MC |
7356 | tnapi->tx_prod = entry; |
7357 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 7358 | netif_tx_stop_queue(txq); |
f65aac16 MC |
7359 | |
7360 | /* netif_tx_stop_queue() must be done before checking | |
7361 | * checking tx index in tg3_tx_avail() below, because in | |
7362 | * tg3_tx(), we update tx index before checking for | |
7363 | * netif_tx_queue_stopped(). | |
7364 | */ | |
7365 | smp_mb(); | |
f3f3f27e | 7366 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 7367 | netif_tx_wake_queue(txq); |
51b91468 | 7368 | } |
1da177e4 | 7369 | |
cdd0db05 | 7370 | mmiowb(); |
1da177e4 | 7371 | return NETDEV_TX_OK; |
f4188d8a AD |
7372 | |
7373 | dma_error: | |
ba1142e4 | 7374 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); |
432aa7ed | 7375 | tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; |
48855432 ED |
7376 | drop: |
7377 | dev_kfree_skb(skb); | |
7378 | drop_nofree: | |
7379 | tp->tx_dropped++; | |
f4188d8a | 7380 | return NETDEV_TX_OK; |
1da177e4 LT |
7381 | } |
7382 | ||
6e01b20b MC |
7383 | static void tg3_mac_loopback(struct tg3 *tp, bool enable) |
7384 | { | |
7385 | if (enable) { | |
7386 | tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | | |
7387 | MAC_MODE_PORT_MODE_MASK); | |
7388 | ||
7389 | tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
7390 | ||
7391 | if (!tg3_flag(tp, 5705_PLUS)) | |
7392 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
7393 | ||
7394 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
7395 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
7396 | else | |
7397 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
7398 | } else { | |
7399 | tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; | |
7400 | ||
7401 | if (tg3_flag(tp, 5705_PLUS) || | |
7402 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || | |
7403 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
7404 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
7405 | } | |
7406 | ||
7407 | tw32(MAC_MODE, tp->mac_mode); | |
7408 | udelay(40); | |
7409 | } | |
7410 | ||
941ec90f | 7411 | static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) |
5e5a7f37 | 7412 | { |
941ec90f | 7413 | u32 val, bmcr, mac_mode, ptest = 0; |
5e5a7f37 MC |
7414 | |
7415 | tg3_phy_toggle_apd(tp, false); | |
7416 | tg3_phy_toggle_automdix(tp, 0); | |
7417 | ||
941ec90f MC |
7418 | if (extlpbk && tg3_phy_set_extloopbk(tp)) |
7419 | return -EIO; | |
7420 | ||
7421 | bmcr = BMCR_FULLDPLX; | |
5e5a7f37 MC |
7422 | switch (speed) { |
7423 | case SPEED_10: | |
7424 | break; | |
7425 | case SPEED_100: | |
7426 | bmcr |= BMCR_SPEED100; | |
7427 | break; | |
7428 | case SPEED_1000: | |
7429 | default: | |
7430 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
7431 | speed = SPEED_100; | |
7432 | bmcr |= BMCR_SPEED100; | |
7433 | } else { | |
7434 | speed = SPEED_1000; | |
7435 | bmcr |= BMCR_SPEED1000; | |
7436 | } | |
7437 | } | |
7438 | ||
941ec90f MC |
7439 | if (extlpbk) { |
7440 | if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
7441 | tg3_readphy(tp, MII_CTRL1000, &val); | |
7442 | val |= CTL1000_AS_MASTER | | |
7443 | CTL1000_ENABLE_MASTER; | |
7444 | tg3_writephy(tp, MII_CTRL1000, val); | |
7445 | } else { | |
7446 | ptest = MII_TG3_FET_PTEST_TRIM_SEL | | |
7447 | MII_TG3_FET_PTEST_TRIM_2; | |
7448 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); | |
7449 | } | |
7450 | } else | |
7451 | bmcr |= BMCR_LOOPBACK; | |
7452 | ||
5e5a7f37 MC |
7453 | tg3_writephy(tp, MII_BMCR, bmcr); |
7454 | ||
7455 | /* The write needs to be flushed for the FETs */ | |
7456 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
7457 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
7458 | ||
7459 | udelay(40); | |
7460 | ||
7461 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && | |
7462 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
941ec90f | 7463 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | |
5e5a7f37 MC |
7464 | MII_TG3_FET_PTEST_FRC_TX_LINK | |
7465 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
7466 | ||
7467 | /* The write needs to be flushed for the AC131 */ | |
7468 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
7469 | } | |
7470 | ||
7471 | /* Reset to prevent losing 1st rx packet intermittently */ | |
7472 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && | |
7473 | tg3_flag(tp, 5780_CLASS)) { | |
7474 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
7475 | udelay(10); | |
7476 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7477 | } | |
7478 | ||
7479 | mac_mode = tp->mac_mode & | |
7480 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
7481 | if (speed == SPEED_1000) | |
7482 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
7483 | else | |
7484 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
7485 | ||
7486 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
7487 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; | |
7488 | ||
7489 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
7490 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
7491 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) | |
7492 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
7493 | ||
7494 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
7495 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
7496 | } | |
7497 | ||
7498 | tw32(MAC_MODE, mac_mode); | |
7499 | udelay(40); | |
941ec90f MC |
7500 | |
7501 | return 0; | |
5e5a7f37 MC |
7502 | } |
7503 | ||
c8f44aff | 7504 | static void tg3_set_loopback(struct net_device *dev, netdev_features_t features) |
06c03c02 MB |
7505 | { |
7506 | struct tg3 *tp = netdev_priv(dev); | |
7507 | ||
7508 | if (features & NETIF_F_LOOPBACK) { | |
7509 | if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) | |
7510 | return; | |
7511 | ||
06c03c02 | 7512 | spin_lock_bh(&tp->lock); |
6e01b20b | 7513 | tg3_mac_loopback(tp, true); |
06c03c02 MB |
7514 | netif_carrier_on(tp->dev); |
7515 | spin_unlock_bh(&tp->lock); | |
7516 | netdev_info(dev, "Internal MAC loopback mode enabled.\n"); | |
7517 | } else { | |
7518 | if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
7519 | return; | |
7520 | ||
06c03c02 | 7521 | spin_lock_bh(&tp->lock); |
6e01b20b | 7522 | tg3_mac_loopback(tp, false); |
06c03c02 MB |
7523 | /* Force link status check */ |
7524 | tg3_setup_phy(tp, 1); | |
7525 | spin_unlock_bh(&tp->lock); | |
7526 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | |
7527 | } | |
7528 | } | |
7529 | ||
c8f44aff MM |
7530 | static netdev_features_t tg3_fix_features(struct net_device *dev, |
7531 | netdev_features_t features) | |
dc668910 MM |
7532 | { |
7533 | struct tg3 *tp = netdev_priv(dev); | |
7534 | ||
63c3a66f | 7535 | if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) |
dc668910 MM |
7536 | features &= ~NETIF_F_ALL_TSO; |
7537 | ||
7538 | return features; | |
7539 | } | |
7540 | ||
c8f44aff | 7541 | static int tg3_set_features(struct net_device *dev, netdev_features_t features) |
06c03c02 | 7542 | { |
c8f44aff | 7543 | netdev_features_t changed = dev->features ^ features; |
06c03c02 MB |
7544 | |
7545 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) | |
7546 | tg3_set_loopback(dev, features); | |
7547 | ||
7548 | return 0; | |
7549 | } | |
7550 | ||
21f581a5 MC |
7551 | static void tg3_rx_prodring_free(struct tg3 *tp, |
7552 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7553 | { |
1da177e4 LT |
7554 | int i; |
7555 | ||
8fea32b9 | 7556 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 7557 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 7558 | i = (i + 1) & tp->rx_std_ring_mask) |
9205fd9c | 7559 | tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], |
b196c7e4 MC |
7560 | tp->rx_pkt_map_sz); |
7561 | ||
63c3a66f | 7562 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
b196c7e4 MC |
7563 | for (i = tpr->rx_jmb_cons_idx; |
7564 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 7565 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
9205fd9c | 7566 | tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], |
b196c7e4 MC |
7567 | TG3_RX_JMB_MAP_SZ); |
7568 | } | |
7569 | } | |
7570 | ||
2b2cdb65 | 7571 | return; |
b196c7e4 | 7572 | } |
1da177e4 | 7573 | |
2c49a44d | 7574 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
9205fd9c | 7575 | tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], |
2b2cdb65 | 7576 | tp->rx_pkt_map_sz); |
1da177e4 | 7577 | |
63c3a66f | 7578 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 7579 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
9205fd9c | 7580 | tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], |
2b2cdb65 | 7581 | TG3_RX_JMB_MAP_SZ); |
1da177e4 LT |
7582 | } |
7583 | } | |
7584 | ||
c6cdf436 | 7585 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
7586 | * |
7587 | * The chip has been shut down and the driver detached from | |
7588 | * the networking, so no interrupts or new tx packets will | |
7589 | * end up in the driver. tp->{tx,}lock are held and thus | |
7590 | * we may not sleep. | |
7591 | */ | |
21f581a5 MC |
7592 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
7593 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7594 | { |
287be12e | 7595 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 7596 | |
b196c7e4 MC |
7597 | tpr->rx_std_cons_idx = 0; |
7598 | tpr->rx_std_prod_idx = 0; | |
7599 | tpr->rx_jmb_cons_idx = 0; | |
7600 | tpr->rx_jmb_prod_idx = 0; | |
7601 | ||
8fea32b9 | 7602 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
7603 | memset(&tpr->rx_std_buffers[0], 0, |
7604 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 7605 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 7606 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 7607 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
7608 | goto done; |
7609 | } | |
7610 | ||
1da177e4 | 7611 | /* Zero out all descriptors. */ |
2c49a44d | 7612 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 7613 | |
287be12e | 7614 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
63c3a66f | 7615 | if (tg3_flag(tp, 5780_CLASS) && |
287be12e MC |
7616 | tp->dev->mtu > ETH_DATA_LEN) |
7617 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
7618 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 7619 | |
1da177e4 LT |
7620 | /* Initialize invariants of the rings, we only set this |
7621 | * stuff once. This works because the card does not | |
7622 | * write into the rx buffer posting rings. | |
7623 | */ | |
2c49a44d | 7624 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
7625 | struct tg3_rx_buffer_desc *rxd; |
7626 | ||
21f581a5 | 7627 | rxd = &tpr->rx_std[i]; |
287be12e | 7628 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
7629 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
7630 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
7631 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
7632 | } | |
7633 | ||
1da177e4 LT |
7634 | /* Now allocate fresh SKBs for each rx ring. */ |
7635 | for (i = 0; i < tp->rx_pending; i++) { | |
8d4057a9 ED |
7636 | unsigned int frag_size; |
7637 | ||
7638 | if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i, | |
7639 | &frag_size) < 0) { | |
5129c3a3 MC |
7640 | netdev_warn(tp->dev, |
7641 | "Using a smaller RX standard ring. Only " | |
7642 | "%d out of %d buffers were allocated " | |
7643 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 7644 | if (i == 0) |
cf7a7298 | 7645 | goto initfail; |
32d8c572 | 7646 | tp->rx_pending = i; |
1da177e4 | 7647 | break; |
32d8c572 | 7648 | } |
1da177e4 LT |
7649 | } |
7650 | ||
63c3a66f | 7651 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
cf7a7298 MC |
7652 | goto done; |
7653 | ||
2c49a44d | 7654 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 7655 | |
63c3a66f | 7656 | if (!tg3_flag(tp, JUMBO_RING_ENABLE)) |
0d86df80 | 7657 | goto done; |
cf7a7298 | 7658 | |
2c49a44d | 7659 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
7660 | struct tg3_rx_buffer_desc *rxd; |
7661 | ||
7662 | rxd = &tpr->rx_jmb[i].std; | |
7663 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
7664 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
7665 | RXD_FLAG_JUMBO; | |
7666 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
7667 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
7668 | } | |
7669 | ||
7670 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
8d4057a9 ED |
7671 | unsigned int frag_size; |
7672 | ||
7673 | if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i, | |
7674 | &frag_size) < 0) { | |
5129c3a3 MC |
7675 | netdev_warn(tp->dev, |
7676 | "Using a smaller RX jumbo ring. Only %d " | |
7677 | "out of %d buffers were allocated " | |
7678 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
7679 | if (i == 0) |
7680 | goto initfail; | |
7681 | tp->rx_jumbo_pending = i; | |
7682 | break; | |
1da177e4 LT |
7683 | } |
7684 | } | |
cf7a7298 MC |
7685 | |
7686 | done: | |
32d8c572 | 7687 | return 0; |
cf7a7298 MC |
7688 | |
7689 | initfail: | |
21f581a5 | 7690 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 7691 | return -ENOMEM; |
1da177e4 LT |
7692 | } |
7693 | ||
21f581a5 MC |
7694 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
7695 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7696 | { |
21f581a5 MC |
7697 | kfree(tpr->rx_std_buffers); |
7698 | tpr->rx_std_buffers = NULL; | |
7699 | kfree(tpr->rx_jmb_buffers); | |
7700 | tpr->rx_jmb_buffers = NULL; | |
7701 | if (tpr->rx_std) { | |
4bae65c8 MC |
7702 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
7703 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 7704 | tpr->rx_std = NULL; |
1da177e4 | 7705 | } |
21f581a5 | 7706 | if (tpr->rx_jmb) { |
4bae65c8 MC |
7707 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
7708 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 7709 | tpr->rx_jmb = NULL; |
1da177e4 | 7710 | } |
cf7a7298 MC |
7711 | } |
7712 | ||
21f581a5 MC |
7713 | static int tg3_rx_prodring_init(struct tg3 *tp, |
7714 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 7715 | { |
2c49a44d MC |
7716 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
7717 | GFP_KERNEL); | |
21f581a5 | 7718 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
7719 | return -ENOMEM; |
7720 | ||
4bae65c8 MC |
7721 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
7722 | TG3_RX_STD_RING_BYTES(tp), | |
7723 | &tpr->rx_std_mapping, | |
7724 | GFP_KERNEL); | |
21f581a5 | 7725 | if (!tpr->rx_std) |
cf7a7298 MC |
7726 | goto err_out; |
7727 | ||
63c3a66f | 7728 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 7729 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
7730 | GFP_KERNEL); |
7731 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
7732 | goto err_out; |
7733 | ||
4bae65c8 MC |
7734 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
7735 | TG3_RX_JMB_RING_BYTES(tp), | |
7736 | &tpr->rx_jmb_mapping, | |
7737 | GFP_KERNEL); | |
21f581a5 | 7738 | if (!tpr->rx_jmb) |
cf7a7298 MC |
7739 | goto err_out; |
7740 | } | |
7741 | ||
7742 | return 0; | |
7743 | ||
7744 | err_out: | |
21f581a5 | 7745 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
7746 | return -ENOMEM; |
7747 | } | |
7748 | ||
7749 | /* Free up pending packets in all rx/tx rings. | |
7750 | * | |
7751 | * The chip has been shut down and the driver detached from | |
7752 | * the networking, so no interrupts or new tx packets will | |
7753 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
7754 | * in an interrupt context and thus may sleep. | |
7755 | */ | |
7756 | static void tg3_free_rings(struct tg3 *tp) | |
7757 | { | |
f77a6a8e | 7758 | int i, j; |
cf7a7298 | 7759 | |
f77a6a8e MC |
7760 | for (j = 0; j < tp->irq_cnt; j++) { |
7761 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 7762 | |
8fea32b9 | 7763 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 7764 | |
0c1d0e2b MC |
7765 | if (!tnapi->tx_buffers) |
7766 | continue; | |
7767 | ||
0d681b27 MC |
7768 | for (i = 0; i < TG3_TX_RING_SIZE; i++) { |
7769 | struct sk_buff *skb = tnapi->tx_buffers[i].skb; | |
cf7a7298 | 7770 | |
0d681b27 | 7771 | if (!skb) |
f77a6a8e | 7772 | continue; |
cf7a7298 | 7773 | |
ba1142e4 MC |
7774 | tg3_tx_skb_unmap(tnapi, i, |
7775 | skb_shinfo(skb)->nr_frags - 1); | |
f77a6a8e MC |
7776 | |
7777 | dev_kfree_skb_any(skb); | |
7778 | } | |
5cb917bc | 7779 | netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); |
2b2cdb65 | 7780 | } |
cf7a7298 MC |
7781 | } |
7782 | ||
7783 | /* Initialize tx/rx rings for packet processing. | |
7784 | * | |
7785 | * The chip has been shut down and the driver detached from | |
7786 | * the networking, so no interrupts or new tx packets will | |
7787 | * end up in the driver. tp->{tx,}lock are held and thus | |
7788 | * we may not sleep. | |
7789 | */ | |
7790 | static int tg3_init_rings(struct tg3 *tp) | |
7791 | { | |
f77a6a8e | 7792 | int i; |
72334482 | 7793 | |
cf7a7298 MC |
7794 | /* Free up all the SKBs. */ |
7795 | tg3_free_rings(tp); | |
7796 | ||
f77a6a8e MC |
7797 | for (i = 0; i < tp->irq_cnt; i++) { |
7798 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7799 | ||
7800 | tnapi->last_tag = 0; | |
7801 | tnapi->last_irq_tag = 0; | |
7802 | tnapi->hw_status->status = 0; | |
7803 | tnapi->hw_status->status_tag = 0; | |
7804 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 7805 | |
f77a6a8e MC |
7806 | tnapi->tx_prod = 0; |
7807 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
7808 | if (tnapi->tx_ring) |
7809 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
7810 | |
7811 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
7812 | if (tnapi->rx_rcb) |
7813 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 7814 | |
8fea32b9 | 7815 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 7816 | tg3_free_rings(tp); |
2b2cdb65 | 7817 | return -ENOMEM; |
e4af1af9 | 7818 | } |
f77a6a8e | 7819 | } |
72334482 | 7820 | |
2b2cdb65 | 7821 | return 0; |
cf7a7298 MC |
7822 | } |
7823 | ||
49a359e3 | 7824 | static void tg3_mem_tx_release(struct tg3 *tp) |
cf7a7298 | 7825 | { |
f77a6a8e | 7826 | int i; |
898a56f8 | 7827 | |
49a359e3 | 7828 | for (i = 0; i < tp->irq_max; i++) { |
f77a6a8e MC |
7829 | struct tg3_napi *tnapi = &tp->napi[i]; |
7830 | ||
7831 | if (tnapi->tx_ring) { | |
4bae65c8 | 7832 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
7833 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
7834 | tnapi->tx_ring = NULL; | |
7835 | } | |
7836 | ||
7837 | kfree(tnapi->tx_buffers); | |
7838 | tnapi->tx_buffers = NULL; | |
49a359e3 MC |
7839 | } |
7840 | } | |
f77a6a8e | 7841 | |
49a359e3 MC |
7842 | static int tg3_mem_tx_acquire(struct tg3 *tp) |
7843 | { | |
7844 | int i; | |
7845 | struct tg3_napi *tnapi = &tp->napi[0]; | |
7846 | ||
7847 | /* If multivector TSS is enabled, vector 0 does not handle | |
7848 | * tx interrupts. Don't allocate any resources for it. | |
7849 | */ | |
7850 | if (tg3_flag(tp, ENABLE_TSS)) | |
7851 | tnapi++; | |
7852 | ||
7853 | for (i = 0; i < tp->txq_cnt; i++, tnapi++) { | |
7854 | tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) * | |
7855 | TG3_TX_RING_SIZE, GFP_KERNEL); | |
7856 | if (!tnapi->tx_buffers) | |
7857 | goto err_out; | |
7858 | ||
7859 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, | |
7860 | TG3_TX_RING_BYTES, | |
7861 | &tnapi->tx_desc_mapping, | |
7862 | GFP_KERNEL); | |
7863 | if (!tnapi->tx_ring) | |
7864 | goto err_out; | |
7865 | } | |
7866 | ||
7867 | return 0; | |
7868 | ||
7869 | err_out: | |
7870 | tg3_mem_tx_release(tp); | |
7871 | return -ENOMEM; | |
7872 | } | |
7873 | ||
7874 | static void tg3_mem_rx_release(struct tg3 *tp) | |
7875 | { | |
7876 | int i; | |
7877 | ||
7878 | for (i = 0; i < tp->irq_max; i++) { | |
7879 | struct tg3_napi *tnapi = &tp->napi[i]; | |
f77a6a8e | 7880 | |
8fea32b9 MC |
7881 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
7882 | ||
49a359e3 MC |
7883 | if (!tnapi->rx_rcb) |
7884 | continue; | |
7885 | ||
7886 | dma_free_coherent(&tp->pdev->dev, | |
7887 | TG3_RX_RCB_RING_BYTES(tp), | |
7888 | tnapi->rx_rcb, | |
7889 | tnapi->rx_rcb_mapping); | |
7890 | tnapi->rx_rcb = NULL; | |
7891 | } | |
7892 | } | |
7893 | ||
7894 | static int tg3_mem_rx_acquire(struct tg3 *tp) | |
7895 | { | |
7896 | unsigned int i, limit; | |
7897 | ||
7898 | limit = tp->rxq_cnt; | |
7899 | ||
7900 | /* If RSS is enabled, we need a (dummy) producer ring | |
7901 | * set on vector zero. This is the true hw prodring. | |
7902 | */ | |
7903 | if (tg3_flag(tp, ENABLE_RSS)) | |
7904 | limit++; | |
7905 | ||
7906 | for (i = 0; i < limit; i++) { | |
7907 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7908 | ||
7909 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) | |
7910 | goto err_out; | |
7911 | ||
7912 | /* If multivector RSS is enabled, vector 0 | |
7913 | * does not handle rx or tx interrupts. | |
7914 | * Don't allocate any resources for it. | |
7915 | */ | |
7916 | if (!i && tg3_flag(tp, ENABLE_RSS)) | |
7917 | continue; | |
7918 | ||
7919 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, | |
7920 | TG3_RX_RCB_RING_BYTES(tp), | |
7921 | &tnapi->rx_rcb_mapping, | |
7922 | GFP_KERNEL); | |
7923 | if (!tnapi->rx_rcb) | |
7924 | goto err_out; | |
7925 | ||
7926 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
7927 | } | |
7928 | ||
7929 | return 0; | |
7930 | ||
7931 | err_out: | |
7932 | tg3_mem_rx_release(tp); | |
7933 | return -ENOMEM; | |
7934 | } | |
7935 | ||
7936 | /* | |
7937 | * Must not be invoked with interrupt sources disabled and | |
7938 | * the hardware shutdown down. | |
7939 | */ | |
7940 | static void tg3_free_consistent(struct tg3 *tp) | |
7941 | { | |
7942 | int i; | |
7943 | ||
7944 | for (i = 0; i < tp->irq_cnt; i++) { | |
7945 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7946 | ||
f77a6a8e | 7947 | if (tnapi->hw_status) { |
4bae65c8 MC |
7948 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
7949 | tnapi->hw_status, | |
7950 | tnapi->status_mapping); | |
f77a6a8e MC |
7951 | tnapi->hw_status = NULL; |
7952 | } | |
1da177e4 | 7953 | } |
f77a6a8e | 7954 | |
49a359e3 MC |
7955 | tg3_mem_rx_release(tp); |
7956 | tg3_mem_tx_release(tp); | |
7957 | ||
1da177e4 | 7958 | if (tp->hw_stats) { |
4bae65c8 MC |
7959 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
7960 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
7961 | tp->hw_stats = NULL; |
7962 | } | |
7963 | } | |
7964 | ||
7965 | /* | |
7966 | * Must not be invoked with interrupt sources disabled and | |
7967 | * the hardware shutdown down. Can sleep. | |
7968 | */ | |
7969 | static int tg3_alloc_consistent(struct tg3 *tp) | |
7970 | { | |
f77a6a8e | 7971 | int i; |
898a56f8 | 7972 | |
4bae65c8 MC |
7973 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
7974 | sizeof(struct tg3_hw_stats), | |
7975 | &tp->stats_mapping, | |
7976 | GFP_KERNEL); | |
f77a6a8e | 7977 | if (!tp->hw_stats) |
1da177e4 LT |
7978 | goto err_out; |
7979 | ||
f77a6a8e | 7980 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 7981 | |
f77a6a8e MC |
7982 | for (i = 0; i < tp->irq_cnt; i++) { |
7983 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 7984 | struct tg3_hw_status *sblk; |
1da177e4 | 7985 | |
4bae65c8 MC |
7986 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
7987 | TG3_HW_STATUS_SIZE, | |
7988 | &tnapi->status_mapping, | |
7989 | GFP_KERNEL); | |
f77a6a8e MC |
7990 | if (!tnapi->hw_status) |
7991 | goto err_out; | |
898a56f8 | 7992 | |
f77a6a8e | 7993 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
7994 | sblk = tnapi->hw_status; |
7995 | ||
49a359e3 | 7996 | if (tg3_flag(tp, ENABLE_RSS)) { |
86449944 | 7997 | u16 *prodptr = NULL; |
8fea32b9 | 7998 | |
49a359e3 MC |
7999 | /* |
8000 | * When RSS is enabled, the status block format changes | |
8001 | * slightly. The "rx_jumbo_consumer", "reserved", | |
8002 | * and "rx_mini_consumer" members get mapped to the | |
8003 | * other three rx return ring producer indexes. | |
8004 | */ | |
8005 | switch (i) { | |
8006 | case 1: | |
8007 | prodptr = &sblk->idx[0].rx_producer; | |
8008 | break; | |
8009 | case 2: | |
8010 | prodptr = &sblk->rx_jumbo_consumer; | |
8011 | break; | |
8012 | case 3: | |
8013 | prodptr = &sblk->reserved; | |
8014 | break; | |
8015 | case 4: | |
8016 | prodptr = &sblk->rx_mini_consumer; | |
f891ea16 MC |
8017 | break; |
8018 | } | |
49a359e3 MC |
8019 | tnapi->rx_rcb_prod_idx = prodptr; |
8020 | } else { | |
8d9d7cfc | 8021 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; |
8d9d7cfc | 8022 | } |
f77a6a8e | 8023 | } |
1da177e4 | 8024 | |
49a359e3 MC |
8025 | if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp)) |
8026 | goto err_out; | |
8027 | ||
1da177e4 LT |
8028 | return 0; |
8029 | ||
8030 | err_out: | |
8031 | tg3_free_consistent(tp); | |
8032 | return -ENOMEM; | |
8033 | } | |
8034 | ||
8035 | #define MAX_WAIT_CNT 1000 | |
8036 | ||
8037 | /* To stop a block, clear the enable bit and poll till it | |
8038 | * clears. tp->lock is held. | |
8039 | */ | |
b3b7d6be | 8040 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
8041 | { |
8042 | unsigned int i; | |
8043 | u32 val; | |
8044 | ||
63c3a66f | 8045 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8046 | switch (ofs) { |
8047 | case RCVLSC_MODE: | |
8048 | case DMAC_MODE: | |
8049 | case MBFREE_MODE: | |
8050 | case BUFMGR_MODE: | |
8051 | case MEMARB_MODE: | |
8052 | /* We can't enable/disable these bits of the | |
8053 | * 5705/5750, just say success. | |
8054 | */ | |
8055 | return 0; | |
8056 | ||
8057 | default: | |
8058 | break; | |
855e1111 | 8059 | } |
1da177e4 LT |
8060 | } |
8061 | ||
8062 | val = tr32(ofs); | |
8063 | val &= ~enable_bit; | |
8064 | tw32_f(ofs, val); | |
8065 | ||
8066 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
8067 | udelay(100); | |
8068 | val = tr32(ofs); | |
8069 | if ((val & enable_bit) == 0) | |
8070 | break; | |
8071 | } | |
8072 | ||
b3b7d6be | 8073 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
8074 | dev_err(&tp->pdev->dev, |
8075 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
8076 | ofs, enable_bit); | |
1da177e4 LT |
8077 | return -ENODEV; |
8078 | } | |
8079 | ||
8080 | return 0; | |
8081 | } | |
8082 | ||
8083 | /* tp->lock is held. */ | |
b3b7d6be | 8084 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
8085 | { |
8086 | int i, err; | |
8087 | ||
8088 | tg3_disable_ints(tp); | |
8089 | ||
8090 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
8091 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8092 | udelay(10); | |
8093 | ||
b3b7d6be DM |
8094 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
8095 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
8096 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
8097 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
8098 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
8099 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
8100 | ||
8101 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
8102 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
8103 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
8104 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
8105 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
8106 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
8107 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
8108 | |
8109 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
8110 | tw32_f(MAC_MODE, tp->mac_mode); | |
8111 | udelay(40); | |
8112 | ||
8113 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
8114 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
8115 | ||
8116 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
8117 | udelay(100); | |
8118 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
8119 | break; | |
8120 | } | |
8121 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
8122 | dev_err(&tp->pdev->dev, |
8123 | "%s timed out, TX_MODE_ENABLE will not clear " | |
8124 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 8125 | err |= -ENODEV; |
1da177e4 LT |
8126 | } |
8127 | ||
e6de8ad1 | 8128 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
8129 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
8130 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
8131 | |
8132 | tw32(FTQ_RESET, 0xffffffff); | |
8133 | tw32(FTQ_RESET, 0x00000000); | |
8134 | ||
b3b7d6be DM |
8135 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
8136 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 8137 | |
f77a6a8e MC |
8138 | for (i = 0; i < tp->irq_cnt; i++) { |
8139 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8140 | if (tnapi->hw_status) | |
8141 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8142 | } | |
1da177e4 | 8143 | |
1da177e4 LT |
8144 | return err; |
8145 | } | |
8146 | ||
ee6a99b5 MC |
8147 | /* Save PCI command register before chip reset */ |
8148 | static void tg3_save_pci_state(struct tg3 *tp) | |
8149 | { | |
8a6eac90 | 8150 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
8151 | } |
8152 | ||
8153 | /* Restore PCI state after chip reset */ | |
8154 | static void tg3_restore_pci_state(struct tg3 *tp) | |
8155 | { | |
8156 | u32 val; | |
8157 | ||
8158 | /* Re-enable indirect register accesses. */ | |
8159 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
8160 | tp->misc_host_ctrl); | |
8161 | ||
8162 | /* Set MAX PCI retry to zero. */ | |
8163 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
8164 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 8165 | tg3_flag(tp, PCIX_MODE)) |
ee6a99b5 | 8166 | val |= PCISTATE_RETRY_SAME_DMA; |
0d3031d9 | 8167 | /* Allow reads and writes to the APE register and memory space. */ |
63c3a66f | 8168 | if (tg3_flag(tp, ENABLE_APE)) |
0d3031d9 | 8169 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
f92d9dc1 MC |
8170 | PCISTATE_ALLOW_APE_SHMEM_WR | |
8171 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
8172 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
8173 | ||
8a6eac90 | 8174 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 8175 | |
2c55a3d0 MC |
8176 | if (!tg3_flag(tp, PCI_EXPRESS)) { |
8177 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
8178 | tp->pci_cacheline_sz); | |
8179 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
8180 | tp->pci_lat_timer); | |
114342f2 | 8181 | } |
5f5c51e3 | 8182 | |
ee6a99b5 | 8183 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
63c3a66f | 8184 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
8185 | u16 pcix_cmd; |
8186 | ||
8187 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8188 | &pcix_cmd); | |
8189 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
8190 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8191 | pcix_cmd); | |
8192 | } | |
ee6a99b5 | 8193 | |
63c3a66f | 8194 | if (tg3_flag(tp, 5780_CLASS)) { |
ee6a99b5 MC |
8195 | |
8196 | /* Chip reset on 5780 will reset MSI enable bit, | |
8197 | * so need to restore it. | |
8198 | */ | |
63c3a66f | 8199 | if (tg3_flag(tp, USING_MSI)) { |
ee6a99b5 MC |
8200 | u16 ctrl; |
8201 | ||
8202 | pci_read_config_word(tp->pdev, | |
8203 | tp->msi_cap + PCI_MSI_FLAGS, | |
8204 | &ctrl); | |
8205 | pci_write_config_word(tp->pdev, | |
8206 | tp->msi_cap + PCI_MSI_FLAGS, | |
8207 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
8208 | val = tr32(MSGINT_MODE); | |
8209 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
8210 | } | |
8211 | } | |
8212 | } | |
8213 | ||
1da177e4 LT |
8214 | /* tp->lock is held. */ |
8215 | static int tg3_chip_reset(struct tg3 *tp) | |
8216 | { | |
8217 | u32 val; | |
1ee582d8 | 8218 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 8219 | int i, err; |
1da177e4 | 8220 | |
f49639e6 DM |
8221 | tg3_nvram_lock(tp); |
8222 | ||
77b483f1 MC |
8223 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
8224 | ||
f49639e6 DM |
8225 | /* No matching tg3_nvram_unlock() after this because |
8226 | * chip reset below will undo the nvram lock. | |
8227 | */ | |
8228 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 8229 | |
ee6a99b5 MC |
8230 | /* GRC_MISC_CFG core clock reset will clear the memory |
8231 | * enable bit in PCI register 4 and the MSI enable bit | |
8232 | * on some chips, so we save relevant registers here. | |
8233 | */ | |
8234 | tg3_save_pci_state(tp); | |
8235 | ||
d9ab5ad1 | 8236 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
63c3a66f | 8237 | tg3_flag(tp, 5755_PLUS)) |
d9ab5ad1 MC |
8238 | tw32(GRC_FASTBOOT_PC, 0); |
8239 | ||
1da177e4 LT |
8240 | /* |
8241 | * We must avoid the readl() that normally takes place. | |
8242 | * It locks machines, causes machine checks, and other | |
8243 | * fun things. So, temporarily disable the 5701 | |
8244 | * hardware workaround, while we do the reset. | |
8245 | */ | |
1ee582d8 MC |
8246 | write_op = tp->write32; |
8247 | if (write_op == tg3_write_flush_reg32) | |
8248 | tp->write32 = tg3_write32; | |
1da177e4 | 8249 | |
d18edcb2 MC |
8250 | /* Prevent the irq handler from reading or writing PCI registers |
8251 | * during chip reset when the memory enable bit in the PCI command | |
8252 | * register may be cleared. The chip does not generate interrupt | |
8253 | * at this time, but the irq handler may still be called due to irq | |
8254 | * sharing or irqpoll. | |
8255 | */ | |
63c3a66f | 8256 | tg3_flag_set(tp, CHIP_RESETTING); |
f77a6a8e MC |
8257 | for (i = 0; i < tp->irq_cnt; i++) { |
8258 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8259 | if (tnapi->hw_status) { | |
8260 | tnapi->hw_status->status = 0; | |
8261 | tnapi->hw_status->status_tag = 0; | |
8262 | } | |
8263 | tnapi->last_tag = 0; | |
8264 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 8265 | } |
d18edcb2 | 8266 | smp_mb(); |
4f125f42 MC |
8267 | |
8268 | for (i = 0; i < tp->irq_cnt; i++) | |
8269 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 8270 | |
255ca311 MC |
8271 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8272 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
8273 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
8274 | } | |
8275 | ||
1da177e4 LT |
8276 | /* do the reset */ |
8277 | val = GRC_MISC_CFG_CORECLK_RESET; | |
8278 | ||
63c3a66f | 8279 | if (tg3_flag(tp, PCI_EXPRESS)) { |
88075d91 MC |
8280 | /* Force PCIe 1.0a mode */ |
8281 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 8282 | !tg3_flag(tp, 57765_PLUS) && |
88075d91 MC |
8283 | tr32(TG3_PCIE_PHY_TSTCTL) == |
8284 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
8285 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
8286 | ||
1da177e4 LT |
8287 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
8288 | tw32(GRC_MISC_CFG, (1 << 29)); | |
8289 | val |= (1 << 29); | |
8290 | } | |
8291 | } | |
8292 | ||
b5d3772c MC |
8293 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
8294 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
8295 | tw32(GRC_VCPU_EXT_CTRL, | |
8296 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
8297 | } | |
8298 | ||
f37500d3 | 8299 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
63c3a66f | 8300 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) |
1da177e4 | 8301 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 8302 | |
1da177e4 LT |
8303 | tw32(GRC_MISC_CFG, val); |
8304 | ||
1ee582d8 MC |
8305 | /* restore 5701 hardware bug workaround write method */ |
8306 | tp->write32 = write_op; | |
1da177e4 LT |
8307 | |
8308 | /* Unfortunately, we have to delay before the PCI read back. | |
8309 | * Some 575X chips even will not respond to a PCI cfg access | |
8310 | * when the reset command is given to the chip. | |
8311 | * | |
8312 | * How do these hardware designers expect things to work | |
8313 | * properly if the PCI write is posted for a long period | |
8314 | * of time? It is always necessary to have some method by | |
8315 | * which a register read back can occur to push the write | |
8316 | * out which does the reset. | |
8317 | * | |
8318 | * For most tg3 variants the trick below was working. | |
8319 | * Ho hum... | |
8320 | */ | |
8321 | udelay(120); | |
8322 | ||
8323 | /* Flush PCI posted writes. The normal MMIO registers | |
8324 | * are inaccessible at this time so this is the only | |
8325 | * way to make this reliably (actually, this is no longer | |
8326 | * the case, see above). I tried to use indirect | |
8327 | * register read/write but this upset some 5701 variants. | |
8328 | */ | |
8329 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
8330 | ||
8331 | udelay(120); | |
8332 | ||
0f49bfbd | 8333 | if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { |
e7126997 MC |
8334 | u16 val16; |
8335 | ||
1da177e4 | 8336 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
86449944 | 8337 | int j; |
1da177e4 LT |
8338 | u32 cfg_val; |
8339 | ||
8340 | /* Wait for link training to complete. */ | |
86449944 | 8341 | for (j = 0; j < 5000; j++) |
1da177e4 LT |
8342 | udelay(100); |
8343 | ||
8344 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
8345 | pci_write_config_dword(tp->pdev, 0xc4, | |
8346 | cfg_val | (1 << 15)); | |
8347 | } | |
5e7dfd0f | 8348 | |
e7126997 | 8349 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
0f49bfbd | 8350 | val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN; |
e7126997 MC |
8351 | /* |
8352 | * Older PCIe devices only support the 128 byte | |
8353 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 8354 | */ |
63c3a66f | 8355 | if (!tg3_flag(tp, CPMU_PRESENT)) |
0f49bfbd JL |
8356 | val16 |= PCI_EXP_DEVCTL_PAYLOAD; |
8357 | pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); | |
5e7dfd0f | 8358 | |
5e7dfd0f | 8359 | /* Clear error status */ |
0f49bfbd | 8360 | pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, |
5e7dfd0f MC |
8361 | PCI_EXP_DEVSTA_CED | |
8362 | PCI_EXP_DEVSTA_NFED | | |
8363 | PCI_EXP_DEVSTA_FED | | |
8364 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
8365 | } |
8366 | ||
ee6a99b5 | 8367 | tg3_restore_pci_state(tp); |
1da177e4 | 8368 | |
63c3a66f JP |
8369 | tg3_flag_clear(tp, CHIP_RESETTING); |
8370 | tg3_flag_clear(tp, ERROR_PROCESSED); | |
d18edcb2 | 8371 | |
ee6a99b5 | 8372 | val = 0; |
63c3a66f | 8373 | if (tg3_flag(tp, 5780_CLASS)) |
4cf78e4f | 8374 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 8375 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
8376 | |
8377 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
8378 | tg3_stop_fw(tp); | |
8379 | tw32(0x5000, 0x400); | |
8380 | } | |
8381 | ||
8382 | tw32(GRC_MODE, tp->grc_mode); | |
8383 | ||
8384 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 8385 | val = tr32(0xc4); |
1da177e4 LT |
8386 | |
8387 | tw32(0xc4, val | (1 << 15)); | |
8388 | } | |
8389 | ||
8390 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
8391 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
8392 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
8393 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
8394 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
8395 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8396 | } | |
8397 | ||
f07e9af3 | 8398 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
9e975cc2 | 8399 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; |
d2394e6b | 8400 | val = tp->mac_mode; |
f07e9af3 | 8401 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
9e975cc2 | 8402 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; |
d2394e6b | 8403 | val = tp->mac_mode; |
1da177e4 | 8404 | } else |
d2394e6b MC |
8405 | val = 0; |
8406 | ||
8407 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
8408 | udelay(40); |
8409 | ||
77b483f1 MC |
8410 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
8411 | ||
7a6f4369 MC |
8412 | err = tg3_poll_fw(tp); |
8413 | if (err) | |
8414 | return err; | |
1da177e4 | 8415 | |
0a9140cf MC |
8416 | tg3_mdio_start(tp); |
8417 | ||
63c3a66f | 8418 | if (tg3_flag(tp, PCI_EXPRESS) && |
f6eb9b1f MC |
8419 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
8420 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 8421 | !tg3_flag(tp, 57765_PLUS)) { |
ab0049b4 | 8422 | val = tr32(0x7c00); |
1da177e4 LT |
8423 | |
8424 | tw32(0x7c00, val | (1 << 25)); | |
8425 | } | |
8426 | ||
d78b59f5 MC |
8427 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
8428 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
8429 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
8430 | } | |
8431 | ||
1da177e4 | 8432 | /* Reprobe ASF enable state. */ |
63c3a66f JP |
8433 | tg3_flag_clear(tp, ENABLE_ASF); |
8434 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
8435 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
8436 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
8437 | u32 nic_cfg; | |
8438 | ||
8439 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
8440 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f | 8441 | tg3_flag_set(tp, ENABLE_ASF); |
4ba526ce | 8442 | tp->last_event_jiffies = jiffies; |
63c3a66f JP |
8443 | if (tg3_flag(tp, 5750_PLUS)) |
8444 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
8445 | } |
8446 | } | |
8447 | ||
8448 | return 0; | |
8449 | } | |
8450 | ||
65ec698d MC |
8451 | static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *); |
8452 | static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *); | |
92feeabf | 8453 | |
1da177e4 | 8454 | /* tp->lock is held. */ |
944d980e | 8455 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
8456 | { |
8457 | int err; | |
8458 | ||
8459 | tg3_stop_fw(tp); | |
8460 | ||
944d980e | 8461 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 8462 | |
b3b7d6be | 8463 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
8464 | err = tg3_chip_reset(tp); |
8465 | ||
daba2a63 MC |
8466 | __tg3_set_mac_addr(tp, 0); |
8467 | ||
944d980e MC |
8468 | tg3_write_sig_legacy(tp, kind); |
8469 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 | 8470 | |
92feeabf MC |
8471 | if (tp->hw_stats) { |
8472 | /* Save the stats across chip resets... */ | |
b4017c53 | 8473 | tg3_get_nstats(tp, &tp->net_stats_prev); |
92feeabf MC |
8474 | tg3_get_estats(tp, &tp->estats_prev); |
8475 | ||
8476 | /* And make sure the next sample is new data */ | |
8477 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
8478 | } | |
8479 | ||
1da177e4 LT |
8480 | if (err) |
8481 | return err; | |
8482 | ||
8483 | return 0; | |
8484 | } | |
8485 | ||
1da177e4 LT |
8486 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
8487 | { | |
8488 | struct tg3 *tp = netdev_priv(dev); | |
8489 | struct sockaddr *addr = p; | |
986e0aeb | 8490 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 8491 | |
f9804ddb | 8492 | if (!is_valid_ether_addr(addr->sa_data)) |
504f9b5a | 8493 | return -EADDRNOTAVAIL; |
f9804ddb | 8494 | |
1da177e4 LT |
8495 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
8496 | ||
e75f7c90 MC |
8497 | if (!netif_running(dev)) |
8498 | return 0; | |
8499 | ||
63c3a66f | 8500 | if (tg3_flag(tp, ENABLE_ASF)) { |
986e0aeb | 8501 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 8502 | |
986e0aeb MC |
8503 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
8504 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
8505 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
8506 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
8507 | ||
8508 | /* Skip MAC addr 1 if ASF is using it. */ | |
8509 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
8510 | !(addr1_high == 0 && addr1_low == 0)) | |
8511 | skip_mac_1 = 1; | |
58712ef9 | 8512 | } |
986e0aeb MC |
8513 | spin_lock_bh(&tp->lock); |
8514 | __tg3_set_mac_addr(tp, skip_mac_1); | |
8515 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 8516 | |
b9ec6c1b | 8517 | return err; |
1da177e4 LT |
8518 | } |
8519 | ||
8520 | /* tp->lock is held. */ | |
8521 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
8522 | dma_addr_t mapping, u32 maxlen_flags, | |
8523 | u32 nic_addr) | |
8524 | { | |
8525 | tg3_write_mem(tp, | |
8526 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
8527 | ((u64) mapping >> 32)); | |
8528 | tg3_write_mem(tp, | |
8529 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
8530 | ((u64) mapping & 0xffffffff)); | |
8531 | tg3_write_mem(tp, | |
8532 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
8533 | maxlen_flags); | |
8534 | ||
63c3a66f | 8535 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8536 | tg3_write_mem(tp, |
8537 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
8538 | nic_addr); | |
8539 | } | |
8540 | ||
a489b6d9 MC |
8541 | |
8542 | static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec) | |
15f9850d | 8543 | { |
a489b6d9 | 8544 | int i = 0; |
b6080e12 | 8545 | |
63c3a66f | 8546 | if (!tg3_flag(tp, ENABLE_TSS)) { |
b6080e12 MC |
8547 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
8548 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
8549 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
8550 | } else { |
8551 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
8552 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
8553 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
a489b6d9 MC |
8554 | |
8555 | for (; i < tp->txq_cnt; i++) { | |
8556 | u32 reg; | |
8557 | ||
8558 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; | |
8559 | tw32(reg, ec->tx_coalesce_usecs); | |
8560 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
8561 | tw32(reg, ec->tx_max_coalesced_frames); | |
8562 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
8563 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
8564 | } | |
19cfaecc | 8565 | } |
b6080e12 | 8566 | |
a489b6d9 MC |
8567 | for (; i < tp->irq_max - 1; i++) { |
8568 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); | |
8569 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
8570 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
8571 | } | |
8572 | } | |
8573 | ||
8574 | static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec) | |
8575 | { | |
8576 | int i = 0; | |
8577 | u32 limit = tp->rxq_cnt; | |
8578 | ||
63c3a66f | 8579 | if (!tg3_flag(tp, ENABLE_RSS)) { |
19cfaecc MC |
8580 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
8581 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
8582 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
a489b6d9 | 8583 | limit--; |
19cfaecc | 8584 | } else { |
b6080e12 MC |
8585 | tw32(HOSTCC_RXCOL_TICKS, 0); |
8586 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
8587 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 8588 | } |
b6080e12 | 8589 | |
a489b6d9 | 8590 | for (; i < limit; i++) { |
b6080e12 MC |
8591 | u32 reg; |
8592 | ||
8593 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
8594 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
8595 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
8596 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
8597 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
8598 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
b6080e12 MC |
8599 | } |
8600 | ||
8601 | for (; i < tp->irq_max - 1; i++) { | |
8602 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 8603 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 8604 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
a489b6d9 MC |
8605 | } |
8606 | } | |
19cfaecc | 8607 | |
a489b6d9 MC |
8608 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
8609 | { | |
8610 | tg3_coal_tx_init(tp, ec); | |
8611 | tg3_coal_rx_init(tp, ec); | |
8612 | ||
8613 | if (!tg3_flag(tp, 5705_PLUS)) { | |
8614 | u32 val = ec->stats_block_coalesce_usecs; | |
8615 | ||
8616 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); | |
8617 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
8618 | ||
f4a46d1f | 8619 | if (!tp->link_up) |
a489b6d9 MC |
8620 | val = 0; |
8621 | ||
8622 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
b6080e12 | 8623 | } |
15f9850d | 8624 | } |
1da177e4 | 8625 | |
2d31ecaf MC |
8626 | /* tp->lock is held. */ |
8627 | static void tg3_rings_reset(struct tg3 *tp) | |
8628 | { | |
8629 | int i; | |
f77a6a8e | 8630 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
8631 | struct tg3_napi *tnapi = &tp->napi[0]; |
8632 | ||
8633 | /* Disable all transmit rings but the first. */ | |
63c3a66f | 8634 | if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 8635 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; |
63c3a66f | 8636 | else if (tg3_flag(tp, 5717_PLUS)) |
3d37728b | 8637 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
55086ad9 | 8638 | else if (tg3_flag(tp, 57765_CLASS)) |
b703df6f | 8639 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; |
2d31ecaf MC |
8640 | else |
8641 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
8642 | ||
8643 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
8644 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
8645 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
8646 | BDINFO_FLAGS_DISABLED); | |
8647 | ||
8648 | ||
8649 | /* Disable all receive return rings but the first. */ | |
63c3a66f | 8650 | if (tg3_flag(tp, 5717_PLUS)) |
f6eb9b1f | 8651 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
63c3a66f | 8652 | else if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 8653 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f | 8654 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
55086ad9 | 8655 | tg3_flag(tp, 57765_CLASS)) |
2d31ecaf MC |
8656 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
8657 | else | |
8658 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
8659 | ||
8660 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
8661 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
8662 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
8663 | BDINFO_FLAGS_DISABLED); | |
8664 | ||
8665 | /* Disable interrupts */ | |
8666 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
0e6cf6a9 MC |
8667 | tp->napi[0].chk_msi_cnt = 0; |
8668 | tp->napi[0].last_rx_cons = 0; | |
8669 | tp->napi[0].last_tx_cons = 0; | |
2d31ecaf MC |
8670 | |
8671 | /* Zero mailbox registers. */ | |
63c3a66f | 8672 | if (tg3_flag(tp, SUPPORT_MSIX)) { |
6fd45cb8 | 8673 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
8674 | tp->napi[i].tx_prod = 0; |
8675 | tp->napi[i].tx_cons = 0; | |
63c3a66f | 8676 | if (tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 8677 | tw32_mailbox(tp->napi[i].prodmbox, 0); |
f77a6a8e MC |
8678 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
8679 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7f230735 | 8680 | tp->napi[i].chk_msi_cnt = 0; |
0e6cf6a9 MC |
8681 | tp->napi[i].last_rx_cons = 0; |
8682 | tp->napi[i].last_tx_cons = 0; | |
f77a6a8e | 8683 | } |
63c3a66f | 8684 | if (!tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 8685 | tw32_mailbox(tp->napi[0].prodmbox, 0); |
f77a6a8e MC |
8686 | } else { |
8687 | tp->napi[0].tx_prod = 0; | |
8688 | tp->napi[0].tx_cons = 0; | |
8689 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
8690 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
8691 | } | |
2d31ecaf MC |
8692 | |
8693 | /* Make sure the NIC-based send BD rings are disabled. */ | |
63c3a66f | 8694 | if (!tg3_flag(tp, 5705_PLUS)) { |
2d31ecaf MC |
8695 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
8696 | for (i = 0; i < 16; i++) | |
8697 | tw32_tx_mbox(mbox + i * 8, 0); | |
8698 | } | |
8699 | ||
8700 | txrcb = NIC_SRAM_SEND_RCB; | |
8701 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
8702 | ||
8703 | /* Clear status block in ram. */ | |
8704 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8705 | ||
8706 | /* Set status block DMA address */ | |
8707 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
8708 | ((u64) tnapi->status_mapping >> 32)); | |
8709 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8710 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
8711 | ||
f77a6a8e MC |
8712 | if (tnapi->tx_ring) { |
8713 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8714 | (TG3_TX_RING_SIZE << | |
8715 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8716 | NIC_SRAM_TX_BUFFER_DESC); | |
8717 | txrcb += TG3_BDINFO_SIZE; | |
8718 | } | |
8719 | ||
8720 | if (tnapi->rx_rcb) { | |
8721 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
8722 | (tp->rx_ret_ring_mask + 1) << |
8723 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
8724 | rxrcb += TG3_BDINFO_SIZE; |
8725 | } | |
8726 | ||
8727 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 8728 | |
f77a6a8e MC |
8729 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
8730 | u64 mapping = (u64)tnapi->status_mapping; | |
8731 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
8732 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
8733 | ||
8734 | /* Clear status block in ram. */ | |
8735 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8736 | ||
19cfaecc MC |
8737 | if (tnapi->tx_ring) { |
8738 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8739 | (TG3_TX_RING_SIZE << | |
8740 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8741 | NIC_SRAM_TX_BUFFER_DESC); | |
8742 | txrcb += TG3_BDINFO_SIZE; | |
8743 | } | |
f77a6a8e MC |
8744 | |
8745 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 8746 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
8747 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
8748 | ||
8749 | stblk += 8; | |
f77a6a8e MC |
8750 | rxrcb += TG3_BDINFO_SIZE; |
8751 | } | |
2d31ecaf MC |
8752 | } |
8753 | ||
eb07a940 MC |
8754 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
8755 | { | |
8756 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
8757 | ||
63c3a66f JP |
8758 | if (!tg3_flag(tp, 5750_PLUS) || |
8759 | tg3_flag(tp, 5780_CLASS) || | |
eb07a940 | 8760 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
513aa6ea MC |
8761 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
8762 | tg3_flag(tp, 57765_PLUS)) | |
eb07a940 MC |
8763 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; |
8764 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
8765 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
8766 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
8767 | else | |
8768 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
8769 | ||
8770 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
8771 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
8772 | ||
8773 | val = min(nic_rep_thresh, host_rep_thresh); | |
8774 | tw32(RCVBDI_STD_THRESH, val); | |
8775 | ||
63c3a66f | 8776 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8777 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); |
8778 | ||
63c3a66f | 8779 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
eb07a940 MC |
8780 | return; |
8781 | ||
513aa6ea | 8782 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; |
eb07a940 MC |
8783 | |
8784 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
8785 | ||
8786 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
8787 | tw32(RCVBDI_JUMBO_THRESH, val); | |
8788 | ||
63c3a66f | 8789 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8790 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); |
8791 | } | |
8792 | ||
ccd5ba9d MC |
8793 | static inline u32 calc_crc(unsigned char *buf, int len) |
8794 | { | |
8795 | u32 reg; | |
8796 | u32 tmp; | |
8797 | int j, k; | |
8798 | ||
8799 | reg = 0xffffffff; | |
8800 | ||
8801 | for (j = 0; j < len; j++) { | |
8802 | reg ^= buf[j]; | |
8803 | ||
8804 | for (k = 0; k < 8; k++) { | |
8805 | tmp = reg & 0x01; | |
8806 | ||
8807 | reg >>= 1; | |
8808 | ||
8809 | if (tmp) | |
8810 | reg ^= 0xedb88320; | |
8811 | } | |
8812 | } | |
8813 | ||
8814 | return ~reg; | |
8815 | } | |
8816 | ||
8817 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
8818 | { | |
8819 | /* accept or reject all multicast frames */ | |
8820 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
8821 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
8822 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
8823 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
8824 | } | |
8825 | ||
8826 | static void __tg3_set_rx_mode(struct net_device *dev) | |
8827 | { | |
8828 | struct tg3 *tp = netdev_priv(dev); | |
8829 | u32 rx_mode; | |
8830 | ||
8831 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
8832 | RX_MODE_KEEP_VLAN_TAG); | |
8833 | ||
8834 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) | |
8835 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG | |
8836 | * flag clear. | |
8837 | */ | |
8838 | if (!tg3_flag(tp, ENABLE_ASF)) | |
8839 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
8840 | #endif | |
8841 | ||
8842 | if (dev->flags & IFF_PROMISC) { | |
8843 | /* Promiscuous mode. */ | |
8844 | rx_mode |= RX_MODE_PROMISC; | |
8845 | } else if (dev->flags & IFF_ALLMULTI) { | |
8846 | /* Accept all multicast. */ | |
8847 | tg3_set_multi(tp, 1); | |
8848 | } else if (netdev_mc_empty(dev)) { | |
8849 | /* Reject all multicast. */ | |
8850 | tg3_set_multi(tp, 0); | |
8851 | } else { | |
8852 | /* Accept one or more multicast(s). */ | |
8853 | struct netdev_hw_addr *ha; | |
8854 | u32 mc_filter[4] = { 0, }; | |
8855 | u32 regidx; | |
8856 | u32 bit; | |
8857 | u32 crc; | |
8858 | ||
8859 | netdev_for_each_mc_addr(ha, dev) { | |
8860 | crc = calc_crc(ha->addr, ETH_ALEN); | |
8861 | bit = ~crc & 0x7f; | |
8862 | regidx = (bit & 0x60) >> 5; | |
8863 | bit &= 0x1f; | |
8864 | mc_filter[regidx] |= (1 << bit); | |
8865 | } | |
8866 | ||
8867 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
8868 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
8869 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
8870 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
8871 | } | |
8872 | ||
8873 | if (rx_mode != tp->rx_mode) { | |
8874 | tp->rx_mode = rx_mode; | |
8875 | tw32_f(MAC_RX_MODE, rx_mode); | |
8876 | udelay(10); | |
8877 | } | |
8878 | } | |
8879 | ||
9102426a | 8880 | static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt) |
90415477 MC |
8881 | { |
8882 | int i; | |
8883 | ||
8884 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) | |
9102426a | 8885 | tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); |
90415477 MC |
8886 | } |
8887 | ||
8888 | static void tg3_rss_check_indir_tbl(struct tg3 *tp) | |
bcebcc46 MC |
8889 | { |
8890 | int i; | |
8891 | ||
8892 | if (!tg3_flag(tp, SUPPORT_MSIX)) | |
8893 | return; | |
8894 | ||
0b3ba055 | 8895 | if (tp->rxq_cnt == 1) { |
bcebcc46 | 8896 | memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); |
90415477 MC |
8897 | return; |
8898 | } | |
8899 | ||
8900 | /* Validate table against current IRQ count */ | |
8901 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
0b3ba055 | 8902 | if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) |
90415477 MC |
8903 | break; |
8904 | } | |
8905 | ||
8906 | if (i != TG3_RSS_INDIR_TBL_SIZE) | |
9102426a | 8907 | tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); |
bcebcc46 MC |
8908 | } |
8909 | ||
90415477 | 8910 | static void tg3_rss_write_indir_tbl(struct tg3 *tp) |
bcebcc46 MC |
8911 | { |
8912 | int i = 0; | |
8913 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8914 | ||
8915 | while (i < TG3_RSS_INDIR_TBL_SIZE) { | |
8916 | u32 val = tp->rss_ind_tbl[i]; | |
8917 | i++; | |
8918 | for (; i % 8; i++) { | |
8919 | val <<= 4; | |
8920 | val |= tp->rss_ind_tbl[i]; | |
8921 | } | |
8922 | tw32(reg, val); | |
8923 | reg += 4; | |
8924 | } | |
8925 | } | |
8926 | ||
1da177e4 | 8927 | /* tp->lock is held. */ |
8e7a22e3 | 8928 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
8929 | { |
8930 | u32 val, rdmac_mode; | |
8931 | int i, err, limit; | |
8fea32b9 | 8932 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
8933 | |
8934 | tg3_disable_ints(tp); | |
8935 | ||
8936 | tg3_stop_fw(tp); | |
8937 | ||
8938 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
8939 | ||
63c3a66f | 8940 | if (tg3_flag(tp, INIT_COMPLETE)) |
e6de8ad1 | 8941 | tg3_abort_hw(tp, 1); |
1da177e4 | 8942 | |
699c0193 MC |
8943 | /* Enable MAC control of LPI */ |
8944 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
8945 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
8946 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
8947 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
8948 | ||
8949 | tw32_f(TG3_CPMU_EEE_CTRL, | |
8950 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
8951 | ||
a386b901 MC |
8952 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
8953 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
8954 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
8955 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
8956 | ||
8957 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8958 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
8959 | ||
63c3a66f | 8960 | if (tg3_flag(tp, ENABLE_APE)) |
a386b901 MC |
8961 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; |
8962 | ||
8963 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
8964 | ||
8965 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
8966 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
8967 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
8968 | ||
8969 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 8970 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 8971 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
8972 | } |
8973 | ||
603f1173 | 8974 | if (reset_phy) |
d4d2c558 MC |
8975 | tg3_phy_reset(tp); |
8976 | ||
1da177e4 LT |
8977 | err = tg3_chip_reset(tp); |
8978 | if (err) | |
8979 | return err; | |
8980 | ||
8981 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
8982 | ||
bcb37f6c | 8983 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
8984 | val = tr32(TG3_CPMU_CTRL); |
8985 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
8986 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
8987 | |
8988 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8989 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8990 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8991 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8992 | ||
8993 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
8994 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
8995 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
8996 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
8997 | ||
8998 | val = tr32(TG3_CPMU_HST_ACC); | |
8999 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
9000 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
9001 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
9002 | } |
9003 | ||
33466d93 MC |
9004 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
9005 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
9006 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
9007 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
9008 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
9009 | |
9010 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
9011 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
9012 | ||
9013 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 9014 | |
f40386c8 MC |
9015 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
9016 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
9017 | } |
9018 | ||
63c3a66f | 9019 | if (tg3_flag(tp, L1PLLPD_EN)) { |
614b0590 MC |
9020 | u32 grc_mode = tr32(GRC_MODE); |
9021 | ||
9022 | /* Access the lower 1K of PL PCIE block registers. */ | |
9023 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
9024 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
9025 | ||
9026 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
9027 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
9028 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
9029 | ||
9030 | tw32(GRC_MODE, grc_mode); | |
9031 | } | |
9032 | ||
55086ad9 | 9033 | if (tg3_flag(tp, 57765_CLASS)) { |
5093eedc MC |
9034 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
9035 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 9036 | |
5093eedc MC |
9037 | /* Access the lower 1K of PL PCIE block registers. */ |
9038 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
9039 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 9040 | |
5093eedc MC |
9041 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
9042 | TG3_PCIE_PL_LO_PHYCTL5); | |
9043 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
9044 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 9045 | |
5093eedc MC |
9046 | tw32(GRC_MODE, grc_mode); |
9047 | } | |
a977dbe8 | 9048 | |
1ff30a59 MC |
9049 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { |
9050 | u32 grc_mode = tr32(GRC_MODE); | |
9051 | ||
9052 | /* Access the lower 1K of DL PCIE block registers. */ | |
9053 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
9054 | tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); | |
9055 | ||
9056 | val = tr32(TG3_PCIE_TLDLPL_PORT + | |
9057 | TG3_PCIE_DL_LO_FTSMAX); | |
9058 | val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; | |
9059 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, | |
9060 | val | TG3_PCIE_DL_LO_FTSMAX_VAL); | |
9061 | ||
9062 | tw32(GRC_MODE, grc_mode); | |
9063 | } | |
9064 | ||
a977dbe8 MC |
9065 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
9066 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
9067 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
9068 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
9069 | } |
9070 | ||
1da177e4 LT |
9071 | /* This works around an issue with Athlon chipsets on |
9072 | * B3 tigon3 silicon. This bit has no effect on any | |
9073 | * other revision. But do not set this on PCI Express | |
795d01c5 | 9074 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 9075 | */ |
63c3a66f JP |
9076 | if (!tg3_flag(tp, CPMU_PRESENT)) { |
9077 | if (!tg3_flag(tp, PCI_EXPRESS)) | |
795d01c5 MC |
9078 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; |
9079 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
9080 | } | |
1da177e4 LT |
9081 | |
9082 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 9083 | tg3_flag(tp, PCIX_MODE)) { |
1da177e4 LT |
9084 | val = tr32(TG3PCI_PCISTATE); |
9085 | val |= PCISTATE_RETRY_SAME_DMA; | |
9086 | tw32(TG3PCI_PCISTATE, val); | |
9087 | } | |
9088 | ||
63c3a66f | 9089 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
9090 | /* Allow reads and writes to the |
9091 | * APE register and memory space. | |
9092 | */ | |
9093 | val = tr32(TG3PCI_PCISTATE); | |
9094 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
9095 | PCISTATE_ALLOW_APE_SHMEM_WR | |
9096 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
9097 | tw32(TG3PCI_PCISTATE, val); |
9098 | } | |
9099 | ||
1da177e4 LT |
9100 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
9101 | /* Enable some hw fixes. */ | |
9102 | val = tr32(TG3PCI_MSI_DATA); | |
9103 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
9104 | tw32(TG3PCI_MSI_DATA, val); | |
9105 | } | |
9106 | ||
9107 | /* Descriptor ring init may make accesses to the | |
9108 | * NIC SRAM area to setup the TX descriptors, so we | |
9109 | * can only do this after the hardware has been | |
9110 | * successfully reset. | |
9111 | */ | |
32d8c572 MC |
9112 | err = tg3_init_rings(tp); |
9113 | if (err) | |
9114 | return err; | |
1da177e4 | 9115 | |
63c3a66f | 9116 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
9117 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
9118 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
9119 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
9120 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
55086ad9 | 9121 | if (!tg3_flag(tp, 57765_CLASS) && |
0aebff48 MC |
9122 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) |
9123 | val |= DMA_RWCTRL_TAGGED_STAT_WA; | |
cbf9ca6c MC |
9124 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
9125 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
9126 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
9127 | /* This value is determined during the probe time DMA |
9128 | * engine test, tg3_test_dma. | |
9129 | */ | |
9130 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
9131 | } | |
1da177e4 LT |
9132 | |
9133 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
9134 | GRC_MODE_4X_NIC_SEND_RINGS | | |
9135 | GRC_MODE_NO_TX_PHDR_CSUM | | |
9136 | GRC_MODE_NO_RX_PHDR_CSUM); | |
9137 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
9138 | |
9139 | /* Pseudo-header checksum is done by hardware logic and not | |
9140 | * the offload processers, so make the chip do the pseudo- | |
9141 | * header checksums on receive. For transmit it is more | |
9142 | * convenient to do the pseudo-header checksum in software | |
9143 | * as Linux does that on transmit for us in all cases. | |
9144 | */ | |
9145 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
9146 | |
9147 | tw32(GRC_MODE, | |
9148 | tp->grc_mode | | |
9149 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
9150 | ||
9151 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
9152 | val = tr32(GRC_MISC_CFG); | |
9153 | val &= ~0xff; | |
9154 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
9155 | tw32(GRC_MISC_CFG, val); | |
9156 | ||
9157 | /* Initialize MBUF/DESC pool. */ | |
63c3a66f | 9158 | if (tg3_flag(tp, 5750_PLUS)) { |
1da177e4 LT |
9159 | /* Do nothing. */ |
9160 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
9161 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
9162 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
9163 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
9164 | else | |
9165 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
9166 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
9167 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
63c3a66f | 9168 | } else if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
9169 | int fw_len; |
9170 | ||
077f849d | 9171 | fw_len = tp->fw_len; |
1da177e4 LT |
9172 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
9173 | tw32(BUFMGR_MB_POOL_ADDR, | |
9174 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
9175 | tw32(BUFMGR_MB_POOL_SIZE, | |
9176 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
9177 | } | |
1da177e4 | 9178 | |
0f893dc6 | 9179 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
9180 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
9181 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
9182 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
9183 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
9184 | tw32(BUFMGR_MB_HIGH_WATER, | |
9185 | tp->bufmgr_config.mbuf_high_water); | |
9186 | } else { | |
9187 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
9188 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
9189 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
9190 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
9191 | tw32(BUFMGR_MB_HIGH_WATER, | |
9192 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
9193 | } | |
9194 | tw32(BUFMGR_DMA_LOW_WATER, | |
9195 | tp->bufmgr_config.dma_low_water); | |
9196 | tw32(BUFMGR_DMA_HIGH_WATER, | |
9197 | tp->bufmgr_config.dma_high_water); | |
9198 | ||
d309a46e MC |
9199 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
9200 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
9201 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
4d958473 MC |
9202 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
9203 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
9204 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
9205 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
d309a46e | 9206 | tw32(BUFMGR_MODE, val); |
1da177e4 LT |
9207 | for (i = 0; i < 2000; i++) { |
9208 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
9209 | break; | |
9210 | udelay(10); | |
9211 | } | |
9212 | if (i >= 2000) { | |
05dbe005 | 9213 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
9214 | return -ENODEV; |
9215 | } | |
9216 | ||
eb07a940 MC |
9217 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
9218 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
b5d3772c | 9219 | |
eb07a940 | 9220 | tg3_setup_rxbd_thresholds(tp); |
1da177e4 LT |
9221 | |
9222 | /* Initialize TG3_BDINFO's at: | |
9223 | * RCVDBDI_STD_BD: standard eth size rx ring | |
9224 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
9225 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
9226 | * | |
9227 | * like so: | |
9228 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
9229 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
9230 | * ring attribute flags | |
9231 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
9232 | * | |
9233 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
9234 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
9235 | * | |
9236 | * The size of each ring is fixed in the firmware, but the location is | |
9237 | * configurable. | |
9238 | */ | |
9239 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 9240 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 9241 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 9242 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
63c3a66f | 9243 | if (!tg3_flag(tp, 5717_PLUS)) |
87668d35 MC |
9244 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
9245 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 9246 | |
fdb72b38 | 9247 | /* Disable the mini ring */ |
63c3a66f | 9248 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
9249 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
9250 | BDINFO_FLAGS_DISABLED); | |
9251 | ||
fdb72b38 MC |
9252 | /* Program the jumbo buffer descriptor ring control |
9253 | * blocks on those devices that have them. | |
9254 | */ | |
a0512944 | 9255 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
63c3a66f | 9256 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { |
1da177e4 | 9257 | |
63c3a66f | 9258 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { |
1da177e4 | 9259 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 9260 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 9261 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 9262 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
9263 | val = TG3_RX_JMB_RING_SIZE(tp) << |
9264 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 9265 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 9266 | val | BDINFO_FLAGS_USE_EXT_RECV); |
63c3a66f | 9267 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || |
55086ad9 | 9268 | tg3_flag(tp, 57765_CLASS)) |
87668d35 MC |
9269 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
9270 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
9271 | } else { |
9272 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
9273 | BDINFO_FLAGS_DISABLED); | |
9274 | } | |
9275 | ||
63c3a66f | 9276 | if (tg3_flag(tp, 57765_PLUS)) { |
fa6b2aae | 9277 | val = TG3_RX_STD_RING_SIZE(tp); |
7cb32cf2 MC |
9278 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
9279 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
9280 | } else | |
04380d40 | 9281 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 9282 | } else |
de9f5230 | 9283 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
9284 | |
9285 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 9286 | |
411da640 | 9287 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 9288 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 9289 | |
63c3a66f JP |
9290 | tpr->rx_jmb_prod_idx = |
9291 | tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; | |
66711e66 | 9292 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 9293 | |
2d31ecaf MC |
9294 | tg3_rings_reset(tp); |
9295 | ||
1da177e4 | 9296 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 9297 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
9298 | |
9299 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
9300 | tw32(MAC_RX_MTU_SIZE, |
9301 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
9302 | |
9303 | /* The slot time is changed by tg3_setup_phy if we | |
9304 | * run at gigabit with half duplex. | |
9305 | */ | |
f2096f94 MC |
9306 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
9307 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
9308 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
9309 | ||
9310 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
9311 | val |= tr32(MAC_TX_LENGTHS) & | |
9312 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
9313 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
9314 | ||
9315 | tw32(MAC_TX_LENGTHS, val); | |
1da177e4 LT |
9316 | |
9317 | /* Receive rules. */ | |
9318 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
9319 | tw32(RCVLPC_CONFIG, 0x0181); | |
9320 | ||
9321 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
9322 | * the RCVLPC_STATE_ENABLE mask. | |
9323 | */ | |
9324 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
9325 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
9326 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
9327 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
9328 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 9329 | |
deabaac8 | 9330 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
9331 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
9332 | ||
57e6983c | 9333 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
9334 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
9335 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
9336 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
9337 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
9338 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
9339 | ||
c5908939 MC |
9340 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
9341 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 9342 | if (tg3_flag(tp, TSO_CAPABLE) && |
c13e3713 | 9343 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
9344 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
9345 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 9346 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
9347 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
9348 | } | |
9349 | } | |
9350 | ||
63c3a66f | 9351 | if (tg3_flag(tp, PCI_EXPRESS)) |
85e94ced MC |
9352 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
9353 | ||
63c3a66f JP |
9354 | if (tg3_flag(tp, HW_TSO_1) || |
9355 | tg3_flag(tp, HW_TSO_2) || | |
9356 | tg3_flag(tp, HW_TSO_3)) | |
027455ad MC |
9357 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
9358 | ||
108a6c16 | 9359 | if (tg3_flag(tp, 57765_PLUS) || |
e849cdc3 | 9360 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
027455ad MC |
9361 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
9362 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 9363 | |
f2096f94 MC |
9364 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
9365 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
9366 | ||
41a8a7ee MC |
9367 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9368 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
9369 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
9370 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
63c3a66f | 9371 | tg3_flag(tp, 57765_PLUS)) { |
41a8a7ee | 9372 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
10ce95d6 | 9373 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) { |
b4495ed8 MC |
9374 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
9375 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
9376 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
9377 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
9378 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
9379 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 9380 | } |
41a8a7ee MC |
9381 | tw32(TG3_RDMA_RSRVCTRL_REG, |
9382 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
9383 | } | |
9384 | ||
d78b59f5 MC |
9385 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
9386 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
9387 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
9388 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
9389 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
9390 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
9391 | } | |
9392 | ||
1da177e4 | 9393 | /* Receive/send statistics. */ |
63c3a66f | 9394 | if (tg3_flag(tp, 5750_PLUS)) { |
1661394e MC |
9395 | val = tr32(RCVLPC_STATS_ENABLE); |
9396 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
9397 | tw32(RCVLPC_STATS_ENABLE, val); | |
9398 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
63c3a66f | 9399 | tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
9400 | val = tr32(RCVLPC_STATS_ENABLE); |
9401 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
9402 | tw32(RCVLPC_STATS_ENABLE, val); | |
9403 | } else { | |
9404 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
9405 | } | |
9406 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
9407 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
9408 | tw32(SNDDATAI_STATSCTRL, | |
9409 | (SNDDATAI_SCTRL_ENABLE | | |
9410 | SNDDATAI_SCTRL_FASTUPD)); | |
9411 | ||
9412 | /* Setup host coalescing engine. */ | |
9413 | tw32(HOSTCC_MODE, 0); | |
9414 | for (i = 0; i < 2000; i++) { | |
9415 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
9416 | break; | |
9417 | udelay(10); | |
9418 | } | |
9419 | ||
d244c892 | 9420 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 9421 | |
63c3a66f | 9422 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
9423 | /* Status/statistics block address. See tg3_timer, |
9424 | * the tg3_periodic_fetch_stats call there, and | |
9425 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
9426 | */ | |
1da177e4 LT |
9427 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
9428 | ((u64) tp->stats_mapping >> 32)); | |
9429 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
9430 | ((u64) tp->stats_mapping & 0xffffffff)); | |
9431 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 9432 | |
1da177e4 | 9433 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
9434 | |
9435 | /* Clear statistics and status block memory areas */ | |
9436 | for (i = NIC_SRAM_STATS_BLK; | |
9437 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
9438 | i += sizeof(u32)) { | |
9439 | tg3_write_mem(tp, i, 0); | |
9440 | udelay(40); | |
9441 | } | |
1da177e4 LT |
9442 | } |
9443 | ||
9444 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
9445 | ||
9446 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
9447 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
63c3a66f | 9448 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
9449 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); |
9450 | ||
f07e9af3 MC |
9451 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
9452 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
9453 | /* reset to prevent losing 1st rx packet intermittently */ |
9454 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
9455 | udelay(10); | |
9456 | } | |
9457 | ||
3bda1258 | 9458 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | |
9e975cc2 MC |
9459 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | |
9460 | MAC_MODE_FHDE_ENABLE; | |
9461 | if (tg3_flag(tp, ENABLE_APE)) | |
9462 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
63c3a66f | 9463 | if (!tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 9464 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
9465 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
9466 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
9467 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
9468 | udelay(40); | |
9469 | ||
314fba34 | 9470 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
63c3a66f | 9471 | * If TG3_FLAG_IS_NIC is zero, we should read the |
314fba34 MC |
9472 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
9473 | * whether used as inputs or outputs, are set by boot code after | |
9474 | * reset. | |
9475 | */ | |
63c3a66f | 9476 | if (!tg3_flag(tp, IS_NIC)) { |
314fba34 MC |
9477 | u32 gpio_mask; |
9478 | ||
9d26e213 MC |
9479 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
9480 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
9481 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
9482 | |
9483 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
9484 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
9485 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
9486 | ||
af36e6b6 MC |
9487 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
9488 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
9489 | ||
aaf84465 | 9490 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
9491 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
9492 | ||
9493 | /* GPIO1 must be driven high for eeprom write protect */ | |
63c3a66f | 9494 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) |
9d26e213 MC |
9495 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
9496 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 9497 | } |
1da177e4 LT |
9498 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
9499 | udelay(100); | |
9500 | ||
c3b5003b | 9501 | if (tg3_flag(tp, USING_MSIX)) { |
baf8a94a | 9502 | val = tr32(MSGINT_MODE); |
c3b5003b MC |
9503 | val |= MSGINT_MODE_ENABLE; |
9504 | if (tp->irq_cnt > 1) | |
9505 | val |= MSGINT_MODE_MULTIVEC_EN; | |
5b39de91 MC |
9506 | if (!tg3_flag(tp, 1SHOT_MSI)) |
9507 | val |= MSGINT_MODE_ONE_SHOT_DISABLE; | |
baf8a94a MC |
9508 | tw32(MSGINT_MODE, val); |
9509 | } | |
9510 | ||
63c3a66f | 9511 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
9512 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); |
9513 | udelay(40); | |
9514 | } | |
9515 | ||
9516 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
9517 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
9518 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
9519 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
9520 | WDMAC_MODE_LNGREAD_ENAB); | |
9521 | ||
c5908939 MC |
9522 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
9523 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 9524 | if (tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 LT |
9525 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
9526 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
9527 | /* nothing */ | |
9528 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 9529 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
9530 | val |= WDMAC_MODE_RX_ACCEL; |
9531 | } | |
9532 | } | |
9533 | ||
d9ab5ad1 | 9534 | /* Enable host coalescing bug fix */ |
63c3a66f | 9535 | if (tg3_flag(tp, 5755_PLUS)) |
f51f3562 | 9536 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 9537 | |
788a035e MC |
9538 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
9539 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
9540 | ||
1da177e4 LT |
9541 | tw32_f(WDMAC_MODE, val); |
9542 | udelay(40); | |
9543 | ||
63c3a66f | 9544 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
9545 | u16 pcix_cmd; |
9546 | ||
9547 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
9548 | &pcix_cmd); | |
1da177e4 | 9549 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
9550 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
9551 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 9552 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
9553 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
9554 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 9555 | } |
9974a356 MC |
9556 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
9557 | pcix_cmd); | |
1da177e4 LT |
9558 | } |
9559 | ||
9560 | tw32_f(RDMAC_MODE, rdmac_mode); | |
9561 | udelay(40); | |
9562 | ||
091f0ea3 MC |
9563 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { |
9564 | for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) { | |
9565 | if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) | |
9566 | break; | |
9567 | } | |
9568 | if (i < TG3_NUM_RDMA_CHANNELS) { | |
9569 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); | |
9570 | val |= TG3_LSO_RD_DMA_TX_LENGTH_WA; | |
9571 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); | |
9572 | tg3_flag_set(tp, 5719_RDMA_BUG); | |
9573 | } | |
9574 | } | |
9575 | ||
1da177e4 | 9576 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); |
63c3a66f | 9577 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 | 9578 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); |
9936bcf6 MC |
9579 | |
9580 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
9581 | tw32(SNDDATAC_MODE, | |
9582 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
9583 | else | |
9584 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
9585 | ||
1da177e4 LT |
9586 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
9587 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 9588 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
63c3a66f | 9589 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
7cb32cf2 MC |
9590 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
9591 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 9592 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
63c3a66f JP |
9593 | if (tg3_flag(tp, HW_TSO_1) || |
9594 | tg3_flag(tp, HW_TSO_2) || | |
9595 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 | 9596 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); |
baf8a94a | 9597 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
63c3a66f | 9598 | if (tg3_flag(tp, ENABLE_TSS)) |
baf8a94a MC |
9599 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
9600 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
9601 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
9602 | ||
9603 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9604 | err = tg3_load_5701_a0_firmware_fix(tp); | |
9605 | if (err) | |
9606 | return err; | |
9607 | } | |
9608 | ||
63c3a66f | 9609 | if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
9610 | err = tg3_load_tso_firmware(tp); |
9611 | if (err) | |
9612 | return err; | |
9613 | } | |
1da177e4 LT |
9614 | |
9615 | tp->tx_mode = TX_MODE_ENABLE; | |
f2096f94 | 9616 | |
63c3a66f | 9617 | if (tg3_flag(tp, 5755_PLUS) || |
b1d05210 MC |
9618 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
9619 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
f2096f94 MC |
9620 | |
9621 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
9622 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
9623 | tp->tx_mode &= ~val; | |
9624 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
9625 | } | |
9626 | ||
1da177e4 LT |
9627 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
9628 | udelay(100); | |
9629 | ||
63c3a66f | 9630 | if (tg3_flag(tp, ENABLE_RSS)) { |
bcebcc46 | 9631 | tg3_rss_write_indir_tbl(tp); |
baf8a94a MC |
9632 | |
9633 | /* Setup the "secret" hash key. */ | |
9634 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
9635 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
9636 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
9637 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
9638 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
9639 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
9640 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
9641 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
9642 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
9643 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
9644 | } | |
9645 | ||
1da177e4 | 9646 | tp->rx_mode = RX_MODE_ENABLE; |
63c3a66f | 9647 | if (tg3_flag(tp, 5755_PLUS)) |
af36e6b6 MC |
9648 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
9649 | ||
63c3a66f | 9650 | if (tg3_flag(tp, ENABLE_RSS)) |
baf8a94a MC |
9651 | tp->rx_mode |= RX_MODE_RSS_ENABLE | |
9652 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
9653 | RX_MODE_RSS_IPV6_HASH_EN | | |
9654 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
9655 | RX_MODE_RSS_IPV4_HASH_EN | | |
9656 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
9657 | ||
1da177e4 LT |
9658 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
9659 | udelay(10); | |
9660 | ||
1da177e4 LT |
9661 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
9662 | ||
9663 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 9664 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
9665 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
9666 | udelay(10); | |
9667 | } | |
9668 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
9669 | udelay(10); | |
9670 | ||
f07e9af3 | 9671 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 9672 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 9673 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
9674 | /* Set drive transmission level to 1.2V */ |
9675 | /* only if the signal pre-emphasis bit is not set */ | |
9676 | val = tr32(MAC_SERDES_CFG); | |
9677 | val &= 0xfffff000; | |
9678 | val |= 0x880; | |
9679 | tw32(MAC_SERDES_CFG, val); | |
9680 | } | |
9681 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
9682 | tw32(MAC_SERDES_CFG, 0x616000); | |
9683 | } | |
9684 | ||
9685 | /* Prevent chip from dropping frames when flow control | |
9686 | * is enabled. | |
9687 | */ | |
55086ad9 | 9688 | if (tg3_flag(tp, 57765_CLASS)) |
666bc831 MC |
9689 | val = 1; |
9690 | else | |
9691 | val = 2; | |
9692 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
9693 | |
9694 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 9695 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 | 9696 | /* Use hardware link auto-negotiation */ |
63c3a66f | 9697 | tg3_flag_set(tp, HW_AUTONEG); |
1da177e4 LT |
9698 | } |
9699 | ||
f07e9af3 | 9700 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
6ff6f81d | 9701 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
d4d2c558 MC |
9702 | u32 tmp; |
9703 | ||
9704 | tmp = tr32(SERDES_RX_CTRL); | |
9705 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
9706 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
9707 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
9708 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
9709 | } | |
9710 | ||
63c3a66f | 9711 | if (!tg3_flag(tp, USE_PHYLIB)) { |
c6700ce2 | 9712 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
80096068 | 9713 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; |
1da177e4 | 9714 | |
dd477003 MC |
9715 | err = tg3_setup_phy(tp, 0); |
9716 | if (err) | |
9717 | return err; | |
1da177e4 | 9718 | |
f07e9af3 MC |
9719 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
9720 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
9721 | u32 tmp; |
9722 | ||
9723 | /* Clear CRC stats. */ | |
9724 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
9725 | tg3_writephy(tp, MII_TG3_TEST1, | |
9726 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9727 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 9728 | } |
1da177e4 LT |
9729 | } |
9730 | } | |
9731 | ||
9732 | __tg3_set_rx_mode(tp->dev); | |
9733 | ||
9734 | /* Initialize receive rules. */ | |
9735 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
9736 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
9737 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
9738 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
9739 | ||
63c3a66f | 9740 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) |
1da177e4 LT |
9741 | limit = 8; |
9742 | else | |
9743 | limit = 16; | |
63c3a66f | 9744 | if (tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
9745 | limit -= 4; |
9746 | switch (limit) { | |
9747 | case 16: | |
9748 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
9749 | case 15: | |
9750 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
9751 | case 14: | |
9752 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
9753 | case 13: | |
9754 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
9755 | case 12: | |
9756 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
9757 | case 11: | |
9758 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
9759 | case 10: | |
9760 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
9761 | case 9: | |
9762 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
9763 | case 8: | |
9764 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
9765 | case 7: | |
9766 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
9767 | case 6: | |
9768 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
9769 | case 5: | |
9770 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
9771 | case 4: | |
9772 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
9773 | case 3: | |
9774 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
9775 | case 2: | |
9776 | case 1: | |
9777 | ||
9778 | default: | |
9779 | break; | |
855e1111 | 9780 | } |
1da177e4 | 9781 | |
63c3a66f | 9782 | if (tg3_flag(tp, ENABLE_APE)) |
9ce768ea MC |
9783 | /* Write our heartbeat update interval to APE. */ |
9784 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
9785 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 9786 | |
1da177e4 LT |
9787 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
9788 | ||
1da177e4 LT |
9789 | return 0; |
9790 | } | |
9791 | ||
9792 | /* Called at device open time to get the chip ready for | |
9793 | * packet processing. Invoked with tp->lock held. | |
9794 | */ | |
8e7a22e3 | 9795 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 9796 | { |
1da177e4 LT |
9797 | tg3_switch_clocks(tp); |
9798 | ||
9799 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
9800 | ||
2f751b67 | 9801 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
9802 | } |
9803 | ||
aed93e0b MC |
9804 | static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir) |
9805 | { | |
9806 | int i; | |
9807 | ||
9808 | for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) { | |
9809 | u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN; | |
9810 | ||
9811 | tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len); | |
9812 | off += len; | |
9813 | ||
9814 | if (ocir->signature != TG3_OCIR_SIG_MAGIC || | |
9815 | !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE)) | |
9816 | memset(ocir, 0, TG3_OCIR_LEN); | |
9817 | } | |
9818 | } | |
9819 | ||
9820 | /* sysfs attributes for hwmon */ | |
9821 | static ssize_t tg3_show_temp(struct device *dev, | |
9822 | struct device_attribute *devattr, char *buf) | |
9823 | { | |
9824 | struct pci_dev *pdev = to_pci_dev(dev); | |
9825 | struct net_device *netdev = pci_get_drvdata(pdev); | |
9826 | struct tg3 *tp = netdev_priv(netdev); | |
9827 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
9828 | u32 temperature; | |
9829 | ||
9830 | spin_lock_bh(&tp->lock); | |
9831 | tg3_ape_scratchpad_read(tp, &temperature, attr->index, | |
9832 | sizeof(temperature)); | |
9833 | spin_unlock_bh(&tp->lock); | |
9834 | return sprintf(buf, "%u\n", temperature); | |
9835 | } | |
9836 | ||
9837 | ||
9838 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL, | |
9839 | TG3_TEMP_SENSOR_OFFSET); | |
9840 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL, | |
9841 | TG3_TEMP_CAUTION_OFFSET); | |
9842 | static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL, | |
9843 | TG3_TEMP_MAX_OFFSET); | |
9844 | ||
9845 | static struct attribute *tg3_attributes[] = { | |
9846 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
9847 | &sensor_dev_attr_temp1_crit.dev_attr.attr, | |
9848 | &sensor_dev_attr_temp1_max.dev_attr.attr, | |
9849 | NULL | |
9850 | }; | |
9851 | ||
9852 | static const struct attribute_group tg3_group = { | |
9853 | .attrs = tg3_attributes, | |
9854 | }; | |
9855 | ||
aed93e0b MC |
9856 | static void tg3_hwmon_close(struct tg3 *tp) |
9857 | { | |
aed93e0b MC |
9858 | if (tp->hwmon_dev) { |
9859 | hwmon_device_unregister(tp->hwmon_dev); | |
9860 | tp->hwmon_dev = NULL; | |
9861 | sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group); | |
9862 | } | |
aed93e0b MC |
9863 | } |
9864 | ||
9865 | static void tg3_hwmon_open(struct tg3 *tp) | |
9866 | { | |
aed93e0b MC |
9867 | int i, err; |
9868 | u32 size = 0; | |
9869 | struct pci_dev *pdev = tp->pdev; | |
9870 | struct tg3_ocir ocirs[TG3_SD_NUM_RECS]; | |
9871 | ||
9872 | tg3_sd_scan_scratchpad(tp, ocirs); | |
9873 | ||
9874 | for (i = 0; i < TG3_SD_NUM_RECS; i++) { | |
9875 | if (!ocirs[i].src_data_length) | |
9876 | continue; | |
9877 | ||
9878 | size += ocirs[i].src_hdr_length; | |
9879 | size += ocirs[i].src_data_length; | |
9880 | } | |
9881 | ||
9882 | if (!size) | |
9883 | return; | |
9884 | ||
9885 | /* Register hwmon sysfs hooks */ | |
9886 | err = sysfs_create_group(&pdev->dev.kobj, &tg3_group); | |
9887 | if (err) { | |
9888 | dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n"); | |
9889 | return; | |
9890 | } | |
9891 | ||
9892 | tp->hwmon_dev = hwmon_device_register(&pdev->dev); | |
9893 | if (IS_ERR(tp->hwmon_dev)) { | |
9894 | tp->hwmon_dev = NULL; | |
9895 | dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); | |
9896 | sysfs_remove_group(&pdev->dev.kobj, &tg3_group); | |
9897 | } | |
aed93e0b MC |
9898 | } |
9899 | ||
9900 | ||
1da177e4 LT |
9901 | #define TG3_STAT_ADD32(PSTAT, REG) \ |
9902 | do { u32 __val = tr32(REG); \ | |
9903 | (PSTAT)->low += __val; \ | |
9904 | if ((PSTAT)->low < __val) \ | |
9905 | (PSTAT)->high += 1; \ | |
9906 | } while (0) | |
9907 | ||
9908 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
9909 | { | |
9910 | struct tg3_hw_stats *sp = tp->hw_stats; | |
9911 | ||
f4a46d1f | 9912 | if (!tp->link_up) |
1da177e4 LT |
9913 | return; |
9914 | ||
9915 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
9916 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
9917 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
9918 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
9919 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
9920 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
9921 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
9922 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
9923 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
9924 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
9925 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
9926 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
9927 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
091f0ea3 MC |
9928 | if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) && |
9929 | (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + | |
9930 | sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { | |
9931 | u32 val; | |
9932 | ||
9933 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); | |
9934 | val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA; | |
9935 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); | |
9936 | tg3_flag_clear(tp, 5719_RDMA_BUG); | |
9937 | } | |
1da177e4 LT |
9938 | |
9939 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
9940 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
9941 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
9942 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
9943 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
9944 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
9945 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
9946 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
9947 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
9948 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
9949 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
9950 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
9951 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
9952 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
9953 | |
9954 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
310050fa MC |
9955 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
9956 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && | |
9957 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { | |
4d958473 MC |
9958 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); |
9959 | } else { | |
9960 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
9961 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
9962 | if (val) { | |
9963 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
9964 | sp->rx_discards.low += val; | |
9965 | if (sp->rx_discards.low < val) | |
9966 | sp->rx_discards.high += 1; | |
9967 | } | |
9968 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
9969 | } | |
463d305b | 9970 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
1da177e4 LT |
9971 | } |
9972 | ||
0e6cf6a9 MC |
9973 | static void tg3_chk_missed_msi(struct tg3 *tp) |
9974 | { | |
9975 | u32 i; | |
9976 | ||
9977 | for (i = 0; i < tp->irq_cnt; i++) { | |
9978 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9979 | ||
9980 | if (tg3_has_work(tnapi)) { | |
9981 | if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && | |
9982 | tnapi->last_tx_cons == tnapi->tx_cons) { | |
9983 | if (tnapi->chk_msi_cnt < 1) { | |
9984 | tnapi->chk_msi_cnt++; | |
9985 | return; | |
9986 | } | |
7f230735 | 9987 | tg3_msi(0, tnapi); |
0e6cf6a9 MC |
9988 | } |
9989 | } | |
9990 | tnapi->chk_msi_cnt = 0; | |
9991 | tnapi->last_rx_cons = tnapi->rx_rcb_ptr; | |
9992 | tnapi->last_tx_cons = tnapi->tx_cons; | |
9993 | } | |
9994 | } | |
9995 | ||
1da177e4 LT |
9996 | static void tg3_timer(unsigned long __opaque) |
9997 | { | |
9998 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 9999 | |
5b190624 | 10000 | if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) |
f475f163 MC |
10001 | goto restart_timer; |
10002 | ||
f47c11ee | 10003 | spin_lock(&tp->lock); |
1da177e4 | 10004 | |
0e6cf6a9 | 10005 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
55086ad9 | 10006 | tg3_flag(tp, 57765_CLASS)) |
0e6cf6a9 MC |
10007 | tg3_chk_missed_msi(tp); |
10008 | ||
63c3a66f | 10009 | if (!tg3_flag(tp, TAGGED_STATUS)) { |
fac9b83e DM |
10010 | /* All of this garbage is because when using non-tagged |
10011 | * IRQ status the mailbox/status_block protocol the chip | |
10012 | * uses with the cpu is race prone. | |
10013 | */ | |
898a56f8 | 10014 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
10015 | tw32(GRC_LOCAL_CTRL, |
10016 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
10017 | } else { | |
10018 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 10019 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 10020 | } |
1da177e4 | 10021 | |
fac9b83e | 10022 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
f47c11ee | 10023 | spin_unlock(&tp->lock); |
db219973 | 10024 | tg3_reset_task_schedule(tp); |
5b190624 | 10025 | goto restart_timer; |
fac9b83e | 10026 | } |
1da177e4 LT |
10027 | } |
10028 | ||
1da177e4 LT |
10029 | /* This part only runs once per second. */ |
10030 | if (!--tp->timer_counter) { | |
63c3a66f | 10031 | if (tg3_flag(tp, 5705_PLUS)) |
fac9b83e DM |
10032 | tg3_periodic_fetch_stats(tp); |
10033 | ||
b0c5943f MC |
10034 | if (tp->setlpicnt && !--tp->setlpicnt) |
10035 | tg3_phy_eee_enable(tp); | |
52b02d04 | 10036 | |
63c3a66f | 10037 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
10038 | u32 mac_stat; |
10039 | int phy_event; | |
10040 | ||
10041 | mac_stat = tr32(MAC_STATUS); | |
10042 | ||
10043 | phy_event = 0; | |
f07e9af3 | 10044 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
10045 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
10046 | phy_event = 1; | |
10047 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
10048 | phy_event = 1; | |
10049 | ||
10050 | if (phy_event) | |
10051 | tg3_setup_phy(tp, 0); | |
63c3a66f | 10052 | } else if (tg3_flag(tp, POLL_SERDES)) { |
1da177e4 LT |
10053 | u32 mac_stat = tr32(MAC_STATUS); |
10054 | int need_setup = 0; | |
10055 | ||
f4a46d1f | 10056 | if (tp->link_up && |
1da177e4 LT |
10057 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { |
10058 | need_setup = 1; | |
10059 | } | |
f4a46d1f | 10060 | if (!tp->link_up && |
1da177e4 LT |
10061 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
10062 | MAC_STATUS_SIGNAL_DET))) { | |
10063 | need_setup = 1; | |
10064 | } | |
10065 | if (need_setup) { | |
3d3ebe74 MC |
10066 | if (!tp->serdes_counter) { |
10067 | tw32_f(MAC_MODE, | |
10068 | (tp->mac_mode & | |
10069 | ~MAC_MODE_PORT_MODE_MASK)); | |
10070 | udelay(40); | |
10071 | tw32_f(MAC_MODE, tp->mac_mode); | |
10072 | udelay(40); | |
10073 | } | |
1da177e4 LT |
10074 | tg3_setup_phy(tp, 0); |
10075 | } | |
f07e9af3 | 10076 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
63c3a66f | 10077 | tg3_flag(tp, 5780_CLASS)) { |
747e8f8b | 10078 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 10079 | } |
1da177e4 LT |
10080 | |
10081 | tp->timer_counter = tp->timer_multiplier; | |
10082 | } | |
10083 | ||
130b8e4d MC |
10084 | /* Heartbeat is only sent once every 2 seconds. |
10085 | * | |
10086 | * The heartbeat is to tell the ASF firmware that the host | |
10087 | * driver is still alive. In the event that the OS crashes, | |
10088 | * ASF needs to reset the hardware to free up the FIFO space | |
10089 | * that may be filled with rx packets destined for the host. | |
10090 | * If the FIFO is full, ASF will no longer function properly. | |
10091 | * | |
10092 | * Unintended resets have been reported on real time kernels | |
10093 | * where the timer doesn't run on time. Netpoll will also have | |
10094 | * same problem. | |
10095 | * | |
10096 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
10097 | * to check the ring condition when the heartbeat is expiring | |
10098 | * before doing the reset. This will prevent most unintended | |
10099 | * resets. | |
10100 | */ | |
1da177e4 | 10101 | if (!--tp->asf_counter) { |
63c3a66f | 10102 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
10103 | tg3_wait_for_event_ack(tp); |
10104 | ||
bbadf503 | 10105 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 10106 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 10107 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
10108 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
10109 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
10110 | |
10111 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
10112 | } |
10113 | tp->asf_counter = tp->asf_multiplier; | |
10114 | } | |
10115 | ||
f47c11ee | 10116 | spin_unlock(&tp->lock); |
1da177e4 | 10117 | |
f475f163 | 10118 | restart_timer: |
1da177e4 LT |
10119 | tp->timer.expires = jiffies + tp->timer_offset; |
10120 | add_timer(&tp->timer); | |
10121 | } | |
10122 | ||
229b1ad1 | 10123 | static void tg3_timer_init(struct tg3 *tp) |
21f7638e MC |
10124 | { |
10125 | if (tg3_flag(tp, TAGGED_STATUS) && | |
10126 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
10127 | !tg3_flag(tp, 57765_CLASS)) | |
10128 | tp->timer_offset = HZ; | |
10129 | else | |
10130 | tp->timer_offset = HZ / 10; | |
10131 | ||
10132 | BUG_ON(tp->timer_offset > HZ); | |
10133 | ||
10134 | tp->timer_multiplier = (HZ / tp->timer_offset); | |
10135 | tp->asf_multiplier = (HZ / tp->timer_offset) * | |
10136 | TG3_FW_UPDATE_FREQ_SEC; | |
10137 | ||
10138 | init_timer(&tp->timer); | |
10139 | tp->timer.data = (unsigned long) tp; | |
10140 | tp->timer.function = tg3_timer; | |
10141 | } | |
10142 | ||
10143 | static void tg3_timer_start(struct tg3 *tp) | |
10144 | { | |
10145 | tp->asf_counter = tp->asf_multiplier; | |
10146 | tp->timer_counter = tp->timer_multiplier; | |
10147 | ||
10148 | tp->timer.expires = jiffies + tp->timer_offset; | |
10149 | add_timer(&tp->timer); | |
10150 | } | |
10151 | ||
10152 | static void tg3_timer_stop(struct tg3 *tp) | |
10153 | { | |
10154 | del_timer_sync(&tp->timer); | |
10155 | } | |
10156 | ||
10157 | /* Restart hardware after configuration changes, self-test, etc. | |
10158 | * Invoked with tp->lock held. | |
10159 | */ | |
10160 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
10161 | __releases(tp->lock) | |
10162 | __acquires(tp->lock) | |
10163 | { | |
10164 | int err; | |
10165 | ||
10166 | err = tg3_init_hw(tp, reset_phy); | |
10167 | if (err) { | |
10168 | netdev_err(tp->dev, | |
10169 | "Failed to re-initialize device, aborting\n"); | |
10170 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10171 | tg3_full_unlock(tp); | |
10172 | tg3_timer_stop(tp); | |
10173 | tp->irq_sync = 0; | |
10174 | tg3_napi_enable(tp); | |
10175 | dev_close(tp->dev); | |
10176 | tg3_full_lock(tp, 0); | |
10177 | } | |
10178 | return err; | |
10179 | } | |
10180 | ||
10181 | static void tg3_reset_task(struct work_struct *work) | |
10182 | { | |
10183 | struct tg3 *tp = container_of(work, struct tg3, reset_task); | |
10184 | int err; | |
10185 | ||
10186 | tg3_full_lock(tp, 0); | |
10187 | ||
10188 | if (!netif_running(tp->dev)) { | |
10189 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
10190 | tg3_full_unlock(tp); | |
10191 | return; | |
10192 | } | |
10193 | ||
10194 | tg3_full_unlock(tp); | |
10195 | ||
10196 | tg3_phy_stop(tp); | |
10197 | ||
10198 | tg3_netif_stop(tp); | |
10199 | ||
10200 | tg3_full_lock(tp, 1); | |
10201 | ||
10202 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { | |
10203 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
10204 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
10205 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
10206 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | |
10207 | } | |
10208 | ||
10209 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
10210 | err = tg3_init_hw(tp, 1); | |
10211 | if (err) | |
10212 | goto out; | |
10213 | ||
10214 | tg3_netif_start(tp); | |
10215 | ||
10216 | out: | |
10217 | tg3_full_unlock(tp); | |
10218 | ||
10219 | if (!err) | |
10220 | tg3_phy_start(tp); | |
10221 | ||
10222 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
10223 | } | |
10224 | ||
4f125f42 | 10225 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 10226 | { |
7d12e780 | 10227 | irq_handler_t fn; |
fcfa0a32 | 10228 | unsigned long flags; |
4f125f42 MC |
10229 | char *name; |
10230 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
10231 | ||
10232 | if (tp->irq_cnt == 1) | |
10233 | name = tp->dev->name; | |
10234 | else { | |
10235 | name = &tnapi->irq_lbl[0]; | |
10236 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
10237 | name[IFNAMSIZ-1] = 0; | |
10238 | } | |
fcfa0a32 | 10239 | |
63c3a66f | 10240 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
fcfa0a32 | 10241 | fn = tg3_msi; |
63c3a66f | 10242 | if (tg3_flag(tp, 1SHOT_MSI)) |
fcfa0a32 | 10243 | fn = tg3_msi_1shot; |
ab392d2d | 10244 | flags = 0; |
fcfa0a32 MC |
10245 | } else { |
10246 | fn = tg3_interrupt; | |
63c3a66f | 10247 | if (tg3_flag(tp, TAGGED_STATUS)) |
fcfa0a32 | 10248 | fn = tg3_interrupt_tagged; |
ab392d2d | 10249 | flags = IRQF_SHARED; |
fcfa0a32 | 10250 | } |
4f125f42 MC |
10251 | |
10252 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
10253 | } |
10254 | ||
7938109f MC |
10255 | static int tg3_test_interrupt(struct tg3 *tp) |
10256 | { | |
09943a18 | 10257 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 10258 | struct net_device *dev = tp->dev; |
b16250e3 | 10259 | int err, i, intr_ok = 0; |
f6eb9b1f | 10260 | u32 val; |
7938109f | 10261 | |
d4bc3927 MC |
10262 | if (!netif_running(dev)) |
10263 | return -ENODEV; | |
10264 | ||
7938109f MC |
10265 | tg3_disable_ints(tp); |
10266 | ||
4f125f42 | 10267 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 10268 | |
f6eb9b1f MC |
10269 | /* |
10270 | * Turn off MSI one shot mode. Otherwise this test has no | |
10271 | * observable way to know whether the interrupt was delivered. | |
10272 | */ | |
3aa1cdf8 | 10273 | if (tg3_flag(tp, 57765_PLUS)) { |
f6eb9b1f MC |
10274 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; |
10275 | tw32(MSGINT_MODE, val); | |
10276 | } | |
10277 | ||
4f125f42 | 10278 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
f274fd9a | 10279 | IRQF_SHARED, dev->name, tnapi); |
7938109f MC |
10280 | if (err) |
10281 | return err; | |
10282 | ||
898a56f8 | 10283 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
10284 | tg3_enable_ints(tp); |
10285 | ||
10286 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 10287 | tnapi->coal_now); |
7938109f MC |
10288 | |
10289 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
10290 | u32 int_mbox, misc_host_ctrl; |
10291 | ||
898a56f8 | 10292 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
10293 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
10294 | ||
10295 | if ((int_mbox != 0) || | |
10296 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
10297 | intr_ok = 1; | |
7938109f | 10298 | break; |
b16250e3 MC |
10299 | } |
10300 | ||
3aa1cdf8 MC |
10301 | if (tg3_flag(tp, 57765_PLUS) && |
10302 | tnapi->hw_status->status_tag != tnapi->last_tag) | |
10303 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
10304 | ||
7938109f MC |
10305 | msleep(10); |
10306 | } | |
10307 | ||
10308 | tg3_disable_ints(tp); | |
10309 | ||
4f125f42 | 10310 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 10311 | |
4f125f42 | 10312 | err = tg3_request_irq(tp, 0); |
7938109f MC |
10313 | |
10314 | if (err) | |
10315 | return err; | |
10316 | ||
f6eb9b1f MC |
10317 | if (intr_ok) { |
10318 | /* Reenable MSI one shot mode. */ | |
5b39de91 | 10319 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { |
f6eb9b1f MC |
10320 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; |
10321 | tw32(MSGINT_MODE, val); | |
10322 | } | |
7938109f | 10323 | return 0; |
f6eb9b1f | 10324 | } |
7938109f MC |
10325 | |
10326 | return -EIO; | |
10327 | } | |
10328 | ||
10329 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
10330 | * successfully restored | |
10331 | */ | |
10332 | static int tg3_test_msi(struct tg3 *tp) | |
10333 | { | |
7938109f MC |
10334 | int err; |
10335 | u16 pci_cmd; | |
10336 | ||
63c3a66f | 10337 | if (!tg3_flag(tp, USING_MSI)) |
7938109f MC |
10338 | return 0; |
10339 | ||
10340 | /* Turn off SERR reporting in case MSI terminates with Master | |
10341 | * Abort. | |
10342 | */ | |
10343 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
10344 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
10345 | pci_cmd & ~PCI_COMMAND_SERR); | |
10346 | ||
10347 | err = tg3_test_interrupt(tp); | |
10348 | ||
10349 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
10350 | ||
10351 | if (!err) | |
10352 | return 0; | |
10353 | ||
10354 | /* other failures */ | |
10355 | if (err != -EIO) | |
10356 | return err; | |
10357 | ||
10358 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
10359 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
10360 | "to INTx mode. Please report this failure to the PCI " | |
10361 | "maintainer and include system chipset information\n"); | |
7938109f | 10362 | |
4f125f42 | 10363 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 10364 | |
7938109f MC |
10365 | pci_disable_msi(tp->pdev); |
10366 | ||
63c3a66f | 10367 | tg3_flag_clear(tp, USING_MSI); |
dc8bf1b1 | 10368 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 10369 | |
4f125f42 | 10370 | err = tg3_request_irq(tp, 0); |
7938109f MC |
10371 | if (err) |
10372 | return err; | |
10373 | ||
10374 | /* Need to reset the chip because the MSI cycle may have terminated | |
10375 | * with Master Abort. | |
10376 | */ | |
f47c11ee | 10377 | tg3_full_lock(tp, 1); |
7938109f | 10378 | |
944d980e | 10379 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 10380 | err = tg3_init_hw(tp, 1); |
7938109f | 10381 | |
f47c11ee | 10382 | tg3_full_unlock(tp); |
7938109f MC |
10383 | |
10384 | if (err) | |
4f125f42 | 10385 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
10386 | |
10387 | return err; | |
10388 | } | |
10389 | ||
9e9fd12d MC |
10390 | static int tg3_request_firmware(struct tg3 *tp) |
10391 | { | |
10392 | const __be32 *fw_data; | |
10393 | ||
10394 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
10395 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
10396 | tp->fw_needed); | |
9e9fd12d MC |
10397 | return -ENOENT; |
10398 | } | |
10399 | ||
10400 | fw_data = (void *)tp->fw->data; | |
10401 | ||
10402 | /* Firmware blob starts with version numbers, followed by | |
10403 | * start address and _full_ length including BSS sections | |
10404 | * (which must be longer than the actual data, of course | |
10405 | */ | |
10406 | ||
10407 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
10408 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
10409 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
10410 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
10411 | release_firmware(tp->fw); |
10412 | tp->fw = NULL; | |
10413 | return -EINVAL; | |
10414 | } | |
10415 | ||
10416 | /* We no longer need firmware; we have it. */ | |
10417 | tp->fw_needed = NULL; | |
10418 | return 0; | |
10419 | } | |
10420 | ||
9102426a | 10421 | static u32 tg3_irq_count(struct tg3 *tp) |
679563f4 | 10422 | { |
9102426a | 10423 | u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); |
679563f4 | 10424 | |
9102426a | 10425 | if (irq_cnt > 1) { |
c3b5003b MC |
10426 | /* We want as many rx rings enabled as there are cpus. |
10427 | * In multiqueue MSI-X mode, the first MSI-X vector | |
10428 | * only deals with link interrupts, etc, so we add | |
10429 | * one to the number of vectors we are requesting. | |
10430 | */ | |
9102426a | 10431 | irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); |
c3b5003b | 10432 | } |
679563f4 | 10433 | |
9102426a MC |
10434 | return irq_cnt; |
10435 | } | |
10436 | ||
10437 | static bool tg3_enable_msix(struct tg3 *tp) | |
10438 | { | |
10439 | int i, rc; | |
86449944 | 10440 | struct msix_entry msix_ent[TG3_IRQ_MAX_VECS]; |
9102426a | 10441 | |
0968169c MC |
10442 | tp->txq_cnt = tp->txq_req; |
10443 | tp->rxq_cnt = tp->rxq_req; | |
10444 | if (!tp->rxq_cnt) | |
10445 | tp->rxq_cnt = netif_get_num_default_rss_queues(); | |
9102426a MC |
10446 | if (tp->rxq_cnt > tp->rxq_max) |
10447 | tp->rxq_cnt = tp->rxq_max; | |
cf6d6ea6 MC |
10448 | |
10449 | /* Disable multiple TX rings by default. Simple round-robin hardware | |
10450 | * scheduling of the TX rings can cause starvation of rings with | |
10451 | * small packets when other rings have TSO or jumbo packets. | |
10452 | */ | |
10453 | if (!tp->txq_req) | |
10454 | tp->txq_cnt = 1; | |
9102426a MC |
10455 | |
10456 | tp->irq_cnt = tg3_irq_count(tp); | |
10457 | ||
679563f4 MC |
10458 | for (i = 0; i < tp->irq_max; i++) { |
10459 | msix_ent[i].entry = i; | |
10460 | msix_ent[i].vector = 0; | |
10461 | } | |
10462 | ||
10463 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
10464 | if (rc < 0) { |
10465 | return false; | |
10466 | } else if (rc != 0) { | |
679563f4 MC |
10467 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
10468 | return false; | |
05dbe005 JP |
10469 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
10470 | tp->irq_cnt, rc); | |
679563f4 | 10471 | tp->irq_cnt = rc; |
49a359e3 | 10472 | tp->rxq_cnt = max(rc - 1, 1); |
9102426a MC |
10473 | if (tp->txq_cnt) |
10474 | tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); | |
679563f4 MC |
10475 | } |
10476 | ||
10477 | for (i = 0; i < tp->irq_max; i++) | |
10478 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
10479 | ||
49a359e3 | 10480 | if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { |
2ddaad39 BH |
10481 | pci_disable_msix(tp->pdev); |
10482 | return false; | |
10483 | } | |
b92b9040 | 10484 | |
9102426a MC |
10485 | if (tp->irq_cnt == 1) |
10486 | return true; | |
d78b59f5 | 10487 | |
9102426a MC |
10488 | tg3_flag_set(tp, ENABLE_RSS); |
10489 | ||
10490 | if (tp->txq_cnt > 1) | |
10491 | tg3_flag_set(tp, ENABLE_TSS); | |
10492 | ||
10493 | netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); | |
2430b031 | 10494 | |
679563f4 MC |
10495 | return true; |
10496 | } | |
10497 | ||
07b0173c MC |
10498 | static void tg3_ints_init(struct tg3 *tp) |
10499 | { | |
63c3a66f JP |
10500 | if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && |
10501 | !tg3_flag(tp, TAGGED_STATUS)) { | |
07b0173c MC |
10502 | /* All MSI supporting chips should support tagged |
10503 | * status. Assert that this is the case. | |
10504 | */ | |
5129c3a3 MC |
10505 | netdev_warn(tp->dev, |
10506 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 10507 | goto defcfg; |
07b0173c | 10508 | } |
4f125f42 | 10509 | |
63c3a66f JP |
10510 | if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) |
10511 | tg3_flag_set(tp, USING_MSIX); | |
10512 | else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) | |
10513 | tg3_flag_set(tp, USING_MSI); | |
679563f4 | 10514 | |
63c3a66f | 10515 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
679563f4 | 10516 | u32 msi_mode = tr32(MSGINT_MODE); |
63c3a66f | 10517 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) |
baf8a94a | 10518 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
5b39de91 MC |
10519 | if (!tg3_flag(tp, 1SHOT_MSI)) |
10520 | msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE; | |
679563f4 MC |
10521 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
10522 | } | |
10523 | defcfg: | |
63c3a66f | 10524 | if (!tg3_flag(tp, USING_MSIX)) { |
679563f4 MC |
10525 | tp->irq_cnt = 1; |
10526 | tp->napi[0].irq_vec = tp->pdev->irq; | |
49a359e3 MC |
10527 | } |
10528 | ||
10529 | if (tp->irq_cnt == 1) { | |
10530 | tp->txq_cnt = 1; | |
10531 | tp->rxq_cnt = 1; | |
2ddaad39 | 10532 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 10533 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 10534 | } |
07b0173c MC |
10535 | } |
10536 | ||
10537 | static void tg3_ints_fini(struct tg3 *tp) | |
10538 | { | |
63c3a66f | 10539 | if (tg3_flag(tp, USING_MSIX)) |
679563f4 | 10540 | pci_disable_msix(tp->pdev); |
63c3a66f | 10541 | else if (tg3_flag(tp, USING_MSI)) |
679563f4 | 10542 | pci_disable_msi(tp->pdev); |
63c3a66f JP |
10543 | tg3_flag_clear(tp, USING_MSI); |
10544 | tg3_flag_clear(tp, USING_MSIX); | |
10545 | tg3_flag_clear(tp, ENABLE_RSS); | |
10546 | tg3_flag_clear(tp, ENABLE_TSS); | |
07b0173c MC |
10547 | } |
10548 | ||
be947307 MC |
10549 | static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq, |
10550 | bool init) | |
1da177e4 | 10551 | { |
d8f4cd38 | 10552 | struct net_device *dev = tp->dev; |
4f125f42 | 10553 | int i, err; |
1da177e4 | 10554 | |
679563f4 MC |
10555 | /* |
10556 | * Setup interrupts first so we know how | |
10557 | * many NAPI resources to allocate | |
10558 | */ | |
10559 | tg3_ints_init(tp); | |
10560 | ||
90415477 | 10561 | tg3_rss_check_indir_tbl(tp); |
bcebcc46 | 10562 | |
1da177e4 LT |
10563 | /* The placement of this call is tied |
10564 | * to the setup and use of Host TX descriptors. | |
10565 | */ | |
10566 | err = tg3_alloc_consistent(tp); | |
10567 | if (err) | |
679563f4 | 10568 | goto err_out1; |
88b06bc2 | 10569 | |
66cfd1bd MC |
10570 | tg3_napi_init(tp); |
10571 | ||
fed97810 | 10572 | tg3_napi_enable(tp); |
1da177e4 | 10573 | |
4f125f42 MC |
10574 | for (i = 0; i < tp->irq_cnt; i++) { |
10575 | struct tg3_napi *tnapi = &tp->napi[i]; | |
10576 | err = tg3_request_irq(tp, i); | |
10577 | if (err) { | |
5bc09186 MC |
10578 | for (i--; i >= 0; i--) { |
10579 | tnapi = &tp->napi[i]; | |
4f125f42 | 10580 | free_irq(tnapi->irq_vec, tnapi); |
5bc09186 MC |
10581 | } |
10582 | goto err_out2; | |
4f125f42 MC |
10583 | } |
10584 | } | |
1da177e4 | 10585 | |
f47c11ee | 10586 | tg3_full_lock(tp, 0); |
1da177e4 | 10587 | |
d8f4cd38 | 10588 | err = tg3_init_hw(tp, reset_phy); |
1da177e4 | 10589 | if (err) { |
944d980e | 10590 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 10591 | tg3_free_rings(tp); |
1da177e4 LT |
10592 | } |
10593 | ||
f47c11ee | 10594 | tg3_full_unlock(tp); |
1da177e4 | 10595 | |
07b0173c | 10596 | if (err) |
679563f4 | 10597 | goto err_out3; |
1da177e4 | 10598 | |
d8f4cd38 | 10599 | if (test_irq && tg3_flag(tp, USING_MSI)) { |
7938109f | 10600 | err = tg3_test_msi(tp); |
fac9b83e | 10601 | |
7938109f | 10602 | if (err) { |
f47c11ee | 10603 | tg3_full_lock(tp, 0); |
944d980e | 10604 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 10605 | tg3_free_rings(tp); |
f47c11ee | 10606 | tg3_full_unlock(tp); |
7938109f | 10607 | |
679563f4 | 10608 | goto err_out2; |
7938109f | 10609 | } |
fcfa0a32 | 10610 | |
63c3a66f | 10611 | if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f | 10612 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 10613 | |
f6eb9b1f MC |
10614 | tw32(PCIE_TRANSACTION_CFG, |
10615 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 10616 | } |
7938109f MC |
10617 | } |
10618 | ||
b02fd9e3 MC |
10619 | tg3_phy_start(tp); |
10620 | ||
aed93e0b MC |
10621 | tg3_hwmon_open(tp); |
10622 | ||
f47c11ee | 10623 | tg3_full_lock(tp, 0); |
1da177e4 | 10624 | |
21f7638e | 10625 | tg3_timer_start(tp); |
63c3a66f | 10626 | tg3_flag_set(tp, INIT_COMPLETE); |
1da177e4 LT |
10627 | tg3_enable_ints(tp); |
10628 | ||
be947307 MC |
10629 | if (init) |
10630 | tg3_ptp_init(tp); | |
10631 | else | |
10632 | tg3_ptp_resume(tp); | |
10633 | ||
10634 | ||
f47c11ee | 10635 | tg3_full_unlock(tp); |
1da177e4 | 10636 | |
fe5f5787 | 10637 | netif_tx_start_all_queues(dev); |
1da177e4 | 10638 | |
06c03c02 MB |
10639 | /* |
10640 | * Reset loopback feature if it was turned on while the device was down | |
10641 | * make sure that it's installed properly now. | |
10642 | */ | |
10643 | if (dev->features & NETIF_F_LOOPBACK) | |
10644 | tg3_set_loopback(dev, dev->features); | |
10645 | ||
1da177e4 | 10646 | return 0; |
07b0173c | 10647 | |
679563f4 | 10648 | err_out3: |
4f125f42 MC |
10649 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
10650 | struct tg3_napi *tnapi = &tp->napi[i]; | |
10651 | free_irq(tnapi->irq_vec, tnapi); | |
10652 | } | |
07b0173c | 10653 | |
679563f4 | 10654 | err_out2: |
fed97810 | 10655 | tg3_napi_disable(tp); |
66cfd1bd | 10656 | tg3_napi_fini(tp); |
07b0173c | 10657 | tg3_free_consistent(tp); |
679563f4 MC |
10658 | |
10659 | err_out1: | |
10660 | tg3_ints_fini(tp); | |
d8f4cd38 | 10661 | |
07b0173c | 10662 | return err; |
1da177e4 LT |
10663 | } |
10664 | ||
65138594 | 10665 | static void tg3_stop(struct tg3 *tp) |
1da177e4 | 10666 | { |
4f125f42 | 10667 | int i; |
1da177e4 | 10668 | |
db219973 | 10669 | tg3_reset_task_cancel(tp); |
bd473da3 | 10670 | tg3_netif_stop(tp); |
1da177e4 | 10671 | |
21f7638e | 10672 | tg3_timer_stop(tp); |
1da177e4 | 10673 | |
aed93e0b MC |
10674 | tg3_hwmon_close(tp); |
10675 | ||
24bb4fb6 MC |
10676 | tg3_phy_stop(tp); |
10677 | ||
f47c11ee | 10678 | tg3_full_lock(tp, 1); |
1da177e4 LT |
10679 | |
10680 | tg3_disable_ints(tp); | |
10681 | ||
944d980e | 10682 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 10683 | tg3_free_rings(tp); |
63c3a66f | 10684 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 10685 | |
f47c11ee | 10686 | tg3_full_unlock(tp); |
1da177e4 | 10687 | |
4f125f42 MC |
10688 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
10689 | struct tg3_napi *tnapi = &tp->napi[i]; | |
10690 | free_irq(tnapi->irq_vec, tnapi); | |
10691 | } | |
07b0173c MC |
10692 | |
10693 | tg3_ints_fini(tp); | |
1da177e4 | 10694 | |
66cfd1bd MC |
10695 | tg3_napi_fini(tp); |
10696 | ||
1da177e4 | 10697 | tg3_free_consistent(tp); |
65138594 MC |
10698 | } |
10699 | ||
d8f4cd38 MC |
10700 | static int tg3_open(struct net_device *dev) |
10701 | { | |
10702 | struct tg3 *tp = netdev_priv(dev); | |
10703 | int err; | |
10704 | ||
10705 | if (tp->fw_needed) { | |
10706 | err = tg3_request_firmware(tp); | |
10707 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
10708 | if (err) | |
10709 | return err; | |
10710 | } else if (err) { | |
10711 | netdev_warn(tp->dev, "TSO capability disabled\n"); | |
10712 | tg3_flag_clear(tp, TSO_CAPABLE); | |
10713 | } else if (!tg3_flag(tp, TSO_CAPABLE)) { | |
10714 | netdev_notice(tp->dev, "TSO capability restored\n"); | |
10715 | tg3_flag_set(tp, TSO_CAPABLE); | |
10716 | } | |
10717 | } | |
10718 | ||
f4a46d1f | 10719 | tg3_carrier_off(tp); |
d8f4cd38 MC |
10720 | |
10721 | err = tg3_power_up(tp); | |
10722 | if (err) | |
10723 | return err; | |
10724 | ||
10725 | tg3_full_lock(tp, 0); | |
10726 | ||
10727 | tg3_disable_ints(tp); | |
10728 | tg3_flag_clear(tp, INIT_COMPLETE); | |
10729 | ||
10730 | tg3_full_unlock(tp); | |
10731 | ||
be947307 | 10732 | err = tg3_start(tp, true, true, true); |
d8f4cd38 MC |
10733 | if (err) { |
10734 | tg3_frob_aux_power(tp, false); | |
10735 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
10736 | } | |
be947307 | 10737 | |
7d41e49a MC |
10738 | if (tg3_flag(tp, PTP_CAPABLE)) { |
10739 | tp->ptp_clock = ptp_clock_register(&tp->ptp_info, | |
10740 | &tp->pdev->dev); | |
10741 | if (IS_ERR(tp->ptp_clock)) | |
10742 | tp->ptp_clock = NULL; | |
10743 | } | |
10744 | ||
07b0173c | 10745 | return err; |
1da177e4 LT |
10746 | } |
10747 | ||
1da177e4 LT |
10748 | static int tg3_close(struct net_device *dev) |
10749 | { | |
10750 | struct tg3 *tp = netdev_priv(dev); | |
10751 | ||
be947307 MC |
10752 | tg3_ptp_fini(tp); |
10753 | ||
65138594 | 10754 | tg3_stop(tp); |
1da177e4 | 10755 | |
92feeabf MC |
10756 | /* Clear stats across close / open calls */ |
10757 | memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev)); | |
10758 | memset(&tp->estats_prev, 0, sizeof(tp->estats_prev)); | |
1da177e4 | 10759 | |
c866b7ea | 10760 | tg3_power_down(tp); |
bc1c7567 | 10761 | |
f4a46d1f | 10762 | tg3_carrier_off(tp); |
bc1c7567 | 10763 | |
1da177e4 LT |
10764 | return 0; |
10765 | } | |
10766 | ||
511d2224 | 10767 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
10768 | { |
10769 | return ((u64)val->high << 32) | ((u64)val->low); | |
10770 | } | |
10771 | ||
65ec698d | 10772 | static u64 tg3_calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
10773 | { |
10774 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
10775 | ||
f07e9af3 | 10776 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
10777 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
10778 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
10779 | u32 val; |
10780 | ||
569a5df8 MC |
10781 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
10782 | tg3_writephy(tp, MII_TG3_TEST1, | |
10783 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 10784 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
10785 | } else |
10786 | val = 0; | |
1da177e4 LT |
10787 | |
10788 | tp->phy_crc_errors += val; | |
10789 | ||
10790 | return tp->phy_crc_errors; | |
10791 | } | |
10792 | ||
10793 | return get_stat64(&hw_stats->rx_fcs_errors); | |
10794 | } | |
10795 | ||
10796 | #define ESTAT_ADD(member) \ | |
10797 | estats->member = old_estats->member + \ | |
511d2224 | 10798 | get_stat64(&hw_stats->member) |
1da177e4 | 10799 | |
65ec698d | 10800 | static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats) |
1da177e4 | 10801 | { |
1da177e4 LT |
10802 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; |
10803 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
10804 | ||
1da177e4 LT |
10805 | ESTAT_ADD(rx_octets); |
10806 | ESTAT_ADD(rx_fragments); | |
10807 | ESTAT_ADD(rx_ucast_packets); | |
10808 | ESTAT_ADD(rx_mcast_packets); | |
10809 | ESTAT_ADD(rx_bcast_packets); | |
10810 | ESTAT_ADD(rx_fcs_errors); | |
10811 | ESTAT_ADD(rx_align_errors); | |
10812 | ESTAT_ADD(rx_xon_pause_rcvd); | |
10813 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
10814 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
10815 | ESTAT_ADD(rx_xoff_entered); | |
10816 | ESTAT_ADD(rx_frame_too_long_errors); | |
10817 | ESTAT_ADD(rx_jabbers); | |
10818 | ESTAT_ADD(rx_undersize_packets); | |
10819 | ESTAT_ADD(rx_in_length_errors); | |
10820 | ESTAT_ADD(rx_out_length_errors); | |
10821 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
10822 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
10823 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
10824 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
10825 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
10826 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
10827 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
10828 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
10829 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
10830 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
10831 | ||
10832 | ESTAT_ADD(tx_octets); | |
10833 | ESTAT_ADD(tx_collisions); | |
10834 | ESTAT_ADD(tx_xon_sent); | |
10835 | ESTAT_ADD(tx_xoff_sent); | |
10836 | ESTAT_ADD(tx_flow_control); | |
10837 | ESTAT_ADD(tx_mac_errors); | |
10838 | ESTAT_ADD(tx_single_collisions); | |
10839 | ESTAT_ADD(tx_mult_collisions); | |
10840 | ESTAT_ADD(tx_deferred); | |
10841 | ESTAT_ADD(tx_excessive_collisions); | |
10842 | ESTAT_ADD(tx_late_collisions); | |
10843 | ESTAT_ADD(tx_collide_2times); | |
10844 | ESTAT_ADD(tx_collide_3times); | |
10845 | ESTAT_ADD(tx_collide_4times); | |
10846 | ESTAT_ADD(tx_collide_5times); | |
10847 | ESTAT_ADD(tx_collide_6times); | |
10848 | ESTAT_ADD(tx_collide_7times); | |
10849 | ESTAT_ADD(tx_collide_8times); | |
10850 | ESTAT_ADD(tx_collide_9times); | |
10851 | ESTAT_ADD(tx_collide_10times); | |
10852 | ESTAT_ADD(tx_collide_11times); | |
10853 | ESTAT_ADD(tx_collide_12times); | |
10854 | ESTAT_ADD(tx_collide_13times); | |
10855 | ESTAT_ADD(tx_collide_14times); | |
10856 | ESTAT_ADD(tx_collide_15times); | |
10857 | ESTAT_ADD(tx_ucast_packets); | |
10858 | ESTAT_ADD(tx_mcast_packets); | |
10859 | ESTAT_ADD(tx_bcast_packets); | |
10860 | ESTAT_ADD(tx_carrier_sense_errors); | |
10861 | ESTAT_ADD(tx_discards); | |
10862 | ESTAT_ADD(tx_errors); | |
10863 | ||
10864 | ESTAT_ADD(dma_writeq_full); | |
10865 | ESTAT_ADD(dma_write_prioq_full); | |
10866 | ESTAT_ADD(rxbds_empty); | |
10867 | ESTAT_ADD(rx_discards); | |
10868 | ESTAT_ADD(rx_errors); | |
10869 | ESTAT_ADD(rx_threshold_hit); | |
10870 | ||
10871 | ESTAT_ADD(dma_readq_full); | |
10872 | ESTAT_ADD(dma_read_prioq_full); | |
10873 | ESTAT_ADD(tx_comp_queue_full); | |
10874 | ||
10875 | ESTAT_ADD(ring_set_send_prod_index); | |
10876 | ESTAT_ADD(ring_status_update); | |
10877 | ESTAT_ADD(nic_irqs); | |
10878 | ESTAT_ADD(nic_avoided_irqs); | |
10879 | ESTAT_ADD(nic_tx_threshold_hit); | |
10880 | ||
4452d099 | 10881 | ESTAT_ADD(mbuf_lwm_thresh_hit); |
1da177e4 LT |
10882 | } |
10883 | ||
65ec698d | 10884 | static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats) |
1da177e4 | 10885 | { |
511d2224 | 10886 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
10887 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
10888 | ||
1da177e4 LT |
10889 | stats->rx_packets = old_stats->rx_packets + |
10890 | get_stat64(&hw_stats->rx_ucast_packets) + | |
10891 | get_stat64(&hw_stats->rx_mcast_packets) + | |
10892 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 10893 | |
1da177e4 LT |
10894 | stats->tx_packets = old_stats->tx_packets + |
10895 | get_stat64(&hw_stats->tx_ucast_packets) + | |
10896 | get_stat64(&hw_stats->tx_mcast_packets) + | |
10897 | get_stat64(&hw_stats->tx_bcast_packets); | |
10898 | ||
10899 | stats->rx_bytes = old_stats->rx_bytes + | |
10900 | get_stat64(&hw_stats->rx_octets); | |
10901 | stats->tx_bytes = old_stats->tx_bytes + | |
10902 | get_stat64(&hw_stats->tx_octets); | |
10903 | ||
10904 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 10905 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
10906 | stats->tx_errors = old_stats->tx_errors + |
10907 | get_stat64(&hw_stats->tx_errors) + | |
10908 | get_stat64(&hw_stats->tx_mac_errors) + | |
10909 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
10910 | get_stat64(&hw_stats->tx_discards); | |
10911 | ||
10912 | stats->multicast = old_stats->multicast + | |
10913 | get_stat64(&hw_stats->rx_mcast_packets); | |
10914 | stats->collisions = old_stats->collisions + | |
10915 | get_stat64(&hw_stats->tx_collisions); | |
10916 | ||
10917 | stats->rx_length_errors = old_stats->rx_length_errors + | |
10918 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
10919 | get_stat64(&hw_stats->rx_undersize_packets); | |
10920 | ||
10921 | stats->rx_over_errors = old_stats->rx_over_errors + | |
10922 | get_stat64(&hw_stats->rxbds_empty); | |
10923 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
10924 | get_stat64(&hw_stats->rx_align_errors); | |
10925 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
10926 | get_stat64(&hw_stats->tx_discards); | |
10927 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
10928 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
10929 | ||
10930 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
65ec698d | 10931 | tg3_calc_crc_errors(tp); |
1da177e4 | 10932 | |
4f63b877 JL |
10933 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
10934 | get_stat64(&hw_stats->rx_discards); | |
10935 | ||
b0057c51 | 10936 | stats->rx_dropped = tp->rx_dropped; |
48855432 | 10937 | stats->tx_dropped = tp->tx_dropped; |
1da177e4 LT |
10938 | } |
10939 | ||
1da177e4 LT |
10940 | static int tg3_get_regs_len(struct net_device *dev) |
10941 | { | |
97bd8e49 | 10942 | return TG3_REG_BLK_SIZE; |
1da177e4 LT |
10943 | } |
10944 | ||
10945 | static void tg3_get_regs(struct net_device *dev, | |
10946 | struct ethtool_regs *regs, void *_p) | |
10947 | { | |
1da177e4 | 10948 | struct tg3 *tp = netdev_priv(dev); |
1da177e4 LT |
10949 | |
10950 | regs->version = 0; | |
10951 | ||
97bd8e49 | 10952 | memset(_p, 0, TG3_REG_BLK_SIZE); |
1da177e4 | 10953 | |
80096068 | 10954 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10955 | return; |
10956 | ||
f47c11ee | 10957 | tg3_full_lock(tp, 0); |
1da177e4 | 10958 | |
97bd8e49 | 10959 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
1da177e4 | 10960 | |
f47c11ee | 10961 | tg3_full_unlock(tp); |
1da177e4 LT |
10962 | } |
10963 | ||
10964 | static int tg3_get_eeprom_len(struct net_device *dev) | |
10965 | { | |
10966 | struct tg3 *tp = netdev_priv(dev); | |
10967 | ||
10968 | return tp->nvram_size; | |
10969 | } | |
10970 | ||
1da177e4 LT |
10971 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
10972 | { | |
10973 | struct tg3 *tp = netdev_priv(dev); | |
10974 | int ret; | |
10975 | u8 *pd; | |
b9fc7dc5 | 10976 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 10977 | __be32 val; |
1da177e4 | 10978 | |
63c3a66f | 10979 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10980 | return -EINVAL; |
10981 | ||
80096068 | 10982 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10983 | return -EAGAIN; |
10984 | ||
1da177e4 LT |
10985 | offset = eeprom->offset; |
10986 | len = eeprom->len; | |
10987 | eeprom->len = 0; | |
10988 | ||
10989 | eeprom->magic = TG3_EEPROM_MAGIC; | |
10990 | ||
10991 | if (offset & 3) { | |
10992 | /* adjustments to start on required 4 byte boundary */ | |
10993 | b_offset = offset & 3; | |
10994 | b_count = 4 - b_offset; | |
10995 | if (b_count > len) { | |
10996 | /* i.e. offset=1 len=2 */ | |
10997 | b_count = len; | |
10998 | } | |
a9dc529d | 10999 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
11000 | if (ret) |
11001 | return ret; | |
be98da6a | 11002 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
11003 | len -= b_count; |
11004 | offset += b_count; | |
c6cdf436 | 11005 | eeprom->len += b_count; |
1da177e4 LT |
11006 | } |
11007 | ||
25985edc | 11008 | /* read bytes up to the last 4 byte boundary */ |
1da177e4 LT |
11009 | pd = &data[eeprom->len]; |
11010 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 11011 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
11012 | if (ret) { |
11013 | eeprom->len += i; | |
11014 | return ret; | |
11015 | } | |
1da177e4 LT |
11016 | memcpy(pd + i, &val, 4); |
11017 | } | |
11018 | eeprom->len += i; | |
11019 | ||
11020 | if (len & 3) { | |
11021 | /* read last bytes not ending on 4 byte boundary */ | |
11022 | pd = &data[eeprom->len]; | |
11023 | b_count = len & 3; | |
11024 | b_offset = offset + len - b_count; | |
a9dc529d | 11025 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
11026 | if (ret) |
11027 | return ret; | |
b9fc7dc5 | 11028 | memcpy(pd, &val, b_count); |
1da177e4 LT |
11029 | eeprom->len += b_count; |
11030 | } | |
11031 | return 0; | |
11032 | } | |
11033 | ||
1da177e4 LT |
11034 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
11035 | { | |
11036 | struct tg3 *tp = netdev_priv(dev); | |
11037 | int ret; | |
b9fc7dc5 | 11038 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 11039 | u8 *buf; |
a9dc529d | 11040 | __be32 start, end; |
1da177e4 | 11041 | |
80096068 | 11042 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
11043 | return -EAGAIN; |
11044 | ||
63c3a66f | 11045 | if (tg3_flag(tp, NO_NVRAM) || |
df259d8c | 11046 | eeprom->magic != TG3_EEPROM_MAGIC) |
1da177e4 LT |
11047 | return -EINVAL; |
11048 | ||
11049 | offset = eeprom->offset; | |
11050 | len = eeprom->len; | |
11051 | ||
11052 | if ((b_offset = (offset & 3))) { | |
11053 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 11054 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
11055 | if (ret) |
11056 | return ret; | |
1da177e4 LT |
11057 | len += b_offset; |
11058 | offset &= ~3; | |
1c8594b4 MC |
11059 | if (len < 4) |
11060 | len = 4; | |
1da177e4 LT |
11061 | } |
11062 | ||
11063 | odd_len = 0; | |
1c8594b4 | 11064 | if (len & 3) { |
1da177e4 LT |
11065 | /* adjustments to end on required 4 byte boundary */ |
11066 | odd_len = 1; | |
11067 | len = (len + 3) & ~3; | |
a9dc529d | 11068 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
11069 | if (ret) |
11070 | return ret; | |
1da177e4 LT |
11071 | } |
11072 | ||
11073 | buf = data; | |
11074 | if (b_offset || odd_len) { | |
11075 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 11076 | if (!buf) |
1da177e4 LT |
11077 | return -ENOMEM; |
11078 | if (b_offset) | |
11079 | memcpy(buf, &start, 4); | |
11080 | if (odd_len) | |
11081 | memcpy(buf+len-4, &end, 4); | |
11082 | memcpy(buf + b_offset, data, eeprom->len); | |
11083 | } | |
11084 | ||
11085 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
11086 | ||
11087 | if (buf != data) | |
11088 | kfree(buf); | |
11089 | ||
11090 | return ret; | |
11091 | } | |
11092 | ||
11093 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
11094 | { | |
b02fd9e3 MC |
11095 | struct tg3 *tp = netdev_priv(dev); |
11096 | ||
63c3a66f | 11097 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 11098 | struct phy_device *phydev; |
f07e9af3 | 11099 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11100 | return -EAGAIN; |
3f0e3ad7 MC |
11101 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
11102 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 11103 | } |
6aa20a22 | 11104 | |
1da177e4 LT |
11105 | cmd->supported = (SUPPORTED_Autoneg); |
11106 | ||
f07e9af3 | 11107 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
11108 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
11109 | SUPPORTED_1000baseT_Full); | |
11110 | ||
f07e9af3 | 11111 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
11112 | cmd->supported |= (SUPPORTED_100baseT_Half | |
11113 | SUPPORTED_100baseT_Full | | |
11114 | SUPPORTED_10baseT_Half | | |
11115 | SUPPORTED_10baseT_Full | | |
3bebab59 | 11116 | SUPPORTED_TP); |
ef348144 KK |
11117 | cmd->port = PORT_TP; |
11118 | } else { | |
1da177e4 | 11119 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
11120 | cmd->port = PORT_FIBRE; |
11121 | } | |
6aa20a22 | 11122 | |
1da177e4 | 11123 | cmd->advertising = tp->link_config.advertising; |
5bb09778 MC |
11124 | if (tg3_flag(tp, PAUSE_AUTONEG)) { |
11125 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) { | |
11126 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
11127 | cmd->advertising |= ADVERTISED_Pause; | |
11128 | } else { | |
11129 | cmd->advertising |= ADVERTISED_Pause | | |
11130 | ADVERTISED_Asym_Pause; | |
11131 | } | |
11132 | } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
11133 | cmd->advertising |= ADVERTISED_Asym_Pause; | |
11134 | } | |
11135 | } | |
f4a46d1f | 11136 | if (netif_running(dev) && tp->link_up) { |
70739497 | 11137 | ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); |
1da177e4 | 11138 | cmd->duplex = tp->link_config.active_duplex; |
859edb26 | 11139 | cmd->lp_advertising = tp->link_config.rmt_adv; |
e348c5e7 MC |
11140 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
11141 | if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) | |
11142 | cmd->eth_tp_mdix = ETH_TP_MDI_X; | |
11143 | else | |
11144 | cmd->eth_tp_mdix = ETH_TP_MDI; | |
11145 | } | |
64c22182 | 11146 | } else { |
e740522e MC |
11147 | ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); |
11148 | cmd->duplex = DUPLEX_UNKNOWN; | |
e348c5e7 | 11149 | cmd->eth_tp_mdix = ETH_TP_MDI_INVALID; |
1da177e4 | 11150 | } |
882e9793 | 11151 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 11152 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
11153 | cmd->autoneg = tp->link_config.autoneg; |
11154 | cmd->maxtxpkt = 0; | |
11155 | cmd->maxrxpkt = 0; | |
11156 | return 0; | |
11157 | } | |
6aa20a22 | 11158 | |
1da177e4 LT |
11159 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
11160 | { | |
11161 | struct tg3 *tp = netdev_priv(dev); | |
25db0338 | 11162 | u32 speed = ethtool_cmd_speed(cmd); |
6aa20a22 | 11163 | |
63c3a66f | 11164 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 11165 | struct phy_device *phydev; |
f07e9af3 | 11166 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11167 | return -EAGAIN; |
3f0e3ad7 MC |
11168 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
11169 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
11170 | } |
11171 | ||
7e5856bd MC |
11172 | if (cmd->autoneg != AUTONEG_ENABLE && |
11173 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 11174 | return -EINVAL; |
7e5856bd MC |
11175 | |
11176 | if (cmd->autoneg == AUTONEG_DISABLE && | |
11177 | cmd->duplex != DUPLEX_FULL && | |
11178 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 11179 | return -EINVAL; |
1da177e4 | 11180 | |
7e5856bd MC |
11181 | if (cmd->autoneg == AUTONEG_ENABLE) { |
11182 | u32 mask = ADVERTISED_Autoneg | | |
11183 | ADVERTISED_Pause | | |
11184 | ADVERTISED_Asym_Pause; | |
11185 | ||
f07e9af3 | 11186 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
11187 | mask |= ADVERTISED_1000baseT_Half | |
11188 | ADVERTISED_1000baseT_Full; | |
11189 | ||
f07e9af3 | 11190 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
11191 | mask |= ADVERTISED_100baseT_Half | |
11192 | ADVERTISED_100baseT_Full | | |
11193 | ADVERTISED_10baseT_Half | | |
11194 | ADVERTISED_10baseT_Full | | |
11195 | ADVERTISED_TP; | |
11196 | else | |
11197 | mask |= ADVERTISED_FIBRE; | |
11198 | ||
11199 | if (cmd->advertising & ~mask) | |
11200 | return -EINVAL; | |
11201 | ||
11202 | mask &= (ADVERTISED_1000baseT_Half | | |
11203 | ADVERTISED_1000baseT_Full | | |
11204 | ADVERTISED_100baseT_Half | | |
11205 | ADVERTISED_100baseT_Full | | |
11206 | ADVERTISED_10baseT_Half | | |
11207 | ADVERTISED_10baseT_Full); | |
11208 | ||
11209 | cmd->advertising &= mask; | |
11210 | } else { | |
f07e9af3 | 11211 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
25db0338 | 11212 | if (speed != SPEED_1000) |
7e5856bd MC |
11213 | return -EINVAL; |
11214 | ||
11215 | if (cmd->duplex != DUPLEX_FULL) | |
11216 | return -EINVAL; | |
11217 | } else { | |
25db0338 DD |
11218 | if (speed != SPEED_100 && |
11219 | speed != SPEED_10) | |
7e5856bd MC |
11220 | return -EINVAL; |
11221 | } | |
11222 | } | |
11223 | ||
f47c11ee | 11224 | tg3_full_lock(tp, 0); |
1da177e4 LT |
11225 | |
11226 | tp->link_config.autoneg = cmd->autoneg; | |
11227 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
11228 | tp->link_config.advertising = (cmd->advertising | |
11229 | ADVERTISED_Autoneg); | |
e740522e MC |
11230 | tp->link_config.speed = SPEED_UNKNOWN; |
11231 | tp->link_config.duplex = DUPLEX_UNKNOWN; | |
1da177e4 LT |
11232 | } else { |
11233 | tp->link_config.advertising = 0; | |
25db0338 | 11234 | tp->link_config.speed = speed; |
1da177e4 | 11235 | tp->link_config.duplex = cmd->duplex; |
b02fd9e3 | 11236 | } |
6aa20a22 | 11237 | |
1da177e4 LT |
11238 | if (netif_running(dev)) |
11239 | tg3_setup_phy(tp, 1); | |
11240 | ||
f47c11ee | 11241 | tg3_full_unlock(tp); |
6aa20a22 | 11242 | |
1da177e4 LT |
11243 | return 0; |
11244 | } | |
6aa20a22 | 11245 | |
1da177e4 LT |
11246 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
11247 | { | |
11248 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 11249 | |
68aad78c RJ |
11250 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
11251 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); | |
11252 | strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); | |
11253 | strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); | |
1da177e4 | 11254 | } |
6aa20a22 | 11255 | |
1da177e4 LT |
11256 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
11257 | { | |
11258 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 11259 | |
63c3a66f | 11260 | if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) |
a85feb8c GZ |
11261 | wol->supported = WAKE_MAGIC; |
11262 | else | |
11263 | wol->supported = 0; | |
1da177e4 | 11264 | wol->wolopts = 0; |
63c3a66f | 11265 | if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) |
1da177e4 LT |
11266 | wol->wolopts = WAKE_MAGIC; |
11267 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
11268 | } | |
6aa20a22 | 11269 | |
1da177e4 LT |
11270 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
11271 | { | |
11272 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 11273 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 11274 | |
1da177e4 LT |
11275 | if (wol->wolopts & ~WAKE_MAGIC) |
11276 | return -EINVAL; | |
11277 | if ((wol->wolopts & WAKE_MAGIC) && | |
63c3a66f | 11278 | !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 11279 | return -EINVAL; |
6aa20a22 | 11280 | |
f2dc0d18 RW |
11281 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
11282 | ||
f47c11ee | 11283 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 11284 | if (device_may_wakeup(dp)) |
63c3a66f | 11285 | tg3_flag_set(tp, WOL_ENABLE); |
f2dc0d18 | 11286 | else |
63c3a66f | 11287 | tg3_flag_clear(tp, WOL_ENABLE); |
f47c11ee | 11288 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 11289 | |
1da177e4 LT |
11290 | return 0; |
11291 | } | |
6aa20a22 | 11292 | |
1da177e4 LT |
11293 | static u32 tg3_get_msglevel(struct net_device *dev) |
11294 | { | |
11295 | struct tg3 *tp = netdev_priv(dev); | |
11296 | return tp->msg_enable; | |
11297 | } | |
6aa20a22 | 11298 | |
1da177e4 LT |
11299 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
11300 | { | |
11301 | struct tg3 *tp = netdev_priv(dev); | |
11302 | tp->msg_enable = value; | |
11303 | } | |
6aa20a22 | 11304 | |
1da177e4 LT |
11305 | static int tg3_nway_reset(struct net_device *dev) |
11306 | { | |
11307 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 11308 | int r; |
6aa20a22 | 11309 | |
1da177e4 LT |
11310 | if (!netif_running(dev)) |
11311 | return -EAGAIN; | |
11312 | ||
f07e9af3 | 11313 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
11314 | return -EINVAL; |
11315 | ||
63c3a66f | 11316 | if (tg3_flag(tp, USE_PHYLIB)) { |
f07e9af3 | 11317 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11318 | return -EAGAIN; |
3f0e3ad7 | 11319 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
11320 | } else { |
11321 | u32 bmcr; | |
11322 | ||
11323 | spin_lock_bh(&tp->lock); | |
11324 | r = -EINVAL; | |
11325 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
11326 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
11327 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 11328 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
11329 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
11330 | BMCR_ANENABLE); | |
11331 | r = 0; | |
11332 | } | |
11333 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 11334 | } |
6aa20a22 | 11335 | |
1da177e4 LT |
11336 | return r; |
11337 | } | |
6aa20a22 | 11338 | |
1da177e4 LT |
11339 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
11340 | { | |
11341 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 11342 | |
2c49a44d | 11343 | ering->rx_max_pending = tp->rx_std_ring_mask; |
63c3a66f | 11344 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
2c49a44d | 11345 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
11346 | else |
11347 | ering->rx_jumbo_max_pending = 0; | |
11348 | ||
11349 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
11350 | |
11351 | ering->rx_pending = tp->rx_pending; | |
63c3a66f | 11352 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
4f81c32b MC |
11353 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; |
11354 | else | |
11355 | ering->rx_jumbo_pending = 0; | |
11356 | ||
f3f3f27e | 11357 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 11358 | } |
6aa20a22 | 11359 | |
1da177e4 LT |
11360 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
11361 | { | |
11362 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 11363 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 11364 | |
2c49a44d MC |
11365 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
11366 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
11367 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
11368 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
63c3a66f | 11369 | (tg3_flag(tp, TSO_BUG) && |
bc3a9254 | 11370 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 11371 | return -EINVAL; |
6aa20a22 | 11372 | |
bbe832c0 | 11373 | if (netif_running(dev)) { |
b02fd9e3 | 11374 | tg3_phy_stop(tp); |
1da177e4 | 11375 | tg3_netif_stop(tp); |
bbe832c0 MC |
11376 | irq_sync = 1; |
11377 | } | |
1da177e4 | 11378 | |
bbe832c0 | 11379 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 11380 | |
1da177e4 LT |
11381 | tp->rx_pending = ering->rx_pending; |
11382 | ||
63c3a66f | 11383 | if (tg3_flag(tp, MAX_RXPEND_64) && |
1da177e4 LT |
11384 | tp->rx_pending > 63) |
11385 | tp->rx_pending = 63; | |
11386 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 11387 | |
6fd45cb8 | 11388 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 11389 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
11390 | |
11391 | if (netif_running(dev)) { | |
944d980e | 11392 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
11393 | err = tg3_restart_hw(tp, 1); |
11394 | if (!err) | |
11395 | tg3_netif_start(tp); | |
1da177e4 LT |
11396 | } |
11397 | ||
f47c11ee | 11398 | tg3_full_unlock(tp); |
6aa20a22 | 11399 | |
b02fd9e3 MC |
11400 | if (irq_sync && !err) |
11401 | tg3_phy_start(tp); | |
11402 | ||
b9ec6c1b | 11403 | return err; |
1da177e4 | 11404 | } |
6aa20a22 | 11405 | |
1da177e4 LT |
11406 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
11407 | { | |
11408 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 11409 | |
63c3a66f | 11410 | epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); |
8d018621 | 11411 | |
4a2db503 | 11412 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
11413 | epause->rx_pause = 1; |
11414 | else | |
11415 | epause->rx_pause = 0; | |
11416 | ||
4a2db503 | 11417 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
11418 | epause->tx_pause = 1; |
11419 | else | |
11420 | epause->tx_pause = 0; | |
1da177e4 | 11421 | } |
6aa20a22 | 11422 | |
1da177e4 LT |
11423 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
11424 | { | |
11425 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 11426 | int err = 0; |
6aa20a22 | 11427 | |
63c3a66f | 11428 | if (tg3_flag(tp, USE_PHYLIB)) { |
2712168f MC |
11429 | u32 newadv; |
11430 | struct phy_device *phydev; | |
1da177e4 | 11431 | |
2712168f | 11432 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 11433 | |
2712168f MC |
11434 | if (!(phydev->supported & SUPPORTED_Pause) || |
11435 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 11436 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 11437 | return -EINVAL; |
1da177e4 | 11438 | |
2712168f MC |
11439 | tp->link_config.flowctrl = 0; |
11440 | if (epause->rx_pause) { | |
11441 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
11442 | ||
11443 | if (epause->tx_pause) { | |
11444 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
11445 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 11446 | } else |
2712168f MC |
11447 | newadv = ADVERTISED_Pause | |
11448 | ADVERTISED_Asym_Pause; | |
11449 | } else if (epause->tx_pause) { | |
11450 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
11451 | newadv = ADVERTISED_Asym_Pause; | |
11452 | } else | |
11453 | newadv = 0; | |
11454 | ||
11455 | if (epause->autoneg) | |
63c3a66f | 11456 | tg3_flag_set(tp, PAUSE_AUTONEG); |
2712168f | 11457 | else |
63c3a66f | 11458 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
2712168f | 11459 | |
f07e9af3 | 11460 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
11461 | u32 oldadv = phydev->advertising & |
11462 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
11463 | if (oldadv != newadv) { | |
11464 | phydev->advertising &= | |
11465 | ~(ADVERTISED_Pause | | |
11466 | ADVERTISED_Asym_Pause); | |
11467 | phydev->advertising |= newadv; | |
11468 | if (phydev->autoneg) { | |
11469 | /* | |
11470 | * Always renegotiate the link to | |
11471 | * inform our link partner of our | |
11472 | * flow control settings, even if the | |
11473 | * flow control is forced. Let | |
11474 | * tg3_adjust_link() do the final | |
11475 | * flow control setup. | |
11476 | */ | |
11477 | return phy_start_aneg(phydev); | |
b02fd9e3 | 11478 | } |
b02fd9e3 | 11479 | } |
b02fd9e3 | 11480 | |
2712168f | 11481 | if (!epause->autoneg) |
b02fd9e3 | 11482 | tg3_setup_flow_control(tp, 0, 0); |
2712168f | 11483 | } else { |
c6700ce2 | 11484 | tp->link_config.advertising &= |
2712168f MC |
11485 | ~(ADVERTISED_Pause | |
11486 | ADVERTISED_Asym_Pause); | |
c6700ce2 | 11487 | tp->link_config.advertising |= newadv; |
b02fd9e3 MC |
11488 | } |
11489 | } else { | |
11490 | int irq_sync = 0; | |
11491 | ||
11492 | if (netif_running(dev)) { | |
11493 | tg3_netif_stop(tp); | |
11494 | irq_sync = 1; | |
11495 | } | |
11496 | ||
11497 | tg3_full_lock(tp, irq_sync); | |
11498 | ||
11499 | if (epause->autoneg) | |
63c3a66f | 11500 | tg3_flag_set(tp, PAUSE_AUTONEG); |
b02fd9e3 | 11501 | else |
63c3a66f | 11502 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
b02fd9e3 | 11503 | if (epause->rx_pause) |
e18ce346 | 11504 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 11505 | else |
e18ce346 | 11506 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 11507 | if (epause->tx_pause) |
e18ce346 | 11508 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 11509 | else |
e18ce346 | 11510 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
11511 | |
11512 | if (netif_running(dev)) { | |
11513 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
11514 | err = tg3_restart_hw(tp, 1); | |
11515 | if (!err) | |
11516 | tg3_netif_start(tp); | |
11517 | } | |
11518 | ||
11519 | tg3_full_unlock(tp); | |
11520 | } | |
6aa20a22 | 11521 | |
b9ec6c1b | 11522 | return err; |
1da177e4 | 11523 | } |
6aa20a22 | 11524 | |
de6f31eb | 11525 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 11526 | { |
b9f2c044 JG |
11527 | switch (sset) { |
11528 | case ETH_SS_TEST: | |
11529 | return TG3_NUM_TEST; | |
11530 | case ETH_SS_STATS: | |
11531 | return TG3_NUM_STATS; | |
11532 | default: | |
11533 | return -EOPNOTSUPP; | |
11534 | } | |
4cafd3f5 MC |
11535 | } |
11536 | ||
90415477 MC |
11537 | static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, |
11538 | u32 *rules __always_unused) | |
11539 | { | |
11540 | struct tg3 *tp = netdev_priv(dev); | |
11541 | ||
11542 | if (!tg3_flag(tp, SUPPORT_MSIX)) | |
11543 | return -EOPNOTSUPP; | |
11544 | ||
11545 | switch (info->cmd) { | |
11546 | case ETHTOOL_GRXRINGS: | |
11547 | if (netif_running(tp->dev)) | |
9102426a | 11548 | info->data = tp->rxq_cnt; |
90415477 MC |
11549 | else { |
11550 | info->data = num_online_cpus(); | |
9102426a MC |
11551 | if (info->data > TG3_RSS_MAX_NUM_QS) |
11552 | info->data = TG3_RSS_MAX_NUM_QS; | |
90415477 MC |
11553 | } |
11554 | ||
11555 | /* The first interrupt vector only | |
11556 | * handles link interrupts. | |
11557 | */ | |
11558 | info->data -= 1; | |
11559 | return 0; | |
11560 | ||
11561 | default: | |
11562 | return -EOPNOTSUPP; | |
11563 | } | |
11564 | } | |
11565 | ||
11566 | static u32 tg3_get_rxfh_indir_size(struct net_device *dev) | |
11567 | { | |
11568 | u32 size = 0; | |
11569 | struct tg3 *tp = netdev_priv(dev); | |
11570 | ||
11571 | if (tg3_flag(tp, SUPPORT_MSIX)) | |
11572 | size = TG3_RSS_INDIR_TBL_SIZE; | |
11573 | ||
11574 | return size; | |
11575 | } | |
11576 | ||
11577 | static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir) | |
11578 | { | |
11579 | struct tg3 *tp = netdev_priv(dev); | |
11580 | int i; | |
11581 | ||
11582 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) | |
11583 | indir[i] = tp->rss_ind_tbl[i]; | |
11584 | ||
11585 | return 0; | |
11586 | } | |
11587 | ||
11588 | static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir) | |
11589 | { | |
11590 | struct tg3 *tp = netdev_priv(dev); | |
11591 | size_t i; | |
11592 | ||
11593 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) | |
11594 | tp->rss_ind_tbl[i] = indir[i]; | |
11595 | ||
11596 | if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) | |
11597 | return 0; | |
11598 | ||
11599 | /* It is legal to write the indirection | |
11600 | * table while the device is running. | |
11601 | */ | |
11602 | tg3_full_lock(tp, 0); | |
11603 | tg3_rss_write_indir_tbl(tp); | |
11604 | tg3_full_unlock(tp); | |
11605 | ||
11606 | return 0; | |
11607 | } | |
11608 | ||
0968169c MC |
11609 | static void tg3_get_channels(struct net_device *dev, |
11610 | struct ethtool_channels *channel) | |
11611 | { | |
11612 | struct tg3 *tp = netdev_priv(dev); | |
11613 | u32 deflt_qs = netif_get_num_default_rss_queues(); | |
11614 | ||
11615 | channel->max_rx = tp->rxq_max; | |
11616 | channel->max_tx = tp->txq_max; | |
11617 | ||
11618 | if (netif_running(dev)) { | |
11619 | channel->rx_count = tp->rxq_cnt; | |
11620 | channel->tx_count = tp->txq_cnt; | |
11621 | } else { | |
11622 | if (tp->rxq_req) | |
11623 | channel->rx_count = tp->rxq_req; | |
11624 | else | |
11625 | channel->rx_count = min(deflt_qs, tp->rxq_max); | |
11626 | ||
11627 | if (tp->txq_req) | |
11628 | channel->tx_count = tp->txq_req; | |
11629 | else | |
11630 | channel->tx_count = min(deflt_qs, tp->txq_max); | |
11631 | } | |
11632 | } | |
11633 | ||
11634 | static int tg3_set_channels(struct net_device *dev, | |
11635 | struct ethtool_channels *channel) | |
11636 | { | |
11637 | struct tg3 *tp = netdev_priv(dev); | |
11638 | ||
11639 | if (!tg3_flag(tp, SUPPORT_MSIX)) | |
11640 | return -EOPNOTSUPP; | |
11641 | ||
11642 | if (channel->rx_count > tp->rxq_max || | |
11643 | channel->tx_count > tp->txq_max) | |
11644 | return -EINVAL; | |
11645 | ||
11646 | tp->rxq_req = channel->rx_count; | |
11647 | tp->txq_req = channel->tx_count; | |
11648 | ||
11649 | if (!netif_running(dev)) | |
11650 | return 0; | |
11651 | ||
11652 | tg3_stop(tp); | |
11653 | ||
f4a46d1f | 11654 | tg3_carrier_off(tp); |
0968169c | 11655 | |
be947307 | 11656 | tg3_start(tp, true, false, false); |
0968169c MC |
11657 | |
11658 | return 0; | |
11659 | } | |
11660 | ||
de6f31eb | 11661 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
11662 | { |
11663 | switch (stringset) { | |
11664 | case ETH_SS_STATS: | |
11665 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
11666 | break; | |
4cafd3f5 MC |
11667 | case ETH_SS_TEST: |
11668 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
11669 | break; | |
1da177e4 LT |
11670 | default: |
11671 | WARN_ON(1); /* we need a WARN() */ | |
11672 | break; | |
11673 | } | |
11674 | } | |
11675 | ||
81b8709c | 11676 | static int tg3_set_phys_id(struct net_device *dev, |
11677 | enum ethtool_phys_id_state state) | |
4009a93d MC |
11678 | { |
11679 | struct tg3 *tp = netdev_priv(dev); | |
4009a93d MC |
11680 | |
11681 | if (!netif_running(tp->dev)) | |
11682 | return -EAGAIN; | |
11683 | ||
81b8709c | 11684 | switch (state) { |
11685 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 11686 | return 1; /* cycle on/off once per second */ |
4009a93d | 11687 | |
81b8709c | 11688 | case ETHTOOL_ID_ON: |
11689 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
11690 | LED_CTRL_1000MBPS_ON | | |
11691 | LED_CTRL_100MBPS_ON | | |
11692 | LED_CTRL_10MBPS_ON | | |
11693 | LED_CTRL_TRAFFIC_OVERRIDE | | |
11694 | LED_CTRL_TRAFFIC_BLINK | | |
11695 | LED_CTRL_TRAFFIC_LED); | |
11696 | break; | |
6aa20a22 | 11697 | |
81b8709c | 11698 | case ETHTOOL_ID_OFF: |
11699 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
11700 | LED_CTRL_TRAFFIC_OVERRIDE); | |
11701 | break; | |
4009a93d | 11702 | |
81b8709c | 11703 | case ETHTOOL_ID_INACTIVE: |
11704 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
11705 | break; | |
4009a93d | 11706 | } |
81b8709c | 11707 | |
4009a93d MC |
11708 | return 0; |
11709 | } | |
11710 | ||
de6f31eb | 11711 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
11712 | struct ethtool_stats *estats, u64 *tmp_stats) |
11713 | { | |
11714 | struct tg3 *tp = netdev_priv(dev); | |
0e6c9da3 | 11715 | |
b546e46f MC |
11716 | if (tp->hw_stats) |
11717 | tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); | |
11718 | else | |
11719 | memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats)); | |
1da177e4 LT |
11720 | } |
11721 | ||
535a490e | 11722 | static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen) |
c3e94500 MC |
11723 | { |
11724 | int i; | |
11725 | __be32 *buf; | |
11726 | u32 offset = 0, len = 0; | |
11727 | u32 magic, val; | |
11728 | ||
63c3a66f | 11729 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) |
c3e94500 MC |
11730 | return NULL; |
11731 | ||
11732 | if (magic == TG3_EEPROM_MAGIC) { | |
11733 | for (offset = TG3_NVM_DIR_START; | |
11734 | offset < TG3_NVM_DIR_END; | |
11735 | offset += TG3_NVM_DIRENT_SIZE) { | |
11736 | if (tg3_nvram_read(tp, offset, &val)) | |
11737 | return NULL; | |
11738 | ||
11739 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
11740 | TG3_NVM_DIRTYPE_EXTVPD) | |
11741 | break; | |
11742 | } | |
11743 | ||
11744 | if (offset != TG3_NVM_DIR_END) { | |
11745 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
11746 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
11747 | return NULL; | |
11748 | ||
11749 | offset = tg3_nvram_logical_addr(tp, offset); | |
11750 | } | |
11751 | } | |
11752 | ||
11753 | if (!offset || !len) { | |
11754 | offset = TG3_NVM_VPD_OFF; | |
11755 | len = TG3_NVM_VPD_LEN; | |
11756 | } | |
11757 | ||
11758 | buf = kmalloc(len, GFP_KERNEL); | |
11759 | if (buf == NULL) | |
11760 | return NULL; | |
11761 | ||
11762 | if (magic == TG3_EEPROM_MAGIC) { | |
11763 | for (i = 0; i < len; i += 4) { | |
11764 | /* The data is in little-endian format in NVRAM. | |
11765 | * Use the big-endian read routines to preserve | |
11766 | * the byte order as it exists in NVRAM. | |
11767 | */ | |
11768 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
11769 | goto error; | |
11770 | } | |
11771 | } else { | |
11772 | u8 *ptr; | |
11773 | ssize_t cnt; | |
11774 | unsigned int pos = 0; | |
11775 | ||
11776 | ptr = (u8 *)&buf[0]; | |
11777 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
11778 | cnt = pci_read_vpd(tp->pdev, pos, | |
11779 | len - pos, ptr); | |
11780 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
11781 | cnt = 0; | |
11782 | else if (cnt < 0) | |
11783 | goto error; | |
11784 | } | |
11785 | if (pos != len) | |
11786 | goto error; | |
11787 | } | |
11788 | ||
535a490e MC |
11789 | *vpdlen = len; |
11790 | ||
c3e94500 MC |
11791 | return buf; |
11792 | ||
11793 | error: | |
11794 | kfree(buf); | |
11795 | return NULL; | |
11796 | } | |
11797 | ||
566f86ad | 11798 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
11799 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
11800 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
11801 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
727a6d9f MC |
11802 | #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 |
11803 | #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 | |
bda18faf | 11804 | #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50 |
b16250e3 MC |
11805 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
11806 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
11807 | |
11808 | static int tg3_test_nvram(struct tg3 *tp) | |
11809 | { | |
535a490e | 11810 | u32 csum, magic, len; |
a9dc529d | 11811 | __be32 *buf; |
ab0049b4 | 11812 | int i, j, k, err = 0, size; |
566f86ad | 11813 | |
63c3a66f | 11814 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
11815 | return 0; |
11816 | ||
e4f34110 | 11817 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
11818 | return -EIO; |
11819 | ||
1b27777a MC |
11820 | if (magic == TG3_EEPROM_MAGIC) |
11821 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 11822 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
11823 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
11824 | TG3_EEPROM_SB_FORMAT_1) { | |
11825 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
11826 | case TG3_EEPROM_SB_REVISION_0: | |
11827 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
11828 | break; | |
11829 | case TG3_EEPROM_SB_REVISION_2: | |
11830 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
11831 | break; | |
11832 | case TG3_EEPROM_SB_REVISION_3: | |
11833 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
11834 | break; | |
727a6d9f MC |
11835 | case TG3_EEPROM_SB_REVISION_4: |
11836 | size = NVRAM_SELFBOOT_FORMAT1_4_SIZE; | |
11837 | break; | |
11838 | case TG3_EEPROM_SB_REVISION_5: | |
11839 | size = NVRAM_SELFBOOT_FORMAT1_5_SIZE; | |
11840 | break; | |
11841 | case TG3_EEPROM_SB_REVISION_6: | |
11842 | size = NVRAM_SELFBOOT_FORMAT1_6_SIZE; | |
11843 | break; | |
a5767dec | 11844 | default: |
727a6d9f | 11845 | return -EIO; |
a5767dec MC |
11846 | } |
11847 | } else | |
1b27777a | 11848 | return 0; |
b16250e3 MC |
11849 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
11850 | size = NVRAM_SELFBOOT_HW_SIZE; | |
11851 | else | |
1b27777a MC |
11852 | return -EIO; |
11853 | ||
11854 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
11855 | if (buf == NULL) |
11856 | return -ENOMEM; | |
11857 | ||
1b27777a MC |
11858 | err = -EIO; |
11859 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
11860 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
11861 | if (err) | |
566f86ad | 11862 | break; |
566f86ad | 11863 | } |
1b27777a | 11864 | if (i < size) |
566f86ad MC |
11865 | goto out; |
11866 | ||
1b27777a | 11867 | /* Selfboot format */ |
a9dc529d | 11868 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 11869 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 11870 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
11871 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
11872 | ||
b9fc7dc5 | 11873 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
11874 | TG3_EEPROM_SB_REVISION_2) { |
11875 | /* For rev 2, the csum doesn't include the MBA. */ | |
11876 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
11877 | csum8 += buf8[i]; | |
11878 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
11879 | csum8 += buf8[i]; | |
11880 | } else { | |
11881 | for (i = 0; i < size; i++) | |
11882 | csum8 += buf8[i]; | |
11883 | } | |
1b27777a | 11884 | |
ad96b485 AB |
11885 | if (csum8 == 0) { |
11886 | err = 0; | |
11887 | goto out; | |
11888 | } | |
11889 | ||
11890 | err = -EIO; | |
11891 | goto out; | |
1b27777a | 11892 | } |
566f86ad | 11893 | |
b9fc7dc5 | 11894 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
11895 | TG3_EEPROM_MAGIC_HW) { |
11896 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 11897 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 11898 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
11899 | |
11900 | /* Separate the parity bits and the data bytes. */ | |
11901 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
11902 | if ((i == 0) || (i == 8)) { | |
11903 | int l; | |
11904 | u8 msk; | |
11905 | ||
11906 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
11907 | parity[k++] = buf8[i] & msk; | |
11908 | i++; | |
859a5887 | 11909 | } else if (i == 16) { |
b16250e3 MC |
11910 | int l; |
11911 | u8 msk; | |
11912 | ||
11913 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
11914 | parity[k++] = buf8[i] & msk; | |
11915 | i++; | |
11916 | ||
11917 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
11918 | parity[k++] = buf8[i] & msk; | |
11919 | i++; | |
11920 | } | |
11921 | data[j++] = buf8[i]; | |
11922 | } | |
11923 | ||
11924 | err = -EIO; | |
11925 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
11926 | u8 hw8 = hweight8(data[i]); | |
11927 | ||
11928 | if ((hw8 & 0x1) && parity[i]) | |
11929 | goto out; | |
11930 | else if (!(hw8 & 0x1) && !parity[i]) | |
11931 | goto out; | |
11932 | } | |
11933 | err = 0; | |
11934 | goto out; | |
11935 | } | |
11936 | ||
01c3a392 MC |
11937 | err = -EIO; |
11938 | ||
566f86ad MC |
11939 | /* Bootstrap checksum at offset 0x10 */ |
11940 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 11941 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
11942 | goto out; |
11943 | ||
11944 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
11945 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 11946 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 11947 | goto out; |
566f86ad | 11948 | |
c3e94500 MC |
11949 | kfree(buf); |
11950 | ||
535a490e | 11951 | buf = tg3_vpd_readblock(tp, &len); |
c3e94500 MC |
11952 | if (!buf) |
11953 | return -ENOMEM; | |
d4894f3e | 11954 | |
535a490e | 11955 | i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA); |
d4894f3e MC |
11956 | if (i > 0) { |
11957 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
11958 | if (j < 0) | |
11959 | goto out; | |
11960 | ||
535a490e | 11961 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > len) |
d4894f3e MC |
11962 | goto out; |
11963 | ||
11964 | i += PCI_VPD_LRDT_TAG_SIZE; | |
11965 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
11966 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
11967 | if (j > 0) { | |
11968 | u8 csum8 = 0; | |
11969 | ||
11970 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11971 | ||
11972 | for (i = 0; i <= j; i++) | |
11973 | csum8 += ((u8 *)buf)[i]; | |
11974 | ||
11975 | if (csum8) | |
11976 | goto out; | |
11977 | } | |
11978 | } | |
11979 | ||
566f86ad MC |
11980 | err = 0; |
11981 | ||
11982 | out: | |
11983 | kfree(buf); | |
11984 | return err; | |
11985 | } | |
11986 | ||
ca43007a MC |
11987 | #define TG3_SERDES_TIMEOUT_SEC 2 |
11988 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
11989 | ||
11990 | static int tg3_test_link(struct tg3 *tp) | |
11991 | { | |
11992 | int i, max; | |
11993 | ||
11994 | if (!netif_running(tp->dev)) | |
11995 | return -ENODEV; | |
11996 | ||
f07e9af3 | 11997 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
11998 | max = TG3_SERDES_TIMEOUT_SEC; |
11999 | else | |
12000 | max = TG3_COPPER_TIMEOUT_SEC; | |
12001 | ||
12002 | for (i = 0; i < max; i++) { | |
f4a46d1f | 12003 | if (tp->link_up) |
ca43007a MC |
12004 | return 0; |
12005 | ||
12006 | if (msleep_interruptible(1000)) | |
12007 | break; | |
12008 | } | |
12009 | ||
12010 | return -EIO; | |
12011 | } | |
12012 | ||
a71116d1 | 12013 | /* Only test the commonly used registers */ |
30ca3e37 | 12014 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 12015 | { |
b16250e3 | 12016 | int i, is_5705, is_5750; |
a71116d1 MC |
12017 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
12018 | static struct { | |
12019 | u16 offset; | |
12020 | u16 flags; | |
12021 | #define TG3_FL_5705 0x1 | |
12022 | #define TG3_FL_NOT_5705 0x2 | |
12023 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 12024 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
12025 | u32 read_mask; |
12026 | u32 write_mask; | |
12027 | } reg_tbl[] = { | |
12028 | /* MAC Control Registers */ | |
12029 | { MAC_MODE, TG3_FL_NOT_5705, | |
12030 | 0x00000000, 0x00ef6f8c }, | |
12031 | { MAC_MODE, TG3_FL_5705, | |
12032 | 0x00000000, 0x01ef6b8c }, | |
12033 | { MAC_STATUS, TG3_FL_NOT_5705, | |
12034 | 0x03800107, 0x00000000 }, | |
12035 | { MAC_STATUS, TG3_FL_5705, | |
12036 | 0x03800100, 0x00000000 }, | |
12037 | { MAC_ADDR_0_HIGH, 0x0000, | |
12038 | 0x00000000, 0x0000ffff }, | |
12039 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 12040 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
12041 | { MAC_RX_MTU_SIZE, 0x0000, |
12042 | 0x00000000, 0x0000ffff }, | |
12043 | { MAC_TX_MODE, 0x0000, | |
12044 | 0x00000000, 0x00000070 }, | |
12045 | { MAC_TX_LENGTHS, 0x0000, | |
12046 | 0x00000000, 0x00003fff }, | |
12047 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
12048 | 0x00000000, 0x000007fc }, | |
12049 | { MAC_RX_MODE, TG3_FL_5705, | |
12050 | 0x00000000, 0x000007dc }, | |
12051 | { MAC_HASH_REG_0, 0x0000, | |
12052 | 0x00000000, 0xffffffff }, | |
12053 | { MAC_HASH_REG_1, 0x0000, | |
12054 | 0x00000000, 0xffffffff }, | |
12055 | { MAC_HASH_REG_2, 0x0000, | |
12056 | 0x00000000, 0xffffffff }, | |
12057 | { MAC_HASH_REG_3, 0x0000, | |
12058 | 0x00000000, 0xffffffff }, | |
12059 | ||
12060 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
12061 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
12062 | 0x00000000, 0xffffffff }, | |
12063 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
12064 | 0x00000000, 0xffffffff }, | |
12065 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
12066 | 0x00000000, 0x00000003 }, | |
12067 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
12068 | 0x00000000, 0xffffffff }, | |
12069 | { RCVDBDI_STD_BD+0, 0x0000, | |
12070 | 0x00000000, 0xffffffff }, | |
12071 | { RCVDBDI_STD_BD+4, 0x0000, | |
12072 | 0x00000000, 0xffffffff }, | |
12073 | { RCVDBDI_STD_BD+8, 0x0000, | |
12074 | 0x00000000, 0xffff0002 }, | |
12075 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
12076 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 12077 | |
a71116d1 MC |
12078 | /* Receive BD Initiator Control Registers. */ |
12079 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
12080 | 0x00000000, 0xffffffff }, | |
12081 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
12082 | 0x00000000, 0x000003ff }, | |
12083 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
12084 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 12085 | |
a71116d1 MC |
12086 | /* Host Coalescing Control Registers. */ |
12087 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
12088 | 0x00000000, 0x00000004 }, | |
12089 | { HOSTCC_MODE, TG3_FL_5705, | |
12090 | 0x00000000, 0x000000f6 }, | |
12091 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
12092 | 0x00000000, 0xffffffff }, | |
12093 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
12094 | 0x00000000, 0x000003ff }, | |
12095 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
12096 | 0x00000000, 0xffffffff }, | |
12097 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
12098 | 0x00000000, 0x000003ff }, | |
12099 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
12100 | 0x00000000, 0xffffffff }, | |
12101 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
12102 | 0x00000000, 0x000000ff }, | |
12103 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
12104 | 0x00000000, 0xffffffff }, | |
12105 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
12106 | 0x00000000, 0x000000ff }, | |
12107 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
12108 | 0x00000000, 0xffffffff }, | |
12109 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
12110 | 0x00000000, 0xffffffff }, | |
12111 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
12112 | 0x00000000, 0xffffffff }, | |
12113 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
12114 | 0x00000000, 0x000000ff }, | |
12115 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
12116 | 0x00000000, 0xffffffff }, | |
12117 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
12118 | 0x00000000, 0x000000ff }, | |
12119 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
12120 | 0x00000000, 0xffffffff }, | |
12121 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
12122 | 0x00000000, 0xffffffff }, | |
12123 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
12124 | 0x00000000, 0xffffffff }, | |
12125 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
12126 | 0x00000000, 0xffffffff }, | |
12127 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
12128 | 0x00000000, 0xffffffff }, | |
12129 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
12130 | 0xffffffff, 0x00000000 }, | |
12131 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
12132 | 0xffffffff, 0x00000000 }, | |
12133 | ||
12134 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 12135 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 12136 | 0x00000000, 0x007fff80 }, |
b16250e3 | 12137 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
12138 | 0x00000000, 0x007fffff }, |
12139 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
12140 | 0x00000000, 0x0000003f }, | |
12141 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
12142 | 0x00000000, 0x000001ff }, | |
12143 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
12144 | 0x00000000, 0x000001ff }, | |
12145 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
12146 | 0xffffffff, 0x00000000 }, | |
12147 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
12148 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 12149 | |
a71116d1 MC |
12150 | /* Mailbox Registers */ |
12151 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
12152 | 0x00000000, 0x000001ff }, | |
12153 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
12154 | 0x00000000, 0x000001ff }, | |
12155 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
12156 | 0x00000000, 0x000007ff }, | |
12157 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
12158 | 0x00000000, 0x000001ff }, | |
12159 | ||
12160 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
12161 | }; | |
12162 | ||
b16250e3 | 12163 | is_5705 = is_5750 = 0; |
63c3a66f | 12164 | if (tg3_flag(tp, 5705_PLUS)) { |
a71116d1 | 12165 | is_5705 = 1; |
63c3a66f | 12166 | if (tg3_flag(tp, 5750_PLUS)) |
b16250e3 MC |
12167 | is_5750 = 1; |
12168 | } | |
a71116d1 MC |
12169 | |
12170 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
12171 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
12172 | continue; | |
12173 | ||
12174 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
12175 | continue; | |
12176 | ||
63c3a66f | 12177 | if (tg3_flag(tp, IS_5788) && |
a71116d1 MC |
12178 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) |
12179 | continue; | |
12180 | ||
b16250e3 MC |
12181 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
12182 | continue; | |
12183 | ||
a71116d1 MC |
12184 | offset = (u32) reg_tbl[i].offset; |
12185 | read_mask = reg_tbl[i].read_mask; | |
12186 | write_mask = reg_tbl[i].write_mask; | |
12187 | ||
12188 | /* Save the original register content */ | |
12189 | save_val = tr32(offset); | |
12190 | ||
12191 | /* Determine the read-only value. */ | |
12192 | read_val = save_val & read_mask; | |
12193 | ||
12194 | /* Write zero to the register, then make sure the read-only bits | |
12195 | * are not changed and the read/write bits are all zeros. | |
12196 | */ | |
12197 | tw32(offset, 0); | |
12198 | ||
12199 | val = tr32(offset); | |
12200 | ||
12201 | /* Test the read-only and read/write bits. */ | |
12202 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
12203 | goto out; | |
12204 | ||
12205 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
12206 | * make sure the read-only bits are not changed and the | |
12207 | * read/write bits are all ones. | |
12208 | */ | |
12209 | tw32(offset, read_mask | write_mask); | |
12210 | ||
12211 | val = tr32(offset); | |
12212 | ||
12213 | /* Test the read-only bits. */ | |
12214 | if ((val & read_mask) != read_val) | |
12215 | goto out; | |
12216 | ||
12217 | /* Test the read/write bits. */ | |
12218 | if ((val & write_mask) != write_mask) | |
12219 | goto out; | |
12220 | ||
12221 | tw32(offset, save_val); | |
12222 | } | |
12223 | ||
12224 | return 0; | |
12225 | ||
12226 | out: | |
9f88f29f | 12227 | if (netif_msg_hw(tp)) |
2445e461 MC |
12228 | netdev_err(tp->dev, |
12229 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
12230 | tw32(offset, save_val); |
12231 | return -EIO; | |
12232 | } | |
12233 | ||
7942e1db MC |
12234 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
12235 | { | |
f71e1309 | 12236 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
12237 | int i; |
12238 | u32 j; | |
12239 | ||
e9edda69 | 12240 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
12241 | for (j = 0; j < len; j += 4) { |
12242 | u32 val; | |
12243 | ||
12244 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
12245 | tg3_read_mem(tp, offset + j, &val); | |
12246 | if (val != test_pattern[i]) | |
12247 | return -EIO; | |
12248 | } | |
12249 | } | |
12250 | return 0; | |
12251 | } | |
12252 | ||
12253 | static int tg3_test_memory(struct tg3 *tp) | |
12254 | { | |
12255 | static struct mem_entry { | |
12256 | u32 offset; | |
12257 | u32 len; | |
12258 | } mem_tbl_570x[] = { | |
38690194 | 12259 | { 0x00000000, 0x00b50}, |
7942e1db MC |
12260 | { 0x00002000, 0x1c000}, |
12261 | { 0xffffffff, 0x00000} | |
12262 | }, mem_tbl_5705[] = { | |
12263 | { 0x00000100, 0x0000c}, | |
12264 | { 0x00000200, 0x00008}, | |
7942e1db MC |
12265 | { 0x00004000, 0x00800}, |
12266 | { 0x00006000, 0x01000}, | |
12267 | { 0x00008000, 0x02000}, | |
12268 | { 0x00010000, 0x0e000}, | |
12269 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
12270 | }, mem_tbl_5755[] = { |
12271 | { 0x00000200, 0x00008}, | |
12272 | { 0x00004000, 0x00800}, | |
12273 | { 0x00006000, 0x00800}, | |
12274 | { 0x00008000, 0x02000}, | |
12275 | { 0x00010000, 0x0c000}, | |
12276 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
12277 | }, mem_tbl_5906[] = { |
12278 | { 0x00000200, 0x00008}, | |
12279 | { 0x00004000, 0x00400}, | |
12280 | { 0x00006000, 0x00400}, | |
12281 | { 0x00008000, 0x01000}, | |
12282 | { 0x00010000, 0x01000}, | |
12283 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
12284 | }, mem_tbl_5717[] = { |
12285 | { 0x00000200, 0x00008}, | |
12286 | { 0x00010000, 0x0a000}, | |
12287 | { 0x00020000, 0x13c00}, | |
12288 | { 0xffffffff, 0x00000} | |
12289 | }, mem_tbl_57765[] = { | |
12290 | { 0x00000200, 0x00008}, | |
12291 | { 0x00004000, 0x00800}, | |
12292 | { 0x00006000, 0x09800}, | |
12293 | { 0x00010000, 0x0a000}, | |
12294 | { 0xffffffff, 0x00000} | |
7942e1db MC |
12295 | }; |
12296 | struct mem_entry *mem_tbl; | |
12297 | int err = 0; | |
12298 | int i; | |
12299 | ||
63c3a66f | 12300 | if (tg3_flag(tp, 5717_PLUS)) |
8b5a6c42 | 12301 | mem_tbl = mem_tbl_5717; |
55086ad9 | 12302 | else if (tg3_flag(tp, 57765_CLASS)) |
8b5a6c42 | 12303 | mem_tbl = mem_tbl_57765; |
63c3a66f | 12304 | else if (tg3_flag(tp, 5755_PLUS)) |
321d32a0 MC |
12305 | mem_tbl = mem_tbl_5755; |
12306 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
12307 | mem_tbl = mem_tbl_5906; | |
63c3a66f | 12308 | else if (tg3_flag(tp, 5705_PLUS)) |
321d32a0 MC |
12309 | mem_tbl = mem_tbl_5705; |
12310 | else | |
7942e1db MC |
12311 | mem_tbl = mem_tbl_570x; |
12312 | ||
12313 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
12314 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
12315 | if (err) | |
7942e1db MC |
12316 | break; |
12317 | } | |
6aa20a22 | 12318 | |
7942e1db MC |
12319 | return err; |
12320 | } | |
12321 | ||
bb158d69 MC |
12322 | #define TG3_TSO_MSS 500 |
12323 | ||
12324 | #define TG3_TSO_IP_HDR_LEN 20 | |
12325 | #define TG3_TSO_TCP_HDR_LEN 20 | |
12326 | #define TG3_TSO_TCP_OPT_LEN 12 | |
12327 | ||
12328 | static const u8 tg3_tso_header[] = { | |
12329 | 0x08, 0x00, | |
12330 | 0x45, 0x00, 0x00, 0x00, | |
12331 | 0x00, 0x00, 0x40, 0x00, | |
12332 | 0x40, 0x06, 0x00, 0x00, | |
12333 | 0x0a, 0x00, 0x00, 0x01, | |
12334 | 0x0a, 0x00, 0x00, 0x02, | |
12335 | 0x0d, 0x00, 0xe0, 0x00, | |
12336 | 0x00, 0x00, 0x01, 0x00, | |
12337 | 0x00, 0x00, 0x02, 0x00, | |
12338 | 0x80, 0x10, 0x10, 0x00, | |
12339 | 0x14, 0x09, 0x00, 0x00, | |
12340 | 0x01, 0x01, 0x08, 0x0a, | |
12341 | 0x11, 0x11, 0x11, 0x11, | |
12342 | 0x11, 0x11, 0x11, 0x11, | |
12343 | }; | |
9f40dead | 12344 | |
28a45957 | 12345 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) |
c76949a6 | 12346 | { |
5e5a7f37 | 12347 | u32 rx_start_idx, rx_idx, tx_idx, opaque_key; |
bb158d69 | 12348 | u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; |
84b67b27 | 12349 | u32 budget; |
9205fd9c ED |
12350 | struct sk_buff *skb; |
12351 | u8 *tx_data, *rx_data; | |
c76949a6 MC |
12352 | dma_addr_t map; |
12353 | int num_pkts, tx_len, rx_len, i, err; | |
12354 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 12355 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 12356 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 12357 | |
c8873405 MC |
12358 | tnapi = &tp->napi[0]; |
12359 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 12360 | if (tp->irq_cnt > 1) { |
63c3a66f | 12361 | if (tg3_flag(tp, ENABLE_RSS)) |
1da85aa3 | 12362 | rnapi = &tp->napi[1]; |
63c3a66f | 12363 | if (tg3_flag(tp, ENABLE_TSS)) |
c8873405 | 12364 | tnapi = &tp->napi[1]; |
0c1d0e2b | 12365 | } |
fd2ce37f | 12366 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 12367 | |
c76949a6 MC |
12368 | err = -EIO; |
12369 | ||
4852a861 | 12370 | tx_len = pktsz; |
a20e9c62 | 12371 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
12372 | if (!skb) |
12373 | return -ENOMEM; | |
12374 | ||
c76949a6 MC |
12375 | tx_data = skb_put(skb, tx_len); |
12376 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
12377 | memset(tx_data + 6, 0x0, 8); | |
12378 | ||
4852a861 | 12379 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
c76949a6 | 12380 | |
28a45957 | 12381 | if (tso_loopback) { |
bb158d69 MC |
12382 | struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN]; |
12383 | ||
12384 | u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN + | |
12385 | TG3_TSO_TCP_OPT_LEN; | |
12386 | ||
12387 | memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header, | |
12388 | sizeof(tg3_tso_header)); | |
12389 | mss = TG3_TSO_MSS; | |
12390 | ||
12391 | val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); | |
12392 | num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); | |
12393 | ||
12394 | /* Set the total length field in the IP header */ | |
12395 | iph->tot_len = htons((u16)(mss + hdr_len)); | |
12396 | ||
12397 | base_flags = (TXD_FLAG_CPU_PRE_DMA | | |
12398 | TXD_FLAG_CPU_POST_DMA); | |
12399 | ||
63c3a66f JP |
12400 | if (tg3_flag(tp, HW_TSO_1) || |
12401 | tg3_flag(tp, HW_TSO_2) || | |
12402 | tg3_flag(tp, HW_TSO_3)) { | |
bb158d69 MC |
12403 | struct tcphdr *th; |
12404 | val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; | |
12405 | th = (struct tcphdr *)&tx_data[val]; | |
12406 | th->check = 0; | |
12407 | } else | |
12408 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
12409 | ||
63c3a66f | 12410 | if (tg3_flag(tp, HW_TSO_3)) { |
bb158d69 MC |
12411 | mss |= (hdr_len & 0xc) << 12; |
12412 | if (hdr_len & 0x10) | |
12413 | base_flags |= 0x00000010; | |
12414 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 12415 | } else if (tg3_flag(tp, HW_TSO_2)) |
bb158d69 | 12416 | mss |= hdr_len << 9; |
63c3a66f | 12417 | else if (tg3_flag(tp, HW_TSO_1) || |
bb158d69 MC |
12418 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
12419 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); | |
12420 | } else { | |
12421 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); | |
12422 | } | |
12423 | ||
12424 | data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header); | |
12425 | } else { | |
12426 | num_pkts = 1; | |
12427 | data_off = ETH_HLEN; | |
c441b456 MC |
12428 | |
12429 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && | |
12430 | tx_len > VLAN_ETH_FRAME_LEN) | |
12431 | base_flags |= TXD_FLAG_JMB_PKT; | |
bb158d69 MC |
12432 | } |
12433 | ||
12434 | for (i = data_off; i < tx_len; i++) | |
c76949a6 MC |
12435 | tx_data[i] = (u8) (i & 0xff); |
12436 | ||
f4188d8a AD |
12437 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
12438 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
12439 | dev_kfree_skb(skb); |
12440 | return -EIO; | |
12441 | } | |
c76949a6 | 12442 | |
0d681b27 MC |
12443 | val = tnapi->tx_prod; |
12444 | tnapi->tx_buffers[val].skb = skb; | |
12445 | dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); | |
12446 | ||
c76949a6 | 12447 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 12448 | rnapi->coal_now); |
c76949a6 MC |
12449 | |
12450 | udelay(10); | |
12451 | ||
898a56f8 | 12452 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 12453 | |
84b67b27 MC |
12454 | budget = tg3_tx_avail(tnapi); |
12455 | if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len, | |
d1a3b737 MC |
12456 | base_flags | TXD_FLAG_END, mss, 0)) { |
12457 | tnapi->tx_buffers[val].skb = NULL; | |
12458 | dev_kfree_skb(skb); | |
12459 | return -EIO; | |
12460 | } | |
c76949a6 | 12461 | |
f3f3f27e | 12462 | tnapi->tx_prod++; |
c76949a6 | 12463 | |
6541b806 MC |
12464 | /* Sync BD data before updating mailbox */ |
12465 | wmb(); | |
12466 | ||
f3f3f27e MC |
12467 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
12468 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
12469 | |
12470 | udelay(10); | |
12471 | ||
303fc921 MC |
12472 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
12473 | for (i = 0; i < 35; i++) { | |
c76949a6 | 12474 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 12475 | coal_now); |
c76949a6 MC |
12476 | |
12477 | udelay(10); | |
12478 | ||
898a56f8 MC |
12479 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
12480 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 12481 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
12482 | (rx_idx == (rx_start_idx + num_pkts))) |
12483 | break; | |
12484 | } | |
12485 | ||
ba1142e4 | 12486 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); |
c76949a6 MC |
12487 | dev_kfree_skb(skb); |
12488 | ||
f3f3f27e | 12489 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
12490 | goto out; |
12491 | ||
12492 | if (rx_idx != rx_start_idx + num_pkts) | |
12493 | goto out; | |
12494 | ||
bb158d69 MC |
12495 | val = data_off; |
12496 | while (rx_idx != rx_start_idx) { | |
12497 | desc = &rnapi->rx_rcb[rx_start_idx++]; | |
12498 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
12499 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
c76949a6 | 12500 | |
bb158d69 MC |
12501 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && |
12502 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
12503 | goto out; | |
c76949a6 | 12504 | |
bb158d69 MC |
12505 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) |
12506 | - ETH_FCS_LEN; | |
c76949a6 | 12507 | |
28a45957 | 12508 | if (!tso_loopback) { |
bb158d69 MC |
12509 | if (rx_len != tx_len) |
12510 | goto out; | |
4852a861 | 12511 | |
bb158d69 MC |
12512 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
12513 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
12514 | goto out; | |
12515 | } else { | |
12516 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
12517 | goto out; | |
12518 | } | |
12519 | } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
12520 | (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
54e0a67f | 12521 | >> RXD_TCPCSUM_SHIFT != 0xffff) { |
4852a861 | 12522 | goto out; |
bb158d69 | 12523 | } |
4852a861 | 12524 | |
bb158d69 | 12525 | if (opaque_key == RXD_OPAQUE_RING_STD) { |
9205fd9c | 12526 | rx_data = tpr->rx_std_buffers[desc_idx].data; |
bb158d69 MC |
12527 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], |
12528 | mapping); | |
12529 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
9205fd9c | 12530 | rx_data = tpr->rx_jmb_buffers[desc_idx].data; |
bb158d69 MC |
12531 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], |
12532 | mapping); | |
12533 | } else | |
12534 | goto out; | |
c76949a6 | 12535 | |
bb158d69 MC |
12536 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, |
12537 | PCI_DMA_FROMDEVICE); | |
c76949a6 | 12538 | |
9205fd9c | 12539 | rx_data += TG3_RX_OFFSET(tp); |
bb158d69 | 12540 | for (i = data_off; i < rx_len; i++, val++) { |
9205fd9c | 12541 | if (*(rx_data + i) != (u8) (val & 0xff)) |
bb158d69 MC |
12542 | goto out; |
12543 | } | |
c76949a6 | 12544 | } |
bb158d69 | 12545 | |
c76949a6 | 12546 | err = 0; |
6aa20a22 | 12547 | |
9205fd9c | 12548 | /* tg3_free_rings will unmap and free the rx_data */ |
c76949a6 MC |
12549 | out: |
12550 | return err; | |
12551 | } | |
12552 | ||
00c266b7 MC |
12553 | #define TG3_STD_LOOPBACK_FAILED 1 |
12554 | #define TG3_JMB_LOOPBACK_FAILED 2 | |
bb158d69 | 12555 | #define TG3_TSO_LOOPBACK_FAILED 4 |
28a45957 MC |
12556 | #define TG3_LOOPBACK_FAILED \ |
12557 | (TG3_STD_LOOPBACK_FAILED | \ | |
12558 | TG3_JMB_LOOPBACK_FAILED | \ | |
12559 | TG3_TSO_LOOPBACK_FAILED) | |
00c266b7 | 12560 | |
941ec90f | 12561 | static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) |
9f40dead | 12562 | { |
28a45957 | 12563 | int err = -EIO; |
2215e24c | 12564 | u32 eee_cap; |
c441b456 MC |
12565 | u32 jmb_pkt_sz = 9000; |
12566 | ||
12567 | if (tp->dma_limit) | |
12568 | jmb_pkt_sz = tp->dma_limit - ETH_HLEN; | |
9f40dead | 12569 | |
ab789046 MC |
12570 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
12571 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
12572 | ||
28a45957 | 12573 | if (!netif_running(tp->dev)) { |
93df8b8f NNS |
12574 | data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED; |
12575 | data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED; | |
941ec90f | 12576 | if (do_extlpbk) |
93df8b8f | 12577 | data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED; |
28a45957 MC |
12578 | goto done; |
12579 | } | |
12580 | ||
b9ec6c1b | 12581 | err = tg3_reset_hw(tp, 1); |
ab789046 | 12582 | if (err) { |
93df8b8f NNS |
12583 | data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED; |
12584 | data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED; | |
941ec90f | 12585 | if (do_extlpbk) |
93df8b8f | 12586 | data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED; |
ab789046 MC |
12587 | goto done; |
12588 | } | |
9f40dead | 12589 | |
63c3a66f | 12590 | if (tg3_flag(tp, ENABLE_RSS)) { |
4a85f098 MC |
12591 | int i; |
12592 | ||
12593 | /* Reroute all rx packets to the 1st queue */ | |
12594 | for (i = MAC_RSS_INDIR_TBL_0; | |
12595 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
12596 | tw32(i, 0x0); | |
12597 | } | |
12598 | ||
6e01b20b MC |
12599 | /* HW errata - mac loopback fails in some cases on 5780. |
12600 | * Normal traffic and PHY loopback are not affected by | |
12601 | * errata. Also, the MAC loopback test is deprecated for | |
12602 | * all newer ASIC revisions. | |
12603 | */ | |
12604 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
12605 | !tg3_flag(tp, CPMU_PRESENT)) { | |
12606 | tg3_mac_loopback(tp, true); | |
9936bcf6 | 12607 | |
28a45957 | 12608 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
93df8b8f | 12609 | data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED; |
6e01b20b MC |
12610 | |
12611 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
c441b456 | 12612 | tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) |
93df8b8f | 12613 | data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED; |
6e01b20b MC |
12614 | |
12615 | tg3_mac_loopback(tp, false); | |
12616 | } | |
4852a861 | 12617 | |
f07e9af3 | 12618 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
63c3a66f | 12619 | !tg3_flag(tp, USE_PHYLIB)) { |
5e5a7f37 MC |
12620 | int i; |
12621 | ||
941ec90f | 12622 | tg3_phy_lpbk_set(tp, 0, false); |
5e5a7f37 MC |
12623 | |
12624 | /* Wait for link */ | |
12625 | for (i = 0; i < 100; i++) { | |
12626 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
12627 | break; | |
12628 | mdelay(1); | |
12629 | } | |
12630 | ||
28a45957 | 12631 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
93df8b8f | 12632 | data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED; |
63c3a66f | 12633 | if (tg3_flag(tp, TSO_CAPABLE) && |
28a45957 | 12634 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) |
93df8b8f | 12635 | data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED; |
63c3a66f | 12636 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
c441b456 | 12637 | tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) |
93df8b8f | 12638 | data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED; |
9f40dead | 12639 | |
941ec90f MC |
12640 | if (do_extlpbk) { |
12641 | tg3_phy_lpbk_set(tp, 0, true); | |
12642 | ||
12643 | /* All link indications report up, but the hardware | |
12644 | * isn't really ready for about 20 msec. Double it | |
12645 | * to be sure. | |
12646 | */ | |
12647 | mdelay(40); | |
12648 | ||
12649 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) | |
93df8b8f NNS |
12650 | data[TG3_EXT_LOOPB_TEST] |= |
12651 | TG3_STD_LOOPBACK_FAILED; | |
941ec90f MC |
12652 | if (tg3_flag(tp, TSO_CAPABLE) && |
12653 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) | |
93df8b8f NNS |
12654 | data[TG3_EXT_LOOPB_TEST] |= |
12655 | TG3_TSO_LOOPBACK_FAILED; | |
941ec90f | 12656 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
c441b456 | 12657 | tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) |
93df8b8f NNS |
12658 | data[TG3_EXT_LOOPB_TEST] |= |
12659 | TG3_JMB_LOOPBACK_FAILED; | |
941ec90f MC |
12660 | } |
12661 | ||
5e5a7f37 MC |
12662 | /* Re-enable gphy autopowerdown. */ |
12663 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) | |
12664 | tg3_phy_toggle_apd(tp, true); | |
12665 | } | |
6833c043 | 12666 | |
93df8b8f NNS |
12667 | err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] | |
12668 | data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0; | |
28a45957 | 12669 | |
ab789046 MC |
12670 | done: |
12671 | tp->phy_flags |= eee_cap; | |
12672 | ||
9f40dead MC |
12673 | return err; |
12674 | } | |
12675 | ||
4cafd3f5 MC |
12676 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
12677 | u64 *data) | |
12678 | { | |
566f86ad | 12679 | struct tg3 *tp = netdev_priv(dev); |
941ec90f | 12680 | bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; |
566f86ad | 12681 | |
bed9829f MC |
12682 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && |
12683 | tg3_power_up(tp)) { | |
12684 | etest->flags |= ETH_TEST_FL_FAILED; | |
12685 | memset(data, 1, sizeof(u64) * TG3_NUM_TEST); | |
12686 | return; | |
12687 | } | |
bc1c7567 | 12688 | |
566f86ad MC |
12689 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
12690 | ||
12691 | if (tg3_test_nvram(tp) != 0) { | |
12692 | etest->flags |= ETH_TEST_FL_FAILED; | |
93df8b8f | 12693 | data[TG3_NVRAM_TEST] = 1; |
566f86ad | 12694 | } |
941ec90f | 12695 | if (!doextlpbk && tg3_test_link(tp)) { |
ca43007a | 12696 | etest->flags |= ETH_TEST_FL_FAILED; |
93df8b8f | 12697 | data[TG3_LINK_TEST] = 1; |
ca43007a | 12698 | } |
a71116d1 | 12699 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 12700 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
12701 | |
12702 | if (netif_running(dev)) { | |
b02fd9e3 | 12703 | tg3_phy_stop(tp); |
a71116d1 | 12704 | tg3_netif_stop(tp); |
bbe832c0 MC |
12705 | irq_sync = 1; |
12706 | } | |
a71116d1 | 12707 | |
bbe832c0 | 12708 | tg3_full_lock(tp, irq_sync); |
a71116d1 | 12709 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); |
ec41c7df | 12710 | err = tg3_nvram_lock(tp); |
a71116d1 | 12711 | tg3_halt_cpu(tp, RX_CPU_BASE); |
63c3a66f | 12712 | if (!tg3_flag(tp, 5705_PLUS)) |
a71116d1 | 12713 | tg3_halt_cpu(tp, TX_CPU_BASE); |
ec41c7df MC |
12714 | if (!err) |
12715 | tg3_nvram_unlock(tp); | |
a71116d1 | 12716 | |
f07e9af3 | 12717 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
12718 | tg3_phy_reset(tp); |
12719 | ||
a71116d1 MC |
12720 | if (tg3_test_registers(tp) != 0) { |
12721 | etest->flags |= ETH_TEST_FL_FAILED; | |
93df8b8f | 12722 | data[TG3_REGISTER_TEST] = 1; |
a71116d1 | 12723 | } |
28a45957 | 12724 | |
7942e1db MC |
12725 | if (tg3_test_memory(tp) != 0) { |
12726 | etest->flags |= ETH_TEST_FL_FAILED; | |
93df8b8f | 12727 | data[TG3_MEMORY_TEST] = 1; |
7942e1db | 12728 | } |
28a45957 | 12729 | |
941ec90f MC |
12730 | if (doextlpbk) |
12731 | etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; | |
12732 | ||
93df8b8f | 12733 | if (tg3_test_loopback(tp, data, doextlpbk)) |
c76949a6 | 12734 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 12735 | |
f47c11ee DM |
12736 | tg3_full_unlock(tp); |
12737 | ||
d4bc3927 MC |
12738 | if (tg3_test_interrupt(tp) != 0) { |
12739 | etest->flags |= ETH_TEST_FL_FAILED; | |
93df8b8f | 12740 | data[TG3_INTERRUPT_TEST] = 1; |
d4bc3927 | 12741 | } |
f47c11ee DM |
12742 | |
12743 | tg3_full_lock(tp, 0); | |
d4bc3927 | 12744 | |
a71116d1 MC |
12745 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
12746 | if (netif_running(dev)) { | |
63c3a66f | 12747 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
12748 | err2 = tg3_restart_hw(tp, 1); |
12749 | if (!err2) | |
b9ec6c1b | 12750 | tg3_netif_start(tp); |
a71116d1 | 12751 | } |
f47c11ee DM |
12752 | |
12753 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
12754 | |
12755 | if (irq_sync && !err2) | |
12756 | tg3_phy_start(tp); | |
a71116d1 | 12757 | } |
80096068 | 12758 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 12759 | tg3_power_down(tp); |
bc1c7567 | 12760 | |
4cafd3f5 MC |
12761 | } |
12762 | ||
1da177e4 LT |
12763 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
12764 | { | |
12765 | struct mii_ioctl_data *data = if_mii(ifr); | |
12766 | struct tg3 *tp = netdev_priv(dev); | |
12767 | int err; | |
12768 | ||
63c3a66f | 12769 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 12770 | struct phy_device *phydev; |
f07e9af3 | 12771 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 12772 | return -EAGAIN; |
3f0e3ad7 | 12773 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 12774 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
12775 | } |
12776 | ||
33f401ae | 12777 | switch (cmd) { |
1da177e4 | 12778 | case SIOCGMIIPHY: |
882e9793 | 12779 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
12780 | |
12781 | /* fallthru */ | |
12782 | case SIOCGMIIREG: { | |
12783 | u32 mii_regval; | |
12784 | ||
f07e9af3 | 12785 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
12786 | break; /* We have no PHY */ |
12787 | ||
34eea5ac | 12788 | if (!netif_running(dev)) |
bc1c7567 MC |
12789 | return -EAGAIN; |
12790 | ||
f47c11ee | 12791 | spin_lock_bh(&tp->lock); |
1da177e4 | 12792 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 12793 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
12794 | |
12795 | data->val_out = mii_regval; | |
12796 | ||
12797 | return err; | |
12798 | } | |
12799 | ||
12800 | case SIOCSMIIREG: | |
f07e9af3 | 12801 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
12802 | break; /* We have no PHY */ |
12803 | ||
34eea5ac | 12804 | if (!netif_running(dev)) |
bc1c7567 MC |
12805 | return -EAGAIN; |
12806 | ||
f47c11ee | 12807 | spin_lock_bh(&tp->lock); |
1da177e4 | 12808 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 12809 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
12810 | |
12811 | return err; | |
12812 | ||
12813 | default: | |
12814 | /* do nothing */ | |
12815 | break; | |
12816 | } | |
12817 | return -EOPNOTSUPP; | |
12818 | } | |
12819 | ||
15f9850d DM |
12820 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
12821 | { | |
12822 | struct tg3 *tp = netdev_priv(dev); | |
12823 | ||
12824 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
12825 | return 0; | |
12826 | } | |
12827 | ||
d244c892 MC |
12828 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
12829 | { | |
12830 | struct tg3 *tp = netdev_priv(dev); | |
12831 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
12832 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
12833 | ||
63c3a66f | 12834 | if (!tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
12835 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; |
12836 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
12837 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
12838 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
12839 | } | |
12840 | ||
12841 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
12842 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
12843 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
12844 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
12845 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
12846 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
12847 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
12848 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
12849 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
12850 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
12851 | return -EINVAL; | |
12852 | ||
12853 | /* No rx interrupts will be generated if both are zero */ | |
12854 | if ((ec->rx_coalesce_usecs == 0) && | |
12855 | (ec->rx_max_coalesced_frames == 0)) | |
12856 | return -EINVAL; | |
12857 | ||
12858 | /* No tx interrupts will be generated if both are zero */ | |
12859 | if ((ec->tx_coalesce_usecs == 0) && | |
12860 | (ec->tx_max_coalesced_frames == 0)) | |
12861 | return -EINVAL; | |
12862 | ||
12863 | /* Only copy relevant parameters, ignore all others. */ | |
12864 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
12865 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
12866 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
12867 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
12868 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
12869 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
12870 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
12871 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
12872 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
12873 | ||
12874 | if (netif_running(dev)) { | |
12875 | tg3_full_lock(tp, 0); | |
12876 | __tg3_set_coalesce(tp, &tp->coal); | |
12877 | tg3_full_unlock(tp); | |
12878 | } | |
12879 | return 0; | |
12880 | } | |
12881 | ||
7282d491 | 12882 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
12883 | .get_settings = tg3_get_settings, |
12884 | .set_settings = tg3_set_settings, | |
12885 | .get_drvinfo = tg3_get_drvinfo, | |
12886 | .get_regs_len = tg3_get_regs_len, | |
12887 | .get_regs = tg3_get_regs, | |
12888 | .get_wol = tg3_get_wol, | |
12889 | .set_wol = tg3_set_wol, | |
12890 | .get_msglevel = tg3_get_msglevel, | |
12891 | .set_msglevel = tg3_set_msglevel, | |
12892 | .nway_reset = tg3_nway_reset, | |
12893 | .get_link = ethtool_op_get_link, | |
12894 | .get_eeprom_len = tg3_get_eeprom_len, | |
12895 | .get_eeprom = tg3_get_eeprom, | |
12896 | .set_eeprom = tg3_set_eeprom, | |
12897 | .get_ringparam = tg3_get_ringparam, | |
12898 | .set_ringparam = tg3_set_ringparam, | |
12899 | .get_pauseparam = tg3_get_pauseparam, | |
12900 | .set_pauseparam = tg3_set_pauseparam, | |
4cafd3f5 | 12901 | .self_test = tg3_self_test, |
1da177e4 | 12902 | .get_strings = tg3_get_strings, |
81b8709c | 12903 | .set_phys_id = tg3_set_phys_id, |
1da177e4 | 12904 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 12905 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 12906 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 12907 | .get_sset_count = tg3_get_sset_count, |
90415477 MC |
12908 | .get_rxnfc = tg3_get_rxnfc, |
12909 | .get_rxfh_indir_size = tg3_get_rxfh_indir_size, | |
12910 | .get_rxfh_indir = tg3_get_rxfh_indir, | |
12911 | .set_rxfh_indir = tg3_set_rxfh_indir, | |
0968169c MC |
12912 | .get_channels = tg3_get_channels, |
12913 | .set_channels = tg3_set_channels, | |
7d41e49a | 12914 | .get_ts_info = tg3_get_ts_info, |
1da177e4 LT |
12915 | }; |
12916 | ||
b4017c53 DM |
12917 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
12918 | struct rtnl_link_stats64 *stats) | |
12919 | { | |
12920 | struct tg3 *tp = netdev_priv(dev); | |
12921 | ||
0f566b20 MC |
12922 | spin_lock_bh(&tp->lock); |
12923 | if (!tp->hw_stats) { | |
12924 | spin_unlock_bh(&tp->lock); | |
b4017c53 | 12925 | return &tp->net_stats_prev; |
0f566b20 | 12926 | } |
b4017c53 | 12927 | |
b4017c53 DM |
12928 | tg3_get_nstats(tp, stats); |
12929 | spin_unlock_bh(&tp->lock); | |
12930 | ||
12931 | return stats; | |
12932 | } | |
12933 | ||
ccd5ba9d MC |
12934 | static void tg3_set_rx_mode(struct net_device *dev) |
12935 | { | |
12936 | struct tg3 *tp = netdev_priv(dev); | |
12937 | ||
12938 | if (!netif_running(dev)) | |
12939 | return; | |
12940 | ||
12941 | tg3_full_lock(tp, 0); | |
12942 | __tg3_set_rx_mode(dev); | |
12943 | tg3_full_unlock(tp); | |
12944 | } | |
12945 | ||
faf1627a MC |
12946 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
12947 | int new_mtu) | |
12948 | { | |
12949 | dev->mtu = new_mtu; | |
12950 | ||
12951 | if (new_mtu > ETH_DATA_LEN) { | |
12952 | if (tg3_flag(tp, 5780_CLASS)) { | |
12953 | netdev_update_features(dev); | |
12954 | tg3_flag_clear(tp, TSO_CAPABLE); | |
12955 | } else { | |
12956 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
12957 | } | |
12958 | } else { | |
12959 | if (tg3_flag(tp, 5780_CLASS)) { | |
12960 | tg3_flag_set(tp, TSO_CAPABLE); | |
12961 | netdev_update_features(dev); | |
12962 | } | |
12963 | tg3_flag_clear(tp, JUMBO_RING_ENABLE); | |
12964 | } | |
12965 | } | |
12966 | ||
12967 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
12968 | { | |
12969 | struct tg3 *tp = netdev_priv(dev); | |
2fae5e36 | 12970 | int err, reset_phy = 0; |
faf1627a MC |
12971 | |
12972 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
12973 | return -EINVAL; | |
12974 | ||
12975 | if (!netif_running(dev)) { | |
12976 | /* We'll just catch it later when the | |
12977 | * device is up'd. | |
12978 | */ | |
12979 | tg3_set_mtu(dev, tp, new_mtu); | |
12980 | return 0; | |
12981 | } | |
12982 | ||
12983 | tg3_phy_stop(tp); | |
12984 | ||
12985 | tg3_netif_stop(tp); | |
12986 | ||
12987 | tg3_full_lock(tp, 1); | |
12988 | ||
12989 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
12990 | ||
12991 | tg3_set_mtu(dev, tp, new_mtu); | |
12992 | ||
2fae5e36 MC |
12993 | /* Reset PHY, otherwise the read DMA engine will be in a mode that |
12994 | * breaks all requests to 256 bytes. | |
12995 | */ | |
12996 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) | |
12997 | reset_phy = 1; | |
12998 | ||
12999 | err = tg3_restart_hw(tp, reset_phy); | |
faf1627a MC |
13000 | |
13001 | if (!err) | |
13002 | tg3_netif_start(tp); | |
13003 | ||
13004 | tg3_full_unlock(tp); | |
13005 | ||
13006 | if (!err) | |
13007 | tg3_phy_start(tp); | |
13008 | ||
13009 | return err; | |
13010 | } | |
13011 | ||
13012 | static const struct net_device_ops tg3_netdev_ops = { | |
13013 | .ndo_open = tg3_open, | |
13014 | .ndo_stop = tg3_close, | |
13015 | .ndo_start_xmit = tg3_start_xmit, | |
13016 | .ndo_get_stats64 = tg3_get_stats64, | |
13017 | .ndo_validate_addr = eth_validate_addr, | |
13018 | .ndo_set_rx_mode = tg3_set_rx_mode, | |
13019 | .ndo_set_mac_address = tg3_set_mac_addr, | |
13020 | .ndo_do_ioctl = tg3_ioctl, | |
13021 | .ndo_tx_timeout = tg3_tx_timeout, | |
13022 | .ndo_change_mtu = tg3_change_mtu, | |
13023 | .ndo_fix_features = tg3_fix_features, | |
13024 | .ndo_set_features = tg3_set_features, | |
13025 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
13026 | .ndo_poll_controller = tg3_poll_controller, | |
13027 | #endif | |
13028 | }; | |
13029 | ||
229b1ad1 | 13030 | static void tg3_get_eeprom_size(struct tg3 *tp) |
1da177e4 | 13031 | { |
1b27777a | 13032 | u32 cursize, val, magic; |
1da177e4 LT |
13033 | |
13034 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
13035 | ||
e4f34110 | 13036 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
13037 | return; |
13038 | ||
b16250e3 MC |
13039 | if ((magic != TG3_EEPROM_MAGIC) && |
13040 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
13041 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
13042 | return; |
13043 | ||
13044 | /* | |
13045 | * Size the chip by reading offsets at increasing powers of two. | |
13046 | * When we encounter our validation signature, we know the addressing | |
13047 | * has wrapped around, and thus have our chip size. | |
13048 | */ | |
1b27777a | 13049 | cursize = 0x10; |
1da177e4 LT |
13050 | |
13051 | while (cursize < tp->nvram_size) { | |
e4f34110 | 13052 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
13053 | return; |
13054 | ||
1820180b | 13055 | if (val == magic) |
1da177e4 LT |
13056 | break; |
13057 | ||
13058 | cursize <<= 1; | |
13059 | } | |
13060 | ||
13061 | tp->nvram_size = cursize; | |
13062 | } | |
6aa20a22 | 13063 | |
229b1ad1 | 13064 | static void tg3_get_nvram_size(struct tg3 *tp) |
1da177e4 LT |
13065 | { |
13066 | u32 val; | |
13067 | ||
63c3a66f | 13068 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) |
1b27777a MC |
13069 | return; |
13070 | ||
13071 | /* Selfboot format */ | |
1820180b | 13072 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
13073 | tg3_get_eeprom_size(tp); |
13074 | return; | |
13075 | } | |
13076 | ||
6d348f2c | 13077 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 13078 | if (val != 0) { |
6d348f2c MC |
13079 | /* This is confusing. We want to operate on the |
13080 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
13081 | * call will read from NVRAM and byteswap the data | |
13082 | * according to the byteswapping settings for all | |
13083 | * other register accesses. This ensures the data we | |
13084 | * want will always reside in the lower 16-bits. | |
13085 | * However, the data in NVRAM is in LE format, which | |
13086 | * means the data from the NVRAM read will always be | |
13087 | * opposite the endianness of the CPU. The 16-bit | |
13088 | * byteswap then brings the data to CPU endianness. | |
13089 | */ | |
13090 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
13091 | return; |
13092 | } | |
13093 | } | |
fd1122a2 | 13094 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
13095 | } |
13096 | ||
229b1ad1 | 13097 | static void tg3_get_nvram_info(struct tg3 *tp) |
1da177e4 LT |
13098 | { |
13099 | u32 nvcfg1; | |
13100 | ||
13101 | nvcfg1 = tr32(NVRAM_CFG1); | |
13102 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
63c3a66f | 13103 | tg3_flag_set(tp, FLASH); |
8590a603 | 13104 | } else { |
1da177e4 LT |
13105 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
13106 | tw32(NVRAM_CFG1, nvcfg1); | |
13107 | } | |
13108 | ||
6ff6f81d | 13109 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
63c3a66f | 13110 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 | 13111 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
13112 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
13113 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
13114 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 13115 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
13116 | break; |
13117 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
13118 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
13119 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
13120 | break; | |
13121 | case FLASH_VENDOR_ATMEL_EEPROM: | |
13122 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
13123 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
63c3a66f | 13124 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
13125 | break; |
13126 | case FLASH_VENDOR_ST: | |
13127 | tp->nvram_jedecnum = JEDEC_ST; | |
13128 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
63c3a66f | 13129 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
13130 | break; |
13131 | case FLASH_VENDOR_SAIFUN: | |
13132 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
13133 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
13134 | break; | |
13135 | case FLASH_VENDOR_SST_SMALL: | |
13136 | case FLASH_VENDOR_SST_LARGE: | |
13137 | tp->nvram_jedecnum = JEDEC_SST; | |
13138 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
13139 | break; | |
1da177e4 | 13140 | } |
8590a603 | 13141 | } else { |
1da177e4 LT |
13142 | tp->nvram_jedecnum = JEDEC_ATMEL; |
13143 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 13144 | tg3_flag_set(tp, NVRAM_BUFFERED); |
1da177e4 LT |
13145 | } |
13146 | } | |
13147 | ||
229b1ad1 | 13148 | static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
a1b950d5 MC |
13149 | { |
13150 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
13151 | case FLASH_5752PAGE_SIZE_256: | |
13152 | tp->nvram_pagesize = 256; | |
13153 | break; | |
13154 | case FLASH_5752PAGE_SIZE_512: | |
13155 | tp->nvram_pagesize = 512; | |
13156 | break; | |
13157 | case FLASH_5752PAGE_SIZE_1K: | |
13158 | tp->nvram_pagesize = 1024; | |
13159 | break; | |
13160 | case FLASH_5752PAGE_SIZE_2K: | |
13161 | tp->nvram_pagesize = 2048; | |
13162 | break; | |
13163 | case FLASH_5752PAGE_SIZE_4K: | |
13164 | tp->nvram_pagesize = 4096; | |
13165 | break; | |
13166 | case FLASH_5752PAGE_SIZE_264: | |
13167 | tp->nvram_pagesize = 264; | |
13168 | break; | |
13169 | case FLASH_5752PAGE_SIZE_528: | |
13170 | tp->nvram_pagesize = 528; | |
13171 | break; | |
13172 | } | |
13173 | } | |
13174 | ||
229b1ad1 | 13175 | static void tg3_get_5752_nvram_info(struct tg3 *tp) |
361b4ac2 MC |
13176 | { |
13177 | u32 nvcfg1; | |
13178 | ||
13179 | nvcfg1 = tr32(NVRAM_CFG1); | |
13180 | ||
e6af301b MC |
13181 | /* NVRAM protection for TPM */ |
13182 | if (nvcfg1 & (1 << 27)) | |
63c3a66f | 13183 | tg3_flag_set(tp, PROTECTED_NVRAM); |
e6af301b | 13184 | |
361b4ac2 | 13185 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
13186 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
13187 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
13188 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13189 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
13190 | break; |
13191 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
13192 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13193 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13194 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13195 | break; |
13196 | case FLASH_5752VENDOR_ST_M45PE10: | |
13197 | case FLASH_5752VENDOR_ST_M45PE20: | |
13198 | case FLASH_5752VENDOR_ST_M45PE40: | |
13199 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13200 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13201 | tg3_flag_set(tp, FLASH); | |
8590a603 | 13202 | break; |
361b4ac2 MC |
13203 | } |
13204 | ||
63c3a66f | 13205 | if (tg3_flag(tp, FLASH)) { |
a1b950d5 | 13206 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 13207 | } else { |
361b4ac2 MC |
13208 | /* For eeprom, set pagesize to maximum eeprom size */ |
13209 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
13210 | ||
13211 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
13212 | tw32(NVRAM_CFG1, nvcfg1); | |
13213 | } | |
13214 | } | |
13215 | ||
229b1ad1 | 13216 | static void tg3_get_5755_nvram_info(struct tg3 *tp) |
d3c7b886 | 13217 | { |
989a9d23 | 13218 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
13219 | |
13220 | nvcfg1 = tr32(NVRAM_CFG1); | |
13221 | ||
13222 | /* NVRAM protection for TPM */ | |
989a9d23 | 13223 | if (nvcfg1 & (1 << 27)) { |
63c3a66f | 13224 | tg3_flag_set(tp, PROTECTED_NVRAM); |
989a9d23 MC |
13225 | protect = 1; |
13226 | } | |
d3c7b886 | 13227 | |
989a9d23 MC |
13228 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
13229 | switch (nvcfg1) { | |
8590a603 MC |
13230 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
13231 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
13232 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
13233 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
13234 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13235 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13236 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13237 | tp->nvram_pagesize = 264; |
13238 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
13239 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
13240 | tp->nvram_size = (protect ? 0x3e200 : | |
13241 | TG3_NVRAM_SIZE_512KB); | |
13242 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
13243 | tp->nvram_size = (protect ? 0x1f200 : | |
13244 | TG3_NVRAM_SIZE_256KB); | |
13245 | else | |
13246 | tp->nvram_size = (protect ? 0x1f200 : | |
13247 | TG3_NVRAM_SIZE_128KB); | |
13248 | break; | |
13249 | case FLASH_5752VENDOR_ST_M45PE10: | |
13250 | case FLASH_5752VENDOR_ST_M45PE20: | |
13251 | case FLASH_5752VENDOR_ST_M45PE40: | |
13252 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13253 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13254 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13255 | tp->nvram_pagesize = 256; |
13256 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
13257 | tp->nvram_size = (protect ? | |
13258 | TG3_NVRAM_SIZE_64KB : | |
13259 | TG3_NVRAM_SIZE_128KB); | |
13260 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
13261 | tp->nvram_size = (protect ? | |
13262 | TG3_NVRAM_SIZE_64KB : | |
13263 | TG3_NVRAM_SIZE_256KB); | |
13264 | else | |
13265 | tp->nvram_size = (protect ? | |
13266 | TG3_NVRAM_SIZE_128KB : | |
13267 | TG3_NVRAM_SIZE_512KB); | |
13268 | break; | |
d3c7b886 MC |
13269 | } |
13270 | } | |
13271 | ||
229b1ad1 | 13272 | static void tg3_get_5787_nvram_info(struct tg3 *tp) |
1b27777a MC |
13273 | { |
13274 | u32 nvcfg1; | |
13275 | ||
13276 | nvcfg1 = tr32(NVRAM_CFG1); | |
13277 | ||
13278 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
13279 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
13280 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
13281 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
13282 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
13283 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13284 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 | 13285 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
1b27777a | 13286 | |
8590a603 MC |
13287 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
13288 | tw32(NVRAM_CFG1, nvcfg1); | |
13289 | break; | |
13290 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
13291 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
13292 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
13293 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
13294 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13295 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13296 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13297 | tp->nvram_pagesize = 264; |
13298 | break; | |
13299 | case FLASH_5752VENDOR_ST_M45PE10: | |
13300 | case FLASH_5752VENDOR_ST_M45PE20: | |
13301 | case FLASH_5752VENDOR_ST_M45PE40: | |
13302 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13303 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13304 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13305 | tp->nvram_pagesize = 256; |
13306 | break; | |
1b27777a MC |
13307 | } |
13308 | } | |
13309 | ||
229b1ad1 | 13310 | static void tg3_get_5761_nvram_info(struct tg3 *tp) |
6b91fa02 MC |
13311 | { |
13312 | u32 nvcfg1, protect = 0; | |
13313 | ||
13314 | nvcfg1 = tr32(NVRAM_CFG1); | |
13315 | ||
13316 | /* NVRAM protection for TPM */ | |
13317 | if (nvcfg1 & (1 << 27)) { | |
63c3a66f | 13318 | tg3_flag_set(tp, PROTECTED_NVRAM); |
6b91fa02 MC |
13319 | protect = 1; |
13320 | } | |
13321 | ||
13322 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
13323 | switch (nvcfg1) { | |
8590a603 MC |
13324 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
13325 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
13326 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
13327 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
13328 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
13329 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
13330 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
13331 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
13332 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13333 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13334 | tg3_flag_set(tp, FLASH); | |
13335 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
8590a603 MC |
13336 | tp->nvram_pagesize = 256; |
13337 | break; | |
13338 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
13339 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
13340 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
13341 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
13342 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
13343 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
13344 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
13345 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
13346 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13347 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13348 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13349 | tp->nvram_pagesize = 256; |
13350 | break; | |
6b91fa02 MC |
13351 | } |
13352 | ||
13353 | if (protect) { | |
13354 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
13355 | } else { | |
13356 | switch (nvcfg1) { | |
8590a603 MC |
13357 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
13358 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
13359 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
13360 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
13361 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
13362 | break; | |
13363 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
13364 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
13365 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
13366 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
13367 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
13368 | break; | |
13369 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
13370 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
13371 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
13372 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
13373 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
13374 | break; | |
13375 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
13376 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
13377 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
13378 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
13379 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13380 | break; | |
6b91fa02 MC |
13381 | } |
13382 | } | |
13383 | } | |
13384 | ||
229b1ad1 | 13385 | static void tg3_get_5906_nvram_info(struct tg3 *tp) |
b5d3772c MC |
13386 | { |
13387 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13388 | tg3_flag_set(tp, NVRAM_BUFFERED); |
b5d3772c MC |
13389 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
13390 | } | |
13391 | ||
229b1ad1 | 13392 | static void tg3_get_57780_nvram_info(struct tg3 *tp) |
321d32a0 MC |
13393 | { |
13394 | u32 nvcfg1; | |
13395 | ||
13396 | nvcfg1 = tr32(NVRAM_CFG1); | |
13397 | ||
13398 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13399 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
13400 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
13401 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13402 | tg3_flag_set(tp, NVRAM_BUFFERED); |
321d32a0 MC |
13403 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
13404 | ||
13405 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
13406 | tw32(NVRAM_CFG1, nvcfg1); | |
13407 | return; | |
13408 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
13409 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
13410 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
13411 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
13412 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
13413 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
13414 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
13415 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13416 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13417 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
13418 | |
13419 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13420 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
13421 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
13422 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
13423 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13424 | break; | |
13425 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
13426 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
13427 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13428 | break; | |
13429 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
13430 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
13431 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
13432 | break; | |
13433 | } | |
13434 | break; | |
13435 | case FLASH_5752VENDOR_ST_M45PE10: | |
13436 | case FLASH_5752VENDOR_ST_M45PE20: | |
13437 | case FLASH_5752VENDOR_ST_M45PE40: | |
13438 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13439 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13440 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
13441 | |
13442 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13443 | case FLASH_5752VENDOR_ST_M45PE10: | |
13444 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13445 | break; | |
13446 | case FLASH_5752VENDOR_ST_M45PE20: | |
13447 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13448 | break; | |
13449 | case FLASH_5752VENDOR_ST_M45PE40: | |
13450 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
13451 | break; | |
13452 | } | |
13453 | break; | |
13454 | default: | |
63c3a66f | 13455 | tg3_flag_set(tp, NO_NVRAM); |
321d32a0 MC |
13456 | return; |
13457 | } | |
13458 | ||
a1b950d5 MC |
13459 | tg3_nvram_get_pagesize(tp, nvcfg1); |
13460 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 13461 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
a1b950d5 MC |
13462 | } |
13463 | ||
13464 | ||
229b1ad1 | 13465 | static void tg3_get_5717_nvram_info(struct tg3 *tp) |
a1b950d5 MC |
13466 | { |
13467 | u32 nvcfg1; | |
13468 | ||
13469 | nvcfg1 = tr32(NVRAM_CFG1); | |
13470 | ||
13471 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13472 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
13473 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
13474 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13475 | tg3_flag_set(tp, NVRAM_BUFFERED); |
a1b950d5 MC |
13476 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
13477 | ||
13478 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
13479 | tw32(NVRAM_CFG1, nvcfg1); | |
13480 | return; | |
13481 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
13482 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
13483 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
13484 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
13485 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
13486 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
13487 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
13488 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13489 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13490 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
13491 | |
13492 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13493 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
66ee33bf MC |
13494 | /* Detect size with tg3_nvram_get_size() */ |
13495 | break; | |
a1b950d5 MC |
13496 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
13497 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
13498 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13499 | break; | |
13500 | default: | |
13501 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13502 | break; | |
13503 | } | |
321d32a0 | 13504 | break; |
a1b950d5 MC |
13505 | case FLASH_5717VENDOR_ST_M_M25PE10: |
13506 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
13507 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
13508 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
13509 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
13510 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
13511 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
13512 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
13513 | case FLASH_5717VENDOR_ST_25USPT: | |
13514 | case FLASH_5717VENDOR_ST_45USPT: | |
13515 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13516 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13517 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
13518 | |
13519 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13520 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
a1b950d5 | 13521 | case FLASH_5717VENDOR_ST_M_M45PE20: |
66ee33bf MC |
13522 | /* Detect size with tg3_nvram_get_size() */ |
13523 | break; | |
13524 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
a1b950d5 MC |
13525 | case FLASH_5717VENDOR_ST_A_M45PE20: |
13526 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13527 | break; | |
13528 | default: | |
13529 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13530 | break; | |
13531 | } | |
321d32a0 | 13532 | break; |
a1b950d5 | 13533 | default: |
63c3a66f | 13534 | tg3_flag_set(tp, NO_NVRAM); |
a1b950d5 | 13535 | return; |
321d32a0 | 13536 | } |
a1b950d5 MC |
13537 | |
13538 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
13539 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 13540 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
321d32a0 MC |
13541 | } |
13542 | ||
229b1ad1 | 13543 | static void tg3_get_5720_nvram_info(struct tg3 *tp) |
9b91b5f1 MC |
13544 | { |
13545 | u32 nvcfg1, nvmpinstrp; | |
13546 | ||
13547 | nvcfg1 = tr32(NVRAM_CFG1); | |
13548 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
13549 | ||
13550 | switch (nvmpinstrp) { | |
13551 | case FLASH_5720_EEPROM_HD: | |
13552 | case FLASH_5720_EEPROM_LD: | |
13553 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13554 | tg3_flag_set(tp, NVRAM_BUFFERED); |
9b91b5f1 MC |
13555 | |
13556 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
13557 | tw32(NVRAM_CFG1, nvcfg1); | |
13558 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
13559 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
13560 | else | |
13561 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
13562 | return; | |
13563 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
13564 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
13565 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
13566 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
13567 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
13568 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
13569 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
13570 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
13571 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
13572 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
13573 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
13574 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
13575 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13576 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13577 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
13578 | |
13579 | switch (nvmpinstrp) { | |
13580 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
13581 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
13582 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
13583 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13584 | break; | |
13585 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
13586 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
13587 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
13588 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
13589 | break; | |
13590 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
13591 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
13592 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
13593 | break; | |
13594 | default: | |
13595 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13596 | break; | |
13597 | } | |
13598 | break; | |
13599 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
13600 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
13601 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
13602 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
13603 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
13604 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
13605 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
13606 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
13607 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
13608 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
13609 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
13610 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
13611 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
13612 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
13613 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
13614 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
13615 | case FLASH_5720VENDOR_ST_25USPT: | |
13616 | case FLASH_5720VENDOR_ST_45USPT: | |
13617 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13618 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13619 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
13620 | |
13621 | switch (nvmpinstrp) { | |
13622 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
13623 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
13624 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
13625 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
13626 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13627 | break; | |
13628 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
13629 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
13630 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
13631 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
13632 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
13633 | break; | |
13634 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
13635 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
13636 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
13637 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
13638 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
13639 | break; | |
13640 | default: | |
13641 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13642 | break; | |
13643 | } | |
13644 | break; | |
13645 | default: | |
63c3a66f | 13646 | tg3_flag_set(tp, NO_NVRAM); |
9b91b5f1 MC |
13647 | return; |
13648 | } | |
13649 | ||
13650 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
13651 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 13652 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
9b91b5f1 MC |
13653 | } |
13654 | ||
1da177e4 | 13655 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
229b1ad1 | 13656 | static void tg3_nvram_init(struct tg3 *tp) |
1da177e4 | 13657 | { |
1da177e4 LT |
13658 | tw32_f(GRC_EEPROM_ADDR, |
13659 | (EEPROM_ADDR_FSM_RESET | | |
13660 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
13661 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
13662 | ||
9d57f01c | 13663 | msleep(1); |
1da177e4 LT |
13664 | |
13665 | /* Enable seeprom accesses. */ | |
13666 | tw32_f(GRC_LOCAL_CTRL, | |
13667 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
13668 | udelay(100); | |
13669 | ||
13670 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13671 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
63c3a66f | 13672 | tg3_flag_set(tp, NVRAM); |
1da177e4 | 13673 | |
ec41c7df | 13674 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
13675 | netdev_warn(tp->dev, |
13676 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 13677 | __func__); |
ec41c7df MC |
13678 | return; |
13679 | } | |
e6af301b | 13680 | tg3_enable_nvram_access(tp); |
1da177e4 | 13681 | |
989a9d23 MC |
13682 | tp->nvram_size = 0; |
13683 | ||
361b4ac2 MC |
13684 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
13685 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
13686 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
13687 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 13688 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
13689 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
13690 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 13691 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
13692 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
13693 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
13694 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
13695 | tg3_get_5906_nvram_info(tp); | |
b703df6f | 13696 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
55086ad9 | 13697 | tg3_flag(tp, 57765_CLASS)) |
321d32a0 | 13698 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
13699 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13700 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 13701 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
13702 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
13703 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
13704 | else |
13705 | tg3_get_nvram_info(tp); | |
13706 | ||
989a9d23 MC |
13707 | if (tp->nvram_size == 0) |
13708 | tg3_get_nvram_size(tp); | |
1da177e4 | 13709 | |
e6af301b | 13710 | tg3_disable_nvram_access(tp); |
381291b7 | 13711 | tg3_nvram_unlock(tp); |
1da177e4 LT |
13712 | |
13713 | } else { | |
63c3a66f JP |
13714 | tg3_flag_clear(tp, NVRAM); |
13715 | tg3_flag_clear(tp, NVRAM_BUFFERED); | |
1da177e4 LT |
13716 | |
13717 | tg3_get_eeprom_size(tp); | |
13718 | } | |
13719 | } | |
13720 | ||
1da177e4 LT |
13721 | struct subsys_tbl_ent { |
13722 | u16 subsys_vendor, subsys_devid; | |
13723 | u32 phy_id; | |
13724 | }; | |
13725 | ||
229b1ad1 | 13726 | static struct subsys_tbl_ent subsys_id_to_phy_id[] = { |
1da177e4 | 13727 | /* Broadcom boards. */ |
24daf2b0 | 13728 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13729 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13730 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13731 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13732 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13733 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
13734 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
13735 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
13736 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 13737 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13738 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13739 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
13740 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
13741 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
13742 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 13743 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13744 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13745 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13746 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13747 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 13748 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13749 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
13750 | |
13751 | /* 3com boards. */ | |
24daf2b0 | 13752 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 13753 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13754 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 13755 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
13756 | { TG3PCI_SUBVENDOR_ID_3COM, |
13757 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
13758 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 13759 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13760 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 13761 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
13762 | |
13763 | /* DELL boards. */ | |
24daf2b0 | 13764 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13765 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13766 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13767 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13768 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13769 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 13770 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13771 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
13772 | |
13773 | /* Compaq boards. */ | |
24daf2b0 | 13774 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 13775 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13776 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 13777 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
13778 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
13779 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
13780 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 13781 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13782 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 13783 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
13784 | |
13785 | /* IBM boards. */ | |
24daf2b0 MC |
13786 | { TG3PCI_SUBVENDOR_ID_IBM, |
13787 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
13788 | }; |
13789 | ||
229b1ad1 | 13790 | static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
13791 | { |
13792 | int i; | |
13793 | ||
13794 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
13795 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
13796 | tp->pdev->subsystem_vendor) && | |
13797 | (subsys_id_to_phy_id[i].subsys_devid == | |
13798 | tp->pdev->subsystem_device)) | |
13799 | return &subsys_id_to_phy_id[i]; | |
13800 | } | |
13801 | return NULL; | |
13802 | } | |
13803 | ||
229b1ad1 | 13804 | static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 13805 | { |
1da177e4 | 13806 | u32 val; |
f49639e6 | 13807 | |
79eb6904 | 13808 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
13809 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
13810 | ||
a85feb8c | 13811 | /* Assume an onboard device and WOL capable by default. */ |
63c3a66f JP |
13812 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
13813 | tg3_flag_set(tp, WOL_CAP); | |
72b845e0 | 13814 | |
b5d3772c | 13815 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 13816 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
63c3a66f JP |
13817 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
13818 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 13819 | } |
0527ba35 MC |
13820 | val = tr32(VCPU_CFGSHDW); |
13821 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
63c3a66f | 13822 | tg3_flag_set(tp, ASPM_WORKAROUND); |
0527ba35 | 13823 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
6fdbab9d | 13824 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) { |
63c3a66f | 13825 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
13826 | device_set_wakeup_enable(&tp->pdev->dev, true); |
13827 | } | |
05ac4cb7 | 13828 | goto done; |
b5d3772c MC |
13829 | } |
13830 | ||
1da177e4 LT |
13831 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
13832 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
13833 | u32 nic_cfg, led_cfg; | |
a9daf367 | 13834 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 13835 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
13836 | |
13837 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
13838 | tp->nic_sram_data_cfg = nic_cfg; | |
13839 | ||
13840 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
13841 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
6ff6f81d MC |
13842 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
13843 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13844 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && | |
1da177e4 LT |
13845 | (ver > 0) && (ver < 0x100)) |
13846 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
13847 | ||
a9daf367 MC |
13848 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
13849 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
13850 | ||
1da177e4 LT |
13851 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
13852 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
13853 | eeprom_phy_serdes = 1; | |
13854 | ||
13855 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
13856 | if (nic_phy_id != 0) { | |
13857 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
13858 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
13859 | ||
13860 | eeprom_phy_id = (id1 >> 16) << 10; | |
13861 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
13862 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
13863 | } else | |
13864 | eeprom_phy_id = 0; | |
13865 | ||
7d0c41ef | 13866 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 13867 | if (eeprom_phy_serdes) { |
63c3a66f | 13868 | if (!tg3_flag(tp, 5705_PLUS)) |
f07e9af3 | 13869 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 13870 | else |
f07e9af3 | 13871 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 13872 | } |
7d0c41ef | 13873 | |
63c3a66f | 13874 | if (tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
13875 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
13876 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 13877 | else |
1da177e4 LT |
13878 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
13879 | ||
13880 | switch (led_cfg) { | |
13881 | default: | |
13882 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
13883 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
13884 | break; | |
13885 | ||
13886 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
13887 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
13888 | break; | |
13889 | ||
13890 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
13891 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
13892 | |
13893 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
13894 | * read on some older 5700/5701 bootcode. | |
13895 | */ | |
13896 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13897 | ASIC_REV_5700 || | |
13898 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13899 | ASIC_REV_5701) | |
13900 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
13901 | ||
1da177e4 LT |
13902 | break; |
13903 | ||
13904 | case SHASTA_EXT_LED_SHARED: | |
13905 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
13906 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
13907 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
13908 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
13909 | LED_CTRL_MODE_PHY_2); | |
13910 | break; | |
13911 | ||
13912 | case SHASTA_EXT_LED_MAC: | |
13913 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
13914 | break; | |
13915 | ||
13916 | case SHASTA_EXT_LED_COMBO: | |
13917 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
13918 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
13919 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
13920 | LED_CTRL_MODE_PHY_2); | |
13921 | break; | |
13922 | ||
855e1111 | 13923 | } |
1da177e4 LT |
13924 | |
13925 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13926 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
13927 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
13928 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
13929 | ||
b2a5c19c MC |
13930 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
13931 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 13932 | |
9d26e213 | 13933 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
63c3a66f | 13934 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
9d26e213 MC |
13935 | if ((tp->pdev->subsystem_vendor == |
13936 | PCI_VENDOR_ID_ARIMA) && | |
13937 | (tp->pdev->subsystem_device == 0x205a || | |
13938 | tp->pdev->subsystem_device == 0x2063)) | |
63c3a66f | 13939 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
9d26e213 | 13940 | } else { |
63c3a66f JP |
13941 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
13942 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 13943 | } |
1da177e4 LT |
13944 | |
13945 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f JP |
13946 | tg3_flag_set(tp, ENABLE_ASF); |
13947 | if (tg3_flag(tp, 5750_PLUS)) | |
13948 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 | 13949 | } |
b2b98d4a MC |
13950 | |
13951 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
63c3a66f JP |
13952 | tg3_flag(tp, 5750_PLUS)) |
13953 | tg3_flag_set(tp, ENABLE_APE); | |
b2b98d4a | 13954 | |
f07e9af3 | 13955 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c | 13956 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
63c3a66f | 13957 | tg3_flag_clear(tp, WOL_CAP); |
1da177e4 | 13958 | |
63c3a66f | 13959 | if (tg3_flag(tp, WOL_CAP) && |
6fdbab9d | 13960 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) { |
63c3a66f | 13961 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
13962 | device_set_wakeup_enable(&tp->pdev->dev, true); |
13963 | } | |
0527ba35 | 13964 | |
1da177e4 | 13965 | if (cfg2 & (1 << 17)) |
f07e9af3 | 13966 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
13967 | |
13968 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
13969 | /* bootcode if bit 18 is set */ | |
13970 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 13971 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 13972 | |
63c3a66f JP |
13973 | if ((tg3_flag(tp, 57765_PLUS) || |
13974 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
13975 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 | 13976 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 13977 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 13978 | |
63c3a66f | 13979 | if (tg3_flag(tp, PCI_EXPRESS) && |
8c69b1e7 | 13980 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
63c3a66f | 13981 | !tg3_flag(tp, 57765_PLUS)) { |
8ed5d97e MC |
13982 | u32 cfg3; |
13983 | ||
13984 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
13985 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
63c3a66f | 13986 | tg3_flag_set(tp, ASPM_WORKAROUND); |
8ed5d97e | 13987 | } |
a9daf367 | 13988 | |
14417063 | 13989 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
63c3a66f | 13990 | tg3_flag_set(tp, RGMII_INBAND_DISABLE); |
a9daf367 | 13991 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
63c3a66f | 13992 | tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); |
a9daf367 | 13993 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) |
63c3a66f | 13994 | tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); |
1da177e4 | 13995 | } |
05ac4cb7 | 13996 | done: |
63c3a66f | 13997 | if (tg3_flag(tp, WOL_CAP)) |
43067ed8 | 13998 | device_set_wakeup_enable(&tp->pdev->dev, |
63c3a66f | 13999 | tg3_flag(tp, WOL_ENABLE)); |
43067ed8 RW |
14000 | else |
14001 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
14002 | } |
14003 | ||
229b1ad1 | 14004 | static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
b2a5c19c MC |
14005 | { |
14006 | int i; | |
14007 | u32 val; | |
14008 | ||
14009 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
14010 | tw32(OTP_CTRL, cmd); | |
14011 | ||
14012 | /* Wait for up to 1 ms for command to execute. */ | |
14013 | for (i = 0; i < 100; i++) { | |
14014 | val = tr32(OTP_STATUS); | |
14015 | if (val & OTP_STATUS_CMD_DONE) | |
14016 | break; | |
14017 | udelay(10); | |
14018 | } | |
14019 | ||
14020 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
14021 | } | |
14022 | ||
14023 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
14024 | * configuration is a 32-bit value that straddles the alignment boundary. | |
14025 | * We do two 32-bit reads and then shift and merge the results. | |
14026 | */ | |
229b1ad1 | 14027 | static u32 tg3_read_otp_phycfg(struct tg3 *tp) |
b2a5c19c MC |
14028 | { |
14029 | u32 bhalf_otp, thalf_otp; | |
14030 | ||
14031 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
14032 | ||
14033 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
14034 | return 0; | |
14035 | ||
14036 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
14037 | ||
14038 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
14039 | return 0; | |
14040 | ||
14041 | thalf_otp = tr32(OTP_READ_DATA); | |
14042 | ||
14043 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
14044 | ||
14045 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
14046 | return 0; | |
14047 | ||
14048 | bhalf_otp = tr32(OTP_READ_DATA); | |
14049 | ||
14050 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
14051 | } | |
14052 | ||
229b1ad1 | 14053 | static void tg3_phy_init_link_config(struct tg3 *tp) |
e256f8a3 | 14054 | { |
202ff1c2 | 14055 | u32 adv = ADVERTISED_Autoneg; |
e256f8a3 MC |
14056 | |
14057 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
14058 | adv |= ADVERTISED_1000baseT_Half | | |
14059 | ADVERTISED_1000baseT_Full; | |
14060 | ||
14061 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
14062 | adv |= ADVERTISED_100baseT_Half | | |
14063 | ADVERTISED_100baseT_Full | | |
14064 | ADVERTISED_10baseT_Half | | |
14065 | ADVERTISED_10baseT_Full | | |
14066 | ADVERTISED_TP; | |
14067 | else | |
14068 | adv |= ADVERTISED_FIBRE; | |
14069 | ||
14070 | tp->link_config.advertising = adv; | |
e740522e MC |
14071 | tp->link_config.speed = SPEED_UNKNOWN; |
14072 | tp->link_config.duplex = DUPLEX_UNKNOWN; | |
e256f8a3 | 14073 | tp->link_config.autoneg = AUTONEG_ENABLE; |
e740522e MC |
14074 | tp->link_config.active_speed = SPEED_UNKNOWN; |
14075 | tp->link_config.active_duplex = DUPLEX_UNKNOWN; | |
34655ad6 MC |
14076 | |
14077 | tp->old_link = -1; | |
e256f8a3 MC |
14078 | } |
14079 | ||
229b1ad1 | 14080 | static int tg3_phy_probe(struct tg3 *tp) |
7d0c41ef MC |
14081 | { |
14082 | u32 hw_phy_id_1, hw_phy_id_2; | |
14083 | u32 hw_phy_id, hw_phy_id_masked; | |
14084 | int err; | |
1da177e4 | 14085 | |
e256f8a3 | 14086 | /* flow control autonegotiation is default behavior */ |
63c3a66f | 14087 | tg3_flag_set(tp, PAUSE_AUTONEG); |
e256f8a3 MC |
14088 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
14089 | ||
8151ad57 MC |
14090 | if (tg3_flag(tp, ENABLE_APE)) { |
14091 | switch (tp->pci_fn) { | |
14092 | case 0: | |
14093 | tp->phy_ape_lock = TG3_APE_LOCK_PHY0; | |
14094 | break; | |
14095 | case 1: | |
14096 | tp->phy_ape_lock = TG3_APE_LOCK_PHY1; | |
14097 | break; | |
14098 | case 2: | |
14099 | tp->phy_ape_lock = TG3_APE_LOCK_PHY2; | |
14100 | break; | |
14101 | case 3: | |
14102 | tp->phy_ape_lock = TG3_APE_LOCK_PHY3; | |
14103 | break; | |
14104 | } | |
14105 | } | |
14106 | ||
63c3a66f | 14107 | if (tg3_flag(tp, USE_PHYLIB)) |
b02fd9e3 MC |
14108 | return tg3_phy_init(tp); |
14109 | ||
1da177e4 | 14110 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 14111 | * firmware access to the PHY hardware. |
1da177e4 LT |
14112 | */ |
14113 | err = 0; | |
63c3a66f | 14114 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { |
79eb6904 | 14115 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
14116 | } else { |
14117 | /* Now read the physical PHY_ID from the chip and verify | |
14118 | * that it is sane. If it doesn't look good, we fall back | |
14119 | * to either the hard-coded table based PHY_ID and failing | |
14120 | * that the value found in the eeprom area. | |
14121 | */ | |
14122 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
14123 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
14124 | ||
14125 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
14126 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
14127 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
14128 | ||
79eb6904 | 14129 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
14130 | } |
14131 | ||
79eb6904 | 14132 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 14133 | tp->phy_id = hw_phy_id; |
79eb6904 | 14134 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 14135 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 14136 | else |
f07e9af3 | 14137 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 14138 | } else { |
79eb6904 | 14139 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
14140 | /* Do nothing, phy ID already set up in |
14141 | * tg3_get_eeprom_hw_cfg(). | |
14142 | */ | |
1da177e4 LT |
14143 | } else { |
14144 | struct subsys_tbl_ent *p; | |
14145 | ||
14146 | /* No eeprom signature? Try the hardcoded | |
14147 | * subsys device table. | |
14148 | */ | |
24daf2b0 | 14149 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
14150 | if (!p) |
14151 | return -ENODEV; | |
14152 | ||
14153 | tp->phy_id = p->phy_id; | |
14154 | if (!tp->phy_id || | |
79eb6904 | 14155 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 14156 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
14157 | } |
14158 | } | |
14159 | ||
a6b68dab | 14160 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
5baa5e9a MC |
14161 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
14162 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | |
14163 | (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
a6b68dab MC |
14164 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || |
14165 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
14166 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
14167 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
14168 | ||
e256f8a3 MC |
14169 | tg3_phy_init_link_config(tp); |
14170 | ||
f07e9af3 | 14171 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
63c3a66f JP |
14172 | !tg3_flag(tp, ENABLE_APE) && |
14173 | !tg3_flag(tp, ENABLE_ASF)) { | |
e2bf73e7 | 14174 | u32 bmsr, dummy; |
1da177e4 LT |
14175 | |
14176 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
14177 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
14178 | (bmsr & BMSR_LSTATUS)) | |
14179 | goto skip_phy_reset; | |
6aa20a22 | 14180 | |
1da177e4 LT |
14181 | err = tg3_phy_reset(tp); |
14182 | if (err) | |
14183 | return err; | |
14184 | ||
42b64a45 | 14185 | tg3_phy_set_wirespeed(tp); |
1da177e4 | 14186 | |
e2bf73e7 | 14187 | if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { |
42b64a45 MC |
14188 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, |
14189 | tp->link_config.flowctrl); | |
1da177e4 LT |
14190 | |
14191 | tg3_writephy(tp, MII_BMCR, | |
14192 | BMCR_ANENABLE | BMCR_ANRESTART); | |
14193 | } | |
1da177e4 LT |
14194 | } |
14195 | ||
14196 | skip_phy_reset: | |
79eb6904 | 14197 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
14198 | err = tg3_init_5401phy_dsp(tp); |
14199 | if (err) | |
14200 | return err; | |
1da177e4 | 14201 | |
1da177e4 LT |
14202 | err = tg3_init_5401phy_dsp(tp); |
14203 | } | |
14204 | ||
1da177e4 LT |
14205 | return err; |
14206 | } | |
14207 | ||
229b1ad1 | 14208 | static void tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 14209 | { |
a4a8bb15 | 14210 | u8 *vpd_data; |
4181b2c8 | 14211 | unsigned int block_end, rosize, len; |
535a490e | 14212 | u32 vpdlen; |
184b8904 | 14213 | int j, i = 0; |
a4a8bb15 | 14214 | |
535a490e | 14215 | vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); |
a4a8bb15 MC |
14216 | if (!vpd_data) |
14217 | goto out_no_vpd; | |
1da177e4 | 14218 | |
535a490e | 14219 | i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA); |
4181b2c8 MC |
14220 | if (i < 0) |
14221 | goto out_not_found; | |
1da177e4 | 14222 | |
4181b2c8 MC |
14223 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
14224 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
14225 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 14226 | |
535a490e | 14227 | if (block_end > vpdlen) |
4181b2c8 | 14228 | goto out_not_found; |
af2c6a4a | 14229 | |
184b8904 MC |
14230 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
14231 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
14232 | if (j > 0) { | |
14233 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
14234 | ||
14235 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
14236 | if (j + len > block_end || len != 4 || | |
14237 | memcmp(&vpd_data[j], "1028", 4)) | |
14238 | goto partno; | |
14239 | ||
14240 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
14241 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
14242 | if (j < 0) | |
14243 | goto partno; | |
14244 | ||
14245 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
14246 | ||
14247 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
14248 | if (j + len > block_end) | |
14249 | goto partno; | |
14250 | ||
14251 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
535a490e | 14252 | strncat(tp->fw_ver, " bc ", vpdlen - len - 1); |
184b8904 MC |
14253 | } |
14254 | ||
14255 | partno: | |
4181b2c8 MC |
14256 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
14257 | PCI_VPD_RO_KEYWORD_PARTNO); | |
14258 | if (i < 0) | |
14259 | goto out_not_found; | |
af2c6a4a | 14260 | |
4181b2c8 | 14261 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 14262 | |
4181b2c8 MC |
14263 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
14264 | if (len > TG3_BPN_SIZE || | |
535a490e | 14265 | (len + i) > vpdlen) |
4181b2c8 | 14266 | goto out_not_found; |
1da177e4 | 14267 | |
4181b2c8 | 14268 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 14269 | |
1da177e4 | 14270 | out_not_found: |
a4a8bb15 | 14271 | kfree(vpd_data); |
37a949c5 | 14272 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
14273 | return; |
14274 | ||
14275 | out_no_vpd: | |
37a949c5 | 14276 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
79d49695 MC |
14277 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
14278 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) | |
37a949c5 MC |
14279 | strcpy(tp->board_part_number, "BCM5717"); |
14280 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
14281 | strcpy(tp->board_part_number, "BCM5718"); | |
14282 | else | |
14283 | goto nomatch; | |
14284 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
14285 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
14286 | strcpy(tp->board_part_number, "BCM57780"); | |
14287 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
14288 | strcpy(tp->board_part_number, "BCM57760"); | |
14289 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
14290 | strcpy(tp->board_part_number, "BCM57790"); | |
14291 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
14292 | strcpy(tp->board_part_number, "BCM57788"); | |
14293 | else | |
14294 | goto nomatch; | |
14295 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
14296 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
14297 | strcpy(tp->board_part_number, "BCM57761"); | |
14298 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
14299 | strcpy(tp->board_part_number, "BCM57765"); | |
14300 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
14301 | strcpy(tp->board_part_number, "BCM57781"); | |
14302 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
14303 | strcpy(tp->board_part_number, "BCM57785"); | |
14304 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
14305 | strcpy(tp->board_part_number, "BCM57791"); | |
14306 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
14307 | strcpy(tp->board_part_number, "BCM57795"); | |
14308 | else | |
14309 | goto nomatch; | |
55086ad9 MC |
14310 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) { |
14311 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) | |
14312 | strcpy(tp->board_part_number, "BCM57762"); | |
14313 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) | |
14314 | strcpy(tp->board_part_number, "BCM57766"); | |
14315 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) | |
14316 | strcpy(tp->board_part_number, "BCM57782"); | |
14317 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) | |
14318 | strcpy(tp->board_part_number, "BCM57786"); | |
14319 | else | |
14320 | goto nomatch; | |
37a949c5 | 14321 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
b5d3772c | 14322 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
14323 | } else { |
14324 | nomatch: | |
b5d3772c | 14325 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 14326 | } |
1da177e4 LT |
14327 | } |
14328 | ||
229b1ad1 | 14329 | static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
9c8a620e MC |
14330 | { |
14331 | u32 val; | |
14332 | ||
e4f34110 | 14333 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 14334 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 14335 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
14336 | val != 0) |
14337 | return 0; | |
14338 | ||
14339 | return 1; | |
14340 | } | |
14341 | ||
229b1ad1 | 14342 | static void tg3_read_bc_ver(struct tg3 *tp) |
acd9c119 | 14343 | { |
ff3a7cb2 | 14344 | u32 val, offset, start, ver_offset; |
75f9936e | 14345 | int i, dst_off; |
ff3a7cb2 | 14346 | bool newver = false; |
acd9c119 MC |
14347 | |
14348 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
14349 | tg3_nvram_read(tp, 0x4, &start)) | |
14350 | return; | |
14351 | ||
14352 | offset = tg3_nvram_logical_addr(tp, offset); | |
14353 | ||
ff3a7cb2 | 14354 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
14355 | return; |
14356 | ||
ff3a7cb2 MC |
14357 | if ((val & 0xfc000000) == 0x0c000000) { |
14358 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
14359 | return; |
14360 | ||
ff3a7cb2 MC |
14361 | if (val == 0) |
14362 | newver = true; | |
14363 | } | |
14364 | ||
75f9936e MC |
14365 | dst_off = strlen(tp->fw_ver); |
14366 | ||
ff3a7cb2 | 14367 | if (newver) { |
75f9936e MC |
14368 | if (TG3_VER_SIZE - dst_off < 16 || |
14369 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
14370 | return; |
14371 | ||
14372 | offset = offset + ver_offset - start; | |
14373 | for (i = 0; i < 16; i += 4) { | |
14374 | __be32 v; | |
14375 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
14376 | return; | |
14377 | ||
75f9936e | 14378 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
14379 | } |
14380 | } else { | |
14381 | u32 major, minor; | |
14382 | ||
14383 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
14384 | return; | |
14385 | ||
14386 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
14387 | TG3_NVM_BCVER_MAJSFT; | |
14388 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
14389 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
14390 | "v%d.%02d", major, minor); | |
acd9c119 MC |
14391 | } |
14392 | } | |
14393 | ||
229b1ad1 | 14394 | static void tg3_read_hwsb_ver(struct tg3 *tp) |
a6f6cb1c MC |
14395 | { |
14396 | u32 val, major, minor; | |
14397 | ||
14398 | /* Use native endian representation */ | |
14399 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
14400 | return; | |
14401 | ||
14402 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
14403 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
14404 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
14405 | TG3_NVM_HWSB_CFG1_MINSFT; | |
14406 | ||
14407 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
14408 | } | |
14409 | ||
229b1ad1 | 14410 | static void tg3_read_sb_ver(struct tg3 *tp, u32 val) |
dfe00d7d MC |
14411 | { |
14412 | u32 offset, major, minor, build; | |
14413 | ||
75f9936e | 14414 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
14415 | |
14416 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
14417 | return; | |
14418 | ||
14419 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
14420 | case TG3_EEPROM_SB_REVISION_0: | |
14421 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
14422 | break; | |
14423 | case TG3_EEPROM_SB_REVISION_2: | |
14424 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
14425 | break; | |
14426 | case TG3_EEPROM_SB_REVISION_3: | |
14427 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
14428 | break; | |
a4153d40 MC |
14429 | case TG3_EEPROM_SB_REVISION_4: |
14430 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
14431 | break; | |
14432 | case TG3_EEPROM_SB_REVISION_5: | |
14433 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
14434 | break; | |
bba226ac MC |
14435 | case TG3_EEPROM_SB_REVISION_6: |
14436 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
14437 | break; | |
dfe00d7d MC |
14438 | default: |
14439 | return; | |
14440 | } | |
14441 | ||
e4f34110 | 14442 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
14443 | return; |
14444 | ||
14445 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
14446 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
14447 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
14448 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
14449 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
14450 | ||
14451 | if (minor > 99 || build > 26) | |
14452 | return; | |
14453 | ||
75f9936e MC |
14454 | offset = strlen(tp->fw_ver); |
14455 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
14456 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
14457 | |
14458 | if (build > 0) { | |
75f9936e MC |
14459 | offset = strlen(tp->fw_ver); |
14460 | if (offset < TG3_VER_SIZE - 1) | |
14461 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
14462 | } |
14463 | } | |
14464 | ||
229b1ad1 | 14465 | static void tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
14466 | { |
14467 | u32 val, offset, start; | |
acd9c119 | 14468 | int i, vlen; |
9c8a620e MC |
14469 | |
14470 | for (offset = TG3_NVM_DIR_START; | |
14471 | offset < TG3_NVM_DIR_END; | |
14472 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 14473 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
14474 | return; |
14475 | ||
9c8a620e MC |
14476 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
14477 | break; | |
14478 | } | |
14479 | ||
14480 | if (offset == TG3_NVM_DIR_END) | |
14481 | return; | |
14482 | ||
63c3a66f | 14483 | if (!tg3_flag(tp, 5705_PLUS)) |
9c8a620e | 14484 | start = 0x08000000; |
e4f34110 | 14485 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
14486 | return; |
14487 | ||
e4f34110 | 14488 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 14489 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 14490 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
14491 | return; |
14492 | ||
14493 | offset += val - start; | |
14494 | ||
acd9c119 | 14495 | vlen = strlen(tp->fw_ver); |
9c8a620e | 14496 | |
acd9c119 MC |
14497 | tp->fw_ver[vlen++] = ','; |
14498 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
14499 | |
14500 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
14501 | __be32 v; |
14502 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
14503 | return; |
14504 | ||
b9fc7dc5 | 14505 | offset += sizeof(v); |
c4e6575c | 14506 | |
acd9c119 MC |
14507 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
14508 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 14509 | break; |
c4e6575c | 14510 | } |
9c8a620e | 14511 | |
acd9c119 MC |
14512 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
14513 | vlen += sizeof(v); | |
c4e6575c | 14514 | } |
acd9c119 MC |
14515 | } |
14516 | ||
229b1ad1 | 14517 | static void tg3_probe_ncsi(struct tg3 *tp) |
7fd76445 | 14518 | { |
7fd76445 | 14519 | u32 apedata; |
7fd76445 MC |
14520 | |
14521 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
14522 | if (apedata != APE_SEG_SIG_MAGIC) | |
14523 | return; | |
14524 | ||
14525 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
14526 | if (!(apedata & APE_FW_STATUS_READY)) | |
14527 | return; | |
14528 | ||
165f4d1c MC |
14529 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) |
14530 | tg3_flag_set(tp, APE_HAS_NCSI); | |
14531 | } | |
14532 | ||
229b1ad1 | 14533 | static void tg3_read_dash_ver(struct tg3 *tp) |
165f4d1c MC |
14534 | { |
14535 | int vlen; | |
14536 | u32 apedata; | |
14537 | char *fwtype; | |
14538 | ||
7fd76445 MC |
14539 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); |
14540 | ||
165f4d1c | 14541 | if (tg3_flag(tp, APE_HAS_NCSI)) |
ecc79648 | 14542 | fwtype = "NCSI"; |
165f4d1c | 14543 | else |
ecc79648 MC |
14544 | fwtype = "DASH"; |
14545 | ||
7fd76445 MC |
14546 | vlen = strlen(tp->fw_ver); |
14547 | ||
ecc79648 MC |
14548 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
14549 | fwtype, | |
7fd76445 MC |
14550 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
14551 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
14552 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
14553 | (apedata & APE_FW_VERSION_BLDMSK)); | |
14554 | } | |
14555 | ||
229b1ad1 | 14556 | static void tg3_read_fw_ver(struct tg3 *tp) |
acd9c119 MC |
14557 | { |
14558 | u32 val; | |
75f9936e | 14559 | bool vpd_vers = false; |
acd9c119 | 14560 | |
75f9936e MC |
14561 | if (tp->fw_ver[0] != 0) |
14562 | vpd_vers = true; | |
df259d8c | 14563 | |
63c3a66f | 14564 | if (tg3_flag(tp, NO_NVRAM)) { |
75f9936e | 14565 | strcat(tp->fw_ver, "sb"); |
df259d8c MC |
14566 | return; |
14567 | } | |
14568 | ||
acd9c119 MC |
14569 | if (tg3_nvram_read(tp, 0, &val)) |
14570 | return; | |
14571 | ||
14572 | if (val == TG3_EEPROM_MAGIC) | |
14573 | tg3_read_bc_ver(tp); | |
14574 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
14575 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
14576 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
14577 | tg3_read_hwsb_ver(tp); | |
acd9c119 | 14578 | |
165f4d1c MC |
14579 | if (tg3_flag(tp, ENABLE_ASF)) { |
14580 | if (tg3_flag(tp, ENABLE_APE)) { | |
14581 | tg3_probe_ncsi(tp); | |
14582 | if (!vpd_vers) | |
14583 | tg3_read_dash_ver(tp); | |
14584 | } else if (!vpd_vers) { | |
14585 | tg3_read_mgmtfw_ver(tp); | |
14586 | } | |
c9cab24e | 14587 | } |
9c8a620e MC |
14588 | |
14589 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; | |
c4e6575c MC |
14590 | } |
14591 | ||
7cb32cf2 MC |
14592 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
14593 | { | |
63c3a66f | 14594 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
de9f5230 | 14595 | return TG3_RX_RET_MAX_SIZE_5717; |
63c3a66f | 14596 | else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) |
de9f5230 | 14597 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 14598 | else |
de9f5230 | 14599 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
14600 | } |
14601 | ||
4143470c | 14602 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
14603 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
14604 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
14605 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
14606 | { }, | |
14607 | }; | |
14608 | ||
229b1ad1 | 14609 | static struct pci_dev *tg3_find_peer(struct tg3 *tp) |
16c7fa7d MC |
14610 | { |
14611 | struct pci_dev *peer; | |
14612 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
14613 | ||
14614 | for (func = 0; func < 8; func++) { | |
14615 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
14616 | if (peer && peer != tp->pdev) | |
14617 | break; | |
14618 | pci_dev_put(peer); | |
14619 | } | |
14620 | /* 5704 can be configured in single-port mode, set peer to | |
14621 | * tp->pdev in that case. | |
14622 | */ | |
14623 | if (!peer) { | |
14624 | peer = tp->pdev; | |
14625 | return peer; | |
14626 | } | |
14627 | ||
14628 | /* | |
14629 | * We don't need to keep the refcount elevated; there's no way | |
14630 | * to remove one half of this device without removing the other | |
14631 | */ | |
14632 | pci_dev_put(peer); | |
14633 | ||
14634 | return peer; | |
14635 | } | |
14636 | ||
229b1ad1 | 14637 | static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) |
42b123b1 MC |
14638 | { |
14639 | tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; | |
14640 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { | |
14641 | u32 reg; | |
14642 | ||
14643 | /* All devices that use the alternate | |
14644 | * ASIC REV location have a CPMU. | |
14645 | */ | |
14646 | tg3_flag_set(tp, CPMU_PRESENT); | |
14647 | ||
14648 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
79d49695 | 14649 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || |
42b123b1 MC |
14650 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || |
14651 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
14652 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
14653 | reg = TG3PCI_GEN2_PRODID_ASICREV; | |
14654 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || | |
14655 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
14656 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
14657 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
14658 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
14659 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
14660 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || | |
14661 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || | |
14662 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || | |
14663 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) | |
14664 | reg = TG3PCI_GEN15_PRODID_ASICREV; | |
14665 | else | |
14666 | reg = TG3PCI_PRODID_ASICREV; | |
14667 | ||
14668 | pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); | |
14669 | } | |
14670 | ||
14671 | /* Wrong chip ID in 5752 A0. This code can be removed later | |
14672 | * as A0 is not in production. | |
14673 | */ | |
14674 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
14675 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
14676 | ||
79d49695 MC |
14677 | if (tp->pci_chip_rev_id == CHIPREV_ID_5717_C0) |
14678 | tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; | |
14679 | ||
42b123b1 MC |
14680 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
14681 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14682 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
14683 | tg3_flag_set(tp, 5717_PLUS); | |
14684 | ||
14685 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
14686 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) | |
14687 | tg3_flag_set(tp, 57765_CLASS); | |
14688 | ||
14689 | if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS)) | |
14690 | tg3_flag_set(tp, 57765_PLUS); | |
14691 | ||
14692 | /* Intentionally exclude ASIC_REV_5906 */ | |
14693 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
14694 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
14695 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
14696 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
14697 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
14698 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
14699 | tg3_flag(tp, 57765_PLUS)) | |
14700 | tg3_flag_set(tp, 5755_PLUS); | |
14701 | ||
14702 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || | |
14703 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) | |
14704 | tg3_flag_set(tp, 5780_CLASS); | |
14705 | ||
14706 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14707 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14708 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || | |
14709 | tg3_flag(tp, 5755_PLUS) || | |
14710 | tg3_flag(tp, 5780_CLASS)) | |
14711 | tg3_flag_set(tp, 5750_PLUS); | |
14712 | ||
14713 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || | |
14714 | tg3_flag(tp, 5750_PLUS)) | |
14715 | tg3_flag_set(tp, 5705_PLUS); | |
14716 | } | |
14717 | ||
3d567e0e NNS |
14718 | static bool tg3_10_100_only_device(struct tg3 *tp, |
14719 | const struct pci_device_id *ent) | |
14720 | { | |
14721 | u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK; | |
14722 | ||
14723 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14724 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14725 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) | |
14726 | return true; | |
14727 | ||
14728 | if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { | |
14729 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
14730 | if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) | |
14731 | return true; | |
14732 | } else { | |
14733 | return true; | |
14734 | } | |
14735 | } | |
14736 | ||
14737 | return false; | |
14738 | } | |
14739 | ||
229b1ad1 | 14740 | static int tg3_get_invariants(struct tg3 *tp, |
3d567e0e | 14741 | const struct pci_device_id *ent) |
1da177e4 | 14742 | { |
1da177e4 | 14743 | u32 misc_ctrl_reg; |
1da177e4 LT |
14744 | u32 pci_state_reg, grc_misc_cfg; |
14745 | u32 val; | |
14746 | u16 pci_cmd; | |
5e7dfd0f | 14747 | int err; |
1da177e4 | 14748 | |
1da177e4 LT |
14749 | /* Force memory write invalidate off. If we leave it on, |
14750 | * then on 5700_BX chips we have to enable a workaround. | |
14751 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
14752 | * to match the cacheline size. The Broadcom driver have this | |
14753 | * workaround but turns MWI off all the times so never uses | |
14754 | * it. This seems to suggest that the workaround is insufficient. | |
14755 | */ | |
14756 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14757 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
14758 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14759 | ||
16821285 MC |
14760 | /* Important! -- Make sure register accesses are byteswapped |
14761 | * correctly. Also, for those chips that require it, make | |
14762 | * sure that indirect register accesses are enabled before | |
14763 | * the first operation. | |
1da177e4 LT |
14764 | */ |
14765 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14766 | &misc_ctrl_reg); | |
16821285 MC |
14767 | tp->misc_host_ctrl |= (misc_ctrl_reg & |
14768 | MISC_HOST_CTRL_CHIPREV); | |
14769 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14770 | tp->misc_host_ctrl); | |
1da177e4 | 14771 | |
42b123b1 | 14772 | tg3_detect_asic_rev(tp, misc_ctrl_reg); |
ff645bec | 14773 | |
6892914f MC |
14774 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
14775 | * we need to disable memory and use config. cycles | |
14776 | * only to access all registers. The 5702/03 chips | |
14777 | * can mistakenly decode the special cycles from the | |
14778 | * ICH chipsets as memory write cycles, causing corruption | |
14779 | * of register and memory space. Only certain ICH bridges | |
14780 | * will drive special cycles with non-zero data during the | |
14781 | * address phase which can fall within the 5703's address | |
14782 | * range. This is not an ICH bug as the PCI spec allows | |
14783 | * non-zero address during special cycles. However, only | |
14784 | * these ICH bridges are known to drive non-zero addresses | |
14785 | * during special cycles. | |
14786 | * | |
14787 | * Since special cycles do not cross PCI bridges, we only | |
14788 | * enable this workaround if the 5703 is on the secondary | |
14789 | * bus of these ICH bridges. | |
14790 | */ | |
14791 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
14792 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
14793 | static struct tg3_dev_id { | |
14794 | u32 vendor; | |
14795 | u32 device; | |
14796 | u32 rev; | |
14797 | } ich_chipsets[] = { | |
14798 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
14799 | PCI_ANY_ID }, | |
14800 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
14801 | PCI_ANY_ID }, | |
14802 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
14803 | 0xa }, | |
14804 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
14805 | PCI_ANY_ID }, | |
14806 | { }, | |
14807 | }; | |
14808 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
14809 | struct pci_dev *bridge = NULL; | |
14810 | ||
14811 | while (pci_id->vendor != 0) { | |
14812 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
14813 | bridge); | |
14814 | if (!bridge) { | |
14815 | pci_id++; | |
14816 | continue; | |
14817 | } | |
14818 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 14819 | if (bridge->revision > pci_id->rev) |
6892914f MC |
14820 | continue; |
14821 | } | |
14822 | if (bridge->subordinate && | |
14823 | (bridge->subordinate->number == | |
14824 | tp->pdev->bus->number)) { | |
63c3a66f | 14825 | tg3_flag_set(tp, ICH_WORKAROUND); |
6892914f MC |
14826 | pci_dev_put(bridge); |
14827 | break; | |
14828 | } | |
14829 | } | |
14830 | } | |
14831 | ||
6ff6f81d | 14832 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
41588ba1 MC |
14833 | static struct tg3_dev_id { |
14834 | u32 vendor; | |
14835 | u32 device; | |
14836 | } bridge_chipsets[] = { | |
14837 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
14838 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
14839 | { }, | |
14840 | }; | |
14841 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
14842 | struct pci_dev *bridge = NULL; | |
14843 | ||
14844 | while (pci_id->vendor != 0) { | |
14845 | bridge = pci_get_device(pci_id->vendor, | |
14846 | pci_id->device, | |
14847 | bridge); | |
14848 | if (!bridge) { | |
14849 | pci_id++; | |
14850 | continue; | |
14851 | } | |
14852 | if (bridge->subordinate && | |
14853 | (bridge->subordinate->number <= | |
14854 | tp->pdev->bus->number) && | |
b918c62e | 14855 | (bridge->subordinate->busn_res.end >= |
41588ba1 | 14856 | tp->pdev->bus->number)) { |
63c3a66f | 14857 | tg3_flag_set(tp, 5701_DMA_BUG); |
41588ba1 MC |
14858 | pci_dev_put(bridge); |
14859 | break; | |
14860 | } | |
14861 | } | |
14862 | } | |
14863 | ||
4a29cc2e MC |
14864 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
14865 | * DMA addresses > 40-bit. This bridge may have other additional | |
14866 | * 57xx devices behind it in some 4-port NIC designs for example. | |
14867 | * Any tg3 device found behind the bridge will also need the 40-bit | |
14868 | * DMA workaround. | |
14869 | */ | |
42b123b1 | 14870 | if (tg3_flag(tp, 5780_CLASS)) { |
63c3a66f | 14871 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4cf78e4f | 14872 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 14873 | } else { |
4a29cc2e MC |
14874 | struct pci_dev *bridge = NULL; |
14875 | ||
14876 | do { | |
14877 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
14878 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
14879 | bridge); | |
14880 | if (bridge && bridge->subordinate && | |
14881 | (bridge->subordinate->number <= | |
14882 | tp->pdev->bus->number) && | |
b918c62e | 14883 | (bridge->subordinate->busn_res.end >= |
4a29cc2e | 14884 | tp->pdev->bus->number)) { |
63c3a66f | 14885 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4a29cc2e MC |
14886 | pci_dev_put(bridge); |
14887 | break; | |
14888 | } | |
14889 | } while (bridge); | |
14890 | } | |
4cf78e4f | 14891 | |
f6eb9b1f | 14892 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
3a1e19d3 | 14893 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) |
7544b097 MC |
14894 | tp->pdev_peer = tg3_find_peer(tp); |
14895 | ||
507399f1 | 14896 | /* Determine TSO capabilities */ |
a0512944 | 14897 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) |
4d163b75 | 14898 | ; /* Do nothing. HW bug. */ |
63c3a66f JP |
14899 | else if (tg3_flag(tp, 57765_PLUS)) |
14900 | tg3_flag_set(tp, HW_TSO_3); | |
14901 | else if (tg3_flag(tp, 5755_PLUS) || | |
e849cdc3 | 14902 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
63c3a66f JP |
14903 | tg3_flag_set(tp, HW_TSO_2); |
14904 | else if (tg3_flag(tp, 5750_PLUS)) { | |
14905 | tg3_flag_set(tp, HW_TSO_1); | |
14906 | tg3_flag_set(tp, TSO_BUG); | |
507399f1 MC |
14907 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && |
14908 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
63c3a66f | 14909 | tg3_flag_clear(tp, TSO_BUG); |
507399f1 MC |
14910 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14911 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
14912 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 14913 | tg3_flag_set(tp, TSO_BUG); |
507399f1 MC |
14914 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) |
14915 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
14916 | else | |
14917 | tp->fw_needed = FIRMWARE_TG3TSO; | |
14918 | } | |
14919 | ||
dabc5c67 | 14920 | /* Selectively allow TSO based on operating conditions */ |
6ff6f81d MC |
14921 | if (tg3_flag(tp, HW_TSO_1) || |
14922 | tg3_flag(tp, HW_TSO_2) || | |
14923 | tg3_flag(tp, HW_TSO_3) || | |
cf9ecf4b MC |
14924 | tp->fw_needed) { |
14925 | /* For firmware TSO, assume ASF is disabled. | |
14926 | * We'll disable TSO later if we discover ASF | |
14927 | * is enabled in tg3_get_eeprom_hw_cfg(). | |
14928 | */ | |
dabc5c67 | 14929 | tg3_flag_set(tp, TSO_CAPABLE); |
cf9ecf4b | 14930 | } else { |
dabc5c67 MC |
14931 | tg3_flag_clear(tp, TSO_CAPABLE); |
14932 | tg3_flag_clear(tp, TSO_BUG); | |
14933 | tp->fw_needed = NULL; | |
14934 | } | |
14935 | ||
14936 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
14937 | tp->fw_needed = FIRMWARE_TG3; | |
14938 | ||
507399f1 MC |
14939 | tp->irq_max = 1; |
14940 | ||
63c3a66f JP |
14941 | if (tg3_flag(tp, 5750_PLUS)) { |
14942 | tg3_flag_set(tp, SUPPORT_MSI); | |
7544b097 MC |
14943 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || |
14944 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
14945 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
14946 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
14947 | tp->pdev_peer == tp->pdev)) | |
63c3a66f | 14948 | tg3_flag_clear(tp, SUPPORT_MSI); |
7544b097 | 14949 | |
63c3a66f | 14950 | if (tg3_flag(tp, 5755_PLUS) || |
b5d3772c | 14951 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
63c3a66f | 14952 | tg3_flag_set(tp, 1SHOT_MSI); |
52c0fd83 | 14953 | } |
4f125f42 | 14954 | |
63c3a66f JP |
14955 | if (tg3_flag(tp, 57765_PLUS)) { |
14956 | tg3_flag_set(tp, SUPPORT_MSIX); | |
507399f1 MC |
14957 | tp->irq_max = TG3_IRQ_MAX_VECS; |
14958 | } | |
f6eb9b1f | 14959 | } |
0e1406dd | 14960 | |
9102426a MC |
14961 | tp->txq_max = 1; |
14962 | tp->rxq_max = 1; | |
14963 | if (tp->irq_max > 1) { | |
14964 | tp->rxq_max = TG3_RSS_MAX_NUM_QS; | |
14965 | tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS); | |
14966 | ||
14967 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14968 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
14969 | tp->txq_max = tp->irq_max - 1; | |
14970 | } | |
14971 | ||
b7abee6e MC |
14972 | if (tg3_flag(tp, 5755_PLUS) || |
14973 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
63c3a66f | 14974 | tg3_flag_set(tp, SHORT_DMA_BUG); |
f6eb9b1f | 14975 | |
e31aa987 | 14976 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
a4cb428d | 14977 | tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; |
e31aa987 | 14978 | |
fa6b2aae MC |
14979 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
14980 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14981 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
63c3a66f | 14982 | tg3_flag_set(tp, LRG_PROD_RING_CAP); |
de9f5230 | 14983 | |
63c3a66f | 14984 | if (tg3_flag(tp, 57765_PLUS) && |
a0512944 | 14985 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0) |
63c3a66f | 14986 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); |
b703df6f | 14987 | |
63c3a66f JP |
14988 | if (!tg3_flag(tp, 5705_PLUS) || |
14989 | tg3_flag(tp, 5780_CLASS) || | |
14990 | tg3_flag(tp, USE_JUMBO_BDFLAG)) | |
14991 | tg3_flag_set(tp, JUMBO_CAPABLE); | |
0f893dc6 | 14992 | |
52f4490c MC |
14993 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14994 | &pci_state_reg); | |
14995 | ||
708ebb3a | 14996 | if (pci_is_pcie(tp->pdev)) { |
5e7dfd0f MC |
14997 | u16 lnkctl; |
14998 | ||
63c3a66f | 14999 | tg3_flag_set(tp, PCI_EXPRESS); |
5f5c51e3 | 15000 | |
0f49bfbd | 15001 | pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); |
5e7dfd0f | 15002 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { |
7196cd6c MC |
15003 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
15004 | ASIC_REV_5906) { | |
63c3a66f | 15005 | tg3_flag_clear(tp, HW_TSO_2); |
dabc5c67 | 15006 | tg3_flag_clear(tp, TSO_CAPABLE); |
7196cd6c | 15007 | } |
5e7dfd0f | 15008 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 15009 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
15010 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
15011 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
63c3a66f | 15012 | tg3_flag_set(tp, CLKREQ_BUG); |
614b0590 | 15013 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
63c3a66f | 15014 | tg3_flag_set(tp, L1PLLPD_EN); |
c7835a77 | 15015 | } |
52f4490c | 15016 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
708ebb3a JM |
15017 | /* BCM5785 devices are effectively PCIe devices, and should |
15018 | * follow PCIe codepaths, but do not have a PCIe capabilities | |
15019 | * section. | |
93a700a9 | 15020 | */ |
63c3a66f JP |
15021 | tg3_flag_set(tp, PCI_EXPRESS); |
15022 | } else if (!tg3_flag(tp, 5705_PLUS) || | |
15023 | tg3_flag(tp, 5780_CLASS)) { | |
52f4490c MC |
15024 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); |
15025 | if (!tp->pcix_cap) { | |
2445e461 MC |
15026 | dev_err(&tp->pdev->dev, |
15027 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
15028 | return -EIO; |
15029 | } | |
15030 | ||
15031 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
63c3a66f | 15032 | tg3_flag_set(tp, PCIX_MODE); |
52f4490c | 15033 | } |
1da177e4 | 15034 | |
399de50b MC |
15035 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
15036 | * reordering to the mailbox registers done by the host | |
15037 | * controller can cause major troubles. We read back from | |
15038 | * every mailbox register write to force the writes to be | |
15039 | * posted to the chip in order. | |
15040 | */ | |
4143470c | 15041 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
63c3a66f JP |
15042 | !tg3_flag(tp, PCI_EXPRESS)) |
15043 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
399de50b | 15044 | |
69fc4053 MC |
15045 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
15046 | &tp->pci_cacheline_sz); | |
15047 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
15048 | &tp->pci_lat_timer); | |
1da177e4 LT |
15049 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
15050 | tp->pci_lat_timer < 64) { | |
15051 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
15052 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
15053 | tp->pci_lat_timer); | |
1da177e4 LT |
15054 | } |
15055 | ||
16821285 MC |
15056 | /* Important! -- It is critical that the PCI-X hw workaround |
15057 | * situation is decided before the first MMIO register access. | |
15058 | */ | |
52f4490c MC |
15059 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
15060 | /* 5700 BX chips need to have their TX producer index | |
15061 | * mailboxes written twice to workaround a bug. | |
15062 | */ | |
63c3a66f | 15063 | tg3_flag_set(tp, TXD_MBOX_HWBUG); |
1da177e4 | 15064 | |
52f4490c | 15065 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
15066 | * |
15067 | * The workaround is to use indirect register accesses | |
15068 | * for all chip writes not to mailbox registers. | |
15069 | */ | |
63c3a66f | 15070 | if (tg3_flag(tp, PCIX_MODE)) { |
1da177e4 | 15071 | u32 pm_reg; |
1da177e4 | 15072 | |
63c3a66f | 15073 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
15074 | |
15075 | /* The chip can have it's power management PCI config | |
15076 | * space registers clobbered due to this bug. | |
15077 | * So explicitly force the chip into D0 here. | |
15078 | */ | |
9974a356 MC |
15079 | pci_read_config_dword(tp->pdev, |
15080 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
15081 | &pm_reg); |
15082 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
15083 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
15084 | pci_write_config_dword(tp->pdev, |
15085 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
15086 | pm_reg); |
15087 | ||
15088 | /* Also, force SERR#/PERR# in PCI command. */ | |
15089 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
15090 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
15091 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
15092 | } | |
15093 | } | |
15094 | ||
1da177e4 | 15095 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
63c3a66f | 15096 | tg3_flag_set(tp, PCI_HIGH_SPEED); |
1da177e4 | 15097 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) |
63c3a66f | 15098 | tg3_flag_set(tp, PCI_32BIT); |
1da177e4 LT |
15099 | |
15100 | /* Chip-specific fixup from Broadcom driver */ | |
15101 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
15102 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
15103 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
15104 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
15105 | } | |
15106 | ||
1ee582d8 | 15107 | /* Default fast path register access methods */ |
20094930 | 15108 | tp->read32 = tg3_read32; |
1ee582d8 | 15109 | tp->write32 = tg3_write32; |
09ee929c | 15110 | tp->read32_mbox = tg3_read32; |
20094930 | 15111 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
15112 | tp->write32_tx_mbox = tg3_write32; |
15113 | tp->write32_rx_mbox = tg3_write32; | |
15114 | ||
15115 | /* Various workaround register access methods */ | |
63c3a66f | 15116 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) |
1ee582d8 | 15117 | tp->write32 = tg3_write_indirect_reg32; |
98efd8a6 | 15118 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
63c3a66f | 15119 | (tg3_flag(tp, PCI_EXPRESS) && |
98efd8a6 MC |
15120 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { |
15121 | /* | |
15122 | * Back to back register writes can cause problems on these | |
15123 | * chips, the workaround is to read back all reg writes | |
15124 | * except those to mailbox regs. | |
15125 | * | |
15126 | * See tg3_write_indirect_reg32(). | |
15127 | */ | |
1ee582d8 | 15128 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
15129 | } |
15130 | ||
63c3a66f | 15131 | if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { |
1ee582d8 | 15132 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
63c3a66f | 15133 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1ee582d8 MC |
15134 | tp->write32_rx_mbox = tg3_write_flush_reg32; |
15135 | } | |
20094930 | 15136 | |
63c3a66f | 15137 | if (tg3_flag(tp, ICH_WORKAROUND)) { |
6892914f MC |
15138 | tp->read32 = tg3_read_indirect_reg32; |
15139 | tp->write32 = tg3_write_indirect_reg32; | |
15140 | tp->read32_mbox = tg3_read_indirect_mbox; | |
15141 | tp->write32_mbox = tg3_write_indirect_mbox; | |
15142 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
15143 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
15144 | ||
15145 | iounmap(tp->regs); | |
22abe310 | 15146 | tp->regs = NULL; |
6892914f MC |
15147 | |
15148 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
15149 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
15150 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
15151 | } | |
b5d3772c MC |
15152 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
15153 | tp->read32_mbox = tg3_read32_mbox_5906; | |
15154 | tp->write32_mbox = tg3_write32_mbox_5906; | |
15155 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
15156 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
15157 | } | |
6892914f | 15158 | |
bbadf503 | 15159 | if (tp->write32 == tg3_write_indirect_reg32 || |
63c3a66f | 15160 | (tg3_flag(tp, PCIX_MODE) && |
bbadf503 | 15161 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
f49639e6 | 15162 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
63c3a66f | 15163 | tg3_flag_set(tp, SRAM_USE_CONFIG); |
bbadf503 | 15164 | |
16821285 MC |
15165 | /* The memory arbiter has to be enabled in order for SRAM accesses |
15166 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
15167 | * sure it is enabled, but other entities such as system netboot | |
15168 | * code might disable it. | |
15169 | */ | |
15170 | val = tr32(MEMARB_MODE); | |
15171 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
15172 | ||
9dc5e342 MC |
15173 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; |
15174 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
15175 | tg3_flag(tp, 5780_CLASS)) { | |
15176 | if (tg3_flag(tp, PCIX_MODE)) { | |
15177 | pci_read_config_dword(tp->pdev, | |
15178 | tp->pcix_cap + PCI_X_STATUS, | |
15179 | &val); | |
15180 | tp->pci_fn = val & 0x7; | |
15181 | } | |
15182 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
15183 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | |
15184 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == | |
15185 | NIC_SRAM_CPMUSTAT_SIG) { | |
15186 | tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717; | |
15187 | tp->pci_fn = tp->pci_fn ? 1 : 0; | |
15188 | } | |
15189 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
15190 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
15191 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | |
15192 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == | |
15193 | NIC_SRAM_CPMUSTAT_SIG) { | |
15194 | tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> | |
15195 | TG3_CPMU_STATUS_FSHFT_5719; | |
15196 | } | |
69f11c99 MC |
15197 | } |
15198 | ||
7d0c41ef | 15199 | /* Get eeprom hw config before calling tg3_set_power_state(). |
63c3a66f | 15200 | * In particular, the TG3_FLAG_IS_NIC flag must be |
7d0c41ef MC |
15201 | * determined before calling tg3_set_power_state() so that |
15202 | * we know whether or not to switch out of Vaux power. | |
15203 | * When the flag is set, it means that GPIO1 is used for eeprom | |
15204 | * write protect and also implies that it is a LOM where GPIOs | |
15205 | * are not used to switch power. | |
6aa20a22 | 15206 | */ |
7d0c41ef MC |
15207 | tg3_get_eeprom_hw_cfg(tp); |
15208 | ||
cf9ecf4b MC |
15209 | if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) { |
15210 | tg3_flag_clear(tp, TSO_CAPABLE); | |
15211 | tg3_flag_clear(tp, TSO_BUG); | |
15212 | tp->fw_needed = NULL; | |
15213 | } | |
15214 | ||
63c3a66f | 15215 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
15216 | /* Allow reads and writes to the |
15217 | * APE register and memory space. | |
15218 | */ | |
15219 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
15220 | PCISTATE_ALLOW_APE_SHMEM_WR | |
15221 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
15222 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
15223 | pci_state_reg); | |
c9cab24e MC |
15224 | |
15225 | tg3_ape_lock_init(tp); | |
0d3031d9 MC |
15226 | } |
15227 | ||
16821285 MC |
15228 | /* Set up tp->grc_local_ctrl before calling |
15229 | * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high | |
15230 | * will bring 5700's external PHY out of reset. | |
314fba34 MC |
15231 | * It is also used as eeprom write protect on LOMs. |
15232 | */ | |
15233 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
6ff6f81d | 15234 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
63c3a66f | 15235 | tg3_flag(tp, EEPROM_WRITE_PROT)) |
314fba34 MC |
15236 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
15237 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
15238 | /* Unused GPIO3 must be driven as output on 5752 because there |
15239 | * are no pull-up resistors on unused GPIO pins. | |
15240 | */ | |
15241 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
15242 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 15243 | |
321d32a0 | 15244 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd | 15245 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
55086ad9 | 15246 | tg3_flag(tp, 57765_CLASS)) |
af36e6b6 MC |
15247 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
15248 | ||
8d519ab2 MC |
15249 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
15250 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
15251 | /* Turn off the debug UART. */ |
15252 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
63c3a66f | 15253 | if (tg3_flag(tp, IS_NIC)) |
5f0c4a3c MC |
15254 | /* Keep VMain power. */ |
15255 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
15256 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
15257 | } | |
15258 | ||
16821285 MC |
15259 | /* Switch out of Vaux if it is a NIC */ |
15260 | tg3_pwrsrc_switch_to_vmain(tp); | |
1da177e4 | 15261 | |
1da177e4 LT |
15262 | /* Derive initial jumbo mode from MTU assigned in |
15263 | * ether_setup() via the alloc_etherdev() call | |
15264 | */ | |
63c3a66f JP |
15265 | if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) |
15266 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
1da177e4 LT |
15267 | |
15268 | /* Determine WakeOnLan speed to use. */ | |
15269 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
15270 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
15271 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
15272 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
63c3a66f | 15273 | tg3_flag_clear(tp, WOL_SPEED_100MB); |
1da177e4 | 15274 | } else { |
63c3a66f | 15275 | tg3_flag_set(tp, WOL_SPEED_100MB); |
1da177e4 LT |
15276 | } |
15277 | ||
7f97a4bd | 15278 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 15279 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 15280 | |
1da177e4 | 15281 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
6ff6f81d MC |
15282 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
15283 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
1da177e4 | 15284 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && |
747e8f8b | 15285 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
15286 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
15287 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
15288 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
15289 | |
15290 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
15291 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 15292 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 15293 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 15294 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 15295 | |
63c3a66f | 15296 | if (tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 15297 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 15298 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 15299 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
63c3a66f | 15300 | !tg3_flag(tp, 57765_PLUS)) { |
c424cb24 | 15301 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 15302 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
15303 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
15304 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
15305 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
15306 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 15307 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 15308 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 15309 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 15310 | } else |
f07e9af3 | 15311 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 15312 | } |
1da177e4 | 15313 | |
b2a5c19c MC |
15314 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
15315 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
15316 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
15317 | if (tp->phy_otp == 0) | |
15318 | tp->phy_otp = TG3_OTP_DEFAULT; | |
15319 | } | |
15320 | ||
63c3a66f | 15321 | if (tg3_flag(tp, CPMU_PRESENT)) |
8ef21428 MC |
15322 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
15323 | else | |
15324 | tp->mi_mode = MAC_MI_MODE_BASE; | |
15325 | ||
1da177e4 | 15326 | tp->coalesce_mode = 0; |
1da177e4 LT |
15327 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
15328 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
15329 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
15330 | ||
4d958473 MC |
15331 | /* Set these bits to enable statistics workaround. */ |
15332 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
15333 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
15334 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
15335 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
15336 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
15337 | } | |
15338 | ||
321d32a0 MC |
15339 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
15340 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
63c3a66f | 15341 | tg3_flag_set(tp, USE_PHYLIB); |
57e6983c | 15342 | |
158d7abd MC |
15343 | err = tg3_mdio_init(tp); |
15344 | if (err) | |
15345 | return err; | |
1da177e4 LT |
15346 | |
15347 | /* Initialize data/descriptor byte/word swapping. */ | |
15348 | val = tr32(GRC_MODE); | |
f2096f94 MC |
15349 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
15350 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
15351 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
15352 | GRC_MODE_B2HRX_ENABLE | | |
15353 | GRC_MODE_HTX2B_ENABLE | | |
15354 | GRC_MODE_HOST_STACKUP); | |
15355 | else | |
15356 | val &= GRC_MODE_HOST_STACKUP; | |
15357 | ||
1da177e4 LT |
15358 | tw32(GRC_MODE, val | tp->grc_mode); |
15359 | ||
15360 | tg3_switch_clocks(tp); | |
15361 | ||
15362 | /* Clear this out for sanity. */ | |
15363 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
15364 | ||
15365 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
15366 | &pci_state_reg); | |
15367 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
63c3a66f | 15368 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { |
1da177e4 LT |
15369 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); |
15370 | ||
15371 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
15372 | chiprevid == CHIPREV_ID_5701_B0 || | |
15373 | chiprevid == CHIPREV_ID_5701_B2 || | |
15374 | chiprevid == CHIPREV_ID_5701_B5) { | |
15375 | void __iomem *sram_base; | |
15376 | ||
15377 | /* Write some dummy words into the SRAM status block | |
15378 | * area, see if it reads back correctly. If the return | |
15379 | * value is bad, force enable the PCIX workaround. | |
15380 | */ | |
15381 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
15382 | ||
15383 | writel(0x00000000, sram_base); | |
15384 | writel(0x00000000, sram_base + 4); | |
15385 | writel(0xffffffff, sram_base + 4); | |
15386 | if (readl(sram_base) != 0x00000000) | |
63c3a66f | 15387 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
15388 | } |
15389 | } | |
15390 | ||
15391 | udelay(50); | |
15392 | tg3_nvram_init(tp); | |
15393 | ||
15394 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
15395 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
15396 | ||
1da177e4 LT |
15397 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
15398 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
15399 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
63c3a66f | 15400 | tg3_flag_set(tp, IS_5788); |
1da177e4 | 15401 | |
63c3a66f | 15402 | if (!tg3_flag(tp, IS_5788) && |
6ff6f81d | 15403 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
63c3a66f JP |
15404 | tg3_flag_set(tp, TAGGED_STATUS); |
15405 | if (tg3_flag(tp, TAGGED_STATUS)) { | |
fac9b83e DM |
15406 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | |
15407 | HOSTCC_MODE_CLRTICK_TXBD); | |
15408 | ||
15409 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
15410 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
15411 | tp->misc_host_ctrl); | |
15412 | } | |
15413 | ||
3bda1258 | 15414 | /* Preserve the APE MAC_MODE bits */ |
63c3a66f | 15415 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b | 15416 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 | 15417 | else |
6e01b20b | 15418 | tp->mac_mode = 0; |
3bda1258 | 15419 | |
3d567e0e | 15420 | if (tg3_10_100_only_device(tp, ent)) |
f07e9af3 | 15421 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; |
1da177e4 LT |
15422 | |
15423 | err = tg3_phy_probe(tp); | |
15424 | if (err) { | |
2445e461 | 15425 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 15426 | /* ... but do not return immediately ... */ |
b02fd9e3 | 15427 | tg3_mdio_fini(tp); |
1da177e4 LT |
15428 | } |
15429 | ||
184b8904 | 15430 | tg3_read_vpd(tp); |
c4e6575c | 15431 | tg3_read_fw_ver(tp); |
1da177e4 | 15432 | |
f07e9af3 MC |
15433 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
15434 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
15435 | } else { |
15436 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 15437 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 15438 | else |
f07e9af3 | 15439 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
15440 | } |
15441 | ||
15442 | /* 5700 {AX,BX} chips have a broken status block link | |
15443 | * change bit implementation, so we must use the | |
15444 | * status register in those cases. | |
15445 | */ | |
15446 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
63c3a66f | 15447 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 | 15448 | else |
63c3a66f | 15449 | tg3_flag_clear(tp, USE_LINKCHG_REG); |
1da177e4 LT |
15450 | |
15451 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
15452 | * have to force the link status polling mechanism based | |
15453 | * upon subsystem IDs. | |
15454 | */ | |
15455 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 15456 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
15457 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
15458 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
63c3a66f | 15459 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 LT |
15460 | } |
15461 | ||
15462 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 15463 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
63c3a66f | 15464 | tg3_flag_set(tp, POLL_SERDES); |
1da177e4 | 15465 | else |
63c3a66f | 15466 | tg3_flag_clear(tp, POLL_SERDES); |
1da177e4 | 15467 | |
9205fd9c | 15468 | tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; |
d2757fc4 | 15469 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 15470 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
63c3a66f | 15471 | tg3_flag(tp, PCIX_MODE)) { |
9205fd9c | 15472 | tp->rx_offset = NET_SKB_PAD; |
d2757fc4 | 15473 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 15474 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
15475 | #endif |
15476 | } | |
1da177e4 | 15477 | |
2c49a44d MC |
15478 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
15479 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
15480 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
15481 | ||
2c49a44d | 15482 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
15483 | |
15484 | /* Increment the rx prod index on the rx std ring by at most | |
15485 | * 8 for these chips to workaround hw errata. | |
15486 | */ | |
15487 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
15488 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
15489 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
15490 | tp->rx_std_max_post = 8; | |
15491 | ||
63c3a66f | 15492 | if (tg3_flag(tp, ASPM_WORKAROUND)) |
8ed5d97e MC |
15493 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & |
15494 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
15495 | ||
1da177e4 LT |
15496 | return err; |
15497 | } | |
15498 | ||
49b6e95f | 15499 | #ifdef CONFIG_SPARC |
229b1ad1 | 15500 | static int tg3_get_macaddr_sparc(struct tg3 *tp) |
1da177e4 LT |
15501 | { |
15502 | struct net_device *dev = tp->dev; | |
15503 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 15504 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 15505 | const unsigned char *addr; |
49b6e95f DM |
15506 | int len; |
15507 | ||
15508 | addr = of_get_property(dp, "local-mac-address", &len); | |
15509 | if (addr && len == 6) { | |
15510 | memcpy(dev->dev_addr, addr, 6); | |
15511 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
15512 | return 0; | |
1da177e4 LT |
15513 | } |
15514 | return -ENODEV; | |
15515 | } | |
15516 | ||
229b1ad1 | 15517 | static int tg3_get_default_macaddr_sparc(struct tg3 *tp) |
1da177e4 LT |
15518 | { |
15519 | struct net_device *dev = tp->dev; | |
15520 | ||
15521 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 15522 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
15523 | return 0; |
15524 | } | |
15525 | #endif | |
15526 | ||
229b1ad1 | 15527 | static int tg3_get_device_address(struct tg3 *tp) |
1da177e4 LT |
15528 | { |
15529 | struct net_device *dev = tp->dev; | |
15530 | u32 hi, lo, mac_offset; | |
008652b3 | 15531 | int addr_ok = 0; |
1da177e4 | 15532 | |
49b6e95f | 15533 | #ifdef CONFIG_SPARC |
1da177e4 LT |
15534 | if (!tg3_get_macaddr_sparc(tp)) |
15535 | return 0; | |
15536 | #endif | |
15537 | ||
15538 | mac_offset = 0x7c; | |
6ff6f81d | 15539 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
63c3a66f | 15540 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 LT |
15541 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
15542 | mac_offset = 0xcc; | |
15543 | if (tg3_nvram_lock(tp)) | |
15544 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
15545 | else | |
15546 | tg3_nvram_unlock(tp); | |
63c3a66f | 15547 | } else if (tg3_flag(tp, 5717_PLUS)) { |
69f11c99 | 15548 | if (tp->pci_fn & 1) |
a1b950d5 | 15549 | mac_offset = 0xcc; |
69f11c99 | 15550 | if (tp->pci_fn > 1) |
a50d0796 | 15551 | mac_offset += 0x18c; |
a1b950d5 | 15552 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 15553 | mac_offset = 0x10; |
1da177e4 LT |
15554 | |
15555 | /* First try to get it from MAC address mailbox. */ | |
15556 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
15557 | if ((hi >> 16) == 0x484b) { | |
15558 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
15559 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
15560 | ||
15561 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
15562 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
15563 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
15564 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
15565 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 15566 | |
008652b3 MC |
15567 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
15568 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
15569 | } | |
15570 | if (!addr_ok) { | |
15571 | /* Next, try NVRAM. */ | |
63c3a66f | 15572 | if (!tg3_flag(tp, NO_NVRAM) && |
df259d8c | 15573 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && |
6d348f2c | 15574 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
15575 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
15576 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
15577 | } |
15578 | /* Finally just fetch it out of the MAC control regs. */ | |
15579 | else { | |
15580 | hi = tr32(MAC_ADDR_0_HIGH); | |
15581 | lo = tr32(MAC_ADDR_0_LOW); | |
15582 | ||
15583 | dev->dev_addr[5] = lo & 0xff; | |
15584 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
15585 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
15586 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
15587 | dev->dev_addr[1] = hi & 0xff; | |
15588 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
15589 | } | |
1da177e4 LT |
15590 | } |
15591 | ||
15592 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 15593 | #ifdef CONFIG_SPARC |
1da177e4 LT |
15594 | if (!tg3_get_default_macaddr_sparc(tp)) |
15595 | return 0; | |
15596 | #endif | |
15597 | return -EINVAL; | |
15598 | } | |
2ff43697 | 15599 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
15600 | return 0; |
15601 | } | |
15602 | ||
59e6b434 DM |
15603 | #define BOUNDARY_SINGLE_CACHELINE 1 |
15604 | #define BOUNDARY_MULTI_CACHELINE 2 | |
15605 | ||
229b1ad1 | 15606 | static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val) |
59e6b434 DM |
15607 | { |
15608 | int cacheline_size; | |
15609 | u8 byte; | |
15610 | int goal; | |
15611 | ||
15612 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
15613 | if (byte == 0) | |
15614 | cacheline_size = 1024; | |
15615 | else | |
15616 | cacheline_size = (int) byte * 4; | |
15617 | ||
15618 | /* On 5703 and later chips, the boundary bits have no | |
15619 | * effect. | |
15620 | */ | |
15621 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
15622 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
63c3a66f | 15623 | !tg3_flag(tp, PCI_EXPRESS)) |
59e6b434 DM |
15624 | goto out; |
15625 | ||
15626 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
15627 | goal = BOUNDARY_MULTI_CACHELINE; | |
15628 | #else | |
15629 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
15630 | goal = BOUNDARY_SINGLE_CACHELINE; | |
15631 | #else | |
15632 | goal = 0; | |
15633 | #endif | |
15634 | #endif | |
15635 | ||
63c3a66f | 15636 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
15637 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
15638 | goto out; | |
15639 | } | |
15640 | ||
59e6b434 DM |
15641 | if (!goal) |
15642 | goto out; | |
15643 | ||
15644 | /* PCI controllers on most RISC systems tend to disconnect | |
15645 | * when a device tries to burst across a cache-line boundary. | |
15646 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
15647 | * | |
15648 | * Unfortunately, for PCI-E there are only limited | |
15649 | * write-side controls for this, and thus for reads | |
15650 | * we will still get the disconnects. We'll also waste | |
15651 | * these PCI cycles for both read and write for chips | |
15652 | * other than 5700 and 5701 which do not implement the | |
15653 | * boundary bits. | |
15654 | */ | |
63c3a66f | 15655 | if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
15656 | switch (cacheline_size) { |
15657 | case 16: | |
15658 | case 32: | |
15659 | case 64: | |
15660 | case 128: | |
15661 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15662 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
15663 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
15664 | } else { | |
15665 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
15666 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
15667 | } | |
15668 | break; | |
15669 | ||
15670 | case 256: | |
15671 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
15672 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
15673 | break; | |
15674 | ||
15675 | default: | |
15676 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
15677 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
15678 | break; | |
855e1111 | 15679 | } |
63c3a66f | 15680 | } else if (tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
15681 | switch (cacheline_size) { |
15682 | case 16: | |
15683 | case 32: | |
15684 | case 64: | |
15685 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15686 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
15687 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
15688 | break; | |
15689 | } | |
15690 | /* fallthrough */ | |
15691 | case 128: | |
15692 | default: | |
15693 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
15694 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
15695 | break; | |
855e1111 | 15696 | } |
59e6b434 DM |
15697 | } else { |
15698 | switch (cacheline_size) { | |
15699 | case 16: | |
15700 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15701 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
15702 | DMA_RWCTRL_WRITE_BNDRY_16); | |
15703 | break; | |
15704 | } | |
15705 | /* fallthrough */ | |
15706 | case 32: | |
15707 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15708 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
15709 | DMA_RWCTRL_WRITE_BNDRY_32); | |
15710 | break; | |
15711 | } | |
15712 | /* fallthrough */ | |
15713 | case 64: | |
15714 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15715 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
15716 | DMA_RWCTRL_WRITE_BNDRY_64); | |
15717 | break; | |
15718 | } | |
15719 | /* fallthrough */ | |
15720 | case 128: | |
15721 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15722 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
15723 | DMA_RWCTRL_WRITE_BNDRY_128); | |
15724 | break; | |
15725 | } | |
15726 | /* fallthrough */ | |
15727 | case 256: | |
15728 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
15729 | DMA_RWCTRL_WRITE_BNDRY_256); | |
15730 | break; | |
15731 | case 512: | |
15732 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
15733 | DMA_RWCTRL_WRITE_BNDRY_512); | |
15734 | break; | |
15735 | case 1024: | |
15736 | default: | |
15737 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
15738 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
15739 | break; | |
855e1111 | 15740 | } |
59e6b434 DM |
15741 | } |
15742 | ||
15743 | out: | |
15744 | return val; | |
15745 | } | |
15746 | ||
229b1ad1 BP |
15747 | static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, |
15748 | int size, int to_device) | |
1da177e4 LT |
15749 | { |
15750 | struct tg3_internal_buffer_desc test_desc; | |
15751 | u32 sram_dma_descs; | |
15752 | int i, ret; | |
15753 | ||
15754 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
15755 | ||
15756 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
15757 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
15758 | tw32(RDMAC_STATUS, 0); | |
15759 | tw32(WDMAC_STATUS, 0); | |
15760 | ||
15761 | tw32(BUFMGR_MODE, 0); | |
15762 | tw32(FTQ_RESET, 0); | |
15763 | ||
15764 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
15765 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
15766 | test_desc.nic_mbuf = 0x00002100; | |
15767 | test_desc.len = size; | |
15768 | ||
15769 | /* | |
15770 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
15771 | * the *second* time the tg3 driver was getting loaded after an | |
15772 | * initial scan. | |
15773 | * | |
15774 | * Broadcom tells me: | |
15775 | * ...the DMA engine is connected to the GRC block and a DMA | |
15776 | * reset may affect the GRC block in some unpredictable way... | |
15777 | * The behavior of resets to individual blocks has not been tested. | |
15778 | * | |
15779 | * Broadcom noted the GRC reset will also reset all sub-components. | |
15780 | */ | |
15781 | if (to_device) { | |
15782 | test_desc.cqid_sqid = (13 << 8) | 2; | |
15783 | ||
15784 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
15785 | udelay(40); | |
15786 | } else { | |
15787 | test_desc.cqid_sqid = (16 << 8) | 7; | |
15788 | ||
15789 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
15790 | udelay(40); | |
15791 | } | |
15792 | test_desc.flags = 0x00000005; | |
15793 | ||
15794 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
15795 | u32 val; | |
15796 | ||
15797 | val = *(((u32 *)&test_desc) + i); | |
15798 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
15799 | sram_dma_descs + (i * sizeof(u32))); | |
15800 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
15801 | } | |
15802 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
15803 | ||
859a5887 | 15804 | if (to_device) |
1da177e4 | 15805 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 15806 | else |
1da177e4 | 15807 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
15808 | |
15809 | ret = -ENODEV; | |
15810 | for (i = 0; i < 40; i++) { | |
15811 | u32 val; | |
15812 | ||
15813 | if (to_device) | |
15814 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
15815 | else | |
15816 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
15817 | if ((val & 0xffff) == sram_dma_descs) { | |
15818 | ret = 0; | |
15819 | break; | |
15820 | } | |
15821 | ||
15822 | udelay(100); | |
15823 | } | |
15824 | ||
15825 | return ret; | |
15826 | } | |
15827 | ||
ded7340d | 15828 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 15829 | |
4143470c | 15830 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
15831 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
15832 | { }, | |
15833 | }; | |
15834 | ||
229b1ad1 | 15835 | static int tg3_test_dma(struct tg3 *tp) |
1da177e4 LT |
15836 | { |
15837 | dma_addr_t buf_dma; | |
59e6b434 | 15838 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 15839 | int ret = 0; |
1da177e4 | 15840 | |
4bae65c8 MC |
15841 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
15842 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
15843 | if (!buf) { |
15844 | ret = -ENOMEM; | |
15845 | goto out_nofree; | |
15846 | } | |
15847 | ||
15848 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
15849 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
15850 | ||
59e6b434 | 15851 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 15852 | |
63c3a66f | 15853 | if (tg3_flag(tp, 57765_PLUS)) |
cbf9ca6c MC |
15854 | goto out; |
15855 | ||
63c3a66f | 15856 | if (tg3_flag(tp, PCI_EXPRESS)) { |
1da177e4 LT |
15857 | /* DMA read watermark not used on PCIE */ |
15858 | tp->dma_rwctrl |= 0x00180000; | |
63c3a66f | 15859 | } else if (!tg3_flag(tp, PCIX_MODE)) { |
85e94ced MC |
15860 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
15861 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
15862 | tp->dma_rwctrl |= 0x003f0000; |
15863 | else | |
15864 | tp->dma_rwctrl |= 0x003f000f; | |
15865 | } else { | |
15866 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
15867 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
15868 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 15869 | u32 read_water = 0x7; |
1da177e4 | 15870 | |
4a29cc2e MC |
15871 | /* If the 5704 is behind the EPB bridge, we can |
15872 | * do the less restrictive ONE_DMA workaround for | |
15873 | * better performance. | |
15874 | */ | |
63c3a66f | 15875 | if (tg3_flag(tp, 40BIT_DMA_BUG) && |
4a29cc2e MC |
15876 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
15877 | tp->dma_rwctrl |= 0x8000; | |
15878 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
15879 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
15880 | ||
49afdeb6 MC |
15881 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
15882 | read_water = 4; | |
59e6b434 | 15883 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
15884 | tp->dma_rwctrl |= |
15885 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
15886 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
15887 | (1 << 23); | |
4cf78e4f MC |
15888 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
15889 | /* 5780 always in PCIX mode */ | |
15890 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
15891 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
15892 | /* 5714 always in PCIX mode */ | |
15893 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
15894 | } else { |
15895 | tp->dma_rwctrl |= 0x001b000f; | |
15896 | } | |
15897 | } | |
15898 | ||
15899 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
15900 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
15901 | tp->dma_rwctrl &= 0xfffffff0; | |
15902 | ||
15903 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
15904 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
15905 | /* Remove this if it causes problems for some boards. */ | |
15906 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
15907 | ||
15908 | /* On 5700/5701 chips, we need to set this bit. | |
15909 | * Otherwise the chip will issue cacheline transactions | |
15910 | * to streamable DMA memory with not all the byte | |
15911 | * enables turned on. This is an error on several | |
15912 | * RISC PCI controllers, in particular sparc64. | |
15913 | * | |
15914 | * On 5703/5704 chips, this bit has been reassigned | |
15915 | * a different meaning. In particular, it is used | |
15916 | * on those chips to enable a PCI-X workaround. | |
15917 | */ | |
15918 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
15919 | } | |
15920 | ||
15921 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15922 | ||
15923 | #if 0 | |
15924 | /* Unneeded, already done by tg3_get_invariants. */ | |
15925 | tg3_switch_clocks(tp); | |
15926 | #endif | |
15927 | ||
1da177e4 LT |
15928 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
15929 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
15930 | goto out; | |
15931 | ||
59e6b434 DM |
15932 | /* It is best to perform DMA test with maximum write burst size |
15933 | * to expose the 5700/5701 write DMA bug. | |
15934 | */ | |
15935 | saved_dma_rwctrl = tp->dma_rwctrl; | |
15936 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
15937 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15938 | ||
1da177e4 LT |
15939 | while (1) { |
15940 | u32 *p = buf, i; | |
15941 | ||
15942 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
15943 | p[i] = i; | |
15944 | ||
15945 | /* Send the buffer to the chip. */ | |
15946 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
15947 | if (ret) { | |
2445e461 MC |
15948 | dev_err(&tp->pdev->dev, |
15949 | "%s: Buffer write failed. err = %d\n", | |
15950 | __func__, ret); | |
1da177e4 LT |
15951 | break; |
15952 | } | |
15953 | ||
15954 | #if 0 | |
15955 | /* validate data reached card RAM correctly. */ | |
15956 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
15957 | u32 val; | |
15958 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
15959 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
15960 | dev_err(&tp->pdev->dev, |
15961 | "%s: Buffer corrupted on device! " | |
15962 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
15963 | /* ret = -ENODEV here? */ |
15964 | } | |
15965 | p[i] = 0; | |
15966 | } | |
15967 | #endif | |
15968 | /* Now read it back. */ | |
15969 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
15970 | if (ret) { | |
5129c3a3 MC |
15971 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
15972 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
15973 | break; |
15974 | } | |
15975 | ||
15976 | /* Verify it. */ | |
15977 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
15978 | if (p[i] == i) | |
15979 | continue; | |
15980 | ||
59e6b434 DM |
15981 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
15982 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
15983 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
15984 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
15985 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15986 | break; | |
15987 | } else { | |
2445e461 MC |
15988 | dev_err(&tp->pdev->dev, |
15989 | "%s: Buffer corrupted on read back! " | |
15990 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
15991 | ret = -ENODEV; |
15992 | goto out; | |
15993 | } | |
15994 | } | |
15995 | ||
15996 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
15997 | /* Success. */ | |
15998 | ret = 0; | |
15999 | break; | |
16000 | } | |
16001 | } | |
59e6b434 DM |
16002 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
16003 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
16004 | /* DMA test passed without adjusting DMA boundary, | |
6d1cfbab MC |
16005 | * now look for chipsets that are known to expose the |
16006 | * DMA bug without failing the test. | |
59e6b434 | 16007 | */ |
4143470c | 16008 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
16009 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
16010 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 16011 | } else { |
6d1cfbab MC |
16012 | /* Safe to use the calculated DMA boundary. */ |
16013 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 16014 | } |
6d1cfbab | 16015 | |
59e6b434 DM |
16016 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
16017 | } | |
1da177e4 LT |
16018 | |
16019 | out: | |
4bae65c8 | 16020 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
16021 | out_nofree: |
16022 | return ret; | |
16023 | } | |
16024 | ||
229b1ad1 | 16025 | static void tg3_init_bufmgr_config(struct tg3 *tp) |
1da177e4 | 16026 | { |
63c3a66f | 16027 | if (tg3_flag(tp, 57765_PLUS)) { |
666bc831 MC |
16028 | tp->bufmgr_config.mbuf_read_dma_low_water = |
16029 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
16030 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
16031 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
16032 | tp->bufmgr_config.mbuf_high_water = | |
16033 | DEFAULT_MB_HIGH_WATER_57765; | |
16034 | ||
16035 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
16036 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
16037 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
16038 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
16039 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
16040 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
63c3a66f | 16041 | } else if (tg3_flag(tp, 5705_PLUS)) { |
fdfec172 MC |
16042 | tp->bufmgr_config.mbuf_read_dma_low_water = |
16043 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
16044 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
16045 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
16046 | tp->bufmgr_config.mbuf_high_water = | |
16047 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
16048 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
16049 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
16050 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
16051 | tp->bufmgr_config.mbuf_high_water = | |
16052 | DEFAULT_MB_HIGH_WATER_5906; | |
16053 | } | |
fdfec172 MC |
16054 | |
16055 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
16056 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
16057 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
16058 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
16059 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
16060 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
16061 | } else { | |
16062 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
16063 | DEFAULT_MB_RDMA_LOW_WATER; | |
16064 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
16065 | DEFAULT_MB_MACRX_LOW_WATER; | |
16066 | tp->bufmgr_config.mbuf_high_water = | |
16067 | DEFAULT_MB_HIGH_WATER; | |
16068 | ||
16069 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
16070 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
16071 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
16072 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
16073 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
16074 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
16075 | } | |
1da177e4 LT |
16076 | |
16077 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
16078 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
16079 | } | |
16080 | ||
229b1ad1 | 16081 | static char *tg3_phy_string(struct tg3 *tp) |
1da177e4 | 16082 | { |
79eb6904 MC |
16083 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
16084 | case TG3_PHY_ID_BCM5400: return "5400"; | |
16085 | case TG3_PHY_ID_BCM5401: return "5401"; | |
16086 | case TG3_PHY_ID_BCM5411: return "5411"; | |
16087 | case TG3_PHY_ID_BCM5701: return "5701"; | |
16088 | case TG3_PHY_ID_BCM5703: return "5703"; | |
16089 | case TG3_PHY_ID_BCM5704: return "5704"; | |
16090 | case TG3_PHY_ID_BCM5705: return "5705"; | |
16091 | case TG3_PHY_ID_BCM5750: return "5750"; | |
16092 | case TG3_PHY_ID_BCM5752: return "5752"; | |
16093 | case TG3_PHY_ID_BCM5714: return "5714"; | |
16094 | case TG3_PHY_ID_BCM5780: return "5780"; | |
16095 | case TG3_PHY_ID_BCM5755: return "5755"; | |
16096 | case TG3_PHY_ID_BCM5787: return "5787"; | |
16097 | case TG3_PHY_ID_BCM5784: return "5784"; | |
16098 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
16099 | case TG3_PHY_ID_BCM5906: return "5906"; | |
16100 | case TG3_PHY_ID_BCM5761: return "5761"; | |
16101 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
16102 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
16103 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 16104 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
6418f2c1 | 16105 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
79eb6904 | 16106 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
16107 | case 0: return "serdes"; |
16108 | default: return "unknown"; | |
855e1111 | 16109 | } |
1da177e4 LT |
16110 | } |
16111 | ||
229b1ad1 | 16112 | static char *tg3_bus_string(struct tg3 *tp, char *str) |
f9804ddb | 16113 | { |
63c3a66f | 16114 | if (tg3_flag(tp, PCI_EXPRESS)) { |
f9804ddb MC |
16115 | strcpy(str, "PCI Express"); |
16116 | return str; | |
63c3a66f | 16117 | } else if (tg3_flag(tp, PCIX_MODE)) { |
f9804ddb MC |
16118 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; |
16119 | ||
16120 | strcpy(str, "PCIX:"); | |
16121 | ||
16122 | if ((clock_ctrl == 7) || | |
16123 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
16124 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
16125 | strcat(str, "133MHz"); | |
16126 | else if (clock_ctrl == 0) | |
16127 | strcat(str, "33MHz"); | |
16128 | else if (clock_ctrl == 2) | |
16129 | strcat(str, "50MHz"); | |
16130 | else if (clock_ctrl == 4) | |
16131 | strcat(str, "66MHz"); | |
16132 | else if (clock_ctrl == 6) | |
16133 | strcat(str, "100MHz"); | |
f9804ddb MC |
16134 | } else { |
16135 | strcpy(str, "PCI:"); | |
63c3a66f | 16136 | if (tg3_flag(tp, PCI_HIGH_SPEED)) |
f9804ddb MC |
16137 | strcat(str, "66MHz"); |
16138 | else | |
16139 | strcat(str, "33MHz"); | |
16140 | } | |
63c3a66f | 16141 | if (tg3_flag(tp, PCI_32BIT)) |
f9804ddb MC |
16142 | strcat(str, ":32-bit"); |
16143 | else | |
16144 | strcat(str, ":64-bit"); | |
16145 | return str; | |
16146 | } | |
16147 | ||
229b1ad1 | 16148 | static void tg3_init_coal(struct tg3 *tp) |
15f9850d DM |
16149 | { |
16150 | struct ethtool_coalesce *ec = &tp->coal; | |
16151 | ||
16152 | memset(ec, 0, sizeof(*ec)); | |
16153 | ec->cmd = ETHTOOL_GCOALESCE; | |
16154 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
16155 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
16156 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
16157 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
16158 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
16159 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
16160 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
16161 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
16162 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
16163 | ||
16164 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
16165 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
16166 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
16167 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
16168 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
16169 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
16170 | } | |
d244c892 | 16171 | |
63c3a66f | 16172 | if (tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
16173 | ec->rx_coalesce_usecs_irq = 0; |
16174 | ec->tx_coalesce_usecs_irq = 0; | |
16175 | ec->stats_block_coalesce_usecs = 0; | |
16176 | } | |
15f9850d DM |
16177 | } |
16178 | ||
229b1ad1 | 16179 | static int tg3_init_one(struct pci_dev *pdev, |
1da177e4 LT |
16180 | const struct pci_device_id *ent) |
16181 | { | |
1da177e4 LT |
16182 | struct net_device *dev; |
16183 | struct tg3 *tp; | |
646c9edd MC |
16184 | int i, err, pm_cap; |
16185 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 16186 | char str[40]; |
72f2afb8 | 16187 | u64 dma_mask, persist_dma_mask; |
c8f44aff | 16188 | netdev_features_t features = 0; |
1da177e4 | 16189 | |
05dbe005 | 16190 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
16191 | |
16192 | err = pci_enable_device(pdev); | |
16193 | if (err) { | |
2445e461 | 16194 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
16195 | return err; |
16196 | } | |
16197 | ||
1da177e4 LT |
16198 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
16199 | if (err) { | |
2445e461 | 16200 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
16201 | goto err_out_disable_pdev; |
16202 | } | |
16203 | ||
16204 | pci_set_master(pdev); | |
16205 | ||
16206 | /* Find power-management capability. */ | |
16207 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
16208 | if (pm_cap == 0) { | |
2445e461 MC |
16209 | dev_err(&pdev->dev, |
16210 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
16211 | err = -EIO; |
16212 | goto err_out_free_res; | |
16213 | } | |
16214 | ||
16821285 MC |
16215 | err = pci_set_power_state(pdev, PCI_D0); |
16216 | if (err) { | |
16217 | dev_err(&pdev->dev, "Transition to D0 failed, aborting\n"); | |
16218 | goto err_out_free_res; | |
16219 | } | |
16220 | ||
fe5f5787 | 16221 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 16222 | if (!dev) { |
1da177e4 | 16223 | err = -ENOMEM; |
16821285 | 16224 | goto err_out_power_down; |
1da177e4 LT |
16225 | } |
16226 | ||
1da177e4 LT |
16227 | SET_NETDEV_DEV(dev, &pdev->dev); |
16228 | ||
1da177e4 LT |
16229 | tp = netdev_priv(dev); |
16230 | tp->pdev = pdev; | |
16231 | tp->dev = dev; | |
16232 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
16233 | tp->rx_mode = TG3_DEF_RX_MODE; |
16234 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 16235 | |
1da177e4 LT |
16236 | if (tg3_debug > 0) |
16237 | tp->msg_enable = tg3_debug; | |
16238 | else | |
16239 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
16240 | ||
16241 | /* The word/byte swap controls here control register access byte | |
16242 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
16243 | * setting below. | |
16244 | */ | |
16245 | tp->misc_host_ctrl = | |
16246 | MISC_HOST_CTRL_MASK_PCI_INT | | |
16247 | MISC_HOST_CTRL_WORD_SWAP | | |
16248 | MISC_HOST_CTRL_INDIR_ACCESS | | |
16249 | MISC_HOST_CTRL_PCISTATE_RW; | |
16250 | ||
16251 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
16252 | * on descriptor entries, anything which isn't packet data. | |
16253 | * | |
16254 | * The StrongARM chips on the board (one for tx, one for rx) | |
16255 | * are running in big-endian mode. | |
16256 | */ | |
16257 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
16258 | GRC_MODE_WSWAP_NONFRM_DATA); | |
16259 | #ifdef __BIG_ENDIAN | |
16260 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
16261 | #endif | |
16262 | spin_lock_init(&tp->lock); | |
1da177e4 | 16263 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 16264 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 16265 | |
d5fe488a | 16266 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 16267 | if (!tp->regs) { |
ab96b241 | 16268 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
16269 | err = -ENOMEM; |
16270 | goto err_out_free_dev; | |
16271 | } | |
16272 | ||
c9cab24e MC |
16273 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
16274 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || | |
16275 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || | |
16276 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || | |
16277 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
79d49695 | 16278 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || |
c9cab24e MC |
16279 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || |
16280 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
16281 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) { | |
16282 | tg3_flag_set(tp, ENABLE_APE); | |
16283 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
16284 | if (!tp->aperegs) { | |
16285 | dev_err(&pdev->dev, | |
16286 | "Cannot map APE registers, aborting\n"); | |
16287 | err = -ENOMEM; | |
16288 | goto err_out_iounmap; | |
16289 | } | |
16290 | } | |
16291 | ||
1da177e4 LT |
16292 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
16293 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 16294 | |
1da177e4 | 16295 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 16296 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
2ffcc981 | 16297 | dev->netdev_ops = &tg3_netdev_ops; |
1da177e4 | 16298 | dev->irq = pdev->irq; |
1da177e4 | 16299 | |
3d567e0e | 16300 | err = tg3_get_invariants(tp, ent); |
1da177e4 | 16301 | if (err) { |
ab96b241 MC |
16302 | dev_err(&pdev->dev, |
16303 | "Problem fetching invariants of chip, aborting\n"); | |
c9cab24e | 16304 | goto err_out_apeunmap; |
1da177e4 LT |
16305 | } |
16306 | ||
4a29cc2e MC |
16307 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
16308 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
16309 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
16310 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
16311 | * do DMA address check in tg3_start_xmit(). | |
16312 | */ | |
63c3a66f | 16313 | if (tg3_flag(tp, IS_5788)) |
284901a9 | 16314 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
63c3a66f | 16315 | else if (tg3_flag(tp, 40BIT_DMA_BUG)) { |
50cf156a | 16316 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 16317 | #ifdef CONFIG_HIGHMEM |
6a35528a | 16318 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 16319 | #endif |
4a29cc2e | 16320 | } else |
6a35528a | 16321 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
16322 | |
16323 | /* Configure DMA attributes. */ | |
284901a9 | 16324 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
16325 | err = pci_set_dma_mask(pdev, dma_mask); |
16326 | if (!err) { | |
0da0606f | 16327 | features |= NETIF_F_HIGHDMA; |
72f2afb8 MC |
16328 | err = pci_set_consistent_dma_mask(pdev, |
16329 | persist_dma_mask); | |
16330 | if (err < 0) { | |
ab96b241 MC |
16331 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
16332 | "DMA for consistent allocations\n"); | |
c9cab24e | 16333 | goto err_out_apeunmap; |
72f2afb8 MC |
16334 | } |
16335 | } | |
16336 | } | |
284901a9 YH |
16337 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
16338 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 16339 | if (err) { |
ab96b241 MC |
16340 | dev_err(&pdev->dev, |
16341 | "No usable DMA configuration, aborting\n"); | |
c9cab24e | 16342 | goto err_out_apeunmap; |
72f2afb8 MC |
16343 | } |
16344 | } | |
16345 | ||
fdfec172 | 16346 | tg3_init_bufmgr_config(tp); |
1da177e4 | 16347 | |
0da0606f MC |
16348 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
16349 | ||
16350 | /* 5700 B0 chips do not support checksumming correctly due | |
16351 | * to hardware bugs. | |
16352 | */ | |
16353 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { | |
16354 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
16355 | ||
16356 | if (tg3_flag(tp, 5755_PLUS)) | |
16357 | features |= NETIF_F_IPV6_CSUM; | |
16358 | } | |
16359 | ||
4e3a7aaa MC |
16360 | /* TSO is on by default on chips that support hardware TSO. |
16361 | * Firmware TSO on older chips gives lower performance, so it | |
16362 | * is off by default, but can be enabled using ethtool. | |
16363 | */ | |
63c3a66f JP |
16364 | if ((tg3_flag(tp, HW_TSO_1) || |
16365 | tg3_flag(tp, HW_TSO_2) || | |
16366 | tg3_flag(tp, HW_TSO_3)) && | |
0da0606f MC |
16367 | (features & NETIF_F_IP_CSUM)) |
16368 | features |= NETIF_F_TSO; | |
63c3a66f | 16369 | if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { |
0da0606f MC |
16370 | if (features & NETIF_F_IPV6_CSUM) |
16371 | features |= NETIF_F_TSO6; | |
63c3a66f | 16372 | if (tg3_flag(tp, HW_TSO_3) || |
e849cdc3 | 16373 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c MC |
16374 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
16375 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
63c3a66f | 16376 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
dc668910 | 16377 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
0da0606f | 16378 | features |= NETIF_F_TSO_ECN; |
b0026624 | 16379 | } |
1da177e4 | 16380 | |
d542fe27 MC |
16381 | dev->features |= features; |
16382 | dev->vlan_features |= features; | |
16383 | ||
06c03c02 MB |
16384 | /* |
16385 | * Add loopback capability only for a subset of devices that support | |
16386 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY | |
16387 | * loopback for the remaining devices. | |
16388 | */ | |
16389 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
16390 | !tg3_flag(tp, CPMU_PRESENT)) | |
16391 | /* Add the loopback capability */ | |
0da0606f MC |
16392 | features |= NETIF_F_LOOPBACK; |
16393 | ||
0da0606f | 16394 | dev->hw_features |= features; |
06c03c02 | 16395 | |
1da177e4 | 16396 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
63c3a66f | 16397 | !tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 | 16398 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { |
63c3a66f | 16399 | tg3_flag_set(tp, MAX_RXPEND_64); |
1da177e4 LT |
16400 | tp->rx_pending = 63; |
16401 | } | |
16402 | ||
1da177e4 LT |
16403 | err = tg3_get_device_address(tp); |
16404 | if (err) { | |
ab96b241 MC |
16405 | dev_err(&pdev->dev, |
16406 | "Could not obtain valid ethernet address, aborting\n"); | |
c9cab24e | 16407 | goto err_out_apeunmap; |
c88864df MC |
16408 | } |
16409 | ||
1da177e4 LT |
16410 | /* |
16411 | * Reset chip in case UNDI or EFI driver did not shutdown | |
16412 | * DMA self test will enable WDMAC and we'll see (spurious) | |
16413 | * pending DMA on the PCI bus at that point. | |
16414 | */ | |
16415 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
16416 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 16417 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 16418 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
16419 | } |
16420 | ||
16421 | err = tg3_test_dma(tp); | |
16422 | if (err) { | |
ab96b241 | 16423 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 16424 | goto err_out_apeunmap; |
1da177e4 LT |
16425 | } |
16426 | ||
78f90dcf MC |
16427 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
16428 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
16429 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 16430 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
16431 | struct tg3_napi *tnapi = &tp->napi[i]; |
16432 | ||
16433 | tnapi->tp = tp; | |
16434 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
16435 | ||
16436 | tnapi->int_mbox = intmbx; | |
93a700a9 | 16437 | if (i <= 4) |
78f90dcf MC |
16438 | intmbx += 0x8; |
16439 | else | |
16440 | intmbx += 0x4; | |
16441 | ||
16442 | tnapi->consmbox = rcvmbx; | |
16443 | tnapi->prodmbox = sndmbx; | |
16444 | ||
66cfd1bd | 16445 | if (i) |
78f90dcf | 16446 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 16447 | else |
78f90dcf | 16448 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf | 16449 | |
63c3a66f | 16450 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
78f90dcf MC |
16451 | break; |
16452 | ||
16453 | /* | |
16454 | * If we support MSIX, we'll be using RSS. If we're using | |
16455 | * RSS, the first vector only handles link interrupts and the | |
16456 | * remaining vectors handle rx and tx interrupts. Reuse the | |
16457 | * mailbox values for the next iteration. The values we setup | |
16458 | * above are still useful for the single vectored mode. | |
16459 | */ | |
16460 | if (!i) | |
16461 | continue; | |
16462 | ||
16463 | rcvmbx += 0x8; | |
16464 | ||
16465 | if (sndmbx & 0x4) | |
16466 | sndmbx -= 0x4; | |
16467 | else | |
16468 | sndmbx += 0xc; | |
16469 | } | |
16470 | ||
15f9850d DM |
16471 | tg3_init_coal(tp); |
16472 | ||
c49a1561 MC |
16473 | pci_set_drvdata(pdev, dev); |
16474 | ||
cd0d7228 MC |
16475 | if (tg3_flag(tp, 5717_PLUS)) { |
16476 | /* Resume a low-power mode */ | |
16477 | tg3_frob_aux_power(tp, false); | |
16478 | } | |
16479 | ||
21f7638e MC |
16480 | tg3_timer_init(tp); |
16481 | ||
1da177e4 LT |
16482 | err = register_netdev(dev); |
16483 | if (err) { | |
ab96b241 | 16484 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 16485 | goto err_out_apeunmap; |
1da177e4 LT |
16486 | } |
16487 | ||
05dbe005 JP |
16488 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
16489 | tp->board_part_number, | |
16490 | tp->pci_chip_rev_id, | |
16491 | tg3_bus_string(tp, str), | |
16492 | dev->dev_addr); | |
1da177e4 | 16493 | |
f07e9af3 | 16494 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
16495 | struct phy_device *phydev; |
16496 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
16497 | netdev_info(dev, |
16498 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 16499 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
16500 | } else { |
16501 | char *ethtype; | |
16502 | ||
16503 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
16504 | ethtype = "10/100Base-TX"; | |
16505 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
16506 | ethtype = "1000Base-SX"; | |
16507 | else | |
16508 | ethtype = "10/100/1000Base-T"; | |
16509 | ||
5129c3a3 | 16510 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
47007831 MC |
16511 | "(WireSpeed[%d], EEE[%d])\n", |
16512 | tg3_phy_string(tp), ethtype, | |
16513 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, | |
16514 | (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); | |
f07e9af3 | 16515 | } |
05dbe005 JP |
16516 | |
16517 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
dc668910 | 16518 | (dev->features & NETIF_F_RXCSUM) != 0, |
63c3a66f | 16519 | tg3_flag(tp, USE_LINKCHG_REG) != 0, |
f07e9af3 | 16520 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
63c3a66f JP |
16521 | tg3_flag(tp, ENABLE_ASF) != 0, |
16522 | tg3_flag(tp, TSO_CAPABLE) != 0); | |
05dbe005 JP |
16523 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
16524 | tp->dma_rwctrl, | |
16525 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
16526 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 | 16527 | |
b45aa2f6 MC |
16528 | pci_save_state(pdev); |
16529 | ||
1da177e4 LT |
16530 | return 0; |
16531 | ||
0d3031d9 MC |
16532 | err_out_apeunmap: |
16533 | if (tp->aperegs) { | |
16534 | iounmap(tp->aperegs); | |
16535 | tp->aperegs = NULL; | |
16536 | } | |
16537 | ||
1da177e4 | 16538 | err_out_iounmap: |
6892914f MC |
16539 | if (tp->regs) { |
16540 | iounmap(tp->regs); | |
22abe310 | 16541 | tp->regs = NULL; |
6892914f | 16542 | } |
1da177e4 LT |
16543 | |
16544 | err_out_free_dev: | |
16545 | free_netdev(dev); | |
16546 | ||
16821285 MC |
16547 | err_out_power_down: |
16548 | pci_set_power_state(pdev, PCI_D3hot); | |
16549 | ||
1da177e4 LT |
16550 | err_out_free_res: |
16551 | pci_release_regions(pdev); | |
16552 | ||
16553 | err_out_disable_pdev: | |
16554 | pci_disable_device(pdev); | |
16555 | pci_set_drvdata(pdev, NULL); | |
16556 | return err; | |
16557 | } | |
16558 | ||
229b1ad1 | 16559 | static void tg3_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
16560 | { |
16561 | struct net_device *dev = pci_get_drvdata(pdev); | |
16562 | ||
16563 | if (dev) { | |
16564 | struct tg3 *tp = netdev_priv(dev); | |
16565 | ||
e3c5530b | 16566 | release_firmware(tp->fw); |
077f849d | 16567 | |
db219973 | 16568 | tg3_reset_task_cancel(tp); |
158d7abd | 16569 | |
e730c823 | 16570 | if (tg3_flag(tp, USE_PHYLIB)) { |
b02fd9e3 | 16571 | tg3_phy_fini(tp); |
158d7abd | 16572 | tg3_mdio_fini(tp); |
b02fd9e3 | 16573 | } |
158d7abd | 16574 | |
1da177e4 | 16575 | unregister_netdev(dev); |
0d3031d9 MC |
16576 | if (tp->aperegs) { |
16577 | iounmap(tp->aperegs); | |
16578 | tp->aperegs = NULL; | |
16579 | } | |
6892914f MC |
16580 | if (tp->regs) { |
16581 | iounmap(tp->regs); | |
22abe310 | 16582 | tp->regs = NULL; |
6892914f | 16583 | } |
1da177e4 LT |
16584 | free_netdev(dev); |
16585 | pci_release_regions(pdev); | |
16586 | pci_disable_device(pdev); | |
16587 | pci_set_drvdata(pdev, NULL); | |
16588 | } | |
16589 | } | |
16590 | ||
aa6027ca | 16591 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 16592 | static int tg3_suspend(struct device *device) |
1da177e4 | 16593 | { |
c866b7ea | 16594 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
16595 | struct net_device *dev = pci_get_drvdata(pdev); |
16596 | struct tg3 *tp = netdev_priv(dev); | |
16597 | int err; | |
16598 | ||
16599 | if (!netif_running(dev)) | |
16600 | return 0; | |
16601 | ||
db219973 | 16602 | tg3_reset_task_cancel(tp); |
b02fd9e3 | 16603 | tg3_phy_stop(tp); |
1da177e4 LT |
16604 | tg3_netif_stop(tp); |
16605 | ||
21f7638e | 16606 | tg3_timer_stop(tp); |
1da177e4 | 16607 | |
f47c11ee | 16608 | tg3_full_lock(tp, 1); |
1da177e4 | 16609 | tg3_disable_ints(tp); |
f47c11ee | 16610 | tg3_full_unlock(tp); |
1da177e4 LT |
16611 | |
16612 | netif_device_detach(dev); | |
16613 | ||
f47c11ee | 16614 | tg3_full_lock(tp, 0); |
944d980e | 16615 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
63c3a66f | 16616 | tg3_flag_clear(tp, INIT_COMPLETE); |
f47c11ee | 16617 | tg3_full_unlock(tp); |
1da177e4 | 16618 | |
c866b7ea | 16619 | err = tg3_power_down_prepare(tp); |
1da177e4 | 16620 | if (err) { |
b02fd9e3 MC |
16621 | int err2; |
16622 | ||
f47c11ee | 16623 | tg3_full_lock(tp, 0); |
1da177e4 | 16624 | |
63c3a66f | 16625 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
16626 | err2 = tg3_restart_hw(tp, 1); |
16627 | if (err2) | |
b9ec6c1b | 16628 | goto out; |
1da177e4 | 16629 | |
21f7638e | 16630 | tg3_timer_start(tp); |
1da177e4 LT |
16631 | |
16632 | netif_device_attach(dev); | |
16633 | tg3_netif_start(tp); | |
16634 | ||
b9ec6c1b | 16635 | out: |
f47c11ee | 16636 | tg3_full_unlock(tp); |
b02fd9e3 MC |
16637 | |
16638 | if (!err2) | |
16639 | tg3_phy_start(tp); | |
1da177e4 LT |
16640 | } |
16641 | ||
16642 | return err; | |
16643 | } | |
16644 | ||
c866b7ea | 16645 | static int tg3_resume(struct device *device) |
1da177e4 | 16646 | { |
c866b7ea | 16647 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
16648 | struct net_device *dev = pci_get_drvdata(pdev); |
16649 | struct tg3 *tp = netdev_priv(dev); | |
16650 | int err; | |
16651 | ||
16652 | if (!netif_running(dev)) | |
16653 | return 0; | |
16654 | ||
1da177e4 LT |
16655 | netif_device_attach(dev); |
16656 | ||
f47c11ee | 16657 | tg3_full_lock(tp, 0); |
1da177e4 | 16658 | |
63c3a66f | 16659 | tg3_flag_set(tp, INIT_COMPLETE); |
b9ec6c1b MC |
16660 | err = tg3_restart_hw(tp, 1); |
16661 | if (err) | |
16662 | goto out; | |
1da177e4 | 16663 | |
21f7638e | 16664 | tg3_timer_start(tp); |
1da177e4 | 16665 | |
1da177e4 LT |
16666 | tg3_netif_start(tp); |
16667 | ||
b9ec6c1b | 16668 | out: |
f47c11ee | 16669 | tg3_full_unlock(tp); |
1da177e4 | 16670 | |
b02fd9e3 MC |
16671 | if (!err) |
16672 | tg3_phy_start(tp); | |
16673 | ||
b9ec6c1b | 16674 | return err; |
1da177e4 LT |
16675 | } |
16676 | ||
c866b7ea | 16677 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
16678 | #define TG3_PM_OPS (&tg3_pm_ops) |
16679 | ||
16680 | #else | |
16681 | ||
16682 | #define TG3_PM_OPS NULL | |
16683 | ||
16684 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 16685 | |
b45aa2f6 MC |
16686 | /** |
16687 | * tg3_io_error_detected - called when PCI error is detected | |
16688 | * @pdev: Pointer to PCI device | |
16689 | * @state: The current pci connection state | |
16690 | * | |
16691 | * This function is called after a PCI bus error affecting | |
16692 | * this device has been detected. | |
16693 | */ | |
16694 | static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |
16695 | pci_channel_state_t state) | |
16696 | { | |
16697 | struct net_device *netdev = pci_get_drvdata(pdev); | |
16698 | struct tg3 *tp = netdev_priv(netdev); | |
16699 | pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET; | |
16700 | ||
16701 | netdev_info(netdev, "PCI I/O error detected\n"); | |
16702 | ||
16703 | rtnl_lock(); | |
16704 | ||
16705 | if (!netif_running(netdev)) | |
16706 | goto done; | |
16707 | ||
16708 | tg3_phy_stop(tp); | |
16709 | ||
16710 | tg3_netif_stop(tp); | |
16711 | ||
21f7638e | 16712 | tg3_timer_stop(tp); |
b45aa2f6 MC |
16713 | |
16714 | /* Want to make sure that the reset task doesn't run */ | |
db219973 | 16715 | tg3_reset_task_cancel(tp); |
b45aa2f6 MC |
16716 | |
16717 | netif_device_detach(netdev); | |
16718 | ||
16719 | /* Clean up software state, even if MMIO is blocked */ | |
16720 | tg3_full_lock(tp, 0); | |
16721 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
16722 | tg3_full_unlock(tp); | |
16723 | ||
16724 | done: | |
16725 | if (state == pci_channel_io_perm_failure) | |
16726 | err = PCI_ERS_RESULT_DISCONNECT; | |
16727 | else | |
16728 | pci_disable_device(pdev); | |
16729 | ||
16730 | rtnl_unlock(); | |
16731 | ||
16732 | return err; | |
16733 | } | |
16734 | ||
16735 | /** | |
16736 | * tg3_io_slot_reset - called after the pci bus has been reset. | |
16737 | * @pdev: Pointer to PCI device | |
16738 | * | |
16739 | * Restart the card from scratch, as if from a cold-boot. | |
16740 | * At this point, the card has exprienced a hard reset, | |
16741 | * followed by fixups by BIOS, and has its config space | |
16742 | * set up identically to what it was at cold boot. | |
16743 | */ | |
16744 | static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) | |
16745 | { | |
16746 | struct net_device *netdev = pci_get_drvdata(pdev); | |
16747 | struct tg3 *tp = netdev_priv(netdev); | |
16748 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; | |
16749 | int err; | |
16750 | ||
16751 | rtnl_lock(); | |
16752 | ||
16753 | if (pci_enable_device(pdev)) { | |
16754 | netdev_err(netdev, "Cannot re-enable PCI device after reset.\n"); | |
16755 | goto done; | |
16756 | } | |
16757 | ||
16758 | pci_set_master(pdev); | |
16759 | pci_restore_state(pdev); | |
16760 | pci_save_state(pdev); | |
16761 | ||
16762 | if (!netif_running(netdev)) { | |
16763 | rc = PCI_ERS_RESULT_RECOVERED; | |
16764 | goto done; | |
16765 | } | |
16766 | ||
16767 | err = tg3_power_up(tp); | |
bed9829f | 16768 | if (err) |
b45aa2f6 | 16769 | goto done; |
b45aa2f6 MC |
16770 | |
16771 | rc = PCI_ERS_RESULT_RECOVERED; | |
16772 | ||
16773 | done: | |
16774 | rtnl_unlock(); | |
16775 | ||
16776 | return rc; | |
16777 | } | |
16778 | ||
16779 | /** | |
16780 | * tg3_io_resume - called when traffic can start flowing again. | |
16781 | * @pdev: Pointer to PCI device | |
16782 | * | |
16783 | * This callback is called when the error recovery driver tells | |
16784 | * us that its OK to resume normal operation. | |
16785 | */ | |
16786 | static void tg3_io_resume(struct pci_dev *pdev) | |
16787 | { | |
16788 | struct net_device *netdev = pci_get_drvdata(pdev); | |
16789 | struct tg3 *tp = netdev_priv(netdev); | |
16790 | int err; | |
16791 | ||
16792 | rtnl_lock(); | |
16793 | ||
16794 | if (!netif_running(netdev)) | |
16795 | goto done; | |
16796 | ||
16797 | tg3_full_lock(tp, 0); | |
63c3a66f | 16798 | tg3_flag_set(tp, INIT_COMPLETE); |
b45aa2f6 | 16799 | err = tg3_restart_hw(tp, 1); |
b45aa2f6 | 16800 | if (err) { |
35763066 | 16801 | tg3_full_unlock(tp); |
b45aa2f6 MC |
16802 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); |
16803 | goto done; | |
16804 | } | |
16805 | ||
16806 | netif_device_attach(netdev); | |
16807 | ||
21f7638e | 16808 | tg3_timer_start(tp); |
b45aa2f6 MC |
16809 | |
16810 | tg3_netif_start(tp); | |
16811 | ||
35763066 NNS |
16812 | tg3_full_unlock(tp); |
16813 | ||
b45aa2f6 MC |
16814 | tg3_phy_start(tp); |
16815 | ||
16816 | done: | |
16817 | rtnl_unlock(); | |
16818 | } | |
16819 | ||
3646f0e5 | 16820 | static const struct pci_error_handlers tg3_err_handler = { |
b45aa2f6 MC |
16821 | .error_detected = tg3_io_error_detected, |
16822 | .slot_reset = tg3_io_slot_reset, | |
16823 | .resume = tg3_io_resume | |
16824 | }; | |
16825 | ||
1da177e4 LT |
16826 | static struct pci_driver tg3_driver = { |
16827 | .name = DRV_MODULE_NAME, | |
16828 | .id_table = tg3_pci_tbl, | |
16829 | .probe = tg3_init_one, | |
229b1ad1 | 16830 | .remove = tg3_remove_one, |
b45aa2f6 | 16831 | .err_handler = &tg3_err_handler, |
aa6027ca | 16832 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
16833 | }; |
16834 | ||
16835 | static int __init tg3_init(void) | |
16836 | { | |
29917620 | 16837 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
16838 | } |
16839 | ||
16840 | static void __exit tg3_cleanup(void) | |
16841 | { | |
16842 | pci_unregister_driver(&tg3_driver); | |
16843 | } | |
16844 | ||
16845 | module_init(tg3_init); | |
16846 | module_exit(tg3_cleanup); |