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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
9e056c03 | 7 | * Copyright (C) 2005-2012 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 | 28 | #include <linux/init.h> |
a6b7a407 | 29 | #include <linux/interrupt.h> |
1da177e4 LT |
30 | #include <linux/ioport.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/ethtool.h> | |
3110f5f5 | 36 | #include <linux/mdio.h> |
1da177e4 | 37 | #include <linux/mii.h> |
158d7abd | 38 | #include <linux/phy.h> |
a9daf367 | 39 | #include <linux/brcmphy.h> |
1da177e4 LT |
40 | #include <linux/if_vlan.h> |
41 | #include <linux/ip.h> | |
42 | #include <linux/tcp.h> | |
43 | #include <linux/workqueue.h> | |
61487480 | 44 | #include <linux/prefetch.h> |
f9a5f7d3 | 45 | #include <linux/dma-mapping.h> |
077f849d | 46 | #include <linux/firmware.h> |
1da177e4 LT |
47 | |
48 | #include <net/checksum.h> | |
c9bdd4b5 | 49 | #include <net/ip.h> |
1da177e4 | 50 | |
27fd9de8 | 51 | #include <linux/io.h> |
1da177e4 | 52 | #include <asm/byteorder.h> |
27fd9de8 | 53 | #include <linux/uaccess.h> |
1da177e4 | 54 | |
49b6e95f | 55 | #ifdef CONFIG_SPARC |
1da177e4 | 56 | #include <asm/idprom.h> |
49b6e95f | 57 | #include <asm/prom.h> |
1da177e4 LT |
58 | #endif |
59 | ||
63532394 MC |
60 | #define BAR_0 0 |
61 | #define BAR_2 2 | |
62 | ||
1da177e4 LT |
63 | #include "tg3.h" |
64 | ||
63c3a66f JP |
65 | /* Functions & macros to verify TG3_FLAGS types */ |
66 | ||
67 | static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) | |
68 | { | |
69 | return test_bit(flag, bits); | |
70 | } | |
71 | ||
72 | static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) | |
73 | { | |
74 | set_bit(flag, bits); | |
75 | } | |
76 | ||
77 | static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) | |
78 | { | |
79 | clear_bit(flag, bits); | |
80 | } | |
81 | ||
82 | #define tg3_flag(tp, flag) \ | |
83 | _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) | |
84 | #define tg3_flag_set(tp, flag) \ | |
85 | _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) | |
86 | #define tg3_flag_clear(tp, flag) \ | |
87 | _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) | |
88 | ||
1da177e4 | 89 | #define DRV_MODULE_NAME "tg3" |
6867c843 | 90 | #define TG3_MAJ_NUM 3 |
7ae52890 | 91 | #define TG3_MIN_NUM 123 |
6867c843 MC |
92 | #define DRV_MODULE_VERSION \ |
93 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
7ae52890 | 94 | #define DRV_MODULE_RELDATE "March 21, 2012" |
1da177e4 | 95 | |
fd6d3f0e MC |
96 | #define RESET_KIND_SHUTDOWN 0 |
97 | #define RESET_KIND_INIT 1 | |
98 | #define RESET_KIND_SUSPEND 2 | |
99 | ||
1da177e4 LT |
100 | #define TG3_DEF_RX_MODE 0 |
101 | #define TG3_DEF_TX_MODE 0 | |
102 | #define TG3_DEF_MSG_ENABLE \ | |
103 | (NETIF_MSG_DRV | \ | |
104 | NETIF_MSG_PROBE | \ | |
105 | NETIF_MSG_LINK | \ | |
106 | NETIF_MSG_TIMER | \ | |
107 | NETIF_MSG_IFDOWN | \ | |
108 | NETIF_MSG_IFUP | \ | |
109 | NETIF_MSG_RX_ERR | \ | |
110 | NETIF_MSG_TX_ERR) | |
111 | ||
520b2756 MC |
112 | #define TG3_GRC_LCLCTL_PWRSW_DELAY 100 |
113 | ||
1da177e4 LT |
114 | /* length of time before we decide the hardware is borked, |
115 | * and dev->tx_timeout() should be called to fix the problem | |
116 | */ | |
63c3a66f | 117 | |
1da177e4 LT |
118 | #define TG3_TX_TIMEOUT (5 * HZ) |
119 | ||
120 | /* hardware minimum and maximum for a single frame's data payload */ | |
121 | #define TG3_MIN_MTU 60 | |
122 | #define TG3_MAX_MTU(tp) \ | |
63c3a66f | 123 | (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
124 | |
125 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
126 | * You can't change the ring sizes, but you can change where you place | |
127 | * them in the NIC onboard memory. | |
128 | */ | |
7cb32cf2 | 129 | #define TG3_RX_STD_RING_SIZE(tp) \ |
63c3a66f | 130 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 131 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) |
1da177e4 | 132 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 133 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
63c3a66f | 134 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 135 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) |
1da177e4 LT |
136 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
137 | ||
138 | /* Do not place this n-ring entries value into the tp struct itself, | |
139 | * we really want to expose these constants to GCC so that modulo et | |
140 | * al. operations are done with shifts and masks instead of with | |
141 | * hw multiply/modulo instructions. Another solution would be to | |
142 | * replace things like '% foo' with '& (foo - 1)'. | |
143 | */ | |
1da177e4 LT |
144 | |
145 | #define TG3_TX_RING_SIZE 512 | |
146 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
147 | ||
2c49a44d MC |
148 | #define TG3_RX_STD_RING_BYTES(tp) \ |
149 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
150 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
151 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
152 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 153 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
154 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
155 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
156 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
157 | ||
287be12e MC |
158 | #define TG3_DMA_BYTE_ENAB 64 |
159 | ||
160 | #define TG3_RX_STD_DMA_SZ 1536 | |
161 | #define TG3_RX_JMB_DMA_SZ 9046 | |
162 | ||
163 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
164 | ||
165 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
166 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 167 | |
2c49a44d MC |
168 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
169 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 170 | |
2c49a44d MC |
171 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
172 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 173 | |
d2757fc4 MC |
174 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
175 | * that are at least dword aligned when used in PCIX mode. The driver | |
176 | * works around this bug by double copying the packet. This workaround | |
177 | * is built into the normal double copy length check for efficiency. | |
178 | * | |
179 | * However, the double copy is only necessary on those architectures | |
180 | * where unaligned memory accesses are inefficient. For those architectures | |
181 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
182 | * the 5701 in the normal rx path. Doing so saves a device structure | |
183 | * dereference by hardcoding the double copy threshold in place. | |
184 | */ | |
185 | #define TG3_RX_COPY_THRESHOLD 256 | |
186 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
187 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
188 | #else | |
189 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
190 | #endif | |
191 | ||
81389f57 MC |
192 | #if (NET_IP_ALIGN != 0) |
193 | #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) | |
194 | #else | |
9205fd9c | 195 | #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) |
81389f57 MC |
196 | #endif |
197 | ||
1da177e4 | 198 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 199 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
55086ad9 | 200 | #define TG3_TX_BD_DMA_MAX_2K 2048 |
a4cb428d | 201 | #define TG3_TX_BD_DMA_MAX_4K 4096 |
1da177e4 | 202 | |
ad829268 MC |
203 | #define TG3_RAW_IP_ALIGN 2 |
204 | ||
c6cdf436 | 205 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
21f7638e | 206 | #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2) |
c6cdf436 | 207 | |
077f849d JSR |
208 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
209 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
210 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
211 | ||
1da177e4 | 212 | static char version[] __devinitdata = |
05dbe005 | 213 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
214 | |
215 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
216 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
217 | MODULE_LICENSE("GPL"); | |
218 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
219 | MODULE_FIRMWARE(FIRMWARE_TG3); |
220 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
221 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
222 | ||
1da177e4 LT |
223 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
224 | module_param(tg3_debug, int, 0); | |
225 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
226 | ||
a3aa1884 | 227 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
13185217 | 250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 HK |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
269 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
272 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
275 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
276 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
277 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
278 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
279 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 280 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
281 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
282 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
283 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
284 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
285 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
286 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
287 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
288 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
289 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 290 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
291 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
292 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
b0f75221 MC |
293 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
294 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
295 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
296 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
297 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
298 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
302b500b | 299 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
ba1f3c76 | 300 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
13185217 HK |
301 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
302 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
303 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
304 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
305 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
306 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
307 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
1dcb14d9 | 308 | {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */ |
13185217 | 309 | {} |
1da177e4 LT |
310 | }; |
311 | ||
312 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
313 | ||
50da859d | 314 | static const struct { |
1da177e4 | 315 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 316 | } ethtool_stats_keys[] = { |
1da177e4 LT |
317 | { "rx_octets" }, |
318 | { "rx_fragments" }, | |
319 | { "rx_ucast_packets" }, | |
320 | { "rx_mcast_packets" }, | |
321 | { "rx_bcast_packets" }, | |
322 | { "rx_fcs_errors" }, | |
323 | { "rx_align_errors" }, | |
324 | { "rx_xon_pause_rcvd" }, | |
325 | { "rx_xoff_pause_rcvd" }, | |
326 | { "rx_mac_ctrl_rcvd" }, | |
327 | { "rx_xoff_entered" }, | |
328 | { "rx_frame_too_long_errors" }, | |
329 | { "rx_jabbers" }, | |
330 | { "rx_undersize_packets" }, | |
331 | { "rx_in_length_errors" }, | |
332 | { "rx_out_length_errors" }, | |
333 | { "rx_64_or_less_octet_packets" }, | |
334 | { "rx_65_to_127_octet_packets" }, | |
335 | { "rx_128_to_255_octet_packets" }, | |
336 | { "rx_256_to_511_octet_packets" }, | |
337 | { "rx_512_to_1023_octet_packets" }, | |
338 | { "rx_1024_to_1522_octet_packets" }, | |
339 | { "rx_1523_to_2047_octet_packets" }, | |
340 | { "rx_2048_to_4095_octet_packets" }, | |
341 | { "rx_4096_to_8191_octet_packets" }, | |
342 | { "rx_8192_to_9022_octet_packets" }, | |
343 | ||
344 | { "tx_octets" }, | |
345 | { "tx_collisions" }, | |
346 | ||
347 | { "tx_xon_sent" }, | |
348 | { "tx_xoff_sent" }, | |
349 | { "tx_flow_control" }, | |
350 | { "tx_mac_errors" }, | |
351 | { "tx_single_collisions" }, | |
352 | { "tx_mult_collisions" }, | |
353 | { "tx_deferred" }, | |
354 | { "tx_excessive_collisions" }, | |
355 | { "tx_late_collisions" }, | |
356 | { "tx_collide_2times" }, | |
357 | { "tx_collide_3times" }, | |
358 | { "tx_collide_4times" }, | |
359 | { "tx_collide_5times" }, | |
360 | { "tx_collide_6times" }, | |
361 | { "tx_collide_7times" }, | |
362 | { "tx_collide_8times" }, | |
363 | { "tx_collide_9times" }, | |
364 | { "tx_collide_10times" }, | |
365 | { "tx_collide_11times" }, | |
366 | { "tx_collide_12times" }, | |
367 | { "tx_collide_13times" }, | |
368 | { "tx_collide_14times" }, | |
369 | { "tx_collide_15times" }, | |
370 | { "tx_ucast_packets" }, | |
371 | { "tx_mcast_packets" }, | |
372 | { "tx_bcast_packets" }, | |
373 | { "tx_carrier_sense_errors" }, | |
374 | { "tx_discards" }, | |
375 | { "tx_errors" }, | |
376 | ||
377 | { "dma_writeq_full" }, | |
378 | { "dma_write_prioq_full" }, | |
379 | { "rxbds_empty" }, | |
380 | { "rx_discards" }, | |
381 | { "rx_errors" }, | |
382 | { "rx_threshold_hit" }, | |
383 | ||
384 | { "dma_readq_full" }, | |
385 | { "dma_read_prioq_full" }, | |
386 | { "tx_comp_queue_full" }, | |
387 | ||
388 | { "ring_set_send_prod_index" }, | |
389 | { "ring_status_update" }, | |
390 | { "nic_irqs" }, | |
391 | { "nic_avoided_irqs" }, | |
4452d099 MC |
392 | { "nic_tx_threshold_hit" }, |
393 | ||
394 | { "mbuf_lwm_thresh_hit" }, | |
1da177e4 LT |
395 | }; |
396 | ||
48fa55a0 MC |
397 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
398 | ||
399 | ||
50da859d | 400 | static const struct { |
4cafd3f5 | 401 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 402 | } ethtool_test_keys[] = { |
28a45957 MC |
403 | { "nvram test (online) " }, |
404 | { "link test (online) " }, | |
405 | { "register test (offline)" }, | |
406 | { "memory test (offline)" }, | |
407 | { "mac loopback test (offline)" }, | |
408 | { "phy loopback test (offline)" }, | |
941ec90f | 409 | { "ext loopback test (offline)" }, |
28a45957 | 410 | { "interrupt test (offline)" }, |
4cafd3f5 MC |
411 | }; |
412 | ||
48fa55a0 MC |
413 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
414 | ||
415 | ||
b401e9e2 MC |
416 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
417 | { | |
418 | writel(val, tp->regs + off); | |
419 | } | |
420 | ||
421 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
422 | { | |
de6f31eb | 423 | return readl(tp->regs + off); |
b401e9e2 MC |
424 | } |
425 | ||
0d3031d9 MC |
426 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
427 | { | |
428 | writel(val, tp->aperegs + off); | |
429 | } | |
430 | ||
431 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
432 | { | |
de6f31eb | 433 | return readl(tp->aperegs + off); |
0d3031d9 MC |
434 | } |
435 | ||
1da177e4 LT |
436 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
437 | { | |
6892914f MC |
438 | unsigned long flags; |
439 | ||
440 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
441 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
442 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 443 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
444 | } |
445 | ||
446 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
447 | { | |
448 | writel(val, tp->regs + off); | |
449 | readl(tp->regs + off); | |
1da177e4 LT |
450 | } |
451 | ||
6892914f | 452 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 453 | { |
6892914f MC |
454 | unsigned long flags; |
455 | u32 val; | |
456 | ||
457 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
458 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
459 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
460 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
461 | return val; | |
462 | } | |
463 | ||
464 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
465 | { | |
466 | unsigned long flags; | |
467 | ||
468 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
469 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
470 | TG3_64BIT_REG_LOW, val); | |
471 | return; | |
472 | } | |
66711e66 | 473 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
474 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
475 | TG3_64BIT_REG_LOW, val); | |
476 | return; | |
1da177e4 | 477 | } |
6892914f MC |
478 | |
479 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
480 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
481 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
482 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
483 | ||
484 | /* In indirect mode when disabling interrupts, we also need | |
485 | * to clear the interrupt bit in the GRC local ctrl register. | |
486 | */ | |
487 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
488 | (val == 0x1)) { | |
489 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
490 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
491 | } | |
492 | } | |
493 | ||
494 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
495 | { | |
496 | unsigned long flags; | |
497 | u32 val; | |
498 | ||
499 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
500 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
501 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
502 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
503 | return val; | |
504 | } | |
505 | ||
b401e9e2 MC |
506 | /* usec_wait specifies the wait time in usec when writing to certain registers |
507 | * where it is unsafe to read back the register without some delay. | |
508 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
509 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
510 | */ | |
511 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 512 | { |
63c3a66f | 513 | if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) |
b401e9e2 MC |
514 | /* Non-posted methods */ |
515 | tp->write32(tp, off, val); | |
516 | else { | |
517 | /* Posted method */ | |
518 | tg3_write32(tp, off, val); | |
519 | if (usec_wait) | |
520 | udelay(usec_wait); | |
521 | tp->read32(tp, off); | |
522 | } | |
523 | /* Wait again after the read for the posted method to guarantee that | |
524 | * the wait time is met. | |
525 | */ | |
526 | if (usec_wait) | |
527 | udelay(usec_wait); | |
1da177e4 LT |
528 | } |
529 | ||
09ee929c MC |
530 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
531 | { | |
532 | tp->write32_mbox(tp, off, val); | |
63c3a66f | 533 | if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) |
6892914f | 534 | tp->read32_mbox(tp, off); |
09ee929c MC |
535 | } |
536 | ||
20094930 | 537 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
538 | { |
539 | void __iomem *mbox = tp->regs + off; | |
540 | writel(val, mbox); | |
63c3a66f | 541 | if (tg3_flag(tp, TXD_MBOX_HWBUG)) |
1da177e4 | 542 | writel(val, mbox); |
63c3a66f | 543 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1da177e4 LT |
544 | readl(mbox); |
545 | } | |
546 | ||
b5d3772c MC |
547 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
548 | { | |
de6f31eb | 549 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
550 | } |
551 | ||
552 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
553 | { | |
554 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
555 | } | |
556 | ||
c6cdf436 | 557 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 558 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
559 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
560 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
561 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 562 | |
c6cdf436 MC |
563 | #define tw32(reg, val) tp->write32(tp, reg, val) |
564 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
565 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
566 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
567 | |
568 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
569 | { | |
6892914f MC |
570 | unsigned long flags; |
571 | ||
6ff6f81d | 572 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
573 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) |
574 | return; | |
575 | ||
6892914f | 576 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 577 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
578 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
579 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 580 | |
bbadf503 MC |
581 | /* Always leave this as zero. */ |
582 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
583 | } else { | |
584 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
585 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 586 | |
bbadf503 MC |
587 | /* Always leave this as zero. */ |
588 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
589 | } | |
590 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
591 | } |
592 | ||
1da177e4 LT |
593 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
594 | { | |
6892914f MC |
595 | unsigned long flags; |
596 | ||
6ff6f81d | 597 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
598 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { |
599 | *val = 0; | |
600 | return; | |
601 | } | |
602 | ||
6892914f | 603 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 604 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
605 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
606 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 607 | |
bbadf503 MC |
608 | /* Always leave this as zero. */ |
609 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
610 | } else { | |
611 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
612 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
613 | ||
614 | /* Always leave this as zero. */ | |
615 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
616 | } | |
6892914f | 617 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
618 | } |
619 | ||
0d3031d9 MC |
620 | static void tg3_ape_lock_init(struct tg3 *tp) |
621 | { | |
622 | int i; | |
6f5c8f83 | 623 | u32 regbase, bit; |
f92d9dc1 MC |
624 | |
625 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
626 | regbase = TG3_APE_LOCK_GRANT; | |
627 | else | |
628 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
629 | |
630 | /* Make sure the driver hasn't any stale locks. */ | |
78f94dc7 MC |
631 | for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) { |
632 | switch (i) { | |
633 | case TG3_APE_LOCK_PHY0: | |
634 | case TG3_APE_LOCK_PHY1: | |
635 | case TG3_APE_LOCK_PHY2: | |
636 | case TG3_APE_LOCK_PHY3: | |
637 | bit = APE_LOCK_GRANT_DRIVER; | |
638 | break; | |
639 | default: | |
640 | if (!tp->pci_fn) | |
641 | bit = APE_LOCK_GRANT_DRIVER; | |
642 | else | |
643 | bit = 1 << tp->pci_fn; | |
644 | } | |
645 | tg3_ape_write32(tp, regbase + 4 * i, bit); | |
6f5c8f83 MC |
646 | } |
647 | ||
0d3031d9 MC |
648 | } |
649 | ||
650 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
651 | { | |
652 | int i, off; | |
653 | int ret = 0; | |
6f5c8f83 | 654 | u32 status, req, gnt, bit; |
0d3031d9 | 655 | |
63c3a66f | 656 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
657 | return 0; |
658 | ||
659 | switch (locknum) { | |
6f5c8f83 MC |
660 | case TG3_APE_LOCK_GPIO: |
661 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
662 | return 0; | |
33f401ae MC |
663 | case TG3_APE_LOCK_GRC: |
664 | case TG3_APE_LOCK_MEM: | |
78f94dc7 MC |
665 | if (!tp->pci_fn) |
666 | bit = APE_LOCK_REQ_DRIVER; | |
667 | else | |
668 | bit = 1 << tp->pci_fn; | |
33f401ae MC |
669 | break; |
670 | default: | |
671 | return -EINVAL; | |
0d3031d9 MC |
672 | } |
673 | ||
f92d9dc1 MC |
674 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
675 | req = TG3_APE_LOCK_REQ; | |
676 | gnt = TG3_APE_LOCK_GRANT; | |
677 | } else { | |
678 | req = TG3_APE_PER_LOCK_REQ; | |
679 | gnt = TG3_APE_PER_LOCK_GRANT; | |
680 | } | |
681 | ||
0d3031d9 MC |
682 | off = 4 * locknum; |
683 | ||
6f5c8f83 | 684 | tg3_ape_write32(tp, req + off, bit); |
0d3031d9 MC |
685 | |
686 | /* Wait for up to 1 millisecond to acquire lock. */ | |
687 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 688 | status = tg3_ape_read32(tp, gnt + off); |
6f5c8f83 | 689 | if (status == bit) |
0d3031d9 MC |
690 | break; |
691 | udelay(10); | |
692 | } | |
693 | ||
6f5c8f83 | 694 | if (status != bit) { |
0d3031d9 | 695 | /* Revoke the lock request. */ |
6f5c8f83 | 696 | tg3_ape_write32(tp, gnt + off, bit); |
0d3031d9 MC |
697 | ret = -EBUSY; |
698 | } | |
699 | ||
700 | return ret; | |
701 | } | |
702 | ||
703 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
704 | { | |
6f5c8f83 | 705 | u32 gnt, bit; |
0d3031d9 | 706 | |
63c3a66f | 707 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
708 | return; |
709 | ||
710 | switch (locknum) { | |
6f5c8f83 MC |
711 | case TG3_APE_LOCK_GPIO: |
712 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
713 | return; | |
33f401ae MC |
714 | case TG3_APE_LOCK_GRC: |
715 | case TG3_APE_LOCK_MEM: | |
78f94dc7 MC |
716 | if (!tp->pci_fn) |
717 | bit = APE_LOCK_GRANT_DRIVER; | |
718 | else | |
719 | bit = 1 << tp->pci_fn; | |
33f401ae MC |
720 | break; |
721 | default: | |
722 | return; | |
0d3031d9 MC |
723 | } |
724 | ||
f92d9dc1 MC |
725 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
726 | gnt = TG3_APE_LOCK_GRANT; | |
727 | else | |
728 | gnt = TG3_APE_PER_LOCK_GRANT; | |
729 | ||
6f5c8f83 | 730 | tg3_ape_write32(tp, gnt + 4 * locknum, bit); |
0d3031d9 MC |
731 | } |
732 | ||
fd6d3f0e MC |
733 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
734 | { | |
735 | int i; | |
736 | u32 apedata; | |
737 | ||
738 | /* NCSI does not support APE events */ | |
739 | if (tg3_flag(tp, APE_HAS_NCSI)) | |
740 | return; | |
741 | ||
742 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
743 | if (apedata != APE_SEG_SIG_MAGIC) | |
744 | return; | |
745 | ||
746 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
747 | if (!(apedata & APE_FW_STATUS_READY)) | |
748 | return; | |
749 | ||
750 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
751 | for (i = 0; i < 10; i++) { | |
752 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
753 | return; | |
754 | ||
755 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
756 | ||
757 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
758 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
759 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
760 | ||
761 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
762 | ||
763 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
764 | break; | |
765 | ||
766 | udelay(100); | |
767 | } | |
768 | ||
769 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
770 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
771 | } | |
772 | ||
773 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
774 | { | |
775 | u32 event; | |
776 | u32 apedata; | |
777 | ||
778 | if (!tg3_flag(tp, ENABLE_APE)) | |
779 | return; | |
780 | ||
781 | switch (kind) { | |
782 | case RESET_KIND_INIT: | |
783 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
784 | APE_HOST_SEG_SIG_MAGIC); | |
785 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
786 | APE_HOST_SEG_LEN_MAGIC); | |
787 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
788 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
789 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
790 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); | |
791 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
792 | APE_HOST_BEHAV_NO_PHYLOCK); | |
793 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, | |
794 | TG3_APE_HOST_DRVR_STATE_START); | |
795 | ||
796 | event = APE_EVENT_STATUS_STATE_START; | |
797 | break; | |
798 | case RESET_KIND_SHUTDOWN: | |
799 | /* With the interface we are currently using, | |
800 | * APE does not track driver state. Wiping | |
801 | * out the HOST SEGMENT SIGNATURE forces | |
802 | * the APE to assume OS absent status. | |
803 | */ | |
804 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
805 | ||
806 | if (device_may_wakeup(&tp->pdev->dev) && | |
807 | tg3_flag(tp, WOL_ENABLE)) { | |
808 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, | |
809 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
810 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
811 | } else | |
812 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
813 | ||
814 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
815 | ||
816 | event = APE_EVENT_STATUS_STATE_UNLOAD; | |
817 | break; | |
818 | case RESET_KIND_SUSPEND: | |
819 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
820 | break; | |
821 | default: | |
822 | return; | |
823 | } | |
824 | ||
825 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
826 | ||
827 | tg3_ape_send_event(tp, event); | |
828 | } | |
829 | ||
1da177e4 LT |
830 | static void tg3_disable_ints(struct tg3 *tp) |
831 | { | |
89aeb3bc MC |
832 | int i; |
833 | ||
1da177e4 LT |
834 | tw32(TG3PCI_MISC_HOST_CTRL, |
835 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
836 | for (i = 0; i < tp->irq_max; i++) |
837 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
838 | } |
839 | ||
1da177e4 LT |
840 | static void tg3_enable_ints(struct tg3 *tp) |
841 | { | |
89aeb3bc | 842 | int i; |
89aeb3bc | 843 | |
bbe832c0 MC |
844 | tp->irq_sync = 0; |
845 | wmb(); | |
846 | ||
1da177e4 LT |
847 | tw32(TG3PCI_MISC_HOST_CTRL, |
848 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 849 | |
f89f38b8 | 850 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
851 | for (i = 0; i < tp->irq_cnt; i++) { |
852 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 853 | |
898a56f8 | 854 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
63c3a66f | 855 | if (tg3_flag(tp, 1SHOT_MSI)) |
89aeb3bc | 856 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
f19af9c2 | 857 | |
f89f38b8 | 858 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 859 | } |
f19af9c2 MC |
860 | |
861 | /* Force an initial interrupt */ | |
63c3a66f | 862 | if (!tg3_flag(tp, TAGGED_STATUS) && |
f19af9c2 MC |
863 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) |
864 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
865 | else | |
f89f38b8 MC |
866 | tw32(HOSTCC_MODE, tp->coal_now); |
867 | ||
868 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
869 | } |
870 | ||
17375d25 | 871 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 872 | { |
17375d25 | 873 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 874 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
875 | unsigned int work_exists = 0; |
876 | ||
877 | /* check for phy events */ | |
63c3a66f | 878 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
04237ddd MC |
879 | if (sblk->status & SD_STATUS_LINK_CHG) |
880 | work_exists = 1; | |
881 | } | |
f891ea16 MC |
882 | |
883 | /* check for TX work to do */ | |
884 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons) | |
885 | work_exists = 1; | |
886 | ||
887 | /* check for RX work to do */ | |
888 | if (tnapi->rx_rcb_prod_idx && | |
8d9d7cfc | 889 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
890 | work_exists = 1; |
891 | ||
892 | return work_exists; | |
893 | } | |
894 | ||
17375d25 | 895 | /* tg3_int_reenable |
04237ddd MC |
896 | * similar to tg3_enable_ints, but it accurately determines whether there |
897 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 898 | * which reenables interrupts |
1da177e4 | 899 | */ |
17375d25 | 900 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 901 | { |
17375d25 MC |
902 | struct tg3 *tp = tnapi->tp; |
903 | ||
898a56f8 | 904 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
905 | mmiowb(); |
906 | ||
fac9b83e DM |
907 | /* When doing tagged status, this work check is unnecessary. |
908 | * The last_tag we write above tells the chip which piece of | |
909 | * work we've completed. | |
910 | */ | |
63c3a66f | 911 | if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) |
04237ddd | 912 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 913 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
914 | } |
915 | ||
1da177e4 LT |
916 | static void tg3_switch_clocks(struct tg3 *tp) |
917 | { | |
f6eb9b1f | 918 | u32 clock_ctrl; |
1da177e4 LT |
919 | u32 orig_clock_ctrl; |
920 | ||
63c3a66f | 921 | if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) |
4cf78e4f MC |
922 | return; |
923 | ||
f6eb9b1f MC |
924 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
925 | ||
1da177e4 LT |
926 | orig_clock_ctrl = clock_ctrl; |
927 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
928 | CLOCK_CTRL_CLKRUN_OENABLE | | |
929 | 0x1f); | |
930 | tp->pci_clock_ctrl = clock_ctrl; | |
931 | ||
63c3a66f | 932 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 | 933 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { |
b401e9e2 MC |
934 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
935 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
936 | } |
937 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
938 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
939 | clock_ctrl | | |
940 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
941 | 40); | |
942 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
943 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
944 | 40); | |
1da177e4 | 945 | } |
b401e9e2 | 946 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
947 | } |
948 | ||
949 | #define PHY_BUSY_LOOPS 5000 | |
950 | ||
951 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
952 | { | |
953 | u32 frame_val; | |
954 | unsigned int loops; | |
955 | int ret; | |
956 | ||
957 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
958 | tw32_f(MAC_MI_MODE, | |
959 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
960 | udelay(80); | |
961 | } | |
962 | ||
963 | *val = 0x0; | |
964 | ||
882e9793 | 965 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
966 | MI_COM_PHY_ADDR_MASK); |
967 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
968 | MI_COM_REG_ADDR_MASK); | |
969 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 970 | |
1da177e4 LT |
971 | tw32_f(MAC_MI_COM, frame_val); |
972 | ||
973 | loops = PHY_BUSY_LOOPS; | |
974 | while (loops != 0) { | |
975 | udelay(10); | |
976 | frame_val = tr32(MAC_MI_COM); | |
977 | ||
978 | if ((frame_val & MI_COM_BUSY) == 0) { | |
979 | udelay(5); | |
980 | frame_val = tr32(MAC_MI_COM); | |
981 | break; | |
982 | } | |
983 | loops -= 1; | |
984 | } | |
985 | ||
986 | ret = -EBUSY; | |
987 | if (loops != 0) { | |
988 | *val = frame_val & MI_COM_DATA_MASK; | |
989 | ret = 0; | |
990 | } | |
991 | ||
992 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
993 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
994 | udelay(80); | |
995 | } | |
996 | ||
997 | return ret; | |
998 | } | |
999 | ||
1000 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
1001 | { | |
1002 | u32 frame_val; | |
1003 | unsigned int loops; | |
1004 | int ret; | |
1005 | ||
f07e9af3 | 1006 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
221c5637 | 1007 | (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) |
b5d3772c MC |
1008 | return 0; |
1009 | ||
1da177e4 LT |
1010 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
1011 | tw32_f(MAC_MI_MODE, | |
1012 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
1013 | udelay(80); | |
1014 | } | |
1015 | ||
882e9793 | 1016 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
1017 | MI_COM_PHY_ADDR_MASK); |
1018 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
1019 | MI_COM_REG_ADDR_MASK); | |
1020 | frame_val |= (val & MI_COM_DATA_MASK); | |
1021 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 1022 | |
1da177e4 LT |
1023 | tw32_f(MAC_MI_COM, frame_val); |
1024 | ||
1025 | loops = PHY_BUSY_LOOPS; | |
1026 | while (loops != 0) { | |
1027 | udelay(10); | |
1028 | frame_val = tr32(MAC_MI_COM); | |
1029 | if ((frame_val & MI_COM_BUSY) == 0) { | |
1030 | udelay(5); | |
1031 | frame_val = tr32(MAC_MI_COM); | |
1032 | break; | |
1033 | } | |
1034 | loops -= 1; | |
1035 | } | |
1036 | ||
1037 | ret = -EBUSY; | |
1038 | if (loops != 0) | |
1039 | ret = 0; | |
1040 | ||
1041 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
1042 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1043 | udelay(80); | |
1044 | } | |
1045 | ||
1046 | return ret; | |
1047 | } | |
1048 | ||
b0988c15 MC |
1049 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
1050 | { | |
1051 | int err; | |
1052 | ||
1053 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1054 | if (err) | |
1055 | goto done; | |
1056 | ||
1057 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1058 | if (err) | |
1059 | goto done; | |
1060 | ||
1061 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1062 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1063 | if (err) | |
1064 | goto done; | |
1065 | ||
1066 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
1067 | ||
1068 | done: | |
1069 | return err; | |
1070 | } | |
1071 | ||
1072 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
1073 | { | |
1074 | int err; | |
1075 | ||
1076 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1077 | if (err) | |
1078 | goto done; | |
1079 | ||
1080 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1081 | if (err) | |
1082 | goto done; | |
1083 | ||
1084 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1085 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1086 | if (err) | |
1087 | goto done; | |
1088 | ||
1089 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
1090 | ||
1091 | done: | |
1092 | return err; | |
1093 | } | |
1094 | ||
1095 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) | |
1096 | { | |
1097 | int err; | |
1098 | ||
1099 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1100 | if (!err) | |
1101 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
1102 | ||
1103 | return err; | |
1104 | } | |
1105 | ||
1106 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
1107 | { | |
1108 | int err; | |
1109 | ||
1110 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1111 | if (!err) | |
1112 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1113 | ||
1114 | return err; | |
1115 | } | |
1116 | ||
15ee95c3 MC |
1117 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) |
1118 | { | |
1119 | int err; | |
1120 | ||
1121 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1122 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | | |
1123 | MII_TG3_AUXCTL_SHDWSEL_MISC); | |
1124 | if (!err) | |
1125 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); | |
1126 | ||
1127 | return err; | |
1128 | } | |
1129 | ||
b4bd2929 MC |
1130 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) |
1131 | { | |
1132 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) | |
1133 | set |= MII_TG3_AUXCTL_MISC_WREN; | |
1134 | ||
1135 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); | |
1136 | } | |
1137 | ||
1d36ba45 MC |
1138 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ |
1139 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1140 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ | |
1141 | MII_TG3_AUXCTL_ACTL_TX_6DB) | |
1142 | ||
1143 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ | |
1144 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1145 | MII_TG3_AUXCTL_ACTL_TX_6DB); | |
1146 | ||
95e2869a MC |
1147 | static int tg3_bmcr_reset(struct tg3 *tp) |
1148 | { | |
1149 | u32 phy_control; | |
1150 | int limit, err; | |
1151 | ||
1152 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
1153 | * clears or we time out. | |
1154 | */ | |
1155 | phy_control = BMCR_RESET; | |
1156 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
1157 | if (err != 0) | |
1158 | return -EBUSY; | |
1159 | ||
1160 | limit = 5000; | |
1161 | while (limit--) { | |
1162 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
1163 | if (err != 0) | |
1164 | return -EBUSY; | |
1165 | ||
1166 | if ((phy_control & BMCR_RESET) == 0) { | |
1167 | udelay(40); | |
1168 | break; | |
1169 | } | |
1170 | udelay(10); | |
1171 | } | |
d4675b52 | 1172 | if (limit < 0) |
95e2869a MC |
1173 | return -EBUSY; |
1174 | ||
1175 | return 0; | |
1176 | } | |
1177 | ||
158d7abd MC |
1178 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
1179 | { | |
3d16543d | 1180 | struct tg3 *tp = bp->priv; |
158d7abd MC |
1181 | u32 val; |
1182 | ||
24bb4fb6 | 1183 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1184 | |
1185 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
1186 | val = -EIO; |
1187 | ||
1188 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
1189 | |
1190 | return val; | |
1191 | } | |
1192 | ||
1193 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
1194 | { | |
3d16543d | 1195 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 1196 | u32 ret = 0; |
158d7abd | 1197 | |
24bb4fb6 | 1198 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1199 | |
1200 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 1201 | ret = -EIO; |
158d7abd | 1202 | |
24bb4fb6 MC |
1203 | spin_unlock_bh(&tp->lock); |
1204 | ||
1205 | return ret; | |
158d7abd MC |
1206 | } |
1207 | ||
1208 | static int tg3_mdio_reset(struct mii_bus *bp) | |
1209 | { | |
1210 | return 0; | |
1211 | } | |
1212 | ||
9c61d6bc | 1213 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
1214 | { |
1215 | u32 val; | |
fcb389df | 1216 | struct phy_device *phydev; |
a9daf367 | 1217 | |
3f0e3ad7 | 1218 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 1219 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
1220 | case PHY_ID_BCM50610: |
1221 | case PHY_ID_BCM50610M: | |
fcb389df MC |
1222 | val = MAC_PHYCFG2_50610_LED_MODES; |
1223 | break; | |
6a443a0f | 1224 | case PHY_ID_BCMAC131: |
fcb389df MC |
1225 | val = MAC_PHYCFG2_AC131_LED_MODES; |
1226 | break; | |
6a443a0f | 1227 | case PHY_ID_RTL8211C: |
fcb389df MC |
1228 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
1229 | break; | |
6a443a0f | 1230 | case PHY_ID_RTL8201E: |
fcb389df MC |
1231 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
1232 | break; | |
1233 | default: | |
a9daf367 | 1234 | return; |
fcb389df MC |
1235 | } |
1236 | ||
1237 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
1238 | tw32(MAC_PHYCFG2, val); | |
1239 | ||
1240 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
1241 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
1242 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1243 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
1244 | tw32(MAC_PHYCFG1, val); |
1245 | ||
1246 | return; | |
1247 | } | |
1248 | ||
63c3a66f | 1249 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) |
fcb389df MC |
1250 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
1251 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1252 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1253 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1254 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1255 | MAC_PHYCFG2_INBAND_ENABLE; | |
1256 | ||
1257 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 1258 | |
bb85fbb6 MC |
1259 | val = tr32(MAC_PHYCFG1); |
1260 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1261 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
63c3a66f JP |
1262 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1263 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 | 1264 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; |
63c3a66f | 1265 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1266 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; |
1267 | } | |
bb85fbb6 MC |
1268 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1269 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1270 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1271 | |
a9daf367 MC |
1272 | val = tr32(MAC_EXT_RGMII_MODE); |
1273 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1274 | MAC_RGMII_MODE_RX_QUALITY | | |
1275 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1276 | MAC_RGMII_MODE_RX_ENG_DET | | |
1277 | MAC_RGMII_MODE_TX_ENABLE | | |
1278 | MAC_RGMII_MODE_TX_LOWPWR | | |
1279 | MAC_RGMII_MODE_TX_RESET); | |
63c3a66f JP |
1280 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1281 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 MC |
1282 | val |= MAC_RGMII_MODE_RX_INT_B | |
1283 | MAC_RGMII_MODE_RX_QUALITY | | |
1284 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1285 | MAC_RGMII_MODE_RX_ENG_DET; | |
63c3a66f | 1286 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1287 | val |= MAC_RGMII_MODE_TX_ENABLE | |
1288 | MAC_RGMII_MODE_TX_LOWPWR | | |
1289 | MAC_RGMII_MODE_TX_RESET; | |
1290 | } | |
1291 | tw32(MAC_EXT_RGMII_MODE, val); | |
1292 | } | |
1293 | ||
158d7abd MC |
1294 | static void tg3_mdio_start(struct tg3 *tp) |
1295 | { | |
158d7abd MC |
1296 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1297 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1298 | udelay(80); | |
a9daf367 | 1299 | |
63c3a66f | 1300 | if (tg3_flag(tp, MDIOBUS_INITED) && |
9ea4818d MC |
1301 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
1302 | tg3_mdio_config_5785(tp); | |
1303 | } | |
1304 | ||
1305 | static int tg3_mdio_init(struct tg3 *tp) | |
1306 | { | |
1307 | int i; | |
1308 | u32 reg; | |
1309 | struct phy_device *phydev; | |
1310 | ||
63c3a66f | 1311 | if (tg3_flag(tp, 5717_PLUS)) { |
9c7df915 | 1312 | u32 is_serdes; |
882e9793 | 1313 | |
69f11c99 | 1314 | tp->phy_addr = tp->pci_fn + 1; |
882e9793 | 1315 | |
d1ec96af MC |
1316 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1317 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1318 | else | |
1319 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1320 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1321 | if (is_serdes) |
1322 | tp->phy_addr += 7; | |
1323 | } else | |
3f0e3ad7 | 1324 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1325 | |
158d7abd MC |
1326 | tg3_mdio_start(tp); |
1327 | ||
63c3a66f | 1328 | if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) |
158d7abd MC |
1329 | return 0; |
1330 | ||
298cf9be LB |
1331 | tp->mdio_bus = mdiobus_alloc(); |
1332 | if (tp->mdio_bus == NULL) | |
1333 | return -ENOMEM; | |
158d7abd | 1334 | |
298cf9be LB |
1335 | tp->mdio_bus->name = "tg3 mdio bus"; |
1336 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1337 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1338 | tp->mdio_bus->priv = tp; |
1339 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1340 | tp->mdio_bus->read = &tg3_mdio_read; | |
1341 | tp->mdio_bus->write = &tg3_mdio_write; | |
1342 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1343 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1344 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1345 | |
1346 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1347 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1348 | |
1349 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1350 | * Unfortunately, it does not ensure the PHY is powered up before | |
1351 | * accessing the PHY ID registers. A chip reset is the | |
1352 | * quickest way to bring the device back to an operational state.. | |
1353 | */ | |
1354 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1355 | tg3_bmcr_reset(tp); | |
1356 | ||
298cf9be | 1357 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1358 | if (i) { |
ab96b241 | 1359 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1360 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1361 | return i; |
1362 | } | |
158d7abd | 1363 | |
3f0e3ad7 | 1364 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1365 | |
9c61d6bc | 1366 | if (!phydev || !phydev->drv) { |
ab96b241 | 1367 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1368 | mdiobus_unregister(tp->mdio_bus); |
1369 | mdiobus_free(tp->mdio_bus); | |
1370 | return -ENODEV; | |
1371 | } | |
1372 | ||
1373 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1374 | case PHY_ID_BCM57780: |
321d32a0 | 1375 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1376 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1377 | break; |
6a443a0f MC |
1378 | case PHY_ID_BCM50610: |
1379 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1380 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1381 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1382 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1383 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
63c3a66f | 1384 | if (tg3_flag(tp, RGMII_INBAND_DISABLE)) |
a9daf367 | 1385 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
63c3a66f | 1386 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
a9daf367 | 1387 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; |
63c3a66f | 1388 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 | 1389 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; |
fcb389df | 1390 | /* fallthru */ |
6a443a0f | 1391 | case PHY_ID_RTL8211C: |
fcb389df | 1392 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1393 | break; |
6a443a0f MC |
1394 | case PHY_ID_RTL8201E: |
1395 | case PHY_ID_BCMAC131: | |
a9daf367 | 1396 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1397 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1398 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1399 | break; |
1400 | } | |
1401 | ||
63c3a66f | 1402 | tg3_flag_set(tp, MDIOBUS_INITED); |
9c61d6bc MC |
1403 | |
1404 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1405 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1406 | |
1407 | return 0; | |
158d7abd MC |
1408 | } |
1409 | ||
1410 | static void tg3_mdio_fini(struct tg3 *tp) | |
1411 | { | |
63c3a66f JP |
1412 | if (tg3_flag(tp, MDIOBUS_INITED)) { |
1413 | tg3_flag_clear(tp, MDIOBUS_INITED); | |
298cf9be LB |
1414 | mdiobus_unregister(tp->mdio_bus); |
1415 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1416 | } |
1417 | } | |
1418 | ||
4ba526ce MC |
1419 | /* tp->lock is held. */ |
1420 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1421 | { | |
1422 | u32 val; | |
1423 | ||
1424 | val = tr32(GRC_RX_CPU_EVENT); | |
1425 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1426 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1427 | ||
1428 | tp->last_event_jiffies = jiffies; | |
1429 | } | |
1430 | ||
1431 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1432 | ||
95e2869a MC |
1433 | /* tp->lock is held. */ |
1434 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1435 | { | |
1436 | int i; | |
4ba526ce MC |
1437 | unsigned int delay_cnt; |
1438 | long time_remain; | |
1439 | ||
1440 | /* If enough time has passed, no wait is necessary. */ | |
1441 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1442 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1443 | (long)jiffies; | |
1444 | if (time_remain < 0) | |
1445 | return; | |
1446 | ||
1447 | /* Check if we can shorten the wait time. */ | |
1448 | delay_cnt = jiffies_to_usecs(time_remain); | |
1449 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1450 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1451 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1452 | |
4ba526ce | 1453 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1454 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1455 | break; | |
4ba526ce | 1456 | udelay(8); |
95e2869a MC |
1457 | } |
1458 | } | |
1459 | ||
1460 | /* tp->lock is held. */ | |
b28f389d | 1461 | static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data) |
95e2869a | 1462 | { |
b28f389d | 1463 | u32 reg, val; |
95e2869a MC |
1464 | |
1465 | val = 0; | |
1466 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1467 | val = reg << 16; | |
1468 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1469 | val |= (reg & 0xffff); | |
b28f389d | 1470 | *data++ = val; |
95e2869a MC |
1471 | |
1472 | val = 0; | |
1473 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1474 | val = reg << 16; | |
1475 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1476 | val |= (reg & 0xffff); | |
b28f389d | 1477 | *data++ = val; |
95e2869a MC |
1478 | |
1479 | val = 0; | |
f07e9af3 | 1480 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1481 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1482 | val = reg << 16; | |
1483 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1484 | val |= (reg & 0xffff); | |
1485 | } | |
b28f389d | 1486 | *data++ = val; |
95e2869a MC |
1487 | |
1488 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1489 | val = reg << 16; | |
1490 | else | |
1491 | val = 0; | |
b28f389d MC |
1492 | *data++ = val; |
1493 | } | |
1494 | ||
1495 | /* tp->lock is held. */ | |
1496 | static void tg3_ump_link_report(struct tg3 *tp) | |
1497 | { | |
1498 | u32 data[4]; | |
1499 | ||
1500 | if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) | |
1501 | return; | |
1502 | ||
1503 | tg3_phy_gather_ump_data(tp, data); | |
1504 | ||
1505 | tg3_wait_for_event_ack(tp); | |
1506 | ||
1507 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1508 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1509 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]); | |
1510 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]); | |
1511 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]); | |
1512 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]); | |
95e2869a | 1513 | |
4ba526ce | 1514 | tg3_generate_fw_event(tp); |
95e2869a MC |
1515 | } |
1516 | ||
8d5a89b3 MC |
1517 | /* tp->lock is held. */ |
1518 | static void tg3_stop_fw(struct tg3 *tp) | |
1519 | { | |
1520 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { | |
1521 | /* Wait for RX cpu to ACK the previous event. */ | |
1522 | tg3_wait_for_event_ack(tp); | |
1523 | ||
1524 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
1525 | ||
1526 | tg3_generate_fw_event(tp); | |
1527 | ||
1528 | /* Wait for RX cpu to ACK this event. */ | |
1529 | tg3_wait_for_event_ack(tp); | |
1530 | } | |
1531 | } | |
1532 | ||
fd6d3f0e MC |
1533 | /* tp->lock is held. */ |
1534 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
1535 | { | |
1536 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, | |
1537 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1538 | ||
1539 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
1540 | switch (kind) { | |
1541 | case RESET_KIND_INIT: | |
1542 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1543 | DRV_STATE_START); | |
1544 | break; | |
1545 | ||
1546 | case RESET_KIND_SHUTDOWN: | |
1547 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1548 | DRV_STATE_UNLOAD); | |
1549 | break; | |
1550 | ||
1551 | case RESET_KIND_SUSPEND: | |
1552 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1553 | DRV_STATE_SUSPEND); | |
1554 | break; | |
1555 | ||
1556 | default: | |
1557 | break; | |
1558 | } | |
1559 | } | |
1560 | ||
1561 | if (kind == RESET_KIND_INIT || | |
1562 | kind == RESET_KIND_SUSPEND) | |
1563 | tg3_ape_driver_state_change(tp, kind); | |
1564 | } | |
1565 | ||
1566 | /* tp->lock is held. */ | |
1567 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
1568 | { | |
1569 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
1570 | switch (kind) { | |
1571 | case RESET_KIND_INIT: | |
1572 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1573 | DRV_STATE_START_DONE); | |
1574 | break; | |
1575 | ||
1576 | case RESET_KIND_SHUTDOWN: | |
1577 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1578 | DRV_STATE_UNLOAD_DONE); | |
1579 | break; | |
1580 | ||
1581 | default: | |
1582 | break; | |
1583 | } | |
1584 | } | |
1585 | ||
1586 | if (kind == RESET_KIND_SHUTDOWN) | |
1587 | tg3_ape_driver_state_change(tp, kind); | |
1588 | } | |
1589 | ||
1590 | /* tp->lock is held. */ | |
1591 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
1592 | { | |
1593 | if (tg3_flag(tp, ENABLE_ASF)) { | |
1594 | switch (kind) { | |
1595 | case RESET_KIND_INIT: | |
1596 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1597 | DRV_STATE_START); | |
1598 | break; | |
1599 | ||
1600 | case RESET_KIND_SHUTDOWN: | |
1601 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1602 | DRV_STATE_UNLOAD); | |
1603 | break; | |
1604 | ||
1605 | case RESET_KIND_SUSPEND: | |
1606 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1607 | DRV_STATE_SUSPEND); | |
1608 | break; | |
1609 | ||
1610 | default: | |
1611 | break; | |
1612 | } | |
1613 | } | |
1614 | } | |
1615 | ||
1616 | static int tg3_poll_fw(struct tg3 *tp) | |
1617 | { | |
1618 | int i; | |
1619 | u32 val; | |
1620 | ||
1621 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
1622 | /* Wait up to 20ms for init done. */ | |
1623 | for (i = 0; i < 200; i++) { | |
1624 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) | |
1625 | return 0; | |
1626 | udelay(100); | |
1627 | } | |
1628 | return -ENODEV; | |
1629 | } | |
1630 | ||
1631 | /* Wait for firmware initialization to complete. */ | |
1632 | for (i = 0; i < 100000; i++) { | |
1633 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
1634 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
1635 | break; | |
1636 | udelay(10); | |
1637 | } | |
1638 | ||
1639 | /* Chip might not be fitted with firmware. Some Sun onboard | |
1640 | * parts are configured like that. So don't signal the timeout | |
1641 | * of the above loop as an error, but do report the lack of | |
1642 | * running firmware once. | |
1643 | */ | |
1644 | if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { | |
1645 | tg3_flag_set(tp, NO_FWARE_REPORTED); | |
1646 | ||
1647 | netdev_info(tp->dev, "No firmware running\n"); | |
1648 | } | |
1649 | ||
1650 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
1651 | /* The 57765 A0 needs a little more | |
1652 | * time to do some important work. | |
1653 | */ | |
1654 | mdelay(10); | |
1655 | } | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
95e2869a MC |
1660 | static void tg3_link_report(struct tg3 *tp) |
1661 | { | |
1662 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1663 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1664 | tg3_ump_link_report(tp); |
1665 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1666 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1667 | (tp->link_config.active_speed == SPEED_1000 ? | |
1668 | 1000 : | |
1669 | (tp->link_config.active_speed == SPEED_100 ? | |
1670 | 100 : 10)), | |
1671 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1672 | "full" : "half")); | |
1673 | ||
1674 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1675 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1676 | "on" : "off", | |
1677 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1678 | "on" : "off"); | |
47007831 MC |
1679 | |
1680 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) | |
1681 | netdev_info(tp->dev, "EEE is %s\n", | |
1682 | tp->setlpicnt ? "enabled" : "disabled"); | |
1683 | ||
95e2869a MC |
1684 | tg3_ump_link_report(tp); |
1685 | } | |
1686 | } | |
1687 | ||
95e2869a MC |
1688 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) |
1689 | { | |
1690 | u16 miireg; | |
1691 | ||
e18ce346 | 1692 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1693 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1694 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1695 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1696 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1697 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1698 | else | |
1699 | miireg = 0; | |
1700 | ||
1701 | return miireg; | |
1702 | } | |
1703 | ||
95e2869a MC |
1704 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1705 | { | |
1706 | u8 cap = 0; | |
1707 | ||
f3791cdf MC |
1708 | if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) { |
1709 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1710 | } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) { | |
1711 | if (lcladv & ADVERTISE_1000XPAUSE) | |
1712 | cap = FLOW_CTRL_RX; | |
1713 | if (rmtadv & ADVERTISE_1000XPAUSE) | |
e18ce346 | 1714 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1715 | } |
1716 | ||
1717 | return cap; | |
1718 | } | |
1719 | ||
f51f3562 | 1720 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1721 | { |
b02fd9e3 | 1722 | u8 autoneg; |
f51f3562 | 1723 | u8 flowctrl = 0; |
95e2869a MC |
1724 | u32 old_rx_mode = tp->rx_mode; |
1725 | u32 old_tx_mode = tp->tx_mode; | |
1726 | ||
63c3a66f | 1727 | if (tg3_flag(tp, USE_PHYLIB)) |
3f0e3ad7 | 1728 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1729 | else |
1730 | autoneg = tp->link_config.autoneg; | |
1731 | ||
63c3a66f | 1732 | if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { |
f07e9af3 | 1733 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1734 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1735 | else |
bc02ff95 | 1736 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1737 | } else |
1738 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1739 | |
f51f3562 | 1740 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1741 | |
e18ce346 | 1742 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1743 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1744 | else | |
1745 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1746 | ||
f51f3562 | 1747 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1748 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1749 | |
e18ce346 | 1750 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1751 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1752 | else | |
1753 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1754 | ||
f51f3562 | 1755 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1756 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1757 | } |
1758 | ||
b02fd9e3 MC |
1759 | static void tg3_adjust_link(struct net_device *dev) |
1760 | { | |
1761 | u8 oldflowctrl, linkmesg = 0; | |
1762 | u32 mac_mode, lcl_adv, rmt_adv; | |
1763 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1764 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1765 | |
24bb4fb6 | 1766 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1767 | |
1768 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1769 | MAC_MODE_HALF_DUPLEX); | |
1770 | ||
1771 | oldflowctrl = tp->link_config.active_flowctrl; | |
1772 | ||
1773 | if (phydev->link) { | |
1774 | lcl_adv = 0; | |
1775 | rmt_adv = 0; | |
1776 | ||
1777 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1778 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1779 | else if (phydev->speed == SPEED_1000 || |
1780 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1781 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1782 | else |
1783 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1784 | |
1785 | if (phydev->duplex == DUPLEX_HALF) | |
1786 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1787 | else { | |
f88788f0 | 1788 | lcl_adv = mii_advertise_flowctrl( |
b02fd9e3 MC |
1789 | tp->link_config.flowctrl); |
1790 | ||
1791 | if (phydev->pause) | |
1792 | rmt_adv = LPA_PAUSE_CAP; | |
1793 | if (phydev->asym_pause) | |
1794 | rmt_adv |= LPA_PAUSE_ASYM; | |
1795 | } | |
1796 | ||
1797 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1798 | } else | |
1799 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1800 | ||
1801 | if (mac_mode != tp->mac_mode) { | |
1802 | tp->mac_mode = mac_mode; | |
1803 | tw32_f(MAC_MODE, tp->mac_mode); | |
1804 | udelay(40); | |
1805 | } | |
1806 | ||
fcb389df MC |
1807 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1808 | if (phydev->speed == SPEED_10) | |
1809 | tw32(MAC_MI_STAT, | |
1810 | MAC_MI_STAT_10MBPS_MODE | | |
1811 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1812 | else | |
1813 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1814 | } | |
1815 | ||
b02fd9e3 MC |
1816 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1817 | tw32(MAC_TX_LENGTHS, | |
1818 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1819 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1820 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1821 | else | |
1822 | tw32(MAC_TX_LENGTHS, | |
1823 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1824 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1825 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1826 | ||
34655ad6 | 1827 | if (phydev->link != tp->old_link || |
b02fd9e3 MC |
1828 | phydev->speed != tp->link_config.active_speed || |
1829 | phydev->duplex != tp->link_config.active_duplex || | |
1830 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1831 | linkmesg = 1; |
b02fd9e3 | 1832 | |
34655ad6 | 1833 | tp->old_link = phydev->link; |
b02fd9e3 MC |
1834 | tp->link_config.active_speed = phydev->speed; |
1835 | tp->link_config.active_duplex = phydev->duplex; | |
1836 | ||
24bb4fb6 | 1837 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1838 | |
1839 | if (linkmesg) | |
1840 | tg3_link_report(tp); | |
1841 | } | |
1842 | ||
1843 | static int tg3_phy_init(struct tg3 *tp) | |
1844 | { | |
1845 | struct phy_device *phydev; | |
1846 | ||
f07e9af3 | 1847 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1848 | return 0; |
1849 | ||
1850 | /* Bring the PHY back to a known state. */ | |
1851 | tg3_bmcr_reset(tp); | |
1852 | ||
3f0e3ad7 | 1853 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1854 | |
1855 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1856 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1857 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1858 | if (IS_ERR(phydev)) { |
ab96b241 | 1859 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1860 | return PTR_ERR(phydev); |
1861 | } | |
1862 | ||
b02fd9e3 | 1863 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1864 | switch (phydev->interface) { |
1865 | case PHY_INTERFACE_MODE_GMII: | |
1866 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 1867 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
1868 | phydev->supported &= (PHY_GBIT_FEATURES | |
1869 | SUPPORTED_Pause | | |
1870 | SUPPORTED_Asym_Pause); | |
1871 | break; | |
1872 | } | |
1873 | /* fallthru */ | |
9c61d6bc MC |
1874 | case PHY_INTERFACE_MODE_MII: |
1875 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1876 | SUPPORTED_Pause | | |
1877 | SUPPORTED_Asym_Pause); | |
1878 | break; | |
1879 | default: | |
3f0e3ad7 | 1880 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1881 | return -EINVAL; |
1882 | } | |
1883 | ||
f07e9af3 | 1884 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1885 | |
1886 | phydev->advertising = phydev->supported; | |
1887 | ||
b02fd9e3 MC |
1888 | return 0; |
1889 | } | |
1890 | ||
1891 | static void tg3_phy_start(struct tg3 *tp) | |
1892 | { | |
1893 | struct phy_device *phydev; | |
1894 | ||
f07e9af3 | 1895 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1896 | return; |
1897 | ||
3f0e3ad7 | 1898 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1899 | |
80096068 MC |
1900 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1901 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
c6700ce2 MC |
1902 | phydev->speed = tp->link_config.speed; |
1903 | phydev->duplex = tp->link_config.duplex; | |
1904 | phydev->autoneg = tp->link_config.autoneg; | |
1905 | phydev->advertising = tp->link_config.advertising; | |
b02fd9e3 MC |
1906 | } |
1907 | ||
1908 | phy_start(phydev); | |
1909 | ||
1910 | phy_start_aneg(phydev); | |
1911 | } | |
1912 | ||
1913 | static void tg3_phy_stop(struct tg3 *tp) | |
1914 | { | |
f07e9af3 | 1915 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1916 | return; |
1917 | ||
3f0e3ad7 | 1918 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1919 | } |
1920 | ||
1921 | static void tg3_phy_fini(struct tg3 *tp) | |
1922 | { | |
f07e9af3 | 1923 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 1924 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 1925 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1926 | } |
1927 | } | |
1928 | ||
941ec90f MC |
1929 | static int tg3_phy_set_extloopbk(struct tg3 *tp) |
1930 | { | |
1931 | int err; | |
1932 | u32 val; | |
1933 | ||
1934 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
1935 | return 0; | |
1936 | ||
1937 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { | |
1938 | /* Cannot do read-modify-write on 5401 */ | |
1939 | err = tg3_phy_auxctl_write(tp, | |
1940 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, | |
1941 | MII_TG3_AUXCTL_ACTL_EXTLOOPBK | | |
1942 | 0x4c20); | |
1943 | goto done; | |
1944 | } | |
1945 | ||
1946 | err = tg3_phy_auxctl_read(tp, | |
1947 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
1948 | if (err) | |
1949 | return err; | |
1950 | ||
1951 | val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK; | |
1952 | err = tg3_phy_auxctl_write(tp, | |
1953 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val); | |
1954 | ||
1955 | done: | |
1956 | return err; | |
1957 | } | |
1958 | ||
7f97a4bd MC |
1959 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1960 | { | |
1961 | u32 phytest; | |
1962 | ||
1963 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1964 | u32 phy; | |
1965 | ||
1966 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1967 | phytest | MII_TG3_FET_SHADOW_EN); | |
1968 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1969 | if (enable) | |
1970 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1971 | else | |
1972 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1973 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1974 | } | |
1975 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1976 | } | |
1977 | } | |
1978 | ||
6833c043 MC |
1979 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1980 | { | |
1981 | u32 reg; | |
1982 | ||
63c3a66f JP |
1983 | if (!tg3_flag(tp, 5705_PLUS) || |
1984 | (tg3_flag(tp, 5717_PLUS) && | |
f07e9af3 | 1985 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
1986 | return; |
1987 | ||
f07e9af3 | 1988 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
1989 | tg3_phy_fet_toggle_apd(tp, enable); |
1990 | return; | |
1991 | } | |
1992 | ||
6833c043 MC |
1993 | reg = MII_TG3_MISC_SHDW_WREN | |
1994 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1995 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1996 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1997 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1998 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1999 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
2000 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
2001 | ||
2002 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
2003 | ||
2004 | ||
2005 | reg = MII_TG3_MISC_SHDW_WREN | | |
2006 | MII_TG3_MISC_SHDW_APD_SEL | | |
2007 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
2008 | if (enable) | |
2009 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
2010 | ||
2011 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
2012 | } | |
2013 | ||
9ef8ca99 MC |
2014 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
2015 | { | |
2016 | u32 phy; | |
2017 | ||
63c3a66f | 2018 | if (!tg3_flag(tp, 5705_PLUS) || |
f07e9af3 | 2019 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
2020 | return; |
2021 | ||
f07e9af3 | 2022 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
2023 | u32 ephy; |
2024 | ||
535ef6e1 MC |
2025 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
2026 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
2027 | ||
2028 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2029 | ephy | MII_TG3_FET_SHADOW_EN); | |
2030 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 2031 | if (enable) |
535ef6e1 | 2032 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 2033 | else |
535ef6e1 MC |
2034 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
2035 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 2036 | } |
535ef6e1 | 2037 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
2038 | } |
2039 | } else { | |
15ee95c3 MC |
2040 | int ret; |
2041 | ||
2042 | ret = tg3_phy_auxctl_read(tp, | |
2043 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); | |
2044 | if (!ret) { | |
9ef8ca99 MC |
2045 | if (enable) |
2046 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
2047 | else | |
2048 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
b4bd2929 MC |
2049 | tg3_phy_auxctl_write(tp, |
2050 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); | |
9ef8ca99 MC |
2051 | } |
2052 | } | |
2053 | } | |
2054 | ||
1da177e4 LT |
2055 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
2056 | { | |
15ee95c3 | 2057 | int ret; |
1da177e4 LT |
2058 | u32 val; |
2059 | ||
f07e9af3 | 2060 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
2061 | return; |
2062 | ||
15ee95c3 MC |
2063 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); |
2064 | if (!ret) | |
b4bd2929 MC |
2065 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, |
2066 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); | |
1da177e4 LT |
2067 | } |
2068 | ||
b2a5c19c MC |
2069 | static void tg3_phy_apply_otp(struct tg3 *tp) |
2070 | { | |
2071 | u32 otp, phy; | |
2072 | ||
2073 | if (!tp->phy_otp) | |
2074 | return; | |
2075 | ||
2076 | otp = tp->phy_otp; | |
2077 | ||
1d36ba45 MC |
2078 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) |
2079 | return; | |
b2a5c19c MC |
2080 | |
2081 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
2082 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
2083 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
2084 | ||
2085 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
2086 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
2087 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
2088 | ||
2089 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
2090 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
2091 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
2092 | ||
2093 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
2094 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
2095 | ||
2096 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
2097 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
2098 | ||
2099 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
2100 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
2101 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
2102 | ||
1d36ba45 | 2103 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
b2a5c19c MC |
2104 | } |
2105 | ||
52b02d04 MC |
2106 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
2107 | { | |
2108 | u32 val; | |
2109 | ||
2110 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
2111 | return; | |
2112 | ||
2113 | tp->setlpicnt = 0; | |
2114 | ||
2115 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
2116 | current_link_up == 1 && | |
a6b68dab MC |
2117 | tp->link_config.active_duplex == DUPLEX_FULL && |
2118 | (tp->link_config.active_speed == SPEED_100 || | |
2119 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
2120 | u32 eeectl; |
2121 | ||
2122 | if (tp->link_config.active_speed == SPEED_1000) | |
2123 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
2124 | else | |
2125 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
2126 | ||
2127 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
2128 | ||
3110f5f5 MC |
2129 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
2130 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 2131 | |
b0c5943f MC |
2132 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || |
2133 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) | |
52b02d04 MC |
2134 | tp->setlpicnt = 2; |
2135 | } | |
2136 | ||
2137 | if (!tp->setlpicnt) { | |
b715ce94 MC |
2138 | if (current_link_up == 1 && |
2139 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
2140 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | |
2141 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2142 | } | |
2143 | ||
52b02d04 MC |
2144 | val = tr32(TG3_CPMU_EEE_MODE); |
2145 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
2146 | } | |
2147 | } | |
2148 | ||
b0c5943f MC |
2149 | static void tg3_phy_eee_enable(struct tg3 *tp) |
2150 | { | |
2151 | u32 val; | |
2152 | ||
2153 | if (tp->link_config.active_speed == SPEED_1000 && | |
2154 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2155 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
55086ad9 | 2156 | tg3_flag(tp, 57765_CLASS)) && |
b0c5943f | 2157 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
b715ce94 MC |
2158 | val = MII_TG3_DSP_TAP26_ALNOKO | |
2159 | MII_TG3_DSP_TAP26_RMRXSTO; | |
2160 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
b0c5943f MC |
2161 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
2162 | } | |
2163 | ||
2164 | val = tr32(TG3_CPMU_EEE_MODE); | |
2165 | tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
2166 | } | |
2167 | ||
1da177e4 LT |
2168 | static int tg3_wait_macro_done(struct tg3 *tp) |
2169 | { | |
2170 | int limit = 100; | |
2171 | ||
2172 | while (limit--) { | |
2173 | u32 tmp32; | |
2174 | ||
f08aa1a8 | 2175 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
2176 | if ((tmp32 & 0x1000) == 0) |
2177 | break; | |
2178 | } | |
2179 | } | |
d4675b52 | 2180 | if (limit < 0) |
1da177e4 LT |
2181 | return -EBUSY; |
2182 | ||
2183 | return 0; | |
2184 | } | |
2185 | ||
2186 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
2187 | { | |
2188 | static const u32 test_pat[4][6] = { | |
2189 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
2190 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
2191 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
2192 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
2193 | }; | |
2194 | int chan; | |
2195 | ||
2196 | for (chan = 0; chan < 4; chan++) { | |
2197 | int i; | |
2198 | ||
2199 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2200 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2201 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
2202 | |
2203 | for (i = 0; i < 6; i++) | |
2204 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
2205 | test_pat[chan][i]); | |
2206 | ||
f08aa1a8 | 2207 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
2208 | if (tg3_wait_macro_done(tp)) { |
2209 | *resetp = 1; | |
2210 | return -EBUSY; | |
2211 | } | |
2212 | ||
2213 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2214 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2215 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
2216 | if (tg3_wait_macro_done(tp)) { |
2217 | *resetp = 1; | |
2218 | return -EBUSY; | |
2219 | } | |
2220 | ||
f08aa1a8 | 2221 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
2222 | if (tg3_wait_macro_done(tp)) { |
2223 | *resetp = 1; | |
2224 | return -EBUSY; | |
2225 | } | |
2226 | ||
2227 | for (i = 0; i < 6; i += 2) { | |
2228 | u32 low, high; | |
2229 | ||
2230 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
2231 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
2232 | tg3_wait_macro_done(tp)) { | |
2233 | *resetp = 1; | |
2234 | return -EBUSY; | |
2235 | } | |
2236 | low &= 0x7fff; | |
2237 | high &= 0x000f; | |
2238 | if (low != test_pat[chan][i] || | |
2239 | high != test_pat[chan][i+1]) { | |
2240 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
2241 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
2242 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
2243 | ||
2244 | return -EBUSY; | |
2245 | } | |
2246 | } | |
2247 | } | |
2248 | ||
2249 | return 0; | |
2250 | } | |
2251 | ||
2252 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
2253 | { | |
2254 | int chan; | |
2255 | ||
2256 | for (chan = 0; chan < 4; chan++) { | |
2257 | int i; | |
2258 | ||
2259 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2260 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2261 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
2262 | for (i = 0; i < 6; i++) |
2263 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 2264 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
2265 | if (tg3_wait_macro_done(tp)) |
2266 | return -EBUSY; | |
2267 | } | |
2268 | ||
2269 | return 0; | |
2270 | } | |
2271 | ||
2272 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
2273 | { | |
2274 | u32 reg32, phy9_orig; | |
2275 | int retries, do_phy_reset, err; | |
2276 | ||
2277 | retries = 10; | |
2278 | do_phy_reset = 1; | |
2279 | do { | |
2280 | if (do_phy_reset) { | |
2281 | err = tg3_bmcr_reset(tp); | |
2282 | if (err) | |
2283 | return err; | |
2284 | do_phy_reset = 0; | |
2285 | } | |
2286 | ||
2287 | /* Disable transmitter and interrupt. */ | |
2288 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
2289 | continue; | |
2290 | ||
2291 | reg32 |= 0x3000; | |
2292 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2293 | ||
2294 | /* Set full-duplex, 1000 mbps. */ | |
2295 | tg3_writephy(tp, MII_BMCR, | |
221c5637 | 2296 | BMCR_FULLDPLX | BMCR_SPEED1000); |
1da177e4 LT |
2297 | |
2298 | /* Set to master mode. */ | |
221c5637 | 2299 | if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) |
1da177e4 LT |
2300 | continue; |
2301 | ||
221c5637 MC |
2302 | tg3_writephy(tp, MII_CTRL1000, |
2303 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
1da177e4 | 2304 | |
1d36ba45 MC |
2305 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
2306 | if (err) | |
2307 | return err; | |
1da177e4 LT |
2308 | |
2309 | /* Block the PHY control access. */ | |
6ee7c0a0 | 2310 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
2311 | |
2312 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
2313 | if (!err) | |
2314 | break; | |
2315 | } while (--retries); | |
2316 | ||
2317 | err = tg3_phy_reset_chanpat(tp); | |
2318 | if (err) | |
2319 | return err; | |
2320 | ||
6ee7c0a0 | 2321 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
2322 | |
2323 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 2324 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 | 2325 | |
1d36ba45 | 2326 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2327 | |
221c5637 | 2328 | tg3_writephy(tp, MII_CTRL1000, phy9_orig); |
1da177e4 LT |
2329 | |
2330 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
2331 | reg32 &= ~0x3000; | |
2332 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2333 | } else if (!err) | |
2334 | err = -EBUSY; | |
2335 | ||
2336 | return err; | |
2337 | } | |
2338 | ||
2339 | /* This will reset the tigon3 PHY if there is no valid | |
2340 | * link unless the FORCE argument is non-zero. | |
2341 | */ | |
2342 | static int tg3_phy_reset(struct tg3 *tp) | |
2343 | { | |
f833c4c1 | 2344 | u32 val, cpmuctrl; |
1da177e4 LT |
2345 | int err; |
2346 | ||
60189ddf | 2347 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2348 | val = tr32(GRC_MISC_CFG); |
2349 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
2350 | udelay(40); | |
2351 | } | |
f833c4c1 MC |
2352 | err = tg3_readphy(tp, MII_BMSR, &val); |
2353 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
2354 | if (err != 0) |
2355 | return -EBUSY; | |
2356 | ||
c8e1e82b MC |
2357 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
2358 | netif_carrier_off(tp->dev); | |
2359 | tg3_link_report(tp); | |
2360 | } | |
2361 | ||
1da177e4 LT |
2362 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2363 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2364 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2365 | err = tg3_phy_reset_5703_4_5(tp); | |
2366 | if (err) | |
2367 | return err; | |
2368 | goto out; | |
2369 | } | |
2370 | ||
b2a5c19c MC |
2371 | cpmuctrl = 0; |
2372 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2373 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2374 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2375 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2376 | tw32(TG3_CPMU_CTRL, | |
2377 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2378 | } | |
2379 | ||
1da177e4 LT |
2380 | err = tg3_bmcr_reset(tp); |
2381 | if (err) | |
2382 | return err; | |
2383 | ||
b2a5c19c | 2384 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2385 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2386 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2387 | |
2388 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2389 | } | |
2390 | ||
bcb37f6c MC |
2391 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2392 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2393 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2394 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2395 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2396 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2397 | udelay(40); | |
2398 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2399 | } | |
2400 | } | |
2401 | ||
63c3a66f | 2402 | if (tg3_flag(tp, 5717_PLUS) && |
f07e9af3 | 2403 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2404 | return 0; |
2405 | ||
b2a5c19c MC |
2406 | tg3_phy_apply_otp(tp); |
2407 | ||
f07e9af3 | 2408 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2409 | tg3_phy_toggle_apd(tp, true); |
2410 | else | |
2411 | tg3_phy_toggle_apd(tp, false); | |
2412 | ||
1da177e4 | 2413 | out: |
1d36ba45 MC |
2414 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && |
2415 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
6ee7c0a0 MC |
2416 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2417 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1d36ba45 | 2418 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2419 | } |
1d36ba45 | 2420 | |
f07e9af3 | 2421 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2422 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2423 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2424 | } |
1d36ba45 | 2425 | |
f07e9af3 | 2426 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1d36ba45 MC |
2427 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2428 | tg3_phydsp_write(tp, 0x000a, 0x310b); | |
2429 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2430 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
2431 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2432 | } | |
f07e9af3 | 2433 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
1d36ba45 MC |
2434 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2435 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
2436 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { | |
2437 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2438 | tg3_writephy(tp, MII_TG3_TEST1, | |
2439 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2440 | } else | |
2441 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
2442 | ||
2443 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2444 | } | |
c424cb24 | 2445 | } |
1d36ba45 | 2446 | |
1da177e4 LT |
2447 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2448 | /* support jumbo frames */ | |
79eb6904 | 2449 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 | 2450 | /* Cannot do read-modify-write on 5401 */ |
b4bd2929 | 2451 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
63c3a66f | 2452 | } else if (tg3_flag(tp, JUMBO_CAPABLE)) { |
1da177e4 | 2453 | /* Set bit 14 with read-modify-write to preserve other bits */ |
15ee95c3 MC |
2454 | err = tg3_phy_auxctl_read(tp, |
2455 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2456 | if (!err) | |
b4bd2929 MC |
2457 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
2458 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); | |
1da177e4 LT |
2459 | } |
2460 | ||
2461 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2462 | * jumbo frames transmission. | |
2463 | */ | |
63c3a66f | 2464 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
f833c4c1 | 2465 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2466 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2467 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2468 | } |
2469 | ||
715116a1 | 2470 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2471 | /* adjust output voltage */ |
535ef6e1 | 2472 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2473 | } |
2474 | ||
9ef8ca99 | 2475 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2476 | tg3_phy_set_wirespeed(tp); |
2477 | return 0; | |
2478 | } | |
2479 | ||
3a1e19d3 MC |
2480 | #define TG3_GPIO_MSG_DRVR_PRES 0x00000001 |
2481 | #define TG3_GPIO_MSG_NEED_VAUX 0x00000002 | |
2482 | #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \ | |
2483 | TG3_GPIO_MSG_NEED_VAUX) | |
2484 | #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \ | |
2485 | ((TG3_GPIO_MSG_DRVR_PRES << 0) | \ | |
2486 | (TG3_GPIO_MSG_DRVR_PRES << 4) | \ | |
2487 | (TG3_GPIO_MSG_DRVR_PRES << 8) | \ | |
2488 | (TG3_GPIO_MSG_DRVR_PRES << 12)) | |
2489 | ||
2490 | #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \ | |
2491 | ((TG3_GPIO_MSG_NEED_VAUX << 0) | \ | |
2492 | (TG3_GPIO_MSG_NEED_VAUX << 4) | \ | |
2493 | (TG3_GPIO_MSG_NEED_VAUX << 8) | \ | |
2494 | (TG3_GPIO_MSG_NEED_VAUX << 12)) | |
2495 | ||
2496 | static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) | |
2497 | { | |
2498 | u32 status, shift; | |
2499 | ||
2500 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2501 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2502 | status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); | |
2503 | else | |
2504 | status = tr32(TG3_CPMU_DRV_STATUS); | |
2505 | ||
2506 | shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; | |
2507 | status &= ~(TG3_GPIO_MSG_MASK << shift); | |
2508 | status |= (newstat << shift); | |
2509 | ||
2510 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2511 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2512 | tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); | |
2513 | else | |
2514 | tw32(TG3_CPMU_DRV_STATUS, status); | |
2515 | ||
2516 | return status >> TG3_APE_GPIO_MSG_SHIFT; | |
2517 | } | |
2518 | ||
520b2756 MC |
2519 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) |
2520 | { | |
2521 | if (!tg3_flag(tp, IS_NIC)) | |
2522 | return 0; | |
2523 | ||
3a1e19d3 MC |
2524 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2525 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2526 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
2527 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2528 | return -EIO; | |
520b2756 | 2529 | |
3a1e19d3 MC |
2530 | tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); |
2531 | ||
2532 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2533 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2534 | ||
2535 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); | |
2536 | } else { | |
2537 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2538 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2539 | } | |
6f5c8f83 | 2540 | |
520b2756 MC |
2541 | return 0; |
2542 | } | |
2543 | ||
2544 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) | |
2545 | { | |
2546 | u32 grc_local_ctrl; | |
2547 | ||
2548 | if (!tg3_flag(tp, IS_NIC) || | |
2549 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2550 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) | |
2551 | return; | |
2552 | ||
2553 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; | |
2554 | ||
2555 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2556 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2557 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2558 | ||
2559 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2560 | grc_local_ctrl, | |
2561 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2562 | ||
2563 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2564 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2565 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2566 | } | |
2567 | ||
2568 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) | |
2569 | { | |
2570 | if (!tg3_flag(tp, IS_NIC)) | |
2571 | return; | |
2572 | ||
2573 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2574 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2575 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2576 | (GRC_LCLCTRL_GPIO_OE0 | | |
2577 | GRC_LCLCTRL_GPIO_OE1 | | |
2578 | GRC_LCLCTRL_GPIO_OE2 | | |
2579 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2580 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2581 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2582 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
2583 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
2584 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
2585 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2586 | GRC_LCLCTRL_GPIO_OE1 | | |
2587 | GRC_LCLCTRL_GPIO_OE2 | | |
2588 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2589 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2590 | tp->grc_local_ctrl; | |
2591 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2592 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2593 | ||
2594 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2595 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2596 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2597 | ||
2598 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2599 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2600 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2601 | } else { | |
2602 | u32 no_gpio2; | |
2603 | u32 grc_local_ctrl = 0; | |
2604 | ||
2605 | /* Workaround to prevent overdrawing Amps. */ | |
2606 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
2607 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
2608 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2609 | grc_local_ctrl, | |
2610 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2611 | } | |
2612 | ||
2613 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
2614 | no_gpio2 = tp->nic_sram_data_cfg & | |
2615 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2616 | ||
2617 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
2618 | GRC_LCLCTRL_GPIO_OE1 | | |
2619 | GRC_LCLCTRL_GPIO_OE2 | | |
2620 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2621 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2622 | if (no_gpio2) { | |
2623 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2624 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2625 | } | |
2626 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2627 | tp->grc_local_ctrl | grc_local_ctrl, | |
2628 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2629 | ||
2630 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2631 | ||
2632 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2633 | tp->grc_local_ctrl | grc_local_ctrl, | |
2634 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2635 | ||
2636 | if (!no_gpio2) { | |
2637 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2638 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2639 | tp->grc_local_ctrl | grc_local_ctrl, | |
2640 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2641 | } | |
2642 | } | |
3a1e19d3 MC |
2643 | } |
2644 | ||
cd0d7228 | 2645 | static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) |
3a1e19d3 MC |
2646 | { |
2647 | u32 msg = 0; | |
2648 | ||
2649 | /* Serialize power state transitions */ | |
2650 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2651 | return; | |
2652 | ||
cd0d7228 | 2653 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) |
3a1e19d3 MC |
2654 | msg = TG3_GPIO_MSG_NEED_VAUX; |
2655 | ||
2656 | msg = tg3_set_function_status(tp, msg); | |
2657 | ||
2658 | if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK) | |
2659 | goto done; | |
6f5c8f83 | 2660 | |
3a1e19d3 MC |
2661 | if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK) |
2662 | tg3_pwrsrc_switch_to_vaux(tp); | |
2663 | else | |
2664 | tg3_pwrsrc_die_with_vmain(tp); | |
2665 | ||
2666 | done: | |
6f5c8f83 | 2667 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); |
520b2756 MC |
2668 | } |
2669 | ||
cd0d7228 | 2670 | static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) |
1da177e4 | 2671 | { |
683644b7 | 2672 | bool need_vaux = false; |
1da177e4 | 2673 | |
334355aa | 2674 | /* The GPIOs do something completely different on 57765. */ |
55086ad9 | 2675 | if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) |
1da177e4 LT |
2676 | return; |
2677 | ||
3a1e19d3 MC |
2678 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2679 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2680 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
cd0d7228 MC |
2681 | tg3_frob_aux_power_5717(tp, include_wol ? |
2682 | tg3_flag(tp, WOL_ENABLE) != 0 : 0); | |
3a1e19d3 MC |
2683 | return; |
2684 | } | |
2685 | ||
2686 | if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { | |
8c2dc7e1 MC |
2687 | struct net_device *dev_peer; |
2688 | ||
2689 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2690 | |
bc1c7567 | 2691 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2692 | if (dev_peer) { |
2693 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2694 | ||
63c3a66f | 2695 | if (tg3_flag(tp_peer, INIT_COMPLETE)) |
683644b7 MC |
2696 | return; |
2697 | ||
cd0d7228 | 2698 | if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) || |
63c3a66f | 2699 | tg3_flag(tp_peer, ENABLE_ASF)) |
683644b7 MC |
2700 | need_vaux = true; |
2701 | } | |
1da177e4 LT |
2702 | } |
2703 | ||
cd0d7228 MC |
2704 | if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || |
2705 | tg3_flag(tp, ENABLE_ASF)) | |
683644b7 MC |
2706 | need_vaux = true; |
2707 | ||
520b2756 MC |
2708 | if (need_vaux) |
2709 | tg3_pwrsrc_switch_to_vaux(tp); | |
2710 | else | |
2711 | tg3_pwrsrc_die_with_vmain(tp); | |
1da177e4 LT |
2712 | } |
2713 | ||
e8f3f6ca MC |
2714 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2715 | { | |
2716 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2717 | return 1; | |
79eb6904 | 2718 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2719 | if (speed != SPEED_10) |
2720 | return 1; | |
2721 | } else if (speed == SPEED_10) | |
2722 | return 1; | |
2723 | ||
2724 | return 0; | |
2725 | } | |
2726 | ||
0a459aac | 2727 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2728 | { |
ce057f01 MC |
2729 | u32 val; |
2730 | ||
f07e9af3 | 2731 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2732 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2733 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2734 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2735 | ||
2736 | sg_dig_ctrl |= | |
2737 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2738 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2739 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2740 | } | |
3f7045c1 | 2741 | return; |
5129724a | 2742 | } |
3f7045c1 | 2743 | |
60189ddf | 2744 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2745 | tg3_bmcr_reset(tp); |
2746 | val = tr32(GRC_MISC_CFG); | |
2747 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2748 | udelay(40); | |
2749 | return; | |
f07e9af3 | 2750 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2751 | u32 phytest; |
2752 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2753 | u32 phy; | |
2754 | ||
2755 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2756 | tg3_writephy(tp, MII_BMCR, | |
2757 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2758 | ||
2759 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2760 | phytest | MII_TG3_FET_SHADOW_EN); | |
2761 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2762 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2763 | tg3_writephy(tp, | |
2764 | MII_TG3_FET_SHDW_AUXMODE4, | |
2765 | phy); | |
2766 | } | |
2767 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2768 | } | |
2769 | return; | |
0a459aac | 2770 | } else if (do_low_power) { |
715116a1 MC |
2771 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2772 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac | 2773 | |
b4bd2929 MC |
2774 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
2775 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2776 | MII_TG3_AUXCTL_PCTL_VREG_11V; | |
2777 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); | |
715116a1 | 2778 | } |
3f7045c1 | 2779 | |
15c3b696 MC |
2780 | /* The PHY should not be powered down on some chips because |
2781 | * of bugs. | |
2782 | */ | |
2783 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2784 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2785 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
085f1afc MC |
2786 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) || |
2787 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | |
2788 | !tp->pci_fn)) | |
15c3b696 | 2789 | return; |
ce057f01 | 2790 | |
bcb37f6c MC |
2791 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2792 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2793 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2794 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2795 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2796 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2797 | } | |
2798 | ||
15c3b696 MC |
2799 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2800 | } | |
2801 | ||
ffbcfed4 MC |
2802 | /* tp->lock is held. */ |
2803 | static int tg3_nvram_lock(struct tg3 *tp) | |
2804 | { | |
63c3a66f | 2805 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2806 | int i; |
2807 | ||
2808 | if (tp->nvram_lock_cnt == 0) { | |
2809 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2810 | for (i = 0; i < 8000; i++) { | |
2811 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2812 | break; | |
2813 | udelay(20); | |
2814 | } | |
2815 | if (i == 8000) { | |
2816 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2817 | return -ENODEV; | |
2818 | } | |
2819 | } | |
2820 | tp->nvram_lock_cnt++; | |
2821 | } | |
2822 | return 0; | |
2823 | } | |
2824 | ||
2825 | /* tp->lock is held. */ | |
2826 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2827 | { | |
63c3a66f | 2828 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2829 | if (tp->nvram_lock_cnt > 0) |
2830 | tp->nvram_lock_cnt--; | |
2831 | if (tp->nvram_lock_cnt == 0) | |
2832 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2833 | } | |
2834 | } | |
2835 | ||
2836 | /* tp->lock is held. */ | |
2837 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2838 | { | |
63c3a66f | 2839 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2840 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2841 | ||
2842 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2843 | } | |
2844 | } | |
2845 | ||
2846 | /* tp->lock is held. */ | |
2847 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2848 | { | |
63c3a66f | 2849 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2850 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2851 | ||
2852 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2853 | } | |
2854 | } | |
2855 | ||
2856 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2857 | u32 offset, u32 *val) | |
2858 | { | |
2859 | u32 tmp; | |
2860 | int i; | |
2861 | ||
2862 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2863 | return -EINVAL; | |
2864 | ||
2865 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2866 | EEPROM_ADDR_DEVID_MASK | | |
2867 | EEPROM_ADDR_READ); | |
2868 | tw32(GRC_EEPROM_ADDR, | |
2869 | tmp | | |
2870 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2871 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2872 | EEPROM_ADDR_ADDR_MASK) | | |
2873 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2874 | ||
2875 | for (i = 0; i < 1000; i++) { | |
2876 | tmp = tr32(GRC_EEPROM_ADDR); | |
2877 | ||
2878 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2879 | break; | |
2880 | msleep(1); | |
2881 | } | |
2882 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2883 | return -EBUSY; | |
2884 | ||
62cedd11 MC |
2885 | tmp = tr32(GRC_EEPROM_DATA); |
2886 | ||
2887 | /* | |
2888 | * The data will always be opposite the native endian | |
2889 | * format. Perform a blind byteswap to compensate. | |
2890 | */ | |
2891 | *val = swab32(tmp); | |
2892 | ||
ffbcfed4 MC |
2893 | return 0; |
2894 | } | |
2895 | ||
2896 | #define NVRAM_CMD_TIMEOUT 10000 | |
2897 | ||
2898 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2899 | { | |
2900 | int i; | |
2901 | ||
2902 | tw32(NVRAM_CMD, nvram_cmd); | |
2903 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2904 | udelay(10); | |
2905 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2906 | udelay(10); | |
2907 | break; | |
2908 | } | |
2909 | } | |
2910 | ||
2911 | if (i == NVRAM_CMD_TIMEOUT) | |
2912 | return -EBUSY; | |
2913 | ||
2914 | return 0; | |
2915 | } | |
2916 | ||
2917 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2918 | { | |
63c3a66f JP |
2919 | if (tg3_flag(tp, NVRAM) && |
2920 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2921 | tg3_flag(tp, FLASH) && | |
2922 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2923 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2924 | ||
2925 | addr = ((addr / tp->nvram_pagesize) << | |
2926 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2927 | (addr % tp->nvram_pagesize); | |
2928 | ||
2929 | return addr; | |
2930 | } | |
2931 | ||
2932 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2933 | { | |
63c3a66f JP |
2934 | if (tg3_flag(tp, NVRAM) && |
2935 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2936 | tg3_flag(tp, FLASH) && | |
2937 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2938 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2939 | ||
2940 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2941 | tp->nvram_pagesize) + | |
2942 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2943 | ||
2944 | return addr; | |
2945 | } | |
2946 | ||
e4f34110 MC |
2947 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2948 | * the byteswapping settings for all other register accesses. | |
2949 | * tg3 devices are BE devices, so on a BE machine, the data | |
2950 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2951 | * machine, the 32-bit value will be byteswapped. | |
2952 | */ | |
ffbcfed4 MC |
2953 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2954 | { | |
2955 | int ret; | |
2956 | ||
63c3a66f | 2957 | if (!tg3_flag(tp, NVRAM)) |
ffbcfed4 MC |
2958 | return tg3_nvram_read_using_eeprom(tp, offset, val); |
2959 | ||
2960 | offset = tg3_nvram_phys_addr(tp, offset); | |
2961 | ||
2962 | if (offset > NVRAM_ADDR_MSK) | |
2963 | return -EINVAL; | |
2964 | ||
2965 | ret = tg3_nvram_lock(tp); | |
2966 | if (ret) | |
2967 | return ret; | |
2968 | ||
2969 | tg3_enable_nvram_access(tp); | |
2970 | ||
2971 | tw32(NVRAM_ADDR, offset); | |
2972 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2973 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2974 | ||
2975 | if (ret == 0) | |
e4f34110 | 2976 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2977 | |
2978 | tg3_disable_nvram_access(tp); | |
2979 | ||
2980 | tg3_nvram_unlock(tp); | |
2981 | ||
2982 | return ret; | |
2983 | } | |
2984 | ||
a9dc529d MC |
2985 | /* Ensures NVRAM data is in bytestream format. */ |
2986 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2987 | { |
2988 | u32 v; | |
a9dc529d | 2989 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2990 | if (!res) |
a9dc529d | 2991 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2992 | return res; |
2993 | } | |
2994 | ||
dbe9b92a MC |
2995 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
2996 | u32 offset, u32 len, u8 *buf) | |
2997 | { | |
2998 | int i, j, rc = 0; | |
2999 | u32 val; | |
3000 | ||
3001 | for (i = 0; i < len; i += 4) { | |
3002 | u32 addr; | |
3003 | __be32 data; | |
3004 | ||
3005 | addr = offset + i; | |
3006 | ||
3007 | memcpy(&data, buf + i, 4); | |
3008 | ||
3009 | /* | |
3010 | * The SEEPROM interface expects the data to always be opposite | |
3011 | * the native endian format. We accomplish this by reversing | |
3012 | * all the operations that would have been performed on the | |
3013 | * data from a call to tg3_nvram_read_be32(). | |
3014 | */ | |
3015 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
3016 | ||
3017 | val = tr32(GRC_EEPROM_ADDR); | |
3018 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
3019 | ||
3020 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
3021 | EEPROM_ADDR_READ); | |
3022 | tw32(GRC_EEPROM_ADDR, val | | |
3023 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
3024 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
3025 | EEPROM_ADDR_START | | |
3026 | EEPROM_ADDR_WRITE); | |
3027 | ||
3028 | for (j = 0; j < 1000; j++) { | |
3029 | val = tr32(GRC_EEPROM_ADDR); | |
3030 | ||
3031 | if (val & EEPROM_ADDR_COMPLETE) | |
3032 | break; | |
3033 | msleep(1); | |
3034 | } | |
3035 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
3036 | rc = -EBUSY; | |
3037 | break; | |
3038 | } | |
3039 | } | |
3040 | ||
3041 | return rc; | |
3042 | } | |
3043 | ||
3044 | /* offset and length are dword aligned */ | |
3045 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
3046 | u8 *buf) | |
3047 | { | |
3048 | int ret = 0; | |
3049 | u32 pagesize = tp->nvram_pagesize; | |
3050 | u32 pagemask = pagesize - 1; | |
3051 | u32 nvram_cmd; | |
3052 | u8 *tmp; | |
3053 | ||
3054 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
3055 | if (tmp == NULL) | |
3056 | return -ENOMEM; | |
3057 | ||
3058 | while (len) { | |
3059 | int j; | |
3060 | u32 phy_addr, page_off, size; | |
3061 | ||
3062 | phy_addr = offset & ~pagemask; | |
3063 | ||
3064 | for (j = 0; j < pagesize; j += 4) { | |
3065 | ret = tg3_nvram_read_be32(tp, phy_addr + j, | |
3066 | (__be32 *) (tmp + j)); | |
3067 | if (ret) | |
3068 | break; | |
3069 | } | |
3070 | if (ret) | |
3071 | break; | |
3072 | ||
3073 | page_off = offset & pagemask; | |
3074 | size = pagesize; | |
3075 | if (len < size) | |
3076 | size = len; | |
3077 | ||
3078 | len -= size; | |
3079 | ||
3080 | memcpy(tmp + page_off, buf, size); | |
3081 | ||
3082 | offset = offset + (pagesize - page_off); | |
3083 | ||
3084 | tg3_enable_nvram_access(tp); | |
3085 | ||
3086 | /* | |
3087 | * Before we can erase the flash page, we need | |
3088 | * to issue a special "write enable" command. | |
3089 | */ | |
3090 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3091 | ||
3092 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
3093 | break; | |
3094 | ||
3095 | /* Erase the target page */ | |
3096 | tw32(NVRAM_ADDR, phy_addr); | |
3097 | ||
3098 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
3099 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
3100 | ||
3101 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
3102 | break; | |
3103 | ||
3104 | /* Issue another write enable to start the write. */ | |
3105 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3106 | ||
3107 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
3108 | break; | |
3109 | ||
3110 | for (j = 0; j < pagesize; j += 4) { | |
3111 | __be32 data; | |
3112 | ||
3113 | data = *((__be32 *) (tmp + j)); | |
3114 | ||
3115 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
3116 | ||
3117 | tw32(NVRAM_ADDR, phy_addr + j); | |
3118 | ||
3119 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
3120 | NVRAM_CMD_WR; | |
3121 | ||
3122 | if (j == 0) | |
3123 | nvram_cmd |= NVRAM_CMD_FIRST; | |
3124 | else if (j == (pagesize - 4)) | |
3125 | nvram_cmd |= NVRAM_CMD_LAST; | |
3126 | ||
3127 | ret = tg3_nvram_exec_cmd(tp, nvram_cmd); | |
3128 | if (ret) | |
3129 | break; | |
3130 | } | |
3131 | if (ret) | |
3132 | break; | |
3133 | } | |
3134 | ||
3135 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3136 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
3137 | ||
3138 | kfree(tmp); | |
3139 | ||
3140 | return ret; | |
3141 | } | |
3142 | ||
3143 | /* offset and length are dword aligned */ | |
3144 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
3145 | u8 *buf) | |
3146 | { | |
3147 | int i, ret = 0; | |
3148 | ||
3149 | for (i = 0; i < len; i += 4, offset += 4) { | |
3150 | u32 page_off, phy_addr, nvram_cmd; | |
3151 | __be32 data; | |
3152 | ||
3153 | memcpy(&data, buf + i, 4); | |
3154 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
3155 | ||
3156 | page_off = offset % tp->nvram_pagesize; | |
3157 | ||
3158 | phy_addr = tg3_nvram_phys_addr(tp, offset); | |
3159 | ||
dbe9b92a MC |
3160 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; |
3161 | ||
3162 | if (page_off == 0 || i == 0) | |
3163 | nvram_cmd |= NVRAM_CMD_FIRST; | |
3164 | if (page_off == (tp->nvram_pagesize - 4)) | |
3165 | nvram_cmd |= NVRAM_CMD_LAST; | |
3166 | ||
3167 | if (i == (len - 4)) | |
3168 | nvram_cmd |= NVRAM_CMD_LAST; | |
3169 | ||
42278224 MC |
3170 | if ((nvram_cmd & NVRAM_CMD_FIRST) || |
3171 | !tg3_flag(tp, FLASH) || | |
3172 | !tg3_flag(tp, 57765_PLUS)) | |
3173 | tw32(NVRAM_ADDR, phy_addr); | |
3174 | ||
dbe9b92a MC |
3175 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
3176 | !tg3_flag(tp, 5755_PLUS) && | |
3177 | (tp->nvram_jedecnum == JEDEC_ST) && | |
3178 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
3179 | u32 cmd; | |
3180 | ||
3181 | cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3182 | ret = tg3_nvram_exec_cmd(tp, cmd); | |
3183 | if (ret) | |
3184 | break; | |
3185 | } | |
3186 | if (!tg3_flag(tp, FLASH)) { | |
3187 | /* We always do complete word writes to eeprom. */ | |
3188 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
3189 | } | |
3190 | ||
3191 | ret = tg3_nvram_exec_cmd(tp, nvram_cmd); | |
3192 | if (ret) | |
3193 | break; | |
3194 | } | |
3195 | return ret; | |
3196 | } | |
3197 | ||
3198 | /* offset and length are dword aligned */ | |
3199 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
3200 | { | |
3201 | int ret; | |
3202 | ||
3203 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { | |
3204 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & | |
3205 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
3206 | udelay(40); | |
3207 | } | |
3208 | ||
3209 | if (!tg3_flag(tp, NVRAM)) { | |
3210 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
3211 | } else { | |
3212 | u32 grc_mode; | |
3213 | ||
3214 | ret = tg3_nvram_lock(tp); | |
3215 | if (ret) | |
3216 | return ret; | |
3217 | ||
3218 | tg3_enable_nvram_access(tp); | |
3219 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) | |
3220 | tw32(NVRAM_WRITE1, 0x406); | |
3221 | ||
3222 | grc_mode = tr32(GRC_MODE); | |
3223 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
3224 | ||
3225 | if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { | |
3226 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
3227 | buf); | |
3228 | } else { | |
3229 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, | |
3230 | buf); | |
3231 | } | |
3232 | ||
3233 | grc_mode = tr32(GRC_MODE); | |
3234 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
3235 | ||
3236 | tg3_disable_nvram_access(tp); | |
3237 | tg3_nvram_unlock(tp); | |
3238 | } | |
3239 | ||
3240 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { | |
3241 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
3242 | udelay(40); | |
3243 | } | |
3244 | ||
3245 | return ret; | |
3246 | } | |
3247 | ||
997b4f13 MC |
3248 | #define RX_CPU_SCRATCH_BASE 0x30000 |
3249 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
3250 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
3251 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
3252 | ||
3253 | /* tp->lock is held. */ | |
3254 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
3255 | { | |
3256 | int i; | |
3257 | ||
3258 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); | |
3259 | ||
3260 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
3261 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
3262 | ||
3263 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
3264 | return 0; | |
3265 | } | |
3266 | if (offset == RX_CPU_BASE) { | |
3267 | for (i = 0; i < 10000; i++) { | |
3268 | tw32(offset + CPU_STATE, 0xffffffff); | |
3269 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
3270 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
3271 | break; | |
3272 | } | |
3273 | ||
3274 | tw32(offset + CPU_STATE, 0xffffffff); | |
3275 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
3276 | udelay(10); | |
3277 | } else { | |
3278 | for (i = 0; i < 10000; i++) { | |
3279 | tw32(offset + CPU_STATE, 0xffffffff); | |
3280 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
3281 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
3282 | break; | |
3283 | } | |
3284 | } | |
3285 | ||
3286 | if (i >= 10000) { | |
3287 | netdev_err(tp->dev, "%s timed out, %s CPU\n", | |
3288 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
3289 | return -ENODEV; | |
3290 | } | |
3291 | ||
3292 | /* Clear firmware's nvram arbitration. */ | |
3293 | if (tg3_flag(tp, NVRAM)) | |
3294 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
3295 | return 0; | |
3296 | } | |
3297 | ||
3298 | struct fw_info { | |
3299 | unsigned int fw_base; | |
3300 | unsigned int fw_len; | |
3301 | const __be32 *fw_data; | |
3302 | }; | |
3303 | ||
3304 | /* tp->lock is held. */ | |
3305 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, | |
3306 | u32 cpu_scratch_base, int cpu_scratch_size, | |
3307 | struct fw_info *info) | |
3308 | { | |
3309 | int err, lock_err, i; | |
3310 | void (*write_op)(struct tg3 *, u32, u32); | |
3311 | ||
3312 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { | |
3313 | netdev_err(tp->dev, | |
3314 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
3315 | __func__); | |
3316 | return -EINVAL; | |
3317 | } | |
3318 | ||
3319 | if (tg3_flag(tp, 5705_PLUS)) | |
3320 | write_op = tg3_write_mem; | |
3321 | else | |
3322 | write_op = tg3_write_indirect_reg32; | |
3323 | ||
3324 | /* It is possible that bootcode is still loading at this point. | |
3325 | * Get the nvram lock first before halting the cpu. | |
3326 | */ | |
3327 | lock_err = tg3_nvram_lock(tp); | |
3328 | err = tg3_halt_cpu(tp, cpu_base); | |
3329 | if (!lock_err) | |
3330 | tg3_nvram_unlock(tp); | |
3331 | if (err) | |
3332 | goto out; | |
3333 | ||
3334 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
3335 | write_op(tp, cpu_scratch_base + i, 0); | |
3336 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3337 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
3338 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) | |
3339 | write_op(tp, (cpu_scratch_base + | |
3340 | (info->fw_base & 0xffff) + | |
3341 | (i * sizeof(u32))), | |
3342 | be32_to_cpu(info->fw_data[i])); | |
3343 | ||
3344 | err = 0; | |
3345 | ||
3346 | out: | |
3347 | return err; | |
3348 | } | |
3349 | ||
3350 | /* tp->lock is held. */ | |
3351 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
3352 | { | |
3353 | struct fw_info info; | |
3354 | const __be32 *fw_data; | |
3355 | int err, i; | |
3356 | ||
3357 | fw_data = (void *)tp->fw->data; | |
3358 | ||
3359 | /* Firmware blob starts with version numbers, followed by | |
3360 | start address and length. We are setting complete length. | |
3361 | length = end_address_of_bss - start_address_of_text. | |
3362 | Remainder is the blob to be loaded contiguously | |
3363 | from start address. */ | |
3364 | ||
3365 | info.fw_base = be32_to_cpu(fw_data[1]); | |
3366 | info.fw_len = tp->fw->size - 12; | |
3367 | info.fw_data = &fw_data[3]; | |
3368 | ||
3369 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
3370 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
3371 | &info); | |
3372 | if (err) | |
3373 | return err; | |
3374 | ||
3375 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
3376 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
3377 | &info); | |
3378 | if (err) | |
3379 | return err; | |
3380 | ||
3381 | /* Now startup only the RX cpu. */ | |
3382 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3383 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
3384 | ||
3385 | for (i = 0; i < 5; i++) { | |
3386 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) | |
3387 | break; | |
3388 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3389 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
3390 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
3391 | udelay(1000); | |
3392 | } | |
3393 | if (i >= 5) { | |
3394 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " | |
3395 | "should be %08x\n", __func__, | |
3396 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); | |
3397 | return -ENODEV; | |
3398 | } | |
3399 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3400 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
3401 | ||
3402 | return 0; | |
3403 | } | |
3404 | ||
3405 | /* tp->lock is held. */ | |
3406 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
3407 | { | |
3408 | struct fw_info info; | |
3409 | const __be32 *fw_data; | |
3410 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; | |
3411 | int err, i; | |
3412 | ||
3413 | if (tg3_flag(tp, HW_TSO_1) || | |
3414 | tg3_flag(tp, HW_TSO_2) || | |
3415 | tg3_flag(tp, HW_TSO_3)) | |
3416 | return 0; | |
3417 | ||
3418 | fw_data = (void *)tp->fw->data; | |
3419 | ||
3420 | /* Firmware blob starts with version numbers, followed by | |
3421 | start address and length. We are setting complete length. | |
3422 | length = end_address_of_bss - start_address_of_text. | |
3423 | Remainder is the blob to be loaded contiguously | |
3424 | from start address. */ | |
3425 | ||
3426 | info.fw_base = be32_to_cpu(fw_data[1]); | |
3427 | cpu_scratch_size = tp->fw_len; | |
3428 | info.fw_len = tp->fw->size - 12; | |
3429 | info.fw_data = &fw_data[3]; | |
3430 | ||
3431 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
3432 | cpu_base = RX_CPU_BASE; | |
3433 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
3434 | } else { | |
3435 | cpu_base = TX_CPU_BASE; | |
3436 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
3437 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
3438 | } | |
3439 | ||
3440 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
3441 | cpu_scratch_base, cpu_scratch_size, | |
3442 | &info); | |
3443 | if (err) | |
3444 | return err; | |
3445 | ||
3446 | /* Now startup the cpu. */ | |
3447 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3448 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
3449 | ||
3450 | for (i = 0; i < 5; i++) { | |
3451 | if (tr32(cpu_base + CPU_PC) == info.fw_base) | |
3452 | break; | |
3453 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3454 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
3455 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
3456 | udelay(1000); | |
3457 | } | |
3458 | if (i >= 5) { | |
3459 | netdev_err(tp->dev, | |
3460 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
3461 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); | |
3462 | return -ENODEV; | |
3463 | } | |
3464 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3465 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
3466 | return 0; | |
3467 | } | |
3468 | ||
3469 | ||
3f007891 MC |
3470 | /* tp->lock is held. */ |
3471 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
3472 | { | |
3473 | u32 addr_high, addr_low; | |
3474 | int i; | |
3475 | ||
3476 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
3477 | tp->dev->dev_addr[1]); | |
3478 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
3479 | (tp->dev->dev_addr[3] << 16) | | |
3480 | (tp->dev->dev_addr[4] << 8) | | |
3481 | (tp->dev->dev_addr[5] << 0)); | |
3482 | for (i = 0; i < 4; i++) { | |
3483 | if (i == 1 && skip_mac_1) | |
3484 | continue; | |
3485 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
3486 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
3487 | } | |
3488 | ||
3489 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3490 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
3491 | for (i = 0; i < 12; i++) { | |
3492 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
3493 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
3494 | } | |
3495 | } | |
3496 | ||
3497 | addr_high = (tp->dev->dev_addr[0] + | |
3498 | tp->dev->dev_addr[1] + | |
3499 | tp->dev->dev_addr[2] + | |
3500 | tp->dev->dev_addr[3] + | |
3501 | tp->dev->dev_addr[4] + | |
3502 | tp->dev->dev_addr[5]) & | |
3503 | TX_BACKOFF_SEED_MASK; | |
3504 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
3505 | } | |
3506 | ||
c866b7ea | 3507 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 3508 | { |
c866b7ea RW |
3509 | /* |
3510 | * Make sure register accesses (indirect or otherwise) will function | |
3511 | * correctly. | |
1da177e4 LT |
3512 | */ |
3513 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
3514 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
3515 | } | |
1da177e4 | 3516 | |
c866b7ea RW |
3517 | static int tg3_power_up(struct tg3 *tp) |
3518 | { | |
bed9829f | 3519 | int err; |
8c6bda1a | 3520 | |
bed9829f | 3521 | tg3_enable_register_access(tp); |
1da177e4 | 3522 | |
bed9829f MC |
3523 | err = pci_set_power_state(tp->pdev, PCI_D0); |
3524 | if (!err) { | |
3525 | /* Switch out of Vaux if it is a NIC */ | |
3526 | tg3_pwrsrc_switch_to_vmain(tp); | |
3527 | } else { | |
3528 | netdev_err(tp->dev, "Transition to D0 failed\n"); | |
3529 | } | |
1da177e4 | 3530 | |
bed9829f | 3531 | return err; |
c866b7ea | 3532 | } |
1da177e4 | 3533 | |
4b409522 MC |
3534 | static int tg3_setup_phy(struct tg3 *, int); |
3535 | ||
c866b7ea RW |
3536 | static int tg3_power_down_prepare(struct tg3 *tp) |
3537 | { | |
3538 | u32 misc_host_ctrl; | |
3539 | bool device_should_wake, do_low_power; | |
3540 | ||
3541 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
3542 | |
3543 | /* Restore the CLKREQ setting. */ | |
63c3a66f | 3544 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
3545 | u16 lnkctl; |
3546 | ||
3547 | pci_read_config_word(tp->pdev, | |
708ebb3a | 3548 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3549 | &lnkctl); |
3550 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
3551 | pci_write_config_word(tp->pdev, | |
708ebb3a | 3552 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3553 | lnkctl); |
3554 | } | |
3555 | ||
1da177e4 LT |
3556 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
3557 | tw32(TG3PCI_MISC_HOST_CTRL, | |
3558 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
3559 | ||
c866b7ea | 3560 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 3561 | tg3_flag(tp, WOL_ENABLE); |
05ac4cb7 | 3562 | |
63c3a66f | 3563 | if (tg3_flag(tp, USE_PHYLIB)) { |
0a459aac | 3564 | do_low_power = false; |
f07e9af3 | 3565 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 3566 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 3567 | struct phy_device *phydev; |
0a459aac | 3568 | u32 phyid, advertising; |
b02fd9e3 | 3569 | |
3f0e3ad7 | 3570 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 3571 | |
80096068 | 3572 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 | 3573 | |
c6700ce2 MC |
3574 | tp->link_config.speed = phydev->speed; |
3575 | tp->link_config.duplex = phydev->duplex; | |
3576 | tp->link_config.autoneg = phydev->autoneg; | |
3577 | tp->link_config.advertising = phydev->advertising; | |
b02fd9e3 MC |
3578 | |
3579 | advertising = ADVERTISED_TP | | |
3580 | ADVERTISED_Pause | | |
3581 | ADVERTISED_Autoneg | | |
3582 | ADVERTISED_10baseT_Half; | |
3583 | ||
63c3a66f JP |
3584 | if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { |
3585 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
b02fd9e3 MC |
3586 | advertising |= |
3587 | ADVERTISED_100baseT_Half | | |
3588 | ADVERTISED_100baseT_Full | | |
3589 | ADVERTISED_10baseT_Full; | |
3590 | else | |
3591 | advertising |= ADVERTISED_10baseT_Full; | |
3592 | } | |
3593 | ||
3594 | phydev->advertising = advertising; | |
3595 | ||
3596 | phy_start_aneg(phydev); | |
0a459aac MC |
3597 | |
3598 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
3599 | if (phyid != PHY_ID_BCMAC131) { |
3600 | phyid &= PHY_BCM_OUI_MASK; | |
3601 | if (phyid == PHY_BCM_OUI_1 || | |
3602 | phyid == PHY_BCM_OUI_2 || | |
3603 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
3604 | do_low_power = true; |
3605 | } | |
b02fd9e3 | 3606 | } |
dd477003 | 3607 | } else { |
2023276e | 3608 | do_low_power = true; |
0a459aac | 3609 | |
c6700ce2 | 3610 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) |
80096068 | 3611 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
1da177e4 | 3612 | |
2855b9fe | 3613 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
dd477003 | 3614 | tg3_setup_phy(tp, 0); |
1da177e4 LT |
3615 | } |
3616 | ||
b5d3772c MC |
3617 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
3618 | u32 val; | |
3619 | ||
3620 | val = tr32(GRC_VCPU_EXT_CTRL); | |
3621 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
63c3a66f | 3622 | } else if (!tg3_flag(tp, ENABLE_ASF)) { |
6921d201 MC |
3623 | int i; |
3624 | u32 val; | |
3625 | ||
3626 | for (i = 0; i < 200; i++) { | |
3627 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
3628 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
3629 | break; | |
3630 | msleep(1); | |
3631 | } | |
3632 | } | |
63c3a66f | 3633 | if (tg3_flag(tp, WOL_CAP)) |
a85feb8c GZ |
3634 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | |
3635 | WOL_DRV_STATE_SHUTDOWN | | |
3636 | WOL_DRV_WOL | | |
3637 | WOL_SET_MAGIC_PKT); | |
6921d201 | 3638 | |
05ac4cb7 | 3639 | if (device_should_wake) { |
1da177e4 LT |
3640 | u32 mac_mode; |
3641 | ||
f07e9af3 | 3642 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
b4bd2929 MC |
3643 | if (do_low_power && |
3644 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
3645 | tg3_phy_auxctl_write(tp, | |
3646 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, | |
3647 | MII_TG3_AUXCTL_PCTL_WOL_EN | | |
3648 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
3649 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); | |
dd477003 MC |
3650 | udelay(40); |
3651 | } | |
1da177e4 | 3652 | |
f07e9af3 | 3653 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
3654 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
3655 | else | |
3656 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 3657 | |
e8f3f6ca MC |
3658 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
3659 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
3660 | ASIC_REV_5700) { | |
63c3a66f | 3661 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? |
e8f3f6ca MC |
3662 | SPEED_100 : SPEED_10; |
3663 | if (tg3_5700_link_polarity(tp, speed)) | |
3664 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
3665 | else | |
3666 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
3667 | } | |
1da177e4 LT |
3668 | } else { |
3669 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
3670 | } | |
3671 | ||
63c3a66f | 3672 | if (!tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
3673 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
3674 | ||
05ac4cb7 | 3675 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
63c3a66f JP |
3676 | if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && |
3677 | (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) | |
05ac4cb7 | 3678 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; |
1da177e4 | 3679 | |
63c3a66f | 3680 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b MC |
3681 | mac_mode |= MAC_MODE_APE_TX_EN | |
3682 | MAC_MODE_APE_RX_EN | | |
3683 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 3684 | |
1da177e4 LT |
3685 | tw32_f(MAC_MODE, mac_mode); |
3686 | udelay(100); | |
3687 | ||
3688 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
3689 | udelay(10); | |
3690 | } | |
3691 | ||
63c3a66f | 3692 | if (!tg3_flag(tp, WOL_SPEED_100MB) && |
1da177e4 LT |
3693 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
3694 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
3695 | u32 base_val; | |
3696 | ||
3697 | base_val = tp->pci_clock_ctrl; | |
3698 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
3699 | CLOCK_CTRL_TXCLK_DISABLE); | |
3700 | ||
b401e9e2 MC |
3701 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
3702 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
63c3a66f JP |
3703 | } else if (tg3_flag(tp, 5780_CLASS) || |
3704 | tg3_flag(tp, CPMU_PRESENT) || | |
6ff6f81d | 3705 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
4cf78e4f | 3706 | /* do nothing */ |
63c3a66f | 3707 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { |
1da177e4 LT |
3708 | u32 newbits1, newbits2; |
3709 | ||
3710 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3711 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3712 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
3713 | CLOCK_CTRL_TXCLK_DISABLE | | |
3714 | CLOCK_CTRL_ALTCLK); | |
3715 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
63c3a66f | 3716 | } else if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
3717 | newbits1 = CLOCK_CTRL_625_CORE; |
3718 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
3719 | } else { | |
3720 | newbits1 = CLOCK_CTRL_ALTCLK; | |
3721 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
3722 | } | |
3723 | ||
b401e9e2 MC |
3724 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
3725 | 40); | |
1da177e4 | 3726 | |
b401e9e2 MC |
3727 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
3728 | 40); | |
1da177e4 | 3729 | |
63c3a66f | 3730 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
3731 | u32 newbits3; |
3732 | ||
3733 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3734 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3735 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
3736 | CLOCK_CTRL_TXCLK_DISABLE | | |
3737 | CLOCK_CTRL_44MHZ_CORE); | |
3738 | } else { | |
3739 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
3740 | } | |
3741 | ||
b401e9e2 MC |
3742 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
3743 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
3744 | } |
3745 | } | |
3746 | ||
63c3a66f | 3747 | if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) |
0a459aac | 3748 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 3749 | |
cd0d7228 | 3750 | tg3_frob_aux_power(tp, true); |
1da177e4 LT |
3751 | |
3752 | /* Workaround for unstable PLL clock */ | |
3753 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
3754 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
3755 | u32 val = tr32(0x7d00); | |
3756 | ||
3757 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
3758 | tw32(0x7d00, val); | |
63c3a66f | 3759 | if (!tg3_flag(tp, ENABLE_ASF)) { |
ec41c7df MC |
3760 | int err; |
3761 | ||
3762 | err = tg3_nvram_lock(tp); | |
1da177e4 | 3763 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
3764 | if (!err) |
3765 | tg3_nvram_unlock(tp); | |
6921d201 | 3766 | } |
1da177e4 LT |
3767 | } |
3768 | ||
bbadf503 MC |
3769 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
3770 | ||
c866b7ea RW |
3771 | return 0; |
3772 | } | |
12dac075 | 3773 | |
c866b7ea RW |
3774 | static void tg3_power_down(struct tg3 *tp) |
3775 | { | |
3776 | tg3_power_down_prepare(tp); | |
1da177e4 | 3777 | |
63c3a66f | 3778 | pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); |
c866b7ea | 3779 | pci_set_power_state(tp->pdev, PCI_D3hot); |
1da177e4 LT |
3780 | } |
3781 | ||
1da177e4 LT |
3782 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
3783 | { | |
3784 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
3785 | case MII_TG3_AUX_STAT_10HALF: | |
3786 | *speed = SPEED_10; | |
3787 | *duplex = DUPLEX_HALF; | |
3788 | break; | |
3789 | ||
3790 | case MII_TG3_AUX_STAT_10FULL: | |
3791 | *speed = SPEED_10; | |
3792 | *duplex = DUPLEX_FULL; | |
3793 | break; | |
3794 | ||
3795 | case MII_TG3_AUX_STAT_100HALF: | |
3796 | *speed = SPEED_100; | |
3797 | *duplex = DUPLEX_HALF; | |
3798 | break; | |
3799 | ||
3800 | case MII_TG3_AUX_STAT_100FULL: | |
3801 | *speed = SPEED_100; | |
3802 | *duplex = DUPLEX_FULL; | |
3803 | break; | |
3804 | ||
3805 | case MII_TG3_AUX_STAT_1000HALF: | |
3806 | *speed = SPEED_1000; | |
3807 | *duplex = DUPLEX_HALF; | |
3808 | break; | |
3809 | ||
3810 | case MII_TG3_AUX_STAT_1000FULL: | |
3811 | *speed = SPEED_1000; | |
3812 | *duplex = DUPLEX_FULL; | |
3813 | break; | |
3814 | ||
3815 | default: | |
f07e9af3 | 3816 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
3817 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
3818 | SPEED_10; | |
3819 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
3820 | DUPLEX_HALF; | |
3821 | break; | |
3822 | } | |
e740522e MC |
3823 | *speed = SPEED_UNKNOWN; |
3824 | *duplex = DUPLEX_UNKNOWN; | |
1da177e4 | 3825 | break; |
855e1111 | 3826 | } |
1da177e4 LT |
3827 | } |
3828 | ||
42b64a45 | 3829 | static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) |
1da177e4 | 3830 | { |
42b64a45 MC |
3831 | int err = 0; |
3832 | u32 val, new_adv; | |
1da177e4 | 3833 | |
42b64a45 | 3834 | new_adv = ADVERTISE_CSMA; |
202ff1c2 | 3835 | new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL; |
f88788f0 | 3836 | new_adv |= mii_advertise_flowctrl(flowctrl); |
1da177e4 | 3837 | |
42b64a45 MC |
3838 | err = tg3_writephy(tp, MII_ADVERTISE, new_adv); |
3839 | if (err) | |
3840 | goto done; | |
ba4d07a8 | 3841 | |
4f272096 MC |
3842 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
3843 | new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise); | |
ba4d07a8 | 3844 | |
4f272096 MC |
3845 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
3846 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
3847 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; | |
ba4d07a8 | 3848 | |
4f272096 MC |
3849 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
3850 | if (err) | |
3851 | goto done; | |
3852 | } | |
1da177e4 | 3853 | |
42b64a45 MC |
3854 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) |
3855 | goto done; | |
52b02d04 | 3856 | |
42b64a45 MC |
3857 | tw32(TG3_CPMU_EEE_MODE, |
3858 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
52b02d04 | 3859 | |
42b64a45 MC |
3860 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
3861 | if (!err) { | |
3862 | u32 err2; | |
52b02d04 | 3863 | |
b715ce94 MC |
3864 | val = 0; |
3865 | /* Advertise 100-BaseTX EEE ability */ | |
3866 | if (advertise & ADVERTISED_100baseT_Full) | |
3867 | val |= MDIO_AN_EEE_ADV_100TX; | |
3868 | /* Advertise 1000-BaseT EEE ability */ | |
3869 | if (advertise & ADVERTISED_1000baseT_Full) | |
3870 | val |= MDIO_AN_EEE_ADV_1000T; | |
3871 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3872 | if (err) | |
3873 | val = 0; | |
3874 | ||
21a00ab2 MC |
3875 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
3876 | case ASIC_REV_5717: | |
3877 | case ASIC_REV_57765: | |
55086ad9 | 3878 | case ASIC_REV_57766: |
21a00ab2 | 3879 | case ASIC_REV_5719: |
b715ce94 MC |
3880 | /* If we advertised any eee advertisements above... */ |
3881 | if (val) | |
3882 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
3883 | MII_TG3_DSP_TAP26_RMRXSTO | | |
3884 | MII_TG3_DSP_TAP26_OPCSINPT; | |
21a00ab2 | 3885 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); |
be671947 MC |
3886 | /* Fall through */ |
3887 | case ASIC_REV_5720: | |
3888 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
3889 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
3890 | MII_TG3_DSP_CH34TP2_HIBW01); | |
21a00ab2 | 3891 | } |
52b02d04 | 3892 | |
42b64a45 MC |
3893 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
3894 | if (!err) | |
3895 | err = err2; | |
3896 | } | |
3897 | ||
3898 | done: | |
3899 | return err; | |
3900 | } | |
3901 | ||
3902 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
3903 | { | |
d13ba512 MC |
3904 | if (tp->link_config.autoneg == AUTONEG_ENABLE || |
3905 | (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { | |
3906 | u32 adv, fc; | |
3907 | ||
3908 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
3909 | adv = ADVERTISED_10baseT_Half | | |
3910 | ADVERTISED_10baseT_Full; | |
3911 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
3912 | adv |= ADVERTISED_100baseT_Half | | |
3913 | ADVERTISED_100baseT_Full; | |
3914 | ||
3915 | fc = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
42b64a45 | 3916 | } else { |
d13ba512 MC |
3917 | adv = tp->link_config.advertising; |
3918 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
3919 | adv &= ~(ADVERTISED_1000baseT_Half | | |
3920 | ADVERTISED_1000baseT_Full); | |
3921 | ||
3922 | fc = tp->link_config.flowctrl; | |
52b02d04 | 3923 | } |
52b02d04 | 3924 | |
d13ba512 | 3925 | tg3_phy_autoneg_cfg(tp, adv, fc); |
52b02d04 | 3926 | |
d13ba512 MC |
3927 | tg3_writephy(tp, MII_BMCR, |
3928 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3929 | } else { | |
3930 | int i; | |
1da177e4 LT |
3931 | u32 bmcr, orig_bmcr; |
3932 | ||
3933 | tp->link_config.active_speed = tp->link_config.speed; | |
3934 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3935 | ||
3936 | bmcr = 0; | |
3937 | switch (tp->link_config.speed) { | |
3938 | default: | |
3939 | case SPEED_10: | |
3940 | break; | |
3941 | ||
3942 | case SPEED_100: | |
3943 | bmcr |= BMCR_SPEED100; | |
3944 | break; | |
3945 | ||
3946 | case SPEED_1000: | |
221c5637 | 3947 | bmcr |= BMCR_SPEED1000; |
1da177e4 | 3948 | break; |
855e1111 | 3949 | } |
1da177e4 LT |
3950 | |
3951 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3952 | bmcr |= BMCR_FULLDPLX; | |
3953 | ||
3954 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3955 | (bmcr != orig_bmcr)) { | |
3956 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3957 | for (i = 0; i < 1500; i++) { | |
3958 | u32 tmp; | |
3959 | ||
3960 | udelay(10); | |
3961 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3962 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3963 | continue; | |
3964 | if (!(tmp & BMSR_LSTATUS)) { | |
3965 | udelay(40); | |
3966 | break; | |
3967 | } | |
3968 | } | |
3969 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3970 | udelay(40); | |
3971 | } | |
1da177e4 LT |
3972 | } |
3973 | } | |
3974 | ||
3975 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3976 | { | |
3977 | int err; | |
3978 | ||
3979 | /* Turn off tap power management. */ | |
3980 | /* Set Extended packet length bit */ | |
b4bd2929 | 3981 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
1da177e4 | 3982 | |
6ee7c0a0 MC |
3983 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
3984 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3985 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3986 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3987 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
3988 | |
3989 | udelay(40); | |
3990 | ||
3991 | return err; | |
3992 | } | |
3993 | ||
e2bf73e7 | 3994 | static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) |
1da177e4 | 3995 | { |
e2bf73e7 | 3996 | u32 advmsk, tgtadv, advertising; |
3600d918 | 3997 | |
e2bf73e7 MC |
3998 | advertising = tp->link_config.advertising; |
3999 | tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL; | |
1da177e4 | 4000 | |
e2bf73e7 MC |
4001 | advmsk = ADVERTISE_ALL; |
4002 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
f88788f0 | 4003 | tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); |
e2bf73e7 MC |
4004 | advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4005 | } | |
1da177e4 | 4006 | |
e2bf73e7 MC |
4007 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) |
4008 | return false; | |
4009 | ||
4010 | if ((*lcladv & advmsk) != tgtadv) | |
4011 | return false; | |
b99d2a57 | 4012 | |
f07e9af3 | 4013 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
4014 | u32 tg3_ctrl; |
4015 | ||
e2bf73e7 | 4016 | tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising); |
3600d918 | 4017 | |
221c5637 | 4018 | if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) |
e2bf73e7 | 4019 | return false; |
1da177e4 | 4020 | |
3198e07f MC |
4021 | if (tgtadv && |
4022 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
4023 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) { | |
4024 | tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; | |
4025 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL | | |
4026 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
4027 | } else { | |
4028 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL); | |
4029 | } | |
4030 | ||
e2bf73e7 MC |
4031 | if (tg3_ctrl != tgtadv) |
4032 | return false; | |
ef167e27 MC |
4033 | } |
4034 | ||
e2bf73e7 | 4035 | return true; |
ef167e27 MC |
4036 | } |
4037 | ||
859edb26 MC |
4038 | static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) |
4039 | { | |
4040 | u32 lpeth = 0; | |
4041 | ||
4042 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { | |
4043 | u32 val; | |
4044 | ||
4045 | if (tg3_readphy(tp, MII_STAT1000, &val)) | |
4046 | return false; | |
4047 | ||
4048 | lpeth = mii_stat1000_to_ethtool_lpa_t(val); | |
4049 | } | |
4050 | ||
4051 | if (tg3_readphy(tp, MII_LPA, rmtadv)) | |
4052 | return false; | |
4053 | ||
4054 | lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv); | |
4055 | tp->link_config.rmt_adv = lpeth; | |
4056 | ||
4057 | return true; | |
4058 | } | |
4059 | ||
1da177e4 LT |
4060 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
4061 | { | |
4062 | int current_link_up; | |
f833c4c1 | 4063 | u32 bmsr, val; |
ef167e27 | 4064 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
4065 | u16 current_speed; |
4066 | u8 current_duplex; | |
4067 | int i, err; | |
4068 | ||
4069 | tw32(MAC_EVENT, 0); | |
4070 | ||
4071 | tw32_f(MAC_STATUS, | |
4072 | (MAC_STATUS_SYNC_CHANGED | | |
4073 | MAC_STATUS_CFG_CHANGED | | |
4074 | MAC_STATUS_MI_COMPLETION | | |
4075 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4076 | udelay(40); | |
4077 | ||
8ef21428 MC |
4078 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
4079 | tw32_f(MAC_MI_MODE, | |
4080 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
4081 | udelay(80); | |
4082 | } | |
1da177e4 | 4083 | |
b4bd2929 | 4084 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); |
1da177e4 LT |
4085 | |
4086 | /* Some third-party PHYs need to be reset on link going | |
4087 | * down. | |
4088 | */ | |
4089 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
4090 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
4091 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
4092 | netif_carrier_ok(tp->dev)) { | |
4093 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
4094 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
4095 | !(bmsr & BMSR_LSTATUS)) | |
4096 | force_reset = 1; | |
4097 | } | |
4098 | if (force_reset) | |
4099 | tg3_phy_reset(tp); | |
4100 | ||
79eb6904 | 4101 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
4102 | tg3_readphy(tp, MII_BMSR, &bmsr); |
4103 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
63c3a66f | 4104 | !tg3_flag(tp, INIT_COMPLETE)) |
1da177e4 LT |
4105 | bmsr = 0; |
4106 | ||
4107 | if (!(bmsr & BMSR_LSTATUS)) { | |
4108 | err = tg3_init_5401phy_dsp(tp); | |
4109 | if (err) | |
4110 | return err; | |
4111 | ||
4112 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
4113 | for (i = 0; i < 1000; i++) { | |
4114 | udelay(10); | |
4115 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
4116 | (bmsr & BMSR_LSTATUS)) { | |
4117 | udelay(40); | |
4118 | break; | |
4119 | } | |
4120 | } | |
4121 | ||
79eb6904 MC |
4122 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
4123 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
4124 | !(bmsr & BMSR_LSTATUS) && |
4125 | tp->link_config.active_speed == SPEED_1000) { | |
4126 | err = tg3_phy_reset(tp); | |
4127 | if (!err) | |
4128 | err = tg3_init_5401phy_dsp(tp); | |
4129 | if (err) | |
4130 | return err; | |
4131 | } | |
4132 | } | |
4133 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
4134 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
4135 | /* 5701 {A0,B0} CRC bug workaround */ | |
4136 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
4137 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
4138 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
4139 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
4140 | } |
4141 | ||
4142 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
4143 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
4144 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 4145 | |
f07e9af3 | 4146 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 4147 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 4148 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
4149 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
4150 | ||
4151 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
4152 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
4153 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
4154 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
4155 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
4156 | else | |
4157 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
4158 | } | |
4159 | ||
4160 | current_link_up = 0; | |
e740522e MC |
4161 | current_speed = SPEED_UNKNOWN; |
4162 | current_duplex = DUPLEX_UNKNOWN; | |
e348c5e7 | 4163 | tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; |
859edb26 | 4164 | tp->link_config.rmt_adv = 0; |
1da177e4 | 4165 | |
f07e9af3 | 4166 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
15ee95c3 MC |
4167 | err = tg3_phy_auxctl_read(tp, |
4168 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
4169 | &val); | |
4170 | if (!err && !(val & (1 << 10))) { | |
b4bd2929 MC |
4171 | tg3_phy_auxctl_write(tp, |
4172 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
4173 | val | (1 << 10)); | |
1da177e4 LT |
4174 | goto relink; |
4175 | } | |
4176 | } | |
4177 | ||
4178 | bmsr = 0; | |
4179 | for (i = 0; i < 100; i++) { | |
4180 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
4181 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
4182 | (bmsr & BMSR_LSTATUS)) | |
4183 | break; | |
4184 | udelay(40); | |
4185 | } | |
4186 | ||
4187 | if (bmsr & BMSR_LSTATUS) { | |
4188 | u32 aux_stat, bmcr; | |
4189 | ||
4190 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
4191 | for (i = 0; i < 2000; i++) { | |
4192 | udelay(10); | |
4193 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
4194 | aux_stat) | |
4195 | break; | |
4196 | } | |
4197 | ||
4198 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
4199 | ¤t_speed, | |
4200 | ¤t_duplex); | |
4201 | ||
4202 | bmcr = 0; | |
4203 | for (i = 0; i < 200; i++) { | |
4204 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4205 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
4206 | continue; | |
4207 | if (bmcr && bmcr != 0x7fff) | |
4208 | break; | |
4209 | udelay(10); | |
4210 | } | |
4211 | ||
ef167e27 MC |
4212 | lcl_adv = 0; |
4213 | rmt_adv = 0; | |
1da177e4 | 4214 | |
ef167e27 MC |
4215 | tp->link_config.active_speed = current_speed; |
4216 | tp->link_config.active_duplex = current_duplex; | |
4217 | ||
4218 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4219 | if ((bmcr & BMCR_ANENABLE) && | |
e2bf73e7 | 4220 | tg3_phy_copper_an_config_ok(tp, &lcl_adv) && |
859edb26 | 4221 | tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) |
e2bf73e7 | 4222 | current_link_up = 1; |
1da177e4 LT |
4223 | } else { |
4224 | if (!(bmcr & BMCR_ANENABLE) && | |
4225 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
4226 | tp->link_config.duplex == current_duplex && |
4227 | tp->link_config.flowctrl == | |
4228 | tp->link_config.active_flowctrl) { | |
1da177e4 | 4229 | current_link_up = 1; |
1da177e4 LT |
4230 | } |
4231 | } | |
4232 | ||
ef167e27 | 4233 | if (current_link_up == 1 && |
e348c5e7 MC |
4234 | tp->link_config.active_duplex == DUPLEX_FULL) { |
4235 | u32 reg, bit; | |
4236 | ||
4237 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
4238 | reg = MII_TG3_FET_GEN_STAT; | |
4239 | bit = MII_TG3_FET_GEN_STAT_MDIXSTAT; | |
4240 | } else { | |
4241 | reg = MII_TG3_EXT_STAT; | |
4242 | bit = MII_TG3_EXT_STAT_MDIX; | |
4243 | } | |
4244 | ||
4245 | if (!tg3_readphy(tp, reg, &val) && (val & bit)) | |
4246 | tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; | |
4247 | ||
ef167e27 | 4248 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); |
e348c5e7 | 4249 | } |
1da177e4 LT |
4250 | } |
4251 | ||
1da177e4 | 4252 | relink: |
80096068 | 4253 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
4254 | tg3_phy_copper_begin(tp); |
4255 | ||
f833c4c1 | 4256 | tg3_readphy(tp, MII_BMSR, &bmsr); |
06c03c02 MB |
4257 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
4258 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
1da177e4 LT |
4259 | current_link_up = 1; |
4260 | } | |
4261 | ||
4262 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
4263 | if (current_link_up == 1) { | |
4264 | if (tp->link_config.active_speed == SPEED_100 || | |
4265 | tp->link_config.active_speed == SPEED_10) | |
4266 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
4267 | else | |
4268 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 4269 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
4270 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
4271 | else | |
1da177e4 LT |
4272 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
4273 | ||
4274 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
4275 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4276 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4277 | ||
1da177e4 | 4278 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
4279 | if (current_link_up == 1 && |
4280 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 4281 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
4282 | else |
4283 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
4284 | } |
4285 | ||
4286 | /* ??? Without this setting Netgear GA302T PHY does not | |
4287 | * ??? send/receive packets... | |
4288 | */ | |
79eb6904 | 4289 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
4290 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
4291 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
4292 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
4293 | udelay(80); | |
4294 | } | |
4295 | ||
4296 | tw32_f(MAC_MODE, tp->mac_mode); | |
4297 | udelay(40); | |
4298 | ||
52b02d04 MC |
4299 | tg3_phy_eee_adjust(tp, current_link_up); |
4300 | ||
63c3a66f | 4301 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
4302 | /* Polled via timer. */ |
4303 | tw32_f(MAC_EVENT, 0); | |
4304 | } else { | |
4305 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4306 | } | |
4307 | udelay(40); | |
4308 | ||
4309 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
4310 | current_link_up == 1 && | |
4311 | tp->link_config.active_speed == SPEED_1000 && | |
63c3a66f | 4312 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
1da177e4 LT |
4313 | udelay(120); |
4314 | tw32_f(MAC_STATUS, | |
4315 | (MAC_STATUS_SYNC_CHANGED | | |
4316 | MAC_STATUS_CFG_CHANGED)); | |
4317 | udelay(40); | |
4318 | tg3_write_mem(tp, | |
4319 | NIC_SRAM_FIRMWARE_MBOX, | |
4320 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
4321 | } | |
4322 | ||
5e7dfd0f | 4323 | /* Prevent send BD corruption. */ |
63c3a66f | 4324 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
4325 | u16 oldlnkctl, newlnkctl; |
4326 | ||
4327 | pci_read_config_word(tp->pdev, | |
708ebb3a | 4328 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
4329 | &oldlnkctl); |
4330 | if (tp->link_config.active_speed == SPEED_100 || | |
4331 | tp->link_config.active_speed == SPEED_10) | |
4332 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
4333 | else | |
4334 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
4335 | if (newlnkctl != oldlnkctl) | |
4336 | pci_write_config_word(tp->pdev, | |
93a700a9 MC |
4337 | pci_pcie_cap(tp->pdev) + |
4338 | PCI_EXP_LNKCTL, newlnkctl); | |
5e7dfd0f MC |
4339 | } |
4340 | ||
1da177e4 LT |
4341 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
4342 | if (current_link_up) | |
4343 | netif_carrier_on(tp->dev); | |
4344 | else | |
4345 | netif_carrier_off(tp->dev); | |
4346 | tg3_link_report(tp); | |
4347 | } | |
4348 | ||
4349 | return 0; | |
4350 | } | |
4351 | ||
4352 | struct tg3_fiber_aneginfo { | |
4353 | int state; | |
4354 | #define ANEG_STATE_UNKNOWN 0 | |
4355 | #define ANEG_STATE_AN_ENABLE 1 | |
4356 | #define ANEG_STATE_RESTART_INIT 2 | |
4357 | #define ANEG_STATE_RESTART 3 | |
4358 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
4359 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
4360 | #define ANEG_STATE_ABILITY_DETECT 6 | |
4361 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
4362 | #define ANEG_STATE_ACK_DETECT 8 | |
4363 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
4364 | #define ANEG_STATE_COMPLETE_ACK 10 | |
4365 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
4366 | #define ANEG_STATE_IDLE_DETECT 12 | |
4367 | #define ANEG_STATE_LINK_OK 13 | |
4368 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
4369 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
4370 | ||
4371 | u32 flags; | |
4372 | #define MR_AN_ENABLE 0x00000001 | |
4373 | #define MR_RESTART_AN 0x00000002 | |
4374 | #define MR_AN_COMPLETE 0x00000004 | |
4375 | #define MR_PAGE_RX 0x00000008 | |
4376 | #define MR_NP_LOADED 0x00000010 | |
4377 | #define MR_TOGGLE_TX 0x00000020 | |
4378 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
4379 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
4380 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
4381 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
4382 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
4383 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
4384 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
4385 | #define MR_TOGGLE_RX 0x00002000 | |
4386 | #define MR_NP_RX 0x00004000 | |
4387 | ||
4388 | #define MR_LINK_OK 0x80000000 | |
4389 | ||
4390 | unsigned long link_time, cur_time; | |
4391 | ||
4392 | u32 ability_match_cfg; | |
4393 | int ability_match_count; | |
4394 | ||
4395 | char ability_match, idle_match, ack_match; | |
4396 | ||
4397 | u32 txconfig, rxconfig; | |
4398 | #define ANEG_CFG_NP 0x00000080 | |
4399 | #define ANEG_CFG_ACK 0x00000040 | |
4400 | #define ANEG_CFG_RF2 0x00000020 | |
4401 | #define ANEG_CFG_RF1 0x00000010 | |
4402 | #define ANEG_CFG_PS2 0x00000001 | |
4403 | #define ANEG_CFG_PS1 0x00008000 | |
4404 | #define ANEG_CFG_HD 0x00004000 | |
4405 | #define ANEG_CFG_FD 0x00002000 | |
4406 | #define ANEG_CFG_INVAL 0x00001f06 | |
4407 | ||
4408 | }; | |
4409 | #define ANEG_OK 0 | |
4410 | #define ANEG_DONE 1 | |
4411 | #define ANEG_TIMER_ENAB 2 | |
4412 | #define ANEG_FAILED -1 | |
4413 | ||
4414 | #define ANEG_STATE_SETTLE_TIME 10000 | |
4415 | ||
4416 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
4417 | struct tg3_fiber_aneginfo *ap) | |
4418 | { | |
5be73b47 | 4419 | u16 flowctrl; |
1da177e4 LT |
4420 | unsigned long delta; |
4421 | u32 rx_cfg_reg; | |
4422 | int ret; | |
4423 | ||
4424 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
4425 | ap->rxconfig = 0; | |
4426 | ap->link_time = 0; | |
4427 | ap->cur_time = 0; | |
4428 | ap->ability_match_cfg = 0; | |
4429 | ap->ability_match_count = 0; | |
4430 | ap->ability_match = 0; | |
4431 | ap->idle_match = 0; | |
4432 | ap->ack_match = 0; | |
4433 | } | |
4434 | ap->cur_time++; | |
4435 | ||
4436 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
4437 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
4438 | ||
4439 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
4440 | ap->ability_match_cfg = rx_cfg_reg; | |
4441 | ap->ability_match = 0; | |
4442 | ap->ability_match_count = 0; | |
4443 | } else { | |
4444 | if (++ap->ability_match_count > 1) { | |
4445 | ap->ability_match = 1; | |
4446 | ap->ability_match_cfg = rx_cfg_reg; | |
4447 | } | |
4448 | } | |
4449 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
4450 | ap->ack_match = 1; | |
4451 | else | |
4452 | ap->ack_match = 0; | |
4453 | ||
4454 | ap->idle_match = 0; | |
4455 | } else { | |
4456 | ap->idle_match = 1; | |
4457 | ap->ability_match_cfg = 0; | |
4458 | ap->ability_match_count = 0; | |
4459 | ap->ability_match = 0; | |
4460 | ap->ack_match = 0; | |
4461 | ||
4462 | rx_cfg_reg = 0; | |
4463 | } | |
4464 | ||
4465 | ap->rxconfig = rx_cfg_reg; | |
4466 | ret = ANEG_OK; | |
4467 | ||
33f401ae | 4468 | switch (ap->state) { |
1da177e4 LT |
4469 | case ANEG_STATE_UNKNOWN: |
4470 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
4471 | ap->state = ANEG_STATE_AN_ENABLE; | |
4472 | ||
4473 | /* fallthru */ | |
4474 | case ANEG_STATE_AN_ENABLE: | |
4475 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
4476 | if (ap->flags & MR_AN_ENABLE) { | |
4477 | ap->link_time = 0; | |
4478 | ap->cur_time = 0; | |
4479 | ap->ability_match_cfg = 0; | |
4480 | ap->ability_match_count = 0; | |
4481 | ap->ability_match = 0; | |
4482 | ap->idle_match = 0; | |
4483 | ap->ack_match = 0; | |
4484 | ||
4485 | ap->state = ANEG_STATE_RESTART_INIT; | |
4486 | } else { | |
4487 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
4488 | } | |
4489 | break; | |
4490 | ||
4491 | case ANEG_STATE_RESTART_INIT: | |
4492 | ap->link_time = ap->cur_time; | |
4493 | ap->flags &= ~(MR_NP_LOADED); | |
4494 | ap->txconfig = 0; | |
4495 | tw32(MAC_TX_AUTO_NEG, 0); | |
4496 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4497 | tw32_f(MAC_MODE, tp->mac_mode); | |
4498 | udelay(40); | |
4499 | ||
4500 | ret = ANEG_TIMER_ENAB; | |
4501 | ap->state = ANEG_STATE_RESTART; | |
4502 | ||
4503 | /* fallthru */ | |
4504 | case ANEG_STATE_RESTART: | |
4505 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 4506 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 4507 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 4508 | else |
1da177e4 | 4509 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
4510 | break; |
4511 | ||
4512 | case ANEG_STATE_DISABLE_LINK_OK: | |
4513 | ret = ANEG_DONE; | |
4514 | break; | |
4515 | ||
4516 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
4517 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
4518 | ap->txconfig = ANEG_CFG_FD; |
4519 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
4520 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4521 | ap->txconfig |= ANEG_CFG_PS1; | |
4522 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4523 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
4524 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
4525 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4526 | tw32_f(MAC_MODE, tp->mac_mode); | |
4527 | udelay(40); | |
4528 | ||
4529 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
4530 | break; | |
4531 | ||
4532 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 4533 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 4534 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
4535 | break; |
4536 | ||
4537 | case ANEG_STATE_ACK_DETECT_INIT: | |
4538 | ap->txconfig |= ANEG_CFG_ACK; | |
4539 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
4540 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4541 | tw32_f(MAC_MODE, tp->mac_mode); | |
4542 | udelay(40); | |
4543 | ||
4544 | ap->state = ANEG_STATE_ACK_DETECT; | |
4545 | ||
4546 | /* fallthru */ | |
4547 | case ANEG_STATE_ACK_DETECT: | |
4548 | if (ap->ack_match != 0) { | |
4549 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
4550 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
4551 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
4552 | } else { | |
4553 | ap->state = ANEG_STATE_AN_ENABLE; | |
4554 | } | |
4555 | } else if (ap->ability_match != 0 && | |
4556 | ap->rxconfig == 0) { | |
4557 | ap->state = ANEG_STATE_AN_ENABLE; | |
4558 | } | |
4559 | break; | |
4560 | ||
4561 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
4562 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
4563 | ret = ANEG_FAILED; | |
4564 | break; | |
4565 | } | |
4566 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
4567 | MR_LP_ADV_HALF_DUPLEX | | |
4568 | MR_LP_ADV_SYM_PAUSE | | |
4569 | MR_LP_ADV_ASYM_PAUSE | | |
4570 | MR_LP_ADV_REMOTE_FAULT1 | | |
4571 | MR_LP_ADV_REMOTE_FAULT2 | | |
4572 | MR_LP_ADV_NEXT_PAGE | | |
4573 | MR_TOGGLE_RX | | |
4574 | MR_NP_RX); | |
4575 | if (ap->rxconfig & ANEG_CFG_FD) | |
4576 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
4577 | if (ap->rxconfig & ANEG_CFG_HD) | |
4578 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
4579 | if (ap->rxconfig & ANEG_CFG_PS1) | |
4580 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
4581 | if (ap->rxconfig & ANEG_CFG_PS2) | |
4582 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
4583 | if (ap->rxconfig & ANEG_CFG_RF1) | |
4584 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
4585 | if (ap->rxconfig & ANEG_CFG_RF2) | |
4586 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
4587 | if (ap->rxconfig & ANEG_CFG_NP) | |
4588 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
4589 | ||
4590 | ap->link_time = ap->cur_time; | |
4591 | ||
4592 | ap->flags ^= (MR_TOGGLE_TX); | |
4593 | if (ap->rxconfig & 0x0008) | |
4594 | ap->flags |= MR_TOGGLE_RX; | |
4595 | if (ap->rxconfig & ANEG_CFG_NP) | |
4596 | ap->flags |= MR_NP_RX; | |
4597 | ap->flags |= MR_PAGE_RX; | |
4598 | ||
4599 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
4600 | ret = ANEG_TIMER_ENAB; | |
4601 | break; | |
4602 | ||
4603 | case ANEG_STATE_COMPLETE_ACK: | |
4604 | if (ap->ability_match != 0 && | |
4605 | ap->rxconfig == 0) { | |
4606 | ap->state = ANEG_STATE_AN_ENABLE; | |
4607 | break; | |
4608 | } | |
4609 | delta = ap->cur_time - ap->link_time; | |
4610 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
4611 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
4612 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
4613 | } else { | |
4614 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
4615 | !(ap->flags & MR_NP_RX)) { | |
4616 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
4617 | } else { | |
4618 | ret = ANEG_FAILED; | |
4619 | } | |
4620 | } | |
4621 | } | |
4622 | break; | |
4623 | ||
4624 | case ANEG_STATE_IDLE_DETECT_INIT: | |
4625 | ap->link_time = ap->cur_time; | |
4626 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
4627 | tw32_f(MAC_MODE, tp->mac_mode); | |
4628 | udelay(40); | |
4629 | ||
4630 | ap->state = ANEG_STATE_IDLE_DETECT; | |
4631 | ret = ANEG_TIMER_ENAB; | |
4632 | break; | |
4633 | ||
4634 | case ANEG_STATE_IDLE_DETECT: | |
4635 | if (ap->ability_match != 0 && | |
4636 | ap->rxconfig == 0) { | |
4637 | ap->state = ANEG_STATE_AN_ENABLE; | |
4638 | break; | |
4639 | } | |
4640 | delta = ap->cur_time - ap->link_time; | |
4641 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
4642 | /* XXX another gem from the Broadcom driver :( */ | |
4643 | ap->state = ANEG_STATE_LINK_OK; | |
4644 | } | |
4645 | break; | |
4646 | ||
4647 | case ANEG_STATE_LINK_OK: | |
4648 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
4649 | ret = ANEG_DONE; | |
4650 | break; | |
4651 | ||
4652 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
4653 | /* ??? unimplemented */ | |
4654 | break; | |
4655 | ||
4656 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
4657 | /* ??? unimplemented */ | |
4658 | break; | |
4659 | ||
4660 | default: | |
4661 | ret = ANEG_FAILED; | |
4662 | break; | |
855e1111 | 4663 | } |
1da177e4 LT |
4664 | |
4665 | return ret; | |
4666 | } | |
4667 | ||
5be73b47 | 4668 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
4669 | { |
4670 | int res = 0; | |
4671 | struct tg3_fiber_aneginfo aninfo; | |
4672 | int status = ANEG_FAILED; | |
4673 | unsigned int tick; | |
4674 | u32 tmp; | |
4675 | ||
4676 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4677 | ||
4678 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
4679 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
4680 | udelay(40); | |
4681 | ||
4682 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
4683 | udelay(40); | |
4684 | ||
4685 | memset(&aninfo, 0, sizeof(aninfo)); | |
4686 | aninfo.flags |= MR_AN_ENABLE; | |
4687 | aninfo.state = ANEG_STATE_UNKNOWN; | |
4688 | aninfo.cur_time = 0; | |
4689 | tick = 0; | |
4690 | while (++tick < 195000) { | |
4691 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
4692 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
4693 | break; | |
4694 | ||
4695 | udelay(1); | |
4696 | } | |
4697 | ||
4698 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
4699 | tw32_f(MAC_MODE, tp->mac_mode); | |
4700 | udelay(40); | |
4701 | ||
5be73b47 MC |
4702 | *txflags = aninfo.txconfig; |
4703 | *rxflags = aninfo.flags; | |
1da177e4 LT |
4704 | |
4705 | if (status == ANEG_DONE && | |
4706 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
4707 | MR_LP_ADV_FULL_DUPLEX))) | |
4708 | res = 1; | |
4709 | ||
4710 | return res; | |
4711 | } | |
4712 | ||
4713 | static void tg3_init_bcm8002(struct tg3 *tp) | |
4714 | { | |
4715 | u32 mac_status = tr32(MAC_STATUS); | |
4716 | int i; | |
4717 | ||
4718 | /* Reset when initting first time or we have a link. */ | |
63c3a66f | 4719 | if (tg3_flag(tp, INIT_COMPLETE) && |
1da177e4 LT |
4720 | !(mac_status & MAC_STATUS_PCS_SYNCED)) |
4721 | return; | |
4722 | ||
4723 | /* Set PLL lock range. */ | |
4724 | tg3_writephy(tp, 0x16, 0x8007); | |
4725 | ||
4726 | /* SW reset */ | |
4727 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
4728 | ||
4729 | /* Wait for reset to complete. */ | |
4730 | /* XXX schedule_timeout() ... */ | |
4731 | for (i = 0; i < 500; i++) | |
4732 | udelay(10); | |
4733 | ||
4734 | /* Config mode; select PMA/Ch 1 regs. */ | |
4735 | tg3_writephy(tp, 0x10, 0x8411); | |
4736 | ||
4737 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
4738 | tg3_writephy(tp, 0x11, 0x0a10); | |
4739 | ||
4740 | tg3_writephy(tp, 0x18, 0x00a0); | |
4741 | tg3_writephy(tp, 0x16, 0x41ff); | |
4742 | ||
4743 | /* Assert and deassert POR. */ | |
4744 | tg3_writephy(tp, 0x13, 0x0400); | |
4745 | udelay(40); | |
4746 | tg3_writephy(tp, 0x13, 0x0000); | |
4747 | ||
4748 | tg3_writephy(tp, 0x11, 0x0a50); | |
4749 | udelay(40); | |
4750 | tg3_writephy(tp, 0x11, 0x0a10); | |
4751 | ||
4752 | /* Wait for signal to stabilize */ | |
4753 | /* XXX schedule_timeout() ... */ | |
4754 | for (i = 0; i < 15000; i++) | |
4755 | udelay(10); | |
4756 | ||
4757 | /* Deselect the channel register so we can read the PHYID | |
4758 | * later. | |
4759 | */ | |
4760 | tg3_writephy(tp, 0x10, 0x8011); | |
4761 | } | |
4762 | ||
4763 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
4764 | { | |
82cd3d11 | 4765 | u16 flowctrl; |
1da177e4 LT |
4766 | u32 sg_dig_ctrl, sg_dig_status; |
4767 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
4768 | int workaround, port_a; | |
4769 | int current_link_up; | |
4770 | ||
4771 | serdes_cfg = 0; | |
4772 | expected_sg_dig_ctrl = 0; | |
4773 | workaround = 0; | |
4774 | port_a = 1; | |
4775 | current_link_up = 0; | |
4776 | ||
4777 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
4778 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
4779 | workaround = 1; | |
4780 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
4781 | port_a = 0; | |
4782 | ||
4783 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
4784 | /* preserve bits 20-23 for voltage regulator */ | |
4785 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
4786 | } | |
4787 | ||
4788 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
4789 | ||
4790 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 4791 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
4792 | if (workaround) { |
4793 | u32 val = serdes_cfg; | |
4794 | ||
4795 | if (port_a) | |
4796 | val |= 0xc010000; | |
4797 | else | |
4798 | val |= 0x4010000; | |
4799 | tw32_f(MAC_SERDES_CFG, val); | |
4800 | } | |
c98f6e3b MC |
4801 | |
4802 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
4803 | } |
4804 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
4805 | tg3_setup_flow_control(tp, 0, 0); | |
4806 | current_link_up = 1; | |
4807 | } | |
4808 | goto out; | |
4809 | } | |
4810 | ||
4811 | /* Want auto-negotiation. */ | |
c98f6e3b | 4812 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 4813 | |
82cd3d11 MC |
4814 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
4815 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4816 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
4817 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4818 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
4819 | |
4820 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 4821 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
4822 | tp->serdes_counter && |
4823 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
4824 | MAC_STATUS_RCVD_CFG)) == | |
4825 | MAC_STATUS_PCS_SYNCED)) { | |
4826 | tp->serdes_counter--; | |
4827 | current_link_up = 1; | |
4828 | goto out; | |
4829 | } | |
4830 | restart_autoneg: | |
1da177e4 LT |
4831 | if (workaround) |
4832 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 4833 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
4834 | udelay(5); |
4835 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
4836 | ||
3d3ebe74 | 4837 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 4838 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4839 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
4840 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 4841 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
4842 | mac_status = tr32(MAC_STATUS); |
4843 | ||
c98f6e3b | 4844 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 4845 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
4846 | u32 local_adv = 0, remote_adv = 0; |
4847 | ||
4848 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
4849 | local_adv |= ADVERTISE_1000XPAUSE; | |
4850 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
4851 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 4852 | |
c98f6e3b | 4853 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 4854 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 4855 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 4856 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 | 4857 | |
859edb26 MC |
4858 | tp->link_config.rmt_adv = |
4859 | mii_adv_to_ethtool_adv_x(remote_adv); | |
4860 | ||
1da177e4 LT |
4861 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
4862 | current_link_up = 1; | |
3d3ebe74 | 4863 | tp->serdes_counter = 0; |
f07e9af3 | 4864 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 4865 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
4866 | if (tp->serdes_counter) |
4867 | tp->serdes_counter--; | |
1da177e4 LT |
4868 | else { |
4869 | if (workaround) { | |
4870 | u32 val = serdes_cfg; | |
4871 | ||
4872 | if (port_a) | |
4873 | val |= 0xc010000; | |
4874 | else | |
4875 | val |= 0x4010000; | |
4876 | ||
4877 | tw32_f(MAC_SERDES_CFG, val); | |
4878 | } | |
4879 | ||
c98f6e3b | 4880 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
4881 | udelay(40); |
4882 | ||
4883 | /* Link parallel detection - link is up */ | |
4884 | /* only if we have PCS_SYNC and not */ | |
4885 | /* receiving config code words */ | |
4886 | mac_status = tr32(MAC_STATUS); | |
4887 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
4888 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
4889 | tg3_setup_flow_control(tp, 0, 0); | |
4890 | current_link_up = 1; | |
f07e9af3 MC |
4891 | tp->phy_flags |= |
4892 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
4893 | tp->serdes_counter = |
4894 | SERDES_PARALLEL_DET_TIMEOUT; | |
4895 | } else | |
4896 | goto restart_autoneg; | |
1da177e4 LT |
4897 | } |
4898 | } | |
3d3ebe74 MC |
4899 | } else { |
4900 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 4901 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4902 | } |
4903 | ||
4904 | out: | |
4905 | return current_link_up; | |
4906 | } | |
4907 | ||
4908 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
4909 | { | |
4910 | int current_link_up = 0; | |
4911 | ||
5cf64b8a | 4912 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 4913 | goto out; |
1da177e4 LT |
4914 | |
4915 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 4916 | u32 txflags, rxflags; |
1da177e4 | 4917 | int i; |
6aa20a22 | 4918 | |
5be73b47 MC |
4919 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
4920 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 4921 | |
5be73b47 MC |
4922 | if (txflags & ANEG_CFG_PS1) |
4923 | local_adv |= ADVERTISE_1000XPAUSE; | |
4924 | if (txflags & ANEG_CFG_PS2) | |
4925 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
4926 | ||
4927 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
4928 | remote_adv |= LPA_1000XPAUSE; | |
4929 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
4930 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 | 4931 | |
859edb26 MC |
4932 | tp->link_config.rmt_adv = |
4933 | mii_adv_to_ethtool_adv_x(remote_adv); | |
4934 | ||
1da177e4 LT |
4935 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
4936 | ||
1da177e4 LT |
4937 | current_link_up = 1; |
4938 | } | |
4939 | for (i = 0; i < 30; i++) { | |
4940 | udelay(20); | |
4941 | tw32_f(MAC_STATUS, | |
4942 | (MAC_STATUS_SYNC_CHANGED | | |
4943 | MAC_STATUS_CFG_CHANGED)); | |
4944 | udelay(40); | |
4945 | if ((tr32(MAC_STATUS) & | |
4946 | (MAC_STATUS_SYNC_CHANGED | | |
4947 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4948 | break; | |
4949 | } | |
4950 | ||
4951 | mac_status = tr32(MAC_STATUS); | |
4952 | if (current_link_up == 0 && | |
4953 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4954 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4955 | current_link_up = 1; | |
4956 | } else { | |
5be73b47 MC |
4957 | tg3_setup_flow_control(tp, 0, 0); |
4958 | ||
1da177e4 LT |
4959 | /* Forcing 1000FD link up. */ |
4960 | current_link_up = 1; | |
1da177e4 LT |
4961 | |
4962 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4963 | udelay(40); | |
e8f3f6ca MC |
4964 | |
4965 | tw32_f(MAC_MODE, tp->mac_mode); | |
4966 | udelay(40); | |
1da177e4 LT |
4967 | } |
4968 | ||
4969 | out: | |
4970 | return current_link_up; | |
4971 | } | |
4972 | ||
4973 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4974 | { | |
4975 | u32 orig_pause_cfg; | |
4976 | u16 orig_active_speed; | |
4977 | u8 orig_active_duplex; | |
4978 | u32 mac_status; | |
4979 | int current_link_up; | |
4980 | int i; | |
4981 | ||
8d018621 | 4982 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4983 | orig_active_speed = tp->link_config.active_speed; |
4984 | orig_active_duplex = tp->link_config.active_duplex; | |
4985 | ||
63c3a66f | 4986 | if (!tg3_flag(tp, HW_AUTONEG) && |
1da177e4 | 4987 | netif_carrier_ok(tp->dev) && |
63c3a66f | 4988 | tg3_flag(tp, INIT_COMPLETE)) { |
1da177e4 LT |
4989 | mac_status = tr32(MAC_STATUS); |
4990 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4991 | MAC_STATUS_SIGNAL_DET | | |
4992 | MAC_STATUS_CFG_CHANGED | | |
4993 | MAC_STATUS_RCVD_CFG); | |
4994 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4995 | MAC_STATUS_SIGNAL_DET)) { | |
4996 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4997 | MAC_STATUS_CFG_CHANGED)); | |
4998 | return 0; | |
4999 | } | |
5000 | } | |
5001 | ||
5002 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
5003 | ||
5004 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
5005 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
5006 | tw32_f(MAC_MODE, tp->mac_mode); | |
5007 | udelay(40); | |
5008 | ||
79eb6904 | 5009 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
5010 | tg3_init_bcm8002(tp); |
5011 | ||
5012 | /* Enable link change event even when serdes polling. */ | |
5013 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
5014 | udelay(40); | |
5015 | ||
5016 | current_link_up = 0; | |
859edb26 | 5017 | tp->link_config.rmt_adv = 0; |
1da177e4 LT |
5018 | mac_status = tr32(MAC_STATUS); |
5019 | ||
63c3a66f | 5020 | if (tg3_flag(tp, HW_AUTONEG)) |
1da177e4 LT |
5021 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); |
5022 | else | |
5023 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
5024 | ||
898a56f8 | 5025 | tp->napi[0].hw_status->status = |
1da177e4 | 5026 | (SD_STATUS_UPDATED | |
898a56f8 | 5027 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
5028 | |
5029 | for (i = 0; i < 100; i++) { | |
5030 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
5031 | MAC_STATUS_CFG_CHANGED)); | |
5032 | udelay(5); | |
5033 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
5034 | MAC_STATUS_CFG_CHANGED | |
5035 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
5036 | break; |
5037 | } | |
5038 | ||
5039 | mac_status = tr32(MAC_STATUS); | |
5040 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
5041 | current_link_up = 0; | |
3d3ebe74 MC |
5042 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
5043 | tp->serdes_counter == 0) { | |
1da177e4 LT |
5044 | tw32_f(MAC_MODE, (tp->mac_mode | |
5045 | MAC_MODE_SEND_CONFIGS)); | |
5046 | udelay(1); | |
5047 | tw32_f(MAC_MODE, tp->mac_mode); | |
5048 | } | |
5049 | } | |
5050 | ||
5051 | if (current_link_up == 1) { | |
5052 | tp->link_config.active_speed = SPEED_1000; | |
5053 | tp->link_config.active_duplex = DUPLEX_FULL; | |
5054 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
5055 | LED_CTRL_LNKLED_OVERRIDE | | |
5056 | LED_CTRL_1000MBPS_ON)); | |
5057 | } else { | |
e740522e MC |
5058 | tp->link_config.active_speed = SPEED_UNKNOWN; |
5059 | tp->link_config.active_duplex = DUPLEX_UNKNOWN; | |
1da177e4 LT |
5060 | tw32(MAC_LED_CTRL, (tp->led_ctrl | |
5061 | LED_CTRL_LNKLED_OVERRIDE | | |
5062 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
5063 | } | |
5064 | ||
5065 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
5066 | if (current_link_up) | |
5067 | netif_carrier_on(tp->dev); | |
5068 | else | |
5069 | netif_carrier_off(tp->dev); | |
5070 | tg3_link_report(tp); | |
5071 | } else { | |
8d018621 | 5072 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
5073 | if (orig_pause_cfg != now_pause_cfg || |
5074 | orig_active_speed != tp->link_config.active_speed || | |
5075 | orig_active_duplex != tp->link_config.active_duplex) | |
5076 | tg3_link_report(tp); | |
5077 | } | |
5078 | ||
5079 | return 0; | |
5080 | } | |
5081 | ||
747e8f8b MC |
5082 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
5083 | { | |
5084 | int current_link_up, err = 0; | |
5085 | u32 bmsr, bmcr; | |
5086 | u16 current_speed; | |
5087 | u8 current_duplex; | |
ef167e27 | 5088 | u32 local_adv, remote_adv; |
747e8f8b MC |
5089 | |
5090 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
5091 | tw32_f(MAC_MODE, tp->mac_mode); | |
5092 | udelay(40); | |
5093 | ||
5094 | tw32(MAC_EVENT, 0); | |
5095 | ||
5096 | tw32_f(MAC_STATUS, | |
5097 | (MAC_STATUS_SYNC_CHANGED | | |
5098 | MAC_STATUS_CFG_CHANGED | | |
5099 | MAC_STATUS_MI_COMPLETION | | |
5100 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5101 | udelay(40); | |
5102 | ||
5103 | if (force_reset) | |
5104 | tg3_phy_reset(tp); | |
5105 | ||
5106 | current_link_up = 0; | |
e740522e MC |
5107 | current_speed = SPEED_UNKNOWN; |
5108 | current_duplex = DUPLEX_UNKNOWN; | |
859edb26 | 5109 | tp->link_config.rmt_adv = 0; |
747e8f8b MC |
5110 | |
5111 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
5112 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
5113 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
5114 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
5115 | bmsr |= BMSR_LSTATUS; | |
5116 | else | |
5117 | bmsr &= ~BMSR_LSTATUS; | |
5118 | } | |
747e8f8b MC |
5119 | |
5120 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
5121 | ||
5122 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 5123 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
5124 | /* do nothing, just check for link up at the end */ |
5125 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
28011cf1 | 5126 | u32 adv, newadv; |
747e8f8b MC |
5127 | |
5128 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
28011cf1 MC |
5129 | newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | |
5130 | ADVERTISE_1000XPAUSE | | |
5131 | ADVERTISE_1000XPSE_ASYM | | |
5132 | ADVERTISE_SLCT); | |
747e8f8b | 5133 | |
28011cf1 | 5134 | newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
37f07023 | 5135 | newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); |
747e8f8b | 5136 | |
28011cf1 MC |
5137 | if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) { |
5138 | tg3_writephy(tp, MII_ADVERTISE, newadv); | |
747e8f8b MC |
5139 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; |
5140 | tg3_writephy(tp, MII_BMCR, bmcr); | |
5141 | ||
5142 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 5143 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 5144 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5145 | |
5146 | return err; | |
5147 | } | |
5148 | } else { | |
5149 | u32 new_bmcr; | |
5150 | ||
5151 | bmcr &= ~BMCR_SPEED1000; | |
5152 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
5153 | ||
5154 | if (tp->link_config.duplex == DUPLEX_FULL) | |
5155 | new_bmcr |= BMCR_FULLDPLX; | |
5156 | ||
5157 | if (new_bmcr != bmcr) { | |
5158 | /* BMCR_SPEED1000 is a reserved bit that needs | |
5159 | * to be set on write. | |
5160 | */ | |
5161 | new_bmcr |= BMCR_SPEED1000; | |
5162 | ||
5163 | /* Force a linkdown */ | |
5164 | if (netif_carrier_ok(tp->dev)) { | |
5165 | u32 adv; | |
5166 | ||
5167 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
5168 | adv &= ~(ADVERTISE_1000XFULL | | |
5169 | ADVERTISE_1000XHALF | | |
5170 | ADVERTISE_SLCT); | |
5171 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
5172 | tg3_writephy(tp, MII_BMCR, bmcr | | |
5173 | BMCR_ANRESTART | | |
5174 | BMCR_ANENABLE); | |
5175 | udelay(10); | |
5176 | netif_carrier_off(tp->dev); | |
5177 | } | |
5178 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
5179 | bmcr = new_bmcr; | |
5180 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
5181 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
5182 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
5183 | ASIC_REV_5714) { | |
5184 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
5185 | bmsr |= BMSR_LSTATUS; | |
5186 | else | |
5187 | bmsr &= ~BMSR_LSTATUS; | |
5188 | } | |
f07e9af3 | 5189 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5190 | } |
5191 | } | |
5192 | ||
5193 | if (bmsr & BMSR_LSTATUS) { | |
5194 | current_speed = SPEED_1000; | |
5195 | current_link_up = 1; | |
5196 | if (bmcr & BMCR_FULLDPLX) | |
5197 | current_duplex = DUPLEX_FULL; | |
5198 | else | |
5199 | current_duplex = DUPLEX_HALF; | |
5200 | ||
ef167e27 MC |
5201 | local_adv = 0; |
5202 | remote_adv = 0; | |
5203 | ||
747e8f8b | 5204 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 5205 | u32 common; |
747e8f8b MC |
5206 | |
5207 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
5208 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
5209 | common = local_adv & remote_adv; | |
5210 | if (common & (ADVERTISE_1000XHALF | | |
5211 | ADVERTISE_1000XFULL)) { | |
5212 | if (common & ADVERTISE_1000XFULL) | |
5213 | current_duplex = DUPLEX_FULL; | |
5214 | else | |
5215 | current_duplex = DUPLEX_HALF; | |
859edb26 MC |
5216 | |
5217 | tp->link_config.rmt_adv = | |
5218 | mii_adv_to_ethtool_adv_x(remote_adv); | |
63c3a66f | 5219 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
57d8b880 | 5220 | /* Link is up via parallel detect */ |
859a5887 | 5221 | } else { |
747e8f8b | 5222 | current_link_up = 0; |
859a5887 | 5223 | } |
747e8f8b MC |
5224 | } |
5225 | } | |
5226 | ||
ef167e27 MC |
5227 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
5228 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
5229 | ||
747e8f8b MC |
5230 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
5231 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
5232 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
5233 | ||
5234 | tw32_f(MAC_MODE, tp->mac_mode); | |
5235 | udelay(40); | |
5236 | ||
5237 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
5238 | ||
5239 | tp->link_config.active_speed = current_speed; | |
5240 | tp->link_config.active_duplex = current_duplex; | |
5241 | ||
5242 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
5243 | if (current_link_up) | |
5244 | netif_carrier_on(tp->dev); | |
5245 | else { | |
5246 | netif_carrier_off(tp->dev); | |
f07e9af3 | 5247 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5248 | } |
5249 | tg3_link_report(tp); | |
5250 | } | |
5251 | return err; | |
5252 | } | |
5253 | ||
5254 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
5255 | { | |
3d3ebe74 | 5256 | if (tp->serdes_counter) { |
747e8f8b | 5257 | /* Give autoneg time to complete. */ |
3d3ebe74 | 5258 | tp->serdes_counter--; |
747e8f8b MC |
5259 | return; |
5260 | } | |
c6cdf436 | 5261 | |
747e8f8b MC |
5262 | if (!netif_carrier_ok(tp->dev) && |
5263 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
5264 | u32 bmcr; | |
5265 | ||
5266 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
5267 | if (bmcr & BMCR_ANENABLE) { | |
5268 | u32 phy1, phy2; | |
5269 | ||
5270 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
5271 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
5272 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
5273 | |
5274 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
5275 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
5276 | MII_TG3_DSP_EXP1_INT_STAT); | |
5277 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
5278 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
5279 | |
5280 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
5281 | /* We have signal detect and not receiving | |
5282 | * config code words, link is up by parallel | |
5283 | * detection. | |
5284 | */ | |
5285 | ||
5286 | bmcr &= ~BMCR_ANENABLE; | |
5287 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
5288 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 5289 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5290 | } |
5291 | } | |
859a5887 MC |
5292 | } else if (netif_carrier_ok(tp->dev) && |
5293 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
f07e9af3 | 5294 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
5295 | u32 phy2; |
5296 | ||
5297 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
5298 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
5299 | MII_TG3_DSP_EXP1_INT_STAT); | |
5300 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
5301 | if (phy2 & 0x20) { |
5302 | u32 bmcr; | |
5303 | ||
5304 | /* Config code words received, turn on autoneg. */ | |
5305 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
5306 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
5307 | ||
f07e9af3 | 5308 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5309 | |
5310 | } | |
5311 | } | |
5312 | } | |
5313 | ||
1da177e4 LT |
5314 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
5315 | { | |
f2096f94 | 5316 | u32 val; |
1da177e4 LT |
5317 | int err; |
5318 | ||
f07e9af3 | 5319 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 5320 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 5321 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 5322 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 5323 | else |
1da177e4 | 5324 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 5325 | |
bcb37f6c | 5326 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
f2096f94 | 5327 | u32 scale; |
aa6c91fe MC |
5328 | |
5329 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
5330 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
5331 | scale = 65; | |
5332 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
5333 | scale = 6; | |
5334 | else | |
5335 | scale = 12; | |
5336 | ||
5337 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
5338 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
5339 | tw32(GRC_MISC_CFG, val); | |
5340 | } | |
5341 | ||
f2096f94 MC |
5342 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
5343 | (6 << TX_LENGTHS_IPG_SHIFT); | |
5344 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
5345 | val |= tr32(MAC_TX_LENGTHS) & | |
5346 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
5347 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
5348 | ||
1da177e4 LT |
5349 | if (tp->link_config.active_speed == SPEED_1000 && |
5350 | tp->link_config.active_duplex == DUPLEX_HALF) | |
f2096f94 MC |
5351 | tw32(MAC_TX_LENGTHS, val | |
5352 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 5353 | else |
f2096f94 MC |
5354 | tw32(MAC_TX_LENGTHS, val | |
5355 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 5356 | |
63c3a66f | 5357 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
5358 | if (netif_carrier_ok(tp->dev)) { |
5359 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 5360 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
5361 | } else { |
5362 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
5363 | } | |
5364 | } | |
5365 | ||
63c3a66f | 5366 | if (tg3_flag(tp, ASPM_WORKAROUND)) { |
f2096f94 | 5367 | val = tr32(PCIE_PWR_MGMT_THRESH); |
8ed5d97e MC |
5368 | if (!netif_carrier_ok(tp->dev)) |
5369 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
5370 | tp->pwrmgmt_thresh; | |
5371 | else | |
5372 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
5373 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
5374 | } | |
5375 | ||
1da177e4 LT |
5376 | return err; |
5377 | } | |
5378 | ||
66cfd1bd MC |
5379 | static inline int tg3_irq_sync(struct tg3 *tp) |
5380 | { | |
5381 | return tp->irq_sync; | |
5382 | } | |
5383 | ||
97bd8e49 MC |
5384 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
5385 | { | |
5386 | int i; | |
5387 | ||
5388 | dst = (u32 *)((u8 *)dst + off); | |
5389 | for (i = 0; i < len; i += sizeof(u32)) | |
5390 | *dst++ = tr32(off + i); | |
5391 | } | |
5392 | ||
5393 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
5394 | { | |
5395 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
5396 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
5397 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
5398 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
5399 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
5400 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
5401 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
5402 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
5403 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
5404 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
5405 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
5406 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
5407 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
5408 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
5409 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
5410 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
5411 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
5412 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
5413 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
5414 | ||
63c3a66f | 5415 | if (tg3_flag(tp, SUPPORT_MSIX)) |
97bd8e49 MC |
5416 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); |
5417 | ||
5418 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
5419 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
5420 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
5421 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
5422 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
5423 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
5424 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
5425 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
5426 | ||
63c3a66f | 5427 | if (!tg3_flag(tp, 5705_PLUS)) { |
97bd8e49 MC |
5428 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); |
5429 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
5430 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
5431 | } | |
5432 | ||
5433 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
5434 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
5435 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
5436 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
5437 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
5438 | ||
63c3a66f | 5439 | if (tg3_flag(tp, NVRAM)) |
97bd8e49 MC |
5440 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); |
5441 | } | |
5442 | ||
5443 | static void tg3_dump_state(struct tg3 *tp) | |
5444 | { | |
5445 | int i; | |
5446 | u32 *regs; | |
5447 | ||
5448 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
5449 | if (!regs) { | |
5450 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
5451 | return; | |
5452 | } | |
5453 | ||
63c3a66f | 5454 | if (tg3_flag(tp, PCI_EXPRESS)) { |
97bd8e49 MC |
5455 | /* Read up to but not including private PCI registers */ |
5456 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
5457 | regs[i / sizeof(u32)] = tr32(i); | |
5458 | } else | |
5459 | tg3_dump_legacy_regs(tp, regs); | |
5460 | ||
5461 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
5462 | if (!regs[i + 0] && !regs[i + 1] && | |
5463 | !regs[i + 2] && !regs[i + 3]) | |
5464 | continue; | |
5465 | ||
5466 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
5467 | i * 4, | |
5468 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
5469 | } | |
5470 | ||
5471 | kfree(regs); | |
5472 | ||
5473 | for (i = 0; i < tp->irq_cnt; i++) { | |
5474 | struct tg3_napi *tnapi = &tp->napi[i]; | |
5475 | ||
5476 | /* SW status block */ | |
5477 | netdev_err(tp->dev, | |
5478 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
5479 | i, | |
5480 | tnapi->hw_status->status, | |
5481 | tnapi->hw_status->status_tag, | |
5482 | tnapi->hw_status->rx_jumbo_consumer, | |
5483 | tnapi->hw_status->rx_consumer, | |
5484 | tnapi->hw_status->rx_mini_consumer, | |
5485 | tnapi->hw_status->idx[0].rx_producer, | |
5486 | tnapi->hw_status->idx[0].tx_consumer); | |
5487 | ||
5488 | netdev_err(tp->dev, | |
5489 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
5490 | i, | |
5491 | tnapi->last_tag, tnapi->last_irq_tag, | |
5492 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
5493 | tnapi->rx_rcb_ptr, | |
5494 | tnapi->prodring.rx_std_prod_idx, | |
5495 | tnapi->prodring.rx_std_cons_idx, | |
5496 | tnapi->prodring.rx_jmb_prod_idx, | |
5497 | tnapi->prodring.rx_jmb_cons_idx); | |
5498 | } | |
5499 | } | |
5500 | ||
df3e6548 MC |
5501 | /* This is called whenever we suspect that the system chipset is re- |
5502 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
5503 | * is bogus tx completions. We try to recover by setting the | |
5504 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
5505 | * in the workqueue. | |
5506 | */ | |
5507 | static void tg3_tx_recover(struct tg3 *tp) | |
5508 | { | |
63c3a66f | 5509 | BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || |
df3e6548 MC |
5510 | tp->write32_tx_mbox == tg3_write_indirect_mbox); |
5511 | ||
5129c3a3 MC |
5512 | netdev_warn(tp->dev, |
5513 | "The system may be re-ordering memory-mapped I/O " | |
5514 | "cycles to the network device, attempting to recover. " | |
5515 | "Please report the problem to the driver maintainer " | |
5516 | "and include system chipset information.\n"); | |
df3e6548 MC |
5517 | |
5518 | spin_lock(&tp->lock); | |
63c3a66f | 5519 | tg3_flag_set(tp, TX_RECOVERY_PENDING); |
df3e6548 MC |
5520 | spin_unlock(&tp->lock); |
5521 | } | |
5522 | ||
f3f3f27e | 5523 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 5524 | { |
f65aac16 MC |
5525 | /* Tell compiler to fetch tx indices from memory. */ |
5526 | barrier(); | |
f3f3f27e MC |
5527 | return tnapi->tx_pending - |
5528 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
5529 | } |
5530 | ||
1da177e4 LT |
5531 | /* Tigon3 never reports partial packet sends. So we do not |
5532 | * need special logic to handle SKBs that have not had all | |
5533 | * of their frags sent yet, like SunGEM does. | |
5534 | */ | |
17375d25 | 5535 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 5536 | { |
17375d25 | 5537 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 5538 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 5539 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
5540 | struct netdev_queue *txq; |
5541 | int index = tnapi - tp->napi; | |
298376d3 | 5542 | unsigned int pkts_compl = 0, bytes_compl = 0; |
fe5f5787 | 5543 | |
63c3a66f | 5544 | if (tg3_flag(tp, ENABLE_TSS)) |
fe5f5787 MC |
5545 | index--; |
5546 | ||
5547 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
5548 | |
5549 | while (sw_idx != hw_idx) { | |
df8944cf | 5550 | struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 5551 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
5552 | int i, tx_bug = 0; |
5553 | ||
5554 | if (unlikely(skb == NULL)) { | |
5555 | tg3_tx_recover(tp); | |
5556 | return; | |
5557 | } | |
1da177e4 | 5558 | |
f4188d8a | 5559 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 5560 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
5561 | skb_headlen(skb), |
5562 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
5563 | |
5564 | ri->skb = NULL; | |
5565 | ||
e01ee14d MC |
5566 | while (ri->fragmented) { |
5567 | ri->fragmented = false; | |
5568 | sw_idx = NEXT_TX(sw_idx); | |
5569 | ri = &tnapi->tx_buffers[sw_idx]; | |
5570 | } | |
5571 | ||
1da177e4 LT |
5572 | sw_idx = NEXT_TX(sw_idx); |
5573 | ||
5574 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 5575 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
5576 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
5577 | tx_bug = 1; | |
f4188d8a AD |
5578 | |
5579 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 5580 | dma_unmap_addr(ri, mapping), |
9e903e08 | 5581 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
f4188d8a | 5582 | PCI_DMA_TODEVICE); |
e01ee14d MC |
5583 | |
5584 | while (ri->fragmented) { | |
5585 | ri->fragmented = false; | |
5586 | sw_idx = NEXT_TX(sw_idx); | |
5587 | ri = &tnapi->tx_buffers[sw_idx]; | |
5588 | } | |
5589 | ||
1da177e4 LT |
5590 | sw_idx = NEXT_TX(sw_idx); |
5591 | } | |
5592 | ||
298376d3 TH |
5593 | pkts_compl++; |
5594 | bytes_compl += skb->len; | |
5595 | ||
f47c11ee | 5596 | dev_kfree_skb(skb); |
df3e6548 MC |
5597 | |
5598 | if (unlikely(tx_bug)) { | |
5599 | tg3_tx_recover(tp); | |
5600 | return; | |
5601 | } | |
1da177e4 LT |
5602 | } |
5603 | ||
5cb917bc | 5604 | netdev_tx_completed_queue(txq, pkts_compl, bytes_compl); |
298376d3 | 5605 | |
f3f3f27e | 5606 | tnapi->tx_cons = sw_idx; |
1da177e4 | 5607 | |
1b2a7205 MC |
5608 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
5609 | * before checking for netif_queue_stopped(). Without the | |
5610 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
5611 | * will miss it and cause the queue to be stopped forever. | |
5612 | */ | |
5613 | smp_mb(); | |
5614 | ||
fe5f5787 | 5615 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 5616 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
5617 | __netif_tx_lock(txq, smp_processor_id()); |
5618 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 5619 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
5620 | netif_tx_wake_queue(txq); |
5621 | __netif_tx_unlock(txq); | |
51b91468 | 5622 | } |
1da177e4 LT |
5623 | } |
5624 | ||
8d4057a9 ED |
5625 | static void tg3_frag_free(bool is_frag, void *data) |
5626 | { | |
5627 | if (is_frag) | |
5628 | put_page(virt_to_head_page(data)); | |
5629 | else | |
5630 | kfree(data); | |
5631 | } | |
5632 | ||
9205fd9c | 5633 | static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
2b2cdb65 | 5634 | { |
8d4057a9 ED |
5635 | unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) + |
5636 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
5637 | ||
9205fd9c | 5638 | if (!ri->data) |
2b2cdb65 MC |
5639 | return; |
5640 | ||
4e5e4f0d | 5641 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 | 5642 | map_sz, PCI_DMA_FROMDEVICE); |
a1e8b307 | 5643 | tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); |
9205fd9c | 5644 | ri->data = NULL; |
2b2cdb65 MC |
5645 | } |
5646 | ||
8d4057a9 | 5647 | |
1da177e4 LT |
5648 | /* Returns size of skb allocated or < 0 on error. |
5649 | * | |
5650 | * We only need to fill in the address because the other members | |
5651 | * of the RX descriptor are invariant, see tg3_init_rings. | |
5652 | * | |
5653 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
5654 | * posting buffers we only dirty the first cache line of the RX | |
5655 | * descriptor (containing the address). Whereas for the RX status | |
5656 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
5657 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
5658 | */ | |
9205fd9c | 5659 | static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
8d4057a9 ED |
5660 | u32 opaque_key, u32 dest_idx_unmasked, |
5661 | unsigned int *frag_size) | |
1da177e4 LT |
5662 | { |
5663 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 5664 | struct ring_info *map; |
9205fd9c | 5665 | u8 *data; |
1da177e4 | 5666 | dma_addr_t mapping; |
9205fd9c | 5667 | int skb_size, data_size, dest_idx; |
1da177e4 | 5668 | |
1da177e4 LT |
5669 | switch (opaque_key) { |
5670 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 5671 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
5672 | desc = &tpr->rx_std[dest_idx]; |
5673 | map = &tpr->rx_std_buffers[dest_idx]; | |
9205fd9c | 5674 | data_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
5675 | break; |
5676 | ||
5677 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 5678 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 5679 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 5680 | map = &tpr->rx_jmb_buffers[dest_idx]; |
9205fd9c | 5681 | data_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
5682 | break; |
5683 | ||
5684 | default: | |
5685 | return -EINVAL; | |
855e1111 | 5686 | } |
1da177e4 LT |
5687 | |
5688 | /* Do not overwrite any of the map or rp information | |
5689 | * until we are sure we can commit to a new buffer. | |
5690 | * | |
5691 | * Callers depend upon this behavior and assume that | |
5692 | * we leave everything unchanged if we fail. | |
5693 | */ | |
9205fd9c ED |
5694 | skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + |
5695 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
a1e8b307 ED |
5696 | if (skb_size <= PAGE_SIZE) { |
5697 | data = netdev_alloc_frag(skb_size); | |
5698 | *frag_size = skb_size; | |
8d4057a9 ED |
5699 | } else { |
5700 | data = kmalloc(skb_size, GFP_ATOMIC); | |
5701 | *frag_size = 0; | |
5702 | } | |
9205fd9c | 5703 | if (!data) |
1da177e4 LT |
5704 | return -ENOMEM; |
5705 | ||
9205fd9c ED |
5706 | mapping = pci_map_single(tp->pdev, |
5707 | data + TG3_RX_OFFSET(tp), | |
5708 | data_size, | |
1da177e4 | 5709 | PCI_DMA_FROMDEVICE); |
8d4057a9 | 5710 | if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) { |
a1e8b307 | 5711 | tg3_frag_free(skb_size <= PAGE_SIZE, data); |
a21771dd MC |
5712 | return -EIO; |
5713 | } | |
1da177e4 | 5714 | |
9205fd9c | 5715 | map->data = data; |
4e5e4f0d | 5716 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 5717 | |
1da177e4 LT |
5718 | desc->addr_hi = ((u64)mapping >> 32); |
5719 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
5720 | ||
9205fd9c | 5721 | return data_size; |
1da177e4 LT |
5722 | } |
5723 | ||
5724 | /* We only need to move over in the address because the other | |
5725 | * members of the RX descriptor are invariant. See notes above | |
9205fd9c | 5726 | * tg3_alloc_rx_data for full details. |
1da177e4 | 5727 | */ |
a3896167 MC |
5728 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
5729 | struct tg3_rx_prodring_set *dpr, | |
5730 | u32 opaque_key, int src_idx, | |
5731 | u32 dest_idx_unmasked) | |
1da177e4 | 5732 | { |
17375d25 | 5733 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
5734 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
5735 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 5736 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 5737 | int dest_idx; |
1da177e4 LT |
5738 | |
5739 | switch (opaque_key) { | |
5740 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 5741 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
5742 | dest_desc = &dpr->rx_std[dest_idx]; |
5743 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
5744 | src_desc = &spr->rx_std[src_idx]; | |
5745 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
5746 | break; |
5747 | ||
5748 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 5749 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
5750 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
5751 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
5752 | src_desc = &spr->rx_jmb[src_idx].std; | |
5753 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
5754 | break; |
5755 | ||
5756 | default: | |
5757 | return; | |
855e1111 | 5758 | } |
1da177e4 | 5759 | |
9205fd9c | 5760 | dest_map->data = src_map->data; |
4e5e4f0d FT |
5761 | dma_unmap_addr_set(dest_map, mapping, |
5762 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
5763 | dest_desc->addr_hi = src_desc->addr_hi; |
5764 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
5765 | |
5766 | /* Ensure that the update to the skb happens after the physical | |
5767 | * addresses have been transferred to the new BD location. | |
5768 | */ | |
5769 | smp_wmb(); | |
5770 | ||
9205fd9c | 5771 | src_map->data = NULL; |
1da177e4 LT |
5772 | } |
5773 | ||
1da177e4 LT |
5774 | /* The RX ring scheme is composed of multiple rings which post fresh |
5775 | * buffers to the chip, and one special ring the chip uses to report | |
5776 | * status back to the host. | |
5777 | * | |
5778 | * The special ring reports the status of received packets to the | |
5779 | * host. The chip does not write into the original descriptor the | |
5780 | * RX buffer was obtained from. The chip simply takes the original | |
5781 | * descriptor as provided by the host, updates the status and length | |
5782 | * field, then writes this into the next status ring entry. | |
5783 | * | |
5784 | * Each ring the host uses to post buffers to the chip is described | |
5785 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
5786 | * it is first placed into the on-chip ram. When the packet's length | |
5787 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
5788 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
5789 | * which is within the range of the new packet's length is chosen. | |
5790 | * | |
5791 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
5792 | * sense from a cache coherency perspective. If only the host writes | |
5793 | * to the buffer post rings, and only the chip writes to the rx status | |
5794 | * rings, then cache lines never move beyond shared-modified state. | |
5795 | * If both the host and chip were to write into the same ring, cache line | |
5796 | * eviction could occur since both entities want it in an exclusive state. | |
5797 | */ | |
17375d25 | 5798 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 5799 | { |
17375d25 | 5800 | struct tg3 *tp = tnapi->tp; |
f92905de | 5801 | u32 work_mask, rx_std_posted = 0; |
4361935a | 5802 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 5803 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 5804 | u16 hw_idx; |
1da177e4 | 5805 | int received; |
8fea32b9 | 5806 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 5807 | |
8d9d7cfc | 5808 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
5809 | /* |
5810 | * We need to order the read of hw_idx and the read of | |
5811 | * the opaque cookie. | |
5812 | */ | |
5813 | rmb(); | |
1da177e4 LT |
5814 | work_mask = 0; |
5815 | received = 0; | |
4361935a MC |
5816 | std_prod_idx = tpr->rx_std_prod_idx; |
5817 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 5818 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 5819 | struct ring_info *ri; |
72334482 | 5820 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
5821 | unsigned int len; |
5822 | struct sk_buff *skb; | |
5823 | dma_addr_t dma_addr; | |
5824 | u32 opaque_key, desc_idx, *post_ptr; | |
9205fd9c | 5825 | u8 *data; |
1da177e4 LT |
5826 | |
5827 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
5828 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
5829 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 5830 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 5831 | dma_addr = dma_unmap_addr(ri, mapping); |
9205fd9c | 5832 | data = ri->data; |
4361935a | 5833 | post_ptr = &std_prod_idx; |
f92905de | 5834 | rx_std_posted++; |
1da177e4 | 5835 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 5836 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 5837 | dma_addr = dma_unmap_addr(ri, mapping); |
9205fd9c | 5838 | data = ri->data; |
4361935a | 5839 | post_ptr = &jmb_prod_idx; |
21f581a5 | 5840 | } else |
1da177e4 | 5841 | goto next_pkt_nopost; |
1da177e4 LT |
5842 | |
5843 | work_mask |= opaque_key; | |
5844 | ||
5845 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
5846 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
5847 | drop_it: | |
a3896167 | 5848 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5849 | desc_idx, *post_ptr); |
5850 | drop_it_no_recycle: | |
5851 | /* Other statistics kept track of by card. */ | |
b0057c51 | 5852 | tp->rx_dropped++; |
1da177e4 LT |
5853 | goto next_pkt; |
5854 | } | |
5855 | ||
9205fd9c | 5856 | prefetch(data + TG3_RX_OFFSET(tp)); |
ad829268 MC |
5857 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
5858 | ETH_FCS_LEN; | |
1da177e4 | 5859 | |
d2757fc4 | 5860 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 | 5861 | int skb_size; |
8d4057a9 | 5862 | unsigned int frag_size; |
1da177e4 | 5863 | |
9205fd9c | 5864 | skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, |
8d4057a9 | 5865 | *post_ptr, &frag_size); |
1da177e4 LT |
5866 | if (skb_size < 0) |
5867 | goto drop_it; | |
5868 | ||
287be12e | 5869 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
5870 | PCI_DMA_FROMDEVICE); |
5871 | ||
8d4057a9 | 5872 | skb = build_skb(data, frag_size); |
9205fd9c | 5873 | if (!skb) { |
8d4057a9 | 5874 | tg3_frag_free(frag_size != 0, data); |
9205fd9c ED |
5875 | goto drop_it_no_recycle; |
5876 | } | |
5877 | skb_reserve(skb, TG3_RX_OFFSET(tp)); | |
5878 | /* Ensure that the update to the data happens | |
61e800cf MC |
5879 | * after the usage of the old DMA mapping. |
5880 | */ | |
5881 | smp_wmb(); | |
5882 | ||
9205fd9c | 5883 | ri->data = NULL; |
61e800cf | 5884 | |
1da177e4 | 5885 | } else { |
a3896167 | 5886 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5887 | desc_idx, *post_ptr); |
5888 | ||
9205fd9c ED |
5889 | skb = netdev_alloc_skb(tp->dev, |
5890 | len + TG3_RAW_IP_ALIGN); | |
5891 | if (skb == NULL) | |
1da177e4 LT |
5892 | goto drop_it_no_recycle; |
5893 | ||
9205fd9c | 5894 | skb_reserve(skb, TG3_RAW_IP_ALIGN); |
1da177e4 | 5895 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
9205fd9c ED |
5896 | memcpy(skb->data, |
5897 | data + TG3_RX_OFFSET(tp), | |
5898 | len); | |
1da177e4 | 5899 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
5900 | } |
5901 | ||
9205fd9c | 5902 | skb_put(skb, len); |
dc668910 | 5903 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
1da177e4 LT |
5904 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
5905 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
5906 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
5907 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5908 | else | |
bc8acf2c | 5909 | skb_checksum_none_assert(skb); |
1da177e4 LT |
5910 | |
5911 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
5912 | |
5913 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
5914 | skb->protocol != htons(ETH_P_8021Q)) { | |
5915 | dev_kfree_skb(skb); | |
b0057c51 | 5916 | goto drop_it_no_recycle; |
f7b493e0 MC |
5917 | } |
5918 | ||
9dc7a113 | 5919 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
5920 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
5921 | __vlan_hwaccel_put_tag(skb, | |
5922 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 5923 | |
bf933c80 | 5924 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 5925 | |
1da177e4 LT |
5926 | received++; |
5927 | budget--; | |
5928 | ||
5929 | next_pkt: | |
5930 | (*post_ptr)++; | |
f92905de MC |
5931 | |
5932 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
5933 | tpr->rx_std_prod_idx = std_prod_idx & |
5934 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
5935 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5936 | tpr->rx_std_prod_idx); | |
f92905de MC |
5937 | work_mask &= ~RXD_OPAQUE_RING_STD; |
5938 | rx_std_posted = 0; | |
5939 | } | |
1da177e4 | 5940 | next_pkt_nopost: |
483ba50b | 5941 | sw_idx++; |
7cb32cf2 | 5942 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
5943 | |
5944 | /* Refresh hw_idx to see if there is new work */ | |
5945 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 5946 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
5947 | rmb(); |
5948 | } | |
1da177e4 LT |
5949 | } |
5950 | ||
5951 | /* ACK the status ring. */ | |
72334482 MC |
5952 | tnapi->rx_rcb_ptr = sw_idx; |
5953 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
5954 | |
5955 | /* Refill RX ring(s). */ | |
63c3a66f | 5956 | if (!tg3_flag(tp, ENABLE_RSS)) { |
6541b806 MC |
5957 | /* Sync BD data before updating mailbox */ |
5958 | wmb(); | |
5959 | ||
b196c7e4 | 5960 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
5961 | tpr->rx_std_prod_idx = std_prod_idx & |
5962 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5963 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5964 | tpr->rx_std_prod_idx); | |
5965 | } | |
5966 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
5967 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
5968 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
5969 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
5970 | tpr->rx_jmb_prod_idx); | |
5971 | } | |
5972 | mmiowb(); | |
5973 | } else if (work_mask) { | |
5974 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
5975 | * updated before the producer indices can be updated. | |
5976 | */ | |
5977 | smp_wmb(); | |
5978 | ||
2c49a44d MC |
5979 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
5980 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 5981 | |
7ae52890 MC |
5982 | if (tnapi != &tp->napi[1]) { |
5983 | tp->rx_refill = true; | |
e4af1af9 | 5984 | napi_schedule(&tp->napi[1].napi); |
7ae52890 | 5985 | } |
1da177e4 | 5986 | } |
1da177e4 LT |
5987 | |
5988 | return received; | |
5989 | } | |
5990 | ||
35f2d7d0 | 5991 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 5992 | { |
1da177e4 | 5993 | /* handle link change and other phy events */ |
63c3a66f | 5994 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
35f2d7d0 MC |
5995 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
5996 | ||
1da177e4 LT |
5997 | if (sblk->status & SD_STATUS_LINK_CHG) { |
5998 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 5999 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 6000 | spin_lock(&tp->lock); |
63c3a66f | 6001 | if (tg3_flag(tp, USE_PHYLIB)) { |
dd477003 MC |
6002 | tw32_f(MAC_STATUS, |
6003 | (MAC_STATUS_SYNC_CHANGED | | |
6004 | MAC_STATUS_CFG_CHANGED | | |
6005 | MAC_STATUS_MI_COMPLETION | | |
6006 | MAC_STATUS_LNKSTATE_CHANGED)); | |
6007 | udelay(40); | |
6008 | } else | |
6009 | tg3_setup_phy(tp, 0); | |
f47c11ee | 6010 | spin_unlock(&tp->lock); |
1da177e4 LT |
6011 | } |
6012 | } | |
35f2d7d0 MC |
6013 | } |
6014 | ||
f89f38b8 MC |
6015 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
6016 | struct tg3_rx_prodring_set *dpr, | |
6017 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
6018 | { |
6019 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 6020 | int i, err = 0; |
b196c7e4 MC |
6021 | |
6022 | while (1) { | |
6023 | src_prod_idx = spr->rx_std_prod_idx; | |
6024 | ||
6025 | /* Make sure updates to the rx_std_buffers[] entries and the | |
6026 | * standard producer index are seen in the correct order. | |
6027 | */ | |
6028 | smp_rmb(); | |
6029 | ||
6030 | if (spr->rx_std_cons_idx == src_prod_idx) | |
6031 | break; | |
6032 | ||
6033 | if (spr->rx_std_cons_idx < src_prod_idx) | |
6034 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
6035 | else | |
2c49a44d MC |
6036 | cpycnt = tp->rx_std_ring_mask + 1 - |
6037 | spr->rx_std_cons_idx; | |
b196c7e4 | 6038 | |
2c49a44d MC |
6039 | cpycnt = min(cpycnt, |
6040 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
6041 | |
6042 | si = spr->rx_std_cons_idx; | |
6043 | di = dpr->rx_std_prod_idx; | |
6044 | ||
e92967bf | 6045 | for (i = di; i < di + cpycnt; i++) { |
9205fd9c | 6046 | if (dpr->rx_std_buffers[i].data) { |
e92967bf | 6047 | cpycnt = i - di; |
f89f38b8 | 6048 | err = -ENOSPC; |
e92967bf MC |
6049 | break; |
6050 | } | |
6051 | } | |
6052 | ||
6053 | if (!cpycnt) | |
6054 | break; | |
6055 | ||
6056 | /* Ensure that updates to the rx_std_buffers ring and the | |
6057 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
6058 | * ordered correctly WRT the skb check above. | |
6059 | */ | |
6060 | smp_rmb(); | |
6061 | ||
b196c7e4 MC |
6062 | memcpy(&dpr->rx_std_buffers[di], |
6063 | &spr->rx_std_buffers[si], | |
6064 | cpycnt * sizeof(struct ring_info)); | |
6065 | ||
6066 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
6067 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
6068 | sbd = &spr->rx_std[si]; | |
6069 | dbd = &dpr->rx_std[di]; | |
6070 | dbd->addr_hi = sbd->addr_hi; | |
6071 | dbd->addr_lo = sbd->addr_lo; | |
6072 | } | |
6073 | ||
2c49a44d MC |
6074 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
6075 | tp->rx_std_ring_mask; | |
6076 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
6077 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
6078 | } |
6079 | ||
6080 | while (1) { | |
6081 | src_prod_idx = spr->rx_jmb_prod_idx; | |
6082 | ||
6083 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
6084 | * the jumbo producer index are seen in the correct order. | |
6085 | */ | |
6086 | smp_rmb(); | |
6087 | ||
6088 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
6089 | break; | |
6090 | ||
6091 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
6092 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
6093 | else | |
2c49a44d MC |
6094 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
6095 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
6096 | |
6097 | cpycnt = min(cpycnt, | |
2c49a44d | 6098 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
6099 | |
6100 | si = spr->rx_jmb_cons_idx; | |
6101 | di = dpr->rx_jmb_prod_idx; | |
6102 | ||
e92967bf | 6103 | for (i = di; i < di + cpycnt; i++) { |
9205fd9c | 6104 | if (dpr->rx_jmb_buffers[i].data) { |
e92967bf | 6105 | cpycnt = i - di; |
f89f38b8 | 6106 | err = -ENOSPC; |
e92967bf MC |
6107 | break; |
6108 | } | |
6109 | } | |
6110 | ||
6111 | if (!cpycnt) | |
6112 | break; | |
6113 | ||
6114 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
6115 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
6116 | * ordered correctly WRT the skb check above. | |
6117 | */ | |
6118 | smp_rmb(); | |
6119 | ||
b196c7e4 MC |
6120 | memcpy(&dpr->rx_jmb_buffers[di], |
6121 | &spr->rx_jmb_buffers[si], | |
6122 | cpycnt * sizeof(struct ring_info)); | |
6123 | ||
6124 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
6125 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
6126 | sbd = &spr->rx_jmb[si].std; | |
6127 | dbd = &dpr->rx_jmb[di].std; | |
6128 | dbd->addr_hi = sbd->addr_hi; | |
6129 | dbd->addr_lo = sbd->addr_lo; | |
6130 | } | |
6131 | ||
2c49a44d MC |
6132 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
6133 | tp->rx_jmb_ring_mask; | |
6134 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
6135 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 6136 | } |
f89f38b8 MC |
6137 | |
6138 | return err; | |
b196c7e4 MC |
6139 | } |
6140 | ||
35f2d7d0 MC |
6141 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
6142 | { | |
6143 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
6144 | |
6145 | /* run TX completion thread */ | |
f3f3f27e | 6146 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 6147 | tg3_tx(tnapi); |
63c3a66f | 6148 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
4fd7ab59 | 6149 | return work_done; |
1da177e4 LT |
6150 | } |
6151 | ||
f891ea16 MC |
6152 | if (!tnapi->rx_rcb_prod_idx) |
6153 | return work_done; | |
6154 | ||
1da177e4 LT |
6155 | /* run RX thread, within the bounds set by NAPI. |
6156 | * All RX "locking" is done by ensuring outside | |
bea3348e | 6157 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 6158 | */ |
8d9d7cfc | 6159 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 6160 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 6161 | |
63c3a66f | 6162 | if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 6163 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 6164 | int i, err = 0; |
e4af1af9 MC |
6165 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
6166 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 6167 | |
7ae52890 | 6168 | tp->rx_refill = false; |
e4af1af9 | 6169 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 | 6170 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 6171 | &tp->napi[i].prodring); |
b196c7e4 MC |
6172 | |
6173 | wmb(); | |
6174 | ||
e4af1af9 MC |
6175 | if (std_prod_idx != dpr->rx_std_prod_idx) |
6176 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
6177 | dpr->rx_std_prod_idx); | |
b196c7e4 | 6178 | |
e4af1af9 MC |
6179 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
6180 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
6181 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
6182 | |
6183 | mmiowb(); | |
f89f38b8 MC |
6184 | |
6185 | if (err) | |
6186 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
6187 | } |
6188 | ||
6f535763 DM |
6189 | return work_done; |
6190 | } | |
6191 | ||
db219973 MC |
6192 | static inline void tg3_reset_task_schedule(struct tg3 *tp) |
6193 | { | |
6194 | if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) | |
6195 | schedule_work(&tp->reset_task); | |
6196 | } | |
6197 | ||
6198 | static inline void tg3_reset_task_cancel(struct tg3 *tp) | |
6199 | { | |
6200 | cancel_work_sync(&tp->reset_task); | |
6201 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
c7101359 | 6202 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); |
db219973 MC |
6203 | } |
6204 | ||
35f2d7d0 MC |
6205 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
6206 | { | |
6207 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
6208 | struct tg3 *tp = tnapi->tp; | |
6209 | int work_done = 0; | |
6210 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
6211 | ||
6212 | while (1) { | |
6213 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
6214 | ||
63c3a66f | 6215 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
35f2d7d0 MC |
6216 | goto tx_recovery; |
6217 | ||
6218 | if (unlikely(work_done >= budget)) | |
6219 | break; | |
6220 | ||
c6cdf436 | 6221 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
6222 | * to tell the hw how much work has been processed, |
6223 | * so we must read it before checking for more work. | |
6224 | */ | |
6225 | tnapi->last_tag = sblk->status_tag; | |
6226 | tnapi->last_irq_tag = tnapi->last_tag; | |
6227 | rmb(); | |
6228 | ||
6229 | /* check for RX/TX work to do */ | |
6d40db7b MC |
6230 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
6231 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
7ae52890 MC |
6232 | |
6233 | /* This test here is not race free, but will reduce | |
6234 | * the number of interrupts by looping again. | |
6235 | */ | |
6236 | if (tnapi == &tp->napi[1] && tp->rx_refill) | |
6237 | continue; | |
6238 | ||
35f2d7d0 MC |
6239 | napi_complete(napi); |
6240 | /* Reenable interrupts. */ | |
6241 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
7ae52890 MC |
6242 | |
6243 | /* This test here is synchronized by napi_schedule() | |
6244 | * and napi_complete() to close the race condition. | |
6245 | */ | |
6246 | if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { | |
6247 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
6248 | HOSTCC_MODE_ENABLE | | |
6249 | tnapi->coal_now); | |
6250 | } | |
35f2d7d0 MC |
6251 | mmiowb(); |
6252 | break; | |
6253 | } | |
6254 | } | |
6255 | ||
6256 | return work_done; | |
6257 | ||
6258 | tx_recovery: | |
6259 | /* work_done is guaranteed to be less than budget. */ | |
6260 | napi_complete(napi); | |
db219973 | 6261 | tg3_reset_task_schedule(tp); |
35f2d7d0 MC |
6262 | return work_done; |
6263 | } | |
6264 | ||
e64de4e6 MC |
6265 | static void tg3_process_error(struct tg3 *tp) |
6266 | { | |
6267 | u32 val; | |
6268 | bool real_error = false; | |
6269 | ||
63c3a66f | 6270 | if (tg3_flag(tp, ERROR_PROCESSED)) |
e64de4e6 MC |
6271 | return; |
6272 | ||
6273 | /* Check Flow Attention register */ | |
6274 | val = tr32(HOSTCC_FLOW_ATTN); | |
6275 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
6276 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
6277 | real_error = true; | |
6278 | } | |
6279 | ||
6280 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
6281 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
6282 | real_error = true; | |
6283 | } | |
6284 | ||
6285 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
6286 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
6287 | real_error = true; | |
6288 | } | |
6289 | ||
6290 | if (!real_error) | |
6291 | return; | |
6292 | ||
6293 | tg3_dump_state(tp); | |
6294 | ||
63c3a66f | 6295 | tg3_flag_set(tp, ERROR_PROCESSED); |
db219973 | 6296 | tg3_reset_task_schedule(tp); |
e64de4e6 MC |
6297 | } |
6298 | ||
6f535763 DM |
6299 | static int tg3_poll(struct napi_struct *napi, int budget) |
6300 | { | |
8ef0442f MC |
6301 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
6302 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 6303 | int work_done = 0; |
898a56f8 | 6304 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
6305 | |
6306 | while (1) { | |
e64de4e6 MC |
6307 | if (sblk->status & SD_STATUS_ERROR) |
6308 | tg3_process_error(tp); | |
6309 | ||
35f2d7d0 MC |
6310 | tg3_poll_link(tp); |
6311 | ||
17375d25 | 6312 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 | 6313 | |
63c3a66f | 6314 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
6f535763 DM |
6315 | goto tx_recovery; |
6316 | ||
6317 | if (unlikely(work_done >= budget)) | |
6318 | break; | |
6319 | ||
63c3a66f | 6320 | if (tg3_flag(tp, TAGGED_STATUS)) { |
17375d25 | 6321 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
6322 | * to tell the hw how much work has been processed, |
6323 | * so we must read it before checking for more work. | |
6324 | */ | |
898a56f8 MC |
6325 | tnapi->last_tag = sblk->status_tag; |
6326 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
6327 | rmb(); |
6328 | } else | |
6329 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 6330 | |
17375d25 | 6331 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 6332 | napi_complete(napi); |
17375d25 | 6333 | tg3_int_reenable(tnapi); |
6f535763 DM |
6334 | break; |
6335 | } | |
1da177e4 LT |
6336 | } |
6337 | ||
bea3348e | 6338 | return work_done; |
6f535763 DM |
6339 | |
6340 | tx_recovery: | |
4fd7ab59 | 6341 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 6342 | napi_complete(napi); |
db219973 | 6343 | tg3_reset_task_schedule(tp); |
4fd7ab59 | 6344 | return work_done; |
1da177e4 LT |
6345 | } |
6346 | ||
66cfd1bd MC |
6347 | static void tg3_napi_disable(struct tg3 *tp) |
6348 | { | |
6349 | int i; | |
6350 | ||
6351 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
6352 | napi_disable(&tp->napi[i].napi); | |
6353 | } | |
6354 | ||
6355 | static void tg3_napi_enable(struct tg3 *tp) | |
6356 | { | |
6357 | int i; | |
6358 | ||
6359 | for (i = 0; i < tp->irq_cnt; i++) | |
6360 | napi_enable(&tp->napi[i].napi); | |
6361 | } | |
6362 | ||
6363 | static void tg3_napi_init(struct tg3 *tp) | |
6364 | { | |
6365 | int i; | |
6366 | ||
6367 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
6368 | for (i = 1; i < tp->irq_cnt; i++) | |
6369 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
6370 | } | |
6371 | ||
6372 | static void tg3_napi_fini(struct tg3 *tp) | |
6373 | { | |
6374 | int i; | |
6375 | ||
6376 | for (i = 0; i < tp->irq_cnt; i++) | |
6377 | netif_napi_del(&tp->napi[i].napi); | |
6378 | } | |
6379 | ||
6380 | static inline void tg3_netif_stop(struct tg3 *tp) | |
6381 | { | |
6382 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
6383 | tg3_napi_disable(tp); | |
6384 | netif_tx_disable(tp->dev); | |
6385 | } | |
6386 | ||
6387 | static inline void tg3_netif_start(struct tg3 *tp) | |
6388 | { | |
6389 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
6390 | * appropriate so long as all callers are assured to | |
6391 | * have free tx slots (such as after tg3_init_hw) | |
6392 | */ | |
6393 | netif_tx_wake_all_queues(tp->dev); | |
6394 | ||
6395 | tg3_napi_enable(tp); | |
6396 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
6397 | tg3_enable_ints(tp); | |
6398 | } | |
6399 | ||
f47c11ee DM |
6400 | static void tg3_irq_quiesce(struct tg3 *tp) |
6401 | { | |
4f125f42 MC |
6402 | int i; |
6403 | ||
f47c11ee DM |
6404 | BUG_ON(tp->irq_sync); |
6405 | ||
6406 | tp->irq_sync = 1; | |
6407 | smp_mb(); | |
6408 | ||
4f125f42 MC |
6409 | for (i = 0; i < tp->irq_cnt; i++) |
6410 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
6411 | } |
6412 | ||
f47c11ee DM |
6413 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
6414 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
6415 | * with as well. Most of the time, this is not necessary except when | |
6416 | * shutting down the device. | |
6417 | */ | |
6418 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
6419 | { | |
46966545 | 6420 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
6421 | if (irq_sync) |
6422 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
6423 | } |
6424 | ||
6425 | static inline void tg3_full_unlock(struct tg3 *tp) | |
6426 | { | |
f47c11ee DM |
6427 | spin_unlock_bh(&tp->lock); |
6428 | } | |
6429 | ||
fcfa0a32 MC |
6430 | /* One-shot MSI handler - Chip automatically disables interrupt |
6431 | * after sending MSI so driver doesn't have to do it. | |
6432 | */ | |
7d12e780 | 6433 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 6434 | { |
09943a18 MC |
6435 | struct tg3_napi *tnapi = dev_id; |
6436 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 6437 | |
898a56f8 | 6438 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
6439 | if (tnapi->rx_rcb) |
6440 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
6441 | |
6442 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 6443 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
6444 | |
6445 | return IRQ_HANDLED; | |
6446 | } | |
6447 | ||
88b06bc2 MC |
6448 | /* MSI ISR - No need to check for interrupt sharing and no need to |
6449 | * flush status block and interrupt mailbox. PCI ordering rules | |
6450 | * guarantee that MSI will arrive after the status block. | |
6451 | */ | |
7d12e780 | 6452 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 6453 | { |
09943a18 MC |
6454 | struct tg3_napi *tnapi = dev_id; |
6455 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 6456 | |
898a56f8 | 6457 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
6458 | if (tnapi->rx_rcb) |
6459 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 6460 | /* |
fac9b83e | 6461 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 6462 | * chip-internal interrupt pending events. |
fac9b83e | 6463 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
6464 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
6465 | * event coalescing. | |
6466 | */ | |
5b39de91 | 6467 | tw32_mailbox(tnapi->int_mbox, 0x00000001); |
61487480 | 6468 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 6469 | napi_schedule(&tnapi->napi); |
61487480 | 6470 | |
88b06bc2 MC |
6471 | return IRQ_RETVAL(1); |
6472 | } | |
6473 | ||
7d12e780 | 6474 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 6475 | { |
09943a18 MC |
6476 | struct tg3_napi *tnapi = dev_id; |
6477 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6478 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
6479 | unsigned int handled = 1; |
6480 | ||
1da177e4 LT |
6481 | /* In INTx mode, it is possible for the interrupt to arrive at |
6482 | * the CPU before the status block posted prior to the interrupt. | |
6483 | * Reading the PCI State register will confirm whether the | |
6484 | * interrupt is ours and will flush the status block. | |
6485 | */ | |
d18edcb2 | 6486 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
63c3a66f | 6487 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
6488 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
6489 | handled = 0; | |
f47c11ee | 6490 | goto out; |
fac9b83e | 6491 | } |
d18edcb2 MC |
6492 | } |
6493 | ||
6494 | /* | |
6495 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
6496 | * chip-internal interrupt pending events. | |
6497 | * Writing non-zero to intr-mbox-0 additional tells the | |
6498 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
6499 | * event coalescing. | |
c04cb347 MC |
6500 | * |
6501 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
6502 | * spurious interrupts. The flush impacts performance but | |
6503 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 6504 | */ |
c04cb347 | 6505 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
6506 | if (tg3_irq_sync(tp)) |
6507 | goto out; | |
6508 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 6509 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 6510 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 6511 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
6512 | } else { |
6513 | /* No work, shared interrupt perhaps? re-enable | |
6514 | * interrupts, and flush that PCI write | |
6515 | */ | |
6516 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
6517 | 0x00000000); | |
fac9b83e | 6518 | } |
f47c11ee | 6519 | out: |
fac9b83e DM |
6520 | return IRQ_RETVAL(handled); |
6521 | } | |
6522 | ||
7d12e780 | 6523 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 6524 | { |
09943a18 MC |
6525 | struct tg3_napi *tnapi = dev_id; |
6526 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6527 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
6528 | unsigned int handled = 1; |
6529 | ||
fac9b83e DM |
6530 | /* In INTx mode, it is possible for the interrupt to arrive at |
6531 | * the CPU before the status block posted prior to the interrupt. | |
6532 | * Reading the PCI State register will confirm whether the | |
6533 | * interrupt is ours and will flush the status block. | |
6534 | */ | |
898a56f8 | 6535 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
63c3a66f | 6536 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
6537 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
6538 | handled = 0; | |
f47c11ee | 6539 | goto out; |
1da177e4 | 6540 | } |
d18edcb2 MC |
6541 | } |
6542 | ||
6543 | /* | |
6544 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
6545 | * chip-internal interrupt pending events. | |
6546 | * writing non-zero to intr-mbox-0 additional tells the | |
6547 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
6548 | * event coalescing. | |
c04cb347 MC |
6549 | * |
6550 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
6551 | * spurious interrupts. The flush impacts performance but | |
6552 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 6553 | */ |
c04cb347 | 6554 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
6555 | |
6556 | /* | |
6557 | * In a shared interrupt configuration, sometimes other devices' | |
6558 | * interrupts will scream. We record the current status tag here | |
6559 | * so that the above check can report that the screaming interrupts | |
6560 | * are unhandled. Eventually they will be silenced. | |
6561 | */ | |
898a56f8 | 6562 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 6563 | |
d18edcb2 MC |
6564 | if (tg3_irq_sync(tp)) |
6565 | goto out; | |
624f8e50 | 6566 | |
72334482 | 6567 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 6568 | |
09943a18 | 6569 | napi_schedule(&tnapi->napi); |
624f8e50 | 6570 | |
f47c11ee | 6571 | out: |
1da177e4 LT |
6572 | return IRQ_RETVAL(handled); |
6573 | } | |
6574 | ||
7938109f | 6575 | /* ISR for interrupt test */ |
7d12e780 | 6576 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 6577 | { |
09943a18 MC |
6578 | struct tg3_napi *tnapi = dev_id; |
6579 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6580 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 6581 | |
f9804ddb MC |
6582 | if ((sblk->status & SD_STATUS_UPDATED) || |
6583 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 6584 | tg3_disable_ints(tp); |
7938109f MC |
6585 | return IRQ_RETVAL(1); |
6586 | } | |
6587 | return IRQ_RETVAL(0); | |
6588 | } | |
6589 | ||
1da177e4 LT |
6590 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6591 | static void tg3_poll_controller(struct net_device *dev) | |
6592 | { | |
4f125f42 | 6593 | int i; |
88b06bc2 MC |
6594 | struct tg3 *tp = netdev_priv(dev); |
6595 | ||
4f125f42 | 6596 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 6597 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
6598 | } |
6599 | #endif | |
6600 | ||
1da177e4 LT |
6601 | static void tg3_tx_timeout(struct net_device *dev) |
6602 | { | |
6603 | struct tg3 *tp = netdev_priv(dev); | |
6604 | ||
b0408751 | 6605 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 6606 | netdev_err(dev, "transmit timed out, resetting\n"); |
97bd8e49 | 6607 | tg3_dump_state(tp); |
b0408751 | 6608 | } |
1da177e4 | 6609 | |
db219973 | 6610 | tg3_reset_task_schedule(tp); |
1da177e4 LT |
6611 | } |
6612 | ||
c58ec932 MC |
6613 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
6614 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
6615 | { | |
6616 | u32 base = (u32) mapping & 0xffffffff; | |
6617 | ||
807540ba | 6618 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
6619 | } |
6620 | ||
72f2afb8 MC |
6621 | /* Test for DMA addresses > 40-bit */ |
6622 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
6623 | int len) | |
6624 | { | |
6625 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
63c3a66f | 6626 | if (tg3_flag(tp, 40BIT_DMA_BUG)) |
807540ba | 6627 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
6628 | return 0; |
6629 | #else | |
6630 | return 0; | |
6631 | #endif | |
6632 | } | |
6633 | ||
d1a3b737 | 6634 | static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd, |
92cd3a17 MC |
6635 | dma_addr_t mapping, u32 len, u32 flags, |
6636 | u32 mss, u32 vlan) | |
2ffcc981 | 6637 | { |
92cd3a17 MC |
6638 | txbd->addr_hi = ((u64) mapping >> 32); |
6639 | txbd->addr_lo = ((u64) mapping & 0xffffffff); | |
6640 | txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); | |
6641 | txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); | |
2ffcc981 | 6642 | } |
1da177e4 | 6643 | |
84b67b27 | 6644 | static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget, |
d1a3b737 MC |
6645 | dma_addr_t map, u32 len, u32 flags, |
6646 | u32 mss, u32 vlan) | |
6647 | { | |
6648 | struct tg3 *tp = tnapi->tp; | |
6649 | bool hwbug = false; | |
6650 | ||
6651 | if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) | |
3db1cd5c | 6652 | hwbug = true; |
d1a3b737 MC |
6653 | |
6654 | if (tg3_4g_overflow_test(map, len)) | |
3db1cd5c | 6655 | hwbug = true; |
d1a3b737 MC |
6656 | |
6657 | if (tg3_40bit_overflow_test(tp, map, len)) | |
3db1cd5c | 6658 | hwbug = true; |
d1a3b737 | 6659 | |
a4cb428d | 6660 | if (tp->dma_limit) { |
b9e45482 | 6661 | u32 prvidx = *entry; |
e31aa987 | 6662 | u32 tmp_flag = flags & ~TXD_FLAG_END; |
a4cb428d MC |
6663 | while (len > tp->dma_limit && *budget) { |
6664 | u32 frag_len = tp->dma_limit; | |
6665 | len -= tp->dma_limit; | |
e31aa987 | 6666 | |
b9e45482 MC |
6667 | /* Avoid the 8byte DMA problem */ |
6668 | if (len <= 8) { | |
a4cb428d MC |
6669 | len += tp->dma_limit / 2; |
6670 | frag_len = tp->dma_limit / 2; | |
e31aa987 MC |
6671 | } |
6672 | ||
b9e45482 MC |
6673 | tnapi->tx_buffers[*entry].fragmented = true; |
6674 | ||
6675 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
6676 | frag_len, tmp_flag, mss, vlan); | |
6677 | *budget -= 1; | |
6678 | prvidx = *entry; | |
6679 | *entry = NEXT_TX(*entry); | |
6680 | ||
e31aa987 MC |
6681 | map += frag_len; |
6682 | } | |
6683 | ||
6684 | if (len) { | |
6685 | if (*budget) { | |
6686 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
6687 | len, flags, mss, vlan); | |
b9e45482 | 6688 | *budget -= 1; |
e31aa987 MC |
6689 | *entry = NEXT_TX(*entry); |
6690 | } else { | |
3db1cd5c | 6691 | hwbug = true; |
b9e45482 | 6692 | tnapi->tx_buffers[prvidx].fragmented = false; |
e31aa987 MC |
6693 | } |
6694 | } | |
6695 | } else { | |
84b67b27 MC |
6696 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, |
6697 | len, flags, mss, vlan); | |
e31aa987 MC |
6698 | *entry = NEXT_TX(*entry); |
6699 | } | |
d1a3b737 MC |
6700 | |
6701 | return hwbug; | |
6702 | } | |
6703 | ||
0d681b27 | 6704 | static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last) |
432aa7ed MC |
6705 | { |
6706 | int i; | |
0d681b27 | 6707 | struct sk_buff *skb; |
df8944cf | 6708 | struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; |
432aa7ed | 6709 | |
0d681b27 MC |
6710 | skb = txb->skb; |
6711 | txb->skb = NULL; | |
6712 | ||
432aa7ed MC |
6713 | pci_unmap_single(tnapi->tp->pdev, |
6714 | dma_unmap_addr(txb, mapping), | |
6715 | skb_headlen(skb), | |
6716 | PCI_DMA_TODEVICE); | |
e01ee14d MC |
6717 | |
6718 | while (txb->fragmented) { | |
6719 | txb->fragmented = false; | |
6720 | entry = NEXT_TX(entry); | |
6721 | txb = &tnapi->tx_buffers[entry]; | |
6722 | } | |
6723 | ||
ba1142e4 | 6724 | for (i = 0; i <= last; i++) { |
9e903e08 | 6725 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
432aa7ed MC |
6726 | |
6727 | entry = NEXT_TX(entry); | |
6728 | txb = &tnapi->tx_buffers[entry]; | |
6729 | ||
6730 | pci_unmap_page(tnapi->tp->pdev, | |
6731 | dma_unmap_addr(txb, mapping), | |
9e903e08 | 6732 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
e01ee14d MC |
6733 | |
6734 | while (txb->fragmented) { | |
6735 | txb->fragmented = false; | |
6736 | entry = NEXT_TX(entry); | |
6737 | txb = &tnapi->tx_buffers[entry]; | |
6738 | } | |
432aa7ed MC |
6739 | } |
6740 | } | |
6741 | ||
72f2afb8 | 6742 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 | 6743 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
f7ff1987 | 6744 | struct sk_buff **pskb, |
84b67b27 | 6745 | u32 *entry, u32 *budget, |
92cd3a17 | 6746 | u32 base_flags, u32 mss, u32 vlan) |
1da177e4 | 6747 | { |
24f4efd4 | 6748 | struct tg3 *tp = tnapi->tp; |
f7ff1987 | 6749 | struct sk_buff *new_skb, *skb = *pskb; |
c58ec932 | 6750 | dma_addr_t new_addr = 0; |
432aa7ed | 6751 | int ret = 0; |
1da177e4 | 6752 | |
41588ba1 MC |
6753 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
6754 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
6755 | else { | |
6756 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
6757 | ||
6758 | new_skb = skb_copy_expand(skb, | |
6759 | skb_headroom(skb) + more_headroom, | |
6760 | skb_tailroom(skb), GFP_ATOMIC); | |
6761 | } | |
6762 | ||
1da177e4 | 6763 | if (!new_skb) { |
c58ec932 MC |
6764 | ret = -1; |
6765 | } else { | |
6766 | /* New SKB is guaranteed to be linear. */ | |
f4188d8a AD |
6767 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
6768 | PCI_DMA_TODEVICE); | |
6769 | /* Make sure the mapping succeeded */ | |
6770 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
f4188d8a | 6771 | dev_kfree_skb(new_skb); |
c58ec932 | 6772 | ret = -1; |
c58ec932 | 6773 | } else { |
b9e45482 MC |
6774 | u32 save_entry = *entry; |
6775 | ||
92cd3a17 MC |
6776 | base_flags |= TXD_FLAG_END; |
6777 | ||
84b67b27 MC |
6778 | tnapi->tx_buffers[*entry].skb = new_skb; |
6779 | dma_unmap_addr_set(&tnapi->tx_buffers[*entry], | |
432aa7ed MC |
6780 | mapping, new_addr); |
6781 | ||
84b67b27 | 6782 | if (tg3_tx_frag_set(tnapi, entry, budget, new_addr, |
d1a3b737 MC |
6783 | new_skb->len, base_flags, |
6784 | mss, vlan)) { | |
ba1142e4 | 6785 | tg3_tx_skb_unmap(tnapi, save_entry, -1); |
d1a3b737 MC |
6786 | dev_kfree_skb(new_skb); |
6787 | ret = -1; | |
6788 | } | |
f4188d8a | 6789 | } |
1da177e4 LT |
6790 | } |
6791 | ||
6792 | dev_kfree_skb(skb); | |
f7ff1987 | 6793 | *pskb = new_skb; |
c58ec932 | 6794 | return ret; |
1da177e4 LT |
6795 | } |
6796 | ||
2ffcc981 | 6797 | static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *); |
52c0fd83 MC |
6798 | |
6799 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
6800 | * TSO header is greater than 80 bytes. | |
6801 | */ | |
6802 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
6803 | { | |
6804 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 6805 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
6806 | |
6807 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 6808 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 6809 | netif_stop_queue(tp->dev); |
f65aac16 MC |
6810 | |
6811 | /* netif_tx_stop_queue() must be done before checking | |
6812 | * checking tx index in tg3_tx_avail() below, because in | |
6813 | * tg3_tx(), we update tx index before checking for | |
6814 | * netif_tx_queue_stopped(). | |
6815 | */ | |
6816 | smp_mb(); | |
f3f3f27e | 6817 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
6818 | return NETDEV_TX_BUSY; |
6819 | ||
6820 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
6821 | } |
6822 | ||
6823 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 6824 | if (IS_ERR(segs)) |
52c0fd83 MC |
6825 | goto tg3_tso_bug_end; |
6826 | ||
6827 | do { | |
6828 | nskb = segs; | |
6829 | segs = segs->next; | |
6830 | nskb->next = NULL; | |
2ffcc981 | 6831 | tg3_start_xmit(nskb, tp->dev); |
52c0fd83 MC |
6832 | } while (segs); |
6833 | ||
6834 | tg3_tso_bug_end: | |
6835 | dev_kfree_skb(skb); | |
6836 | ||
6837 | return NETDEV_TX_OK; | |
6838 | } | |
52c0fd83 | 6839 | |
5a6f3074 | 6840 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
63c3a66f | 6841 | * support TG3_FLAG_HW_TSO_1 or firmware TSO only. |
5a6f3074 | 6842 | */ |
2ffcc981 | 6843 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
6844 | { |
6845 | struct tg3 *tp = netdev_priv(dev); | |
92cd3a17 | 6846 | u32 len, entry, base_flags, mss, vlan = 0; |
84b67b27 | 6847 | u32 budget; |
432aa7ed | 6848 | int i = -1, would_hit_hwbug; |
90079ce8 | 6849 | dma_addr_t mapping; |
24f4efd4 MC |
6850 | struct tg3_napi *tnapi; |
6851 | struct netdev_queue *txq; | |
432aa7ed | 6852 | unsigned int last; |
f4188d8a | 6853 | |
24f4efd4 MC |
6854 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
6855 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
63c3a66f | 6856 | if (tg3_flag(tp, ENABLE_TSS)) |
24f4efd4 | 6857 | tnapi++; |
1da177e4 | 6858 | |
84b67b27 MC |
6859 | budget = tg3_tx_avail(tnapi); |
6860 | ||
00b70504 | 6861 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 6862 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
6863 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
6864 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 6865 | */ |
84b67b27 | 6866 | if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
6867 | if (!netif_tx_queue_stopped(txq)) { |
6868 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
6869 | |
6870 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
6871 | netdev_err(dev, |
6872 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 6873 | } |
1da177e4 LT |
6874 | return NETDEV_TX_BUSY; |
6875 | } | |
6876 | ||
f3f3f27e | 6877 | entry = tnapi->tx_prod; |
1da177e4 | 6878 | base_flags = 0; |
84fa7933 | 6879 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 6880 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 6881 | |
be98da6a MC |
6882 | mss = skb_shinfo(skb)->gso_size; |
6883 | if (mss) { | |
eddc9ec5 | 6884 | struct iphdr *iph; |
34195c3d | 6885 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
6886 | |
6887 | if (skb_header_cloned(skb) && | |
48855432 ED |
6888 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) |
6889 | goto drop; | |
1da177e4 | 6890 | |
34195c3d | 6891 | iph = ip_hdr(skb); |
ab6a5bb6 | 6892 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 6893 | |
a5a11955 | 6894 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN; |
34195c3d | 6895 | |
a5a11955 | 6896 | if (!skb_is_gso_v6(skb)) { |
34195c3d MC |
6897 | iph->check = 0; |
6898 | iph->tot_len = htons(mss + hdr_len); | |
6899 | } | |
6900 | ||
52c0fd83 | 6901 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
63c3a66f | 6902 | tg3_flag(tp, TSO_BUG)) |
de6f31eb | 6903 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 6904 | |
1da177e4 LT |
6905 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
6906 | TXD_FLAG_CPU_POST_DMA); | |
6907 | ||
63c3a66f JP |
6908 | if (tg3_flag(tp, HW_TSO_1) || |
6909 | tg3_flag(tp, HW_TSO_2) || | |
6910 | tg3_flag(tp, HW_TSO_3)) { | |
aa8223c7 | 6911 | tcp_hdr(skb)->check = 0; |
1da177e4 | 6912 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
6913 | } else |
6914 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6915 | iph->daddr, 0, | |
6916 | IPPROTO_TCP, | |
6917 | 0); | |
1da177e4 | 6918 | |
63c3a66f | 6919 | if (tg3_flag(tp, HW_TSO_3)) { |
615774fe MC |
6920 | mss |= (hdr_len & 0xc) << 12; |
6921 | if (hdr_len & 0x10) | |
6922 | base_flags |= 0x00000010; | |
6923 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 6924 | } else if (tg3_flag(tp, HW_TSO_2)) |
92c6b8d1 | 6925 | mss |= hdr_len << 9; |
63c3a66f | 6926 | else if (tg3_flag(tp, HW_TSO_1) || |
92c6b8d1 | 6927 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
eddc9ec5 | 6928 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6929 | int tsflags; |
6930 | ||
eddc9ec5 | 6931 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6932 | mss |= (tsflags << 11); |
6933 | } | |
6934 | } else { | |
eddc9ec5 | 6935 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6936 | int tsflags; |
6937 | ||
eddc9ec5 | 6938 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6939 | base_flags |= tsflags << 12; |
6940 | } | |
6941 | } | |
6942 | } | |
bf933c80 | 6943 | |
93a700a9 MC |
6944 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && |
6945 | !mss && skb->len > VLAN_ETH_FRAME_LEN) | |
6946 | base_flags |= TXD_FLAG_JMB_PKT; | |
6947 | ||
92cd3a17 MC |
6948 | if (vlan_tx_tag_present(skb)) { |
6949 | base_flags |= TXD_FLAG_VLAN; | |
6950 | vlan = vlan_tx_tag_get(skb); | |
6951 | } | |
1da177e4 | 6952 | |
f4188d8a AD |
6953 | len = skb_headlen(skb); |
6954 | ||
6955 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
48855432 ED |
6956 | if (pci_dma_mapping_error(tp->pdev, mapping)) |
6957 | goto drop; | |
6958 | ||
90079ce8 | 6959 | |
f3f3f27e | 6960 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 6961 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
6962 | |
6963 | would_hit_hwbug = 0; | |
6964 | ||
63c3a66f | 6965 | if (tg3_flag(tp, 5701_DMA_BUG)) |
c58ec932 | 6966 | would_hit_hwbug = 1; |
1da177e4 | 6967 | |
84b67b27 | 6968 | if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags | |
d1a3b737 | 6969 | ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), |
ba1142e4 | 6970 | mss, vlan)) { |
d1a3b737 | 6971 | would_hit_hwbug = 1; |
ba1142e4 | 6972 | } else if (skb_shinfo(skb)->nr_frags > 0) { |
92cd3a17 MC |
6973 | u32 tmp_mss = mss; |
6974 | ||
6975 | if (!tg3_flag(tp, HW_TSO_1) && | |
6976 | !tg3_flag(tp, HW_TSO_2) && | |
6977 | !tg3_flag(tp, HW_TSO_3)) | |
6978 | tmp_mss = 0; | |
6979 | ||
c5665a53 MC |
6980 | /* Now loop through additional data |
6981 | * fragments, and queue them. | |
6982 | */ | |
1da177e4 LT |
6983 | last = skb_shinfo(skb)->nr_frags - 1; |
6984 | for (i = 0; i <= last; i++) { | |
6985 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6986 | ||
9e903e08 | 6987 | len = skb_frag_size(frag); |
dc234d0b | 6988 | mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, |
5d6bcdfe | 6989 | len, DMA_TO_DEVICE); |
1da177e4 | 6990 | |
f3f3f27e | 6991 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 6992 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a | 6993 | mapping); |
5d6bcdfe | 6994 | if (dma_mapping_error(&tp->pdev->dev, mapping)) |
f4188d8a | 6995 | goto dma_error; |
1da177e4 | 6996 | |
b9e45482 MC |
6997 | if (!budget || |
6998 | tg3_tx_frag_set(tnapi, &entry, &budget, mapping, | |
84b67b27 MC |
6999 | len, base_flags | |
7000 | ((i == last) ? TXD_FLAG_END : 0), | |
b9e45482 | 7001 | tmp_mss, vlan)) { |
72f2afb8 | 7002 | would_hit_hwbug = 1; |
b9e45482 MC |
7003 | break; |
7004 | } | |
1da177e4 LT |
7005 | } |
7006 | } | |
7007 | ||
7008 | if (would_hit_hwbug) { | |
0d681b27 | 7009 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); |
1da177e4 LT |
7010 | |
7011 | /* If the workaround fails due to memory/mapping | |
7012 | * failure, silently drop this packet. | |
7013 | */ | |
84b67b27 MC |
7014 | entry = tnapi->tx_prod; |
7015 | budget = tg3_tx_avail(tnapi); | |
f7ff1987 | 7016 | if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget, |
84b67b27 | 7017 | base_flags, mss, vlan)) |
48855432 | 7018 | goto drop_nofree; |
1da177e4 LT |
7019 | } |
7020 | ||
d515b450 | 7021 | skb_tx_timestamp(skb); |
5cb917bc | 7022 | netdev_tx_sent_queue(txq, skb->len); |
d515b450 | 7023 | |
6541b806 MC |
7024 | /* Sync BD data before updating mailbox */ |
7025 | wmb(); | |
7026 | ||
1da177e4 | 7027 | /* Packets are ready, update Tx producer idx local and on card. */ |
24f4efd4 | 7028 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 7029 | |
f3f3f27e MC |
7030 | tnapi->tx_prod = entry; |
7031 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 7032 | netif_tx_stop_queue(txq); |
f65aac16 MC |
7033 | |
7034 | /* netif_tx_stop_queue() must be done before checking | |
7035 | * checking tx index in tg3_tx_avail() below, because in | |
7036 | * tg3_tx(), we update tx index before checking for | |
7037 | * netif_tx_queue_stopped(). | |
7038 | */ | |
7039 | smp_mb(); | |
f3f3f27e | 7040 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 7041 | netif_tx_wake_queue(txq); |
51b91468 | 7042 | } |
1da177e4 | 7043 | |
cdd0db05 | 7044 | mmiowb(); |
1da177e4 | 7045 | return NETDEV_TX_OK; |
f4188d8a AD |
7046 | |
7047 | dma_error: | |
ba1142e4 | 7048 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); |
432aa7ed | 7049 | tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; |
48855432 ED |
7050 | drop: |
7051 | dev_kfree_skb(skb); | |
7052 | drop_nofree: | |
7053 | tp->tx_dropped++; | |
f4188d8a | 7054 | return NETDEV_TX_OK; |
1da177e4 LT |
7055 | } |
7056 | ||
6e01b20b MC |
7057 | static void tg3_mac_loopback(struct tg3 *tp, bool enable) |
7058 | { | |
7059 | if (enable) { | |
7060 | tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | | |
7061 | MAC_MODE_PORT_MODE_MASK); | |
7062 | ||
7063 | tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
7064 | ||
7065 | if (!tg3_flag(tp, 5705_PLUS)) | |
7066 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
7067 | ||
7068 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
7069 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
7070 | else | |
7071 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
7072 | } else { | |
7073 | tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; | |
7074 | ||
7075 | if (tg3_flag(tp, 5705_PLUS) || | |
7076 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || | |
7077 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
7078 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
7079 | } | |
7080 | ||
7081 | tw32(MAC_MODE, tp->mac_mode); | |
7082 | udelay(40); | |
7083 | } | |
7084 | ||
941ec90f | 7085 | static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) |
5e5a7f37 | 7086 | { |
941ec90f | 7087 | u32 val, bmcr, mac_mode, ptest = 0; |
5e5a7f37 MC |
7088 | |
7089 | tg3_phy_toggle_apd(tp, false); | |
7090 | tg3_phy_toggle_automdix(tp, 0); | |
7091 | ||
941ec90f MC |
7092 | if (extlpbk && tg3_phy_set_extloopbk(tp)) |
7093 | return -EIO; | |
7094 | ||
7095 | bmcr = BMCR_FULLDPLX; | |
5e5a7f37 MC |
7096 | switch (speed) { |
7097 | case SPEED_10: | |
7098 | break; | |
7099 | case SPEED_100: | |
7100 | bmcr |= BMCR_SPEED100; | |
7101 | break; | |
7102 | case SPEED_1000: | |
7103 | default: | |
7104 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
7105 | speed = SPEED_100; | |
7106 | bmcr |= BMCR_SPEED100; | |
7107 | } else { | |
7108 | speed = SPEED_1000; | |
7109 | bmcr |= BMCR_SPEED1000; | |
7110 | } | |
7111 | } | |
7112 | ||
941ec90f MC |
7113 | if (extlpbk) { |
7114 | if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
7115 | tg3_readphy(tp, MII_CTRL1000, &val); | |
7116 | val |= CTL1000_AS_MASTER | | |
7117 | CTL1000_ENABLE_MASTER; | |
7118 | tg3_writephy(tp, MII_CTRL1000, val); | |
7119 | } else { | |
7120 | ptest = MII_TG3_FET_PTEST_TRIM_SEL | | |
7121 | MII_TG3_FET_PTEST_TRIM_2; | |
7122 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); | |
7123 | } | |
7124 | } else | |
7125 | bmcr |= BMCR_LOOPBACK; | |
7126 | ||
5e5a7f37 MC |
7127 | tg3_writephy(tp, MII_BMCR, bmcr); |
7128 | ||
7129 | /* The write needs to be flushed for the FETs */ | |
7130 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
7131 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
7132 | ||
7133 | udelay(40); | |
7134 | ||
7135 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && | |
7136 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
941ec90f | 7137 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | |
5e5a7f37 MC |
7138 | MII_TG3_FET_PTEST_FRC_TX_LINK | |
7139 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
7140 | ||
7141 | /* The write needs to be flushed for the AC131 */ | |
7142 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
7143 | } | |
7144 | ||
7145 | /* Reset to prevent losing 1st rx packet intermittently */ | |
7146 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && | |
7147 | tg3_flag(tp, 5780_CLASS)) { | |
7148 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
7149 | udelay(10); | |
7150 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7151 | } | |
7152 | ||
7153 | mac_mode = tp->mac_mode & | |
7154 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
7155 | if (speed == SPEED_1000) | |
7156 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
7157 | else | |
7158 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
7159 | ||
7160 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
7161 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; | |
7162 | ||
7163 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
7164 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
7165 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) | |
7166 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
7167 | ||
7168 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
7169 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
7170 | } | |
7171 | ||
7172 | tw32(MAC_MODE, mac_mode); | |
7173 | udelay(40); | |
941ec90f MC |
7174 | |
7175 | return 0; | |
5e5a7f37 MC |
7176 | } |
7177 | ||
c8f44aff | 7178 | static void tg3_set_loopback(struct net_device *dev, netdev_features_t features) |
06c03c02 MB |
7179 | { |
7180 | struct tg3 *tp = netdev_priv(dev); | |
7181 | ||
7182 | if (features & NETIF_F_LOOPBACK) { | |
7183 | if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) | |
7184 | return; | |
7185 | ||
06c03c02 | 7186 | spin_lock_bh(&tp->lock); |
6e01b20b | 7187 | tg3_mac_loopback(tp, true); |
06c03c02 MB |
7188 | netif_carrier_on(tp->dev); |
7189 | spin_unlock_bh(&tp->lock); | |
7190 | netdev_info(dev, "Internal MAC loopback mode enabled.\n"); | |
7191 | } else { | |
7192 | if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
7193 | return; | |
7194 | ||
06c03c02 | 7195 | spin_lock_bh(&tp->lock); |
6e01b20b | 7196 | tg3_mac_loopback(tp, false); |
06c03c02 MB |
7197 | /* Force link status check */ |
7198 | tg3_setup_phy(tp, 1); | |
7199 | spin_unlock_bh(&tp->lock); | |
7200 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | |
7201 | } | |
7202 | } | |
7203 | ||
c8f44aff MM |
7204 | static netdev_features_t tg3_fix_features(struct net_device *dev, |
7205 | netdev_features_t features) | |
dc668910 MM |
7206 | { |
7207 | struct tg3 *tp = netdev_priv(dev); | |
7208 | ||
63c3a66f | 7209 | if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) |
dc668910 MM |
7210 | features &= ~NETIF_F_ALL_TSO; |
7211 | ||
7212 | return features; | |
7213 | } | |
7214 | ||
c8f44aff | 7215 | static int tg3_set_features(struct net_device *dev, netdev_features_t features) |
06c03c02 | 7216 | { |
c8f44aff | 7217 | netdev_features_t changed = dev->features ^ features; |
06c03c02 MB |
7218 | |
7219 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) | |
7220 | tg3_set_loopback(dev, features); | |
7221 | ||
7222 | return 0; | |
7223 | } | |
7224 | ||
21f581a5 MC |
7225 | static void tg3_rx_prodring_free(struct tg3 *tp, |
7226 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7227 | { |
1da177e4 LT |
7228 | int i; |
7229 | ||
8fea32b9 | 7230 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 7231 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 7232 | i = (i + 1) & tp->rx_std_ring_mask) |
9205fd9c | 7233 | tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], |
b196c7e4 MC |
7234 | tp->rx_pkt_map_sz); |
7235 | ||
63c3a66f | 7236 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
b196c7e4 MC |
7237 | for (i = tpr->rx_jmb_cons_idx; |
7238 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 7239 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
9205fd9c | 7240 | tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], |
b196c7e4 MC |
7241 | TG3_RX_JMB_MAP_SZ); |
7242 | } | |
7243 | } | |
7244 | ||
2b2cdb65 | 7245 | return; |
b196c7e4 | 7246 | } |
1da177e4 | 7247 | |
2c49a44d | 7248 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
9205fd9c | 7249 | tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], |
2b2cdb65 | 7250 | tp->rx_pkt_map_sz); |
1da177e4 | 7251 | |
63c3a66f | 7252 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 7253 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
9205fd9c | 7254 | tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], |
2b2cdb65 | 7255 | TG3_RX_JMB_MAP_SZ); |
1da177e4 LT |
7256 | } |
7257 | } | |
7258 | ||
c6cdf436 | 7259 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
7260 | * |
7261 | * The chip has been shut down and the driver detached from | |
7262 | * the networking, so no interrupts or new tx packets will | |
7263 | * end up in the driver. tp->{tx,}lock are held and thus | |
7264 | * we may not sleep. | |
7265 | */ | |
21f581a5 MC |
7266 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
7267 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7268 | { |
287be12e | 7269 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 7270 | |
b196c7e4 MC |
7271 | tpr->rx_std_cons_idx = 0; |
7272 | tpr->rx_std_prod_idx = 0; | |
7273 | tpr->rx_jmb_cons_idx = 0; | |
7274 | tpr->rx_jmb_prod_idx = 0; | |
7275 | ||
8fea32b9 | 7276 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
7277 | memset(&tpr->rx_std_buffers[0], 0, |
7278 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 7279 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 7280 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 7281 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
7282 | goto done; |
7283 | } | |
7284 | ||
1da177e4 | 7285 | /* Zero out all descriptors. */ |
2c49a44d | 7286 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 7287 | |
287be12e | 7288 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
63c3a66f | 7289 | if (tg3_flag(tp, 5780_CLASS) && |
287be12e MC |
7290 | tp->dev->mtu > ETH_DATA_LEN) |
7291 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
7292 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 7293 | |
1da177e4 LT |
7294 | /* Initialize invariants of the rings, we only set this |
7295 | * stuff once. This works because the card does not | |
7296 | * write into the rx buffer posting rings. | |
7297 | */ | |
2c49a44d | 7298 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
7299 | struct tg3_rx_buffer_desc *rxd; |
7300 | ||
21f581a5 | 7301 | rxd = &tpr->rx_std[i]; |
287be12e | 7302 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
7303 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
7304 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
7305 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
7306 | } | |
7307 | ||
1da177e4 LT |
7308 | /* Now allocate fresh SKBs for each rx ring. */ |
7309 | for (i = 0; i < tp->rx_pending; i++) { | |
8d4057a9 ED |
7310 | unsigned int frag_size; |
7311 | ||
7312 | if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i, | |
7313 | &frag_size) < 0) { | |
5129c3a3 MC |
7314 | netdev_warn(tp->dev, |
7315 | "Using a smaller RX standard ring. Only " | |
7316 | "%d out of %d buffers were allocated " | |
7317 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 7318 | if (i == 0) |
cf7a7298 | 7319 | goto initfail; |
32d8c572 | 7320 | tp->rx_pending = i; |
1da177e4 | 7321 | break; |
32d8c572 | 7322 | } |
1da177e4 LT |
7323 | } |
7324 | ||
63c3a66f | 7325 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
cf7a7298 MC |
7326 | goto done; |
7327 | ||
2c49a44d | 7328 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 7329 | |
63c3a66f | 7330 | if (!tg3_flag(tp, JUMBO_RING_ENABLE)) |
0d86df80 | 7331 | goto done; |
cf7a7298 | 7332 | |
2c49a44d | 7333 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
7334 | struct tg3_rx_buffer_desc *rxd; |
7335 | ||
7336 | rxd = &tpr->rx_jmb[i].std; | |
7337 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
7338 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
7339 | RXD_FLAG_JUMBO; | |
7340 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
7341 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
7342 | } | |
7343 | ||
7344 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
8d4057a9 ED |
7345 | unsigned int frag_size; |
7346 | ||
7347 | if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i, | |
7348 | &frag_size) < 0) { | |
5129c3a3 MC |
7349 | netdev_warn(tp->dev, |
7350 | "Using a smaller RX jumbo ring. Only %d " | |
7351 | "out of %d buffers were allocated " | |
7352 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
7353 | if (i == 0) |
7354 | goto initfail; | |
7355 | tp->rx_jumbo_pending = i; | |
7356 | break; | |
1da177e4 LT |
7357 | } |
7358 | } | |
cf7a7298 MC |
7359 | |
7360 | done: | |
32d8c572 | 7361 | return 0; |
cf7a7298 MC |
7362 | |
7363 | initfail: | |
21f581a5 | 7364 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 7365 | return -ENOMEM; |
1da177e4 LT |
7366 | } |
7367 | ||
21f581a5 MC |
7368 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
7369 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7370 | { |
21f581a5 MC |
7371 | kfree(tpr->rx_std_buffers); |
7372 | tpr->rx_std_buffers = NULL; | |
7373 | kfree(tpr->rx_jmb_buffers); | |
7374 | tpr->rx_jmb_buffers = NULL; | |
7375 | if (tpr->rx_std) { | |
4bae65c8 MC |
7376 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
7377 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 7378 | tpr->rx_std = NULL; |
1da177e4 | 7379 | } |
21f581a5 | 7380 | if (tpr->rx_jmb) { |
4bae65c8 MC |
7381 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
7382 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 7383 | tpr->rx_jmb = NULL; |
1da177e4 | 7384 | } |
cf7a7298 MC |
7385 | } |
7386 | ||
21f581a5 MC |
7387 | static int tg3_rx_prodring_init(struct tg3 *tp, |
7388 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 7389 | { |
2c49a44d MC |
7390 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
7391 | GFP_KERNEL); | |
21f581a5 | 7392 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
7393 | return -ENOMEM; |
7394 | ||
4bae65c8 MC |
7395 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
7396 | TG3_RX_STD_RING_BYTES(tp), | |
7397 | &tpr->rx_std_mapping, | |
7398 | GFP_KERNEL); | |
21f581a5 | 7399 | if (!tpr->rx_std) |
cf7a7298 MC |
7400 | goto err_out; |
7401 | ||
63c3a66f | 7402 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 7403 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
7404 | GFP_KERNEL); |
7405 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
7406 | goto err_out; |
7407 | ||
4bae65c8 MC |
7408 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
7409 | TG3_RX_JMB_RING_BYTES(tp), | |
7410 | &tpr->rx_jmb_mapping, | |
7411 | GFP_KERNEL); | |
21f581a5 | 7412 | if (!tpr->rx_jmb) |
cf7a7298 MC |
7413 | goto err_out; |
7414 | } | |
7415 | ||
7416 | return 0; | |
7417 | ||
7418 | err_out: | |
21f581a5 | 7419 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
7420 | return -ENOMEM; |
7421 | } | |
7422 | ||
7423 | /* Free up pending packets in all rx/tx rings. | |
7424 | * | |
7425 | * The chip has been shut down and the driver detached from | |
7426 | * the networking, so no interrupts or new tx packets will | |
7427 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
7428 | * in an interrupt context and thus may sleep. | |
7429 | */ | |
7430 | static void tg3_free_rings(struct tg3 *tp) | |
7431 | { | |
f77a6a8e | 7432 | int i, j; |
cf7a7298 | 7433 | |
f77a6a8e MC |
7434 | for (j = 0; j < tp->irq_cnt; j++) { |
7435 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 7436 | |
8fea32b9 | 7437 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 7438 | |
0c1d0e2b MC |
7439 | if (!tnapi->tx_buffers) |
7440 | continue; | |
7441 | ||
0d681b27 MC |
7442 | for (i = 0; i < TG3_TX_RING_SIZE; i++) { |
7443 | struct sk_buff *skb = tnapi->tx_buffers[i].skb; | |
cf7a7298 | 7444 | |
0d681b27 | 7445 | if (!skb) |
f77a6a8e | 7446 | continue; |
cf7a7298 | 7447 | |
ba1142e4 MC |
7448 | tg3_tx_skb_unmap(tnapi, i, |
7449 | skb_shinfo(skb)->nr_frags - 1); | |
f77a6a8e MC |
7450 | |
7451 | dev_kfree_skb_any(skb); | |
7452 | } | |
5cb917bc | 7453 | netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); |
2b2cdb65 | 7454 | } |
cf7a7298 MC |
7455 | } |
7456 | ||
7457 | /* Initialize tx/rx rings for packet processing. | |
7458 | * | |
7459 | * The chip has been shut down and the driver detached from | |
7460 | * the networking, so no interrupts or new tx packets will | |
7461 | * end up in the driver. tp->{tx,}lock are held and thus | |
7462 | * we may not sleep. | |
7463 | */ | |
7464 | static int tg3_init_rings(struct tg3 *tp) | |
7465 | { | |
f77a6a8e | 7466 | int i; |
72334482 | 7467 | |
cf7a7298 MC |
7468 | /* Free up all the SKBs. */ |
7469 | tg3_free_rings(tp); | |
7470 | ||
f77a6a8e MC |
7471 | for (i = 0; i < tp->irq_cnt; i++) { |
7472 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7473 | ||
7474 | tnapi->last_tag = 0; | |
7475 | tnapi->last_irq_tag = 0; | |
7476 | tnapi->hw_status->status = 0; | |
7477 | tnapi->hw_status->status_tag = 0; | |
7478 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 7479 | |
f77a6a8e MC |
7480 | tnapi->tx_prod = 0; |
7481 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
7482 | if (tnapi->tx_ring) |
7483 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
7484 | |
7485 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
7486 | if (tnapi->rx_rcb) |
7487 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 7488 | |
8fea32b9 | 7489 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 7490 | tg3_free_rings(tp); |
2b2cdb65 | 7491 | return -ENOMEM; |
e4af1af9 | 7492 | } |
f77a6a8e | 7493 | } |
72334482 | 7494 | |
2b2cdb65 | 7495 | return 0; |
cf7a7298 MC |
7496 | } |
7497 | ||
7498 | /* | |
7499 | * Must not be invoked with interrupt sources disabled and | |
7500 | * the hardware shutdown down. | |
7501 | */ | |
7502 | static void tg3_free_consistent(struct tg3 *tp) | |
7503 | { | |
f77a6a8e | 7504 | int i; |
898a56f8 | 7505 | |
f77a6a8e MC |
7506 | for (i = 0; i < tp->irq_cnt; i++) { |
7507 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7508 | ||
7509 | if (tnapi->tx_ring) { | |
4bae65c8 | 7510 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
7511 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
7512 | tnapi->tx_ring = NULL; | |
7513 | } | |
7514 | ||
7515 | kfree(tnapi->tx_buffers); | |
7516 | tnapi->tx_buffers = NULL; | |
7517 | ||
7518 | if (tnapi->rx_rcb) { | |
4bae65c8 MC |
7519 | dma_free_coherent(&tp->pdev->dev, |
7520 | TG3_RX_RCB_RING_BYTES(tp), | |
7521 | tnapi->rx_rcb, | |
7522 | tnapi->rx_rcb_mapping); | |
f77a6a8e MC |
7523 | tnapi->rx_rcb = NULL; |
7524 | } | |
7525 | ||
8fea32b9 MC |
7526 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
7527 | ||
f77a6a8e | 7528 | if (tnapi->hw_status) { |
4bae65c8 MC |
7529 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
7530 | tnapi->hw_status, | |
7531 | tnapi->status_mapping); | |
f77a6a8e MC |
7532 | tnapi->hw_status = NULL; |
7533 | } | |
1da177e4 | 7534 | } |
f77a6a8e | 7535 | |
1da177e4 | 7536 | if (tp->hw_stats) { |
4bae65c8 MC |
7537 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
7538 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
7539 | tp->hw_stats = NULL; |
7540 | } | |
7541 | } | |
7542 | ||
7543 | /* | |
7544 | * Must not be invoked with interrupt sources disabled and | |
7545 | * the hardware shutdown down. Can sleep. | |
7546 | */ | |
7547 | static int tg3_alloc_consistent(struct tg3 *tp) | |
7548 | { | |
f77a6a8e | 7549 | int i; |
898a56f8 | 7550 | |
4bae65c8 MC |
7551 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
7552 | sizeof(struct tg3_hw_stats), | |
7553 | &tp->stats_mapping, | |
7554 | GFP_KERNEL); | |
f77a6a8e | 7555 | if (!tp->hw_stats) |
1da177e4 LT |
7556 | goto err_out; |
7557 | ||
f77a6a8e | 7558 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 7559 | |
f77a6a8e MC |
7560 | for (i = 0; i < tp->irq_cnt; i++) { |
7561 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 7562 | struct tg3_hw_status *sblk; |
1da177e4 | 7563 | |
4bae65c8 MC |
7564 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
7565 | TG3_HW_STATUS_SIZE, | |
7566 | &tnapi->status_mapping, | |
7567 | GFP_KERNEL); | |
f77a6a8e MC |
7568 | if (!tnapi->hw_status) |
7569 | goto err_out; | |
898a56f8 | 7570 | |
f77a6a8e | 7571 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
7572 | sblk = tnapi->hw_status; |
7573 | ||
8fea32b9 MC |
7574 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
7575 | goto err_out; | |
7576 | ||
19cfaecc MC |
7577 | /* If multivector TSS is enabled, vector 0 does not handle |
7578 | * tx interrupts. Don't allocate any resources for it. | |
7579 | */ | |
63c3a66f JP |
7580 | if ((!i && !tg3_flag(tp, ENABLE_TSS)) || |
7581 | (i && tg3_flag(tp, ENABLE_TSS))) { | |
df8944cf MC |
7582 | tnapi->tx_buffers = kzalloc( |
7583 | sizeof(struct tg3_tx_ring_info) * | |
7584 | TG3_TX_RING_SIZE, GFP_KERNEL); | |
19cfaecc MC |
7585 | if (!tnapi->tx_buffers) |
7586 | goto err_out; | |
7587 | ||
4bae65c8 MC |
7588 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
7589 | TG3_TX_RING_BYTES, | |
7590 | &tnapi->tx_desc_mapping, | |
7591 | GFP_KERNEL); | |
19cfaecc MC |
7592 | if (!tnapi->tx_ring) |
7593 | goto err_out; | |
7594 | } | |
7595 | ||
8d9d7cfc MC |
7596 | /* |
7597 | * When RSS is enabled, the status block format changes | |
7598 | * slightly. The "rx_jumbo_consumer", "reserved", | |
7599 | * and "rx_mini_consumer" members get mapped to the | |
7600 | * other three rx return ring producer indexes. | |
7601 | */ | |
7602 | switch (i) { | |
7603 | default: | |
f891ea16 MC |
7604 | if (tg3_flag(tp, ENABLE_RSS)) { |
7605 | tnapi->rx_rcb_prod_idx = NULL; | |
7606 | break; | |
7607 | } | |
7608 | /* Fall through */ | |
7609 | case 1: | |
8d9d7cfc MC |
7610 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; |
7611 | break; | |
7612 | case 2: | |
7613 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
7614 | break; | |
7615 | case 3: | |
7616 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
7617 | break; | |
7618 | case 4: | |
7619 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
7620 | break; | |
7621 | } | |
72334482 | 7622 | |
0c1d0e2b MC |
7623 | /* |
7624 | * If multivector RSS is enabled, vector 0 does not handle | |
7625 | * rx or tx interrupts. Don't allocate any resources for it. | |
7626 | */ | |
63c3a66f | 7627 | if (!i && tg3_flag(tp, ENABLE_RSS)) |
0c1d0e2b MC |
7628 | continue; |
7629 | ||
4bae65c8 MC |
7630 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
7631 | TG3_RX_RCB_RING_BYTES(tp), | |
7632 | &tnapi->rx_rcb_mapping, | |
7633 | GFP_KERNEL); | |
f77a6a8e MC |
7634 | if (!tnapi->rx_rcb) |
7635 | goto err_out; | |
72334482 | 7636 | |
f77a6a8e | 7637 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 7638 | } |
1da177e4 LT |
7639 | |
7640 | return 0; | |
7641 | ||
7642 | err_out: | |
7643 | tg3_free_consistent(tp); | |
7644 | return -ENOMEM; | |
7645 | } | |
7646 | ||
7647 | #define MAX_WAIT_CNT 1000 | |
7648 | ||
7649 | /* To stop a block, clear the enable bit and poll till it | |
7650 | * clears. tp->lock is held. | |
7651 | */ | |
b3b7d6be | 7652 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
7653 | { |
7654 | unsigned int i; | |
7655 | u32 val; | |
7656 | ||
63c3a66f | 7657 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
7658 | switch (ofs) { |
7659 | case RCVLSC_MODE: | |
7660 | case DMAC_MODE: | |
7661 | case MBFREE_MODE: | |
7662 | case BUFMGR_MODE: | |
7663 | case MEMARB_MODE: | |
7664 | /* We can't enable/disable these bits of the | |
7665 | * 5705/5750, just say success. | |
7666 | */ | |
7667 | return 0; | |
7668 | ||
7669 | default: | |
7670 | break; | |
855e1111 | 7671 | } |
1da177e4 LT |
7672 | } |
7673 | ||
7674 | val = tr32(ofs); | |
7675 | val &= ~enable_bit; | |
7676 | tw32_f(ofs, val); | |
7677 | ||
7678 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
7679 | udelay(100); | |
7680 | val = tr32(ofs); | |
7681 | if ((val & enable_bit) == 0) | |
7682 | break; | |
7683 | } | |
7684 | ||
b3b7d6be | 7685 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
7686 | dev_err(&tp->pdev->dev, |
7687 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
7688 | ofs, enable_bit); | |
1da177e4 LT |
7689 | return -ENODEV; |
7690 | } | |
7691 | ||
7692 | return 0; | |
7693 | } | |
7694 | ||
7695 | /* tp->lock is held. */ | |
b3b7d6be | 7696 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
7697 | { |
7698 | int i, err; | |
7699 | ||
7700 | tg3_disable_ints(tp); | |
7701 | ||
7702 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
7703 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7704 | udelay(10); | |
7705 | ||
b3b7d6be DM |
7706 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
7707 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
7708 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
7709 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
7710 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
7711 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
7712 | ||
7713 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
7714 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
7715 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
7716 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
7717 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
7718 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
7719 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
7720 | |
7721 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
7722 | tw32_f(MAC_MODE, tp->mac_mode); | |
7723 | udelay(40); | |
7724 | ||
7725 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
7726 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
7727 | ||
7728 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
7729 | udelay(100); | |
7730 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
7731 | break; | |
7732 | } | |
7733 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
7734 | dev_err(&tp->pdev->dev, |
7735 | "%s timed out, TX_MODE_ENABLE will not clear " | |
7736 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 7737 | err |= -ENODEV; |
1da177e4 LT |
7738 | } |
7739 | ||
e6de8ad1 | 7740 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
7741 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
7742 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
7743 | |
7744 | tw32(FTQ_RESET, 0xffffffff); | |
7745 | tw32(FTQ_RESET, 0x00000000); | |
7746 | ||
b3b7d6be DM |
7747 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
7748 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 7749 | |
f77a6a8e MC |
7750 | for (i = 0; i < tp->irq_cnt; i++) { |
7751 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7752 | if (tnapi->hw_status) | |
7753 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7754 | } | |
1da177e4 | 7755 | |
1da177e4 LT |
7756 | return err; |
7757 | } | |
7758 | ||
ee6a99b5 MC |
7759 | /* Save PCI command register before chip reset */ |
7760 | static void tg3_save_pci_state(struct tg3 *tp) | |
7761 | { | |
8a6eac90 | 7762 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
7763 | } |
7764 | ||
7765 | /* Restore PCI state after chip reset */ | |
7766 | static void tg3_restore_pci_state(struct tg3 *tp) | |
7767 | { | |
7768 | u32 val; | |
7769 | ||
7770 | /* Re-enable indirect register accesses. */ | |
7771 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
7772 | tp->misc_host_ctrl); | |
7773 | ||
7774 | /* Set MAX PCI retry to zero. */ | |
7775 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
7776 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 7777 | tg3_flag(tp, PCIX_MODE)) |
ee6a99b5 | 7778 | val |= PCISTATE_RETRY_SAME_DMA; |
0d3031d9 | 7779 | /* Allow reads and writes to the APE register and memory space. */ |
63c3a66f | 7780 | if (tg3_flag(tp, ENABLE_APE)) |
0d3031d9 | 7781 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
f92d9dc1 MC |
7782 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7783 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
7784 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
7785 | ||
8a6eac90 | 7786 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 7787 | |
2c55a3d0 MC |
7788 | if (!tg3_flag(tp, PCI_EXPRESS)) { |
7789 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
7790 | tp->pci_cacheline_sz); | |
7791 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
7792 | tp->pci_lat_timer); | |
114342f2 | 7793 | } |
5f5c51e3 | 7794 | |
ee6a99b5 | 7795 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
63c3a66f | 7796 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
7797 | u16 pcix_cmd; |
7798 | ||
7799 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7800 | &pcix_cmd); | |
7801 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
7802 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7803 | pcix_cmd); | |
7804 | } | |
ee6a99b5 | 7805 | |
63c3a66f | 7806 | if (tg3_flag(tp, 5780_CLASS)) { |
ee6a99b5 MC |
7807 | |
7808 | /* Chip reset on 5780 will reset MSI enable bit, | |
7809 | * so need to restore it. | |
7810 | */ | |
63c3a66f | 7811 | if (tg3_flag(tp, USING_MSI)) { |
ee6a99b5 MC |
7812 | u16 ctrl; |
7813 | ||
7814 | pci_read_config_word(tp->pdev, | |
7815 | tp->msi_cap + PCI_MSI_FLAGS, | |
7816 | &ctrl); | |
7817 | pci_write_config_word(tp->pdev, | |
7818 | tp->msi_cap + PCI_MSI_FLAGS, | |
7819 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
7820 | val = tr32(MSGINT_MODE); | |
7821 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
7822 | } | |
7823 | } | |
7824 | } | |
7825 | ||
1da177e4 LT |
7826 | /* tp->lock is held. */ |
7827 | static int tg3_chip_reset(struct tg3 *tp) | |
7828 | { | |
7829 | u32 val; | |
1ee582d8 | 7830 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 7831 | int i, err; |
1da177e4 | 7832 | |
f49639e6 DM |
7833 | tg3_nvram_lock(tp); |
7834 | ||
77b483f1 MC |
7835 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
7836 | ||
f49639e6 DM |
7837 | /* No matching tg3_nvram_unlock() after this because |
7838 | * chip reset below will undo the nvram lock. | |
7839 | */ | |
7840 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 7841 | |
ee6a99b5 MC |
7842 | /* GRC_MISC_CFG core clock reset will clear the memory |
7843 | * enable bit in PCI register 4 and the MSI enable bit | |
7844 | * on some chips, so we save relevant registers here. | |
7845 | */ | |
7846 | tg3_save_pci_state(tp); | |
7847 | ||
d9ab5ad1 | 7848 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
63c3a66f | 7849 | tg3_flag(tp, 5755_PLUS)) |
d9ab5ad1 MC |
7850 | tw32(GRC_FASTBOOT_PC, 0); |
7851 | ||
1da177e4 LT |
7852 | /* |
7853 | * We must avoid the readl() that normally takes place. | |
7854 | * It locks machines, causes machine checks, and other | |
7855 | * fun things. So, temporarily disable the 5701 | |
7856 | * hardware workaround, while we do the reset. | |
7857 | */ | |
1ee582d8 MC |
7858 | write_op = tp->write32; |
7859 | if (write_op == tg3_write_flush_reg32) | |
7860 | tp->write32 = tg3_write32; | |
1da177e4 | 7861 | |
d18edcb2 MC |
7862 | /* Prevent the irq handler from reading or writing PCI registers |
7863 | * during chip reset when the memory enable bit in the PCI command | |
7864 | * register may be cleared. The chip does not generate interrupt | |
7865 | * at this time, but the irq handler may still be called due to irq | |
7866 | * sharing or irqpoll. | |
7867 | */ | |
63c3a66f | 7868 | tg3_flag_set(tp, CHIP_RESETTING); |
f77a6a8e MC |
7869 | for (i = 0; i < tp->irq_cnt; i++) { |
7870 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7871 | if (tnapi->hw_status) { | |
7872 | tnapi->hw_status->status = 0; | |
7873 | tnapi->hw_status->status_tag = 0; | |
7874 | } | |
7875 | tnapi->last_tag = 0; | |
7876 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 7877 | } |
d18edcb2 | 7878 | smp_mb(); |
4f125f42 MC |
7879 | |
7880 | for (i = 0; i < tp->irq_cnt; i++) | |
7881 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 7882 | |
255ca311 MC |
7883 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7884 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7885 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7886 | } | |
7887 | ||
1da177e4 LT |
7888 | /* do the reset */ |
7889 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7890 | ||
63c3a66f | 7891 | if (tg3_flag(tp, PCI_EXPRESS)) { |
88075d91 MC |
7892 | /* Force PCIe 1.0a mode */ |
7893 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7894 | !tg3_flag(tp, 57765_PLUS) && |
88075d91 MC |
7895 | tr32(TG3_PCIE_PHY_TSTCTL) == |
7896 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7897 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7898 | ||
1da177e4 LT |
7899 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
7900 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7901 | val |= (1 << 29); | |
7902 | } | |
7903 | } | |
7904 | ||
b5d3772c MC |
7905 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7906 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7907 | tw32(GRC_VCPU_EXT_CTRL, | |
7908 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7909 | } | |
7910 | ||
f37500d3 | 7911 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
63c3a66f | 7912 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) |
1da177e4 | 7913 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 7914 | |
1da177e4 LT |
7915 | tw32(GRC_MISC_CFG, val); |
7916 | ||
1ee582d8 MC |
7917 | /* restore 5701 hardware bug workaround write method */ |
7918 | tp->write32 = write_op; | |
1da177e4 LT |
7919 | |
7920 | /* Unfortunately, we have to delay before the PCI read back. | |
7921 | * Some 575X chips even will not respond to a PCI cfg access | |
7922 | * when the reset command is given to the chip. | |
7923 | * | |
7924 | * How do these hardware designers expect things to work | |
7925 | * properly if the PCI write is posted for a long period | |
7926 | * of time? It is always necessary to have some method by | |
7927 | * which a register read back can occur to push the write | |
7928 | * out which does the reset. | |
7929 | * | |
7930 | * For most tg3 variants the trick below was working. | |
7931 | * Ho hum... | |
7932 | */ | |
7933 | udelay(120); | |
7934 | ||
7935 | /* Flush PCI posted writes. The normal MMIO registers | |
7936 | * are inaccessible at this time so this is the only | |
7937 | * way to make this reliably (actually, this is no longer | |
7938 | * the case, see above). I tried to use indirect | |
7939 | * register read/write but this upset some 5701 variants. | |
7940 | */ | |
7941 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7942 | ||
7943 | udelay(120); | |
7944 | ||
708ebb3a | 7945 | if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) { |
e7126997 MC |
7946 | u16 val16; |
7947 | ||
1da177e4 LT |
7948 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
7949 | int i; | |
7950 | u32 cfg_val; | |
7951 | ||
7952 | /* Wait for link training to complete. */ | |
7953 | for (i = 0; i < 5000; i++) | |
7954 | udelay(100); | |
7955 | ||
7956 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7957 | pci_write_config_dword(tp->pdev, 0xc4, | |
7958 | cfg_val | (1 << 15)); | |
7959 | } | |
5e7dfd0f | 7960 | |
e7126997 MC |
7961 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
7962 | pci_read_config_word(tp->pdev, | |
708ebb3a | 7963 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 MC |
7964 | &val16); |
7965 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7966 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7967 | /* | |
7968 | * Older PCIe devices only support the 128 byte | |
7969 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 7970 | */ |
63c3a66f | 7971 | if (!tg3_flag(tp, CPMU_PRESENT)) |
e7126997 | 7972 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
5e7dfd0f | 7973 | pci_write_config_word(tp->pdev, |
708ebb3a | 7974 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 | 7975 | val16); |
5e7dfd0f | 7976 | |
5e7dfd0f MC |
7977 | /* Clear error status */ |
7978 | pci_write_config_word(tp->pdev, | |
708ebb3a | 7979 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA, |
5e7dfd0f MC |
7980 | PCI_EXP_DEVSTA_CED | |
7981 | PCI_EXP_DEVSTA_NFED | | |
7982 | PCI_EXP_DEVSTA_FED | | |
7983 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
7984 | } |
7985 | ||
ee6a99b5 | 7986 | tg3_restore_pci_state(tp); |
1da177e4 | 7987 | |
63c3a66f JP |
7988 | tg3_flag_clear(tp, CHIP_RESETTING); |
7989 | tg3_flag_clear(tp, ERROR_PROCESSED); | |
d18edcb2 | 7990 | |
ee6a99b5 | 7991 | val = 0; |
63c3a66f | 7992 | if (tg3_flag(tp, 5780_CLASS)) |
4cf78e4f | 7993 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 7994 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
7995 | |
7996 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7997 | tg3_stop_fw(tp); | |
7998 | tw32(0x5000, 0x400); | |
7999 | } | |
8000 | ||
8001 | tw32(GRC_MODE, tp->grc_mode); | |
8002 | ||
8003 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 8004 | val = tr32(0xc4); |
1da177e4 LT |
8005 | |
8006 | tw32(0xc4, val | (1 << 15)); | |
8007 | } | |
8008 | ||
8009 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
8010 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
8011 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
8012 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
8013 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
8014 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8015 | } | |
8016 | ||
f07e9af3 | 8017 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
9e975cc2 | 8018 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; |
d2394e6b | 8019 | val = tp->mac_mode; |
f07e9af3 | 8020 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
9e975cc2 | 8021 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; |
d2394e6b | 8022 | val = tp->mac_mode; |
1da177e4 | 8023 | } else |
d2394e6b MC |
8024 | val = 0; |
8025 | ||
8026 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
8027 | udelay(40); |
8028 | ||
77b483f1 MC |
8029 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
8030 | ||
7a6f4369 MC |
8031 | err = tg3_poll_fw(tp); |
8032 | if (err) | |
8033 | return err; | |
1da177e4 | 8034 | |
0a9140cf MC |
8035 | tg3_mdio_start(tp); |
8036 | ||
63c3a66f | 8037 | if (tg3_flag(tp, PCI_EXPRESS) && |
f6eb9b1f MC |
8038 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
8039 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 8040 | !tg3_flag(tp, 57765_PLUS)) { |
ab0049b4 | 8041 | val = tr32(0x7c00); |
1da177e4 LT |
8042 | |
8043 | tw32(0x7c00, val | (1 << 25)); | |
8044 | } | |
8045 | ||
d78b59f5 MC |
8046 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
8047 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
8048 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
8049 | } | |
8050 | ||
1da177e4 | 8051 | /* Reprobe ASF enable state. */ |
63c3a66f JP |
8052 | tg3_flag_clear(tp, ENABLE_ASF); |
8053 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
8054 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
8055 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
8056 | u32 nic_cfg; | |
8057 | ||
8058 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
8059 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f | 8060 | tg3_flag_set(tp, ENABLE_ASF); |
4ba526ce | 8061 | tp->last_event_jiffies = jiffies; |
63c3a66f JP |
8062 | if (tg3_flag(tp, 5750_PLUS)) |
8063 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
8064 | } |
8065 | } | |
8066 | ||
8067 | return 0; | |
8068 | } | |
8069 | ||
65ec698d MC |
8070 | static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *); |
8071 | static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *); | |
92feeabf | 8072 | |
1da177e4 | 8073 | /* tp->lock is held. */ |
944d980e | 8074 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
8075 | { |
8076 | int err; | |
8077 | ||
8078 | tg3_stop_fw(tp); | |
8079 | ||
944d980e | 8080 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 8081 | |
b3b7d6be | 8082 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
8083 | err = tg3_chip_reset(tp); |
8084 | ||
daba2a63 MC |
8085 | __tg3_set_mac_addr(tp, 0); |
8086 | ||
944d980e MC |
8087 | tg3_write_sig_legacy(tp, kind); |
8088 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 | 8089 | |
92feeabf MC |
8090 | if (tp->hw_stats) { |
8091 | /* Save the stats across chip resets... */ | |
b4017c53 | 8092 | tg3_get_nstats(tp, &tp->net_stats_prev); |
92feeabf MC |
8093 | tg3_get_estats(tp, &tp->estats_prev); |
8094 | ||
8095 | /* And make sure the next sample is new data */ | |
8096 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
8097 | } | |
8098 | ||
1da177e4 LT |
8099 | if (err) |
8100 | return err; | |
8101 | ||
8102 | return 0; | |
8103 | } | |
8104 | ||
1da177e4 LT |
8105 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
8106 | { | |
8107 | struct tg3 *tp = netdev_priv(dev); | |
8108 | struct sockaddr *addr = p; | |
986e0aeb | 8109 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 8110 | |
f9804ddb | 8111 | if (!is_valid_ether_addr(addr->sa_data)) |
504f9b5a | 8112 | return -EADDRNOTAVAIL; |
f9804ddb | 8113 | |
1da177e4 LT |
8114 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
8115 | ||
e75f7c90 MC |
8116 | if (!netif_running(dev)) |
8117 | return 0; | |
8118 | ||
63c3a66f | 8119 | if (tg3_flag(tp, ENABLE_ASF)) { |
986e0aeb | 8120 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 8121 | |
986e0aeb MC |
8122 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
8123 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
8124 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
8125 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
8126 | ||
8127 | /* Skip MAC addr 1 if ASF is using it. */ | |
8128 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
8129 | !(addr1_high == 0 && addr1_low == 0)) | |
8130 | skip_mac_1 = 1; | |
58712ef9 | 8131 | } |
986e0aeb MC |
8132 | spin_lock_bh(&tp->lock); |
8133 | __tg3_set_mac_addr(tp, skip_mac_1); | |
8134 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 8135 | |
b9ec6c1b | 8136 | return err; |
1da177e4 LT |
8137 | } |
8138 | ||
8139 | /* tp->lock is held. */ | |
8140 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
8141 | dma_addr_t mapping, u32 maxlen_flags, | |
8142 | u32 nic_addr) | |
8143 | { | |
8144 | tg3_write_mem(tp, | |
8145 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
8146 | ((u64) mapping >> 32)); | |
8147 | tg3_write_mem(tp, | |
8148 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
8149 | ((u64) mapping & 0xffffffff)); | |
8150 | tg3_write_mem(tp, | |
8151 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
8152 | maxlen_flags); | |
8153 | ||
63c3a66f | 8154 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8155 | tg3_write_mem(tp, |
8156 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
8157 | nic_addr); | |
8158 | } | |
8159 | ||
d244c892 | 8160 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 8161 | { |
b6080e12 MC |
8162 | int i; |
8163 | ||
63c3a66f | 8164 | if (!tg3_flag(tp, ENABLE_TSS)) { |
b6080e12 MC |
8165 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
8166 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
8167 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
8168 | } else { |
8169 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
8170 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
8171 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 8172 | } |
b6080e12 | 8173 | |
63c3a66f | 8174 | if (!tg3_flag(tp, ENABLE_RSS)) { |
19cfaecc MC |
8175 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
8176 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
8177 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
8178 | } else { | |
b6080e12 MC |
8179 | tw32(HOSTCC_RXCOL_TICKS, 0); |
8180 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
8181 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 8182 | } |
b6080e12 | 8183 | |
63c3a66f | 8184 | if (!tg3_flag(tp, 5705_PLUS)) { |
15f9850d DM |
8185 | u32 val = ec->stats_block_coalesce_usecs; |
8186 | ||
b6080e12 MC |
8187 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
8188 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
8189 | ||
15f9850d DM |
8190 | if (!netif_carrier_ok(tp->dev)) |
8191 | val = 0; | |
8192 | ||
8193 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
8194 | } | |
b6080e12 MC |
8195 | |
8196 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
8197 | u32 reg; | |
8198 | ||
8199 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
8200 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
8201 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
8202 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
8203 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
8204 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc | 8205 | |
63c3a66f | 8206 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
8207 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; |
8208 | tw32(reg, ec->tx_coalesce_usecs); | |
8209 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
8210 | tw32(reg, ec->tx_max_coalesced_frames); | |
8211 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
8212 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
8213 | } | |
b6080e12 MC |
8214 | } |
8215 | ||
8216 | for (; i < tp->irq_max - 1; i++) { | |
8217 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 8218 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 8219 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc | 8220 | |
63c3a66f | 8221 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
8222 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); |
8223 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
8224 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
8225 | } | |
b6080e12 | 8226 | } |
15f9850d | 8227 | } |
1da177e4 | 8228 | |
2d31ecaf MC |
8229 | /* tp->lock is held. */ |
8230 | static void tg3_rings_reset(struct tg3 *tp) | |
8231 | { | |
8232 | int i; | |
f77a6a8e | 8233 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
8234 | struct tg3_napi *tnapi = &tp->napi[0]; |
8235 | ||
8236 | /* Disable all transmit rings but the first. */ | |
63c3a66f | 8237 | if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 8238 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; |
63c3a66f | 8239 | else if (tg3_flag(tp, 5717_PLUS)) |
3d37728b | 8240 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
55086ad9 | 8241 | else if (tg3_flag(tp, 57765_CLASS)) |
b703df6f | 8242 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; |
2d31ecaf MC |
8243 | else |
8244 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
8245 | ||
8246 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
8247 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
8248 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
8249 | BDINFO_FLAGS_DISABLED); | |
8250 | ||
8251 | ||
8252 | /* Disable all receive return rings but the first. */ | |
63c3a66f | 8253 | if (tg3_flag(tp, 5717_PLUS)) |
f6eb9b1f | 8254 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
63c3a66f | 8255 | else if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 8256 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f | 8257 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
55086ad9 | 8258 | tg3_flag(tp, 57765_CLASS)) |
2d31ecaf MC |
8259 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
8260 | else | |
8261 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
8262 | ||
8263 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
8264 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
8265 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
8266 | BDINFO_FLAGS_DISABLED); | |
8267 | ||
8268 | /* Disable interrupts */ | |
8269 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
0e6cf6a9 MC |
8270 | tp->napi[0].chk_msi_cnt = 0; |
8271 | tp->napi[0].last_rx_cons = 0; | |
8272 | tp->napi[0].last_tx_cons = 0; | |
2d31ecaf MC |
8273 | |
8274 | /* Zero mailbox registers. */ | |
63c3a66f | 8275 | if (tg3_flag(tp, SUPPORT_MSIX)) { |
6fd45cb8 | 8276 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
8277 | tp->napi[i].tx_prod = 0; |
8278 | tp->napi[i].tx_cons = 0; | |
63c3a66f | 8279 | if (tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 8280 | tw32_mailbox(tp->napi[i].prodmbox, 0); |
f77a6a8e MC |
8281 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
8282 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7f230735 | 8283 | tp->napi[i].chk_msi_cnt = 0; |
0e6cf6a9 MC |
8284 | tp->napi[i].last_rx_cons = 0; |
8285 | tp->napi[i].last_tx_cons = 0; | |
f77a6a8e | 8286 | } |
63c3a66f | 8287 | if (!tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 8288 | tw32_mailbox(tp->napi[0].prodmbox, 0); |
f77a6a8e MC |
8289 | } else { |
8290 | tp->napi[0].tx_prod = 0; | |
8291 | tp->napi[0].tx_cons = 0; | |
8292 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
8293 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
8294 | } | |
2d31ecaf MC |
8295 | |
8296 | /* Make sure the NIC-based send BD rings are disabled. */ | |
63c3a66f | 8297 | if (!tg3_flag(tp, 5705_PLUS)) { |
2d31ecaf MC |
8298 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
8299 | for (i = 0; i < 16; i++) | |
8300 | tw32_tx_mbox(mbox + i * 8, 0); | |
8301 | } | |
8302 | ||
8303 | txrcb = NIC_SRAM_SEND_RCB; | |
8304 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
8305 | ||
8306 | /* Clear status block in ram. */ | |
8307 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8308 | ||
8309 | /* Set status block DMA address */ | |
8310 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
8311 | ((u64) tnapi->status_mapping >> 32)); | |
8312 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8313 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
8314 | ||
f77a6a8e MC |
8315 | if (tnapi->tx_ring) { |
8316 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8317 | (TG3_TX_RING_SIZE << | |
8318 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8319 | NIC_SRAM_TX_BUFFER_DESC); | |
8320 | txrcb += TG3_BDINFO_SIZE; | |
8321 | } | |
8322 | ||
8323 | if (tnapi->rx_rcb) { | |
8324 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
8325 | (tp->rx_ret_ring_mask + 1) << |
8326 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
8327 | rxrcb += TG3_BDINFO_SIZE; |
8328 | } | |
8329 | ||
8330 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 8331 | |
f77a6a8e MC |
8332 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
8333 | u64 mapping = (u64)tnapi->status_mapping; | |
8334 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
8335 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
8336 | ||
8337 | /* Clear status block in ram. */ | |
8338 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8339 | ||
19cfaecc MC |
8340 | if (tnapi->tx_ring) { |
8341 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8342 | (TG3_TX_RING_SIZE << | |
8343 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8344 | NIC_SRAM_TX_BUFFER_DESC); | |
8345 | txrcb += TG3_BDINFO_SIZE; | |
8346 | } | |
f77a6a8e MC |
8347 | |
8348 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 8349 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
8350 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
8351 | ||
8352 | stblk += 8; | |
f77a6a8e MC |
8353 | rxrcb += TG3_BDINFO_SIZE; |
8354 | } | |
2d31ecaf MC |
8355 | } |
8356 | ||
eb07a940 MC |
8357 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
8358 | { | |
8359 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
8360 | ||
63c3a66f JP |
8361 | if (!tg3_flag(tp, 5750_PLUS) || |
8362 | tg3_flag(tp, 5780_CLASS) || | |
eb07a940 | 8363 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
513aa6ea MC |
8364 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
8365 | tg3_flag(tp, 57765_PLUS)) | |
eb07a940 MC |
8366 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; |
8367 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
8368 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
8369 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
8370 | else | |
8371 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
8372 | ||
8373 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
8374 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
8375 | ||
8376 | val = min(nic_rep_thresh, host_rep_thresh); | |
8377 | tw32(RCVBDI_STD_THRESH, val); | |
8378 | ||
63c3a66f | 8379 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8380 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); |
8381 | ||
63c3a66f | 8382 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
eb07a940 MC |
8383 | return; |
8384 | ||
513aa6ea | 8385 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; |
eb07a940 MC |
8386 | |
8387 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
8388 | ||
8389 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
8390 | tw32(RCVBDI_JUMBO_THRESH, val); | |
8391 | ||
63c3a66f | 8392 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8393 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); |
8394 | } | |
8395 | ||
ccd5ba9d MC |
8396 | static inline u32 calc_crc(unsigned char *buf, int len) |
8397 | { | |
8398 | u32 reg; | |
8399 | u32 tmp; | |
8400 | int j, k; | |
8401 | ||
8402 | reg = 0xffffffff; | |
8403 | ||
8404 | for (j = 0; j < len; j++) { | |
8405 | reg ^= buf[j]; | |
8406 | ||
8407 | for (k = 0; k < 8; k++) { | |
8408 | tmp = reg & 0x01; | |
8409 | ||
8410 | reg >>= 1; | |
8411 | ||
8412 | if (tmp) | |
8413 | reg ^= 0xedb88320; | |
8414 | } | |
8415 | } | |
8416 | ||
8417 | return ~reg; | |
8418 | } | |
8419 | ||
8420 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
8421 | { | |
8422 | /* accept or reject all multicast frames */ | |
8423 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
8424 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
8425 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
8426 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
8427 | } | |
8428 | ||
8429 | static void __tg3_set_rx_mode(struct net_device *dev) | |
8430 | { | |
8431 | struct tg3 *tp = netdev_priv(dev); | |
8432 | u32 rx_mode; | |
8433 | ||
8434 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
8435 | RX_MODE_KEEP_VLAN_TAG); | |
8436 | ||
8437 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) | |
8438 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG | |
8439 | * flag clear. | |
8440 | */ | |
8441 | if (!tg3_flag(tp, ENABLE_ASF)) | |
8442 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
8443 | #endif | |
8444 | ||
8445 | if (dev->flags & IFF_PROMISC) { | |
8446 | /* Promiscuous mode. */ | |
8447 | rx_mode |= RX_MODE_PROMISC; | |
8448 | } else if (dev->flags & IFF_ALLMULTI) { | |
8449 | /* Accept all multicast. */ | |
8450 | tg3_set_multi(tp, 1); | |
8451 | } else if (netdev_mc_empty(dev)) { | |
8452 | /* Reject all multicast. */ | |
8453 | tg3_set_multi(tp, 0); | |
8454 | } else { | |
8455 | /* Accept one or more multicast(s). */ | |
8456 | struct netdev_hw_addr *ha; | |
8457 | u32 mc_filter[4] = { 0, }; | |
8458 | u32 regidx; | |
8459 | u32 bit; | |
8460 | u32 crc; | |
8461 | ||
8462 | netdev_for_each_mc_addr(ha, dev) { | |
8463 | crc = calc_crc(ha->addr, ETH_ALEN); | |
8464 | bit = ~crc & 0x7f; | |
8465 | regidx = (bit & 0x60) >> 5; | |
8466 | bit &= 0x1f; | |
8467 | mc_filter[regidx] |= (1 << bit); | |
8468 | } | |
8469 | ||
8470 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
8471 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
8472 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
8473 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
8474 | } | |
8475 | ||
8476 | if (rx_mode != tp->rx_mode) { | |
8477 | tp->rx_mode = rx_mode; | |
8478 | tw32_f(MAC_RX_MODE, rx_mode); | |
8479 | udelay(10); | |
8480 | } | |
8481 | } | |
8482 | ||
90415477 MC |
8483 | static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp) |
8484 | { | |
8485 | int i; | |
8486 | ||
8487 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) | |
8488 | tp->rss_ind_tbl[i] = | |
8489 | ethtool_rxfh_indir_default(i, tp->irq_cnt - 1); | |
8490 | } | |
8491 | ||
8492 | static void tg3_rss_check_indir_tbl(struct tg3 *tp) | |
bcebcc46 MC |
8493 | { |
8494 | int i; | |
8495 | ||
8496 | if (!tg3_flag(tp, SUPPORT_MSIX)) | |
8497 | return; | |
8498 | ||
90415477 | 8499 | if (tp->irq_cnt <= 2) { |
bcebcc46 | 8500 | memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); |
90415477 MC |
8501 | return; |
8502 | } | |
8503 | ||
8504 | /* Validate table against current IRQ count */ | |
8505 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8506 | if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1) | |
8507 | break; | |
8508 | } | |
8509 | ||
8510 | if (i != TG3_RSS_INDIR_TBL_SIZE) | |
8511 | tg3_rss_init_dflt_indir_tbl(tp); | |
bcebcc46 MC |
8512 | } |
8513 | ||
90415477 | 8514 | static void tg3_rss_write_indir_tbl(struct tg3 *tp) |
bcebcc46 MC |
8515 | { |
8516 | int i = 0; | |
8517 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8518 | ||
8519 | while (i < TG3_RSS_INDIR_TBL_SIZE) { | |
8520 | u32 val = tp->rss_ind_tbl[i]; | |
8521 | i++; | |
8522 | for (; i % 8; i++) { | |
8523 | val <<= 4; | |
8524 | val |= tp->rss_ind_tbl[i]; | |
8525 | } | |
8526 | tw32(reg, val); | |
8527 | reg += 4; | |
8528 | } | |
8529 | } | |
8530 | ||
1da177e4 | 8531 | /* tp->lock is held. */ |
8e7a22e3 | 8532 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
8533 | { |
8534 | u32 val, rdmac_mode; | |
8535 | int i, err, limit; | |
8fea32b9 | 8536 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
8537 | |
8538 | tg3_disable_ints(tp); | |
8539 | ||
8540 | tg3_stop_fw(tp); | |
8541 | ||
8542 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
8543 | ||
63c3a66f | 8544 | if (tg3_flag(tp, INIT_COMPLETE)) |
e6de8ad1 | 8545 | tg3_abort_hw(tp, 1); |
1da177e4 | 8546 | |
699c0193 MC |
8547 | /* Enable MAC control of LPI */ |
8548 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
8549 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
8550 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
8551 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
8552 | ||
8553 | tw32_f(TG3_CPMU_EEE_CTRL, | |
8554 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
8555 | ||
a386b901 MC |
8556 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
8557 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
8558 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
8559 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
8560 | ||
8561 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8562 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
8563 | ||
63c3a66f | 8564 | if (tg3_flag(tp, ENABLE_APE)) |
a386b901 MC |
8565 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; |
8566 | ||
8567 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
8568 | ||
8569 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
8570 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
8571 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
8572 | ||
8573 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 8574 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 8575 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
8576 | } |
8577 | ||
603f1173 | 8578 | if (reset_phy) |
d4d2c558 MC |
8579 | tg3_phy_reset(tp); |
8580 | ||
1da177e4 LT |
8581 | err = tg3_chip_reset(tp); |
8582 | if (err) | |
8583 | return err; | |
8584 | ||
8585 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
8586 | ||
bcb37f6c | 8587 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
8588 | val = tr32(TG3_CPMU_CTRL); |
8589 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
8590 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
8591 | |
8592 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8593 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8594 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8595 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8596 | ||
8597 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
8598 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
8599 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
8600 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
8601 | ||
8602 | val = tr32(TG3_CPMU_HST_ACC); | |
8603 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
8604 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
8605 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
8606 | } |
8607 | ||
33466d93 MC |
8608 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8609 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
8610 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
8611 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
8612 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
8613 | |
8614 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
8615 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
8616 | ||
8617 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 8618 | |
f40386c8 MC |
8619 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
8620 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
8621 | } |
8622 | ||
63c3a66f | 8623 | if (tg3_flag(tp, L1PLLPD_EN)) { |
614b0590 MC |
8624 | u32 grc_mode = tr32(GRC_MODE); |
8625 | ||
8626 | /* Access the lower 1K of PL PCIE block registers. */ | |
8627 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8628 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
8629 | ||
8630 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
8631 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
8632 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
8633 | ||
8634 | tw32(GRC_MODE, grc_mode); | |
8635 | } | |
8636 | ||
55086ad9 | 8637 | if (tg3_flag(tp, 57765_CLASS)) { |
5093eedc MC |
8638 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
8639 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 8640 | |
5093eedc MC |
8641 | /* Access the lower 1K of PL PCIE block registers. */ |
8642 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8643 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 8644 | |
5093eedc MC |
8645 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
8646 | TG3_PCIE_PL_LO_PHYCTL5); | |
8647 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
8648 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 8649 | |
5093eedc MC |
8650 | tw32(GRC_MODE, grc_mode); |
8651 | } | |
a977dbe8 | 8652 | |
1ff30a59 MC |
8653 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { |
8654 | u32 grc_mode = tr32(GRC_MODE); | |
8655 | ||
8656 | /* Access the lower 1K of DL PCIE block registers. */ | |
8657 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8658 | tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); | |
8659 | ||
8660 | val = tr32(TG3_PCIE_TLDLPL_PORT + | |
8661 | TG3_PCIE_DL_LO_FTSMAX); | |
8662 | val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; | |
8663 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, | |
8664 | val | TG3_PCIE_DL_LO_FTSMAX_VAL); | |
8665 | ||
8666 | tw32(GRC_MODE, grc_mode); | |
8667 | } | |
8668 | ||
a977dbe8 MC |
8669 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
8670 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8671 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8672 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
8673 | } |
8674 | ||
1da177e4 LT |
8675 | /* This works around an issue with Athlon chipsets on |
8676 | * B3 tigon3 silicon. This bit has no effect on any | |
8677 | * other revision. But do not set this on PCI Express | |
795d01c5 | 8678 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 8679 | */ |
63c3a66f JP |
8680 | if (!tg3_flag(tp, CPMU_PRESENT)) { |
8681 | if (!tg3_flag(tp, PCI_EXPRESS)) | |
795d01c5 MC |
8682 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; |
8683 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8684 | } | |
1da177e4 LT |
8685 | |
8686 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 8687 | tg3_flag(tp, PCIX_MODE)) { |
1da177e4 LT |
8688 | val = tr32(TG3PCI_PCISTATE); |
8689 | val |= PCISTATE_RETRY_SAME_DMA; | |
8690 | tw32(TG3PCI_PCISTATE, val); | |
8691 | } | |
8692 | ||
63c3a66f | 8693 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
8694 | /* Allow reads and writes to the |
8695 | * APE register and memory space. | |
8696 | */ | |
8697 | val = tr32(TG3PCI_PCISTATE); | |
8698 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
8699 | PCISTATE_ALLOW_APE_SHMEM_WR | |
8700 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
8701 | tw32(TG3PCI_PCISTATE, val); |
8702 | } | |
8703 | ||
1da177e4 LT |
8704 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
8705 | /* Enable some hw fixes. */ | |
8706 | val = tr32(TG3PCI_MSI_DATA); | |
8707 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
8708 | tw32(TG3PCI_MSI_DATA, val); | |
8709 | } | |
8710 | ||
8711 | /* Descriptor ring init may make accesses to the | |
8712 | * NIC SRAM area to setup the TX descriptors, so we | |
8713 | * can only do this after the hardware has been | |
8714 | * successfully reset. | |
8715 | */ | |
32d8c572 MC |
8716 | err = tg3_init_rings(tp); |
8717 | if (err) | |
8718 | return err; | |
1da177e4 | 8719 | |
63c3a66f | 8720 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
8721 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
8722 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
8723 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
8724 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
55086ad9 | 8725 | if (!tg3_flag(tp, 57765_CLASS) && |
0aebff48 MC |
8726 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) |
8727 | val |= DMA_RWCTRL_TAGGED_STAT_WA; | |
cbf9ca6c MC |
8728 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
8729 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
8730 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
8731 | /* This value is determined during the probe time DMA |
8732 | * engine test, tg3_test_dma. | |
8733 | */ | |
8734 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
8735 | } | |
1da177e4 LT |
8736 | |
8737 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
8738 | GRC_MODE_4X_NIC_SEND_RINGS | | |
8739 | GRC_MODE_NO_TX_PHDR_CSUM | | |
8740 | GRC_MODE_NO_RX_PHDR_CSUM); | |
8741 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
8742 | |
8743 | /* Pseudo-header checksum is done by hardware logic and not | |
8744 | * the offload processers, so make the chip do the pseudo- | |
8745 | * header checksums on receive. For transmit it is more | |
8746 | * convenient to do the pseudo-header checksum in software | |
8747 | * as Linux does that on transmit for us in all cases. | |
8748 | */ | |
8749 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
8750 | |
8751 | tw32(GRC_MODE, | |
8752 | tp->grc_mode | | |
8753 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
8754 | ||
8755 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
8756 | val = tr32(GRC_MISC_CFG); | |
8757 | val &= ~0xff; | |
8758 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
8759 | tw32(GRC_MISC_CFG, val); | |
8760 | ||
8761 | /* Initialize MBUF/DESC pool. */ | |
63c3a66f | 8762 | if (tg3_flag(tp, 5750_PLUS)) { |
1da177e4 LT |
8763 | /* Do nothing. */ |
8764 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8765 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8766 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8767 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8768 | else | |
8769 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8770 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8771 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
63c3a66f | 8772 | } else if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8773 | int fw_len; |
8774 | ||
077f849d | 8775 | fw_len = tp->fw_len; |
1da177e4 LT |
8776 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
8777 | tw32(BUFMGR_MB_POOL_ADDR, | |
8778 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8779 | tw32(BUFMGR_MB_POOL_SIZE, | |
8780 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8781 | } | |
1da177e4 | 8782 | |
0f893dc6 | 8783 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
8784 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
8785 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8786 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8787 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8788 | tw32(BUFMGR_MB_HIGH_WATER, | |
8789 | tp->bufmgr_config.mbuf_high_water); | |
8790 | } else { | |
8791 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8792 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8793 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8794 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8795 | tw32(BUFMGR_MB_HIGH_WATER, | |
8796 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8797 | } | |
8798 | tw32(BUFMGR_DMA_LOW_WATER, | |
8799 | tp->bufmgr_config.dma_low_water); | |
8800 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8801 | tp->bufmgr_config.dma_high_water); | |
8802 | ||
d309a46e MC |
8803 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8804 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8805 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
4d958473 MC |
8806 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8807 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
8808 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
8809 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
d309a46e | 8810 | tw32(BUFMGR_MODE, val); |
1da177e4 LT |
8811 | for (i = 0; i < 2000; i++) { |
8812 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8813 | break; | |
8814 | udelay(10); | |
8815 | } | |
8816 | if (i >= 2000) { | |
05dbe005 | 8817 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
8818 | return -ENODEV; |
8819 | } | |
8820 | ||
eb07a940 MC |
8821 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
8822 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
b5d3772c | 8823 | |
eb07a940 | 8824 | tg3_setup_rxbd_thresholds(tp); |
1da177e4 LT |
8825 | |
8826 | /* Initialize TG3_BDINFO's at: | |
8827 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8828 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8829 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8830 | * | |
8831 | * like so: | |
8832 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8833 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8834 | * ring attribute flags | |
8835 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8836 | * | |
8837 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8838 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8839 | * | |
8840 | * The size of each ring is fixed in the firmware, but the location is | |
8841 | * configurable. | |
8842 | */ | |
8843 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 8844 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 8845 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8846 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
63c3a66f | 8847 | if (!tg3_flag(tp, 5717_PLUS)) |
87668d35 MC |
8848 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
8849 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 8850 | |
fdb72b38 | 8851 | /* Disable the mini ring */ |
63c3a66f | 8852 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8853 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8854 | BDINFO_FLAGS_DISABLED); | |
8855 | ||
fdb72b38 MC |
8856 | /* Program the jumbo buffer descriptor ring control |
8857 | * blocks on those devices that have them. | |
8858 | */ | |
a0512944 | 8859 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
63c3a66f | 8860 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { |
1da177e4 | 8861 | |
63c3a66f | 8862 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { |
1da177e4 | 8863 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 8864 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 8865 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8866 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
8867 | val = TG3_RX_JMB_RING_SIZE(tp) << |
8868 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 8869 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 8870 | val | BDINFO_FLAGS_USE_EXT_RECV); |
63c3a66f | 8871 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || |
55086ad9 | 8872 | tg3_flag(tp, 57765_CLASS)) |
87668d35 MC |
8873 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
8874 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
8875 | } else { |
8876 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8877 | BDINFO_FLAGS_DISABLED); | |
8878 | } | |
8879 | ||
63c3a66f | 8880 | if (tg3_flag(tp, 57765_PLUS)) { |
fa6b2aae | 8881 | val = TG3_RX_STD_RING_SIZE(tp); |
7cb32cf2 MC |
8882 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
8883 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8884 | } else | |
04380d40 | 8885 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 8886 | } else |
de9f5230 | 8887 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
8888 | |
8889 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 8890 | |
411da640 | 8891 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 8892 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 8893 | |
63c3a66f JP |
8894 | tpr->rx_jmb_prod_idx = |
8895 | tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; | |
66711e66 | 8896 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 8897 | |
2d31ecaf MC |
8898 | tg3_rings_reset(tp); |
8899 | ||
1da177e4 | 8900 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 8901 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
8902 | |
8903 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
8904 | tw32(MAC_RX_MTU_SIZE, |
8905 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
8906 | |
8907 | /* The slot time is changed by tg3_setup_phy if we | |
8908 | * run at gigabit with half duplex. | |
8909 | */ | |
f2096f94 MC |
8910 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
8911 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8912 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
8913 | ||
8914 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
8915 | val |= tr32(MAC_TX_LENGTHS) & | |
8916 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
8917 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
8918 | ||
8919 | tw32(MAC_TX_LENGTHS, val); | |
1da177e4 LT |
8920 | |
8921 | /* Receive rules. */ | |
8922 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8923 | tw32(RCVLPC_CONFIG, 0x0181); | |
8924 | ||
8925 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8926 | * the RCVLPC_STATE_ENABLE mask. | |
8927 | */ | |
8928 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8929 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8930 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8931 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8932 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 8933 | |
deabaac8 | 8934 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
8935 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
8936 | ||
57e6983c | 8937 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
8938 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
8939 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
8940 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
8941 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8942 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8943 | ||
c5908939 MC |
8944 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8945 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8946 | if (tg3_flag(tp, TSO_CAPABLE) && |
c13e3713 | 8947 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
8948 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
8949 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8950 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8951 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8952 | } | |
8953 | } | |
8954 | ||
63c3a66f | 8955 | if (tg3_flag(tp, PCI_EXPRESS)) |
85e94ced MC |
8956 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8957 | ||
63c3a66f JP |
8958 | if (tg3_flag(tp, HW_TSO_1) || |
8959 | tg3_flag(tp, HW_TSO_2) || | |
8960 | tg3_flag(tp, HW_TSO_3)) | |
027455ad MC |
8961 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
8962 | ||
108a6c16 | 8963 | if (tg3_flag(tp, 57765_PLUS) || |
e849cdc3 | 8964 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
027455ad MC |
8965 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
8966 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 8967 | |
f2096f94 MC |
8968 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
8969 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
8970 | ||
41a8a7ee MC |
8971 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
8972 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8973 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8974 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
63c3a66f | 8975 | tg3_flag(tp, 57765_PLUS)) { |
41a8a7ee | 8976 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
d78b59f5 MC |
8977 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8978 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b4495ed8 MC |
8979 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
8980 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8981 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8982 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8983 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8984 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 8985 | } |
41a8a7ee MC |
8986 | tw32(TG3_RDMA_RSRVCTRL_REG, |
8987 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8988 | } | |
8989 | ||
d78b59f5 MC |
8990 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8991 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
8992 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
8993 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8994 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8995 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8996 | } | |
8997 | ||
1da177e4 | 8998 | /* Receive/send statistics. */ |
63c3a66f | 8999 | if (tg3_flag(tp, 5750_PLUS)) { |
1661394e MC |
9000 | val = tr32(RCVLPC_STATS_ENABLE); |
9001 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
9002 | tw32(RCVLPC_STATS_ENABLE, val); | |
9003 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
63c3a66f | 9004 | tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
9005 | val = tr32(RCVLPC_STATS_ENABLE); |
9006 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
9007 | tw32(RCVLPC_STATS_ENABLE, val); | |
9008 | } else { | |
9009 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
9010 | } | |
9011 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
9012 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
9013 | tw32(SNDDATAI_STATSCTRL, | |
9014 | (SNDDATAI_SCTRL_ENABLE | | |
9015 | SNDDATAI_SCTRL_FASTUPD)); | |
9016 | ||
9017 | /* Setup host coalescing engine. */ | |
9018 | tw32(HOSTCC_MODE, 0); | |
9019 | for (i = 0; i < 2000; i++) { | |
9020 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
9021 | break; | |
9022 | udelay(10); | |
9023 | } | |
9024 | ||
d244c892 | 9025 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 9026 | |
63c3a66f | 9027 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
9028 | /* Status/statistics block address. See tg3_timer, |
9029 | * the tg3_periodic_fetch_stats call there, and | |
9030 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
9031 | */ | |
1da177e4 LT |
9032 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
9033 | ((u64) tp->stats_mapping >> 32)); | |
9034 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
9035 | ((u64) tp->stats_mapping & 0xffffffff)); | |
9036 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 9037 | |
1da177e4 | 9038 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
9039 | |
9040 | /* Clear statistics and status block memory areas */ | |
9041 | for (i = NIC_SRAM_STATS_BLK; | |
9042 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
9043 | i += sizeof(u32)) { | |
9044 | tg3_write_mem(tp, i, 0); | |
9045 | udelay(40); | |
9046 | } | |
1da177e4 LT |
9047 | } |
9048 | ||
9049 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
9050 | ||
9051 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
9052 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
63c3a66f | 9053 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
9054 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); |
9055 | ||
f07e9af3 MC |
9056 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
9057 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
9058 | /* reset to prevent losing 1st rx packet intermittently */ |
9059 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
9060 | udelay(10); | |
9061 | } | |
9062 | ||
3bda1258 | 9063 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | |
9e975cc2 MC |
9064 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | |
9065 | MAC_MODE_FHDE_ENABLE; | |
9066 | if (tg3_flag(tp, ENABLE_APE)) | |
9067 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
63c3a66f | 9068 | if (!tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 9069 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
9070 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
9071 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
9072 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
9073 | udelay(40); | |
9074 | ||
314fba34 | 9075 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
63c3a66f | 9076 | * If TG3_FLAG_IS_NIC is zero, we should read the |
314fba34 MC |
9077 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
9078 | * whether used as inputs or outputs, are set by boot code after | |
9079 | * reset. | |
9080 | */ | |
63c3a66f | 9081 | if (!tg3_flag(tp, IS_NIC)) { |
314fba34 MC |
9082 | u32 gpio_mask; |
9083 | ||
9d26e213 MC |
9084 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
9085 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
9086 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
9087 | |
9088 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
9089 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
9090 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
9091 | ||
af36e6b6 MC |
9092 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
9093 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
9094 | ||
aaf84465 | 9095 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
9096 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
9097 | ||
9098 | /* GPIO1 must be driven high for eeprom write protect */ | |
63c3a66f | 9099 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) |
9d26e213 MC |
9100 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
9101 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 9102 | } |
1da177e4 LT |
9103 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
9104 | udelay(100); | |
9105 | ||
c3b5003b | 9106 | if (tg3_flag(tp, USING_MSIX)) { |
baf8a94a | 9107 | val = tr32(MSGINT_MODE); |
c3b5003b MC |
9108 | val |= MSGINT_MODE_ENABLE; |
9109 | if (tp->irq_cnt > 1) | |
9110 | val |= MSGINT_MODE_MULTIVEC_EN; | |
5b39de91 MC |
9111 | if (!tg3_flag(tp, 1SHOT_MSI)) |
9112 | val |= MSGINT_MODE_ONE_SHOT_DISABLE; | |
baf8a94a MC |
9113 | tw32(MSGINT_MODE, val); |
9114 | } | |
9115 | ||
63c3a66f | 9116 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
9117 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); |
9118 | udelay(40); | |
9119 | } | |
9120 | ||
9121 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
9122 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
9123 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
9124 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
9125 | WDMAC_MODE_LNGREAD_ENAB); | |
9126 | ||
c5908939 MC |
9127 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
9128 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 9129 | if (tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 LT |
9130 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
9131 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
9132 | /* nothing */ | |
9133 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 9134 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
9135 | val |= WDMAC_MODE_RX_ACCEL; |
9136 | } | |
9137 | } | |
9138 | ||
d9ab5ad1 | 9139 | /* Enable host coalescing bug fix */ |
63c3a66f | 9140 | if (tg3_flag(tp, 5755_PLUS)) |
f51f3562 | 9141 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 9142 | |
788a035e MC |
9143 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
9144 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
9145 | ||
1da177e4 LT |
9146 | tw32_f(WDMAC_MODE, val); |
9147 | udelay(40); | |
9148 | ||
63c3a66f | 9149 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
9150 | u16 pcix_cmd; |
9151 | ||
9152 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
9153 | &pcix_cmd); | |
1da177e4 | 9154 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
9155 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
9156 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 9157 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
9158 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
9159 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 9160 | } |
9974a356 MC |
9161 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
9162 | pcix_cmd); | |
1da177e4 LT |
9163 | } |
9164 | ||
9165 | tw32_f(RDMAC_MODE, rdmac_mode); | |
9166 | udelay(40); | |
9167 | ||
9168 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
63c3a66f | 9169 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 | 9170 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); |
9936bcf6 MC |
9171 | |
9172 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
9173 | tw32(SNDDATAC_MODE, | |
9174 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
9175 | else | |
9176 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
9177 | ||
1da177e4 LT |
9178 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
9179 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 9180 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
63c3a66f | 9181 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
7cb32cf2 MC |
9182 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
9183 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 9184 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
63c3a66f JP |
9185 | if (tg3_flag(tp, HW_TSO_1) || |
9186 | tg3_flag(tp, HW_TSO_2) || | |
9187 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 | 9188 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); |
baf8a94a | 9189 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
63c3a66f | 9190 | if (tg3_flag(tp, ENABLE_TSS)) |
baf8a94a MC |
9191 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
9192 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
9193 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
9194 | ||
9195 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9196 | err = tg3_load_5701_a0_firmware_fix(tp); | |
9197 | if (err) | |
9198 | return err; | |
9199 | } | |
9200 | ||
63c3a66f | 9201 | if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
9202 | err = tg3_load_tso_firmware(tp); |
9203 | if (err) | |
9204 | return err; | |
9205 | } | |
1da177e4 LT |
9206 | |
9207 | tp->tx_mode = TX_MODE_ENABLE; | |
f2096f94 | 9208 | |
63c3a66f | 9209 | if (tg3_flag(tp, 5755_PLUS) || |
b1d05210 MC |
9210 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
9211 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
f2096f94 MC |
9212 | |
9213 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
9214 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
9215 | tp->tx_mode &= ~val; | |
9216 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
9217 | } | |
9218 | ||
1da177e4 LT |
9219 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
9220 | udelay(100); | |
9221 | ||
63c3a66f | 9222 | if (tg3_flag(tp, ENABLE_RSS)) { |
bcebcc46 | 9223 | tg3_rss_write_indir_tbl(tp); |
baf8a94a MC |
9224 | |
9225 | /* Setup the "secret" hash key. */ | |
9226 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
9227 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
9228 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
9229 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
9230 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
9231 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
9232 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
9233 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
9234 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
9235 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
9236 | } | |
9237 | ||
1da177e4 | 9238 | tp->rx_mode = RX_MODE_ENABLE; |
63c3a66f | 9239 | if (tg3_flag(tp, 5755_PLUS)) |
af36e6b6 MC |
9240 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
9241 | ||
63c3a66f | 9242 | if (tg3_flag(tp, ENABLE_RSS)) |
baf8a94a MC |
9243 | tp->rx_mode |= RX_MODE_RSS_ENABLE | |
9244 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
9245 | RX_MODE_RSS_IPV6_HASH_EN | | |
9246 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
9247 | RX_MODE_RSS_IPV4_HASH_EN | | |
9248 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
9249 | ||
1da177e4 LT |
9250 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
9251 | udelay(10); | |
9252 | ||
1da177e4 LT |
9253 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
9254 | ||
9255 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 9256 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
9257 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
9258 | udelay(10); | |
9259 | } | |
9260 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
9261 | udelay(10); | |
9262 | ||
f07e9af3 | 9263 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 9264 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 9265 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
9266 | /* Set drive transmission level to 1.2V */ |
9267 | /* only if the signal pre-emphasis bit is not set */ | |
9268 | val = tr32(MAC_SERDES_CFG); | |
9269 | val &= 0xfffff000; | |
9270 | val |= 0x880; | |
9271 | tw32(MAC_SERDES_CFG, val); | |
9272 | } | |
9273 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
9274 | tw32(MAC_SERDES_CFG, 0x616000); | |
9275 | } | |
9276 | ||
9277 | /* Prevent chip from dropping frames when flow control | |
9278 | * is enabled. | |
9279 | */ | |
55086ad9 | 9280 | if (tg3_flag(tp, 57765_CLASS)) |
666bc831 MC |
9281 | val = 1; |
9282 | else | |
9283 | val = 2; | |
9284 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
9285 | |
9286 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 9287 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 | 9288 | /* Use hardware link auto-negotiation */ |
63c3a66f | 9289 | tg3_flag_set(tp, HW_AUTONEG); |
1da177e4 LT |
9290 | } |
9291 | ||
f07e9af3 | 9292 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
6ff6f81d | 9293 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
d4d2c558 MC |
9294 | u32 tmp; |
9295 | ||
9296 | tmp = tr32(SERDES_RX_CTRL); | |
9297 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
9298 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
9299 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
9300 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
9301 | } | |
9302 | ||
63c3a66f | 9303 | if (!tg3_flag(tp, USE_PHYLIB)) { |
c6700ce2 | 9304 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
80096068 | 9305 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; |
1da177e4 | 9306 | |
dd477003 MC |
9307 | err = tg3_setup_phy(tp, 0); |
9308 | if (err) | |
9309 | return err; | |
1da177e4 | 9310 | |
f07e9af3 MC |
9311 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
9312 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
9313 | u32 tmp; |
9314 | ||
9315 | /* Clear CRC stats. */ | |
9316 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
9317 | tg3_writephy(tp, MII_TG3_TEST1, | |
9318 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9319 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 9320 | } |
1da177e4 LT |
9321 | } |
9322 | } | |
9323 | ||
9324 | __tg3_set_rx_mode(tp->dev); | |
9325 | ||
9326 | /* Initialize receive rules. */ | |
9327 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
9328 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
9329 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
9330 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
9331 | ||
63c3a66f | 9332 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) |
1da177e4 LT |
9333 | limit = 8; |
9334 | else | |
9335 | limit = 16; | |
63c3a66f | 9336 | if (tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
9337 | limit -= 4; |
9338 | switch (limit) { | |
9339 | case 16: | |
9340 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
9341 | case 15: | |
9342 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
9343 | case 14: | |
9344 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
9345 | case 13: | |
9346 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
9347 | case 12: | |
9348 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
9349 | case 11: | |
9350 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
9351 | case 10: | |
9352 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
9353 | case 9: | |
9354 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
9355 | case 8: | |
9356 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
9357 | case 7: | |
9358 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
9359 | case 6: | |
9360 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
9361 | case 5: | |
9362 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
9363 | case 4: | |
9364 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
9365 | case 3: | |
9366 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
9367 | case 2: | |
9368 | case 1: | |
9369 | ||
9370 | default: | |
9371 | break; | |
855e1111 | 9372 | } |
1da177e4 | 9373 | |
63c3a66f | 9374 | if (tg3_flag(tp, ENABLE_APE)) |
9ce768ea MC |
9375 | /* Write our heartbeat update interval to APE. */ |
9376 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
9377 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 9378 | |
1da177e4 LT |
9379 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
9380 | ||
1da177e4 LT |
9381 | return 0; |
9382 | } | |
9383 | ||
9384 | /* Called at device open time to get the chip ready for | |
9385 | * packet processing. Invoked with tp->lock held. | |
9386 | */ | |
8e7a22e3 | 9387 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 9388 | { |
1da177e4 LT |
9389 | tg3_switch_clocks(tp); |
9390 | ||
9391 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
9392 | ||
2f751b67 | 9393 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
9394 | } |
9395 | ||
9396 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
9397 | do { u32 __val = tr32(REG); \ | |
9398 | (PSTAT)->low += __val; \ | |
9399 | if ((PSTAT)->low < __val) \ | |
9400 | (PSTAT)->high += 1; \ | |
9401 | } while (0) | |
9402 | ||
9403 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
9404 | { | |
9405 | struct tg3_hw_stats *sp = tp->hw_stats; | |
9406 | ||
9407 | if (!netif_carrier_ok(tp->dev)) | |
9408 | return; | |
9409 | ||
9410 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
9411 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
9412 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
9413 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
9414 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
9415 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
9416 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
9417 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
9418 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
9419 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
9420 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
9421 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
9422 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
9423 | ||
9424 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
9425 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
9426 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
9427 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
9428 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
9429 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
9430 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
9431 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
9432 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
9433 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
9434 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
9435 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
9436 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
9437 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
9438 | |
9439 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
310050fa MC |
9440 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
9441 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && | |
9442 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { | |
4d958473 MC |
9443 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); |
9444 | } else { | |
9445 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
9446 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
9447 | if (val) { | |
9448 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
9449 | sp->rx_discards.low += val; | |
9450 | if (sp->rx_discards.low < val) | |
9451 | sp->rx_discards.high += 1; | |
9452 | } | |
9453 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
9454 | } | |
463d305b | 9455 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
1da177e4 LT |
9456 | } |
9457 | ||
0e6cf6a9 MC |
9458 | static void tg3_chk_missed_msi(struct tg3 *tp) |
9459 | { | |
9460 | u32 i; | |
9461 | ||
9462 | for (i = 0; i < tp->irq_cnt; i++) { | |
9463 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9464 | ||
9465 | if (tg3_has_work(tnapi)) { | |
9466 | if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && | |
9467 | tnapi->last_tx_cons == tnapi->tx_cons) { | |
9468 | if (tnapi->chk_msi_cnt < 1) { | |
9469 | tnapi->chk_msi_cnt++; | |
9470 | return; | |
9471 | } | |
7f230735 | 9472 | tg3_msi(0, tnapi); |
0e6cf6a9 MC |
9473 | } |
9474 | } | |
9475 | tnapi->chk_msi_cnt = 0; | |
9476 | tnapi->last_rx_cons = tnapi->rx_rcb_ptr; | |
9477 | tnapi->last_tx_cons = tnapi->tx_cons; | |
9478 | } | |
9479 | } | |
9480 | ||
1da177e4 LT |
9481 | static void tg3_timer(unsigned long __opaque) |
9482 | { | |
9483 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 9484 | |
5b190624 | 9485 | if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) |
f475f163 MC |
9486 | goto restart_timer; |
9487 | ||
f47c11ee | 9488 | spin_lock(&tp->lock); |
1da177e4 | 9489 | |
0e6cf6a9 | 9490 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
55086ad9 | 9491 | tg3_flag(tp, 57765_CLASS)) |
0e6cf6a9 MC |
9492 | tg3_chk_missed_msi(tp); |
9493 | ||
63c3a66f | 9494 | if (!tg3_flag(tp, TAGGED_STATUS)) { |
fac9b83e DM |
9495 | /* All of this garbage is because when using non-tagged |
9496 | * IRQ status the mailbox/status_block protocol the chip | |
9497 | * uses with the cpu is race prone. | |
9498 | */ | |
898a56f8 | 9499 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
9500 | tw32(GRC_LOCAL_CTRL, |
9501 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
9502 | } else { | |
9503 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 9504 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 9505 | } |
1da177e4 | 9506 | |
fac9b83e | 9507 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
f47c11ee | 9508 | spin_unlock(&tp->lock); |
db219973 | 9509 | tg3_reset_task_schedule(tp); |
5b190624 | 9510 | goto restart_timer; |
fac9b83e | 9511 | } |
1da177e4 LT |
9512 | } |
9513 | ||
1da177e4 LT |
9514 | /* This part only runs once per second. */ |
9515 | if (!--tp->timer_counter) { | |
63c3a66f | 9516 | if (tg3_flag(tp, 5705_PLUS)) |
fac9b83e DM |
9517 | tg3_periodic_fetch_stats(tp); |
9518 | ||
b0c5943f MC |
9519 | if (tp->setlpicnt && !--tp->setlpicnt) |
9520 | tg3_phy_eee_enable(tp); | |
52b02d04 | 9521 | |
63c3a66f | 9522 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
9523 | u32 mac_stat; |
9524 | int phy_event; | |
9525 | ||
9526 | mac_stat = tr32(MAC_STATUS); | |
9527 | ||
9528 | phy_event = 0; | |
f07e9af3 | 9529 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
9530 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
9531 | phy_event = 1; | |
9532 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
9533 | phy_event = 1; | |
9534 | ||
9535 | if (phy_event) | |
9536 | tg3_setup_phy(tp, 0); | |
63c3a66f | 9537 | } else if (tg3_flag(tp, POLL_SERDES)) { |
1da177e4 LT |
9538 | u32 mac_stat = tr32(MAC_STATUS); |
9539 | int need_setup = 0; | |
9540 | ||
9541 | if (netif_carrier_ok(tp->dev) && | |
9542 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
9543 | need_setup = 1; | |
9544 | } | |
be98da6a | 9545 | if (!netif_carrier_ok(tp->dev) && |
1da177e4 LT |
9546 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
9547 | MAC_STATUS_SIGNAL_DET))) { | |
9548 | need_setup = 1; | |
9549 | } | |
9550 | if (need_setup) { | |
3d3ebe74 MC |
9551 | if (!tp->serdes_counter) { |
9552 | tw32_f(MAC_MODE, | |
9553 | (tp->mac_mode & | |
9554 | ~MAC_MODE_PORT_MODE_MASK)); | |
9555 | udelay(40); | |
9556 | tw32_f(MAC_MODE, tp->mac_mode); | |
9557 | udelay(40); | |
9558 | } | |
1da177e4 LT |
9559 | tg3_setup_phy(tp, 0); |
9560 | } | |
f07e9af3 | 9561 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
63c3a66f | 9562 | tg3_flag(tp, 5780_CLASS)) { |
747e8f8b | 9563 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 9564 | } |
1da177e4 LT |
9565 | |
9566 | tp->timer_counter = tp->timer_multiplier; | |
9567 | } | |
9568 | ||
130b8e4d MC |
9569 | /* Heartbeat is only sent once every 2 seconds. |
9570 | * | |
9571 | * The heartbeat is to tell the ASF firmware that the host | |
9572 | * driver is still alive. In the event that the OS crashes, | |
9573 | * ASF needs to reset the hardware to free up the FIFO space | |
9574 | * that may be filled with rx packets destined for the host. | |
9575 | * If the FIFO is full, ASF will no longer function properly. | |
9576 | * | |
9577 | * Unintended resets have been reported on real time kernels | |
9578 | * where the timer doesn't run on time. Netpoll will also have | |
9579 | * same problem. | |
9580 | * | |
9581 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
9582 | * to check the ring condition when the heartbeat is expiring | |
9583 | * before doing the reset. This will prevent most unintended | |
9584 | * resets. | |
9585 | */ | |
1da177e4 | 9586 | if (!--tp->asf_counter) { |
63c3a66f | 9587 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
9588 | tg3_wait_for_event_ack(tp); |
9589 | ||
bbadf503 | 9590 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 9591 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 9592 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
9593 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
9594 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
9595 | |
9596 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
9597 | } |
9598 | tp->asf_counter = tp->asf_multiplier; | |
9599 | } | |
9600 | ||
f47c11ee | 9601 | spin_unlock(&tp->lock); |
1da177e4 | 9602 | |
f475f163 | 9603 | restart_timer: |
1da177e4 LT |
9604 | tp->timer.expires = jiffies + tp->timer_offset; |
9605 | add_timer(&tp->timer); | |
9606 | } | |
9607 | ||
21f7638e MC |
9608 | static void __devinit tg3_timer_init(struct tg3 *tp) |
9609 | { | |
9610 | if (tg3_flag(tp, TAGGED_STATUS) && | |
9611 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
9612 | !tg3_flag(tp, 57765_CLASS)) | |
9613 | tp->timer_offset = HZ; | |
9614 | else | |
9615 | tp->timer_offset = HZ / 10; | |
9616 | ||
9617 | BUG_ON(tp->timer_offset > HZ); | |
9618 | ||
9619 | tp->timer_multiplier = (HZ / tp->timer_offset); | |
9620 | tp->asf_multiplier = (HZ / tp->timer_offset) * | |
9621 | TG3_FW_UPDATE_FREQ_SEC; | |
9622 | ||
9623 | init_timer(&tp->timer); | |
9624 | tp->timer.data = (unsigned long) tp; | |
9625 | tp->timer.function = tg3_timer; | |
9626 | } | |
9627 | ||
9628 | static void tg3_timer_start(struct tg3 *tp) | |
9629 | { | |
9630 | tp->asf_counter = tp->asf_multiplier; | |
9631 | tp->timer_counter = tp->timer_multiplier; | |
9632 | ||
9633 | tp->timer.expires = jiffies + tp->timer_offset; | |
9634 | add_timer(&tp->timer); | |
9635 | } | |
9636 | ||
9637 | static void tg3_timer_stop(struct tg3 *tp) | |
9638 | { | |
9639 | del_timer_sync(&tp->timer); | |
9640 | } | |
9641 | ||
9642 | /* Restart hardware after configuration changes, self-test, etc. | |
9643 | * Invoked with tp->lock held. | |
9644 | */ | |
9645 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
9646 | __releases(tp->lock) | |
9647 | __acquires(tp->lock) | |
9648 | { | |
9649 | int err; | |
9650 | ||
9651 | err = tg3_init_hw(tp, reset_phy); | |
9652 | if (err) { | |
9653 | netdev_err(tp->dev, | |
9654 | "Failed to re-initialize device, aborting\n"); | |
9655 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9656 | tg3_full_unlock(tp); | |
9657 | tg3_timer_stop(tp); | |
9658 | tp->irq_sync = 0; | |
9659 | tg3_napi_enable(tp); | |
9660 | dev_close(tp->dev); | |
9661 | tg3_full_lock(tp, 0); | |
9662 | } | |
9663 | return err; | |
9664 | } | |
9665 | ||
9666 | static void tg3_reset_task(struct work_struct *work) | |
9667 | { | |
9668 | struct tg3 *tp = container_of(work, struct tg3, reset_task); | |
9669 | int err; | |
9670 | ||
9671 | tg3_full_lock(tp, 0); | |
9672 | ||
9673 | if (!netif_running(tp->dev)) { | |
9674 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
9675 | tg3_full_unlock(tp); | |
9676 | return; | |
9677 | } | |
9678 | ||
9679 | tg3_full_unlock(tp); | |
9680 | ||
9681 | tg3_phy_stop(tp); | |
9682 | ||
9683 | tg3_netif_stop(tp); | |
9684 | ||
9685 | tg3_full_lock(tp, 1); | |
9686 | ||
9687 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { | |
9688 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
9689 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
9690 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
9691 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | |
9692 | } | |
9693 | ||
9694 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
9695 | err = tg3_init_hw(tp, 1); | |
9696 | if (err) | |
9697 | goto out; | |
9698 | ||
9699 | tg3_netif_start(tp); | |
9700 | ||
9701 | out: | |
9702 | tg3_full_unlock(tp); | |
9703 | ||
9704 | if (!err) | |
9705 | tg3_phy_start(tp); | |
9706 | ||
9707 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
9708 | } | |
9709 | ||
4f125f42 | 9710 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 9711 | { |
7d12e780 | 9712 | irq_handler_t fn; |
fcfa0a32 | 9713 | unsigned long flags; |
4f125f42 MC |
9714 | char *name; |
9715 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
9716 | ||
9717 | if (tp->irq_cnt == 1) | |
9718 | name = tp->dev->name; | |
9719 | else { | |
9720 | name = &tnapi->irq_lbl[0]; | |
9721 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
9722 | name[IFNAMSIZ-1] = 0; | |
9723 | } | |
fcfa0a32 | 9724 | |
63c3a66f | 9725 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
fcfa0a32 | 9726 | fn = tg3_msi; |
63c3a66f | 9727 | if (tg3_flag(tp, 1SHOT_MSI)) |
fcfa0a32 | 9728 | fn = tg3_msi_1shot; |
ab392d2d | 9729 | flags = 0; |
fcfa0a32 MC |
9730 | } else { |
9731 | fn = tg3_interrupt; | |
63c3a66f | 9732 | if (tg3_flag(tp, TAGGED_STATUS)) |
fcfa0a32 | 9733 | fn = tg3_interrupt_tagged; |
ab392d2d | 9734 | flags = IRQF_SHARED; |
fcfa0a32 | 9735 | } |
4f125f42 MC |
9736 | |
9737 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
9738 | } |
9739 | ||
7938109f MC |
9740 | static int tg3_test_interrupt(struct tg3 *tp) |
9741 | { | |
09943a18 | 9742 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 9743 | struct net_device *dev = tp->dev; |
b16250e3 | 9744 | int err, i, intr_ok = 0; |
f6eb9b1f | 9745 | u32 val; |
7938109f | 9746 | |
d4bc3927 MC |
9747 | if (!netif_running(dev)) |
9748 | return -ENODEV; | |
9749 | ||
7938109f MC |
9750 | tg3_disable_ints(tp); |
9751 | ||
4f125f42 | 9752 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 9753 | |
f6eb9b1f MC |
9754 | /* |
9755 | * Turn off MSI one shot mode. Otherwise this test has no | |
9756 | * observable way to know whether the interrupt was delivered. | |
9757 | */ | |
3aa1cdf8 | 9758 | if (tg3_flag(tp, 57765_PLUS)) { |
f6eb9b1f MC |
9759 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; |
9760 | tw32(MSGINT_MODE, val); | |
9761 | } | |
9762 | ||
4f125f42 | 9763 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
f274fd9a | 9764 | IRQF_SHARED, dev->name, tnapi); |
7938109f MC |
9765 | if (err) |
9766 | return err; | |
9767 | ||
898a56f8 | 9768 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
9769 | tg3_enable_ints(tp); |
9770 | ||
9771 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 9772 | tnapi->coal_now); |
7938109f MC |
9773 | |
9774 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
9775 | u32 int_mbox, misc_host_ctrl; |
9776 | ||
898a56f8 | 9777 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
9778 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
9779 | ||
9780 | if ((int_mbox != 0) || | |
9781 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
9782 | intr_ok = 1; | |
7938109f | 9783 | break; |
b16250e3 MC |
9784 | } |
9785 | ||
3aa1cdf8 MC |
9786 | if (tg3_flag(tp, 57765_PLUS) && |
9787 | tnapi->hw_status->status_tag != tnapi->last_tag) | |
9788 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
9789 | ||
7938109f MC |
9790 | msleep(10); |
9791 | } | |
9792 | ||
9793 | tg3_disable_ints(tp); | |
9794 | ||
4f125f42 | 9795 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 9796 | |
4f125f42 | 9797 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9798 | |
9799 | if (err) | |
9800 | return err; | |
9801 | ||
f6eb9b1f MC |
9802 | if (intr_ok) { |
9803 | /* Reenable MSI one shot mode. */ | |
5b39de91 | 9804 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { |
f6eb9b1f MC |
9805 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; |
9806 | tw32(MSGINT_MODE, val); | |
9807 | } | |
7938109f | 9808 | return 0; |
f6eb9b1f | 9809 | } |
7938109f MC |
9810 | |
9811 | return -EIO; | |
9812 | } | |
9813 | ||
9814 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
9815 | * successfully restored | |
9816 | */ | |
9817 | static int tg3_test_msi(struct tg3 *tp) | |
9818 | { | |
7938109f MC |
9819 | int err; |
9820 | u16 pci_cmd; | |
9821 | ||
63c3a66f | 9822 | if (!tg3_flag(tp, USING_MSI)) |
7938109f MC |
9823 | return 0; |
9824 | ||
9825 | /* Turn off SERR reporting in case MSI terminates with Master | |
9826 | * Abort. | |
9827 | */ | |
9828 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
9829 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
9830 | pci_cmd & ~PCI_COMMAND_SERR); | |
9831 | ||
9832 | err = tg3_test_interrupt(tp); | |
9833 | ||
9834 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
9835 | ||
9836 | if (!err) | |
9837 | return 0; | |
9838 | ||
9839 | /* other failures */ | |
9840 | if (err != -EIO) | |
9841 | return err; | |
9842 | ||
9843 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
9844 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
9845 | "to INTx mode. Please report this failure to the PCI " | |
9846 | "maintainer and include system chipset information\n"); | |
7938109f | 9847 | |
4f125f42 | 9848 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 9849 | |
7938109f MC |
9850 | pci_disable_msi(tp->pdev); |
9851 | ||
63c3a66f | 9852 | tg3_flag_clear(tp, USING_MSI); |
dc8bf1b1 | 9853 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 9854 | |
4f125f42 | 9855 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9856 | if (err) |
9857 | return err; | |
9858 | ||
9859 | /* Need to reset the chip because the MSI cycle may have terminated | |
9860 | * with Master Abort. | |
9861 | */ | |
f47c11ee | 9862 | tg3_full_lock(tp, 1); |
7938109f | 9863 | |
944d980e | 9864 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 9865 | err = tg3_init_hw(tp, 1); |
7938109f | 9866 | |
f47c11ee | 9867 | tg3_full_unlock(tp); |
7938109f MC |
9868 | |
9869 | if (err) | |
4f125f42 | 9870 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
9871 | |
9872 | return err; | |
9873 | } | |
9874 | ||
9e9fd12d MC |
9875 | static int tg3_request_firmware(struct tg3 *tp) |
9876 | { | |
9877 | const __be32 *fw_data; | |
9878 | ||
9879 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
9880 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
9881 | tp->fw_needed); | |
9e9fd12d MC |
9882 | return -ENOENT; |
9883 | } | |
9884 | ||
9885 | fw_data = (void *)tp->fw->data; | |
9886 | ||
9887 | /* Firmware blob starts with version numbers, followed by | |
9888 | * start address and _full_ length including BSS sections | |
9889 | * (which must be longer than the actual data, of course | |
9890 | */ | |
9891 | ||
9892 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
9893 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
9894 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
9895 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
9896 | release_firmware(tp->fw); |
9897 | tp->fw = NULL; | |
9898 | return -EINVAL; | |
9899 | } | |
9900 | ||
9901 | /* We no longer need firmware; we have it. */ | |
9902 | tp->fw_needed = NULL; | |
9903 | return 0; | |
9904 | } | |
9905 | ||
679563f4 MC |
9906 | static bool tg3_enable_msix(struct tg3 *tp) |
9907 | { | |
c3b5003b | 9908 | int i, rc; |
679563f4 MC |
9909 | struct msix_entry msix_ent[tp->irq_max]; |
9910 | ||
c3b5003b MC |
9911 | tp->irq_cnt = num_online_cpus(); |
9912 | if (tp->irq_cnt > 1) { | |
9913 | /* We want as many rx rings enabled as there are cpus. | |
9914 | * In multiqueue MSI-X mode, the first MSI-X vector | |
9915 | * only deals with link interrupts, etc, so we add | |
9916 | * one to the number of vectors we are requesting. | |
9917 | */ | |
9918 | tp->irq_cnt = min_t(unsigned, tp->irq_cnt + 1, tp->irq_max); | |
9919 | } | |
679563f4 MC |
9920 | |
9921 | for (i = 0; i < tp->irq_max; i++) { | |
9922 | msix_ent[i].entry = i; | |
9923 | msix_ent[i].vector = 0; | |
9924 | } | |
9925 | ||
9926 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
9927 | if (rc < 0) { |
9928 | return false; | |
9929 | } else if (rc != 0) { | |
679563f4 MC |
9930 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
9931 | return false; | |
05dbe005 JP |
9932 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
9933 | tp->irq_cnt, rc); | |
679563f4 MC |
9934 | tp->irq_cnt = rc; |
9935 | } | |
9936 | ||
9937 | for (i = 0; i < tp->irq_max; i++) | |
9938 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9939 | ||
2ddaad39 BH |
9940 | netif_set_real_num_tx_queues(tp->dev, 1); |
9941 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9942 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9943 | pci_disable_msix(tp->pdev); | |
9944 | return false; | |
9945 | } | |
b92b9040 MC |
9946 | |
9947 | if (tp->irq_cnt > 1) { | |
63c3a66f | 9948 | tg3_flag_set(tp, ENABLE_RSS); |
d78b59f5 MC |
9949 | |
9950 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
9951 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
63c3a66f | 9952 | tg3_flag_set(tp, ENABLE_TSS); |
b92b9040 MC |
9953 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); |
9954 | } | |
9955 | } | |
2430b031 | 9956 | |
679563f4 MC |
9957 | return true; |
9958 | } | |
9959 | ||
07b0173c MC |
9960 | static void tg3_ints_init(struct tg3 *tp) |
9961 | { | |
63c3a66f JP |
9962 | if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && |
9963 | !tg3_flag(tp, TAGGED_STATUS)) { | |
07b0173c MC |
9964 | /* All MSI supporting chips should support tagged |
9965 | * status. Assert that this is the case. | |
9966 | */ | |
5129c3a3 MC |
9967 | netdev_warn(tp->dev, |
9968 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 9969 | goto defcfg; |
07b0173c | 9970 | } |
4f125f42 | 9971 | |
63c3a66f JP |
9972 | if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) |
9973 | tg3_flag_set(tp, USING_MSIX); | |
9974 | else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) | |
9975 | tg3_flag_set(tp, USING_MSI); | |
679563f4 | 9976 | |
63c3a66f | 9977 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
679563f4 | 9978 | u32 msi_mode = tr32(MSGINT_MODE); |
63c3a66f | 9979 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) |
baf8a94a | 9980 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
5b39de91 MC |
9981 | if (!tg3_flag(tp, 1SHOT_MSI)) |
9982 | msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE; | |
679563f4 MC |
9983 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
9984 | } | |
9985 | defcfg: | |
63c3a66f | 9986 | if (!tg3_flag(tp, USING_MSIX)) { |
679563f4 MC |
9987 | tp->irq_cnt = 1; |
9988 | tp->napi[0].irq_vec = tp->pdev->irq; | |
2ddaad39 | 9989 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 9990 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 9991 | } |
07b0173c MC |
9992 | } |
9993 | ||
9994 | static void tg3_ints_fini(struct tg3 *tp) | |
9995 | { | |
63c3a66f | 9996 | if (tg3_flag(tp, USING_MSIX)) |
679563f4 | 9997 | pci_disable_msix(tp->pdev); |
63c3a66f | 9998 | else if (tg3_flag(tp, USING_MSI)) |
679563f4 | 9999 | pci_disable_msi(tp->pdev); |
63c3a66f JP |
10000 | tg3_flag_clear(tp, USING_MSI); |
10001 | tg3_flag_clear(tp, USING_MSIX); | |
10002 | tg3_flag_clear(tp, ENABLE_RSS); | |
10003 | tg3_flag_clear(tp, ENABLE_TSS); | |
07b0173c MC |
10004 | } |
10005 | ||
1da177e4 LT |
10006 | static int tg3_open(struct net_device *dev) |
10007 | { | |
10008 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 10009 | int i, err; |
1da177e4 | 10010 | |
9e9fd12d MC |
10011 | if (tp->fw_needed) { |
10012 | err = tg3_request_firmware(tp); | |
10013 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
10014 | if (err) | |
10015 | return err; | |
10016 | } else if (err) { | |
05dbe005 | 10017 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
63c3a66f JP |
10018 | tg3_flag_clear(tp, TSO_CAPABLE); |
10019 | } else if (!tg3_flag(tp, TSO_CAPABLE)) { | |
05dbe005 | 10020 | netdev_notice(tp->dev, "TSO capability restored\n"); |
63c3a66f | 10021 | tg3_flag_set(tp, TSO_CAPABLE); |
9e9fd12d MC |
10022 | } |
10023 | } | |
10024 | ||
c49a1561 MC |
10025 | netif_carrier_off(tp->dev); |
10026 | ||
c866b7ea | 10027 | err = tg3_power_up(tp); |
2f751b67 | 10028 | if (err) |
bc1c7567 | 10029 | return err; |
2f751b67 MC |
10030 | |
10031 | tg3_full_lock(tp, 0); | |
bc1c7567 | 10032 | |
1da177e4 | 10033 | tg3_disable_ints(tp); |
63c3a66f | 10034 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 10035 | |
f47c11ee | 10036 | tg3_full_unlock(tp); |
1da177e4 | 10037 | |
679563f4 MC |
10038 | /* |
10039 | * Setup interrupts first so we know how | |
10040 | * many NAPI resources to allocate | |
10041 | */ | |
10042 | tg3_ints_init(tp); | |
10043 | ||
90415477 | 10044 | tg3_rss_check_indir_tbl(tp); |
bcebcc46 | 10045 | |
1da177e4 LT |
10046 | /* The placement of this call is tied |
10047 | * to the setup and use of Host TX descriptors. | |
10048 | */ | |
10049 | err = tg3_alloc_consistent(tp); | |
10050 | if (err) | |
679563f4 | 10051 | goto err_out1; |
88b06bc2 | 10052 | |
66cfd1bd MC |
10053 | tg3_napi_init(tp); |
10054 | ||
fed97810 | 10055 | tg3_napi_enable(tp); |
1da177e4 | 10056 | |
4f125f42 MC |
10057 | for (i = 0; i < tp->irq_cnt; i++) { |
10058 | struct tg3_napi *tnapi = &tp->napi[i]; | |
10059 | err = tg3_request_irq(tp, i); | |
10060 | if (err) { | |
5bc09186 MC |
10061 | for (i--; i >= 0; i--) { |
10062 | tnapi = &tp->napi[i]; | |
4f125f42 | 10063 | free_irq(tnapi->irq_vec, tnapi); |
5bc09186 MC |
10064 | } |
10065 | goto err_out2; | |
4f125f42 MC |
10066 | } |
10067 | } | |
1da177e4 | 10068 | |
f47c11ee | 10069 | tg3_full_lock(tp, 0); |
1da177e4 | 10070 | |
8e7a22e3 | 10071 | err = tg3_init_hw(tp, 1); |
1da177e4 | 10072 | if (err) { |
944d980e | 10073 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 10074 | tg3_free_rings(tp); |
1da177e4 LT |
10075 | } |
10076 | ||
f47c11ee | 10077 | tg3_full_unlock(tp); |
1da177e4 | 10078 | |
07b0173c | 10079 | if (err) |
679563f4 | 10080 | goto err_out3; |
1da177e4 | 10081 | |
63c3a66f | 10082 | if (tg3_flag(tp, USING_MSI)) { |
7938109f | 10083 | err = tg3_test_msi(tp); |
fac9b83e | 10084 | |
7938109f | 10085 | if (err) { |
f47c11ee | 10086 | tg3_full_lock(tp, 0); |
944d980e | 10087 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 10088 | tg3_free_rings(tp); |
f47c11ee | 10089 | tg3_full_unlock(tp); |
7938109f | 10090 | |
679563f4 | 10091 | goto err_out2; |
7938109f | 10092 | } |
fcfa0a32 | 10093 | |
63c3a66f | 10094 | if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f | 10095 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 10096 | |
f6eb9b1f MC |
10097 | tw32(PCIE_TRANSACTION_CFG, |
10098 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 10099 | } |
7938109f MC |
10100 | } |
10101 | ||
b02fd9e3 MC |
10102 | tg3_phy_start(tp); |
10103 | ||
f47c11ee | 10104 | tg3_full_lock(tp, 0); |
1da177e4 | 10105 | |
21f7638e | 10106 | tg3_timer_start(tp); |
63c3a66f | 10107 | tg3_flag_set(tp, INIT_COMPLETE); |
1da177e4 LT |
10108 | tg3_enable_ints(tp); |
10109 | ||
f47c11ee | 10110 | tg3_full_unlock(tp); |
1da177e4 | 10111 | |
fe5f5787 | 10112 | netif_tx_start_all_queues(dev); |
1da177e4 | 10113 | |
06c03c02 MB |
10114 | /* |
10115 | * Reset loopback feature if it was turned on while the device was down | |
10116 | * make sure that it's installed properly now. | |
10117 | */ | |
10118 | if (dev->features & NETIF_F_LOOPBACK) | |
10119 | tg3_set_loopback(dev, dev->features); | |
10120 | ||
1da177e4 | 10121 | return 0; |
07b0173c | 10122 | |
679563f4 | 10123 | err_out3: |
4f125f42 MC |
10124 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
10125 | struct tg3_napi *tnapi = &tp->napi[i]; | |
10126 | free_irq(tnapi->irq_vec, tnapi); | |
10127 | } | |
07b0173c | 10128 | |
679563f4 | 10129 | err_out2: |
fed97810 | 10130 | tg3_napi_disable(tp); |
66cfd1bd | 10131 | tg3_napi_fini(tp); |
07b0173c | 10132 | tg3_free_consistent(tp); |
679563f4 MC |
10133 | |
10134 | err_out1: | |
10135 | tg3_ints_fini(tp); | |
cd0d7228 MC |
10136 | tg3_frob_aux_power(tp, false); |
10137 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
07b0173c | 10138 | return err; |
1da177e4 LT |
10139 | } |
10140 | ||
1da177e4 LT |
10141 | static int tg3_close(struct net_device *dev) |
10142 | { | |
4f125f42 | 10143 | int i; |
1da177e4 LT |
10144 | struct tg3 *tp = netdev_priv(dev); |
10145 | ||
fed97810 | 10146 | tg3_napi_disable(tp); |
db219973 | 10147 | tg3_reset_task_cancel(tp); |
7faa006f | 10148 | |
fe5f5787 | 10149 | netif_tx_stop_all_queues(dev); |
1da177e4 | 10150 | |
21f7638e | 10151 | tg3_timer_stop(tp); |
1da177e4 | 10152 | |
24bb4fb6 MC |
10153 | tg3_phy_stop(tp); |
10154 | ||
f47c11ee | 10155 | tg3_full_lock(tp, 1); |
1da177e4 LT |
10156 | |
10157 | tg3_disable_ints(tp); | |
10158 | ||
944d980e | 10159 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 10160 | tg3_free_rings(tp); |
63c3a66f | 10161 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 10162 | |
f47c11ee | 10163 | tg3_full_unlock(tp); |
1da177e4 | 10164 | |
4f125f42 MC |
10165 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
10166 | struct tg3_napi *tnapi = &tp->napi[i]; | |
10167 | free_irq(tnapi->irq_vec, tnapi); | |
10168 | } | |
07b0173c MC |
10169 | |
10170 | tg3_ints_fini(tp); | |
1da177e4 | 10171 | |
92feeabf MC |
10172 | /* Clear stats across close / open calls */ |
10173 | memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev)); | |
10174 | memset(&tp->estats_prev, 0, sizeof(tp->estats_prev)); | |
1da177e4 | 10175 | |
66cfd1bd MC |
10176 | tg3_napi_fini(tp); |
10177 | ||
1da177e4 LT |
10178 | tg3_free_consistent(tp); |
10179 | ||
c866b7ea | 10180 | tg3_power_down(tp); |
bc1c7567 MC |
10181 | |
10182 | netif_carrier_off(tp->dev); | |
10183 | ||
1da177e4 LT |
10184 | return 0; |
10185 | } | |
10186 | ||
511d2224 | 10187 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
10188 | { |
10189 | return ((u64)val->high << 32) | ((u64)val->low); | |
10190 | } | |
10191 | ||
65ec698d | 10192 | static u64 tg3_calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
10193 | { |
10194 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
10195 | ||
f07e9af3 | 10196 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
10197 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
10198 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
10199 | u32 val; |
10200 | ||
569a5df8 MC |
10201 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
10202 | tg3_writephy(tp, MII_TG3_TEST1, | |
10203 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 10204 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
10205 | } else |
10206 | val = 0; | |
1da177e4 LT |
10207 | |
10208 | tp->phy_crc_errors += val; | |
10209 | ||
10210 | return tp->phy_crc_errors; | |
10211 | } | |
10212 | ||
10213 | return get_stat64(&hw_stats->rx_fcs_errors); | |
10214 | } | |
10215 | ||
10216 | #define ESTAT_ADD(member) \ | |
10217 | estats->member = old_estats->member + \ | |
511d2224 | 10218 | get_stat64(&hw_stats->member) |
1da177e4 | 10219 | |
65ec698d | 10220 | static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats) |
1da177e4 | 10221 | { |
1da177e4 LT |
10222 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; |
10223 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
10224 | ||
1da177e4 LT |
10225 | ESTAT_ADD(rx_octets); |
10226 | ESTAT_ADD(rx_fragments); | |
10227 | ESTAT_ADD(rx_ucast_packets); | |
10228 | ESTAT_ADD(rx_mcast_packets); | |
10229 | ESTAT_ADD(rx_bcast_packets); | |
10230 | ESTAT_ADD(rx_fcs_errors); | |
10231 | ESTAT_ADD(rx_align_errors); | |
10232 | ESTAT_ADD(rx_xon_pause_rcvd); | |
10233 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
10234 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
10235 | ESTAT_ADD(rx_xoff_entered); | |
10236 | ESTAT_ADD(rx_frame_too_long_errors); | |
10237 | ESTAT_ADD(rx_jabbers); | |
10238 | ESTAT_ADD(rx_undersize_packets); | |
10239 | ESTAT_ADD(rx_in_length_errors); | |
10240 | ESTAT_ADD(rx_out_length_errors); | |
10241 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
10242 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
10243 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
10244 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
10245 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
10246 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
10247 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
10248 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
10249 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
10250 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
10251 | ||
10252 | ESTAT_ADD(tx_octets); | |
10253 | ESTAT_ADD(tx_collisions); | |
10254 | ESTAT_ADD(tx_xon_sent); | |
10255 | ESTAT_ADD(tx_xoff_sent); | |
10256 | ESTAT_ADD(tx_flow_control); | |
10257 | ESTAT_ADD(tx_mac_errors); | |
10258 | ESTAT_ADD(tx_single_collisions); | |
10259 | ESTAT_ADD(tx_mult_collisions); | |
10260 | ESTAT_ADD(tx_deferred); | |
10261 | ESTAT_ADD(tx_excessive_collisions); | |
10262 | ESTAT_ADD(tx_late_collisions); | |
10263 | ESTAT_ADD(tx_collide_2times); | |
10264 | ESTAT_ADD(tx_collide_3times); | |
10265 | ESTAT_ADD(tx_collide_4times); | |
10266 | ESTAT_ADD(tx_collide_5times); | |
10267 | ESTAT_ADD(tx_collide_6times); | |
10268 | ESTAT_ADD(tx_collide_7times); | |
10269 | ESTAT_ADD(tx_collide_8times); | |
10270 | ESTAT_ADD(tx_collide_9times); | |
10271 | ESTAT_ADD(tx_collide_10times); | |
10272 | ESTAT_ADD(tx_collide_11times); | |
10273 | ESTAT_ADD(tx_collide_12times); | |
10274 | ESTAT_ADD(tx_collide_13times); | |
10275 | ESTAT_ADD(tx_collide_14times); | |
10276 | ESTAT_ADD(tx_collide_15times); | |
10277 | ESTAT_ADD(tx_ucast_packets); | |
10278 | ESTAT_ADD(tx_mcast_packets); | |
10279 | ESTAT_ADD(tx_bcast_packets); | |
10280 | ESTAT_ADD(tx_carrier_sense_errors); | |
10281 | ESTAT_ADD(tx_discards); | |
10282 | ESTAT_ADD(tx_errors); | |
10283 | ||
10284 | ESTAT_ADD(dma_writeq_full); | |
10285 | ESTAT_ADD(dma_write_prioq_full); | |
10286 | ESTAT_ADD(rxbds_empty); | |
10287 | ESTAT_ADD(rx_discards); | |
10288 | ESTAT_ADD(rx_errors); | |
10289 | ESTAT_ADD(rx_threshold_hit); | |
10290 | ||
10291 | ESTAT_ADD(dma_readq_full); | |
10292 | ESTAT_ADD(dma_read_prioq_full); | |
10293 | ESTAT_ADD(tx_comp_queue_full); | |
10294 | ||
10295 | ESTAT_ADD(ring_set_send_prod_index); | |
10296 | ESTAT_ADD(ring_status_update); | |
10297 | ESTAT_ADD(nic_irqs); | |
10298 | ESTAT_ADD(nic_avoided_irqs); | |
10299 | ESTAT_ADD(nic_tx_threshold_hit); | |
10300 | ||
4452d099 | 10301 | ESTAT_ADD(mbuf_lwm_thresh_hit); |
1da177e4 LT |
10302 | } |
10303 | ||
65ec698d | 10304 | static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats) |
1da177e4 | 10305 | { |
511d2224 | 10306 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
10307 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
10308 | ||
1da177e4 LT |
10309 | stats->rx_packets = old_stats->rx_packets + |
10310 | get_stat64(&hw_stats->rx_ucast_packets) + | |
10311 | get_stat64(&hw_stats->rx_mcast_packets) + | |
10312 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 10313 | |
1da177e4 LT |
10314 | stats->tx_packets = old_stats->tx_packets + |
10315 | get_stat64(&hw_stats->tx_ucast_packets) + | |
10316 | get_stat64(&hw_stats->tx_mcast_packets) + | |
10317 | get_stat64(&hw_stats->tx_bcast_packets); | |
10318 | ||
10319 | stats->rx_bytes = old_stats->rx_bytes + | |
10320 | get_stat64(&hw_stats->rx_octets); | |
10321 | stats->tx_bytes = old_stats->tx_bytes + | |
10322 | get_stat64(&hw_stats->tx_octets); | |
10323 | ||
10324 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 10325 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
10326 | stats->tx_errors = old_stats->tx_errors + |
10327 | get_stat64(&hw_stats->tx_errors) + | |
10328 | get_stat64(&hw_stats->tx_mac_errors) + | |
10329 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
10330 | get_stat64(&hw_stats->tx_discards); | |
10331 | ||
10332 | stats->multicast = old_stats->multicast + | |
10333 | get_stat64(&hw_stats->rx_mcast_packets); | |
10334 | stats->collisions = old_stats->collisions + | |
10335 | get_stat64(&hw_stats->tx_collisions); | |
10336 | ||
10337 | stats->rx_length_errors = old_stats->rx_length_errors + | |
10338 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
10339 | get_stat64(&hw_stats->rx_undersize_packets); | |
10340 | ||
10341 | stats->rx_over_errors = old_stats->rx_over_errors + | |
10342 | get_stat64(&hw_stats->rxbds_empty); | |
10343 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
10344 | get_stat64(&hw_stats->rx_align_errors); | |
10345 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
10346 | get_stat64(&hw_stats->tx_discards); | |
10347 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
10348 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
10349 | ||
10350 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
65ec698d | 10351 | tg3_calc_crc_errors(tp); |
1da177e4 | 10352 | |
4f63b877 JL |
10353 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
10354 | get_stat64(&hw_stats->rx_discards); | |
10355 | ||
b0057c51 | 10356 | stats->rx_dropped = tp->rx_dropped; |
48855432 | 10357 | stats->tx_dropped = tp->tx_dropped; |
1da177e4 LT |
10358 | } |
10359 | ||
1da177e4 LT |
10360 | static int tg3_get_regs_len(struct net_device *dev) |
10361 | { | |
97bd8e49 | 10362 | return TG3_REG_BLK_SIZE; |
1da177e4 LT |
10363 | } |
10364 | ||
10365 | static void tg3_get_regs(struct net_device *dev, | |
10366 | struct ethtool_regs *regs, void *_p) | |
10367 | { | |
1da177e4 | 10368 | struct tg3 *tp = netdev_priv(dev); |
1da177e4 LT |
10369 | |
10370 | regs->version = 0; | |
10371 | ||
97bd8e49 | 10372 | memset(_p, 0, TG3_REG_BLK_SIZE); |
1da177e4 | 10373 | |
80096068 | 10374 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10375 | return; |
10376 | ||
f47c11ee | 10377 | tg3_full_lock(tp, 0); |
1da177e4 | 10378 | |
97bd8e49 | 10379 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
1da177e4 | 10380 | |
f47c11ee | 10381 | tg3_full_unlock(tp); |
1da177e4 LT |
10382 | } |
10383 | ||
10384 | static int tg3_get_eeprom_len(struct net_device *dev) | |
10385 | { | |
10386 | struct tg3 *tp = netdev_priv(dev); | |
10387 | ||
10388 | return tp->nvram_size; | |
10389 | } | |
10390 | ||
1da177e4 LT |
10391 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
10392 | { | |
10393 | struct tg3 *tp = netdev_priv(dev); | |
10394 | int ret; | |
10395 | u8 *pd; | |
b9fc7dc5 | 10396 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 10397 | __be32 val; |
1da177e4 | 10398 | |
63c3a66f | 10399 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10400 | return -EINVAL; |
10401 | ||
80096068 | 10402 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10403 | return -EAGAIN; |
10404 | ||
1da177e4 LT |
10405 | offset = eeprom->offset; |
10406 | len = eeprom->len; | |
10407 | eeprom->len = 0; | |
10408 | ||
10409 | eeprom->magic = TG3_EEPROM_MAGIC; | |
10410 | ||
10411 | if (offset & 3) { | |
10412 | /* adjustments to start on required 4 byte boundary */ | |
10413 | b_offset = offset & 3; | |
10414 | b_count = 4 - b_offset; | |
10415 | if (b_count > len) { | |
10416 | /* i.e. offset=1 len=2 */ | |
10417 | b_count = len; | |
10418 | } | |
a9dc529d | 10419 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
10420 | if (ret) |
10421 | return ret; | |
be98da6a | 10422 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
10423 | len -= b_count; |
10424 | offset += b_count; | |
c6cdf436 | 10425 | eeprom->len += b_count; |
1da177e4 LT |
10426 | } |
10427 | ||
25985edc | 10428 | /* read bytes up to the last 4 byte boundary */ |
1da177e4 LT |
10429 | pd = &data[eeprom->len]; |
10430 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 10431 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
10432 | if (ret) { |
10433 | eeprom->len += i; | |
10434 | return ret; | |
10435 | } | |
1da177e4 LT |
10436 | memcpy(pd + i, &val, 4); |
10437 | } | |
10438 | eeprom->len += i; | |
10439 | ||
10440 | if (len & 3) { | |
10441 | /* read last bytes not ending on 4 byte boundary */ | |
10442 | pd = &data[eeprom->len]; | |
10443 | b_count = len & 3; | |
10444 | b_offset = offset + len - b_count; | |
a9dc529d | 10445 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
10446 | if (ret) |
10447 | return ret; | |
b9fc7dc5 | 10448 | memcpy(pd, &val, b_count); |
1da177e4 LT |
10449 | eeprom->len += b_count; |
10450 | } | |
10451 | return 0; | |
10452 | } | |
10453 | ||
1da177e4 LT |
10454 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
10455 | { | |
10456 | struct tg3 *tp = netdev_priv(dev); | |
10457 | int ret; | |
b9fc7dc5 | 10458 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 10459 | u8 *buf; |
a9dc529d | 10460 | __be32 start, end; |
1da177e4 | 10461 | |
80096068 | 10462 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10463 | return -EAGAIN; |
10464 | ||
63c3a66f | 10465 | if (tg3_flag(tp, NO_NVRAM) || |
df259d8c | 10466 | eeprom->magic != TG3_EEPROM_MAGIC) |
1da177e4 LT |
10467 | return -EINVAL; |
10468 | ||
10469 | offset = eeprom->offset; | |
10470 | len = eeprom->len; | |
10471 | ||
10472 | if ((b_offset = (offset & 3))) { | |
10473 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 10474 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
10475 | if (ret) |
10476 | return ret; | |
1da177e4 LT |
10477 | len += b_offset; |
10478 | offset &= ~3; | |
1c8594b4 MC |
10479 | if (len < 4) |
10480 | len = 4; | |
1da177e4 LT |
10481 | } |
10482 | ||
10483 | odd_len = 0; | |
1c8594b4 | 10484 | if (len & 3) { |
1da177e4 LT |
10485 | /* adjustments to end on required 4 byte boundary */ |
10486 | odd_len = 1; | |
10487 | len = (len + 3) & ~3; | |
a9dc529d | 10488 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
10489 | if (ret) |
10490 | return ret; | |
1da177e4 LT |
10491 | } |
10492 | ||
10493 | buf = data; | |
10494 | if (b_offset || odd_len) { | |
10495 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 10496 | if (!buf) |
1da177e4 LT |
10497 | return -ENOMEM; |
10498 | if (b_offset) | |
10499 | memcpy(buf, &start, 4); | |
10500 | if (odd_len) | |
10501 | memcpy(buf+len-4, &end, 4); | |
10502 | memcpy(buf + b_offset, data, eeprom->len); | |
10503 | } | |
10504 | ||
10505 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
10506 | ||
10507 | if (buf != data) | |
10508 | kfree(buf); | |
10509 | ||
10510 | return ret; | |
10511 | } | |
10512 | ||
10513 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
10514 | { | |
b02fd9e3 MC |
10515 | struct tg3 *tp = netdev_priv(dev); |
10516 | ||
63c3a66f | 10517 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10518 | struct phy_device *phydev; |
f07e9af3 | 10519 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10520 | return -EAGAIN; |
3f0e3ad7 MC |
10521 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10522 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 10523 | } |
6aa20a22 | 10524 | |
1da177e4 LT |
10525 | cmd->supported = (SUPPORTED_Autoneg); |
10526 | ||
f07e9af3 | 10527 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
10528 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
10529 | SUPPORTED_1000baseT_Full); | |
10530 | ||
f07e9af3 | 10531 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
10532 | cmd->supported |= (SUPPORTED_100baseT_Half | |
10533 | SUPPORTED_100baseT_Full | | |
10534 | SUPPORTED_10baseT_Half | | |
10535 | SUPPORTED_10baseT_Full | | |
3bebab59 | 10536 | SUPPORTED_TP); |
ef348144 KK |
10537 | cmd->port = PORT_TP; |
10538 | } else { | |
1da177e4 | 10539 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
10540 | cmd->port = PORT_FIBRE; |
10541 | } | |
6aa20a22 | 10542 | |
1da177e4 | 10543 | cmd->advertising = tp->link_config.advertising; |
5bb09778 MC |
10544 | if (tg3_flag(tp, PAUSE_AUTONEG)) { |
10545 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) { | |
10546 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10547 | cmd->advertising |= ADVERTISED_Pause; | |
10548 | } else { | |
10549 | cmd->advertising |= ADVERTISED_Pause | | |
10550 | ADVERTISED_Asym_Pause; | |
10551 | } | |
10552 | } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10553 | cmd->advertising |= ADVERTISED_Asym_Pause; | |
10554 | } | |
10555 | } | |
859edb26 | 10556 | if (netif_running(dev) && netif_carrier_ok(dev)) { |
70739497 | 10557 | ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); |
1da177e4 | 10558 | cmd->duplex = tp->link_config.active_duplex; |
859edb26 | 10559 | cmd->lp_advertising = tp->link_config.rmt_adv; |
e348c5e7 MC |
10560 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
10561 | if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) | |
10562 | cmd->eth_tp_mdix = ETH_TP_MDI_X; | |
10563 | else | |
10564 | cmd->eth_tp_mdix = ETH_TP_MDI; | |
10565 | } | |
64c22182 | 10566 | } else { |
e740522e MC |
10567 | ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); |
10568 | cmd->duplex = DUPLEX_UNKNOWN; | |
e348c5e7 | 10569 | cmd->eth_tp_mdix = ETH_TP_MDI_INVALID; |
1da177e4 | 10570 | } |
882e9793 | 10571 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 10572 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
10573 | cmd->autoneg = tp->link_config.autoneg; |
10574 | cmd->maxtxpkt = 0; | |
10575 | cmd->maxrxpkt = 0; | |
10576 | return 0; | |
10577 | } | |
6aa20a22 | 10578 | |
1da177e4 LT |
10579 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
10580 | { | |
10581 | struct tg3 *tp = netdev_priv(dev); | |
25db0338 | 10582 | u32 speed = ethtool_cmd_speed(cmd); |
6aa20a22 | 10583 | |
63c3a66f | 10584 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10585 | struct phy_device *phydev; |
f07e9af3 | 10586 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10587 | return -EAGAIN; |
3f0e3ad7 MC |
10588 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10589 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
10590 | } |
10591 | ||
7e5856bd MC |
10592 | if (cmd->autoneg != AUTONEG_ENABLE && |
10593 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 10594 | return -EINVAL; |
7e5856bd MC |
10595 | |
10596 | if (cmd->autoneg == AUTONEG_DISABLE && | |
10597 | cmd->duplex != DUPLEX_FULL && | |
10598 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 10599 | return -EINVAL; |
1da177e4 | 10600 | |
7e5856bd MC |
10601 | if (cmd->autoneg == AUTONEG_ENABLE) { |
10602 | u32 mask = ADVERTISED_Autoneg | | |
10603 | ADVERTISED_Pause | | |
10604 | ADVERTISED_Asym_Pause; | |
10605 | ||
f07e9af3 | 10606 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
10607 | mask |= ADVERTISED_1000baseT_Half | |
10608 | ADVERTISED_1000baseT_Full; | |
10609 | ||
f07e9af3 | 10610 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
10611 | mask |= ADVERTISED_100baseT_Half | |
10612 | ADVERTISED_100baseT_Full | | |
10613 | ADVERTISED_10baseT_Half | | |
10614 | ADVERTISED_10baseT_Full | | |
10615 | ADVERTISED_TP; | |
10616 | else | |
10617 | mask |= ADVERTISED_FIBRE; | |
10618 | ||
10619 | if (cmd->advertising & ~mask) | |
10620 | return -EINVAL; | |
10621 | ||
10622 | mask &= (ADVERTISED_1000baseT_Half | | |
10623 | ADVERTISED_1000baseT_Full | | |
10624 | ADVERTISED_100baseT_Half | | |
10625 | ADVERTISED_100baseT_Full | | |
10626 | ADVERTISED_10baseT_Half | | |
10627 | ADVERTISED_10baseT_Full); | |
10628 | ||
10629 | cmd->advertising &= mask; | |
10630 | } else { | |
f07e9af3 | 10631 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
25db0338 | 10632 | if (speed != SPEED_1000) |
7e5856bd MC |
10633 | return -EINVAL; |
10634 | ||
10635 | if (cmd->duplex != DUPLEX_FULL) | |
10636 | return -EINVAL; | |
10637 | } else { | |
25db0338 DD |
10638 | if (speed != SPEED_100 && |
10639 | speed != SPEED_10) | |
7e5856bd MC |
10640 | return -EINVAL; |
10641 | } | |
10642 | } | |
10643 | ||
f47c11ee | 10644 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10645 | |
10646 | tp->link_config.autoneg = cmd->autoneg; | |
10647 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
10648 | tp->link_config.advertising = (cmd->advertising | |
10649 | ADVERTISED_Autoneg); | |
e740522e MC |
10650 | tp->link_config.speed = SPEED_UNKNOWN; |
10651 | tp->link_config.duplex = DUPLEX_UNKNOWN; | |
1da177e4 LT |
10652 | } else { |
10653 | tp->link_config.advertising = 0; | |
25db0338 | 10654 | tp->link_config.speed = speed; |
1da177e4 | 10655 | tp->link_config.duplex = cmd->duplex; |
b02fd9e3 | 10656 | } |
6aa20a22 | 10657 | |
1da177e4 LT |
10658 | if (netif_running(dev)) |
10659 | tg3_setup_phy(tp, 1); | |
10660 | ||
f47c11ee | 10661 | tg3_full_unlock(tp); |
6aa20a22 | 10662 | |
1da177e4 LT |
10663 | return 0; |
10664 | } | |
6aa20a22 | 10665 | |
1da177e4 LT |
10666 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
10667 | { | |
10668 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10669 | |
68aad78c RJ |
10670 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
10671 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); | |
10672 | strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); | |
10673 | strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); | |
1da177e4 | 10674 | } |
6aa20a22 | 10675 | |
1da177e4 LT |
10676 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10677 | { | |
10678 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10679 | |
63c3a66f | 10680 | if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) |
a85feb8c GZ |
10681 | wol->supported = WAKE_MAGIC; |
10682 | else | |
10683 | wol->supported = 0; | |
1da177e4 | 10684 | wol->wolopts = 0; |
63c3a66f | 10685 | if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) |
1da177e4 LT |
10686 | wol->wolopts = WAKE_MAGIC; |
10687 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
10688 | } | |
6aa20a22 | 10689 | |
1da177e4 LT |
10690 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10691 | { | |
10692 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 10693 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 10694 | |
1da177e4 LT |
10695 | if (wol->wolopts & ~WAKE_MAGIC) |
10696 | return -EINVAL; | |
10697 | if ((wol->wolopts & WAKE_MAGIC) && | |
63c3a66f | 10698 | !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 10699 | return -EINVAL; |
6aa20a22 | 10700 | |
f2dc0d18 RW |
10701 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
10702 | ||
f47c11ee | 10703 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 10704 | if (device_may_wakeup(dp)) |
63c3a66f | 10705 | tg3_flag_set(tp, WOL_ENABLE); |
f2dc0d18 | 10706 | else |
63c3a66f | 10707 | tg3_flag_clear(tp, WOL_ENABLE); |
f47c11ee | 10708 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10709 | |
1da177e4 LT |
10710 | return 0; |
10711 | } | |
6aa20a22 | 10712 | |
1da177e4 LT |
10713 | static u32 tg3_get_msglevel(struct net_device *dev) |
10714 | { | |
10715 | struct tg3 *tp = netdev_priv(dev); | |
10716 | return tp->msg_enable; | |
10717 | } | |
6aa20a22 | 10718 | |
1da177e4 LT |
10719 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
10720 | { | |
10721 | struct tg3 *tp = netdev_priv(dev); | |
10722 | tp->msg_enable = value; | |
10723 | } | |
6aa20a22 | 10724 | |
1da177e4 LT |
10725 | static int tg3_nway_reset(struct net_device *dev) |
10726 | { | |
10727 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 10728 | int r; |
6aa20a22 | 10729 | |
1da177e4 LT |
10730 | if (!netif_running(dev)) |
10731 | return -EAGAIN; | |
10732 | ||
f07e9af3 | 10733 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
10734 | return -EINVAL; |
10735 | ||
63c3a66f | 10736 | if (tg3_flag(tp, USE_PHYLIB)) { |
f07e9af3 | 10737 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10738 | return -EAGAIN; |
3f0e3ad7 | 10739 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
10740 | } else { |
10741 | u32 bmcr; | |
10742 | ||
10743 | spin_lock_bh(&tp->lock); | |
10744 | r = -EINVAL; | |
10745 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10746 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10747 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 10748 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
10749 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
10750 | BMCR_ANENABLE); | |
10751 | r = 0; | |
10752 | } | |
10753 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 10754 | } |
6aa20a22 | 10755 | |
1da177e4 LT |
10756 | return r; |
10757 | } | |
6aa20a22 | 10758 | |
1da177e4 LT |
10759 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10760 | { | |
10761 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10762 | |
2c49a44d | 10763 | ering->rx_max_pending = tp->rx_std_ring_mask; |
63c3a66f | 10764 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
2c49a44d | 10765 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
10766 | else |
10767 | ering->rx_jumbo_max_pending = 0; | |
10768 | ||
10769 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
10770 | |
10771 | ering->rx_pending = tp->rx_pending; | |
63c3a66f | 10772 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
4f81c32b MC |
10773 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; |
10774 | else | |
10775 | ering->rx_jumbo_pending = 0; | |
10776 | ||
f3f3f27e | 10777 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 10778 | } |
6aa20a22 | 10779 | |
1da177e4 LT |
10780 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10781 | { | |
10782 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 10783 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 10784 | |
2c49a44d MC |
10785 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
10786 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
10787 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
10788 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
63c3a66f | 10789 | (tg3_flag(tp, TSO_BUG) && |
bc3a9254 | 10790 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 10791 | return -EINVAL; |
6aa20a22 | 10792 | |
bbe832c0 | 10793 | if (netif_running(dev)) { |
b02fd9e3 | 10794 | tg3_phy_stop(tp); |
1da177e4 | 10795 | tg3_netif_stop(tp); |
bbe832c0 MC |
10796 | irq_sync = 1; |
10797 | } | |
1da177e4 | 10798 | |
bbe832c0 | 10799 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 10800 | |
1da177e4 LT |
10801 | tp->rx_pending = ering->rx_pending; |
10802 | ||
63c3a66f | 10803 | if (tg3_flag(tp, MAX_RXPEND_64) && |
1da177e4 LT |
10804 | tp->rx_pending > 63) |
10805 | tp->rx_pending = 63; | |
10806 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 10807 | |
6fd45cb8 | 10808 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 10809 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
10810 | |
10811 | if (netif_running(dev)) { | |
944d980e | 10812 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
10813 | err = tg3_restart_hw(tp, 1); |
10814 | if (!err) | |
10815 | tg3_netif_start(tp); | |
1da177e4 LT |
10816 | } |
10817 | ||
f47c11ee | 10818 | tg3_full_unlock(tp); |
6aa20a22 | 10819 | |
b02fd9e3 MC |
10820 | if (irq_sync && !err) |
10821 | tg3_phy_start(tp); | |
10822 | ||
b9ec6c1b | 10823 | return err; |
1da177e4 | 10824 | } |
6aa20a22 | 10825 | |
1da177e4 LT |
10826 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10827 | { | |
10828 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10829 | |
63c3a66f | 10830 | epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); |
8d018621 | 10831 | |
4a2db503 | 10832 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
10833 | epause->rx_pause = 1; |
10834 | else | |
10835 | epause->rx_pause = 0; | |
10836 | ||
4a2db503 | 10837 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
10838 | epause->tx_pause = 1; |
10839 | else | |
10840 | epause->tx_pause = 0; | |
1da177e4 | 10841 | } |
6aa20a22 | 10842 | |
1da177e4 LT |
10843 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10844 | { | |
10845 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 10846 | int err = 0; |
6aa20a22 | 10847 | |
63c3a66f | 10848 | if (tg3_flag(tp, USE_PHYLIB)) { |
2712168f MC |
10849 | u32 newadv; |
10850 | struct phy_device *phydev; | |
1da177e4 | 10851 | |
2712168f | 10852 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 10853 | |
2712168f MC |
10854 | if (!(phydev->supported & SUPPORTED_Pause) || |
10855 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 10856 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 10857 | return -EINVAL; |
1da177e4 | 10858 | |
2712168f MC |
10859 | tp->link_config.flowctrl = 0; |
10860 | if (epause->rx_pause) { | |
10861 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10862 | ||
10863 | if (epause->tx_pause) { | |
10864 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10865 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 10866 | } else |
2712168f MC |
10867 | newadv = ADVERTISED_Pause | |
10868 | ADVERTISED_Asym_Pause; | |
10869 | } else if (epause->tx_pause) { | |
10870 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10871 | newadv = ADVERTISED_Asym_Pause; | |
10872 | } else | |
10873 | newadv = 0; | |
10874 | ||
10875 | if (epause->autoneg) | |
63c3a66f | 10876 | tg3_flag_set(tp, PAUSE_AUTONEG); |
2712168f | 10877 | else |
63c3a66f | 10878 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
2712168f | 10879 | |
f07e9af3 | 10880 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
10881 | u32 oldadv = phydev->advertising & |
10882 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10883 | if (oldadv != newadv) { | |
10884 | phydev->advertising &= | |
10885 | ~(ADVERTISED_Pause | | |
10886 | ADVERTISED_Asym_Pause); | |
10887 | phydev->advertising |= newadv; | |
10888 | if (phydev->autoneg) { | |
10889 | /* | |
10890 | * Always renegotiate the link to | |
10891 | * inform our link partner of our | |
10892 | * flow control settings, even if the | |
10893 | * flow control is forced. Let | |
10894 | * tg3_adjust_link() do the final | |
10895 | * flow control setup. | |
10896 | */ | |
10897 | return phy_start_aneg(phydev); | |
b02fd9e3 | 10898 | } |
b02fd9e3 | 10899 | } |
b02fd9e3 | 10900 | |
2712168f | 10901 | if (!epause->autoneg) |
b02fd9e3 | 10902 | tg3_setup_flow_control(tp, 0, 0); |
2712168f | 10903 | } else { |
c6700ce2 | 10904 | tp->link_config.advertising &= |
2712168f MC |
10905 | ~(ADVERTISED_Pause | |
10906 | ADVERTISED_Asym_Pause); | |
c6700ce2 | 10907 | tp->link_config.advertising |= newadv; |
b02fd9e3 MC |
10908 | } |
10909 | } else { | |
10910 | int irq_sync = 0; | |
10911 | ||
10912 | if (netif_running(dev)) { | |
10913 | tg3_netif_stop(tp); | |
10914 | irq_sync = 1; | |
10915 | } | |
10916 | ||
10917 | tg3_full_lock(tp, irq_sync); | |
10918 | ||
10919 | if (epause->autoneg) | |
63c3a66f | 10920 | tg3_flag_set(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10921 | else |
63c3a66f | 10922 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10923 | if (epause->rx_pause) |
e18ce346 | 10924 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 10925 | else |
e18ce346 | 10926 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 10927 | if (epause->tx_pause) |
e18ce346 | 10928 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 10929 | else |
e18ce346 | 10930 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
10931 | |
10932 | if (netif_running(dev)) { | |
10933 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10934 | err = tg3_restart_hw(tp, 1); | |
10935 | if (!err) | |
10936 | tg3_netif_start(tp); | |
10937 | } | |
10938 | ||
10939 | tg3_full_unlock(tp); | |
10940 | } | |
6aa20a22 | 10941 | |
b9ec6c1b | 10942 | return err; |
1da177e4 | 10943 | } |
6aa20a22 | 10944 | |
de6f31eb | 10945 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10946 | { |
b9f2c044 JG |
10947 | switch (sset) { |
10948 | case ETH_SS_TEST: | |
10949 | return TG3_NUM_TEST; | |
10950 | case ETH_SS_STATS: | |
10951 | return TG3_NUM_STATS; | |
10952 | default: | |
10953 | return -EOPNOTSUPP; | |
10954 | } | |
4cafd3f5 MC |
10955 | } |
10956 | ||
90415477 MC |
10957 | static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, |
10958 | u32 *rules __always_unused) | |
10959 | { | |
10960 | struct tg3 *tp = netdev_priv(dev); | |
10961 | ||
10962 | if (!tg3_flag(tp, SUPPORT_MSIX)) | |
10963 | return -EOPNOTSUPP; | |
10964 | ||
10965 | switch (info->cmd) { | |
10966 | case ETHTOOL_GRXRINGS: | |
10967 | if (netif_running(tp->dev)) | |
10968 | info->data = tp->irq_cnt; | |
10969 | else { | |
10970 | info->data = num_online_cpus(); | |
10971 | if (info->data > TG3_IRQ_MAX_VECS_RSS) | |
10972 | info->data = TG3_IRQ_MAX_VECS_RSS; | |
10973 | } | |
10974 | ||
10975 | /* The first interrupt vector only | |
10976 | * handles link interrupts. | |
10977 | */ | |
10978 | info->data -= 1; | |
10979 | return 0; | |
10980 | ||
10981 | default: | |
10982 | return -EOPNOTSUPP; | |
10983 | } | |
10984 | } | |
10985 | ||
10986 | static u32 tg3_get_rxfh_indir_size(struct net_device *dev) | |
10987 | { | |
10988 | u32 size = 0; | |
10989 | struct tg3 *tp = netdev_priv(dev); | |
10990 | ||
10991 | if (tg3_flag(tp, SUPPORT_MSIX)) | |
10992 | size = TG3_RSS_INDIR_TBL_SIZE; | |
10993 | ||
10994 | return size; | |
10995 | } | |
10996 | ||
10997 | static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir) | |
10998 | { | |
10999 | struct tg3 *tp = netdev_priv(dev); | |
11000 | int i; | |
11001 | ||
11002 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) | |
11003 | indir[i] = tp->rss_ind_tbl[i]; | |
11004 | ||
11005 | return 0; | |
11006 | } | |
11007 | ||
11008 | static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir) | |
11009 | { | |
11010 | struct tg3 *tp = netdev_priv(dev); | |
11011 | size_t i; | |
11012 | ||
11013 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) | |
11014 | tp->rss_ind_tbl[i] = indir[i]; | |
11015 | ||
11016 | if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) | |
11017 | return 0; | |
11018 | ||
11019 | /* It is legal to write the indirection | |
11020 | * table while the device is running. | |
11021 | */ | |
11022 | tg3_full_lock(tp, 0); | |
11023 | tg3_rss_write_indir_tbl(tp); | |
11024 | tg3_full_unlock(tp); | |
11025 | ||
11026 | return 0; | |
11027 | } | |
11028 | ||
de6f31eb | 11029 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
11030 | { |
11031 | switch (stringset) { | |
11032 | case ETH_SS_STATS: | |
11033 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
11034 | break; | |
4cafd3f5 MC |
11035 | case ETH_SS_TEST: |
11036 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
11037 | break; | |
1da177e4 LT |
11038 | default: |
11039 | WARN_ON(1); /* we need a WARN() */ | |
11040 | break; | |
11041 | } | |
11042 | } | |
11043 | ||
81b8709c | 11044 | static int tg3_set_phys_id(struct net_device *dev, |
11045 | enum ethtool_phys_id_state state) | |
4009a93d MC |
11046 | { |
11047 | struct tg3 *tp = netdev_priv(dev); | |
4009a93d MC |
11048 | |
11049 | if (!netif_running(tp->dev)) | |
11050 | return -EAGAIN; | |
11051 | ||
81b8709c | 11052 | switch (state) { |
11053 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 11054 | return 1; /* cycle on/off once per second */ |
4009a93d | 11055 | |
81b8709c | 11056 | case ETHTOOL_ID_ON: |
11057 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
11058 | LED_CTRL_1000MBPS_ON | | |
11059 | LED_CTRL_100MBPS_ON | | |
11060 | LED_CTRL_10MBPS_ON | | |
11061 | LED_CTRL_TRAFFIC_OVERRIDE | | |
11062 | LED_CTRL_TRAFFIC_BLINK | | |
11063 | LED_CTRL_TRAFFIC_LED); | |
11064 | break; | |
6aa20a22 | 11065 | |
81b8709c | 11066 | case ETHTOOL_ID_OFF: |
11067 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
11068 | LED_CTRL_TRAFFIC_OVERRIDE); | |
11069 | break; | |
4009a93d | 11070 | |
81b8709c | 11071 | case ETHTOOL_ID_INACTIVE: |
11072 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
11073 | break; | |
4009a93d | 11074 | } |
81b8709c | 11075 | |
4009a93d MC |
11076 | return 0; |
11077 | } | |
11078 | ||
de6f31eb | 11079 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
11080 | struct ethtool_stats *estats, u64 *tmp_stats) |
11081 | { | |
11082 | struct tg3 *tp = netdev_priv(dev); | |
0e6c9da3 | 11083 | |
b546e46f MC |
11084 | if (tp->hw_stats) |
11085 | tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); | |
11086 | else | |
11087 | memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats)); | |
1da177e4 LT |
11088 | } |
11089 | ||
535a490e | 11090 | static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen) |
c3e94500 MC |
11091 | { |
11092 | int i; | |
11093 | __be32 *buf; | |
11094 | u32 offset = 0, len = 0; | |
11095 | u32 magic, val; | |
11096 | ||
63c3a66f | 11097 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) |
c3e94500 MC |
11098 | return NULL; |
11099 | ||
11100 | if (magic == TG3_EEPROM_MAGIC) { | |
11101 | for (offset = TG3_NVM_DIR_START; | |
11102 | offset < TG3_NVM_DIR_END; | |
11103 | offset += TG3_NVM_DIRENT_SIZE) { | |
11104 | if (tg3_nvram_read(tp, offset, &val)) | |
11105 | return NULL; | |
11106 | ||
11107 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
11108 | TG3_NVM_DIRTYPE_EXTVPD) | |
11109 | break; | |
11110 | } | |
11111 | ||
11112 | if (offset != TG3_NVM_DIR_END) { | |
11113 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
11114 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
11115 | return NULL; | |
11116 | ||
11117 | offset = tg3_nvram_logical_addr(tp, offset); | |
11118 | } | |
11119 | } | |
11120 | ||
11121 | if (!offset || !len) { | |
11122 | offset = TG3_NVM_VPD_OFF; | |
11123 | len = TG3_NVM_VPD_LEN; | |
11124 | } | |
11125 | ||
11126 | buf = kmalloc(len, GFP_KERNEL); | |
11127 | if (buf == NULL) | |
11128 | return NULL; | |
11129 | ||
11130 | if (magic == TG3_EEPROM_MAGIC) { | |
11131 | for (i = 0; i < len; i += 4) { | |
11132 | /* The data is in little-endian format in NVRAM. | |
11133 | * Use the big-endian read routines to preserve | |
11134 | * the byte order as it exists in NVRAM. | |
11135 | */ | |
11136 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
11137 | goto error; | |
11138 | } | |
11139 | } else { | |
11140 | u8 *ptr; | |
11141 | ssize_t cnt; | |
11142 | unsigned int pos = 0; | |
11143 | ||
11144 | ptr = (u8 *)&buf[0]; | |
11145 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
11146 | cnt = pci_read_vpd(tp->pdev, pos, | |
11147 | len - pos, ptr); | |
11148 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
11149 | cnt = 0; | |
11150 | else if (cnt < 0) | |
11151 | goto error; | |
11152 | } | |
11153 | if (pos != len) | |
11154 | goto error; | |
11155 | } | |
11156 | ||
535a490e MC |
11157 | *vpdlen = len; |
11158 | ||
c3e94500 MC |
11159 | return buf; |
11160 | ||
11161 | error: | |
11162 | kfree(buf); | |
11163 | return NULL; | |
11164 | } | |
11165 | ||
566f86ad | 11166 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
11167 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
11168 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
11169 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
727a6d9f MC |
11170 | #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 |
11171 | #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 | |
bda18faf | 11172 | #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50 |
b16250e3 MC |
11173 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
11174 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
11175 | |
11176 | static int tg3_test_nvram(struct tg3 *tp) | |
11177 | { | |
535a490e | 11178 | u32 csum, magic, len; |
a9dc529d | 11179 | __be32 *buf; |
ab0049b4 | 11180 | int i, j, k, err = 0, size; |
566f86ad | 11181 | |
63c3a66f | 11182 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
11183 | return 0; |
11184 | ||
e4f34110 | 11185 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
11186 | return -EIO; |
11187 | ||
1b27777a MC |
11188 | if (magic == TG3_EEPROM_MAGIC) |
11189 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 11190 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
11191 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
11192 | TG3_EEPROM_SB_FORMAT_1) { | |
11193 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
11194 | case TG3_EEPROM_SB_REVISION_0: | |
11195 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
11196 | break; | |
11197 | case TG3_EEPROM_SB_REVISION_2: | |
11198 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
11199 | break; | |
11200 | case TG3_EEPROM_SB_REVISION_3: | |
11201 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
11202 | break; | |
727a6d9f MC |
11203 | case TG3_EEPROM_SB_REVISION_4: |
11204 | size = NVRAM_SELFBOOT_FORMAT1_4_SIZE; | |
11205 | break; | |
11206 | case TG3_EEPROM_SB_REVISION_5: | |
11207 | size = NVRAM_SELFBOOT_FORMAT1_5_SIZE; | |
11208 | break; | |
11209 | case TG3_EEPROM_SB_REVISION_6: | |
11210 | size = NVRAM_SELFBOOT_FORMAT1_6_SIZE; | |
11211 | break; | |
a5767dec | 11212 | default: |
727a6d9f | 11213 | return -EIO; |
a5767dec MC |
11214 | } |
11215 | } else | |
1b27777a | 11216 | return 0; |
b16250e3 MC |
11217 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
11218 | size = NVRAM_SELFBOOT_HW_SIZE; | |
11219 | else | |
1b27777a MC |
11220 | return -EIO; |
11221 | ||
11222 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
11223 | if (buf == NULL) |
11224 | return -ENOMEM; | |
11225 | ||
1b27777a MC |
11226 | err = -EIO; |
11227 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
11228 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
11229 | if (err) | |
566f86ad | 11230 | break; |
566f86ad | 11231 | } |
1b27777a | 11232 | if (i < size) |
566f86ad MC |
11233 | goto out; |
11234 | ||
1b27777a | 11235 | /* Selfboot format */ |
a9dc529d | 11236 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 11237 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 11238 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
11239 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
11240 | ||
b9fc7dc5 | 11241 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
11242 | TG3_EEPROM_SB_REVISION_2) { |
11243 | /* For rev 2, the csum doesn't include the MBA. */ | |
11244 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
11245 | csum8 += buf8[i]; | |
11246 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
11247 | csum8 += buf8[i]; | |
11248 | } else { | |
11249 | for (i = 0; i < size; i++) | |
11250 | csum8 += buf8[i]; | |
11251 | } | |
1b27777a | 11252 | |
ad96b485 AB |
11253 | if (csum8 == 0) { |
11254 | err = 0; | |
11255 | goto out; | |
11256 | } | |
11257 | ||
11258 | err = -EIO; | |
11259 | goto out; | |
1b27777a | 11260 | } |
566f86ad | 11261 | |
b9fc7dc5 | 11262 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
11263 | TG3_EEPROM_MAGIC_HW) { |
11264 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 11265 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 11266 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
11267 | |
11268 | /* Separate the parity bits and the data bytes. */ | |
11269 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
11270 | if ((i == 0) || (i == 8)) { | |
11271 | int l; | |
11272 | u8 msk; | |
11273 | ||
11274 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
11275 | parity[k++] = buf8[i] & msk; | |
11276 | i++; | |
859a5887 | 11277 | } else if (i == 16) { |
b16250e3 MC |
11278 | int l; |
11279 | u8 msk; | |
11280 | ||
11281 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
11282 | parity[k++] = buf8[i] & msk; | |
11283 | i++; | |
11284 | ||
11285 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
11286 | parity[k++] = buf8[i] & msk; | |
11287 | i++; | |
11288 | } | |
11289 | data[j++] = buf8[i]; | |
11290 | } | |
11291 | ||
11292 | err = -EIO; | |
11293 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
11294 | u8 hw8 = hweight8(data[i]); | |
11295 | ||
11296 | if ((hw8 & 0x1) && parity[i]) | |
11297 | goto out; | |
11298 | else if (!(hw8 & 0x1) && !parity[i]) | |
11299 | goto out; | |
11300 | } | |
11301 | err = 0; | |
11302 | goto out; | |
11303 | } | |
11304 | ||
01c3a392 MC |
11305 | err = -EIO; |
11306 | ||
566f86ad MC |
11307 | /* Bootstrap checksum at offset 0x10 */ |
11308 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 11309 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
11310 | goto out; |
11311 | ||
11312 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
11313 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 11314 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 11315 | goto out; |
566f86ad | 11316 | |
c3e94500 MC |
11317 | kfree(buf); |
11318 | ||
535a490e | 11319 | buf = tg3_vpd_readblock(tp, &len); |
c3e94500 MC |
11320 | if (!buf) |
11321 | return -ENOMEM; | |
d4894f3e | 11322 | |
535a490e | 11323 | i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA); |
d4894f3e MC |
11324 | if (i > 0) { |
11325 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
11326 | if (j < 0) | |
11327 | goto out; | |
11328 | ||
535a490e | 11329 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > len) |
d4894f3e MC |
11330 | goto out; |
11331 | ||
11332 | i += PCI_VPD_LRDT_TAG_SIZE; | |
11333 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
11334 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
11335 | if (j > 0) { | |
11336 | u8 csum8 = 0; | |
11337 | ||
11338 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11339 | ||
11340 | for (i = 0; i <= j; i++) | |
11341 | csum8 += ((u8 *)buf)[i]; | |
11342 | ||
11343 | if (csum8) | |
11344 | goto out; | |
11345 | } | |
11346 | } | |
11347 | ||
566f86ad MC |
11348 | err = 0; |
11349 | ||
11350 | out: | |
11351 | kfree(buf); | |
11352 | return err; | |
11353 | } | |
11354 | ||
ca43007a MC |
11355 | #define TG3_SERDES_TIMEOUT_SEC 2 |
11356 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
11357 | ||
11358 | static int tg3_test_link(struct tg3 *tp) | |
11359 | { | |
11360 | int i, max; | |
11361 | ||
11362 | if (!netif_running(tp->dev)) | |
11363 | return -ENODEV; | |
11364 | ||
f07e9af3 | 11365 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
11366 | max = TG3_SERDES_TIMEOUT_SEC; |
11367 | else | |
11368 | max = TG3_COPPER_TIMEOUT_SEC; | |
11369 | ||
11370 | for (i = 0; i < max; i++) { | |
11371 | if (netif_carrier_ok(tp->dev)) | |
11372 | return 0; | |
11373 | ||
11374 | if (msleep_interruptible(1000)) | |
11375 | break; | |
11376 | } | |
11377 | ||
11378 | return -EIO; | |
11379 | } | |
11380 | ||
a71116d1 | 11381 | /* Only test the commonly used registers */ |
30ca3e37 | 11382 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 11383 | { |
b16250e3 | 11384 | int i, is_5705, is_5750; |
a71116d1 MC |
11385 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
11386 | static struct { | |
11387 | u16 offset; | |
11388 | u16 flags; | |
11389 | #define TG3_FL_5705 0x1 | |
11390 | #define TG3_FL_NOT_5705 0x2 | |
11391 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 11392 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
11393 | u32 read_mask; |
11394 | u32 write_mask; | |
11395 | } reg_tbl[] = { | |
11396 | /* MAC Control Registers */ | |
11397 | { MAC_MODE, TG3_FL_NOT_5705, | |
11398 | 0x00000000, 0x00ef6f8c }, | |
11399 | { MAC_MODE, TG3_FL_5705, | |
11400 | 0x00000000, 0x01ef6b8c }, | |
11401 | { MAC_STATUS, TG3_FL_NOT_5705, | |
11402 | 0x03800107, 0x00000000 }, | |
11403 | { MAC_STATUS, TG3_FL_5705, | |
11404 | 0x03800100, 0x00000000 }, | |
11405 | { MAC_ADDR_0_HIGH, 0x0000, | |
11406 | 0x00000000, 0x0000ffff }, | |
11407 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 11408 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
11409 | { MAC_RX_MTU_SIZE, 0x0000, |
11410 | 0x00000000, 0x0000ffff }, | |
11411 | { MAC_TX_MODE, 0x0000, | |
11412 | 0x00000000, 0x00000070 }, | |
11413 | { MAC_TX_LENGTHS, 0x0000, | |
11414 | 0x00000000, 0x00003fff }, | |
11415 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
11416 | 0x00000000, 0x000007fc }, | |
11417 | { MAC_RX_MODE, TG3_FL_5705, | |
11418 | 0x00000000, 0x000007dc }, | |
11419 | { MAC_HASH_REG_0, 0x0000, | |
11420 | 0x00000000, 0xffffffff }, | |
11421 | { MAC_HASH_REG_1, 0x0000, | |
11422 | 0x00000000, 0xffffffff }, | |
11423 | { MAC_HASH_REG_2, 0x0000, | |
11424 | 0x00000000, 0xffffffff }, | |
11425 | { MAC_HASH_REG_3, 0x0000, | |
11426 | 0x00000000, 0xffffffff }, | |
11427 | ||
11428 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
11429 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
11430 | 0x00000000, 0xffffffff }, | |
11431 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
11432 | 0x00000000, 0xffffffff }, | |
11433 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
11434 | 0x00000000, 0x00000003 }, | |
11435 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
11436 | 0x00000000, 0xffffffff }, | |
11437 | { RCVDBDI_STD_BD+0, 0x0000, | |
11438 | 0x00000000, 0xffffffff }, | |
11439 | { RCVDBDI_STD_BD+4, 0x0000, | |
11440 | 0x00000000, 0xffffffff }, | |
11441 | { RCVDBDI_STD_BD+8, 0x0000, | |
11442 | 0x00000000, 0xffff0002 }, | |
11443 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
11444 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 11445 | |
a71116d1 MC |
11446 | /* Receive BD Initiator Control Registers. */ |
11447 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
11448 | 0x00000000, 0xffffffff }, | |
11449 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
11450 | 0x00000000, 0x000003ff }, | |
11451 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
11452 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 11453 | |
a71116d1 MC |
11454 | /* Host Coalescing Control Registers. */ |
11455 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
11456 | 0x00000000, 0x00000004 }, | |
11457 | { HOSTCC_MODE, TG3_FL_5705, | |
11458 | 0x00000000, 0x000000f6 }, | |
11459 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
11460 | 0x00000000, 0xffffffff }, | |
11461 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
11462 | 0x00000000, 0x000003ff }, | |
11463 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
11464 | 0x00000000, 0xffffffff }, | |
11465 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
11466 | 0x00000000, 0x000003ff }, | |
11467 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
11468 | 0x00000000, 0xffffffff }, | |
11469 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11470 | 0x00000000, 0x000000ff }, | |
11471 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
11472 | 0x00000000, 0xffffffff }, | |
11473 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11474 | 0x00000000, 0x000000ff }, | |
11475 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
11476 | 0x00000000, 0xffffffff }, | |
11477 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
11478 | 0x00000000, 0xffffffff }, | |
11479 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
11480 | 0x00000000, 0xffffffff }, | |
11481 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11482 | 0x00000000, 0x000000ff }, | |
11483 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
11484 | 0x00000000, 0xffffffff }, | |
11485 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11486 | 0x00000000, 0x000000ff }, | |
11487 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
11488 | 0x00000000, 0xffffffff }, | |
11489 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
11490 | 0x00000000, 0xffffffff }, | |
11491 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
11492 | 0x00000000, 0xffffffff }, | |
11493 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
11494 | 0x00000000, 0xffffffff }, | |
11495 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
11496 | 0x00000000, 0xffffffff }, | |
11497 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
11498 | 0xffffffff, 0x00000000 }, | |
11499 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
11500 | 0xffffffff, 0x00000000 }, | |
11501 | ||
11502 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 11503 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 11504 | 0x00000000, 0x007fff80 }, |
b16250e3 | 11505 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
11506 | 0x00000000, 0x007fffff }, |
11507 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
11508 | 0x00000000, 0x0000003f }, | |
11509 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
11510 | 0x00000000, 0x000001ff }, | |
11511 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
11512 | 0x00000000, 0x000001ff }, | |
11513 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
11514 | 0xffffffff, 0x00000000 }, | |
11515 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
11516 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 11517 | |
a71116d1 MC |
11518 | /* Mailbox Registers */ |
11519 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
11520 | 0x00000000, 0x000001ff }, | |
11521 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
11522 | 0x00000000, 0x000001ff }, | |
11523 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
11524 | 0x00000000, 0x000007ff }, | |
11525 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
11526 | 0x00000000, 0x000001ff }, | |
11527 | ||
11528 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
11529 | }; | |
11530 | ||
b16250e3 | 11531 | is_5705 = is_5750 = 0; |
63c3a66f | 11532 | if (tg3_flag(tp, 5705_PLUS)) { |
a71116d1 | 11533 | is_5705 = 1; |
63c3a66f | 11534 | if (tg3_flag(tp, 5750_PLUS)) |
b16250e3 MC |
11535 | is_5750 = 1; |
11536 | } | |
a71116d1 MC |
11537 | |
11538 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
11539 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
11540 | continue; | |
11541 | ||
11542 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
11543 | continue; | |
11544 | ||
63c3a66f | 11545 | if (tg3_flag(tp, IS_5788) && |
a71116d1 MC |
11546 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) |
11547 | continue; | |
11548 | ||
b16250e3 MC |
11549 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
11550 | continue; | |
11551 | ||
a71116d1 MC |
11552 | offset = (u32) reg_tbl[i].offset; |
11553 | read_mask = reg_tbl[i].read_mask; | |
11554 | write_mask = reg_tbl[i].write_mask; | |
11555 | ||
11556 | /* Save the original register content */ | |
11557 | save_val = tr32(offset); | |
11558 | ||
11559 | /* Determine the read-only value. */ | |
11560 | read_val = save_val & read_mask; | |
11561 | ||
11562 | /* Write zero to the register, then make sure the read-only bits | |
11563 | * are not changed and the read/write bits are all zeros. | |
11564 | */ | |
11565 | tw32(offset, 0); | |
11566 | ||
11567 | val = tr32(offset); | |
11568 | ||
11569 | /* Test the read-only and read/write bits. */ | |
11570 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
11571 | goto out; | |
11572 | ||
11573 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
11574 | * make sure the read-only bits are not changed and the | |
11575 | * read/write bits are all ones. | |
11576 | */ | |
11577 | tw32(offset, read_mask | write_mask); | |
11578 | ||
11579 | val = tr32(offset); | |
11580 | ||
11581 | /* Test the read-only bits. */ | |
11582 | if ((val & read_mask) != read_val) | |
11583 | goto out; | |
11584 | ||
11585 | /* Test the read/write bits. */ | |
11586 | if ((val & write_mask) != write_mask) | |
11587 | goto out; | |
11588 | ||
11589 | tw32(offset, save_val); | |
11590 | } | |
11591 | ||
11592 | return 0; | |
11593 | ||
11594 | out: | |
9f88f29f | 11595 | if (netif_msg_hw(tp)) |
2445e461 MC |
11596 | netdev_err(tp->dev, |
11597 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
11598 | tw32(offset, save_val); |
11599 | return -EIO; | |
11600 | } | |
11601 | ||
7942e1db MC |
11602 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
11603 | { | |
f71e1309 | 11604 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
11605 | int i; |
11606 | u32 j; | |
11607 | ||
e9edda69 | 11608 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
11609 | for (j = 0; j < len; j += 4) { |
11610 | u32 val; | |
11611 | ||
11612 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
11613 | tg3_read_mem(tp, offset + j, &val); | |
11614 | if (val != test_pattern[i]) | |
11615 | return -EIO; | |
11616 | } | |
11617 | } | |
11618 | return 0; | |
11619 | } | |
11620 | ||
11621 | static int tg3_test_memory(struct tg3 *tp) | |
11622 | { | |
11623 | static struct mem_entry { | |
11624 | u32 offset; | |
11625 | u32 len; | |
11626 | } mem_tbl_570x[] = { | |
38690194 | 11627 | { 0x00000000, 0x00b50}, |
7942e1db MC |
11628 | { 0x00002000, 0x1c000}, |
11629 | { 0xffffffff, 0x00000} | |
11630 | }, mem_tbl_5705[] = { | |
11631 | { 0x00000100, 0x0000c}, | |
11632 | { 0x00000200, 0x00008}, | |
7942e1db MC |
11633 | { 0x00004000, 0x00800}, |
11634 | { 0x00006000, 0x01000}, | |
11635 | { 0x00008000, 0x02000}, | |
11636 | { 0x00010000, 0x0e000}, | |
11637 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
11638 | }, mem_tbl_5755[] = { |
11639 | { 0x00000200, 0x00008}, | |
11640 | { 0x00004000, 0x00800}, | |
11641 | { 0x00006000, 0x00800}, | |
11642 | { 0x00008000, 0x02000}, | |
11643 | { 0x00010000, 0x0c000}, | |
11644 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
11645 | }, mem_tbl_5906[] = { |
11646 | { 0x00000200, 0x00008}, | |
11647 | { 0x00004000, 0x00400}, | |
11648 | { 0x00006000, 0x00400}, | |
11649 | { 0x00008000, 0x01000}, | |
11650 | { 0x00010000, 0x01000}, | |
11651 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
11652 | }, mem_tbl_5717[] = { |
11653 | { 0x00000200, 0x00008}, | |
11654 | { 0x00010000, 0x0a000}, | |
11655 | { 0x00020000, 0x13c00}, | |
11656 | { 0xffffffff, 0x00000} | |
11657 | }, mem_tbl_57765[] = { | |
11658 | { 0x00000200, 0x00008}, | |
11659 | { 0x00004000, 0x00800}, | |
11660 | { 0x00006000, 0x09800}, | |
11661 | { 0x00010000, 0x0a000}, | |
11662 | { 0xffffffff, 0x00000} | |
7942e1db MC |
11663 | }; |
11664 | struct mem_entry *mem_tbl; | |
11665 | int err = 0; | |
11666 | int i; | |
11667 | ||
63c3a66f | 11668 | if (tg3_flag(tp, 5717_PLUS)) |
8b5a6c42 | 11669 | mem_tbl = mem_tbl_5717; |
55086ad9 | 11670 | else if (tg3_flag(tp, 57765_CLASS)) |
8b5a6c42 | 11671 | mem_tbl = mem_tbl_57765; |
63c3a66f | 11672 | else if (tg3_flag(tp, 5755_PLUS)) |
321d32a0 MC |
11673 | mem_tbl = mem_tbl_5755; |
11674 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11675 | mem_tbl = mem_tbl_5906; | |
63c3a66f | 11676 | else if (tg3_flag(tp, 5705_PLUS)) |
321d32a0 MC |
11677 | mem_tbl = mem_tbl_5705; |
11678 | else | |
7942e1db MC |
11679 | mem_tbl = mem_tbl_570x; |
11680 | ||
11681 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
11682 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
11683 | if (err) | |
7942e1db MC |
11684 | break; |
11685 | } | |
6aa20a22 | 11686 | |
7942e1db MC |
11687 | return err; |
11688 | } | |
11689 | ||
bb158d69 MC |
11690 | #define TG3_TSO_MSS 500 |
11691 | ||
11692 | #define TG3_TSO_IP_HDR_LEN 20 | |
11693 | #define TG3_TSO_TCP_HDR_LEN 20 | |
11694 | #define TG3_TSO_TCP_OPT_LEN 12 | |
11695 | ||
11696 | static const u8 tg3_tso_header[] = { | |
11697 | 0x08, 0x00, | |
11698 | 0x45, 0x00, 0x00, 0x00, | |
11699 | 0x00, 0x00, 0x40, 0x00, | |
11700 | 0x40, 0x06, 0x00, 0x00, | |
11701 | 0x0a, 0x00, 0x00, 0x01, | |
11702 | 0x0a, 0x00, 0x00, 0x02, | |
11703 | 0x0d, 0x00, 0xe0, 0x00, | |
11704 | 0x00, 0x00, 0x01, 0x00, | |
11705 | 0x00, 0x00, 0x02, 0x00, | |
11706 | 0x80, 0x10, 0x10, 0x00, | |
11707 | 0x14, 0x09, 0x00, 0x00, | |
11708 | 0x01, 0x01, 0x08, 0x0a, | |
11709 | 0x11, 0x11, 0x11, 0x11, | |
11710 | 0x11, 0x11, 0x11, 0x11, | |
11711 | }; | |
9f40dead | 11712 | |
28a45957 | 11713 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) |
c76949a6 | 11714 | { |
5e5a7f37 | 11715 | u32 rx_start_idx, rx_idx, tx_idx, opaque_key; |
bb158d69 | 11716 | u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; |
84b67b27 | 11717 | u32 budget; |
9205fd9c ED |
11718 | struct sk_buff *skb; |
11719 | u8 *tx_data, *rx_data; | |
c76949a6 MC |
11720 | dma_addr_t map; |
11721 | int num_pkts, tx_len, rx_len, i, err; | |
11722 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 11723 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 11724 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 11725 | |
c8873405 MC |
11726 | tnapi = &tp->napi[0]; |
11727 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 11728 | if (tp->irq_cnt > 1) { |
63c3a66f | 11729 | if (tg3_flag(tp, ENABLE_RSS)) |
1da85aa3 | 11730 | rnapi = &tp->napi[1]; |
63c3a66f | 11731 | if (tg3_flag(tp, ENABLE_TSS)) |
c8873405 | 11732 | tnapi = &tp->napi[1]; |
0c1d0e2b | 11733 | } |
fd2ce37f | 11734 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 11735 | |
c76949a6 MC |
11736 | err = -EIO; |
11737 | ||
4852a861 | 11738 | tx_len = pktsz; |
a20e9c62 | 11739 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
11740 | if (!skb) |
11741 | return -ENOMEM; | |
11742 | ||
c76949a6 MC |
11743 | tx_data = skb_put(skb, tx_len); |
11744 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
11745 | memset(tx_data + 6, 0x0, 8); | |
11746 | ||
4852a861 | 11747 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
c76949a6 | 11748 | |
28a45957 | 11749 | if (tso_loopback) { |
bb158d69 MC |
11750 | struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN]; |
11751 | ||
11752 | u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN + | |
11753 | TG3_TSO_TCP_OPT_LEN; | |
11754 | ||
11755 | memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header, | |
11756 | sizeof(tg3_tso_header)); | |
11757 | mss = TG3_TSO_MSS; | |
11758 | ||
11759 | val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); | |
11760 | num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); | |
11761 | ||
11762 | /* Set the total length field in the IP header */ | |
11763 | iph->tot_len = htons((u16)(mss + hdr_len)); | |
11764 | ||
11765 | base_flags = (TXD_FLAG_CPU_PRE_DMA | | |
11766 | TXD_FLAG_CPU_POST_DMA); | |
11767 | ||
63c3a66f JP |
11768 | if (tg3_flag(tp, HW_TSO_1) || |
11769 | tg3_flag(tp, HW_TSO_2) || | |
11770 | tg3_flag(tp, HW_TSO_3)) { | |
bb158d69 MC |
11771 | struct tcphdr *th; |
11772 | val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; | |
11773 | th = (struct tcphdr *)&tx_data[val]; | |
11774 | th->check = 0; | |
11775 | } else | |
11776 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
11777 | ||
63c3a66f | 11778 | if (tg3_flag(tp, HW_TSO_3)) { |
bb158d69 MC |
11779 | mss |= (hdr_len & 0xc) << 12; |
11780 | if (hdr_len & 0x10) | |
11781 | base_flags |= 0x00000010; | |
11782 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 11783 | } else if (tg3_flag(tp, HW_TSO_2)) |
bb158d69 | 11784 | mss |= hdr_len << 9; |
63c3a66f | 11785 | else if (tg3_flag(tp, HW_TSO_1) || |
bb158d69 MC |
11786 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
11787 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); | |
11788 | } else { | |
11789 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); | |
11790 | } | |
11791 | ||
11792 | data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header); | |
11793 | } else { | |
11794 | num_pkts = 1; | |
11795 | data_off = ETH_HLEN; | |
c441b456 MC |
11796 | |
11797 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && | |
11798 | tx_len > VLAN_ETH_FRAME_LEN) | |
11799 | base_flags |= TXD_FLAG_JMB_PKT; | |
bb158d69 MC |
11800 | } |
11801 | ||
11802 | for (i = data_off; i < tx_len; i++) | |
c76949a6 MC |
11803 | tx_data[i] = (u8) (i & 0xff); |
11804 | ||
f4188d8a AD |
11805 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
11806 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
11807 | dev_kfree_skb(skb); |
11808 | return -EIO; | |
11809 | } | |
c76949a6 | 11810 | |
0d681b27 MC |
11811 | val = tnapi->tx_prod; |
11812 | tnapi->tx_buffers[val].skb = skb; | |
11813 | dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); | |
11814 | ||
c76949a6 | 11815 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11816 | rnapi->coal_now); |
c76949a6 MC |
11817 | |
11818 | udelay(10); | |
11819 | ||
898a56f8 | 11820 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 11821 | |
84b67b27 MC |
11822 | budget = tg3_tx_avail(tnapi); |
11823 | if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len, | |
d1a3b737 MC |
11824 | base_flags | TXD_FLAG_END, mss, 0)) { |
11825 | tnapi->tx_buffers[val].skb = NULL; | |
11826 | dev_kfree_skb(skb); | |
11827 | return -EIO; | |
11828 | } | |
c76949a6 | 11829 | |
f3f3f27e | 11830 | tnapi->tx_prod++; |
c76949a6 | 11831 | |
6541b806 MC |
11832 | /* Sync BD data before updating mailbox */ |
11833 | wmb(); | |
11834 | ||
f3f3f27e MC |
11835 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
11836 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
11837 | |
11838 | udelay(10); | |
11839 | ||
303fc921 MC |
11840 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
11841 | for (i = 0; i < 35; i++) { | |
c76949a6 | 11842 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11843 | coal_now); |
c76949a6 MC |
11844 | |
11845 | udelay(10); | |
11846 | ||
898a56f8 MC |
11847 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
11848 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 11849 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
11850 | (rx_idx == (rx_start_idx + num_pkts))) |
11851 | break; | |
11852 | } | |
11853 | ||
ba1142e4 | 11854 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); |
c76949a6 MC |
11855 | dev_kfree_skb(skb); |
11856 | ||
f3f3f27e | 11857 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
11858 | goto out; |
11859 | ||
11860 | if (rx_idx != rx_start_idx + num_pkts) | |
11861 | goto out; | |
11862 | ||
bb158d69 MC |
11863 | val = data_off; |
11864 | while (rx_idx != rx_start_idx) { | |
11865 | desc = &rnapi->rx_rcb[rx_start_idx++]; | |
11866 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
11867 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
c76949a6 | 11868 | |
bb158d69 MC |
11869 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && |
11870 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
11871 | goto out; | |
c76949a6 | 11872 | |
bb158d69 MC |
11873 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) |
11874 | - ETH_FCS_LEN; | |
c76949a6 | 11875 | |
28a45957 | 11876 | if (!tso_loopback) { |
bb158d69 MC |
11877 | if (rx_len != tx_len) |
11878 | goto out; | |
4852a861 | 11879 | |
bb158d69 MC |
11880 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
11881 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
11882 | goto out; | |
11883 | } else { | |
11884 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
11885 | goto out; | |
11886 | } | |
11887 | } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
11888 | (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
54e0a67f | 11889 | >> RXD_TCPCSUM_SHIFT != 0xffff) { |
4852a861 | 11890 | goto out; |
bb158d69 | 11891 | } |
4852a861 | 11892 | |
bb158d69 | 11893 | if (opaque_key == RXD_OPAQUE_RING_STD) { |
9205fd9c | 11894 | rx_data = tpr->rx_std_buffers[desc_idx].data; |
bb158d69 MC |
11895 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], |
11896 | mapping); | |
11897 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
9205fd9c | 11898 | rx_data = tpr->rx_jmb_buffers[desc_idx].data; |
bb158d69 MC |
11899 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], |
11900 | mapping); | |
11901 | } else | |
11902 | goto out; | |
c76949a6 | 11903 | |
bb158d69 MC |
11904 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, |
11905 | PCI_DMA_FROMDEVICE); | |
c76949a6 | 11906 | |
9205fd9c | 11907 | rx_data += TG3_RX_OFFSET(tp); |
bb158d69 | 11908 | for (i = data_off; i < rx_len; i++, val++) { |
9205fd9c | 11909 | if (*(rx_data + i) != (u8) (val & 0xff)) |
bb158d69 MC |
11910 | goto out; |
11911 | } | |
c76949a6 | 11912 | } |
bb158d69 | 11913 | |
c76949a6 | 11914 | err = 0; |
6aa20a22 | 11915 | |
9205fd9c | 11916 | /* tg3_free_rings will unmap and free the rx_data */ |
c76949a6 MC |
11917 | out: |
11918 | return err; | |
11919 | } | |
11920 | ||
00c266b7 MC |
11921 | #define TG3_STD_LOOPBACK_FAILED 1 |
11922 | #define TG3_JMB_LOOPBACK_FAILED 2 | |
bb158d69 | 11923 | #define TG3_TSO_LOOPBACK_FAILED 4 |
28a45957 MC |
11924 | #define TG3_LOOPBACK_FAILED \ |
11925 | (TG3_STD_LOOPBACK_FAILED | \ | |
11926 | TG3_JMB_LOOPBACK_FAILED | \ | |
11927 | TG3_TSO_LOOPBACK_FAILED) | |
00c266b7 | 11928 | |
941ec90f | 11929 | static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) |
9f40dead | 11930 | { |
28a45957 | 11931 | int err = -EIO; |
2215e24c | 11932 | u32 eee_cap; |
c441b456 MC |
11933 | u32 jmb_pkt_sz = 9000; |
11934 | ||
11935 | if (tp->dma_limit) | |
11936 | jmb_pkt_sz = tp->dma_limit - ETH_HLEN; | |
9f40dead | 11937 | |
ab789046 MC |
11938 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
11939 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
11940 | ||
28a45957 MC |
11941 | if (!netif_running(tp->dev)) { |
11942 | data[0] = TG3_LOOPBACK_FAILED; | |
11943 | data[1] = TG3_LOOPBACK_FAILED; | |
941ec90f MC |
11944 | if (do_extlpbk) |
11945 | data[2] = TG3_LOOPBACK_FAILED; | |
28a45957 MC |
11946 | goto done; |
11947 | } | |
11948 | ||
b9ec6c1b | 11949 | err = tg3_reset_hw(tp, 1); |
ab789046 | 11950 | if (err) { |
28a45957 MC |
11951 | data[0] = TG3_LOOPBACK_FAILED; |
11952 | data[1] = TG3_LOOPBACK_FAILED; | |
941ec90f MC |
11953 | if (do_extlpbk) |
11954 | data[2] = TG3_LOOPBACK_FAILED; | |
ab789046 MC |
11955 | goto done; |
11956 | } | |
9f40dead | 11957 | |
63c3a66f | 11958 | if (tg3_flag(tp, ENABLE_RSS)) { |
4a85f098 MC |
11959 | int i; |
11960 | ||
11961 | /* Reroute all rx packets to the 1st queue */ | |
11962 | for (i = MAC_RSS_INDIR_TBL_0; | |
11963 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
11964 | tw32(i, 0x0); | |
11965 | } | |
11966 | ||
6e01b20b MC |
11967 | /* HW errata - mac loopback fails in some cases on 5780. |
11968 | * Normal traffic and PHY loopback are not affected by | |
11969 | * errata. Also, the MAC loopback test is deprecated for | |
11970 | * all newer ASIC revisions. | |
11971 | */ | |
11972 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
11973 | !tg3_flag(tp, CPMU_PRESENT)) { | |
11974 | tg3_mac_loopback(tp, true); | |
9936bcf6 | 11975 | |
28a45957 MC |
11976 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
11977 | data[0] |= TG3_STD_LOOPBACK_FAILED; | |
6e01b20b MC |
11978 | |
11979 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
c441b456 | 11980 | tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) |
28a45957 | 11981 | data[0] |= TG3_JMB_LOOPBACK_FAILED; |
6e01b20b MC |
11982 | |
11983 | tg3_mac_loopback(tp, false); | |
11984 | } | |
4852a861 | 11985 | |
f07e9af3 | 11986 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
63c3a66f | 11987 | !tg3_flag(tp, USE_PHYLIB)) { |
5e5a7f37 MC |
11988 | int i; |
11989 | ||
941ec90f | 11990 | tg3_phy_lpbk_set(tp, 0, false); |
5e5a7f37 MC |
11991 | |
11992 | /* Wait for link */ | |
11993 | for (i = 0; i < 100; i++) { | |
11994 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
11995 | break; | |
11996 | mdelay(1); | |
11997 | } | |
11998 | ||
28a45957 MC |
11999 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
12000 | data[1] |= TG3_STD_LOOPBACK_FAILED; | |
63c3a66f | 12001 | if (tg3_flag(tp, TSO_CAPABLE) && |
28a45957 MC |
12002 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) |
12003 | data[1] |= TG3_TSO_LOOPBACK_FAILED; | |
63c3a66f | 12004 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
c441b456 | 12005 | tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) |
28a45957 | 12006 | data[1] |= TG3_JMB_LOOPBACK_FAILED; |
9f40dead | 12007 | |
941ec90f MC |
12008 | if (do_extlpbk) { |
12009 | tg3_phy_lpbk_set(tp, 0, true); | |
12010 | ||
12011 | /* All link indications report up, but the hardware | |
12012 | * isn't really ready for about 20 msec. Double it | |
12013 | * to be sure. | |
12014 | */ | |
12015 | mdelay(40); | |
12016 | ||
12017 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) | |
12018 | data[2] |= TG3_STD_LOOPBACK_FAILED; | |
12019 | if (tg3_flag(tp, TSO_CAPABLE) && | |
12020 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) | |
12021 | data[2] |= TG3_TSO_LOOPBACK_FAILED; | |
12022 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
c441b456 | 12023 | tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) |
941ec90f MC |
12024 | data[2] |= TG3_JMB_LOOPBACK_FAILED; |
12025 | } | |
12026 | ||
5e5a7f37 MC |
12027 | /* Re-enable gphy autopowerdown. */ |
12028 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) | |
12029 | tg3_phy_toggle_apd(tp, true); | |
12030 | } | |
6833c043 | 12031 | |
941ec90f | 12032 | err = (data[0] | data[1] | data[2]) ? -EIO : 0; |
28a45957 | 12033 | |
ab789046 MC |
12034 | done: |
12035 | tp->phy_flags |= eee_cap; | |
12036 | ||
9f40dead MC |
12037 | return err; |
12038 | } | |
12039 | ||
4cafd3f5 MC |
12040 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
12041 | u64 *data) | |
12042 | { | |
566f86ad | 12043 | struct tg3 *tp = netdev_priv(dev); |
941ec90f | 12044 | bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; |
566f86ad | 12045 | |
bed9829f MC |
12046 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && |
12047 | tg3_power_up(tp)) { | |
12048 | etest->flags |= ETH_TEST_FL_FAILED; | |
12049 | memset(data, 1, sizeof(u64) * TG3_NUM_TEST); | |
12050 | return; | |
12051 | } | |
bc1c7567 | 12052 | |
566f86ad MC |
12053 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
12054 | ||
12055 | if (tg3_test_nvram(tp) != 0) { | |
12056 | etest->flags |= ETH_TEST_FL_FAILED; | |
12057 | data[0] = 1; | |
12058 | } | |
941ec90f | 12059 | if (!doextlpbk && tg3_test_link(tp)) { |
ca43007a MC |
12060 | etest->flags |= ETH_TEST_FL_FAILED; |
12061 | data[1] = 1; | |
12062 | } | |
a71116d1 | 12063 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 12064 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
12065 | |
12066 | if (netif_running(dev)) { | |
b02fd9e3 | 12067 | tg3_phy_stop(tp); |
a71116d1 | 12068 | tg3_netif_stop(tp); |
bbe832c0 MC |
12069 | irq_sync = 1; |
12070 | } | |
a71116d1 | 12071 | |
bbe832c0 | 12072 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
12073 | |
12074 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 12075 | err = tg3_nvram_lock(tp); |
a71116d1 | 12076 | tg3_halt_cpu(tp, RX_CPU_BASE); |
63c3a66f | 12077 | if (!tg3_flag(tp, 5705_PLUS)) |
a71116d1 | 12078 | tg3_halt_cpu(tp, TX_CPU_BASE); |
ec41c7df MC |
12079 | if (!err) |
12080 | tg3_nvram_unlock(tp); | |
a71116d1 | 12081 | |
f07e9af3 | 12082 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
12083 | tg3_phy_reset(tp); |
12084 | ||
a71116d1 MC |
12085 | if (tg3_test_registers(tp) != 0) { |
12086 | etest->flags |= ETH_TEST_FL_FAILED; | |
12087 | data[2] = 1; | |
12088 | } | |
28a45957 | 12089 | |
7942e1db MC |
12090 | if (tg3_test_memory(tp) != 0) { |
12091 | etest->flags |= ETH_TEST_FL_FAILED; | |
12092 | data[3] = 1; | |
12093 | } | |
28a45957 | 12094 | |
941ec90f MC |
12095 | if (doextlpbk) |
12096 | etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; | |
12097 | ||
12098 | if (tg3_test_loopback(tp, &data[4], doextlpbk)) | |
c76949a6 | 12099 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 12100 | |
f47c11ee DM |
12101 | tg3_full_unlock(tp); |
12102 | ||
d4bc3927 MC |
12103 | if (tg3_test_interrupt(tp) != 0) { |
12104 | etest->flags |= ETH_TEST_FL_FAILED; | |
941ec90f | 12105 | data[7] = 1; |
d4bc3927 | 12106 | } |
f47c11ee DM |
12107 | |
12108 | tg3_full_lock(tp, 0); | |
d4bc3927 | 12109 | |
a71116d1 MC |
12110 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
12111 | if (netif_running(dev)) { | |
63c3a66f | 12112 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
12113 | err2 = tg3_restart_hw(tp, 1); |
12114 | if (!err2) | |
b9ec6c1b | 12115 | tg3_netif_start(tp); |
a71116d1 | 12116 | } |
f47c11ee DM |
12117 | |
12118 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
12119 | |
12120 | if (irq_sync && !err2) | |
12121 | tg3_phy_start(tp); | |
a71116d1 | 12122 | } |
80096068 | 12123 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 12124 | tg3_power_down(tp); |
bc1c7567 | 12125 | |
4cafd3f5 MC |
12126 | } |
12127 | ||
1da177e4 LT |
12128 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
12129 | { | |
12130 | struct mii_ioctl_data *data = if_mii(ifr); | |
12131 | struct tg3 *tp = netdev_priv(dev); | |
12132 | int err; | |
12133 | ||
63c3a66f | 12134 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 12135 | struct phy_device *phydev; |
f07e9af3 | 12136 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 12137 | return -EAGAIN; |
3f0e3ad7 | 12138 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 12139 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
12140 | } |
12141 | ||
33f401ae | 12142 | switch (cmd) { |
1da177e4 | 12143 | case SIOCGMIIPHY: |
882e9793 | 12144 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
12145 | |
12146 | /* fallthru */ | |
12147 | case SIOCGMIIREG: { | |
12148 | u32 mii_regval; | |
12149 | ||
f07e9af3 | 12150 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
12151 | break; /* We have no PHY */ |
12152 | ||
34eea5ac | 12153 | if (!netif_running(dev)) |
bc1c7567 MC |
12154 | return -EAGAIN; |
12155 | ||
f47c11ee | 12156 | spin_lock_bh(&tp->lock); |
1da177e4 | 12157 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 12158 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
12159 | |
12160 | data->val_out = mii_regval; | |
12161 | ||
12162 | return err; | |
12163 | } | |
12164 | ||
12165 | case SIOCSMIIREG: | |
f07e9af3 | 12166 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
12167 | break; /* We have no PHY */ |
12168 | ||
34eea5ac | 12169 | if (!netif_running(dev)) |
bc1c7567 MC |
12170 | return -EAGAIN; |
12171 | ||
f47c11ee | 12172 | spin_lock_bh(&tp->lock); |
1da177e4 | 12173 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 12174 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
12175 | |
12176 | return err; | |
12177 | ||
12178 | default: | |
12179 | /* do nothing */ | |
12180 | break; | |
12181 | } | |
12182 | return -EOPNOTSUPP; | |
12183 | } | |
12184 | ||
15f9850d DM |
12185 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
12186 | { | |
12187 | struct tg3 *tp = netdev_priv(dev); | |
12188 | ||
12189 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
12190 | return 0; | |
12191 | } | |
12192 | ||
d244c892 MC |
12193 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
12194 | { | |
12195 | struct tg3 *tp = netdev_priv(dev); | |
12196 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
12197 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
12198 | ||
63c3a66f | 12199 | if (!tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
12200 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; |
12201 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
12202 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
12203 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
12204 | } | |
12205 | ||
12206 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
12207 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
12208 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
12209 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
12210 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
12211 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
12212 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
12213 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
12214 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
12215 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
12216 | return -EINVAL; | |
12217 | ||
12218 | /* No rx interrupts will be generated if both are zero */ | |
12219 | if ((ec->rx_coalesce_usecs == 0) && | |
12220 | (ec->rx_max_coalesced_frames == 0)) | |
12221 | return -EINVAL; | |
12222 | ||
12223 | /* No tx interrupts will be generated if both are zero */ | |
12224 | if ((ec->tx_coalesce_usecs == 0) && | |
12225 | (ec->tx_max_coalesced_frames == 0)) | |
12226 | return -EINVAL; | |
12227 | ||
12228 | /* Only copy relevant parameters, ignore all others. */ | |
12229 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
12230 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
12231 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
12232 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
12233 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
12234 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
12235 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
12236 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
12237 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
12238 | ||
12239 | if (netif_running(dev)) { | |
12240 | tg3_full_lock(tp, 0); | |
12241 | __tg3_set_coalesce(tp, &tp->coal); | |
12242 | tg3_full_unlock(tp); | |
12243 | } | |
12244 | return 0; | |
12245 | } | |
12246 | ||
7282d491 | 12247 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
12248 | .get_settings = tg3_get_settings, |
12249 | .set_settings = tg3_set_settings, | |
12250 | .get_drvinfo = tg3_get_drvinfo, | |
12251 | .get_regs_len = tg3_get_regs_len, | |
12252 | .get_regs = tg3_get_regs, | |
12253 | .get_wol = tg3_get_wol, | |
12254 | .set_wol = tg3_set_wol, | |
12255 | .get_msglevel = tg3_get_msglevel, | |
12256 | .set_msglevel = tg3_set_msglevel, | |
12257 | .nway_reset = tg3_nway_reset, | |
12258 | .get_link = ethtool_op_get_link, | |
12259 | .get_eeprom_len = tg3_get_eeprom_len, | |
12260 | .get_eeprom = tg3_get_eeprom, | |
12261 | .set_eeprom = tg3_set_eeprom, | |
12262 | .get_ringparam = tg3_get_ringparam, | |
12263 | .set_ringparam = tg3_set_ringparam, | |
12264 | .get_pauseparam = tg3_get_pauseparam, | |
12265 | .set_pauseparam = tg3_set_pauseparam, | |
4cafd3f5 | 12266 | .self_test = tg3_self_test, |
1da177e4 | 12267 | .get_strings = tg3_get_strings, |
81b8709c | 12268 | .set_phys_id = tg3_set_phys_id, |
1da177e4 | 12269 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 12270 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 12271 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 12272 | .get_sset_count = tg3_get_sset_count, |
90415477 MC |
12273 | .get_rxnfc = tg3_get_rxnfc, |
12274 | .get_rxfh_indir_size = tg3_get_rxfh_indir_size, | |
12275 | .get_rxfh_indir = tg3_get_rxfh_indir, | |
12276 | .set_rxfh_indir = tg3_set_rxfh_indir, | |
3f847490 | 12277 | .get_ts_info = ethtool_op_get_ts_info, |
1da177e4 LT |
12278 | }; |
12279 | ||
b4017c53 DM |
12280 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
12281 | struct rtnl_link_stats64 *stats) | |
12282 | { | |
12283 | struct tg3 *tp = netdev_priv(dev); | |
12284 | ||
12285 | if (!tp->hw_stats) | |
12286 | return &tp->net_stats_prev; | |
12287 | ||
12288 | spin_lock_bh(&tp->lock); | |
12289 | tg3_get_nstats(tp, stats); | |
12290 | spin_unlock_bh(&tp->lock); | |
12291 | ||
12292 | return stats; | |
12293 | } | |
12294 | ||
ccd5ba9d MC |
12295 | static void tg3_set_rx_mode(struct net_device *dev) |
12296 | { | |
12297 | struct tg3 *tp = netdev_priv(dev); | |
12298 | ||
12299 | if (!netif_running(dev)) | |
12300 | return; | |
12301 | ||
12302 | tg3_full_lock(tp, 0); | |
12303 | __tg3_set_rx_mode(dev); | |
12304 | tg3_full_unlock(tp); | |
12305 | } | |
12306 | ||
faf1627a MC |
12307 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
12308 | int new_mtu) | |
12309 | { | |
12310 | dev->mtu = new_mtu; | |
12311 | ||
12312 | if (new_mtu > ETH_DATA_LEN) { | |
12313 | if (tg3_flag(tp, 5780_CLASS)) { | |
12314 | netdev_update_features(dev); | |
12315 | tg3_flag_clear(tp, TSO_CAPABLE); | |
12316 | } else { | |
12317 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
12318 | } | |
12319 | } else { | |
12320 | if (tg3_flag(tp, 5780_CLASS)) { | |
12321 | tg3_flag_set(tp, TSO_CAPABLE); | |
12322 | netdev_update_features(dev); | |
12323 | } | |
12324 | tg3_flag_clear(tp, JUMBO_RING_ENABLE); | |
12325 | } | |
12326 | } | |
12327 | ||
12328 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
12329 | { | |
12330 | struct tg3 *tp = netdev_priv(dev); | |
2fae5e36 | 12331 | int err, reset_phy = 0; |
faf1627a MC |
12332 | |
12333 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
12334 | return -EINVAL; | |
12335 | ||
12336 | if (!netif_running(dev)) { | |
12337 | /* We'll just catch it later when the | |
12338 | * device is up'd. | |
12339 | */ | |
12340 | tg3_set_mtu(dev, tp, new_mtu); | |
12341 | return 0; | |
12342 | } | |
12343 | ||
12344 | tg3_phy_stop(tp); | |
12345 | ||
12346 | tg3_netif_stop(tp); | |
12347 | ||
12348 | tg3_full_lock(tp, 1); | |
12349 | ||
12350 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
12351 | ||
12352 | tg3_set_mtu(dev, tp, new_mtu); | |
12353 | ||
2fae5e36 MC |
12354 | /* Reset PHY, otherwise the read DMA engine will be in a mode that |
12355 | * breaks all requests to 256 bytes. | |
12356 | */ | |
12357 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) | |
12358 | reset_phy = 1; | |
12359 | ||
12360 | err = tg3_restart_hw(tp, reset_phy); | |
faf1627a MC |
12361 | |
12362 | if (!err) | |
12363 | tg3_netif_start(tp); | |
12364 | ||
12365 | tg3_full_unlock(tp); | |
12366 | ||
12367 | if (!err) | |
12368 | tg3_phy_start(tp); | |
12369 | ||
12370 | return err; | |
12371 | } | |
12372 | ||
12373 | static const struct net_device_ops tg3_netdev_ops = { | |
12374 | .ndo_open = tg3_open, | |
12375 | .ndo_stop = tg3_close, | |
12376 | .ndo_start_xmit = tg3_start_xmit, | |
12377 | .ndo_get_stats64 = tg3_get_stats64, | |
12378 | .ndo_validate_addr = eth_validate_addr, | |
12379 | .ndo_set_rx_mode = tg3_set_rx_mode, | |
12380 | .ndo_set_mac_address = tg3_set_mac_addr, | |
12381 | .ndo_do_ioctl = tg3_ioctl, | |
12382 | .ndo_tx_timeout = tg3_tx_timeout, | |
12383 | .ndo_change_mtu = tg3_change_mtu, | |
12384 | .ndo_fix_features = tg3_fix_features, | |
12385 | .ndo_set_features = tg3_set_features, | |
12386 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
12387 | .ndo_poll_controller = tg3_poll_controller, | |
12388 | #endif | |
12389 | }; | |
12390 | ||
1da177e4 LT |
12391 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) |
12392 | { | |
1b27777a | 12393 | u32 cursize, val, magic; |
1da177e4 LT |
12394 | |
12395 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
12396 | ||
e4f34110 | 12397 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
12398 | return; |
12399 | ||
b16250e3 MC |
12400 | if ((magic != TG3_EEPROM_MAGIC) && |
12401 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
12402 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
12403 | return; |
12404 | ||
12405 | /* | |
12406 | * Size the chip by reading offsets at increasing powers of two. | |
12407 | * When we encounter our validation signature, we know the addressing | |
12408 | * has wrapped around, and thus have our chip size. | |
12409 | */ | |
1b27777a | 12410 | cursize = 0x10; |
1da177e4 LT |
12411 | |
12412 | while (cursize < tp->nvram_size) { | |
e4f34110 | 12413 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
12414 | return; |
12415 | ||
1820180b | 12416 | if (val == magic) |
1da177e4 LT |
12417 | break; |
12418 | ||
12419 | cursize <<= 1; | |
12420 | } | |
12421 | ||
12422 | tp->nvram_size = cursize; | |
12423 | } | |
6aa20a22 | 12424 | |
1da177e4 LT |
12425 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
12426 | { | |
12427 | u32 val; | |
12428 | ||
63c3a66f | 12429 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) |
1b27777a MC |
12430 | return; |
12431 | ||
12432 | /* Selfboot format */ | |
1820180b | 12433 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
12434 | tg3_get_eeprom_size(tp); |
12435 | return; | |
12436 | } | |
12437 | ||
6d348f2c | 12438 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 12439 | if (val != 0) { |
6d348f2c MC |
12440 | /* This is confusing. We want to operate on the |
12441 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
12442 | * call will read from NVRAM and byteswap the data | |
12443 | * according to the byteswapping settings for all | |
12444 | * other register accesses. This ensures the data we | |
12445 | * want will always reside in the lower 16-bits. | |
12446 | * However, the data in NVRAM is in LE format, which | |
12447 | * means the data from the NVRAM read will always be | |
12448 | * opposite the endianness of the CPU. The 16-bit | |
12449 | * byteswap then brings the data to CPU endianness. | |
12450 | */ | |
12451 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
12452 | return; |
12453 | } | |
12454 | } | |
fd1122a2 | 12455 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
12456 | } |
12457 | ||
12458 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
12459 | { | |
12460 | u32 nvcfg1; | |
12461 | ||
12462 | nvcfg1 = tr32(NVRAM_CFG1); | |
12463 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
63c3a66f | 12464 | tg3_flag_set(tp, FLASH); |
8590a603 | 12465 | } else { |
1da177e4 LT |
12466 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
12467 | tw32(NVRAM_CFG1, nvcfg1); | |
12468 | } | |
12469 | ||
6ff6f81d | 12470 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
63c3a66f | 12471 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 | 12472 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
12473 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
12474 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12475 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 12476 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12477 | break; |
12478 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
12479 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12480 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
12481 | break; | |
12482 | case FLASH_VENDOR_ATMEL_EEPROM: | |
12483 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12484 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
63c3a66f | 12485 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12486 | break; |
12487 | case FLASH_VENDOR_ST: | |
12488 | tp->nvram_jedecnum = JEDEC_ST; | |
12489 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
63c3a66f | 12490 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12491 | break; |
12492 | case FLASH_VENDOR_SAIFUN: | |
12493 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
12494 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
12495 | break; | |
12496 | case FLASH_VENDOR_SST_SMALL: | |
12497 | case FLASH_VENDOR_SST_LARGE: | |
12498 | tp->nvram_jedecnum = JEDEC_SST; | |
12499 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
12500 | break; | |
1da177e4 | 12501 | } |
8590a603 | 12502 | } else { |
1da177e4 LT |
12503 | tp->nvram_jedecnum = JEDEC_ATMEL; |
12504 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 12505 | tg3_flag_set(tp, NVRAM_BUFFERED); |
1da177e4 LT |
12506 | } |
12507 | } | |
12508 | ||
a1b950d5 MC |
12509 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
12510 | { | |
12511 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
12512 | case FLASH_5752PAGE_SIZE_256: | |
12513 | tp->nvram_pagesize = 256; | |
12514 | break; | |
12515 | case FLASH_5752PAGE_SIZE_512: | |
12516 | tp->nvram_pagesize = 512; | |
12517 | break; | |
12518 | case FLASH_5752PAGE_SIZE_1K: | |
12519 | tp->nvram_pagesize = 1024; | |
12520 | break; | |
12521 | case FLASH_5752PAGE_SIZE_2K: | |
12522 | tp->nvram_pagesize = 2048; | |
12523 | break; | |
12524 | case FLASH_5752PAGE_SIZE_4K: | |
12525 | tp->nvram_pagesize = 4096; | |
12526 | break; | |
12527 | case FLASH_5752PAGE_SIZE_264: | |
12528 | tp->nvram_pagesize = 264; | |
12529 | break; | |
12530 | case FLASH_5752PAGE_SIZE_528: | |
12531 | tp->nvram_pagesize = 528; | |
12532 | break; | |
12533 | } | |
12534 | } | |
12535 | ||
361b4ac2 MC |
12536 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
12537 | { | |
12538 | u32 nvcfg1; | |
12539 | ||
12540 | nvcfg1 = tr32(NVRAM_CFG1); | |
12541 | ||
e6af301b MC |
12542 | /* NVRAM protection for TPM */ |
12543 | if (nvcfg1 & (1 << 27)) | |
63c3a66f | 12544 | tg3_flag_set(tp, PROTECTED_NVRAM); |
e6af301b | 12545 | |
361b4ac2 | 12546 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
12547 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
12548 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
12549 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12550 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12551 | break; |
12552 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12553 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12554 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12555 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12556 | break; |
12557 | case FLASH_5752VENDOR_ST_M45PE10: | |
12558 | case FLASH_5752VENDOR_ST_M45PE20: | |
12559 | case FLASH_5752VENDOR_ST_M45PE40: | |
12560 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12561 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12562 | tg3_flag_set(tp, FLASH); | |
8590a603 | 12563 | break; |
361b4ac2 MC |
12564 | } |
12565 | ||
63c3a66f | 12566 | if (tg3_flag(tp, FLASH)) { |
a1b950d5 | 12567 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 12568 | } else { |
361b4ac2 MC |
12569 | /* For eeprom, set pagesize to maximum eeprom size */ |
12570 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12571 | ||
12572 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12573 | tw32(NVRAM_CFG1, nvcfg1); | |
12574 | } | |
12575 | } | |
12576 | ||
d3c7b886 MC |
12577 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
12578 | { | |
989a9d23 | 12579 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
12580 | |
12581 | nvcfg1 = tr32(NVRAM_CFG1); | |
12582 | ||
12583 | /* NVRAM protection for TPM */ | |
989a9d23 | 12584 | if (nvcfg1 & (1 << 27)) { |
63c3a66f | 12585 | tg3_flag_set(tp, PROTECTED_NVRAM); |
989a9d23 MC |
12586 | protect = 1; |
12587 | } | |
d3c7b886 | 12588 | |
989a9d23 MC |
12589 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
12590 | switch (nvcfg1) { | |
8590a603 MC |
12591 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
12592 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
12593 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
12594 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
12595 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12596 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12597 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12598 | tp->nvram_pagesize = 264; |
12599 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
12600 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
12601 | tp->nvram_size = (protect ? 0x3e200 : | |
12602 | TG3_NVRAM_SIZE_512KB); | |
12603 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
12604 | tp->nvram_size = (protect ? 0x1f200 : | |
12605 | TG3_NVRAM_SIZE_256KB); | |
12606 | else | |
12607 | tp->nvram_size = (protect ? 0x1f200 : | |
12608 | TG3_NVRAM_SIZE_128KB); | |
12609 | break; | |
12610 | case FLASH_5752VENDOR_ST_M45PE10: | |
12611 | case FLASH_5752VENDOR_ST_M45PE20: | |
12612 | case FLASH_5752VENDOR_ST_M45PE40: | |
12613 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12614 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12615 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12616 | tp->nvram_pagesize = 256; |
12617 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
12618 | tp->nvram_size = (protect ? | |
12619 | TG3_NVRAM_SIZE_64KB : | |
12620 | TG3_NVRAM_SIZE_128KB); | |
12621 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
12622 | tp->nvram_size = (protect ? | |
12623 | TG3_NVRAM_SIZE_64KB : | |
12624 | TG3_NVRAM_SIZE_256KB); | |
12625 | else | |
12626 | tp->nvram_size = (protect ? | |
12627 | TG3_NVRAM_SIZE_128KB : | |
12628 | TG3_NVRAM_SIZE_512KB); | |
12629 | break; | |
d3c7b886 MC |
12630 | } |
12631 | } | |
12632 | ||
1b27777a MC |
12633 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
12634 | { | |
12635 | u32 nvcfg1; | |
12636 | ||
12637 | nvcfg1 = tr32(NVRAM_CFG1); | |
12638 | ||
12639 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
12640 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
12641 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12642 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
12643 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12644 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12645 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 | 12646 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
1b27777a | 12647 | |
8590a603 MC |
12648 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
12649 | tw32(NVRAM_CFG1, nvcfg1); | |
12650 | break; | |
12651 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12652 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
12653 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
12654 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
12655 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12656 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12657 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12658 | tp->nvram_pagesize = 264; |
12659 | break; | |
12660 | case FLASH_5752VENDOR_ST_M45PE10: | |
12661 | case FLASH_5752VENDOR_ST_M45PE20: | |
12662 | case FLASH_5752VENDOR_ST_M45PE40: | |
12663 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12664 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12665 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12666 | tp->nvram_pagesize = 256; |
12667 | break; | |
1b27777a MC |
12668 | } |
12669 | } | |
12670 | ||
6b91fa02 MC |
12671 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
12672 | { | |
12673 | u32 nvcfg1, protect = 0; | |
12674 | ||
12675 | nvcfg1 = tr32(NVRAM_CFG1); | |
12676 | ||
12677 | /* NVRAM protection for TPM */ | |
12678 | if (nvcfg1 & (1 << 27)) { | |
63c3a66f | 12679 | tg3_flag_set(tp, PROTECTED_NVRAM); |
6b91fa02 MC |
12680 | protect = 1; |
12681 | } | |
12682 | ||
12683 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
12684 | switch (nvcfg1) { | |
8590a603 MC |
12685 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
12686 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12687 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12688 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
12689 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12690 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12691 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12692 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12693 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12694 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12695 | tg3_flag_set(tp, FLASH); | |
12696 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
8590a603 MC |
12697 | tp->nvram_pagesize = 256; |
12698 | break; | |
12699 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12700 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12701 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12702 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12703 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12704 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12705 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12706 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12707 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12708 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12709 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12710 | tp->nvram_pagesize = 256; |
12711 | break; | |
6b91fa02 MC |
12712 | } |
12713 | ||
12714 | if (protect) { | |
12715 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
12716 | } else { | |
12717 | switch (nvcfg1) { | |
8590a603 MC |
12718 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
12719 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12720 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12721 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12722 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
12723 | break; | |
12724 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12725 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12726 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12727 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12728 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12729 | break; | |
12730 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12731 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12732 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12733 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12734 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12735 | break; | |
12736 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
12737 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12738 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12739 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12740 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12741 | break; | |
6b91fa02 MC |
12742 | } |
12743 | } | |
12744 | } | |
12745 | ||
b5d3772c MC |
12746 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
12747 | { | |
12748 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12749 | tg3_flag_set(tp, NVRAM_BUFFERED); |
b5d3772c MC |
12750 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12751 | } | |
12752 | ||
321d32a0 MC |
12753 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
12754 | { | |
12755 | u32 nvcfg1; | |
12756 | ||
12757 | nvcfg1 = tr32(NVRAM_CFG1); | |
12758 | ||
12759 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12760 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12761 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12762 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12763 | tg3_flag_set(tp, NVRAM_BUFFERED); |
321d32a0 MC |
12764 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12765 | ||
12766 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12767 | tw32(NVRAM_CFG1, nvcfg1); | |
12768 | return; | |
12769 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12770 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12771 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12772 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12773 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12774 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12775 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12776 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12777 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12778 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12779 | |
12780 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12781 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12782 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12783 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12784 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12785 | break; | |
12786 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12787 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12788 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12789 | break; | |
12790 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12791 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12792 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12793 | break; | |
12794 | } | |
12795 | break; | |
12796 | case FLASH_5752VENDOR_ST_M45PE10: | |
12797 | case FLASH_5752VENDOR_ST_M45PE20: | |
12798 | case FLASH_5752VENDOR_ST_M45PE40: | |
12799 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12800 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12801 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12802 | |
12803 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12804 | case FLASH_5752VENDOR_ST_M45PE10: | |
12805 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12806 | break; | |
12807 | case FLASH_5752VENDOR_ST_M45PE20: | |
12808 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12809 | break; | |
12810 | case FLASH_5752VENDOR_ST_M45PE40: | |
12811 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12812 | break; | |
12813 | } | |
12814 | break; | |
12815 | default: | |
63c3a66f | 12816 | tg3_flag_set(tp, NO_NVRAM); |
321d32a0 MC |
12817 | return; |
12818 | } | |
12819 | ||
a1b950d5 MC |
12820 | tg3_nvram_get_pagesize(tp, nvcfg1); |
12821 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12822 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
a1b950d5 MC |
12823 | } |
12824 | ||
12825 | ||
12826 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
12827 | { | |
12828 | u32 nvcfg1; | |
12829 | ||
12830 | nvcfg1 = tr32(NVRAM_CFG1); | |
12831 | ||
12832 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12833 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
12834 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
12835 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12836 | tg3_flag_set(tp, NVRAM_BUFFERED); |
a1b950d5 MC |
12837 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12838 | ||
12839 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12840 | tw32(NVRAM_CFG1, nvcfg1); | |
12841 | return; | |
12842 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
12843 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
12844 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
12845 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
12846 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
12847 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12848 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
12849 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12850 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12851 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12852 | |
12853 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12854 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
66ee33bf MC |
12855 | /* Detect size with tg3_nvram_get_size() */ |
12856 | break; | |
a1b950d5 MC |
12857 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
12858 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12859 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12860 | break; | |
12861 | default: | |
12862 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12863 | break; | |
12864 | } | |
321d32a0 | 12865 | break; |
a1b950d5 MC |
12866 | case FLASH_5717VENDOR_ST_M_M25PE10: |
12867 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
12868 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
12869 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
12870 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
12871 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
12872 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
12873 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
12874 | case FLASH_5717VENDOR_ST_25USPT: | |
12875 | case FLASH_5717VENDOR_ST_45USPT: | |
12876 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12877 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12878 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12879 | |
12880 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12881 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
a1b950d5 | 12882 | case FLASH_5717VENDOR_ST_M_M45PE20: |
66ee33bf MC |
12883 | /* Detect size with tg3_nvram_get_size() */ |
12884 | break; | |
12885 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
a1b950d5 MC |
12886 | case FLASH_5717VENDOR_ST_A_M45PE20: |
12887 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12888 | break; | |
12889 | default: | |
12890 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12891 | break; | |
12892 | } | |
321d32a0 | 12893 | break; |
a1b950d5 | 12894 | default: |
63c3a66f | 12895 | tg3_flag_set(tp, NO_NVRAM); |
a1b950d5 | 12896 | return; |
321d32a0 | 12897 | } |
a1b950d5 MC |
12898 | |
12899 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12900 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12901 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
321d32a0 MC |
12902 | } |
12903 | ||
9b91b5f1 MC |
12904 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
12905 | { | |
12906 | u32 nvcfg1, nvmpinstrp; | |
12907 | ||
12908 | nvcfg1 = tr32(NVRAM_CFG1); | |
12909 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
12910 | ||
12911 | switch (nvmpinstrp) { | |
12912 | case FLASH_5720_EEPROM_HD: | |
12913 | case FLASH_5720_EEPROM_LD: | |
12914 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12915 | tg3_flag_set(tp, NVRAM_BUFFERED); |
9b91b5f1 MC |
12916 | |
12917 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12918 | tw32(NVRAM_CFG1, nvcfg1); | |
12919 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
12920 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12921 | else | |
12922 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
12923 | return; | |
12924 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
12925 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
12926 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
12927 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12928 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12929 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12930 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12931 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12932 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12933 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12934 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12935 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
12936 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12937 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12938 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12939 | |
12940 | switch (nvmpinstrp) { | |
12941 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12942 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12943 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12944 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12945 | break; | |
12946 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12947 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12948 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12949 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12950 | break; | |
12951 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12952 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12953 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12954 | break; | |
12955 | default: | |
12956 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12957 | break; | |
12958 | } | |
12959 | break; | |
12960 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
12961 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
12962 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
12963 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
12964 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12965 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12966 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12967 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12968 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12969 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12970 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12971 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12972 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12973 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12974 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12975 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12976 | case FLASH_5720VENDOR_ST_25USPT: | |
12977 | case FLASH_5720VENDOR_ST_45USPT: | |
12978 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12979 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12980 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12981 | |
12982 | switch (nvmpinstrp) { | |
12983 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12984 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12985 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12986 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12987 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12988 | break; | |
12989 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12990 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12991 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12992 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12993 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12994 | break; | |
12995 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12996 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12997 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12998 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12999 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
13000 | break; | |
13001 | default: | |
13002 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13003 | break; | |
13004 | } | |
13005 | break; | |
13006 | default: | |
63c3a66f | 13007 | tg3_flag_set(tp, NO_NVRAM); |
9b91b5f1 MC |
13008 | return; |
13009 | } | |
13010 | ||
13011 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
13012 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 13013 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
9b91b5f1 MC |
13014 | } |
13015 | ||
1da177e4 LT |
13016 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
13017 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
13018 | { | |
1da177e4 LT |
13019 | tw32_f(GRC_EEPROM_ADDR, |
13020 | (EEPROM_ADDR_FSM_RESET | | |
13021 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
13022 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
13023 | ||
9d57f01c | 13024 | msleep(1); |
1da177e4 LT |
13025 | |
13026 | /* Enable seeprom accesses. */ | |
13027 | tw32_f(GRC_LOCAL_CTRL, | |
13028 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
13029 | udelay(100); | |
13030 | ||
13031 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13032 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
63c3a66f | 13033 | tg3_flag_set(tp, NVRAM); |
1da177e4 | 13034 | |
ec41c7df | 13035 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
13036 | netdev_warn(tp->dev, |
13037 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 13038 | __func__); |
ec41c7df MC |
13039 | return; |
13040 | } | |
e6af301b | 13041 | tg3_enable_nvram_access(tp); |
1da177e4 | 13042 | |
989a9d23 MC |
13043 | tp->nvram_size = 0; |
13044 | ||
361b4ac2 MC |
13045 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
13046 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
13047 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
13048 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 13049 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
13050 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
13051 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 13052 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
13053 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
13054 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
13055 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
13056 | tg3_get_5906_nvram_info(tp); | |
b703df6f | 13057 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
55086ad9 | 13058 | tg3_flag(tp, 57765_CLASS)) |
321d32a0 | 13059 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
13060 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13061 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 13062 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
13063 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
13064 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
13065 | else |
13066 | tg3_get_nvram_info(tp); | |
13067 | ||
989a9d23 MC |
13068 | if (tp->nvram_size == 0) |
13069 | tg3_get_nvram_size(tp); | |
1da177e4 | 13070 | |
e6af301b | 13071 | tg3_disable_nvram_access(tp); |
381291b7 | 13072 | tg3_nvram_unlock(tp); |
1da177e4 LT |
13073 | |
13074 | } else { | |
63c3a66f JP |
13075 | tg3_flag_clear(tp, NVRAM); |
13076 | tg3_flag_clear(tp, NVRAM_BUFFERED); | |
1da177e4 LT |
13077 | |
13078 | tg3_get_eeprom_size(tp); | |
13079 | } | |
13080 | } | |
13081 | ||
1da177e4 LT |
13082 | struct subsys_tbl_ent { |
13083 | u16 subsys_vendor, subsys_devid; | |
13084 | u32 phy_id; | |
13085 | }; | |
13086 | ||
24daf2b0 | 13087 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 13088 | /* Broadcom boards. */ |
24daf2b0 | 13089 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13090 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13091 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13092 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13093 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13094 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
13095 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
13096 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
13097 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 13098 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13099 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13100 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
13101 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
13102 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
13103 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 13104 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13105 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13106 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13107 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13108 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 13109 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13110 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
13111 | |
13112 | /* 3com boards. */ | |
24daf2b0 | 13113 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 13114 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13115 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 13116 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
13117 | { TG3PCI_SUBVENDOR_ID_3COM, |
13118 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
13119 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 13120 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13121 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 13122 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
13123 | |
13124 | /* DELL boards. */ | |
24daf2b0 | 13125 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13126 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13127 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13128 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13129 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13130 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 13131 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13132 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
13133 | |
13134 | /* Compaq boards. */ | |
24daf2b0 | 13135 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 13136 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13137 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 13138 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
13139 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
13140 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
13141 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 13142 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13143 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 13144 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
13145 | |
13146 | /* IBM boards. */ | |
24daf2b0 MC |
13147 | { TG3PCI_SUBVENDOR_ID_IBM, |
13148 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
13149 | }; |
13150 | ||
24daf2b0 | 13151 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
13152 | { |
13153 | int i; | |
13154 | ||
13155 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
13156 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
13157 | tp->pdev->subsystem_vendor) && | |
13158 | (subsys_id_to_phy_id[i].subsys_devid == | |
13159 | tp->pdev->subsystem_device)) | |
13160 | return &subsys_id_to_phy_id[i]; | |
13161 | } | |
13162 | return NULL; | |
13163 | } | |
13164 | ||
7d0c41ef | 13165 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 13166 | { |
1da177e4 | 13167 | u32 val; |
f49639e6 | 13168 | |
79eb6904 | 13169 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
13170 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
13171 | ||
a85feb8c | 13172 | /* Assume an onboard device and WOL capable by default. */ |
63c3a66f JP |
13173 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
13174 | tg3_flag_set(tp, WOL_CAP); | |
72b845e0 | 13175 | |
b5d3772c | 13176 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 13177 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
63c3a66f JP |
13178 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
13179 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 13180 | } |
0527ba35 MC |
13181 | val = tr32(VCPU_CFGSHDW); |
13182 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
63c3a66f | 13183 | tg3_flag_set(tp, ASPM_WORKAROUND); |
0527ba35 | 13184 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
6fdbab9d | 13185 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) { |
63c3a66f | 13186 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
13187 | device_set_wakeup_enable(&tp->pdev->dev, true); |
13188 | } | |
05ac4cb7 | 13189 | goto done; |
b5d3772c MC |
13190 | } |
13191 | ||
1da177e4 LT |
13192 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
13193 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
13194 | u32 nic_cfg, led_cfg; | |
a9daf367 | 13195 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 13196 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
13197 | |
13198 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
13199 | tp->nic_sram_data_cfg = nic_cfg; | |
13200 | ||
13201 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
13202 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
6ff6f81d MC |
13203 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
13204 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13205 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && | |
1da177e4 LT |
13206 | (ver > 0) && (ver < 0x100)) |
13207 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
13208 | ||
a9daf367 MC |
13209 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
13210 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
13211 | ||
1da177e4 LT |
13212 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
13213 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
13214 | eeprom_phy_serdes = 1; | |
13215 | ||
13216 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
13217 | if (nic_phy_id != 0) { | |
13218 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
13219 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
13220 | ||
13221 | eeprom_phy_id = (id1 >> 16) << 10; | |
13222 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
13223 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
13224 | } else | |
13225 | eeprom_phy_id = 0; | |
13226 | ||
7d0c41ef | 13227 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 13228 | if (eeprom_phy_serdes) { |
63c3a66f | 13229 | if (!tg3_flag(tp, 5705_PLUS)) |
f07e9af3 | 13230 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 13231 | else |
f07e9af3 | 13232 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 13233 | } |
7d0c41ef | 13234 | |
63c3a66f | 13235 | if (tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
13236 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
13237 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 13238 | else |
1da177e4 LT |
13239 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
13240 | ||
13241 | switch (led_cfg) { | |
13242 | default: | |
13243 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
13244 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
13245 | break; | |
13246 | ||
13247 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
13248 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
13249 | break; | |
13250 | ||
13251 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
13252 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
13253 | |
13254 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
13255 | * read on some older 5700/5701 bootcode. | |
13256 | */ | |
13257 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13258 | ASIC_REV_5700 || | |
13259 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13260 | ASIC_REV_5701) | |
13261 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
13262 | ||
1da177e4 LT |
13263 | break; |
13264 | ||
13265 | case SHASTA_EXT_LED_SHARED: | |
13266 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
13267 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
13268 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
13269 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
13270 | LED_CTRL_MODE_PHY_2); | |
13271 | break; | |
13272 | ||
13273 | case SHASTA_EXT_LED_MAC: | |
13274 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
13275 | break; | |
13276 | ||
13277 | case SHASTA_EXT_LED_COMBO: | |
13278 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
13279 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
13280 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
13281 | LED_CTRL_MODE_PHY_2); | |
13282 | break; | |
13283 | ||
855e1111 | 13284 | } |
1da177e4 LT |
13285 | |
13286 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13287 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
13288 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
13289 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
13290 | ||
b2a5c19c MC |
13291 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
13292 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 13293 | |
9d26e213 | 13294 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
63c3a66f | 13295 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
9d26e213 MC |
13296 | if ((tp->pdev->subsystem_vendor == |
13297 | PCI_VENDOR_ID_ARIMA) && | |
13298 | (tp->pdev->subsystem_device == 0x205a || | |
13299 | tp->pdev->subsystem_device == 0x2063)) | |
63c3a66f | 13300 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
9d26e213 | 13301 | } else { |
63c3a66f JP |
13302 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
13303 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 13304 | } |
1da177e4 LT |
13305 | |
13306 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f JP |
13307 | tg3_flag_set(tp, ENABLE_ASF); |
13308 | if (tg3_flag(tp, 5750_PLUS)) | |
13309 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 | 13310 | } |
b2b98d4a MC |
13311 | |
13312 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
63c3a66f JP |
13313 | tg3_flag(tp, 5750_PLUS)) |
13314 | tg3_flag_set(tp, ENABLE_APE); | |
b2b98d4a | 13315 | |
f07e9af3 | 13316 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c | 13317 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
63c3a66f | 13318 | tg3_flag_clear(tp, WOL_CAP); |
1da177e4 | 13319 | |
63c3a66f | 13320 | if (tg3_flag(tp, WOL_CAP) && |
6fdbab9d | 13321 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) { |
63c3a66f | 13322 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
13323 | device_set_wakeup_enable(&tp->pdev->dev, true); |
13324 | } | |
0527ba35 | 13325 | |
1da177e4 | 13326 | if (cfg2 & (1 << 17)) |
f07e9af3 | 13327 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
13328 | |
13329 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
13330 | /* bootcode if bit 18 is set */ | |
13331 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 13332 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 13333 | |
63c3a66f JP |
13334 | if ((tg3_flag(tp, 57765_PLUS) || |
13335 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
13336 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 | 13337 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 13338 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 13339 | |
63c3a66f | 13340 | if (tg3_flag(tp, PCI_EXPRESS) && |
8c69b1e7 | 13341 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
63c3a66f | 13342 | !tg3_flag(tp, 57765_PLUS)) { |
8ed5d97e MC |
13343 | u32 cfg3; |
13344 | ||
13345 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
13346 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
63c3a66f | 13347 | tg3_flag_set(tp, ASPM_WORKAROUND); |
8ed5d97e | 13348 | } |
a9daf367 | 13349 | |
14417063 | 13350 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
63c3a66f | 13351 | tg3_flag_set(tp, RGMII_INBAND_DISABLE); |
a9daf367 | 13352 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
63c3a66f | 13353 | tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); |
a9daf367 | 13354 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) |
63c3a66f | 13355 | tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); |
1da177e4 | 13356 | } |
05ac4cb7 | 13357 | done: |
63c3a66f | 13358 | if (tg3_flag(tp, WOL_CAP)) |
43067ed8 | 13359 | device_set_wakeup_enable(&tp->pdev->dev, |
63c3a66f | 13360 | tg3_flag(tp, WOL_ENABLE)); |
43067ed8 RW |
13361 | else |
13362 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
13363 | } |
13364 | ||
b2a5c19c MC |
13365 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
13366 | { | |
13367 | int i; | |
13368 | u32 val; | |
13369 | ||
13370 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
13371 | tw32(OTP_CTRL, cmd); | |
13372 | ||
13373 | /* Wait for up to 1 ms for command to execute. */ | |
13374 | for (i = 0; i < 100; i++) { | |
13375 | val = tr32(OTP_STATUS); | |
13376 | if (val & OTP_STATUS_CMD_DONE) | |
13377 | break; | |
13378 | udelay(10); | |
13379 | } | |
13380 | ||
13381 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
13382 | } | |
13383 | ||
13384 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
13385 | * configuration is a 32-bit value that straddles the alignment boundary. | |
13386 | * We do two 32-bit reads and then shift and merge the results. | |
13387 | */ | |
13388 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
13389 | { | |
13390 | u32 bhalf_otp, thalf_otp; | |
13391 | ||
13392 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
13393 | ||
13394 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
13395 | return 0; | |
13396 | ||
13397 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
13398 | ||
13399 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13400 | return 0; | |
13401 | ||
13402 | thalf_otp = tr32(OTP_READ_DATA); | |
13403 | ||
13404 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
13405 | ||
13406 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13407 | return 0; | |
13408 | ||
13409 | bhalf_otp = tr32(OTP_READ_DATA); | |
13410 | ||
13411 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
13412 | } | |
13413 | ||
e256f8a3 MC |
13414 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
13415 | { | |
202ff1c2 | 13416 | u32 adv = ADVERTISED_Autoneg; |
e256f8a3 MC |
13417 | |
13418 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
13419 | adv |= ADVERTISED_1000baseT_Half | | |
13420 | ADVERTISED_1000baseT_Full; | |
13421 | ||
13422 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
13423 | adv |= ADVERTISED_100baseT_Half | | |
13424 | ADVERTISED_100baseT_Full | | |
13425 | ADVERTISED_10baseT_Half | | |
13426 | ADVERTISED_10baseT_Full | | |
13427 | ADVERTISED_TP; | |
13428 | else | |
13429 | adv |= ADVERTISED_FIBRE; | |
13430 | ||
13431 | tp->link_config.advertising = adv; | |
e740522e MC |
13432 | tp->link_config.speed = SPEED_UNKNOWN; |
13433 | tp->link_config.duplex = DUPLEX_UNKNOWN; | |
e256f8a3 | 13434 | tp->link_config.autoneg = AUTONEG_ENABLE; |
e740522e MC |
13435 | tp->link_config.active_speed = SPEED_UNKNOWN; |
13436 | tp->link_config.active_duplex = DUPLEX_UNKNOWN; | |
34655ad6 MC |
13437 | |
13438 | tp->old_link = -1; | |
e256f8a3 MC |
13439 | } |
13440 | ||
7d0c41ef MC |
13441 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
13442 | { | |
13443 | u32 hw_phy_id_1, hw_phy_id_2; | |
13444 | u32 hw_phy_id, hw_phy_id_masked; | |
13445 | int err; | |
1da177e4 | 13446 | |
e256f8a3 | 13447 | /* flow control autonegotiation is default behavior */ |
63c3a66f | 13448 | tg3_flag_set(tp, PAUSE_AUTONEG); |
e256f8a3 MC |
13449 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
13450 | ||
63c3a66f | 13451 | if (tg3_flag(tp, USE_PHYLIB)) |
b02fd9e3 MC |
13452 | return tg3_phy_init(tp); |
13453 | ||
1da177e4 | 13454 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 13455 | * firmware access to the PHY hardware. |
1da177e4 LT |
13456 | */ |
13457 | err = 0; | |
63c3a66f | 13458 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { |
79eb6904 | 13459 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
13460 | } else { |
13461 | /* Now read the physical PHY_ID from the chip and verify | |
13462 | * that it is sane. If it doesn't look good, we fall back | |
13463 | * to either the hard-coded table based PHY_ID and failing | |
13464 | * that the value found in the eeprom area. | |
13465 | */ | |
13466 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
13467 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
13468 | ||
13469 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
13470 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
13471 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
13472 | ||
79eb6904 | 13473 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
13474 | } |
13475 | ||
79eb6904 | 13476 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 13477 | tp->phy_id = hw_phy_id; |
79eb6904 | 13478 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13479 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 13480 | else |
f07e9af3 | 13481 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 13482 | } else { |
79eb6904 | 13483 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
13484 | /* Do nothing, phy ID already set up in |
13485 | * tg3_get_eeprom_hw_cfg(). | |
13486 | */ | |
1da177e4 LT |
13487 | } else { |
13488 | struct subsys_tbl_ent *p; | |
13489 | ||
13490 | /* No eeprom signature? Try the hardcoded | |
13491 | * subsys device table. | |
13492 | */ | |
24daf2b0 | 13493 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
13494 | if (!p) |
13495 | return -ENODEV; | |
13496 | ||
13497 | tp->phy_id = p->phy_id; | |
13498 | if (!tp->phy_id || | |
79eb6904 | 13499 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13500 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
13501 | } |
13502 | } | |
13503 | ||
a6b68dab | 13504 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
5baa5e9a MC |
13505 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13506 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | |
13507 | (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
a6b68dab MC |
13508 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || |
13509 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
13510 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
13511 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
13512 | ||
e256f8a3 MC |
13513 | tg3_phy_init_link_config(tp); |
13514 | ||
f07e9af3 | 13515 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
63c3a66f JP |
13516 | !tg3_flag(tp, ENABLE_APE) && |
13517 | !tg3_flag(tp, ENABLE_ASF)) { | |
e2bf73e7 | 13518 | u32 bmsr, dummy; |
1da177e4 LT |
13519 | |
13520 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
13521 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
13522 | (bmsr & BMSR_LSTATUS)) | |
13523 | goto skip_phy_reset; | |
6aa20a22 | 13524 | |
1da177e4 LT |
13525 | err = tg3_phy_reset(tp); |
13526 | if (err) | |
13527 | return err; | |
13528 | ||
42b64a45 | 13529 | tg3_phy_set_wirespeed(tp); |
1da177e4 | 13530 | |
e2bf73e7 | 13531 | if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { |
42b64a45 MC |
13532 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, |
13533 | tp->link_config.flowctrl); | |
1da177e4 LT |
13534 | |
13535 | tg3_writephy(tp, MII_BMCR, | |
13536 | BMCR_ANENABLE | BMCR_ANRESTART); | |
13537 | } | |
1da177e4 LT |
13538 | } |
13539 | ||
13540 | skip_phy_reset: | |
79eb6904 | 13541 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
13542 | err = tg3_init_5401phy_dsp(tp); |
13543 | if (err) | |
13544 | return err; | |
1da177e4 | 13545 | |
1da177e4 LT |
13546 | err = tg3_init_5401phy_dsp(tp); |
13547 | } | |
13548 | ||
1da177e4 LT |
13549 | return err; |
13550 | } | |
13551 | ||
184b8904 | 13552 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 13553 | { |
a4a8bb15 | 13554 | u8 *vpd_data; |
4181b2c8 | 13555 | unsigned int block_end, rosize, len; |
535a490e | 13556 | u32 vpdlen; |
184b8904 | 13557 | int j, i = 0; |
a4a8bb15 | 13558 | |
535a490e | 13559 | vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); |
a4a8bb15 MC |
13560 | if (!vpd_data) |
13561 | goto out_no_vpd; | |
1da177e4 | 13562 | |
535a490e | 13563 | i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA); |
4181b2c8 MC |
13564 | if (i < 0) |
13565 | goto out_not_found; | |
1da177e4 | 13566 | |
4181b2c8 MC |
13567 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
13568 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
13569 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 13570 | |
535a490e | 13571 | if (block_end > vpdlen) |
4181b2c8 | 13572 | goto out_not_found; |
af2c6a4a | 13573 | |
184b8904 MC |
13574 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13575 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
13576 | if (j > 0) { | |
13577 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13578 | ||
13579 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13580 | if (j + len > block_end || len != 4 || | |
13581 | memcmp(&vpd_data[j], "1028", 4)) | |
13582 | goto partno; | |
13583 | ||
13584 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13585 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
13586 | if (j < 0) | |
13587 | goto partno; | |
13588 | ||
13589 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13590 | ||
13591 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13592 | if (j + len > block_end) | |
13593 | goto partno; | |
13594 | ||
13595 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
535a490e | 13596 | strncat(tp->fw_ver, " bc ", vpdlen - len - 1); |
184b8904 MC |
13597 | } |
13598 | ||
13599 | partno: | |
4181b2c8 MC |
13600 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13601 | PCI_VPD_RO_KEYWORD_PARTNO); | |
13602 | if (i < 0) | |
13603 | goto out_not_found; | |
af2c6a4a | 13604 | |
4181b2c8 | 13605 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 13606 | |
4181b2c8 MC |
13607 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
13608 | if (len > TG3_BPN_SIZE || | |
535a490e | 13609 | (len + i) > vpdlen) |
4181b2c8 | 13610 | goto out_not_found; |
1da177e4 | 13611 | |
4181b2c8 | 13612 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 13613 | |
1da177e4 | 13614 | out_not_found: |
a4a8bb15 | 13615 | kfree(vpd_data); |
37a949c5 | 13616 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
13617 | return; |
13618 | ||
13619 | out_no_vpd: | |
37a949c5 MC |
13620 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
13621 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
13622 | strcpy(tp->board_part_number, "BCM5717"); | |
13623 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
13624 | strcpy(tp->board_part_number, "BCM5718"); | |
13625 | else | |
13626 | goto nomatch; | |
13627 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
13628 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
13629 | strcpy(tp->board_part_number, "BCM57780"); | |
13630 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
13631 | strcpy(tp->board_part_number, "BCM57760"); | |
13632 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
13633 | strcpy(tp->board_part_number, "BCM57790"); | |
13634 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
13635 | strcpy(tp->board_part_number, "BCM57788"); | |
13636 | else | |
13637 | goto nomatch; | |
13638 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13639 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
13640 | strcpy(tp->board_part_number, "BCM57761"); | |
13641 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
13642 | strcpy(tp->board_part_number, "BCM57765"); | |
13643 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
13644 | strcpy(tp->board_part_number, "BCM57781"); | |
13645 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
13646 | strcpy(tp->board_part_number, "BCM57785"); | |
13647 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
13648 | strcpy(tp->board_part_number, "BCM57791"); | |
13649 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13650 | strcpy(tp->board_part_number, "BCM57795"); | |
13651 | else | |
13652 | goto nomatch; | |
55086ad9 MC |
13653 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) { |
13654 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) | |
13655 | strcpy(tp->board_part_number, "BCM57762"); | |
13656 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) | |
13657 | strcpy(tp->board_part_number, "BCM57766"); | |
13658 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) | |
13659 | strcpy(tp->board_part_number, "BCM57782"); | |
13660 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) | |
13661 | strcpy(tp->board_part_number, "BCM57786"); | |
13662 | else | |
13663 | goto nomatch; | |
37a949c5 | 13664 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
b5d3772c | 13665 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
13666 | } else { |
13667 | nomatch: | |
b5d3772c | 13668 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 13669 | } |
1da177e4 LT |
13670 | } |
13671 | ||
9c8a620e MC |
13672 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
13673 | { | |
13674 | u32 val; | |
13675 | ||
e4f34110 | 13676 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 13677 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 13678 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
13679 | val != 0) |
13680 | return 0; | |
13681 | ||
13682 | return 1; | |
13683 | } | |
13684 | ||
acd9c119 MC |
13685 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
13686 | { | |
ff3a7cb2 | 13687 | u32 val, offset, start, ver_offset; |
75f9936e | 13688 | int i, dst_off; |
ff3a7cb2 | 13689 | bool newver = false; |
acd9c119 MC |
13690 | |
13691 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
13692 | tg3_nvram_read(tp, 0x4, &start)) | |
13693 | return; | |
13694 | ||
13695 | offset = tg3_nvram_logical_addr(tp, offset); | |
13696 | ||
ff3a7cb2 | 13697 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
13698 | return; |
13699 | ||
ff3a7cb2 MC |
13700 | if ((val & 0xfc000000) == 0x0c000000) { |
13701 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
13702 | return; |
13703 | ||
ff3a7cb2 MC |
13704 | if (val == 0) |
13705 | newver = true; | |
13706 | } | |
13707 | ||
75f9936e MC |
13708 | dst_off = strlen(tp->fw_ver); |
13709 | ||
ff3a7cb2 | 13710 | if (newver) { |
75f9936e MC |
13711 | if (TG3_VER_SIZE - dst_off < 16 || |
13712 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
13713 | return; |
13714 | ||
13715 | offset = offset + ver_offset - start; | |
13716 | for (i = 0; i < 16; i += 4) { | |
13717 | __be32 v; | |
13718 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
13719 | return; | |
13720 | ||
75f9936e | 13721 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
13722 | } |
13723 | } else { | |
13724 | u32 major, minor; | |
13725 | ||
13726 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
13727 | return; | |
13728 | ||
13729 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
13730 | TG3_NVM_BCVER_MAJSFT; | |
13731 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
13732 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
13733 | "v%d.%02d", major, minor); | |
acd9c119 MC |
13734 | } |
13735 | } | |
13736 | ||
a6f6cb1c MC |
13737 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
13738 | { | |
13739 | u32 val, major, minor; | |
13740 | ||
13741 | /* Use native endian representation */ | |
13742 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
13743 | return; | |
13744 | ||
13745 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
13746 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
13747 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
13748 | TG3_NVM_HWSB_CFG1_MINSFT; | |
13749 | ||
13750 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
13751 | } | |
13752 | ||
dfe00d7d MC |
13753 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
13754 | { | |
13755 | u32 offset, major, minor, build; | |
13756 | ||
75f9936e | 13757 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
13758 | |
13759 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
13760 | return; | |
13761 | ||
13762 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
13763 | case TG3_EEPROM_SB_REVISION_0: | |
13764 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
13765 | break; | |
13766 | case TG3_EEPROM_SB_REVISION_2: | |
13767 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
13768 | break; | |
13769 | case TG3_EEPROM_SB_REVISION_3: | |
13770 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
13771 | break; | |
a4153d40 MC |
13772 | case TG3_EEPROM_SB_REVISION_4: |
13773 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
13774 | break; | |
13775 | case TG3_EEPROM_SB_REVISION_5: | |
13776 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
13777 | break; | |
bba226ac MC |
13778 | case TG3_EEPROM_SB_REVISION_6: |
13779 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
13780 | break; | |
dfe00d7d MC |
13781 | default: |
13782 | return; | |
13783 | } | |
13784 | ||
e4f34110 | 13785 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
13786 | return; |
13787 | ||
13788 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
13789 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
13790 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
13791 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
13792 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
13793 | ||
13794 | if (minor > 99 || build > 26) | |
13795 | return; | |
13796 | ||
75f9936e MC |
13797 | offset = strlen(tp->fw_ver); |
13798 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
13799 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
13800 | |
13801 | if (build > 0) { | |
75f9936e MC |
13802 | offset = strlen(tp->fw_ver); |
13803 | if (offset < TG3_VER_SIZE - 1) | |
13804 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
13805 | } |
13806 | } | |
13807 | ||
acd9c119 | 13808 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
13809 | { |
13810 | u32 val, offset, start; | |
acd9c119 | 13811 | int i, vlen; |
9c8a620e MC |
13812 | |
13813 | for (offset = TG3_NVM_DIR_START; | |
13814 | offset < TG3_NVM_DIR_END; | |
13815 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 13816 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
13817 | return; |
13818 | ||
9c8a620e MC |
13819 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
13820 | break; | |
13821 | } | |
13822 | ||
13823 | if (offset == TG3_NVM_DIR_END) | |
13824 | return; | |
13825 | ||
63c3a66f | 13826 | if (!tg3_flag(tp, 5705_PLUS)) |
9c8a620e | 13827 | start = 0x08000000; |
e4f34110 | 13828 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
13829 | return; |
13830 | ||
e4f34110 | 13831 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 13832 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 13833 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
13834 | return; |
13835 | ||
13836 | offset += val - start; | |
13837 | ||
acd9c119 | 13838 | vlen = strlen(tp->fw_ver); |
9c8a620e | 13839 | |
acd9c119 MC |
13840 | tp->fw_ver[vlen++] = ','; |
13841 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
13842 | |
13843 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
13844 | __be32 v; |
13845 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
13846 | return; |
13847 | ||
b9fc7dc5 | 13848 | offset += sizeof(v); |
c4e6575c | 13849 | |
acd9c119 MC |
13850 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
13851 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 13852 | break; |
c4e6575c | 13853 | } |
9c8a620e | 13854 | |
acd9c119 MC |
13855 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
13856 | vlen += sizeof(v); | |
c4e6575c | 13857 | } |
acd9c119 MC |
13858 | } |
13859 | ||
7fd76445 MC |
13860 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
13861 | { | |
13862 | int vlen; | |
13863 | u32 apedata; | |
ecc79648 | 13864 | char *fwtype; |
7fd76445 | 13865 | |
63c3a66f | 13866 | if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF)) |
7fd76445 MC |
13867 | return; |
13868 | ||
13869 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
13870 | if (apedata != APE_SEG_SIG_MAGIC) | |
13871 | return; | |
13872 | ||
13873 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
13874 | if (!(apedata & APE_FW_STATUS_READY)) | |
13875 | return; | |
13876 | ||
13877 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
13878 | ||
dc6d0744 | 13879 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
63c3a66f | 13880 | tg3_flag_set(tp, APE_HAS_NCSI); |
ecc79648 | 13881 | fwtype = "NCSI"; |
dc6d0744 | 13882 | } else { |
ecc79648 | 13883 | fwtype = "DASH"; |
dc6d0744 | 13884 | } |
ecc79648 | 13885 | |
7fd76445 MC |
13886 | vlen = strlen(tp->fw_ver); |
13887 | ||
ecc79648 MC |
13888 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
13889 | fwtype, | |
7fd76445 MC |
13890 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
13891 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
13892 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
13893 | (apedata & APE_FW_VERSION_BLDMSK)); | |
13894 | } | |
13895 | ||
acd9c119 MC |
13896 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
13897 | { | |
13898 | u32 val; | |
75f9936e | 13899 | bool vpd_vers = false; |
acd9c119 | 13900 | |
75f9936e MC |
13901 | if (tp->fw_ver[0] != 0) |
13902 | vpd_vers = true; | |
df259d8c | 13903 | |
63c3a66f | 13904 | if (tg3_flag(tp, NO_NVRAM)) { |
75f9936e | 13905 | strcat(tp->fw_ver, "sb"); |
df259d8c MC |
13906 | return; |
13907 | } | |
13908 | ||
acd9c119 MC |
13909 | if (tg3_nvram_read(tp, 0, &val)) |
13910 | return; | |
13911 | ||
13912 | if (val == TG3_EEPROM_MAGIC) | |
13913 | tg3_read_bc_ver(tp); | |
13914 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13915 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
13916 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
13917 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
13918 | else |
13919 | return; | |
13920 | ||
c9cab24e | 13921 | if (vpd_vers) |
75f9936e | 13922 | goto done; |
acd9c119 | 13923 | |
c9cab24e MC |
13924 | if (tg3_flag(tp, ENABLE_APE)) { |
13925 | if (tg3_flag(tp, ENABLE_ASF)) | |
13926 | tg3_read_dash_ver(tp); | |
13927 | } else if (tg3_flag(tp, ENABLE_ASF)) { | |
13928 | tg3_read_mgmtfw_ver(tp); | |
13929 | } | |
9c8a620e | 13930 | |
75f9936e | 13931 | done: |
9c8a620e | 13932 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
13933 | } |
13934 | ||
7cb32cf2 MC |
13935 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13936 | { | |
63c3a66f | 13937 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
de9f5230 | 13938 | return TG3_RX_RET_MAX_SIZE_5717; |
63c3a66f | 13939 | else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) |
de9f5230 | 13940 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 13941 | else |
de9f5230 | 13942 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
13943 | } |
13944 | ||
4143470c | 13945 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
13946 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
13947 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13948 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13949 | { }, | |
13950 | }; | |
13951 | ||
16c7fa7d MC |
13952 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
13953 | { | |
13954 | struct pci_dev *peer; | |
13955 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
13956 | ||
13957 | for (func = 0; func < 8; func++) { | |
13958 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
13959 | if (peer && peer != tp->pdev) | |
13960 | break; | |
13961 | pci_dev_put(peer); | |
13962 | } | |
13963 | /* 5704 can be configured in single-port mode, set peer to | |
13964 | * tp->pdev in that case. | |
13965 | */ | |
13966 | if (!peer) { | |
13967 | peer = tp->pdev; | |
13968 | return peer; | |
13969 | } | |
13970 | ||
13971 | /* | |
13972 | * We don't need to keep the refcount elevated; there's no way | |
13973 | * to remove one half of this device without removing the other | |
13974 | */ | |
13975 | pci_dev_put(peer); | |
13976 | ||
13977 | return peer; | |
13978 | } | |
13979 | ||
42b123b1 MC |
13980 | static void __devinit tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) |
13981 | { | |
13982 | tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; | |
13983 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { | |
13984 | u32 reg; | |
13985 | ||
13986 | /* All devices that use the alternate | |
13987 | * ASIC REV location have a CPMU. | |
13988 | */ | |
13989 | tg3_flag_set(tp, CPMU_PRESENT); | |
13990 | ||
13991 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
13992 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
13993 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
13994 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
13995 | reg = TG3PCI_GEN2_PRODID_ASICREV; | |
13996 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || | |
13997 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13998 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13999 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
14000 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
14001 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
14002 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || | |
14003 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || | |
14004 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || | |
14005 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) | |
14006 | reg = TG3PCI_GEN15_PRODID_ASICREV; | |
14007 | else | |
14008 | reg = TG3PCI_PRODID_ASICREV; | |
14009 | ||
14010 | pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); | |
14011 | } | |
14012 | ||
14013 | /* Wrong chip ID in 5752 A0. This code can be removed later | |
14014 | * as A0 is not in production. | |
14015 | */ | |
14016 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
14017 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
14018 | ||
14019 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14020 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14021 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
14022 | tg3_flag_set(tp, 5717_PLUS); | |
14023 | ||
14024 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
14025 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) | |
14026 | tg3_flag_set(tp, 57765_CLASS); | |
14027 | ||
14028 | if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS)) | |
14029 | tg3_flag_set(tp, 57765_PLUS); | |
14030 | ||
14031 | /* Intentionally exclude ASIC_REV_5906 */ | |
14032 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
14033 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
14034 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
14035 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
14036 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
14037 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
14038 | tg3_flag(tp, 57765_PLUS)) | |
14039 | tg3_flag_set(tp, 5755_PLUS); | |
14040 | ||
14041 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || | |
14042 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) | |
14043 | tg3_flag_set(tp, 5780_CLASS); | |
14044 | ||
14045 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14046 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14047 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || | |
14048 | tg3_flag(tp, 5755_PLUS) || | |
14049 | tg3_flag(tp, 5780_CLASS)) | |
14050 | tg3_flag_set(tp, 5750_PLUS); | |
14051 | ||
14052 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || | |
14053 | tg3_flag(tp, 5750_PLUS)) | |
14054 | tg3_flag_set(tp, 5705_PLUS); | |
14055 | } | |
14056 | ||
1da177e4 LT |
14057 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
14058 | { | |
1da177e4 | 14059 | u32 misc_ctrl_reg; |
1da177e4 LT |
14060 | u32 pci_state_reg, grc_misc_cfg; |
14061 | u32 val; | |
14062 | u16 pci_cmd; | |
5e7dfd0f | 14063 | int err; |
1da177e4 | 14064 | |
1da177e4 LT |
14065 | /* Force memory write invalidate off. If we leave it on, |
14066 | * then on 5700_BX chips we have to enable a workaround. | |
14067 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
14068 | * to match the cacheline size. The Broadcom driver have this | |
14069 | * workaround but turns MWI off all the times so never uses | |
14070 | * it. This seems to suggest that the workaround is insufficient. | |
14071 | */ | |
14072 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14073 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
14074 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14075 | ||
16821285 MC |
14076 | /* Important! -- Make sure register accesses are byteswapped |
14077 | * correctly. Also, for those chips that require it, make | |
14078 | * sure that indirect register accesses are enabled before | |
14079 | * the first operation. | |
1da177e4 LT |
14080 | */ |
14081 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14082 | &misc_ctrl_reg); | |
16821285 MC |
14083 | tp->misc_host_ctrl |= (misc_ctrl_reg & |
14084 | MISC_HOST_CTRL_CHIPREV); | |
14085 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14086 | tp->misc_host_ctrl); | |
1da177e4 | 14087 | |
42b123b1 | 14088 | tg3_detect_asic_rev(tp, misc_ctrl_reg); |
ff645bec | 14089 | |
6892914f MC |
14090 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
14091 | * we need to disable memory and use config. cycles | |
14092 | * only to access all registers. The 5702/03 chips | |
14093 | * can mistakenly decode the special cycles from the | |
14094 | * ICH chipsets as memory write cycles, causing corruption | |
14095 | * of register and memory space. Only certain ICH bridges | |
14096 | * will drive special cycles with non-zero data during the | |
14097 | * address phase which can fall within the 5703's address | |
14098 | * range. This is not an ICH bug as the PCI spec allows | |
14099 | * non-zero address during special cycles. However, only | |
14100 | * these ICH bridges are known to drive non-zero addresses | |
14101 | * during special cycles. | |
14102 | * | |
14103 | * Since special cycles do not cross PCI bridges, we only | |
14104 | * enable this workaround if the 5703 is on the secondary | |
14105 | * bus of these ICH bridges. | |
14106 | */ | |
14107 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
14108 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
14109 | static struct tg3_dev_id { | |
14110 | u32 vendor; | |
14111 | u32 device; | |
14112 | u32 rev; | |
14113 | } ich_chipsets[] = { | |
14114 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
14115 | PCI_ANY_ID }, | |
14116 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
14117 | PCI_ANY_ID }, | |
14118 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
14119 | 0xa }, | |
14120 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
14121 | PCI_ANY_ID }, | |
14122 | { }, | |
14123 | }; | |
14124 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
14125 | struct pci_dev *bridge = NULL; | |
14126 | ||
14127 | while (pci_id->vendor != 0) { | |
14128 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
14129 | bridge); | |
14130 | if (!bridge) { | |
14131 | pci_id++; | |
14132 | continue; | |
14133 | } | |
14134 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 14135 | if (bridge->revision > pci_id->rev) |
6892914f MC |
14136 | continue; |
14137 | } | |
14138 | if (bridge->subordinate && | |
14139 | (bridge->subordinate->number == | |
14140 | tp->pdev->bus->number)) { | |
63c3a66f | 14141 | tg3_flag_set(tp, ICH_WORKAROUND); |
6892914f MC |
14142 | pci_dev_put(bridge); |
14143 | break; | |
14144 | } | |
14145 | } | |
14146 | } | |
14147 | ||
6ff6f81d | 14148 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
41588ba1 MC |
14149 | static struct tg3_dev_id { |
14150 | u32 vendor; | |
14151 | u32 device; | |
14152 | } bridge_chipsets[] = { | |
14153 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
14154 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
14155 | { }, | |
14156 | }; | |
14157 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
14158 | struct pci_dev *bridge = NULL; | |
14159 | ||
14160 | while (pci_id->vendor != 0) { | |
14161 | bridge = pci_get_device(pci_id->vendor, | |
14162 | pci_id->device, | |
14163 | bridge); | |
14164 | if (!bridge) { | |
14165 | pci_id++; | |
14166 | continue; | |
14167 | } | |
14168 | if (bridge->subordinate && | |
14169 | (bridge->subordinate->number <= | |
14170 | tp->pdev->bus->number) && | |
14171 | (bridge->subordinate->subordinate >= | |
14172 | tp->pdev->bus->number)) { | |
63c3a66f | 14173 | tg3_flag_set(tp, 5701_DMA_BUG); |
41588ba1 MC |
14174 | pci_dev_put(bridge); |
14175 | break; | |
14176 | } | |
14177 | } | |
14178 | } | |
14179 | ||
4a29cc2e MC |
14180 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
14181 | * DMA addresses > 40-bit. This bridge may have other additional | |
14182 | * 57xx devices behind it in some 4-port NIC designs for example. | |
14183 | * Any tg3 device found behind the bridge will also need the 40-bit | |
14184 | * DMA workaround. | |
14185 | */ | |
42b123b1 | 14186 | if (tg3_flag(tp, 5780_CLASS)) { |
63c3a66f | 14187 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4cf78e4f | 14188 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 14189 | } else { |
4a29cc2e MC |
14190 | struct pci_dev *bridge = NULL; |
14191 | ||
14192 | do { | |
14193 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
14194 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
14195 | bridge); | |
14196 | if (bridge && bridge->subordinate && | |
14197 | (bridge->subordinate->number <= | |
14198 | tp->pdev->bus->number) && | |
14199 | (bridge->subordinate->subordinate >= | |
14200 | tp->pdev->bus->number)) { | |
63c3a66f | 14201 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4a29cc2e MC |
14202 | pci_dev_put(bridge); |
14203 | break; | |
14204 | } | |
14205 | } while (bridge); | |
14206 | } | |
4cf78e4f | 14207 | |
f6eb9b1f | 14208 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
3a1e19d3 | 14209 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) |
7544b097 MC |
14210 | tp->pdev_peer = tg3_find_peer(tp); |
14211 | ||
507399f1 | 14212 | /* Determine TSO capabilities */ |
a0512944 | 14213 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) |
4d163b75 | 14214 | ; /* Do nothing. HW bug. */ |
63c3a66f JP |
14215 | else if (tg3_flag(tp, 57765_PLUS)) |
14216 | tg3_flag_set(tp, HW_TSO_3); | |
14217 | else if (tg3_flag(tp, 5755_PLUS) || | |
e849cdc3 | 14218 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
63c3a66f JP |
14219 | tg3_flag_set(tp, HW_TSO_2); |
14220 | else if (tg3_flag(tp, 5750_PLUS)) { | |
14221 | tg3_flag_set(tp, HW_TSO_1); | |
14222 | tg3_flag_set(tp, TSO_BUG); | |
507399f1 MC |
14223 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && |
14224 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
63c3a66f | 14225 | tg3_flag_clear(tp, TSO_BUG); |
507399f1 MC |
14226 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14227 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
14228 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 14229 | tg3_flag_set(tp, TSO_BUG); |
507399f1 MC |
14230 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) |
14231 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
14232 | else | |
14233 | tp->fw_needed = FIRMWARE_TG3TSO; | |
14234 | } | |
14235 | ||
dabc5c67 | 14236 | /* Selectively allow TSO based on operating conditions */ |
6ff6f81d MC |
14237 | if (tg3_flag(tp, HW_TSO_1) || |
14238 | tg3_flag(tp, HW_TSO_2) || | |
14239 | tg3_flag(tp, HW_TSO_3) || | |
cf9ecf4b MC |
14240 | tp->fw_needed) { |
14241 | /* For firmware TSO, assume ASF is disabled. | |
14242 | * We'll disable TSO later if we discover ASF | |
14243 | * is enabled in tg3_get_eeprom_hw_cfg(). | |
14244 | */ | |
dabc5c67 | 14245 | tg3_flag_set(tp, TSO_CAPABLE); |
cf9ecf4b | 14246 | } else { |
dabc5c67 MC |
14247 | tg3_flag_clear(tp, TSO_CAPABLE); |
14248 | tg3_flag_clear(tp, TSO_BUG); | |
14249 | tp->fw_needed = NULL; | |
14250 | } | |
14251 | ||
14252 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
14253 | tp->fw_needed = FIRMWARE_TG3; | |
14254 | ||
507399f1 MC |
14255 | tp->irq_max = 1; |
14256 | ||
63c3a66f JP |
14257 | if (tg3_flag(tp, 5750_PLUS)) { |
14258 | tg3_flag_set(tp, SUPPORT_MSI); | |
7544b097 MC |
14259 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || |
14260 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
14261 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
14262 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
14263 | tp->pdev_peer == tp->pdev)) | |
63c3a66f | 14264 | tg3_flag_clear(tp, SUPPORT_MSI); |
7544b097 | 14265 | |
63c3a66f | 14266 | if (tg3_flag(tp, 5755_PLUS) || |
b5d3772c | 14267 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
63c3a66f | 14268 | tg3_flag_set(tp, 1SHOT_MSI); |
52c0fd83 | 14269 | } |
4f125f42 | 14270 | |
63c3a66f JP |
14271 | if (tg3_flag(tp, 57765_PLUS)) { |
14272 | tg3_flag_set(tp, SUPPORT_MSIX); | |
507399f1 | 14273 | tp->irq_max = TG3_IRQ_MAX_VECS; |
90415477 | 14274 | tg3_rss_init_dflt_indir_tbl(tp); |
507399f1 | 14275 | } |
f6eb9b1f | 14276 | } |
0e1406dd | 14277 | |
2ffcc981 | 14278 | if (tg3_flag(tp, 5755_PLUS)) |
63c3a66f | 14279 | tg3_flag_set(tp, SHORT_DMA_BUG); |
f6eb9b1f | 14280 | |
e31aa987 | 14281 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
a4cb428d | 14282 | tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; |
e31aa987 | 14283 | |
fa6b2aae MC |
14284 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
14285 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14286 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
63c3a66f | 14287 | tg3_flag_set(tp, LRG_PROD_RING_CAP); |
de9f5230 | 14288 | |
63c3a66f | 14289 | if (tg3_flag(tp, 57765_PLUS) && |
a0512944 | 14290 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0) |
63c3a66f | 14291 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); |
b703df6f | 14292 | |
63c3a66f JP |
14293 | if (!tg3_flag(tp, 5705_PLUS) || |
14294 | tg3_flag(tp, 5780_CLASS) || | |
14295 | tg3_flag(tp, USE_JUMBO_BDFLAG)) | |
14296 | tg3_flag_set(tp, JUMBO_CAPABLE); | |
0f893dc6 | 14297 | |
52f4490c MC |
14298 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14299 | &pci_state_reg); | |
14300 | ||
708ebb3a | 14301 | if (pci_is_pcie(tp->pdev)) { |
5e7dfd0f MC |
14302 | u16 lnkctl; |
14303 | ||
63c3a66f | 14304 | tg3_flag_set(tp, PCI_EXPRESS); |
5f5c51e3 | 14305 | |
5e7dfd0f | 14306 | pci_read_config_word(tp->pdev, |
708ebb3a | 14307 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
14308 | &lnkctl); |
14309 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
7196cd6c MC |
14310 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
14311 | ASIC_REV_5906) { | |
63c3a66f | 14312 | tg3_flag_clear(tp, HW_TSO_2); |
dabc5c67 | 14313 | tg3_flag_clear(tp, TSO_CAPABLE); |
7196cd6c | 14314 | } |
5e7dfd0f | 14315 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 14316 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
14317 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
14318 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
63c3a66f | 14319 | tg3_flag_set(tp, CLKREQ_BUG); |
614b0590 | 14320 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
63c3a66f | 14321 | tg3_flag_set(tp, L1PLLPD_EN); |
c7835a77 | 14322 | } |
52f4490c | 14323 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
708ebb3a JM |
14324 | /* BCM5785 devices are effectively PCIe devices, and should |
14325 | * follow PCIe codepaths, but do not have a PCIe capabilities | |
14326 | * section. | |
93a700a9 | 14327 | */ |
63c3a66f JP |
14328 | tg3_flag_set(tp, PCI_EXPRESS); |
14329 | } else if (!tg3_flag(tp, 5705_PLUS) || | |
14330 | tg3_flag(tp, 5780_CLASS)) { | |
52f4490c MC |
14331 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); |
14332 | if (!tp->pcix_cap) { | |
2445e461 MC |
14333 | dev_err(&tp->pdev->dev, |
14334 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
14335 | return -EIO; |
14336 | } | |
14337 | ||
14338 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
63c3a66f | 14339 | tg3_flag_set(tp, PCIX_MODE); |
52f4490c | 14340 | } |
1da177e4 | 14341 | |
399de50b MC |
14342 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
14343 | * reordering to the mailbox registers done by the host | |
14344 | * controller can cause major troubles. We read back from | |
14345 | * every mailbox register write to force the writes to be | |
14346 | * posted to the chip in order. | |
14347 | */ | |
4143470c | 14348 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
63c3a66f JP |
14349 | !tg3_flag(tp, PCI_EXPRESS)) |
14350 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
399de50b | 14351 | |
69fc4053 MC |
14352 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
14353 | &tp->pci_cacheline_sz); | |
14354 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
14355 | &tp->pci_lat_timer); | |
1da177e4 LT |
14356 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
14357 | tp->pci_lat_timer < 64) { | |
14358 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
14359 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
14360 | tp->pci_lat_timer); | |
1da177e4 LT |
14361 | } |
14362 | ||
16821285 MC |
14363 | /* Important! -- It is critical that the PCI-X hw workaround |
14364 | * situation is decided before the first MMIO register access. | |
14365 | */ | |
52f4490c MC |
14366 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
14367 | /* 5700 BX chips need to have their TX producer index | |
14368 | * mailboxes written twice to workaround a bug. | |
14369 | */ | |
63c3a66f | 14370 | tg3_flag_set(tp, TXD_MBOX_HWBUG); |
1da177e4 | 14371 | |
52f4490c | 14372 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
14373 | * |
14374 | * The workaround is to use indirect register accesses | |
14375 | * for all chip writes not to mailbox registers. | |
14376 | */ | |
63c3a66f | 14377 | if (tg3_flag(tp, PCIX_MODE)) { |
1da177e4 | 14378 | u32 pm_reg; |
1da177e4 | 14379 | |
63c3a66f | 14380 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14381 | |
14382 | /* The chip can have it's power management PCI config | |
14383 | * space registers clobbered due to this bug. | |
14384 | * So explicitly force the chip into D0 here. | |
14385 | */ | |
9974a356 MC |
14386 | pci_read_config_dword(tp->pdev, |
14387 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
14388 | &pm_reg); |
14389 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
14390 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
14391 | pci_write_config_dword(tp->pdev, |
14392 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
14393 | pm_reg); |
14394 | ||
14395 | /* Also, force SERR#/PERR# in PCI command. */ | |
14396 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14397 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
14398 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14399 | } | |
14400 | } | |
14401 | ||
1da177e4 | 14402 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
63c3a66f | 14403 | tg3_flag_set(tp, PCI_HIGH_SPEED); |
1da177e4 | 14404 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) |
63c3a66f | 14405 | tg3_flag_set(tp, PCI_32BIT); |
1da177e4 LT |
14406 | |
14407 | /* Chip-specific fixup from Broadcom driver */ | |
14408 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
14409 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
14410 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
14411 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
14412 | } | |
14413 | ||
1ee582d8 | 14414 | /* Default fast path register access methods */ |
20094930 | 14415 | tp->read32 = tg3_read32; |
1ee582d8 | 14416 | tp->write32 = tg3_write32; |
09ee929c | 14417 | tp->read32_mbox = tg3_read32; |
20094930 | 14418 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
14419 | tp->write32_tx_mbox = tg3_write32; |
14420 | tp->write32_rx_mbox = tg3_write32; | |
14421 | ||
14422 | /* Various workaround register access methods */ | |
63c3a66f | 14423 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) |
1ee582d8 | 14424 | tp->write32 = tg3_write_indirect_reg32; |
98efd8a6 | 14425 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
63c3a66f | 14426 | (tg3_flag(tp, PCI_EXPRESS) && |
98efd8a6 MC |
14427 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { |
14428 | /* | |
14429 | * Back to back register writes can cause problems on these | |
14430 | * chips, the workaround is to read back all reg writes | |
14431 | * except those to mailbox regs. | |
14432 | * | |
14433 | * See tg3_write_indirect_reg32(). | |
14434 | */ | |
1ee582d8 | 14435 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
14436 | } |
14437 | ||
63c3a66f | 14438 | if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { |
1ee582d8 | 14439 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
63c3a66f | 14440 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1ee582d8 MC |
14441 | tp->write32_rx_mbox = tg3_write_flush_reg32; |
14442 | } | |
20094930 | 14443 | |
63c3a66f | 14444 | if (tg3_flag(tp, ICH_WORKAROUND)) { |
6892914f MC |
14445 | tp->read32 = tg3_read_indirect_reg32; |
14446 | tp->write32 = tg3_write_indirect_reg32; | |
14447 | tp->read32_mbox = tg3_read_indirect_mbox; | |
14448 | tp->write32_mbox = tg3_write_indirect_mbox; | |
14449 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
14450 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
14451 | ||
14452 | iounmap(tp->regs); | |
22abe310 | 14453 | tp->regs = NULL; |
6892914f MC |
14454 | |
14455 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14456 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
14457 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14458 | } | |
b5d3772c MC |
14459 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14460 | tp->read32_mbox = tg3_read32_mbox_5906; | |
14461 | tp->write32_mbox = tg3_write32_mbox_5906; | |
14462 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
14463 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
14464 | } | |
6892914f | 14465 | |
bbadf503 | 14466 | if (tp->write32 == tg3_write_indirect_reg32 || |
63c3a66f | 14467 | (tg3_flag(tp, PCIX_MODE) && |
bbadf503 | 14468 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
f49639e6 | 14469 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
63c3a66f | 14470 | tg3_flag_set(tp, SRAM_USE_CONFIG); |
bbadf503 | 14471 | |
16821285 MC |
14472 | /* The memory arbiter has to be enabled in order for SRAM accesses |
14473 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
14474 | * sure it is enabled, but other entities such as system netboot | |
14475 | * code might disable it. | |
14476 | */ | |
14477 | val = tr32(MEMARB_MODE); | |
14478 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
14479 | ||
9dc5e342 MC |
14480 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; |
14481 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
14482 | tg3_flag(tp, 5780_CLASS)) { | |
14483 | if (tg3_flag(tp, PCIX_MODE)) { | |
14484 | pci_read_config_dword(tp->pdev, | |
14485 | tp->pcix_cap + PCI_X_STATUS, | |
14486 | &val); | |
14487 | tp->pci_fn = val & 0x7; | |
14488 | } | |
14489 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
14490 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | |
14491 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == | |
14492 | NIC_SRAM_CPMUSTAT_SIG) { | |
14493 | tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717; | |
14494 | tp->pci_fn = tp->pci_fn ? 1 : 0; | |
14495 | } | |
14496 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14497 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
14498 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | |
14499 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == | |
14500 | NIC_SRAM_CPMUSTAT_SIG) { | |
14501 | tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> | |
14502 | TG3_CPMU_STATUS_FSHFT_5719; | |
14503 | } | |
69f11c99 MC |
14504 | } |
14505 | ||
7d0c41ef | 14506 | /* Get eeprom hw config before calling tg3_set_power_state(). |
63c3a66f | 14507 | * In particular, the TG3_FLAG_IS_NIC flag must be |
7d0c41ef MC |
14508 | * determined before calling tg3_set_power_state() so that |
14509 | * we know whether or not to switch out of Vaux power. | |
14510 | * When the flag is set, it means that GPIO1 is used for eeprom | |
14511 | * write protect and also implies that it is a LOM where GPIOs | |
14512 | * are not used to switch power. | |
6aa20a22 | 14513 | */ |
7d0c41ef MC |
14514 | tg3_get_eeprom_hw_cfg(tp); |
14515 | ||
cf9ecf4b MC |
14516 | if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) { |
14517 | tg3_flag_clear(tp, TSO_CAPABLE); | |
14518 | tg3_flag_clear(tp, TSO_BUG); | |
14519 | tp->fw_needed = NULL; | |
14520 | } | |
14521 | ||
63c3a66f | 14522 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
14523 | /* Allow reads and writes to the |
14524 | * APE register and memory space. | |
14525 | */ | |
14526 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
14527 | PCISTATE_ALLOW_APE_SHMEM_WR | |
14528 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
14529 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14530 | pci_state_reg); | |
c9cab24e MC |
14531 | |
14532 | tg3_ape_lock_init(tp); | |
0d3031d9 MC |
14533 | } |
14534 | ||
16821285 MC |
14535 | /* Set up tp->grc_local_ctrl before calling |
14536 | * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high | |
14537 | * will bring 5700's external PHY out of reset. | |
314fba34 MC |
14538 | * It is also used as eeprom write protect on LOMs. |
14539 | */ | |
14540 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
6ff6f81d | 14541 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
63c3a66f | 14542 | tg3_flag(tp, EEPROM_WRITE_PROT)) |
314fba34 MC |
14543 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
14544 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
14545 | /* Unused GPIO3 must be driven as output on 5752 because there |
14546 | * are no pull-up resistors on unused GPIO pins. | |
14547 | */ | |
14548 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
14549 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 14550 | |
321d32a0 | 14551 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd | 14552 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
55086ad9 | 14553 | tg3_flag(tp, 57765_CLASS)) |
af36e6b6 MC |
14554 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
14555 | ||
8d519ab2 MC |
14556 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
14557 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
14558 | /* Turn off the debug UART. */ |
14559 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
63c3a66f | 14560 | if (tg3_flag(tp, IS_NIC)) |
5f0c4a3c MC |
14561 | /* Keep VMain power. */ |
14562 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
14563 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
14564 | } | |
14565 | ||
16821285 MC |
14566 | /* Switch out of Vaux if it is a NIC */ |
14567 | tg3_pwrsrc_switch_to_vmain(tp); | |
1da177e4 | 14568 | |
1da177e4 LT |
14569 | /* Derive initial jumbo mode from MTU assigned in |
14570 | * ether_setup() via the alloc_etherdev() call | |
14571 | */ | |
63c3a66f JP |
14572 | if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) |
14573 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
1da177e4 LT |
14574 | |
14575 | /* Determine WakeOnLan speed to use. */ | |
14576 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14577 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
14578 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
14579 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
63c3a66f | 14580 | tg3_flag_clear(tp, WOL_SPEED_100MB); |
1da177e4 | 14581 | } else { |
63c3a66f | 14582 | tg3_flag_set(tp, WOL_SPEED_100MB); |
1da177e4 LT |
14583 | } |
14584 | ||
7f97a4bd | 14585 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 14586 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 14587 | |
1da177e4 | 14588 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
6ff6f81d MC |
14589 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
14590 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
1da177e4 | 14591 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && |
747e8f8b | 14592 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
14593 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
14594 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
14595 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
14596 | |
14597 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
14598 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 14599 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 14600 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 14601 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 14602 | |
63c3a66f | 14603 | if (tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 14604 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 14605 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 14606 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
63c3a66f | 14607 | !tg3_flag(tp, 57765_PLUS)) { |
c424cb24 | 14608 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 14609 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
14610 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
14611 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
14612 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
14613 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 14614 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 14615 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 14616 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 14617 | } else |
f07e9af3 | 14618 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 14619 | } |
1da177e4 | 14620 | |
b2a5c19c MC |
14621 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14622 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
14623 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
14624 | if (tp->phy_otp == 0) | |
14625 | tp->phy_otp = TG3_OTP_DEFAULT; | |
14626 | } | |
14627 | ||
63c3a66f | 14628 | if (tg3_flag(tp, CPMU_PRESENT)) |
8ef21428 MC |
14629 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
14630 | else | |
14631 | tp->mi_mode = MAC_MI_MODE_BASE; | |
14632 | ||
1da177e4 | 14633 | tp->coalesce_mode = 0; |
1da177e4 LT |
14634 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
14635 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
14636 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
14637 | ||
4d958473 MC |
14638 | /* Set these bits to enable statistics workaround. */ |
14639 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14640 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
14641 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
14642 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
14643 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
14644 | } | |
14645 | ||
321d32a0 MC |
14646 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
14647 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
63c3a66f | 14648 | tg3_flag_set(tp, USE_PHYLIB); |
57e6983c | 14649 | |
158d7abd MC |
14650 | err = tg3_mdio_init(tp); |
14651 | if (err) | |
14652 | return err; | |
1da177e4 LT |
14653 | |
14654 | /* Initialize data/descriptor byte/word swapping. */ | |
14655 | val = tr32(GRC_MODE); | |
f2096f94 MC |
14656 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
14657 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
14658 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
14659 | GRC_MODE_B2HRX_ENABLE | | |
14660 | GRC_MODE_HTX2B_ENABLE | | |
14661 | GRC_MODE_HOST_STACKUP); | |
14662 | else | |
14663 | val &= GRC_MODE_HOST_STACKUP; | |
14664 | ||
1da177e4 LT |
14665 | tw32(GRC_MODE, val | tp->grc_mode); |
14666 | ||
14667 | tg3_switch_clocks(tp); | |
14668 | ||
14669 | /* Clear this out for sanity. */ | |
14670 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14671 | ||
14672 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
14673 | &pci_state_reg); | |
14674 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
63c3a66f | 14675 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { |
1da177e4 LT |
14676 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); |
14677 | ||
14678 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
14679 | chiprevid == CHIPREV_ID_5701_B0 || | |
14680 | chiprevid == CHIPREV_ID_5701_B2 || | |
14681 | chiprevid == CHIPREV_ID_5701_B5) { | |
14682 | void __iomem *sram_base; | |
14683 | ||
14684 | /* Write some dummy words into the SRAM status block | |
14685 | * area, see if it reads back correctly. If the return | |
14686 | * value is bad, force enable the PCIX workaround. | |
14687 | */ | |
14688 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
14689 | ||
14690 | writel(0x00000000, sram_base); | |
14691 | writel(0x00000000, sram_base + 4); | |
14692 | writel(0xffffffff, sram_base + 4); | |
14693 | if (readl(sram_base) != 0x00000000) | |
63c3a66f | 14694 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14695 | } |
14696 | } | |
14697 | ||
14698 | udelay(50); | |
14699 | tg3_nvram_init(tp); | |
14700 | ||
14701 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
14702 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
14703 | ||
1da177e4 LT |
14704 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
14705 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
14706 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
63c3a66f | 14707 | tg3_flag_set(tp, IS_5788); |
1da177e4 | 14708 | |
63c3a66f | 14709 | if (!tg3_flag(tp, IS_5788) && |
6ff6f81d | 14710 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
63c3a66f JP |
14711 | tg3_flag_set(tp, TAGGED_STATUS); |
14712 | if (tg3_flag(tp, TAGGED_STATUS)) { | |
fac9b83e DM |
14713 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | |
14714 | HOSTCC_MODE_CLRTICK_TXBD); | |
14715 | ||
14716 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
14717 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14718 | tp->misc_host_ctrl); | |
14719 | } | |
14720 | ||
3bda1258 | 14721 | /* Preserve the APE MAC_MODE bits */ |
63c3a66f | 14722 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b | 14723 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 | 14724 | else |
6e01b20b | 14725 | tp->mac_mode = 0; |
3bda1258 | 14726 | |
1da177e4 LT |
14727 | /* these are limited to 10/100 only */ |
14728 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14729 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14730 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14731 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14732 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
14733 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
14734 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
14735 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14736 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
14737 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
14738 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 14739 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
14740 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
14741 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
f07e9af3 MC |
14742 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
14743 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
1da177e4 LT |
14744 | |
14745 | err = tg3_phy_probe(tp); | |
14746 | if (err) { | |
2445e461 | 14747 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 14748 | /* ... but do not return immediately ... */ |
b02fd9e3 | 14749 | tg3_mdio_fini(tp); |
1da177e4 LT |
14750 | } |
14751 | ||
184b8904 | 14752 | tg3_read_vpd(tp); |
c4e6575c | 14753 | tg3_read_fw_ver(tp); |
1da177e4 | 14754 | |
f07e9af3 MC |
14755 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
14756 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
14757 | } else { |
14758 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 14759 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 14760 | else |
f07e9af3 | 14761 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
14762 | } |
14763 | ||
14764 | /* 5700 {AX,BX} chips have a broken status block link | |
14765 | * change bit implementation, so we must use the | |
14766 | * status register in those cases. | |
14767 | */ | |
14768 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
63c3a66f | 14769 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 | 14770 | else |
63c3a66f | 14771 | tg3_flag_clear(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14772 | |
14773 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
14774 | * have to force the link status polling mechanism based | |
14775 | * upon subsystem IDs. | |
14776 | */ | |
14777 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 14778 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
14779 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
14780 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
63c3a66f | 14781 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14782 | } |
14783 | ||
14784 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 14785 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
63c3a66f | 14786 | tg3_flag_set(tp, POLL_SERDES); |
1da177e4 | 14787 | else |
63c3a66f | 14788 | tg3_flag_clear(tp, POLL_SERDES); |
1da177e4 | 14789 | |
9205fd9c | 14790 | tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; |
d2757fc4 | 14791 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 14792 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
63c3a66f | 14793 | tg3_flag(tp, PCIX_MODE)) { |
9205fd9c | 14794 | tp->rx_offset = NET_SKB_PAD; |
d2757fc4 | 14795 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 14796 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
14797 | #endif |
14798 | } | |
1da177e4 | 14799 | |
2c49a44d MC |
14800 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
14801 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
14802 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
14803 | ||
2c49a44d | 14804 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
14805 | |
14806 | /* Increment the rx prod index on the rx std ring by at most | |
14807 | * 8 for these chips to workaround hw errata. | |
14808 | */ | |
14809 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14810 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14811 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
14812 | tp->rx_std_max_post = 8; | |
14813 | ||
63c3a66f | 14814 | if (tg3_flag(tp, ASPM_WORKAROUND)) |
8ed5d97e MC |
14815 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & |
14816 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
14817 | ||
1da177e4 LT |
14818 | return err; |
14819 | } | |
14820 | ||
49b6e95f | 14821 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14822 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
14823 | { | |
14824 | struct net_device *dev = tp->dev; | |
14825 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 14826 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 14827 | const unsigned char *addr; |
49b6e95f DM |
14828 | int len; |
14829 | ||
14830 | addr = of_get_property(dp, "local-mac-address", &len); | |
14831 | if (addr && len == 6) { | |
14832 | memcpy(dev->dev_addr, addr, 6); | |
14833 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
14834 | return 0; | |
1da177e4 LT |
14835 | } |
14836 | return -ENODEV; | |
14837 | } | |
14838 | ||
14839 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
14840 | { | |
14841 | struct net_device *dev = tp->dev; | |
14842 | ||
14843 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 14844 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
14845 | return 0; |
14846 | } | |
14847 | #endif | |
14848 | ||
14849 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
14850 | { | |
14851 | struct net_device *dev = tp->dev; | |
14852 | u32 hi, lo, mac_offset; | |
008652b3 | 14853 | int addr_ok = 0; |
1da177e4 | 14854 | |
49b6e95f | 14855 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14856 | if (!tg3_get_macaddr_sparc(tp)) |
14857 | return 0; | |
14858 | #endif | |
14859 | ||
14860 | mac_offset = 0x7c; | |
6ff6f81d | 14861 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
63c3a66f | 14862 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 LT |
14863 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
14864 | mac_offset = 0xcc; | |
14865 | if (tg3_nvram_lock(tp)) | |
14866 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
14867 | else | |
14868 | tg3_nvram_unlock(tp); | |
63c3a66f | 14869 | } else if (tg3_flag(tp, 5717_PLUS)) { |
69f11c99 | 14870 | if (tp->pci_fn & 1) |
a1b950d5 | 14871 | mac_offset = 0xcc; |
69f11c99 | 14872 | if (tp->pci_fn > 1) |
a50d0796 | 14873 | mac_offset += 0x18c; |
a1b950d5 | 14874 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 14875 | mac_offset = 0x10; |
1da177e4 LT |
14876 | |
14877 | /* First try to get it from MAC address mailbox. */ | |
14878 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
14879 | if ((hi >> 16) == 0x484b) { | |
14880 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14881 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
14882 | ||
14883 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
14884 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14885 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14886 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14887 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 14888 | |
008652b3 MC |
14889 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
14890 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
14891 | } | |
14892 | if (!addr_ok) { | |
14893 | /* Next, try NVRAM. */ | |
63c3a66f | 14894 | if (!tg3_flag(tp, NO_NVRAM) && |
df259d8c | 14895 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && |
6d348f2c | 14896 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
14897 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
14898 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
14899 | } |
14900 | /* Finally just fetch it out of the MAC control regs. */ | |
14901 | else { | |
14902 | hi = tr32(MAC_ADDR_0_HIGH); | |
14903 | lo = tr32(MAC_ADDR_0_LOW); | |
14904 | ||
14905 | dev->dev_addr[5] = lo & 0xff; | |
14906 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14907 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14908 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14909 | dev->dev_addr[1] = hi & 0xff; | |
14910 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14911 | } | |
1da177e4 LT |
14912 | } |
14913 | ||
14914 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 14915 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14916 | if (!tg3_get_default_macaddr_sparc(tp)) |
14917 | return 0; | |
14918 | #endif | |
14919 | return -EINVAL; | |
14920 | } | |
2ff43697 | 14921 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
14922 | return 0; |
14923 | } | |
14924 | ||
59e6b434 DM |
14925 | #define BOUNDARY_SINGLE_CACHELINE 1 |
14926 | #define BOUNDARY_MULTI_CACHELINE 2 | |
14927 | ||
14928 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
14929 | { | |
14930 | int cacheline_size; | |
14931 | u8 byte; | |
14932 | int goal; | |
14933 | ||
14934 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
14935 | if (byte == 0) | |
14936 | cacheline_size = 1024; | |
14937 | else | |
14938 | cacheline_size = (int) byte * 4; | |
14939 | ||
14940 | /* On 5703 and later chips, the boundary bits have no | |
14941 | * effect. | |
14942 | */ | |
14943 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14944 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
63c3a66f | 14945 | !tg3_flag(tp, PCI_EXPRESS)) |
59e6b434 DM |
14946 | goto out; |
14947 | ||
14948 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
14949 | goal = BOUNDARY_MULTI_CACHELINE; | |
14950 | #else | |
14951 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
14952 | goal = BOUNDARY_SINGLE_CACHELINE; | |
14953 | #else | |
14954 | goal = 0; | |
14955 | #endif | |
14956 | #endif | |
14957 | ||
63c3a66f | 14958 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
14959 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
14960 | goto out; | |
14961 | } | |
14962 | ||
59e6b434 DM |
14963 | if (!goal) |
14964 | goto out; | |
14965 | ||
14966 | /* PCI controllers on most RISC systems tend to disconnect | |
14967 | * when a device tries to burst across a cache-line boundary. | |
14968 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
14969 | * | |
14970 | * Unfortunately, for PCI-E there are only limited | |
14971 | * write-side controls for this, and thus for reads | |
14972 | * we will still get the disconnects. We'll also waste | |
14973 | * these PCI cycles for both read and write for chips | |
14974 | * other than 5700 and 5701 which do not implement the | |
14975 | * boundary bits. | |
14976 | */ | |
63c3a66f | 14977 | if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14978 | switch (cacheline_size) { |
14979 | case 16: | |
14980 | case 32: | |
14981 | case 64: | |
14982 | case 128: | |
14983 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14984 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
14985 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
14986 | } else { | |
14987 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14988 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14989 | } | |
14990 | break; | |
14991 | ||
14992 | case 256: | |
14993 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
14994 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
14995 | break; | |
14996 | ||
14997 | default: | |
14998 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14999 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
15000 | break; | |
855e1111 | 15001 | } |
63c3a66f | 15002 | } else if (tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
15003 | switch (cacheline_size) { |
15004 | case 16: | |
15005 | case 32: | |
15006 | case 64: | |
15007 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15008 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
15009 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
15010 | break; | |
15011 | } | |
15012 | /* fallthrough */ | |
15013 | case 128: | |
15014 | default: | |
15015 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
15016 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
15017 | break; | |
855e1111 | 15018 | } |
59e6b434 DM |
15019 | } else { |
15020 | switch (cacheline_size) { | |
15021 | case 16: | |
15022 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15023 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
15024 | DMA_RWCTRL_WRITE_BNDRY_16); | |
15025 | break; | |
15026 | } | |
15027 | /* fallthrough */ | |
15028 | case 32: | |
15029 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15030 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
15031 | DMA_RWCTRL_WRITE_BNDRY_32); | |
15032 | break; | |
15033 | } | |
15034 | /* fallthrough */ | |
15035 | case 64: | |
15036 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15037 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
15038 | DMA_RWCTRL_WRITE_BNDRY_64); | |
15039 | break; | |
15040 | } | |
15041 | /* fallthrough */ | |
15042 | case 128: | |
15043 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15044 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
15045 | DMA_RWCTRL_WRITE_BNDRY_128); | |
15046 | break; | |
15047 | } | |
15048 | /* fallthrough */ | |
15049 | case 256: | |
15050 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
15051 | DMA_RWCTRL_WRITE_BNDRY_256); | |
15052 | break; | |
15053 | case 512: | |
15054 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
15055 | DMA_RWCTRL_WRITE_BNDRY_512); | |
15056 | break; | |
15057 | case 1024: | |
15058 | default: | |
15059 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
15060 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
15061 | break; | |
855e1111 | 15062 | } |
59e6b434 DM |
15063 | } |
15064 | ||
15065 | out: | |
15066 | return val; | |
15067 | } | |
15068 | ||
1da177e4 LT |
15069 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
15070 | { | |
15071 | struct tg3_internal_buffer_desc test_desc; | |
15072 | u32 sram_dma_descs; | |
15073 | int i, ret; | |
15074 | ||
15075 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
15076 | ||
15077 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
15078 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
15079 | tw32(RDMAC_STATUS, 0); | |
15080 | tw32(WDMAC_STATUS, 0); | |
15081 | ||
15082 | tw32(BUFMGR_MODE, 0); | |
15083 | tw32(FTQ_RESET, 0); | |
15084 | ||
15085 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
15086 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
15087 | test_desc.nic_mbuf = 0x00002100; | |
15088 | test_desc.len = size; | |
15089 | ||
15090 | /* | |
15091 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
15092 | * the *second* time the tg3 driver was getting loaded after an | |
15093 | * initial scan. | |
15094 | * | |
15095 | * Broadcom tells me: | |
15096 | * ...the DMA engine is connected to the GRC block and a DMA | |
15097 | * reset may affect the GRC block in some unpredictable way... | |
15098 | * The behavior of resets to individual blocks has not been tested. | |
15099 | * | |
15100 | * Broadcom noted the GRC reset will also reset all sub-components. | |
15101 | */ | |
15102 | if (to_device) { | |
15103 | test_desc.cqid_sqid = (13 << 8) | 2; | |
15104 | ||
15105 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
15106 | udelay(40); | |
15107 | } else { | |
15108 | test_desc.cqid_sqid = (16 << 8) | 7; | |
15109 | ||
15110 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
15111 | udelay(40); | |
15112 | } | |
15113 | test_desc.flags = 0x00000005; | |
15114 | ||
15115 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
15116 | u32 val; | |
15117 | ||
15118 | val = *(((u32 *)&test_desc) + i); | |
15119 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
15120 | sram_dma_descs + (i * sizeof(u32))); | |
15121 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
15122 | } | |
15123 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
15124 | ||
859a5887 | 15125 | if (to_device) |
1da177e4 | 15126 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 15127 | else |
1da177e4 | 15128 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
15129 | |
15130 | ret = -ENODEV; | |
15131 | for (i = 0; i < 40; i++) { | |
15132 | u32 val; | |
15133 | ||
15134 | if (to_device) | |
15135 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
15136 | else | |
15137 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
15138 | if ((val & 0xffff) == sram_dma_descs) { | |
15139 | ret = 0; | |
15140 | break; | |
15141 | } | |
15142 | ||
15143 | udelay(100); | |
15144 | } | |
15145 | ||
15146 | return ret; | |
15147 | } | |
15148 | ||
ded7340d | 15149 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 15150 | |
4143470c | 15151 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
15152 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
15153 | { }, | |
15154 | }; | |
15155 | ||
1da177e4 LT |
15156 | static int __devinit tg3_test_dma(struct tg3 *tp) |
15157 | { | |
15158 | dma_addr_t buf_dma; | |
59e6b434 | 15159 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 15160 | int ret = 0; |
1da177e4 | 15161 | |
4bae65c8 MC |
15162 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
15163 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
15164 | if (!buf) { |
15165 | ret = -ENOMEM; | |
15166 | goto out_nofree; | |
15167 | } | |
15168 | ||
15169 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
15170 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
15171 | ||
59e6b434 | 15172 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 15173 | |
63c3a66f | 15174 | if (tg3_flag(tp, 57765_PLUS)) |
cbf9ca6c MC |
15175 | goto out; |
15176 | ||
63c3a66f | 15177 | if (tg3_flag(tp, PCI_EXPRESS)) { |
1da177e4 LT |
15178 | /* DMA read watermark not used on PCIE */ |
15179 | tp->dma_rwctrl |= 0x00180000; | |
63c3a66f | 15180 | } else if (!tg3_flag(tp, PCIX_MODE)) { |
85e94ced MC |
15181 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
15182 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
15183 | tp->dma_rwctrl |= 0x003f0000; |
15184 | else | |
15185 | tp->dma_rwctrl |= 0x003f000f; | |
15186 | } else { | |
15187 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
15188 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
15189 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 15190 | u32 read_water = 0x7; |
1da177e4 | 15191 | |
4a29cc2e MC |
15192 | /* If the 5704 is behind the EPB bridge, we can |
15193 | * do the less restrictive ONE_DMA workaround for | |
15194 | * better performance. | |
15195 | */ | |
63c3a66f | 15196 | if (tg3_flag(tp, 40BIT_DMA_BUG) && |
4a29cc2e MC |
15197 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
15198 | tp->dma_rwctrl |= 0x8000; | |
15199 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
15200 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
15201 | ||
49afdeb6 MC |
15202 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
15203 | read_water = 4; | |
59e6b434 | 15204 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
15205 | tp->dma_rwctrl |= |
15206 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
15207 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
15208 | (1 << 23); | |
4cf78e4f MC |
15209 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
15210 | /* 5780 always in PCIX mode */ | |
15211 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
15212 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
15213 | /* 5714 always in PCIX mode */ | |
15214 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
15215 | } else { |
15216 | tp->dma_rwctrl |= 0x001b000f; | |
15217 | } | |
15218 | } | |
15219 | ||
15220 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
15221 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
15222 | tp->dma_rwctrl &= 0xfffffff0; | |
15223 | ||
15224 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
15225 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
15226 | /* Remove this if it causes problems for some boards. */ | |
15227 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
15228 | ||
15229 | /* On 5700/5701 chips, we need to set this bit. | |
15230 | * Otherwise the chip will issue cacheline transactions | |
15231 | * to streamable DMA memory with not all the byte | |
15232 | * enables turned on. This is an error on several | |
15233 | * RISC PCI controllers, in particular sparc64. | |
15234 | * | |
15235 | * On 5703/5704 chips, this bit has been reassigned | |
15236 | * a different meaning. In particular, it is used | |
15237 | * on those chips to enable a PCI-X workaround. | |
15238 | */ | |
15239 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
15240 | } | |
15241 | ||
15242 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15243 | ||
15244 | #if 0 | |
15245 | /* Unneeded, already done by tg3_get_invariants. */ | |
15246 | tg3_switch_clocks(tp); | |
15247 | #endif | |
15248 | ||
1da177e4 LT |
15249 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
15250 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
15251 | goto out; | |
15252 | ||
59e6b434 DM |
15253 | /* It is best to perform DMA test with maximum write burst size |
15254 | * to expose the 5700/5701 write DMA bug. | |
15255 | */ | |
15256 | saved_dma_rwctrl = tp->dma_rwctrl; | |
15257 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
15258 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15259 | ||
1da177e4 LT |
15260 | while (1) { |
15261 | u32 *p = buf, i; | |
15262 | ||
15263 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
15264 | p[i] = i; | |
15265 | ||
15266 | /* Send the buffer to the chip. */ | |
15267 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
15268 | if (ret) { | |
2445e461 MC |
15269 | dev_err(&tp->pdev->dev, |
15270 | "%s: Buffer write failed. err = %d\n", | |
15271 | __func__, ret); | |
1da177e4 LT |
15272 | break; |
15273 | } | |
15274 | ||
15275 | #if 0 | |
15276 | /* validate data reached card RAM correctly. */ | |
15277 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
15278 | u32 val; | |
15279 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
15280 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
15281 | dev_err(&tp->pdev->dev, |
15282 | "%s: Buffer corrupted on device! " | |
15283 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
15284 | /* ret = -ENODEV here? */ |
15285 | } | |
15286 | p[i] = 0; | |
15287 | } | |
15288 | #endif | |
15289 | /* Now read it back. */ | |
15290 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
15291 | if (ret) { | |
5129c3a3 MC |
15292 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
15293 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
15294 | break; |
15295 | } | |
15296 | ||
15297 | /* Verify it. */ | |
15298 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
15299 | if (p[i] == i) | |
15300 | continue; | |
15301 | ||
59e6b434 DM |
15302 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
15303 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
15304 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
15305 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
15306 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15307 | break; | |
15308 | } else { | |
2445e461 MC |
15309 | dev_err(&tp->pdev->dev, |
15310 | "%s: Buffer corrupted on read back! " | |
15311 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
15312 | ret = -ENODEV; |
15313 | goto out; | |
15314 | } | |
15315 | } | |
15316 | ||
15317 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
15318 | /* Success. */ | |
15319 | ret = 0; | |
15320 | break; | |
15321 | } | |
15322 | } | |
59e6b434 DM |
15323 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
15324 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
15325 | /* DMA test passed without adjusting DMA boundary, | |
6d1cfbab MC |
15326 | * now look for chipsets that are known to expose the |
15327 | * DMA bug without failing the test. | |
59e6b434 | 15328 | */ |
4143470c | 15329 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
15330 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
15331 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 15332 | } else { |
6d1cfbab MC |
15333 | /* Safe to use the calculated DMA boundary. */ |
15334 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 15335 | } |
6d1cfbab | 15336 | |
59e6b434 DM |
15337 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
15338 | } | |
1da177e4 LT |
15339 | |
15340 | out: | |
4bae65c8 | 15341 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
15342 | out_nofree: |
15343 | return ret; | |
15344 | } | |
15345 | ||
1da177e4 LT |
15346 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
15347 | { | |
63c3a66f | 15348 | if (tg3_flag(tp, 57765_PLUS)) { |
666bc831 MC |
15349 | tp->bufmgr_config.mbuf_read_dma_low_water = |
15350 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15351 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15352 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
15353 | tp->bufmgr_config.mbuf_high_water = | |
15354 | DEFAULT_MB_HIGH_WATER_57765; | |
15355 | ||
15356 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15357 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15358 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15359 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
15360 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15361 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
63c3a66f | 15362 | } else if (tg3_flag(tp, 5705_PLUS)) { |
fdfec172 MC |
15363 | tp->bufmgr_config.mbuf_read_dma_low_water = |
15364 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15365 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15366 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
15367 | tp->bufmgr_config.mbuf_high_water = | |
15368 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
15369 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
15370 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15371 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
15372 | tp->bufmgr_config.mbuf_high_water = | |
15373 | DEFAULT_MB_HIGH_WATER_5906; | |
15374 | } | |
fdfec172 MC |
15375 | |
15376 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15377 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
15378 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15379 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
15380 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15381 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
15382 | } else { | |
15383 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
15384 | DEFAULT_MB_RDMA_LOW_WATER; | |
15385 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15386 | DEFAULT_MB_MACRX_LOW_WATER; | |
15387 | tp->bufmgr_config.mbuf_high_water = | |
15388 | DEFAULT_MB_HIGH_WATER; | |
15389 | ||
15390 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15391 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
15392 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15393 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
15394 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15395 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
15396 | } | |
1da177e4 LT |
15397 | |
15398 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
15399 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
15400 | } | |
15401 | ||
15402 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
15403 | { | |
79eb6904 MC |
15404 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
15405 | case TG3_PHY_ID_BCM5400: return "5400"; | |
15406 | case TG3_PHY_ID_BCM5401: return "5401"; | |
15407 | case TG3_PHY_ID_BCM5411: return "5411"; | |
15408 | case TG3_PHY_ID_BCM5701: return "5701"; | |
15409 | case TG3_PHY_ID_BCM5703: return "5703"; | |
15410 | case TG3_PHY_ID_BCM5704: return "5704"; | |
15411 | case TG3_PHY_ID_BCM5705: return "5705"; | |
15412 | case TG3_PHY_ID_BCM5750: return "5750"; | |
15413 | case TG3_PHY_ID_BCM5752: return "5752"; | |
15414 | case TG3_PHY_ID_BCM5714: return "5714"; | |
15415 | case TG3_PHY_ID_BCM5780: return "5780"; | |
15416 | case TG3_PHY_ID_BCM5755: return "5755"; | |
15417 | case TG3_PHY_ID_BCM5787: return "5787"; | |
15418 | case TG3_PHY_ID_BCM5784: return "5784"; | |
15419 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
15420 | case TG3_PHY_ID_BCM5906: return "5906"; | |
15421 | case TG3_PHY_ID_BCM5761: return "5761"; | |
15422 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
15423 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
15424 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 15425 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
6418f2c1 | 15426 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
79eb6904 | 15427 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
15428 | case 0: return "serdes"; |
15429 | default: return "unknown"; | |
855e1111 | 15430 | } |
1da177e4 LT |
15431 | } |
15432 | ||
f9804ddb MC |
15433 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
15434 | { | |
63c3a66f | 15435 | if (tg3_flag(tp, PCI_EXPRESS)) { |
f9804ddb MC |
15436 | strcpy(str, "PCI Express"); |
15437 | return str; | |
63c3a66f | 15438 | } else if (tg3_flag(tp, PCIX_MODE)) { |
f9804ddb MC |
15439 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; |
15440 | ||
15441 | strcpy(str, "PCIX:"); | |
15442 | ||
15443 | if ((clock_ctrl == 7) || | |
15444 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
15445 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
15446 | strcat(str, "133MHz"); | |
15447 | else if (clock_ctrl == 0) | |
15448 | strcat(str, "33MHz"); | |
15449 | else if (clock_ctrl == 2) | |
15450 | strcat(str, "50MHz"); | |
15451 | else if (clock_ctrl == 4) | |
15452 | strcat(str, "66MHz"); | |
15453 | else if (clock_ctrl == 6) | |
15454 | strcat(str, "100MHz"); | |
f9804ddb MC |
15455 | } else { |
15456 | strcpy(str, "PCI:"); | |
63c3a66f | 15457 | if (tg3_flag(tp, PCI_HIGH_SPEED)) |
f9804ddb MC |
15458 | strcat(str, "66MHz"); |
15459 | else | |
15460 | strcat(str, "33MHz"); | |
15461 | } | |
63c3a66f | 15462 | if (tg3_flag(tp, PCI_32BIT)) |
f9804ddb MC |
15463 | strcat(str, ":32-bit"); |
15464 | else | |
15465 | strcat(str, ":64-bit"); | |
15466 | return str; | |
15467 | } | |
15468 | ||
15f9850d DM |
15469 | static void __devinit tg3_init_coal(struct tg3 *tp) |
15470 | { | |
15471 | struct ethtool_coalesce *ec = &tp->coal; | |
15472 | ||
15473 | memset(ec, 0, sizeof(*ec)); | |
15474 | ec->cmd = ETHTOOL_GCOALESCE; | |
15475 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
15476 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
15477 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
15478 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
15479 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
15480 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
15481 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
15482 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
15483 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
15484 | ||
15485 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
15486 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
15487 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
15488 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
15489 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
15490 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
15491 | } | |
d244c892 | 15492 | |
63c3a66f | 15493 | if (tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
15494 | ec->rx_coalesce_usecs_irq = 0; |
15495 | ec->tx_coalesce_usecs_irq = 0; | |
15496 | ec->stats_block_coalesce_usecs = 0; | |
15497 | } | |
15f9850d DM |
15498 | } |
15499 | ||
1da177e4 LT |
15500 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
15501 | const struct pci_device_id *ent) | |
15502 | { | |
1da177e4 LT |
15503 | struct net_device *dev; |
15504 | struct tg3 *tp; | |
646c9edd MC |
15505 | int i, err, pm_cap; |
15506 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 15507 | char str[40]; |
72f2afb8 | 15508 | u64 dma_mask, persist_dma_mask; |
c8f44aff | 15509 | netdev_features_t features = 0; |
1da177e4 | 15510 | |
05dbe005 | 15511 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
15512 | |
15513 | err = pci_enable_device(pdev); | |
15514 | if (err) { | |
2445e461 | 15515 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
15516 | return err; |
15517 | } | |
15518 | ||
1da177e4 LT |
15519 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
15520 | if (err) { | |
2445e461 | 15521 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
15522 | goto err_out_disable_pdev; |
15523 | } | |
15524 | ||
15525 | pci_set_master(pdev); | |
15526 | ||
15527 | /* Find power-management capability. */ | |
15528 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
15529 | if (pm_cap == 0) { | |
2445e461 MC |
15530 | dev_err(&pdev->dev, |
15531 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
15532 | err = -EIO; |
15533 | goto err_out_free_res; | |
15534 | } | |
15535 | ||
16821285 MC |
15536 | err = pci_set_power_state(pdev, PCI_D0); |
15537 | if (err) { | |
15538 | dev_err(&pdev->dev, "Transition to D0 failed, aborting\n"); | |
15539 | goto err_out_free_res; | |
15540 | } | |
15541 | ||
fe5f5787 | 15542 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 15543 | if (!dev) { |
1da177e4 | 15544 | err = -ENOMEM; |
16821285 | 15545 | goto err_out_power_down; |
1da177e4 LT |
15546 | } |
15547 | ||
1da177e4 LT |
15548 | SET_NETDEV_DEV(dev, &pdev->dev); |
15549 | ||
1da177e4 LT |
15550 | tp = netdev_priv(dev); |
15551 | tp->pdev = pdev; | |
15552 | tp->dev = dev; | |
15553 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
15554 | tp->rx_mode = TG3_DEF_RX_MODE; |
15555 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 15556 | |
1da177e4 LT |
15557 | if (tg3_debug > 0) |
15558 | tp->msg_enable = tg3_debug; | |
15559 | else | |
15560 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
15561 | ||
15562 | /* The word/byte swap controls here control register access byte | |
15563 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
15564 | * setting below. | |
15565 | */ | |
15566 | tp->misc_host_ctrl = | |
15567 | MISC_HOST_CTRL_MASK_PCI_INT | | |
15568 | MISC_HOST_CTRL_WORD_SWAP | | |
15569 | MISC_HOST_CTRL_INDIR_ACCESS | | |
15570 | MISC_HOST_CTRL_PCISTATE_RW; | |
15571 | ||
15572 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
15573 | * on descriptor entries, anything which isn't packet data. | |
15574 | * | |
15575 | * The StrongARM chips on the board (one for tx, one for rx) | |
15576 | * are running in big-endian mode. | |
15577 | */ | |
15578 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
15579 | GRC_MODE_WSWAP_NONFRM_DATA); | |
15580 | #ifdef __BIG_ENDIAN | |
15581 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
15582 | #endif | |
15583 | spin_lock_init(&tp->lock); | |
1da177e4 | 15584 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 15585 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 15586 | |
d5fe488a | 15587 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 15588 | if (!tp->regs) { |
ab96b241 | 15589 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
15590 | err = -ENOMEM; |
15591 | goto err_out_free_dev; | |
15592 | } | |
15593 | ||
c9cab24e MC |
15594 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
15595 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || | |
15596 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || | |
15597 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || | |
15598 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
15599 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
15600 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
15601 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) { | |
15602 | tg3_flag_set(tp, ENABLE_APE); | |
15603 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
15604 | if (!tp->aperegs) { | |
15605 | dev_err(&pdev->dev, | |
15606 | "Cannot map APE registers, aborting\n"); | |
15607 | err = -ENOMEM; | |
15608 | goto err_out_iounmap; | |
15609 | } | |
15610 | } | |
15611 | ||
1da177e4 LT |
15612 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
15613 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 15614 | |
1da177e4 | 15615 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 15616 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
2ffcc981 | 15617 | dev->netdev_ops = &tg3_netdev_ops; |
1da177e4 | 15618 | dev->irq = pdev->irq; |
1da177e4 LT |
15619 | |
15620 | err = tg3_get_invariants(tp); | |
15621 | if (err) { | |
ab96b241 MC |
15622 | dev_err(&pdev->dev, |
15623 | "Problem fetching invariants of chip, aborting\n"); | |
c9cab24e | 15624 | goto err_out_apeunmap; |
1da177e4 LT |
15625 | } |
15626 | ||
4a29cc2e MC |
15627 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
15628 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
15629 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
15630 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
15631 | * do DMA address check in tg3_start_xmit(). | |
15632 | */ | |
63c3a66f | 15633 | if (tg3_flag(tp, IS_5788)) |
284901a9 | 15634 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
63c3a66f | 15635 | else if (tg3_flag(tp, 40BIT_DMA_BUG)) { |
50cf156a | 15636 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 15637 | #ifdef CONFIG_HIGHMEM |
6a35528a | 15638 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 15639 | #endif |
4a29cc2e | 15640 | } else |
6a35528a | 15641 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
15642 | |
15643 | /* Configure DMA attributes. */ | |
284901a9 | 15644 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
15645 | err = pci_set_dma_mask(pdev, dma_mask); |
15646 | if (!err) { | |
0da0606f | 15647 | features |= NETIF_F_HIGHDMA; |
72f2afb8 MC |
15648 | err = pci_set_consistent_dma_mask(pdev, |
15649 | persist_dma_mask); | |
15650 | if (err < 0) { | |
ab96b241 MC |
15651 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
15652 | "DMA for consistent allocations\n"); | |
c9cab24e | 15653 | goto err_out_apeunmap; |
72f2afb8 MC |
15654 | } |
15655 | } | |
15656 | } | |
284901a9 YH |
15657 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
15658 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 15659 | if (err) { |
ab96b241 MC |
15660 | dev_err(&pdev->dev, |
15661 | "No usable DMA configuration, aborting\n"); | |
c9cab24e | 15662 | goto err_out_apeunmap; |
72f2afb8 MC |
15663 | } |
15664 | } | |
15665 | ||
fdfec172 | 15666 | tg3_init_bufmgr_config(tp); |
1da177e4 | 15667 | |
0da0606f MC |
15668 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
15669 | ||
15670 | /* 5700 B0 chips do not support checksumming correctly due | |
15671 | * to hardware bugs. | |
15672 | */ | |
15673 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { | |
15674 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
15675 | ||
15676 | if (tg3_flag(tp, 5755_PLUS)) | |
15677 | features |= NETIF_F_IPV6_CSUM; | |
15678 | } | |
15679 | ||
4e3a7aaa MC |
15680 | /* TSO is on by default on chips that support hardware TSO. |
15681 | * Firmware TSO on older chips gives lower performance, so it | |
15682 | * is off by default, but can be enabled using ethtool. | |
15683 | */ | |
63c3a66f JP |
15684 | if ((tg3_flag(tp, HW_TSO_1) || |
15685 | tg3_flag(tp, HW_TSO_2) || | |
15686 | tg3_flag(tp, HW_TSO_3)) && | |
0da0606f MC |
15687 | (features & NETIF_F_IP_CSUM)) |
15688 | features |= NETIF_F_TSO; | |
63c3a66f | 15689 | if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { |
0da0606f MC |
15690 | if (features & NETIF_F_IPV6_CSUM) |
15691 | features |= NETIF_F_TSO6; | |
63c3a66f | 15692 | if (tg3_flag(tp, HW_TSO_3) || |
e849cdc3 | 15693 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c MC |
15694 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
15695 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
63c3a66f | 15696 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
dc668910 | 15697 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
0da0606f | 15698 | features |= NETIF_F_TSO_ECN; |
b0026624 | 15699 | } |
1da177e4 | 15700 | |
d542fe27 MC |
15701 | dev->features |= features; |
15702 | dev->vlan_features |= features; | |
15703 | ||
06c03c02 MB |
15704 | /* |
15705 | * Add loopback capability only for a subset of devices that support | |
15706 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY | |
15707 | * loopback for the remaining devices. | |
15708 | */ | |
15709 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
15710 | !tg3_flag(tp, CPMU_PRESENT)) | |
15711 | /* Add the loopback capability */ | |
0da0606f MC |
15712 | features |= NETIF_F_LOOPBACK; |
15713 | ||
0da0606f | 15714 | dev->hw_features |= features; |
06c03c02 | 15715 | |
1da177e4 | 15716 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
63c3a66f | 15717 | !tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 | 15718 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { |
63c3a66f | 15719 | tg3_flag_set(tp, MAX_RXPEND_64); |
1da177e4 LT |
15720 | tp->rx_pending = 63; |
15721 | } | |
15722 | ||
1da177e4 LT |
15723 | err = tg3_get_device_address(tp); |
15724 | if (err) { | |
ab96b241 MC |
15725 | dev_err(&pdev->dev, |
15726 | "Could not obtain valid ethernet address, aborting\n"); | |
c9cab24e | 15727 | goto err_out_apeunmap; |
c88864df MC |
15728 | } |
15729 | ||
1da177e4 LT |
15730 | /* |
15731 | * Reset chip in case UNDI or EFI driver did not shutdown | |
15732 | * DMA self test will enable WDMAC and we'll see (spurious) | |
15733 | * pending DMA on the PCI bus at that point. | |
15734 | */ | |
15735 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
15736 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 15737 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 15738 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
15739 | } |
15740 | ||
15741 | err = tg3_test_dma(tp); | |
15742 | if (err) { | |
ab96b241 | 15743 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 15744 | goto err_out_apeunmap; |
1da177e4 LT |
15745 | } |
15746 | ||
78f90dcf MC |
15747 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
15748 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
15749 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 15750 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
15751 | struct tg3_napi *tnapi = &tp->napi[i]; |
15752 | ||
15753 | tnapi->tp = tp; | |
15754 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
15755 | ||
15756 | tnapi->int_mbox = intmbx; | |
93a700a9 | 15757 | if (i <= 4) |
78f90dcf MC |
15758 | intmbx += 0x8; |
15759 | else | |
15760 | intmbx += 0x4; | |
15761 | ||
15762 | tnapi->consmbox = rcvmbx; | |
15763 | tnapi->prodmbox = sndmbx; | |
15764 | ||
66cfd1bd | 15765 | if (i) |
78f90dcf | 15766 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 15767 | else |
78f90dcf | 15768 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf | 15769 | |
63c3a66f | 15770 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
78f90dcf MC |
15771 | break; |
15772 | ||
15773 | /* | |
15774 | * If we support MSIX, we'll be using RSS. If we're using | |
15775 | * RSS, the first vector only handles link interrupts and the | |
15776 | * remaining vectors handle rx and tx interrupts. Reuse the | |
15777 | * mailbox values for the next iteration. The values we setup | |
15778 | * above are still useful for the single vectored mode. | |
15779 | */ | |
15780 | if (!i) | |
15781 | continue; | |
15782 | ||
15783 | rcvmbx += 0x8; | |
15784 | ||
15785 | if (sndmbx & 0x4) | |
15786 | sndmbx -= 0x4; | |
15787 | else | |
15788 | sndmbx += 0xc; | |
15789 | } | |
15790 | ||
15f9850d DM |
15791 | tg3_init_coal(tp); |
15792 | ||
c49a1561 MC |
15793 | pci_set_drvdata(pdev, dev); |
15794 | ||
cd0d7228 MC |
15795 | if (tg3_flag(tp, 5717_PLUS)) { |
15796 | /* Resume a low-power mode */ | |
15797 | tg3_frob_aux_power(tp, false); | |
15798 | } | |
15799 | ||
21f7638e MC |
15800 | tg3_timer_init(tp); |
15801 | ||
1da177e4 LT |
15802 | err = register_netdev(dev); |
15803 | if (err) { | |
ab96b241 | 15804 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 15805 | goto err_out_apeunmap; |
1da177e4 LT |
15806 | } |
15807 | ||
05dbe005 JP |
15808 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
15809 | tp->board_part_number, | |
15810 | tp->pci_chip_rev_id, | |
15811 | tg3_bus_string(tp, str), | |
15812 | dev->dev_addr); | |
1da177e4 | 15813 | |
f07e9af3 | 15814 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
15815 | struct phy_device *phydev; |
15816 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
15817 | netdev_info(dev, |
15818 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 15819 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
15820 | } else { |
15821 | char *ethtype; | |
15822 | ||
15823 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
15824 | ethtype = "10/100Base-TX"; | |
15825 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
15826 | ethtype = "1000Base-SX"; | |
15827 | else | |
15828 | ethtype = "10/100/1000Base-T"; | |
15829 | ||
5129c3a3 | 15830 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
47007831 MC |
15831 | "(WireSpeed[%d], EEE[%d])\n", |
15832 | tg3_phy_string(tp), ethtype, | |
15833 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, | |
15834 | (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); | |
f07e9af3 | 15835 | } |
05dbe005 JP |
15836 | |
15837 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
dc668910 | 15838 | (dev->features & NETIF_F_RXCSUM) != 0, |
63c3a66f | 15839 | tg3_flag(tp, USE_LINKCHG_REG) != 0, |
f07e9af3 | 15840 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
63c3a66f JP |
15841 | tg3_flag(tp, ENABLE_ASF) != 0, |
15842 | tg3_flag(tp, TSO_CAPABLE) != 0); | |
05dbe005 JP |
15843 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
15844 | tp->dma_rwctrl, | |
15845 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
15846 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 | 15847 | |
b45aa2f6 MC |
15848 | pci_save_state(pdev); |
15849 | ||
1da177e4 LT |
15850 | return 0; |
15851 | ||
0d3031d9 MC |
15852 | err_out_apeunmap: |
15853 | if (tp->aperegs) { | |
15854 | iounmap(tp->aperegs); | |
15855 | tp->aperegs = NULL; | |
15856 | } | |
15857 | ||
1da177e4 | 15858 | err_out_iounmap: |
6892914f MC |
15859 | if (tp->regs) { |
15860 | iounmap(tp->regs); | |
22abe310 | 15861 | tp->regs = NULL; |
6892914f | 15862 | } |
1da177e4 LT |
15863 | |
15864 | err_out_free_dev: | |
15865 | free_netdev(dev); | |
15866 | ||
16821285 MC |
15867 | err_out_power_down: |
15868 | pci_set_power_state(pdev, PCI_D3hot); | |
15869 | ||
1da177e4 LT |
15870 | err_out_free_res: |
15871 | pci_release_regions(pdev); | |
15872 | ||
15873 | err_out_disable_pdev: | |
15874 | pci_disable_device(pdev); | |
15875 | pci_set_drvdata(pdev, NULL); | |
15876 | return err; | |
15877 | } | |
15878 | ||
15879 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
15880 | { | |
15881 | struct net_device *dev = pci_get_drvdata(pdev); | |
15882 | ||
15883 | if (dev) { | |
15884 | struct tg3 *tp = netdev_priv(dev); | |
15885 | ||
e3c5530b | 15886 | release_firmware(tp->fw); |
077f849d | 15887 | |
db219973 | 15888 | tg3_reset_task_cancel(tp); |
158d7abd | 15889 | |
e730c823 | 15890 | if (tg3_flag(tp, USE_PHYLIB)) { |
b02fd9e3 | 15891 | tg3_phy_fini(tp); |
158d7abd | 15892 | tg3_mdio_fini(tp); |
b02fd9e3 | 15893 | } |
158d7abd | 15894 | |
1da177e4 | 15895 | unregister_netdev(dev); |
0d3031d9 MC |
15896 | if (tp->aperegs) { |
15897 | iounmap(tp->aperegs); | |
15898 | tp->aperegs = NULL; | |
15899 | } | |
6892914f MC |
15900 | if (tp->regs) { |
15901 | iounmap(tp->regs); | |
22abe310 | 15902 | tp->regs = NULL; |
6892914f | 15903 | } |
1da177e4 LT |
15904 | free_netdev(dev); |
15905 | pci_release_regions(pdev); | |
15906 | pci_disable_device(pdev); | |
15907 | pci_set_drvdata(pdev, NULL); | |
15908 | } | |
15909 | } | |
15910 | ||
aa6027ca | 15911 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 15912 | static int tg3_suspend(struct device *device) |
1da177e4 | 15913 | { |
c866b7ea | 15914 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15915 | struct net_device *dev = pci_get_drvdata(pdev); |
15916 | struct tg3 *tp = netdev_priv(dev); | |
15917 | int err; | |
15918 | ||
15919 | if (!netif_running(dev)) | |
15920 | return 0; | |
15921 | ||
db219973 | 15922 | tg3_reset_task_cancel(tp); |
b02fd9e3 | 15923 | tg3_phy_stop(tp); |
1da177e4 LT |
15924 | tg3_netif_stop(tp); |
15925 | ||
21f7638e | 15926 | tg3_timer_stop(tp); |
1da177e4 | 15927 | |
f47c11ee | 15928 | tg3_full_lock(tp, 1); |
1da177e4 | 15929 | tg3_disable_ints(tp); |
f47c11ee | 15930 | tg3_full_unlock(tp); |
1da177e4 LT |
15931 | |
15932 | netif_device_detach(dev); | |
15933 | ||
f47c11ee | 15934 | tg3_full_lock(tp, 0); |
944d980e | 15935 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
63c3a66f | 15936 | tg3_flag_clear(tp, INIT_COMPLETE); |
f47c11ee | 15937 | tg3_full_unlock(tp); |
1da177e4 | 15938 | |
c866b7ea | 15939 | err = tg3_power_down_prepare(tp); |
1da177e4 | 15940 | if (err) { |
b02fd9e3 MC |
15941 | int err2; |
15942 | ||
f47c11ee | 15943 | tg3_full_lock(tp, 0); |
1da177e4 | 15944 | |
63c3a66f | 15945 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
15946 | err2 = tg3_restart_hw(tp, 1); |
15947 | if (err2) | |
b9ec6c1b | 15948 | goto out; |
1da177e4 | 15949 | |
21f7638e | 15950 | tg3_timer_start(tp); |
1da177e4 LT |
15951 | |
15952 | netif_device_attach(dev); | |
15953 | tg3_netif_start(tp); | |
15954 | ||
b9ec6c1b | 15955 | out: |
f47c11ee | 15956 | tg3_full_unlock(tp); |
b02fd9e3 MC |
15957 | |
15958 | if (!err2) | |
15959 | tg3_phy_start(tp); | |
1da177e4 LT |
15960 | } |
15961 | ||
15962 | return err; | |
15963 | } | |
15964 | ||
c866b7ea | 15965 | static int tg3_resume(struct device *device) |
1da177e4 | 15966 | { |
c866b7ea | 15967 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15968 | struct net_device *dev = pci_get_drvdata(pdev); |
15969 | struct tg3 *tp = netdev_priv(dev); | |
15970 | int err; | |
15971 | ||
15972 | if (!netif_running(dev)) | |
15973 | return 0; | |
15974 | ||
1da177e4 LT |
15975 | netif_device_attach(dev); |
15976 | ||
f47c11ee | 15977 | tg3_full_lock(tp, 0); |
1da177e4 | 15978 | |
63c3a66f | 15979 | tg3_flag_set(tp, INIT_COMPLETE); |
b9ec6c1b MC |
15980 | err = tg3_restart_hw(tp, 1); |
15981 | if (err) | |
15982 | goto out; | |
1da177e4 | 15983 | |
21f7638e | 15984 | tg3_timer_start(tp); |
1da177e4 | 15985 | |
1da177e4 LT |
15986 | tg3_netif_start(tp); |
15987 | ||
b9ec6c1b | 15988 | out: |
f47c11ee | 15989 | tg3_full_unlock(tp); |
1da177e4 | 15990 | |
b02fd9e3 MC |
15991 | if (!err) |
15992 | tg3_phy_start(tp); | |
15993 | ||
b9ec6c1b | 15994 | return err; |
1da177e4 LT |
15995 | } |
15996 | ||
c866b7ea | 15997 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
15998 | #define TG3_PM_OPS (&tg3_pm_ops) |
15999 | ||
16000 | #else | |
16001 | ||
16002 | #define TG3_PM_OPS NULL | |
16003 | ||
16004 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 16005 | |
b45aa2f6 MC |
16006 | /** |
16007 | * tg3_io_error_detected - called when PCI error is detected | |
16008 | * @pdev: Pointer to PCI device | |
16009 | * @state: The current pci connection state | |
16010 | * | |
16011 | * This function is called after a PCI bus error affecting | |
16012 | * this device has been detected. | |
16013 | */ | |
16014 | static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |
16015 | pci_channel_state_t state) | |
16016 | { | |
16017 | struct net_device *netdev = pci_get_drvdata(pdev); | |
16018 | struct tg3 *tp = netdev_priv(netdev); | |
16019 | pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET; | |
16020 | ||
16021 | netdev_info(netdev, "PCI I/O error detected\n"); | |
16022 | ||
16023 | rtnl_lock(); | |
16024 | ||
16025 | if (!netif_running(netdev)) | |
16026 | goto done; | |
16027 | ||
16028 | tg3_phy_stop(tp); | |
16029 | ||
16030 | tg3_netif_stop(tp); | |
16031 | ||
21f7638e | 16032 | tg3_timer_stop(tp); |
b45aa2f6 MC |
16033 | |
16034 | /* Want to make sure that the reset task doesn't run */ | |
db219973 | 16035 | tg3_reset_task_cancel(tp); |
b45aa2f6 MC |
16036 | |
16037 | netif_device_detach(netdev); | |
16038 | ||
16039 | /* Clean up software state, even if MMIO is blocked */ | |
16040 | tg3_full_lock(tp, 0); | |
16041 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
16042 | tg3_full_unlock(tp); | |
16043 | ||
16044 | done: | |
16045 | if (state == pci_channel_io_perm_failure) | |
16046 | err = PCI_ERS_RESULT_DISCONNECT; | |
16047 | else | |
16048 | pci_disable_device(pdev); | |
16049 | ||
16050 | rtnl_unlock(); | |
16051 | ||
16052 | return err; | |
16053 | } | |
16054 | ||
16055 | /** | |
16056 | * tg3_io_slot_reset - called after the pci bus has been reset. | |
16057 | * @pdev: Pointer to PCI device | |
16058 | * | |
16059 | * Restart the card from scratch, as if from a cold-boot. | |
16060 | * At this point, the card has exprienced a hard reset, | |
16061 | * followed by fixups by BIOS, and has its config space | |
16062 | * set up identically to what it was at cold boot. | |
16063 | */ | |
16064 | static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) | |
16065 | { | |
16066 | struct net_device *netdev = pci_get_drvdata(pdev); | |
16067 | struct tg3 *tp = netdev_priv(netdev); | |
16068 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; | |
16069 | int err; | |
16070 | ||
16071 | rtnl_lock(); | |
16072 | ||
16073 | if (pci_enable_device(pdev)) { | |
16074 | netdev_err(netdev, "Cannot re-enable PCI device after reset.\n"); | |
16075 | goto done; | |
16076 | } | |
16077 | ||
16078 | pci_set_master(pdev); | |
16079 | pci_restore_state(pdev); | |
16080 | pci_save_state(pdev); | |
16081 | ||
16082 | if (!netif_running(netdev)) { | |
16083 | rc = PCI_ERS_RESULT_RECOVERED; | |
16084 | goto done; | |
16085 | } | |
16086 | ||
16087 | err = tg3_power_up(tp); | |
bed9829f | 16088 | if (err) |
b45aa2f6 | 16089 | goto done; |
b45aa2f6 MC |
16090 | |
16091 | rc = PCI_ERS_RESULT_RECOVERED; | |
16092 | ||
16093 | done: | |
16094 | rtnl_unlock(); | |
16095 | ||
16096 | return rc; | |
16097 | } | |
16098 | ||
16099 | /** | |
16100 | * tg3_io_resume - called when traffic can start flowing again. | |
16101 | * @pdev: Pointer to PCI device | |
16102 | * | |
16103 | * This callback is called when the error recovery driver tells | |
16104 | * us that its OK to resume normal operation. | |
16105 | */ | |
16106 | static void tg3_io_resume(struct pci_dev *pdev) | |
16107 | { | |
16108 | struct net_device *netdev = pci_get_drvdata(pdev); | |
16109 | struct tg3 *tp = netdev_priv(netdev); | |
16110 | int err; | |
16111 | ||
16112 | rtnl_lock(); | |
16113 | ||
16114 | if (!netif_running(netdev)) | |
16115 | goto done; | |
16116 | ||
16117 | tg3_full_lock(tp, 0); | |
63c3a66f | 16118 | tg3_flag_set(tp, INIT_COMPLETE); |
b45aa2f6 MC |
16119 | err = tg3_restart_hw(tp, 1); |
16120 | tg3_full_unlock(tp); | |
16121 | if (err) { | |
16122 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); | |
16123 | goto done; | |
16124 | } | |
16125 | ||
16126 | netif_device_attach(netdev); | |
16127 | ||
21f7638e | 16128 | tg3_timer_start(tp); |
b45aa2f6 MC |
16129 | |
16130 | tg3_netif_start(tp); | |
16131 | ||
16132 | tg3_phy_start(tp); | |
16133 | ||
16134 | done: | |
16135 | rtnl_unlock(); | |
16136 | } | |
16137 | ||
16138 | static struct pci_error_handlers tg3_err_handler = { | |
16139 | .error_detected = tg3_io_error_detected, | |
16140 | .slot_reset = tg3_io_slot_reset, | |
16141 | .resume = tg3_io_resume | |
16142 | }; | |
16143 | ||
1da177e4 LT |
16144 | static struct pci_driver tg3_driver = { |
16145 | .name = DRV_MODULE_NAME, | |
16146 | .id_table = tg3_pci_tbl, | |
16147 | .probe = tg3_init_one, | |
16148 | .remove = __devexit_p(tg3_remove_one), | |
b45aa2f6 | 16149 | .err_handler = &tg3_err_handler, |
aa6027ca | 16150 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
16151 | }; |
16152 | ||
16153 | static int __init tg3_init(void) | |
16154 | { | |
29917620 | 16155 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
16156 | } |
16157 | ||
16158 | static void __exit tg3_cleanup(void) | |
16159 | { | |
16160 | pci_unregister_driver(&tg3_driver); | |
16161 | } | |
16162 | ||
16163 | module_init(tg3_init); | |
16164 | module_exit(tg3_cleanup); |