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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
b86fb2cf | 7 | * Copyright (C) 2005-2011 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 | 28 | #include <linux/init.h> |
a6b7a407 | 29 | #include <linux/interrupt.h> |
1da177e4 LT |
30 | #include <linux/ioport.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/ethtool.h> | |
3110f5f5 | 36 | #include <linux/mdio.h> |
1da177e4 | 37 | #include <linux/mii.h> |
158d7abd | 38 | #include <linux/phy.h> |
a9daf367 | 39 | #include <linux/brcmphy.h> |
1da177e4 LT |
40 | #include <linux/if_vlan.h> |
41 | #include <linux/ip.h> | |
42 | #include <linux/tcp.h> | |
43 | #include <linux/workqueue.h> | |
61487480 | 44 | #include <linux/prefetch.h> |
f9a5f7d3 | 45 | #include <linux/dma-mapping.h> |
077f849d | 46 | #include <linux/firmware.h> |
1da177e4 LT |
47 | |
48 | #include <net/checksum.h> | |
c9bdd4b5 | 49 | #include <net/ip.h> |
1da177e4 LT |
50 | |
51 | #include <asm/system.h> | |
27fd9de8 | 52 | #include <linux/io.h> |
1da177e4 | 53 | #include <asm/byteorder.h> |
27fd9de8 | 54 | #include <linux/uaccess.h> |
1da177e4 | 55 | |
49b6e95f | 56 | #ifdef CONFIG_SPARC |
1da177e4 | 57 | #include <asm/idprom.h> |
49b6e95f | 58 | #include <asm/prom.h> |
1da177e4 LT |
59 | #endif |
60 | ||
63532394 MC |
61 | #define BAR_0 0 |
62 | #define BAR_2 2 | |
63 | ||
1da177e4 LT |
64 | #include "tg3.h" |
65 | ||
63c3a66f JP |
66 | /* Functions & macros to verify TG3_FLAGS types */ |
67 | ||
68 | static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) | |
69 | { | |
70 | return test_bit(flag, bits); | |
71 | } | |
72 | ||
73 | static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) | |
74 | { | |
75 | set_bit(flag, bits); | |
76 | } | |
77 | ||
78 | static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) | |
79 | { | |
80 | clear_bit(flag, bits); | |
81 | } | |
82 | ||
83 | #define tg3_flag(tp, flag) \ | |
84 | _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) | |
85 | #define tg3_flag_set(tp, flag) \ | |
86 | _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) | |
87 | #define tg3_flag_clear(tp, flag) \ | |
88 | _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) | |
89 | ||
1da177e4 | 90 | #define DRV_MODULE_NAME "tg3" |
6867c843 | 91 | #define TG3_MAJ_NUM 3 |
efab79c5 | 92 | #define TG3_MIN_NUM 122 |
6867c843 MC |
93 | #define DRV_MODULE_VERSION \ |
94 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
efab79c5 | 95 | #define DRV_MODULE_RELDATE "December 7, 2011" |
1da177e4 | 96 | |
fd6d3f0e MC |
97 | #define RESET_KIND_SHUTDOWN 0 |
98 | #define RESET_KIND_INIT 1 | |
99 | #define RESET_KIND_SUSPEND 2 | |
100 | ||
1da177e4 LT |
101 | #define TG3_DEF_RX_MODE 0 |
102 | #define TG3_DEF_TX_MODE 0 | |
103 | #define TG3_DEF_MSG_ENABLE \ | |
104 | (NETIF_MSG_DRV | \ | |
105 | NETIF_MSG_PROBE | \ | |
106 | NETIF_MSG_LINK | \ | |
107 | NETIF_MSG_TIMER | \ | |
108 | NETIF_MSG_IFDOWN | \ | |
109 | NETIF_MSG_IFUP | \ | |
110 | NETIF_MSG_RX_ERR | \ | |
111 | NETIF_MSG_TX_ERR) | |
112 | ||
520b2756 MC |
113 | #define TG3_GRC_LCLCTL_PWRSW_DELAY 100 |
114 | ||
1da177e4 LT |
115 | /* length of time before we decide the hardware is borked, |
116 | * and dev->tx_timeout() should be called to fix the problem | |
117 | */ | |
63c3a66f | 118 | |
1da177e4 LT |
119 | #define TG3_TX_TIMEOUT (5 * HZ) |
120 | ||
121 | /* hardware minimum and maximum for a single frame's data payload */ | |
122 | #define TG3_MIN_MTU 60 | |
123 | #define TG3_MAX_MTU(tp) \ | |
63c3a66f | 124 | (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
125 | |
126 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
127 | * You can't change the ring sizes, but you can change where you place | |
128 | * them in the NIC onboard memory. | |
129 | */ | |
7cb32cf2 | 130 | #define TG3_RX_STD_RING_SIZE(tp) \ |
63c3a66f | 131 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 132 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) |
1da177e4 | 133 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 134 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
63c3a66f | 135 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 136 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) |
1da177e4 LT |
137 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
138 | ||
139 | /* Do not place this n-ring entries value into the tp struct itself, | |
140 | * we really want to expose these constants to GCC so that modulo et | |
141 | * al. operations are done with shifts and masks instead of with | |
142 | * hw multiply/modulo instructions. Another solution would be to | |
143 | * replace things like '% foo' with '& (foo - 1)'. | |
144 | */ | |
1da177e4 LT |
145 | |
146 | #define TG3_TX_RING_SIZE 512 | |
147 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
148 | ||
2c49a44d MC |
149 | #define TG3_RX_STD_RING_BYTES(tp) \ |
150 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
151 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
152 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
153 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 154 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
155 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
156 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
157 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
158 | ||
287be12e MC |
159 | #define TG3_DMA_BYTE_ENAB 64 |
160 | ||
161 | #define TG3_RX_STD_DMA_SZ 1536 | |
162 | #define TG3_RX_JMB_DMA_SZ 9046 | |
163 | ||
164 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
165 | ||
166 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
167 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 168 | |
2c49a44d MC |
169 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
170 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 171 | |
2c49a44d MC |
172 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
173 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 174 | |
d2757fc4 MC |
175 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
176 | * that are at least dword aligned when used in PCIX mode. The driver | |
177 | * works around this bug by double copying the packet. This workaround | |
178 | * is built into the normal double copy length check for efficiency. | |
179 | * | |
180 | * However, the double copy is only necessary on those architectures | |
181 | * where unaligned memory accesses are inefficient. For those architectures | |
182 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
183 | * the 5701 in the normal rx path. Doing so saves a device structure | |
184 | * dereference by hardcoding the double copy threshold in place. | |
185 | */ | |
186 | #define TG3_RX_COPY_THRESHOLD 256 | |
187 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
188 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
189 | #else | |
190 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
191 | #endif | |
192 | ||
81389f57 MC |
193 | #if (NET_IP_ALIGN != 0) |
194 | #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) | |
195 | #else | |
9205fd9c | 196 | #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) |
81389f57 MC |
197 | #endif |
198 | ||
1da177e4 | 199 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 200 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
55086ad9 | 201 | #define TG3_TX_BD_DMA_MAX_2K 2048 |
a4cb428d | 202 | #define TG3_TX_BD_DMA_MAX_4K 4096 |
1da177e4 | 203 | |
ad829268 MC |
204 | #define TG3_RAW_IP_ALIGN 2 |
205 | ||
c6cdf436 MC |
206 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
207 | ||
077f849d JSR |
208 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
209 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
210 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
211 | ||
1da177e4 | 212 | static char version[] __devinitdata = |
05dbe005 | 213 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
214 | |
215 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
216 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
217 | MODULE_LICENSE("GPL"); | |
218 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
219 | MODULE_FIRMWARE(FIRMWARE_TG3); |
220 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
221 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
222 | ||
1da177e4 LT |
223 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
224 | module_param(tg3_debug, int, 0); | |
225 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
226 | ||
a3aa1884 | 227 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
13185217 | 250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 HK |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
269 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
272 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
275 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
276 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
277 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
278 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
279 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 280 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
281 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
282 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
283 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
284 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
285 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
286 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
287 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
288 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
289 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 290 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
291 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
292 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
b0f75221 MC |
293 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
294 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
295 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
296 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
297 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
298 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
302b500b | 299 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
ba1f3c76 | 300 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
13185217 HK |
301 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
302 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
303 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
304 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
305 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
306 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
307 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
1dcb14d9 | 308 | {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */ |
13185217 | 309 | {} |
1da177e4 LT |
310 | }; |
311 | ||
312 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
313 | ||
50da859d | 314 | static const struct { |
1da177e4 | 315 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 316 | } ethtool_stats_keys[] = { |
1da177e4 LT |
317 | { "rx_octets" }, |
318 | { "rx_fragments" }, | |
319 | { "rx_ucast_packets" }, | |
320 | { "rx_mcast_packets" }, | |
321 | { "rx_bcast_packets" }, | |
322 | { "rx_fcs_errors" }, | |
323 | { "rx_align_errors" }, | |
324 | { "rx_xon_pause_rcvd" }, | |
325 | { "rx_xoff_pause_rcvd" }, | |
326 | { "rx_mac_ctrl_rcvd" }, | |
327 | { "rx_xoff_entered" }, | |
328 | { "rx_frame_too_long_errors" }, | |
329 | { "rx_jabbers" }, | |
330 | { "rx_undersize_packets" }, | |
331 | { "rx_in_length_errors" }, | |
332 | { "rx_out_length_errors" }, | |
333 | { "rx_64_or_less_octet_packets" }, | |
334 | { "rx_65_to_127_octet_packets" }, | |
335 | { "rx_128_to_255_octet_packets" }, | |
336 | { "rx_256_to_511_octet_packets" }, | |
337 | { "rx_512_to_1023_octet_packets" }, | |
338 | { "rx_1024_to_1522_octet_packets" }, | |
339 | { "rx_1523_to_2047_octet_packets" }, | |
340 | { "rx_2048_to_4095_octet_packets" }, | |
341 | { "rx_4096_to_8191_octet_packets" }, | |
342 | { "rx_8192_to_9022_octet_packets" }, | |
343 | ||
344 | { "tx_octets" }, | |
345 | { "tx_collisions" }, | |
346 | ||
347 | { "tx_xon_sent" }, | |
348 | { "tx_xoff_sent" }, | |
349 | { "tx_flow_control" }, | |
350 | { "tx_mac_errors" }, | |
351 | { "tx_single_collisions" }, | |
352 | { "tx_mult_collisions" }, | |
353 | { "tx_deferred" }, | |
354 | { "tx_excessive_collisions" }, | |
355 | { "tx_late_collisions" }, | |
356 | { "tx_collide_2times" }, | |
357 | { "tx_collide_3times" }, | |
358 | { "tx_collide_4times" }, | |
359 | { "tx_collide_5times" }, | |
360 | { "tx_collide_6times" }, | |
361 | { "tx_collide_7times" }, | |
362 | { "tx_collide_8times" }, | |
363 | { "tx_collide_9times" }, | |
364 | { "tx_collide_10times" }, | |
365 | { "tx_collide_11times" }, | |
366 | { "tx_collide_12times" }, | |
367 | { "tx_collide_13times" }, | |
368 | { "tx_collide_14times" }, | |
369 | { "tx_collide_15times" }, | |
370 | { "tx_ucast_packets" }, | |
371 | { "tx_mcast_packets" }, | |
372 | { "tx_bcast_packets" }, | |
373 | { "tx_carrier_sense_errors" }, | |
374 | { "tx_discards" }, | |
375 | { "tx_errors" }, | |
376 | ||
377 | { "dma_writeq_full" }, | |
378 | { "dma_write_prioq_full" }, | |
379 | { "rxbds_empty" }, | |
380 | { "rx_discards" }, | |
381 | { "rx_errors" }, | |
382 | { "rx_threshold_hit" }, | |
383 | ||
384 | { "dma_readq_full" }, | |
385 | { "dma_read_prioq_full" }, | |
386 | { "tx_comp_queue_full" }, | |
387 | ||
388 | { "ring_set_send_prod_index" }, | |
389 | { "ring_status_update" }, | |
390 | { "nic_irqs" }, | |
391 | { "nic_avoided_irqs" }, | |
4452d099 MC |
392 | { "nic_tx_threshold_hit" }, |
393 | ||
394 | { "mbuf_lwm_thresh_hit" }, | |
1da177e4 LT |
395 | }; |
396 | ||
48fa55a0 MC |
397 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
398 | ||
399 | ||
50da859d | 400 | static const struct { |
4cafd3f5 | 401 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 402 | } ethtool_test_keys[] = { |
28a45957 MC |
403 | { "nvram test (online) " }, |
404 | { "link test (online) " }, | |
405 | { "register test (offline)" }, | |
406 | { "memory test (offline)" }, | |
407 | { "mac loopback test (offline)" }, | |
408 | { "phy loopback test (offline)" }, | |
941ec90f | 409 | { "ext loopback test (offline)" }, |
28a45957 | 410 | { "interrupt test (offline)" }, |
4cafd3f5 MC |
411 | }; |
412 | ||
48fa55a0 MC |
413 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
414 | ||
415 | ||
b401e9e2 MC |
416 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
417 | { | |
418 | writel(val, tp->regs + off); | |
419 | } | |
420 | ||
421 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
422 | { | |
de6f31eb | 423 | return readl(tp->regs + off); |
b401e9e2 MC |
424 | } |
425 | ||
0d3031d9 MC |
426 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
427 | { | |
428 | writel(val, tp->aperegs + off); | |
429 | } | |
430 | ||
431 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
432 | { | |
de6f31eb | 433 | return readl(tp->aperegs + off); |
0d3031d9 MC |
434 | } |
435 | ||
1da177e4 LT |
436 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
437 | { | |
6892914f MC |
438 | unsigned long flags; |
439 | ||
440 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
441 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
442 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 443 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
444 | } |
445 | ||
446 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
447 | { | |
448 | writel(val, tp->regs + off); | |
449 | readl(tp->regs + off); | |
1da177e4 LT |
450 | } |
451 | ||
6892914f | 452 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 453 | { |
6892914f MC |
454 | unsigned long flags; |
455 | u32 val; | |
456 | ||
457 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
458 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
459 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
460 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
461 | return val; | |
462 | } | |
463 | ||
464 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
465 | { | |
466 | unsigned long flags; | |
467 | ||
468 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
469 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
470 | TG3_64BIT_REG_LOW, val); | |
471 | return; | |
472 | } | |
66711e66 | 473 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
474 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
475 | TG3_64BIT_REG_LOW, val); | |
476 | return; | |
1da177e4 | 477 | } |
6892914f MC |
478 | |
479 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
480 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
481 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
482 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
483 | ||
484 | /* In indirect mode when disabling interrupts, we also need | |
485 | * to clear the interrupt bit in the GRC local ctrl register. | |
486 | */ | |
487 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
488 | (val == 0x1)) { | |
489 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
490 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
491 | } | |
492 | } | |
493 | ||
494 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
495 | { | |
496 | unsigned long flags; | |
497 | u32 val; | |
498 | ||
499 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
500 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
501 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
502 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
503 | return val; | |
504 | } | |
505 | ||
b401e9e2 MC |
506 | /* usec_wait specifies the wait time in usec when writing to certain registers |
507 | * where it is unsafe to read back the register without some delay. | |
508 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
509 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
510 | */ | |
511 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 512 | { |
63c3a66f | 513 | if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) |
b401e9e2 MC |
514 | /* Non-posted methods */ |
515 | tp->write32(tp, off, val); | |
516 | else { | |
517 | /* Posted method */ | |
518 | tg3_write32(tp, off, val); | |
519 | if (usec_wait) | |
520 | udelay(usec_wait); | |
521 | tp->read32(tp, off); | |
522 | } | |
523 | /* Wait again after the read for the posted method to guarantee that | |
524 | * the wait time is met. | |
525 | */ | |
526 | if (usec_wait) | |
527 | udelay(usec_wait); | |
1da177e4 LT |
528 | } |
529 | ||
09ee929c MC |
530 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
531 | { | |
532 | tp->write32_mbox(tp, off, val); | |
63c3a66f | 533 | if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) |
6892914f | 534 | tp->read32_mbox(tp, off); |
09ee929c MC |
535 | } |
536 | ||
20094930 | 537 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
538 | { |
539 | void __iomem *mbox = tp->regs + off; | |
540 | writel(val, mbox); | |
63c3a66f | 541 | if (tg3_flag(tp, TXD_MBOX_HWBUG)) |
1da177e4 | 542 | writel(val, mbox); |
63c3a66f | 543 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1da177e4 LT |
544 | readl(mbox); |
545 | } | |
546 | ||
b5d3772c MC |
547 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
548 | { | |
de6f31eb | 549 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
550 | } |
551 | ||
552 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
553 | { | |
554 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
555 | } | |
556 | ||
c6cdf436 | 557 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 558 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
559 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
560 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
561 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 562 | |
c6cdf436 MC |
563 | #define tw32(reg, val) tp->write32(tp, reg, val) |
564 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
565 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
566 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
567 | |
568 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
569 | { | |
6892914f MC |
570 | unsigned long flags; |
571 | ||
6ff6f81d | 572 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
573 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) |
574 | return; | |
575 | ||
6892914f | 576 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 577 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
578 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
579 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 580 | |
bbadf503 MC |
581 | /* Always leave this as zero. */ |
582 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
583 | } else { | |
584 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
585 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 586 | |
bbadf503 MC |
587 | /* Always leave this as zero. */ |
588 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
589 | } | |
590 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
591 | } |
592 | ||
1da177e4 LT |
593 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
594 | { | |
6892914f MC |
595 | unsigned long flags; |
596 | ||
6ff6f81d | 597 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
598 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { |
599 | *val = 0; | |
600 | return; | |
601 | } | |
602 | ||
6892914f | 603 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 604 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
605 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
606 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 607 | |
bbadf503 MC |
608 | /* Always leave this as zero. */ |
609 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
610 | } else { | |
611 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
612 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
613 | ||
614 | /* Always leave this as zero. */ | |
615 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
616 | } | |
6892914f | 617 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
618 | } |
619 | ||
0d3031d9 MC |
620 | static void tg3_ape_lock_init(struct tg3 *tp) |
621 | { | |
622 | int i; | |
6f5c8f83 | 623 | u32 regbase, bit; |
f92d9dc1 MC |
624 | |
625 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
626 | regbase = TG3_APE_LOCK_GRANT; | |
627 | else | |
628 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
629 | |
630 | /* Make sure the driver hasn't any stale locks. */ | |
78f94dc7 MC |
631 | for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) { |
632 | switch (i) { | |
633 | case TG3_APE_LOCK_PHY0: | |
634 | case TG3_APE_LOCK_PHY1: | |
635 | case TG3_APE_LOCK_PHY2: | |
636 | case TG3_APE_LOCK_PHY3: | |
637 | bit = APE_LOCK_GRANT_DRIVER; | |
638 | break; | |
639 | default: | |
640 | if (!tp->pci_fn) | |
641 | bit = APE_LOCK_GRANT_DRIVER; | |
642 | else | |
643 | bit = 1 << tp->pci_fn; | |
644 | } | |
645 | tg3_ape_write32(tp, regbase + 4 * i, bit); | |
6f5c8f83 MC |
646 | } |
647 | ||
0d3031d9 MC |
648 | } |
649 | ||
650 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
651 | { | |
652 | int i, off; | |
653 | int ret = 0; | |
6f5c8f83 | 654 | u32 status, req, gnt, bit; |
0d3031d9 | 655 | |
63c3a66f | 656 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
657 | return 0; |
658 | ||
659 | switch (locknum) { | |
6f5c8f83 MC |
660 | case TG3_APE_LOCK_GPIO: |
661 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
662 | return 0; | |
33f401ae MC |
663 | case TG3_APE_LOCK_GRC: |
664 | case TG3_APE_LOCK_MEM: | |
78f94dc7 MC |
665 | if (!tp->pci_fn) |
666 | bit = APE_LOCK_REQ_DRIVER; | |
667 | else | |
668 | bit = 1 << tp->pci_fn; | |
33f401ae MC |
669 | break; |
670 | default: | |
671 | return -EINVAL; | |
0d3031d9 MC |
672 | } |
673 | ||
f92d9dc1 MC |
674 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
675 | req = TG3_APE_LOCK_REQ; | |
676 | gnt = TG3_APE_LOCK_GRANT; | |
677 | } else { | |
678 | req = TG3_APE_PER_LOCK_REQ; | |
679 | gnt = TG3_APE_PER_LOCK_GRANT; | |
680 | } | |
681 | ||
0d3031d9 MC |
682 | off = 4 * locknum; |
683 | ||
6f5c8f83 | 684 | tg3_ape_write32(tp, req + off, bit); |
0d3031d9 MC |
685 | |
686 | /* Wait for up to 1 millisecond to acquire lock. */ | |
687 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 688 | status = tg3_ape_read32(tp, gnt + off); |
6f5c8f83 | 689 | if (status == bit) |
0d3031d9 MC |
690 | break; |
691 | udelay(10); | |
692 | } | |
693 | ||
6f5c8f83 | 694 | if (status != bit) { |
0d3031d9 | 695 | /* Revoke the lock request. */ |
6f5c8f83 | 696 | tg3_ape_write32(tp, gnt + off, bit); |
0d3031d9 MC |
697 | ret = -EBUSY; |
698 | } | |
699 | ||
700 | return ret; | |
701 | } | |
702 | ||
703 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
704 | { | |
6f5c8f83 | 705 | u32 gnt, bit; |
0d3031d9 | 706 | |
63c3a66f | 707 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
708 | return; |
709 | ||
710 | switch (locknum) { | |
6f5c8f83 MC |
711 | case TG3_APE_LOCK_GPIO: |
712 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
713 | return; | |
33f401ae MC |
714 | case TG3_APE_LOCK_GRC: |
715 | case TG3_APE_LOCK_MEM: | |
78f94dc7 MC |
716 | if (!tp->pci_fn) |
717 | bit = APE_LOCK_GRANT_DRIVER; | |
718 | else | |
719 | bit = 1 << tp->pci_fn; | |
33f401ae MC |
720 | break; |
721 | default: | |
722 | return; | |
0d3031d9 MC |
723 | } |
724 | ||
f92d9dc1 MC |
725 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
726 | gnt = TG3_APE_LOCK_GRANT; | |
727 | else | |
728 | gnt = TG3_APE_PER_LOCK_GRANT; | |
729 | ||
6f5c8f83 | 730 | tg3_ape_write32(tp, gnt + 4 * locknum, bit); |
0d3031d9 MC |
731 | } |
732 | ||
fd6d3f0e MC |
733 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
734 | { | |
735 | int i; | |
736 | u32 apedata; | |
737 | ||
738 | /* NCSI does not support APE events */ | |
739 | if (tg3_flag(tp, APE_HAS_NCSI)) | |
740 | return; | |
741 | ||
742 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
743 | if (apedata != APE_SEG_SIG_MAGIC) | |
744 | return; | |
745 | ||
746 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
747 | if (!(apedata & APE_FW_STATUS_READY)) | |
748 | return; | |
749 | ||
750 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
751 | for (i = 0; i < 10; i++) { | |
752 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
753 | return; | |
754 | ||
755 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
756 | ||
757 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
758 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
759 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
760 | ||
761 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
762 | ||
763 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
764 | break; | |
765 | ||
766 | udelay(100); | |
767 | } | |
768 | ||
769 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
770 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
771 | } | |
772 | ||
773 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
774 | { | |
775 | u32 event; | |
776 | u32 apedata; | |
777 | ||
778 | if (!tg3_flag(tp, ENABLE_APE)) | |
779 | return; | |
780 | ||
781 | switch (kind) { | |
782 | case RESET_KIND_INIT: | |
783 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
784 | APE_HOST_SEG_SIG_MAGIC); | |
785 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
786 | APE_HOST_SEG_LEN_MAGIC); | |
787 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
788 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
789 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
790 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); | |
791 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
792 | APE_HOST_BEHAV_NO_PHYLOCK); | |
793 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, | |
794 | TG3_APE_HOST_DRVR_STATE_START); | |
795 | ||
796 | event = APE_EVENT_STATUS_STATE_START; | |
797 | break; | |
798 | case RESET_KIND_SHUTDOWN: | |
799 | /* With the interface we are currently using, | |
800 | * APE does not track driver state. Wiping | |
801 | * out the HOST SEGMENT SIGNATURE forces | |
802 | * the APE to assume OS absent status. | |
803 | */ | |
804 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
805 | ||
806 | if (device_may_wakeup(&tp->pdev->dev) && | |
807 | tg3_flag(tp, WOL_ENABLE)) { | |
808 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, | |
809 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
810 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
811 | } else | |
812 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
813 | ||
814 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
815 | ||
816 | event = APE_EVENT_STATUS_STATE_UNLOAD; | |
817 | break; | |
818 | case RESET_KIND_SUSPEND: | |
819 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
820 | break; | |
821 | default: | |
822 | return; | |
823 | } | |
824 | ||
825 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
826 | ||
827 | tg3_ape_send_event(tp, event); | |
828 | } | |
829 | ||
1da177e4 LT |
830 | static void tg3_disable_ints(struct tg3 *tp) |
831 | { | |
89aeb3bc MC |
832 | int i; |
833 | ||
1da177e4 LT |
834 | tw32(TG3PCI_MISC_HOST_CTRL, |
835 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
836 | for (i = 0; i < tp->irq_max; i++) |
837 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
838 | } |
839 | ||
1da177e4 LT |
840 | static void tg3_enable_ints(struct tg3 *tp) |
841 | { | |
89aeb3bc | 842 | int i; |
89aeb3bc | 843 | |
bbe832c0 MC |
844 | tp->irq_sync = 0; |
845 | wmb(); | |
846 | ||
1da177e4 LT |
847 | tw32(TG3PCI_MISC_HOST_CTRL, |
848 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 849 | |
f89f38b8 | 850 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
851 | for (i = 0; i < tp->irq_cnt; i++) { |
852 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 853 | |
898a56f8 | 854 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
63c3a66f | 855 | if (tg3_flag(tp, 1SHOT_MSI)) |
89aeb3bc | 856 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
f19af9c2 | 857 | |
f89f38b8 | 858 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 859 | } |
f19af9c2 MC |
860 | |
861 | /* Force an initial interrupt */ | |
63c3a66f | 862 | if (!tg3_flag(tp, TAGGED_STATUS) && |
f19af9c2 MC |
863 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) |
864 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
865 | else | |
f89f38b8 MC |
866 | tw32(HOSTCC_MODE, tp->coal_now); |
867 | ||
868 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
869 | } |
870 | ||
17375d25 | 871 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 872 | { |
17375d25 | 873 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 874 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
875 | unsigned int work_exists = 0; |
876 | ||
877 | /* check for phy events */ | |
63c3a66f | 878 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
04237ddd MC |
879 | if (sblk->status & SD_STATUS_LINK_CHG) |
880 | work_exists = 1; | |
881 | } | |
882 | /* check for RX/TX work to do */ | |
f3f3f27e | 883 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 884 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
885 | work_exists = 1; |
886 | ||
887 | return work_exists; | |
888 | } | |
889 | ||
17375d25 | 890 | /* tg3_int_reenable |
04237ddd MC |
891 | * similar to tg3_enable_ints, but it accurately determines whether there |
892 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 893 | * which reenables interrupts |
1da177e4 | 894 | */ |
17375d25 | 895 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 896 | { |
17375d25 MC |
897 | struct tg3 *tp = tnapi->tp; |
898 | ||
898a56f8 | 899 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
900 | mmiowb(); |
901 | ||
fac9b83e DM |
902 | /* When doing tagged status, this work check is unnecessary. |
903 | * The last_tag we write above tells the chip which piece of | |
904 | * work we've completed. | |
905 | */ | |
63c3a66f | 906 | if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) |
04237ddd | 907 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 908 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
909 | } |
910 | ||
1da177e4 LT |
911 | static void tg3_switch_clocks(struct tg3 *tp) |
912 | { | |
f6eb9b1f | 913 | u32 clock_ctrl; |
1da177e4 LT |
914 | u32 orig_clock_ctrl; |
915 | ||
63c3a66f | 916 | if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) |
4cf78e4f MC |
917 | return; |
918 | ||
f6eb9b1f MC |
919 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
920 | ||
1da177e4 LT |
921 | orig_clock_ctrl = clock_ctrl; |
922 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
923 | CLOCK_CTRL_CLKRUN_OENABLE | | |
924 | 0x1f); | |
925 | tp->pci_clock_ctrl = clock_ctrl; | |
926 | ||
63c3a66f | 927 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 | 928 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { |
b401e9e2 MC |
929 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
930 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
931 | } |
932 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
933 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
934 | clock_ctrl | | |
935 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
936 | 40); | |
937 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
938 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
939 | 40); | |
1da177e4 | 940 | } |
b401e9e2 | 941 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
942 | } |
943 | ||
944 | #define PHY_BUSY_LOOPS 5000 | |
945 | ||
946 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
947 | { | |
948 | u32 frame_val; | |
949 | unsigned int loops; | |
950 | int ret; | |
951 | ||
952 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
953 | tw32_f(MAC_MI_MODE, | |
954 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
955 | udelay(80); | |
956 | } | |
957 | ||
958 | *val = 0x0; | |
959 | ||
882e9793 | 960 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
961 | MI_COM_PHY_ADDR_MASK); |
962 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
963 | MI_COM_REG_ADDR_MASK); | |
964 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 965 | |
1da177e4 LT |
966 | tw32_f(MAC_MI_COM, frame_val); |
967 | ||
968 | loops = PHY_BUSY_LOOPS; | |
969 | while (loops != 0) { | |
970 | udelay(10); | |
971 | frame_val = tr32(MAC_MI_COM); | |
972 | ||
973 | if ((frame_val & MI_COM_BUSY) == 0) { | |
974 | udelay(5); | |
975 | frame_val = tr32(MAC_MI_COM); | |
976 | break; | |
977 | } | |
978 | loops -= 1; | |
979 | } | |
980 | ||
981 | ret = -EBUSY; | |
982 | if (loops != 0) { | |
983 | *val = frame_val & MI_COM_DATA_MASK; | |
984 | ret = 0; | |
985 | } | |
986 | ||
987 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
988 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
989 | udelay(80); | |
990 | } | |
991 | ||
992 | return ret; | |
993 | } | |
994 | ||
995 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
996 | { | |
997 | u32 frame_val; | |
998 | unsigned int loops; | |
999 | int ret; | |
1000 | ||
f07e9af3 | 1001 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
221c5637 | 1002 | (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) |
b5d3772c MC |
1003 | return 0; |
1004 | ||
1da177e4 LT |
1005 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
1006 | tw32_f(MAC_MI_MODE, | |
1007 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
1008 | udelay(80); | |
1009 | } | |
1010 | ||
882e9793 | 1011 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
1012 | MI_COM_PHY_ADDR_MASK); |
1013 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
1014 | MI_COM_REG_ADDR_MASK); | |
1015 | frame_val |= (val & MI_COM_DATA_MASK); | |
1016 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 1017 | |
1da177e4 LT |
1018 | tw32_f(MAC_MI_COM, frame_val); |
1019 | ||
1020 | loops = PHY_BUSY_LOOPS; | |
1021 | while (loops != 0) { | |
1022 | udelay(10); | |
1023 | frame_val = tr32(MAC_MI_COM); | |
1024 | if ((frame_val & MI_COM_BUSY) == 0) { | |
1025 | udelay(5); | |
1026 | frame_val = tr32(MAC_MI_COM); | |
1027 | break; | |
1028 | } | |
1029 | loops -= 1; | |
1030 | } | |
1031 | ||
1032 | ret = -EBUSY; | |
1033 | if (loops != 0) | |
1034 | ret = 0; | |
1035 | ||
1036 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
1037 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1038 | udelay(80); | |
1039 | } | |
1040 | ||
1041 | return ret; | |
1042 | } | |
1043 | ||
b0988c15 MC |
1044 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
1045 | { | |
1046 | int err; | |
1047 | ||
1048 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1049 | if (err) | |
1050 | goto done; | |
1051 | ||
1052 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1053 | if (err) | |
1054 | goto done; | |
1055 | ||
1056 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1057 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1058 | if (err) | |
1059 | goto done; | |
1060 | ||
1061 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
1062 | ||
1063 | done: | |
1064 | return err; | |
1065 | } | |
1066 | ||
1067 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
1068 | { | |
1069 | int err; | |
1070 | ||
1071 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1072 | if (err) | |
1073 | goto done; | |
1074 | ||
1075 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1076 | if (err) | |
1077 | goto done; | |
1078 | ||
1079 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1080 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1081 | if (err) | |
1082 | goto done; | |
1083 | ||
1084 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
1085 | ||
1086 | done: | |
1087 | return err; | |
1088 | } | |
1089 | ||
1090 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) | |
1091 | { | |
1092 | int err; | |
1093 | ||
1094 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1095 | if (!err) | |
1096 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
1097 | ||
1098 | return err; | |
1099 | } | |
1100 | ||
1101 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
1102 | { | |
1103 | int err; | |
1104 | ||
1105 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1106 | if (!err) | |
1107 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1108 | ||
1109 | return err; | |
1110 | } | |
1111 | ||
15ee95c3 MC |
1112 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) |
1113 | { | |
1114 | int err; | |
1115 | ||
1116 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1117 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | | |
1118 | MII_TG3_AUXCTL_SHDWSEL_MISC); | |
1119 | if (!err) | |
1120 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); | |
1121 | ||
1122 | return err; | |
1123 | } | |
1124 | ||
b4bd2929 MC |
1125 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) |
1126 | { | |
1127 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) | |
1128 | set |= MII_TG3_AUXCTL_MISC_WREN; | |
1129 | ||
1130 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); | |
1131 | } | |
1132 | ||
1d36ba45 MC |
1133 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ |
1134 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1135 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ | |
1136 | MII_TG3_AUXCTL_ACTL_TX_6DB) | |
1137 | ||
1138 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ | |
1139 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1140 | MII_TG3_AUXCTL_ACTL_TX_6DB); | |
1141 | ||
95e2869a MC |
1142 | static int tg3_bmcr_reset(struct tg3 *tp) |
1143 | { | |
1144 | u32 phy_control; | |
1145 | int limit, err; | |
1146 | ||
1147 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
1148 | * clears or we time out. | |
1149 | */ | |
1150 | phy_control = BMCR_RESET; | |
1151 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
1152 | if (err != 0) | |
1153 | return -EBUSY; | |
1154 | ||
1155 | limit = 5000; | |
1156 | while (limit--) { | |
1157 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
1158 | if (err != 0) | |
1159 | return -EBUSY; | |
1160 | ||
1161 | if ((phy_control & BMCR_RESET) == 0) { | |
1162 | udelay(40); | |
1163 | break; | |
1164 | } | |
1165 | udelay(10); | |
1166 | } | |
d4675b52 | 1167 | if (limit < 0) |
95e2869a MC |
1168 | return -EBUSY; |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
158d7abd MC |
1173 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
1174 | { | |
3d16543d | 1175 | struct tg3 *tp = bp->priv; |
158d7abd MC |
1176 | u32 val; |
1177 | ||
24bb4fb6 | 1178 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1179 | |
1180 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
1181 | val = -EIO; |
1182 | ||
1183 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
1184 | |
1185 | return val; | |
1186 | } | |
1187 | ||
1188 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
1189 | { | |
3d16543d | 1190 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 1191 | u32 ret = 0; |
158d7abd | 1192 | |
24bb4fb6 | 1193 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1194 | |
1195 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 1196 | ret = -EIO; |
158d7abd | 1197 | |
24bb4fb6 MC |
1198 | spin_unlock_bh(&tp->lock); |
1199 | ||
1200 | return ret; | |
158d7abd MC |
1201 | } |
1202 | ||
1203 | static int tg3_mdio_reset(struct mii_bus *bp) | |
1204 | { | |
1205 | return 0; | |
1206 | } | |
1207 | ||
9c61d6bc | 1208 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
1209 | { |
1210 | u32 val; | |
fcb389df | 1211 | struct phy_device *phydev; |
a9daf367 | 1212 | |
3f0e3ad7 | 1213 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 1214 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
1215 | case PHY_ID_BCM50610: |
1216 | case PHY_ID_BCM50610M: | |
fcb389df MC |
1217 | val = MAC_PHYCFG2_50610_LED_MODES; |
1218 | break; | |
6a443a0f | 1219 | case PHY_ID_BCMAC131: |
fcb389df MC |
1220 | val = MAC_PHYCFG2_AC131_LED_MODES; |
1221 | break; | |
6a443a0f | 1222 | case PHY_ID_RTL8211C: |
fcb389df MC |
1223 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
1224 | break; | |
6a443a0f | 1225 | case PHY_ID_RTL8201E: |
fcb389df MC |
1226 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
1227 | break; | |
1228 | default: | |
a9daf367 | 1229 | return; |
fcb389df MC |
1230 | } |
1231 | ||
1232 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
1233 | tw32(MAC_PHYCFG2, val); | |
1234 | ||
1235 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
1236 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
1237 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1238 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
1239 | tw32(MAC_PHYCFG1, val); |
1240 | ||
1241 | return; | |
1242 | } | |
1243 | ||
63c3a66f | 1244 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) |
fcb389df MC |
1245 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
1246 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1247 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1248 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1249 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1250 | MAC_PHYCFG2_INBAND_ENABLE; | |
1251 | ||
1252 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 1253 | |
bb85fbb6 MC |
1254 | val = tr32(MAC_PHYCFG1); |
1255 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1256 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
63c3a66f JP |
1257 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1258 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 | 1259 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; |
63c3a66f | 1260 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1261 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; |
1262 | } | |
bb85fbb6 MC |
1263 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1264 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1265 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1266 | |
a9daf367 MC |
1267 | val = tr32(MAC_EXT_RGMII_MODE); |
1268 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1269 | MAC_RGMII_MODE_RX_QUALITY | | |
1270 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1271 | MAC_RGMII_MODE_RX_ENG_DET | | |
1272 | MAC_RGMII_MODE_TX_ENABLE | | |
1273 | MAC_RGMII_MODE_TX_LOWPWR | | |
1274 | MAC_RGMII_MODE_TX_RESET); | |
63c3a66f JP |
1275 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1276 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 MC |
1277 | val |= MAC_RGMII_MODE_RX_INT_B | |
1278 | MAC_RGMII_MODE_RX_QUALITY | | |
1279 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1280 | MAC_RGMII_MODE_RX_ENG_DET; | |
63c3a66f | 1281 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1282 | val |= MAC_RGMII_MODE_TX_ENABLE | |
1283 | MAC_RGMII_MODE_TX_LOWPWR | | |
1284 | MAC_RGMII_MODE_TX_RESET; | |
1285 | } | |
1286 | tw32(MAC_EXT_RGMII_MODE, val); | |
1287 | } | |
1288 | ||
158d7abd MC |
1289 | static void tg3_mdio_start(struct tg3 *tp) |
1290 | { | |
158d7abd MC |
1291 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1292 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1293 | udelay(80); | |
a9daf367 | 1294 | |
63c3a66f | 1295 | if (tg3_flag(tp, MDIOBUS_INITED) && |
9ea4818d MC |
1296 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
1297 | tg3_mdio_config_5785(tp); | |
1298 | } | |
1299 | ||
1300 | static int tg3_mdio_init(struct tg3 *tp) | |
1301 | { | |
1302 | int i; | |
1303 | u32 reg; | |
1304 | struct phy_device *phydev; | |
1305 | ||
63c3a66f | 1306 | if (tg3_flag(tp, 5717_PLUS)) { |
9c7df915 | 1307 | u32 is_serdes; |
882e9793 | 1308 | |
69f11c99 | 1309 | tp->phy_addr = tp->pci_fn + 1; |
882e9793 | 1310 | |
d1ec96af MC |
1311 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1312 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1313 | else | |
1314 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1315 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1316 | if (is_serdes) |
1317 | tp->phy_addr += 7; | |
1318 | } else | |
3f0e3ad7 | 1319 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1320 | |
158d7abd MC |
1321 | tg3_mdio_start(tp); |
1322 | ||
63c3a66f | 1323 | if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) |
158d7abd MC |
1324 | return 0; |
1325 | ||
298cf9be LB |
1326 | tp->mdio_bus = mdiobus_alloc(); |
1327 | if (tp->mdio_bus == NULL) | |
1328 | return -ENOMEM; | |
158d7abd | 1329 | |
298cf9be LB |
1330 | tp->mdio_bus->name = "tg3 mdio bus"; |
1331 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1332 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1333 | tp->mdio_bus->priv = tp; |
1334 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1335 | tp->mdio_bus->read = &tg3_mdio_read; | |
1336 | tp->mdio_bus->write = &tg3_mdio_write; | |
1337 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1338 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1339 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1340 | |
1341 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1342 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1343 | |
1344 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1345 | * Unfortunately, it does not ensure the PHY is powered up before | |
1346 | * accessing the PHY ID registers. A chip reset is the | |
1347 | * quickest way to bring the device back to an operational state.. | |
1348 | */ | |
1349 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1350 | tg3_bmcr_reset(tp); | |
1351 | ||
298cf9be | 1352 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1353 | if (i) { |
ab96b241 | 1354 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1355 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1356 | return i; |
1357 | } | |
158d7abd | 1358 | |
3f0e3ad7 | 1359 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1360 | |
9c61d6bc | 1361 | if (!phydev || !phydev->drv) { |
ab96b241 | 1362 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1363 | mdiobus_unregister(tp->mdio_bus); |
1364 | mdiobus_free(tp->mdio_bus); | |
1365 | return -ENODEV; | |
1366 | } | |
1367 | ||
1368 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1369 | case PHY_ID_BCM57780: |
321d32a0 | 1370 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1371 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1372 | break; |
6a443a0f MC |
1373 | case PHY_ID_BCM50610: |
1374 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1375 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1376 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1377 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1378 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
63c3a66f | 1379 | if (tg3_flag(tp, RGMII_INBAND_DISABLE)) |
a9daf367 | 1380 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
63c3a66f | 1381 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
a9daf367 | 1382 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; |
63c3a66f | 1383 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 | 1384 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; |
fcb389df | 1385 | /* fallthru */ |
6a443a0f | 1386 | case PHY_ID_RTL8211C: |
fcb389df | 1387 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1388 | break; |
6a443a0f MC |
1389 | case PHY_ID_RTL8201E: |
1390 | case PHY_ID_BCMAC131: | |
a9daf367 | 1391 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1392 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1393 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1394 | break; |
1395 | } | |
1396 | ||
63c3a66f | 1397 | tg3_flag_set(tp, MDIOBUS_INITED); |
9c61d6bc MC |
1398 | |
1399 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1400 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1401 | |
1402 | return 0; | |
158d7abd MC |
1403 | } |
1404 | ||
1405 | static void tg3_mdio_fini(struct tg3 *tp) | |
1406 | { | |
63c3a66f JP |
1407 | if (tg3_flag(tp, MDIOBUS_INITED)) { |
1408 | tg3_flag_clear(tp, MDIOBUS_INITED); | |
298cf9be LB |
1409 | mdiobus_unregister(tp->mdio_bus); |
1410 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1411 | } |
1412 | } | |
1413 | ||
4ba526ce MC |
1414 | /* tp->lock is held. */ |
1415 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1416 | { | |
1417 | u32 val; | |
1418 | ||
1419 | val = tr32(GRC_RX_CPU_EVENT); | |
1420 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1421 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1422 | ||
1423 | tp->last_event_jiffies = jiffies; | |
1424 | } | |
1425 | ||
1426 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1427 | ||
95e2869a MC |
1428 | /* tp->lock is held. */ |
1429 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1430 | { | |
1431 | int i; | |
4ba526ce MC |
1432 | unsigned int delay_cnt; |
1433 | long time_remain; | |
1434 | ||
1435 | /* If enough time has passed, no wait is necessary. */ | |
1436 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1437 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1438 | (long)jiffies; | |
1439 | if (time_remain < 0) | |
1440 | return; | |
1441 | ||
1442 | /* Check if we can shorten the wait time. */ | |
1443 | delay_cnt = jiffies_to_usecs(time_remain); | |
1444 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1445 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1446 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1447 | |
4ba526ce | 1448 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1449 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1450 | break; | |
4ba526ce | 1451 | udelay(8); |
95e2869a MC |
1452 | } |
1453 | } | |
1454 | ||
1455 | /* tp->lock is held. */ | |
1456 | static void tg3_ump_link_report(struct tg3 *tp) | |
1457 | { | |
1458 | u32 reg; | |
1459 | u32 val; | |
1460 | ||
63c3a66f | 1461 | if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) |
95e2869a MC |
1462 | return; |
1463 | ||
1464 | tg3_wait_for_event_ack(tp); | |
1465 | ||
1466 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1467 | ||
1468 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1469 | ||
1470 | val = 0; | |
1471 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1472 | val = reg << 16; | |
1473 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1474 | val |= (reg & 0xffff); | |
1475 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1476 | ||
1477 | val = 0; | |
1478 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1479 | val = reg << 16; | |
1480 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1481 | val |= (reg & 0xffff); | |
1482 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1483 | ||
1484 | val = 0; | |
f07e9af3 | 1485 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1486 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1487 | val = reg << 16; | |
1488 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1489 | val |= (reg & 0xffff); | |
1490 | } | |
1491 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1492 | ||
1493 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1494 | val = reg << 16; | |
1495 | else | |
1496 | val = 0; | |
1497 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1498 | ||
4ba526ce | 1499 | tg3_generate_fw_event(tp); |
95e2869a MC |
1500 | } |
1501 | ||
8d5a89b3 MC |
1502 | /* tp->lock is held. */ |
1503 | static void tg3_stop_fw(struct tg3 *tp) | |
1504 | { | |
1505 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { | |
1506 | /* Wait for RX cpu to ACK the previous event. */ | |
1507 | tg3_wait_for_event_ack(tp); | |
1508 | ||
1509 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
1510 | ||
1511 | tg3_generate_fw_event(tp); | |
1512 | ||
1513 | /* Wait for RX cpu to ACK this event. */ | |
1514 | tg3_wait_for_event_ack(tp); | |
1515 | } | |
1516 | } | |
1517 | ||
fd6d3f0e MC |
1518 | /* tp->lock is held. */ |
1519 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
1520 | { | |
1521 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, | |
1522 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1523 | ||
1524 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
1525 | switch (kind) { | |
1526 | case RESET_KIND_INIT: | |
1527 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1528 | DRV_STATE_START); | |
1529 | break; | |
1530 | ||
1531 | case RESET_KIND_SHUTDOWN: | |
1532 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1533 | DRV_STATE_UNLOAD); | |
1534 | break; | |
1535 | ||
1536 | case RESET_KIND_SUSPEND: | |
1537 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1538 | DRV_STATE_SUSPEND); | |
1539 | break; | |
1540 | ||
1541 | default: | |
1542 | break; | |
1543 | } | |
1544 | } | |
1545 | ||
1546 | if (kind == RESET_KIND_INIT || | |
1547 | kind == RESET_KIND_SUSPEND) | |
1548 | tg3_ape_driver_state_change(tp, kind); | |
1549 | } | |
1550 | ||
1551 | /* tp->lock is held. */ | |
1552 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
1553 | { | |
1554 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
1555 | switch (kind) { | |
1556 | case RESET_KIND_INIT: | |
1557 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1558 | DRV_STATE_START_DONE); | |
1559 | break; | |
1560 | ||
1561 | case RESET_KIND_SHUTDOWN: | |
1562 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1563 | DRV_STATE_UNLOAD_DONE); | |
1564 | break; | |
1565 | ||
1566 | default: | |
1567 | break; | |
1568 | } | |
1569 | } | |
1570 | ||
1571 | if (kind == RESET_KIND_SHUTDOWN) | |
1572 | tg3_ape_driver_state_change(tp, kind); | |
1573 | } | |
1574 | ||
1575 | /* tp->lock is held. */ | |
1576 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
1577 | { | |
1578 | if (tg3_flag(tp, ENABLE_ASF)) { | |
1579 | switch (kind) { | |
1580 | case RESET_KIND_INIT: | |
1581 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1582 | DRV_STATE_START); | |
1583 | break; | |
1584 | ||
1585 | case RESET_KIND_SHUTDOWN: | |
1586 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1587 | DRV_STATE_UNLOAD); | |
1588 | break; | |
1589 | ||
1590 | case RESET_KIND_SUSPEND: | |
1591 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1592 | DRV_STATE_SUSPEND); | |
1593 | break; | |
1594 | ||
1595 | default: | |
1596 | break; | |
1597 | } | |
1598 | } | |
1599 | } | |
1600 | ||
1601 | static int tg3_poll_fw(struct tg3 *tp) | |
1602 | { | |
1603 | int i; | |
1604 | u32 val; | |
1605 | ||
1606 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
1607 | /* Wait up to 20ms for init done. */ | |
1608 | for (i = 0; i < 200; i++) { | |
1609 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) | |
1610 | return 0; | |
1611 | udelay(100); | |
1612 | } | |
1613 | return -ENODEV; | |
1614 | } | |
1615 | ||
1616 | /* Wait for firmware initialization to complete. */ | |
1617 | for (i = 0; i < 100000; i++) { | |
1618 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
1619 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
1620 | break; | |
1621 | udelay(10); | |
1622 | } | |
1623 | ||
1624 | /* Chip might not be fitted with firmware. Some Sun onboard | |
1625 | * parts are configured like that. So don't signal the timeout | |
1626 | * of the above loop as an error, but do report the lack of | |
1627 | * running firmware once. | |
1628 | */ | |
1629 | if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { | |
1630 | tg3_flag_set(tp, NO_FWARE_REPORTED); | |
1631 | ||
1632 | netdev_info(tp->dev, "No firmware running\n"); | |
1633 | } | |
1634 | ||
1635 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
1636 | /* The 57765 A0 needs a little more | |
1637 | * time to do some important work. | |
1638 | */ | |
1639 | mdelay(10); | |
1640 | } | |
1641 | ||
1642 | return 0; | |
1643 | } | |
1644 | ||
95e2869a MC |
1645 | static void tg3_link_report(struct tg3 *tp) |
1646 | { | |
1647 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1648 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1649 | tg3_ump_link_report(tp); |
1650 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1651 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1652 | (tp->link_config.active_speed == SPEED_1000 ? | |
1653 | 1000 : | |
1654 | (tp->link_config.active_speed == SPEED_100 ? | |
1655 | 100 : 10)), | |
1656 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1657 | "full" : "half")); | |
1658 | ||
1659 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1660 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1661 | "on" : "off", | |
1662 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1663 | "on" : "off"); | |
47007831 MC |
1664 | |
1665 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) | |
1666 | netdev_info(tp->dev, "EEE is %s\n", | |
1667 | tp->setlpicnt ? "enabled" : "disabled"); | |
1668 | ||
95e2869a MC |
1669 | tg3_ump_link_report(tp); |
1670 | } | |
1671 | } | |
1672 | ||
95e2869a MC |
1673 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) |
1674 | { | |
1675 | u16 miireg; | |
1676 | ||
e18ce346 | 1677 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1678 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1679 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1680 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1681 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1682 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1683 | else | |
1684 | miireg = 0; | |
1685 | ||
1686 | return miireg; | |
1687 | } | |
1688 | ||
95e2869a MC |
1689 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1690 | { | |
1691 | u8 cap = 0; | |
1692 | ||
f3791cdf MC |
1693 | if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) { |
1694 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1695 | } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) { | |
1696 | if (lcladv & ADVERTISE_1000XPAUSE) | |
1697 | cap = FLOW_CTRL_RX; | |
1698 | if (rmtadv & ADVERTISE_1000XPAUSE) | |
e18ce346 | 1699 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1700 | } |
1701 | ||
1702 | return cap; | |
1703 | } | |
1704 | ||
f51f3562 | 1705 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1706 | { |
b02fd9e3 | 1707 | u8 autoneg; |
f51f3562 | 1708 | u8 flowctrl = 0; |
95e2869a MC |
1709 | u32 old_rx_mode = tp->rx_mode; |
1710 | u32 old_tx_mode = tp->tx_mode; | |
1711 | ||
63c3a66f | 1712 | if (tg3_flag(tp, USE_PHYLIB)) |
3f0e3ad7 | 1713 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1714 | else |
1715 | autoneg = tp->link_config.autoneg; | |
1716 | ||
63c3a66f | 1717 | if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { |
f07e9af3 | 1718 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1719 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1720 | else |
bc02ff95 | 1721 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1722 | } else |
1723 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1724 | |
f51f3562 | 1725 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1726 | |
e18ce346 | 1727 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1728 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1729 | else | |
1730 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1731 | ||
f51f3562 | 1732 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1733 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1734 | |
e18ce346 | 1735 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1736 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1737 | else | |
1738 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1739 | ||
f51f3562 | 1740 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1741 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1742 | } |
1743 | ||
b02fd9e3 MC |
1744 | static void tg3_adjust_link(struct net_device *dev) |
1745 | { | |
1746 | u8 oldflowctrl, linkmesg = 0; | |
1747 | u32 mac_mode, lcl_adv, rmt_adv; | |
1748 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1749 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1750 | |
24bb4fb6 | 1751 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1752 | |
1753 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1754 | MAC_MODE_HALF_DUPLEX); | |
1755 | ||
1756 | oldflowctrl = tp->link_config.active_flowctrl; | |
1757 | ||
1758 | if (phydev->link) { | |
1759 | lcl_adv = 0; | |
1760 | rmt_adv = 0; | |
1761 | ||
1762 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1763 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1764 | else if (phydev->speed == SPEED_1000 || |
1765 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1766 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1767 | else |
1768 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1769 | |
1770 | if (phydev->duplex == DUPLEX_HALF) | |
1771 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1772 | else { | |
f88788f0 | 1773 | lcl_adv = mii_advertise_flowctrl( |
b02fd9e3 MC |
1774 | tp->link_config.flowctrl); |
1775 | ||
1776 | if (phydev->pause) | |
1777 | rmt_adv = LPA_PAUSE_CAP; | |
1778 | if (phydev->asym_pause) | |
1779 | rmt_adv |= LPA_PAUSE_ASYM; | |
1780 | } | |
1781 | ||
1782 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1783 | } else | |
1784 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1785 | ||
1786 | if (mac_mode != tp->mac_mode) { | |
1787 | tp->mac_mode = mac_mode; | |
1788 | tw32_f(MAC_MODE, tp->mac_mode); | |
1789 | udelay(40); | |
1790 | } | |
1791 | ||
fcb389df MC |
1792 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1793 | if (phydev->speed == SPEED_10) | |
1794 | tw32(MAC_MI_STAT, | |
1795 | MAC_MI_STAT_10MBPS_MODE | | |
1796 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1797 | else | |
1798 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1799 | } | |
1800 | ||
b02fd9e3 MC |
1801 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1802 | tw32(MAC_TX_LENGTHS, | |
1803 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1804 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1805 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1806 | else | |
1807 | tw32(MAC_TX_LENGTHS, | |
1808 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1809 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1810 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1811 | ||
1812 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1813 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1814 | phydev->speed != tp->link_config.active_speed || | |
1815 | phydev->duplex != tp->link_config.active_duplex || | |
1816 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1817 | linkmesg = 1; |
b02fd9e3 MC |
1818 | |
1819 | tp->link_config.active_speed = phydev->speed; | |
1820 | tp->link_config.active_duplex = phydev->duplex; | |
1821 | ||
24bb4fb6 | 1822 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1823 | |
1824 | if (linkmesg) | |
1825 | tg3_link_report(tp); | |
1826 | } | |
1827 | ||
1828 | static int tg3_phy_init(struct tg3 *tp) | |
1829 | { | |
1830 | struct phy_device *phydev; | |
1831 | ||
f07e9af3 | 1832 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1833 | return 0; |
1834 | ||
1835 | /* Bring the PHY back to a known state. */ | |
1836 | tg3_bmcr_reset(tp); | |
1837 | ||
3f0e3ad7 | 1838 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1839 | |
1840 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1841 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1842 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1843 | if (IS_ERR(phydev)) { |
ab96b241 | 1844 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1845 | return PTR_ERR(phydev); |
1846 | } | |
1847 | ||
b02fd9e3 | 1848 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1849 | switch (phydev->interface) { |
1850 | case PHY_INTERFACE_MODE_GMII: | |
1851 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 1852 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
1853 | phydev->supported &= (PHY_GBIT_FEATURES | |
1854 | SUPPORTED_Pause | | |
1855 | SUPPORTED_Asym_Pause); | |
1856 | break; | |
1857 | } | |
1858 | /* fallthru */ | |
9c61d6bc MC |
1859 | case PHY_INTERFACE_MODE_MII: |
1860 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1861 | SUPPORTED_Pause | | |
1862 | SUPPORTED_Asym_Pause); | |
1863 | break; | |
1864 | default: | |
3f0e3ad7 | 1865 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1866 | return -EINVAL; |
1867 | } | |
1868 | ||
f07e9af3 | 1869 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1870 | |
1871 | phydev->advertising = phydev->supported; | |
1872 | ||
b02fd9e3 MC |
1873 | return 0; |
1874 | } | |
1875 | ||
1876 | static void tg3_phy_start(struct tg3 *tp) | |
1877 | { | |
1878 | struct phy_device *phydev; | |
1879 | ||
f07e9af3 | 1880 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1881 | return; |
1882 | ||
3f0e3ad7 | 1883 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1884 | |
80096068 MC |
1885 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1886 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
b02fd9e3 MC |
1887 | phydev->speed = tp->link_config.orig_speed; |
1888 | phydev->duplex = tp->link_config.orig_duplex; | |
1889 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1890 | phydev->advertising = tp->link_config.orig_advertising; | |
1891 | } | |
1892 | ||
1893 | phy_start(phydev); | |
1894 | ||
1895 | phy_start_aneg(phydev); | |
1896 | } | |
1897 | ||
1898 | static void tg3_phy_stop(struct tg3 *tp) | |
1899 | { | |
f07e9af3 | 1900 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1901 | return; |
1902 | ||
3f0e3ad7 | 1903 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1904 | } |
1905 | ||
1906 | static void tg3_phy_fini(struct tg3 *tp) | |
1907 | { | |
f07e9af3 | 1908 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 1909 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 1910 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1911 | } |
1912 | } | |
1913 | ||
941ec90f MC |
1914 | static int tg3_phy_set_extloopbk(struct tg3 *tp) |
1915 | { | |
1916 | int err; | |
1917 | u32 val; | |
1918 | ||
1919 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
1920 | return 0; | |
1921 | ||
1922 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { | |
1923 | /* Cannot do read-modify-write on 5401 */ | |
1924 | err = tg3_phy_auxctl_write(tp, | |
1925 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, | |
1926 | MII_TG3_AUXCTL_ACTL_EXTLOOPBK | | |
1927 | 0x4c20); | |
1928 | goto done; | |
1929 | } | |
1930 | ||
1931 | err = tg3_phy_auxctl_read(tp, | |
1932 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
1933 | if (err) | |
1934 | return err; | |
1935 | ||
1936 | val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK; | |
1937 | err = tg3_phy_auxctl_write(tp, | |
1938 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val); | |
1939 | ||
1940 | done: | |
1941 | return err; | |
1942 | } | |
1943 | ||
7f97a4bd MC |
1944 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1945 | { | |
1946 | u32 phytest; | |
1947 | ||
1948 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1949 | u32 phy; | |
1950 | ||
1951 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1952 | phytest | MII_TG3_FET_SHADOW_EN); | |
1953 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1954 | if (enable) | |
1955 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1956 | else | |
1957 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1958 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1959 | } | |
1960 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1961 | } | |
1962 | } | |
1963 | ||
6833c043 MC |
1964 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1965 | { | |
1966 | u32 reg; | |
1967 | ||
63c3a66f JP |
1968 | if (!tg3_flag(tp, 5705_PLUS) || |
1969 | (tg3_flag(tp, 5717_PLUS) && | |
f07e9af3 | 1970 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
1971 | return; |
1972 | ||
f07e9af3 | 1973 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
1974 | tg3_phy_fet_toggle_apd(tp, enable); |
1975 | return; | |
1976 | } | |
1977 | ||
6833c043 MC |
1978 | reg = MII_TG3_MISC_SHDW_WREN | |
1979 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1980 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1981 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1982 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1983 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1984 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1985 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1986 | ||
1987 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1988 | ||
1989 | ||
1990 | reg = MII_TG3_MISC_SHDW_WREN | | |
1991 | MII_TG3_MISC_SHDW_APD_SEL | | |
1992 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1993 | if (enable) | |
1994 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1995 | ||
1996 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1997 | } | |
1998 | ||
9ef8ca99 MC |
1999 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
2000 | { | |
2001 | u32 phy; | |
2002 | ||
63c3a66f | 2003 | if (!tg3_flag(tp, 5705_PLUS) || |
f07e9af3 | 2004 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
2005 | return; |
2006 | ||
f07e9af3 | 2007 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
2008 | u32 ephy; |
2009 | ||
535ef6e1 MC |
2010 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
2011 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
2012 | ||
2013 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2014 | ephy | MII_TG3_FET_SHADOW_EN); | |
2015 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 2016 | if (enable) |
535ef6e1 | 2017 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 2018 | else |
535ef6e1 MC |
2019 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
2020 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 2021 | } |
535ef6e1 | 2022 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
2023 | } |
2024 | } else { | |
15ee95c3 MC |
2025 | int ret; |
2026 | ||
2027 | ret = tg3_phy_auxctl_read(tp, | |
2028 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); | |
2029 | if (!ret) { | |
9ef8ca99 MC |
2030 | if (enable) |
2031 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
2032 | else | |
2033 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
b4bd2929 MC |
2034 | tg3_phy_auxctl_write(tp, |
2035 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); | |
9ef8ca99 MC |
2036 | } |
2037 | } | |
2038 | } | |
2039 | ||
1da177e4 LT |
2040 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
2041 | { | |
15ee95c3 | 2042 | int ret; |
1da177e4 LT |
2043 | u32 val; |
2044 | ||
f07e9af3 | 2045 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
2046 | return; |
2047 | ||
15ee95c3 MC |
2048 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); |
2049 | if (!ret) | |
b4bd2929 MC |
2050 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, |
2051 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); | |
1da177e4 LT |
2052 | } |
2053 | ||
b2a5c19c MC |
2054 | static void tg3_phy_apply_otp(struct tg3 *tp) |
2055 | { | |
2056 | u32 otp, phy; | |
2057 | ||
2058 | if (!tp->phy_otp) | |
2059 | return; | |
2060 | ||
2061 | otp = tp->phy_otp; | |
2062 | ||
1d36ba45 MC |
2063 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) |
2064 | return; | |
b2a5c19c MC |
2065 | |
2066 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
2067 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
2068 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
2069 | ||
2070 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
2071 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
2072 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
2073 | ||
2074 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
2075 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
2076 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
2077 | ||
2078 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
2079 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
2080 | ||
2081 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
2082 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
2083 | ||
2084 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
2085 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
2086 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
2087 | ||
1d36ba45 | 2088 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
b2a5c19c MC |
2089 | } |
2090 | ||
52b02d04 MC |
2091 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
2092 | { | |
2093 | u32 val; | |
2094 | ||
2095 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
2096 | return; | |
2097 | ||
2098 | tp->setlpicnt = 0; | |
2099 | ||
2100 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
2101 | current_link_up == 1 && | |
a6b68dab MC |
2102 | tp->link_config.active_duplex == DUPLEX_FULL && |
2103 | (tp->link_config.active_speed == SPEED_100 || | |
2104 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
2105 | u32 eeectl; |
2106 | ||
2107 | if (tp->link_config.active_speed == SPEED_1000) | |
2108 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
2109 | else | |
2110 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
2111 | ||
2112 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
2113 | ||
3110f5f5 MC |
2114 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
2115 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 2116 | |
b0c5943f MC |
2117 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || |
2118 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) | |
52b02d04 MC |
2119 | tp->setlpicnt = 2; |
2120 | } | |
2121 | ||
2122 | if (!tp->setlpicnt) { | |
b715ce94 MC |
2123 | if (current_link_up == 1 && |
2124 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
2125 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | |
2126 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2127 | } | |
2128 | ||
52b02d04 MC |
2129 | val = tr32(TG3_CPMU_EEE_MODE); |
2130 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
2131 | } | |
2132 | } | |
2133 | ||
b0c5943f MC |
2134 | static void tg3_phy_eee_enable(struct tg3 *tp) |
2135 | { | |
2136 | u32 val; | |
2137 | ||
2138 | if (tp->link_config.active_speed == SPEED_1000 && | |
2139 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2140 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
55086ad9 | 2141 | tg3_flag(tp, 57765_CLASS)) && |
b0c5943f | 2142 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
b715ce94 MC |
2143 | val = MII_TG3_DSP_TAP26_ALNOKO | |
2144 | MII_TG3_DSP_TAP26_RMRXSTO; | |
2145 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
b0c5943f MC |
2146 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
2147 | } | |
2148 | ||
2149 | val = tr32(TG3_CPMU_EEE_MODE); | |
2150 | tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
2151 | } | |
2152 | ||
1da177e4 LT |
2153 | static int tg3_wait_macro_done(struct tg3 *tp) |
2154 | { | |
2155 | int limit = 100; | |
2156 | ||
2157 | while (limit--) { | |
2158 | u32 tmp32; | |
2159 | ||
f08aa1a8 | 2160 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
2161 | if ((tmp32 & 0x1000) == 0) |
2162 | break; | |
2163 | } | |
2164 | } | |
d4675b52 | 2165 | if (limit < 0) |
1da177e4 LT |
2166 | return -EBUSY; |
2167 | ||
2168 | return 0; | |
2169 | } | |
2170 | ||
2171 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
2172 | { | |
2173 | static const u32 test_pat[4][6] = { | |
2174 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
2175 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
2176 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
2177 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
2178 | }; | |
2179 | int chan; | |
2180 | ||
2181 | for (chan = 0; chan < 4; chan++) { | |
2182 | int i; | |
2183 | ||
2184 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2185 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2186 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
2187 | |
2188 | for (i = 0; i < 6; i++) | |
2189 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
2190 | test_pat[chan][i]); | |
2191 | ||
f08aa1a8 | 2192 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
2193 | if (tg3_wait_macro_done(tp)) { |
2194 | *resetp = 1; | |
2195 | return -EBUSY; | |
2196 | } | |
2197 | ||
2198 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2199 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2200 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
2201 | if (tg3_wait_macro_done(tp)) { |
2202 | *resetp = 1; | |
2203 | return -EBUSY; | |
2204 | } | |
2205 | ||
f08aa1a8 | 2206 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
2207 | if (tg3_wait_macro_done(tp)) { |
2208 | *resetp = 1; | |
2209 | return -EBUSY; | |
2210 | } | |
2211 | ||
2212 | for (i = 0; i < 6; i += 2) { | |
2213 | u32 low, high; | |
2214 | ||
2215 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
2216 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
2217 | tg3_wait_macro_done(tp)) { | |
2218 | *resetp = 1; | |
2219 | return -EBUSY; | |
2220 | } | |
2221 | low &= 0x7fff; | |
2222 | high &= 0x000f; | |
2223 | if (low != test_pat[chan][i] || | |
2224 | high != test_pat[chan][i+1]) { | |
2225 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
2226 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
2227 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
2228 | ||
2229 | return -EBUSY; | |
2230 | } | |
2231 | } | |
2232 | } | |
2233 | ||
2234 | return 0; | |
2235 | } | |
2236 | ||
2237 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
2238 | { | |
2239 | int chan; | |
2240 | ||
2241 | for (chan = 0; chan < 4; chan++) { | |
2242 | int i; | |
2243 | ||
2244 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2245 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2246 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
2247 | for (i = 0; i < 6; i++) |
2248 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 2249 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
2250 | if (tg3_wait_macro_done(tp)) |
2251 | return -EBUSY; | |
2252 | } | |
2253 | ||
2254 | return 0; | |
2255 | } | |
2256 | ||
2257 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
2258 | { | |
2259 | u32 reg32, phy9_orig; | |
2260 | int retries, do_phy_reset, err; | |
2261 | ||
2262 | retries = 10; | |
2263 | do_phy_reset = 1; | |
2264 | do { | |
2265 | if (do_phy_reset) { | |
2266 | err = tg3_bmcr_reset(tp); | |
2267 | if (err) | |
2268 | return err; | |
2269 | do_phy_reset = 0; | |
2270 | } | |
2271 | ||
2272 | /* Disable transmitter and interrupt. */ | |
2273 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
2274 | continue; | |
2275 | ||
2276 | reg32 |= 0x3000; | |
2277 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2278 | ||
2279 | /* Set full-duplex, 1000 mbps. */ | |
2280 | tg3_writephy(tp, MII_BMCR, | |
221c5637 | 2281 | BMCR_FULLDPLX | BMCR_SPEED1000); |
1da177e4 LT |
2282 | |
2283 | /* Set to master mode. */ | |
221c5637 | 2284 | if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) |
1da177e4 LT |
2285 | continue; |
2286 | ||
221c5637 MC |
2287 | tg3_writephy(tp, MII_CTRL1000, |
2288 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
1da177e4 | 2289 | |
1d36ba45 MC |
2290 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
2291 | if (err) | |
2292 | return err; | |
1da177e4 LT |
2293 | |
2294 | /* Block the PHY control access. */ | |
6ee7c0a0 | 2295 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
2296 | |
2297 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
2298 | if (!err) | |
2299 | break; | |
2300 | } while (--retries); | |
2301 | ||
2302 | err = tg3_phy_reset_chanpat(tp); | |
2303 | if (err) | |
2304 | return err; | |
2305 | ||
6ee7c0a0 | 2306 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
2307 | |
2308 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 2309 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 | 2310 | |
1d36ba45 | 2311 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2312 | |
221c5637 | 2313 | tg3_writephy(tp, MII_CTRL1000, phy9_orig); |
1da177e4 LT |
2314 | |
2315 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
2316 | reg32 &= ~0x3000; | |
2317 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2318 | } else if (!err) | |
2319 | err = -EBUSY; | |
2320 | ||
2321 | return err; | |
2322 | } | |
2323 | ||
2324 | /* This will reset the tigon3 PHY if there is no valid | |
2325 | * link unless the FORCE argument is non-zero. | |
2326 | */ | |
2327 | static int tg3_phy_reset(struct tg3 *tp) | |
2328 | { | |
f833c4c1 | 2329 | u32 val, cpmuctrl; |
1da177e4 LT |
2330 | int err; |
2331 | ||
60189ddf | 2332 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2333 | val = tr32(GRC_MISC_CFG); |
2334 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
2335 | udelay(40); | |
2336 | } | |
f833c4c1 MC |
2337 | err = tg3_readphy(tp, MII_BMSR, &val); |
2338 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
2339 | if (err != 0) |
2340 | return -EBUSY; | |
2341 | ||
c8e1e82b MC |
2342 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
2343 | netif_carrier_off(tp->dev); | |
2344 | tg3_link_report(tp); | |
2345 | } | |
2346 | ||
1da177e4 LT |
2347 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2348 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2349 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2350 | err = tg3_phy_reset_5703_4_5(tp); | |
2351 | if (err) | |
2352 | return err; | |
2353 | goto out; | |
2354 | } | |
2355 | ||
b2a5c19c MC |
2356 | cpmuctrl = 0; |
2357 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2358 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2359 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2360 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2361 | tw32(TG3_CPMU_CTRL, | |
2362 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2363 | } | |
2364 | ||
1da177e4 LT |
2365 | err = tg3_bmcr_reset(tp); |
2366 | if (err) | |
2367 | return err; | |
2368 | ||
b2a5c19c | 2369 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2370 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2371 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2372 | |
2373 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2374 | } | |
2375 | ||
bcb37f6c MC |
2376 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2377 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2378 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2379 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2380 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2381 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2382 | udelay(40); | |
2383 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2384 | } | |
2385 | } | |
2386 | ||
63c3a66f | 2387 | if (tg3_flag(tp, 5717_PLUS) && |
f07e9af3 | 2388 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2389 | return 0; |
2390 | ||
b2a5c19c MC |
2391 | tg3_phy_apply_otp(tp); |
2392 | ||
f07e9af3 | 2393 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2394 | tg3_phy_toggle_apd(tp, true); |
2395 | else | |
2396 | tg3_phy_toggle_apd(tp, false); | |
2397 | ||
1da177e4 | 2398 | out: |
1d36ba45 MC |
2399 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && |
2400 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
6ee7c0a0 MC |
2401 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2402 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1d36ba45 | 2403 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2404 | } |
1d36ba45 | 2405 | |
f07e9af3 | 2406 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2407 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2408 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2409 | } |
1d36ba45 | 2410 | |
f07e9af3 | 2411 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1d36ba45 MC |
2412 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2413 | tg3_phydsp_write(tp, 0x000a, 0x310b); | |
2414 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2415 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
2416 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2417 | } | |
f07e9af3 | 2418 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
1d36ba45 MC |
2419 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2420 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
2421 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { | |
2422 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2423 | tg3_writephy(tp, MII_TG3_TEST1, | |
2424 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2425 | } else | |
2426 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
2427 | ||
2428 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2429 | } | |
c424cb24 | 2430 | } |
1d36ba45 | 2431 | |
1da177e4 LT |
2432 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2433 | /* support jumbo frames */ | |
79eb6904 | 2434 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 | 2435 | /* Cannot do read-modify-write on 5401 */ |
b4bd2929 | 2436 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
63c3a66f | 2437 | } else if (tg3_flag(tp, JUMBO_CAPABLE)) { |
1da177e4 | 2438 | /* Set bit 14 with read-modify-write to preserve other bits */ |
15ee95c3 MC |
2439 | err = tg3_phy_auxctl_read(tp, |
2440 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2441 | if (!err) | |
b4bd2929 MC |
2442 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
2443 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); | |
1da177e4 LT |
2444 | } |
2445 | ||
2446 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2447 | * jumbo frames transmission. | |
2448 | */ | |
63c3a66f | 2449 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
f833c4c1 | 2450 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2451 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2452 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2453 | } |
2454 | ||
715116a1 | 2455 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2456 | /* adjust output voltage */ |
535ef6e1 | 2457 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2458 | } |
2459 | ||
9ef8ca99 | 2460 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2461 | tg3_phy_set_wirespeed(tp); |
2462 | return 0; | |
2463 | } | |
2464 | ||
3a1e19d3 MC |
2465 | #define TG3_GPIO_MSG_DRVR_PRES 0x00000001 |
2466 | #define TG3_GPIO_MSG_NEED_VAUX 0x00000002 | |
2467 | #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \ | |
2468 | TG3_GPIO_MSG_NEED_VAUX) | |
2469 | #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \ | |
2470 | ((TG3_GPIO_MSG_DRVR_PRES << 0) | \ | |
2471 | (TG3_GPIO_MSG_DRVR_PRES << 4) | \ | |
2472 | (TG3_GPIO_MSG_DRVR_PRES << 8) | \ | |
2473 | (TG3_GPIO_MSG_DRVR_PRES << 12)) | |
2474 | ||
2475 | #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \ | |
2476 | ((TG3_GPIO_MSG_NEED_VAUX << 0) | \ | |
2477 | (TG3_GPIO_MSG_NEED_VAUX << 4) | \ | |
2478 | (TG3_GPIO_MSG_NEED_VAUX << 8) | \ | |
2479 | (TG3_GPIO_MSG_NEED_VAUX << 12)) | |
2480 | ||
2481 | static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) | |
2482 | { | |
2483 | u32 status, shift; | |
2484 | ||
2485 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2486 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2487 | status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); | |
2488 | else | |
2489 | status = tr32(TG3_CPMU_DRV_STATUS); | |
2490 | ||
2491 | shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; | |
2492 | status &= ~(TG3_GPIO_MSG_MASK << shift); | |
2493 | status |= (newstat << shift); | |
2494 | ||
2495 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2496 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2497 | tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); | |
2498 | else | |
2499 | tw32(TG3_CPMU_DRV_STATUS, status); | |
2500 | ||
2501 | return status >> TG3_APE_GPIO_MSG_SHIFT; | |
2502 | } | |
2503 | ||
520b2756 MC |
2504 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) |
2505 | { | |
2506 | if (!tg3_flag(tp, IS_NIC)) | |
2507 | return 0; | |
2508 | ||
3a1e19d3 MC |
2509 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2510 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2511 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
2512 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2513 | return -EIO; | |
520b2756 | 2514 | |
3a1e19d3 MC |
2515 | tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); |
2516 | ||
2517 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2518 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2519 | ||
2520 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); | |
2521 | } else { | |
2522 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2523 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2524 | } | |
6f5c8f83 | 2525 | |
520b2756 MC |
2526 | return 0; |
2527 | } | |
2528 | ||
2529 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) | |
2530 | { | |
2531 | u32 grc_local_ctrl; | |
2532 | ||
2533 | if (!tg3_flag(tp, IS_NIC) || | |
2534 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2535 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) | |
2536 | return; | |
2537 | ||
2538 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; | |
2539 | ||
2540 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2541 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2542 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2543 | ||
2544 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2545 | grc_local_ctrl, | |
2546 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2547 | ||
2548 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2549 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2550 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2551 | } | |
2552 | ||
2553 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) | |
2554 | { | |
2555 | if (!tg3_flag(tp, IS_NIC)) | |
2556 | return; | |
2557 | ||
2558 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2559 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2560 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2561 | (GRC_LCLCTRL_GPIO_OE0 | | |
2562 | GRC_LCLCTRL_GPIO_OE1 | | |
2563 | GRC_LCLCTRL_GPIO_OE2 | | |
2564 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2565 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2566 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2567 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
2568 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
2569 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
2570 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2571 | GRC_LCLCTRL_GPIO_OE1 | | |
2572 | GRC_LCLCTRL_GPIO_OE2 | | |
2573 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2574 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2575 | tp->grc_local_ctrl; | |
2576 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2577 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2578 | ||
2579 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2580 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2581 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2582 | ||
2583 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2584 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2585 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2586 | } else { | |
2587 | u32 no_gpio2; | |
2588 | u32 grc_local_ctrl = 0; | |
2589 | ||
2590 | /* Workaround to prevent overdrawing Amps. */ | |
2591 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
2592 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
2593 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2594 | grc_local_ctrl, | |
2595 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2596 | } | |
2597 | ||
2598 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
2599 | no_gpio2 = tp->nic_sram_data_cfg & | |
2600 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2601 | ||
2602 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
2603 | GRC_LCLCTRL_GPIO_OE1 | | |
2604 | GRC_LCLCTRL_GPIO_OE2 | | |
2605 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2606 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2607 | if (no_gpio2) { | |
2608 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2609 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2610 | } | |
2611 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2612 | tp->grc_local_ctrl | grc_local_ctrl, | |
2613 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2614 | ||
2615 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2616 | ||
2617 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2618 | tp->grc_local_ctrl | grc_local_ctrl, | |
2619 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2620 | ||
2621 | if (!no_gpio2) { | |
2622 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2623 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2624 | tp->grc_local_ctrl | grc_local_ctrl, | |
2625 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2626 | } | |
2627 | } | |
3a1e19d3 MC |
2628 | } |
2629 | ||
cd0d7228 | 2630 | static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) |
3a1e19d3 MC |
2631 | { |
2632 | u32 msg = 0; | |
2633 | ||
2634 | /* Serialize power state transitions */ | |
2635 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2636 | return; | |
2637 | ||
cd0d7228 | 2638 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) |
3a1e19d3 MC |
2639 | msg = TG3_GPIO_MSG_NEED_VAUX; |
2640 | ||
2641 | msg = tg3_set_function_status(tp, msg); | |
2642 | ||
2643 | if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK) | |
2644 | goto done; | |
6f5c8f83 | 2645 | |
3a1e19d3 MC |
2646 | if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK) |
2647 | tg3_pwrsrc_switch_to_vaux(tp); | |
2648 | else | |
2649 | tg3_pwrsrc_die_with_vmain(tp); | |
2650 | ||
2651 | done: | |
6f5c8f83 | 2652 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); |
520b2756 MC |
2653 | } |
2654 | ||
cd0d7228 | 2655 | static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) |
1da177e4 | 2656 | { |
683644b7 | 2657 | bool need_vaux = false; |
1da177e4 | 2658 | |
334355aa | 2659 | /* The GPIOs do something completely different on 57765. */ |
55086ad9 | 2660 | if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) |
1da177e4 LT |
2661 | return; |
2662 | ||
3a1e19d3 MC |
2663 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2664 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2665 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
cd0d7228 MC |
2666 | tg3_frob_aux_power_5717(tp, include_wol ? |
2667 | tg3_flag(tp, WOL_ENABLE) != 0 : 0); | |
3a1e19d3 MC |
2668 | return; |
2669 | } | |
2670 | ||
2671 | if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { | |
8c2dc7e1 MC |
2672 | struct net_device *dev_peer; |
2673 | ||
2674 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2675 | |
bc1c7567 | 2676 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2677 | if (dev_peer) { |
2678 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2679 | ||
63c3a66f | 2680 | if (tg3_flag(tp_peer, INIT_COMPLETE)) |
683644b7 MC |
2681 | return; |
2682 | ||
cd0d7228 | 2683 | if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) || |
63c3a66f | 2684 | tg3_flag(tp_peer, ENABLE_ASF)) |
683644b7 MC |
2685 | need_vaux = true; |
2686 | } | |
1da177e4 LT |
2687 | } |
2688 | ||
cd0d7228 MC |
2689 | if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || |
2690 | tg3_flag(tp, ENABLE_ASF)) | |
683644b7 MC |
2691 | need_vaux = true; |
2692 | ||
520b2756 MC |
2693 | if (need_vaux) |
2694 | tg3_pwrsrc_switch_to_vaux(tp); | |
2695 | else | |
2696 | tg3_pwrsrc_die_with_vmain(tp); | |
1da177e4 LT |
2697 | } |
2698 | ||
e8f3f6ca MC |
2699 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2700 | { | |
2701 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2702 | return 1; | |
79eb6904 | 2703 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2704 | if (speed != SPEED_10) |
2705 | return 1; | |
2706 | } else if (speed == SPEED_10) | |
2707 | return 1; | |
2708 | ||
2709 | return 0; | |
2710 | } | |
2711 | ||
1da177e4 | 2712 | static int tg3_setup_phy(struct tg3 *, int); |
1da177e4 LT |
2713 | static int tg3_halt_cpu(struct tg3 *, u32); |
2714 | ||
0a459aac | 2715 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2716 | { |
ce057f01 MC |
2717 | u32 val; |
2718 | ||
f07e9af3 | 2719 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2720 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2721 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2722 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2723 | ||
2724 | sg_dig_ctrl |= | |
2725 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2726 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2727 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2728 | } | |
3f7045c1 | 2729 | return; |
5129724a | 2730 | } |
3f7045c1 | 2731 | |
60189ddf | 2732 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2733 | tg3_bmcr_reset(tp); |
2734 | val = tr32(GRC_MISC_CFG); | |
2735 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2736 | udelay(40); | |
2737 | return; | |
f07e9af3 | 2738 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2739 | u32 phytest; |
2740 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2741 | u32 phy; | |
2742 | ||
2743 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2744 | tg3_writephy(tp, MII_BMCR, | |
2745 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2746 | ||
2747 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2748 | phytest | MII_TG3_FET_SHADOW_EN); | |
2749 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2750 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2751 | tg3_writephy(tp, | |
2752 | MII_TG3_FET_SHDW_AUXMODE4, | |
2753 | phy); | |
2754 | } | |
2755 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2756 | } | |
2757 | return; | |
0a459aac | 2758 | } else if (do_low_power) { |
715116a1 MC |
2759 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2760 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac | 2761 | |
b4bd2929 MC |
2762 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
2763 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2764 | MII_TG3_AUXCTL_PCTL_VREG_11V; | |
2765 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); | |
715116a1 | 2766 | } |
3f7045c1 | 2767 | |
15c3b696 MC |
2768 | /* The PHY should not be powered down on some chips because |
2769 | * of bugs. | |
2770 | */ | |
2771 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2772 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2773 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
f07e9af3 | 2774 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
15c3b696 | 2775 | return; |
ce057f01 | 2776 | |
bcb37f6c MC |
2777 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2778 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2779 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2780 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2781 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2782 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2783 | } | |
2784 | ||
15c3b696 MC |
2785 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2786 | } | |
2787 | ||
ffbcfed4 MC |
2788 | /* tp->lock is held. */ |
2789 | static int tg3_nvram_lock(struct tg3 *tp) | |
2790 | { | |
63c3a66f | 2791 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2792 | int i; |
2793 | ||
2794 | if (tp->nvram_lock_cnt == 0) { | |
2795 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2796 | for (i = 0; i < 8000; i++) { | |
2797 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2798 | break; | |
2799 | udelay(20); | |
2800 | } | |
2801 | if (i == 8000) { | |
2802 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2803 | return -ENODEV; | |
2804 | } | |
2805 | } | |
2806 | tp->nvram_lock_cnt++; | |
2807 | } | |
2808 | return 0; | |
2809 | } | |
2810 | ||
2811 | /* tp->lock is held. */ | |
2812 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2813 | { | |
63c3a66f | 2814 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2815 | if (tp->nvram_lock_cnt > 0) |
2816 | tp->nvram_lock_cnt--; | |
2817 | if (tp->nvram_lock_cnt == 0) | |
2818 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2819 | } | |
2820 | } | |
2821 | ||
2822 | /* tp->lock is held. */ | |
2823 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2824 | { | |
63c3a66f | 2825 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2826 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2827 | ||
2828 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2829 | } | |
2830 | } | |
2831 | ||
2832 | /* tp->lock is held. */ | |
2833 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2834 | { | |
63c3a66f | 2835 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2836 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2837 | ||
2838 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2839 | } | |
2840 | } | |
2841 | ||
2842 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2843 | u32 offset, u32 *val) | |
2844 | { | |
2845 | u32 tmp; | |
2846 | int i; | |
2847 | ||
2848 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2849 | return -EINVAL; | |
2850 | ||
2851 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2852 | EEPROM_ADDR_DEVID_MASK | | |
2853 | EEPROM_ADDR_READ); | |
2854 | tw32(GRC_EEPROM_ADDR, | |
2855 | tmp | | |
2856 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2857 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2858 | EEPROM_ADDR_ADDR_MASK) | | |
2859 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2860 | ||
2861 | for (i = 0; i < 1000; i++) { | |
2862 | tmp = tr32(GRC_EEPROM_ADDR); | |
2863 | ||
2864 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2865 | break; | |
2866 | msleep(1); | |
2867 | } | |
2868 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2869 | return -EBUSY; | |
2870 | ||
62cedd11 MC |
2871 | tmp = tr32(GRC_EEPROM_DATA); |
2872 | ||
2873 | /* | |
2874 | * The data will always be opposite the native endian | |
2875 | * format. Perform a blind byteswap to compensate. | |
2876 | */ | |
2877 | *val = swab32(tmp); | |
2878 | ||
ffbcfed4 MC |
2879 | return 0; |
2880 | } | |
2881 | ||
2882 | #define NVRAM_CMD_TIMEOUT 10000 | |
2883 | ||
2884 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2885 | { | |
2886 | int i; | |
2887 | ||
2888 | tw32(NVRAM_CMD, nvram_cmd); | |
2889 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2890 | udelay(10); | |
2891 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2892 | udelay(10); | |
2893 | break; | |
2894 | } | |
2895 | } | |
2896 | ||
2897 | if (i == NVRAM_CMD_TIMEOUT) | |
2898 | return -EBUSY; | |
2899 | ||
2900 | return 0; | |
2901 | } | |
2902 | ||
2903 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2904 | { | |
63c3a66f JP |
2905 | if (tg3_flag(tp, NVRAM) && |
2906 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2907 | tg3_flag(tp, FLASH) && | |
2908 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2909 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2910 | ||
2911 | addr = ((addr / tp->nvram_pagesize) << | |
2912 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2913 | (addr % tp->nvram_pagesize); | |
2914 | ||
2915 | return addr; | |
2916 | } | |
2917 | ||
2918 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2919 | { | |
63c3a66f JP |
2920 | if (tg3_flag(tp, NVRAM) && |
2921 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2922 | tg3_flag(tp, FLASH) && | |
2923 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
2924 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
2925 | ||
2926 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2927 | tp->nvram_pagesize) + | |
2928 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2929 | ||
2930 | return addr; | |
2931 | } | |
2932 | ||
e4f34110 MC |
2933 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2934 | * the byteswapping settings for all other register accesses. | |
2935 | * tg3 devices are BE devices, so on a BE machine, the data | |
2936 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2937 | * machine, the 32-bit value will be byteswapped. | |
2938 | */ | |
ffbcfed4 MC |
2939 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2940 | { | |
2941 | int ret; | |
2942 | ||
63c3a66f | 2943 | if (!tg3_flag(tp, NVRAM)) |
ffbcfed4 MC |
2944 | return tg3_nvram_read_using_eeprom(tp, offset, val); |
2945 | ||
2946 | offset = tg3_nvram_phys_addr(tp, offset); | |
2947 | ||
2948 | if (offset > NVRAM_ADDR_MSK) | |
2949 | return -EINVAL; | |
2950 | ||
2951 | ret = tg3_nvram_lock(tp); | |
2952 | if (ret) | |
2953 | return ret; | |
2954 | ||
2955 | tg3_enable_nvram_access(tp); | |
2956 | ||
2957 | tw32(NVRAM_ADDR, offset); | |
2958 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2959 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2960 | ||
2961 | if (ret == 0) | |
e4f34110 | 2962 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2963 | |
2964 | tg3_disable_nvram_access(tp); | |
2965 | ||
2966 | tg3_nvram_unlock(tp); | |
2967 | ||
2968 | return ret; | |
2969 | } | |
2970 | ||
a9dc529d MC |
2971 | /* Ensures NVRAM data is in bytestream format. */ |
2972 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2973 | { |
2974 | u32 v; | |
a9dc529d | 2975 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2976 | if (!res) |
a9dc529d | 2977 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2978 | return res; |
2979 | } | |
2980 | ||
997b4f13 MC |
2981 | #define RX_CPU_SCRATCH_BASE 0x30000 |
2982 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
2983 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
2984 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
2985 | ||
2986 | /* tp->lock is held. */ | |
2987 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
2988 | { | |
2989 | int i; | |
2990 | ||
2991 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); | |
2992 | ||
2993 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2994 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
2995 | ||
2996 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
2997 | return 0; | |
2998 | } | |
2999 | if (offset == RX_CPU_BASE) { | |
3000 | for (i = 0; i < 10000; i++) { | |
3001 | tw32(offset + CPU_STATE, 0xffffffff); | |
3002 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
3003 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
3004 | break; | |
3005 | } | |
3006 | ||
3007 | tw32(offset + CPU_STATE, 0xffffffff); | |
3008 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
3009 | udelay(10); | |
3010 | } else { | |
3011 | for (i = 0; i < 10000; i++) { | |
3012 | tw32(offset + CPU_STATE, 0xffffffff); | |
3013 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
3014 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
3015 | break; | |
3016 | } | |
3017 | } | |
3018 | ||
3019 | if (i >= 10000) { | |
3020 | netdev_err(tp->dev, "%s timed out, %s CPU\n", | |
3021 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
3022 | return -ENODEV; | |
3023 | } | |
3024 | ||
3025 | /* Clear firmware's nvram arbitration. */ | |
3026 | if (tg3_flag(tp, NVRAM)) | |
3027 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
3028 | return 0; | |
3029 | } | |
3030 | ||
3031 | struct fw_info { | |
3032 | unsigned int fw_base; | |
3033 | unsigned int fw_len; | |
3034 | const __be32 *fw_data; | |
3035 | }; | |
3036 | ||
3037 | /* tp->lock is held. */ | |
3038 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, | |
3039 | u32 cpu_scratch_base, int cpu_scratch_size, | |
3040 | struct fw_info *info) | |
3041 | { | |
3042 | int err, lock_err, i; | |
3043 | void (*write_op)(struct tg3 *, u32, u32); | |
3044 | ||
3045 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { | |
3046 | netdev_err(tp->dev, | |
3047 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
3048 | __func__); | |
3049 | return -EINVAL; | |
3050 | } | |
3051 | ||
3052 | if (tg3_flag(tp, 5705_PLUS)) | |
3053 | write_op = tg3_write_mem; | |
3054 | else | |
3055 | write_op = tg3_write_indirect_reg32; | |
3056 | ||
3057 | /* It is possible that bootcode is still loading at this point. | |
3058 | * Get the nvram lock first before halting the cpu. | |
3059 | */ | |
3060 | lock_err = tg3_nvram_lock(tp); | |
3061 | err = tg3_halt_cpu(tp, cpu_base); | |
3062 | if (!lock_err) | |
3063 | tg3_nvram_unlock(tp); | |
3064 | if (err) | |
3065 | goto out; | |
3066 | ||
3067 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
3068 | write_op(tp, cpu_scratch_base + i, 0); | |
3069 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3070 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
3071 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) | |
3072 | write_op(tp, (cpu_scratch_base + | |
3073 | (info->fw_base & 0xffff) + | |
3074 | (i * sizeof(u32))), | |
3075 | be32_to_cpu(info->fw_data[i])); | |
3076 | ||
3077 | err = 0; | |
3078 | ||
3079 | out: | |
3080 | return err; | |
3081 | } | |
3082 | ||
3083 | /* tp->lock is held. */ | |
3084 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
3085 | { | |
3086 | struct fw_info info; | |
3087 | const __be32 *fw_data; | |
3088 | int err, i; | |
3089 | ||
3090 | fw_data = (void *)tp->fw->data; | |
3091 | ||
3092 | /* Firmware blob starts with version numbers, followed by | |
3093 | start address and length. We are setting complete length. | |
3094 | length = end_address_of_bss - start_address_of_text. | |
3095 | Remainder is the blob to be loaded contiguously | |
3096 | from start address. */ | |
3097 | ||
3098 | info.fw_base = be32_to_cpu(fw_data[1]); | |
3099 | info.fw_len = tp->fw->size - 12; | |
3100 | info.fw_data = &fw_data[3]; | |
3101 | ||
3102 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
3103 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
3104 | &info); | |
3105 | if (err) | |
3106 | return err; | |
3107 | ||
3108 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
3109 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
3110 | &info); | |
3111 | if (err) | |
3112 | return err; | |
3113 | ||
3114 | /* Now startup only the RX cpu. */ | |
3115 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3116 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
3117 | ||
3118 | for (i = 0; i < 5; i++) { | |
3119 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) | |
3120 | break; | |
3121 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3122 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
3123 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
3124 | udelay(1000); | |
3125 | } | |
3126 | if (i >= 5) { | |
3127 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " | |
3128 | "should be %08x\n", __func__, | |
3129 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); | |
3130 | return -ENODEV; | |
3131 | } | |
3132 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3133 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
3134 | ||
3135 | return 0; | |
3136 | } | |
3137 | ||
3138 | /* tp->lock is held. */ | |
3139 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
3140 | { | |
3141 | struct fw_info info; | |
3142 | const __be32 *fw_data; | |
3143 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; | |
3144 | int err, i; | |
3145 | ||
3146 | if (tg3_flag(tp, HW_TSO_1) || | |
3147 | tg3_flag(tp, HW_TSO_2) || | |
3148 | tg3_flag(tp, HW_TSO_3)) | |
3149 | return 0; | |
3150 | ||
3151 | fw_data = (void *)tp->fw->data; | |
3152 | ||
3153 | /* Firmware blob starts with version numbers, followed by | |
3154 | start address and length. We are setting complete length. | |
3155 | length = end_address_of_bss - start_address_of_text. | |
3156 | Remainder is the blob to be loaded contiguously | |
3157 | from start address. */ | |
3158 | ||
3159 | info.fw_base = be32_to_cpu(fw_data[1]); | |
3160 | cpu_scratch_size = tp->fw_len; | |
3161 | info.fw_len = tp->fw->size - 12; | |
3162 | info.fw_data = &fw_data[3]; | |
3163 | ||
3164 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
3165 | cpu_base = RX_CPU_BASE; | |
3166 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
3167 | } else { | |
3168 | cpu_base = TX_CPU_BASE; | |
3169 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
3170 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
3171 | } | |
3172 | ||
3173 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
3174 | cpu_scratch_base, cpu_scratch_size, | |
3175 | &info); | |
3176 | if (err) | |
3177 | return err; | |
3178 | ||
3179 | /* Now startup the cpu. */ | |
3180 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3181 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
3182 | ||
3183 | for (i = 0; i < 5; i++) { | |
3184 | if (tr32(cpu_base + CPU_PC) == info.fw_base) | |
3185 | break; | |
3186 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3187 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
3188 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
3189 | udelay(1000); | |
3190 | } | |
3191 | if (i >= 5) { | |
3192 | netdev_err(tp->dev, | |
3193 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
3194 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); | |
3195 | return -ENODEV; | |
3196 | } | |
3197 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3198 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
3199 | return 0; | |
3200 | } | |
3201 | ||
3202 | ||
3f007891 MC |
3203 | /* tp->lock is held. */ |
3204 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
3205 | { | |
3206 | u32 addr_high, addr_low; | |
3207 | int i; | |
3208 | ||
3209 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
3210 | tp->dev->dev_addr[1]); | |
3211 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
3212 | (tp->dev->dev_addr[3] << 16) | | |
3213 | (tp->dev->dev_addr[4] << 8) | | |
3214 | (tp->dev->dev_addr[5] << 0)); | |
3215 | for (i = 0; i < 4; i++) { | |
3216 | if (i == 1 && skip_mac_1) | |
3217 | continue; | |
3218 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
3219 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
3220 | } | |
3221 | ||
3222 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3223 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
3224 | for (i = 0; i < 12; i++) { | |
3225 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
3226 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
3227 | } | |
3228 | } | |
3229 | ||
3230 | addr_high = (tp->dev->dev_addr[0] + | |
3231 | tp->dev->dev_addr[1] + | |
3232 | tp->dev->dev_addr[2] + | |
3233 | tp->dev->dev_addr[3] + | |
3234 | tp->dev->dev_addr[4] + | |
3235 | tp->dev->dev_addr[5]) & | |
3236 | TX_BACKOFF_SEED_MASK; | |
3237 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
3238 | } | |
3239 | ||
c866b7ea | 3240 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 3241 | { |
c866b7ea RW |
3242 | /* |
3243 | * Make sure register accesses (indirect or otherwise) will function | |
3244 | * correctly. | |
1da177e4 LT |
3245 | */ |
3246 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
3247 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
3248 | } | |
1da177e4 | 3249 | |
c866b7ea RW |
3250 | static int tg3_power_up(struct tg3 *tp) |
3251 | { | |
bed9829f | 3252 | int err; |
8c6bda1a | 3253 | |
bed9829f | 3254 | tg3_enable_register_access(tp); |
1da177e4 | 3255 | |
bed9829f MC |
3256 | err = pci_set_power_state(tp->pdev, PCI_D0); |
3257 | if (!err) { | |
3258 | /* Switch out of Vaux if it is a NIC */ | |
3259 | tg3_pwrsrc_switch_to_vmain(tp); | |
3260 | } else { | |
3261 | netdev_err(tp->dev, "Transition to D0 failed\n"); | |
3262 | } | |
1da177e4 | 3263 | |
bed9829f | 3264 | return err; |
c866b7ea | 3265 | } |
1da177e4 | 3266 | |
c866b7ea RW |
3267 | static int tg3_power_down_prepare(struct tg3 *tp) |
3268 | { | |
3269 | u32 misc_host_ctrl; | |
3270 | bool device_should_wake, do_low_power; | |
3271 | ||
3272 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
3273 | |
3274 | /* Restore the CLKREQ setting. */ | |
63c3a66f | 3275 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
3276 | u16 lnkctl; |
3277 | ||
3278 | pci_read_config_word(tp->pdev, | |
708ebb3a | 3279 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3280 | &lnkctl); |
3281 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
3282 | pci_write_config_word(tp->pdev, | |
708ebb3a | 3283 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
3284 | lnkctl); |
3285 | } | |
3286 | ||
1da177e4 LT |
3287 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
3288 | tw32(TG3PCI_MISC_HOST_CTRL, | |
3289 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
3290 | ||
c866b7ea | 3291 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 3292 | tg3_flag(tp, WOL_ENABLE); |
05ac4cb7 | 3293 | |
63c3a66f | 3294 | if (tg3_flag(tp, USE_PHYLIB)) { |
0a459aac | 3295 | do_low_power = false; |
f07e9af3 | 3296 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 3297 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 3298 | struct phy_device *phydev; |
0a459aac | 3299 | u32 phyid, advertising; |
b02fd9e3 | 3300 | |
3f0e3ad7 | 3301 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 3302 | |
80096068 | 3303 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 MC |
3304 | |
3305 | tp->link_config.orig_speed = phydev->speed; | |
3306 | tp->link_config.orig_duplex = phydev->duplex; | |
3307 | tp->link_config.orig_autoneg = phydev->autoneg; | |
3308 | tp->link_config.orig_advertising = phydev->advertising; | |
3309 | ||
3310 | advertising = ADVERTISED_TP | | |
3311 | ADVERTISED_Pause | | |
3312 | ADVERTISED_Autoneg | | |
3313 | ADVERTISED_10baseT_Half; | |
3314 | ||
63c3a66f JP |
3315 | if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { |
3316 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
b02fd9e3 MC |
3317 | advertising |= |
3318 | ADVERTISED_100baseT_Half | | |
3319 | ADVERTISED_100baseT_Full | | |
3320 | ADVERTISED_10baseT_Full; | |
3321 | else | |
3322 | advertising |= ADVERTISED_10baseT_Full; | |
3323 | } | |
3324 | ||
3325 | phydev->advertising = advertising; | |
3326 | ||
3327 | phy_start_aneg(phydev); | |
0a459aac MC |
3328 | |
3329 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
3330 | if (phyid != PHY_ID_BCMAC131) { |
3331 | phyid &= PHY_BCM_OUI_MASK; | |
3332 | if (phyid == PHY_BCM_OUI_1 || | |
3333 | phyid == PHY_BCM_OUI_2 || | |
3334 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
3335 | do_low_power = true; |
3336 | } | |
b02fd9e3 | 3337 | } |
dd477003 | 3338 | } else { |
2023276e | 3339 | do_low_power = true; |
0a459aac | 3340 | |
80096068 MC |
3341 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
3342 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
3343 | tp->link_config.orig_speed = tp->link_config.speed; |
3344 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
3345 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
3346 | } | |
1da177e4 | 3347 | |
f07e9af3 | 3348 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
dd477003 MC |
3349 | tp->link_config.speed = SPEED_10; |
3350 | tp->link_config.duplex = DUPLEX_HALF; | |
3351 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
3352 | tg3_setup_phy(tp, 0); | |
3353 | } | |
1da177e4 LT |
3354 | } |
3355 | ||
b5d3772c MC |
3356 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
3357 | u32 val; | |
3358 | ||
3359 | val = tr32(GRC_VCPU_EXT_CTRL); | |
3360 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
63c3a66f | 3361 | } else if (!tg3_flag(tp, ENABLE_ASF)) { |
6921d201 MC |
3362 | int i; |
3363 | u32 val; | |
3364 | ||
3365 | for (i = 0; i < 200; i++) { | |
3366 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
3367 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
3368 | break; | |
3369 | msleep(1); | |
3370 | } | |
3371 | } | |
63c3a66f | 3372 | if (tg3_flag(tp, WOL_CAP)) |
a85feb8c GZ |
3373 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | |
3374 | WOL_DRV_STATE_SHUTDOWN | | |
3375 | WOL_DRV_WOL | | |
3376 | WOL_SET_MAGIC_PKT); | |
6921d201 | 3377 | |
05ac4cb7 | 3378 | if (device_should_wake) { |
1da177e4 LT |
3379 | u32 mac_mode; |
3380 | ||
f07e9af3 | 3381 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
b4bd2929 MC |
3382 | if (do_low_power && |
3383 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
3384 | tg3_phy_auxctl_write(tp, | |
3385 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, | |
3386 | MII_TG3_AUXCTL_PCTL_WOL_EN | | |
3387 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
3388 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); | |
dd477003 MC |
3389 | udelay(40); |
3390 | } | |
1da177e4 | 3391 | |
f07e9af3 | 3392 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
3393 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
3394 | else | |
3395 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 3396 | |
e8f3f6ca MC |
3397 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
3398 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
3399 | ASIC_REV_5700) { | |
63c3a66f | 3400 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? |
e8f3f6ca MC |
3401 | SPEED_100 : SPEED_10; |
3402 | if (tg3_5700_link_polarity(tp, speed)) | |
3403 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
3404 | else | |
3405 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
3406 | } | |
1da177e4 LT |
3407 | } else { |
3408 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
3409 | } | |
3410 | ||
63c3a66f | 3411 | if (!tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
3412 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
3413 | ||
05ac4cb7 | 3414 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
63c3a66f JP |
3415 | if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && |
3416 | (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) | |
05ac4cb7 | 3417 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; |
1da177e4 | 3418 | |
63c3a66f | 3419 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b MC |
3420 | mac_mode |= MAC_MODE_APE_TX_EN | |
3421 | MAC_MODE_APE_RX_EN | | |
3422 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 3423 | |
1da177e4 LT |
3424 | tw32_f(MAC_MODE, mac_mode); |
3425 | udelay(100); | |
3426 | ||
3427 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
3428 | udelay(10); | |
3429 | } | |
3430 | ||
63c3a66f | 3431 | if (!tg3_flag(tp, WOL_SPEED_100MB) && |
1da177e4 LT |
3432 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
3433 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
3434 | u32 base_val; | |
3435 | ||
3436 | base_val = tp->pci_clock_ctrl; | |
3437 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
3438 | CLOCK_CTRL_TXCLK_DISABLE); | |
3439 | ||
b401e9e2 MC |
3440 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
3441 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
63c3a66f JP |
3442 | } else if (tg3_flag(tp, 5780_CLASS) || |
3443 | tg3_flag(tp, CPMU_PRESENT) || | |
6ff6f81d | 3444 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
4cf78e4f | 3445 | /* do nothing */ |
63c3a66f | 3446 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { |
1da177e4 LT |
3447 | u32 newbits1, newbits2; |
3448 | ||
3449 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3450 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3451 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
3452 | CLOCK_CTRL_TXCLK_DISABLE | | |
3453 | CLOCK_CTRL_ALTCLK); | |
3454 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
63c3a66f | 3455 | } else if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
3456 | newbits1 = CLOCK_CTRL_625_CORE; |
3457 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
3458 | } else { | |
3459 | newbits1 = CLOCK_CTRL_ALTCLK; | |
3460 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
3461 | } | |
3462 | ||
b401e9e2 MC |
3463 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
3464 | 40); | |
1da177e4 | 3465 | |
b401e9e2 MC |
3466 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
3467 | 40); | |
1da177e4 | 3468 | |
63c3a66f | 3469 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
3470 | u32 newbits3; |
3471 | ||
3472 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3473 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3474 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
3475 | CLOCK_CTRL_TXCLK_DISABLE | | |
3476 | CLOCK_CTRL_44MHZ_CORE); | |
3477 | } else { | |
3478 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
3479 | } | |
3480 | ||
b401e9e2 MC |
3481 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
3482 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
3483 | } |
3484 | } | |
3485 | ||
63c3a66f | 3486 | if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) |
0a459aac | 3487 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 3488 | |
cd0d7228 | 3489 | tg3_frob_aux_power(tp, true); |
1da177e4 LT |
3490 | |
3491 | /* Workaround for unstable PLL clock */ | |
3492 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
3493 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
3494 | u32 val = tr32(0x7d00); | |
3495 | ||
3496 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
3497 | tw32(0x7d00, val); | |
63c3a66f | 3498 | if (!tg3_flag(tp, ENABLE_ASF)) { |
ec41c7df MC |
3499 | int err; |
3500 | ||
3501 | err = tg3_nvram_lock(tp); | |
1da177e4 | 3502 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
3503 | if (!err) |
3504 | tg3_nvram_unlock(tp); | |
6921d201 | 3505 | } |
1da177e4 LT |
3506 | } |
3507 | ||
bbadf503 MC |
3508 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
3509 | ||
c866b7ea RW |
3510 | return 0; |
3511 | } | |
12dac075 | 3512 | |
c866b7ea RW |
3513 | static void tg3_power_down(struct tg3 *tp) |
3514 | { | |
3515 | tg3_power_down_prepare(tp); | |
1da177e4 | 3516 | |
63c3a66f | 3517 | pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); |
c866b7ea | 3518 | pci_set_power_state(tp->pdev, PCI_D3hot); |
1da177e4 LT |
3519 | } |
3520 | ||
1da177e4 LT |
3521 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
3522 | { | |
3523 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
3524 | case MII_TG3_AUX_STAT_10HALF: | |
3525 | *speed = SPEED_10; | |
3526 | *duplex = DUPLEX_HALF; | |
3527 | break; | |
3528 | ||
3529 | case MII_TG3_AUX_STAT_10FULL: | |
3530 | *speed = SPEED_10; | |
3531 | *duplex = DUPLEX_FULL; | |
3532 | break; | |
3533 | ||
3534 | case MII_TG3_AUX_STAT_100HALF: | |
3535 | *speed = SPEED_100; | |
3536 | *duplex = DUPLEX_HALF; | |
3537 | break; | |
3538 | ||
3539 | case MII_TG3_AUX_STAT_100FULL: | |
3540 | *speed = SPEED_100; | |
3541 | *duplex = DUPLEX_FULL; | |
3542 | break; | |
3543 | ||
3544 | case MII_TG3_AUX_STAT_1000HALF: | |
3545 | *speed = SPEED_1000; | |
3546 | *duplex = DUPLEX_HALF; | |
3547 | break; | |
3548 | ||
3549 | case MII_TG3_AUX_STAT_1000FULL: | |
3550 | *speed = SPEED_1000; | |
3551 | *duplex = DUPLEX_FULL; | |
3552 | break; | |
3553 | ||
3554 | default: | |
f07e9af3 | 3555 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
3556 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
3557 | SPEED_10; | |
3558 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
3559 | DUPLEX_HALF; | |
3560 | break; | |
3561 | } | |
1da177e4 LT |
3562 | *speed = SPEED_INVALID; |
3563 | *duplex = DUPLEX_INVALID; | |
3564 | break; | |
855e1111 | 3565 | } |
1da177e4 LT |
3566 | } |
3567 | ||
42b64a45 | 3568 | static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) |
1da177e4 | 3569 | { |
42b64a45 MC |
3570 | int err = 0; |
3571 | u32 val, new_adv; | |
1da177e4 | 3572 | |
42b64a45 | 3573 | new_adv = ADVERTISE_CSMA; |
202ff1c2 | 3574 | new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL; |
f88788f0 | 3575 | new_adv |= mii_advertise_flowctrl(flowctrl); |
1da177e4 | 3576 | |
42b64a45 MC |
3577 | err = tg3_writephy(tp, MII_ADVERTISE, new_adv); |
3578 | if (err) | |
3579 | goto done; | |
ba4d07a8 | 3580 | |
4f272096 MC |
3581 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
3582 | new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise); | |
ba4d07a8 | 3583 | |
4f272096 MC |
3584 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
3585 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
3586 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; | |
ba4d07a8 | 3587 | |
4f272096 MC |
3588 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
3589 | if (err) | |
3590 | goto done; | |
3591 | } | |
1da177e4 | 3592 | |
42b64a45 MC |
3593 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) |
3594 | goto done; | |
52b02d04 | 3595 | |
42b64a45 MC |
3596 | tw32(TG3_CPMU_EEE_MODE, |
3597 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
52b02d04 | 3598 | |
42b64a45 MC |
3599 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
3600 | if (!err) { | |
3601 | u32 err2; | |
52b02d04 | 3602 | |
b715ce94 MC |
3603 | val = 0; |
3604 | /* Advertise 100-BaseTX EEE ability */ | |
3605 | if (advertise & ADVERTISED_100baseT_Full) | |
3606 | val |= MDIO_AN_EEE_ADV_100TX; | |
3607 | /* Advertise 1000-BaseT EEE ability */ | |
3608 | if (advertise & ADVERTISED_1000baseT_Full) | |
3609 | val |= MDIO_AN_EEE_ADV_1000T; | |
3610 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3611 | if (err) | |
3612 | val = 0; | |
3613 | ||
21a00ab2 MC |
3614 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
3615 | case ASIC_REV_5717: | |
3616 | case ASIC_REV_57765: | |
55086ad9 | 3617 | case ASIC_REV_57766: |
21a00ab2 | 3618 | case ASIC_REV_5719: |
b715ce94 MC |
3619 | /* If we advertised any eee advertisements above... */ |
3620 | if (val) | |
3621 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
3622 | MII_TG3_DSP_TAP26_RMRXSTO | | |
3623 | MII_TG3_DSP_TAP26_OPCSINPT; | |
21a00ab2 | 3624 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); |
be671947 MC |
3625 | /* Fall through */ |
3626 | case ASIC_REV_5720: | |
3627 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
3628 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
3629 | MII_TG3_DSP_CH34TP2_HIBW01); | |
21a00ab2 | 3630 | } |
52b02d04 | 3631 | |
42b64a45 MC |
3632 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
3633 | if (!err) | |
3634 | err = err2; | |
3635 | } | |
3636 | ||
3637 | done: | |
3638 | return err; | |
3639 | } | |
3640 | ||
3641 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
3642 | { | |
3643 | u32 new_adv; | |
3644 | int i; | |
3645 | ||
3646 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
3647 | new_adv = ADVERTISED_10baseT_Half | | |
3648 | ADVERTISED_10baseT_Full; | |
3649 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
3650 | new_adv |= ADVERTISED_100baseT_Half | | |
3651 | ADVERTISED_100baseT_Full; | |
3652 | ||
3653 | tg3_phy_autoneg_cfg(tp, new_adv, | |
3654 | FLOW_CTRL_TX | FLOW_CTRL_RX); | |
3655 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
3656 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
3657 | tp->link_config.advertising &= | |
3658 | ~(ADVERTISED_1000baseT_Half | | |
3659 | ADVERTISED_1000baseT_Full); | |
3660 | ||
3661 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, | |
3662 | tp->link_config.flowctrl); | |
3663 | } else { | |
3664 | /* Asking for a specific link mode. */ | |
3665 | if (tp->link_config.speed == SPEED_1000) { | |
3666 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3667 | new_adv = ADVERTISED_1000baseT_Full; | |
3668 | else | |
3669 | new_adv = ADVERTISED_1000baseT_Half; | |
3670 | } else if (tp->link_config.speed == SPEED_100) { | |
3671 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3672 | new_adv = ADVERTISED_100baseT_Full; | |
3673 | else | |
3674 | new_adv = ADVERTISED_100baseT_Half; | |
3675 | } else { | |
3676 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3677 | new_adv = ADVERTISED_10baseT_Full; | |
3678 | else | |
3679 | new_adv = ADVERTISED_10baseT_Half; | |
52b02d04 | 3680 | } |
52b02d04 | 3681 | |
42b64a45 MC |
3682 | tg3_phy_autoneg_cfg(tp, new_adv, |
3683 | tp->link_config.flowctrl); | |
52b02d04 MC |
3684 | } |
3685 | ||
1da177e4 LT |
3686 | if (tp->link_config.autoneg == AUTONEG_DISABLE && |
3687 | tp->link_config.speed != SPEED_INVALID) { | |
3688 | u32 bmcr, orig_bmcr; | |
3689 | ||
3690 | tp->link_config.active_speed = tp->link_config.speed; | |
3691 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3692 | ||
3693 | bmcr = 0; | |
3694 | switch (tp->link_config.speed) { | |
3695 | default: | |
3696 | case SPEED_10: | |
3697 | break; | |
3698 | ||
3699 | case SPEED_100: | |
3700 | bmcr |= BMCR_SPEED100; | |
3701 | break; | |
3702 | ||
3703 | case SPEED_1000: | |
221c5637 | 3704 | bmcr |= BMCR_SPEED1000; |
1da177e4 | 3705 | break; |
855e1111 | 3706 | } |
1da177e4 LT |
3707 | |
3708 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3709 | bmcr |= BMCR_FULLDPLX; | |
3710 | ||
3711 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3712 | (bmcr != orig_bmcr)) { | |
3713 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3714 | for (i = 0; i < 1500; i++) { | |
3715 | u32 tmp; | |
3716 | ||
3717 | udelay(10); | |
3718 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3719 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3720 | continue; | |
3721 | if (!(tmp & BMSR_LSTATUS)) { | |
3722 | udelay(40); | |
3723 | break; | |
3724 | } | |
3725 | } | |
3726 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3727 | udelay(40); | |
3728 | } | |
3729 | } else { | |
3730 | tg3_writephy(tp, MII_BMCR, | |
3731 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3732 | } | |
3733 | } | |
3734 | ||
3735 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3736 | { | |
3737 | int err; | |
3738 | ||
3739 | /* Turn off tap power management. */ | |
3740 | /* Set Extended packet length bit */ | |
b4bd2929 | 3741 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
1da177e4 | 3742 | |
6ee7c0a0 MC |
3743 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
3744 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3745 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3746 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3747 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
3748 | |
3749 | udelay(40); | |
3750 | ||
3751 | return err; | |
3752 | } | |
3753 | ||
e2bf73e7 | 3754 | static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) |
1da177e4 | 3755 | { |
e2bf73e7 | 3756 | u32 advmsk, tgtadv, advertising; |
3600d918 | 3757 | |
e2bf73e7 MC |
3758 | advertising = tp->link_config.advertising; |
3759 | tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL; | |
1da177e4 | 3760 | |
e2bf73e7 MC |
3761 | advmsk = ADVERTISE_ALL; |
3762 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
f88788f0 | 3763 | tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); |
e2bf73e7 MC |
3764 | advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
3765 | } | |
1da177e4 | 3766 | |
e2bf73e7 MC |
3767 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) |
3768 | return false; | |
3769 | ||
3770 | if ((*lcladv & advmsk) != tgtadv) | |
3771 | return false; | |
b99d2a57 | 3772 | |
f07e9af3 | 3773 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
3774 | u32 tg3_ctrl; |
3775 | ||
e2bf73e7 | 3776 | tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising); |
3600d918 | 3777 | |
221c5637 | 3778 | if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) |
e2bf73e7 | 3779 | return false; |
1da177e4 | 3780 | |
b99d2a57 | 3781 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL); |
e2bf73e7 MC |
3782 | if (tg3_ctrl != tgtadv) |
3783 | return false; | |
ef167e27 MC |
3784 | } |
3785 | ||
e2bf73e7 | 3786 | return true; |
ef167e27 MC |
3787 | } |
3788 | ||
859edb26 MC |
3789 | static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) |
3790 | { | |
3791 | u32 lpeth = 0; | |
3792 | ||
3793 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { | |
3794 | u32 val; | |
3795 | ||
3796 | if (tg3_readphy(tp, MII_STAT1000, &val)) | |
3797 | return false; | |
3798 | ||
3799 | lpeth = mii_stat1000_to_ethtool_lpa_t(val); | |
3800 | } | |
3801 | ||
3802 | if (tg3_readphy(tp, MII_LPA, rmtadv)) | |
3803 | return false; | |
3804 | ||
3805 | lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv); | |
3806 | tp->link_config.rmt_adv = lpeth; | |
3807 | ||
3808 | return true; | |
3809 | } | |
3810 | ||
1da177e4 LT |
3811 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3812 | { | |
3813 | int current_link_up; | |
f833c4c1 | 3814 | u32 bmsr, val; |
ef167e27 | 3815 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3816 | u16 current_speed; |
3817 | u8 current_duplex; | |
3818 | int i, err; | |
3819 | ||
3820 | tw32(MAC_EVENT, 0); | |
3821 | ||
3822 | tw32_f(MAC_STATUS, | |
3823 | (MAC_STATUS_SYNC_CHANGED | | |
3824 | MAC_STATUS_CFG_CHANGED | | |
3825 | MAC_STATUS_MI_COMPLETION | | |
3826 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3827 | udelay(40); | |
3828 | ||
8ef21428 MC |
3829 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3830 | tw32_f(MAC_MI_MODE, | |
3831 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3832 | udelay(80); | |
3833 | } | |
1da177e4 | 3834 | |
b4bd2929 | 3835 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); |
1da177e4 LT |
3836 | |
3837 | /* Some third-party PHYs need to be reset on link going | |
3838 | * down. | |
3839 | */ | |
3840 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3841 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3842 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3843 | netif_carrier_ok(tp->dev)) { | |
3844 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3845 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3846 | !(bmsr & BMSR_LSTATUS)) | |
3847 | force_reset = 1; | |
3848 | } | |
3849 | if (force_reset) | |
3850 | tg3_phy_reset(tp); | |
3851 | ||
79eb6904 | 3852 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
3853 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3854 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
63c3a66f | 3855 | !tg3_flag(tp, INIT_COMPLETE)) |
1da177e4 LT |
3856 | bmsr = 0; |
3857 | ||
3858 | if (!(bmsr & BMSR_LSTATUS)) { | |
3859 | err = tg3_init_5401phy_dsp(tp); | |
3860 | if (err) | |
3861 | return err; | |
3862 | ||
3863 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3864 | for (i = 0; i < 1000; i++) { | |
3865 | udelay(10); | |
3866 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3867 | (bmsr & BMSR_LSTATUS)) { | |
3868 | udelay(40); | |
3869 | break; | |
3870 | } | |
3871 | } | |
3872 | ||
79eb6904 MC |
3873 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
3874 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
3875 | !(bmsr & BMSR_LSTATUS) && |
3876 | tp->link_config.active_speed == SPEED_1000) { | |
3877 | err = tg3_phy_reset(tp); | |
3878 | if (!err) | |
3879 | err = tg3_init_5401phy_dsp(tp); | |
3880 | if (err) | |
3881 | return err; | |
3882 | } | |
3883 | } | |
3884 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3885 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3886 | /* 5701 {A0,B0} CRC bug workaround */ | |
3887 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
3888 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
3889 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
3890 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
3891 | } |
3892 | ||
3893 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
3894 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
3895 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 3896 | |
f07e9af3 | 3897 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 3898 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 3899 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
3900 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3901 | ||
3902 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3903 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3904 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3905 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3906 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3907 | else | |
3908 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3909 | } | |
3910 | ||
3911 | current_link_up = 0; | |
3912 | current_speed = SPEED_INVALID; | |
3913 | current_duplex = DUPLEX_INVALID; | |
e348c5e7 | 3914 | tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; |
859edb26 | 3915 | tp->link_config.rmt_adv = 0; |
1da177e4 | 3916 | |
f07e9af3 | 3917 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
15ee95c3 MC |
3918 | err = tg3_phy_auxctl_read(tp, |
3919 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3920 | &val); | |
3921 | if (!err && !(val & (1 << 10))) { | |
b4bd2929 MC |
3922 | tg3_phy_auxctl_write(tp, |
3923 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3924 | val | (1 << 10)); | |
1da177e4 LT |
3925 | goto relink; |
3926 | } | |
3927 | } | |
3928 | ||
3929 | bmsr = 0; | |
3930 | for (i = 0; i < 100; i++) { | |
3931 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3932 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3933 | (bmsr & BMSR_LSTATUS)) | |
3934 | break; | |
3935 | udelay(40); | |
3936 | } | |
3937 | ||
3938 | if (bmsr & BMSR_LSTATUS) { | |
3939 | u32 aux_stat, bmcr; | |
3940 | ||
3941 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3942 | for (i = 0; i < 2000; i++) { | |
3943 | udelay(10); | |
3944 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3945 | aux_stat) | |
3946 | break; | |
3947 | } | |
3948 | ||
3949 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3950 | ¤t_speed, | |
3951 | ¤t_duplex); | |
3952 | ||
3953 | bmcr = 0; | |
3954 | for (i = 0; i < 200; i++) { | |
3955 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3956 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3957 | continue; | |
3958 | if (bmcr && bmcr != 0x7fff) | |
3959 | break; | |
3960 | udelay(10); | |
3961 | } | |
3962 | ||
ef167e27 MC |
3963 | lcl_adv = 0; |
3964 | rmt_adv = 0; | |
1da177e4 | 3965 | |
ef167e27 MC |
3966 | tp->link_config.active_speed = current_speed; |
3967 | tp->link_config.active_duplex = current_duplex; | |
3968 | ||
3969 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3970 | if ((bmcr & BMCR_ANENABLE) && | |
e2bf73e7 | 3971 | tg3_phy_copper_an_config_ok(tp, &lcl_adv) && |
859edb26 | 3972 | tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) |
e2bf73e7 | 3973 | current_link_up = 1; |
1da177e4 LT |
3974 | } else { |
3975 | if (!(bmcr & BMCR_ANENABLE) && | |
3976 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3977 | tp->link_config.duplex == current_duplex && |
3978 | tp->link_config.flowctrl == | |
3979 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3980 | current_link_up = 1; |
1da177e4 LT |
3981 | } |
3982 | } | |
3983 | ||
ef167e27 | 3984 | if (current_link_up == 1 && |
e348c5e7 MC |
3985 | tp->link_config.active_duplex == DUPLEX_FULL) { |
3986 | u32 reg, bit; | |
3987 | ||
3988 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
3989 | reg = MII_TG3_FET_GEN_STAT; | |
3990 | bit = MII_TG3_FET_GEN_STAT_MDIXSTAT; | |
3991 | } else { | |
3992 | reg = MII_TG3_EXT_STAT; | |
3993 | bit = MII_TG3_EXT_STAT_MDIX; | |
3994 | } | |
3995 | ||
3996 | if (!tg3_readphy(tp, reg, &val) && (val & bit)) | |
3997 | tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; | |
3998 | ||
ef167e27 | 3999 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); |
e348c5e7 | 4000 | } |
1da177e4 LT |
4001 | } |
4002 | ||
1da177e4 | 4003 | relink: |
80096068 | 4004 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
4005 | tg3_phy_copper_begin(tp); |
4006 | ||
f833c4c1 | 4007 | tg3_readphy(tp, MII_BMSR, &bmsr); |
06c03c02 MB |
4008 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
4009 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
1da177e4 LT |
4010 | current_link_up = 1; |
4011 | } | |
4012 | ||
4013 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
4014 | if (current_link_up == 1) { | |
4015 | if (tp->link_config.active_speed == SPEED_100 || | |
4016 | tp->link_config.active_speed == SPEED_10) | |
4017 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
4018 | else | |
4019 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 4020 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
4021 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
4022 | else | |
1da177e4 LT |
4023 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
4024 | ||
4025 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
4026 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4027 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4028 | ||
1da177e4 | 4029 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
4030 | if (current_link_up == 1 && |
4031 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 4032 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
4033 | else |
4034 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
4035 | } |
4036 | ||
4037 | /* ??? Without this setting Netgear GA302T PHY does not | |
4038 | * ??? send/receive packets... | |
4039 | */ | |
79eb6904 | 4040 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
4041 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
4042 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
4043 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
4044 | udelay(80); | |
4045 | } | |
4046 | ||
4047 | tw32_f(MAC_MODE, tp->mac_mode); | |
4048 | udelay(40); | |
4049 | ||
52b02d04 MC |
4050 | tg3_phy_eee_adjust(tp, current_link_up); |
4051 | ||
63c3a66f | 4052 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
4053 | /* Polled via timer. */ |
4054 | tw32_f(MAC_EVENT, 0); | |
4055 | } else { | |
4056 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4057 | } | |
4058 | udelay(40); | |
4059 | ||
4060 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
4061 | current_link_up == 1 && | |
4062 | tp->link_config.active_speed == SPEED_1000 && | |
63c3a66f | 4063 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
1da177e4 LT |
4064 | udelay(120); |
4065 | tw32_f(MAC_STATUS, | |
4066 | (MAC_STATUS_SYNC_CHANGED | | |
4067 | MAC_STATUS_CFG_CHANGED)); | |
4068 | udelay(40); | |
4069 | tg3_write_mem(tp, | |
4070 | NIC_SRAM_FIRMWARE_MBOX, | |
4071 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
4072 | } | |
4073 | ||
5e7dfd0f | 4074 | /* Prevent send BD corruption. */ |
63c3a66f | 4075 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
4076 | u16 oldlnkctl, newlnkctl; |
4077 | ||
4078 | pci_read_config_word(tp->pdev, | |
708ebb3a | 4079 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
4080 | &oldlnkctl); |
4081 | if (tp->link_config.active_speed == SPEED_100 || | |
4082 | tp->link_config.active_speed == SPEED_10) | |
4083 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
4084 | else | |
4085 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
4086 | if (newlnkctl != oldlnkctl) | |
4087 | pci_write_config_word(tp->pdev, | |
93a700a9 MC |
4088 | pci_pcie_cap(tp->pdev) + |
4089 | PCI_EXP_LNKCTL, newlnkctl); | |
5e7dfd0f MC |
4090 | } |
4091 | ||
1da177e4 LT |
4092 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
4093 | if (current_link_up) | |
4094 | netif_carrier_on(tp->dev); | |
4095 | else | |
4096 | netif_carrier_off(tp->dev); | |
4097 | tg3_link_report(tp); | |
4098 | } | |
4099 | ||
4100 | return 0; | |
4101 | } | |
4102 | ||
4103 | struct tg3_fiber_aneginfo { | |
4104 | int state; | |
4105 | #define ANEG_STATE_UNKNOWN 0 | |
4106 | #define ANEG_STATE_AN_ENABLE 1 | |
4107 | #define ANEG_STATE_RESTART_INIT 2 | |
4108 | #define ANEG_STATE_RESTART 3 | |
4109 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
4110 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
4111 | #define ANEG_STATE_ABILITY_DETECT 6 | |
4112 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
4113 | #define ANEG_STATE_ACK_DETECT 8 | |
4114 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
4115 | #define ANEG_STATE_COMPLETE_ACK 10 | |
4116 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
4117 | #define ANEG_STATE_IDLE_DETECT 12 | |
4118 | #define ANEG_STATE_LINK_OK 13 | |
4119 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
4120 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
4121 | ||
4122 | u32 flags; | |
4123 | #define MR_AN_ENABLE 0x00000001 | |
4124 | #define MR_RESTART_AN 0x00000002 | |
4125 | #define MR_AN_COMPLETE 0x00000004 | |
4126 | #define MR_PAGE_RX 0x00000008 | |
4127 | #define MR_NP_LOADED 0x00000010 | |
4128 | #define MR_TOGGLE_TX 0x00000020 | |
4129 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
4130 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
4131 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
4132 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
4133 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
4134 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
4135 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
4136 | #define MR_TOGGLE_RX 0x00002000 | |
4137 | #define MR_NP_RX 0x00004000 | |
4138 | ||
4139 | #define MR_LINK_OK 0x80000000 | |
4140 | ||
4141 | unsigned long link_time, cur_time; | |
4142 | ||
4143 | u32 ability_match_cfg; | |
4144 | int ability_match_count; | |
4145 | ||
4146 | char ability_match, idle_match, ack_match; | |
4147 | ||
4148 | u32 txconfig, rxconfig; | |
4149 | #define ANEG_CFG_NP 0x00000080 | |
4150 | #define ANEG_CFG_ACK 0x00000040 | |
4151 | #define ANEG_CFG_RF2 0x00000020 | |
4152 | #define ANEG_CFG_RF1 0x00000010 | |
4153 | #define ANEG_CFG_PS2 0x00000001 | |
4154 | #define ANEG_CFG_PS1 0x00008000 | |
4155 | #define ANEG_CFG_HD 0x00004000 | |
4156 | #define ANEG_CFG_FD 0x00002000 | |
4157 | #define ANEG_CFG_INVAL 0x00001f06 | |
4158 | ||
4159 | }; | |
4160 | #define ANEG_OK 0 | |
4161 | #define ANEG_DONE 1 | |
4162 | #define ANEG_TIMER_ENAB 2 | |
4163 | #define ANEG_FAILED -1 | |
4164 | ||
4165 | #define ANEG_STATE_SETTLE_TIME 10000 | |
4166 | ||
4167 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
4168 | struct tg3_fiber_aneginfo *ap) | |
4169 | { | |
5be73b47 | 4170 | u16 flowctrl; |
1da177e4 LT |
4171 | unsigned long delta; |
4172 | u32 rx_cfg_reg; | |
4173 | int ret; | |
4174 | ||
4175 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
4176 | ap->rxconfig = 0; | |
4177 | ap->link_time = 0; | |
4178 | ap->cur_time = 0; | |
4179 | ap->ability_match_cfg = 0; | |
4180 | ap->ability_match_count = 0; | |
4181 | ap->ability_match = 0; | |
4182 | ap->idle_match = 0; | |
4183 | ap->ack_match = 0; | |
4184 | } | |
4185 | ap->cur_time++; | |
4186 | ||
4187 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
4188 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
4189 | ||
4190 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
4191 | ap->ability_match_cfg = rx_cfg_reg; | |
4192 | ap->ability_match = 0; | |
4193 | ap->ability_match_count = 0; | |
4194 | } else { | |
4195 | if (++ap->ability_match_count > 1) { | |
4196 | ap->ability_match = 1; | |
4197 | ap->ability_match_cfg = rx_cfg_reg; | |
4198 | } | |
4199 | } | |
4200 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
4201 | ap->ack_match = 1; | |
4202 | else | |
4203 | ap->ack_match = 0; | |
4204 | ||
4205 | ap->idle_match = 0; | |
4206 | } else { | |
4207 | ap->idle_match = 1; | |
4208 | ap->ability_match_cfg = 0; | |
4209 | ap->ability_match_count = 0; | |
4210 | ap->ability_match = 0; | |
4211 | ap->ack_match = 0; | |
4212 | ||
4213 | rx_cfg_reg = 0; | |
4214 | } | |
4215 | ||
4216 | ap->rxconfig = rx_cfg_reg; | |
4217 | ret = ANEG_OK; | |
4218 | ||
33f401ae | 4219 | switch (ap->state) { |
1da177e4 LT |
4220 | case ANEG_STATE_UNKNOWN: |
4221 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
4222 | ap->state = ANEG_STATE_AN_ENABLE; | |
4223 | ||
4224 | /* fallthru */ | |
4225 | case ANEG_STATE_AN_ENABLE: | |
4226 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
4227 | if (ap->flags & MR_AN_ENABLE) { | |
4228 | ap->link_time = 0; | |
4229 | ap->cur_time = 0; | |
4230 | ap->ability_match_cfg = 0; | |
4231 | ap->ability_match_count = 0; | |
4232 | ap->ability_match = 0; | |
4233 | ap->idle_match = 0; | |
4234 | ap->ack_match = 0; | |
4235 | ||
4236 | ap->state = ANEG_STATE_RESTART_INIT; | |
4237 | } else { | |
4238 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
4239 | } | |
4240 | break; | |
4241 | ||
4242 | case ANEG_STATE_RESTART_INIT: | |
4243 | ap->link_time = ap->cur_time; | |
4244 | ap->flags &= ~(MR_NP_LOADED); | |
4245 | ap->txconfig = 0; | |
4246 | tw32(MAC_TX_AUTO_NEG, 0); | |
4247 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4248 | tw32_f(MAC_MODE, tp->mac_mode); | |
4249 | udelay(40); | |
4250 | ||
4251 | ret = ANEG_TIMER_ENAB; | |
4252 | ap->state = ANEG_STATE_RESTART; | |
4253 | ||
4254 | /* fallthru */ | |
4255 | case ANEG_STATE_RESTART: | |
4256 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 4257 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 4258 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 4259 | else |
1da177e4 | 4260 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
4261 | break; |
4262 | ||
4263 | case ANEG_STATE_DISABLE_LINK_OK: | |
4264 | ret = ANEG_DONE; | |
4265 | break; | |
4266 | ||
4267 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
4268 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
4269 | ap->txconfig = ANEG_CFG_FD; |
4270 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
4271 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4272 | ap->txconfig |= ANEG_CFG_PS1; | |
4273 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4274 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
4275 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
4276 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4277 | tw32_f(MAC_MODE, tp->mac_mode); | |
4278 | udelay(40); | |
4279 | ||
4280 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
4281 | break; | |
4282 | ||
4283 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 4284 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 4285 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
4286 | break; |
4287 | ||
4288 | case ANEG_STATE_ACK_DETECT_INIT: | |
4289 | ap->txconfig |= ANEG_CFG_ACK; | |
4290 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
4291 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4292 | tw32_f(MAC_MODE, tp->mac_mode); | |
4293 | udelay(40); | |
4294 | ||
4295 | ap->state = ANEG_STATE_ACK_DETECT; | |
4296 | ||
4297 | /* fallthru */ | |
4298 | case ANEG_STATE_ACK_DETECT: | |
4299 | if (ap->ack_match != 0) { | |
4300 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
4301 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
4302 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
4303 | } else { | |
4304 | ap->state = ANEG_STATE_AN_ENABLE; | |
4305 | } | |
4306 | } else if (ap->ability_match != 0 && | |
4307 | ap->rxconfig == 0) { | |
4308 | ap->state = ANEG_STATE_AN_ENABLE; | |
4309 | } | |
4310 | break; | |
4311 | ||
4312 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
4313 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
4314 | ret = ANEG_FAILED; | |
4315 | break; | |
4316 | } | |
4317 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
4318 | MR_LP_ADV_HALF_DUPLEX | | |
4319 | MR_LP_ADV_SYM_PAUSE | | |
4320 | MR_LP_ADV_ASYM_PAUSE | | |
4321 | MR_LP_ADV_REMOTE_FAULT1 | | |
4322 | MR_LP_ADV_REMOTE_FAULT2 | | |
4323 | MR_LP_ADV_NEXT_PAGE | | |
4324 | MR_TOGGLE_RX | | |
4325 | MR_NP_RX); | |
4326 | if (ap->rxconfig & ANEG_CFG_FD) | |
4327 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
4328 | if (ap->rxconfig & ANEG_CFG_HD) | |
4329 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
4330 | if (ap->rxconfig & ANEG_CFG_PS1) | |
4331 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
4332 | if (ap->rxconfig & ANEG_CFG_PS2) | |
4333 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
4334 | if (ap->rxconfig & ANEG_CFG_RF1) | |
4335 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
4336 | if (ap->rxconfig & ANEG_CFG_RF2) | |
4337 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
4338 | if (ap->rxconfig & ANEG_CFG_NP) | |
4339 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
4340 | ||
4341 | ap->link_time = ap->cur_time; | |
4342 | ||
4343 | ap->flags ^= (MR_TOGGLE_TX); | |
4344 | if (ap->rxconfig & 0x0008) | |
4345 | ap->flags |= MR_TOGGLE_RX; | |
4346 | if (ap->rxconfig & ANEG_CFG_NP) | |
4347 | ap->flags |= MR_NP_RX; | |
4348 | ap->flags |= MR_PAGE_RX; | |
4349 | ||
4350 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
4351 | ret = ANEG_TIMER_ENAB; | |
4352 | break; | |
4353 | ||
4354 | case ANEG_STATE_COMPLETE_ACK: | |
4355 | if (ap->ability_match != 0 && | |
4356 | ap->rxconfig == 0) { | |
4357 | ap->state = ANEG_STATE_AN_ENABLE; | |
4358 | break; | |
4359 | } | |
4360 | delta = ap->cur_time - ap->link_time; | |
4361 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
4362 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
4363 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
4364 | } else { | |
4365 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
4366 | !(ap->flags & MR_NP_RX)) { | |
4367 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
4368 | } else { | |
4369 | ret = ANEG_FAILED; | |
4370 | } | |
4371 | } | |
4372 | } | |
4373 | break; | |
4374 | ||
4375 | case ANEG_STATE_IDLE_DETECT_INIT: | |
4376 | ap->link_time = ap->cur_time; | |
4377 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
4378 | tw32_f(MAC_MODE, tp->mac_mode); | |
4379 | udelay(40); | |
4380 | ||
4381 | ap->state = ANEG_STATE_IDLE_DETECT; | |
4382 | ret = ANEG_TIMER_ENAB; | |
4383 | break; | |
4384 | ||
4385 | case ANEG_STATE_IDLE_DETECT: | |
4386 | if (ap->ability_match != 0 && | |
4387 | ap->rxconfig == 0) { | |
4388 | ap->state = ANEG_STATE_AN_ENABLE; | |
4389 | break; | |
4390 | } | |
4391 | delta = ap->cur_time - ap->link_time; | |
4392 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
4393 | /* XXX another gem from the Broadcom driver :( */ | |
4394 | ap->state = ANEG_STATE_LINK_OK; | |
4395 | } | |
4396 | break; | |
4397 | ||
4398 | case ANEG_STATE_LINK_OK: | |
4399 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
4400 | ret = ANEG_DONE; | |
4401 | break; | |
4402 | ||
4403 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
4404 | /* ??? unimplemented */ | |
4405 | break; | |
4406 | ||
4407 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
4408 | /* ??? unimplemented */ | |
4409 | break; | |
4410 | ||
4411 | default: | |
4412 | ret = ANEG_FAILED; | |
4413 | break; | |
855e1111 | 4414 | } |
1da177e4 LT |
4415 | |
4416 | return ret; | |
4417 | } | |
4418 | ||
5be73b47 | 4419 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
4420 | { |
4421 | int res = 0; | |
4422 | struct tg3_fiber_aneginfo aninfo; | |
4423 | int status = ANEG_FAILED; | |
4424 | unsigned int tick; | |
4425 | u32 tmp; | |
4426 | ||
4427 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4428 | ||
4429 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
4430 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
4431 | udelay(40); | |
4432 | ||
4433 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
4434 | udelay(40); | |
4435 | ||
4436 | memset(&aninfo, 0, sizeof(aninfo)); | |
4437 | aninfo.flags |= MR_AN_ENABLE; | |
4438 | aninfo.state = ANEG_STATE_UNKNOWN; | |
4439 | aninfo.cur_time = 0; | |
4440 | tick = 0; | |
4441 | while (++tick < 195000) { | |
4442 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
4443 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
4444 | break; | |
4445 | ||
4446 | udelay(1); | |
4447 | } | |
4448 | ||
4449 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
4450 | tw32_f(MAC_MODE, tp->mac_mode); | |
4451 | udelay(40); | |
4452 | ||
5be73b47 MC |
4453 | *txflags = aninfo.txconfig; |
4454 | *rxflags = aninfo.flags; | |
1da177e4 LT |
4455 | |
4456 | if (status == ANEG_DONE && | |
4457 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
4458 | MR_LP_ADV_FULL_DUPLEX))) | |
4459 | res = 1; | |
4460 | ||
4461 | return res; | |
4462 | } | |
4463 | ||
4464 | static void tg3_init_bcm8002(struct tg3 *tp) | |
4465 | { | |
4466 | u32 mac_status = tr32(MAC_STATUS); | |
4467 | int i; | |
4468 | ||
4469 | /* Reset when initting first time or we have a link. */ | |
63c3a66f | 4470 | if (tg3_flag(tp, INIT_COMPLETE) && |
1da177e4 LT |
4471 | !(mac_status & MAC_STATUS_PCS_SYNCED)) |
4472 | return; | |
4473 | ||
4474 | /* Set PLL lock range. */ | |
4475 | tg3_writephy(tp, 0x16, 0x8007); | |
4476 | ||
4477 | /* SW reset */ | |
4478 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
4479 | ||
4480 | /* Wait for reset to complete. */ | |
4481 | /* XXX schedule_timeout() ... */ | |
4482 | for (i = 0; i < 500; i++) | |
4483 | udelay(10); | |
4484 | ||
4485 | /* Config mode; select PMA/Ch 1 regs. */ | |
4486 | tg3_writephy(tp, 0x10, 0x8411); | |
4487 | ||
4488 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
4489 | tg3_writephy(tp, 0x11, 0x0a10); | |
4490 | ||
4491 | tg3_writephy(tp, 0x18, 0x00a0); | |
4492 | tg3_writephy(tp, 0x16, 0x41ff); | |
4493 | ||
4494 | /* Assert and deassert POR. */ | |
4495 | tg3_writephy(tp, 0x13, 0x0400); | |
4496 | udelay(40); | |
4497 | tg3_writephy(tp, 0x13, 0x0000); | |
4498 | ||
4499 | tg3_writephy(tp, 0x11, 0x0a50); | |
4500 | udelay(40); | |
4501 | tg3_writephy(tp, 0x11, 0x0a10); | |
4502 | ||
4503 | /* Wait for signal to stabilize */ | |
4504 | /* XXX schedule_timeout() ... */ | |
4505 | for (i = 0; i < 15000; i++) | |
4506 | udelay(10); | |
4507 | ||
4508 | /* Deselect the channel register so we can read the PHYID | |
4509 | * later. | |
4510 | */ | |
4511 | tg3_writephy(tp, 0x10, 0x8011); | |
4512 | } | |
4513 | ||
4514 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
4515 | { | |
82cd3d11 | 4516 | u16 flowctrl; |
1da177e4 LT |
4517 | u32 sg_dig_ctrl, sg_dig_status; |
4518 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
4519 | int workaround, port_a; | |
4520 | int current_link_up; | |
4521 | ||
4522 | serdes_cfg = 0; | |
4523 | expected_sg_dig_ctrl = 0; | |
4524 | workaround = 0; | |
4525 | port_a = 1; | |
4526 | current_link_up = 0; | |
4527 | ||
4528 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
4529 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
4530 | workaround = 1; | |
4531 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
4532 | port_a = 0; | |
4533 | ||
4534 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
4535 | /* preserve bits 20-23 for voltage regulator */ | |
4536 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
4537 | } | |
4538 | ||
4539 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
4540 | ||
4541 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 4542 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
4543 | if (workaround) { |
4544 | u32 val = serdes_cfg; | |
4545 | ||
4546 | if (port_a) | |
4547 | val |= 0xc010000; | |
4548 | else | |
4549 | val |= 0x4010000; | |
4550 | tw32_f(MAC_SERDES_CFG, val); | |
4551 | } | |
c98f6e3b MC |
4552 | |
4553 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
4554 | } |
4555 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
4556 | tg3_setup_flow_control(tp, 0, 0); | |
4557 | current_link_up = 1; | |
4558 | } | |
4559 | goto out; | |
4560 | } | |
4561 | ||
4562 | /* Want auto-negotiation. */ | |
c98f6e3b | 4563 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 4564 | |
82cd3d11 MC |
4565 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
4566 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4567 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
4568 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4569 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
4570 | |
4571 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 4572 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
4573 | tp->serdes_counter && |
4574 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
4575 | MAC_STATUS_RCVD_CFG)) == | |
4576 | MAC_STATUS_PCS_SYNCED)) { | |
4577 | tp->serdes_counter--; | |
4578 | current_link_up = 1; | |
4579 | goto out; | |
4580 | } | |
4581 | restart_autoneg: | |
1da177e4 LT |
4582 | if (workaround) |
4583 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 4584 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
4585 | udelay(5); |
4586 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
4587 | ||
3d3ebe74 | 4588 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 4589 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4590 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
4591 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 4592 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
4593 | mac_status = tr32(MAC_STATUS); |
4594 | ||
c98f6e3b | 4595 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 4596 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
4597 | u32 local_adv = 0, remote_adv = 0; |
4598 | ||
4599 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
4600 | local_adv |= ADVERTISE_1000XPAUSE; | |
4601 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
4602 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 4603 | |
c98f6e3b | 4604 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 4605 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 4606 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 4607 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 | 4608 | |
859edb26 MC |
4609 | tp->link_config.rmt_adv = |
4610 | mii_adv_to_ethtool_adv_x(remote_adv); | |
4611 | ||
1da177e4 LT |
4612 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
4613 | current_link_up = 1; | |
3d3ebe74 | 4614 | tp->serdes_counter = 0; |
f07e9af3 | 4615 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 4616 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
4617 | if (tp->serdes_counter) |
4618 | tp->serdes_counter--; | |
1da177e4 LT |
4619 | else { |
4620 | if (workaround) { | |
4621 | u32 val = serdes_cfg; | |
4622 | ||
4623 | if (port_a) | |
4624 | val |= 0xc010000; | |
4625 | else | |
4626 | val |= 0x4010000; | |
4627 | ||
4628 | tw32_f(MAC_SERDES_CFG, val); | |
4629 | } | |
4630 | ||
c98f6e3b | 4631 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
4632 | udelay(40); |
4633 | ||
4634 | /* Link parallel detection - link is up */ | |
4635 | /* only if we have PCS_SYNC and not */ | |
4636 | /* receiving config code words */ | |
4637 | mac_status = tr32(MAC_STATUS); | |
4638 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
4639 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
4640 | tg3_setup_flow_control(tp, 0, 0); | |
4641 | current_link_up = 1; | |
f07e9af3 MC |
4642 | tp->phy_flags |= |
4643 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
4644 | tp->serdes_counter = |
4645 | SERDES_PARALLEL_DET_TIMEOUT; | |
4646 | } else | |
4647 | goto restart_autoneg; | |
1da177e4 LT |
4648 | } |
4649 | } | |
3d3ebe74 MC |
4650 | } else { |
4651 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 4652 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4653 | } |
4654 | ||
4655 | out: | |
4656 | return current_link_up; | |
4657 | } | |
4658 | ||
4659 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
4660 | { | |
4661 | int current_link_up = 0; | |
4662 | ||
5cf64b8a | 4663 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 4664 | goto out; |
1da177e4 LT |
4665 | |
4666 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 4667 | u32 txflags, rxflags; |
1da177e4 | 4668 | int i; |
6aa20a22 | 4669 | |
5be73b47 MC |
4670 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
4671 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 4672 | |
5be73b47 MC |
4673 | if (txflags & ANEG_CFG_PS1) |
4674 | local_adv |= ADVERTISE_1000XPAUSE; | |
4675 | if (txflags & ANEG_CFG_PS2) | |
4676 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
4677 | ||
4678 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
4679 | remote_adv |= LPA_1000XPAUSE; | |
4680 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
4681 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 | 4682 | |
859edb26 MC |
4683 | tp->link_config.rmt_adv = |
4684 | mii_adv_to_ethtool_adv_x(remote_adv); | |
4685 | ||
1da177e4 LT |
4686 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
4687 | ||
1da177e4 LT |
4688 | current_link_up = 1; |
4689 | } | |
4690 | for (i = 0; i < 30; i++) { | |
4691 | udelay(20); | |
4692 | tw32_f(MAC_STATUS, | |
4693 | (MAC_STATUS_SYNC_CHANGED | | |
4694 | MAC_STATUS_CFG_CHANGED)); | |
4695 | udelay(40); | |
4696 | if ((tr32(MAC_STATUS) & | |
4697 | (MAC_STATUS_SYNC_CHANGED | | |
4698 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4699 | break; | |
4700 | } | |
4701 | ||
4702 | mac_status = tr32(MAC_STATUS); | |
4703 | if (current_link_up == 0 && | |
4704 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4705 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4706 | current_link_up = 1; | |
4707 | } else { | |
5be73b47 MC |
4708 | tg3_setup_flow_control(tp, 0, 0); |
4709 | ||
1da177e4 LT |
4710 | /* Forcing 1000FD link up. */ |
4711 | current_link_up = 1; | |
1da177e4 LT |
4712 | |
4713 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4714 | udelay(40); | |
e8f3f6ca MC |
4715 | |
4716 | tw32_f(MAC_MODE, tp->mac_mode); | |
4717 | udelay(40); | |
1da177e4 LT |
4718 | } |
4719 | ||
4720 | out: | |
4721 | return current_link_up; | |
4722 | } | |
4723 | ||
4724 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4725 | { | |
4726 | u32 orig_pause_cfg; | |
4727 | u16 orig_active_speed; | |
4728 | u8 orig_active_duplex; | |
4729 | u32 mac_status; | |
4730 | int current_link_up; | |
4731 | int i; | |
4732 | ||
8d018621 | 4733 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4734 | orig_active_speed = tp->link_config.active_speed; |
4735 | orig_active_duplex = tp->link_config.active_duplex; | |
4736 | ||
63c3a66f | 4737 | if (!tg3_flag(tp, HW_AUTONEG) && |
1da177e4 | 4738 | netif_carrier_ok(tp->dev) && |
63c3a66f | 4739 | tg3_flag(tp, INIT_COMPLETE)) { |
1da177e4 LT |
4740 | mac_status = tr32(MAC_STATUS); |
4741 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4742 | MAC_STATUS_SIGNAL_DET | | |
4743 | MAC_STATUS_CFG_CHANGED | | |
4744 | MAC_STATUS_RCVD_CFG); | |
4745 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4746 | MAC_STATUS_SIGNAL_DET)) { | |
4747 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4748 | MAC_STATUS_CFG_CHANGED)); | |
4749 | return 0; | |
4750 | } | |
4751 | } | |
4752 | ||
4753 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4754 | ||
4755 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
4756 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
4757 | tw32_f(MAC_MODE, tp->mac_mode); | |
4758 | udelay(40); | |
4759 | ||
79eb6904 | 4760 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
4761 | tg3_init_bcm8002(tp); |
4762 | ||
4763 | /* Enable link change event even when serdes polling. */ | |
4764 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4765 | udelay(40); | |
4766 | ||
4767 | current_link_up = 0; | |
859edb26 | 4768 | tp->link_config.rmt_adv = 0; |
1da177e4 LT |
4769 | mac_status = tr32(MAC_STATUS); |
4770 | ||
63c3a66f | 4771 | if (tg3_flag(tp, HW_AUTONEG)) |
1da177e4 LT |
4772 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); |
4773 | else | |
4774 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
4775 | ||
898a56f8 | 4776 | tp->napi[0].hw_status->status = |
1da177e4 | 4777 | (SD_STATUS_UPDATED | |
898a56f8 | 4778 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
4779 | |
4780 | for (i = 0; i < 100; i++) { | |
4781 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4782 | MAC_STATUS_CFG_CHANGED)); | |
4783 | udelay(5); | |
4784 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
4785 | MAC_STATUS_CFG_CHANGED | |
4786 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
4787 | break; |
4788 | } | |
4789 | ||
4790 | mac_status = tr32(MAC_STATUS); | |
4791 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4792 | current_link_up = 0; | |
3d3ebe74 MC |
4793 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
4794 | tp->serdes_counter == 0) { | |
1da177e4 LT |
4795 | tw32_f(MAC_MODE, (tp->mac_mode | |
4796 | MAC_MODE_SEND_CONFIGS)); | |
4797 | udelay(1); | |
4798 | tw32_f(MAC_MODE, tp->mac_mode); | |
4799 | } | |
4800 | } | |
4801 | ||
4802 | if (current_link_up == 1) { | |
4803 | tp->link_config.active_speed = SPEED_1000; | |
4804 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4805 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4806 | LED_CTRL_LNKLED_OVERRIDE | | |
4807 | LED_CTRL_1000MBPS_ON)); | |
4808 | } else { | |
4809 | tp->link_config.active_speed = SPEED_INVALID; | |
4810 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4811 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4812 | LED_CTRL_LNKLED_OVERRIDE | | |
4813 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4814 | } | |
4815 | ||
4816 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4817 | if (current_link_up) | |
4818 | netif_carrier_on(tp->dev); | |
4819 | else | |
4820 | netif_carrier_off(tp->dev); | |
4821 | tg3_link_report(tp); | |
4822 | } else { | |
8d018621 | 4823 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4824 | if (orig_pause_cfg != now_pause_cfg || |
4825 | orig_active_speed != tp->link_config.active_speed || | |
4826 | orig_active_duplex != tp->link_config.active_duplex) | |
4827 | tg3_link_report(tp); | |
4828 | } | |
4829 | ||
4830 | return 0; | |
4831 | } | |
4832 | ||
747e8f8b MC |
4833 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4834 | { | |
4835 | int current_link_up, err = 0; | |
4836 | u32 bmsr, bmcr; | |
4837 | u16 current_speed; | |
4838 | u8 current_duplex; | |
ef167e27 | 4839 | u32 local_adv, remote_adv; |
747e8f8b MC |
4840 | |
4841 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4842 | tw32_f(MAC_MODE, tp->mac_mode); | |
4843 | udelay(40); | |
4844 | ||
4845 | tw32(MAC_EVENT, 0); | |
4846 | ||
4847 | tw32_f(MAC_STATUS, | |
4848 | (MAC_STATUS_SYNC_CHANGED | | |
4849 | MAC_STATUS_CFG_CHANGED | | |
4850 | MAC_STATUS_MI_COMPLETION | | |
4851 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4852 | udelay(40); | |
4853 | ||
4854 | if (force_reset) | |
4855 | tg3_phy_reset(tp); | |
4856 | ||
4857 | current_link_up = 0; | |
4858 | current_speed = SPEED_INVALID; | |
4859 | current_duplex = DUPLEX_INVALID; | |
859edb26 | 4860 | tp->link_config.rmt_adv = 0; |
747e8f8b MC |
4861 | |
4862 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4863 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4864 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4865 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4866 | bmsr |= BMSR_LSTATUS; | |
4867 | else | |
4868 | bmsr &= ~BMSR_LSTATUS; | |
4869 | } | |
747e8f8b MC |
4870 | |
4871 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4872 | ||
4873 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 4874 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4875 | /* do nothing, just check for link up at the end */ |
4876 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
28011cf1 | 4877 | u32 adv, newadv; |
747e8f8b MC |
4878 | |
4879 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
28011cf1 MC |
4880 | newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | |
4881 | ADVERTISE_1000XPAUSE | | |
4882 | ADVERTISE_1000XPSE_ASYM | | |
4883 | ADVERTISE_SLCT); | |
747e8f8b | 4884 | |
28011cf1 | 4885 | newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
37f07023 | 4886 | newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); |
747e8f8b | 4887 | |
28011cf1 MC |
4888 | if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) { |
4889 | tg3_writephy(tp, MII_ADVERTISE, newadv); | |
747e8f8b MC |
4890 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; |
4891 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4892 | ||
4893 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4894 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 4895 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4896 | |
4897 | return err; | |
4898 | } | |
4899 | } else { | |
4900 | u32 new_bmcr; | |
4901 | ||
4902 | bmcr &= ~BMCR_SPEED1000; | |
4903 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4904 | ||
4905 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4906 | new_bmcr |= BMCR_FULLDPLX; | |
4907 | ||
4908 | if (new_bmcr != bmcr) { | |
4909 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4910 | * to be set on write. | |
4911 | */ | |
4912 | new_bmcr |= BMCR_SPEED1000; | |
4913 | ||
4914 | /* Force a linkdown */ | |
4915 | if (netif_carrier_ok(tp->dev)) { | |
4916 | u32 adv; | |
4917 | ||
4918 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4919 | adv &= ~(ADVERTISE_1000XFULL | | |
4920 | ADVERTISE_1000XHALF | | |
4921 | ADVERTISE_SLCT); | |
4922 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4923 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4924 | BMCR_ANRESTART | | |
4925 | BMCR_ANENABLE); | |
4926 | udelay(10); | |
4927 | netif_carrier_off(tp->dev); | |
4928 | } | |
4929 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4930 | bmcr = new_bmcr; | |
4931 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4932 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4933 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4934 | ASIC_REV_5714) { | |
4935 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4936 | bmsr |= BMSR_LSTATUS; | |
4937 | else | |
4938 | bmsr &= ~BMSR_LSTATUS; | |
4939 | } | |
f07e9af3 | 4940 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4941 | } |
4942 | } | |
4943 | ||
4944 | if (bmsr & BMSR_LSTATUS) { | |
4945 | current_speed = SPEED_1000; | |
4946 | current_link_up = 1; | |
4947 | if (bmcr & BMCR_FULLDPLX) | |
4948 | current_duplex = DUPLEX_FULL; | |
4949 | else | |
4950 | current_duplex = DUPLEX_HALF; | |
4951 | ||
ef167e27 MC |
4952 | local_adv = 0; |
4953 | remote_adv = 0; | |
4954 | ||
747e8f8b | 4955 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4956 | u32 common; |
747e8f8b MC |
4957 | |
4958 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4959 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4960 | common = local_adv & remote_adv; | |
4961 | if (common & (ADVERTISE_1000XHALF | | |
4962 | ADVERTISE_1000XFULL)) { | |
4963 | if (common & ADVERTISE_1000XFULL) | |
4964 | current_duplex = DUPLEX_FULL; | |
4965 | else | |
4966 | current_duplex = DUPLEX_HALF; | |
859edb26 MC |
4967 | |
4968 | tp->link_config.rmt_adv = | |
4969 | mii_adv_to_ethtool_adv_x(remote_adv); | |
63c3a66f | 4970 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
57d8b880 | 4971 | /* Link is up via parallel detect */ |
859a5887 | 4972 | } else { |
747e8f8b | 4973 | current_link_up = 0; |
859a5887 | 4974 | } |
747e8f8b MC |
4975 | } |
4976 | } | |
4977 | ||
ef167e27 MC |
4978 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4979 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4980 | ||
747e8f8b MC |
4981 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4982 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4983 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4984 | ||
4985 | tw32_f(MAC_MODE, tp->mac_mode); | |
4986 | udelay(40); | |
4987 | ||
4988 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4989 | ||
4990 | tp->link_config.active_speed = current_speed; | |
4991 | tp->link_config.active_duplex = current_duplex; | |
4992 | ||
4993 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4994 | if (current_link_up) | |
4995 | netif_carrier_on(tp->dev); | |
4996 | else { | |
4997 | netif_carrier_off(tp->dev); | |
f07e9af3 | 4998 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4999 | } |
5000 | tg3_link_report(tp); | |
5001 | } | |
5002 | return err; | |
5003 | } | |
5004 | ||
5005 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
5006 | { | |
3d3ebe74 | 5007 | if (tp->serdes_counter) { |
747e8f8b | 5008 | /* Give autoneg time to complete. */ |
3d3ebe74 | 5009 | tp->serdes_counter--; |
747e8f8b MC |
5010 | return; |
5011 | } | |
c6cdf436 | 5012 | |
747e8f8b MC |
5013 | if (!netif_carrier_ok(tp->dev) && |
5014 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
5015 | u32 bmcr; | |
5016 | ||
5017 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
5018 | if (bmcr & BMCR_ANENABLE) { | |
5019 | u32 phy1, phy2; | |
5020 | ||
5021 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
5022 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
5023 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
5024 | |
5025 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
5026 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
5027 | MII_TG3_DSP_EXP1_INT_STAT); | |
5028 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
5029 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
5030 | |
5031 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
5032 | /* We have signal detect and not receiving | |
5033 | * config code words, link is up by parallel | |
5034 | * detection. | |
5035 | */ | |
5036 | ||
5037 | bmcr &= ~BMCR_ANENABLE; | |
5038 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
5039 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 5040 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5041 | } |
5042 | } | |
859a5887 MC |
5043 | } else if (netif_carrier_ok(tp->dev) && |
5044 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
f07e9af3 | 5045 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
5046 | u32 phy2; |
5047 | ||
5048 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
5049 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
5050 | MII_TG3_DSP_EXP1_INT_STAT); | |
5051 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
5052 | if (phy2 & 0x20) { |
5053 | u32 bmcr; | |
5054 | ||
5055 | /* Config code words received, turn on autoneg. */ | |
5056 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
5057 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
5058 | ||
f07e9af3 | 5059 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5060 | |
5061 | } | |
5062 | } | |
5063 | } | |
5064 | ||
1da177e4 LT |
5065 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
5066 | { | |
f2096f94 | 5067 | u32 val; |
1da177e4 LT |
5068 | int err; |
5069 | ||
f07e9af3 | 5070 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 5071 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 5072 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 5073 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 5074 | else |
1da177e4 | 5075 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 5076 | |
bcb37f6c | 5077 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
f2096f94 | 5078 | u32 scale; |
aa6c91fe MC |
5079 | |
5080 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
5081 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
5082 | scale = 65; | |
5083 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
5084 | scale = 6; | |
5085 | else | |
5086 | scale = 12; | |
5087 | ||
5088 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
5089 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
5090 | tw32(GRC_MISC_CFG, val); | |
5091 | } | |
5092 | ||
f2096f94 MC |
5093 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
5094 | (6 << TX_LENGTHS_IPG_SHIFT); | |
5095 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
5096 | val |= tr32(MAC_TX_LENGTHS) & | |
5097 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
5098 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
5099 | ||
1da177e4 LT |
5100 | if (tp->link_config.active_speed == SPEED_1000 && |
5101 | tp->link_config.active_duplex == DUPLEX_HALF) | |
f2096f94 MC |
5102 | tw32(MAC_TX_LENGTHS, val | |
5103 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 5104 | else |
f2096f94 MC |
5105 | tw32(MAC_TX_LENGTHS, val | |
5106 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 5107 | |
63c3a66f | 5108 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
5109 | if (netif_carrier_ok(tp->dev)) { |
5110 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 5111 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
5112 | } else { |
5113 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
5114 | } | |
5115 | } | |
5116 | ||
63c3a66f | 5117 | if (tg3_flag(tp, ASPM_WORKAROUND)) { |
f2096f94 | 5118 | val = tr32(PCIE_PWR_MGMT_THRESH); |
8ed5d97e MC |
5119 | if (!netif_carrier_ok(tp->dev)) |
5120 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
5121 | tp->pwrmgmt_thresh; | |
5122 | else | |
5123 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
5124 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
5125 | } | |
5126 | ||
1da177e4 LT |
5127 | return err; |
5128 | } | |
5129 | ||
66cfd1bd MC |
5130 | static inline int tg3_irq_sync(struct tg3 *tp) |
5131 | { | |
5132 | return tp->irq_sync; | |
5133 | } | |
5134 | ||
97bd8e49 MC |
5135 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
5136 | { | |
5137 | int i; | |
5138 | ||
5139 | dst = (u32 *)((u8 *)dst + off); | |
5140 | for (i = 0; i < len; i += sizeof(u32)) | |
5141 | *dst++ = tr32(off + i); | |
5142 | } | |
5143 | ||
5144 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
5145 | { | |
5146 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
5147 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
5148 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
5149 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
5150 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
5151 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
5152 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
5153 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
5154 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
5155 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
5156 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
5157 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
5158 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
5159 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
5160 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
5161 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
5162 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
5163 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
5164 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
5165 | ||
63c3a66f | 5166 | if (tg3_flag(tp, SUPPORT_MSIX)) |
97bd8e49 MC |
5167 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); |
5168 | ||
5169 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
5170 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
5171 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
5172 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
5173 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
5174 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
5175 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
5176 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
5177 | ||
63c3a66f | 5178 | if (!tg3_flag(tp, 5705_PLUS)) { |
97bd8e49 MC |
5179 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); |
5180 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
5181 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
5182 | } | |
5183 | ||
5184 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
5185 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
5186 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
5187 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
5188 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
5189 | ||
63c3a66f | 5190 | if (tg3_flag(tp, NVRAM)) |
97bd8e49 MC |
5191 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); |
5192 | } | |
5193 | ||
5194 | static void tg3_dump_state(struct tg3 *tp) | |
5195 | { | |
5196 | int i; | |
5197 | u32 *regs; | |
5198 | ||
5199 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
5200 | if (!regs) { | |
5201 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
5202 | return; | |
5203 | } | |
5204 | ||
63c3a66f | 5205 | if (tg3_flag(tp, PCI_EXPRESS)) { |
97bd8e49 MC |
5206 | /* Read up to but not including private PCI registers */ |
5207 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
5208 | regs[i / sizeof(u32)] = tr32(i); | |
5209 | } else | |
5210 | tg3_dump_legacy_regs(tp, regs); | |
5211 | ||
5212 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
5213 | if (!regs[i + 0] && !regs[i + 1] && | |
5214 | !regs[i + 2] && !regs[i + 3]) | |
5215 | continue; | |
5216 | ||
5217 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
5218 | i * 4, | |
5219 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
5220 | } | |
5221 | ||
5222 | kfree(regs); | |
5223 | ||
5224 | for (i = 0; i < tp->irq_cnt; i++) { | |
5225 | struct tg3_napi *tnapi = &tp->napi[i]; | |
5226 | ||
5227 | /* SW status block */ | |
5228 | netdev_err(tp->dev, | |
5229 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
5230 | i, | |
5231 | tnapi->hw_status->status, | |
5232 | tnapi->hw_status->status_tag, | |
5233 | tnapi->hw_status->rx_jumbo_consumer, | |
5234 | tnapi->hw_status->rx_consumer, | |
5235 | tnapi->hw_status->rx_mini_consumer, | |
5236 | tnapi->hw_status->idx[0].rx_producer, | |
5237 | tnapi->hw_status->idx[0].tx_consumer); | |
5238 | ||
5239 | netdev_err(tp->dev, | |
5240 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
5241 | i, | |
5242 | tnapi->last_tag, tnapi->last_irq_tag, | |
5243 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
5244 | tnapi->rx_rcb_ptr, | |
5245 | tnapi->prodring.rx_std_prod_idx, | |
5246 | tnapi->prodring.rx_std_cons_idx, | |
5247 | tnapi->prodring.rx_jmb_prod_idx, | |
5248 | tnapi->prodring.rx_jmb_cons_idx); | |
5249 | } | |
5250 | } | |
5251 | ||
df3e6548 MC |
5252 | /* This is called whenever we suspect that the system chipset is re- |
5253 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
5254 | * is bogus tx completions. We try to recover by setting the | |
5255 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
5256 | * in the workqueue. | |
5257 | */ | |
5258 | static void tg3_tx_recover(struct tg3 *tp) | |
5259 | { | |
63c3a66f | 5260 | BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || |
df3e6548 MC |
5261 | tp->write32_tx_mbox == tg3_write_indirect_mbox); |
5262 | ||
5129c3a3 MC |
5263 | netdev_warn(tp->dev, |
5264 | "The system may be re-ordering memory-mapped I/O " | |
5265 | "cycles to the network device, attempting to recover. " | |
5266 | "Please report the problem to the driver maintainer " | |
5267 | "and include system chipset information.\n"); | |
df3e6548 MC |
5268 | |
5269 | spin_lock(&tp->lock); | |
63c3a66f | 5270 | tg3_flag_set(tp, TX_RECOVERY_PENDING); |
df3e6548 MC |
5271 | spin_unlock(&tp->lock); |
5272 | } | |
5273 | ||
f3f3f27e | 5274 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 5275 | { |
f65aac16 MC |
5276 | /* Tell compiler to fetch tx indices from memory. */ |
5277 | barrier(); | |
f3f3f27e MC |
5278 | return tnapi->tx_pending - |
5279 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
5280 | } |
5281 | ||
1da177e4 LT |
5282 | /* Tigon3 never reports partial packet sends. So we do not |
5283 | * need special logic to handle SKBs that have not had all | |
5284 | * of their frags sent yet, like SunGEM does. | |
5285 | */ | |
17375d25 | 5286 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 5287 | { |
17375d25 | 5288 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 5289 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 5290 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
5291 | struct netdev_queue *txq; |
5292 | int index = tnapi - tp->napi; | |
298376d3 | 5293 | unsigned int pkts_compl = 0, bytes_compl = 0; |
fe5f5787 | 5294 | |
63c3a66f | 5295 | if (tg3_flag(tp, ENABLE_TSS)) |
fe5f5787 MC |
5296 | index--; |
5297 | ||
5298 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
5299 | |
5300 | while (sw_idx != hw_idx) { | |
df8944cf | 5301 | struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 5302 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
5303 | int i, tx_bug = 0; |
5304 | ||
5305 | if (unlikely(skb == NULL)) { | |
5306 | tg3_tx_recover(tp); | |
5307 | return; | |
5308 | } | |
1da177e4 | 5309 | |
f4188d8a | 5310 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 5311 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
5312 | skb_headlen(skb), |
5313 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
5314 | |
5315 | ri->skb = NULL; | |
5316 | ||
e01ee14d MC |
5317 | while (ri->fragmented) { |
5318 | ri->fragmented = false; | |
5319 | sw_idx = NEXT_TX(sw_idx); | |
5320 | ri = &tnapi->tx_buffers[sw_idx]; | |
5321 | } | |
5322 | ||
1da177e4 LT |
5323 | sw_idx = NEXT_TX(sw_idx); |
5324 | ||
5325 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 5326 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
5327 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
5328 | tx_bug = 1; | |
f4188d8a AD |
5329 | |
5330 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 5331 | dma_unmap_addr(ri, mapping), |
9e903e08 | 5332 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
f4188d8a | 5333 | PCI_DMA_TODEVICE); |
e01ee14d MC |
5334 | |
5335 | while (ri->fragmented) { | |
5336 | ri->fragmented = false; | |
5337 | sw_idx = NEXT_TX(sw_idx); | |
5338 | ri = &tnapi->tx_buffers[sw_idx]; | |
5339 | } | |
5340 | ||
1da177e4 LT |
5341 | sw_idx = NEXT_TX(sw_idx); |
5342 | } | |
5343 | ||
298376d3 TH |
5344 | pkts_compl++; |
5345 | bytes_compl += skb->len; | |
5346 | ||
f47c11ee | 5347 | dev_kfree_skb(skb); |
df3e6548 MC |
5348 | |
5349 | if (unlikely(tx_bug)) { | |
5350 | tg3_tx_recover(tp); | |
5351 | return; | |
5352 | } | |
1da177e4 LT |
5353 | } |
5354 | ||
298376d3 TH |
5355 | netdev_completed_queue(tp->dev, pkts_compl, bytes_compl); |
5356 | ||
f3f3f27e | 5357 | tnapi->tx_cons = sw_idx; |
1da177e4 | 5358 | |
1b2a7205 MC |
5359 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
5360 | * before checking for netif_queue_stopped(). Without the | |
5361 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
5362 | * will miss it and cause the queue to be stopped forever. | |
5363 | */ | |
5364 | smp_mb(); | |
5365 | ||
fe5f5787 | 5366 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 5367 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
5368 | __netif_tx_lock(txq, smp_processor_id()); |
5369 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 5370 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
5371 | netif_tx_wake_queue(txq); |
5372 | __netif_tx_unlock(txq); | |
51b91468 | 5373 | } |
1da177e4 LT |
5374 | } |
5375 | ||
9205fd9c | 5376 | static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
2b2cdb65 | 5377 | { |
9205fd9c | 5378 | if (!ri->data) |
2b2cdb65 MC |
5379 | return; |
5380 | ||
4e5e4f0d | 5381 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 | 5382 | map_sz, PCI_DMA_FROMDEVICE); |
9205fd9c ED |
5383 | kfree(ri->data); |
5384 | ri->data = NULL; | |
2b2cdb65 MC |
5385 | } |
5386 | ||
1da177e4 LT |
5387 | /* Returns size of skb allocated or < 0 on error. |
5388 | * | |
5389 | * We only need to fill in the address because the other members | |
5390 | * of the RX descriptor are invariant, see tg3_init_rings. | |
5391 | * | |
5392 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
5393 | * posting buffers we only dirty the first cache line of the RX | |
5394 | * descriptor (containing the address). Whereas for the RX status | |
5395 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
5396 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
5397 | */ | |
9205fd9c | 5398 | static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
a3896167 | 5399 | u32 opaque_key, u32 dest_idx_unmasked) |
1da177e4 LT |
5400 | { |
5401 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 5402 | struct ring_info *map; |
9205fd9c | 5403 | u8 *data; |
1da177e4 | 5404 | dma_addr_t mapping; |
9205fd9c | 5405 | int skb_size, data_size, dest_idx; |
1da177e4 | 5406 | |
1da177e4 LT |
5407 | switch (opaque_key) { |
5408 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 5409 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
5410 | desc = &tpr->rx_std[dest_idx]; |
5411 | map = &tpr->rx_std_buffers[dest_idx]; | |
9205fd9c | 5412 | data_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
5413 | break; |
5414 | ||
5415 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 5416 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 5417 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 5418 | map = &tpr->rx_jmb_buffers[dest_idx]; |
9205fd9c | 5419 | data_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
5420 | break; |
5421 | ||
5422 | default: | |
5423 | return -EINVAL; | |
855e1111 | 5424 | } |
1da177e4 LT |
5425 | |
5426 | /* Do not overwrite any of the map or rp information | |
5427 | * until we are sure we can commit to a new buffer. | |
5428 | * | |
5429 | * Callers depend upon this behavior and assume that | |
5430 | * we leave everything unchanged if we fail. | |
5431 | */ | |
9205fd9c ED |
5432 | skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + |
5433 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
5434 | data = kmalloc(skb_size, GFP_ATOMIC); | |
5435 | if (!data) | |
1da177e4 LT |
5436 | return -ENOMEM; |
5437 | ||
9205fd9c ED |
5438 | mapping = pci_map_single(tp->pdev, |
5439 | data + TG3_RX_OFFSET(tp), | |
5440 | data_size, | |
1da177e4 | 5441 | PCI_DMA_FROMDEVICE); |
a21771dd | 5442 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
9205fd9c | 5443 | kfree(data); |
a21771dd MC |
5444 | return -EIO; |
5445 | } | |
1da177e4 | 5446 | |
9205fd9c | 5447 | map->data = data; |
4e5e4f0d | 5448 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 5449 | |
1da177e4 LT |
5450 | desc->addr_hi = ((u64)mapping >> 32); |
5451 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
5452 | ||
9205fd9c | 5453 | return data_size; |
1da177e4 LT |
5454 | } |
5455 | ||
5456 | /* We only need to move over in the address because the other | |
5457 | * members of the RX descriptor are invariant. See notes above | |
9205fd9c | 5458 | * tg3_alloc_rx_data for full details. |
1da177e4 | 5459 | */ |
a3896167 MC |
5460 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
5461 | struct tg3_rx_prodring_set *dpr, | |
5462 | u32 opaque_key, int src_idx, | |
5463 | u32 dest_idx_unmasked) | |
1da177e4 | 5464 | { |
17375d25 | 5465 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
5466 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
5467 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 5468 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 5469 | int dest_idx; |
1da177e4 LT |
5470 | |
5471 | switch (opaque_key) { | |
5472 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 5473 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
5474 | dest_desc = &dpr->rx_std[dest_idx]; |
5475 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
5476 | src_desc = &spr->rx_std[src_idx]; | |
5477 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
5478 | break; |
5479 | ||
5480 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 5481 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
5482 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
5483 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
5484 | src_desc = &spr->rx_jmb[src_idx].std; | |
5485 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
5486 | break; |
5487 | ||
5488 | default: | |
5489 | return; | |
855e1111 | 5490 | } |
1da177e4 | 5491 | |
9205fd9c | 5492 | dest_map->data = src_map->data; |
4e5e4f0d FT |
5493 | dma_unmap_addr_set(dest_map, mapping, |
5494 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
5495 | dest_desc->addr_hi = src_desc->addr_hi; |
5496 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
5497 | |
5498 | /* Ensure that the update to the skb happens after the physical | |
5499 | * addresses have been transferred to the new BD location. | |
5500 | */ | |
5501 | smp_wmb(); | |
5502 | ||
9205fd9c | 5503 | src_map->data = NULL; |
1da177e4 LT |
5504 | } |
5505 | ||
1da177e4 LT |
5506 | /* The RX ring scheme is composed of multiple rings which post fresh |
5507 | * buffers to the chip, and one special ring the chip uses to report | |
5508 | * status back to the host. | |
5509 | * | |
5510 | * The special ring reports the status of received packets to the | |
5511 | * host. The chip does not write into the original descriptor the | |
5512 | * RX buffer was obtained from. The chip simply takes the original | |
5513 | * descriptor as provided by the host, updates the status and length | |
5514 | * field, then writes this into the next status ring entry. | |
5515 | * | |
5516 | * Each ring the host uses to post buffers to the chip is described | |
5517 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
5518 | * it is first placed into the on-chip ram. When the packet's length | |
5519 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
5520 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
5521 | * which is within the range of the new packet's length is chosen. | |
5522 | * | |
5523 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
5524 | * sense from a cache coherency perspective. If only the host writes | |
5525 | * to the buffer post rings, and only the chip writes to the rx status | |
5526 | * rings, then cache lines never move beyond shared-modified state. | |
5527 | * If both the host and chip were to write into the same ring, cache line | |
5528 | * eviction could occur since both entities want it in an exclusive state. | |
5529 | */ | |
17375d25 | 5530 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 5531 | { |
17375d25 | 5532 | struct tg3 *tp = tnapi->tp; |
f92905de | 5533 | u32 work_mask, rx_std_posted = 0; |
4361935a | 5534 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 5535 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 5536 | u16 hw_idx; |
1da177e4 | 5537 | int received; |
8fea32b9 | 5538 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 5539 | |
8d9d7cfc | 5540 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
5541 | /* |
5542 | * We need to order the read of hw_idx and the read of | |
5543 | * the opaque cookie. | |
5544 | */ | |
5545 | rmb(); | |
1da177e4 LT |
5546 | work_mask = 0; |
5547 | received = 0; | |
4361935a MC |
5548 | std_prod_idx = tpr->rx_std_prod_idx; |
5549 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 5550 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 5551 | struct ring_info *ri; |
72334482 | 5552 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
5553 | unsigned int len; |
5554 | struct sk_buff *skb; | |
5555 | dma_addr_t dma_addr; | |
5556 | u32 opaque_key, desc_idx, *post_ptr; | |
9205fd9c | 5557 | u8 *data; |
1da177e4 LT |
5558 | |
5559 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
5560 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
5561 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 5562 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 5563 | dma_addr = dma_unmap_addr(ri, mapping); |
9205fd9c | 5564 | data = ri->data; |
4361935a | 5565 | post_ptr = &std_prod_idx; |
f92905de | 5566 | rx_std_posted++; |
1da177e4 | 5567 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 5568 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 5569 | dma_addr = dma_unmap_addr(ri, mapping); |
9205fd9c | 5570 | data = ri->data; |
4361935a | 5571 | post_ptr = &jmb_prod_idx; |
21f581a5 | 5572 | } else |
1da177e4 | 5573 | goto next_pkt_nopost; |
1da177e4 LT |
5574 | |
5575 | work_mask |= opaque_key; | |
5576 | ||
5577 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
5578 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
5579 | drop_it: | |
a3896167 | 5580 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5581 | desc_idx, *post_ptr); |
5582 | drop_it_no_recycle: | |
5583 | /* Other statistics kept track of by card. */ | |
b0057c51 | 5584 | tp->rx_dropped++; |
1da177e4 LT |
5585 | goto next_pkt; |
5586 | } | |
5587 | ||
9205fd9c | 5588 | prefetch(data + TG3_RX_OFFSET(tp)); |
ad829268 MC |
5589 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
5590 | ETH_FCS_LEN; | |
1da177e4 | 5591 | |
d2757fc4 | 5592 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 LT |
5593 | int skb_size; |
5594 | ||
9205fd9c | 5595 | skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, |
afc081f8 | 5596 | *post_ptr); |
1da177e4 LT |
5597 | if (skb_size < 0) |
5598 | goto drop_it; | |
5599 | ||
287be12e | 5600 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
5601 | PCI_DMA_FROMDEVICE); |
5602 | ||
9205fd9c ED |
5603 | skb = build_skb(data); |
5604 | if (!skb) { | |
5605 | kfree(data); | |
5606 | goto drop_it_no_recycle; | |
5607 | } | |
5608 | skb_reserve(skb, TG3_RX_OFFSET(tp)); | |
5609 | /* Ensure that the update to the data happens | |
61e800cf MC |
5610 | * after the usage of the old DMA mapping. |
5611 | */ | |
5612 | smp_wmb(); | |
5613 | ||
9205fd9c | 5614 | ri->data = NULL; |
61e800cf | 5615 | |
1da177e4 | 5616 | } else { |
a3896167 | 5617 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5618 | desc_idx, *post_ptr); |
5619 | ||
9205fd9c ED |
5620 | skb = netdev_alloc_skb(tp->dev, |
5621 | len + TG3_RAW_IP_ALIGN); | |
5622 | if (skb == NULL) | |
1da177e4 LT |
5623 | goto drop_it_no_recycle; |
5624 | ||
9205fd9c | 5625 | skb_reserve(skb, TG3_RAW_IP_ALIGN); |
1da177e4 | 5626 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
9205fd9c ED |
5627 | memcpy(skb->data, |
5628 | data + TG3_RX_OFFSET(tp), | |
5629 | len); | |
1da177e4 | 5630 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
5631 | } |
5632 | ||
9205fd9c | 5633 | skb_put(skb, len); |
dc668910 | 5634 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
1da177e4 LT |
5635 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
5636 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
5637 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
5638 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5639 | else | |
bc8acf2c | 5640 | skb_checksum_none_assert(skb); |
1da177e4 LT |
5641 | |
5642 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
5643 | |
5644 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
5645 | skb->protocol != htons(ETH_P_8021Q)) { | |
5646 | dev_kfree_skb(skb); | |
b0057c51 | 5647 | goto drop_it_no_recycle; |
f7b493e0 MC |
5648 | } |
5649 | ||
9dc7a113 | 5650 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
5651 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
5652 | __vlan_hwaccel_put_tag(skb, | |
5653 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 5654 | |
bf933c80 | 5655 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 5656 | |
1da177e4 LT |
5657 | received++; |
5658 | budget--; | |
5659 | ||
5660 | next_pkt: | |
5661 | (*post_ptr)++; | |
f92905de MC |
5662 | |
5663 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
5664 | tpr->rx_std_prod_idx = std_prod_idx & |
5665 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
5666 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5667 | tpr->rx_std_prod_idx); | |
f92905de MC |
5668 | work_mask &= ~RXD_OPAQUE_RING_STD; |
5669 | rx_std_posted = 0; | |
5670 | } | |
1da177e4 | 5671 | next_pkt_nopost: |
483ba50b | 5672 | sw_idx++; |
7cb32cf2 | 5673 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
5674 | |
5675 | /* Refresh hw_idx to see if there is new work */ | |
5676 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 5677 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
5678 | rmb(); |
5679 | } | |
1da177e4 LT |
5680 | } |
5681 | ||
5682 | /* ACK the status ring. */ | |
72334482 MC |
5683 | tnapi->rx_rcb_ptr = sw_idx; |
5684 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
5685 | |
5686 | /* Refill RX ring(s). */ | |
63c3a66f | 5687 | if (!tg3_flag(tp, ENABLE_RSS)) { |
b196c7e4 | 5688 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
5689 | tpr->rx_std_prod_idx = std_prod_idx & |
5690 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5691 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5692 | tpr->rx_std_prod_idx); | |
5693 | } | |
5694 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
5695 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
5696 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
5697 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
5698 | tpr->rx_jmb_prod_idx); | |
5699 | } | |
5700 | mmiowb(); | |
5701 | } else if (work_mask) { | |
5702 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
5703 | * updated before the producer indices can be updated. | |
5704 | */ | |
5705 | smp_wmb(); | |
5706 | ||
2c49a44d MC |
5707 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
5708 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 5709 | |
e4af1af9 MC |
5710 | if (tnapi != &tp->napi[1]) |
5711 | napi_schedule(&tp->napi[1].napi); | |
1da177e4 | 5712 | } |
1da177e4 LT |
5713 | |
5714 | return received; | |
5715 | } | |
5716 | ||
35f2d7d0 | 5717 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 5718 | { |
1da177e4 | 5719 | /* handle link change and other phy events */ |
63c3a66f | 5720 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
35f2d7d0 MC |
5721 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
5722 | ||
1da177e4 LT |
5723 | if (sblk->status & SD_STATUS_LINK_CHG) { |
5724 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 5725 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 5726 | spin_lock(&tp->lock); |
63c3a66f | 5727 | if (tg3_flag(tp, USE_PHYLIB)) { |
dd477003 MC |
5728 | tw32_f(MAC_STATUS, |
5729 | (MAC_STATUS_SYNC_CHANGED | | |
5730 | MAC_STATUS_CFG_CHANGED | | |
5731 | MAC_STATUS_MI_COMPLETION | | |
5732 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5733 | udelay(40); | |
5734 | } else | |
5735 | tg3_setup_phy(tp, 0); | |
f47c11ee | 5736 | spin_unlock(&tp->lock); |
1da177e4 LT |
5737 | } |
5738 | } | |
35f2d7d0 MC |
5739 | } |
5740 | ||
f89f38b8 MC |
5741 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
5742 | struct tg3_rx_prodring_set *dpr, | |
5743 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
5744 | { |
5745 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 5746 | int i, err = 0; |
b196c7e4 MC |
5747 | |
5748 | while (1) { | |
5749 | src_prod_idx = spr->rx_std_prod_idx; | |
5750 | ||
5751 | /* Make sure updates to the rx_std_buffers[] entries and the | |
5752 | * standard producer index are seen in the correct order. | |
5753 | */ | |
5754 | smp_rmb(); | |
5755 | ||
5756 | if (spr->rx_std_cons_idx == src_prod_idx) | |
5757 | break; | |
5758 | ||
5759 | if (spr->rx_std_cons_idx < src_prod_idx) | |
5760 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
5761 | else | |
2c49a44d MC |
5762 | cpycnt = tp->rx_std_ring_mask + 1 - |
5763 | spr->rx_std_cons_idx; | |
b196c7e4 | 5764 | |
2c49a44d MC |
5765 | cpycnt = min(cpycnt, |
5766 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
5767 | |
5768 | si = spr->rx_std_cons_idx; | |
5769 | di = dpr->rx_std_prod_idx; | |
5770 | ||
e92967bf | 5771 | for (i = di; i < di + cpycnt; i++) { |
9205fd9c | 5772 | if (dpr->rx_std_buffers[i].data) { |
e92967bf | 5773 | cpycnt = i - di; |
f89f38b8 | 5774 | err = -ENOSPC; |
e92967bf MC |
5775 | break; |
5776 | } | |
5777 | } | |
5778 | ||
5779 | if (!cpycnt) | |
5780 | break; | |
5781 | ||
5782 | /* Ensure that updates to the rx_std_buffers ring and the | |
5783 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5784 | * ordered correctly WRT the skb check above. | |
5785 | */ | |
5786 | smp_rmb(); | |
5787 | ||
b196c7e4 MC |
5788 | memcpy(&dpr->rx_std_buffers[di], |
5789 | &spr->rx_std_buffers[si], | |
5790 | cpycnt * sizeof(struct ring_info)); | |
5791 | ||
5792 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5793 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5794 | sbd = &spr->rx_std[si]; | |
5795 | dbd = &dpr->rx_std[di]; | |
5796 | dbd->addr_hi = sbd->addr_hi; | |
5797 | dbd->addr_lo = sbd->addr_lo; | |
5798 | } | |
5799 | ||
2c49a44d MC |
5800 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
5801 | tp->rx_std_ring_mask; | |
5802 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
5803 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5804 | } |
5805 | ||
5806 | while (1) { | |
5807 | src_prod_idx = spr->rx_jmb_prod_idx; | |
5808 | ||
5809 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
5810 | * the jumbo producer index are seen in the correct order. | |
5811 | */ | |
5812 | smp_rmb(); | |
5813 | ||
5814 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
5815 | break; | |
5816 | ||
5817 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
5818 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
5819 | else | |
2c49a44d MC |
5820 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
5821 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
5822 | |
5823 | cpycnt = min(cpycnt, | |
2c49a44d | 5824 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
5825 | |
5826 | si = spr->rx_jmb_cons_idx; | |
5827 | di = dpr->rx_jmb_prod_idx; | |
5828 | ||
e92967bf | 5829 | for (i = di; i < di + cpycnt; i++) { |
9205fd9c | 5830 | if (dpr->rx_jmb_buffers[i].data) { |
e92967bf | 5831 | cpycnt = i - di; |
f89f38b8 | 5832 | err = -ENOSPC; |
e92967bf MC |
5833 | break; |
5834 | } | |
5835 | } | |
5836 | ||
5837 | if (!cpycnt) | |
5838 | break; | |
5839 | ||
5840 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
5841 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5842 | * ordered correctly WRT the skb check above. | |
5843 | */ | |
5844 | smp_rmb(); | |
5845 | ||
b196c7e4 MC |
5846 | memcpy(&dpr->rx_jmb_buffers[di], |
5847 | &spr->rx_jmb_buffers[si], | |
5848 | cpycnt * sizeof(struct ring_info)); | |
5849 | ||
5850 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5851 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5852 | sbd = &spr->rx_jmb[si].std; | |
5853 | dbd = &dpr->rx_jmb[di].std; | |
5854 | dbd->addr_hi = sbd->addr_hi; | |
5855 | dbd->addr_lo = sbd->addr_lo; | |
5856 | } | |
5857 | ||
2c49a44d MC |
5858 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
5859 | tp->rx_jmb_ring_mask; | |
5860 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
5861 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 5862 | } |
f89f38b8 MC |
5863 | |
5864 | return err; | |
b196c7e4 MC |
5865 | } |
5866 | ||
35f2d7d0 MC |
5867 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
5868 | { | |
5869 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
5870 | |
5871 | /* run TX completion thread */ | |
f3f3f27e | 5872 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 5873 | tg3_tx(tnapi); |
63c3a66f | 5874 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
4fd7ab59 | 5875 | return work_done; |
1da177e4 LT |
5876 | } |
5877 | ||
1da177e4 LT |
5878 | /* run RX thread, within the bounds set by NAPI. |
5879 | * All RX "locking" is done by ensuring outside | |
bea3348e | 5880 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 5881 | */ |
8d9d7cfc | 5882 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 5883 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 5884 | |
63c3a66f | 5885 | if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 5886 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 5887 | int i, err = 0; |
e4af1af9 MC |
5888 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
5889 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 5890 | |
e4af1af9 | 5891 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 | 5892 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 5893 | &tp->napi[i].prodring); |
b196c7e4 MC |
5894 | |
5895 | wmb(); | |
5896 | ||
e4af1af9 MC |
5897 | if (std_prod_idx != dpr->rx_std_prod_idx) |
5898 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5899 | dpr->rx_std_prod_idx); | |
b196c7e4 | 5900 | |
e4af1af9 MC |
5901 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
5902 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5903 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
5904 | |
5905 | mmiowb(); | |
f89f38b8 MC |
5906 | |
5907 | if (err) | |
5908 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
5909 | } |
5910 | ||
6f535763 DM |
5911 | return work_done; |
5912 | } | |
5913 | ||
db219973 MC |
5914 | static inline void tg3_reset_task_schedule(struct tg3 *tp) |
5915 | { | |
5916 | if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) | |
5917 | schedule_work(&tp->reset_task); | |
5918 | } | |
5919 | ||
5920 | static inline void tg3_reset_task_cancel(struct tg3 *tp) | |
5921 | { | |
5922 | cancel_work_sync(&tp->reset_task); | |
5923 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
5924 | } | |
5925 | ||
35f2d7d0 MC |
5926 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
5927 | { | |
5928 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5929 | struct tg3 *tp = tnapi->tp; | |
5930 | int work_done = 0; | |
5931 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5932 | ||
5933 | while (1) { | |
5934 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5935 | ||
63c3a66f | 5936 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
35f2d7d0 MC |
5937 | goto tx_recovery; |
5938 | ||
5939 | if (unlikely(work_done >= budget)) | |
5940 | break; | |
5941 | ||
c6cdf436 | 5942 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
5943 | * to tell the hw how much work has been processed, |
5944 | * so we must read it before checking for more work. | |
5945 | */ | |
5946 | tnapi->last_tag = sblk->status_tag; | |
5947 | tnapi->last_irq_tag = tnapi->last_tag; | |
5948 | rmb(); | |
5949 | ||
5950 | /* check for RX/TX work to do */ | |
6d40db7b MC |
5951 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
5952 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
35f2d7d0 MC |
5953 | napi_complete(napi); |
5954 | /* Reenable interrupts. */ | |
5955 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5956 | mmiowb(); | |
5957 | break; | |
5958 | } | |
5959 | } | |
5960 | ||
5961 | return work_done; | |
5962 | ||
5963 | tx_recovery: | |
5964 | /* work_done is guaranteed to be less than budget. */ | |
5965 | napi_complete(napi); | |
db219973 | 5966 | tg3_reset_task_schedule(tp); |
35f2d7d0 MC |
5967 | return work_done; |
5968 | } | |
5969 | ||
e64de4e6 MC |
5970 | static void tg3_process_error(struct tg3 *tp) |
5971 | { | |
5972 | u32 val; | |
5973 | bool real_error = false; | |
5974 | ||
63c3a66f | 5975 | if (tg3_flag(tp, ERROR_PROCESSED)) |
e64de4e6 MC |
5976 | return; |
5977 | ||
5978 | /* Check Flow Attention register */ | |
5979 | val = tr32(HOSTCC_FLOW_ATTN); | |
5980 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
5981 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
5982 | real_error = true; | |
5983 | } | |
5984 | ||
5985 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
5986 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
5987 | real_error = true; | |
5988 | } | |
5989 | ||
5990 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
5991 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
5992 | real_error = true; | |
5993 | } | |
5994 | ||
5995 | if (!real_error) | |
5996 | return; | |
5997 | ||
5998 | tg3_dump_state(tp); | |
5999 | ||
63c3a66f | 6000 | tg3_flag_set(tp, ERROR_PROCESSED); |
db219973 | 6001 | tg3_reset_task_schedule(tp); |
e64de4e6 MC |
6002 | } |
6003 | ||
6f535763 DM |
6004 | static int tg3_poll(struct napi_struct *napi, int budget) |
6005 | { | |
8ef0442f MC |
6006 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
6007 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 6008 | int work_done = 0; |
898a56f8 | 6009 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
6010 | |
6011 | while (1) { | |
e64de4e6 MC |
6012 | if (sblk->status & SD_STATUS_ERROR) |
6013 | tg3_process_error(tp); | |
6014 | ||
35f2d7d0 MC |
6015 | tg3_poll_link(tp); |
6016 | ||
17375d25 | 6017 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 | 6018 | |
63c3a66f | 6019 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
6f535763 DM |
6020 | goto tx_recovery; |
6021 | ||
6022 | if (unlikely(work_done >= budget)) | |
6023 | break; | |
6024 | ||
63c3a66f | 6025 | if (tg3_flag(tp, TAGGED_STATUS)) { |
17375d25 | 6026 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
6027 | * to tell the hw how much work has been processed, |
6028 | * so we must read it before checking for more work. | |
6029 | */ | |
898a56f8 MC |
6030 | tnapi->last_tag = sblk->status_tag; |
6031 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
6032 | rmb(); |
6033 | } else | |
6034 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 6035 | |
17375d25 | 6036 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 6037 | napi_complete(napi); |
17375d25 | 6038 | tg3_int_reenable(tnapi); |
6f535763 DM |
6039 | break; |
6040 | } | |
1da177e4 LT |
6041 | } |
6042 | ||
bea3348e | 6043 | return work_done; |
6f535763 DM |
6044 | |
6045 | tx_recovery: | |
4fd7ab59 | 6046 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 6047 | napi_complete(napi); |
db219973 | 6048 | tg3_reset_task_schedule(tp); |
4fd7ab59 | 6049 | return work_done; |
1da177e4 LT |
6050 | } |
6051 | ||
66cfd1bd MC |
6052 | static void tg3_napi_disable(struct tg3 *tp) |
6053 | { | |
6054 | int i; | |
6055 | ||
6056 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
6057 | napi_disable(&tp->napi[i].napi); | |
6058 | } | |
6059 | ||
6060 | static void tg3_napi_enable(struct tg3 *tp) | |
6061 | { | |
6062 | int i; | |
6063 | ||
6064 | for (i = 0; i < tp->irq_cnt; i++) | |
6065 | napi_enable(&tp->napi[i].napi); | |
6066 | } | |
6067 | ||
6068 | static void tg3_napi_init(struct tg3 *tp) | |
6069 | { | |
6070 | int i; | |
6071 | ||
6072 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
6073 | for (i = 1; i < tp->irq_cnt; i++) | |
6074 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
6075 | } | |
6076 | ||
6077 | static void tg3_napi_fini(struct tg3 *tp) | |
6078 | { | |
6079 | int i; | |
6080 | ||
6081 | for (i = 0; i < tp->irq_cnt; i++) | |
6082 | netif_napi_del(&tp->napi[i].napi); | |
6083 | } | |
6084 | ||
6085 | static inline void tg3_netif_stop(struct tg3 *tp) | |
6086 | { | |
6087 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
6088 | tg3_napi_disable(tp); | |
6089 | netif_tx_disable(tp->dev); | |
6090 | } | |
6091 | ||
6092 | static inline void tg3_netif_start(struct tg3 *tp) | |
6093 | { | |
6094 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
6095 | * appropriate so long as all callers are assured to | |
6096 | * have free tx slots (such as after tg3_init_hw) | |
6097 | */ | |
6098 | netif_tx_wake_all_queues(tp->dev); | |
6099 | ||
6100 | tg3_napi_enable(tp); | |
6101 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
6102 | tg3_enable_ints(tp); | |
6103 | } | |
6104 | ||
f47c11ee DM |
6105 | static void tg3_irq_quiesce(struct tg3 *tp) |
6106 | { | |
4f125f42 MC |
6107 | int i; |
6108 | ||
f47c11ee DM |
6109 | BUG_ON(tp->irq_sync); |
6110 | ||
6111 | tp->irq_sync = 1; | |
6112 | smp_mb(); | |
6113 | ||
4f125f42 MC |
6114 | for (i = 0; i < tp->irq_cnt; i++) |
6115 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
6116 | } |
6117 | ||
f47c11ee DM |
6118 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
6119 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
6120 | * with as well. Most of the time, this is not necessary except when | |
6121 | * shutting down the device. | |
6122 | */ | |
6123 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
6124 | { | |
46966545 | 6125 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
6126 | if (irq_sync) |
6127 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
6128 | } |
6129 | ||
6130 | static inline void tg3_full_unlock(struct tg3 *tp) | |
6131 | { | |
f47c11ee DM |
6132 | spin_unlock_bh(&tp->lock); |
6133 | } | |
6134 | ||
fcfa0a32 MC |
6135 | /* One-shot MSI handler - Chip automatically disables interrupt |
6136 | * after sending MSI so driver doesn't have to do it. | |
6137 | */ | |
7d12e780 | 6138 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 6139 | { |
09943a18 MC |
6140 | struct tg3_napi *tnapi = dev_id; |
6141 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 6142 | |
898a56f8 | 6143 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
6144 | if (tnapi->rx_rcb) |
6145 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
6146 | |
6147 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 6148 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
6149 | |
6150 | return IRQ_HANDLED; | |
6151 | } | |
6152 | ||
88b06bc2 MC |
6153 | /* MSI ISR - No need to check for interrupt sharing and no need to |
6154 | * flush status block and interrupt mailbox. PCI ordering rules | |
6155 | * guarantee that MSI will arrive after the status block. | |
6156 | */ | |
7d12e780 | 6157 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 6158 | { |
09943a18 MC |
6159 | struct tg3_napi *tnapi = dev_id; |
6160 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 6161 | |
898a56f8 | 6162 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
6163 | if (tnapi->rx_rcb) |
6164 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 6165 | /* |
fac9b83e | 6166 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 6167 | * chip-internal interrupt pending events. |
fac9b83e | 6168 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
6169 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
6170 | * event coalescing. | |
6171 | */ | |
5b39de91 | 6172 | tw32_mailbox(tnapi->int_mbox, 0x00000001); |
61487480 | 6173 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 6174 | napi_schedule(&tnapi->napi); |
61487480 | 6175 | |
88b06bc2 MC |
6176 | return IRQ_RETVAL(1); |
6177 | } | |
6178 | ||
7d12e780 | 6179 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 6180 | { |
09943a18 MC |
6181 | struct tg3_napi *tnapi = dev_id; |
6182 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6183 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
6184 | unsigned int handled = 1; |
6185 | ||
1da177e4 LT |
6186 | /* In INTx mode, it is possible for the interrupt to arrive at |
6187 | * the CPU before the status block posted prior to the interrupt. | |
6188 | * Reading the PCI State register will confirm whether the | |
6189 | * interrupt is ours and will flush the status block. | |
6190 | */ | |
d18edcb2 | 6191 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
63c3a66f | 6192 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
6193 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
6194 | handled = 0; | |
f47c11ee | 6195 | goto out; |
fac9b83e | 6196 | } |
d18edcb2 MC |
6197 | } |
6198 | ||
6199 | /* | |
6200 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
6201 | * chip-internal interrupt pending events. | |
6202 | * Writing non-zero to intr-mbox-0 additional tells the | |
6203 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
6204 | * event coalescing. | |
c04cb347 MC |
6205 | * |
6206 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
6207 | * spurious interrupts. The flush impacts performance but | |
6208 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 6209 | */ |
c04cb347 | 6210 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
6211 | if (tg3_irq_sync(tp)) |
6212 | goto out; | |
6213 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 6214 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 6215 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 6216 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
6217 | } else { |
6218 | /* No work, shared interrupt perhaps? re-enable | |
6219 | * interrupts, and flush that PCI write | |
6220 | */ | |
6221 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
6222 | 0x00000000); | |
fac9b83e | 6223 | } |
f47c11ee | 6224 | out: |
fac9b83e DM |
6225 | return IRQ_RETVAL(handled); |
6226 | } | |
6227 | ||
7d12e780 | 6228 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 6229 | { |
09943a18 MC |
6230 | struct tg3_napi *tnapi = dev_id; |
6231 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6232 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
6233 | unsigned int handled = 1; |
6234 | ||
fac9b83e DM |
6235 | /* In INTx mode, it is possible for the interrupt to arrive at |
6236 | * the CPU before the status block posted prior to the interrupt. | |
6237 | * Reading the PCI State register will confirm whether the | |
6238 | * interrupt is ours and will flush the status block. | |
6239 | */ | |
898a56f8 | 6240 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
63c3a66f | 6241 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
6242 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
6243 | handled = 0; | |
f47c11ee | 6244 | goto out; |
1da177e4 | 6245 | } |
d18edcb2 MC |
6246 | } |
6247 | ||
6248 | /* | |
6249 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
6250 | * chip-internal interrupt pending events. | |
6251 | * writing non-zero to intr-mbox-0 additional tells the | |
6252 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
6253 | * event coalescing. | |
c04cb347 MC |
6254 | * |
6255 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
6256 | * spurious interrupts. The flush impacts performance but | |
6257 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 6258 | */ |
c04cb347 | 6259 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
6260 | |
6261 | /* | |
6262 | * In a shared interrupt configuration, sometimes other devices' | |
6263 | * interrupts will scream. We record the current status tag here | |
6264 | * so that the above check can report that the screaming interrupts | |
6265 | * are unhandled. Eventually they will be silenced. | |
6266 | */ | |
898a56f8 | 6267 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 6268 | |
d18edcb2 MC |
6269 | if (tg3_irq_sync(tp)) |
6270 | goto out; | |
624f8e50 | 6271 | |
72334482 | 6272 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 6273 | |
09943a18 | 6274 | napi_schedule(&tnapi->napi); |
624f8e50 | 6275 | |
f47c11ee | 6276 | out: |
1da177e4 LT |
6277 | return IRQ_RETVAL(handled); |
6278 | } | |
6279 | ||
7938109f | 6280 | /* ISR for interrupt test */ |
7d12e780 | 6281 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 6282 | { |
09943a18 MC |
6283 | struct tg3_napi *tnapi = dev_id; |
6284 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6285 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 6286 | |
f9804ddb MC |
6287 | if ((sblk->status & SD_STATUS_UPDATED) || |
6288 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 6289 | tg3_disable_ints(tp); |
7938109f MC |
6290 | return IRQ_RETVAL(1); |
6291 | } | |
6292 | return IRQ_RETVAL(0); | |
6293 | } | |
6294 | ||
8e7a22e3 | 6295 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 6296 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 6297 | |
b9ec6c1b MC |
6298 | /* Restart hardware after configuration changes, self-test, etc. |
6299 | * Invoked with tp->lock held. | |
6300 | */ | |
6301 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
6302 | __releases(tp->lock) |
6303 | __acquires(tp->lock) | |
b9ec6c1b MC |
6304 | { |
6305 | int err; | |
6306 | ||
6307 | err = tg3_init_hw(tp, reset_phy); | |
6308 | if (err) { | |
5129c3a3 MC |
6309 | netdev_err(tp->dev, |
6310 | "Failed to re-initialize device, aborting\n"); | |
b9ec6c1b MC |
6311 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
6312 | tg3_full_unlock(tp); | |
6313 | del_timer_sync(&tp->timer); | |
6314 | tp->irq_sync = 0; | |
fed97810 | 6315 | tg3_napi_enable(tp); |
b9ec6c1b MC |
6316 | dev_close(tp->dev); |
6317 | tg3_full_lock(tp, 0); | |
6318 | } | |
6319 | return err; | |
6320 | } | |
6321 | ||
1da177e4 LT |
6322 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6323 | static void tg3_poll_controller(struct net_device *dev) | |
6324 | { | |
4f125f42 | 6325 | int i; |
88b06bc2 MC |
6326 | struct tg3 *tp = netdev_priv(dev); |
6327 | ||
4f125f42 | 6328 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 6329 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
6330 | } |
6331 | #endif | |
6332 | ||
c4028958 | 6333 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 6334 | { |
c4028958 | 6335 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 6336 | int err; |
1da177e4 | 6337 | |
7faa006f | 6338 | tg3_full_lock(tp, 0); |
7faa006f MC |
6339 | |
6340 | if (!netif_running(tp->dev)) { | |
db219973 | 6341 | tg3_flag_clear(tp, RESET_TASK_PENDING); |
7faa006f MC |
6342 | tg3_full_unlock(tp); |
6343 | return; | |
6344 | } | |
6345 | ||
6346 | tg3_full_unlock(tp); | |
6347 | ||
b02fd9e3 MC |
6348 | tg3_phy_stop(tp); |
6349 | ||
1da177e4 LT |
6350 | tg3_netif_stop(tp); |
6351 | ||
f47c11ee | 6352 | tg3_full_lock(tp, 1); |
1da177e4 | 6353 | |
63c3a66f | 6354 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { |
df3e6548 MC |
6355 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
6356 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
63c3a66f JP |
6357 | tg3_flag_set(tp, MBOX_WRITE_REORDER); |
6358 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | |
df3e6548 MC |
6359 | } |
6360 | ||
944d980e | 6361 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
6362 | err = tg3_init_hw(tp, 1); |
6363 | if (err) | |
b9ec6c1b | 6364 | goto out; |
1da177e4 LT |
6365 | |
6366 | tg3_netif_start(tp); | |
6367 | ||
b9ec6c1b | 6368 | out: |
7faa006f | 6369 | tg3_full_unlock(tp); |
b02fd9e3 MC |
6370 | |
6371 | if (!err) | |
6372 | tg3_phy_start(tp); | |
db219973 MC |
6373 | |
6374 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
1da177e4 LT |
6375 | } |
6376 | ||
6377 | static void tg3_tx_timeout(struct net_device *dev) | |
6378 | { | |
6379 | struct tg3 *tp = netdev_priv(dev); | |
6380 | ||
b0408751 | 6381 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 6382 | netdev_err(dev, "transmit timed out, resetting\n"); |
97bd8e49 | 6383 | tg3_dump_state(tp); |
b0408751 | 6384 | } |
1da177e4 | 6385 | |
db219973 | 6386 | tg3_reset_task_schedule(tp); |
1da177e4 LT |
6387 | } |
6388 | ||
c58ec932 MC |
6389 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
6390 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
6391 | { | |
6392 | u32 base = (u32) mapping & 0xffffffff; | |
6393 | ||
807540ba | 6394 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
6395 | } |
6396 | ||
72f2afb8 MC |
6397 | /* Test for DMA addresses > 40-bit */ |
6398 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
6399 | int len) | |
6400 | { | |
6401 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
63c3a66f | 6402 | if (tg3_flag(tp, 40BIT_DMA_BUG)) |
807540ba | 6403 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
6404 | return 0; |
6405 | #else | |
6406 | return 0; | |
6407 | #endif | |
6408 | } | |
6409 | ||
d1a3b737 | 6410 | static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd, |
92cd3a17 MC |
6411 | dma_addr_t mapping, u32 len, u32 flags, |
6412 | u32 mss, u32 vlan) | |
2ffcc981 | 6413 | { |
92cd3a17 MC |
6414 | txbd->addr_hi = ((u64) mapping >> 32); |
6415 | txbd->addr_lo = ((u64) mapping & 0xffffffff); | |
6416 | txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); | |
6417 | txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); | |
2ffcc981 | 6418 | } |
1da177e4 | 6419 | |
84b67b27 | 6420 | static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget, |
d1a3b737 MC |
6421 | dma_addr_t map, u32 len, u32 flags, |
6422 | u32 mss, u32 vlan) | |
6423 | { | |
6424 | struct tg3 *tp = tnapi->tp; | |
6425 | bool hwbug = false; | |
6426 | ||
6427 | if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) | |
6428 | hwbug = 1; | |
6429 | ||
6430 | if (tg3_4g_overflow_test(map, len)) | |
6431 | hwbug = 1; | |
6432 | ||
6433 | if (tg3_40bit_overflow_test(tp, map, len)) | |
6434 | hwbug = 1; | |
6435 | ||
a4cb428d | 6436 | if (tp->dma_limit) { |
b9e45482 | 6437 | u32 prvidx = *entry; |
e31aa987 | 6438 | u32 tmp_flag = flags & ~TXD_FLAG_END; |
a4cb428d MC |
6439 | while (len > tp->dma_limit && *budget) { |
6440 | u32 frag_len = tp->dma_limit; | |
6441 | len -= tp->dma_limit; | |
e31aa987 | 6442 | |
b9e45482 MC |
6443 | /* Avoid the 8byte DMA problem */ |
6444 | if (len <= 8) { | |
a4cb428d MC |
6445 | len += tp->dma_limit / 2; |
6446 | frag_len = tp->dma_limit / 2; | |
e31aa987 MC |
6447 | } |
6448 | ||
b9e45482 MC |
6449 | tnapi->tx_buffers[*entry].fragmented = true; |
6450 | ||
6451 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
6452 | frag_len, tmp_flag, mss, vlan); | |
6453 | *budget -= 1; | |
6454 | prvidx = *entry; | |
6455 | *entry = NEXT_TX(*entry); | |
6456 | ||
e31aa987 MC |
6457 | map += frag_len; |
6458 | } | |
6459 | ||
6460 | if (len) { | |
6461 | if (*budget) { | |
6462 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
6463 | len, flags, mss, vlan); | |
b9e45482 | 6464 | *budget -= 1; |
e31aa987 MC |
6465 | *entry = NEXT_TX(*entry); |
6466 | } else { | |
6467 | hwbug = 1; | |
b9e45482 | 6468 | tnapi->tx_buffers[prvidx].fragmented = false; |
e31aa987 MC |
6469 | } |
6470 | } | |
6471 | } else { | |
84b67b27 MC |
6472 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, |
6473 | len, flags, mss, vlan); | |
e31aa987 MC |
6474 | *entry = NEXT_TX(*entry); |
6475 | } | |
d1a3b737 MC |
6476 | |
6477 | return hwbug; | |
6478 | } | |
6479 | ||
0d681b27 | 6480 | static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last) |
432aa7ed MC |
6481 | { |
6482 | int i; | |
0d681b27 | 6483 | struct sk_buff *skb; |
df8944cf | 6484 | struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; |
432aa7ed | 6485 | |
0d681b27 MC |
6486 | skb = txb->skb; |
6487 | txb->skb = NULL; | |
6488 | ||
432aa7ed MC |
6489 | pci_unmap_single(tnapi->tp->pdev, |
6490 | dma_unmap_addr(txb, mapping), | |
6491 | skb_headlen(skb), | |
6492 | PCI_DMA_TODEVICE); | |
e01ee14d MC |
6493 | |
6494 | while (txb->fragmented) { | |
6495 | txb->fragmented = false; | |
6496 | entry = NEXT_TX(entry); | |
6497 | txb = &tnapi->tx_buffers[entry]; | |
6498 | } | |
6499 | ||
ba1142e4 | 6500 | for (i = 0; i <= last; i++) { |
9e903e08 | 6501 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
432aa7ed MC |
6502 | |
6503 | entry = NEXT_TX(entry); | |
6504 | txb = &tnapi->tx_buffers[entry]; | |
6505 | ||
6506 | pci_unmap_page(tnapi->tp->pdev, | |
6507 | dma_unmap_addr(txb, mapping), | |
9e903e08 | 6508 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
e01ee14d MC |
6509 | |
6510 | while (txb->fragmented) { | |
6511 | txb->fragmented = false; | |
6512 | entry = NEXT_TX(entry); | |
6513 | txb = &tnapi->tx_buffers[entry]; | |
6514 | } | |
432aa7ed MC |
6515 | } |
6516 | } | |
6517 | ||
72f2afb8 | 6518 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 | 6519 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
f7ff1987 | 6520 | struct sk_buff **pskb, |
84b67b27 | 6521 | u32 *entry, u32 *budget, |
92cd3a17 | 6522 | u32 base_flags, u32 mss, u32 vlan) |
1da177e4 | 6523 | { |
24f4efd4 | 6524 | struct tg3 *tp = tnapi->tp; |
f7ff1987 | 6525 | struct sk_buff *new_skb, *skb = *pskb; |
c58ec932 | 6526 | dma_addr_t new_addr = 0; |
432aa7ed | 6527 | int ret = 0; |
1da177e4 | 6528 | |
41588ba1 MC |
6529 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
6530 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
6531 | else { | |
6532 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
6533 | ||
6534 | new_skb = skb_copy_expand(skb, | |
6535 | skb_headroom(skb) + more_headroom, | |
6536 | skb_tailroom(skb), GFP_ATOMIC); | |
6537 | } | |
6538 | ||
1da177e4 | 6539 | if (!new_skb) { |
c58ec932 MC |
6540 | ret = -1; |
6541 | } else { | |
6542 | /* New SKB is guaranteed to be linear. */ | |
f4188d8a AD |
6543 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
6544 | PCI_DMA_TODEVICE); | |
6545 | /* Make sure the mapping succeeded */ | |
6546 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
f4188d8a | 6547 | dev_kfree_skb(new_skb); |
c58ec932 | 6548 | ret = -1; |
c58ec932 | 6549 | } else { |
b9e45482 MC |
6550 | u32 save_entry = *entry; |
6551 | ||
92cd3a17 MC |
6552 | base_flags |= TXD_FLAG_END; |
6553 | ||
84b67b27 MC |
6554 | tnapi->tx_buffers[*entry].skb = new_skb; |
6555 | dma_unmap_addr_set(&tnapi->tx_buffers[*entry], | |
432aa7ed MC |
6556 | mapping, new_addr); |
6557 | ||
84b67b27 | 6558 | if (tg3_tx_frag_set(tnapi, entry, budget, new_addr, |
d1a3b737 MC |
6559 | new_skb->len, base_flags, |
6560 | mss, vlan)) { | |
ba1142e4 | 6561 | tg3_tx_skb_unmap(tnapi, save_entry, -1); |
d1a3b737 MC |
6562 | dev_kfree_skb(new_skb); |
6563 | ret = -1; | |
6564 | } | |
f4188d8a | 6565 | } |
1da177e4 LT |
6566 | } |
6567 | ||
6568 | dev_kfree_skb(skb); | |
f7ff1987 | 6569 | *pskb = new_skb; |
c58ec932 | 6570 | return ret; |
1da177e4 LT |
6571 | } |
6572 | ||
2ffcc981 | 6573 | static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *); |
52c0fd83 MC |
6574 | |
6575 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
6576 | * TSO header is greater than 80 bytes. | |
6577 | */ | |
6578 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
6579 | { | |
6580 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 6581 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
6582 | |
6583 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 6584 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 6585 | netif_stop_queue(tp->dev); |
f65aac16 MC |
6586 | |
6587 | /* netif_tx_stop_queue() must be done before checking | |
6588 | * checking tx index in tg3_tx_avail() below, because in | |
6589 | * tg3_tx(), we update tx index before checking for | |
6590 | * netif_tx_queue_stopped(). | |
6591 | */ | |
6592 | smp_mb(); | |
f3f3f27e | 6593 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
6594 | return NETDEV_TX_BUSY; |
6595 | ||
6596 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
6597 | } |
6598 | ||
6599 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 6600 | if (IS_ERR(segs)) |
52c0fd83 MC |
6601 | goto tg3_tso_bug_end; |
6602 | ||
6603 | do { | |
6604 | nskb = segs; | |
6605 | segs = segs->next; | |
6606 | nskb->next = NULL; | |
2ffcc981 | 6607 | tg3_start_xmit(nskb, tp->dev); |
52c0fd83 MC |
6608 | } while (segs); |
6609 | ||
6610 | tg3_tso_bug_end: | |
6611 | dev_kfree_skb(skb); | |
6612 | ||
6613 | return NETDEV_TX_OK; | |
6614 | } | |
52c0fd83 | 6615 | |
5a6f3074 | 6616 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
63c3a66f | 6617 | * support TG3_FLAG_HW_TSO_1 or firmware TSO only. |
5a6f3074 | 6618 | */ |
2ffcc981 | 6619 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
6620 | { |
6621 | struct tg3 *tp = netdev_priv(dev); | |
92cd3a17 | 6622 | u32 len, entry, base_flags, mss, vlan = 0; |
84b67b27 | 6623 | u32 budget; |
432aa7ed | 6624 | int i = -1, would_hit_hwbug; |
90079ce8 | 6625 | dma_addr_t mapping; |
24f4efd4 MC |
6626 | struct tg3_napi *tnapi; |
6627 | struct netdev_queue *txq; | |
432aa7ed | 6628 | unsigned int last; |
f4188d8a | 6629 | |
24f4efd4 MC |
6630 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
6631 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
63c3a66f | 6632 | if (tg3_flag(tp, ENABLE_TSS)) |
24f4efd4 | 6633 | tnapi++; |
1da177e4 | 6634 | |
84b67b27 MC |
6635 | budget = tg3_tx_avail(tnapi); |
6636 | ||
00b70504 | 6637 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 6638 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
6639 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
6640 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 6641 | */ |
84b67b27 | 6642 | if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
6643 | if (!netif_tx_queue_stopped(txq)) { |
6644 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
6645 | |
6646 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
6647 | netdev_err(dev, |
6648 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 6649 | } |
1da177e4 LT |
6650 | return NETDEV_TX_BUSY; |
6651 | } | |
6652 | ||
f3f3f27e | 6653 | entry = tnapi->tx_prod; |
1da177e4 | 6654 | base_flags = 0; |
84fa7933 | 6655 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 6656 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 6657 | |
be98da6a MC |
6658 | mss = skb_shinfo(skb)->gso_size; |
6659 | if (mss) { | |
eddc9ec5 | 6660 | struct iphdr *iph; |
34195c3d | 6661 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
6662 | |
6663 | if (skb_header_cloned(skb) && | |
48855432 ED |
6664 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) |
6665 | goto drop; | |
1da177e4 | 6666 | |
34195c3d | 6667 | iph = ip_hdr(skb); |
ab6a5bb6 | 6668 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 6669 | |
02e96080 | 6670 | if (skb_is_gso_v6(skb)) { |
34195c3d MC |
6671 | hdr_len = skb_headlen(skb) - ETH_HLEN; |
6672 | } else { | |
6673 | u32 ip_tcp_len; | |
6674 | ||
6675 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
6676 | hdr_len = ip_tcp_len + tcp_opt_len; | |
6677 | ||
6678 | iph->check = 0; | |
6679 | iph->tot_len = htons(mss + hdr_len); | |
6680 | } | |
6681 | ||
52c0fd83 | 6682 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
63c3a66f | 6683 | tg3_flag(tp, TSO_BUG)) |
de6f31eb | 6684 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 6685 | |
1da177e4 LT |
6686 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
6687 | TXD_FLAG_CPU_POST_DMA); | |
6688 | ||
63c3a66f JP |
6689 | if (tg3_flag(tp, HW_TSO_1) || |
6690 | tg3_flag(tp, HW_TSO_2) || | |
6691 | tg3_flag(tp, HW_TSO_3)) { | |
aa8223c7 | 6692 | tcp_hdr(skb)->check = 0; |
1da177e4 | 6693 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
6694 | } else |
6695 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6696 | iph->daddr, 0, | |
6697 | IPPROTO_TCP, | |
6698 | 0); | |
1da177e4 | 6699 | |
63c3a66f | 6700 | if (tg3_flag(tp, HW_TSO_3)) { |
615774fe MC |
6701 | mss |= (hdr_len & 0xc) << 12; |
6702 | if (hdr_len & 0x10) | |
6703 | base_flags |= 0x00000010; | |
6704 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 6705 | } else if (tg3_flag(tp, HW_TSO_2)) |
92c6b8d1 | 6706 | mss |= hdr_len << 9; |
63c3a66f | 6707 | else if (tg3_flag(tp, HW_TSO_1) || |
92c6b8d1 | 6708 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
eddc9ec5 | 6709 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6710 | int tsflags; |
6711 | ||
eddc9ec5 | 6712 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6713 | mss |= (tsflags << 11); |
6714 | } | |
6715 | } else { | |
eddc9ec5 | 6716 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6717 | int tsflags; |
6718 | ||
eddc9ec5 | 6719 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6720 | base_flags |= tsflags << 12; |
6721 | } | |
6722 | } | |
6723 | } | |
bf933c80 | 6724 | |
93a700a9 MC |
6725 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && |
6726 | !mss && skb->len > VLAN_ETH_FRAME_LEN) | |
6727 | base_flags |= TXD_FLAG_JMB_PKT; | |
6728 | ||
92cd3a17 MC |
6729 | if (vlan_tx_tag_present(skb)) { |
6730 | base_flags |= TXD_FLAG_VLAN; | |
6731 | vlan = vlan_tx_tag_get(skb); | |
6732 | } | |
1da177e4 | 6733 | |
f4188d8a AD |
6734 | len = skb_headlen(skb); |
6735 | ||
6736 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
48855432 ED |
6737 | if (pci_dma_mapping_error(tp->pdev, mapping)) |
6738 | goto drop; | |
6739 | ||
90079ce8 | 6740 | |
f3f3f27e | 6741 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 6742 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
6743 | |
6744 | would_hit_hwbug = 0; | |
6745 | ||
63c3a66f | 6746 | if (tg3_flag(tp, 5701_DMA_BUG)) |
c58ec932 | 6747 | would_hit_hwbug = 1; |
1da177e4 | 6748 | |
84b67b27 | 6749 | if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags | |
d1a3b737 | 6750 | ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), |
ba1142e4 | 6751 | mss, vlan)) { |
d1a3b737 | 6752 | would_hit_hwbug = 1; |
1da177e4 | 6753 | /* Now loop through additional data fragments, and queue them. */ |
ba1142e4 | 6754 | } else if (skb_shinfo(skb)->nr_frags > 0) { |
92cd3a17 MC |
6755 | u32 tmp_mss = mss; |
6756 | ||
6757 | if (!tg3_flag(tp, HW_TSO_1) && | |
6758 | !tg3_flag(tp, HW_TSO_2) && | |
6759 | !tg3_flag(tp, HW_TSO_3)) | |
6760 | tmp_mss = 0; | |
6761 | ||
1da177e4 LT |
6762 | last = skb_shinfo(skb)->nr_frags - 1; |
6763 | for (i = 0; i <= last; i++) { | |
6764 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6765 | ||
9e903e08 | 6766 | len = skb_frag_size(frag); |
dc234d0b | 6767 | mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, |
5d6bcdfe | 6768 | len, DMA_TO_DEVICE); |
1da177e4 | 6769 | |
f3f3f27e | 6770 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 6771 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a | 6772 | mapping); |
5d6bcdfe | 6773 | if (dma_mapping_error(&tp->pdev->dev, mapping)) |
f4188d8a | 6774 | goto dma_error; |
1da177e4 | 6775 | |
b9e45482 MC |
6776 | if (!budget || |
6777 | tg3_tx_frag_set(tnapi, &entry, &budget, mapping, | |
84b67b27 MC |
6778 | len, base_flags | |
6779 | ((i == last) ? TXD_FLAG_END : 0), | |
b9e45482 | 6780 | tmp_mss, vlan)) { |
72f2afb8 | 6781 | would_hit_hwbug = 1; |
b9e45482 MC |
6782 | break; |
6783 | } | |
1da177e4 LT |
6784 | } |
6785 | } | |
6786 | ||
6787 | if (would_hit_hwbug) { | |
0d681b27 | 6788 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); |
1da177e4 LT |
6789 | |
6790 | /* If the workaround fails due to memory/mapping | |
6791 | * failure, silently drop this packet. | |
6792 | */ | |
84b67b27 MC |
6793 | entry = tnapi->tx_prod; |
6794 | budget = tg3_tx_avail(tnapi); | |
f7ff1987 | 6795 | if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget, |
84b67b27 | 6796 | base_flags, mss, vlan)) |
48855432 | 6797 | goto drop_nofree; |
1da177e4 LT |
6798 | } |
6799 | ||
d515b450 | 6800 | skb_tx_timestamp(skb); |
298376d3 | 6801 | netdev_sent_queue(tp->dev, skb->len); |
d515b450 | 6802 | |
1da177e4 | 6803 | /* Packets are ready, update Tx producer idx local and on card. */ |
24f4efd4 | 6804 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 6805 | |
f3f3f27e MC |
6806 | tnapi->tx_prod = entry; |
6807 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 6808 | netif_tx_stop_queue(txq); |
f65aac16 MC |
6809 | |
6810 | /* netif_tx_stop_queue() must be done before checking | |
6811 | * checking tx index in tg3_tx_avail() below, because in | |
6812 | * tg3_tx(), we update tx index before checking for | |
6813 | * netif_tx_queue_stopped(). | |
6814 | */ | |
6815 | smp_mb(); | |
f3f3f27e | 6816 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 6817 | netif_tx_wake_queue(txq); |
51b91468 | 6818 | } |
1da177e4 | 6819 | |
cdd0db05 | 6820 | mmiowb(); |
1da177e4 | 6821 | return NETDEV_TX_OK; |
f4188d8a AD |
6822 | |
6823 | dma_error: | |
ba1142e4 | 6824 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); |
432aa7ed | 6825 | tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; |
48855432 ED |
6826 | drop: |
6827 | dev_kfree_skb(skb); | |
6828 | drop_nofree: | |
6829 | tp->tx_dropped++; | |
f4188d8a | 6830 | return NETDEV_TX_OK; |
1da177e4 LT |
6831 | } |
6832 | ||
6e01b20b MC |
6833 | static void tg3_mac_loopback(struct tg3 *tp, bool enable) |
6834 | { | |
6835 | if (enable) { | |
6836 | tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | | |
6837 | MAC_MODE_PORT_MODE_MASK); | |
6838 | ||
6839 | tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
6840 | ||
6841 | if (!tg3_flag(tp, 5705_PLUS)) | |
6842 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
6843 | ||
6844 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
6845 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
6846 | else | |
6847 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
6848 | } else { | |
6849 | tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; | |
6850 | ||
6851 | if (tg3_flag(tp, 5705_PLUS) || | |
6852 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || | |
6853 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
6854 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
6855 | } | |
6856 | ||
6857 | tw32(MAC_MODE, tp->mac_mode); | |
6858 | udelay(40); | |
6859 | } | |
6860 | ||
941ec90f | 6861 | static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) |
5e5a7f37 | 6862 | { |
941ec90f | 6863 | u32 val, bmcr, mac_mode, ptest = 0; |
5e5a7f37 MC |
6864 | |
6865 | tg3_phy_toggle_apd(tp, false); | |
6866 | tg3_phy_toggle_automdix(tp, 0); | |
6867 | ||
941ec90f MC |
6868 | if (extlpbk && tg3_phy_set_extloopbk(tp)) |
6869 | return -EIO; | |
6870 | ||
6871 | bmcr = BMCR_FULLDPLX; | |
5e5a7f37 MC |
6872 | switch (speed) { |
6873 | case SPEED_10: | |
6874 | break; | |
6875 | case SPEED_100: | |
6876 | bmcr |= BMCR_SPEED100; | |
6877 | break; | |
6878 | case SPEED_1000: | |
6879 | default: | |
6880 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
6881 | speed = SPEED_100; | |
6882 | bmcr |= BMCR_SPEED100; | |
6883 | } else { | |
6884 | speed = SPEED_1000; | |
6885 | bmcr |= BMCR_SPEED1000; | |
6886 | } | |
6887 | } | |
6888 | ||
941ec90f MC |
6889 | if (extlpbk) { |
6890 | if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
6891 | tg3_readphy(tp, MII_CTRL1000, &val); | |
6892 | val |= CTL1000_AS_MASTER | | |
6893 | CTL1000_ENABLE_MASTER; | |
6894 | tg3_writephy(tp, MII_CTRL1000, val); | |
6895 | } else { | |
6896 | ptest = MII_TG3_FET_PTEST_TRIM_SEL | | |
6897 | MII_TG3_FET_PTEST_TRIM_2; | |
6898 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); | |
6899 | } | |
6900 | } else | |
6901 | bmcr |= BMCR_LOOPBACK; | |
6902 | ||
5e5a7f37 MC |
6903 | tg3_writephy(tp, MII_BMCR, bmcr); |
6904 | ||
6905 | /* The write needs to be flushed for the FETs */ | |
6906 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
6907 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
6908 | ||
6909 | udelay(40); | |
6910 | ||
6911 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && | |
6912 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
941ec90f | 6913 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | |
5e5a7f37 MC |
6914 | MII_TG3_FET_PTEST_FRC_TX_LINK | |
6915 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
6916 | ||
6917 | /* The write needs to be flushed for the AC131 */ | |
6918 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
6919 | } | |
6920 | ||
6921 | /* Reset to prevent losing 1st rx packet intermittently */ | |
6922 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && | |
6923 | tg3_flag(tp, 5780_CLASS)) { | |
6924 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
6925 | udelay(10); | |
6926 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6927 | } | |
6928 | ||
6929 | mac_mode = tp->mac_mode & | |
6930 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
6931 | if (speed == SPEED_1000) | |
6932 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
6933 | else | |
6934 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
6935 | ||
6936 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
6937 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; | |
6938 | ||
6939 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
6940 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
6941 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) | |
6942 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
6943 | ||
6944 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
6945 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
6946 | } | |
6947 | ||
6948 | tw32(MAC_MODE, mac_mode); | |
6949 | udelay(40); | |
941ec90f MC |
6950 | |
6951 | return 0; | |
5e5a7f37 MC |
6952 | } |
6953 | ||
c8f44aff | 6954 | static void tg3_set_loopback(struct net_device *dev, netdev_features_t features) |
06c03c02 MB |
6955 | { |
6956 | struct tg3 *tp = netdev_priv(dev); | |
6957 | ||
6958 | if (features & NETIF_F_LOOPBACK) { | |
6959 | if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) | |
6960 | return; | |
6961 | ||
06c03c02 | 6962 | spin_lock_bh(&tp->lock); |
6e01b20b | 6963 | tg3_mac_loopback(tp, true); |
06c03c02 MB |
6964 | netif_carrier_on(tp->dev); |
6965 | spin_unlock_bh(&tp->lock); | |
6966 | netdev_info(dev, "Internal MAC loopback mode enabled.\n"); | |
6967 | } else { | |
6968 | if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
6969 | return; | |
6970 | ||
06c03c02 | 6971 | spin_lock_bh(&tp->lock); |
6e01b20b | 6972 | tg3_mac_loopback(tp, false); |
06c03c02 MB |
6973 | /* Force link status check */ |
6974 | tg3_setup_phy(tp, 1); | |
6975 | spin_unlock_bh(&tp->lock); | |
6976 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | |
6977 | } | |
6978 | } | |
6979 | ||
c8f44aff MM |
6980 | static netdev_features_t tg3_fix_features(struct net_device *dev, |
6981 | netdev_features_t features) | |
dc668910 MM |
6982 | { |
6983 | struct tg3 *tp = netdev_priv(dev); | |
6984 | ||
63c3a66f | 6985 | if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) |
dc668910 MM |
6986 | features &= ~NETIF_F_ALL_TSO; |
6987 | ||
6988 | return features; | |
6989 | } | |
6990 | ||
c8f44aff | 6991 | static int tg3_set_features(struct net_device *dev, netdev_features_t features) |
06c03c02 | 6992 | { |
c8f44aff | 6993 | netdev_features_t changed = dev->features ^ features; |
06c03c02 MB |
6994 | |
6995 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) | |
6996 | tg3_set_loopback(dev, features); | |
6997 | ||
6998 | return 0; | |
6999 | } | |
7000 | ||
1da177e4 LT |
7001 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
7002 | int new_mtu) | |
7003 | { | |
7004 | dev->mtu = new_mtu; | |
7005 | ||
ef7f5ec0 | 7006 | if (new_mtu > ETH_DATA_LEN) { |
63c3a66f | 7007 | if (tg3_flag(tp, 5780_CLASS)) { |
dc668910 | 7008 | netdev_update_features(dev); |
63c3a66f | 7009 | tg3_flag_clear(tp, TSO_CAPABLE); |
859a5887 | 7010 | } else { |
63c3a66f | 7011 | tg3_flag_set(tp, JUMBO_RING_ENABLE); |
859a5887 | 7012 | } |
ef7f5ec0 | 7013 | } else { |
63c3a66f JP |
7014 | if (tg3_flag(tp, 5780_CLASS)) { |
7015 | tg3_flag_set(tp, TSO_CAPABLE); | |
dc668910 MM |
7016 | netdev_update_features(dev); |
7017 | } | |
63c3a66f | 7018 | tg3_flag_clear(tp, JUMBO_RING_ENABLE); |
ef7f5ec0 | 7019 | } |
1da177e4 LT |
7020 | } |
7021 | ||
7022 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
7023 | { | |
7024 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 7025 | int err; |
1da177e4 LT |
7026 | |
7027 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
7028 | return -EINVAL; | |
7029 | ||
7030 | if (!netif_running(dev)) { | |
7031 | /* We'll just catch it later when the | |
7032 | * device is up'd. | |
7033 | */ | |
7034 | tg3_set_mtu(dev, tp, new_mtu); | |
7035 | return 0; | |
7036 | } | |
7037 | ||
b02fd9e3 MC |
7038 | tg3_phy_stop(tp); |
7039 | ||
1da177e4 | 7040 | tg3_netif_stop(tp); |
f47c11ee DM |
7041 | |
7042 | tg3_full_lock(tp, 1); | |
1da177e4 | 7043 | |
944d980e | 7044 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
7045 | |
7046 | tg3_set_mtu(dev, tp, new_mtu); | |
7047 | ||
b9ec6c1b | 7048 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 7049 | |
b9ec6c1b MC |
7050 | if (!err) |
7051 | tg3_netif_start(tp); | |
1da177e4 | 7052 | |
f47c11ee | 7053 | tg3_full_unlock(tp); |
1da177e4 | 7054 | |
b02fd9e3 MC |
7055 | if (!err) |
7056 | tg3_phy_start(tp); | |
7057 | ||
b9ec6c1b | 7058 | return err; |
1da177e4 LT |
7059 | } |
7060 | ||
21f581a5 MC |
7061 | static void tg3_rx_prodring_free(struct tg3 *tp, |
7062 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7063 | { |
1da177e4 LT |
7064 | int i; |
7065 | ||
8fea32b9 | 7066 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 7067 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 7068 | i = (i + 1) & tp->rx_std_ring_mask) |
9205fd9c | 7069 | tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], |
b196c7e4 MC |
7070 | tp->rx_pkt_map_sz); |
7071 | ||
63c3a66f | 7072 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
b196c7e4 MC |
7073 | for (i = tpr->rx_jmb_cons_idx; |
7074 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 7075 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
9205fd9c | 7076 | tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], |
b196c7e4 MC |
7077 | TG3_RX_JMB_MAP_SZ); |
7078 | } | |
7079 | } | |
7080 | ||
2b2cdb65 | 7081 | return; |
b196c7e4 | 7082 | } |
1da177e4 | 7083 | |
2c49a44d | 7084 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
9205fd9c | 7085 | tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], |
2b2cdb65 | 7086 | tp->rx_pkt_map_sz); |
1da177e4 | 7087 | |
63c3a66f | 7088 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 7089 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
9205fd9c | 7090 | tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], |
2b2cdb65 | 7091 | TG3_RX_JMB_MAP_SZ); |
1da177e4 LT |
7092 | } |
7093 | } | |
7094 | ||
c6cdf436 | 7095 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
7096 | * |
7097 | * The chip has been shut down and the driver detached from | |
7098 | * the networking, so no interrupts or new tx packets will | |
7099 | * end up in the driver. tp->{tx,}lock are held and thus | |
7100 | * we may not sleep. | |
7101 | */ | |
21f581a5 MC |
7102 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
7103 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7104 | { |
287be12e | 7105 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 7106 | |
b196c7e4 MC |
7107 | tpr->rx_std_cons_idx = 0; |
7108 | tpr->rx_std_prod_idx = 0; | |
7109 | tpr->rx_jmb_cons_idx = 0; | |
7110 | tpr->rx_jmb_prod_idx = 0; | |
7111 | ||
8fea32b9 | 7112 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
7113 | memset(&tpr->rx_std_buffers[0], 0, |
7114 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 7115 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 7116 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 7117 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
7118 | goto done; |
7119 | } | |
7120 | ||
1da177e4 | 7121 | /* Zero out all descriptors. */ |
2c49a44d | 7122 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 7123 | |
287be12e | 7124 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
63c3a66f | 7125 | if (tg3_flag(tp, 5780_CLASS) && |
287be12e MC |
7126 | tp->dev->mtu > ETH_DATA_LEN) |
7127 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
7128 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 7129 | |
1da177e4 LT |
7130 | /* Initialize invariants of the rings, we only set this |
7131 | * stuff once. This works because the card does not | |
7132 | * write into the rx buffer posting rings. | |
7133 | */ | |
2c49a44d | 7134 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
7135 | struct tg3_rx_buffer_desc *rxd; |
7136 | ||
21f581a5 | 7137 | rxd = &tpr->rx_std[i]; |
287be12e | 7138 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
7139 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
7140 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
7141 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
7142 | } | |
7143 | ||
1da177e4 LT |
7144 | /* Now allocate fresh SKBs for each rx ring. */ |
7145 | for (i = 0; i < tp->rx_pending; i++) { | |
9205fd9c | 7146 | if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
5129c3a3 MC |
7147 | netdev_warn(tp->dev, |
7148 | "Using a smaller RX standard ring. Only " | |
7149 | "%d out of %d buffers were allocated " | |
7150 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 7151 | if (i == 0) |
cf7a7298 | 7152 | goto initfail; |
32d8c572 | 7153 | tp->rx_pending = i; |
1da177e4 | 7154 | break; |
32d8c572 | 7155 | } |
1da177e4 LT |
7156 | } |
7157 | ||
63c3a66f | 7158 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
cf7a7298 MC |
7159 | goto done; |
7160 | ||
2c49a44d | 7161 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 7162 | |
63c3a66f | 7163 | if (!tg3_flag(tp, JUMBO_RING_ENABLE)) |
0d86df80 | 7164 | goto done; |
cf7a7298 | 7165 | |
2c49a44d | 7166 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
7167 | struct tg3_rx_buffer_desc *rxd; |
7168 | ||
7169 | rxd = &tpr->rx_jmb[i].std; | |
7170 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
7171 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
7172 | RXD_FLAG_JUMBO; | |
7173 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
7174 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
7175 | } | |
7176 | ||
7177 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
9205fd9c | 7178 | if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { |
5129c3a3 MC |
7179 | netdev_warn(tp->dev, |
7180 | "Using a smaller RX jumbo ring. Only %d " | |
7181 | "out of %d buffers were allocated " | |
7182 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
7183 | if (i == 0) |
7184 | goto initfail; | |
7185 | tp->rx_jumbo_pending = i; | |
7186 | break; | |
1da177e4 LT |
7187 | } |
7188 | } | |
cf7a7298 MC |
7189 | |
7190 | done: | |
32d8c572 | 7191 | return 0; |
cf7a7298 MC |
7192 | |
7193 | initfail: | |
21f581a5 | 7194 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 7195 | return -ENOMEM; |
1da177e4 LT |
7196 | } |
7197 | ||
21f581a5 MC |
7198 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
7199 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7200 | { |
21f581a5 MC |
7201 | kfree(tpr->rx_std_buffers); |
7202 | tpr->rx_std_buffers = NULL; | |
7203 | kfree(tpr->rx_jmb_buffers); | |
7204 | tpr->rx_jmb_buffers = NULL; | |
7205 | if (tpr->rx_std) { | |
4bae65c8 MC |
7206 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
7207 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 7208 | tpr->rx_std = NULL; |
1da177e4 | 7209 | } |
21f581a5 | 7210 | if (tpr->rx_jmb) { |
4bae65c8 MC |
7211 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
7212 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 7213 | tpr->rx_jmb = NULL; |
1da177e4 | 7214 | } |
cf7a7298 MC |
7215 | } |
7216 | ||
21f581a5 MC |
7217 | static int tg3_rx_prodring_init(struct tg3 *tp, |
7218 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 7219 | { |
2c49a44d MC |
7220 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
7221 | GFP_KERNEL); | |
21f581a5 | 7222 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
7223 | return -ENOMEM; |
7224 | ||
4bae65c8 MC |
7225 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
7226 | TG3_RX_STD_RING_BYTES(tp), | |
7227 | &tpr->rx_std_mapping, | |
7228 | GFP_KERNEL); | |
21f581a5 | 7229 | if (!tpr->rx_std) |
cf7a7298 MC |
7230 | goto err_out; |
7231 | ||
63c3a66f | 7232 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 7233 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
7234 | GFP_KERNEL); |
7235 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
7236 | goto err_out; |
7237 | ||
4bae65c8 MC |
7238 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
7239 | TG3_RX_JMB_RING_BYTES(tp), | |
7240 | &tpr->rx_jmb_mapping, | |
7241 | GFP_KERNEL); | |
21f581a5 | 7242 | if (!tpr->rx_jmb) |
cf7a7298 MC |
7243 | goto err_out; |
7244 | } | |
7245 | ||
7246 | return 0; | |
7247 | ||
7248 | err_out: | |
21f581a5 | 7249 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
7250 | return -ENOMEM; |
7251 | } | |
7252 | ||
7253 | /* Free up pending packets in all rx/tx rings. | |
7254 | * | |
7255 | * The chip has been shut down and the driver detached from | |
7256 | * the networking, so no interrupts or new tx packets will | |
7257 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
7258 | * in an interrupt context and thus may sleep. | |
7259 | */ | |
7260 | static void tg3_free_rings(struct tg3 *tp) | |
7261 | { | |
f77a6a8e | 7262 | int i, j; |
cf7a7298 | 7263 | |
f77a6a8e MC |
7264 | for (j = 0; j < tp->irq_cnt; j++) { |
7265 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 7266 | |
8fea32b9 | 7267 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 7268 | |
0c1d0e2b MC |
7269 | if (!tnapi->tx_buffers) |
7270 | continue; | |
7271 | ||
0d681b27 MC |
7272 | for (i = 0; i < TG3_TX_RING_SIZE; i++) { |
7273 | struct sk_buff *skb = tnapi->tx_buffers[i].skb; | |
cf7a7298 | 7274 | |
0d681b27 | 7275 | if (!skb) |
f77a6a8e | 7276 | continue; |
cf7a7298 | 7277 | |
ba1142e4 MC |
7278 | tg3_tx_skb_unmap(tnapi, i, |
7279 | skb_shinfo(skb)->nr_frags - 1); | |
f77a6a8e MC |
7280 | |
7281 | dev_kfree_skb_any(skb); | |
7282 | } | |
2b2cdb65 | 7283 | } |
298376d3 | 7284 | netdev_reset_queue(tp->dev); |
cf7a7298 MC |
7285 | } |
7286 | ||
7287 | /* Initialize tx/rx rings for packet processing. | |
7288 | * | |
7289 | * The chip has been shut down and the driver detached from | |
7290 | * the networking, so no interrupts or new tx packets will | |
7291 | * end up in the driver. tp->{tx,}lock are held and thus | |
7292 | * we may not sleep. | |
7293 | */ | |
7294 | static int tg3_init_rings(struct tg3 *tp) | |
7295 | { | |
f77a6a8e | 7296 | int i; |
72334482 | 7297 | |
cf7a7298 MC |
7298 | /* Free up all the SKBs. */ |
7299 | tg3_free_rings(tp); | |
7300 | ||
f77a6a8e MC |
7301 | for (i = 0; i < tp->irq_cnt; i++) { |
7302 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7303 | ||
7304 | tnapi->last_tag = 0; | |
7305 | tnapi->last_irq_tag = 0; | |
7306 | tnapi->hw_status->status = 0; | |
7307 | tnapi->hw_status->status_tag = 0; | |
7308 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 7309 | |
f77a6a8e MC |
7310 | tnapi->tx_prod = 0; |
7311 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
7312 | if (tnapi->tx_ring) |
7313 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
7314 | |
7315 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
7316 | if (tnapi->rx_rcb) |
7317 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 7318 | |
8fea32b9 | 7319 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 7320 | tg3_free_rings(tp); |
2b2cdb65 | 7321 | return -ENOMEM; |
e4af1af9 | 7322 | } |
f77a6a8e | 7323 | } |
72334482 | 7324 | |
2b2cdb65 | 7325 | return 0; |
cf7a7298 MC |
7326 | } |
7327 | ||
7328 | /* | |
7329 | * Must not be invoked with interrupt sources disabled and | |
7330 | * the hardware shutdown down. | |
7331 | */ | |
7332 | static void tg3_free_consistent(struct tg3 *tp) | |
7333 | { | |
f77a6a8e | 7334 | int i; |
898a56f8 | 7335 | |
f77a6a8e MC |
7336 | for (i = 0; i < tp->irq_cnt; i++) { |
7337 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7338 | ||
7339 | if (tnapi->tx_ring) { | |
4bae65c8 | 7340 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
7341 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
7342 | tnapi->tx_ring = NULL; | |
7343 | } | |
7344 | ||
7345 | kfree(tnapi->tx_buffers); | |
7346 | tnapi->tx_buffers = NULL; | |
7347 | ||
7348 | if (tnapi->rx_rcb) { | |
4bae65c8 MC |
7349 | dma_free_coherent(&tp->pdev->dev, |
7350 | TG3_RX_RCB_RING_BYTES(tp), | |
7351 | tnapi->rx_rcb, | |
7352 | tnapi->rx_rcb_mapping); | |
f77a6a8e MC |
7353 | tnapi->rx_rcb = NULL; |
7354 | } | |
7355 | ||
8fea32b9 MC |
7356 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
7357 | ||
f77a6a8e | 7358 | if (tnapi->hw_status) { |
4bae65c8 MC |
7359 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
7360 | tnapi->hw_status, | |
7361 | tnapi->status_mapping); | |
f77a6a8e MC |
7362 | tnapi->hw_status = NULL; |
7363 | } | |
1da177e4 | 7364 | } |
f77a6a8e | 7365 | |
1da177e4 | 7366 | if (tp->hw_stats) { |
4bae65c8 MC |
7367 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
7368 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
7369 | tp->hw_stats = NULL; |
7370 | } | |
7371 | } | |
7372 | ||
7373 | /* | |
7374 | * Must not be invoked with interrupt sources disabled and | |
7375 | * the hardware shutdown down. Can sleep. | |
7376 | */ | |
7377 | static int tg3_alloc_consistent(struct tg3 *tp) | |
7378 | { | |
f77a6a8e | 7379 | int i; |
898a56f8 | 7380 | |
4bae65c8 MC |
7381 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
7382 | sizeof(struct tg3_hw_stats), | |
7383 | &tp->stats_mapping, | |
7384 | GFP_KERNEL); | |
f77a6a8e | 7385 | if (!tp->hw_stats) |
1da177e4 LT |
7386 | goto err_out; |
7387 | ||
f77a6a8e | 7388 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 7389 | |
f77a6a8e MC |
7390 | for (i = 0; i < tp->irq_cnt; i++) { |
7391 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 7392 | struct tg3_hw_status *sblk; |
1da177e4 | 7393 | |
4bae65c8 MC |
7394 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
7395 | TG3_HW_STATUS_SIZE, | |
7396 | &tnapi->status_mapping, | |
7397 | GFP_KERNEL); | |
f77a6a8e MC |
7398 | if (!tnapi->hw_status) |
7399 | goto err_out; | |
898a56f8 | 7400 | |
f77a6a8e | 7401 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
7402 | sblk = tnapi->hw_status; |
7403 | ||
8fea32b9 MC |
7404 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
7405 | goto err_out; | |
7406 | ||
19cfaecc MC |
7407 | /* If multivector TSS is enabled, vector 0 does not handle |
7408 | * tx interrupts. Don't allocate any resources for it. | |
7409 | */ | |
63c3a66f JP |
7410 | if ((!i && !tg3_flag(tp, ENABLE_TSS)) || |
7411 | (i && tg3_flag(tp, ENABLE_TSS))) { | |
df8944cf MC |
7412 | tnapi->tx_buffers = kzalloc( |
7413 | sizeof(struct tg3_tx_ring_info) * | |
7414 | TG3_TX_RING_SIZE, GFP_KERNEL); | |
19cfaecc MC |
7415 | if (!tnapi->tx_buffers) |
7416 | goto err_out; | |
7417 | ||
4bae65c8 MC |
7418 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
7419 | TG3_TX_RING_BYTES, | |
7420 | &tnapi->tx_desc_mapping, | |
7421 | GFP_KERNEL); | |
19cfaecc MC |
7422 | if (!tnapi->tx_ring) |
7423 | goto err_out; | |
7424 | } | |
7425 | ||
8d9d7cfc MC |
7426 | /* |
7427 | * When RSS is enabled, the status block format changes | |
7428 | * slightly. The "rx_jumbo_consumer", "reserved", | |
7429 | * and "rx_mini_consumer" members get mapped to the | |
7430 | * other three rx return ring producer indexes. | |
7431 | */ | |
7432 | switch (i) { | |
7433 | default: | |
7434 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
7435 | break; | |
7436 | case 2: | |
7437 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
7438 | break; | |
7439 | case 3: | |
7440 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
7441 | break; | |
7442 | case 4: | |
7443 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
7444 | break; | |
7445 | } | |
72334482 | 7446 | |
0c1d0e2b MC |
7447 | /* |
7448 | * If multivector RSS is enabled, vector 0 does not handle | |
7449 | * rx or tx interrupts. Don't allocate any resources for it. | |
7450 | */ | |
63c3a66f | 7451 | if (!i && tg3_flag(tp, ENABLE_RSS)) |
0c1d0e2b MC |
7452 | continue; |
7453 | ||
4bae65c8 MC |
7454 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
7455 | TG3_RX_RCB_RING_BYTES(tp), | |
7456 | &tnapi->rx_rcb_mapping, | |
7457 | GFP_KERNEL); | |
f77a6a8e MC |
7458 | if (!tnapi->rx_rcb) |
7459 | goto err_out; | |
72334482 | 7460 | |
f77a6a8e | 7461 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 7462 | } |
1da177e4 LT |
7463 | |
7464 | return 0; | |
7465 | ||
7466 | err_out: | |
7467 | tg3_free_consistent(tp); | |
7468 | return -ENOMEM; | |
7469 | } | |
7470 | ||
7471 | #define MAX_WAIT_CNT 1000 | |
7472 | ||
7473 | /* To stop a block, clear the enable bit and poll till it | |
7474 | * clears. tp->lock is held. | |
7475 | */ | |
b3b7d6be | 7476 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
7477 | { |
7478 | unsigned int i; | |
7479 | u32 val; | |
7480 | ||
63c3a66f | 7481 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
7482 | switch (ofs) { |
7483 | case RCVLSC_MODE: | |
7484 | case DMAC_MODE: | |
7485 | case MBFREE_MODE: | |
7486 | case BUFMGR_MODE: | |
7487 | case MEMARB_MODE: | |
7488 | /* We can't enable/disable these bits of the | |
7489 | * 5705/5750, just say success. | |
7490 | */ | |
7491 | return 0; | |
7492 | ||
7493 | default: | |
7494 | break; | |
855e1111 | 7495 | } |
1da177e4 LT |
7496 | } |
7497 | ||
7498 | val = tr32(ofs); | |
7499 | val &= ~enable_bit; | |
7500 | tw32_f(ofs, val); | |
7501 | ||
7502 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
7503 | udelay(100); | |
7504 | val = tr32(ofs); | |
7505 | if ((val & enable_bit) == 0) | |
7506 | break; | |
7507 | } | |
7508 | ||
b3b7d6be | 7509 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
7510 | dev_err(&tp->pdev->dev, |
7511 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
7512 | ofs, enable_bit); | |
1da177e4 LT |
7513 | return -ENODEV; |
7514 | } | |
7515 | ||
7516 | return 0; | |
7517 | } | |
7518 | ||
7519 | /* tp->lock is held. */ | |
b3b7d6be | 7520 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
7521 | { |
7522 | int i, err; | |
7523 | ||
7524 | tg3_disable_ints(tp); | |
7525 | ||
7526 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
7527 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7528 | udelay(10); | |
7529 | ||
b3b7d6be DM |
7530 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
7531 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
7532 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
7533 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
7534 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
7535 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
7536 | ||
7537 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
7538 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
7539 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
7540 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
7541 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
7542 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
7543 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
7544 | |
7545 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
7546 | tw32_f(MAC_MODE, tp->mac_mode); | |
7547 | udelay(40); | |
7548 | ||
7549 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
7550 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
7551 | ||
7552 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
7553 | udelay(100); | |
7554 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
7555 | break; | |
7556 | } | |
7557 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
7558 | dev_err(&tp->pdev->dev, |
7559 | "%s timed out, TX_MODE_ENABLE will not clear " | |
7560 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 7561 | err |= -ENODEV; |
1da177e4 LT |
7562 | } |
7563 | ||
e6de8ad1 | 7564 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
7565 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
7566 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
7567 | |
7568 | tw32(FTQ_RESET, 0xffffffff); | |
7569 | tw32(FTQ_RESET, 0x00000000); | |
7570 | ||
b3b7d6be DM |
7571 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
7572 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 7573 | |
f77a6a8e MC |
7574 | for (i = 0; i < tp->irq_cnt; i++) { |
7575 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7576 | if (tnapi->hw_status) | |
7577 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7578 | } | |
1da177e4 | 7579 | |
1da177e4 LT |
7580 | return err; |
7581 | } | |
7582 | ||
ee6a99b5 MC |
7583 | /* Save PCI command register before chip reset */ |
7584 | static void tg3_save_pci_state(struct tg3 *tp) | |
7585 | { | |
8a6eac90 | 7586 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
7587 | } |
7588 | ||
7589 | /* Restore PCI state after chip reset */ | |
7590 | static void tg3_restore_pci_state(struct tg3 *tp) | |
7591 | { | |
7592 | u32 val; | |
7593 | ||
7594 | /* Re-enable indirect register accesses. */ | |
7595 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
7596 | tp->misc_host_ctrl); | |
7597 | ||
7598 | /* Set MAX PCI retry to zero. */ | |
7599 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
7600 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 7601 | tg3_flag(tp, PCIX_MODE)) |
ee6a99b5 | 7602 | val |= PCISTATE_RETRY_SAME_DMA; |
0d3031d9 | 7603 | /* Allow reads and writes to the APE register and memory space. */ |
63c3a66f | 7604 | if (tg3_flag(tp, ENABLE_APE)) |
0d3031d9 | 7605 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
f92d9dc1 MC |
7606 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7607 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
7608 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
7609 | ||
8a6eac90 | 7610 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 7611 | |
2c55a3d0 MC |
7612 | if (!tg3_flag(tp, PCI_EXPRESS)) { |
7613 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
7614 | tp->pci_cacheline_sz); | |
7615 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
7616 | tp->pci_lat_timer); | |
114342f2 | 7617 | } |
5f5c51e3 | 7618 | |
ee6a99b5 | 7619 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
63c3a66f | 7620 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
7621 | u16 pcix_cmd; |
7622 | ||
7623 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7624 | &pcix_cmd); | |
7625 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
7626 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7627 | pcix_cmd); | |
7628 | } | |
ee6a99b5 | 7629 | |
63c3a66f | 7630 | if (tg3_flag(tp, 5780_CLASS)) { |
ee6a99b5 MC |
7631 | |
7632 | /* Chip reset on 5780 will reset MSI enable bit, | |
7633 | * so need to restore it. | |
7634 | */ | |
63c3a66f | 7635 | if (tg3_flag(tp, USING_MSI)) { |
ee6a99b5 MC |
7636 | u16 ctrl; |
7637 | ||
7638 | pci_read_config_word(tp->pdev, | |
7639 | tp->msi_cap + PCI_MSI_FLAGS, | |
7640 | &ctrl); | |
7641 | pci_write_config_word(tp->pdev, | |
7642 | tp->msi_cap + PCI_MSI_FLAGS, | |
7643 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
7644 | val = tr32(MSGINT_MODE); | |
7645 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
7646 | } | |
7647 | } | |
7648 | } | |
7649 | ||
1da177e4 LT |
7650 | /* tp->lock is held. */ |
7651 | static int tg3_chip_reset(struct tg3 *tp) | |
7652 | { | |
7653 | u32 val; | |
1ee582d8 | 7654 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 7655 | int i, err; |
1da177e4 | 7656 | |
f49639e6 DM |
7657 | tg3_nvram_lock(tp); |
7658 | ||
77b483f1 MC |
7659 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
7660 | ||
f49639e6 DM |
7661 | /* No matching tg3_nvram_unlock() after this because |
7662 | * chip reset below will undo the nvram lock. | |
7663 | */ | |
7664 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 7665 | |
ee6a99b5 MC |
7666 | /* GRC_MISC_CFG core clock reset will clear the memory |
7667 | * enable bit in PCI register 4 and the MSI enable bit | |
7668 | * on some chips, so we save relevant registers here. | |
7669 | */ | |
7670 | tg3_save_pci_state(tp); | |
7671 | ||
d9ab5ad1 | 7672 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
63c3a66f | 7673 | tg3_flag(tp, 5755_PLUS)) |
d9ab5ad1 MC |
7674 | tw32(GRC_FASTBOOT_PC, 0); |
7675 | ||
1da177e4 LT |
7676 | /* |
7677 | * We must avoid the readl() that normally takes place. | |
7678 | * It locks machines, causes machine checks, and other | |
7679 | * fun things. So, temporarily disable the 5701 | |
7680 | * hardware workaround, while we do the reset. | |
7681 | */ | |
1ee582d8 MC |
7682 | write_op = tp->write32; |
7683 | if (write_op == tg3_write_flush_reg32) | |
7684 | tp->write32 = tg3_write32; | |
1da177e4 | 7685 | |
d18edcb2 MC |
7686 | /* Prevent the irq handler from reading or writing PCI registers |
7687 | * during chip reset when the memory enable bit in the PCI command | |
7688 | * register may be cleared. The chip does not generate interrupt | |
7689 | * at this time, but the irq handler may still be called due to irq | |
7690 | * sharing or irqpoll. | |
7691 | */ | |
63c3a66f | 7692 | tg3_flag_set(tp, CHIP_RESETTING); |
f77a6a8e MC |
7693 | for (i = 0; i < tp->irq_cnt; i++) { |
7694 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7695 | if (tnapi->hw_status) { | |
7696 | tnapi->hw_status->status = 0; | |
7697 | tnapi->hw_status->status_tag = 0; | |
7698 | } | |
7699 | tnapi->last_tag = 0; | |
7700 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 7701 | } |
d18edcb2 | 7702 | smp_mb(); |
4f125f42 MC |
7703 | |
7704 | for (i = 0; i < tp->irq_cnt; i++) | |
7705 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 7706 | |
255ca311 MC |
7707 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7708 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7709 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7710 | } | |
7711 | ||
1da177e4 LT |
7712 | /* do the reset */ |
7713 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7714 | ||
63c3a66f | 7715 | if (tg3_flag(tp, PCI_EXPRESS)) { |
88075d91 MC |
7716 | /* Force PCIe 1.0a mode */ |
7717 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7718 | !tg3_flag(tp, 57765_PLUS) && |
88075d91 MC |
7719 | tr32(TG3_PCIE_PHY_TSTCTL) == |
7720 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7721 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7722 | ||
1da177e4 LT |
7723 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
7724 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7725 | val |= (1 << 29); | |
7726 | } | |
7727 | } | |
7728 | ||
b5d3772c MC |
7729 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7730 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7731 | tw32(GRC_VCPU_EXT_CTRL, | |
7732 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7733 | } | |
7734 | ||
f37500d3 | 7735 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
63c3a66f | 7736 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) |
1da177e4 | 7737 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 7738 | |
1da177e4 LT |
7739 | tw32(GRC_MISC_CFG, val); |
7740 | ||
1ee582d8 MC |
7741 | /* restore 5701 hardware bug workaround write method */ |
7742 | tp->write32 = write_op; | |
1da177e4 LT |
7743 | |
7744 | /* Unfortunately, we have to delay before the PCI read back. | |
7745 | * Some 575X chips even will not respond to a PCI cfg access | |
7746 | * when the reset command is given to the chip. | |
7747 | * | |
7748 | * How do these hardware designers expect things to work | |
7749 | * properly if the PCI write is posted for a long period | |
7750 | * of time? It is always necessary to have some method by | |
7751 | * which a register read back can occur to push the write | |
7752 | * out which does the reset. | |
7753 | * | |
7754 | * For most tg3 variants the trick below was working. | |
7755 | * Ho hum... | |
7756 | */ | |
7757 | udelay(120); | |
7758 | ||
7759 | /* Flush PCI posted writes. The normal MMIO registers | |
7760 | * are inaccessible at this time so this is the only | |
7761 | * way to make this reliably (actually, this is no longer | |
7762 | * the case, see above). I tried to use indirect | |
7763 | * register read/write but this upset some 5701 variants. | |
7764 | */ | |
7765 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7766 | ||
7767 | udelay(120); | |
7768 | ||
708ebb3a | 7769 | if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) { |
e7126997 MC |
7770 | u16 val16; |
7771 | ||
1da177e4 LT |
7772 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
7773 | int i; | |
7774 | u32 cfg_val; | |
7775 | ||
7776 | /* Wait for link training to complete. */ | |
7777 | for (i = 0; i < 5000; i++) | |
7778 | udelay(100); | |
7779 | ||
7780 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7781 | pci_write_config_dword(tp->pdev, 0xc4, | |
7782 | cfg_val | (1 << 15)); | |
7783 | } | |
5e7dfd0f | 7784 | |
e7126997 MC |
7785 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
7786 | pci_read_config_word(tp->pdev, | |
708ebb3a | 7787 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 MC |
7788 | &val16); |
7789 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7790 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7791 | /* | |
7792 | * Older PCIe devices only support the 128 byte | |
7793 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 7794 | */ |
63c3a66f | 7795 | if (!tg3_flag(tp, CPMU_PRESENT)) |
e7126997 | 7796 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
5e7dfd0f | 7797 | pci_write_config_word(tp->pdev, |
708ebb3a | 7798 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
e7126997 | 7799 | val16); |
5e7dfd0f | 7800 | |
5e7dfd0f MC |
7801 | /* Clear error status */ |
7802 | pci_write_config_word(tp->pdev, | |
708ebb3a | 7803 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA, |
5e7dfd0f MC |
7804 | PCI_EXP_DEVSTA_CED | |
7805 | PCI_EXP_DEVSTA_NFED | | |
7806 | PCI_EXP_DEVSTA_FED | | |
7807 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
7808 | } |
7809 | ||
ee6a99b5 | 7810 | tg3_restore_pci_state(tp); |
1da177e4 | 7811 | |
63c3a66f JP |
7812 | tg3_flag_clear(tp, CHIP_RESETTING); |
7813 | tg3_flag_clear(tp, ERROR_PROCESSED); | |
d18edcb2 | 7814 | |
ee6a99b5 | 7815 | val = 0; |
63c3a66f | 7816 | if (tg3_flag(tp, 5780_CLASS)) |
4cf78e4f | 7817 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 7818 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
7819 | |
7820 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7821 | tg3_stop_fw(tp); | |
7822 | tw32(0x5000, 0x400); | |
7823 | } | |
7824 | ||
7825 | tw32(GRC_MODE, tp->grc_mode); | |
7826 | ||
7827 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 7828 | val = tr32(0xc4); |
1da177e4 LT |
7829 | |
7830 | tw32(0xc4, val | (1 << 15)); | |
7831 | } | |
7832 | ||
7833 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7834 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7835 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7836 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7837 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7838 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7839 | } | |
7840 | ||
f07e9af3 | 7841 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
9e975cc2 | 7842 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; |
d2394e6b | 7843 | val = tp->mac_mode; |
f07e9af3 | 7844 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
9e975cc2 | 7845 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; |
d2394e6b | 7846 | val = tp->mac_mode; |
1da177e4 | 7847 | } else |
d2394e6b MC |
7848 | val = 0; |
7849 | ||
7850 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
7851 | udelay(40); |
7852 | ||
77b483f1 MC |
7853 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
7854 | ||
7a6f4369 MC |
7855 | err = tg3_poll_fw(tp); |
7856 | if (err) | |
7857 | return err; | |
1da177e4 | 7858 | |
0a9140cf MC |
7859 | tg3_mdio_start(tp); |
7860 | ||
63c3a66f | 7861 | if (tg3_flag(tp, PCI_EXPRESS) && |
f6eb9b1f MC |
7862 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7863 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 7864 | !tg3_flag(tp, 57765_PLUS)) { |
ab0049b4 | 7865 | val = tr32(0x7c00); |
1da177e4 LT |
7866 | |
7867 | tw32(0x7c00, val | (1 << 25)); | |
7868 | } | |
7869 | ||
d78b59f5 MC |
7870 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
7871 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
7872 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
7873 | } | |
7874 | ||
1da177e4 | 7875 | /* Reprobe ASF enable state. */ |
63c3a66f JP |
7876 | tg3_flag_clear(tp, ENABLE_ASF); |
7877 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
7878 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
7879 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7880 | u32 nic_cfg; | |
7881 | ||
7882 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7883 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f | 7884 | tg3_flag_set(tp, ENABLE_ASF); |
4ba526ce | 7885 | tp->last_event_jiffies = jiffies; |
63c3a66f JP |
7886 | if (tg3_flag(tp, 5750_PLUS)) |
7887 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
7888 | } |
7889 | } | |
7890 | ||
7891 | return 0; | |
7892 | } | |
7893 | ||
92feeabf MC |
7894 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, |
7895 | struct rtnl_link_stats64 *); | |
7896 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *, | |
7897 | struct tg3_ethtool_stats *); | |
7898 | ||
1da177e4 | 7899 | /* tp->lock is held. */ |
944d980e | 7900 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
7901 | { |
7902 | int err; | |
7903 | ||
7904 | tg3_stop_fw(tp); | |
7905 | ||
944d980e | 7906 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 7907 | |
b3b7d6be | 7908 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
7909 | err = tg3_chip_reset(tp); |
7910 | ||
daba2a63 MC |
7911 | __tg3_set_mac_addr(tp, 0); |
7912 | ||
944d980e MC |
7913 | tg3_write_sig_legacy(tp, kind); |
7914 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 | 7915 | |
92feeabf MC |
7916 | if (tp->hw_stats) { |
7917 | /* Save the stats across chip resets... */ | |
7918 | tg3_get_stats64(tp->dev, &tp->net_stats_prev), | |
7919 | tg3_get_estats(tp, &tp->estats_prev); | |
7920 | ||
7921 | /* And make sure the next sample is new data */ | |
7922 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
7923 | } | |
7924 | ||
1da177e4 LT |
7925 | if (err) |
7926 | return err; | |
7927 | ||
7928 | return 0; | |
7929 | } | |
7930 | ||
1da177e4 LT |
7931 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
7932 | { | |
7933 | struct tg3 *tp = netdev_priv(dev); | |
7934 | struct sockaddr *addr = p; | |
986e0aeb | 7935 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 7936 | |
f9804ddb MC |
7937 | if (!is_valid_ether_addr(addr->sa_data)) |
7938 | return -EINVAL; | |
7939 | ||
1da177e4 LT |
7940 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7941 | ||
e75f7c90 MC |
7942 | if (!netif_running(dev)) |
7943 | return 0; | |
7944 | ||
63c3a66f | 7945 | if (tg3_flag(tp, ENABLE_ASF)) { |
986e0aeb | 7946 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 7947 | |
986e0aeb MC |
7948 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
7949 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7950 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7951 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7952 | ||
7953 | /* Skip MAC addr 1 if ASF is using it. */ | |
7954 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7955 | !(addr1_high == 0 && addr1_low == 0)) | |
7956 | skip_mac_1 = 1; | |
58712ef9 | 7957 | } |
986e0aeb MC |
7958 | spin_lock_bh(&tp->lock); |
7959 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7960 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 7961 | |
b9ec6c1b | 7962 | return err; |
1da177e4 LT |
7963 | } |
7964 | ||
7965 | /* tp->lock is held. */ | |
7966 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7967 | dma_addr_t mapping, u32 maxlen_flags, | |
7968 | u32 nic_addr) | |
7969 | { | |
7970 | tg3_write_mem(tp, | |
7971 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7972 | ((u64) mapping >> 32)); | |
7973 | tg3_write_mem(tp, | |
7974 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7975 | ((u64) mapping & 0xffffffff)); | |
7976 | tg3_write_mem(tp, | |
7977 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7978 | maxlen_flags); | |
7979 | ||
63c3a66f | 7980 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
7981 | tg3_write_mem(tp, |
7982 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7983 | nic_addr); | |
7984 | } | |
7985 | ||
7986 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7987 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7988 | { |
b6080e12 MC |
7989 | int i; |
7990 | ||
63c3a66f | 7991 | if (!tg3_flag(tp, ENABLE_TSS)) { |
b6080e12 MC |
7992 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
7993 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7994 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
7995 | } else { |
7996 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7997 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7998 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 7999 | } |
b6080e12 | 8000 | |
63c3a66f | 8001 | if (!tg3_flag(tp, ENABLE_RSS)) { |
19cfaecc MC |
8002 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
8003 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
8004 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
8005 | } else { | |
b6080e12 MC |
8006 | tw32(HOSTCC_RXCOL_TICKS, 0); |
8007 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
8008 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 8009 | } |
b6080e12 | 8010 | |
63c3a66f | 8011 | if (!tg3_flag(tp, 5705_PLUS)) { |
15f9850d DM |
8012 | u32 val = ec->stats_block_coalesce_usecs; |
8013 | ||
b6080e12 MC |
8014 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
8015 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
8016 | ||
15f9850d DM |
8017 | if (!netif_carrier_ok(tp->dev)) |
8018 | val = 0; | |
8019 | ||
8020 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
8021 | } | |
b6080e12 MC |
8022 | |
8023 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
8024 | u32 reg; | |
8025 | ||
8026 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
8027 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
8028 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
8029 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
8030 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
8031 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc | 8032 | |
63c3a66f | 8033 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
8034 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; |
8035 | tw32(reg, ec->tx_coalesce_usecs); | |
8036 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
8037 | tw32(reg, ec->tx_max_coalesced_frames); | |
8038 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
8039 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
8040 | } | |
b6080e12 MC |
8041 | } |
8042 | ||
8043 | for (; i < tp->irq_max - 1; i++) { | |
8044 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 8045 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 8046 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc | 8047 | |
63c3a66f | 8048 | if (tg3_flag(tp, ENABLE_TSS)) { |
19cfaecc MC |
8049 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); |
8050 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
8051 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
8052 | } | |
b6080e12 | 8053 | } |
15f9850d | 8054 | } |
1da177e4 | 8055 | |
2d31ecaf MC |
8056 | /* tp->lock is held. */ |
8057 | static void tg3_rings_reset(struct tg3 *tp) | |
8058 | { | |
8059 | int i; | |
f77a6a8e | 8060 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
8061 | struct tg3_napi *tnapi = &tp->napi[0]; |
8062 | ||
8063 | /* Disable all transmit rings but the first. */ | |
63c3a66f | 8064 | if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 8065 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; |
63c3a66f | 8066 | else if (tg3_flag(tp, 5717_PLUS)) |
3d37728b | 8067 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
55086ad9 | 8068 | else if (tg3_flag(tp, 57765_CLASS)) |
b703df6f | 8069 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; |
2d31ecaf MC |
8070 | else |
8071 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
8072 | ||
8073 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
8074 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
8075 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
8076 | BDINFO_FLAGS_DISABLED); | |
8077 | ||
8078 | ||
8079 | /* Disable all receive return rings but the first. */ | |
63c3a66f | 8080 | if (tg3_flag(tp, 5717_PLUS)) |
f6eb9b1f | 8081 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
63c3a66f | 8082 | else if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 8083 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f | 8084 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
55086ad9 | 8085 | tg3_flag(tp, 57765_CLASS)) |
2d31ecaf MC |
8086 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
8087 | else | |
8088 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
8089 | ||
8090 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
8091 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
8092 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
8093 | BDINFO_FLAGS_DISABLED); | |
8094 | ||
8095 | /* Disable interrupts */ | |
8096 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
0e6cf6a9 MC |
8097 | tp->napi[0].chk_msi_cnt = 0; |
8098 | tp->napi[0].last_rx_cons = 0; | |
8099 | tp->napi[0].last_tx_cons = 0; | |
2d31ecaf MC |
8100 | |
8101 | /* Zero mailbox registers. */ | |
63c3a66f | 8102 | if (tg3_flag(tp, SUPPORT_MSIX)) { |
6fd45cb8 | 8103 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
8104 | tp->napi[i].tx_prod = 0; |
8105 | tp->napi[i].tx_cons = 0; | |
63c3a66f | 8106 | if (tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 8107 | tw32_mailbox(tp->napi[i].prodmbox, 0); |
f77a6a8e MC |
8108 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
8109 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7f230735 | 8110 | tp->napi[i].chk_msi_cnt = 0; |
0e6cf6a9 MC |
8111 | tp->napi[i].last_rx_cons = 0; |
8112 | tp->napi[i].last_tx_cons = 0; | |
f77a6a8e | 8113 | } |
63c3a66f | 8114 | if (!tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 8115 | tw32_mailbox(tp->napi[0].prodmbox, 0); |
f77a6a8e MC |
8116 | } else { |
8117 | tp->napi[0].tx_prod = 0; | |
8118 | tp->napi[0].tx_cons = 0; | |
8119 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
8120 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
8121 | } | |
2d31ecaf MC |
8122 | |
8123 | /* Make sure the NIC-based send BD rings are disabled. */ | |
63c3a66f | 8124 | if (!tg3_flag(tp, 5705_PLUS)) { |
2d31ecaf MC |
8125 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
8126 | for (i = 0; i < 16; i++) | |
8127 | tw32_tx_mbox(mbox + i * 8, 0); | |
8128 | } | |
8129 | ||
8130 | txrcb = NIC_SRAM_SEND_RCB; | |
8131 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
8132 | ||
8133 | /* Clear status block in ram. */ | |
8134 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8135 | ||
8136 | /* Set status block DMA address */ | |
8137 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
8138 | ((u64) tnapi->status_mapping >> 32)); | |
8139 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8140 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
8141 | ||
f77a6a8e MC |
8142 | if (tnapi->tx_ring) { |
8143 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8144 | (TG3_TX_RING_SIZE << | |
8145 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8146 | NIC_SRAM_TX_BUFFER_DESC); | |
8147 | txrcb += TG3_BDINFO_SIZE; | |
8148 | } | |
8149 | ||
8150 | if (tnapi->rx_rcb) { | |
8151 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
8152 | (tp->rx_ret_ring_mask + 1) << |
8153 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
8154 | rxrcb += TG3_BDINFO_SIZE; |
8155 | } | |
8156 | ||
8157 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 8158 | |
f77a6a8e MC |
8159 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
8160 | u64 mapping = (u64)tnapi->status_mapping; | |
8161 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
8162 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
8163 | ||
8164 | /* Clear status block in ram. */ | |
8165 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8166 | ||
19cfaecc MC |
8167 | if (tnapi->tx_ring) { |
8168 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8169 | (TG3_TX_RING_SIZE << | |
8170 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8171 | NIC_SRAM_TX_BUFFER_DESC); | |
8172 | txrcb += TG3_BDINFO_SIZE; | |
8173 | } | |
f77a6a8e MC |
8174 | |
8175 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 8176 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
8177 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
8178 | ||
8179 | stblk += 8; | |
f77a6a8e MC |
8180 | rxrcb += TG3_BDINFO_SIZE; |
8181 | } | |
2d31ecaf MC |
8182 | } |
8183 | ||
eb07a940 MC |
8184 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
8185 | { | |
8186 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
8187 | ||
63c3a66f JP |
8188 | if (!tg3_flag(tp, 5750_PLUS) || |
8189 | tg3_flag(tp, 5780_CLASS) || | |
eb07a940 | 8190 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
513aa6ea MC |
8191 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
8192 | tg3_flag(tp, 57765_PLUS)) | |
eb07a940 MC |
8193 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; |
8194 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
8195 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
8196 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
8197 | else | |
8198 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
8199 | ||
8200 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
8201 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
8202 | ||
8203 | val = min(nic_rep_thresh, host_rep_thresh); | |
8204 | tw32(RCVBDI_STD_THRESH, val); | |
8205 | ||
63c3a66f | 8206 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8207 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); |
8208 | ||
63c3a66f | 8209 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
eb07a940 MC |
8210 | return; |
8211 | ||
513aa6ea | 8212 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; |
eb07a940 MC |
8213 | |
8214 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
8215 | ||
8216 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
8217 | tw32(RCVBDI_JUMBO_THRESH, val); | |
8218 | ||
63c3a66f | 8219 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8220 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); |
8221 | } | |
8222 | ||
bcebcc46 MC |
8223 | void tg3_rss_init_indir_tbl(struct tg3 *tp) |
8224 | { | |
8225 | int i; | |
8226 | ||
8227 | if (!tg3_flag(tp, SUPPORT_MSIX)) | |
8228 | return; | |
8229 | ||
8230 | if (tp->irq_cnt <= 2) | |
8231 | memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); | |
8232 | else | |
8233 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) | |
8234 | tp->rss_ind_tbl[i] = i % (tp->irq_cnt - 1); | |
8235 | } | |
8236 | ||
8237 | void tg3_rss_write_indir_tbl(struct tg3 *tp) | |
8238 | { | |
8239 | int i = 0; | |
8240 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8241 | ||
8242 | while (i < TG3_RSS_INDIR_TBL_SIZE) { | |
8243 | u32 val = tp->rss_ind_tbl[i]; | |
8244 | i++; | |
8245 | for (; i % 8; i++) { | |
8246 | val <<= 4; | |
8247 | val |= tp->rss_ind_tbl[i]; | |
8248 | } | |
8249 | tw32(reg, val); | |
8250 | reg += 4; | |
8251 | } | |
8252 | } | |
8253 | ||
1da177e4 | 8254 | /* tp->lock is held. */ |
8e7a22e3 | 8255 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
8256 | { |
8257 | u32 val, rdmac_mode; | |
8258 | int i, err, limit; | |
8fea32b9 | 8259 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
8260 | |
8261 | tg3_disable_ints(tp); | |
8262 | ||
8263 | tg3_stop_fw(tp); | |
8264 | ||
8265 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
8266 | ||
63c3a66f | 8267 | if (tg3_flag(tp, INIT_COMPLETE)) |
e6de8ad1 | 8268 | tg3_abort_hw(tp, 1); |
1da177e4 | 8269 | |
699c0193 MC |
8270 | /* Enable MAC control of LPI */ |
8271 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
8272 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
8273 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
8274 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
8275 | ||
8276 | tw32_f(TG3_CPMU_EEE_CTRL, | |
8277 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
8278 | ||
a386b901 MC |
8279 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
8280 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
8281 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
8282 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
8283 | ||
8284 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8285 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
8286 | ||
63c3a66f | 8287 | if (tg3_flag(tp, ENABLE_APE)) |
a386b901 MC |
8288 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; |
8289 | ||
8290 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
8291 | ||
8292 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
8293 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
8294 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
8295 | ||
8296 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 8297 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 8298 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
8299 | } |
8300 | ||
603f1173 | 8301 | if (reset_phy) |
d4d2c558 MC |
8302 | tg3_phy_reset(tp); |
8303 | ||
1da177e4 LT |
8304 | err = tg3_chip_reset(tp); |
8305 | if (err) | |
8306 | return err; | |
8307 | ||
8308 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
8309 | ||
bcb37f6c | 8310 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
8311 | val = tr32(TG3_CPMU_CTRL); |
8312 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
8313 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
8314 | |
8315 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8316 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8317 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8318 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8319 | ||
8320 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
8321 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
8322 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
8323 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
8324 | ||
8325 | val = tr32(TG3_CPMU_HST_ACC); | |
8326 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
8327 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
8328 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
8329 | } |
8330 | ||
33466d93 MC |
8331 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8332 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
8333 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
8334 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
8335 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
8336 | |
8337 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
8338 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
8339 | ||
8340 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 8341 | |
f40386c8 MC |
8342 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
8343 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
8344 | } |
8345 | ||
63c3a66f | 8346 | if (tg3_flag(tp, L1PLLPD_EN)) { |
614b0590 MC |
8347 | u32 grc_mode = tr32(GRC_MODE); |
8348 | ||
8349 | /* Access the lower 1K of PL PCIE block registers. */ | |
8350 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8351 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
8352 | ||
8353 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
8354 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
8355 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
8356 | ||
8357 | tw32(GRC_MODE, grc_mode); | |
8358 | } | |
8359 | ||
55086ad9 | 8360 | if (tg3_flag(tp, 57765_CLASS)) { |
5093eedc MC |
8361 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
8362 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 8363 | |
5093eedc MC |
8364 | /* Access the lower 1K of PL PCIE block registers. */ |
8365 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8366 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 8367 | |
5093eedc MC |
8368 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
8369 | TG3_PCIE_PL_LO_PHYCTL5); | |
8370 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
8371 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 8372 | |
5093eedc MC |
8373 | tw32(GRC_MODE, grc_mode); |
8374 | } | |
a977dbe8 | 8375 | |
1ff30a59 MC |
8376 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { |
8377 | u32 grc_mode = tr32(GRC_MODE); | |
8378 | ||
8379 | /* Access the lower 1K of DL PCIE block registers. */ | |
8380 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8381 | tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); | |
8382 | ||
8383 | val = tr32(TG3_PCIE_TLDLPL_PORT + | |
8384 | TG3_PCIE_DL_LO_FTSMAX); | |
8385 | val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; | |
8386 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, | |
8387 | val | TG3_PCIE_DL_LO_FTSMAX_VAL); | |
8388 | ||
8389 | tw32(GRC_MODE, grc_mode); | |
8390 | } | |
8391 | ||
a977dbe8 MC |
8392 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
8393 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8394 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8395 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
8396 | } |
8397 | ||
1da177e4 LT |
8398 | /* This works around an issue with Athlon chipsets on |
8399 | * B3 tigon3 silicon. This bit has no effect on any | |
8400 | * other revision. But do not set this on PCI Express | |
795d01c5 | 8401 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 8402 | */ |
63c3a66f JP |
8403 | if (!tg3_flag(tp, CPMU_PRESENT)) { |
8404 | if (!tg3_flag(tp, PCI_EXPRESS)) | |
795d01c5 MC |
8405 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; |
8406 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8407 | } | |
1da177e4 LT |
8408 | |
8409 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 8410 | tg3_flag(tp, PCIX_MODE)) { |
1da177e4 LT |
8411 | val = tr32(TG3PCI_PCISTATE); |
8412 | val |= PCISTATE_RETRY_SAME_DMA; | |
8413 | tw32(TG3PCI_PCISTATE, val); | |
8414 | } | |
8415 | ||
63c3a66f | 8416 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
8417 | /* Allow reads and writes to the |
8418 | * APE register and memory space. | |
8419 | */ | |
8420 | val = tr32(TG3PCI_PCISTATE); | |
8421 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
8422 | PCISTATE_ALLOW_APE_SHMEM_WR | |
8423 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
8424 | tw32(TG3PCI_PCISTATE, val); |
8425 | } | |
8426 | ||
1da177e4 LT |
8427 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
8428 | /* Enable some hw fixes. */ | |
8429 | val = tr32(TG3PCI_MSI_DATA); | |
8430 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
8431 | tw32(TG3PCI_MSI_DATA, val); | |
8432 | } | |
8433 | ||
8434 | /* Descriptor ring init may make accesses to the | |
8435 | * NIC SRAM area to setup the TX descriptors, so we | |
8436 | * can only do this after the hardware has been | |
8437 | * successfully reset. | |
8438 | */ | |
32d8c572 MC |
8439 | err = tg3_init_rings(tp); |
8440 | if (err) | |
8441 | return err; | |
1da177e4 | 8442 | |
63c3a66f | 8443 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
8444 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
8445 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
8446 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
8447 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
55086ad9 | 8448 | if (!tg3_flag(tp, 57765_CLASS) && |
0aebff48 MC |
8449 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) |
8450 | val |= DMA_RWCTRL_TAGGED_STAT_WA; | |
cbf9ca6c MC |
8451 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
8452 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
8453 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
8454 | /* This value is determined during the probe time DMA |
8455 | * engine test, tg3_test_dma. | |
8456 | */ | |
8457 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
8458 | } | |
1da177e4 LT |
8459 | |
8460 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
8461 | GRC_MODE_4X_NIC_SEND_RINGS | | |
8462 | GRC_MODE_NO_TX_PHDR_CSUM | | |
8463 | GRC_MODE_NO_RX_PHDR_CSUM); | |
8464 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
8465 | |
8466 | /* Pseudo-header checksum is done by hardware logic and not | |
8467 | * the offload processers, so make the chip do the pseudo- | |
8468 | * header checksums on receive. For transmit it is more | |
8469 | * convenient to do the pseudo-header checksum in software | |
8470 | * as Linux does that on transmit for us in all cases. | |
8471 | */ | |
8472 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
8473 | |
8474 | tw32(GRC_MODE, | |
8475 | tp->grc_mode | | |
8476 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
8477 | ||
8478 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
8479 | val = tr32(GRC_MISC_CFG); | |
8480 | val &= ~0xff; | |
8481 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
8482 | tw32(GRC_MISC_CFG, val); | |
8483 | ||
8484 | /* Initialize MBUF/DESC pool. */ | |
63c3a66f | 8485 | if (tg3_flag(tp, 5750_PLUS)) { |
1da177e4 LT |
8486 | /* Do nothing. */ |
8487 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8488 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8489 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8490 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8491 | else | |
8492 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8493 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8494 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
63c3a66f | 8495 | } else if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8496 | int fw_len; |
8497 | ||
077f849d | 8498 | fw_len = tp->fw_len; |
1da177e4 LT |
8499 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
8500 | tw32(BUFMGR_MB_POOL_ADDR, | |
8501 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8502 | tw32(BUFMGR_MB_POOL_SIZE, | |
8503 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8504 | } | |
1da177e4 | 8505 | |
0f893dc6 | 8506 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
8507 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
8508 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8509 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8510 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8511 | tw32(BUFMGR_MB_HIGH_WATER, | |
8512 | tp->bufmgr_config.mbuf_high_water); | |
8513 | } else { | |
8514 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8515 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8516 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8517 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8518 | tw32(BUFMGR_MB_HIGH_WATER, | |
8519 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8520 | } | |
8521 | tw32(BUFMGR_DMA_LOW_WATER, | |
8522 | tp->bufmgr_config.dma_low_water); | |
8523 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8524 | tp->bufmgr_config.dma_high_water); | |
8525 | ||
d309a46e MC |
8526 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8527 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8528 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
4d958473 MC |
8529 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8530 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
8531 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
8532 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
d309a46e | 8533 | tw32(BUFMGR_MODE, val); |
1da177e4 LT |
8534 | for (i = 0; i < 2000; i++) { |
8535 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8536 | break; | |
8537 | udelay(10); | |
8538 | } | |
8539 | if (i >= 2000) { | |
05dbe005 | 8540 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
8541 | return -ENODEV; |
8542 | } | |
8543 | ||
eb07a940 MC |
8544 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
8545 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
b5d3772c | 8546 | |
eb07a940 | 8547 | tg3_setup_rxbd_thresholds(tp); |
1da177e4 LT |
8548 | |
8549 | /* Initialize TG3_BDINFO's at: | |
8550 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8551 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8552 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8553 | * | |
8554 | * like so: | |
8555 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8556 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8557 | * ring attribute flags | |
8558 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8559 | * | |
8560 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8561 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8562 | * | |
8563 | * The size of each ring is fixed in the firmware, but the location is | |
8564 | * configurable. | |
8565 | */ | |
8566 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 8567 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 8568 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8569 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
63c3a66f | 8570 | if (!tg3_flag(tp, 5717_PLUS)) |
87668d35 MC |
8571 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
8572 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 8573 | |
fdb72b38 | 8574 | /* Disable the mini ring */ |
63c3a66f | 8575 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8576 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8577 | BDINFO_FLAGS_DISABLED); | |
8578 | ||
fdb72b38 MC |
8579 | /* Program the jumbo buffer descriptor ring control |
8580 | * blocks on those devices that have them. | |
8581 | */ | |
a0512944 | 8582 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
63c3a66f | 8583 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { |
1da177e4 | 8584 | |
63c3a66f | 8585 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { |
1da177e4 | 8586 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 8587 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 8588 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8589 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
8590 | val = TG3_RX_JMB_RING_SIZE(tp) << |
8591 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 8592 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 8593 | val | BDINFO_FLAGS_USE_EXT_RECV); |
63c3a66f | 8594 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || |
55086ad9 | 8595 | tg3_flag(tp, 57765_CLASS)) |
87668d35 MC |
8596 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
8597 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
8598 | } else { |
8599 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8600 | BDINFO_FLAGS_DISABLED); | |
8601 | } | |
8602 | ||
63c3a66f | 8603 | if (tg3_flag(tp, 57765_PLUS)) { |
fa6b2aae | 8604 | val = TG3_RX_STD_RING_SIZE(tp); |
7cb32cf2 MC |
8605 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
8606 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8607 | } else | |
04380d40 | 8608 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 8609 | } else |
de9f5230 | 8610 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
8611 | |
8612 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 8613 | |
411da640 | 8614 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 8615 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 8616 | |
63c3a66f JP |
8617 | tpr->rx_jmb_prod_idx = |
8618 | tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; | |
66711e66 | 8619 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 8620 | |
2d31ecaf MC |
8621 | tg3_rings_reset(tp); |
8622 | ||
1da177e4 | 8623 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 8624 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
8625 | |
8626 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
8627 | tw32(MAC_RX_MTU_SIZE, |
8628 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
8629 | |
8630 | /* The slot time is changed by tg3_setup_phy if we | |
8631 | * run at gigabit with half duplex. | |
8632 | */ | |
f2096f94 MC |
8633 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
8634 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8635 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
8636 | ||
8637 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
8638 | val |= tr32(MAC_TX_LENGTHS) & | |
8639 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
8640 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
8641 | ||
8642 | tw32(MAC_TX_LENGTHS, val); | |
1da177e4 LT |
8643 | |
8644 | /* Receive rules. */ | |
8645 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8646 | tw32(RCVLPC_CONFIG, 0x0181); | |
8647 | ||
8648 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8649 | * the RCVLPC_STATE_ENABLE mask. | |
8650 | */ | |
8651 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8652 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8653 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8654 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8655 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 8656 | |
deabaac8 | 8657 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
8658 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
8659 | ||
57e6983c | 8660 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
8661 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
8662 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
8663 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
8664 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8665 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8666 | ||
c5908939 MC |
8667 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8668 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8669 | if (tg3_flag(tp, TSO_CAPABLE) && |
c13e3713 | 8670 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
8671 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
8672 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8673 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8674 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8675 | } | |
8676 | } | |
8677 | ||
63c3a66f | 8678 | if (tg3_flag(tp, PCI_EXPRESS)) |
85e94ced MC |
8679 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
8680 | ||
55086ad9 MC |
8681 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) |
8682 | rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR; | |
8683 | ||
63c3a66f JP |
8684 | if (tg3_flag(tp, HW_TSO_1) || |
8685 | tg3_flag(tp, HW_TSO_2) || | |
8686 | tg3_flag(tp, HW_TSO_3)) | |
027455ad MC |
8687 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
8688 | ||
108a6c16 | 8689 | if (tg3_flag(tp, 57765_PLUS) || |
e849cdc3 | 8690 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
027455ad MC |
8691 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
8692 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 8693 | |
f2096f94 MC |
8694 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
8695 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
8696 | ||
41a8a7ee MC |
8697 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
8698 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8699 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8700 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
63c3a66f | 8701 | tg3_flag(tp, 57765_PLUS)) { |
41a8a7ee | 8702 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
d78b59f5 MC |
8703 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8704 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b4495ed8 MC |
8705 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
8706 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8707 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8708 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8709 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8710 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 8711 | } |
41a8a7ee MC |
8712 | tw32(TG3_RDMA_RSRVCTRL_REG, |
8713 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8714 | } | |
8715 | ||
d78b59f5 MC |
8716 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8717 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
8718 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
8719 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8720 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8721 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8722 | } | |
8723 | ||
1da177e4 | 8724 | /* Receive/send statistics. */ |
63c3a66f | 8725 | if (tg3_flag(tp, 5750_PLUS)) { |
1661394e MC |
8726 | val = tr32(RCVLPC_STATS_ENABLE); |
8727 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
8728 | tw32(RCVLPC_STATS_ENABLE, val); | |
8729 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
63c3a66f | 8730 | tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8731 | val = tr32(RCVLPC_STATS_ENABLE); |
8732 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8733 | tw32(RCVLPC_STATS_ENABLE, val); | |
8734 | } else { | |
8735 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8736 | } | |
8737 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8738 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8739 | tw32(SNDDATAI_STATSCTRL, | |
8740 | (SNDDATAI_SCTRL_ENABLE | | |
8741 | SNDDATAI_SCTRL_FASTUPD)); | |
8742 | ||
8743 | /* Setup host coalescing engine. */ | |
8744 | tw32(HOSTCC_MODE, 0); | |
8745 | for (i = 0; i < 2000; i++) { | |
8746 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8747 | break; | |
8748 | udelay(10); | |
8749 | } | |
8750 | ||
d244c892 | 8751 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 8752 | |
63c3a66f | 8753 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8754 | /* Status/statistics block address. See tg3_timer, |
8755 | * the tg3_periodic_fetch_stats call there, and | |
8756 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8757 | */ | |
1da177e4 LT |
8758 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
8759 | ((u64) tp->stats_mapping >> 32)); | |
8760 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8761 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8762 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 8763 | |
1da177e4 | 8764 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
8765 | |
8766 | /* Clear statistics and status block memory areas */ | |
8767 | for (i = NIC_SRAM_STATS_BLK; | |
8768 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8769 | i += sizeof(u32)) { | |
8770 | tg3_write_mem(tp, i, 0); | |
8771 | udelay(40); | |
8772 | } | |
1da177e4 LT |
8773 | } |
8774 | ||
8775 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8776 | ||
8777 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8778 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
63c3a66f | 8779 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8780 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); |
8781 | ||
f07e9af3 MC |
8782 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
8783 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
8784 | /* reset to prevent losing 1st rx packet intermittently */ |
8785 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8786 | udelay(10); | |
8787 | } | |
8788 | ||
3bda1258 | 8789 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | |
9e975cc2 MC |
8790 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | |
8791 | MAC_MODE_FHDE_ENABLE; | |
8792 | if (tg3_flag(tp, ENABLE_APE)) | |
8793 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
63c3a66f | 8794 | if (!tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 8795 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
8796 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
8797 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
8798 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
8799 | udelay(40); | |
8800 | ||
314fba34 | 8801 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
63c3a66f | 8802 | * If TG3_FLAG_IS_NIC is zero, we should read the |
314fba34 MC |
8803 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
8804 | * whether used as inputs or outputs, are set by boot code after | |
8805 | * reset. | |
8806 | */ | |
63c3a66f | 8807 | if (!tg3_flag(tp, IS_NIC)) { |
314fba34 MC |
8808 | u32 gpio_mask; |
8809 | ||
9d26e213 MC |
8810 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
8811 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8812 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
8813 | |
8814 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8815 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8816 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8817 | ||
af36e6b6 MC |
8818 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
8819 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8820 | ||
aaf84465 | 8821 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
8822 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
8823 | ||
8824 | /* GPIO1 must be driven high for eeprom write protect */ | |
63c3a66f | 8825 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) |
9d26e213 MC |
8826 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
8827 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 8828 | } |
1da177e4 LT |
8829 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
8830 | udelay(100); | |
8831 | ||
63c3a66f | 8832 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) { |
baf8a94a MC |
8833 | val = tr32(MSGINT_MODE); |
8834 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
5b39de91 MC |
8835 | if (!tg3_flag(tp, 1SHOT_MSI)) |
8836 | val |= MSGINT_MODE_ONE_SHOT_DISABLE; | |
baf8a94a MC |
8837 | tw32(MSGINT_MODE, val); |
8838 | } | |
8839 | ||
63c3a66f | 8840 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
8841 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); |
8842 | udelay(40); | |
8843 | } | |
8844 | ||
8845 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8846 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8847 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8848 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8849 | WDMAC_MODE_LNGREAD_ENAB); | |
8850 | ||
c5908939 MC |
8851 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8852 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 8853 | if (tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 LT |
8854 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
8855 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8856 | /* nothing */ | |
8857 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 8858 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
8859 | val |= WDMAC_MODE_RX_ACCEL; |
8860 | } | |
8861 | } | |
8862 | ||
d9ab5ad1 | 8863 | /* Enable host coalescing bug fix */ |
63c3a66f | 8864 | if (tg3_flag(tp, 5755_PLUS)) |
f51f3562 | 8865 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 8866 | |
788a035e MC |
8867 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
8868 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8869 | ||
1da177e4 LT |
8870 | tw32_f(WDMAC_MODE, val); |
8871 | udelay(40); | |
8872 | ||
63c3a66f | 8873 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
8874 | u16 pcix_cmd; |
8875 | ||
8876 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8877 | &pcix_cmd); | |
1da177e4 | 8878 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
8879 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
8880 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8881 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
8882 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
8883 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8884 | } |
9974a356 MC |
8885 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
8886 | pcix_cmd); | |
1da177e4 LT |
8887 | } |
8888 | ||
8889 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8890 | udelay(40); | |
8891 | ||
8892 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
63c3a66f | 8893 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 | 8894 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); |
9936bcf6 MC |
8895 | |
8896 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8897 | tw32(SNDDATAC_MODE, | |
8898 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8899 | else | |
8900 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8901 | ||
1da177e4 LT |
8902 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8903 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 8904 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
63c3a66f | 8905 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
7cb32cf2 MC |
8906 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
8907 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 8908 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
63c3a66f JP |
8909 | if (tg3_flag(tp, HW_TSO_1) || |
8910 | tg3_flag(tp, HW_TSO_2) || | |
8911 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 | 8912 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); |
baf8a94a | 8913 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
63c3a66f | 8914 | if (tg3_flag(tp, ENABLE_TSS)) |
baf8a94a MC |
8915 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
8916 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
8917 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
8918 | ||
8919 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8920 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8921 | if (err) | |
8922 | return err; | |
8923 | } | |
8924 | ||
63c3a66f | 8925 | if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8926 | err = tg3_load_tso_firmware(tp); |
8927 | if (err) | |
8928 | return err; | |
8929 | } | |
1da177e4 LT |
8930 | |
8931 | tp->tx_mode = TX_MODE_ENABLE; | |
f2096f94 | 8932 | |
63c3a66f | 8933 | if (tg3_flag(tp, 5755_PLUS) || |
b1d05210 MC |
8934 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
8935 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
f2096f94 MC |
8936 | |
8937 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
8938 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
8939 | tp->tx_mode &= ~val; | |
8940 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
8941 | } | |
8942 | ||
1da177e4 LT |
8943 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
8944 | udelay(100); | |
8945 | ||
63c3a66f | 8946 | if (tg3_flag(tp, ENABLE_RSS)) { |
bcebcc46 | 8947 | tg3_rss_write_indir_tbl(tp); |
baf8a94a MC |
8948 | |
8949 | /* Setup the "secret" hash key. */ | |
8950 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8951 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8952 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8953 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8954 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8955 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8956 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8957 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8958 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8959 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8960 | } | |
8961 | ||
1da177e4 | 8962 | tp->rx_mode = RX_MODE_ENABLE; |
63c3a66f | 8963 | if (tg3_flag(tp, 5755_PLUS)) |
af36e6b6 MC |
8964 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
8965 | ||
63c3a66f | 8966 | if (tg3_flag(tp, ENABLE_RSS)) |
baf8a94a MC |
8967 | tp->rx_mode |= RX_MODE_RSS_ENABLE | |
8968 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8969 | RX_MODE_RSS_IPV6_HASH_EN | | |
8970 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8971 | RX_MODE_RSS_IPV4_HASH_EN | | |
8972 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8973 | ||
1da177e4 LT |
8974 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
8975 | udelay(10); | |
8976 | ||
1da177e4 LT |
8977 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
8978 | ||
8979 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 8980 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
8981 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
8982 | udelay(10); | |
8983 | } | |
8984 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8985 | udelay(10); | |
8986 | ||
f07e9af3 | 8987 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 8988 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 8989 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
8990 | /* Set drive transmission level to 1.2V */ |
8991 | /* only if the signal pre-emphasis bit is not set */ | |
8992 | val = tr32(MAC_SERDES_CFG); | |
8993 | val &= 0xfffff000; | |
8994 | val |= 0x880; | |
8995 | tw32(MAC_SERDES_CFG, val); | |
8996 | } | |
8997 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8998 | tw32(MAC_SERDES_CFG, 0x616000); | |
8999 | } | |
9000 | ||
9001 | /* Prevent chip from dropping frames when flow control | |
9002 | * is enabled. | |
9003 | */ | |
55086ad9 | 9004 | if (tg3_flag(tp, 57765_CLASS)) |
666bc831 MC |
9005 | val = 1; |
9006 | else | |
9007 | val = 2; | |
9008 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
9009 | |
9010 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 9011 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 | 9012 | /* Use hardware link auto-negotiation */ |
63c3a66f | 9013 | tg3_flag_set(tp, HW_AUTONEG); |
1da177e4 LT |
9014 | } |
9015 | ||
f07e9af3 | 9016 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
6ff6f81d | 9017 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
d4d2c558 MC |
9018 | u32 tmp; |
9019 | ||
9020 | tmp = tr32(SERDES_RX_CTRL); | |
9021 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
9022 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
9023 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
9024 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
9025 | } | |
9026 | ||
63c3a66f | 9027 | if (!tg3_flag(tp, USE_PHYLIB)) { |
80096068 MC |
9028 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
9029 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
9030 | tp->link_config.speed = tp->link_config.orig_speed; |
9031 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
9032 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
9033 | } | |
1da177e4 | 9034 | |
dd477003 MC |
9035 | err = tg3_setup_phy(tp, 0); |
9036 | if (err) | |
9037 | return err; | |
1da177e4 | 9038 | |
f07e9af3 MC |
9039 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
9040 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
9041 | u32 tmp; |
9042 | ||
9043 | /* Clear CRC stats. */ | |
9044 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
9045 | tg3_writephy(tp, MII_TG3_TEST1, | |
9046 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9047 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 9048 | } |
1da177e4 LT |
9049 | } |
9050 | } | |
9051 | ||
9052 | __tg3_set_rx_mode(tp->dev); | |
9053 | ||
9054 | /* Initialize receive rules. */ | |
9055 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
9056 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
9057 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
9058 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
9059 | ||
63c3a66f | 9060 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) |
1da177e4 LT |
9061 | limit = 8; |
9062 | else | |
9063 | limit = 16; | |
63c3a66f | 9064 | if (tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
9065 | limit -= 4; |
9066 | switch (limit) { | |
9067 | case 16: | |
9068 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
9069 | case 15: | |
9070 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
9071 | case 14: | |
9072 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
9073 | case 13: | |
9074 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
9075 | case 12: | |
9076 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
9077 | case 11: | |
9078 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
9079 | case 10: | |
9080 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
9081 | case 9: | |
9082 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
9083 | case 8: | |
9084 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
9085 | case 7: | |
9086 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
9087 | case 6: | |
9088 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
9089 | case 5: | |
9090 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
9091 | case 4: | |
9092 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
9093 | case 3: | |
9094 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
9095 | case 2: | |
9096 | case 1: | |
9097 | ||
9098 | default: | |
9099 | break; | |
855e1111 | 9100 | } |
1da177e4 | 9101 | |
63c3a66f | 9102 | if (tg3_flag(tp, ENABLE_APE)) |
9ce768ea MC |
9103 | /* Write our heartbeat update interval to APE. */ |
9104 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
9105 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 9106 | |
1da177e4 LT |
9107 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
9108 | ||
1da177e4 LT |
9109 | return 0; |
9110 | } | |
9111 | ||
9112 | /* Called at device open time to get the chip ready for | |
9113 | * packet processing. Invoked with tp->lock held. | |
9114 | */ | |
8e7a22e3 | 9115 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 9116 | { |
1da177e4 LT |
9117 | tg3_switch_clocks(tp); |
9118 | ||
9119 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
9120 | ||
2f751b67 | 9121 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
9122 | } |
9123 | ||
9124 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
9125 | do { u32 __val = tr32(REG); \ | |
9126 | (PSTAT)->low += __val; \ | |
9127 | if ((PSTAT)->low < __val) \ | |
9128 | (PSTAT)->high += 1; \ | |
9129 | } while (0) | |
9130 | ||
9131 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
9132 | { | |
9133 | struct tg3_hw_stats *sp = tp->hw_stats; | |
9134 | ||
9135 | if (!netif_carrier_ok(tp->dev)) | |
9136 | return; | |
9137 | ||
9138 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
9139 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
9140 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
9141 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
9142 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
9143 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
9144 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
9145 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
9146 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
9147 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
9148 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
9149 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
9150 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
9151 | ||
9152 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
9153 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
9154 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
9155 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
9156 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
9157 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
9158 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
9159 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
9160 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
9161 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
9162 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
9163 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
9164 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
9165 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
9166 | |
9167 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
310050fa MC |
9168 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
9169 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && | |
9170 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { | |
4d958473 MC |
9171 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); |
9172 | } else { | |
9173 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
9174 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
9175 | if (val) { | |
9176 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
9177 | sp->rx_discards.low += val; | |
9178 | if (sp->rx_discards.low < val) | |
9179 | sp->rx_discards.high += 1; | |
9180 | } | |
9181 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
9182 | } | |
463d305b | 9183 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
1da177e4 LT |
9184 | } |
9185 | ||
0e6cf6a9 MC |
9186 | static void tg3_chk_missed_msi(struct tg3 *tp) |
9187 | { | |
9188 | u32 i; | |
9189 | ||
9190 | for (i = 0; i < tp->irq_cnt; i++) { | |
9191 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9192 | ||
9193 | if (tg3_has_work(tnapi)) { | |
9194 | if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && | |
9195 | tnapi->last_tx_cons == tnapi->tx_cons) { | |
9196 | if (tnapi->chk_msi_cnt < 1) { | |
9197 | tnapi->chk_msi_cnt++; | |
9198 | return; | |
9199 | } | |
7f230735 | 9200 | tg3_msi(0, tnapi); |
0e6cf6a9 MC |
9201 | } |
9202 | } | |
9203 | tnapi->chk_msi_cnt = 0; | |
9204 | tnapi->last_rx_cons = tnapi->rx_rcb_ptr; | |
9205 | tnapi->last_tx_cons = tnapi->tx_cons; | |
9206 | } | |
9207 | } | |
9208 | ||
1da177e4 LT |
9209 | static void tg3_timer(unsigned long __opaque) |
9210 | { | |
9211 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 9212 | |
5b190624 | 9213 | if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) |
f475f163 MC |
9214 | goto restart_timer; |
9215 | ||
f47c11ee | 9216 | spin_lock(&tp->lock); |
1da177e4 | 9217 | |
0e6cf6a9 | 9218 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
55086ad9 | 9219 | tg3_flag(tp, 57765_CLASS)) |
0e6cf6a9 MC |
9220 | tg3_chk_missed_msi(tp); |
9221 | ||
63c3a66f | 9222 | if (!tg3_flag(tp, TAGGED_STATUS)) { |
fac9b83e DM |
9223 | /* All of this garbage is because when using non-tagged |
9224 | * IRQ status the mailbox/status_block protocol the chip | |
9225 | * uses with the cpu is race prone. | |
9226 | */ | |
898a56f8 | 9227 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
9228 | tw32(GRC_LOCAL_CTRL, |
9229 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
9230 | } else { | |
9231 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 9232 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 9233 | } |
1da177e4 | 9234 | |
fac9b83e | 9235 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
f47c11ee | 9236 | spin_unlock(&tp->lock); |
db219973 | 9237 | tg3_reset_task_schedule(tp); |
5b190624 | 9238 | goto restart_timer; |
fac9b83e | 9239 | } |
1da177e4 LT |
9240 | } |
9241 | ||
1da177e4 LT |
9242 | /* This part only runs once per second. */ |
9243 | if (!--tp->timer_counter) { | |
63c3a66f | 9244 | if (tg3_flag(tp, 5705_PLUS)) |
fac9b83e DM |
9245 | tg3_periodic_fetch_stats(tp); |
9246 | ||
b0c5943f MC |
9247 | if (tp->setlpicnt && !--tp->setlpicnt) |
9248 | tg3_phy_eee_enable(tp); | |
52b02d04 | 9249 | |
63c3a66f | 9250 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
9251 | u32 mac_stat; |
9252 | int phy_event; | |
9253 | ||
9254 | mac_stat = tr32(MAC_STATUS); | |
9255 | ||
9256 | phy_event = 0; | |
f07e9af3 | 9257 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
9258 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
9259 | phy_event = 1; | |
9260 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
9261 | phy_event = 1; | |
9262 | ||
9263 | if (phy_event) | |
9264 | tg3_setup_phy(tp, 0); | |
63c3a66f | 9265 | } else if (tg3_flag(tp, POLL_SERDES)) { |
1da177e4 LT |
9266 | u32 mac_stat = tr32(MAC_STATUS); |
9267 | int need_setup = 0; | |
9268 | ||
9269 | if (netif_carrier_ok(tp->dev) && | |
9270 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
9271 | need_setup = 1; | |
9272 | } | |
be98da6a | 9273 | if (!netif_carrier_ok(tp->dev) && |
1da177e4 LT |
9274 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
9275 | MAC_STATUS_SIGNAL_DET))) { | |
9276 | need_setup = 1; | |
9277 | } | |
9278 | if (need_setup) { | |
3d3ebe74 MC |
9279 | if (!tp->serdes_counter) { |
9280 | tw32_f(MAC_MODE, | |
9281 | (tp->mac_mode & | |
9282 | ~MAC_MODE_PORT_MODE_MASK)); | |
9283 | udelay(40); | |
9284 | tw32_f(MAC_MODE, tp->mac_mode); | |
9285 | udelay(40); | |
9286 | } | |
1da177e4 LT |
9287 | tg3_setup_phy(tp, 0); |
9288 | } | |
f07e9af3 | 9289 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
63c3a66f | 9290 | tg3_flag(tp, 5780_CLASS)) { |
747e8f8b | 9291 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 9292 | } |
1da177e4 LT |
9293 | |
9294 | tp->timer_counter = tp->timer_multiplier; | |
9295 | } | |
9296 | ||
130b8e4d MC |
9297 | /* Heartbeat is only sent once every 2 seconds. |
9298 | * | |
9299 | * The heartbeat is to tell the ASF firmware that the host | |
9300 | * driver is still alive. In the event that the OS crashes, | |
9301 | * ASF needs to reset the hardware to free up the FIFO space | |
9302 | * that may be filled with rx packets destined for the host. | |
9303 | * If the FIFO is full, ASF will no longer function properly. | |
9304 | * | |
9305 | * Unintended resets have been reported on real time kernels | |
9306 | * where the timer doesn't run on time. Netpoll will also have | |
9307 | * same problem. | |
9308 | * | |
9309 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
9310 | * to check the ring condition when the heartbeat is expiring | |
9311 | * before doing the reset. This will prevent most unintended | |
9312 | * resets. | |
9313 | */ | |
1da177e4 | 9314 | if (!--tp->asf_counter) { |
63c3a66f | 9315 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
9316 | tg3_wait_for_event_ack(tp); |
9317 | ||
bbadf503 | 9318 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 9319 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 9320 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
9321 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
9322 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
9323 | |
9324 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
9325 | } |
9326 | tp->asf_counter = tp->asf_multiplier; | |
9327 | } | |
9328 | ||
f47c11ee | 9329 | spin_unlock(&tp->lock); |
1da177e4 | 9330 | |
f475f163 | 9331 | restart_timer: |
1da177e4 LT |
9332 | tp->timer.expires = jiffies + tp->timer_offset; |
9333 | add_timer(&tp->timer); | |
9334 | } | |
9335 | ||
4f125f42 | 9336 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 9337 | { |
7d12e780 | 9338 | irq_handler_t fn; |
fcfa0a32 | 9339 | unsigned long flags; |
4f125f42 MC |
9340 | char *name; |
9341 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
9342 | ||
9343 | if (tp->irq_cnt == 1) | |
9344 | name = tp->dev->name; | |
9345 | else { | |
9346 | name = &tnapi->irq_lbl[0]; | |
9347 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
9348 | name[IFNAMSIZ-1] = 0; | |
9349 | } | |
fcfa0a32 | 9350 | |
63c3a66f | 9351 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
fcfa0a32 | 9352 | fn = tg3_msi; |
63c3a66f | 9353 | if (tg3_flag(tp, 1SHOT_MSI)) |
fcfa0a32 | 9354 | fn = tg3_msi_1shot; |
ab392d2d | 9355 | flags = 0; |
fcfa0a32 MC |
9356 | } else { |
9357 | fn = tg3_interrupt; | |
63c3a66f | 9358 | if (tg3_flag(tp, TAGGED_STATUS)) |
fcfa0a32 | 9359 | fn = tg3_interrupt_tagged; |
ab392d2d | 9360 | flags = IRQF_SHARED; |
fcfa0a32 | 9361 | } |
4f125f42 MC |
9362 | |
9363 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
9364 | } |
9365 | ||
7938109f MC |
9366 | static int tg3_test_interrupt(struct tg3 *tp) |
9367 | { | |
09943a18 | 9368 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 9369 | struct net_device *dev = tp->dev; |
b16250e3 | 9370 | int err, i, intr_ok = 0; |
f6eb9b1f | 9371 | u32 val; |
7938109f | 9372 | |
d4bc3927 MC |
9373 | if (!netif_running(dev)) |
9374 | return -ENODEV; | |
9375 | ||
7938109f MC |
9376 | tg3_disable_ints(tp); |
9377 | ||
4f125f42 | 9378 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 9379 | |
f6eb9b1f MC |
9380 | /* |
9381 | * Turn off MSI one shot mode. Otherwise this test has no | |
9382 | * observable way to know whether the interrupt was delivered. | |
9383 | */ | |
3aa1cdf8 | 9384 | if (tg3_flag(tp, 57765_PLUS)) { |
f6eb9b1f MC |
9385 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; |
9386 | tw32(MSGINT_MODE, val); | |
9387 | } | |
9388 | ||
4f125f42 | 9389 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 9390 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
9391 | if (err) |
9392 | return err; | |
9393 | ||
898a56f8 | 9394 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
9395 | tg3_enable_ints(tp); |
9396 | ||
9397 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 9398 | tnapi->coal_now); |
7938109f MC |
9399 | |
9400 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
9401 | u32 int_mbox, misc_host_ctrl; |
9402 | ||
898a56f8 | 9403 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
9404 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
9405 | ||
9406 | if ((int_mbox != 0) || | |
9407 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
9408 | intr_ok = 1; | |
7938109f | 9409 | break; |
b16250e3 MC |
9410 | } |
9411 | ||
3aa1cdf8 MC |
9412 | if (tg3_flag(tp, 57765_PLUS) && |
9413 | tnapi->hw_status->status_tag != tnapi->last_tag) | |
9414 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
9415 | ||
7938109f MC |
9416 | msleep(10); |
9417 | } | |
9418 | ||
9419 | tg3_disable_ints(tp); | |
9420 | ||
4f125f42 | 9421 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 9422 | |
4f125f42 | 9423 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9424 | |
9425 | if (err) | |
9426 | return err; | |
9427 | ||
f6eb9b1f MC |
9428 | if (intr_ok) { |
9429 | /* Reenable MSI one shot mode. */ | |
5b39de91 | 9430 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { |
f6eb9b1f MC |
9431 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; |
9432 | tw32(MSGINT_MODE, val); | |
9433 | } | |
7938109f | 9434 | return 0; |
f6eb9b1f | 9435 | } |
7938109f MC |
9436 | |
9437 | return -EIO; | |
9438 | } | |
9439 | ||
9440 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
9441 | * successfully restored | |
9442 | */ | |
9443 | static int tg3_test_msi(struct tg3 *tp) | |
9444 | { | |
7938109f MC |
9445 | int err; |
9446 | u16 pci_cmd; | |
9447 | ||
63c3a66f | 9448 | if (!tg3_flag(tp, USING_MSI)) |
7938109f MC |
9449 | return 0; |
9450 | ||
9451 | /* Turn off SERR reporting in case MSI terminates with Master | |
9452 | * Abort. | |
9453 | */ | |
9454 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
9455 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
9456 | pci_cmd & ~PCI_COMMAND_SERR); | |
9457 | ||
9458 | err = tg3_test_interrupt(tp); | |
9459 | ||
9460 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
9461 | ||
9462 | if (!err) | |
9463 | return 0; | |
9464 | ||
9465 | /* other failures */ | |
9466 | if (err != -EIO) | |
9467 | return err; | |
9468 | ||
9469 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
9470 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
9471 | "to INTx mode. Please report this failure to the PCI " | |
9472 | "maintainer and include system chipset information\n"); | |
7938109f | 9473 | |
4f125f42 | 9474 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 9475 | |
7938109f MC |
9476 | pci_disable_msi(tp->pdev); |
9477 | ||
63c3a66f | 9478 | tg3_flag_clear(tp, USING_MSI); |
dc8bf1b1 | 9479 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 9480 | |
4f125f42 | 9481 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9482 | if (err) |
9483 | return err; | |
9484 | ||
9485 | /* Need to reset the chip because the MSI cycle may have terminated | |
9486 | * with Master Abort. | |
9487 | */ | |
f47c11ee | 9488 | tg3_full_lock(tp, 1); |
7938109f | 9489 | |
944d980e | 9490 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 9491 | err = tg3_init_hw(tp, 1); |
7938109f | 9492 | |
f47c11ee | 9493 | tg3_full_unlock(tp); |
7938109f MC |
9494 | |
9495 | if (err) | |
4f125f42 | 9496 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
9497 | |
9498 | return err; | |
9499 | } | |
9500 | ||
9e9fd12d MC |
9501 | static int tg3_request_firmware(struct tg3 *tp) |
9502 | { | |
9503 | const __be32 *fw_data; | |
9504 | ||
9505 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
9506 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
9507 | tp->fw_needed); | |
9e9fd12d MC |
9508 | return -ENOENT; |
9509 | } | |
9510 | ||
9511 | fw_data = (void *)tp->fw->data; | |
9512 | ||
9513 | /* Firmware blob starts with version numbers, followed by | |
9514 | * start address and _full_ length including BSS sections | |
9515 | * (which must be longer than the actual data, of course | |
9516 | */ | |
9517 | ||
9518 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
9519 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
9520 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
9521 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
9522 | release_firmware(tp->fw); |
9523 | tp->fw = NULL; | |
9524 | return -EINVAL; | |
9525 | } | |
9526 | ||
9527 | /* We no longer need firmware; we have it. */ | |
9528 | tp->fw_needed = NULL; | |
9529 | return 0; | |
9530 | } | |
9531 | ||
679563f4 MC |
9532 | static bool tg3_enable_msix(struct tg3 *tp) |
9533 | { | |
9534 | int i, rc, cpus = num_online_cpus(); | |
9535 | struct msix_entry msix_ent[tp->irq_max]; | |
9536 | ||
9537 | if (cpus == 1) | |
9538 | /* Just fallback to the simpler MSI mode. */ | |
9539 | return false; | |
9540 | ||
9541 | /* | |
9542 | * We want as many rx rings enabled as there are cpus. | |
9543 | * The first MSIX vector only deals with link interrupts, etc, | |
9544 | * so we add one to the number of vectors we are requesting. | |
9545 | */ | |
9546 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
9547 | ||
9548 | for (i = 0; i < tp->irq_max; i++) { | |
9549 | msix_ent[i].entry = i; | |
9550 | msix_ent[i].vector = 0; | |
9551 | } | |
9552 | ||
9553 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
9554 | if (rc < 0) { |
9555 | return false; | |
9556 | } else if (rc != 0) { | |
679563f4 MC |
9557 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
9558 | return false; | |
05dbe005 JP |
9559 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
9560 | tp->irq_cnt, rc); | |
679563f4 MC |
9561 | tp->irq_cnt = rc; |
9562 | } | |
9563 | ||
9564 | for (i = 0; i < tp->irq_max; i++) | |
9565 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9566 | ||
2ddaad39 BH |
9567 | netif_set_real_num_tx_queues(tp->dev, 1); |
9568 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9569 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9570 | pci_disable_msix(tp->pdev); | |
9571 | return false; | |
9572 | } | |
b92b9040 MC |
9573 | |
9574 | if (tp->irq_cnt > 1) { | |
63c3a66f | 9575 | tg3_flag_set(tp, ENABLE_RSS); |
d78b59f5 MC |
9576 | |
9577 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
9578 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
63c3a66f | 9579 | tg3_flag_set(tp, ENABLE_TSS); |
b92b9040 MC |
9580 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); |
9581 | } | |
9582 | } | |
2430b031 | 9583 | |
679563f4 MC |
9584 | return true; |
9585 | } | |
9586 | ||
07b0173c MC |
9587 | static void tg3_ints_init(struct tg3 *tp) |
9588 | { | |
63c3a66f JP |
9589 | if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && |
9590 | !tg3_flag(tp, TAGGED_STATUS)) { | |
07b0173c MC |
9591 | /* All MSI supporting chips should support tagged |
9592 | * status. Assert that this is the case. | |
9593 | */ | |
5129c3a3 MC |
9594 | netdev_warn(tp->dev, |
9595 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 9596 | goto defcfg; |
07b0173c | 9597 | } |
4f125f42 | 9598 | |
63c3a66f JP |
9599 | if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) |
9600 | tg3_flag_set(tp, USING_MSIX); | |
9601 | else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) | |
9602 | tg3_flag_set(tp, USING_MSI); | |
679563f4 | 9603 | |
63c3a66f | 9604 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
679563f4 | 9605 | u32 msi_mode = tr32(MSGINT_MODE); |
63c3a66f | 9606 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) |
baf8a94a | 9607 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
5b39de91 MC |
9608 | if (!tg3_flag(tp, 1SHOT_MSI)) |
9609 | msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE; | |
679563f4 MC |
9610 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
9611 | } | |
9612 | defcfg: | |
63c3a66f | 9613 | if (!tg3_flag(tp, USING_MSIX)) { |
679563f4 MC |
9614 | tp->irq_cnt = 1; |
9615 | tp->napi[0].irq_vec = tp->pdev->irq; | |
2ddaad39 | 9616 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 9617 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 9618 | } |
07b0173c MC |
9619 | } |
9620 | ||
9621 | static void tg3_ints_fini(struct tg3 *tp) | |
9622 | { | |
63c3a66f | 9623 | if (tg3_flag(tp, USING_MSIX)) |
679563f4 | 9624 | pci_disable_msix(tp->pdev); |
63c3a66f | 9625 | else if (tg3_flag(tp, USING_MSI)) |
679563f4 | 9626 | pci_disable_msi(tp->pdev); |
63c3a66f JP |
9627 | tg3_flag_clear(tp, USING_MSI); |
9628 | tg3_flag_clear(tp, USING_MSIX); | |
9629 | tg3_flag_clear(tp, ENABLE_RSS); | |
9630 | tg3_flag_clear(tp, ENABLE_TSS); | |
07b0173c MC |
9631 | } |
9632 | ||
1da177e4 LT |
9633 | static int tg3_open(struct net_device *dev) |
9634 | { | |
9635 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 9636 | int i, err; |
1da177e4 | 9637 | |
9e9fd12d MC |
9638 | if (tp->fw_needed) { |
9639 | err = tg3_request_firmware(tp); | |
9640 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9641 | if (err) | |
9642 | return err; | |
9643 | } else if (err) { | |
05dbe005 | 9644 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
63c3a66f JP |
9645 | tg3_flag_clear(tp, TSO_CAPABLE); |
9646 | } else if (!tg3_flag(tp, TSO_CAPABLE)) { | |
05dbe005 | 9647 | netdev_notice(tp->dev, "TSO capability restored\n"); |
63c3a66f | 9648 | tg3_flag_set(tp, TSO_CAPABLE); |
9e9fd12d MC |
9649 | } |
9650 | } | |
9651 | ||
c49a1561 MC |
9652 | netif_carrier_off(tp->dev); |
9653 | ||
c866b7ea | 9654 | err = tg3_power_up(tp); |
2f751b67 | 9655 | if (err) |
bc1c7567 | 9656 | return err; |
2f751b67 MC |
9657 | |
9658 | tg3_full_lock(tp, 0); | |
bc1c7567 | 9659 | |
1da177e4 | 9660 | tg3_disable_ints(tp); |
63c3a66f | 9661 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 9662 | |
f47c11ee | 9663 | tg3_full_unlock(tp); |
1da177e4 | 9664 | |
679563f4 MC |
9665 | /* |
9666 | * Setup interrupts first so we know how | |
9667 | * many NAPI resources to allocate | |
9668 | */ | |
9669 | tg3_ints_init(tp); | |
9670 | ||
bcebcc46 MC |
9671 | tg3_rss_init_indir_tbl(tp); |
9672 | ||
1da177e4 LT |
9673 | /* The placement of this call is tied |
9674 | * to the setup and use of Host TX descriptors. | |
9675 | */ | |
9676 | err = tg3_alloc_consistent(tp); | |
9677 | if (err) | |
679563f4 | 9678 | goto err_out1; |
88b06bc2 | 9679 | |
66cfd1bd MC |
9680 | tg3_napi_init(tp); |
9681 | ||
fed97810 | 9682 | tg3_napi_enable(tp); |
1da177e4 | 9683 | |
4f125f42 MC |
9684 | for (i = 0; i < tp->irq_cnt; i++) { |
9685 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9686 | err = tg3_request_irq(tp, i); | |
9687 | if (err) { | |
5bc09186 MC |
9688 | for (i--; i >= 0; i--) { |
9689 | tnapi = &tp->napi[i]; | |
4f125f42 | 9690 | free_irq(tnapi->irq_vec, tnapi); |
5bc09186 MC |
9691 | } |
9692 | goto err_out2; | |
4f125f42 MC |
9693 | } |
9694 | } | |
1da177e4 | 9695 | |
f47c11ee | 9696 | tg3_full_lock(tp, 0); |
1da177e4 | 9697 | |
8e7a22e3 | 9698 | err = tg3_init_hw(tp, 1); |
1da177e4 | 9699 | if (err) { |
944d980e | 9700 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
9701 | tg3_free_rings(tp); |
9702 | } else { | |
0e6cf6a9 | 9703 | if (tg3_flag(tp, TAGGED_STATUS) && |
55086ad9 MC |
9704 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
9705 | !tg3_flag(tp, 57765_CLASS)) | |
fac9b83e DM |
9706 | tp->timer_offset = HZ; |
9707 | else | |
9708 | tp->timer_offset = HZ / 10; | |
9709 | ||
9710 | BUG_ON(tp->timer_offset > HZ); | |
9711 | tp->timer_counter = tp->timer_multiplier = | |
9712 | (HZ / tp->timer_offset); | |
9713 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 9714 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
9715 | |
9716 | init_timer(&tp->timer); | |
9717 | tp->timer.expires = jiffies + tp->timer_offset; | |
9718 | tp->timer.data = (unsigned long) tp; | |
9719 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
9720 | } |
9721 | ||
f47c11ee | 9722 | tg3_full_unlock(tp); |
1da177e4 | 9723 | |
07b0173c | 9724 | if (err) |
679563f4 | 9725 | goto err_out3; |
1da177e4 | 9726 | |
63c3a66f | 9727 | if (tg3_flag(tp, USING_MSI)) { |
7938109f | 9728 | err = tg3_test_msi(tp); |
fac9b83e | 9729 | |
7938109f | 9730 | if (err) { |
f47c11ee | 9731 | tg3_full_lock(tp, 0); |
944d980e | 9732 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 9733 | tg3_free_rings(tp); |
f47c11ee | 9734 | tg3_full_unlock(tp); |
7938109f | 9735 | |
679563f4 | 9736 | goto err_out2; |
7938109f | 9737 | } |
fcfa0a32 | 9738 | |
63c3a66f | 9739 | if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f | 9740 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 9741 | |
f6eb9b1f MC |
9742 | tw32(PCIE_TRANSACTION_CFG, |
9743 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 9744 | } |
7938109f MC |
9745 | } |
9746 | ||
b02fd9e3 MC |
9747 | tg3_phy_start(tp); |
9748 | ||
f47c11ee | 9749 | tg3_full_lock(tp, 0); |
1da177e4 | 9750 | |
7938109f | 9751 | add_timer(&tp->timer); |
63c3a66f | 9752 | tg3_flag_set(tp, INIT_COMPLETE); |
1da177e4 LT |
9753 | tg3_enable_ints(tp); |
9754 | ||
f47c11ee | 9755 | tg3_full_unlock(tp); |
1da177e4 | 9756 | |
fe5f5787 | 9757 | netif_tx_start_all_queues(dev); |
1da177e4 | 9758 | |
06c03c02 MB |
9759 | /* |
9760 | * Reset loopback feature if it was turned on while the device was down | |
9761 | * make sure that it's installed properly now. | |
9762 | */ | |
9763 | if (dev->features & NETIF_F_LOOPBACK) | |
9764 | tg3_set_loopback(dev, dev->features); | |
9765 | ||
1da177e4 | 9766 | return 0; |
07b0173c | 9767 | |
679563f4 | 9768 | err_out3: |
4f125f42 MC |
9769 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9770 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9771 | free_irq(tnapi->irq_vec, tnapi); | |
9772 | } | |
07b0173c | 9773 | |
679563f4 | 9774 | err_out2: |
fed97810 | 9775 | tg3_napi_disable(tp); |
66cfd1bd | 9776 | tg3_napi_fini(tp); |
07b0173c | 9777 | tg3_free_consistent(tp); |
679563f4 MC |
9778 | |
9779 | err_out1: | |
9780 | tg3_ints_fini(tp); | |
cd0d7228 MC |
9781 | tg3_frob_aux_power(tp, false); |
9782 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
07b0173c | 9783 | return err; |
1da177e4 LT |
9784 | } |
9785 | ||
1da177e4 LT |
9786 | static int tg3_close(struct net_device *dev) |
9787 | { | |
4f125f42 | 9788 | int i; |
1da177e4 LT |
9789 | struct tg3 *tp = netdev_priv(dev); |
9790 | ||
fed97810 | 9791 | tg3_napi_disable(tp); |
db219973 | 9792 | tg3_reset_task_cancel(tp); |
7faa006f | 9793 | |
fe5f5787 | 9794 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
9795 | |
9796 | del_timer_sync(&tp->timer); | |
9797 | ||
24bb4fb6 MC |
9798 | tg3_phy_stop(tp); |
9799 | ||
f47c11ee | 9800 | tg3_full_lock(tp, 1); |
1da177e4 LT |
9801 | |
9802 | tg3_disable_ints(tp); | |
9803 | ||
944d980e | 9804 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 9805 | tg3_free_rings(tp); |
63c3a66f | 9806 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 9807 | |
f47c11ee | 9808 | tg3_full_unlock(tp); |
1da177e4 | 9809 | |
4f125f42 MC |
9810 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9811 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9812 | free_irq(tnapi->irq_vec, tnapi); | |
9813 | } | |
07b0173c MC |
9814 | |
9815 | tg3_ints_fini(tp); | |
1da177e4 | 9816 | |
92feeabf MC |
9817 | /* Clear stats across close / open calls */ |
9818 | memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev)); | |
9819 | memset(&tp->estats_prev, 0, sizeof(tp->estats_prev)); | |
1da177e4 | 9820 | |
66cfd1bd MC |
9821 | tg3_napi_fini(tp); |
9822 | ||
1da177e4 LT |
9823 | tg3_free_consistent(tp); |
9824 | ||
c866b7ea | 9825 | tg3_power_down(tp); |
bc1c7567 MC |
9826 | |
9827 | netif_carrier_off(tp->dev); | |
9828 | ||
1da177e4 LT |
9829 | return 0; |
9830 | } | |
9831 | ||
511d2224 | 9832 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
9833 | { |
9834 | return ((u64)val->high << 32) | ((u64)val->low); | |
9835 | } | |
9836 | ||
511d2224 | 9837 | static u64 calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
9838 | { |
9839 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9840 | ||
f07e9af3 | 9841 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
9842 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
9843 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
9844 | u32 val; |
9845 | ||
f47c11ee | 9846 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
9847 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
9848 | tg3_writephy(tp, MII_TG3_TEST1, | |
9849 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9850 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
9851 | } else |
9852 | val = 0; | |
f47c11ee | 9853 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
9854 | |
9855 | tp->phy_crc_errors += val; | |
9856 | ||
9857 | return tp->phy_crc_errors; | |
9858 | } | |
9859 | ||
9860 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9861 | } | |
9862 | ||
9863 | #define ESTAT_ADD(member) \ | |
9864 | estats->member = old_estats->member + \ | |
511d2224 | 9865 | get_stat64(&hw_stats->member) |
1da177e4 | 9866 | |
0e6c9da3 MC |
9867 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp, |
9868 | struct tg3_ethtool_stats *estats) | |
1da177e4 | 9869 | { |
1da177e4 LT |
9870 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; |
9871 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9872 | ||
9873 | if (!hw_stats) | |
9874 | return old_estats; | |
9875 | ||
9876 | ESTAT_ADD(rx_octets); | |
9877 | ESTAT_ADD(rx_fragments); | |
9878 | ESTAT_ADD(rx_ucast_packets); | |
9879 | ESTAT_ADD(rx_mcast_packets); | |
9880 | ESTAT_ADD(rx_bcast_packets); | |
9881 | ESTAT_ADD(rx_fcs_errors); | |
9882 | ESTAT_ADD(rx_align_errors); | |
9883 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9884 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9885 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9886 | ESTAT_ADD(rx_xoff_entered); | |
9887 | ESTAT_ADD(rx_frame_too_long_errors); | |
9888 | ESTAT_ADD(rx_jabbers); | |
9889 | ESTAT_ADD(rx_undersize_packets); | |
9890 | ESTAT_ADD(rx_in_length_errors); | |
9891 | ESTAT_ADD(rx_out_length_errors); | |
9892 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9893 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9894 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9895 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9896 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9897 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9898 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9899 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9900 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9901 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9902 | ||
9903 | ESTAT_ADD(tx_octets); | |
9904 | ESTAT_ADD(tx_collisions); | |
9905 | ESTAT_ADD(tx_xon_sent); | |
9906 | ESTAT_ADD(tx_xoff_sent); | |
9907 | ESTAT_ADD(tx_flow_control); | |
9908 | ESTAT_ADD(tx_mac_errors); | |
9909 | ESTAT_ADD(tx_single_collisions); | |
9910 | ESTAT_ADD(tx_mult_collisions); | |
9911 | ESTAT_ADD(tx_deferred); | |
9912 | ESTAT_ADD(tx_excessive_collisions); | |
9913 | ESTAT_ADD(tx_late_collisions); | |
9914 | ESTAT_ADD(tx_collide_2times); | |
9915 | ESTAT_ADD(tx_collide_3times); | |
9916 | ESTAT_ADD(tx_collide_4times); | |
9917 | ESTAT_ADD(tx_collide_5times); | |
9918 | ESTAT_ADD(tx_collide_6times); | |
9919 | ESTAT_ADD(tx_collide_7times); | |
9920 | ESTAT_ADD(tx_collide_8times); | |
9921 | ESTAT_ADD(tx_collide_9times); | |
9922 | ESTAT_ADD(tx_collide_10times); | |
9923 | ESTAT_ADD(tx_collide_11times); | |
9924 | ESTAT_ADD(tx_collide_12times); | |
9925 | ESTAT_ADD(tx_collide_13times); | |
9926 | ESTAT_ADD(tx_collide_14times); | |
9927 | ESTAT_ADD(tx_collide_15times); | |
9928 | ESTAT_ADD(tx_ucast_packets); | |
9929 | ESTAT_ADD(tx_mcast_packets); | |
9930 | ESTAT_ADD(tx_bcast_packets); | |
9931 | ESTAT_ADD(tx_carrier_sense_errors); | |
9932 | ESTAT_ADD(tx_discards); | |
9933 | ESTAT_ADD(tx_errors); | |
9934 | ||
9935 | ESTAT_ADD(dma_writeq_full); | |
9936 | ESTAT_ADD(dma_write_prioq_full); | |
9937 | ESTAT_ADD(rxbds_empty); | |
9938 | ESTAT_ADD(rx_discards); | |
9939 | ESTAT_ADD(rx_errors); | |
9940 | ESTAT_ADD(rx_threshold_hit); | |
9941 | ||
9942 | ESTAT_ADD(dma_readq_full); | |
9943 | ESTAT_ADD(dma_read_prioq_full); | |
9944 | ESTAT_ADD(tx_comp_queue_full); | |
9945 | ||
9946 | ESTAT_ADD(ring_set_send_prod_index); | |
9947 | ESTAT_ADD(ring_status_update); | |
9948 | ESTAT_ADD(nic_irqs); | |
9949 | ESTAT_ADD(nic_avoided_irqs); | |
9950 | ESTAT_ADD(nic_tx_threshold_hit); | |
9951 | ||
4452d099 MC |
9952 | ESTAT_ADD(mbuf_lwm_thresh_hit); |
9953 | ||
1da177e4 LT |
9954 | return estats; |
9955 | } | |
9956 | ||
511d2224 ED |
9957 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
9958 | struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
9959 | { |
9960 | struct tg3 *tp = netdev_priv(dev); | |
511d2224 | 9961 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
9962 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
9963 | ||
9964 | if (!hw_stats) | |
9965 | return old_stats; | |
9966 | ||
9967 | stats->rx_packets = old_stats->rx_packets + | |
9968 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9969 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9970 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 9971 | |
1da177e4 LT |
9972 | stats->tx_packets = old_stats->tx_packets + |
9973 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9974 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9975 | get_stat64(&hw_stats->tx_bcast_packets); | |
9976 | ||
9977 | stats->rx_bytes = old_stats->rx_bytes + | |
9978 | get_stat64(&hw_stats->rx_octets); | |
9979 | stats->tx_bytes = old_stats->tx_bytes + | |
9980 | get_stat64(&hw_stats->tx_octets); | |
9981 | ||
9982 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 9983 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
9984 | stats->tx_errors = old_stats->tx_errors + |
9985 | get_stat64(&hw_stats->tx_errors) + | |
9986 | get_stat64(&hw_stats->tx_mac_errors) + | |
9987 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9988 | get_stat64(&hw_stats->tx_discards); | |
9989 | ||
9990 | stats->multicast = old_stats->multicast + | |
9991 | get_stat64(&hw_stats->rx_mcast_packets); | |
9992 | stats->collisions = old_stats->collisions + | |
9993 | get_stat64(&hw_stats->tx_collisions); | |
9994 | ||
9995 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9996 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9997 | get_stat64(&hw_stats->rx_undersize_packets); | |
9998 | ||
9999 | stats->rx_over_errors = old_stats->rx_over_errors + | |
10000 | get_stat64(&hw_stats->rxbds_empty); | |
10001 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
10002 | get_stat64(&hw_stats->rx_align_errors); | |
10003 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
10004 | get_stat64(&hw_stats->tx_discards); | |
10005 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
10006 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
10007 | ||
10008 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
10009 | calc_crc_errors(tp); | |
10010 | ||
4f63b877 JL |
10011 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
10012 | get_stat64(&hw_stats->rx_discards); | |
10013 | ||
b0057c51 | 10014 | stats->rx_dropped = tp->rx_dropped; |
48855432 | 10015 | stats->tx_dropped = tp->tx_dropped; |
b0057c51 | 10016 | |
1da177e4 LT |
10017 | return stats; |
10018 | } | |
10019 | ||
10020 | static inline u32 calc_crc(unsigned char *buf, int len) | |
10021 | { | |
10022 | u32 reg; | |
10023 | u32 tmp; | |
10024 | int j, k; | |
10025 | ||
10026 | reg = 0xffffffff; | |
10027 | ||
10028 | for (j = 0; j < len; j++) { | |
10029 | reg ^= buf[j]; | |
10030 | ||
10031 | for (k = 0; k < 8; k++) { | |
10032 | tmp = reg & 0x01; | |
10033 | ||
10034 | reg >>= 1; | |
10035 | ||
859a5887 | 10036 | if (tmp) |
1da177e4 | 10037 | reg ^= 0xedb88320; |
1da177e4 LT |
10038 | } |
10039 | } | |
10040 | ||
10041 | return ~reg; | |
10042 | } | |
10043 | ||
10044 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
10045 | { | |
10046 | /* accept or reject all multicast frames */ | |
10047 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
10048 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
10049 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
10050 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
10051 | } | |
10052 | ||
10053 | static void __tg3_set_rx_mode(struct net_device *dev) | |
10054 | { | |
10055 | struct tg3 *tp = netdev_priv(dev); | |
10056 | u32 rx_mode; | |
10057 | ||
10058 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
10059 | RX_MODE_KEEP_VLAN_TAG); | |
10060 | ||
bf933c80 | 10061 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) |
1da177e4 LT |
10062 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG |
10063 | * flag clear. | |
10064 | */ | |
63c3a66f | 10065 | if (!tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
10066 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; |
10067 | #endif | |
10068 | ||
10069 | if (dev->flags & IFF_PROMISC) { | |
10070 | /* Promiscuous mode. */ | |
10071 | rx_mode |= RX_MODE_PROMISC; | |
10072 | } else if (dev->flags & IFF_ALLMULTI) { | |
10073 | /* Accept all multicast. */ | |
de6f31eb | 10074 | tg3_set_multi(tp, 1); |
4cd24eaf | 10075 | } else if (netdev_mc_empty(dev)) { |
1da177e4 | 10076 | /* Reject all multicast. */ |
de6f31eb | 10077 | tg3_set_multi(tp, 0); |
1da177e4 LT |
10078 | } else { |
10079 | /* Accept one or more multicast(s). */ | |
22bedad3 | 10080 | struct netdev_hw_addr *ha; |
1da177e4 LT |
10081 | u32 mc_filter[4] = { 0, }; |
10082 | u32 regidx; | |
10083 | u32 bit; | |
10084 | u32 crc; | |
10085 | ||
22bedad3 JP |
10086 | netdev_for_each_mc_addr(ha, dev) { |
10087 | crc = calc_crc(ha->addr, ETH_ALEN); | |
1da177e4 LT |
10088 | bit = ~crc & 0x7f; |
10089 | regidx = (bit & 0x60) >> 5; | |
10090 | bit &= 0x1f; | |
10091 | mc_filter[regidx] |= (1 << bit); | |
10092 | } | |
10093 | ||
10094 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
10095 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
10096 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
10097 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
10098 | } | |
10099 | ||
10100 | if (rx_mode != tp->rx_mode) { | |
10101 | tp->rx_mode = rx_mode; | |
10102 | tw32_f(MAC_RX_MODE, rx_mode); | |
10103 | udelay(10); | |
10104 | } | |
10105 | } | |
10106 | ||
10107 | static void tg3_set_rx_mode(struct net_device *dev) | |
10108 | { | |
10109 | struct tg3 *tp = netdev_priv(dev); | |
10110 | ||
e75f7c90 MC |
10111 | if (!netif_running(dev)) |
10112 | return; | |
10113 | ||
f47c11ee | 10114 | tg3_full_lock(tp, 0); |
1da177e4 | 10115 | __tg3_set_rx_mode(dev); |
f47c11ee | 10116 | tg3_full_unlock(tp); |
1da177e4 LT |
10117 | } |
10118 | ||
1da177e4 LT |
10119 | static int tg3_get_regs_len(struct net_device *dev) |
10120 | { | |
97bd8e49 | 10121 | return TG3_REG_BLK_SIZE; |
1da177e4 LT |
10122 | } |
10123 | ||
10124 | static void tg3_get_regs(struct net_device *dev, | |
10125 | struct ethtool_regs *regs, void *_p) | |
10126 | { | |
1da177e4 | 10127 | struct tg3 *tp = netdev_priv(dev); |
1da177e4 LT |
10128 | |
10129 | regs->version = 0; | |
10130 | ||
97bd8e49 | 10131 | memset(_p, 0, TG3_REG_BLK_SIZE); |
1da177e4 | 10132 | |
80096068 | 10133 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10134 | return; |
10135 | ||
f47c11ee | 10136 | tg3_full_lock(tp, 0); |
1da177e4 | 10137 | |
97bd8e49 | 10138 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
1da177e4 | 10139 | |
f47c11ee | 10140 | tg3_full_unlock(tp); |
1da177e4 LT |
10141 | } |
10142 | ||
10143 | static int tg3_get_eeprom_len(struct net_device *dev) | |
10144 | { | |
10145 | struct tg3 *tp = netdev_priv(dev); | |
10146 | ||
10147 | return tp->nvram_size; | |
10148 | } | |
10149 | ||
1da177e4 LT |
10150 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
10151 | { | |
10152 | struct tg3 *tp = netdev_priv(dev); | |
10153 | int ret; | |
10154 | u8 *pd; | |
b9fc7dc5 | 10155 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 10156 | __be32 val; |
1da177e4 | 10157 | |
63c3a66f | 10158 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10159 | return -EINVAL; |
10160 | ||
80096068 | 10161 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10162 | return -EAGAIN; |
10163 | ||
1da177e4 LT |
10164 | offset = eeprom->offset; |
10165 | len = eeprom->len; | |
10166 | eeprom->len = 0; | |
10167 | ||
10168 | eeprom->magic = TG3_EEPROM_MAGIC; | |
10169 | ||
10170 | if (offset & 3) { | |
10171 | /* adjustments to start on required 4 byte boundary */ | |
10172 | b_offset = offset & 3; | |
10173 | b_count = 4 - b_offset; | |
10174 | if (b_count > len) { | |
10175 | /* i.e. offset=1 len=2 */ | |
10176 | b_count = len; | |
10177 | } | |
a9dc529d | 10178 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
10179 | if (ret) |
10180 | return ret; | |
be98da6a | 10181 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
10182 | len -= b_count; |
10183 | offset += b_count; | |
c6cdf436 | 10184 | eeprom->len += b_count; |
1da177e4 LT |
10185 | } |
10186 | ||
25985edc | 10187 | /* read bytes up to the last 4 byte boundary */ |
1da177e4 LT |
10188 | pd = &data[eeprom->len]; |
10189 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 10190 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
10191 | if (ret) { |
10192 | eeprom->len += i; | |
10193 | return ret; | |
10194 | } | |
1da177e4 LT |
10195 | memcpy(pd + i, &val, 4); |
10196 | } | |
10197 | eeprom->len += i; | |
10198 | ||
10199 | if (len & 3) { | |
10200 | /* read last bytes not ending on 4 byte boundary */ | |
10201 | pd = &data[eeprom->len]; | |
10202 | b_count = len & 3; | |
10203 | b_offset = offset + len - b_count; | |
a9dc529d | 10204 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
10205 | if (ret) |
10206 | return ret; | |
b9fc7dc5 | 10207 | memcpy(pd, &val, b_count); |
1da177e4 LT |
10208 | eeprom->len += b_count; |
10209 | } | |
10210 | return 0; | |
10211 | } | |
10212 | ||
6aa20a22 | 10213 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
10214 | |
10215 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
10216 | { | |
10217 | struct tg3 *tp = netdev_priv(dev); | |
10218 | int ret; | |
b9fc7dc5 | 10219 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 10220 | u8 *buf; |
a9dc529d | 10221 | __be32 start, end; |
1da177e4 | 10222 | |
80096068 | 10223 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10224 | return -EAGAIN; |
10225 | ||
63c3a66f | 10226 | if (tg3_flag(tp, NO_NVRAM) || |
df259d8c | 10227 | eeprom->magic != TG3_EEPROM_MAGIC) |
1da177e4 LT |
10228 | return -EINVAL; |
10229 | ||
10230 | offset = eeprom->offset; | |
10231 | len = eeprom->len; | |
10232 | ||
10233 | if ((b_offset = (offset & 3))) { | |
10234 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 10235 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
10236 | if (ret) |
10237 | return ret; | |
1da177e4 LT |
10238 | len += b_offset; |
10239 | offset &= ~3; | |
1c8594b4 MC |
10240 | if (len < 4) |
10241 | len = 4; | |
1da177e4 LT |
10242 | } |
10243 | ||
10244 | odd_len = 0; | |
1c8594b4 | 10245 | if (len & 3) { |
1da177e4 LT |
10246 | /* adjustments to end on required 4 byte boundary */ |
10247 | odd_len = 1; | |
10248 | len = (len + 3) & ~3; | |
a9dc529d | 10249 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
10250 | if (ret) |
10251 | return ret; | |
1da177e4 LT |
10252 | } |
10253 | ||
10254 | buf = data; | |
10255 | if (b_offset || odd_len) { | |
10256 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 10257 | if (!buf) |
1da177e4 LT |
10258 | return -ENOMEM; |
10259 | if (b_offset) | |
10260 | memcpy(buf, &start, 4); | |
10261 | if (odd_len) | |
10262 | memcpy(buf+len-4, &end, 4); | |
10263 | memcpy(buf + b_offset, data, eeprom->len); | |
10264 | } | |
10265 | ||
10266 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
10267 | ||
10268 | if (buf != data) | |
10269 | kfree(buf); | |
10270 | ||
10271 | return ret; | |
10272 | } | |
10273 | ||
10274 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
10275 | { | |
b02fd9e3 MC |
10276 | struct tg3 *tp = netdev_priv(dev); |
10277 | ||
63c3a66f | 10278 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10279 | struct phy_device *phydev; |
f07e9af3 | 10280 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10281 | return -EAGAIN; |
3f0e3ad7 MC |
10282 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10283 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 10284 | } |
6aa20a22 | 10285 | |
1da177e4 LT |
10286 | cmd->supported = (SUPPORTED_Autoneg); |
10287 | ||
f07e9af3 | 10288 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
10289 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
10290 | SUPPORTED_1000baseT_Full); | |
10291 | ||
f07e9af3 | 10292 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
10293 | cmd->supported |= (SUPPORTED_100baseT_Half | |
10294 | SUPPORTED_100baseT_Full | | |
10295 | SUPPORTED_10baseT_Half | | |
10296 | SUPPORTED_10baseT_Full | | |
3bebab59 | 10297 | SUPPORTED_TP); |
ef348144 KK |
10298 | cmd->port = PORT_TP; |
10299 | } else { | |
1da177e4 | 10300 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
10301 | cmd->port = PORT_FIBRE; |
10302 | } | |
6aa20a22 | 10303 | |
1da177e4 | 10304 | cmd->advertising = tp->link_config.advertising; |
5bb09778 MC |
10305 | if (tg3_flag(tp, PAUSE_AUTONEG)) { |
10306 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) { | |
10307 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10308 | cmd->advertising |= ADVERTISED_Pause; | |
10309 | } else { | |
10310 | cmd->advertising |= ADVERTISED_Pause | | |
10311 | ADVERTISED_Asym_Pause; | |
10312 | } | |
10313 | } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10314 | cmd->advertising |= ADVERTISED_Asym_Pause; | |
10315 | } | |
10316 | } | |
859edb26 | 10317 | if (netif_running(dev) && netif_carrier_ok(dev)) { |
70739497 | 10318 | ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); |
1da177e4 | 10319 | cmd->duplex = tp->link_config.active_duplex; |
859edb26 | 10320 | cmd->lp_advertising = tp->link_config.rmt_adv; |
e348c5e7 MC |
10321 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
10322 | if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) | |
10323 | cmd->eth_tp_mdix = ETH_TP_MDI_X; | |
10324 | else | |
10325 | cmd->eth_tp_mdix = ETH_TP_MDI; | |
10326 | } | |
64c22182 | 10327 | } else { |
70739497 | 10328 | ethtool_cmd_speed_set(cmd, SPEED_INVALID); |
64c22182 | 10329 | cmd->duplex = DUPLEX_INVALID; |
e348c5e7 | 10330 | cmd->eth_tp_mdix = ETH_TP_MDI_INVALID; |
1da177e4 | 10331 | } |
882e9793 | 10332 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 10333 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
10334 | cmd->autoneg = tp->link_config.autoneg; |
10335 | cmd->maxtxpkt = 0; | |
10336 | cmd->maxrxpkt = 0; | |
10337 | return 0; | |
10338 | } | |
6aa20a22 | 10339 | |
1da177e4 LT |
10340 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
10341 | { | |
10342 | struct tg3 *tp = netdev_priv(dev); | |
25db0338 | 10343 | u32 speed = ethtool_cmd_speed(cmd); |
6aa20a22 | 10344 | |
63c3a66f | 10345 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10346 | struct phy_device *phydev; |
f07e9af3 | 10347 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10348 | return -EAGAIN; |
3f0e3ad7 MC |
10349 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10350 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
10351 | } |
10352 | ||
7e5856bd MC |
10353 | if (cmd->autoneg != AUTONEG_ENABLE && |
10354 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 10355 | return -EINVAL; |
7e5856bd MC |
10356 | |
10357 | if (cmd->autoneg == AUTONEG_DISABLE && | |
10358 | cmd->duplex != DUPLEX_FULL && | |
10359 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 10360 | return -EINVAL; |
1da177e4 | 10361 | |
7e5856bd MC |
10362 | if (cmd->autoneg == AUTONEG_ENABLE) { |
10363 | u32 mask = ADVERTISED_Autoneg | | |
10364 | ADVERTISED_Pause | | |
10365 | ADVERTISED_Asym_Pause; | |
10366 | ||
f07e9af3 | 10367 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
10368 | mask |= ADVERTISED_1000baseT_Half | |
10369 | ADVERTISED_1000baseT_Full; | |
10370 | ||
f07e9af3 | 10371 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
10372 | mask |= ADVERTISED_100baseT_Half | |
10373 | ADVERTISED_100baseT_Full | | |
10374 | ADVERTISED_10baseT_Half | | |
10375 | ADVERTISED_10baseT_Full | | |
10376 | ADVERTISED_TP; | |
10377 | else | |
10378 | mask |= ADVERTISED_FIBRE; | |
10379 | ||
10380 | if (cmd->advertising & ~mask) | |
10381 | return -EINVAL; | |
10382 | ||
10383 | mask &= (ADVERTISED_1000baseT_Half | | |
10384 | ADVERTISED_1000baseT_Full | | |
10385 | ADVERTISED_100baseT_Half | | |
10386 | ADVERTISED_100baseT_Full | | |
10387 | ADVERTISED_10baseT_Half | | |
10388 | ADVERTISED_10baseT_Full); | |
10389 | ||
10390 | cmd->advertising &= mask; | |
10391 | } else { | |
f07e9af3 | 10392 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
25db0338 | 10393 | if (speed != SPEED_1000) |
7e5856bd MC |
10394 | return -EINVAL; |
10395 | ||
10396 | if (cmd->duplex != DUPLEX_FULL) | |
10397 | return -EINVAL; | |
10398 | } else { | |
25db0338 DD |
10399 | if (speed != SPEED_100 && |
10400 | speed != SPEED_10) | |
7e5856bd MC |
10401 | return -EINVAL; |
10402 | } | |
10403 | } | |
10404 | ||
f47c11ee | 10405 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10406 | |
10407 | tp->link_config.autoneg = cmd->autoneg; | |
10408 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
10409 | tp->link_config.advertising = (cmd->advertising | |
10410 | ADVERTISED_Autoneg); | |
1da177e4 LT |
10411 | tp->link_config.speed = SPEED_INVALID; |
10412 | tp->link_config.duplex = DUPLEX_INVALID; | |
10413 | } else { | |
10414 | tp->link_config.advertising = 0; | |
25db0338 | 10415 | tp->link_config.speed = speed; |
1da177e4 | 10416 | tp->link_config.duplex = cmd->duplex; |
b02fd9e3 | 10417 | } |
6aa20a22 | 10418 | |
24fcad6b MC |
10419 | tp->link_config.orig_speed = tp->link_config.speed; |
10420 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
10421 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
10422 | ||
1da177e4 LT |
10423 | if (netif_running(dev)) |
10424 | tg3_setup_phy(tp, 1); | |
10425 | ||
f47c11ee | 10426 | tg3_full_unlock(tp); |
6aa20a22 | 10427 | |
1da177e4 LT |
10428 | return 0; |
10429 | } | |
6aa20a22 | 10430 | |
1da177e4 LT |
10431 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
10432 | { | |
10433 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10434 | |
68aad78c RJ |
10435 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
10436 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); | |
10437 | strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); | |
10438 | strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); | |
1da177e4 | 10439 | } |
6aa20a22 | 10440 | |
1da177e4 LT |
10441 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10442 | { | |
10443 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10444 | |
63c3a66f | 10445 | if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) |
a85feb8c GZ |
10446 | wol->supported = WAKE_MAGIC; |
10447 | else | |
10448 | wol->supported = 0; | |
1da177e4 | 10449 | wol->wolopts = 0; |
63c3a66f | 10450 | if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) |
1da177e4 LT |
10451 | wol->wolopts = WAKE_MAGIC; |
10452 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
10453 | } | |
6aa20a22 | 10454 | |
1da177e4 LT |
10455 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10456 | { | |
10457 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 10458 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 10459 | |
1da177e4 LT |
10460 | if (wol->wolopts & ~WAKE_MAGIC) |
10461 | return -EINVAL; | |
10462 | if ((wol->wolopts & WAKE_MAGIC) && | |
63c3a66f | 10463 | !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 10464 | return -EINVAL; |
6aa20a22 | 10465 | |
f2dc0d18 RW |
10466 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
10467 | ||
f47c11ee | 10468 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 10469 | if (device_may_wakeup(dp)) |
63c3a66f | 10470 | tg3_flag_set(tp, WOL_ENABLE); |
f2dc0d18 | 10471 | else |
63c3a66f | 10472 | tg3_flag_clear(tp, WOL_ENABLE); |
f47c11ee | 10473 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10474 | |
1da177e4 LT |
10475 | return 0; |
10476 | } | |
6aa20a22 | 10477 | |
1da177e4 LT |
10478 | static u32 tg3_get_msglevel(struct net_device *dev) |
10479 | { | |
10480 | struct tg3 *tp = netdev_priv(dev); | |
10481 | return tp->msg_enable; | |
10482 | } | |
6aa20a22 | 10483 | |
1da177e4 LT |
10484 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
10485 | { | |
10486 | struct tg3 *tp = netdev_priv(dev); | |
10487 | tp->msg_enable = value; | |
10488 | } | |
6aa20a22 | 10489 | |
1da177e4 LT |
10490 | static int tg3_nway_reset(struct net_device *dev) |
10491 | { | |
10492 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 10493 | int r; |
6aa20a22 | 10494 | |
1da177e4 LT |
10495 | if (!netif_running(dev)) |
10496 | return -EAGAIN; | |
10497 | ||
f07e9af3 | 10498 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
10499 | return -EINVAL; |
10500 | ||
63c3a66f | 10501 | if (tg3_flag(tp, USE_PHYLIB)) { |
f07e9af3 | 10502 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10503 | return -EAGAIN; |
3f0e3ad7 | 10504 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
10505 | } else { |
10506 | u32 bmcr; | |
10507 | ||
10508 | spin_lock_bh(&tp->lock); | |
10509 | r = -EINVAL; | |
10510 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10511 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10512 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 10513 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
10514 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
10515 | BMCR_ANENABLE); | |
10516 | r = 0; | |
10517 | } | |
10518 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 10519 | } |
6aa20a22 | 10520 | |
1da177e4 LT |
10521 | return r; |
10522 | } | |
6aa20a22 | 10523 | |
1da177e4 LT |
10524 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10525 | { | |
10526 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10527 | |
2c49a44d | 10528 | ering->rx_max_pending = tp->rx_std_ring_mask; |
63c3a66f | 10529 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
2c49a44d | 10530 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
10531 | else |
10532 | ering->rx_jumbo_max_pending = 0; | |
10533 | ||
10534 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
10535 | |
10536 | ering->rx_pending = tp->rx_pending; | |
63c3a66f | 10537 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
4f81c32b MC |
10538 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; |
10539 | else | |
10540 | ering->rx_jumbo_pending = 0; | |
10541 | ||
f3f3f27e | 10542 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 10543 | } |
6aa20a22 | 10544 | |
1da177e4 LT |
10545 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10546 | { | |
10547 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 10548 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 10549 | |
2c49a44d MC |
10550 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
10551 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
10552 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
10553 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
63c3a66f | 10554 | (tg3_flag(tp, TSO_BUG) && |
bc3a9254 | 10555 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 10556 | return -EINVAL; |
6aa20a22 | 10557 | |
bbe832c0 | 10558 | if (netif_running(dev)) { |
b02fd9e3 | 10559 | tg3_phy_stop(tp); |
1da177e4 | 10560 | tg3_netif_stop(tp); |
bbe832c0 MC |
10561 | irq_sync = 1; |
10562 | } | |
1da177e4 | 10563 | |
bbe832c0 | 10564 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 10565 | |
1da177e4 LT |
10566 | tp->rx_pending = ering->rx_pending; |
10567 | ||
63c3a66f | 10568 | if (tg3_flag(tp, MAX_RXPEND_64) && |
1da177e4 LT |
10569 | tp->rx_pending > 63) |
10570 | tp->rx_pending = 63; | |
10571 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 10572 | |
6fd45cb8 | 10573 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 10574 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
10575 | |
10576 | if (netif_running(dev)) { | |
944d980e | 10577 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
10578 | err = tg3_restart_hw(tp, 1); |
10579 | if (!err) | |
10580 | tg3_netif_start(tp); | |
1da177e4 LT |
10581 | } |
10582 | ||
f47c11ee | 10583 | tg3_full_unlock(tp); |
6aa20a22 | 10584 | |
b02fd9e3 MC |
10585 | if (irq_sync && !err) |
10586 | tg3_phy_start(tp); | |
10587 | ||
b9ec6c1b | 10588 | return err; |
1da177e4 | 10589 | } |
6aa20a22 | 10590 | |
1da177e4 LT |
10591 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10592 | { | |
10593 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10594 | |
63c3a66f | 10595 | epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); |
8d018621 | 10596 | |
4a2db503 | 10597 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
10598 | epause->rx_pause = 1; |
10599 | else | |
10600 | epause->rx_pause = 0; | |
10601 | ||
4a2db503 | 10602 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
10603 | epause->tx_pause = 1; |
10604 | else | |
10605 | epause->tx_pause = 0; | |
1da177e4 | 10606 | } |
6aa20a22 | 10607 | |
1da177e4 LT |
10608 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10609 | { | |
10610 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 10611 | int err = 0; |
6aa20a22 | 10612 | |
63c3a66f | 10613 | if (tg3_flag(tp, USE_PHYLIB)) { |
2712168f MC |
10614 | u32 newadv; |
10615 | struct phy_device *phydev; | |
1da177e4 | 10616 | |
2712168f | 10617 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 10618 | |
2712168f MC |
10619 | if (!(phydev->supported & SUPPORTED_Pause) || |
10620 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 10621 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 10622 | return -EINVAL; |
1da177e4 | 10623 | |
2712168f MC |
10624 | tp->link_config.flowctrl = 0; |
10625 | if (epause->rx_pause) { | |
10626 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10627 | ||
10628 | if (epause->tx_pause) { | |
10629 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10630 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 10631 | } else |
2712168f MC |
10632 | newadv = ADVERTISED_Pause | |
10633 | ADVERTISED_Asym_Pause; | |
10634 | } else if (epause->tx_pause) { | |
10635 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10636 | newadv = ADVERTISED_Asym_Pause; | |
10637 | } else | |
10638 | newadv = 0; | |
10639 | ||
10640 | if (epause->autoneg) | |
63c3a66f | 10641 | tg3_flag_set(tp, PAUSE_AUTONEG); |
2712168f | 10642 | else |
63c3a66f | 10643 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
2712168f | 10644 | |
f07e9af3 | 10645 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
10646 | u32 oldadv = phydev->advertising & |
10647 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10648 | if (oldadv != newadv) { | |
10649 | phydev->advertising &= | |
10650 | ~(ADVERTISED_Pause | | |
10651 | ADVERTISED_Asym_Pause); | |
10652 | phydev->advertising |= newadv; | |
10653 | if (phydev->autoneg) { | |
10654 | /* | |
10655 | * Always renegotiate the link to | |
10656 | * inform our link partner of our | |
10657 | * flow control settings, even if the | |
10658 | * flow control is forced. Let | |
10659 | * tg3_adjust_link() do the final | |
10660 | * flow control setup. | |
10661 | */ | |
10662 | return phy_start_aneg(phydev); | |
b02fd9e3 | 10663 | } |
b02fd9e3 | 10664 | } |
b02fd9e3 | 10665 | |
2712168f | 10666 | if (!epause->autoneg) |
b02fd9e3 | 10667 | tg3_setup_flow_control(tp, 0, 0); |
2712168f MC |
10668 | } else { |
10669 | tp->link_config.orig_advertising &= | |
10670 | ~(ADVERTISED_Pause | | |
10671 | ADVERTISED_Asym_Pause); | |
10672 | tp->link_config.orig_advertising |= newadv; | |
b02fd9e3 MC |
10673 | } |
10674 | } else { | |
10675 | int irq_sync = 0; | |
10676 | ||
10677 | if (netif_running(dev)) { | |
10678 | tg3_netif_stop(tp); | |
10679 | irq_sync = 1; | |
10680 | } | |
10681 | ||
10682 | tg3_full_lock(tp, irq_sync); | |
10683 | ||
10684 | if (epause->autoneg) | |
63c3a66f | 10685 | tg3_flag_set(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10686 | else |
63c3a66f | 10687 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
b02fd9e3 | 10688 | if (epause->rx_pause) |
e18ce346 | 10689 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 10690 | else |
e18ce346 | 10691 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 10692 | if (epause->tx_pause) |
e18ce346 | 10693 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 10694 | else |
e18ce346 | 10695 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
10696 | |
10697 | if (netif_running(dev)) { | |
10698 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10699 | err = tg3_restart_hw(tp, 1); | |
10700 | if (!err) | |
10701 | tg3_netif_start(tp); | |
10702 | } | |
10703 | ||
10704 | tg3_full_unlock(tp); | |
10705 | } | |
6aa20a22 | 10706 | |
b9ec6c1b | 10707 | return err; |
1da177e4 | 10708 | } |
6aa20a22 | 10709 | |
de6f31eb | 10710 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10711 | { |
b9f2c044 JG |
10712 | switch (sset) { |
10713 | case ETH_SS_TEST: | |
10714 | return TG3_NUM_TEST; | |
10715 | case ETH_SS_STATS: | |
10716 | return TG3_NUM_STATS; | |
10717 | default: | |
10718 | return -EOPNOTSUPP; | |
10719 | } | |
4cafd3f5 MC |
10720 | } |
10721 | ||
de6f31eb | 10722 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
10723 | { |
10724 | switch (stringset) { | |
10725 | case ETH_SS_STATS: | |
10726 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10727 | break; | |
4cafd3f5 MC |
10728 | case ETH_SS_TEST: |
10729 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10730 | break; | |
1da177e4 LT |
10731 | default: |
10732 | WARN_ON(1); /* we need a WARN() */ | |
10733 | break; | |
10734 | } | |
10735 | } | |
10736 | ||
81b8709c | 10737 | static int tg3_set_phys_id(struct net_device *dev, |
10738 | enum ethtool_phys_id_state state) | |
4009a93d MC |
10739 | { |
10740 | struct tg3 *tp = netdev_priv(dev); | |
4009a93d MC |
10741 | |
10742 | if (!netif_running(tp->dev)) | |
10743 | return -EAGAIN; | |
10744 | ||
81b8709c | 10745 | switch (state) { |
10746 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 10747 | return 1; /* cycle on/off once per second */ |
4009a93d | 10748 | |
81b8709c | 10749 | case ETHTOOL_ID_ON: |
10750 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10751 | LED_CTRL_1000MBPS_ON | | |
10752 | LED_CTRL_100MBPS_ON | | |
10753 | LED_CTRL_10MBPS_ON | | |
10754 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10755 | LED_CTRL_TRAFFIC_BLINK | | |
10756 | LED_CTRL_TRAFFIC_LED); | |
10757 | break; | |
6aa20a22 | 10758 | |
81b8709c | 10759 | case ETHTOOL_ID_OFF: |
10760 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10761 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10762 | break; | |
4009a93d | 10763 | |
81b8709c | 10764 | case ETHTOOL_ID_INACTIVE: |
10765 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10766 | break; | |
4009a93d | 10767 | } |
81b8709c | 10768 | |
4009a93d MC |
10769 | return 0; |
10770 | } | |
10771 | ||
de6f31eb | 10772 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
10773 | struct ethtool_stats *estats, u64 *tmp_stats) |
10774 | { | |
10775 | struct tg3 *tp = netdev_priv(dev); | |
0e6c9da3 MC |
10776 | |
10777 | tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); | |
1da177e4 LT |
10778 | } |
10779 | ||
535a490e | 10780 | static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen) |
c3e94500 MC |
10781 | { |
10782 | int i; | |
10783 | __be32 *buf; | |
10784 | u32 offset = 0, len = 0; | |
10785 | u32 magic, val; | |
10786 | ||
63c3a66f | 10787 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) |
c3e94500 MC |
10788 | return NULL; |
10789 | ||
10790 | if (magic == TG3_EEPROM_MAGIC) { | |
10791 | for (offset = TG3_NVM_DIR_START; | |
10792 | offset < TG3_NVM_DIR_END; | |
10793 | offset += TG3_NVM_DIRENT_SIZE) { | |
10794 | if (tg3_nvram_read(tp, offset, &val)) | |
10795 | return NULL; | |
10796 | ||
10797 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
10798 | TG3_NVM_DIRTYPE_EXTVPD) | |
10799 | break; | |
10800 | } | |
10801 | ||
10802 | if (offset != TG3_NVM_DIR_END) { | |
10803 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
10804 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
10805 | return NULL; | |
10806 | ||
10807 | offset = tg3_nvram_logical_addr(tp, offset); | |
10808 | } | |
10809 | } | |
10810 | ||
10811 | if (!offset || !len) { | |
10812 | offset = TG3_NVM_VPD_OFF; | |
10813 | len = TG3_NVM_VPD_LEN; | |
10814 | } | |
10815 | ||
10816 | buf = kmalloc(len, GFP_KERNEL); | |
10817 | if (buf == NULL) | |
10818 | return NULL; | |
10819 | ||
10820 | if (magic == TG3_EEPROM_MAGIC) { | |
10821 | for (i = 0; i < len; i += 4) { | |
10822 | /* The data is in little-endian format in NVRAM. | |
10823 | * Use the big-endian read routines to preserve | |
10824 | * the byte order as it exists in NVRAM. | |
10825 | */ | |
10826 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
10827 | goto error; | |
10828 | } | |
10829 | } else { | |
10830 | u8 *ptr; | |
10831 | ssize_t cnt; | |
10832 | unsigned int pos = 0; | |
10833 | ||
10834 | ptr = (u8 *)&buf[0]; | |
10835 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
10836 | cnt = pci_read_vpd(tp->pdev, pos, | |
10837 | len - pos, ptr); | |
10838 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
10839 | cnt = 0; | |
10840 | else if (cnt < 0) | |
10841 | goto error; | |
10842 | } | |
10843 | if (pos != len) | |
10844 | goto error; | |
10845 | } | |
10846 | ||
535a490e MC |
10847 | *vpdlen = len; |
10848 | ||
c3e94500 MC |
10849 | return buf; |
10850 | ||
10851 | error: | |
10852 | kfree(buf); | |
10853 | return NULL; | |
10854 | } | |
10855 | ||
566f86ad | 10856 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
10857 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
10858 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10859 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
727a6d9f MC |
10860 | #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 |
10861 | #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 | |
bda18faf | 10862 | #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50 |
b16250e3 MC |
10863 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
10864 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
10865 | |
10866 | static int tg3_test_nvram(struct tg3 *tp) | |
10867 | { | |
535a490e | 10868 | u32 csum, magic, len; |
a9dc529d | 10869 | __be32 *buf; |
ab0049b4 | 10870 | int i, j, k, err = 0, size; |
566f86ad | 10871 | |
63c3a66f | 10872 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10873 | return 0; |
10874 | ||
e4f34110 | 10875 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
10876 | return -EIO; |
10877 | ||
1b27777a MC |
10878 | if (magic == TG3_EEPROM_MAGIC) |
10879 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 10880 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
10881 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
10882 | TG3_EEPROM_SB_FORMAT_1) { | |
10883 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10884 | case TG3_EEPROM_SB_REVISION_0: | |
10885 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10886 | break; | |
10887 | case TG3_EEPROM_SB_REVISION_2: | |
10888 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10889 | break; | |
10890 | case TG3_EEPROM_SB_REVISION_3: | |
10891 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10892 | break; | |
727a6d9f MC |
10893 | case TG3_EEPROM_SB_REVISION_4: |
10894 | size = NVRAM_SELFBOOT_FORMAT1_4_SIZE; | |
10895 | break; | |
10896 | case TG3_EEPROM_SB_REVISION_5: | |
10897 | size = NVRAM_SELFBOOT_FORMAT1_5_SIZE; | |
10898 | break; | |
10899 | case TG3_EEPROM_SB_REVISION_6: | |
10900 | size = NVRAM_SELFBOOT_FORMAT1_6_SIZE; | |
10901 | break; | |
a5767dec | 10902 | default: |
727a6d9f | 10903 | return -EIO; |
a5767dec MC |
10904 | } |
10905 | } else | |
1b27777a | 10906 | return 0; |
b16250e3 MC |
10907 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
10908 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10909 | else | |
1b27777a MC |
10910 | return -EIO; |
10911 | ||
10912 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
10913 | if (buf == NULL) |
10914 | return -ENOMEM; | |
10915 | ||
1b27777a MC |
10916 | err = -EIO; |
10917 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
10918 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
10919 | if (err) | |
566f86ad | 10920 | break; |
566f86ad | 10921 | } |
1b27777a | 10922 | if (i < size) |
566f86ad MC |
10923 | goto out; |
10924 | ||
1b27777a | 10925 | /* Selfboot format */ |
a9dc529d | 10926 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 10927 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 10928 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
10929 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
10930 | ||
b9fc7dc5 | 10931 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
10932 | TG3_EEPROM_SB_REVISION_2) { |
10933 | /* For rev 2, the csum doesn't include the MBA. */ | |
10934 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10935 | csum8 += buf8[i]; | |
10936 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10937 | csum8 += buf8[i]; | |
10938 | } else { | |
10939 | for (i = 0; i < size; i++) | |
10940 | csum8 += buf8[i]; | |
10941 | } | |
1b27777a | 10942 | |
ad96b485 AB |
10943 | if (csum8 == 0) { |
10944 | err = 0; | |
10945 | goto out; | |
10946 | } | |
10947 | ||
10948 | err = -EIO; | |
10949 | goto out; | |
1b27777a | 10950 | } |
566f86ad | 10951 | |
b9fc7dc5 | 10952 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
10953 | TG3_EEPROM_MAGIC_HW) { |
10954 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 10955 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 10956 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
10957 | |
10958 | /* Separate the parity bits and the data bytes. */ | |
10959 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10960 | if ((i == 0) || (i == 8)) { | |
10961 | int l; | |
10962 | u8 msk; | |
10963 | ||
10964 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10965 | parity[k++] = buf8[i] & msk; | |
10966 | i++; | |
859a5887 | 10967 | } else if (i == 16) { |
b16250e3 MC |
10968 | int l; |
10969 | u8 msk; | |
10970 | ||
10971 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10972 | parity[k++] = buf8[i] & msk; | |
10973 | i++; | |
10974 | ||
10975 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10976 | parity[k++] = buf8[i] & msk; | |
10977 | i++; | |
10978 | } | |
10979 | data[j++] = buf8[i]; | |
10980 | } | |
10981 | ||
10982 | err = -EIO; | |
10983 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10984 | u8 hw8 = hweight8(data[i]); | |
10985 | ||
10986 | if ((hw8 & 0x1) && parity[i]) | |
10987 | goto out; | |
10988 | else if (!(hw8 & 0x1) && !parity[i]) | |
10989 | goto out; | |
10990 | } | |
10991 | err = 0; | |
10992 | goto out; | |
10993 | } | |
10994 | ||
01c3a392 MC |
10995 | err = -EIO; |
10996 | ||
566f86ad MC |
10997 | /* Bootstrap checksum at offset 0x10 */ |
10998 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 10999 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
11000 | goto out; |
11001 | ||
11002 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
11003 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 11004 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 11005 | goto out; |
566f86ad | 11006 | |
c3e94500 MC |
11007 | kfree(buf); |
11008 | ||
535a490e | 11009 | buf = tg3_vpd_readblock(tp, &len); |
c3e94500 MC |
11010 | if (!buf) |
11011 | return -ENOMEM; | |
d4894f3e | 11012 | |
535a490e | 11013 | i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA); |
d4894f3e MC |
11014 | if (i > 0) { |
11015 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
11016 | if (j < 0) | |
11017 | goto out; | |
11018 | ||
535a490e | 11019 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > len) |
d4894f3e MC |
11020 | goto out; |
11021 | ||
11022 | i += PCI_VPD_LRDT_TAG_SIZE; | |
11023 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
11024 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
11025 | if (j > 0) { | |
11026 | u8 csum8 = 0; | |
11027 | ||
11028 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11029 | ||
11030 | for (i = 0; i <= j; i++) | |
11031 | csum8 += ((u8 *)buf)[i]; | |
11032 | ||
11033 | if (csum8) | |
11034 | goto out; | |
11035 | } | |
11036 | } | |
11037 | ||
566f86ad MC |
11038 | err = 0; |
11039 | ||
11040 | out: | |
11041 | kfree(buf); | |
11042 | return err; | |
11043 | } | |
11044 | ||
ca43007a MC |
11045 | #define TG3_SERDES_TIMEOUT_SEC 2 |
11046 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
11047 | ||
11048 | static int tg3_test_link(struct tg3 *tp) | |
11049 | { | |
11050 | int i, max; | |
11051 | ||
11052 | if (!netif_running(tp->dev)) | |
11053 | return -ENODEV; | |
11054 | ||
f07e9af3 | 11055 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
11056 | max = TG3_SERDES_TIMEOUT_SEC; |
11057 | else | |
11058 | max = TG3_COPPER_TIMEOUT_SEC; | |
11059 | ||
11060 | for (i = 0; i < max; i++) { | |
11061 | if (netif_carrier_ok(tp->dev)) | |
11062 | return 0; | |
11063 | ||
11064 | if (msleep_interruptible(1000)) | |
11065 | break; | |
11066 | } | |
11067 | ||
11068 | return -EIO; | |
11069 | } | |
11070 | ||
a71116d1 | 11071 | /* Only test the commonly used registers */ |
30ca3e37 | 11072 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 11073 | { |
b16250e3 | 11074 | int i, is_5705, is_5750; |
a71116d1 MC |
11075 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
11076 | static struct { | |
11077 | u16 offset; | |
11078 | u16 flags; | |
11079 | #define TG3_FL_5705 0x1 | |
11080 | #define TG3_FL_NOT_5705 0x2 | |
11081 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 11082 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
11083 | u32 read_mask; |
11084 | u32 write_mask; | |
11085 | } reg_tbl[] = { | |
11086 | /* MAC Control Registers */ | |
11087 | { MAC_MODE, TG3_FL_NOT_5705, | |
11088 | 0x00000000, 0x00ef6f8c }, | |
11089 | { MAC_MODE, TG3_FL_5705, | |
11090 | 0x00000000, 0x01ef6b8c }, | |
11091 | { MAC_STATUS, TG3_FL_NOT_5705, | |
11092 | 0x03800107, 0x00000000 }, | |
11093 | { MAC_STATUS, TG3_FL_5705, | |
11094 | 0x03800100, 0x00000000 }, | |
11095 | { MAC_ADDR_0_HIGH, 0x0000, | |
11096 | 0x00000000, 0x0000ffff }, | |
11097 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 11098 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
11099 | { MAC_RX_MTU_SIZE, 0x0000, |
11100 | 0x00000000, 0x0000ffff }, | |
11101 | { MAC_TX_MODE, 0x0000, | |
11102 | 0x00000000, 0x00000070 }, | |
11103 | { MAC_TX_LENGTHS, 0x0000, | |
11104 | 0x00000000, 0x00003fff }, | |
11105 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
11106 | 0x00000000, 0x000007fc }, | |
11107 | { MAC_RX_MODE, TG3_FL_5705, | |
11108 | 0x00000000, 0x000007dc }, | |
11109 | { MAC_HASH_REG_0, 0x0000, | |
11110 | 0x00000000, 0xffffffff }, | |
11111 | { MAC_HASH_REG_1, 0x0000, | |
11112 | 0x00000000, 0xffffffff }, | |
11113 | { MAC_HASH_REG_2, 0x0000, | |
11114 | 0x00000000, 0xffffffff }, | |
11115 | { MAC_HASH_REG_3, 0x0000, | |
11116 | 0x00000000, 0xffffffff }, | |
11117 | ||
11118 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
11119 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
11120 | 0x00000000, 0xffffffff }, | |
11121 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
11122 | 0x00000000, 0xffffffff }, | |
11123 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
11124 | 0x00000000, 0x00000003 }, | |
11125 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
11126 | 0x00000000, 0xffffffff }, | |
11127 | { RCVDBDI_STD_BD+0, 0x0000, | |
11128 | 0x00000000, 0xffffffff }, | |
11129 | { RCVDBDI_STD_BD+4, 0x0000, | |
11130 | 0x00000000, 0xffffffff }, | |
11131 | { RCVDBDI_STD_BD+8, 0x0000, | |
11132 | 0x00000000, 0xffff0002 }, | |
11133 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
11134 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 11135 | |
a71116d1 MC |
11136 | /* Receive BD Initiator Control Registers. */ |
11137 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
11138 | 0x00000000, 0xffffffff }, | |
11139 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
11140 | 0x00000000, 0x000003ff }, | |
11141 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
11142 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 11143 | |
a71116d1 MC |
11144 | /* Host Coalescing Control Registers. */ |
11145 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
11146 | 0x00000000, 0x00000004 }, | |
11147 | { HOSTCC_MODE, TG3_FL_5705, | |
11148 | 0x00000000, 0x000000f6 }, | |
11149 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
11150 | 0x00000000, 0xffffffff }, | |
11151 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
11152 | 0x00000000, 0x000003ff }, | |
11153 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
11154 | 0x00000000, 0xffffffff }, | |
11155 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
11156 | 0x00000000, 0x000003ff }, | |
11157 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
11158 | 0x00000000, 0xffffffff }, | |
11159 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11160 | 0x00000000, 0x000000ff }, | |
11161 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
11162 | 0x00000000, 0xffffffff }, | |
11163 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11164 | 0x00000000, 0x000000ff }, | |
11165 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
11166 | 0x00000000, 0xffffffff }, | |
11167 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
11168 | 0x00000000, 0xffffffff }, | |
11169 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
11170 | 0x00000000, 0xffffffff }, | |
11171 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11172 | 0x00000000, 0x000000ff }, | |
11173 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
11174 | 0x00000000, 0xffffffff }, | |
11175 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11176 | 0x00000000, 0x000000ff }, | |
11177 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
11178 | 0x00000000, 0xffffffff }, | |
11179 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
11180 | 0x00000000, 0xffffffff }, | |
11181 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
11182 | 0x00000000, 0xffffffff }, | |
11183 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
11184 | 0x00000000, 0xffffffff }, | |
11185 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
11186 | 0x00000000, 0xffffffff }, | |
11187 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
11188 | 0xffffffff, 0x00000000 }, | |
11189 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
11190 | 0xffffffff, 0x00000000 }, | |
11191 | ||
11192 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 11193 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 11194 | 0x00000000, 0x007fff80 }, |
b16250e3 | 11195 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
11196 | 0x00000000, 0x007fffff }, |
11197 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
11198 | 0x00000000, 0x0000003f }, | |
11199 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
11200 | 0x00000000, 0x000001ff }, | |
11201 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
11202 | 0x00000000, 0x000001ff }, | |
11203 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
11204 | 0xffffffff, 0x00000000 }, | |
11205 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
11206 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 11207 | |
a71116d1 MC |
11208 | /* Mailbox Registers */ |
11209 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
11210 | 0x00000000, 0x000001ff }, | |
11211 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
11212 | 0x00000000, 0x000001ff }, | |
11213 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
11214 | 0x00000000, 0x000007ff }, | |
11215 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
11216 | 0x00000000, 0x000001ff }, | |
11217 | ||
11218 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
11219 | }; | |
11220 | ||
b16250e3 | 11221 | is_5705 = is_5750 = 0; |
63c3a66f | 11222 | if (tg3_flag(tp, 5705_PLUS)) { |
a71116d1 | 11223 | is_5705 = 1; |
63c3a66f | 11224 | if (tg3_flag(tp, 5750_PLUS)) |
b16250e3 MC |
11225 | is_5750 = 1; |
11226 | } | |
a71116d1 MC |
11227 | |
11228 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
11229 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
11230 | continue; | |
11231 | ||
11232 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
11233 | continue; | |
11234 | ||
63c3a66f | 11235 | if (tg3_flag(tp, IS_5788) && |
a71116d1 MC |
11236 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) |
11237 | continue; | |
11238 | ||
b16250e3 MC |
11239 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
11240 | continue; | |
11241 | ||
a71116d1 MC |
11242 | offset = (u32) reg_tbl[i].offset; |
11243 | read_mask = reg_tbl[i].read_mask; | |
11244 | write_mask = reg_tbl[i].write_mask; | |
11245 | ||
11246 | /* Save the original register content */ | |
11247 | save_val = tr32(offset); | |
11248 | ||
11249 | /* Determine the read-only value. */ | |
11250 | read_val = save_val & read_mask; | |
11251 | ||
11252 | /* Write zero to the register, then make sure the read-only bits | |
11253 | * are not changed and the read/write bits are all zeros. | |
11254 | */ | |
11255 | tw32(offset, 0); | |
11256 | ||
11257 | val = tr32(offset); | |
11258 | ||
11259 | /* Test the read-only and read/write bits. */ | |
11260 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
11261 | goto out; | |
11262 | ||
11263 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
11264 | * make sure the read-only bits are not changed and the | |
11265 | * read/write bits are all ones. | |
11266 | */ | |
11267 | tw32(offset, read_mask | write_mask); | |
11268 | ||
11269 | val = tr32(offset); | |
11270 | ||
11271 | /* Test the read-only bits. */ | |
11272 | if ((val & read_mask) != read_val) | |
11273 | goto out; | |
11274 | ||
11275 | /* Test the read/write bits. */ | |
11276 | if ((val & write_mask) != write_mask) | |
11277 | goto out; | |
11278 | ||
11279 | tw32(offset, save_val); | |
11280 | } | |
11281 | ||
11282 | return 0; | |
11283 | ||
11284 | out: | |
9f88f29f | 11285 | if (netif_msg_hw(tp)) |
2445e461 MC |
11286 | netdev_err(tp->dev, |
11287 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
11288 | tw32(offset, save_val); |
11289 | return -EIO; | |
11290 | } | |
11291 | ||
7942e1db MC |
11292 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
11293 | { | |
f71e1309 | 11294 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
11295 | int i; |
11296 | u32 j; | |
11297 | ||
e9edda69 | 11298 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
11299 | for (j = 0; j < len; j += 4) { |
11300 | u32 val; | |
11301 | ||
11302 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
11303 | tg3_read_mem(tp, offset + j, &val); | |
11304 | if (val != test_pattern[i]) | |
11305 | return -EIO; | |
11306 | } | |
11307 | } | |
11308 | return 0; | |
11309 | } | |
11310 | ||
11311 | static int tg3_test_memory(struct tg3 *tp) | |
11312 | { | |
11313 | static struct mem_entry { | |
11314 | u32 offset; | |
11315 | u32 len; | |
11316 | } mem_tbl_570x[] = { | |
38690194 | 11317 | { 0x00000000, 0x00b50}, |
7942e1db MC |
11318 | { 0x00002000, 0x1c000}, |
11319 | { 0xffffffff, 0x00000} | |
11320 | }, mem_tbl_5705[] = { | |
11321 | { 0x00000100, 0x0000c}, | |
11322 | { 0x00000200, 0x00008}, | |
7942e1db MC |
11323 | { 0x00004000, 0x00800}, |
11324 | { 0x00006000, 0x01000}, | |
11325 | { 0x00008000, 0x02000}, | |
11326 | { 0x00010000, 0x0e000}, | |
11327 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
11328 | }, mem_tbl_5755[] = { |
11329 | { 0x00000200, 0x00008}, | |
11330 | { 0x00004000, 0x00800}, | |
11331 | { 0x00006000, 0x00800}, | |
11332 | { 0x00008000, 0x02000}, | |
11333 | { 0x00010000, 0x0c000}, | |
11334 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
11335 | }, mem_tbl_5906[] = { |
11336 | { 0x00000200, 0x00008}, | |
11337 | { 0x00004000, 0x00400}, | |
11338 | { 0x00006000, 0x00400}, | |
11339 | { 0x00008000, 0x01000}, | |
11340 | { 0x00010000, 0x01000}, | |
11341 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
11342 | }, mem_tbl_5717[] = { |
11343 | { 0x00000200, 0x00008}, | |
11344 | { 0x00010000, 0x0a000}, | |
11345 | { 0x00020000, 0x13c00}, | |
11346 | { 0xffffffff, 0x00000} | |
11347 | }, mem_tbl_57765[] = { | |
11348 | { 0x00000200, 0x00008}, | |
11349 | { 0x00004000, 0x00800}, | |
11350 | { 0x00006000, 0x09800}, | |
11351 | { 0x00010000, 0x0a000}, | |
11352 | { 0xffffffff, 0x00000} | |
7942e1db MC |
11353 | }; |
11354 | struct mem_entry *mem_tbl; | |
11355 | int err = 0; | |
11356 | int i; | |
11357 | ||
63c3a66f | 11358 | if (tg3_flag(tp, 5717_PLUS)) |
8b5a6c42 | 11359 | mem_tbl = mem_tbl_5717; |
55086ad9 | 11360 | else if (tg3_flag(tp, 57765_CLASS)) |
8b5a6c42 | 11361 | mem_tbl = mem_tbl_57765; |
63c3a66f | 11362 | else if (tg3_flag(tp, 5755_PLUS)) |
321d32a0 MC |
11363 | mem_tbl = mem_tbl_5755; |
11364 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11365 | mem_tbl = mem_tbl_5906; | |
63c3a66f | 11366 | else if (tg3_flag(tp, 5705_PLUS)) |
321d32a0 MC |
11367 | mem_tbl = mem_tbl_5705; |
11368 | else | |
7942e1db MC |
11369 | mem_tbl = mem_tbl_570x; |
11370 | ||
11371 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
11372 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
11373 | if (err) | |
7942e1db MC |
11374 | break; |
11375 | } | |
6aa20a22 | 11376 | |
7942e1db MC |
11377 | return err; |
11378 | } | |
11379 | ||
bb158d69 MC |
11380 | #define TG3_TSO_MSS 500 |
11381 | ||
11382 | #define TG3_TSO_IP_HDR_LEN 20 | |
11383 | #define TG3_TSO_TCP_HDR_LEN 20 | |
11384 | #define TG3_TSO_TCP_OPT_LEN 12 | |
11385 | ||
11386 | static const u8 tg3_tso_header[] = { | |
11387 | 0x08, 0x00, | |
11388 | 0x45, 0x00, 0x00, 0x00, | |
11389 | 0x00, 0x00, 0x40, 0x00, | |
11390 | 0x40, 0x06, 0x00, 0x00, | |
11391 | 0x0a, 0x00, 0x00, 0x01, | |
11392 | 0x0a, 0x00, 0x00, 0x02, | |
11393 | 0x0d, 0x00, 0xe0, 0x00, | |
11394 | 0x00, 0x00, 0x01, 0x00, | |
11395 | 0x00, 0x00, 0x02, 0x00, | |
11396 | 0x80, 0x10, 0x10, 0x00, | |
11397 | 0x14, 0x09, 0x00, 0x00, | |
11398 | 0x01, 0x01, 0x08, 0x0a, | |
11399 | 0x11, 0x11, 0x11, 0x11, | |
11400 | 0x11, 0x11, 0x11, 0x11, | |
11401 | }; | |
9f40dead | 11402 | |
28a45957 | 11403 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) |
c76949a6 | 11404 | { |
5e5a7f37 | 11405 | u32 rx_start_idx, rx_idx, tx_idx, opaque_key; |
bb158d69 | 11406 | u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; |
84b67b27 | 11407 | u32 budget; |
9205fd9c ED |
11408 | struct sk_buff *skb; |
11409 | u8 *tx_data, *rx_data; | |
c76949a6 MC |
11410 | dma_addr_t map; |
11411 | int num_pkts, tx_len, rx_len, i, err; | |
11412 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 11413 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 11414 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 11415 | |
c8873405 MC |
11416 | tnapi = &tp->napi[0]; |
11417 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 11418 | if (tp->irq_cnt > 1) { |
63c3a66f | 11419 | if (tg3_flag(tp, ENABLE_RSS)) |
1da85aa3 | 11420 | rnapi = &tp->napi[1]; |
63c3a66f | 11421 | if (tg3_flag(tp, ENABLE_TSS)) |
c8873405 | 11422 | tnapi = &tp->napi[1]; |
0c1d0e2b | 11423 | } |
fd2ce37f | 11424 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 11425 | |
c76949a6 MC |
11426 | err = -EIO; |
11427 | ||
4852a861 | 11428 | tx_len = pktsz; |
a20e9c62 | 11429 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
11430 | if (!skb) |
11431 | return -ENOMEM; | |
11432 | ||
c76949a6 MC |
11433 | tx_data = skb_put(skb, tx_len); |
11434 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
11435 | memset(tx_data + 6, 0x0, 8); | |
11436 | ||
4852a861 | 11437 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
c76949a6 | 11438 | |
28a45957 | 11439 | if (tso_loopback) { |
bb158d69 MC |
11440 | struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN]; |
11441 | ||
11442 | u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN + | |
11443 | TG3_TSO_TCP_OPT_LEN; | |
11444 | ||
11445 | memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header, | |
11446 | sizeof(tg3_tso_header)); | |
11447 | mss = TG3_TSO_MSS; | |
11448 | ||
11449 | val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); | |
11450 | num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); | |
11451 | ||
11452 | /* Set the total length field in the IP header */ | |
11453 | iph->tot_len = htons((u16)(mss + hdr_len)); | |
11454 | ||
11455 | base_flags = (TXD_FLAG_CPU_PRE_DMA | | |
11456 | TXD_FLAG_CPU_POST_DMA); | |
11457 | ||
63c3a66f JP |
11458 | if (tg3_flag(tp, HW_TSO_1) || |
11459 | tg3_flag(tp, HW_TSO_2) || | |
11460 | tg3_flag(tp, HW_TSO_3)) { | |
bb158d69 MC |
11461 | struct tcphdr *th; |
11462 | val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; | |
11463 | th = (struct tcphdr *)&tx_data[val]; | |
11464 | th->check = 0; | |
11465 | } else | |
11466 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
11467 | ||
63c3a66f | 11468 | if (tg3_flag(tp, HW_TSO_3)) { |
bb158d69 MC |
11469 | mss |= (hdr_len & 0xc) << 12; |
11470 | if (hdr_len & 0x10) | |
11471 | base_flags |= 0x00000010; | |
11472 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 11473 | } else if (tg3_flag(tp, HW_TSO_2)) |
bb158d69 | 11474 | mss |= hdr_len << 9; |
63c3a66f | 11475 | else if (tg3_flag(tp, HW_TSO_1) || |
bb158d69 MC |
11476 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
11477 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); | |
11478 | } else { | |
11479 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); | |
11480 | } | |
11481 | ||
11482 | data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header); | |
11483 | } else { | |
11484 | num_pkts = 1; | |
11485 | data_off = ETH_HLEN; | |
11486 | } | |
11487 | ||
11488 | for (i = data_off; i < tx_len; i++) | |
c76949a6 MC |
11489 | tx_data[i] = (u8) (i & 0xff); |
11490 | ||
f4188d8a AD |
11491 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
11492 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
11493 | dev_kfree_skb(skb); |
11494 | return -EIO; | |
11495 | } | |
c76949a6 | 11496 | |
0d681b27 MC |
11497 | val = tnapi->tx_prod; |
11498 | tnapi->tx_buffers[val].skb = skb; | |
11499 | dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); | |
11500 | ||
c76949a6 | 11501 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11502 | rnapi->coal_now); |
c76949a6 MC |
11503 | |
11504 | udelay(10); | |
11505 | ||
898a56f8 | 11506 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 11507 | |
84b67b27 MC |
11508 | budget = tg3_tx_avail(tnapi); |
11509 | if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len, | |
d1a3b737 MC |
11510 | base_flags | TXD_FLAG_END, mss, 0)) { |
11511 | tnapi->tx_buffers[val].skb = NULL; | |
11512 | dev_kfree_skb(skb); | |
11513 | return -EIO; | |
11514 | } | |
c76949a6 | 11515 | |
f3f3f27e | 11516 | tnapi->tx_prod++; |
c76949a6 | 11517 | |
f3f3f27e MC |
11518 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
11519 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
11520 | |
11521 | udelay(10); | |
11522 | ||
303fc921 MC |
11523 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
11524 | for (i = 0; i < 35; i++) { | |
c76949a6 | 11525 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11526 | coal_now); |
c76949a6 MC |
11527 | |
11528 | udelay(10); | |
11529 | ||
898a56f8 MC |
11530 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
11531 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 11532 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
11533 | (rx_idx == (rx_start_idx + num_pkts))) |
11534 | break; | |
11535 | } | |
11536 | ||
ba1142e4 | 11537 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); |
c76949a6 MC |
11538 | dev_kfree_skb(skb); |
11539 | ||
f3f3f27e | 11540 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
11541 | goto out; |
11542 | ||
11543 | if (rx_idx != rx_start_idx + num_pkts) | |
11544 | goto out; | |
11545 | ||
bb158d69 MC |
11546 | val = data_off; |
11547 | while (rx_idx != rx_start_idx) { | |
11548 | desc = &rnapi->rx_rcb[rx_start_idx++]; | |
11549 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
11550 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
c76949a6 | 11551 | |
bb158d69 MC |
11552 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && |
11553 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
11554 | goto out; | |
c76949a6 | 11555 | |
bb158d69 MC |
11556 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) |
11557 | - ETH_FCS_LEN; | |
c76949a6 | 11558 | |
28a45957 | 11559 | if (!tso_loopback) { |
bb158d69 MC |
11560 | if (rx_len != tx_len) |
11561 | goto out; | |
4852a861 | 11562 | |
bb158d69 MC |
11563 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
11564 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
11565 | goto out; | |
11566 | } else { | |
11567 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
11568 | goto out; | |
11569 | } | |
11570 | } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
11571 | (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
54e0a67f | 11572 | >> RXD_TCPCSUM_SHIFT != 0xffff) { |
4852a861 | 11573 | goto out; |
bb158d69 | 11574 | } |
4852a861 | 11575 | |
bb158d69 | 11576 | if (opaque_key == RXD_OPAQUE_RING_STD) { |
9205fd9c | 11577 | rx_data = tpr->rx_std_buffers[desc_idx].data; |
bb158d69 MC |
11578 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], |
11579 | mapping); | |
11580 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
9205fd9c | 11581 | rx_data = tpr->rx_jmb_buffers[desc_idx].data; |
bb158d69 MC |
11582 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], |
11583 | mapping); | |
11584 | } else | |
11585 | goto out; | |
c76949a6 | 11586 | |
bb158d69 MC |
11587 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, |
11588 | PCI_DMA_FROMDEVICE); | |
c76949a6 | 11589 | |
9205fd9c | 11590 | rx_data += TG3_RX_OFFSET(tp); |
bb158d69 | 11591 | for (i = data_off; i < rx_len; i++, val++) { |
9205fd9c | 11592 | if (*(rx_data + i) != (u8) (val & 0xff)) |
bb158d69 MC |
11593 | goto out; |
11594 | } | |
c76949a6 | 11595 | } |
bb158d69 | 11596 | |
c76949a6 | 11597 | err = 0; |
6aa20a22 | 11598 | |
9205fd9c | 11599 | /* tg3_free_rings will unmap and free the rx_data */ |
c76949a6 MC |
11600 | out: |
11601 | return err; | |
11602 | } | |
11603 | ||
00c266b7 MC |
11604 | #define TG3_STD_LOOPBACK_FAILED 1 |
11605 | #define TG3_JMB_LOOPBACK_FAILED 2 | |
bb158d69 | 11606 | #define TG3_TSO_LOOPBACK_FAILED 4 |
28a45957 MC |
11607 | #define TG3_LOOPBACK_FAILED \ |
11608 | (TG3_STD_LOOPBACK_FAILED | \ | |
11609 | TG3_JMB_LOOPBACK_FAILED | \ | |
11610 | TG3_TSO_LOOPBACK_FAILED) | |
00c266b7 | 11611 | |
941ec90f | 11612 | static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) |
9f40dead | 11613 | { |
28a45957 | 11614 | int err = -EIO; |
2215e24c | 11615 | u32 eee_cap; |
9f40dead | 11616 | |
ab789046 MC |
11617 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
11618 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
11619 | ||
28a45957 MC |
11620 | if (!netif_running(tp->dev)) { |
11621 | data[0] = TG3_LOOPBACK_FAILED; | |
11622 | data[1] = TG3_LOOPBACK_FAILED; | |
941ec90f MC |
11623 | if (do_extlpbk) |
11624 | data[2] = TG3_LOOPBACK_FAILED; | |
28a45957 MC |
11625 | goto done; |
11626 | } | |
11627 | ||
b9ec6c1b | 11628 | err = tg3_reset_hw(tp, 1); |
ab789046 | 11629 | if (err) { |
28a45957 MC |
11630 | data[0] = TG3_LOOPBACK_FAILED; |
11631 | data[1] = TG3_LOOPBACK_FAILED; | |
941ec90f MC |
11632 | if (do_extlpbk) |
11633 | data[2] = TG3_LOOPBACK_FAILED; | |
ab789046 MC |
11634 | goto done; |
11635 | } | |
9f40dead | 11636 | |
63c3a66f | 11637 | if (tg3_flag(tp, ENABLE_RSS)) { |
4a85f098 MC |
11638 | int i; |
11639 | ||
11640 | /* Reroute all rx packets to the 1st queue */ | |
11641 | for (i = MAC_RSS_INDIR_TBL_0; | |
11642 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
11643 | tw32(i, 0x0); | |
11644 | } | |
11645 | ||
6e01b20b MC |
11646 | /* HW errata - mac loopback fails in some cases on 5780. |
11647 | * Normal traffic and PHY loopback are not affected by | |
11648 | * errata. Also, the MAC loopback test is deprecated for | |
11649 | * all newer ASIC revisions. | |
11650 | */ | |
11651 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
11652 | !tg3_flag(tp, CPMU_PRESENT)) { | |
11653 | tg3_mac_loopback(tp, true); | |
9936bcf6 | 11654 | |
28a45957 MC |
11655 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
11656 | data[0] |= TG3_STD_LOOPBACK_FAILED; | |
6e01b20b MC |
11657 | |
11658 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
28a45957 MC |
11659 | tg3_run_loopback(tp, 9000 + ETH_HLEN, false)) |
11660 | data[0] |= TG3_JMB_LOOPBACK_FAILED; | |
6e01b20b MC |
11661 | |
11662 | tg3_mac_loopback(tp, false); | |
11663 | } | |
4852a861 | 11664 | |
f07e9af3 | 11665 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
63c3a66f | 11666 | !tg3_flag(tp, USE_PHYLIB)) { |
5e5a7f37 MC |
11667 | int i; |
11668 | ||
941ec90f | 11669 | tg3_phy_lpbk_set(tp, 0, false); |
5e5a7f37 MC |
11670 | |
11671 | /* Wait for link */ | |
11672 | for (i = 0; i < 100; i++) { | |
11673 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
11674 | break; | |
11675 | mdelay(1); | |
11676 | } | |
11677 | ||
28a45957 MC |
11678 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
11679 | data[1] |= TG3_STD_LOOPBACK_FAILED; | |
63c3a66f | 11680 | if (tg3_flag(tp, TSO_CAPABLE) && |
28a45957 MC |
11681 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) |
11682 | data[1] |= TG3_TSO_LOOPBACK_FAILED; | |
63c3a66f | 11683 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
28a45957 MC |
11684 | tg3_run_loopback(tp, 9000 + ETH_HLEN, false)) |
11685 | data[1] |= TG3_JMB_LOOPBACK_FAILED; | |
9f40dead | 11686 | |
941ec90f MC |
11687 | if (do_extlpbk) { |
11688 | tg3_phy_lpbk_set(tp, 0, true); | |
11689 | ||
11690 | /* All link indications report up, but the hardware | |
11691 | * isn't really ready for about 20 msec. Double it | |
11692 | * to be sure. | |
11693 | */ | |
11694 | mdelay(40); | |
11695 | ||
11696 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) | |
11697 | data[2] |= TG3_STD_LOOPBACK_FAILED; | |
11698 | if (tg3_flag(tp, TSO_CAPABLE) && | |
11699 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) | |
11700 | data[2] |= TG3_TSO_LOOPBACK_FAILED; | |
11701 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
11702 | tg3_run_loopback(tp, 9000 + ETH_HLEN, false)) | |
11703 | data[2] |= TG3_JMB_LOOPBACK_FAILED; | |
11704 | } | |
11705 | ||
5e5a7f37 MC |
11706 | /* Re-enable gphy autopowerdown. */ |
11707 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) | |
11708 | tg3_phy_toggle_apd(tp, true); | |
11709 | } | |
6833c043 | 11710 | |
941ec90f | 11711 | err = (data[0] | data[1] | data[2]) ? -EIO : 0; |
28a45957 | 11712 | |
ab789046 MC |
11713 | done: |
11714 | tp->phy_flags |= eee_cap; | |
11715 | ||
9f40dead MC |
11716 | return err; |
11717 | } | |
11718 | ||
4cafd3f5 MC |
11719 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
11720 | u64 *data) | |
11721 | { | |
566f86ad | 11722 | struct tg3 *tp = netdev_priv(dev); |
941ec90f | 11723 | bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; |
566f86ad | 11724 | |
bed9829f MC |
11725 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && |
11726 | tg3_power_up(tp)) { | |
11727 | etest->flags |= ETH_TEST_FL_FAILED; | |
11728 | memset(data, 1, sizeof(u64) * TG3_NUM_TEST); | |
11729 | return; | |
11730 | } | |
bc1c7567 | 11731 | |
566f86ad MC |
11732 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
11733 | ||
11734 | if (tg3_test_nvram(tp) != 0) { | |
11735 | etest->flags |= ETH_TEST_FL_FAILED; | |
11736 | data[0] = 1; | |
11737 | } | |
941ec90f | 11738 | if (!doextlpbk && tg3_test_link(tp)) { |
ca43007a MC |
11739 | etest->flags |= ETH_TEST_FL_FAILED; |
11740 | data[1] = 1; | |
11741 | } | |
a71116d1 | 11742 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 11743 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
11744 | |
11745 | if (netif_running(dev)) { | |
b02fd9e3 | 11746 | tg3_phy_stop(tp); |
a71116d1 | 11747 | tg3_netif_stop(tp); |
bbe832c0 MC |
11748 | irq_sync = 1; |
11749 | } | |
a71116d1 | 11750 | |
bbe832c0 | 11751 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
11752 | |
11753 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 11754 | err = tg3_nvram_lock(tp); |
a71116d1 | 11755 | tg3_halt_cpu(tp, RX_CPU_BASE); |
63c3a66f | 11756 | if (!tg3_flag(tp, 5705_PLUS)) |
a71116d1 | 11757 | tg3_halt_cpu(tp, TX_CPU_BASE); |
ec41c7df MC |
11758 | if (!err) |
11759 | tg3_nvram_unlock(tp); | |
a71116d1 | 11760 | |
f07e9af3 | 11761 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
11762 | tg3_phy_reset(tp); |
11763 | ||
a71116d1 MC |
11764 | if (tg3_test_registers(tp) != 0) { |
11765 | etest->flags |= ETH_TEST_FL_FAILED; | |
11766 | data[2] = 1; | |
11767 | } | |
28a45957 | 11768 | |
7942e1db MC |
11769 | if (tg3_test_memory(tp) != 0) { |
11770 | etest->flags |= ETH_TEST_FL_FAILED; | |
11771 | data[3] = 1; | |
11772 | } | |
28a45957 | 11773 | |
941ec90f MC |
11774 | if (doextlpbk) |
11775 | etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; | |
11776 | ||
11777 | if (tg3_test_loopback(tp, &data[4], doextlpbk)) | |
c76949a6 | 11778 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 11779 | |
f47c11ee DM |
11780 | tg3_full_unlock(tp); |
11781 | ||
d4bc3927 MC |
11782 | if (tg3_test_interrupt(tp) != 0) { |
11783 | etest->flags |= ETH_TEST_FL_FAILED; | |
941ec90f | 11784 | data[7] = 1; |
d4bc3927 | 11785 | } |
f47c11ee DM |
11786 | |
11787 | tg3_full_lock(tp, 0); | |
d4bc3927 | 11788 | |
a71116d1 MC |
11789 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
11790 | if (netif_running(dev)) { | |
63c3a66f | 11791 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
11792 | err2 = tg3_restart_hw(tp, 1); |
11793 | if (!err2) | |
b9ec6c1b | 11794 | tg3_netif_start(tp); |
a71116d1 | 11795 | } |
f47c11ee DM |
11796 | |
11797 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
11798 | |
11799 | if (irq_sync && !err2) | |
11800 | tg3_phy_start(tp); | |
a71116d1 | 11801 | } |
80096068 | 11802 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11803 | tg3_power_down(tp); |
bc1c7567 | 11804 | |
4cafd3f5 MC |
11805 | } |
11806 | ||
1da177e4 LT |
11807 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
11808 | { | |
11809 | struct mii_ioctl_data *data = if_mii(ifr); | |
11810 | struct tg3 *tp = netdev_priv(dev); | |
11811 | int err; | |
11812 | ||
63c3a66f | 11813 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 11814 | struct phy_device *phydev; |
f07e9af3 | 11815 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11816 | return -EAGAIN; |
3f0e3ad7 | 11817 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 11818 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
11819 | } |
11820 | ||
33f401ae | 11821 | switch (cmd) { |
1da177e4 | 11822 | case SIOCGMIIPHY: |
882e9793 | 11823 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
11824 | |
11825 | /* fallthru */ | |
11826 | case SIOCGMIIREG: { | |
11827 | u32 mii_regval; | |
11828 | ||
f07e9af3 | 11829 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11830 | break; /* We have no PHY */ |
11831 | ||
34eea5ac | 11832 | if (!netif_running(dev)) |
bc1c7567 MC |
11833 | return -EAGAIN; |
11834 | ||
f47c11ee | 11835 | spin_lock_bh(&tp->lock); |
1da177e4 | 11836 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 11837 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11838 | |
11839 | data->val_out = mii_regval; | |
11840 | ||
11841 | return err; | |
11842 | } | |
11843 | ||
11844 | case SIOCSMIIREG: | |
f07e9af3 | 11845 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11846 | break; /* We have no PHY */ |
11847 | ||
34eea5ac | 11848 | if (!netif_running(dev)) |
bc1c7567 MC |
11849 | return -EAGAIN; |
11850 | ||
f47c11ee | 11851 | spin_lock_bh(&tp->lock); |
1da177e4 | 11852 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 11853 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11854 | |
11855 | return err; | |
11856 | ||
11857 | default: | |
11858 | /* do nothing */ | |
11859 | break; | |
11860 | } | |
11861 | return -EOPNOTSUPP; | |
11862 | } | |
11863 | ||
15f9850d DM |
11864 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11865 | { | |
11866 | struct tg3 *tp = netdev_priv(dev); | |
11867 | ||
11868 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11869 | return 0; | |
11870 | } | |
11871 | ||
d244c892 MC |
11872 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11873 | { | |
11874 | struct tg3 *tp = netdev_priv(dev); | |
11875 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11876 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11877 | ||
63c3a66f | 11878 | if (!tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
11879 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; |
11880 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11881 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11882 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11883 | } | |
11884 | ||
11885 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11886 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11887 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11888 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11889 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11890 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11891 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11892 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11893 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11894 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11895 | return -EINVAL; | |
11896 | ||
11897 | /* No rx interrupts will be generated if both are zero */ | |
11898 | if ((ec->rx_coalesce_usecs == 0) && | |
11899 | (ec->rx_max_coalesced_frames == 0)) | |
11900 | return -EINVAL; | |
11901 | ||
11902 | /* No tx interrupts will be generated if both are zero */ | |
11903 | if ((ec->tx_coalesce_usecs == 0) && | |
11904 | (ec->tx_max_coalesced_frames == 0)) | |
11905 | return -EINVAL; | |
11906 | ||
11907 | /* Only copy relevant parameters, ignore all others. */ | |
11908 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11909 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11910 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11911 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11912 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11913 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11914 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11915 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11916 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11917 | ||
11918 | if (netif_running(dev)) { | |
11919 | tg3_full_lock(tp, 0); | |
11920 | __tg3_set_coalesce(tp, &tp->coal); | |
11921 | tg3_full_unlock(tp); | |
11922 | } | |
11923 | return 0; | |
11924 | } | |
11925 | ||
7282d491 | 11926 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
11927 | .get_settings = tg3_get_settings, |
11928 | .set_settings = tg3_set_settings, | |
11929 | .get_drvinfo = tg3_get_drvinfo, | |
11930 | .get_regs_len = tg3_get_regs_len, | |
11931 | .get_regs = tg3_get_regs, | |
11932 | .get_wol = tg3_get_wol, | |
11933 | .set_wol = tg3_set_wol, | |
11934 | .get_msglevel = tg3_get_msglevel, | |
11935 | .set_msglevel = tg3_set_msglevel, | |
11936 | .nway_reset = tg3_nway_reset, | |
11937 | .get_link = ethtool_op_get_link, | |
11938 | .get_eeprom_len = tg3_get_eeprom_len, | |
11939 | .get_eeprom = tg3_get_eeprom, | |
11940 | .set_eeprom = tg3_set_eeprom, | |
11941 | .get_ringparam = tg3_get_ringparam, | |
11942 | .set_ringparam = tg3_set_ringparam, | |
11943 | .get_pauseparam = tg3_get_pauseparam, | |
11944 | .set_pauseparam = tg3_set_pauseparam, | |
4cafd3f5 | 11945 | .self_test = tg3_self_test, |
1da177e4 | 11946 | .get_strings = tg3_get_strings, |
81b8709c | 11947 | .set_phys_id = tg3_set_phys_id, |
1da177e4 | 11948 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 11949 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 11950 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 11951 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
11952 | }; |
11953 | ||
11954 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11955 | { | |
1b27777a | 11956 | u32 cursize, val, magic; |
1da177e4 LT |
11957 | |
11958 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11959 | ||
e4f34110 | 11960 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
11961 | return; |
11962 | ||
b16250e3 MC |
11963 | if ((magic != TG3_EEPROM_MAGIC) && |
11964 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11965 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
11966 | return; |
11967 | ||
11968 | /* | |
11969 | * Size the chip by reading offsets at increasing powers of two. | |
11970 | * When we encounter our validation signature, we know the addressing | |
11971 | * has wrapped around, and thus have our chip size. | |
11972 | */ | |
1b27777a | 11973 | cursize = 0x10; |
1da177e4 LT |
11974 | |
11975 | while (cursize < tp->nvram_size) { | |
e4f34110 | 11976 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
11977 | return; |
11978 | ||
1820180b | 11979 | if (val == magic) |
1da177e4 LT |
11980 | break; |
11981 | ||
11982 | cursize <<= 1; | |
11983 | } | |
11984 | ||
11985 | tp->nvram_size = cursize; | |
11986 | } | |
6aa20a22 | 11987 | |
1da177e4 LT |
11988 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
11989 | { | |
11990 | u32 val; | |
11991 | ||
63c3a66f | 11992 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) |
1b27777a MC |
11993 | return; |
11994 | ||
11995 | /* Selfboot format */ | |
1820180b | 11996 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
11997 | tg3_get_eeprom_size(tp); |
11998 | return; | |
11999 | } | |
12000 | ||
6d348f2c | 12001 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 12002 | if (val != 0) { |
6d348f2c MC |
12003 | /* This is confusing. We want to operate on the |
12004 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
12005 | * call will read from NVRAM and byteswap the data | |
12006 | * according to the byteswapping settings for all | |
12007 | * other register accesses. This ensures the data we | |
12008 | * want will always reside in the lower 16-bits. | |
12009 | * However, the data in NVRAM is in LE format, which | |
12010 | * means the data from the NVRAM read will always be | |
12011 | * opposite the endianness of the CPU. The 16-bit | |
12012 | * byteswap then brings the data to CPU endianness. | |
12013 | */ | |
12014 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
12015 | return; |
12016 | } | |
12017 | } | |
fd1122a2 | 12018 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
12019 | } |
12020 | ||
12021 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
12022 | { | |
12023 | u32 nvcfg1; | |
12024 | ||
12025 | nvcfg1 = tr32(NVRAM_CFG1); | |
12026 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
63c3a66f | 12027 | tg3_flag_set(tp, FLASH); |
8590a603 | 12028 | } else { |
1da177e4 LT |
12029 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
12030 | tw32(NVRAM_CFG1, nvcfg1); | |
12031 | } | |
12032 | ||
6ff6f81d | 12033 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
63c3a66f | 12034 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 | 12035 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
12036 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
12037 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12038 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 12039 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12040 | break; |
12041 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
12042 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12043 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
12044 | break; | |
12045 | case FLASH_VENDOR_ATMEL_EEPROM: | |
12046 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12047 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
63c3a66f | 12048 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12049 | break; |
12050 | case FLASH_VENDOR_ST: | |
12051 | tp->nvram_jedecnum = JEDEC_ST; | |
12052 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
63c3a66f | 12053 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12054 | break; |
12055 | case FLASH_VENDOR_SAIFUN: | |
12056 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
12057 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
12058 | break; | |
12059 | case FLASH_VENDOR_SST_SMALL: | |
12060 | case FLASH_VENDOR_SST_LARGE: | |
12061 | tp->nvram_jedecnum = JEDEC_SST; | |
12062 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
12063 | break; | |
1da177e4 | 12064 | } |
8590a603 | 12065 | } else { |
1da177e4 LT |
12066 | tp->nvram_jedecnum = JEDEC_ATMEL; |
12067 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 12068 | tg3_flag_set(tp, NVRAM_BUFFERED); |
1da177e4 LT |
12069 | } |
12070 | } | |
12071 | ||
a1b950d5 MC |
12072 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
12073 | { | |
12074 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
12075 | case FLASH_5752PAGE_SIZE_256: | |
12076 | tp->nvram_pagesize = 256; | |
12077 | break; | |
12078 | case FLASH_5752PAGE_SIZE_512: | |
12079 | tp->nvram_pagesize = 512; | |
12080 | break; | |
12081 | case FLASH_5752PAGE_SIZE_1K: | |
12082 | tp->nvram_pagesize = 1024; | |
12083 | break; | |
12084 | case FLASH_5752PAGE_SIZE_2K: | |
12085 | tp->nvram_pagesize = 2048; | |
12086 | break; | |
12087 | case FLASH_5752PAGE_SIZE_4K: | |
12088 | tp->nvram_pagesize = 4096; | |
12089 | break; | |
12090 | case FLASH_5752PAGE_SIZE_264: | |
12091 | tp->nvram_pagesize = 264; | |
12092 | break; | |
12093 | case FLASH_5752PAGE_SIZE_528: | |
12094 | tp->nvram_pagesize = 528; | |
12095 | break; | |
12096 | } | |
12097 | } | |
12098 | ||
361b4ac2 MC |
12099 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
12100 | { | |
12101 | u32 nvcfg1; | |
12102 | ||
12103 | nvcfg1 = tr32(NVRAM_CFG1); | |
12104 | ||
e6af301b MC |
12105 | /* NVRAM protection for TPM */ |
12106 | if (nvcfg1 & (1 << 27)) | |
63c3a66f | 12107 | tg3_flag_set(tp, PROTECTED_NVRAM); |
e6af301b | 12108 | |
361b4ac2 | 12109 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
12110 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
12111 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
12112 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12113 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12114 | break; |
12115 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12116 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12117 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12118 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12119 | break; |
12120 | case FLASH_5752VENDOR_ST_M45PE10: | |
12121 | case FLASH_5752VENDOR_ST_M45PE20: | |
12122 | case FLASH_5752VENDOR_ST_M45PE40: | |
12123 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12124 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12125 | tg3_flag_set(tp, FLASH); | |
8590a603 | 12126 | break; |
361b4ac2 MC |
12127 | } |
12128 | ||
63c3a66f | 12129 | if (tg3_flag(tp, FLASH)) { |
a1b950d5 | 12130 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 12131 | } else { |
361b4ac2 MC |
12132 | /* For eeprom, set pagesize to maximum eeprom size */ |
12133 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12134 | ||
12135 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12136 | tw32(NVRAM_CFG1, nvcfg1); | |
12137 | } | |
12138 | } | |
12139 | ||
d3c7b886 MC |
12140 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
12141 | { | |
989a9d23 | 12142 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
12143 | |
12144 | nvcfg1 = tr32(NVRAM_CFG1); | |
12145 | ||
12146 | /* NVRAM protection for TPM */ | |
989a9d23 | 12147 | if (nvcfg1 & (1 << 27)) { |
63c3a66f | 12148 | tg3_flag_set(tp, PROTECTED_NVRAM); |
989a9d23 MC |
12149 | protect = 1; |
12150 | } | |
d3c7b886 | 12151 | |
989a9d23 MC |
12152 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
12153 | switch (nvcfg1) { | |
8590a603 MC |
12154 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
12155 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
12156 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
12157 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
12158 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12159 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12160 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12161 | tp->nvram_pagesize = 264; |
12162 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
12163 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
12164 | tp->nvram_size = (protect ? 0x3e200 : | |
12165 | TG3_NVRAM_SIZE_512KB); | |
12166 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
12167 | tp->nvram_size = (protect ? 0x1f200 : | |
12168 | TG3_NVRAM_SIZE_256KB); | |
12169 | else | |
12170 | tp->nvram_size = (protect ? 0x1f200 : | |
12171 | TG3_NVRAM_SIZE_128KB); | |
12172 | break; | |
12173 | case FLASH_5752VENDOR_ST_M45PE10: | |
12174 | case FLASH_5752VENDOR_ST_M45PE20: | |
12175 | case FLASH_5752VENDOR_ST_M45PE40: | |
12176 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12177 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12178 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12179 | tp->nvram_pagesize = 256; |
12180 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
12181 | tp->nvram_size = (protect ? | |
12182 | TG3_NVRAM_SIZE_64KB : | |
12183 | TG3_NVRAM_SIZE_128KB); | |
12184 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
12185 | tp->nvram_size = (protect ? | |
12186 | TG3_NVRAM_SIZE_64KB : | |
12187 | TG3_NVRAM_SIZE_256KB); | |
12188 | else | |
12189 | tp->nvram_size = (protect ? | |
12190 | TG3_NVRAM_SIZE_128KB : | |
12191 | TG3_NVRAM_SIZE_512KB); | |
12192 | break; | |
d3c7b886 MC |
12193 | } |
12194 | } | |
12195 | ||
1b27777a MC |
12196 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
12197 | { | |
12198 | u32 nvcfg1; | |
12199 | ||
12200 | nvcfg1 = tr32(NVRAM_CFG1); | |
12201 | ||
12202 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
12203 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
12204 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12205 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
12206 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12207 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12208 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 | 12209 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
1b27777a | 12210 | |
8590a603 MC |
12211 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
12212 | tw32(NVRAM_CFG1, nvcfg1); | |
12213 | break; | |
12214 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12215 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
12216 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
12217 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
12218 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12219 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12220 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12221 | tp->nvram_pagesize = 264; |
12222 | break; | |
12223 | case FLASH_5752VENDOR_ST_M45PE10: | |
12224 | case FLASH_5752VENDOR_ST_M45PE20: | |
12225 | case FLASH_5752VENDOR_ST_M45PE40: | |
12226 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12227 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12228 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12229 | tp->nvram_pagesize = 256; |
12230 | break; | |
1b27777a MC |
12231 | } |
12232 | } | |
12233 | ||
6b91fa02 MC |
12234 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
12235 | { | |
12236 | u32 nvcfg1, protect = 0; | |
12237 | ||
12238 | nvcfg1 = tr32(NVRAM_CFG1); | |
12239 | ||
12240 | /* NVRAM protection for TPM */ | |
12241 | if (nvcfg1 & (1 << 27)) { | |
63c3a66f | 12242 | tg3_flag_set(tp, PROTECTED_NVRAM); |
6b91fa02 MC |
12243 | protect = 1; |
12244 | } | |
12245 | ||
12246 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
12247 | switch (nvcfg1) { | |
8590a603 MC |
12248 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
12249 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12250 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12251 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
12252 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12253 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12254 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12255 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12256 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12257 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12258 | tg3_flag_set(tp, FLASH); | |
12259 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
8590a603 MC |
12260 | tp->nvram_pagesize = 256; |
12261 | break; | |
12262 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12263 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12264 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12265 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12266 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12267 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12268 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12269 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12270 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12271 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12272 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12273 | tp->nvram_pagesize = 256; |
12274 | break; | |
6b91fa02 MC |
12275 | } |
12276 | ||
12277 | if (protect) { | |
12278 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
12279 | } else { | |
12280 | switch (nvcfg1) { | |
8590a603 MC |
12281 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
12282 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
12283 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
12284 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
12285 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
12286 | break; | |
12287 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
12288 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
12289 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
12290 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
12291 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12292 | break; | |
12293 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
12294 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
12295 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
12296 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
12297 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12298 | break; | |
12299 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
12300 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
12301 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
12302 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
12303 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12304 | break; | |
6b91fa02 MC |
12305 | } |
12306 | } | |
12307 | } | |
12308 | ||
b5d3772c MC |
12309 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
12310 | { | |
12311 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12312 | tg3_flag_set(tp, NVRAM_BUFFERED); |
b5d3772c MC |
12313 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12314 | } | |
12315 | ||
321d32a0 MC |
12316 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
12317 | { | |
12318 | u32 nvcfg1; | |
12319 | ||
12320 | nvcfg1 = tr32(NVRAM_CFG1); | |
12321 | ||
12322 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12323 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
12324 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
12325 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12326 | tg3_flag_set(tp, NVRAM_BUFFERED); |
321d32a0 MC |
12327 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12328 | ||
12329 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12330 | tw32(NVRAM_CFG1, nvcfg1); | |
12331 | return; | |
12332 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12333 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12334 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12335 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12336 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12337 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12338 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12339 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12340 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12341 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12342 | |
12343 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12344 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12345 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12346 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12347 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12348 | break; | |
12349 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12350 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12351 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12352 | break; | |
12353 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12354 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12355 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12356 | break; | |
12357 | } | |
12358 | break; | |
12359 | case FLASH_5752VENDOR_ST_M45PE10: | |
12360 | case FLASH_5752VENDOR_ST_M45PE20: | |
12361 | case FLASH_5752VENDOR_ST_M45PE40: | |
12362 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12363 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12364 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
12365 | |
12366 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12367 | case FLASH_5752VENDOR_ST_M45PE10: | |
12368 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12369 | break; | |
12370 | case FLASH_5752VENDOR_ST_M45PE20: | |
12371 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12372 | break; | |
12373 | case FLASH_5752VENDOR_ST_M45PE40: | |
12374 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12375 | break; | |
12376 | } | |
12377 | break; | |
12378 | default: | |
63c3a66f | 12379 | tg3_flag_set(tp, NO_NVRAM); |
321d32a0 MC |
12380 | return; |
12381 | } | |
12382 | ||
a1b950d5 MC |
12383 | tg3_nvram_get_pagesize(tp, nvcfg1); |
12384 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12385 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
a1b950d5 MC |
12386 | } |
12387 | ||
12388 | ||
12389 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
12390 | { | |
12391 | u32 nvcfg1; | |
12392 | ||
12393 | nvcfg1 = tr32(NVRAM_CFG1); | |
12394 | ||
12395 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12396 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
12397 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
12398 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12399 | tg3_flag_set(tp, NVRAM_BUFFERED); |
a1b950d5 MC |
12400 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
12401 | ||
12402 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12403 | tw32(NVRAM_CFG1, nvcfg1); | |
12404 | return; | |
12405 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
12406 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
12407 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
12408 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
12409 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
12410 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12411 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
12412 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12413 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12414 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12415 | |
12416 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12417 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
66ee33bf MC |
12418 | /* Detect size with tg3_nvram_get_size() */ |
12419 | break; | |
a1b950d5 MC |
12420 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
12421 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12422 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12423 | break; | |
12424 | default: | |
12425 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12426 | break; | |
12427 | } | |
321d32a0 | 12428 | break; |
a1b950d5 MC |
12429 | case FLASH_5717VENDOR_ST_M_M25PE10: |
12430 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
12431 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
12432 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
12433 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
12434 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
12435 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
12436 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
12437 | case FLASH_5717VENDOR_ST_25USPT: | |
12438 | case FLASH_5717VENDOR_ST_45USPT: | |
12439 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12440 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12441 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
12442 | |
12443 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12444 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
a1b950d5 | 12445 | case FLASH_5717VENDOR_ST_M_M45PE20: |
66ee33bf MC |
12446 | /* Detect size with tg3_nvram_get_size() */ |
12447 | break; | |
12448 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
a1b950d5 MC |
12449 | case FLASH_5717VENDOR_ST_A_M45PE20: |
12450 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12451 | break; | |
12452 | default: | |
12453 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12454 | break; | |
12455 | } | |
321d32a0 | 12456 | break; |
a1b950d5 | 12457 | default: |
63c3a66f | 12458 | tg3_flag_set(tp, NO_NVRAM); |
a1b950d5 | 12459 | return; |
321d32a0 | 12460 | } |
a1b950d5 MC |
12461 | |
12462 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12463 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12464 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
321d32a0 MC |
12465 | } |
12466 | ||
9b91b5f1 MC |
12467 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
12468 | { | |
12469 | u32 nvcfg1, nvmpinstrp; | |
12470 | ||
12471 | nvcfg1 = tr32(NVRAM_CFG1); | |
12472 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
12473 | ||
12474 | switch (nvmpinstrp) { | |
12475 | case FLASH_5720_EEPROM_HD: | |
12476 | case FLASH_5720_EEPROM_LD: | |
12477 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12478 | tg3_flag_set(tp, NVRAM_BUFFERED); |
9b91b5f1 MC |
12479 | |
12480 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12481 | tw32(NVRAM_CFG1, nvcfg1); | |
12482 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
12483 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12484 | else | |
12485 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
12486 | return; | |
12487 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
12488 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
12489 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
12490 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12491 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12492 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12493 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12494 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12495 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12496 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12497 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12498 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
12499 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12500 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12501 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12502 | |
12503 | switch (nvmpinstrp) { | |
12504 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12505 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12506 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12507 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12508 | break; | |
12509 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12510 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12511 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12512 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12513 | break; | |
12514 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12515 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12516 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12517 | break; | |
12518 | default: | |
12519 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12520 | break; | |
12521 | } | |
12522 | break; | |
12523 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
12524 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
12525 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
12526 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
12527 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12528 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12529 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12530 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12531 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12532 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12533 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12534 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12535 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12536 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12537 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12538 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12539 | case FLASH_5720VENDOR_ST_25USPT: | |
12540 | case FLASH_5720VENDOR_ST_45USPT: | |
12541 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12542 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12543 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
12544 | |
12545 | switch (nvmpinstrp) { | |
12546 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12547 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12548 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12549 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12550 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12551 | break; | |
12552 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12553 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12554 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12555 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12556 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12557 | break; | |
12558 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12559 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12560 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12561 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12562 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12563 | break; | |
12564 | default: | |
12565 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12566 | break; | |
12567 | } | |
12568 | break; | |
12569 | default: | |
63c3a66f | 12570 | tg3_flag_set(tp, NO_NVRAM); |
9b91b5f1 MC |
12571 | return; |
12572 | } | |
12573 | ||
12574 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12575 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 12576 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
9b91b5f1 MC |
12577 | } |
12578 | ||
1da177e4 LT |
12579 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
12580 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
12581 | { | |
1da177e4 LT |
12582 | tw32_f(GRC_EEPROM_ADDR, |
12583 | (EEPROM_ADDR_FSM_RESET | | |
12584 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
12585 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
12586 | ||
9d57f01c | 12587 | msleep(1); |
1da177e4 LT |
12588 | |
12589 | /* Enable seeprom accesses. */ | |
12590 | tw32_f(GRC_LOCAL_CTRL, | |
12591 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
12592 | udelay(100); | |
12593 | ||
12594 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12595 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
63c3a66f | 12596 | tg3_flag_set(tp, NVRAM); |
1da177e4 | 12597 | |
ec41c7df | 12598 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
12599 | netdev_warn(tp->dev, |
12600 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 12601 | __func__); |
ec41c7df MC |
12602 | return; |
12603 | } | |
e6af301b | 12604 | tg3_enable_nvram_access(tp); |
1da177e4 | 12605 | |
989a9d23 MC |
12606 | tp->nvram_size = 0; |
12607 | ||
361b4ac2 MC |
12608 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
12609 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
12610 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
12611 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 12612 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
12613 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
12614 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 12615 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
12616 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
12617 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
12618 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12619 | tg3_get_5906_nvram_info(tp); | |
b703df6f | 12620 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
55086ad9 | 12621 | tg3_flag(tp, 57765_CLASS)) |
321d32a0 | 12622 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
12623 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
12624 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 12625 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
12626 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
12627 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
12628 | else |
12629 | tg3_get_nvram_info(tp); | |
12630 | ||
989a9d23 MC |
12631 | if (tp->nvram_size == 0) |
12632 | tg3_get_nvram_size(tp); | |
1da177e4 | 12633 | |
e6af301b | 12634 | tg3_disable_nvram_access(tp); |
381291b7 | 12635 | tg3_nvram_unlock(tp); |
1da177e4 LT |
12636 | |
12637 | } else { | |
63c3a66f JP |
12638 | tg3_flag_clear(tp, NVRAM); |
12639 | tg3_flag_clear(tp, NVRAM_BUFFERED); | |
1da177e4 LT |
12640 | |
12641 | tg3_get_eeprom_size(tp); | |
12642 | } | |
12643 | } | |
12644 | ||
1da177e4 LT |
12645 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
12646 | u32 offset, u32 len, u8 *buf) | |
12647 | { | |
12648 | int i, j, rc = 0; | |
12649 | u32 val; | |
12650 | ||
12651 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 12652 | u32 addr; |
a9dc529d | 12653 | __be32 data; |
1da177e4 LT |
12654 | |
12655 | addr = offset + i; | |
12656 | ||
12657 | memcpy(&data, buf + i, 4); | |
12658 | ||
62cedd11 MC |
12659 | /* |
12660 | * The SEEPROM interface expects the data to always be opposite | |
12661 | * the native endian format. We accomplish this by reversing | |
12662 | * all the operations that would have been performed on the | |
12663 | * data from a call to tg3_nvram_read_be32(). | |
12664 | */ | |
12665 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
12666 | |
12667 | val = tr32(GRC_EEPROM_ADDR); | |
12668 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
12669 | ||
12670 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
12671 | EEPROM_ADDR_READ); | |
12672 | tw32(GRC_EEPROM_ADDR, val | | |
12673 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
12674 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
12675 | EEPROM_ADDR_START | | |
12676 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 12677 | |
9d57f01c | 12678 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
12679 | val = tr32(GRC_EEPROM_ADDR); |
12680 | ||
12681 | if (val & EEPROM_ADDR_COMPLETE) | |
12682 | break; | |
9d57f01c | 12683 | msleep(1); |
1da177e4 LT |
12684 | } |
12685 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
12686 | rc = -EBUSY; | |
12687 | break; | |
12688 | } | |
12689 | } | |
12690 | ||
12691 | return rc; | |
12692 | } | |
12693 | ||
12694 | /* offset and length are dword aligned */ | |
12695 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
12696 | u8 *buf) | |
12697 | { | |
12698 | int ret = 0; | |
12699 | u32 pagesize = tp->nvram_pagesize; | |
12700 | u32 pagemask = pagesize - 1; | |
12701 | u32 nvram_cmd; | |
12702 | u8 *tmp; | |
12703 | ||
12704 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
12705 | if (tmp == NULL) | |
12706 | return -ENOMEM; | |
12707 | ||
12708 | while (len) { | |
12709 | int j; | |
e6af301b | 12710 | u32 phy_addr, page_off, size; |
1da177e4 LT |
12711 | |
12712 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 12713 | |
1da177e4 | 12714 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
12715 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
12716 | (__be32 *) (tmp + j)); | |
12717 | if (ret) | |
1da177e4 LT |
12718 | break; |
12719 | } | |
12720 | if (ret) | |
12721 | break; | |
12722 | ||
c6cdf436 | 12723 | page_off = offset & pagemask; |
1da177e4 LT |
12724 | size = pagesize; |
12725 | if (len < size) | |
12726 | size = len; | |
12727 | ||
12728 | len -= size; | |
12729 | ||
12730 | memcpy(tmp + page_off, buf, size); | |
12731 | ||
12732 | offset = offset + (pagesize - page_off); | |
12733 | ||
e6af301b | 12734 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
12735 | |
12736 | /* | |
12737 | * Before we can erase the flash page, we need | |
12738 | * to issue a special "write enable" command. | |
12739 | */ | |
12740 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12741 | ||
12742 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12743 | break; | |
12744 | ||
12745 | /* Erase the target page */ | |
12746 | tw32(NVRAM_ADDR, phy_addr); | |
12747 | ||
12748 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
12749 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
12750 | ||
c6cdf436 | 12751 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
1da177e4 LT |
12752 | break; |
12753 | ||
12754 | /* Issue another write enable to start the write. */ | |
12755 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12756 | ||
12757 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12758 | break; | |
12759 | ||
12760 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 12761 | __be32 data; |
1da177e4 | 12762 | |
b9fc7dc5 | 12763 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 12764 | |
b9fc7dc5 | 12765 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
12766 | |
12767 | tw32(NVRAM_ADDR, phy_addr + j); | |
12768 | ||
12769 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
12770 | NVRAM_CMD_WR; | |
12771 | ||
12772 | if (j == 0) | |
12773 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12774 | else if (j == (pagesize - 4)) | |
12775 | nvram_cmd |= NVRAM_CMD_LAST; | |
12776 | ||
12777 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12778 | break; | |
12779 | } | |
12780 | if (ret) | |
12781 | break; | |
12782 | } | |
12783 | ||
12784 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12785 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
12786 | ||
12787 | kfree(tmp); | |
12788 | ||
12789 | return ret; | |
12790 | } | |
12791 | ||
12792 | /* offset and length are dword aligned */ | |
12793 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
12794 | u8 *buf) | |
12795 | { | |
12796 | int i, ret = 0; | |
12797 | ||
12798 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
12799 | u32 page_off, phy_addr, nvram_cmd; |
12800 | __be32 data; | |
1da177e4 LT |
12801 | |
12802 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 12803 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 | 12804 | |
c6cdf436 | 12805 | page_off = offset % tp->nvram_pagesize; |
1da177e4 | 12806 | |
1820180b | 12807 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
12808 | |
12809 | tw32(NVRAM_ADDR, phy_addr); | |
12810 | ||
12811 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12812 | ||
c6cdf436 | 12813 | if (page_off == 0 || i == 0) |
1da177e4 | 12814 | nvram_cmd |= NVRAM_CMD_FIRST; |
f6d9a256 | 12815 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
12816 | nvram_cmd |= NVRAM_CMD_LAST; |
12817 | ||
12818 | if (i == (len - 4)) | |
12819 | nvram_cmd |= NVRAM_CMD_LAST; | |
12820 | ||
321d32a0 | 12821 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
63c3a66f | 12822 | !tg3_flag(tp, 5755_PLUS) && |
4c987487 MC |
12823 | (tp->nvram_jedecnum == JEDEC_ST) && |
12824 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
12825 | |
12826 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12827 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12828 | NVRAM_CMD_DONE))) | |
12829 | ||
12830 | break; | |
12831 | } | |
63c3a66f | 12832 | if (!tg3_flag(tp, FLASH)) { |
1da177e4 LT |
12833 | /* We always do complete word writes to eeprom. */ |
12834 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12835 | } | |
12836 | ||
12837 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12838 | break; | |
12839 | } | |
12840 | return ret; | |
12841 | } | |
12842 | ||
12843 | /* offset and length are dword aligned */ | |
12844 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12845 | { | |
12846 | int ret; | |
12847 | ||
63c3a66f | 12848 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
314fba34 MC |
12849 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
12850 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
12851 | udelay(40); |
12852 | } | |
12853 | ||
63c3a66f | 12854 | if (!tg3_flag(tp, NVRAM)) { |
1da177e4 | 12855 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); |
859a5887 | 12856 | } else { |
1da177e4 LT |
12857 | u32 grc_mode; |
12858 | ||
ec41c7df MC |
12859 | ret = tg3_nvram_lock(tp); |
12860 | if (ret) | |
12861 | return ret; | |
1da177e4 | 12862 | |
e6af301b | 12863 | tg3_enable_nvram_access(tp); |
63c3a66f | 12864 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) |
1da177e4 | 12865 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
12866 | |
12867 | grc_mode = tr32(GRC_MODE); | |
12868 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12869 | ||
63c3a66f | 12870 | if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { |
1da177e4 LT |
12871 | ret = tg3_nvram_write_block_buffered(tp, offset, len, |
12872 | buf); | |
859a5887 | 12873 | } else { |
1da177e4 LT |
12874 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
12875 | buf); | |
12876 | } | |
12877 | ||
12878 | grc_mode = tr32(GRC_MODE); | |
12879 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12880 | ||
e6af301b | 12881 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
12882 | tg3_nvram_unlock(tp); |
12883 | } | |
12884 | ||
63c3a66f | 12885 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
314fba34 | 12886 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
12887 | udelay(40); |
12888 | } | |
12889 | ||
12890 | return ret; | |
12891 | } | |
12892 | ||
12893 | struct subsys_tbl_ent { | |
12894 | u16 subsys_vendor, subsys_devid; | |
12895 | u32 phy_id; | |
12896 | }; | |
12897 | ||
24daf2b0 | 12898 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 12899 | /* Broadcom boards. */ |
24daf2b0 | 12900 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12901 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12902 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12903 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12904 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12905 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
12906 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12907 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
12908 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12909 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12910 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12911 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12912 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12913 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
12914 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12915 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12916 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12917 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12918 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12919 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 12920 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12921 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
12922 | |
12923 | /* 3com boards. */ | |
24daf2b0 | 12924 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12925 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12926 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12927 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12928 | { TG3PCI_SUBVENDOR_ID_3COM, |
12929 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
12930 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 12931 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12932 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12933 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12934 | |
12935 | /* DELL boards. */ | |
24daf2b0 | 12936 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12937 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12938 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12939 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12940 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12941 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 12942 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12943 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
12944 | |
12945 | /* Compaq boards. */ | |
24daf2b0 | 12946 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12947 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12948 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12949 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12950 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
12951 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
12952 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 12953 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12954 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12955 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12956 | |
12957 | /* IBM boards. */ | |
24daf2b0 MC |
12958 | { TG3PCI_SUBVENDOR_ID_IBM, |
12959 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
12960 | }; |
12961 | ||
24daf2b0 | 12962 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
12963 | { |
12964 | int i; | |
12965 | ||
12966 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12967 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12968 | tp->pdev->subsystem_vendor) && | |
12969 | (subsys_id_to_phy_id[i].subsys_devid == | |
12970 | tp->pdev->subsystem_device)) | |
12971 | return &subsys_id_to_phy_id[i]; | |
12972 | } | |
12973 | return NULL; | |
12974 | } | |
12975 | ||
7d0c41ef | 12976 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 12977 | { |
1da177e4 | 12978 | u32 val; |
f49639e6 | 12979 | |
79eb6904 | 12980 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
12981 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
12982 | ||
a85feb8c | 12983 | /* Assume an onboard device and WOL capable by default. */ |
63c3a66f JP |
12984 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
12985 | tg3_flag_set(tp, WOL_CAP); | |
72b845e0 | 12986 | |
b5d3772c | 12987 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 12988 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
63c3a66f JP |
12989 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
12990 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 12991 | } |
0527ba35 MC |
12992 | val = tr32(VCPU_CFGSHDW); |
12993 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
63c3a66f | 12994 | tg3_flag_set(tp, ASPM_WORKAROUND); |
0527ba35 | 12995 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
6fdbab9d | 12996 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) { |
63c3a66f | 12997 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
12998 | device_set_wakeup_enable(&tp->pdev->dev, true); |
12999 | } | |
05ac4cb7 | 13000 | goto done; |
b5d3772c MC |
13001 | } |
13002 | ||
1da177e4 LT |
13003 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
13004 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
13005 | u32 nic_cfg, led_cfg; | |
a9daf367 | 13006 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 13007 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
13008 | |
13009 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
13010 | tp->nic_sram_data_cfg = nic_cfg; | |
13011 | ||
13012 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
13013 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
6ff6f81d MC |
13014 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
13015 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13016 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && | |
1da177e4 LT |
13017 | (ver > 0) && (ver < 0x100)) |
13018 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
13019 | ||
a9daf367 MC |
13020 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
13021 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
13022 | ||
1da177e4 LT |
13023 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
13024 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
13025 | eeprom_phy_serdes = 1; | |
13026 | ||
13027 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
13028 | if (nic_phy_id != 0) { | |
13029 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
13030 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
13031 | ||
13032 | eeprom_phy_id = (id1 >> 16) << 10; | |
13033 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
13034 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
13035 | } else | |
13036 | eeprom_phy_id = 0; | |
13037 | ||
7d0c41ef | 13038 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 13039 | if (eeprom_phy_serdes) { |
63c3a66f | 13040 | if (!tg3_flag(tp, 5705_PLUS)) |
f07e9af3 | 13041 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 13042 | else |
f07e9af3 | 13043 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 13044 | } |
7d0c41ef | 13045 | |
63c3a66f | 13046 | if (tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
13047 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
13048 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 13049 | else |
1da177e4 LT |
13050 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
13051 | ||
13052 | switch (led_cfg) { | |
13053 | default: | |
13054 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
13055 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
13056 | break; | |
13057 | ||
13058 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
13059 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
13060 | break; | |
13061 | ||
13062 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
13063 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
13064 | |
13065 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
13066 | * read on some older 5700/5701 bootcode. | |
13067 | */ | |
13068 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13069 | ASIC_REV_5700 || | |
13070 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13071 | ASIC_REV_5701) | |
13072 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
13073 | ||
1da177e4 LT |
13074 | break; |
13075 | ||
13076 | case SHASTA_EXT_LED_SHARED: | |
13077 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
13078 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
13079 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
13080 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
13081 | LED_CTRL_MODE_PHY_2); | |
13082 | break; | |
13083 | ||
13084 | case SHASTA_EXT_LED_MAC: | |
13085 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
13086 | break; | |
13087 | ||
13088 | case SHASTA_EXT_LED_COMBO: | |
13089 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
13090 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
13091 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
13092 | LED_CTRL_MODE_PHY_2); | |
13093 | break; | |
13094 | ||
855e1111 | 13095 | } |
1da177e4 LT |
13096 | |
13097 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13098 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
13099 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
13100 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
13101 | ||
b2a5c19c MC |
13102 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
13103 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 13104 | |
9d26e213 | 13105 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
63c3a66f | 13106 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
9d26e213 MC |
13107 | if ((tp->pdev->subsystem_vendor == |
13108 | PCI_VENDOR_ID_ARIMA) && | |
13109 | (tp->pdev->subsystem_device == 0x205a || | |
13110 | tp->pdev->subsystem_device == 0x2063)) | |
63c3a66f | 13111 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
9d26e213 | 13112 | } else { |
63c3a66f JP |
13113 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
13114 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 13115 | } |
1da177e4 LT |
13116 | |
13117 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f JP |
13118 | tg3_flag_set(tp, ENABLE_ASF); |
13119 | if (tg3_flag(tp, 5750_PLUS)) | |
13120 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 | 13121 | } |
b2b98d4a MC |
13122 | |
13123 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
63c3a66f JP |
13124 | tg3_flag(tp, 5750_PLUS)) |
13125 | tg3_flag_set(tp, ENABLE_APE); | |
b2b98d4a | 13126 | |
f07e9af3 | 13127 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c | 13128 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
63c3a66f | 13129 | tg3_flag_clear(tp, WOL_CAP); |
1da177e4 | 13130 | |
63c3a66f | 13131 | if (tg3_flag(tp, WOL_CAP) && |
6fdbab9d | 13132 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) { |
63c3a66f | 13133 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
13134 | device_set_wakeup_enable(&tp->pdev->dev, true); |
13135 | } | |
0527ba35 | 13136 | |
1da177e4 | 13137 | if (cfg2 & (1 << 17)) |
f07e9af3 | 13138 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
13139 | |
13140 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
13141 | /* bootcode if bit 18 is set */ | |
13142 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 13143 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 13144 | |
63c3a66f JP |
13145 | if ((tg3_flag(tp, 57765_PLUS) || |
13146 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
13147 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 | 13148 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 13149 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 13150 | |
63c3a66f | 13151 | if (tg3_flag(tp, PCI_EXPRESS) && |
8c69b1e7 | 13152 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
63c3a66f | 13153 | !tg3_flag(tp, 57765_PLUS)) { |
8ed5d97e MC |
13154 | u32 cfg3; |
13155 | ||
13156 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
13157 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
63c3a66f | 13158 | tg3_flag_set(tp, ASPM_WORKAROUND); |
8ed5d97e | 13159 | } |
a9daf367 | 13160 | |
14417063 | 13161 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
63c3a66f | 13162 | tg3_flag_set(tp, RGMII_INBAND_DISABLE); |
a9daf367 | 13163 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
63c3a66f | 13164 | tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); |
a9daf367 | 13165 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) |
63c3a66f | 13166 | tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); |
1da177e4 | 13167 | } |
05ac4cb7 | 13168 | done: |
63c3a66f | 13169 | if (tg3_flag(tp, WOL_CAP)) |
43067ed8 | 13170 | device_set_wakeup_enable(&tp->pdev->dev, |
63c3a66f | 13171 | tg3_flag(tp, WOL_ENABLE)); |
43067ed8 RW |
13172 | else |
13173 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
13174 | } |
13175 | ||
b2a5c19c MC |
13176 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
13177 | { | |
13178 | int i; | |
13179 | u32 val; | |
13180 | ||
13181 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
13182 | tw32(OTP_CTRL, cmd); | |
13183 | ||
13184 | /* Wait for up to 1 ms for command to execute. */ | |
13185 | for (i = 0; i < 100; i++) { | |
13186 | val = tr32(OTP_STATUS); | |
13187 | if (val & OTP_STATUS_CMD_DONE) | |
13188 | break; | |
13189 | udelay(10); | |
13190 | } | |
13191 | ||
13192 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
13193 | } | |
13194 | ||
13195 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
13196 | * configuration is a 32-bit value that straddles the alignment boundary. | |
13197 | * We do two 32-bit reads and then shift and merge the results. | |
13198 | */ | |
13199 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
13200 | { | |
13201 | u32 bhalf_otp, thalf_otp; | |
13202 | ||
13203 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
13204 | ||
13205 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
13206 | return 0; | |
13207 | ||
13208 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
13209 | ||
13210 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13211 | return 0; | |
13212 | ||
13213 | thalf_otp = tr32(OTP_READ_DATA); | |
13214 | ||
13215 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
13216 | ||
13217 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13218 | return 0; | |
13219 | ||
13220 | bhalf_otp = tr32(OTP_READ_DATA); | |
13221 | ||
13222 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
13223 | } | |
13224 | ||
e256f8a3 MC |
13225 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
13226 | { | |
202ff1c2 | 13227 | u32 adv = ADVERTISED_Autoneg; |
e256f8a3 MC |
13228 | |
13229 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
13230 | adv |= ADVERTISED_1000baseT_Half | | |
13231 | ADVERTISED_1000baseT_Full; | |
13232 | ||
13233 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
13234 | adv |= ADVERTISED_100baseT_Half | | |
13235 | ADVERTISED_100baseT_Full | | |
13236 | ADVERTISED_10baseT_Half | | |
13237 | ADVERTISED_10baseT_Full | | |
13238 | ADVERTISED_TP; | |
13239 | else | |
13240 | adv |= ADVERTISED_FIBRE; | |
13241 | ||
13242 | tp->link_config.advertising = adv; | |
13243 | tp->link_config.speed = SPEED_INVALID; | |
13244 | tp->link_config.duplex = DUPLEX_INVALID; | |
13245 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
13246 | tp->link_config.active_speed = SPEED_INVALID; | |
13247 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
13248 | tp->link_config.orig_speed = SPEED_INVALID; | |
13249 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
13250 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
13251 | } | |
13252 | ||
7d0c41ef MC |
13253 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
13254 | { | |
13255 | u32 hw_phy_id_1, hw_phy_id_2; | |
13256 | u32 hw_phy_id, hw_phy_id_masked; | |
13257 | int err; | |
1da177e4 | 13258 | |
e256f8a3 | 13259 | /* flow control autonegotiation is default behavior */ |
63c3a66f | 13260 | tg3_flag_set(tp, PAUSE_AUTONEG); |
e256f8a3 MC |
13261 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
13262 | ||
63c3a66f | 13263 | if (tg3_flag(tp, USE_PHYLIB)) |
b02fd9e3 MC |
13264 | return tg3_phy_init(tp); |
13265 | ||
1da177e4 | 13266 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 13267 | * firmware access to the PHY hardware. |
1da177e4 LT |
13268 | */ |
13269 | err = 0; | |
63c3a66f | 13270 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { |
79eb6904 | 13271 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
13272 | } else { |
13273 | /* Now read the physical PHY_ID from the chip and verify | |
13274 | * that it is sane. If it doesn't look good, we fall back | |
13275 | * to either the hard-coded table based PHY_ID and failing | |
13276 | * that the value found in the eeprom area. | |
13277 | */ | |
13278 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
13279 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
13280 | ||
13281 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
13282 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
13283 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
13284 | ||
79eb6904 | 13285 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
13286 | } |
13287 | ||
79eb6904 | 13288 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 13289 | tp->phy_id = hw_phy_id; |
79eb6904 | 13290 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13291 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 13292 | else |
f07e9af3 | 13293 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 13294 | } else { |
79eb6904 | 13295 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
13296 | /* Do nothing, phy ID already set up in |
13297 | * tg3_get_eeprom_hw_cfg(). | |
13298 | */ | |
1da177e4 LT |
13299 | } else { |
13300 | struct subsys_tbl_ent *p; | |
13301 | ||
13302 | /* No eeprom signature? Try the hardcoded | |
13303 | * subsys device table. | |
13304 | */ | |
24daf2b0 | 13305 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
13306 | if (!p) |
13307 | return -ENODEV; | |
13308 | ||
13309 | tp->phy_id = p->phy_id; | |
13310 | if (!tp->phy_id || | |
79eb6904 | 13311 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13312 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
13313 | } |
13314 | } | |
13315 | ||
a6b68dab | 13316 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
5baa5e9a MC |
13317 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13318 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | |
13319 | (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
a6b68dab MC |
13320 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || |
13321 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
13322 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
13323 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
13324 | ||
e256f8a3 MC |
13325 | tg3_phy_init_link_config(tp); |
13326 | ||
f07e9af3 | 13327 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
63c3a66f JP |
13328 | !tg3_flag(tp, ENABLE_APE) && |
13329 | !tg3_flag(tp, ENABLE_ASF)) { | |
e2bf73e7 | 13330 | u32 bmsr, dummy; |
1da177e4 LT |
13331 | |
13332 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
13333 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
13334 | (bmsr & BMSR_LSTATUS)) | |
13335 | goto skip_phy_reset; | |
6aa20a22 | 13336 | |
1da177e4 LT |
13337 | err = tg3_phy_reset(tp); |
13338 | if (err) | |
13339 | return err; | |
13340 | ||
42b64a45 | 13341 | tg3_phy_set_wirespeed(tp); |
1da177e4 | 13342 | |
e2bf73e7 | 13343 | if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { |
42b64a45 MC |
13344 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, |
13345 | tp->link_config.flowctrl); | |
1da177e4 LT |
13346 | |
13347 | tg3_writephy(tp, MII_BMCR, | |
13348 | BMCR_ANENABLE | BMCR_ANRESTART); | |
13349 | } | |
1da177e4 LT |
13350 | } |
13351 | ||
13352 | skip_phy_reset: | |
79eb6904 | 13353 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
13354 | err = tg3_init_5401phy_dsp(tp); |
13355 | if (err) | |
13356 | return err; | |
1da177e4 | 13357 | |
1da177e4 LT |
13358 | err = tg3_init_5401phy_dsp(tp); |
13359 | } | |
13360 | ||
1da177e4 LT |
13361 | return err; |
13362 | } | |
13363 | ||
184b8904 | 13364 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 13365 | { |
a4a8bb15 | 13366 | u8 *vpd_data; |
4181b2c8 | 13367 | unsigned int block_end, rosize, len; |
535a490e | 13368 | u32 vpdlen; |
184b8904 | 13369 | int j, i = 0; |
a4a8bb15 | 13370 | |
535a490e | 13371 | vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); |
a4a8bb15 MC |
13372 | if (!vpd_data) |
13373 | goto out_no_vpd; | |
1da177e4 | 13374 | |
535a490e | 13375 | i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA); |
4181b2c8 MC |
13376 | if (i < 0) |
13377 | goto out_not_found; | |
1da177e4 | 13378 | |
4181b2c8 MC |
13379 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
13380 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
13381 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 13382 | |
535a490e | 13383 | if (block_end > vpdlen) |
4181b2c8 | 13384 | goto out_not_found; |
af2c6a4a | 13385 | |
184b8904 MC |
13386 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13387 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
13388 | if (j > 0) { | |
13389 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13390 | ||
13391 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13392 | if (j + len > block_end || len != 4 || | |
13393 | memcmp(&vpd_data[j], "1028", 4)) | |
13394 | goto partno; | |
13395 | ||
13396 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13397 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
13398 | if (j < 0) | |
13399 | goto partno; | |
13400 | ||
13401 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13402 | ||
13403 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13404 | if (j + len > block_end) | |
13405 | goto partno; | |
13406 | ||
13407 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
535a490e | 13408 | strncat(tp->fw_ver, " bc ", vpdlen - len - 1); |
184b8904 MC |
13409 | } |
13410 | ||
13411 | partno: | |
4181b2c8 MC |
13412 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13413 | PCI_VPD_RO_KEYWORD_PARTNO); | |
13414 | if (i < 0) | |
13415 | goto out_not_found; | |
af2c6a4a | 13416 | |
4181b2c8 | 13417 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 13418 | |
4181b2c8 MC |
13419 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
13420 | if (len > TG3_BPN_SIZE || | |
535a490e | 13421 | (len + i) > vpdlen) |
4181b2c8 | 13422 | goto out_not_found; |
1da177e4 | 13423 | |
4181b2c8 | 13424 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 13425 | |
1da177e4 | 13426 | out_not_found: |
a4a8bb15 | 13427 | kfree(vpd_data); |
37a949c5 | 13428 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
13429 | return; |
13430 | ||
13431 | out_no_vpd: | |
37a949c5 MC |
13432 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
13433 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
13434 | strcpy(tp->board_part_number, "BCM5717"); | |
13435 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
13436 | strcpy(tp->board_part_number, "BCM5718"); | |
13437 | else | |
13438 | goto nomatch; | |
13439 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
13440 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
13441 | strcpy(tp->board_part_number, "BCM57780"); | |
13442 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
13443 | strcpy(tp->board_part_number, "BCM57760"); | |
13444 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
13445 | strcpy(tp->board_part_number, "BCM57790"); | |
13446 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
13447 | strcpy(tp->board_part_number, "BCM57788"); | |
13448 | else | |
13449 | goto nomatch; | |
13450 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13451 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
13452 | strcpy(tp->board_part_number, "BCM57761"); | |
13453 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
13454 | strcpy(tp->board_part_number, "BCM57765"); | |
13455 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
13456 | strcpy(tp->board_part_number, "BCM57781"); | |
13457 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
13458 | strcpy(tp->board_part_number, "BCM57785"); | |
13459 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
13460 | strcpy(tp->board_part_number, "BCM57791"); | |
13461 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13462 | strcpy(tp->board_part_number, "BCM57795"); | |
13463 | else | |
13464 | goto nomatch; | |
55086ad9 MC |
13465 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) { |
13466 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) | |
13467 | strcpy(tp->board_part_number, "BCM57762"); | |
13468 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) | |
13469 | strcpy(tp->board_part_number, "BCM57766"); | |
13470 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) | |
13471 | strcpy(tp->board_part_number, "BCM57782"); | |
13472 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) | |
13473 | strcpy(tp->board_part_number, "BCM57786"); | |
13474 | else | |
13475 | goto nomatch; | |
37a949c5 | 13476 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
b5d3772c | 13477 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
13478 | } else { |
13479 | nomatch: | |
b5d3772c | 13480 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 13481 | } |
1da177e4 LT |
13482 | } |
13483 | ||
9c8a620e MC |
13484 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
13485 | { | |
13486 | u32 val; | |
13487 | ||
e4f34110 | 13488 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 13489 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 13490 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
13491 | val != 0) |
13492 | return 0; | |
13493 | ||
13494 | return 1; | |
13495 | } | |
13496 | ||
acd9c119 MC |
13497 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
13498 | { | |
ff3a7cb2 | 13499 | u32 val, offset, start, ver_offset; |
75f9936e | 13500 | int i, dst_off; |
ff3a7cb2 | 13501 | bool newver = false; |
acd9c119 MC |
13502 | |
13503 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
13504 | tg3_nvram_read(tp, 0x4, &start)) | |
13505 | return; | |
13506 | ||
13507 | offset = tg3_nvram_logical_addr(tp, offset); | |
13508 | ||
ff3a7cb2 | 13509 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
13510 | return; |
13511 | ||
ff3a7cb2 MC |
13512 | if ((val & 0xfc000000) == 0x0c000000) { |
13513 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
13514 | return; |
13515 | ||
ff3a7cb2 MC |
13516 | if (val == 0) |
13517 | newver = true; | |
13518 | } | |
13519 | ||
75f9936e MC |
13520 | dst_off = strlen(tp->fw_ver); |
13521 | ||
ff3a7cb2 | 13522 | if (newver) { |
75f9936e MC |
13523 | if (TG3_VER_SIZE - dst_off < 16 || |
13524 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
13525 | return; |
13526 | ||
13527 | offset = offset + ver_offset - start; | |
13528 | for (i = 0; i < 16; i += 4) { | |
13529 | __be32 v; | |
13530 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
13531 | return; | |
13532 | ||
75f9936e | 13533 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
13534 | } |
13535 | } else { | |
13536 | u32 major, minor; | |
13537 | ||
13538 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
13539 | return; | |
13540 | ||
13541 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
13542 | TG3_NVM_BCVER_MAJSFT; | |
13543 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
13544 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
13545 | "v%d.%02d", major, minor); | |
acd9c119 MC |
13546 | } |
13547 | } | |
13548 | ||
a6f6cb1c MC |
13549 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
13550 | { | |
13551 | u32 val, major, minor; | |
13552 | ||
13553 | /* Use native endian representation */ | |
13554 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
13555 | return; | |
13556 | ||
13557 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
13558 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
13559 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
13560 | TG3_NVM_HWSB_CFG1_MINSFT; | |
13561 | ||
13562 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
13563 | } | |
13564 | ||
dfe00d7d MC |
13565 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
13566 | { | |
13567 | u32 offset, major, minor, build; | |
13568 | ||
75f9936e | 13569 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
13570 | |
13571 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
13572 | return; | |
13573 | ||
13574 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
13575 | case TG3_EEPROM_SB_REVISION_0: | |
13576 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
13577 | break; | |
13578 | case TG3_EEPROM_SB_REVISION_2: | |
13579 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
13580 | break; | |
13581 | case TG3_EEPROM_SB_REVISION_3: | |
13582 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
13583 | break; | |
a4153d40 MC |
13584 | case TG3_EEPROM_SB_REVISION_4: |
13585 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
13586 | break; | |
13587 | case TG3_EEPROM_SB_REVISION_5: | |
13588 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
13589 | break; | |
bba226ac MC |
13590 | case TG3_EEPROM_SB_REVISION_6: |
13591 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
13592 | break; | |
dfe00d7d MC |
13593 | default: |
13594 | return; | |
13595 | } | |
13596 | ||
e4f34110 | 13597 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
13598 | return; |
13599 | ||
13600 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
13601 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
13602 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
13603 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
13604 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
13605 | ||
13606 | if (minor > 99 || build > 26) | |
13607 | return; | |
13608 | ||
75f9936e MC |
13609 | offset = strlen(tp->fw_ver); |
13610 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
13611 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
13612 | |
13613 | if (build > 0) { | |
75f9936e MC |
13614 | offset = strlen(tp->fw_ver); |
13615 | if (offset < TG3_VER_SIZE - 1) | |
13616 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
13617 | } |
13618 | } | |
13619 | ||
acd9c119 | 13620 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
13621 | { |
13622 | u32 val, offset, start; | |
acd9c119 | 13623 | int i, vlen; |
9c8a620e MC |
13624 | |
13625 | for (offset = TG3_NVM_DIR_START; | |
13626 | offset < TG3_NVM_DIR_END; | |
13627 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 13628 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
13629 | return; |
13630 | ||
9c8a620e MC |
13631 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
13632 | break; | |
13633 | } | |
13634 | ||
13635 | if (offset == TG3_NVM_DIR_END) | |
13636 | return; | |
13637 | ||
63c3a66f | 13638 | if (!tg3_flag(tp, 5705_PLUS)) |
9c8a620e | 13639 | start = 0x08000000; |
e4f34110 | 13640 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
13641 | return; |
13642 | ||
e4f34110 | 13643 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 13644 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 13645 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
13646 | return; |
13647 | ||
13648 | offset += val - start; | |
13649 | ||
acd9c119 | 13650 | vlen = strlen(tp->fw_ver); |
9c8a620e | 13651 | |
acd9c119 MC |
13652 | tp->fw_ver[vlen++] = ','; |
13653 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
13654 | |
13655 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
13656 | __be32 v; |
13657 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
13658 | return; |
13659 | ||
b9fc7dc5 | 13660 | offset += sizeof(v); |
c4e6575c | 13661 | |
acd9c119 MC |
13662 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
13663 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 13664 | break; |
c4e6575c | 13665 | } |
9c8a620e | 13666 | |
acd9c119 MC |
13667 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
13668 | vlen += sizeof(v); | |
c4e6575c | 13669 | } |
acd9c119 MC |
13670 | } |
13671 | ||
7fd76445 MC |
13672 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
13673 | { | |
13674 | int vlen; | |
13675 | u32 apedata; | |
ecc79648 | 13676 | char *fwtype; |
7fd76445 | 13677 | |
63c3a66f | 13678 | if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF)) |
7fd76445 MC |
13679 | return; |
13680 | ||
13681 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
13682 | if (apedata != APE_SEG_SIG_MAGIC) | |
13683 | return; | |
13684 | ||
13685 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
13686 | if (!(apedata & APE_FW_STATUS_READY)) | |
13687 | return; | |
13688 | ||
13689 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
13690 | ||
dc6d0744 | 13691 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
63c3a66f | 13692 | tg3_flag_set(tp, APE_HAS_NCSI); |
ecc79648 | 13693 | fwtype = "NCSI"; |
dc6d0744 | 13694 | } else { |
ecc79648 | 13695 | fwtype = "DASH"; |
dc6d0744 | 13696 | } |
ecc79648 | 13697 | |
7fd76445 MC |
13698 | vlen = strlen(tp->fw_ver); |
13699 | ||
ecc79648 MC |
13700 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
13701 | fwtype, | |
7fd76445 MC |
13702 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
13703 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
13704 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
13705 | (apedata & APE_FW_VERSION_BLDMSK)); | |
13706 | } | |
13707 | ||
acd9c119 MC |
13708 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
13709 | { | |
13710 | u32 val; | |
75f9936e | 13711 | bool vpd_vers = false; |
acd9c119 | 13712 | |
75f9936e MC |
13713 | if (tp->fw_ver[0] != 0) |
13714 | vpd_vers = true; | |
df259d8c | 13715 | |
63c3a66f | 13716 | if (tg3_flag(tp, NO_NVRAM)) { |
75f9936e | 13717 | strcat(tp->fw_ver, "sb"); |
df259d8c MC |
13718 | return; |
13719 | } | |
13720 | ||
acd9c119 MC |
13721 | if (tg3_nvram_read(tp, 0, &val)) |
13722 | return; | |
13723 | ||
13724 | if (val == TG3_EEPROM_MAGIC) | |
13725 | tg3_read_bc_ver(tp); | |
13726 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13727 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
13728 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
13729 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
13730 | else |
13731 | return; | |
13732 | ||
c9cab24e | 13733 | if (vpd_vers) |
75f9936e | 13734 | goto done; |
acd9c119 | 13735 | |
c9cab24e MC |
13736 | if (tg3_flag(tp, ENABLE_APE)) { |
13737 | if (tg3_flag(tp, ENABLE_ASF)) | |
13738 | tg3_read_dash_ver(tp); | |
13739 | } else if (tg3_flag(tp, ENABLE_ASF)) { | |
13740 | tg3_read_mgmtfw_ver(tp); | |
13741 | } | |
9c8a620e | 13742 | |
75f9936e | 13743 | done: |
9c8a620e | 13744 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
13745 | } |
13746 | ||
7544b097 MC |
13747 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
13748 | ||
7cb32cf2 MC |
13749 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13750 | { | |
63c3a66f | 13751 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
de9f5230 | 13752 | return TG3_RX_RET_MAX_SIZE_5717; |
63c3a66f | 13753 | else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) |
de9f5230 | 13754 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 13755 | else |
de9f5230 | 13756 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
13757 | } |
13758 | ||
4143470c | 13759 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
13760 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
13761 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13762 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13763 | { }, | |
13764 | }; | |
13765 | ||
1da177e4 LT |
13766 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
13767 | { | |
1da177e4 | 13768 | u32 misc_ctrl_reg; |
1da177e4 LT |
13769 | u32 pci_state_reg, grc_misc_cfg; |
13770 | u32 val; | |
13771 | u16 pci_cmd; | |
5e7dfd0f | 13772 | int err; |
1da177e4 | 13773 | |
1da177e4 LT |
13774 | /* Force memory write invalidate off. If we leave it on, |
13775 | * then on 5700_BX chips we have to enable a workaround. | |
13776 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
13777 | * to match the cacheline size. The Broadcom driver have this | |
13778 | * workaround but turns MWI off all the times so never uses | |
13779 | * it. This seems to suggest that the workaround is insufficient. | |
13780 | */ | |
13781 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13782 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
13783 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13784 | ||
16821285 MC |
13785 | /* Important! -- Make sure register accesses are byteswapped |
13786 | * correctly. Also, for those chips that require it, make | |
13787 | * sure that indirect register accesses are enabled before | |
13788 | * the first operation. | |
1da177e4 LT |
13789 | */ |
13790 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13791 | &misc_ctrl_reg); | |
16821285 MC |
13792 | tp->misc_host_ctrl |= (misc_ctrl_reg & |
13793 | MISC_HOST_CTRL_CHIPREV); | |
13794 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13795 | tp->misc_host_ctrl); | |
1da177e4 LT |
13796 | |
13797 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
13798 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
13799 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
13800 | u32 prod_id_asic_rev; | |
13801 | ||
5001e2f6 MC |
13802 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
13803 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
d78b59f5 MC |
13804 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || |
13805 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
f6eb9b1f MC |
13806 | pci_read_config_dword(tp->pdev, |
13807 | TG3PCI_GEN2_PRODID_ASICREV, | |
13808 | &prod_id_asic_rev); | |
b703df6f MC |
13809 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
13810 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13811 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13812 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
13813 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
55086ad9 MC |
13814 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || |
13815 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || | |
13816 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || | |
13817 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || | |
13818 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) | |
b703df6f MC |
13819 | pci_read_config_dword(tp->pdev, |
13820 | TG3PCI_GEN15_PRODID_ASICREV, | |
13821 | &prod_id_asic_rev); | |
f6eb9b1f MC |
13822 | else |
13823 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
13824 | &prod_id_asic_rev); | |
13825 | ||
321d32a0 | 13826 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 13827 | } |
1da177e4 | 13828 | |
ff645bec MC |
13829 | /* Wrong chip ID in 5752 A0. This code can be removed later |
13830 | * as A0 is not in production. | |
13831 | */ | |
13832 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
13833 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
13834 | ||
6892914f MC |
13835 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
13836 | * we need to disable memory and use config. cycles | |
13837 | * only to access all registers. The 5702/03 chips | |
13838 | * can mistakenly decode the special cycles from the | |
13839 | * ICH chipsets as memory write cycles, causing corruption | |
13840 | * of register and memory space. Only certain ICH bridges | |
13841 | * will drive special cycles with non-zero data during the | |
13842 | * address phase which can fall within the 5703's address | |
13843 | * range. This is not an ICH bug as the PCI spec allows | |
13844 | * non-zero address during special cycles. However, only | |
13845 | * these ICH bridges are known to drive non-zero addresses | |
13846 | * during special cycles. | |
13847 | * | |
13848 | * Since special cycles do not cross PCI bridges, we only | |
13849 | * enable this workaround if the 5703 is on the secondary | |
13850 | * bus of these ICH bridges. | |
13851 | */ | |
13852 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
13853 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
13854 | static struct tg3_dev_id { | |
13855 | u32 vendor; | |
13856 | u32 device; | |
13857 | u32 rev; | |
13858 | } ich_chipsets[] = { | |
13859 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
13860 | PCI_ANY_ID }, | |
13861 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
13862 | PCI_ANY_ID }, | |
13863 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
13864 | 0xa }, | |
13865 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
13866 | PCI_ANY_ID }, | |
13867 | { }, | |
13868 | }; | |
13869 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
13870 | struct pci_dev *bridge = NULL; | |
13871 | ||
13872 | while (pci_id->vendor != 0) { | |
13873 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
13874 | bridge); | |
13875 | if (!bridge) { | |
13876 | pci_id++; | |
13877 | continue; | |
13878 | } | |
13879 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 13880 | if (bridge->revision > pci_id->rev) |
6892914f MC |
13881 | continue; |
13882 | } | |
13883 | if (bridge->subordinate && | |
13884 | (bridge->subordinate->number == | |
13885 | tp->pdev->bus->number)) { | |
63c3a66f | 13886 | tg3_flag_set(tp, ICH_WORKAROUND); |
6892914f MC |
13887 | pci_dev_put(bridge); |
13888 | break; | |
13889 | } | |
13890 | } | |
13891 | } | |
13892 | ||
6ff6f81d | 13893 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
41588ba1 MC |
13894 | static struct tg3_dev_id { |
13895 | u32 vendor; | |
13896 | u32 device; | |
13897 | } bridge_chipsets[] = { | |
13898 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13899 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13900 | { }, | |
13901 | }; | |
13902 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13903 | struct pci_dev *bridge = NULL; | |
13904 | ||
13905 | while (pci_id->vendor != 0) { | |
13906 | bridge = pci_get_device(pci_id->vendor, | |
13907 | pci_id->device, | |
13908 | bridge); | |
13909 | if (!bridge) { | |
13910 | pci_id++; | |
13911 | continue; | |
13912 | } | |
13913 | if (bridge->subordinate && | |
13914 | (bridge->subordinate->number <= | |
13915 | tp->pdev->bus->number) && | |
13916 | (bridge->subordinate->subordinate >= | |
13917 | tp->pdev->bus->number)) { | |
63c3a66f | 13918 | tg3_flag_set(tp, 5701_DMA_BUG); |
41588ba1 MC |
13919 | pci_dev_put(bridge); |
13920 | break; | |
13921 | } | |
13922 | } | |
13923 | } | |
13924 | ||
4a29cc2e MC |
13925 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
13926 | * DMA addresses > 40-bit. This bridge may have other additional | |
13927 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13928 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13929 | * DMA workaround. | |
13930 | */ | |
a4e2b347 MC |
13931 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
13932 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
63c3a66f JP |
13933 | tg3_flag_set(tp, 5780_CLASS); |
13934 | tg3_flag_set(tp, 40BIT_DMA_BUG); | |
4cf78e4f | 13935 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 13936 | } else { |
4a29cc2e MC |
13937 | struct pci_dev *bridge = NULL; |
13938 | ||
13939 | do { | |
13940 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13941 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13942 | bridge); | |
13943 | if (bridge && bridge->subordinate && | |
13944 | (bridge->subordinate->number <= | |
13945 | tp->pdev->bus->number) && | |
13946 | (bridge->subordinate->subordinate >= | |
13947 | tp->pdev->bus->number)) { | |
63c3a66f | 13948 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4a29cc2e MC |
13949 | pci_dev_put(bridge); |
13950 | break; | |
13951 | } | |
13952 | } while (bridge); | |
13953 | } | |
4cf78e4f | 13954 | |
f6eb9b1f | 13955 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
3a1e19d3 | 13956 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) |
7544b097 MC |
13957 | tp->pdev_peer = tg3_find_peer(tp); |
13958 | ||
c885e824 | 13959 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
d78b59f5 MC |
13960 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13961 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
63c3a66f | 13962 | tg3_flag_set(tp, 5717_PLUS); |
0a58d668 MC |
13963 | |
13964 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
55086ad9 MC |
13965 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) |
13966 | tg3_flag_set(tp, 57765_CLASS); | |
13967 | ||
13968 | if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS)) | |
63c3a66f | 13969 | tg3_flag_set(tp, 57765_PLUS); |
c885e824 | 13970 | |
321d32a0 MC |
13971 | /* Intentionally exclude ASIC_REV_5906 */ |
13972 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 13973 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 13974 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 13975 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 13976 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13977 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
63c3a66f JP |
13978 | tg3_flag(tp, 57765_PLUS)) |
13979 | tg3_flag_set(tp, 5755_PLUS); | |
321d32a0 MC |
13980 | |
13981 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13982 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 13983 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
63c3a66f JP |
13984 | tg3_flag(tp, 5755_PLUS) || |
13985 | tg3_flag(tp, 5780_CLASS)) | |
13986 | tg3_flag_set(tp, 5750_PLUS); | |
6708e5cc | 13987 | |
6ff6f81d | 13988 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
63c3a66f JP |
13989 | tg3_flag(tp, 5750_PLUS)) |
13990 | tg3_flag_set(tp, 5705_PLUS); | |
1b440c56 | 13991 | |
507399f1 | 13992 | /* Determine TSO capabilities */ |
a0512944 | 13993 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) |
4d163b75 | 13994 | ; /* Do nothing. HW bug. */ |
63c3a66f JP |
13995 | else if (tg3_flag(tp, 57765_PLUS)) |
13996 | tg3_flag_set(tp, HW_TSO_3); | |
13997 | else if (tg3_flag(tp, 5755_PLUS) || | |
e849cdc3 | 13998 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
63c3a66f JP |
13999 | tg3_flag_set(tp, HW_TSO_2); |
14000 | else if (tg3_flag(tp, 5750_PLUS)) { | |
14001 | tg3_flag_set(tp, HW_TSO_1); | |
14002 | tg3_flag_set(tp, TSO_BUG); | |
507399f1 MC |
14003 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && |
14004 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
63c3a66f | 14005 | tg3_flag_clear(tp, TSO_BUG); |
507399f1 MC |
14006 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14007 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
14008 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 14009 | tg3_flag_set(tp, TSO_BUG); |
507399f1 MC |
14010 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) |
14011 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
14012 | else | |
14013 | tp->fw_needed = FIRMWARE_TG3TSO; | |
14014 | } | |
14015 | ||
dabc5c67 | 14016 | /* Selectively allow TSO based on operating conditions */ |
6ff6f81d MC |
14017 | if (tg3_flag(tp, HW_TSO_1) || |
14018 | tg3_flag(tp, HW_TSO_2) || | |
14019 | tg3_flag(tp, HW_TSO_3) || | |
cf9ecf4b MC |
14020 | tp->fw_needed) { |
14021 | /* For firmware TSO, assume ASF is disabled. | |
14022 | * We'll disable TSO later if we discover ASF | |
14023 | * is enabled in tg3_get_eeprom_hw_cfg(). | |
14024 | */ | |
dabc5c67 | 14025 | tg3_flag_set(tp, TSO_CAPABLE); |
cf9ecf4b | 14026 | } else { |
dabc5c67 MC |
14027 | tg3_flag_clear(tp, TSO_CAPABLE); |
14028 | tg3_flag_clear(tp, TSO_BUG); | |
14029 | tp->fw_needed = NULL; | |
14030 | } | |
14031 | ||
14032 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
14033 | tp->fw_needed = FIRMWARE_TG3; | |
14034 | ||
507399f1 MC |
14035 | tp->irq_max = 1; |
14036 | ||
63c3a66f JP |
14037 | if (tg3_flag(tp, 5750_PLUS)) { |
14038 | tg3_flag_set(tp, SUPPORT_MSI); | |
7544b097 MC |
14039 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || |
14040 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
14041 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
14042 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
14043 | tp->pdev_peer == tp->pdev)) | |
63c3a66f | 14044 | tg3_flag_clear(tp, SUPPORT_MSI); |
7544b097 | 14045 | |
63c3a66f | 14046 | if (tg3_flag(tp, 5755_PLUS) || |
b5d3772c | 14047 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
63c3a66f | 14048 | tg3_flag_set(tp, 1SHOT_MSI); |
52c0fd83 | 14049 | } |
4f125f42 | 14050 | |
63c3a66f JP |
14051 | if (tg3_flag(tp, 57765_PLUS)) { |
14052 | tg3_flag_set(tp, SUPPORT_MSIX); | |
507399f1 MC |
14053 | tp->irq_max = TG3_IRQ_MAX_VECS; |
14054 | } | |
f6eb9b1f | 14055 | } |
0e1406dd | 14056 | |
2ffcc981 | 14057 | if (tg3_flag(tp, 5755_PLUS)) |
63c3a66f | 14058 | tg3_flag_set(tp, SHORT_DMA_BUG); |
f6eb9b1f | 14059 | |
e31aa987 | 14060 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
a4cb428d | 14061 | tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; |
55086ad9 MC |
14062 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) |
14063 | tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; | |
e31aa987 | 14064 | |
fa6b2aae MC |
14065 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
14066 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14067 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
63c3a66f | 14068 | tg3_flag_set(tp, LRG_PROD_RING_CAP); |
de9f5230 | 14069 | |
63c3a66f | 14070 | if (tg3_flag(tp, 57765_PLUS) && |
a0512944 | 14071 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0) |
63c3a66f | 14072 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); |
b703df6f | 14073 | |
63c3a66f JP |
14074 | if (!tg3_flag(tp, 5705_PLUS) || |
14075 | tg3_flag(tp, 5780_CLASS) || | |
14076 | tg3_flag(tp, USE_JUMBO_BDFLAG)) | |
14077 | tg3_flag_set(tp, JUMBO_CAPABLE); | |
0f893dc6 | 14078 | |
52f4490c MC |
14079 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14080 | &pci_state_reg); | |
14081 | ||
708ebb3a | 14082 | if (pci_is_pcie(tp->pdev)) { |
5e7dfd0f MC |
14083 | u16 lnkctl; |
14084 | ||
63c3a66f | 14085 | tg3_flag_set(tp, PCI_EXPRESS); |
5f5c51e3 | 14086 | |
2c55a3d0 MC |
14087 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) { |
14088 | int readrq = pcie_get_readrq(tp->pdev); | |
14089 | if (readrq > 2048) | |
14090 | pcie_set_readrq(tp->pdev, 2048); | |
14091 | } | |
5f5c51e3 | 14092 | |
5e7dfd0f | 14093 | pci_read_config_word(tp->pdev, |
708ebb3a | 14094 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
5e7dfd0f MC |
14095 | &lnkctl); |
14096 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
7196cd6c MC |
14097 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
14098 | ASIC_REV_5906) { | |
63c3a66f | 14099 | tg3_flag_clear(tp, HW_TSO_2); |
dabc5c67 | 14100 | tg3_flag_clear(tp, TSO_CAPABLE); |
7196cd6c | 14101 | } |
5e7dfd0f | 14102 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 14103 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
14104 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
14105 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
63c3a66f | 14106 | tg3_flag_set(tp, CLKREQ_BUG); |
614b0590 | 14107 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
63c3a66f | 14108 | tg3_flag_set(tp, L1PLLPD_EN); |
c7835a77 | 14109 | } |
52f4490c | 14110 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
708ebb3a JM |
14111 | /* BCM5785 devices are effectively PCIe devices, and should |
14112 | * follow PCIe codepaths, but do not have a PCIe capabilities | |
14113 | * section. | |
93a700a9 | 14114 | */ |
63c3a66f JP |
14115 | tg3_flag_set(tp, PCI_EXPRESS); |
14116 | } else if (!tg3_flag(tp, 5705_PLUS) || | |
14117 | tg3_flag(tp, 5780_CLASS)) { | |
52f4490c MC |
14118 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); |
14119 | if (!tp->pcix_cap) { | |
2445e461 MC |
14120 | dev_err(&tp->pdev->dev, |
14121 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
14122 | return -EIO; |
14123 | } | |
14124 | ||
14125 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
63c3a66f | 14126 | tg3_flag_set(tp, PCIX_MODE); |
52f4490c | 14127 | } |
1da177e4 | 14128 | |
399de50b MC |
14129 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
14130 | * reordering to the mailbox registers done by the host | |
14131 | * controller can cause major troubles. We read back from | |
14132 | * every mailbox register write to force the writes to be | |
14133 | * posted to the chip in order. | |
14134 | */ | |
4143470c | 14135 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
63c3a66f JP |
14136 | !tg3_flag(tp, PCI_EXPRESS)) |
14137 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
399de50b | 14138 | |
69fc4053 MC |
14139 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
14140 | &tp->pci_cacheline_sz); | |
14141 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
14142 | &tp->pci_lat_timer); | |
1da177e4 LT |
14143 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
14144 | tp->pci_lat_timer < 64) { | |
14145 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
14146 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
14147 | tp->pci_lat_timer); | |
1da177e4 LT |
14148 | } |
14149 | ||
16821285 MC |
14150 | /* Important! -- It is critical that the PCI-X hw workaround |
14151 | * situation is decided before the first MMIO register access. | |
14152 | */ | |
52f4490c MC |
14153 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
14154 | /* 5700 BX chips need to have their TX producer index | |
14155 | * mailboxes written twice to workaround a bug. | |
14156 | */ | |
63c3a66f | 14157 | tg3_flag_set(tp, TXD_MBOX_HWBUG); |
1da177e4 | 14158 | |
52f4490c | 14159 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
14160 | * |
14161 | * The workaround is to use indirect register accesses | |
14162 | * for all chip writes not to mailbox registers. | |
14163 | */ | |
63c3a66f | 14164 | if (tg3_flag(tp, PCIX_MODE)) { |
1da177e4 | 14165 | u32 pm_reg; |
1da177e4 | 14166 | |
63c3a66f | 14167 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14168 | |
14169 | /* The chip can have it's power management PCI config | |
14170 | * space registers clobbered due to this bug. | |
14171 | * So explicitly force the chip into D0 here. | |
14172 | */ | |
9974a356 MC |
14173 | pci_read_config_dword(tp->pdev, |
14174 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
14175 | &pm_reg); |
14176 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
14177 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
14178 | pci_write_config_dword(tp->pdev, |
14179 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
14180 | pm_reg); |
14181 | ||
14182 | /* Also, force SERR#/PERR# in PCI command. */ | |
14183 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14184 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
14185 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14186 | } | |
14187 | } | |
14188 | ||
1da177e4 | 14189 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
63c3a66f | 14190 | tg3_flag_set(tp, PCI_HIGH_SPEED); |
1da177e4 | 14191 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) |
63c3a66f | 14192 | tg3_flag_set(tp, PCI_32BIT); |
1da177e4 LT |
14193 | |
14194 | /* Chip-specific fixup from Broadcom driver */ | |
14195 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
14196 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
14197 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
14198 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
14199 | } | |
14200 | ||
1ee582d8 | 14201 | /* Default fast path register access methods */ |
20094930 | 14202 | tp->read32 = tg3_read32; |
1ee582d8 | 14203 | tp->write32 = tg3_write32; |
09ee929c | 14204 | tp->read32_mbox = tg3_read32; |
20094930 | 14205 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
14206 | tp->write32_tx_mbox = tg3_write32; |
14207 | tp->write32_rx_mbox = tg3_write32; | |
14208 | ||
14209 | /* Various workaround register access methods */ | |
63c3a66f | 14210 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) |
1ee582d8 | 14211 | tp->write32 = tg3_write_indirect_reg32; |
98efd8a6 | 14212 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
63c3a66f | 14213 | (tg3_flag(tp, PCI_EXPRESS) && |
98efd8a6 MC |
14214 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { |
14215 | /* | |
14216 | * Back to back register writes can cause problems on these | |
14217 | * chips, the workaround is to read back all reg writes | |
14218 | * except those to mailbox regs. | |
14219 | * | |
14220 | * See tg3_write_indirect_reg32(). | |
14221 | */ | |
1ee582d8 | 14222 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
14223 | } |
14224 | ||
63c3a66f | 14225 | if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { |
1ee582d8 | 14226 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
63c3a66f | 14227 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1ee582d8 MC |
14228 | tp->write32_rx_mbox = tg3_write_flush_reg32; |
14229 | } | |
20094930 | 14230 | |
63c3a66f | 14231 | if (tg3_flag(tp, ICH_WORKAROUND)) { |
6892914f MC |
14232 | tp->read32 = tg3_read_indirect_reg32; |
14233 | tp->write32 = tg3_write_indirect_reg32; | |
14234 | tp->read32_mbox = tg3_read_indirect_mbox; | |
14235 | tp->write32_mbox = tg3_write_indirect_mbox; | |
14236 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
14237 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
14238 | ||
14239 | iounmap(tp->regs); | |
22abe310 | 14240 | tp->regs = NULL; |
6892914f MC |
14241 | |
14242 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14243 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
14244 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14245 | } | |
b5d3772c MC |
14246 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14247 | tp->read32_mbox = tg3_read32_mbox_5906; | |
14248 | tp->write32_mbox = tg3_write32_mbox_5906; | |
14249 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
14250 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
14251 | } | |
6892914f | 14252 | |
bbadf503 | 14253 | if (tp->write32 == tg3_write_indirect_reg32 || |
63c3a66f | 14254 | (tg3_flag(tp, PCIX_MODE) && |
bbadf503 | 14255 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
f49639e6 | 14256 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
63c3a66f | 14257 | tg3_flag_set(tp, SRAM_USE_CONFIG); |
bbadf503 | 14258 | |
16821285 MC |
14259 | /* The memory arbiter has to be enabled in order for SRAM accesses |
14260 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
14261 | * sure it is enabled, but other entities such as system netboot | |
14262 | * code might disable it. | |
14263 | */ | |
14264 | val = tr32(MEMARB_MODE); | |
14265 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
14266 | ||
9dc5e342 MC |
14267 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; |
14268 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
14269 | tg3_flag(tp, 5780_CLASS)) { | |
14270 | if (tg3_flag(tp, PCIX_MODE)) { | |
14271 | pci_read_config_dword(tp->pdev, | |
14272 | tp->pcix_cap + PCI_X_STATUS, | |
14273 | &val); | |
14274 | tp->pci_fn = val & 0x7; | |
14275 | } | |
14276 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
14277 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | |
14278 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == | |
14279 | NIC_SRAM_CPMUSTAT_SIG) { | |
14280 | tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717; | |
14281 | tp->pci_fn = tp->pci_fn ? 1 : 0; | |
14282 | } | |
14283 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14284 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
14285 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | |
14286 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == | |
14287 | NIC_SRAM_CPMUSTAT_SIG) { | |
14288 | tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> | |
14289 | TG3_CPMU_STATUS_FSHFT_5719; | |
14290 | } | |
69f11c99 MC |
14291 | } |
14292 | ||
7d0c41ef | 14293 | /* Get eeprom hw config before calling tg3_set_power_state(). |
63c3a66f | 14294 | * In particular, the TG3_FLAG_IS_NIC flag must be |
7d0c41ef MC |
14295 | * determined before calling tg3_set_power_state() so that |
14296 | * we know whether or not to switch out of Vaux power. | |
14297 | * When the flag is set, it means that GPIO1 is used for eeprom | |
14298 | * write protect and also implies that it is a LOM where GPIOs | |
14299 | * are not used to switch power. | |
6aa20a22 | 14300 | */ |
7d0c41ef MC |
14301 | tg3_get_eeprom_hw_cfg(tp); |
14302 | ||
cf9ecf4b MC |
14303 | if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) { |
14304 | tg3_flag_clear(tp, TSO_CAPABLE); | |
14305 | tg3_flag_clear(tp, TSO_BUG); | |
14306 | tp->fw_needed = NULL; | |
14307 | } | |
14308 | ||
63c3a66f | 14309 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
14310 | /* Allow reads and writes to the |
14311 | * APE register and memory space. | |
14312 | */ | |
14313 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
14314 | PCISTATE_ALLOW_APE_SHMEM_WR | |
14315 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
14316 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14317 | pci_state_reg); | |
c9cab24e MC |
14318 | |
14319 | tg3_ape_lock_init(tp); | |
0d3031d9 MC |
14320 | } |
14321 | ||
9936bcf6 | 14322 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 14323 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 14324 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 14325 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
63c3a66f JP |
14326 | tg3_flag(tp, 57765_PLUS)) |
14327 | tg3_flag_set(tp, CPMU_PRESENT); | |
d30cdd28 | 14328 | |
16821285 MC |
14329 | /* Set up tp->grc_local_ctrl before calling |
14330 | * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high | |
14331 | * will bring 5700's external PHY out of reset. | |
314fba34 MC |
14332 | * It is also used as eeprom write protect on LOMs. |
14333 | */ | |
14334 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
6ff6f81d | 14335 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
63c3a66f | 14336 | tg3_flag(tp, EEPROM_WRITE_PROT)) |
314fba34 MC |
14337 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
14338 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
14339 | /* Unused GPIO3 must be driven as output on 5752 because there |
14340 | * are no pull-up resistors on unused GPIO pins. | |
14341 | */ | |
14342 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
14343 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 14344 | |
321d32a0 | 14345 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd | 14346 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
55086ad9 | 14347 | tg3_flag(tp, 57765_CLASS)) |
af36e6b6 MC |
14348 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
14349 | ||
8d519ab2 MC |
14350 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
14351 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
14352 | /* Turn off the debug UART. */ |
14353 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
63c3a66f | 14354 | if (tg3_flag(tp, IS_NIC)) |
5f0c4a3c MC |
14355 | /* Keep VMain power. */ |
14356 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
14357 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
14358 | } | |
14359 | ||
16821285 MC |
14360 | /* Switch out of Vaux if it is a NIC */ |
14361 | tg3_pwrsrc_switch_to_vmain(tp); | |
1da177e4 | 14362 | |
1da177e4 LT |
14363 | /* Derive initial jumbo mode from MTU assigned in |
14364 | * ether_setup() via the alloc_etherdev() call | |
14365 | */ | |
63c3a66f JP |
14366 | if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) |
14367 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
1da177e4 LT |
14368 | |
14369 | /* Determine WakeOnLan speed to use. */ | |
14370 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14371 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
14372 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
14373 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
63c3a66f | 14374 | tg3_flag_clear(tp, WOL_SPEED_100MB); |
1da177e4 | 14375 | } else { |
63c3a66f | 14376 | tg3_flag_set(tp, WOL_SPEED_100MB); |
1da177e4 LT |
14377 | } |
14378 | ||
7f97a4bd | 14379 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 14380 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 14381 | |
1da177e4 | 14382 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
6ff6f81d MC |
14383 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
14384 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
1da177e4 | 14385 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && |
747e8f8b | 14386 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
14387 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
14388 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
14389 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
14390 | |
14391 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
14392 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 14393 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 14394 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 14395 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 14396 | |
63c3a66f | 14397 | if (tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 14398 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 14399 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 14400 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
63c3a66f | 14401 | !tg3_flag(tp, 57765_PLUS)) { |
c424cb24 | 14402 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 14403 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
14404 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
14405 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
14406 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
14407 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 14408 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 14409 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 14410 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 14411 | } else |
f07e9af3 | 14412 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 14413 | } |
1da177e4 | 14414 | |
b2a5c19c MC |
14415 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14416 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
14417 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
14418 | if (tp->phy_otp == 0) | |
14419 | tp->phy_otp = TG3_OTP_DEFAULT; | |
14420 | } | |
14421 | ||
63c3a66f | 14422 | if (tg3_flag(tp, CPMU_PRESENT)) |
8ef21428 MC |
14423 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
14424 | else | |
14425 | tp->mi_mode = MAC_MI_MODE_BASE; | |
14426 | ||
1da177e4 | 14427 | tp->coalesce_mode = 0; |
1da177e4 LT |
14428 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
14429 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
14430 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
14431 | ||
4d958473 MC |
14432 | /* Set these bits to enable statistics workaround. */ |
14433 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14434 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
14435 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
14436 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
14437 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
14438 | } | |
14439 | ||
321d32a0 MC |
14440 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
14441 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
63c3a66f | 14442 | tg3_flag_set(tp, USE_PHYLIB); |
57e6983c | 14443 | |
158d7abd MC |
14444 | err = tg3_mdio_init(tp); |
14445 | if (err) | |
14446 | return err; | |
1da177e4 LT |
14447 | |
14448 | /* Initialize data/descriptor byte/word swapping. */ | |
14449 | val = tr32(GRC_MODE); | |
f2096f94 MC |
14450 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
14451 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
14452 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
14453 | GRC_MODE_B2HRX_ENABLE | | |
14454 | GRC_MODE_HTX2B_ENABLE | | |
14455 | GRC_MODE_HOST_STACKUP); | |
14456 | else | |
14457 | val &= GRC_MODE_HOST_STACKUP; | |
14458 | ||
1da177e4 LT |
14459 | tw32(GRC_MODE, val | tp->grc_mode); |
14460 | ||
14461 | tg3_switch_clocks(tp); | |
14462 | ||
14463 | /* Clear this out for sanity. */ | |
14464 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14465 | ||
14466 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
14467 | &pci_state_reg); | |
14468 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
63c3a66f | 14469 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { |
1da177e4 LT |
14470 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); |
14471 | ||
14472 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
14473 | chiprevid == CHIPREV_ID_5701_B0 || | |
14474 | chiprevid == CHIPREV_ID_5701_B2 || | |
14475 | chiprevid == CHIPREV_ID_5701_B5) { | |
14476 | void __iomem *sram_base; | |
14477 | ||
14478 | /* Write some dummy words into the SRAM status block | |
14479 | * area, see if it reads back correctly. If the return | |
14480 | * value is bad, force enable the PCIX workaround. | |
14481 | */ | |
14482 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
14483 | ||
14484 | writel(0x00000000, sram_base); | |
14485 | writel(0x00000000, sram_base + 4); | |
14486 | writel(0xffffffff, sram_base + 4); | |
14487 | if (readl(sram_base) != 0x00000000) | |
63c3a66f | 14488 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14489 | } |
14490 | } | |
14491 | ||
14492 | udelay(50); | |
14493 | tg3_nvram_init(tp); | |
14494 | ||
14495 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
14496 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
14497 | ||
1da177e4 LT |
14498 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
14499 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
14500 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
63c3a66f | 14501 | tg3_flag_set(tp, IS_5788); |
1da177e4 | 14502 | |
63c3a66f | 14503 | if (!tg3_flag(tp, IS_5788) && |
6ff6f81d | 14504 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
63c3a66f JP |
14505 | tg3_flag_set(tp, TAGGED_STATUS); |
14506 | if (tg3_flag(tp, TAGGED_STATUS)) { | |
fac9b83e DM |
14507 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | |
14508 | HOSTCC_MODE_CLRTICK_TXBD); | |
14509 | ||
14510 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
14511 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14512 | tp->misc_host_ctrl); | |
14513 | } | |
14514 | ||
3bda1258 | 14515 | /* Preserve the APE MAC_MODE bits */ |
63c3a66f | 14516 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b | 14517 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 | 14518 | else |
6e01b20b | 14519 | tp->mac_mode = 0; |
3bda1258 | 14520 | |
1da177e4 LT |
14521 | /* these are limited to 10/100 only */ |
14522 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14523 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14524 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14525 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14526 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
14527 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
14528 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
14529 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14530 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
14531 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
14532 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 14533 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
14534 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
14535 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
f07e9af3 MC |
14536 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
14537 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
1da177e4 LT |
14538 | |
14539 | err = tg3_phy_probe(tp); | |
14540 | if (err) { | |
2445e461 | 14541 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 14542 | /* ... but do not return immediately ... */ |
b02fd9e3 | 14543 | tg3_mdio_fini(tp); |
1da177e4 LT |
14544 | } |
14545 | ||
184b8904 | 14546 | tg3_read_vpd(tp); |
c4e6575c | 14547 | tg3_read_fw_ver(tp); |
1da177e4 | 14548 | |
f07e9af3 MC |
14549 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
14550 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
14551 | } else { |
14552 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 14553 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 14554 | else |
f07e9af3 | 14555 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
14556 | } |
14557 | ||
14558 | /* 5700 {AX,BX} chips have a broken status block link | |
14559 | * change bit implementation, so we must use the | |
14560 | * status register in those cases. | |
14561 | */ | |
14562 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
63c3a66f | 14563 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 | 14564 | else |
63c3a66f | 14565 | tg3_flag_clear(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14566 | |
14567 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
14568 | * have to force the link status polling mechanism based | |
14569 | * upon subsystem IDs. | |
14570 | */ | |
14571 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 14572 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
14573 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
14574 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
63c3a66f | 14575 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 LT |
14576 | } |
14577 | ||
14578 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 14579 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
63c3a66f | 14580 | tg3_flag_set(tp, POLL_SERDES); |
1da177e4 | 14581 | else |
63c3a66f | 14582 | tg3_flag_clear(tp, POLL_SERDES); |
1da177e4 | 14583 | |
9205fd9c | 14584 | tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; |
d2757fc4 | 14585 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 14586 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
63c3a66f | 14587 | tg3_flag(tp, PCIX_MODE)) { |
9205fd9c | 14588 | tp->rx_offset = NET_SKB_PAD; |
d2757fc4 | 14589 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 14590 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
14591 | #endif |
14592 | } | |
1da177e4 | 14593 | |
2c49a44d MC |
14594 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
14595 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
14596 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
14597 | ||
2c49a44d | 14598 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
14599 | |
14600 | /* Increment the rx prod index on the rx std ring by at most | |
14601 | * 8 for these chips to workaround hw errata. | |
14602 | */ | |
14603 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14604 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14605 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
14606 | tp->rx_std_max_post = 8; | |
14607 | ||
63c3a66f | 14608 | if (tg3_flag(tp, ASPM_WORKAROUND)) |
8ed5d97e MC |
14609 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & |
14610 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
14611 | ||
1da177e4 LT |
14612 | return err; |
14613 | } | |
14614 | ||
49b6e95f | 14615 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14616 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
14617 | { | |
14618 | struct net_device *dev = tp->dev; | |
14619 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 14620 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 14621 | const unsigned char *addr; |
49b6e95f DM |
14622 | int len; |
14623 | ||
14624 | addr = of_get_property(dp, "local-mac-address", &len); | |
14625 | if (addr && len == 6) { | |
14626 | memcpy(dev->dev_addr, addr, 6); | |
14627 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
14628 | return 0; | |
1da177e4 LT |
14629 | } |
14630 | return -ENODEV; | |
14631 | } | |
14632 | ||
14633 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
14634 | { | |
14635 | struct net_device *dev = tp->dev; | |
14636 | ||
14637 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 14638 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
14639 | return 0; |
14640 | } | |
14641 | #endif | |
14642 | ||
14643 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
14644 | { | |
14645 | struct net_device *dev = tp->dev; | |
14646 | u32 hi, lo, mac_offset; | |
008652b3 | 14647 | int addr_ok = 0; |
1da177e4 | 14648 | |
49b6e95f | 14649 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14650 | if (!tg3_get_macaddr_sparc(tp)) |
14651 | return 0; | |
14652 | #endif | |
14653 | ||
14654 | mac_offset = 0x7c; | |
6ff6f81d | 14655 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
63c3a66f | 14656 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 LT |
14657 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
14658 | mac_offset = 0xcc; | |
14659 | if (tg3_nvram_lock(tp)) | |
14660 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
14661 | else | |
14662 | tg3_nvram_unlock(tp); | |
63c3a66f | 14663 | } else if (tg3_flag(tp, 5717_PLUS)) { |
69f11c99 | 14664 | if (tp->pci_fn & 1) |
a1b950d5 | 14665 | mac_offset = 0xcc; |
69f11c99 | 14666 | if (tp->pci_fn > 1) |
a50d0796 | 14667 | mac_offset += 0x18c; |
a1b950d5 | 14668 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 14669 | mac_offset = 0x10; |
1da177e4 LT |
14670 | |
14671 | /* First try to get it from MAC address mailbox. */ | |
14672 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
14673 | if ((hi >> 16) == 0x484b) { | |
14674 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14675 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
14676 | ||
14677 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
14678 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14679 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14680 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14681 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 14682 | |
008652b3 MC |
14683 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
14684 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
14685 | } | |
14686 | if (!addr_ok) { | |
14687 | /* Next, try NVRAM. */ | |
63c3a66f | 14688 | if (!tg3_flag(tp, NO_NVRAM) && |
df259d8c | 14689 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && |
6d348f2c | 14690 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
14691 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
14692 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
14693 | } |
14694 | /* Finally just fetch it out of the MAC control regs. */ | |
14695 | else { | |
14696 | hi = tr32(MAC_ADDR_0_HIGH); | |
14697 | lo = tr32(MAC_ADDR_0_LOW); | |
14698 | ||
14699 | dev->dev_addr[5] = lo & 0xff; | |
14700 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14701 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14702 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14703 | dev->dev_addr[1] = hi & 0xff; | |
14704 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14705 | } | |
1da177e4 LT |
14706 | } |
14707 | ||
14708 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 14709 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14710 | if (!tg3_get_default_macaddr_sparc(tp)) |
14711 | return 0; | |
14712 | #endif | |
14713 | return -EINVAL; | |
14714 | } | |
2ff43697 | 14715 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
14716 | return 0; |
14717 | } | |
14718 | ||
59e6b434 DM |
14719 | #define BOUNDARY_SINGLE_CACHELINE 1 |
14720 | #define BOUNDARY_MULTI_CACHELINE 2 | |
14721 | ||
14722 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
14723 | { | |
14724 | int cacheline_size; | |
14725 | u8 byte; | |
14726 | int goal; | |
14727 | ||
14728 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
14729 | if (byte == 0) | |
14730 | cacheline_size = 1024; | |
14731 | else | |
14732 | cacheline_size = (int) byte * 4; | |
14733 | ||
14734 | /* On 5703 and later chips, the boundary bits have no | |
14735 | * effect. | |
14736 | */ | |
14737 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14738 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
63c3a66f | 14739 | !tg3_flag(tp, PCI_EXPRESS)) |
59e6b434 DM |
14740 | goto out; |
14741 | ||
14742 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
14743 | goal = BOUNDARY_MULTI_CACHELINE; | |
14744 | #else | |
14745 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
14746 | goal = BOUNDARY_SINGLE_CACHELINE; | |
14747 | #else | |
14748 | goal = 0; | |
14749 | #endif | |
14750 | #endif | |
14751 | ||
63c3a66f | 14752 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
14753 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
14754 | goto out; | |
14755 | } | |
14756 | ||
59e6b434 DM |
14757 | if (!goal) |
14758 | goto out; | |
14759 | ||
14760 | /* PCI controllers on most RISC systems tend to disconnect | |
14761 | * when a device tries to burst across a cache-line boundary. | |
14762 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
14763 | * | |
14764 | * Unfortunately, for PCI-E there are only limited | |
14765 | * write-side controls for this, and thus for reads | |
14766 | * we will still get the disconnects. We'll also waste | |
14767 | * these PCI cycles for both read and write for chips | |
14768 | * other than 5700 and 5701 which do not implement the | |
14769 | * boundary bits. | |
14770 | */ | |
63c3a66f | 14771 | if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14772 | switch (cacheline_size) { |
14773 | case 16: | |
14774 | case 32: | |
14775 | case 64: | |
14776 | case 128: | |
14777 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14778 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
14779 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
14780 | } else { | |
14781 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14782 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14783 | } | |
14784 | break; | |
14785 | ||
14786 | case 256: | |
14787 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
14788 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
14789 | break; | |
14790 | ||
14791 | default: | |
14792 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14793 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14794 | break; | |
855e1111 | 14795 | } |
63c3a66f | 14796 | } else if (tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
14797 | switch (cacheline_size) { |
14798 | case 16: | |
14799 | case 32: | |
14800 | case 64: | |
14801 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14802 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14803 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
14804 | break; | |
14805 | } | |
14806 | /* fallthrough */ | |
14807 | case 128: | |
14808 | default: | |
14809 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14810 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
14811 | break; | |
855e1111 | 14812 | } |
59e6b434 DM |
14813 | } else { |
14814 | switch (cacheline_size) { | |
14815 | case 16: | |
14816 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14817 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
14818 | DMA_RWCTRL_WRITE_BNDRY_16); | |
14819 | break; | |
14820 | } | |
14821 | /* fallthrough */ | |
14822 | case 32: | |
14823 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14824 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
14825 | DMA_RWCTRL_WRITE_BNDRY_32); | |
14826 | break; | |
14827 | } | |
14828 | /* fallthrough */ | |
14829 | case 64: | |
14830 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14831 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
14832 | DMA_RWCTRL_WRITE_BNDRY_64); | |
14833 | break; | |
14834 | } | |
14835 | /* fallthrough */ | |
14836 | case 128: | |
14837 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14838 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
14839 | DMA_RWCTRL_WRITE_BNDRY_128); | |
14840 | break; | |
14841 | } | |
14842 | /* fallthrough */ | |
14843 | case 256: | |
14844 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
14845 | DMA_RWCTRL_WRITE_BNDRY_256); | |
14846 | break; | |
14847 | case 512: | |
14848 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
14849 | DMA_RWCTRL_WRITE_BNDRY_512); | |
14850 | break; | |
14851 | case 1024: | |
14852 | default: | |
14853 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
14854 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
14855 | break; | |
855e1111 | 14856 | } |
59e6b434 DM |
14857 | } |
14858 | ||
14859 | out: | |
14860 | return val; | |
14861 | } | |
14862 | ||
1da177e4 LT |
14863 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
14864 | { | |
14865 | struct tg3_internal_buffer_desc test_desc; | |
14866 | u32 sram_dma_descs; | |
14867 | int i, ret; | |
14868 | ||
14869 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
14870 | ||
14871 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
14872 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
14873 | tw32(RDMAC_STATUS, 0); | |
14874 | tw32(WDMAC_STATUS, 0); | |
14875 | ||
14876 | tw32(BUFMGR_MODE, 0); | |
14877 | tw32(FTQ_RESET, 0); | |
14878 | ||
14879 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
14880 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
14881 | test_desc.nic_mbuf = 0x00002100; | |
14882 | test_desc.len = size; | |
14883 | ||
14884 | /* | |
14885 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
14886 | * the *second* time the tg3 driver was getting loaded after an | |
14887 | * initial scan. | |
14888 | * | |
14889 | * Broadcom tells me: | |
14890 | * ...the DMA engine is connected to the GRC block and a DMA | |
14891 | * reset may affect the GRC block in some unpredictable way... | |
14892 | * The behavior of resets to individual blocks has not been tested. | |
14893 | * | |
14894 | * Broadcom noted the GRC reset will also reset all sub-components. | |
14895 | */ | |
14896 | if (to_device) { | |
14897 | test_desc.cqid_sqid = (13 << 8) | 2; | |
14898 | ||
14899 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
14900 | udelay(40); | |
14901 | } else { | |
14902 | test_desc.cqid_sqid = (16 << 8) | 7; | |
14903 | ||
14904 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
14905 | udelay(40); | |
14906 | } | |
14907 | test_desc.flags = 0x00000005; | |
14908 | ||
14909 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
14910 | u32 val; | |
14911 | ||
14912 | val = *(((u32 *)&test_desc) + i); | |
14913 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
14914 | sram_dma_descs + (i * sizeof(u32))); | |
14915 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
14916 | } | |
14917 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14918 | ||
859a5887 | 14919 | if (to_device) |
1da177e4 | 14920 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 14921 | else |
1da177e4 | 14922 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
14923 | |
14924 | ret = -ENODEV; | |
14925 | for (i = 0; i < 40; i++) { | |
14926 | u32 val; | |
14927 | ||
14928 | if (to_device) | |
14929 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
14930 | else | |
14931 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
14932 | if ((val & 0xffff) == sram_dma_descs) { | |
14933 | ret = 0; | |
14934 | break; | |
14935 | } | |
14936 | ||
14937 | udelay(100); | |
14938 | } | |
14939 | ||
14940 | return ret; | |
14941 | } | |
14942 | ||
ded7340d | 14943 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 14944 | |
4143470c | 14945 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
14946 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
14947 | { }, | |
14948 | }; | |
14949 | ||
1da177e4 LT |
14950 | static int __devinit tg3_test_dma(struct tg3 *tp) |
14951 | { | |
14952 | dma_addr_t buf_dma; | |
59e6b434 | 14953 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 14954 | int ret = 0; |
1da177e4 | 14955 | |
4bae65c8 MC |
14956 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
14957 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
14958 | if (!buf) { |
14959 | ret = -ENOMEM; | |
14960 | goto out_nofree; | |
14961 | } | |
14962 | ||
14963 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
14964 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
14965 | ||
59e6b434 | 14966 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 14967 | |
63c3a66f | 14968 | if (tg3_flag(tp, 57765_PLUS)) |
cbf9ca6c MC |
14969 | goto out; |
14970 | ||
63c3a66f | 14971 | if (tg3_flag(tp, PCI_EXPRESS)) { |
1da177e4 LT |
14972 | /* DMA read watermark not used on PCIE */ |
14973 | tp->dma_rwctrl |= 0x00180000; | |
63c3a66f | 14974 | } else if (!tg3_flag(tp, PCIX_MODE)) { |
85e94ced MC |
14975 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
14976 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
14977 | tp->dma_rwctrl |= 0x003f0000; |
14978 | else | |
14979 | tp->dma_rwctrl |= 0x003f000f; | |
14980 | } else { | |
14981 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14982 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14983 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 14984 | u32 read_water = 0x7; |
1da177e4 | 14985 | |
4a29cc2e MC |
14986 | /* If the 5704 is behind the EPB bridge, we can |
14987 | * do the less restrictive ONE_DMA workaround for | |
14988 | * better performance. | |
14989 | */ | |
63c3a66f | 14990 | if (tg3_flag(tp, 40BIT_DMA_BUG) && |
4a29cc2e MC |
14991 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
14992 | tp->dma_rwctrl |= 0x8000; | |
14993 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
14994 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
14995 | ||
49afdeb6 MC |
14996 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
14997 | read_water = 4; | |
59e6b434 | 14998 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
14999 | tp->dma_rwctrl |= |
15000 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
15001 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
15002 | (1 << 23); | |
4cf78e4f MC |
15003 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
15004 | /* 5780 always in PCIX mode */ | |
15005 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
15006 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
15007 | /* 5714 always in PCIX mode */ | |
15008 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
15009 | } else { |
15010 | tp->dma_rwctrl |= 0x001b000f; | |
15011 | } | |
15012 | } | |
15013 | ||
15014 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
15015 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
15016 | tp->dma_rwctrl &= 0xfffffff0; | |
15017 | ||
15018 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
15019 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
15020 | /* Remove this if it causes problems for some boards. */ | |
15021 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
15022 | ||
15023 | /* On 5700/5701 chips, we need to set this bit. | |
15024 | * Otherwise the chip will issue cacheline transactions | |
15025 | * to streamable DMA memory with not all the byte | |
15026 | * enables turned on. This is an error on several | |
15027 | * RISC PCI controllers, in particular sparc64. | |
15028 | * | |
15029 | * On 5703/5704 chips, this bit has been reassigned | |
15030 | * a different meaning. In particular, it is used | |
15031 | * on those chips to enable a PCI-X workaround. | |
15032 | */ | |
15033 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
15034 | } | |
15035 | ||
15036 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15037 | ||
15038 | #if 0 | |
15039 | /* Unneeded, already done by tg3_get_invariants. */ | |
15040 | tg3_switch_clocks(tp); | |
15041 | #endif | |
15042 | ||
1da177e4 LT |
15043 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
15044 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
15045 | goto out; | |
15046 | ||
59e6b434 DM |
15047 | /* It is best to perform DMA test with maximum write burst size |
15048 | * to expose the 5700/5701 write DMA bug. | |
15049 | */ | |
15050 | saved_dma_rwctrl = tp->dma_rwctrl; | |
15051 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
15052 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15053 | ||
1da177e4 LT |
15054 | while (1) { |
15055 | u32 *p = buf, i; | |
15056 | ||
15057 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
15058 | p[i] = i; | |
15059 | ||
15060 | /* Send the buffer to the chip. */ | |
15061 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
15062 | if (ret) { | |
2445e461 MC |
15063 | dev_err(&tp->pdev->dev, |
15064 | "%s: Buffer write failed. err = %d\n", | |
15065 | __func__, ret); | |
1da177e4 LT |
15066 | break; |
15067 | } | |
15068 | ||
15069 | #if 0 | |
15070 | /* validate data reached card RAM correctly. */ | |
15071 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
15072 | u32 val; | |
15073 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
15074 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
15075 | dev_err(&tp->pdev->dev, |
15076 | "%s: Buffer corrupted on device! " | |
15077 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
15078 | /* ret = -ENODEV here? */ |
15079 | } | |
15080 | p[i] = 0; | |
15081 | } | |
15082 | #endif | |
15083 | /* Now read it back. */ | |
15084 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
15085 | if (ret) { | |
5129c3a3 MC |
15086 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
15087 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
15088 | break; |
15089 | } | |
15090 | ||
15091 | /* Verify it. */ | |
15092 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
15093 | if (p[i] == i) | |
15094 | continue; | |
15095 | ||
59e6b434 DM |
15096 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
15097 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
15098 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
15099 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
15100 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15101 | break; | |
15102 | } else { | |
2445e461 MC |
15103 | dev_err(&tp->pdev->dev, |
15104 | "%s: Buffer corrupted on read back! " | |
15105 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
15106 | ret = -ENODEV; |
15107 | goto out; | |
15108 | } | |
15109 | } | |
15110 | ||
15111 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
15112 | /* Success. */ | |
15113 | ret = 0; | |
15114 | break; | |
15115 | } | |
15116 | } | |
59e6b434 DM |
15117 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
15118 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
15119 | /* DMA test passed without adjusting DMA boundary, | |
6d1cfbab MC |
15120 | * now look for chipsets that are known to expose the |
15121 | * DMA bug without failing the test. | |
59e6b434 | 15122 | */ |
4143470c | 15123 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
15124 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
15125 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 15126 | } else { |
6d1cfbab MC |
15127 | /* Safe to use the calculated DMA boundary. */ |
15128 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 15129 | } |
6d1cfbab | 15130 | |
59e6b434 DM |
15131 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
15132 | } | |
1da177e4 LT |
15133 | |
15134 | out: | |
4bae65c8 | 15135 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
15136 | out_nofree: |
15137 | return ret; | |
15138 | } | |
15139 | ||
1da177e4 LT |
15140 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
15141 | { | |
63c3a66f | 15142 | if (tg3_flag(tp, 57765_PLUS)) { |
666bc831 MC |
15143 | tp->bufmgr_config.mbuf_read_dma_low_water = |
15144 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15145 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15146 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
15147 | tp->bufmgr_config.mbuf_high_water = | |
15148 | DEFAULT_MB_HIGH_WATER_57765; | |
15149 | ||
15150 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15151 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15152 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15153 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
15154 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15155 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
63c3a66f | 15156 | } else if (tg3_flag(tp, 5705_PLUS)) { |
fdfec172 MC |
15157 | tp->bufmgr_config.mbuf_read_dma_low_water = |
15158 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15159 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15160 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
15161 | tp->bufmgr_config.mbuf_high_water = | |
15162 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
15163 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
15164 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15165 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
15166 | tp->bufmgr_config.mbuf_high_water = | |
15167 | DEFAULT_MB_HIGH_WATER_5906; | |
15168 | } | |
fdfec172 MC |
15169 | |
15170 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15171 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
15172 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15173 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
15174 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15175 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
15176 | } else { | |
15177 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
15178 | DEFAULT_MB_RDMA_LOW_WATER; | |
15179 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15180 | DEFAULT_MB_MACRX_LOW_WATER; | |
15181 | tp->bufmgr_config.mbuf_high_water = | |
15182 | DEFAULT_MB_HIGH_WATER; | |
15183 | ||
15184 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15185 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
15186 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15187 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
15188 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15189 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
15190 | } | |
1da177e4 LT |
15191 | |
15192 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
15193 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
15194 | } | |
15195 | ||
15196 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
15197 | { | |
79eb6904 MC |
15198 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
15199 | case TG3_PHY_ID_BCM5400: return "5400"; | |
15200 | case TG3_PHY_ID_BCM5401: return "5401"; | |
15201 | case TG3_PHY_ID_BCM5411: return "5411"; | |
15202 | case TG3_PHY_ID_BCM5701: return "5701"; | |
15203 | case TG3_PHY_ID_BCM5703: return "5703"; | |
15204 | case TG3_PHY_ID_BCM5704: return "5704"; | |
15205 | case TG3_PHY_ID_BCM5705: return "5705"; | |
15206 | case TG3_PHY_ID_BCM5750: return "5750"; | |
15207 | case TG3_PHY_ID_BCM5752: return "5752"; | |
15208 | case TG3_PHY_ID_BCM5714: return "5714"; | |
15209 | case TG3_PHY_ID_BCM5780: return "5780"; | |
15210 | case TG3_PHY_ID_BCM5755: return "5755"; | |
15211 | case TG3_PHY_ID_BCM5787: return "5787"; | |
15212 | case TG3_PHY_ID_BCM5784: return "5784"; | |
15213 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
15214 | case TG3_PHY_ID_BCM5906: return "5906"; | |
15215 | case TG3_PHY_ID_BCM5761: return "5761"; | |
15216 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
15217 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
15218 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 15219 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
6418f2c1 | 15220 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
79eb6904 | 15221 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
15222 | case 0: return "serdes"; |
15223 | default: return "unknown"; | |
855e1111 | 15224 | } |
1da177e4 LT |
15225 | } |
15226 | ||
f9804ddb MC |
15227 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
15228 | { | |
63c3a66f | 15229 | if (tg3_flag(tp, PCI_EXPRESS)) { |
f9804ddb MC |
15230 | strcpy(str, "PCI Express"); |
15231 | return str; | |
63c3a66f | 15232 | } else if (tg3_flag(tp, PCIX_MODE)) { |
f9804ddb MC |
15233 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; |
15234 | ||
15235 | strcpy(str, "PCIX:"); | |
15236 | ||
15237 | if ((clock_ctrl == 7) || | |
15238 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
15239 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
15240 | strcat(str, "133MHz"); | |
15241 | else if (clock_ctrl == 0) | |
15242 | strcat(str, "33MHz"); | |
15243 | else if (clock_ctrl == 2) | |
15244 | strcat(str, "50MHz"); | |
15245 | else if (clock_ctrl == 4) | |
15246 | strcat(str, "66MHz"); | |
15247 | else if (clock_ctrl == 6) | |
15248 | strcat(str, "100MHz"); | |
f9804ddb MC |
15249 | } else { |
15250 | strcpy(str, "PCI:"); | |
63c3a66f | 15251 | if (tg3_flag(tp, PCI_HIGH_SPEED)) |
f9804ddb MC |
15252 | strcat(str, "66MHz"); |
15253 | else | |
15254 | strcat(str, "33MHz"); | |
15255 | } | |
63c3a66f | 15256 | if (tg3_flag(tp, PCI_32BIT)) |
f9804ddb MC |
15257 | strcat(str, ":32-bit"); |
15258 | else | |
15259 | strcat(str, ":64-bit"); | |
15260 | return str; | |
15261 | } | |
15262 | ||
8c2dc7e1 | 15263 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
15264 | { |
15265 | struct pci_dev *peer; | |
15266 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
15267 | ||
15268 | for (func = 0; func < 8; func++) { | |
15269 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
15270 | if (peer && peer != tp->pdev) | |
15271 | break; | |
15272 | pci_dev_put(peer); | |
15273 | } | |
16fe9d74 MC |
15274 | /* 5704 can be configured in single-port mode, set peer to |
15275 | * tp->pdev in that case. | |
15276 | */ | |
15277 | if (!peer) { | |
15278 | peer = tp->pdev; | |
15279 | return peer; | |
15280 | } | |
1da177e4 LT |
15281 | |
15282 | /* | |
15283 | * We don't need to keep the refcount elevated; there's no way | |
15284 | * to remove one half of this device without removing the other | |
15285 | */ | |
15286 | pci_dev_put(peer); | |
15287 | ||
15288 | return peer; | |
15289 | } | |
15290 | ||
15f9850d DM |
15291 | static void __devinit tg3_init_coal(struct tg3 *tp) |
15292 | { | |
15293 | struct ethtool_coalesce *ec = &tp->coal; | |
15294 | ||
15295 | memset(ec, 0, sizeof(*ec)); | |
15296 | ec->cmd = ETHTOOL_GCOALESCE; | |
15297 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
15298 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
15299 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
15300 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
15301 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
15302 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
15303 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
15304 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
15305 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
15306 | ||
15307 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
15308 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
15309 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
15310 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
15311 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
15312 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
15313 | } | |
d244c892 | 15314 | |
63c3a66f | 15315 | if (tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
15316 | ec->rx_coalesce_usecs_irq = 0; |
15317 | ec->tx_coalesce_usecs_irq = 0; | |
15318 | ec->stats_block_coalesce_usecs = 0; | |
15319 | } | |
15f9850d DM |
15320 | } |
15321 | ||
7c7d64b8 SH |
15322 | static const struct net_device_ops tg3_netdev_ops = { |
15323 | .ndo_open = tg3_open, | |
15324 | .ndo_stop = tg3_close, | |
00829823 | 15325 | .ndo_start_xmit = tg3_start_xmit, |
511d2224 | 15326 | .ndo_get_stats64 = tg3_get_stats64, |
00829823 | 15327 | .ndo_validate_addr = eth_validate_addr, |
afc4b13d | 15328 | .ndo_set_rx_mode = tg3_set_rx_mode, |
00829823 SH |
15329 | .ndo_set_mac_address = tg3_set_mac_addr, |
15330 | .ndo_do_ioctl = tg3_ioctl, | |
15331 | .ndo_tx_timeout = tg3_tx_timeout, | |
15332 | .ndo_change_mtu = tg3_change_mtu, | |
dc668910 | 15333 | .ndo_fix_features = tg3_fix_features, |
06c03c02 | 15334 | .ndo_set_features = tg3_set_features, |
00829823 SH |
15335 | #ifdef CONFIG_NET_POLL_CONTROLLER |
15336 | .ndo_poll_controller = tg3_poll_controller, | |
15337 | #endif | |
15338 | }; | |
15339 | ||
1da177e4 LT |
15340 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
15341 | const struct pci_device_id *ent) | |
15342 | { | |
1da177e4 LT |
15343 | struct net_device *dev; |
15344 | struct tg3 *tp; | |
646c9edd MC |
15345 | int i, err, pm_cap; |
15346 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 15347 | char str[40]; |
72f2afb8 | 15348 | u64 dma_mask, persist_dma_mask; |
c8f44aff | 15349 | netdev_features_t features = 0; |
1da177e4 | 15350 | |
05dbe005 | 15351 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
15352 | |
15353 | err = pci_enable_device(pdev); | |
15354 | if (err) { | |
2445e461 | 15355 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
15356 | return err; |
15357 | } | |
15358 | ||
1da177e4 LT |
15359 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
15360 | if (err) { | |
2445e461 | 15361 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
15362 | goto err_out_disable_pdev; |
15363 | } | |
15364 | ||
15365 | pci_set_master(pdev); | |
15366 | ||
15367 | /* Find power-management capability. */ | |
15368 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
15369 | if (pm_cap == 0) { | |
2445e461 MC |
15370 | dev_err(&pdev->dev, |
15371 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
15372 | err = -EIO; |
15373 | goto err_out_free_res; | |
15374 | } | |
15375 | ||
16821285 MC |
15376 | err = pci_set_power_state(pdev, PCI_D0); |
15377 | if (err) { | |
15378 | dev_err(&pdev->dev, "Transition to D0 failed, aborting\n"); | |
15379 | goto err_out_free_res; | |
15380 | } | |
15381 | ||
fe5f5787 | 15382 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 15383 | if (!dev) { |
2445e461 | 15384 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1da177e4 | 15385 | err = -ENOMEM; |
16821285 | 15386 | goto err_out_power_down; |
1da177e4 LT |
15387 | } |
15388 | ||
1da177e4 LT |
15389 | SET_NETDEV_DEV(dev, &pdev->dev); |
15390 | ||
1da177e4 LT |
15391 | tp = netdev_priv(dev); |
15392 | tp->pdev = pdev; | |
15393 | tp->dev = dev; | |
15394 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
15395 | tp->rx_mode = TG3_DEF_RX_MODE; |
15396 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 15397 | |
1da177e4 LT |
15398 | if (tg3_debug > 0) |
15399 | tp->msg_enable = tg3_debug; | |
15400 | else | |
15401 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
15402 | ||
15403 | /* The word/byte swap controls here control register access byte | |
15404 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
15405 | * setting below. | |
15406 | */ | |
15407 | tp->misc_host_ctrl = | |
15408 | MISC_HOST_CTRL_MASK_PCI_INT | | |
15409 | MISC_HOST_CTRL_WORD_SWAP | | |
15410 | MISC_HOST_CTRL_INDIR_ACCESS | | |
15411 | MISC_HOST_CTRL_PCISTATE_RW; | |
15412 | ||
15413 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
15414 | * on descriptor entries, anything which isn't packet data. | |
15415 | * | |
15416 | * The StrongARM chips on the board (one for tx, one for rx) | |
15417 | * are running in big-endian mode. | |
15418 | */ | |
15419 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
15420 | GRC_MODE_WSWAP_NONFRM_DATA); | |
15421 | #ifdef __BIG_ENDIAN | |
15422 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
15423 | #endif | |
15424 | spin_lock_init(&tp->lock); | |
1da177e4 | 15425 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 15426 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 15427 | |
d5fe488a | 15428 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 15429 | if (!tp->regs) { |
ab96b241 | 15430 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
15431 | err = -ENOMEM; |
15432 | goto err_out_free_dev; | |
15433 | } | |
15434 | ||
c9cab24e MC |
15435 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
15436 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || | |
15437 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || | |
15438 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || | |
15439 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
15440 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
15441 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
15442 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) { | |
15443 | tg3_flag_set(tp, ENABLE_APE); | |
15444 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
15445 | if (!tp->aperegs) { | |
15446 | dev_err(&pdev->dev, | |
15447 | "Cannot map APE registers, aborting\n"); | |
15448 | err = -ENOMEM; | |
15449 | goto err_out_iounmap; | |
15450 | } | |
15451 | } | |
15452 | ||
1da177e4 LT |
15453 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
15454 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 15455 | |
1da177e4 | 15456 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 15457 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
2ffcc981 | 15458 | dev->netdev_ops = &tg3_netdev_ops; |
1da177e4 | 15459 | dev->irq = pdev->irq; |
1da177e4 LT |
15460 | |
15461 | err = tg3_get_invariants(tp); | |
15462 | if (err) { | |
ab96b241 MC |
15463 | dev_err(&pdev->dev, |
15464 | "Problem fetching invariants of chip, aborting\n"); | |
c9cab24e | 15465 | goto err_out_apeunmap; |
1da177e4 LT |
15466 | } |
15467 | ||
4a29cc2e MC |
15468 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
15469 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
15470 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
15471 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
15472 | * do DMA address check in tg3_start_xmit(). | |
15473 | */ | |
63c3a66f | 15474 | if (tg3_flag(tp, IS_5788)) |
284901a9 | 15475 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
63c3a66f | 15476 | else if (tg3_flag(tp, 40BIT_DMA_BUG)) { |
50cf156a | 15477 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 15478 | #ifdef CONFIG_HIGHMEM |
6a35528a | 15479 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 15480 | #endif |
4a29cc2e | 15481 | } else |
6a35528a | 15482 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
15483 | |
15484 | /* Configure DMA attributes. */ | |
284901a9 | 15485 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
15486 | err = pci_set_dma_mask(pdev, dma_mask); |
15487 | if (!err) { | |
0da0606f | 15488 | features |= NETIF_F_HIGHDMA; |
72f2afb8 MC |
15489 | err = pci_set_consistent_dma_mask(pdev, |
15490 | persist_dma_mask); | |
15491 | if (err < 0) { | |
ab96b241 MC |
15492 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
15493 | "DMA for consistent allocations\n"); | |
c9cab24e | 15494 | goto err_out_apeunmap; |
72f2afb8 MC |
15495 | } |
15496 | } | |
15497 | } | |
284901a9 YH |
15498 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
15499 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 15500 | if (err) { |
ab96b241 MC |
15501 | dev_err(&pdev->dev, |
15502 | "No usable DMA configuration, aborting\n"); | |
c9cab24e | 15503 | goto err_out_apeunmap; |
72f2afb8 MC |
15504 | } |
15505 | } | |
15506 | ||
fdfec172 | 15507 | tg3_init_bufmgr_config(tp); |
1da177e4 | 15508 | |
0da0606f MC |
15509 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
15510 | ||
15511 | /* 5700 B0 chips do not support checksumming correctly due | |
15512 | * to hardware bugs. | |
15513 | */ | |
15514 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { | |
15515 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
15516 | ||
15517 | if (tg3_flag(tp, 5755_PLUS)) | |
15518 | features |= NETIF_F_IPV6_CSUM; | |
15519 | } | |
15520 | ||
4e3a7aaa MC |
15521 | /* TSO is on by default on chips that support hardware TSO. |
15522 | * Firmware TSO on older chips gives lower performance, so it | |
15523 | * is off by default, but can be enabled using ethtool. | |
15524 | */ | |
63c3a66f JP |
15525 | if ((tg3_flag(tp, HW_TSO_1) || |
15526 | tg3_flag(tp, HW_TSO_2) || | |
15527 | tg3_flag(tp, HW_TSO_3)) && | |
0da0606f MC |
15528 | (features & NETIF_F_IP_CSUM)) |
15529 | features |= NETIF_F_TSO; | |
63c3a66f | 15530 | if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { |
0da0606f MC |
15531 | if (features & NETIF_F_IPV6_CSUM) |
15532 | features |= NETIF_F_TSO6; | |
63c3a66f | 15533 | if (tg3_flag(tp, HW_TSO_3) || |
e849cdc3 | 15534 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c MC |
15535 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
15536 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
63c3a66f | 15537 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
dc668910 | 15538 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
0da0606f | 15539 | features |= NETIF_F_TSO_ECN; |
b0026624 | 15540 | } |
1da177e4 | 15541 | |
d542fe27 MC |
15542 | dev->features |= features; |
15543 | dev->vlan_features |= features; | |
15544 | ||
06c03c02 MB |
15545 | /* |
15546 | * Add loopback capability only for a subset of devices that support | |
15547 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY | |
15548 | * loopback for the remaining devices. | |
15549 | */ | |
15550 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
15551 | !tg3_flag(tp, CPMU_PRESENT)) | |
15552 | /* Add the loopback capability */ | |
0da0606f MC |
15553 | features |= NETIF_F_LOOPBACK; |
15554 | ||
0da0606f | 15555 | dev->hw_features |= features; |
06c03c02 | 15556 | |
1da177e4 | 15557 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
63c3a66f | 15558 | !tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 | 15559 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { |
63c3a66f | 15560 | tg3_flag_set(tp, MAX_RXPEND_64); |
1da177e4 LT |
15561 | tp->rx_pending = 63; |
15562 | } | |
15563 | ||
1da177e4 LT |
15564 | err = tg3_get_device_address(tp); |
15565 | if (err) { | |
ab96b241 MC |
15566 | dev_err(&pdev->dev, |
15567 | "Could not obtain valid ethernet address, aborting\n"); | |
c9cab24e | 15568 | goto err_out_apeunmap; |
c88864df MC |
15569 | } |
15570 | ||
1da177e4 LT |
15571 | /* |
15572 | * Reset chip in case UNDI or EFI driver did not shutdown | |
15573 | * DMA self test will enable WDMAC and we'll see (spurious) | |
15574 | * pending DMA on the PCI bus at that point. | |
15575 | */ | |
15576 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
15577 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 15578 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 15579 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
15580 | } |
15581 | ||
15582 | err = tg3_test_dma(tp); | |
15583 | if (err) { | |
ab96b241 | 15584 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 15585 | goto err_out_apeunmap; |
1da177e4 LT |
15586 | } |
15587 | ||
78f90dcf MC |
15588 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
15589 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
15590 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 15591 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
15592 | struct tg3_napi *tnapi = &tp->napi[i]; |
15593 | ||
15594 | tnapi->tp = tp; | |
15595 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
15596 | ||
15597 | tnapi->int_mbox = intmbx; | |
93a700a9 | 15598 | if (i <= 4) |
78f90dcf MC |
15599 | intmbx += 0x8; |
15600 | else | |
15601 | intmbx += 0x4; | |
15602 | ||
15603 | tnapi->consmbox = rcvmbx; | |
15604 | tnapi->prodmbox = sndmbx; | |
15605 | ||
66cfd1bd | 15606 | if (i) |
78f90dcf | 15607 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 15608 | else |
78f90dcf | 15609 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf | 15610 | |
63c3a66f | 15611 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
78f90dcf MC |
15612 | break; |
15613 | ||
15614 | /* | |
15615 | * If we support MSIX, we'll be using RSS. If we're using | |
15616 | * RSS, the first vector only handles link interrupts and the | |
15617 | * remaining vectors handle rx and tx interrupts. Reuse the | |
15618 | * mailbox values for the next iteration. The values we setup | |
15619 | * above are still useful for the single vectored mode. | |
15620 | */ | |
15621 | if (!i) | |
15622 | continue; | |
15623 | ||
15624 | rcvmbx += 0x8; | |
15625 | ||
15626 | if (sndmbx & 0x4) | |
15627 | sndmbx -= 0x4; | |
15628 | else | |
15629 | sndmbx += 0xc; | |
15630 | } | |
15631 | ||
15f9850d DM |
15632 | tg3_init_coal(tp); |
15633 | ||
c49a1561 MC |
15634 | pci_set_drvdata(pdev, dev); |
15635 | ||
cd0d7228 MC |
15636 | if (tg3_flag(tp, 5717_PLUS)) { |
15637 | /* Resume a low-power mode */ | |
15638 | tg3_frob_aux_power(tp, false); | |
15639 | } | |
15640 | ||
1da177e4 LT |
15641 | err = register_netdev(dev); |
15642 | if (err) { | |
ab96b241 | 15643 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 15644 | goto err_out_apeunmap; |
1da177e4 LT |
15645 | } |
15646 | ||
05dbe005 JP |
15647 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
15648 | tp->board_part_number, | |
15649 | tp->pci_chip_rev_id, | |
15650 | tg3_bus_string(tp, str), | |
15651 | dev->dev_addr); | |
1da177e4 | 15652 | |
f07e9af3 | 15653 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
15654 | struct phy_device *phydev; |
15655 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
15656 | netdev_info(dev, |
15657 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 15658 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
15659 | } else { |
15660 | char *ethtype; | |
15661 | ||
15662 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
15663 | ethtype = "10/100Base-TX"; | |
15664 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
15665 | ethtype = "1000Base-SX"; | |
15666 | else | |
15667 | ethtype = "10/100/1000Base-T"; | |
15668 | ||
5129c3a3 | 15669 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
47007831 MC |
15670 | "(WireSpeed[%d], EEE[%d])\n", |
15671 | tg3_phy_string(tp), ethtype, | |
15672 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, | |
15673 | (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); | |
f07e9af3 | 15674 | } |
05dbe005 JP |
15675 | |
15676 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
dc668910 | 15677 | (dev->features & NETIF_F_RXCSUM) != 0, |
63c3a66f | 15678 | tg3_flag(tp, USE_LINKCHG_REG) != 0, |
f07e9af3 | 15679 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
63c3a66f JP |
15680 | tg3_flag(tp, ENABLE_ASF) != 0, |
15681 | tg3_flag(tp, TSO_CAPABLE) != 0); | |
05dbe005 JP |
15682 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
15683 | tp->dma_rwctrl, | |
15684 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
15685 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 | 15686 | |
b45aa2f6 MC |
15687 | pci_save_state(pdev); |
15688 | ||
1da177e4 LT |
15689 | return 0; |
15690 | ||
0d3031d9 MC |
15691 | err_out_apeunmap: |
15692 | if (tp->aperegs) { | |
15693 | iounmap(tp->aperegs); | |
15694 | tp->aperegs = NULL; | |
15695 | } | |
15696 | ||
1da177e4 | 15697 | err_out_iounmap: |
6892914f MC |
15698 | if (tp->regs) { |
15699 | iounmap(tp->regs); | |
22abe310 | 15700 | tp->regs = NULL; |
6892914f | 15701 | } |
1da177e4 LT |
15702 | |
15703 | err_out_free_dev: | |
15704 | free_netdev(dev); | |
15705 | ||
16821285 MC |
15706 | err_out_power_down: |
15707 | pci_set_power_state(pdev, PCI_D3hot); | |
15708 | ||
1da177e4 LT |
15709 | err_out_free_res: |
15710 | pci_release_regions(pdev); | |
15711 | ||
15712 | err_out_disable_pdev: | |
15713 | pci_disable_device(pdev); | |
15714 | pci_set_drvdata(pdev, NULL); | |
15715 | return err; | |
15716 | } | |
15717 | ||
15718 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
15719 | { | |
15720 | struct net_device *dev = pci_get_drvdata(pdev); | |
15721 | ||
15722 | if (dev) { | |
15723 | struct tg3 *tp = netdev_priv(dev); | |
15724 | ||
077f849d JSR |
15725 | if (tp->fw) |
15726 | release_firmware(tp->fw); | |
15727 | ||
db219973 | 15728 | tg3_reset_task_cancel(tp); |
158d7abd | 15729 | |
e730c823 | 15730 | if (tg3_flag(tp, USE_PHYLIB)) { |
b02fd9e3 | 15731 | tg3_phy_fini(tp); |
158d7abd | 15732 | tg3_mdio_fini(tp); |
b02fd9e3 | 15733 | } |
158d7abd | 15734 | |
1da177e4 | 15735 | unregister_netdev(dev); |
0d3031d9 MC |
15736 | if (tp->aperegs) { |
15737 | iounmap(tp->aperegs); | |
15738 | tp->aperegs = NULL; | |
15739 | } | |
6892914f MC |
15740 | if (tp->regs) { |
15741 | iounmap(tp->regs); | |
22abe310 | 15742 | tp->regs = NULL; |
6892914f | 15743 | } |
1da177e4 LT |
15744 | free_netdev(dev); |
15745 | pci_release_regions(pdev); | |
15746 | pci_disable_device(pdev); | |
15747 | pci_set_drvdata(pdev, NULL); | |
15748 | } | |
15749 | } | |
15750 | ||
aa6027ca | 15751 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 15752 | static int tg3_suspend(struct device *device) |
1da177e4 | 15753 | { |
c866b7ea | 15754 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15755 | struct net_device *dev = pci_get_drvdata(pdev); |
15756 | struct tg3 *tp = netdev_priv(dev); | |
15757 | int err; | |
15758 | ||
15759 | if (!netif_running(dev)) | |
15760 | return 0; | |
15761 | ||
db219973 | 15762 | tg3_reset_task_cancel(tp); |
b02fd9e3 | 15763 | tg3_phy_stop(tp); |
1da177e4 LT |
15764 | tg3_netif_stop(tp); |
15765 | ||
15766 | del_timer_sync(&tp->timer); | |
15767 | ||
f47c11ee | 15768 | tg3_full_lock(tp, 1); |
1da177e4 | 15769 | tg3_disable_ints(tp); |
f47c11ee | 15770 | tg3_full_unlock(tp); |
1da177e4 LT |
15771 | |
15772 | netif_device_detach(dev); | |
15773 | ||
f47c11ee | 15774 | tg3_full_lock(tp, 0); |
944d980e | 15775 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
63c3a66f | 15776 | tg3_flag_clear(tp, INIT_COMPLETE); |
f47c11ee | 15777 | tg3_full_unlock(tp); |
1da177e4 | 15778 | |
c866b7ea | 15779 | err = tg3_power_down_prepare(tp); |
1da177e4 | 15780 | if (err) { |
b02fd9e3 MC |
15781 | int err2; |
15782 | ||
f47c11ee | 15783 | tg3_full_lock(tp, 0); |
1da177e4 | 15784 | |
63c3a66f | 15785 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
15786 | err2 = tg3_restart_hw(tp, 1); |
15787 | if (err2) | |
b9ec6c1b | 15788 | goto out; |
1da177e4 LT |
15789 | |
15790 | tp->timer.expires = jiffies + tp->timer_offset; | |
15791 | add_timer(&tp->timer); | |
15792 | ||
15793 | netif_device_attach(dev); | |
15794 | tg3_netif_start(tp); | |
15795 | ||
b9ec6c1b | 15796 | out: |
f47c11ee | 15797 | tg3_full_unlock(tp); |
b02fd9e3 MC |
15798 | |
15799 | if (!err2) | |
15800 | tg3_phy_start(tp); | |
1da177e4 LT |
15801 | } |
15802 | ||
15803 | return err; | |
15804 | } | |
15805 | ||
c866b7ea | 15806 | static int tg3_resume(struct device *device) |
1da177e4 | 15807 | { |
c866b7ea | 15808 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15809 | struct net_device *dev = pci_get_drvdata(pdev); |
15810 | struct tg3 *tp = netdev_priv(dev); | |
15811 | int err; | |
15812 | ||
15813 | if (!netif_running(dev)) | |
15814 | return 0; | |
15815 | ||
1da177e4 LT |
15816 | netif_device_attach(dev); |
15817 | ||
f47c11ee | 15818 | tg3_full_lock(tp, 0); |
1da177e4 | 15819 | |
63c3a66f | 15820 | tg3_flag_set(tp, INIT_COMPLETE); |
b9ec6c1b MC |
15821 | err = tg3_restart_hw(tp, 1); |
15822 | if (err) | |
15823 | goto out; | |
1da177e4 LT |
15824 | |
15825 | tp->timer.expires = jiffies + tp->timer_offset; | |
15826 | add_timer(&tp->timer); | |
15827 | ||
1da177e4 LT |
15828 | tg3_netif_start(tp); |
15829 | ||
b9ec6c1b | 15830 | out: |
f47c11ee | 15831 | tg3_full_unlock(tp); |
1da177e4 | 15832 | |
b02fd9e3 MC |
15833 | if (!err) |
15834 | tg3_phy_start(tp); | |
15835 | ||
b9ec6c1b | 15836 | return err; |
1da177e4 LT |
15837 | } |
15838 | ||
c866b7ea | 15839 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
15840 | #define TG3_PM_OPS (&tg3_pm_ops) |
15841 | ||
15842 | #else | |
15843 | ||
15844 | #define TG3_PM_OPS NULL | |
15845 | ||
15846 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 15847 | |
b45aa2f6 MC |
15848 | /** |
15849 | * tg3_io_error_detected - called when PCI error is detected | |
15850 | * @pdev: Pointer to PCI device | |
15851 | * @state: The current pci connection state | |
15852 | * | |
15853 | * This function is called after a PCI bus error affecting | |
15854 | * this device has been detected. | |
15855 | */ | |
15856 | static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |
15857 | pci_channel_state_t state) | |
15858 | { | |
15859 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15860 | struct tg3 *tp = netdev_priv(netdev); | |
15861 | pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET; | |
15862 | ||
15863 | netdev_info(netdev, "PCI I/O error detected\n"); | |
15864 | ||
15865 | rtnl_lock(); | |
15866 | ||
15867 | if (!netif_running(netdev)) | |
15868 | goto done; | |
15869 | ||
15870 | tg3_phy_stop(tp); | |
15871 | ||
15872 | tg3_netif_stop(tp); | |
15873 | ||
15874 | del_timer_sync(&tp->timer); | |
b45aa2f6 MC |
15875 | |
15876 | /* Want to make sure that the reset task doesn't run */ | |
db219973 | 15877 | tg3_reset_task_cancel(tp); |
63c3a66f | 15878 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); |
b45aa2f6 MC |
15879 | |
15880 | netif_device_detach(netdev); | |
15881 | ||
15882 | /* Clean up software state, even if MMIO is blocked */ | |
15883 | tg3_full_lock(tp, 0); | |
15884 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
15885 | tg3_full_unlock(tp); | |
15886 | ||
15887 | done: | |
15888 | if (state == pci_channel_io_perm_failure) | |
15889 | err = PCI_ERS_RESULT_DISCONNECT; | |
15890 | else | |
15891 | pci_disable_device(pdev); | |
15892 | ||
15893 | rtnl_unlock(); | |
15894 | ||
15895 | return err; | |
15896 | } | |
15897 | ||
15898 | /** | |
15899 | * tg3_io_slot_reset - called after the pci bus has been reset. | |
15900 | * @pdev: Pointer to PCI device | |
15901 | * | |
15902 | * Restart the card from scratch, as if from a cold-boot. | |
15903 | * At this point, the card has exprienced a hard reset, | |
15904 | * followed by fixups by BIOS, and has its config space | |
15905 | * set up identically to what it was at cold boot. | |
15906 | */ | |
15907 | static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) | |
15908 | { | |
15909 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15910 | struct tg3 *tp = netdev_priv(netdev); | |
15911 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; | |
15912 | int err; | |
15913 | ||
15914 | rtnl_lock(); | |
15915 | ||
15916 | if (pci_enable_device(pdev)) { | |
15917 | netdev_err(netdev, "Cannot re-enable PCI device after reset.\n"); | |
15918 | goto done; | |
15919 | } | |
15920 | ||
15921 | pci_set_master(pdev); | |
15922 | pci_restore_state(pdev); | |
15923 | pci_save_state(pdev); | |
15924 | ||
15925 | if (!netif_running(netdev)) { | |
15926 | rc = PCI_ERS_RESULT_RECOVERED; | |
15927 | goto done; | |
15928 | } | |
15929 | ||
15930 | err = tg3_power_up(tp); | |
bed9829f | 15931 | if (err) |
b45aa2f6 | 15932 | goto done; |
b45aa2f6 MC |
15933 | |
15934 | rc = PCI_ERS_RESULT_RECOVERED; | |
15935 | ||
15936 | done: | |
15937 | rtnl_unlock(); | |
15938 | ||
15939 | return rc; | |
15940 | } | |
15941 | ||
15942 | /** | |
15943 | * tg3_io_resume - called when traffic can start flowing again. | |
15944 | * @pdev: Pointer to PCI device | |
15945 | * | |
15946 | * This callback is called when the error recovery driver tells | |
15947 | * us that its OK to resume normal operation. | |
15948 | */ | |
15949 | static void tg3_io_resume(struct pci_dev *pdev) | |
15950 | { | |
15951 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15952 | struct tg3 *tp = netdev_priv(netdev); | |
15953 | int err; | |
15954 | ||
15955 | rtnl_lock(); | |
15956 | ||
15957 | if (!netif_running(netdev)) | |
15958 | goto done; | |
15959 | ||
15960 | tg3_full_lock(tp, 0); | |
63c3a66f | 15961 | tg3_flag_set(tp, INIT_COMPLETE); |
b45aa2f6 MC |
15962 | err = tg3_restart_hw(tp, 1); |
15963 | tg3_full_unlock(tp); | |
15964 | if (err) { | |
15965 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); | |
15966 | goto done; | |
15967 | } | |
15968 | ||
15969 | netif_device_attach(netdev); | |
15970 | ||
15971 | tp->timer.expires = jiffies + tp->timer_offset; | |
15972 | add_timer(&tp->timer); | |
15973 | ||
15974 | tg3_netif_start(tp); | |
15975 | ||
15976 | tg3_phy_start(tp); | |
15977 | ||
15978 | done: | |
15979 | rtnl_unlock(); | |
15980 | } | |
15981 | ||
15982 | static struct pci_error_handlers tg3_err_handler = { | |
15983 | .error_detected = tg3_io_error_detected, | |
15984 | .slot_reset = tg3_io_slot_reset, | |
15985 | .resume = tg3_io_resume | |
15986 | }; | |
15987 | ||
1da177e4 LT |
15988 | static struct pci_driver tg3_driver = { |
15989 | .name = DRV_MODULE_NAME, | |
15990 | .id_table = tg3_pci_tbl, | |
15991 | .probe = tg3_init_one, | |
15992 | .remove = __devexit_p(tg3_remove_one), | |
b45aa2f6 | 15993 | .err_handler = &tg3_err_handler, |
aa6027ca | 15994 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
15995 | }; |
15996 | ||
15997 | static int __init tg3_init(void) | |
15998 | { | |
29917620 | 15999 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
16000 | } |
16001 | ||
16002 | static void __exit tg3_cleanup(void) | |
16003 | { | |
16004 | pci_unregister_driver(&tg3_driver); | |
16005 | } | |
16006 | ||
16007 | module_init(tg3_init); | |
16008 | module_exit(tg3_cleanup); |