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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
9e056c03 | 7 | * Copyright (C) 2005-2012 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 | 28 | #include <linux/init.h> |
a6b7a407 | 29 | #include <linux/interrupt.h> |
1da177e4 LT |
30 | #include <linux/ioport.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/ethtool.h> | |
3110f5f5 | 36 | #include <linux/mdio.h> |
1da177e4 | 37 | #include <linux/mii.h> |
158d7abd | 38 | #include <linux/phy.h> |
a9daf367 | 39 | #include <linux/brcmphy.h> |
1da177e4 LT |
40 | #include <linux/if_vlan.h> |
41 | #include <linux/ip.h> | |
42 | #include <linux/tcp.h> | |
43 | #include <linux/workqueue.h> | |
61487480 | 44 | #include <linux/prefetch.h> |
f9a5f7d3 | 45 | #include <linux/dma-mapping.h> |
077f849d | 46 | #include <linux/firmware.h> |
aed93e0b MC |
47 | #include <linux/hwmon.h> |
48 | #include <linux/hwmon-sysfs.h> | |
1da177e4 LT |
49 | |
50 | #include <net/checksum.h> | |
c9bdd4b5 | 51 | #include <net/ip.h> |
1da177e4 | 52 | |
27fd9de8 | 53 | #include <linux/io.h> |
1da177e4 | 54 | #include <asm/byteorder.h> |
27fd9de8 | 55 | #include <linux/uaccess.h> |
1da177e4 | 56 | |
49b6e95f | 57 | #ifdef CONFIG_SPARC |
1da177e4 | 58 | #include <asm/idprom.h> |
49b6e95f | 59 | #include <asm/prom.h> |
1da177e4 LT |
60 | #endif |
61 | ||
63532394 MC |
62 | #define BAR_0 0 |
63 | #define BAR_2 2 | |
64 | ||
1da177e4 LT |
65 | #include "tg3.h" |
66 | ||
63c3a66f JP |
67 | /* Functions & macros to verify TG3_FLAGS types */ |
68 | ||
69 | static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) | |
70 | { | |
71 | return test_bit(flag, bits); | |
72 | } | |
73 | ||
74 | static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) | |
75 | { | |
76 | set_bit(flag, bits); | |
77 | } | |
78 | ||
79 | static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) | |
80 | { | |
81 | clear_bit(flag, bits); | |
82 | } | |
83 | ||
84 | #define tg3_flag(tp, flag) \ | |
85 | _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) | |
86 | #define tg3_flag_set(tp, flag) \ | |
87 | _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) | |
88 | #define tg3_flag_clear(tp, flag) \ | |
89 | _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) | |
90 | ||
1da177e4 | 91 | #define DRV_MODULE_NAME "tg3" |
6867c843 | 92 | #define TG3_MAJ_NUM 3 |
bd473da3 | 93 | #define TG3_MIN_NUM 126 |
6867c843 MC |
94 | #define DRV_MODULE_VERSION \ |
95 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
bd473da3 | 96 | #define DRV_MODULE_RELDATE "November 05, 2012" |
1da177e4 | 97 | |
fd6d3f0e MC |
98 | #define RESET_KIND_SHUTDOWN 0 |
99 | #define RESET_KIND_INIT 1 | |
100 | #define RESET_KIND_SUSPEND 2 | |
101 | ||
1da177e4 LT |
102 | #define TG3_DEF_RX_MODE 0 |
103 | #define TG3_DEF_TX_MODE 0 | |
104 | #define TG3_DEF_MSG_ENABLE \ | |
105 | (NETIF_MSG_DRV | \ | |
106 | NETIF_MSG_PROBE | \ | |
107 | NETIF_MSG_LINK | \ | |
108 | NETIF_MSG_TIMER | \ | |
109 | NETIF_MSG_IFDOWN | \ | |
110 | NETIF_MSG_IFUP | \ | |
111 | NETIF_MSG_RX_ERR | \ | |
112 | NETIF_MSG_TX_ERR) | |
113 | ||
520b2756 MC |
114 | #define TG3_GRC_LCLCTL_PWRSW_DELAY 100 |
115 | ||
1da177e4 LT |
116 | /* length of time before we decide the hardware is borked, |
117 | * and dev->tx_timeout() should be called to fix the problem | |
118 | */ | |
63c3a66f | 119 | |
1da177e4 LT |
120 | #define TG3_TX_TIMEOUT (5 * HZ) |
121 | ||
122 | /* hardware minimum and maximum for a single frame's data payload */ | |
123 | #define TG3_MIN_MTU 60 | |
124 | #define TG3_MAX_MTU(tp) \ | |
63c3a66f | 125 | (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
126 | |
127 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
128 | * You can't change the ring sizes, but you can change where you place | |
129 | * them in the NIC onboard memory. | |
130 | */ | |
7cb32cf2 | 131 | #define TG3_RX_STD_RING_SIZE(tp) \ |
63c3a66f | 132 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 133 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) |
1da177e4 | 134 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 135 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
63c3a66f | 136 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
de9f5230 | 137 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) |
1da177e4 LT |
138 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
139 | ||
140 | /* Do not place this n-ring entries value into the tp struct itself, | |
141 | * we really want to expose these constants to GCC so that modulo et | |
142 | * al. operations are done with shifts and masks instead of with | |
143 | * hw multiply/modulo instructions. Another solution would be to | |
144 | * replace things like '% foo' with '& (foo - 1)'. | |
145 | */ | |
1da177e4 LT |
146 | |
147 | #define TG3_TX_RING_SIZE 512 | |
148 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
149 | ||
2c49a44d MC |
150 | #define TG3_RX_STD_RING_BYTES(tp) \ |
151 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
152 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
153 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
154 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 155 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
156 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
157 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
158 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
159 | ||
287be12e MC |
160 | #define TG3_DMA_BYTE_ENAB 64 |
161 | ||
162 | #define TG3_RX_STD_DMA_SZ 1536 | |
163 | #define TG3_RX_JMB_DMA_SZ 9046 | |
164 | ||
165 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
166 | ||
167 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
168 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 169 | |
2c49a44d MC |
170 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
171 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 172 | |
2c49a44d MC |
173 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
174 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 175 | |
d2757fc4 MC |
176 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
177 | * that are at least dword aligned when used in PCIX mode. The driver | |
178 | * works around this bug by double copying the packet. This workaround | |
179 | * is built into the normal double copy length check for efficiency. | |
180 | * | |
181 | * However, the double copy is only necessary on those architectures | |
182 | * where unaligned memory accesses are inefficient. For those architectures | |
183 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
184 | * the 5701 in the normal rx path. Doing so saves a device structure | |
185 | * dereference by hardcoding the double copy threshold in place. | |
186 | */ | |
187 | #define TG3_RX_COPY_THRESHOLD 256 | |
188 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
189 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
190 | #else | |
191 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
192 | #endif | |
193 | ||
81389f57 MC |
194 | #if (NET_IP_ALIGN != 0) |
195 | #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) | |
196 | #else | |
9205fd9c | 197 | #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) |
81389f57 MC |
198 | #endif |
199 | ||
1da177e4 | 200 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 201 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
55086ad9 | 202 | #define TG3_TX_BD_DMA_MAX_2K 2048 |
a4cb428d | 203 | #define TG3_TX_BD_DMA_MAX_4K 4096 |
1da177e4 | 204 | |
ad829268 MC |
205 | #define TG3_RAW_IP_ALIGN 2 |
206 | ||
c6cdf436 | 207 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
21f7638e | 208 | #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2) |
c6cdf436 | 209 | |
077f849d JSR |
210 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
211 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
212 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
213 | ||
1da177e4 | 214 | static char version[] __devinitdata = |
05dbe005 | 215 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
216 | |
217 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
218 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
219 | MODULE_LICENSE("GPL"); | |
220 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
221 | MODULE_FIRMWARE(FIRMWARE_TG3); |
222 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
223 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
224 | ||
1da177e4 LT |
225 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
226 | module_param(tg3_debug, int, 0); | |
227 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
228 | ||
3d567e0e NNS |
229 | #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001 |
230 | #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002 | |
231 | ||
a3aa1884 | 232 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
3d567e0e NNS |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901), |
252 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY | | |
253 | TG3_DRV_DATA_FLAG_5705_10_100}, | |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2), | |
255 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY | | |
256 | TG3_DRV_DATA_FLAG_5705_10_100}, | |
13185217 | 257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, |
3d567e0e NNS |
258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F), |
259 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY | | |
260 | TG3_DRV_DATA_FLAG_5705_10_100}, | |
13185217 | 261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 | 264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
3d567e0e NNS |
265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F), |
266 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
13185217 HK |
267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, |
268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
269 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
3d567e0e NNS |
271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F), |
272 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
13185217 HK |
273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, |
274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
275 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
276 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 277 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
278 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
279 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
3d567e0e NNS |
280 | {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M, |
281 | PCI_VENDOR_ID_LENOVO, | |
282 | TG3PCI_SUBDEVICE_ID_LENOVO_5787M), | |
283 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
13185217 | 284 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, |
3d567e0e NNS |
285 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F), |
286 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
13185217 HK |
287 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
288 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
289 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
290 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
291 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
292 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
293 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
294 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
295 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
296 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
297 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 298 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
299 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
300 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
301 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
302 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
303 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
304 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
3d567e0e NNS |
305 | {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780, |
306 | PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A), | |
307 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
308 | {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780, | |
309 | PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B), | |
310 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
321d32a0 MC |
311 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
312 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
3d567e0e NNS |
313 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790), |
314 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
5e7ccf20 | 315 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 | 316 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
79d49695 | 317 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)}, |
5001e2f6 | 318 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, |
b0f75221 MC |
319 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
320 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
321 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
322 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
3d567e0e NNS |
323 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791), |
324 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
325 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795), | |
326 | .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY}, | |
302b500b | 327 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
ba1f3c76 | 328 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
02eca3f5 | 329 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)}, |
13185217 HK |
330 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
331 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
332 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
333 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
334 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
335 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
336 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
1dcb14d9 | 337 | {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */ |
13185217 | 338 | {} |
1da177e4 LT |
339 | }; |
340 | ||
341 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
342 | ||
50da859d | 343 | static const struct { |
1da177e4 | 344 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 345 | } ethtool_stats_keys[] = { |
1da177e4 LT |
346 | { "rx_octets" }, |
347 | { "rx_fragments" }, | |
348 | { "rx_ucast_packets" }, | |
349 | { "rx_mcast_packets" }, | |
350 | { "rx_bcast_packets" }, | |
351 | { "rx_fcs_errors" }, | |
352 | { "rx_align_errors" }, | |
353 | { "rx_xon_pause_rcvd" }, | |
354 | { "rx_xoff_pause_rcvd" }, | |
355 | { "rx_mac_ctrl_rcvd" }, | |
356 | { "rx_xoff_entered" }, | |
357 | { "rx_frame_too_long_errors" }, | |
358 | { "rx_jabbers" }, | |
359 | { "rx_undersize_packets" }, | |
360 | { "rx_in_length_errors" }, | |
361 | { "rx_out_length_errors" }, | |
362 | { "rx_64_or_less_octet_packets" }, | |
363 | { "rx_65_to_127_octet_packets" }, | |
364 | { "rx_128_to_255_octet_packets" }, | |
365 | { "rx_256_to_511_octet_packets" }, | |
366 | { "rx_512_to_1023_octet_packets" }, | |
367 | { "rx_1024_to_1522_octet_packets" }, | |
368 | { "rx_1523_to_2047_octet_packets" }, | |
369 | { "rx_2048_to_4095_octet_packets" }, | |
370 | { "rx_4096_to_8191_octet_packets" }, | |
371 | { "rx_8192_to_9022_octet_packets" }, | |
372 | ||
373 | { "tx_octets" }, | |
374 | { "tx_collisions" }, | |
375 | ||
376 | { "tx_xon_sent" }, | |
377 | { "tx_xoff_sent" }, | |
378 | { "tx_flow_control" }, | |
379 | { "tx_mac_errors" }, | |
380 | { "tx_single_collisions" }, | |
381 | { "tx_mult_collisions" }, | |
382 | { "tx_deferred" }, | |
383 | { "tx_excessive_collisions" }, | |
384 | { "tx_late_collisions" }, | |
385 | { "tx_collide_2times" }, | |
386 | { "tx_collide_3times" }, | |
387 | { "tx_collide_4times" }, | |
388 | { "tx_collide_5times" }, | |
389 | { "tx_collide_6times" }, | |
390 | { "tx_collide_7times" }, | |
391 | { "tx_collide_8times" }, | |
392 | { "tx_collide_9times" }, | |
393 | { "tx_collide_10times" }, | |
394 | { "tx_collide_11times" }, | |
395 | { "tx_collide_12times" }, | |
396 | { "tx_collide_13times" }, | |
397 | { "tx_collide_14times" }, | |
398 | { "tx_collide_15times" }, | |
399 | { "tx_ucast_packets" }, | |
400 | { "tx_mcast_packets" }, | |
401 | { "tx_bcast_packets" }, | |
402 | { "tx_carrier_sense_errors" }, | |
403 | { "tx_discards" }, | |
404 | { "tx_errors" }, | |
405 | ||
406 | { "dma_writeq_full" }, | |
407 | { "dma_write_prioq_full" }, | |
408 | { "rxbds_empty" }, | |
409 | { "rx_discards" }, | |
410 | { "rx_errors" }, | |
411 | { "rx_threshold_hit" }, | |
412 | ||
413 | { "dma_readq_full" }, | |
414 | { "dma_read_prioq_full" }, | |
415 | { "tx_comp_queue_full" }, | |
416 | ||
417 | { "ring_set_send_prod_index" }, | |
418 | { "ring_status_update" }, | |
419 | { "nic_irqs" }, | |
420 | { "nic_avoided_irqs" }, | |
4452d099 MC |
421 | { "nic_tx_threshold_hit" }, |
422 | ||
423 | { "mbuf_lwm_thresh_hit" }, | |
1da177e4 LT |
424 | }; |
425 | ||
48fa55a0 MC |
426 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
427 | ||
428 | ||
50da859d | 429 | static const struct { |
4cafd3f5 | 430 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 431 | } ethtool_test_keys[] = { |
28a45957 MC |
432 | { "nvram test (online) " }, |
433 | { "link test (online) " }, | |
434 | { "register test (offline)" }, | |
435 | { "memory test (offline)" }, | |
436 | { "mac loopback test (offline)" }, | |
437 | { "phy loopback test (offline)" }, | |
941ec90f | 438 | { "ext loopback test (offline)" }, |
28a45957 | 439 | { "interrupt test (offline)" }, |
4cafd3f5 MC |
440 | }; |
441 | ||
48fa55a0 MC |
442 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
443 | ||
444 | ||
b401e9e2 MC |
445 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
446 | { | |
447 | writel(val, tp->regs + off); | |
448 | } | |
449 | ||
450 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
451 | { | |
de6f31eb | 452 | return readl(tp->regs + off); |
b401e9e2 MC |
453 | } |
454 | ||
0d3031d9 MC |
455 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
456 | { | |
457 | writel(val, tp->aperegs + off); | |
458 | } | |
459 | ||
460 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
461 | { | |
de6f31eb | 462 | return readl(tp->aperegs + off); |
0d3031d9 MC |
463 | } |
464 | ||
1da177e4 LT |
465 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
466 | { | |
6892914f MC |
467 | unsigned long flags; |
468 | ||
469 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
470 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
471 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 472 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
473 | } |
474 | ||
475 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
476 | { | |
477 | writel(val, tp->regs + off); | |
478 | readl(tp->regs + off); | |
1da177e4 LT |
479 | } |
480 | ||
6892914f | 481 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 482 | { |
6892914f MC |
483 | unsigned long flags; |
484 | u32 val; | |
485 | ||
486 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
487 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
488 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
489 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
490 | return val; | |
491 | } | |
492 | ||
493 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
494 | { | |
495 | unsigned long flags; | |
496 | ||
497 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
498 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
499 | TG3_64BIT_REG_LOW, val); | |
500 | return; | |
501 | } | |
66711e66 | 502 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
503 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
504 | TG3_64BIT_REG_LOW, val); | |
505 | return; | |
1da177e4 | 506 | } |
6892914f MC |
507 | |
508 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
509 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
510 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
511 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
512 | ||
513 | /* In indirect mode when disabling interrupts, we also need | |
514 | * to clear the interrupt bit in the GRC local ctrl register. | |
515 | */ | |
516 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
517 | (val == 0x1)) { | |
518 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
519 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
520 | } | |
521 | } | |
522 | ||
523 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
524 | { | |
525 | unsigned long flags; | |
526 | u32 val; | |
527 | ||
528 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
529 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
530 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
531 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
532 | return val; | |
533 | } | |
534 | ||
b401e9e2 MC |
535 | /* usec_wait specifies the wait time in usec when writing to certain registers |
536 | * where it is unsafe to read back the register without some delay. | |
537 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
538 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
539 | */ | |
540 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 541 | { |
63c3a66f | 542 | if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) |
b401e9e2 MC |
543 | /* Non-posted methods */ |
544 | tp->write32(tp, off, val); | |
545 | else { | |
546 | /* Posted method */ | |
547 | tg3_write32(tp, off, val); | |
548 | if (usec_wait) | |
549 | udelay(usec_wait); | |
550 | tp->read32(tp, off); | |
551 | } | |
552 | /* Wait again after the read for the posted method to guarantee that | |
553 | * the wait time is met. | |
554 | */ | |
555 | if (usec_wait) | |
556 | udelay(usec_wait); | |
1da177e4 LT |
557 | } |
558 | ||
09ee929c MC |
559 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
560 | { | |
561 | tp->write32_mbox(tp, off, val); | |
63c3a66f | 562 | if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) |
6892914f | 563 | tp->read32_mbox(tp, off); |
09ee929c MC |
564 | } |
565 | ||
20094930 | 566 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
567 | { |
568 | void __iomem *mbox = tp->regs + off; | |
569 | writel(val, mbox); | |
63c3a66f | 570 | if (tg3_flag(tp, TXD_MBOX_HWBUG)) |
1da177e4 | 571 | writel(val, mbox); |
63c3a66f | 572 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1da177e4 LT |
573 | readl(mbox); |
574 | } | |
575 | ||
b5d3772c MC |
576 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
577 | { | |
de6f31eb | 578 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
579 | } |
580 | ||
581 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
582 | { | |
583 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
584 | } | |
585 | ||
c6cdf436 | 586 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 587 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
588 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
589 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
590 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 591 | |
c6cdf436 MC |
592 | #define tw32(reg, val) tp->write32(tp, reg, val) |
593 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
594 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
595 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
596 | |
597 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
598 | { | |
6892914f MC |
599 | unsigned long flags; |
600 | ||
6ff6f81d | 601 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
602 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) |
603 | return; | |
604 | ||
6892914f | 605 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 606 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
607 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
608 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 609 | |
bbadf503 MC |
610 | /* Always leave this as zero. */ |
611 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
612 | } else { | |
613 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
614 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 615 | |
bbadf503 MC |
616 | /* Always leave this as zero. */ |
617 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
618 | } | |
619 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
620 | } |
621 | ||
1da177e4 LT |
622 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
623 | { | |
6892914f MC |
624 | unsigned long flags; |
625 | ||
6ff6f81d | 626 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
b5d3772c MC |
627 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { |
628 | *val = 0; | |
629 | return; | |
630 | } | |
631 | ||
6892914f | 632 | spin_lock_irqsave(&tp->indirect_lock, flags); |
63c3a66f | 633 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
bbadf503 MC |
634 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
635 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 636 | |
bbadf503 MC |
637 | /* Always leave this as zero. */ |
638 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
639 | } else { | |
640 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
641 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
642 | ||
643 | /* Always leave this as zero. */ | |
644 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
645 | } | |
6892914f | 646 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
647 | } |
648 | ||
0d3031d9 MC |
649 | static void tg3_ape_lock_init(struct tg3 *tp) |
650 | { | |
651 | int i; | |
6f5c8f83 | 652 | u32 regbase, bit; |
f92d9dc1 MC |
653 | |
654 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
655 | regbase = TG3_APE_LOCK_GRANT; | |
656 | else | |
657 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
658 | |
659 | /* Make sure the driver hasn't any stale locks. */ | |
78f94dc7 MC |
660 | for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) { |
661 | switch (i) { | |
662 | case TG3_APE_LOCK_PHY0: | |
663 | case TG3_APE_LOCK_PHY1: | |
664 | case TG3_APE_LOCK_PHY2: | |
665 | case TG3_APE_LOCK_PHY3: | |
666 | bit = APE_LOCK_GRANT_DRIVER; | |
667 | break; | |
668 | default: | |
669 | if (!tp->pci_fn) | |
670 | bit = APE_LOCK_GRANT_DRIVER; | |
671 | else | |
672 | bit = 1 << tp->pci_fn; | |
673 | } | |
674 | tg3_ape_write32(tp, regbase + 4 * i, bit); | |
6f5c8f83 MC |
675 | } |
676 | ||
0d3031d9 MC |
677 | } |
678 | ||
679 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
680 | { | |
681 | int i, off; | |
682 | int ret = 0; | |
6f5c8f83 | 683 | u32 status, req, gnt, bit; |
0d3031d9 | 684 | |
63c3a66f | 685 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
686 | return 0; |
687 | ||
688 | switch (locknum) { | |
6f5c8f83 MC |
689 | case TG3_APE_LOCK_GPIO: |
690 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
691 | return 0; | |
33f401ae MC |
692 | case TG3_APE_LOCK_GRC: |
693 | case TG3_APE_LOCK_MEM: | |
78f94dc7 MC |
694 | if (!tp->pci_fn) |
695 | bit = APE_LOCK_REQ_DRIVER; | |
696 | else | |
697 | bit = 1 << tp->pci_fn; | |
33f401ae | 698 | break; |
8151ad57 MC |
699 | case TG3_APE_LOCK_PHY0: |
700 | case TG3_APE_LOCK_PHY1: | |
701 | case TG3_APE_LOCK_PHY2: | |
702 | case TG3_APE_LOCK_PHY3: | |
703 | bit = APE_LOCK_REQ_DRIVER; | |
704 | break; | |
33f401ae MC |
705 | default: |
706 | return -EINVAL; | |
0d3031d9 MC |
707 | } |
708 | ||
f92d9dc1 MC |
709 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
710 | req = TG3_APE_LOCK_REQ; | |
711 | gnt = TG3_APE_LOCK_GRANT; | |
712 | } else { | |
713 | req = TG3_APE_PER_LOCK_REQ; | |
714 | gnt = TG3_APE_PER_LOCK_GRANT; | |
715 | } | |
716 | ||
0d3031d9 MC |
717 | off = 4 * locknum; |
718 | ||
6f5c8f83 | 719 | tg3_ape_write32(tp, req + off, bit); |
0d3031d9 MC |
720 | |
721 | /* Wait for up to 1 millisecond to acquire lock. */ | |
722 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 723 | status = tg3_ape_read32(tp, gnt + off); |
6f5c8f83 | 724 | if (status == bit) |
0d3031d9 MC |
725 | break; |
726 | udelay(10); | |
727 | } | |
728 | ||
6f5c8f83 | 729 | if (status != bit) { |
0d3031d9 | 730 | /* Revoke the lock request. */ |
6f5c8f83 | 731 | tg3_ape_write32(tp, gnt + off, bit); |
0d3031d9 MC |
732 | ret = -EBUSY; |
733 | } | |
734 | ||
735 | return ret; | |
736 | } | |
737 | ||
738 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
739 | { | |
6f5c8f83 | 740 | u32 gnt, bit; |
0d3031d9 | 741 | |
63c3a66f | 742 | if (!tg3_flag(tp, ENABLE_APE)) |
0d3031d9 MC |
743 | return; |
744 | ||
745 | switch (locknum) { | |
6f5c8f83 MC |
746 | case TG3_APE_LOCK_GPIO: |
747 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
748 | return; | |
33f401ae MC |
749 | case TG3_APE_LOCK_GRC: |
750 | case TG3_APE_LOCK_MEM: | |
78f94dc7 MC |
751 | if (!tp->pci_fn) |
752 | bit = APE_LOCK_GRANT_DRIVER; | |
753 | else | |
754 | bit = 1 << tp->pci_fn; | |
33f401ae | 755 | break; |
8151ad57 MC |
756 | case TG3_APE_LOCK_PHY0: |
757 | case TG3_APE_LOCK_PHY1: | |
758 | case TG3_APE_LOCK_PHY2: | |
759 | case TG3_APE_LOCK_PHY3: | |
760 | bit = APE_LOCK_GRANT_DRIVER; | |
761 | break; | |
33f401ae MC |
762 | default: |
763 | return; | |
0d3031d9 MC |
764 | } |
765 | ||
f92d9dc1 MC |
766 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
767 | gnt = TG3_APE_LOCK_GRANT; | |
768 | else | |
769 | gnt = TG3_APE_PER_LOCK_GRANT; | |
770 | ||
6f5c8f83 | 771 | tg3_ape_write32(tp, gnt + 4 * locknum, bit); |
0d3031d9 MC |
772 | } |
773 | ||
b65a372b | 774 | static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us) |
fd6d3f0e | 775 | { |
fd6d3f0e MC |
776 | u32 apedata; |
777 | ||
b65a372b MC |
778 | while (timeout_us) { |
779 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
780 | return -EBUSY; | |
781 | ||
782 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
783 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
784 | break; | |
785 | ||
786 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
787 | ||
788 | udelay(10); | |
789 | timeout_us -= (timeout_us > 10) ? 10 : timeout_us; | |
790 | } | |
791 | ||
792 | return timeout_us ? 0 : -EBUSY; | |
793 | } | |
794 | ||
cf8d55ae MC |
795 | static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us) |
796 | { | |
797 | u32 i, apedata; | |
798 | ||
799 | for (i = 0; i < timeout_us / 10; i++) { | |
800 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
801 | ||
802 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
803 | break; | |
804 | ||
805 | udelay(10); | |
806 | } | |
807 | ||
808 | return i == timeout_us / 10; | |
809 | } | |
810 | ||
86449944 MC |
811 | static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, |
812 | u32 len) | |
cf8d55ae MC |
813 | { |
814 | int err; | |
815 | u32 i, bufoff, msgoff, maxlen, apedata; | |
816 | ||
817 | if (!tg3_flag(tp, APE_HAS_NCSI)) | |
818 | return 0; | |
819 | ||
820 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
821 | if (apedata != APE_SEG_SIG_MAGIC) | |
822 | return -ENODEV; | |
823 | ||
824 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
825 | if (!(apedata & APE_FW_STATUS_READY)) | |
826 | return -EAGAIN; | |
827 | ||
828 | bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) + | |
829 | TG3_APE_SHMEM_BASE; | |
830 | msgoff = bufoff + 2 * sizeof(u32); | |
831 | maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN); | |
832 | ||
833 | while (len) { | |
834 | u32 length; | |
835 | ||
836 | /* Cap xfer sizes to scratchpad limits. */ | |
837 | length = (len > maxlen) ? maxlen : len; | |
838 | len -= length; | |
839 | ||
840 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
841 | if (!(apedata & APE_FW_STATUS_READY)) | |
842 | return -EAGAIN; | |
843 | ||
844 | /* Wait for up to 1 msec for APE to service previous event. */ | |
845 | err = tg3_ape_event_lock(tp, 1000); | |
846 | if (err) | |
847 | return err; | |
848 | ||
849 | apedata = APE_EVENT_STATUS_DRIVER_EVNT | | |
850 | APE_EVENT_STATUS_SCRTCHPD_READ | | |
851 | APE_EVENT_STATUS_EVENT_PENDING; | |
852 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata); | |
853 | ||
854 | tg3_ape_write32(tp, bufoff, base_off); | |
855 | tg3_ape_write32(tp, bufoff + sizeof(u32), length); | |
856 | ||
857 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
858 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
859 | ||
860 | base_off += length; | |
861 | ||
862 | if (tg3_ape_wait_for_event(tp, 30000)) | |
863 | return -EAGAIN; | |
864 | ||
865 | for (i = 0; length; i += 4, length -= 4) { | |
866 | u32 val = tg3_ape_read32(tp, msgoff + i); | |
867 | memcpy(data, &val, sizeof(u32)); | |
868 | data++; | |
869 | } | |
870 | } | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
b65a372b MC |
875 | static int tg3_ape_send_event(struct tg3 *tp, u32 event) |
876 | { | |
877 | int err; | |
878 | u32 apedata; | |
fd6d3f0e MC |
879 | |
880 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
881 | if (apedata != APE_SEG_SIG_MAGIC) | |
b65a372b | 882 | return -EAGAIN; |
fd6d3f0e MC |
883 | |
884 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
885 | if (!(apedata & APE_FW_STATUS_READY)) | |
b65a372b | 886 | return -EAGAIN; |
fd6d3f0e MC |
887 | |
888 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
b65a372b MC |
889 | err = tg3_ape_event_lock(tp, 1000); |
890 | if (err) | |
891 | return err; | |
fd6d3f0e | 892 | |
b65a372b MC |
893 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, |
894 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
fd6d3f0e | 895 | |
b65a372b MC |
896 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); |
897 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
fd6d3f0e | 898 | |
b65a372b | 899 | return 0; |
fd6d3f0e MC |
900 | } |
901 | ||
902 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
903 | { | |
904 | u32 event; | |
905 | u32 apedata; | |
906 | ||
907 | if (!tg3_flag(tp, ENABLE_APE)) | |
908 | return; | |
909 | ||
910 | switch (kind) { | |
911 | case RESET_KIND_INIT: | |
912 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
913 | APE_HOST_SEG_SIG_MAGIC); | |
914 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
915 | APE_HOST_SEG_LEN_MAGIC); | |
916 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
917 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
918 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
919 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); | |
920 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
921 | APE_HOST_BEHAV_NO_PHYLOCK); | |
922 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, | |
923 | TG3_APE_HOST_DRVR_STATE_START); | |
924 | ||
925 | event = APE_EVENT_STATUS_STATE_START; | |
926 | break; | |
927 | case RESET_KIND_SHUTDOWN: | |
928 | /* With the interface we are currently using, | |
929 | * APE does not track driver state. Wiping | |
930 | * out the HOST SEGMENT SIGNATURE forces | |
931 | * the APE to assume OS absent status. | |
932 | */ | |
933 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
934 | ||
935 | if (device_may_wakeup(&tp->pdev->dev) && | |
936 | tg3_flag(tp, WOL_ENABLE)) { | |
937 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, | |
938 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
939 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
940 | } else | |
941 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
942 | ||
943 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
944 | ||
945 | event = APE_EVENT_STATUS_STATE_UNLOAD; | |
946 | break; | |
947 | case RESET_KIND_SUSPEND: | |
948 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
949 | break; | |
950 | default: | |
951 | return; | |
952 | } | |
953 | ||
954 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
955 | ||
956 | tg3_ape_send_event(tp, event); | |
957 | } | |
958 | ||
1da177e4 LT |
959 | static void tg3_disable_ints(struct tg3 *tp) |
960 | { | |
89aeb3bc MC |
961 | int i; |
962 | ||
1da177e4 LT |
963 | tw32(TG3PCI_MISC_HOST_CTRL, |
964 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
965 | for (i = 0; i < tp->irq_max; i++) |
966 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
967 | } |
968 | ||
1da177e4 LT |
969 | static void tg3_enable_ints(struct tg3 *tp) |
970 | { | |
89aeb3bc | 971 | int i; |
89aeb3bc | 972 | |
bbe832c0 MC |
973 | tp->irq_sync = 0; |
974 | wmb(); | |
975 | ||
1da177e4 LT |
976 | tw32(TG3PCI_MISC_HOST_CTRL, |
977 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 978 | |
f89f38b8 | 979 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
980 | for (i = 0; i < tp->irq_cnt; i++) { |
981 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 982 | |
898a56f8 | 983 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
63c3a66f | 984 | if (tg3_flag(tp, 1SHOT_MSI)) |
89aeb3bc | 985 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
f19af9c2 | 986 | |
f89f38b8 | 987 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 988 | } |
f19af9c2 MC |
989 | |
990 | /* Force an initial interrupt */ | |
63c3a66f | 991 | if (!tg3_flag(tp, TAGGED_STATUS) && |
f19af9c2 MC |
992 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) |
993 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
994 | else | |
f89f38b8 MC |
995 | tw32(HOSTCC_MODE, tp->coal_now); |
996 | ||
997 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
998 | } |
999 | ||
17375d25 | 1000 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 1001 | { |
17375d25 | 1002 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 1003 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
1004 | unsigned int work_exists = 0; |
1005 | ||
1006 | /* check for phy events */ | |
63c3a66f | 1007 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
04237ddd MC |
1008 | if (sblk->status & SD_STATUS_LINK_CHG) |
1009 | work_exists = 1; | |
1010 | } | |
f891ea16 MC |
1011 | |
1012 | /* check for TX work to do */ | |
1013 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons) | |
1014 | work_exists = 1; | |
1015 | ||
1016 | /* check for RX work to do */ | |
1017 | if (tnapi->rx_rcb_prod_idx && | |
8d9d7cfc | 1018 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
1019 | work_exists = 1; |
1020 | ||
1021 | return work_exists; | |
1022 | } | |
1023 | ||
17375d25 | 1024 | /* tg3_int_reenable |
04237ddd MC |
1025 | * similar to tg3_enable_ints, but it accurately determines whether there |
1026 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 1027 | * which reenables interrupts |
1da177e4 | 1028 | */ |
17375d25 | 1029 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 1030 | { |
17375d25 MC |
1031 | struct tg3 *tp = tnapi->tp; |
1032 | ||
898a56f8 | 1033 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
1034 | mmiowb(); |
1035 | ||
fac9b83e DM |
1036 | /* When doing tagged status, this work check is unnecessary. |
1037 | * The last_tag we write above tells the chip which piece of | |
1038 | * work we've completed. | |
1039 | */ | |
63c3a66f | 1040 | if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) |
04237ddd | 1041 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 1042 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
1043 | } |
1044 | ||
1da177e4 LT |
1045 | static void tg3_switch_clocks(struct tg3 *tp) |
1046 | { | |
f6eb9b1f | 1047 | u32 clock_ctrl; |
1da177e4 LT |
1048 | u32 orig_clock_ctrl; |
1049 | ||
63c3a66f | 1050 | if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) |
4cf78e4f MC |
1051 | return; |
1052 | ||
f6eb9b1f MC |
1053 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
1054 | ||
1da177e4 LT |
1055 | orig_clock_ctrl = clock_ctrl; |
1056 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
1057 | CLOCK_CTRL_CLKRUN_OENABLE | | |
1058 | 0x1f); | |
1059 | tp->pci_clock_ctrl = clock_ctrl; | |
1060 | ||
63c3a66f | 1061 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 | 1062 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { |
b401e9e2 MC |
1063 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
1064 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
1065 | } |
1066 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
1067 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
1068 | clock_ctrl | | |
1069 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
1070 | 40); | |
1071 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
1072 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
1073 | 40); | |
1da177e4 | 1074 | } |
b401e9e2 | 1075 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
1076 | } |
1077 | ||
1078 | #define PHY_BUSY_LOOPS 5000 | |
1079 | ||
1080 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
1081 | { | |
1082 | u32 frame_val; | |
1083 | unsigned int loops; | |
1084 | int ret; | |
1085 | ||
1086 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
1087 | tw32_f(MAC_MI_MODE, | |
1088 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
1089 | udelay(80); | |
1090 | } | |
1091 | ||
8151ad57 MC |
1092 | tg3_ape_lock(tp, tp->phy_ape_lock); |
1093 | ||
1da177e4 LT |
1094 | *val = 0x0; |
1095 | ||
882e9793 | 1096 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
1097 | MI_COM_PHY_ADDR_MASK); |
1098 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
1099 | MI_COM_REG_ADDR_MASK); | |
1100 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 1101 | |
1da177e4 LT |
1102 | tw32_f(MAC_MI_COM, frame_val); |
1103 | ||
1104 | loops = PHY_BUSY_LOOPS; | |
1105 | while (loops != 0) { | |
1106 | udelay(10); | |
1107 | frame_val = tr32(MAC_MI_COM); | |
1108 | ||
1109 | if ((frame_val & MI_COM_BUSY) == 0) { | |
1110 | udelay(5); | |
1111 | frame_val = tr32(MAC_MI_COM); | |
1112 | break; | |
1113 | } | |
1114 | loops -= 1; | |
1115 | } | |
1116 | ||
1117 | ret = -EBUSY; | |
1118 | if (loops != 0) { | |
1119 | *val = frame_val & MI_COM_DATA_MASK; | |
1120 | ret = 0; | |
1121 | } | |
1122 | ||
1123 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
1124 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1125 | udelay(80); | |
1126 | } | |
1127 | ||
8151ad57 MC |
1128 | tg3_ape_unlock(tp, tp->phy_ape_lock); |
1129 | ||
1da177e4 LT |
1130 | return ret; |
1131 | } | |
1132 | ||
1133 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
1134 | { | |
1135 | u32 frame_val; | |
1136 | unsigned int loops; | |
1137 | int ret; | |
1138 | ||
f07e9af3 | 1139 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
221c5637 | 1140 | (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) |
b5d3772c MC |
1141 | return 0; |
1142 | ||
1da177e4 LT |
1143 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
1144 | tw32_f(MAC_MI_MODE, | |
1145 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
1146 | udelay(80); | |
1147 | } | |
1148 | ||
8151ad57 MC |
1149 | tg3_ape_lock(tp, tp->phy_ape_lock); |
1150 | ||
882e9793 | 1151 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
1152 | MI_COM_PHY_ADDR_MASK); |
1153 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
1154 | MI_COM_REG_ADDR_MASK); | |
1155 | frame_val |= (val & MI_COM_DATA_MASK); | |
1156 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 1157 | |
1da177e4 LT |
1158 | tw32_f(MAC_MI_COM, frame_val); |
1159 | ||
1160 | loops = PHY_BUSY_LOOPS; | |
1161 | while (loops != 0) { | |
1162 | udelay(10); | |
1163 | frame_val = tr32(MAC_MI_COM); | |
1164 | if ((frame_val & MI_COM_BUSY) == 0) { | |
1165 | udelay(5); | |
1166 | frame_val = tr32(MAC_MI_COM); | |
1167 | break; | |
1168 | } | |
1169 | loops -= 1; | |
1170 | } | |
1171 | ||
1172 | ret = -EBUSY; | |
1173 | if (loops != 0) | |
1174 | ret = 0; | |
1175 | ||
1176 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
1177 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1178 | udelay(80); | |
1179 | } | |
1180 | ||
8151ad57 MC |
1181 | tg3_ape_unlock(tp, tp->phy_ape_lock); |
1182 | ||
1da177e4 LT |
1183 | return ret; |
1184 | } | |
1185 | ||
b0988c15 MC |
1186 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
1187 | { | |
1188 | int err; | |
1189 | ||
1190 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1191 | if (err) | |
1192 | goto done; | |
1193 | ||
1194 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1195 | if (err) | |
1196 | goto done; | |
1197 | ||
1198 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1199 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1200 | if (err) | |
1201 | goto done; | |
1202 | ||
1203 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
1204 | ||
1205 | done: | |
1206 | return err; | |
1207 | } | |
1208 | ||
1209 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
1210 | { | |
1211 | int err; | |
1212 | ||
1213 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1214 | if (err) | |
1215 | goto done; | |
1216 | ||
1217 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1218 | if (err) | |
1219 | goto done; | |
1220 | ||
1221 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1222 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1223 | if (err) | |
1224 | goto done; | |
1225 | ||
1226 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
1227 | ||
1228 | done: | |
1229 | return err; | |
1230 | } | |
1231 | ||
1232 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) | |
1233 | { | |
1234 | int err; | |
1235 | ||
1236 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1237 | if (!err) | |
1238 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
1239 | ||
1240 | return err; | |
1241 | } | |
1242 | ||
1243 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
1244 | { | |
1245 | int err; | |
1246 | ||
1247 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1248 | if (!err) | |
1249 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1250 | ||
1251 | return err; | |
1252 | } | |
1253 | ||
15ee95c3 MC |
1254 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) |
1255 | { | |
1256 | int err; | |
1257 | ||
1258 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1259 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | | |
1260 | MII_TG3_AUXCTL_SHDWSEL_MISC); | |
1261 | if (!err) | |
1262 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); | |
1263 | ||
1264 | return err; | |
1265 | } | |
1266 | ||
b4bd2929 MC |
1267 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) |
1268 | { | |
1269 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) | |
1270 | set |= MII_TG3_AUXCTL_MISC_WREN; | |
1271 | ||
1272 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); | |
1273 | } | |
1274 | ||
1d36ba45 MC |
1275 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ |
1276 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1277 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ | |
1278 | MII_TG3_AUXCTL_ACTL_TX_6DB) | |
1279 | ||
1280 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ | |
1281 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1282 | MII_TG3_AUXCTL_ACTL_TX_6DB); | |
1283 | ||
95e2869a MC |
1284 | static int tg3_bmcr_reset(struct tg3 *tp) |
1285 | { | |
1286 | u32 phy_control; | |
1287 | int limit, err; | |
1288 | ||
1289 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
1290 | * clears or we time out. | |
1291 | */ | |
1292 | phy_control = BMCR_RESET; | |
1293 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
1294 | if (err != 0) | |
1295 | return -EBUSY; | |
1296 | ||
1297 | limit = 5000; | |
1298 | while (limit--) { | |
1299 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
1300 | if (err != 0) | |
1301 | return -EBUSY; | |
1302 | ||
1303 | if ((phy_control & BMCR_RESET) == 0) { | |
1304 | udelay(40); | |
1305 | break; | |
1306 | } | |
1307 | udelay(10); | |
1308 | } | |
d4675b52 | 1309 | if (limit < 0) |
95e2869a MC |
1310 | return -EBUSY; |
1311 | ||
1312 | return 0; | |
1313 | } | |
1314 | ||
158d7abd MC |
1315 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
1316 | { | |
3d16543d | 1317 | struct tg3 *tp = bp->priv; |
158d7abd MC |
1318 | u32 val; |
1319 | ||
24bb4fb6 | 1320 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1321 | |
1322 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
1323 | val = -EIO; |
1324 | ||
1325 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
1326 | |
1327 | return val; | |
1328 | } | |
1329 | ||
1330 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
1331 | { | |
3d16543d | 1332 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 1333 | u32 ret = 0; |
158d7abd | 1334 | |
24bb4fb6 | 1335 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1336 | |
1337 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 1338 | ret = -EIO; |
158d7abd | 1339 | |
24bb4fb6 MC |
1340 | spin_unlock_bh(&tp->lock); |
1341 | ||
1342 | return ret; | |
158d7abd MC |
1343 | } |
1344 | ||
1345 | static int tg3_mdio_reset(struct mii_bus *bp) | |
1346 | { | |
1347 | return 0; | |
1348 | } | |
1349 | ||
9c61d6bc | 1350 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
1351 | { |
1352 | u32 val; | |
fcb389df | 1353 | struct phy_device *phydev; |
a9daf367 | 1354 | |
3f0e3ad7 | 1355 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 1356 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
1357 | case PHY_ID_BCM50610: |
1358 | case PHY_ID_BCM50610M: | |
fcb389df MC |
1359 | val = MAC_PHYCFG2_50610_LED_MODES; |
1360 | break; | |
6a443a0f | 1361 | case PHY_ID_BCMAC131: |
fcb389df MC |
1362 | val = MAC_PHYCFG2_AC131_LED_MODES; |
1363 | break; | |
6a443a0f | 1364 | case PHY_ID_RTL8211C: |
fcb389df MC |
1365 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
1366 | break; | |
6a443a0f | 1367 | case PHY_ID_RTL8201E: |
fcb389df MC |
1368 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
1369 | break; | |
1370 | default: | |
a9daf367 | 1371 | return; |
fcb389df MC |
1372 | } |
1373 | ||
1374 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
1375 | tw32(MAC_PHYCFG2, val); | |
1376 | ||
1377 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
1378 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
1379 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1380 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
1381 | tw32(MAC_PHYCFG1, val); |
1382 | ||
1383 | return; | |
1384 | } | |
1385 | ||
63c3a66f | 1386 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) |
fcb389df MC |
1387 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
1388 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1389 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1390 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1391 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1392 | MAC_PHYCFG2_INBAND_ENABLE; | |
1393 | ||
1394 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 1395 | |
bb85fbb6 MC |
1396 | val = tr32(MAC_PHYCFG1); |
1397 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1398 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
63c3a66f JP |
1399 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1400 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 | 1401 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; |
63c3a66f | 1402 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1403 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; |
1404 | } | |
bb85fbb6 MC |
1405 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1406 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1407 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1408 | |
a9daf367 MC |
1409 | val = tr32(MAC_EXT_RGMII_MODE); |
1410 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1411 | MAC_RGMII_MODE_RX_QUALITY | | |
1412 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1413 | MAC_RGMII_MODE_RX_ENG_DET | | |
1414 | MAC_RGMII_MODE_TX_ENABLE | | |
1415 | MAC_RGMII_MODE_TX_LOWPWR | | |
1416 | MAC_RGMII_MODE_TX_RESET); | |
63c3a66f JP |
1417 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
1418 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
a9daf367 MC |
1419 | val |= MAC_RGMII_MODE_RX_INT_B | |
1420 | MAC_RGMII_MODE_RX_QUALITY | | |
1421 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1422 | MAC_RGMII_MODE_RX_ENG_DET; | |
63c3a66f | 1423 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 MC |
1424 | val |= MAC_RGMII_MODE_TX_ENABLE | |
1425 | MAC_RGMII_MODE_TX_LOWPWR | | |
1426 | MAC_RGMII_MODE_TX_RESET; | |
1427 | } | |
1428 | tw32(MAC_EXT_RGMII_MODE, val); | |
1429 | } | |
1430 | ||
158d7abd MC |
1431 | static void tg3_mdio_start(struct tg3 *tp) |
1432 | { | |
158d7abd MC |
1433 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1434 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1435 | udelay(80); | |
a9daf367 | 1436 | |
63c3a66f | 1437 | if (tg3_flag(tp, MDIOBUS_INITED) && |
9ea4818d MC |
1438 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
1439 | tg3_mdio_config_5785(tp); | |
1440 | } | |
1441 | ||
1442 | static int tg3_mdio_init(struct tg3 *tp) | |
1443 | { | |
1444 | int i; | |
1445 | u32 reg; | |
1446 | struct phy_device *phydev; | |
1447 | ||
63c3a66f | 1448 | if (tg3_flag(tp, 5717_PLUS)) { |
9c7df915 | 1449 | u32 is_serdes; |
882e9793 | 1450 | |
69f11c99 | 1451 | tp->phy_addr = tp->pci_fn + 1; |
882e9793 | 1452 | |
d1ec96af MC |
1453 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1454 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1455 | else | |
1456 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1457 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1458 | if (is_serdes) |
1459 | tp->phy_addr += 7; | |
1460 | } else | |
3f0e3ad7 | 1461 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1462 | |
158d7abd MC |
1463 | tg3_mdio_start(tp); |
1464 | ||
63c3a66f | 1465 | if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) |
158d7abd MC |
1466 | return 0; |
1467 | ||
298cf9be LB |
1468 | tp->mdio_bus = mdiobus_alloc(); |
1469 | if (tp->mdio_bus == NULL) | |
1470 | return -ENOMEM; | |
158d7abd | 1471 | |
298cf9be LB |
1472 | tp->mdio_bus->name = "tg3 mdio bus"; |
1473 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1474 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1475 | tp->mdio_bus->priv = tp; |
1476 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1477 | tp->mdio_bus->read = &tg3_mdio_read; | |
1478 | tp->mdio_bus->write = &tg3_mdio_write; | |
1479 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1480 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1481 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1482 | |
1483 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1484 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1485 | |
1486 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1487 | * Unfortunately, it does not ensure the PHY is powered up before | |
1488 | * accessing the PHY ID registers. A chip reset is the | |
1489 | * quickest way to bring the device back to an operational state.. | |
1490 | */ | |
1491 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1492 | tg3_bmcr_reset(tp); | |
1493 | ||
298cf9be | 1494 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1495 | if (i) { |
ab96b241 | 1496 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1497 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1498 | return i; |
1499 | } | |
158d7abd | 1500 | |
3f0e3ad7 | 1501 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1502 | |
9c61d6bc | 1503 | if (!phydev || !phydev->drv) { |
ab96b241 | 1504 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1505 | mdiobus_unregister(tp->mdio_bus); |
1506 | mdiobus_free(tp->mdio_bus); | |
1507 | return -ENODEV; | |
1508 | } | |
1509 | ||
1510 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1511 | case PHY_ID_BCM57780: |
321d32a0 | 1512 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1513 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1514 | break; |
6a443a0f MC |
1515 | case PHY_ID_BCM50610: |
1516 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1517 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1518 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1519 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1520 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
63c3a66f | 1521 | if (tg3_flag(tp, RGMII_INBAND_DISABLE)) |
a9daf367 | 1522 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
63c3a66f | 1523 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
a9daf367 | 1524 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; |
63c3a66f | 1525 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
a9daf367 | 1526 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; |
fcb389df | 1527 | /* fallthru */ |
6a443a0f | 1528 | case PHY_ID_RTL8211C: |
fcb389df | 1529 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1530 | break; |
6a443a0f MC |
1531 | case PHY_ID_RTL8201E: |
1532 | case PHY_ID_BCMAC131: | |
a9daf367 | 1533 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1534 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1535 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1536 | break; |
1537 | } | |
1538 | ||
63c3a66f | 1539 | tg3_flag_set(tp, MDIOBUS_INITED); |
9c61d6bc MC |
1540 | |
1541 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1542 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1543 | |
1544 | return 0; | |
158d7abd MC |
1545 | } |
1546 | ||
1547 | static void tg3_mdio_fini(struct tg3 *tp) | |
1548 | { | |
63c3a66f JP |
1549 | if (tg3_flag(tp, MDIOBUS_INITED)) { |
1550 | tg3_flag_clear(tp, MDIOBUS_INITED); | |
298cf9be LB |
1551 | mdiobus_unregister(tp->mdio_bus); |
1552 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1553 | } |
1554 | } | |
1555 | ||
4ba526ce MC |
1556 | /* tp->lock is held. */ |
1557 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1558 | { | |
1559 | u32 val; | |
1560 | ||
1561 | val = tr32(GRC_RX_CPU_EVENT); | |
1562 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1563 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1564 | ||
1565 | tp->last_event_jiffies = jiffies; | |
1566 | } | |
1567 | ||
1568 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1569 | ||
95e2869a MC |
1570 | /* tp->lock is held. */ |
1571 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1572 | { | |
1573 | int i; | |
4ba526ce MC |
1574 | unsigned int delay_cnt; |
1575 | long time_remain; | |
1576 | ||
1577 | /* If enough time has passed, no wait is necessary. */ | |
1578 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1579 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1580 | (long)jiffies; | |
1581 | if (time_remain < 0) | |
1582 | return; | |
1583 | ||
1584 | /* Check if we can shorten the wait time. */ | |
1585 | delay_cnt = jiffies_to_usecs(time_remain); | |
1586 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1587 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1588 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1589 | |
4ba526ce | 1590 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1591 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1592 | break; | |
4ba526ce | 1593 | udelay(8); |
95e2869a MC |
1594 | } |
1595 | } | |
1596 | ||
1597 | /* tp->lock is held. */ | |
b28f389d | 1598 | static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data) |
95e2869a | 1599 | { |
b28f389d | 1600 | u32 reg, val; |
95e2869a MC |
1601 | |
1602 | val = 0; | |
1603 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1604 | val = reg << 16; | |
1605 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1606 | val |= (reg & 0xffff); | |
b28f389d | 1607 | *data++ = val; |
95e2869a MC |
1608 | |
1609 | val = 0; | |
1610 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1611 | val = reg << 16; | |
1612 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1613 | val |= (reg & 0xffff); | |
b28f389d | 1614 | *data++ = val; |
95e2869a MC |
1615 | |
1616 | val = 0; | |
f07e9af3 | 1617 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1618 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1619 | val = reg << 16; | |
1620 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1621 | val |= (reg & 0xffff); | |
1622 | } | |
b28f389d | 1623 | *data++ = val; |
95e2869a MC |
1624 | |
1625 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1626 | val = reg << 16; | |
1627 | else | |
1628 | val = 0; | |
b28f389d MC |
1629 | *data++ = val; |
1630 | } | |
1631 | ||
1632 | /* tp->lock is held. */ | |
1633 | static void tg3_ump_link_report(struct tg3 *tp) | |
1634 | { | |
1635 | u32 data[4]; | |
1636 | ||
1637 | if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) | |
1638 | return; | |
1639 | ||
1640 | tg3_phy_gather_ump_data(tp, data); | |
1641 | ||
1642 | tg3_wait_for_event_ack(tp); | |
1643 | ||
1644 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1645 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1646 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]); | |
1647 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]); | |
1648 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]); | |
1649 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]); | |
95e2869a | 1650 | |
4ba526ce | 1651 | tg3_generate_fw_event(tp); |
95e2869a MC |
1652 | } |
1653 | ||
8d5a89b3 MC |
1654 | /* tp->lock is held. */ |
1655 | static void tg3_stop_fw(struct tg3 *tp) | |
1656 | { | |
1657 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { | |
1658 | /* Wait for RX cpu to ACK the previous event. */ | |
1659 | tg3_wait_for_event_ack(tp); | |
1660 | ||
1661 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
1662 | ||
1663 | tg3_generate_fw_event(tp); | |
1664 | ||
1665 | /* Wait for RX cpu to ACK this event. */ | |
1666 | tg3_wait_for_event_ack(tp); | |
1667 | } | |
1668 | } | |
1669 | ||
fd6d3f0e MC |
1670 | /* tp->lock is held. */ |
1671 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
1672 | { | |
1673 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, | |
1674 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1675 | ||
1676 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
1677 | switch (kind) { | |
1678 | case RESET_KIND_INIT: | |
1679 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1680 | DRV_STATE_START); | |
1681 | break; | |
1682 | ||
1683 | case RESET_KIND_SHUTDOWN: | |
1684 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1685 | DRV_STATE_UNLOAD); | |
1686 | break; | |
1687 | ||
1688 | case RESET_KIND_SUSPEND: | |
1689 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1690 | DRV_STATE_SUSPEND); | |
1691 | break; | |
1692 | ||
1693 | default: | |
1694 | break; | |
1695 | } | |
1696 | } | |
1697 | ||
1698 | if (kind == RESET_KIND_INIT || | |
1699 | kind == RESET_KIND_SUSPEND) | |
1700 | tg3_ape_driver_state_change(tp, kind); | |
1701 | } | |
1702 | ||
1703 | /* tp->lock is held. */ | |
1704 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
1705 | { | |
1706 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
1707 | switch (kind) { | |
1708 | case RESET_KIND_INIT: | |
1709 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1710 | DRV_STATE_START_DONE); | |
1711 | break; | |
1712 | ||
1713 | case RESET_KIND_SHUTDOWN: | |
1714 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1715 | DRV_STATE_UNLOAD_DONE); | |
1716 | break; | |
1717 | ||
1718 | default: | |
1719 | break; | |
1720 | } | |
1721 | } | |
1722 | ||
1723 | if (kind == RESET_KIND_SHUTDOWN) | |
1724 | tg3_ape_driver_state_change(tp, kind); | |
1725 | } | |
1726 | ||
1727 | /* tp->lock is held. */ | |
1728 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
1729 | { | |
1730 | if (tg3_flag(tp, ENABLE_ASF)) { | |
1731 | switch (kind) { | |
1732 | case RESET_KIND_INIT: | |
1733 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1734 | DRV_STATE_START); | |
1735 | break; | |
1736 | ||
1737 | case RESET_KIND_SHUTDOWN: | |
1738 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1739 | DRV_STATE_UNLOAD); | |
1740 | break; | |
1741 | ||
1742 | case RESET_KIND_SUSPEND: | |
1743 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
1744 | DRV_STATE_SUSPEND); | |
1745 | break; | |
1746 | ||
1747 | default: | |
1748 | break; | |
1749 | } | |
1750 | } | |
1751 | } | |
1752 | ||
1753 | static int tg3_poll_fw(struct tg3 *tp) | |
1754 | { | |
1755 | int i; | |
1756 | u32 val; | |
1757 | ||
1758 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
1759 | /* Wait up to 20ms for init done. */ | |
1760 | for (i = 0; i < 200; i++) { | |
1761 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) | |
1762 | return 0; | |
1763 | udelay(100); | |
1764 | } | |
1765 | return -ENODEV; | |
1766 | } | |
1767 | ||
1768 | /* Wait for firmware initialization to complete. */ | |
1769 | for (i = 0; i < 100000; i++) { | |
1770 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
1771 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
1772 | break; | |
1773 | udelay(10); | |
1774 | } | |
1775 | ||
1776 | /* Chip might not be fitted with firmware. Some Sun onboard | |
1777 | * parts are configured like that. So don't signal the timeout | |
1778 | * of the above loop as an error, but do report the lack of | |
1779 | * running firmware once. | |
1780 | */ | |
1781 | if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { | |
1782 | tg3_flag_set(tp, NO_FWARE_REPORTED); | |
1783 | ||
1784 | netdev_info(tp->dev, "No firmware running\n"); | |
1785 | } | |
1786 | ||
1787 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
1788 | /* The 57765 A0 needs a little more | |
1789 | * time to do some important work. | |
1790 | */ | |
1791 | mdelay(10); | |
1792 | } | |
1793 | ||
1794 | return 0; | |
1795 | } | |
1796 | ||
95e2869a MC |
1797 | static void tg3_link_report(struct tg3 *tp) |
1798 | { | |
1799 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1800 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1801 | tg3_ump_link_report(tp); |
1802 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1803 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1804 | (tp->link_config.active_speed == SPEED_1000 ? | |
1805 | 1000 : | |
1806 | (tp->link_config.active_speed == SPEED_100 ? | |
1807 | 100 : 10)), | |
1808 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1809 | "full" : "half")); | |
1810 | ||
1811 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1812 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1813 | "on" : "off", | |
1814 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1815 | "on" : "off"); | |
47007831 MC |
1816 | |
1817 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) | |
1818 | netdev_info(tp->dev, "EEE is %s\n", | |
1819 | tp->setlpicnt ? "enabled" : "disabled"); | |
1820 | ||
95e2869a MC |
1821 | tg3_ump_link_report(tp); |
1822 | } | |
1823 | } | |
1824 | ||
95e2869a MC |
1825 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) |
1826 | { | |
1827 | u16 miireg; | |
1828 | ||
e18ce346 | 1829 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1830 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1831 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1832 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1833 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1834 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1835 | else | |
1836 | miireg = 0; | |
1837 | ||
1838 | return miireg; | |
1839 | } | |
1840 | ||
95e2869a MC |
1841 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1842 | { | |
1843 | u8 cap = 0; | |
1844 | ||
f3791cdf MC |
1845 | if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) { |
1846 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1847 | } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) { | |
1848 | if (lcladv & ADVERTISE_1000XPAUSE) | |
1849 | cap = FLOW_CTRL_RX; | |
1850 | if (rmtadv & ADVERTISE_1000XPAUSE) | |
e18ce346 | 1851 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1852 | } |
1853 | ||
1854 | return cap; | |
1855 | } | |
1856 | ||
f51f3562 | 1857 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1858 | { |
b02fd9e3 | 1859 | u8 autoneg; |
f51f3562 | 1860 | u8 flowctrl = 0; |
95e2869a MC |
1861 | u32 old_rx_mode = tp->rx_mode; |
1862 | u32 old_tx_mode = tp->tx_mode; | |
1863 | ||
63c3a66f | 1864 | if (tg3_flag(tp, USE_PHYLIB)) |
3f0e3ad7 | 1865 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1866 | else |
1867 | autoneg = tp->link_config.autoneg; | |
1868 | ||
63c3a66f | 1869 | if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { |
f07e9af3 | 1870 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1871 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1872 | else |
bc02ff95 | 1873 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1874 | } else |
1875 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1876 | |
f51f3562 | 1877 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1878 | |
e18ce346 | 1879 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1880 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1881 | else | |
1882 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1883 | ||
f51f3562 | 1884 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1885 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1886 | |
e18ce346 | 1887 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1888 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1889 | else | |
1890 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1891 | ||
f51f3562 | 1892 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1893 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1894 | } |
1895 | ||
b02fd9e3 MC |
1896 | static void tg3_adjust_link(struct net_device *dev) |
1897 | { | |
1898 | u8 oldflowctrl, linkmesg = 0; | |
1899 | u32 mac_mode, lcl_adv, rmt_adv; | |
1900 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1901 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1902 | |
24bb4fb6 | 1903 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1904 | |
1905 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1906 | MAC_MODE_HALF_DUPLEX); | |
1907 | ||
1908 | oldflowctrl = tp->link_config.active_flowctrl; | |
1909 | ||
1910 | if (phydev->link) { | |
1911 | lcl_adv = 0; | |
1912 | rmt_adv = 0; | |
1913 | ||
1914 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1915 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1916 | else if (phydev->speed == SPEED_1000 || |
1917 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1918 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1919 | else |
1920 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1921 | |
1922 | if (phydev->duplex == DUPLEX_HALF) | |
1923 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1924 | else { | |
f88788f0 | 1925 | lcl_adv = mii_advertise_flowctrl( |
b02fd9e3 MC |
1926 | tp->link_config.flowctrl); |
1927 | ||
1928 | if (phydev->pause) | |
1929 | rmt_adv = LPA_PAUSE_CAP; | |
1930 | if (phydev->asym_pause) | |
1931 | rmt_adv |= LPA_PAUSE_ASYM; | |
1932 | } | |
1933 | ||
1934 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1935 | } else | |
1936 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1937 | ||
1938 | if (mac_mode != tp->mac_mode) { | |
1939 | tp->mac_mode = mac_mode; | |
1940 | tw32_f(MAC_MODE, tp->mac_mode); | |
1941 | udelay(40); | |
1942 | } | |
1943 | ||
fcb389df MC |
1944 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1945 | if (phydev->speed == SPEED_10) | |
1946 | tw32(MAC_MI_STAT, | |
1947 | MAC_MI_STAT_10MBPS_MODE | | |
1948 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1949 | else | |
1950 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1951 | } | |
1952 | ||
b02fd9e3 MC |
1953 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1954 | tw32(MAC_TX_LENGTHS, | |
1955 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1956 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1957 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1958 | else | |
1959 | tw32(MAC_TX_LENGTHS, | |
1960 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1961 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1962 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1963 | ||
34655ad6 | 1964 | if (phydev->link != tp->old_link || |
b02fd9e3 MC |
1965 | phydev->speed != tp->link_config.active_speed || |
1966 | phydev->duplex != tp->link_config.active_duplex || | |
1967 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1968 | linkmesg = 1; |
b02fd9e3 | 1969 | |
34655ad6 | 1970 | tp->old_link = phydev->link; |
b02fd9e3 MC |
1971 | tp->link_config.active_speed = phydev->speed; |
1972 | tp->link_config.active_duplex = phydev->duplex; | |
1973 | ||
24bb4fb6 | 1974 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1975 | |
1976 | if (linkmesg) | |
1977 | tg3_link_report(tp); | |
1978 | } | |
1979 | ||
1980 | static int tg3_phy_init(struct tg3 *tp) | |
1981 | { | |
1982 | struct phy_device *phydev; | |
1983 | ||
f07e9af3 | 1984 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1985 | return 0; |
1986 | ||
1987 | /* Bring the PHY back to a known state. */ | |
1988 | tg3_bmcr_reset(tp); | |
1989 | ||
3f0e3ad7 | 1990 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1991 | |
1992 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1993 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1994 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1995 | if (IS_ERR(phydev)) { |
ab96b241 | 1996 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1997 | return PTR_ERR(phydev); |
1998 | } | |
1999 | ||
b02fd9e3 | 2000 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
2001 | switch (phydev->interface) { |
2002 | case PHY_INTERFACE_MODE_GMII: | |
2003 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 2004 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
2005 | phydev->supported &= (PHY_GBIT_FEATURES | |
2006 | SUPPORTED_Pause | | |
2007 | SUPPORTED_Asym_Pause); | |
2008 | break; | |
2009 | } | |
2010 | /* fallthru */ | |
9c61d6bc MC |
2011 | case PHY_INTERFACE_MODE_MII: |
2012 | phydev->supported &= (PHY_BASIC_FEATURES | | |
2013 | SUPPORTED_Pause | | |
2014 | SUPPORTED_Asym_Pause); | |
2015 | break; | |
2016 | default: | |
3f0e3ad7 | 2017 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
2018 | return -EINVAL; |
2019 | } | |
2020 | ||
f07e9af3 | 2021 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
2022 | |
2023 | phydev->advertising = phydev->supported; | |
2024 | ||
b02fd9e3 MC |
2025 | return 0; |
2026 | } | |
2027 | ||
2028 | static void tg3_phy_start(struct tg3 *tp) | |
2029 | { | |
2030 | struct phy_device *phydev; | |
2031 | ||
f07e9af3 | 2032 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
2033 | return; |
2034 | ||
3f0e3ad7 | 2035 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 2036 | |
80096068 MC |
2037 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
2038 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
c6700ce2 MC |
2039 | phydev->speed = tp->link_config.speed; |
2040 | phydev->duplex = tp->link_config.duplex; | |
2041 | phydev->autoneg = tp->link_config.autoneg; | |
2042 | phydev->advertising = tp->link_config.advertising; | |
b02fd9e3 MC |
2043 | } |
2044 | ||
2045 | phy_start(phydev); | |
2046 | ||
2047 | phy_start_aneg(phydev); | |
2048 | } | |
2049 | ||
2050 | static void tg3_phy_stop(struct tg3 *tp) | |
2051 | { | |
f07e9af3 | 2052 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
2053 | return; |
2054 | ||
3f0e3ad7 | 2055 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
2056 | } |
2057 | ||
2058 | static void tg3_phy_fini(struct tg3 *tp) | |
2059 | { | |
f07e9af3 | 2060 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 2061 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 2062 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
2063 | } |
2064 | } | |
2065 | ||
941ec90f MC |
2066 | static int tg3_phy_set_extloopbk(struct tg3 *tp) |
2067 | { | |
2068 | int err; | |
2069 | u32 val; | |
2070 | ||
2071 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
2072 | return 0; | |
2073 | ||
2074 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { | |
2075 | /* Cannot do read-modify-write on 5401 */ | |
2076 | err = tg3_phy_auxctl_write(tp, | |
2077 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, | |
2078 | MII_TG3_AUXCTL_ACTL_EXTLOOPBK | | |
2079 | 0x4c20); | |
2080 | goto done; | |
2081 | } | |
2082 | ||
2083 | err = tg3_phy_auxctl_read(tp, | |
2084 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2085 | if (err) | |
2086 | return err; | |
2087 | ||
2088 | val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK; | |
2089 | err = tg3_phy_auxctl_write(tp, | |
2090 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val); | |
2091 | ||
2092 | done: | |
2093 | return err; | |
2094 | } | |
2095 | ||
7f97a4bd MC |
2096 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
2097 | { | |
2098 | u32 phytest; | |
2099 | ||
2100 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2101 | u32 phy; | |
2102 | ||
2103 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2104 | phytest | MII_TG3_FET_SHADOW_EN); | |
2105 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
2106 | if (enable) | |
2107 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
2108 | else | |
2109 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
2110 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
2111 | } | |
2112 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2113 | } | |
2114 | } | |
2115 | ||
6833c043 MC |
2116 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
2117 | { | |
2118 | u32 reg; | |
2119 | ||
63c3a66f JP |
2120 | if (!tg3_flag(tp, 5705_PLUS) || |
2121 | (tg3_flag(tp, 5717_PLUS) && | |
f07e9af3 | 2122 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
2123 | return; |
2124 | ||
f07e9af3 | 2125 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
2126 | tg3_phy_fet_toggle_apd(tp, enable); |
2127 | return; | |
2128 | } | |
2129 | ||
6833c043 MC |
2130 | reg = MII_TG3_MISC_SHDW_WREN | |
2131 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
2132 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
2133 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
2134 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
2135 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
2136 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
2137 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
2138 | ||
2139 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
2140 | ||
2141 | ||
2142 | reg = MII_TG3_MISC_SHDW_WREN | | |
2143 | MII_TG3_MISC_SHDW_APD_SEL | | |
2144 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
2145 | if (enable) | |
2146 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
2147 | ||
2148 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
2149 | } | |
2150 | ||
9ef8ca99 MC |
2151 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
2152 | { | |
2153 | u32 phy; | |
2154 | ||
63c3a66f | 2155 | if (!tg3_flag(tp, 5705_PLUS) || |
f07e9af3 | 2156 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
2157 | return; |
2158 | ||
f07e9af3 | 2159 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
2160 | u32 ephy; |
2161 | ||
535ef6e1 MC |
2162 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
2163 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
2164 | ||
2165 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2166 | ephy | MII_TG3_FET_SHADOW_EN); | |
2167 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 2168 | if (enable) |
535ef6e1 | 2169 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 2170 | else |
535ef6e1 MC |
2171 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
2172 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 2173 | } |
535ef6e1 | 2174 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
2175 | } |
2176 | } else { | |
15ee95c3 MC |
2177 | int ret; |
2178 | ||
2179 | ret = tg3_phy_auxctl_read(tp, | |
2180 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); | |
2181 | if (!ret) { | |
9ef8ca99 MC |
2182 | if (enable) |
2183 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
2184 | else | |
2185 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
b4bd2929 MC |
2186 | tg3_phy_auxctl_write(tp, |
2187 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); | |
9ef8ca99 MC |
2188 | } |
2189 | } | |
2190 | } | |
2191 | ||
1da177e4 LT |
2192 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
2193 | { | |
15ee95c3 | 2194 | int ret; |
1da177e4 LT |
2195 | u32 val; |
2196 | ||
f07e9af3 | 2197 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
2198 | return; |
2199 | ||
15ee95c3 MC |
2200 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); |
2201 | if (!ret) | |
b4bd2929 MC |
2202 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, |
2203 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); | |
1da177e4 LT |
2204 | } |
2205 | ||
b2a5c19c MC |
2206 | static void tg3_phy_apply_otp(struct tg3 *tp) |
2207 | { | |
2208 | u32 otp, phy; | |
2209 | ||
2210 | if (!tp->phy_otp) | |
2211 | return; | |
2212 | ||
2213 | otp = tp->phy_otp; | |
2214 | ||
1d36ba45 MC |
2215 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) |
2216 | return; | |
b2a5c19c MC |
2217 | |
2218 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
2219 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
2220 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
2221 | ||
2222 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
2223 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
2224 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
2225 | ||
2226 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
2227 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
2228 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
2229 | ||
2230 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
2231 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
2232 | ||
2233 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
2234 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
2235 | ||
2236 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
2237 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
2238 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
2239 | ||
1d36ba45 | 2240 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
b2a5c19c MC |
2241 | } |
2242 | ||
52b02d04 MC |
2243 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
2244 | { | |
2245 | u32 val; | |
2246 | ||
2247 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
2248 | return; | |
2249 | ||
2250 | tp->setlpicnt = 0; | |
2251 | ||
2252 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
2253 | current_link_up == 1 && | |
a6b68dab MC |
2254 | tp->link_config.active_duplex == DUPLEX_FULL && |
2255 | (tp->link_config.active_speed == SPEED_100 || | |
2256 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
2257 | u32 eeectl; |
2258 | ||
2259 | if (tp->link_config.active_speed == SPEED_1000) | |
2260 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
2261 | else | |
2262 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
2263 | ||
2264 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
2265 | ||
3110f5f5 MC |
2266 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
2267 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 2268 | |
b0c5943f MC |
2269 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || |
2270 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) | |
52b02d04 MC |
2271 | tp->setlpicnt = 2; |
2272 | } | |
2273 | ||
2274 | if (!tp->setlpicnt) { | |
b715ce94 MC |
2275 | if (current_link_up == 1 && |
2276 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
2277 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | |
2278 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2279 | } | |
2280 | ||
52b02d04 MC |
2281 | val = tr32(TG3_CPMU_EEE_MODE); |
2282 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
2283 | } | |
2284 | } | |
2285 | ||
b0c5943f MC |
2286 | static void tg3_phy_eee_enable(struct tg3 *tp) |
2287 | { | |
2288 | u32 val; | |
2289 | ||
2290 | if (tp->link_config.active_speed == SPEED_1000 && | |
2291 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2292 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
55086ad9 | 2293 | tg3_flag(tp, 57765_CLASS)) && |
b0c5943f | 2294 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
b715ce94 MC |
2295 | val = MII_TG3_DSP_TAP26_ALNOKO | |
2296 | MII_TG3_DSP_TAP26_RMRXSTO; | |
2297 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
b0c5943f MC |
2298 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
2299 | } | |
2300 | ||
2301 | val = tr32(TG3_CPMU_EEE_MODE); | |
2302 | tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
2303 | } | |
2304 | ||
1da177e4 LT |
2305 | static int tg3_wait_macro_done(struct tg3 *tp) |
2306 | { | |
2307 | int limit = 100; | |
2308 | ||
2309 | while (limit--) { | |
2310 | u32 tmp32; | |
2311 | ||
f08aa1a8 | 2312 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
2313 | if ((tmp32 & 0x1000) == 0) |
2314 | break; | |
2315 | } | |
2316 | } | |
d4675b52 | 2317 | if (limit < 0) |
1da177e4 LT |
2318 | return -EBUSY; |
2319 | ||
2320 | return 0; | |
2321 | } | |
2322 | ||
2323 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
2324 | { | |
2325 | static const u32 test_pat[4][6] = { | |
2326 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
2327 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
2328 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
2329 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
2330 | }; | |
2331 | int chan; | |
2332 | ||
2333 | for (chan = 0; chan < 4; chan++) { | |
2334 | int i; | |
2335 | ||
2336 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2337 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2338 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
2339 | |
2340 | for (i = 0; i < 6; i++) | |
2341 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
2342 | test_pat[chan][i]); | |
2343 | ||
f08aa1a8 | 2344 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
2345 | if (tg3_wait_macro_done(tp)) { |
2346 | *resetp = 1; | |
2347 | return -EBUSY; | |
2348 | } | |
2349 | ||
2350 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2351 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2352 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
2353 | if (tg3_wait_macro_done(tp)) { |
2354 | *resetp = 1; | |
2355 | return -EBUSY; | |
2356 | } | |
2357 | ||
f08aa1a8 | 2358 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
2359 | if (tg3_wait_macro_done(tp)) { |
2360 | *resetp = 1; | |
2361 | return -EBUSY; | |
2362 | } | |
2363 | ||
2364 | for (i = 0; i < 6; i += 2) { | |
2365 | u32 low, high; | |
2366 | ||
2367 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
2368 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
2369 | tg3_wait_macro_done(tp)) { | |
2370 | *resetp = 1; | |
2371 | return -EBUSY; | |
2372 | } | |
2373 | low &= 0x7fff; | |
2374 | high &= 0x000f; | |
2375 | if (low != test_pat[chan][i] || | |
2376 | high != test_pat[chan][i+1]) { | |
2377 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
2378 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
2379 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
2380 | ||
2381 | return -EBUSY; | |
2382 | } | |
2383 | } | |
2384 | } | |
2385 | ||
2386 | return 0; | |
2387 | } | |
2388 | ||
2389 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
2390 | { | |
2391 | int chan; | |
2392 | ||
2393 | for (chan = 0; chan < 4; chan++) { | |
2394 | int i; | |
2395 | ||
2396 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
2397 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 2398 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
2399 | for (i = 0; i < 6; i++) |
2400 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 2401 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
2402 | if (tg3_wait_macro_done(tp)) |
2403 | return -EBUSY; | |
2404 | } | |
2405 | ||
2406 | return 0; | |
2407 | } | |
2408 | ||
2409 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
2410 | { | |
2411 | u32 reg32, phy9_orig; | |
2412 | int retries, do_phy_reset, err; | |
2413 | ||
2414 | retries = 10; | |
2415 | do_phy_reset = 1; | |
2416 | do { | |
2417 | if (do_phy_reset) { | |
2418 | err = tg3_bmcr_reset(tp); | |
2419 | if (err) | |
2420 | return err; | |
2421 | do_phy_reset = 0; | |
2422 | } | |
2423 | ||
2424 | /* Disable transmitter and interrupt. */ | |
2425 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
2426 | continue; | |
2427 | ||
2428 | reg32 |= 0x3000; | |
2429 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2430 | ||
2431 | /* Set full-duplex, 1000 mbps. */ | |
2432 | tg3_writephy(tp, MII_BMCR, | |
221c5637 | 2433 | BMCR_FULLDPLX | BMCR_SPEED1000); |
1da177e4 LT |
2434 | |
2435 | /* Set to master mode. */ | |
221c5637 | 2436 | if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) |
1da177e4 LT |
2437 | continue; |
2438 | ||
221c5637 MC |
2439 | tg3_writephy(tp, MII_CTRL1000, |
2440 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
1da177e4 | 2441 | |
1d36ba45 MC |
2442 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
2443 | if (err) | |
2444 | return err; | |
1da177e4 LT |
2445 | |
2446 | /* Block the PHY control access. */ | |
6ee7c0a0 | 2447 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
2448 | |
2449 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
2450 | if (!err) | |
2451 | break; | |
2452 | } while (--retries); | |
2453 | ||
2454 | err = tg3_phy_reset_chanpat(tp); | |
2455 | if (err) | |
2456 | return err; | |
2457 | ||
6ee7c0a0 | 2458 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
2459 | |
2460 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 2461 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 | 2462 | |
1d36ba45 | 2463 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2464 | |
221c5637 | 2465 | tg3_writephy(tp, MII_CTRL1000, phy9_orig); |
1da177e4 LT |
2466 | |
2467 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
2468 | reg32 &= ~0x3000; | |
2469 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2470 | } else if (!err) | |
2471 | err = -EBUSY; | |
2472 | ||
2473 | return err; | |
2474 | } | |
2475 | ||
f4a46d1f NNS |
2476 | static void tg3_carrier_on(struct tg3 *tp) |
2477 | { | |
2478 | netif_carrier_on(tp->dev); | |
2479 | tp->link_up = true; | |
2480 | } | |
2481 | ||
2482 | static void tg3_carrier_off(struct tg3 *tp) | |
2483 | { | |
2484 | netif_carrier_off(tp->dev); | |
2485 | tp->link_up = false; | |
2486 | } | |
2487 | ||
1da177e4 LT |
2488 | /* This will reset the tigon3 PHY if there is no valid |
2489 | * link unless the FORCE argument is non-zero. | |
2490 | */ | |
2491 | static int tg3_phy_reset(struct tg3 *tp) | |
2492 | { | |
f833c4c1 | 2493 | u32 val, cpmuctrl; |
1da177e4 LT |
2494 | int err; |
2495 | ||
60189ddf | 2496 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2497 | val = tr32(GRC_MISC_CFG); |
2498 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
2499 | udelay(40); | |
2500 | } | |
f833c4c1 MC |
2501 | err = tg3_readphy(tp, MII_BMSR, &val); |
2502 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
2503 | if (err != 0) |
2504 | return -EBUSY; | |
2505 | ||
f4a46d1f NNS |
2506 | if (netif_running(tp->dev) && tp->link_up) { |
2507 | tg3_carrier_off(tp); | |
c8e1e82b MC |
2508 | tg3_link_report(tp); |
2509 | } | |
2510 | ||
1da177e4 LT |
2511 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2512 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2513 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2514 | err = tg3_phy_reset_5703_4_5(tp); | |
2515 | if (err) | |
2516 | return err; | |
2517 | goto out; | |
2518 | } | |
2519 | ||
b2a5c19c MC |
2520 | cpmuctrl = 0; |
2521 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2522 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2523 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2524 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2525 | tw32(TG3_CPMU_CTRL, | |
2526 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2527 | } | |
2528 | ||
1da177e4 LT |
2529 | err = tg3_bmcr_reset(tp); |
2530 | if (err) | |
2531 | return err; | |
2532 | ||
b2a5c19c | 2533 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2534 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2535 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2536 | |
2537 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2538 | } | |
2539 | ||
bcb37f6c MC |
2540 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2541 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2542 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2543 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2544 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2545 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2546 | udelay(40); | |
2547 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2548 | } | |
2549 | } | |
2550 | ||
63c3a66f | 2551 | if (tg3_flag(tp, 5717_PLUS) && |
f07e9af3 | 2552 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2553 | return 0; |
2554 | ||
b2a5c19c MC |
2555 | tg3_phy_apply_otp(tp); |
2556 | ||
f07e9af3 | 2557 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2558 | tg3_phy_toggle_apd(tp, true); |
2559 | else | |
2560 | tg3_phy_toggle_apd(tp, false); | |
2561 | ||
1da177e4 | 2562 | out: |
1d36ba45 MC |
2563 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && |
2564 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
6ee7c0a0 MC |
2565 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2566 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1d36ba45 | 2567 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2568 | } |
1d36ba45 | 2569 | |
f07e9af3 | 2570 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2571 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2572 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2573 | } |
1d36ba45 | 2574 | |
f07e9af3 | 2575 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1d36ba45 MC |
2576 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2577 | tg3_phydsp_write(tp, 0x000a, 0x310b); | |
2578 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2579 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
2580 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2581 | } | |
f07e9af3 | 2582 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
1d36ba45 MC |
2583 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2584 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
2585 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { | |
2586 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2587 | tg3_writephy(tp, MII_TG3_TEST1, | |
2588 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2589 | } else | |
2590 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
2591 | ||
2592 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2593 | } | |
c424cb24 | 2594 | } |
1d36ba45 | 2595 | |
1da177e4 LT |
2596 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2597 | /* support jumbo frames */ | |
79eb6904 | 2598 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 | 2599 | /* Cannot do read-modify-write on 5401 */ |
b4bd2929 | 2600 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
63c3a66f | 2601 | } else if (tg3_flag(tp, JUMBO_CAPABLE)) { |
1da177e4 | 2602 | /* Set bit 14 with read-modify-write to preserve other bits */ |
15ee95c3 MC |
2603 | err = tg3_phy_auxctl_read(tp, |
2604 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2605 | if (!err) | |
b4bd2929 MC |
2606 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
2607 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); | |
1da177e4 LT |
2608 | } |
2609 | ||
2610 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2611 | * jumbo frames transmission. | |
2612 | */ | |
63c3a66f | 2613 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
f833c4c1 | 2614 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2615 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2616 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2617 | } |
2618 | ||
715116a1 | 2619 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2620 | /* adjust output voltage */ |
535ef6e1 | 2621 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2622 | } |
2623 | ||
9ef8ca99 | 2624 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2625 | tg3_phy_set_wirespeed(tp); |
2626 | return 0; | |
2627 | } | |
2628 | ||
3a1e19d3 MC |
2629 | #define TG3_GPIO_MSG_DRVR_PRES 0x00000001 |
2630 | #define TG3_GPIO_MSG_NEED_VAUX 0x00000002 | |
2631 | #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \ | |
2632 | TG3_GPIO_MSG_NEED_VAUX) | |
2633 | #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \ | |
2634 | ((TG3_GPIO_MSG_DRVR_PRES << 0) | \ | |
2635 | (TG3_GPIO_MSG_DRVR_PRES << 4) | \ | |
2636 | (TG3_GPIO_MSG_DRVR_PRES << 8) | \ | |
2637 | (TG3_GPIO_MSG_DRVR_PRES << 12)) | |
2638 | ||
2639 | #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \ | |
2640 | ((TG3_GPIO_MSG_NEED_VAUX << 0) | \ | |
2641 | (TG3_GPIO_MSG_NEED_VAUX << 4) | \ | |
2642 | (TG3_GPIO_MSG_NEED_VAUX << 8) | \ | |
2643 | (TG3_GPIO_MSG_NEED_VAUX << 12)) | |
2644 | ||
2645 | static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) | |
2646 | { | |
2647 | u32 status, shift; | |
2648 | ||
2649 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2650 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2651 | status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); | |
2652 | else | |
2653 | status = tr32(TG3_CPMU_DRV_STATUS); | |
2654 | ||
2655 | shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; | |
2656 | status &= ~(TG3_GPIO_MSG_MASK << shift); | |
2657 | status |= (newstat << shift); | |
2658 | ||
2659 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2660 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
2661 | tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); | |
2662 | else | |
2663 | tw32(TG3_CPMU_DRV_STATUS, status); | |
2664 | ||
2665 | return status >> TG3_APE_GPIO_MSG_SHIFT; | |
2666 | } | |
2667 | ||
520b2756 MC |
2668 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) |
2669 | { | |
2670 | if (!tg3_flag(tp, IS_NIC)) | |
2671 | return 0; | |
2672 | ||
3a1e19d3 MC |
2673 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2674 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2675 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
2676 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2677 | return -EIO; | |
520b2756 | 2678 | |
3a1e19d3 MC |
2679 | tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); |
2680 | ||
2681 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2682 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2683 | ||
2684 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); | |
2685 | } else { | |
2686 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, | |
2687 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2688 | } | |
6f5c8f83 | 2689 | |
520b2756 MC |
2690 | return 0; |
2691 | } | |
2692 | ||
2693 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) | |
2694 | { | |
2695 | u32 grc_local_ctrl; | |
2696 | ||
2697 | if (!tg3_flag(tp, IS_NIC) || | |
2698 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2699 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) | |
2700 | return; | |
2701 | ||
2702 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; | |
2703 | ||
2704 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2705 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2706 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2707 | ||
2708 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2709 | grc_local_ctrl, | |
2710 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2711 | ||
2712 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2713 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, | |
2714 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2715 | } | |
2716 | ||
2717 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) | |
2718 | { | |
2719 | if (!tg3_flag(tp, IS_NIC)) | |
2720 | return; | |
2721 | ||
2722 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2723 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2724 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2725 | (GRC_LCLCTRL_GPIO_OE0 | | |
2726 | GRC_LCLCTRL_GPIO_OE1 | | |
2727 | GRC_LCLCTRL_GPIO_OE2 | | |
2728 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2729 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2730 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2731 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
2732 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
2733 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
2734 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2735 | GRC_LCLCTRL_GPIO_OE1 | | |
2736 | GRC_LCLCTRL_GPIO_OE2 | | |
2737 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2738 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2739 | tp->grc_local_ctrl; | |
2740 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2741 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2742 | ||
2743 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2744 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2745 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2746 | ||
2747 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2748 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, | |
2749 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2750 | } else { | |
2751 | u32 no_gpio2; | |
2752 | u32 grc_local_ctrl = 0; | |
2753 | ||
2754 | /* Workaround to prevent overdrawing Amps. */ | |
2755 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
2756 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
2757 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2758 | grc_local_ctrl, | |
2759 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2760 | } | |
2761 | ||
2762 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
2763 | no_gpio2 = tp->nic_sram_data_cfg & | |
2764 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2765 | ||
2766 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
2767 | GRC_LCLCTRL_GPIO_OE1 | | |
2768 | GRC_LCLCTRL_GPIO_OE2 | | |
2769 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2770 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2771 | if (no_gpio2) { | |
2772 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2773 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2774 | } | |
2775 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2776 | tp->grc_local_ctrl | grc_local_ctrl, | |
2777 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2778 | ||
2779 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2780 | ||
2781 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2782 | tp->grc_local_ctrl | grc_local_ctrl, | |
2783 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2784 | ||
2785 | if (!no_gpio2) { | |
2786 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2787 | tw32_wait_f(GRC_LOCAL_CTRL, | |
2788 | tp->grc_local_ctrl | grc_local_ctrl, | |
2789 | TG3_GRC_LCLCTL_PWRSW_DELAY); | |
2790 | } | |
2791 | } | |
3a1e19d3 MC |
2792 | } |
2793 | ||
cd0d7228 | 2794 | static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) |
3a1e19d3 MC |
2795 | { |
2796 | u32 msg = 0; | |
2797 | ||
2798 | /* Serialize power state transitions */ | |
2799 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | |
2800 | return; | |
2801 | ||
cd0d7228 | 2802 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) |
3a1e19d3 MC |
2803 | msg = TG3_GPIO_MSG_NEED_VAUX; |
2804 | ||
2805 | msg = tg3_set_function_status(tp, msg); | |
2806 | ||
2807 | if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK) | |
2808 | goto done; | |
6f5c8f83 | 2809 | |
3a1e19d3 MC |
2810 | if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK) |
2811 | tg3_pwrsrc_switch_to_vaux(tp); | |
2812 | else | |
2813 | tg3_pwrsrc_die_with_vmain(tp); | |
2814 | ||
2815 | done: | |
6f5c8f83 | 2816 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); |
520b2756 MC |
2817 | } |
2818 | ||
cd0d7228 | 2819 | static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) |
1da177e4 | 2820 | { |
683644b7 | 2821 | bool need_vaux = false; |
1da177e4 | 2822 | |
334355aa | 2823 | /* The GPIOs do something completely different on 57765. */ |
55086ad9 | 2824 | if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) |
1da177e4 LT |
2825 | return; |
2826 | ||
3a1e19d3 MC |
2827 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2828 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2829 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
cd0d7228 MC |
2830 | tg3_frob_aux_power_5717(tp, include_wol ? |
2831 | tg3_flag(tp, WOL_ENABLE) != 0 : 0); | |
3a1e19d3 MC |
2832 | return; |
2833 | } | |
2834 | ||
2835 | if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { | |
8c2dc7e1 MC |
2836 | struct net_device *dev_peer; |
2837 | ||
2838 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2839 | |
bc1c7567 | 2840 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2841 | if (dev_peer) { |
2842 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2843 | ||
63c3a66f | 2844 | if (tg3_flag(tp_peer, INIT_COMPLETE)) |
683644b7 MC |
2845 | return; |
2846 | ||
cd0d7228 | 2847 | if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) || |
63c3a66f | 2848 | tg3_flag(tp_peer, ENABLE_ASF)) |
683644b7 MC |
2849 | need_vaux = true; |
2850 | } | |
1da177e4 LT |
2851 | } |
2852 | ||
cd0d7228 MC |
2853 | if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || |
2854 | tg3_flag(tp, ENABLE_ASF)) | |
683644b7 MC |
2855 | need_vaux = true; |
2856 | ||
520b2756 MC |
2857 | if (need_vaux) |
2858 | tg3_pwrsrc_switch_to_vaux(tp); | |
2859 | else | |
2860 | tg3_pwrsrc_die_with_vmain(tp); | |
1da177e4 LT |
2861 | } |
2862 | ||
e8f3f6ca MC |
2863 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2864 | { | |
2865 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2866 | return 1; | |
79eb6904 | 2867 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2868 | if (speed != SPEED_10) |
2869 | return 1; | |
2870 | } else if (speed == SPEED_10) | |
2871 | return 1; | |
2872 | ||
2873 | return 0; | |
2874 | } | |
2875 | ||
0a459aac | 2876 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2877 | { |
ce057f01 MC |
2878 | u32 val; |
2879 | ||
f07e9af3 | 2880 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2881 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2882 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2883 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2884 | ||
2885 | sg_dig_ctrl |= | |
2886 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2887 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2888 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2889 | } | |
3f7045c1 | 2890 | return; |
5129724a | 2891 | } |
3f7045c1 | 2892 | |
60189ddf | 2893 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2894 | tg3_bmcr_reset(tp); |
2895 | val = tr32(GRC_MISC_CFG); | |
2896 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2897 | udelay(40); | |
2898 | return; | |
f07e9af3 | 2899 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2900 | u32 phytest; |
2901 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2902 | u32 phy; | |
2903 | ||
2904 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2905 | tg3_writephy(tp, MII_BMCR, | |
2906 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2907 | ||
2908 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2909 | phytest | MII_TG3_FET_SHADOW_EN); | |
2910 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2911 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2912 | tg3_writephy(tp, | |
2913 | MII_TG3_FET_SHDW_AUXMODE4, | |
2914 | phy); | |
2915 | } | |
2916 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2917 | } | |
2918 | return; | |
0a459aac | 2919 | } else if (do_low_power) { |
715116a1 MC |
2920 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2921 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac | 2922 | |
b4bd2929 MC |
2923 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
2924 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2925 | MII_TG3_AUXCTL_PCTL_VREG_11V; | |
2926 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); | |
715116a1 | 2927 | } |
3f7045c1 | 2928 | |
15c3b696 MC |
2929 | /* The PHY should not be powered down on some chips because |
2930 | * of bugs. | |
2931 | */ | |
2932 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2933 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2934 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
085f1afc MC |
2935 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) || |
2936 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | |
2937 | !tp->pci_fn)) | |
15c3b696 | 2938 | return; |
ce057f01 | 2939 | |
bcb37f6c MC |
2940 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2941 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2942 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2943 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2944 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2945 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2946 | } | |
2947 | ||
15c3b696 MC |
2948 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2949 | } | |
2950 | ||
ffbcfed4 MC |
2951 | /* tp->lock is held. */ |
2952 | static int tg3_nvram_lock(struct tg3 *tp) | |
2953 | { | |
63c3a66f | 2954 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2955 | int i; |
2956 | ||
2957 | if (tp->nvram_lock_cnt == 0) { | |
2958 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2959 | for (i = 0; i < 8000; i++) { | |
2960 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2961 | break; | |
2962 | udelay(20); | |
2963 | } | |
2964 | if (i == 8000) { | |
2965 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2966 | return -ENODEV; | |
2967 | } | |
2968 | } | |
2969 | tp->nvram_lock_cnt++; | |
2970 | } | |
2971 | return 0; | |
2972 | } | |
2973 | ||
2974 | /* tp->lock is held. */ | |
2975 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2976 | { | |
63c3a66f | 2977 | if (tg3_flag(tp, NVRAM)) { |
ffbcfed4 MC |
2978 | if (tp->nvram_lock_cnt > 0) |
2979 | tp->nvram_lock_cnt--; | |
2980 | if (tp->nvram_lock_cnt == 0) | |
2981 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2982 | } | |
2983 | } | |
2984 | ||
2985 | /* tp->lock is held. */ | |
2986 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2987 | { | |
63c3a66f | 2988 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2989 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2990 | ||
2991 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2992 | } | |
2993 | } | |
2994 | ||
2995 | /* tp->lock is held. */ | |
2996 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2997 | { | |
63c3a66f | 2998 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2999 | u32 nvaccess = tr32(NVRAM_ACCESS); |
3000 | ||
3001 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
3002 | } | |
3003 | } | |
3004 | ||
3005 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
3006 | u32 offset, u32 *val) | |
3007 | { | |
3008 | u32 tmp; | |
3009 | int i; | |
3010 | ||
3011 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
3012 | return -EINVAL; | |
3013 | ||
3014 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
3015 | EEPROM_ADDR_DEVID_MASK | | |
3016 | EEPROM_ADDR_READ); | |
3017 | tw32(GRC_EEPROM_ADDR, | |
3018 | tmp | | |
3019 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
3020 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
3021 | EEPROM_ADDR_ADDR_MASK) | | |
3022 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
3023 | ||
3024 | for (i = 0; i < 1000; i++) { | |
3025 | tmp = tr32(GRC_EEPROM_ADDR); | |
3026 | ||
3027 | if (tmp & EEPROM_ADDR_COMPLETE) | |
3028 | break; | |
3029 | msleep(1); | |
3030 | } | |
3031 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
3032 | return -EBUSY; | |
3033 | ||
62cedd11 MC |
3034 | tmp = tr32(GRC_EEPROM_DATA); |
3035 | ||
3036 | /* | |
3037 | * The data will always be opposite the native endian | |
3038 | * format. Perform a blind byteswap to compensate. | |
3039 | */ | |
3040 | *val = swab32(tmp); | |
3041 | ||
ffbcfed4 MC |
3042 | return 0; |
3043 | } | |
3044 | ||
3045 | #define NVRAM_CMD_TIMEOUT 10000 | |
3046 | ||
3047 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
3048 | { | |
3049 | int i; | |
3050 | ||
3051 | tw32(NVRAM_CMD, nvram_cmd); | |
3052 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
3053 | udelay(10); | |
3054 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
3055 | udelay(10); | |
3056 | break; | |
3057 | } | |
3058 | } | |
3059 | ||
3060 | if (i == NVRAM_CMD_TIMEOUT) | |
3061 | return -EBUSY; | |
3062 | ||
3063 | return 0; | |
3064 | } | |
3065 | ||
3066 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
3067 | { | |
63c3a66f JP |
3068 | if (tg3_flag(tp, NVRAM) && |
3069 | tg3_flag(tp, NVRAM_BUFFERED) && | |
3070 | tg3_flag(tp, FLASH) && | |
3071 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
3072 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
3073 | ||
3074 | addr = ((addr / tp->nvram_pagesize) << | |
3075 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
3076 | (addr % tp->nvram_pagesize); | |
3077 | ||
3078 | return addr; | |
3079 | } | |
3080 | ||
3081 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
3082 | { | |
63c3a66f JP |
3083 | if (tg3_flag(tp, NVRAM) && |
3084 | tg3_flag(tp, NVRAM_BUFFERED) && | |
3085 | tg3_flag(tp, FLASH) && | |
3086 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
ffbcfed4 MC |
3087 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
3088 | ||
3089 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
3090 | tp->nvram_pagesize) + | |
3091 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
3092 | ||
3093 | return addr; | |
3094 | } | |
3095 | ||
e4f34110 MC |
3096 | /* NOTE: Data read in from NVRAM is byteswapped according to |
3097 | * the byteswapping settings for all other register accesses. | |
3098 | * tg3 devices are BE devices, so on a BE machine, the data | |
3099 | * returned will be exactly as it is seen in NVRAM. On a LE | |
3100 | * machine, the 32-bit value will be byteswapped. | |
3101 | */ | |
ffbcfed4 MC |
3102 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
3103 | { | |
3104 | int ret; | |
3105 | ||
63c3a66f | 3106 | if (!tg3_flag(tp, NVRAM)) |
ffbcfed4 MC |
3107 | return tg3_nvram_read_using_eeprom(tp, offset, val); |
3108 | ||
3109 | offset = tg3_nvram_phys_addr(tp, offset); | |
3110 | ||
3111 | if (offset > NVRAM_ADDR_MSK) | |
3112 | return -EINVAL; | |
3113 | ||
3114 | ret = tg3_nvram_lock(tp); | |
3115 | if (ret) | |
3116 | return ret; | |
3117 | ||
3118 | tg3_enable_nvram_access(tp); | |
3119 | ||
3120 | tw32(NVRAM_ADDR, offset); | |
3121 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
3122 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
3123 | ||
3124 | if (ret == 0) | |
e4f34110 | 3125 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
3126 | |
3127 | tg3_disable_nvram_access(tp); | |
3128 | ||
3129 | tg3_nvram_unlock(tp); | |
3130 | ||
3131 | return ret; | |
3132 | } | |
3133 | ||
a9dc529d MC |
3134 | /* Ensures NVRAM data is in bytestream format. */ |
3135 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
3136 | { |
3137 | u32 v; | |
a9dc529d | 3138 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 3139 | if (!res) |
a9dc529d | 3140 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
3141 | return res; |
3142 | } | |
3143 | ||
dbe9b92a MC |
3144 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
3145 | u32 offset, u32 len, u8 *buf) | |
3146 | { | |
3147 | int i, j, rc = 0; | |
3148 | u32 val; | |
3149 | ||
3150 | for (i = 0; i < len; i += 4) { | |
3151 | u32 addr; | |
3152 | __be32 data; | |
3153 | ||
3154 | addr = offset + i; | |
3155 | ||
3156 | memcpy(&data, buf + i, 4); | |
3157 | ||
3158 | /* | |
3159 | * The SEEPROM interface expects the data to always be opposite | |
3160 | * the native endian format. We accomplish this by reversing | |
3161 | * all the operations that would have been performed on the | |
3162 | * data from a call to tg3_nvram_read_be32(). | |
3163 | */ | |
3164 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
3165 | ||
3166 | val = tr32(GRC_EEPROM_ADDR); | |
3167 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
3168 | ||
3169 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
3170 | EEPROM_ADDR_READ); | |
3171 | tw32(GRC_EEPROM_ADDR, val | | |
3172 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
3173 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
3174 | EEPROM_ADDR_START | | |
3175 | EEPROM_ADDR_WRITE); | |
3176 | ||
3177 | for (j = 0; j < 1000; j++) { | |
3178 | val = tr32(GRC_EEPROM_ADDR); | |
3179 | ||
3180 | if (val & EEPROM_ADDR_COMPLETE) | |
3181 | break; | |
3182 | msleep(1); | |
3183 | } | |
3184 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
3185 | rc = -EBUSY; | |
3186 | break; | |
3187 | } | |
3188 | } | |
3189 | ||
3190 | return rc; | |
3191 | } | |
3192 | ||
3193 | /* offset and length are dword aligned */ | |
3194 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
3195 | u8 *buf) | |
3196 | { | |
3197 | int ret = 0; | |
3198 | u32 pagesize = tp->nvram_pagesize; | |
3199 | u32 pagemask = pagesize - 1; | |
3200 | u32 nvram_cmd; | |
3201 | u8 *tmp; | |
3202 | ||
3203 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
3204 | if (tmp == NULL) | |
3205 | return -ENOMEM; | |
3206 | ||
3207 | while (len) { | |
3208 | int j; | |
3209 | u32 phy_addr, page_off, size; | |
3210 | ||
3211 | phy_addr = offset & ~pagemask; | |
3212 | ||
3213 | for (j = 0; j < pagesize; j += 4) { | |
3214 | ret = tg3_nvram_read_be32(tp, phy_addr + j, | |
3215 | (__be32 *) (tmp + j)); | |
3216 | if (ret) | |
3217 | break; | |
3218 | } | |
3219 | if (ret) | |
3220 | break; | |
3221 | ||
3222 | page_off = offset & pagemask; | |
3223 | size = pagesize; | |
3224 | if (len < size) | |
3225 | size = len; | |
3226 | ||
3227 | len -= size; | |
3228 | ||
3229 | memcpy(tmp + page_off, buf, size); | |
3230 | ||
3231 | offset = offset + (pagesize - page_off); | |
3232 | ||
3233 | tg3_enable_nvram_access(tp); | |
3234 | ||
3235 | /* | |
3236 | * Before we can erase the flash page, we need | |
3237 | * to issue a special "write enable" command. | |
3238 | */ | |
3239 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3240 | ||
3241 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
3242 | break; | |
3243 | ||
3244 | /* Erase the target page */ | |
3245 | tw32(NVRAM_ADDR, phy_addr); | |
3246 | ||
3247 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
3248 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
3249 | ||
3250 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
3251 | break; | |
3252 | ||
3253 | /* Issue another write enable to start the write. */ | |
3254 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3255 | ||
3256 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
3257 | break; | |
3258 | ||
3259 | for (j = 0; j < pagesize; j += 4) { | |
3260 | __be32 data; | |
3261 | ||
3262 | data = *((__be32 *) (tmp + j)); | |
3263 | ||
3264 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
3265 | ||
3266 | tw32(NVRAM_ADDR, phy_addr + j); | |
3267 | ||
3268 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
3269 | NVRAM_CMD_WR; | |
3270 | ||
3271 | if (j == 0) | |
3272 | nvram_cmd |= NVRAM_CMD_FIRST; | |
3273 | else if (j == (pagesize - 4)) | |
3274 | nvram_cmd |= NVRAM_CMD_LAST; | |
3275 | ||
3276 | ret = tg3_nvram_exec_cmd(tp, nvram_cmd); | |
3277 | if (ret) | |
3278 | break; | |
3279 | } | |
3280 | if (ret) | |
3281 | break; | |
3282 | } | |
3283 | ||
3284 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3285 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
3286 | ||
3287 | kfree(tmp); | |
3288 | ||
3289 | return ret; | |
3290 | } | |
3291 | ||
3292 | /* offset and length are dword aligned */ | |
3293 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
3294 | u8 *buf) | |
3295 | { | |
3296 | int i, ret = 0; | |
3297 | ||
3298 | for (i = 0; i < len; i += 4, offset += 4) { | |
3299 | u32 page_off, phy_addr, nvram_cmd; | |
3300 | __be32 data; | |
3301 | ||
3302 | memcpy(&data, buf + i, 4); | |
3303 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
3304 | ||
3305 | page_off = offset % tp->nvram_pagesize; | |
3306 | ||
3307 | phy_addr = tg3_nvram_phys_addr(tp, offset); | |
3308 | ||
dbe9b92a MC |
3309 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; |
3310 | ||
3311 | if (page_off == 0 || i == 0) | |
3312 | nvram_cmd |= NVRAM_CMD_FIRST; | |
3313 | if (page_off == (tp->nvram_pagesize - 4)) | |
3314 | nvram_cmd |= NVRAM_CMD_LAST; | |
3315 | ||
3316 | if (i == (len - 4)) | |
3317 | nvram_cmd |= NVRAM_CMD_LAST; | |
3318 | ||
42278224 MC |
3319 | if ((nvram_cmd & NVRAM_CMD_FIRST) || |
3320 | !tg3_flag(tp, FLASH) || | |
3321 | !tg3_flag(tp, 57765_PLUS)) | |
3322 | tw32(NVRAM_ADDR, phy_addr); | |
3323 | ||
dbe9b92a MC |
3324 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
3325 | !tg3_flag(tp, 5755_PLUS) && | |
3326 | (tp->nvram_jedecnum == JEDEC_ST) && | |
3327 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
3328 | u32 cmd; | |
3329 | ||
3330 | cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
3331 | ret = tg3_nvram_exec_cmd(tp, cmd); | |
3332 | if (ret) | |
3333 | break; | |
3334 | } | |
3335 | if (!tg3_flag(tp, FLASH)) { | |
3336 | /* We always do complete word writes to eeprom. */ | |
3337 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
3338 | } | |
3339 | ||
3340 | ret = tg3_nvram_exec_cmd(tp, nvram_cmd); | |
3341 | if (ret) | |
3342 | break; | |
3343 | } | |
3344 | return ret; | |
3345 | } | |
3346 | ||
3347 | /* offset and length are dword aligned */ | |
3348 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
3349 | { | |
3350 | int ret; | |
3351 | ||
3352 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { | |
3353 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & | |
3354 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
3355 | udelay(40); | |
3356 | } | |
3357 | ||
3358 | if (!tg3_flag(tp, NVRAM)) { | |
3359 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
3360 | } else { | |
3361 | u32 grc_mode; | |
3362 | ||
3363 | ret = tg3_nvram_lock(tp); | |
3364 | if (ret) | |
3365 | return ret; | |
3366 | ||
3367 | tg3_enable_nvram_access(tp); | |
3368 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) | |
3369 | tw32(NVRAM_WRITE1, 0x406); | |
3370 | ||
3371 | grc_mode = tr32(GRC_MODE); | |
3372 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
3373 | ||
3374 | if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { | |
3375 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
3376 | buf); | |
3377 | } else { | |
3378 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, | |
3379 | buf); | |
3380 | } | |
3381 | ||
3382 | grc_mode = tr32(GRC_MODE); | |
3383 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
3384 | ||
3385 | tg3_disable_nvram_access(tp); | |
3386 | tg3_nvram_unlock(tp); | |
3387 | } | |
3388 | ||
3389 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { | |
3390 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
3391 | udelay(40); | |
3392 | } | |
3393 | ||
3394 | return ret; | |
3395 | } | |
3396 | ||
997b4f13 MC |
3397 | #define RX_CPU_SCRATCH_BASE 0x30000 |
3398 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
3399 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
3400 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
3401 | ||
3402 | /* tp->lock is held. */ | |
3403 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
3404 | { | |
3405 | int i; | |
3406 | ||
3407 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); | |
3408 | ||
3409 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
3410 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
3411 | ||
3412 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
3413 | return 0; | |
3414 | } | |
3415 | if (offset == RX_CPU_BASE) { | |
3416 | for (i = 0; i < 10000; i++) { | |
3417 | tw32(offset + CPU_STATE, 0xffffffff); | |
3418 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
3419 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
3420 | break; | |
3421 | } | |
3422 | ||
3423 | tw32(offset + CPU_STATE, 0xffffffff); | |
3424 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
3425 | udelay(10); | |
3426 | } else { | |
3427 | for (i = 0; i < 10000; i++) { | |
3428 | tw32(offset + CPU_STATE, 0xffffffff); | |
3429 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
3430 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
3431 | break; | |
3432 | } | |
3433 | } | |
3434 | ||
3435 | if (i >= 10000) { | |
3436 | netdev_err(tp->dev, "%s timed out, %s CPU\n", | |
3437 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
3438 | return -ENODEV; | |
3439 | } | |
3440 | ||
3441 | /* Clear firmware's nvram arbitration. */ | |
3442 | if (tg3_flag(tp, NVRAM)) | |
3443 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
3444 | return 0; | |
3445 | } | |
3446 | ||
3447 | struct fw_info { | |
3448 | unsigned int fw_base; | |
3449 | unsigned int fw_len; | |
3450 | const __be32 *fw_data; | |
3451 | }; | |
3452 | ||
3453 | /* tp->lock is held. */ | |
3454 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, | |
3455 | u32 cpu_scratch_base, int cpu_scratch_size, | |
3456 | struct fw_info *info) | |
3457 | { | |
3458 | int err, lock_err, i; | |
3459 | void (*write_op)(struct tg3 *, u32, u32); | |
3460 | ||
3461 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { | |
3462 | netdev_err(tp->dev, | |
3463 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
3464 | __func__); | |
3465 | return -EINVAL; | |
3466 | } | |
3467 | ||
3468 | if (tg3_flag(tp, 5705_PLUS)) | |
3469 | write_op = tg3_write_mem; | |
3470 | else | |
3471 | write_op = tg3_write_indirect_reg32; | |
3472 | ||
3473 | /* It is possible that bootcode is still loading at this point. | |
3474 | * Get the nvram lock first before halting the cpu. | |
3475 | */ | |
3476 | lock_err = tg3_nvram_lock(tp); | |
3477 | err = tg3_halt_cpu(tp, cpu_base); | |
3478 | if (!lock_err) | |
3479 | tg3_nvram_unlock(tp); | |
3480 | if (err) | |
3481 | goto out; | |
3482 | ||
3483 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
3484 | write_op(tp, cpu_scratch_base + i, 0); | |
3485 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3486 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
3487 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) | |
3488 | write_op(tp, (cpu_scratch_base + | |
3489 | (info->fw_base & 0xffff) + | |
3490 | (i * sizeof(u32))), | |
3491 | be32_to_cpu(info->fw_data[i])); | |
3492 | ||
3493 | err = 0; | |
3494 | ||
3495 | out: | |
3496 | return err; | |
3497 | } | |
3498 | ||
3499 | /* tp->lock is held. */ | |
3500 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
3501 | { | |
3502 | struct fw_info info; | |
3503 | const __be32 *fw_data; | |
3504 | int err, i; | |
3505 | ||
3506 | fw_data = (void *)tp->fw->data; | |
3507 | ||
3508 | /* Firmware blob starts with version numbers, followed by | |
3509 | start address and length. We are setting complete length. | |
3510 | length = end_address_of_bss - start_address_of_text. | |
3511 | Remainder is the blob to be loaded contiguously | |
3512 | from start address. */ | |
3513 | ||
3514 | info.fw_base = be32_to_cpu(fw_data[1]); | |
3515 | info.fw_len = tp->fw->size - 12; | |
3516 | info.fw_data = &fw_data[3]; | |
3517 | ||
3518 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
3519 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
3520 | &info); | |
3521 | if (err) | |
3522 | return err; | |
3523 | ||
3524 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
3525 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
3526 | &info); | |
3527 | if (err) | |
3528 | return err; | |
3529 | ||
3530 | /* Now startup only the RX cpu. */ | |
3531 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3532 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
3533 | ||
3534 | for (i = 0; i < 5; i++) { | |
3535 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) | |
3536 | break; | |
3537 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3538 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
3539 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
3540 | udelay(1000); | |
3541 | } | |
3542 | if (i >= 5) { | |
3543 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " | |
3544 | "should be %08x\n", __func__, | |
3545 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); | |
3546 | return -ENODEV; | |
3547 | } | |
3548 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
3549 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
3550 | ||
3551 | return 0; | |
3552 | } | |
3553 | ||
3554 | /* tp->lock is held. */ | |
3555 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
3556 | { | |
3557 | struct fw_info info; | |
3558 | const __be32 *fw_data; | |
3559 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; | |
3560 | int err, i; | |
3561 | ||
3562 | if (tg3_flag(tp, HW_TSO_1) || | |
3563 | tg3_flag(tp, HW_TSO_2) || | |
3564 | tg3_flag(tp, HW_TSO_3)) | |
3565 | return 0; | |
3566 | ||
3567 | fw_data = (void *)tp->fw->data; | |
3568 | ||
3569 | /* Firmware blob starts with version numbers, followed by | |
3570 | start address and length. We are setting complete length. | |
3571 | length = end_address_of_bss - start_address_of_text. | |
3572 | Remainder is the blob to be loaded contiguously | |
3573 | from start address. */ | |
3574 | ||
3575 | info.fw_base = be32_to_cpu(fw_data[1]); | |
3576 | cpu_scratch_size = tp->fw_len; | |
3577 | info.fw_len = tp->fw->size - 12; | |
3578 | info.fw_data = &fw_data[3]; | |
3579 | ||
3580 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
3581 | cpu_base = RX_CPU_BASE; | |
3582 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
3583 | } else { | |
3584 | cpu_base = TX_CPU_BASE; | |
3585 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
3586 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
3587 | } | |
3588 | ||
3589 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
3590 | cpu_scratch_base, cpu_scratch_size, | |
3591 | &info); | |
3592 | if (err) | |
3593 | return err; | |
3594 | ||
3595 | /* Now startup the cpu. */ | |
3596 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3597 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
3598 | ||
3599 | for (i = 0; i < 5; i++) { | |
3600 | if (tr32(cpu_base + CPU_PC) == info.fw_base) | |
3601 | break; | |
3602 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3603 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
3604 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
3605 | udelay(1000); | |
3606 | } | |
3607 | if (i >= 5) { | |
3608 | netdev_err(tp->dev, | |
3609 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
3610 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); | |
3611 | return -ENODEV; | |
3612 | } | |
3613 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
3614 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
3615 | return 0; | |
3616 | } | |
3617 | ||
3618 | ||
3f007891 MC |
3619 | /* tp->lock is held. */ |
3620 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
3621 | { | |
3622 | u32 addr_high, addr_low; | |
3623 | int i; | |
3624 | ||
3625 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
3626 | tp->dev->dev_addr[1]); | |
3627 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
3628 | (tp->dev->dev_addr[3] << 16) | | |
3629 | (tp->dev->dev_addr[4] << 8) | | |
3630 | (tp->dev->dev_addr[5] << 0)); | |
3631 | for (i = 0; i < 4; i++) { | |
3632 | if (i == 1 && skip_mac_1) | |
3633 | continue; | |
3634 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
3635 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
3636 | } | |
3637 | ||
3638 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3639 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
3640 | for (i = 0; i < 12; i++) { | |
3641 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
3642 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
3643 | } | |
3644 | } | |
3645 | ||
3646 | addr_high = (tp->dev->dev_addr[0] + | |
3647 | tp->dev->dev_addr[1] + | |
3648 | tp->dev->dev_addr[2] + | |
3649 | tp->dev->dev_addr[3] + | |
3650 | tp->dev->dev_addr[4] + | |
3651 | tp->dev->dev_addr[5]) & | |
3652 | TX_BACKOFF_SEED_MASK; | |
3653 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
3654 | } | |
3655 | ||
c866b7ea | 3656 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 3657 | { |
c866b7ea RW |
3658 | /* |
3659 | * Make sure register accesses (indirect or otherwise) will function | |
3660 | * correctly. | |
1da177e4 LT |
3661 | */ |
3662 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
3663 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
3664 | } | |
1da177e4 | 3665 | |
c866b7ea RW |
3666 | static int tg3_power_up(struct tg3 *tp) |
3667 | { | |
bed9829f | 3668 | int err; |
8c6bda1a | 3669 | |
bed9829f | 3670 | tg3_enable_register_access(tp); |
1da177e4 | 3671 | |
bed9829f MC |
3672 | err = pci_set_power_state(tp->pdev, PCI_D0); |
3673 | if (!err) { | |
3674 | /* Switch out of Vaux if it is a NIC */ | |
3675 | tg3_pwrsrc_switch_to_vmain(tp); | |
3676 | } else { | |
3677 | netdev_err(tp->dev, "Transition to D0 failed\n"); | |
3678 | } | |
1da177e4 | 3679 | |
bed9829f | 3680 | return err; |
c866b7ea | 3681 | } |
1da177e4 | 3682 | |
4b409522 MC |
3683 | static int tg3_setup_phy(struct tg3 *, int); |
3684 | ||
c866b7ea RW |
3685 | static int tg3_power_down_prepare(struct tg3 *tp) |
3686 | { | |
3687 | u32 misc_host_ctrl; | |
3688 | bool device_should_wake, do_low_power; | |
3689 | ||
3690 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
3691 | |
3692 | /* Restore the CLKREQ setting. */ | |
0f49bfbd JL |
3693 | if (tg3_flag(tp, CLKREQ_BUG)) |
3694 | pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, | |
3695 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
5e7dfd0f | 3696 | |
1da177e4 LT |
3697 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
3698 | tw32(TG3PCI_MISC_HOST_CTRL, | |
3699 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
3700 | ||
c866b7ea | 3701 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
63c3a66f | 3702 | tg3_flag(tp, WOL_ENABLE); |
05ac4cb7 | 3703 | |
63c3a66f | 3704 | if (tg3_flag(tp, USE_PHYLIB)) { |
0a459aac | 3705 | do_low_power = false; |
f07e9af3 | 3706 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 3707 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 3708 | struct phy_device *phydev; |
0a459aac | 3709 | u32 phyid, advertising; |
b02fd9e3 | 3710 | |
3f0e3ad7 | 3711 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 3712 | |
80096068 | 3713 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 | 3714 | |
c6700ce2 MC |
3715 | tp->link_config.speed = phydev->speed; |
3716 | tp->link_config.duplex = phydev->duplex; | |
3717 | tp->link_config.autoneg = phydev->autoneg; | |
3718 | tp->link_config.advertising = phydev->advertising; | |
b02fd9e3 MC |
3719 | |
3720 | advertising = ADVERTISED_TP | | |
3721 | ADVERTISED_Pause | | |
3722 | ADVERTISED_Autoneg | | |
3723 | ADVERTISED_10baseT_Half; | |
3724 | ||
63c3a66f JP |
3725 | if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { |
3726 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
b02fd9e3 MC |
3727 | advertising |= |
3728 | ADVERTISED_100baseT_Half | | |
3729 | ADVERTISED_100baseT_Full | | |
3730 | ADVERTISED_10baseT_Full; | |
3731 | else | |
3732 | advertising |= ADVERTISED_10baseT_Full; | |
3733 | } | |
3734 | ||
3735 | phydev->advertising = advertising; | |
3736 | ||
3737 | phy_start_aneg(phydev); | |
0a459aac MC |
3738 | |
3739 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
3740 | if (phyid != PHY_ID_BCMAC131) { |
3741 | phyid &= PHY_BCM_OUI_MASK; | |
3742 | if (phyid == PHY_BCM_OUI_1 || | |
3743 | phyid == PHY_BCM_OUI_2 || | |
3744 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
3745 | do_low_power = true; |
3746 | } | |
b02fd9e3 | 3747 | } |
dd477003 | 3748 | } else { |
2023276e | 3749 | do_low_power = true; |
0a459aac | 3750 | |
c6700ce2 | 3751 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) |
80096068 | 3752 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
1da177e4 | 3753 | |
2855b9fe | 3754 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
dd477003 | 3755 | tg3_setup_phy(tp, 0); |
1da177e4 LT |
3756 | } |
3757 | ||
b5d3772c MC |
3758 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
3759 | u32 val; | |
3760 | ||
3761 | val = tr32(GRC_VCPU_EXT_CTRL); | |
3762 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
63c3a66f | 3763 | } else if (!tg3_flag(tp, ENABLE_ASF)) { |
6921d201 MC |
3764 | int i; |
3765 | u32 val; | |
3766 | ||
3767 | for (i = 0; i < 200; i++) { | |
3768 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
3769 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
3770 | break; | |
3771 | msleep(1); | |
3772 | } | |
3773 | } | |
63c3a66f | 3774 | if (tg3_flag(tp, WOL_CAP)) |
a85feb8c GZ |
3775 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | |
3776 | WOL_DRV_STATE_SHUTDOWN | | |
3777 | WOL_DRV_WOL | | |
3778 | WOL_SET_MAGIC_PKT); | |
6921d201 | 3779 | |
05ac4cb7 | 3780 | if (device_should_wake) { |
1da177e4 LT |
3781 | u32 mac_mode; |
3782 | ||
f07e9af3 | 3783 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
b4bd2929 MC |
3784 | if (do_low_power && |
3785 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
3786 | tg3_phy_auxctl_write(tp, | |
3787 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, | |
3788 | MII_TG3_AUXCTL_PCTL_WOL_EN | | |
3789 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
3790 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); | |
dd477003 MC |
3791 | udelay(40); |
3792 | } | |
1da177e4 | 3793 | |
f07e9af3 | 3794 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
3795 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
3796 | else | |
3797 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 3798 | |
e8f3f6ca MC |
3799 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
3800 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
3801 | ASIC_REV_5700) { | |
63c3a66f | 3802 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? |
e8f3f6ca MC |
3803 | SPEED_100 : SPEED_10; |
3804 | if (tg3_5700_link_polarity(tp, speed)) | |
3805 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
3806 | else | |
3807 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
3808 | } | |
1da177e4 LT |
3809 | } else { |
3810 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
3811 | } | |
3812 | ||
63c3a66f | 3813 | if (!tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
3814 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
3815 | ||
05ac4cb7 | 3816 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
63c3a66f JP |
3817 | if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && |
3818 | (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) | |
05ac4cb7 | 3819 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; |
1da177e4 | 3820 | |
63c3a66f | 3821 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b MC |
3822 | mac_mode |= MAC_MODE_APE_TX_EN | |
3823 | MAC_MODE_APE_RX_EN | | |
3824 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 3825 | |
1da177e4 LT |
3826 | tw32_f(MAC_MODE, mac_mode); |
3827 | udelay(100); | |
3828 | ||
3829 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
3830 | udelay(10); | |
3831 | } | |
3832 | ||
63c3a66f | 3833 | if (!tg3_flag(tp, WOL_SPEED_100MB) && |
1da177e4 LT |
3834 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
3835 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
3836 | u32 base_val; | |
3837 | ||
3838 | base_val = tp->pci_clock_ctrl; | |
3839 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
3840 | CLOCK_CTRL_TXCLK_DISABLE); | |
3841 | ||
b401e9e2 MC |
3842 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
3843 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
63c3a66f JP |
3844 | } else if (tg3_flag(tp, 5780_CLASS) || |
3845 | tg3_flag(tp, CPMU_PRESENT) || | |
6ff6f81d | 3846 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
4cf78e4f | 3847 | /* do nothing */ |
63c3a66f | 3848 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { |
1da177e4 LT |
3849 | u32 newbits1, newbits2; |
3850 | ||
3851 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3852 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3853 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
3854 | CLOCK_CTRL_TXCLK_DISABLE | | |
3855 | CLOCK_CTRL_ALTCLK); | |
3856 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
63c3a66f | 3857 | } else if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
3858 | newbits1 = CLOCK_CTRL_625_CORE; |
3859 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
3860 | } else { | |
3861 | newbits1 = CLOCK_CTRL_ALTCLK; | |
3862 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
3863 | } | |
3864 | ||
b401e9e2 MC |
3865 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
3866 | 40); | |
1da177e4 | 3867 | |
b401e9e2 MC |
3868 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
3869 | 40); | |
1da177e4 | 3870 | |
63c3a66f | 3871 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
3872 | u32 newbits3; |
3873 | ||
3874 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3875 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3876 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
3877 | CLOCK_CTRL_TXCLK_DISABLE | | |
3878 | CLOCK_CTRL_44MHZ_CORE); | |
3879 | } else { | |
3880 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
3881 | } | |
3882 | ||
b401e9e2 MC |
3883 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
3884 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
3885 | } |
3886 | } | |
3887 | ||
63c3a66f | 3888 | if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) |
0a459aac | 3889 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 3890 | |
cd0d7228 | 3891 | tg3_frob_aux_power(tp, true); |
1da177e4 LT |
3892 | |
3893 | /* Workaround for unstable PLL clock */ | |
3894 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
3895 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
3896 | u32 val = tr32(0x7d00); | |
3897 | ||
3898 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
3899 | tw32(0x7d00, val); | |
63c3a66f | 3900 | if (!tg3_flag(tp, ENABLE_ASF)) { |
ec41c7df MC |
3901 | int err; |
3902 | ||
3903 | err = tg3_nvram_lock(tp); | |
1da177e4 | 3904 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
3905 | if (!err) |
3906 | tg3_nvram_unlock(tp); | |
6921d201 | 3907 | } |
1da177e4 LT |
3908 | } |
3909 | ||
bbadf503 MC |
3910 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
3911 | ||
c866b7ea RW |
3912 | return 0; |
3913 | } | |
12dac075 | 3914 | |
c866b7ea RW |
3915 | static void tg3_power_down(struct tg3 *tp) |
3916 | { | |
3917 | tg3_power_down_prepare(tp); | |
1da177e4 | 3918 | |
63c3a66f | 3919 | pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); |
c866b7ea | 3920 | pci_set_power_state(tp->pdev, PCI_D3hot); |
1da177e4 LT |
3921 | } |
3922 | ||
1da177e4 LT |
3923 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
3924 | { | |
3925 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
3926 | case MII_TG3_AUX_STAT_10HALF: | |
3927 | *speed = SPEED_10; | |
3928 | *duplex = DUPLEX_HALF; | |
3929 | break; | |
3930 | ||
3931 | case MII_TG3_AUX_STAT_10FULL: | |
3932 | *speed = SPEED_10; | |
3933 | *duplex = DUPLEX_FULL; | |
3934 | break; | |
3935 | ||
3936 | case MII_TG3_AUX_STAT_100HALF: | |
3937 | *speed = SPEED_100; | |
3938 | *duplex = DUPLEX_HALF; | |
3939 | break; | |
3940 | ||
3941 | case MII_TG3_AUX_STAT_100FULL: | |
3942 | *speed = SPEED_100; | |
3943 | *duplex = DUPLEX_FULL; | |
3944 | break; | |
3945 | ||
3946 | case MII_TG3_AUX_STAT_1000HALF: | |
3947 | *speed = SPEED_1000; | |
3948 | *duplex = DUPLEX_HALF; | |
3949 | break; | |
3950 | ||
3951 | case MII_TG3_AUX_STAT_1000FULL: | |
3952 | *speed = SPEED_1000; | |
3953 | *duplex = DUPLEX_FULL; | |
3954 | break; | |
3955 | ||
3956 | default: | |
f07e9af3 | 3957 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
3958 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
3959 | SPEED_10; | |
3960 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
3961 | DUPLEX_HALF; | |
3962 | break; | |
3963 | } | |
e740522e MC |
3964 | *speed = SPEED_UNKNOWN; |
3965 | *duplex = DUPLEX_UNKNOWN; | |
1da177e4 | 3966 | break; |
855e1111 | 3967 | } |
1da177e4 LT |
3968 | } |
3969 | ||
42b64a45 | 3970 | static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) |
1da177e4 | 3971 | { |
42b64a45 MC |
3972 | int err = 0; |
3973 | u32 val, new_adv; | |
1da177e4 | 3974 | |
42b64a45 | 3975 | new_adv = ADVERTISE_CSMA; |
202ff1c2 | 3976 | new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL; |
f88788f0 | 3977 | new_adv |= mii_advertise_flowctrl(flowctrl); |
1da177e4 | 3978 | |
42b64a45 MC |
3979 | err = tg3_writephy(tp, MII_ADVERTISE, new_adv); |
3980 | if (err) | |
3981 | goto done; | |
ba4d07a8 | 3982 | |
4f272096 MC |
3983 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
3984 | new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise); | |
ba4d07a8 | 3985 | |
4f272096 MC |
3986 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
3987 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
3988 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; | |
ba4d07a8 | 3989 | |
4f272096 MC |
3990 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
3991 | if (err) | |
3992 | goto done; | |
3993 | } | |
1da177e4 | 3994 | |
42b64a45 MC |
3995 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) |
3996 | goto done; | |
52b02d04 | 3997 | |
42b64a45 MC |
3998 | tw32(TG3_CPMU_EEE_MODE, |
3999 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
52b02d04 | 4000 | |
42b64a45 MC |
4001 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
4002 | if (!err) { | |
4003 | u32 err2; | |
52b02d04 | 4004 | |
b715ce94 MC |
4005 | val = 0; |
4006 | /* Advertise 100-BaseTX EEE ability */ | |
4007 | if (advertise & ADVERTISED_100baseT_Full) | |
4008 | val |= MDIO_AN_EEE_ADV_100TX; | |
4009 | /* Advertise 1000-BaseT EEE ability */ | |
4010 | if (advertise & ADVERTISED_1000baseT_Full) | |
4011 | val |= MDIO_AN_EEE_ADV_1000T; | |
4012 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
4013 | if (err) | |
4014 | val = 0; | |
4015 | ||
21a00ab2 MC |
4016 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
4017 | case ASIC_REV_5717: | |
4018 | case ASIC_REV_57765: | |
55086ad9 | 4019 | case ASIC_REV_57766: |
21a00ab2 | 4020 | case ASIC_REV_5719: |
b715ce94 MC |
4021 | /* If we advertised any eee advertisements above... */ |
4022 | if (val) | |
4023 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
4024 | MII_TG3_DSP_TAP26_RMRXSTO | | |
4025 | MII_TG3_DSP_TAP26_OPCSINPT; | |
21a00ab2 | 4026 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); |
be671947 MC |
4027 | /* Fall through */ |
4028 | case ASIC_REV_5720: | |
4029 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
4030 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
4031 | MII_TG3_DSP_CH34TP2_HIBW01); | |
21a00ab2 | 4032 | } |
52b02d04 | 4033 | |
42b64a45 MC |
4034 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
4035 | if (!err) | |
4036 | err = err2; | |
4037 | } | |
4038 | ||
4039 | done: | |
4040 | return err; | |
4041 | } | |
4042 | ||
4043 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
4044 | { | |
d13ba512 MC |
4045 | if (tp->link_config.autoneg == AUTONEG_ENABLE || |
4046 | (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { | |
4047 | u32 adv, fc; | |
4048 | ||
4049 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
4050 | adv = ADVERTISED_10baseT_Half | | |
4051 | ADVERTISED_10baseT_Full; | |
4052 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
4053 | adv |= ADVERTISED_100baseT_Half | | |
4054 | ADVERTISED_100baseT_Full; | |
4055 | ||
4056 | fc = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
42b64a45 | 4057 | } else { |
d13ba512 MC |
4058 | adv = tp->link_config.advertising; |
4059 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
4060 | adv &= ~(ADVERTISED_1000baseT_Half | | |
4061 | ADVERTISED_1000baseT_Full); | |
4062 | ||
4063 | fc = tp->link_config.flowctrl; | |
52b02d04 | 4064 | } |
52b02d04 | 4065 | |
d13ba512 | 4066 | tg3_phy_autoneg_cfg(tp, adv, fc); |
52b02d04 | 4067 | |
d13ba512 MC |
4068 | tg3_writephy(tp, MII_BMCR, |
4069 | BMCR_ANENABLE | BMCR_ANRESTART); | |
4070 | } else { | |
4071 | int i; | |
1da177e4 LT |
4072 | u32 bmcr, orig_bmcr; |
4073 | ||
4074 | tp->link_config.active_speed = tp->link_config.speed; | |
4075 | tp->link_config.active_duplex = tp->link_config.duplex; | |
4076 | ||
4077 | bmcr = 0; | |
4078 | switch (tp->link_config.speed) { | |
4079 | default: | |
4080 | case SPEED_10: | |
4081 | break; | |
4082 | ||
4083 | case SPEED_100: | |
4084 | bmcr |= BMCR_SPEED100; | |
4085 | break; | |
4086 | ||
4087 | case SPEED_1000: | |
221c5637 | 4088 | bmcr |= BMCR_SPEED1000; |
1da177e4 | 4089 | break; |
855e1111 | 4090 | } |
1da177e4 LT |
4091 | |
4092 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4093 | bmcr |= BMCR_FULLDPLX; | |
4094 | ||
4095 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
4096 | (bmcr != orig_bmcr)) { | |
4097 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
4098 | for (i = 0; i < 1500; i++) { | |
4099 | u32 tmp; | |
4100 | ||
4101 | udelay(10); | |
4102 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
4103 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
4104 | continue; | |
4105 | if (!(tmp & BMSR_LSTATUS)) { | |
4106 | udelay(40); | |
4107 | break; | |
4108 | } | |
4109 | } | |
4110 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4111 | udelay(40); | |
4112 | } | |
1da177e4 LT |
4113 | } |
4114 | } | |
4115 | ||
4116 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
4117 | { | |
4118 | int err; | |
4119 | ||
4120 | /* Turn off tap power management. */ | |
4121 | /* Set Extended packet length bit */ | |
b4bd2929 | 4122 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
1da177e4 | 4123 | |
6ee7c0a0 MC |
4124 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
4125 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
4126 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
4127 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
4128 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
4129 | |
4130 | udelay(40); | |
4131 | ||
4132 | return err; | |
4133 | } | |
4134 | ||
e2bf73e7 | 4135 | static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) |
1da177e4 | 4136 | { |
e2bf73e7 | 4137 | u32 advmsk, tgtadv, advertising; |
3600d918 | 4138 | |
e2bf73e7 MC |
4139 | advertising = tp->link_config.advertising; |
4140 | tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL; | |
1da177e4 | 4141 | |
e2bf73e7 MC |
4142 | advmsk = ADVERTISE_ALL; |
4143 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
f88788f0 | 4144 | tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); |
e2bf73e7 MC |
4145 | advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4146 | } | |
1da177e4 | 4147 | |
e2bf73e7 MC |
4148 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) |
4149 | return false; | |
4150 | ||
4151 | if ((*lcladv & advmsk) != tgtadv) | |
4152 | return false; | |
b99d2a57 | 4153 | |
f07e9af3 | 4154 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
4155 | u32 tg3_ctrl; |
4156 | ||
e2bf73e7 | 4157 | tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising); |
3600d918 | 4158 | |
221c5637 | 4159 | if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) |
e2bf73e7 | 4160 | return false; |
1da177e4 | 4161 | |
3198e07f MC |
4162 | if (tgtadv && |
4163 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
4164 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) { | |
4165 | tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; | |
4166 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL | | |
4167 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | |
4168 | } else { | |
4169 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL); | |
4170 | } | |
4171 | ||
e2bf73e7 MC |
4172 | if (tg3_ctrl != tgtadv) |
4173 | return false; | |
ef167e27 MC |
4174 | } |
4175 | ||
e2bf73e7 | 4176 | return true; |
ef167e27 MC |
4177 | } |
4178 | ||
859edb26 MC |
4179 | static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) |
4180 | { | |
4181 | u32 lpeth = 0; | |
4182 | ||
4183 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { | |
4184 | u32 val; | |
4185 | ||
4186 | if (tg3_readphy(tp, MII_STAT1000, &val)) | |
4187 | return false; | |
4188 | ||
4189 | lpeth = mii_stat1000_to_ethtool_lpa_t(val); | |
4190 | } | |
4191 | ||
4192 | if (tg3_readphy(tp, MII_LPA, rmtadv)) | |
4193 | return false; | |
4194 | ||
4195 | lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv); | |
4196 | tp->link_config.rmt_adv = lpeth; | |
4197 | ||
4198 | return true; | |
4199 | } | |
4200 | ||
f4a46d1f NNS |
4201 | static bool tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up) |
4202 | { | |
4203 | if (curr_link_up != tp->link_up) { | |
4204 | if (curr_link_up) { | |
4205 | tg3_carrier_on(tp); | |
4206 | } else { | |
4207 | tg3_carrier_off(tp); | |
4208 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) | |
4209 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
4210 | } | |
4211 | ||
4212 | tg3_link_report(tp); | |
4213 | return true; | |
4214 | } | |
4215 | ||
4216 | return false; | |
4217 | } | |
4218 | ||
1da177e4 LT |
4219 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
4220 | { | |
4221 | int current_link_up; | |
f833c4c1 | 4222 | u32 bmsr, val; |
ef167e27 | 4223 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
4224 | u16 current_speed; |
4225 | u8 current_duplex; | |
4226 | int i, err; | |
4227 | ||
4228 | tw32(MAC_EVENT, 0); | |
4229 | ||
4230 | tw32_f(MAC_STATUS, | |
4231 | (MAC_STATUS_SYNC_CHANGED | | |
4232 | MAC_STATUS_CFG_CHANGED | | |
4233 | MAC_STATUS_MI_COMPLETION | | |
4234 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4235 | udelay(40); | |
4236 | ||
8ef21428 MC |
4237 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
4238 | tw32_f(MAC_MI_MODE, | |
4239 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
4240 | udelay(80); | |
4241 | } | |
1da177e4 | 4242 | |
b4bd2929 | 4243 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); |
1da177e4 LT |
4244 | |
4245 | /* Some third-party PHYs need to be reset on link going | |
4246 | * down. | |
4247 | */ | |
4248 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
4249 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
4250 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
f4a46d1f | 4251 | tp->link_up) { |
1da177e4 LT |
4252 | tg3_readphy(tp, MII_BMSR, &bmsr); |
4253 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
4254 | !(bmsr & BMSR_LSTATUS)) | |
4255 | force_reset = 1; | |
4256 | } | |
4257 | if (force_reset) | |
4258 | tg3_phy_reset(tp); | |
4259 | ||
79eb6904 | 4260 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
4261 | tg3_readphy(tp, MII_BMSR, &bmsr); |
4262 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
63c3a66f | 4263 | !tg3_flag(tp, INIT_COMPLETE)) |
1da177e4 LT |
4264 | bmsr = 0; |
4265 | ||
4266 | if (!(bmsr & BMSR_LSTATUS)) { | |
4267 | err = tg3_init_5401phy_dsp(tp); | |
4268 | if (err) | |
4269 | return err; | |
4270 | ||
4271 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
4272 | for (i = 0; i < 1000; i++) { | |
4273 | udelay(10); | |
4274 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
4275 | (bmsr & BMSR_LSTATUS)) { | |
4276 | udelay(40); | |
4277 | break; | |
4278 | } | |
4279 | } | |
4280 | ||
79eb6904 MC |
4281 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
4282 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
4283 | !(bmsr & BMSR_LSTATUS) && |
4284 | tp->link_config.active_speed == SPEED_1000) { | |
4285 | err = tg3_phy_reset(tp); | |
4286 | if (!err) | |
4287 | err = tg3_init_5401phy_dsp(tp); | |
4288 | if (err) | |
4289 | return err; | |
4290 | } | |
4291 | } | |
4292 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
4293 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
4294 | /* 5701 {A0,B0} CRC bug workaround */ | |
4295 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
4296 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
4297 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
4298 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
4299 | } |
4300 | ||
4301 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
4302 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
4303 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 4304 | |
f07e9af3 | 4305 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 4306 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 4307 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
4308 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
4309 | ||
4310 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
4311 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
4312 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
4313 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
4314 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
4315 | else | |
4316 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
4317 | } | |
4318 | ||
4319 | current_link_up = 0; | |
e740522e MC |
4320 | current_speed = SPEED_UNKNOWN; |
4321 | current_duplex = DUPLEX_UNKNOWN; | |
e348c5e7 | 4322 | tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; |
859edb26 | 4323 | tp->link_config.rmt_adv = 0; |
1da177e4 | 4324 | |
f07e9af3 | 4325 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
15ee95c3 MC |
4326 | err = tg3_phy_auxctl_read(tp, |
4327 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
4328 | &val); | |
4329 | if (!err && !(val & (1 << 10))) { | |
b4bd2929 MC |
4330 | tg3_phy_auxctl_write(tp, |
4331 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
4332 | val | (1 << 10)); | |
1da177e4 LT |
4333 | goto relink; |
4334 | } | |
4335 | } | |
4336 | ||
4337 | bmsr = 0; | |
4338 | for (i = 0; i < 100; i++) { | |
4339 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
4340 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
4341 | (bmsr & BMSR_LSTATUS)) | |
4342 | break; | |
4343 | udelay(40); | |
4344 | } | |
4345 | ||
4346 | if (bmsr & BMSR_LSTATUS) { | |
4347 | u32 aux_stat, bmcr; | |
4348 | ||
4349 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
4350 | for (i = 0; i < 2000; i++) { | |
4351 | udelay(10); | |
4352 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
4353 | aux_stat) | |
4354 | break; | |
4355 | } | |
4356 | ||
4357 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
4358 | ¤t_speed, | |
4359 | ¤t_duplex); | |
4360 | ||
4361 | bmcr = 0; | |
4362 | for (i = 0; i < 200; i++) { | |
4363 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4364 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
4365 | continue; | |
4366 | if (bmcr && bmcr != 0x7fff) | |
4367 | break; | |
4368 | udelay(10); | |
4369 | } | |
4370 | ||
ef167e27 MC |
4371 | lcl_adv = 0; |
4372 | rmt_adv = 0; | |
1da177e4 | 4373 | |
ef167e27 MC |
4374 | tp->link_config.active_speed = current_speed; |
4375 | tp->link_config.active_duplex = current_duplex; | |
4376 | ||
4377 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4378 | if ((bmcr & BMCR_ANENABLE) && | |
e2bf73e7 | 4379 | tg3_phy_copper_an_config_ok(tp, &lcl_adv) && |
859edb26 | 4380 | tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) |
e2bf73e7 | 4381 | current_link_up = 1; |
1da177e4 LT |
4382 | } else { |
4383 | if (!(bmcr & BMCR_ANENABLE) && | |
4384 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
4385 | tp->link_config.duplex == current_duplex && |
4386 | tp->link_config.flowctrl == | |
4387 | tp->link_config.active_flowctrl) { | |
1da177e4 | 4388 | current_link_up = 1; |
1da177e4 LT |
4389 | } |
4390 | } | |
4391 | ||
ef167e27 | 4392 | if (current_link_up == 1 && |
e348c5e7 MC |
4393 | tp->link_config.active_duplex == DUPLEX_FULL) { |
4394 | u32 reg, bit; | |
4395 | ||
4396 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
4397 | reg = MII_TG3_FET_GEN_STAT; | |
4398 | bit = MII_TG3_FET_GEN_STAT_MDIXSTAT; | |
4399 | } else { | |
4400 | reg = MII_TG3_EXT_STAT; | |
4401 | bit = MII_TG3_EXT_STAT_MDIX; | |
4402 | } | |
4403 | ||
4404 | if (!tg3_readphy(tp, reg, &val) && (val & bit)) | |
4405 | tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; | |
4406 | ||
ef167e27 | 4407 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); |
e348c5e7 | 4408 | } |
1da177e4 LT |
4409 | } |
4410 | ||
1da177e4 | 4411 | relink: |
80096068 | 4412 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
4413 | tg3_phy_copper_begin(tp); |
4414 | ||
f833c4c1 | 4415 | tg3_readphy(tp, MII_BMSR, &bmsr); |
06c03c02 MB |
4416 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
4417 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
1da177e4 LT |
4418 | current_link_up = 1; |
4419 | } | |
4420 | ||
4421 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
4422 | if (current_link_up == 1) { | |
4423 | if (tp->link_config.active_speed == SPEED_100 || | |
4424 | tp->link_config.active_speed == SPEED_10) | |
4425 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
4426 | else | |
4427 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 4428 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
4429 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
4430 | else | |
1da177e4 LT |
4431 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
4432 | ||
4433 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
4434 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4435 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4436 | ||
1da177e4 | 4437 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
4438 | if (current_link_up == 1 && |
4439 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 4440 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
4441 | else |
4442 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
4443 | } |
4444 | ||
4445 | /* ??? Without this setting Netgear GA302T PHY does not | |
4446 | * ??? send/receive packets... | |
4447 | */ | |
79eb6904 | 4448 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
4449 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
4450 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
4451 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
4452 | udelay(80); | |
4453 | } | |
4454 | ||
4455 | tw32_f(MAC_MODE, tp->mac_mode); | |
4456 | udelay(40); | |
4457 | ||
52b02d04 MC |
4458 | tg3_phy_eee_adjust(tp, current_link_up); |
4459 | ||
63c3a66f | 4460 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
4461 | /* Polled via timer. */ |
4462 | tw32_f(MAC_EVENT, 0); | |
4463 | } else { | |
4464 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4465 | } | |
4466 | udelay(40); | |
4467 | ||
4468 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
4469 | current_link_up == 1 && | |
4470 | tp->link_config.active_speed == SPEED_1000 && | |
63c3a66f | 4471 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
1da177e4 LT |
4472 | udelay(120); |
4473 | tw32_f(MAC_STATUS, | |
4474 | (MAC_STATUS_SYNC_CHANGED | | |
4475 | MAC_STATUS_CFG_CHANGED)); | |
4476 | udelay(40); | |
4477 | tg3_write_mem(tp, | |
4478 | NIC_SRAM_FIRMWARE_MBOX, | |
4479 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
4480 | } | |
4481 | ||
5e7dfd0f | 4482 | /* Prevent send BD corruption. */ |
63c3a66f | 4483 | if (tg3_flag(tp, CLKREQ_BUG)) { |
5e7dfd0f MC |
4484 | if (tp->link_config.active_speed == SPEED_100 || |
4485 | tp->link_config.active_speed == SPEED_10) | |
0f49bfbd JL |
4486 | pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, |
4487 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
5e7dfd0f | 4488 | else |
0f49bfbd JL |
4489 | pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, |
4490 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
5e7dfd0f MC |
4491 | } |
4492 | ||
f4a46d1f | 4493 | tg3_test_and_report_link_chg(tp, current_link_up); |
1da177e4 LT |
4494 | |
4495 | return 0; | |
4496 | } | |
4497 | ||
4498 | struct tg3_fiber_aneginfo { | |
4499 | int state; | |
4500 | #define ANEG_STATE_UNKNOWN 0 | |
4501 | #define ANEG_STATE_AN_ENABLE 1 | |
4502 | #define ANEG_STATE_RESTART_INIT 2 | |
4503 | #define ANEG_STATE_RESTART 3 | |
4504 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
4505 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
4506 | #define ANEG_STATE_ABILITY_DETECT 6 | |
4507 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
4508 | #define ANEG_STATE_ACK_DETECT 8 | |
4509 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
4510 | #define ANEG_STATE_COMPLETE_ACK 10 | |
4511 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
4512 | #define ANEG_STATE_IDLE_DETECT 12 | |
4513 | #define ANEG_STATE_LINK_OK 13 | |
4514 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
4515 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
4516 | ||
4517 | u32 flags; | |
4518 | #define MR_AN_ENABLE 0x00000001 | |
4519 | #define MR_RESTART_AN 0x00000002 | |
4520 | #define MR_AN_COMPLETE 0x00000004 | |
4521 | #define MR_PAGE_RX 0x00000008 | |
4522 | #define MR_NP_LOADED 0x00000010 | |
4523 | #define MR_TOGGLE_TX 0x00000020 | |
4524 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
4525 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
4526 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
4527 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
4528 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
4529 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
4530 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
4531 | #define MR_TOGGLE_RX 0x00002000 | |
4532 | #define MR_NP_RX 0x00004000 | |
4533 | ||
4534 | #define MR_LINK_OK 0x80000000 | |
4535 | ||
4536 | unsigned long link_time, cur_time; | |
4537 | ||
4538 | u32 ability_match_cfg; | |
4539 | int ability_match_count; | |
4540 | ||
4541 | char ability_match, idle_match, ack_match; | |
4542 | ||
4543 | u32 txconfig, rxconfig; | |
4544 | #define ANEG_CFG_NP 0x00000080 | |
4545 | #define ANEG_CFG_ACK 0x00000040 | |
4546 | #define ANEG_CFG_RF2 0x00000020 | |
4547 | #define ANEG_CFG_RF1 0x00000010 | |
4548 | #define ANEG_CFG_PS2 0x00000001 | |
4549 | #define ANEG_CFG_PS1 0x00008000 | |
4550 | #define ANEG_CFG_HD 0x00004000 | |
4551 | #define ANEG_CFG_FD 0x00002000 | |
4552 | #define ANEG_CFG_INVAL 0x00001f06 | |
4553 | ||
4554 | }; | |
4555 | #define ANEG_OK 0 | |
4556 | #define ANEG_DONE 1 | |
4557 | #define ANEG_TIMER_ENAB 2 | |
4558 | #define ANEG_FAILED -1 | |
4559 | ||
4560 | #define ANEG_STATE_SETTLE_TIME 10000 | |
4561 | ||
4562 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
4563 | struct tg3_fiber_aneginfo *ap) | |
4564 | { | |
5be73b47 | 4565 | u16 flowctrl; |
1da177e4 LT |
4566 | unsigned long delta; |
4567 | u32 rx_cfg_reg; | |
4568 | int ret; | |
4569 | ||
4570 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
4571 | ap->rxconfig = 0; | |
4572 | ap->link_time = 0; | |
4573 | ap->cur_time = 0; | |
4574 | ap->ability_match_cfg = 0; | |
4575 | ap->ability_match_count = 0; | |
4576 | ap->ability_match = 0; | |
4577 | ap->idle_match = 0; | |
4578 | ap->ack_match = 0; | |
4579 | } | |
4580 | ap->cur_time++; | |
4581 | ||
4582 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
4583 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
4584 | ||
4585 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
4586 | ap->ability_match_cfg = rx_cfg_reg; | |
4587 | ap->ability_match = 0; | |
4588 | ap->ability_match_count = 0; | |
4589 | } else { | |
4590 | if (++ap->ability_match_count > 1) { | |
4591 | ap->ability_match = 1; | |
4592 | ap->ability_match_cfg = rx_cfg_reg; | |
4593 | } | |
4594 | } | |
4595 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
4596 | ap->ack_match = 1; | |
4597 | else | |
4598 | ap->ack_match = 0; | |
4599 | ||
4600 | ap->idle_match = 0; | |
4601 | } else { | |
4602 | ap->idle_match = 1; | |
4603 | ap->ability_match_cfg = 0; | |
4604 | ap->ability_match_count = 0; | |
4605 | ap->ability_match = 0; | |
4606 | ap->ack_match = 0; | |
4607 | ||
4608 | rx_cfg_reg = 0; | |
4609 | } | |
4610 | ||
4611 | ap->rxconfig = rx_cfg_reg; | |
4612 | ret = ANEG_OK; | |
4613 | ||
33f401ae | 4614 | switch (ap->state) { |
1da177e4 LT |
4615 | case ANEG_STATE_UNKNOWN: |
4616 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
4617 | ap->state = ANEG_STATE_AN_ENABLE; | |
4618 | ||
4619 | /* fallthru */ | |
4620 | case ANEG_STATE_AN_ENABLE: | |
4621 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
4622 | if (ap->flags & MR_AN_ENABLE) { | |
4623 | ap->link_time = 0; | |
4624 | ap->cur_time = 0; | |
4625 | ap->ability_match_cfg = 0; | |
4626 | ap->ability_match_count = 0; | |
4627 | ap->ability_match = 0; | |
4628 | ap->idle_match = 0; | |
4629 | ap->ack_match = 0; | |
4630 | ||
4631 | ap->state = ANEG_STATE_RESTART_INIT; | |
4632 | } else { | |
4633 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
4634 | } | |
4635 | break; | |
4636 | ||
4637 | case ANEG_STATE_RESTART_INIT: | |
4638 | ap->link_time = ap->cur_time; | |
4639 | ap->flags &= ~(MR_NP_LOADED); | |
4640 | ap->txconfig = 0; | |
4641 | tw32(MAC_TX_AUTO_NEG, 0); | |
4642 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4643 | tw32_f(MAC_MODE, tp->mac_mode); | |
4644 | udelay(40); | |
4645 | ||
4646 | ret = ANEG_TIMER_ENAB; | |
4647 | ap->state = ANEG_STATE_RESTART; | |
4648 | ||
4649 | /* fallthru */ | |
4650 | case ANEG_STATE_RESTART: | |
4651 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 4652 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 4653 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 4654 | else |
1da177e4 | 4655 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
4656 | break; |
4657 | ||
4658 | case ANEG_STATE_DISABLE_LINK_OK: | |
4659 | ret = ANEG_DONE; | |
4660 | break; | |
4661 | ||
4662 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
4663 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
4664 | ap->txconfig = ANEG_CFG_FD; |
4665 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
4666 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4667 | ap->txconfig |= ANEG_CFG_PS1; | |
4668 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4669 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
4670 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
4671 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4672 | tw32_f(MAC_MODE, tp->mac_mode); | |
4673 | udelay(40); | |
4674 | ||
4675 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
4676 | break; | |
4677 | ||
4678 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 4679 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 4680 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
4681 | break; |
4682 | ||
4683 | case ANEG_STATE_ACK_DETECT_INIT: | |
4684 | ap->txconfig |= ANEG_CFG_ACK; | |
4685 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
4686 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
4687 | tw32_f(MAC_MODE, tp->mac_mode); | |
4688 | udelay(40); | |
4689 | ||
4690 | ap->state = ANEG_STATE_ACK_DETECT; | |
4691 | ||
4692 | /* fallthru */ | |
4693 | case ANEG_STATE_ACK_DETECT: | |
4694 | if (ap->ack_match != 0) { | |
4695 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
4696 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
4697 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
4698 | } else { | |
4699 | ap->state = ANEG_STATE_AN_ENABLE; | |
4700 | } | |
4701 | } else if (ap->ability_match != 0 && | |
4702 | ap->rxconfig == 0) { | |
4703 | ap->state = ANEG_STATE_AN_ENABLE; | |
4704 | } | |
4705 | break; | |
4706 | ||
4707 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
4708 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
4709 | ret = ANEG_FAILED; | |
4710 | break; | |
4711 | } | |
4712 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
4713 | MR_LP_ADV_HALF_DUPLEX | | |
4714 | MR_LP_ADV_SYM_PAUSE | | |
4715 | MR_LP_ADV_ASYM_PAUSE | | |
4716 | MR_LP_ADV_REMOTE_FAULT1 | | |
4717 | MR_LP_ADV_REMOTE_FAULT2 | | |
4718 | MR_LP_ADV_NEXT_PAGE | | |
4719 | MR_TOGGLE_RX | | |
4720 | MR_NP_RX); | |
4721 | if (ap->rxconfig & ANEG_CFG_FD) | |
4722 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
4723 | if (ap->rxconfig & ANEG_CFG_HD) | |
4724 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
4725 | if (ap->rxconfig & ANEG_CFG_PS1) | |
4726 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
4727 | if (ap->rxconfig & ANEG_CFG_PS2) | |
4728 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
4729 | if (ap->rxconfig & ANEG_CFG_RF1) | |
4730 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
4731 | if (ap->rxconfig & ANEG_CFG_RF2) | |
4732 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
4733 | if (ap->rxconfig & ANEG_CFG_NP) | |
4734 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
4735 | ||
4736 | ap->link_time = ap->cur_time; | |
4737 | ||
4738 | ap->flags ^= (MR_TOGGLE_TX); | |
4739 | if (ap->rxconfig & 0x0008) | |
4740 | ap->flags |= MR_TOGGLE_RX; | |
4741 | if (ap->rxconfig & ANEG_CFG_NP) | |
4742 | ap->flags |= MR_NP_RX; | |
4743 | ap->flags |= MR_PAGE_RX; | |
4744 | ||
4745 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
4746 | ret = ANEG_TIMER_ENAB; | |
4747 | break; | |
4748 | ||
4749 | case ANEG_STATE_COMPLETE_ACK: | |
4750 | if (ap->ability_match != 0 && | |
4751 | ap->rxconfig == 0) { | |
4752 | ap->state = ANEG_STATE_AN_ENABLE; | |
4753 | break; | |
4754 | } | |
4755 | delta = ap->cur_time - ap->link_time; | |
4756 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
4757 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
4758 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
4759 | } else { | |
4760 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
4761 | !(ap->flags & MR_NP_RX)) { | |
4762 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
4763 | } else { | |
4764 | ret = ANEG_FAILED; | |
4765 | } | |
4766 | } | |
4767 | } | |
4768 | break; | |
4769 | ||
4770 | case ANEG_STATE_IDLE_DETECT_INIT: | |
4771 | ap->link_time = ap->cur_time; | |
4772 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
4773 | tw32_f(MAC_MODE, tp->mac_mode); | |
4774 | udelay(40); | |
4775 | ||
4776 | ap->state = ANEG_STATE_IDLE_DETECT; | |
4777 | ret = ANEG_TIMER_ENAB; | |
4778 | break; | |
4779 | ||
4780 | case ANEG_STATE_IDLE_DETECT: | |
4781 | if (ap->ability_match != 0 && | |
4782 | ap->rxconfig == 0) { | |
4783 | ap->state = ANEG_STATE_AN_ENABLE; | |
4784 | break; | |
4785 | } | |
4786 | delta = ap->cur_time - ap->link_time; | |
4787 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
4788 | /* XXX another gem from the Broadcom driver :( */ | |
4789 | ap->state = ANEG_STATE_LINK_OK; | |
4790 | } | |
4791 | break; | |
4792 | ||
4793 | case ANEG_STATE_LINK_OK: | |
4794 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
4795 | ret = ANEG_DONE; | |
4796 | break; | |
4797 | ||
4798 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
4799 | /* ??? unimplemented */ | |
4800 | break; | |
4801 | ||
4802 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
4803 | /* ??? unimplemented */ | |
4804 | break; | |
4805 | ||
4806 | default: | |
4807 | ret = ANEG_FAILED; | |
4808 | break; | |
855e1111 | 4809 | } |
1da177e4 LT |
4810 | |
4811 | return ret; | |
4812 | } | |
4813 | ||
5be73b47 | 4814 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
4815 | { |
4816 | int res = 0; | |
4817 | struct tg3_fiber_aneginfo aninfo; | |
4818 | int status = ANEG_FAILED; | |
4819 | unsigned int tick; | |
4820 | u32 tmp; | |
4821 | ||
4822 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4823 | ||
4824 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
4825 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
4826 | udelay(40); | |
4827 | ||
4828 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
4829 | udelay(40); | |
4830 | ||
4831 | memset(&aninfo, 0, sizeof(aninfo)); | |
4832 | aninfo.flags |= MR_AN_ENABLE; | |
4833 | aninfo.state = ANEG_STATE_UNKNOWN; | |
4834 | aninfo.cur_time = 0; | |
4835 | tick = 0; | |
4836 | while (++tick < 195000) { | |
4837 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
4838 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
4839 | break; | |
4840 | ||
4841 | udelay(1); | |
4842 | } | |
4843 | ||
4844 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
4845 | tw32_f(MAC_MODE, tp->mac_mode); | |
4846 | udelay(40); | |
4847 | ||
5be73b47 MC |
4848 | *txflags = aninfo.txconfig; |
4849 | *rxflags = aninfo.flags; | |
1da177e4 LT |
4850 | |
4851 | if (status == ANEG_DONE && | |
4852 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
4853 | MR_LP_ADV_FULL_DUPLEX))) | |
4854 | res = 1; | |
4855 | ||
4856 | return res; | |
4857 | } | |
4858 | ||
4859 | static void tg3_init_bcm8002(struct tg3 *tp) | |
4860 | { | |
4861 | u32 mac_status = tr32(MAC_STATUS); | |
4862 | int i; | |
4863 | ||
4864 | /* Reset when initting first time or we have a link. */ | |
63c3a66f | 4865 | if (tg3_flag(tp, INIT_COMPLETE) && |
1da177e4 LT |
4866 | !(mac_status & MAC_STATUS_PCS_SYNCED)) |
4867 | return; | |
4868 | ||
4869 | /* Set PLL lock range. */ | |
4870 | tg3_writephy(tp, 0x16, 0x8007); | |
4871 | ||
4872 | /* SW reset */ | |
4873 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
4874 | ||
4875 | /* Wait for reset to complete. */ | |
4876 | /* XXX schedule_timeout() ... */ | |
4877 | for (i = 0; i < 500; i++) | |
4878 | udelay(10); | |
4879 | ||
4880 | /* Config mode; select PMA/Ch 1 regs. */ | |
4881 | tg3_writephy(tp, 0x10, 0x8411); | |
4882 | ||
4883 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
4884 | tg3_writephy(tp, 0x11, 0x0a10); | |
4885 | ||
4886 | tg3_writephy(tp, 0x18, 0x00a0); | |
4887 | tg3_writephy(tp, 0x16, 0x41ff); | |
4888 | ||
4889 | /* Assert and deassert POR. */ | |
4890 | tg3_writephy(tp, 0x13, 0x0400); | |
4891 | udelay(40); | |
4892 | tg3_writephy(tp, 0x13, 0x0000); | |
4893 | ||
4894 | tg3_writephy(tp, 0x11, 0x0a50); | |
4895 | udelay(40); | |
4896 | tg3_writephy(tp, 0x11, 0x0a10); | |
4897 | ||
4898 | /* Wait for signal to stabilize */ | |
4899 | /* XXX schedule_timeout() ... */ | |
4900 | for (i = 0; i < 15000; i++) | |
4901 | udelay(10); | |
4902 | ||
4903 | /* Deselect the channel register so we can read the PHYID | |
4904 | * later. | |
4905 | */ | |
4906 | tg3_writephy(tp, 0x10, 0x8011); | |
4907 | } | |
4908 | ||
4909 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
4910 | { | |
82cd3d11 | 4911 | u16 flowctrl; |
1da177e4 LT |
4912 | u32 sg_dig_ctrl, sg_dig_status; |
4913 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
4914 | int workaround, port_a; | |
4915 | int current_link_up; | |
4916 | ||
4917 | serdes_cfg = 0; | |
4918 | expected_sg_dig_ctrl = 0; | |
4919 | workaround = 0; | |
4920 | port_a = 1; | |
4921 | current_link_up = 0; | |
4922 | ||
4923 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
4924 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
4925 | workaround = 1; | |
4926 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
4927 | port_a = 0; | |
4928 | ||
4929 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
4930 | /* preserve bits 20-23 for voltage regulator */ | |
4931 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
4932 | } | |
4933 | ||
4934 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
4935 | ||
4936 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 4937 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
4938 | if (workaround) { |
4939 | u32 val = serdes_cfg; | |
4940 | ||
4941 | if (port_a) | |
4942 | val |= 0xc010000; | |
4943 | else | |
4944 | val |= 0x4010000; | |
4945 | tw32_f(MAC_SERDES_CFG, val); | |
4946 | } | |
c98f6e3b MC |
4947 | |
4948 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
4949 | } |
4950 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
4951 | tg3_setup_flow_control(tp, 0, 0); | |
4952 | current_link_up = 1; | |
4953 | } | |
4954 | goto out; | |
4955 | } | |
4956 | ||
4957 | /* Want auto-negotiation. */ | |
c98f6e3b | 4958 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 4959 | |
82cd3d11 MC |
4960 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
4961 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
4962 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
4963 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
4964 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
4965 | |
4966 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 4967 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
4968 | tp->serdes_counter && |
4969 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
4970 | MAC_STATUS_RCVD_CFG)) == | |
4971 | MAC_STATUS_PCS_SYNCED)) { | |
4972 | tp->serdes_counter--; | |
4973 | current_link_up = 1; | |
4974 | goto out; | |
4975 | } | |
4976 | restart_autoneg: | |
1da177e4 LT |
4977 | if (workaround) |
4978 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 4979 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
4980 | udelay(5); |
4981 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
4982 | ||
3d3ebe74 | 4983 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 4984 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4985 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
4986 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 4987 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
4988 | mac_status = tr32(MAC_STATUS); |
4989 | ||
c98f6e3b | 4990 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 4991 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
4992 | u32 local_adv = 0, remote_adv = 0; |
4993 | ||
4994 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
4995 | local_adv |= ADVERTISE_1000XPAUSE; | |
4996 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
4997 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 4998 | |
c98f6e3b | 4999 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 5000 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 5001 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 5002 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 | 5003 | |
859edb26 MC |
5004 | tp->link_config.rmt_adv = |
5005 | mii_adv_to_ethtool_adv_x(remote_adv); | |
5006 | ||
1da177e4 LT |
5007 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
5008 | current_link_up = 1; | |
3d3ebe74 | 5009 | tp->serdes_counter = 0; |
f07e9af3 | 5010 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 5011 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
5012 | if (tp->serdes_counter) |
5013 | tp->serdes_counter--; | |
1da177e4 LT |
5014 | else { |
5015 | if (workaround) { | |
5016 | u32 val = serdes_cfg; | |
5017 | ||
5018 | if (port_a) | |
5019 | val |= 0xc010000; | |
5020 | else | |
5021 | val |= 0x4010000; | |
5022 | ||
5023 | tw32_f(MAC_SERDES_CFG, val); | |
5024 | } | |
5025 | ||
c98f6e3b | 5026 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
5027 | udelay(40); |
5028 | ||
5029 | /* Link parallel detection - link is up */ | |
5030 | /* only if we have PCS_SYNC and not */ | |
5031 | /* receiving config code words */ | |
5032 | mac_status = tr32(MAC_STATUS); | |
5033 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
5034 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
5035 | tg3_setup_flow_control(tp, 0, 0); | |
5036 | current_link_up = 1; | |
f07e9af3 MC |
5037 | tp->phy_flags |= |
5038 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
5039 | tp->serdes_counter = |
5040 | SERDES_PARALLEL_DET_TIMEOUT; | |
5041 | } else | |
5042 | goto restart_autoneg; | |
1da177e4 LT |
5043 | } |
5044 | } | |
3d3ebe74 MC |
5045 | } else { |
5046 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 5047 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
5048 | } |
5049 | ||
5050 | out: | |
5051 | return current_link_up; | |
5052 | } | |
5053 | ||
5054 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
5055 | { | |
5056 | int current_link_up = 0; | |
5057 | ||
5cf64b8a | 5058 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 5059 | goto out; |
1da177e4 LT |
5060 | |
5061 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 5062 | u32 txflags, rxflags; |
1da177e4 | 5063 | int i; |
6aa20a22 | 5064 | |
5be73b47 MC |
5065 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
5066 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 5067 | |
5be73b47 MC |
5068 | if (txflags & ANEG_CFG_PS1) |
5069 | local_adv |= ADVERTISE_1000XPAUSE; | |
5070 | if (txflags & ANEG_CFG_PS2) | |
5071 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
5072 | ||
5073 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
5074 | remote_adv |= LPA_1000XPAUSE; | |
5075 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
5076 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 | 5077 | |
859edb26 MC |
5078 | tp->link_config.rmt_adv = |
5079 | mii_adv_to_ethtool_adv_x(remote_adv); | |
5080 | ||
1da177e4 LT |
5081 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
5082 | ||
1da177e4 LT |
5083 | current_link_up = 1; |
5084 | } | |
5085 | for (i = 0; i < 30; i++) { | |
5086 | udelay(20); | |
5087 | tw32_f(MAC_STATUS, | |
5088 | (MAC_STATUS_SYNC_CHANGED | | |
5089 | MAC_STATUS_CFG_CHANGED)); | |
5090 | udelay(40); | |
5091 | if ((tr32(MAC_STATUS) & | |
5092 | (MAC_STATUS_SYNC_CHANGED | | |
5093 | MAC_STATUS_CFG_CHANGED)) == 0) | |
5094 | break; | |
5095 | } | |
5096 | ||
5097 | mac_status = tr32(MAC_STATUS); | |
5098 | if (current_link_up == 0 && | |
5099 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
5100 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
5101 | current_link_up = 1; | |
5102 | } else { | |
5be73b47 MC |
5103 | tg3_setup_flow_control(tp, 0, 0); |
5104 | ||
1da177e4 LT |
5105 | /* Forcing 1000FD link up. */ |
5106 | current_link_up = 1; | |
1da177e4 LT |
5107 | |
5108 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
5109 | udelay(40); | |
e8f3f6ca MC |
5110 | |
5111 | tw32_f(MAC_MODE, tp->mac_mode); | |
5112 | udelay(40); | |
1da177e4 LT |
5113 | } |
5114 | ||
5115 | out: | |
5116 | return current_link_up; | |
5117 | } | |
5118 | ||
5119 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
5120 | { | |
5121 | u32 orig_pause_cfg; | |
5122 | u16 orig_active_speed; | |
5123 | u8 orig_active_duplex; | |
5124 | u32 mac_status; | |
5125 | int current_link_up; | |
5126 | int i; | |
5127 | ||
8d018621 | 5128 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
5129 | orig_active_speed = tp->link_config.active_speed; |
5130 | orig_active_duplex = tp->link_config.active_duplex; | |
5131 | ||
63c3a66f | 5132 | if (!tg3_flag(tp, HW_AUTONEG) && |
f4a46d1f | 5133 | tp->link_up && |
63c3a66f | 5134 | tg3_flag(tp, INIT_COMPLETE)) { |
1da177e4 LT |
5135 | mac_status = tr32(MAC_STATUS); |
5136 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
5137 | MAC_STATUS_SIGNAL_DET | | |
5138 | MAC_STATUS_CFG_CHANGED | | |
5139 | MAC_STATUS_RCVD_CFG); | |
5140 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
5141 | MAC_STATUS_SIGNAL_DET)) { | |
5142 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
5143 | MAC_STATUS_CFG_CHANGED)); | |
5144 | return 0; | |
5145 | } | |
5146 | } | |
5147 | ||
5148 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
5149 | ||
5150 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
5151 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
5152 | tw32_f(MAC_MODE, tp->mac_mode); | |
5153 | udelay(40); | |
5154 | ||
79eb6904 | 5155 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
5156 | tg3_init_bcm8002(tp); |
5157 | ||
5158 | /* Enable link change event even when serdes polling. */ | |
5159 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
5160 | udelay(40); | |
5161 | ||
5162 | current_link_up = 0; | |
859edb26 | 5163 | tp->link_config.rmt_adv = 0; |
1da177e4 LT |
5164 | mac_status = tr32(MAC_STATUS); |
5165 | ||
63c3a66f | 5166 | if (tg3_flag(tp, HW_AUTONEG)) |
1da177e4 LT |
5167 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); |
5168 | else | |
5169 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
5170 | ||
898a56f8 | 5171 | tp->napi[0].hw_status->status = |
1da177e4 | 5172 | (SD_STATUS_UPDATED | |
898a56f8 | 5173 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
5174 | |
5175 | for (i = 0; i < 100; i++) { | |
5176 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
5177 | MAC_STATUS_CFG_CHANGED)); | |
5178 | udelay(5); | |
5179 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
5180 | MAC_STATUS_CFG_CHANGED | |
5181 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
5182 | break; |
5183 | } | |
5184 | ||
5185 | mac_status = tr32(MAC_STATUS); | |
5186 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
5187 | current_link_up = 0; | |
3d3ebe74 MC |
5188 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
5189 | tp->serdes_counter == 0) { | |
1da177e4 LT |
5190 | tw32_f(MAC_MODE, (tp->mac_mode | |
5191 | MAC_MODE_SEND_CONFIGS)); | |
5192 | udelay(1); | |
5193 | tw32_f(MAC_MODE, tp->mac_mode); | |
5194 | } | |
5195 | } | |
5196 | ||
5197 | if (current_link_up == 1) { | |
5198 | tp->link_config.active_speed = SPEED_1000; | |
5199 | tp->link_config.active_duplex = DUPLEX_FULL; | |
5200 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
5201 | LED_CTRL_LNKLED_OVERRIDE | | |
5202 | LED_CTRL_1000MBPS_ON)); | |
5203 | } else { | |
e740522e MC |
5204 | tp->link_config.active_speed = SPEED_UNKNOWN; |
5205 | tp->link_config.active_duplex = DUPLEX_UNKNOWN; | |
1da177e4 LT |
5206 | tw32(MAC_LED_CTRL, (tp->led_ctrl | |
5207 | LED_CTRL_LNKLED_OVERRIDE | | |
5208 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
5209 | } | |
5210 | ||
f4a46d1f | 5211 | if (!tg3_test_and_report_link_chg(tp, current_link_up)) { |
8d018621 | 5212 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
5213 | if (orig_pause_cfg != now_pause_cfg || |
5214 | orig_active_speed != tp->link_config.active_speed || | |
5215 | orig_active_duplex != tp->link_config.active_duplex) | |
5216 | tg3_link_report(tp); | |
5217 | } | |
5218 | ||
5219 | return 0; | |
5220 | } | |
5221 | ||
747e8f8b MC |
5222 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
5223 | { | |
5224 | int current_link_up, err = 0; | |
5225 | u32 bmsr, bmcr; | |
5226 | u16 current_speed; | |
5227 | u8 current_duplex; | |
ef167e27 | 5228 | u32 local_adv, remote_adv; |
747e8f8b MC |
5229 | |
5230 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
5231 | tw32_f(MAC_MODE, tp->mac_mode); | |
5232 | udelay(40); | |
5233 | ||
5234 | tw32(MAC_EVENT, 0); | |
5235 | ||
5236 | tw32_f(MAC_STATUS, | |
5237 | (MAC_STATUS_SYNC_CHANGED | | |
5238 | MAC_STATUS_CFG_CHANGED | | |
5239 | MAC_STATUS_MI_COMPLETION | | |
5240 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5241 | udelay(40); | |
5242 | ||
5243 | if (force_reset) | |
5244 | tg3_phy_reset(tp); | |
5245 | ||
5246 | current_link_up = 0; | |
e740522e MC |
5247 | current_speed = SPEED_UNKNOWN; |
5248 | current_duplex = DUPLEX_UNKNOWN; | |
859edb26 | 5249 | tp->link_config.rmt_adv = 0; |
747e8f8b MC |
5250 | |
5251 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
5252 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
5253 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
5254 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
5255 | bmsr |= BMSR_LSTATUS; | |
5256 | else | |
5257 | bmsr &= ~BMSR_LSTATUS; | |
5258 | } | |
747e8f8b MC |
5259 | |
5260 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
5261 | ||
5262 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 5263 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
5264 | /* do nothing, just check for link up at the end */ |
5265 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
28011cf1 | 5266 | u32 adv, newadv; |
747e8f8b MC |
5267 | |
5268 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
28011cf1 MC |
5269 | newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | |
5270 | ADVERTISE_1000XPAUSE | | |
5271 | ADVERTISE_1000XPSE_ASYM | | |
5272 | ADVERTISE_SLCT); | |
747e8f8b | 5273 | |
28011cf1 | 5274 | newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
37f07023 | 5275 | newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); |
747e8f8b | 5276 | |
28011cf1 MC |
5277 | if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) { |
5278 | tg3_writephy(tp, MII_ADVERTISE, newadv); | |
747e8f8b MC |
5279 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; |
5280 | tg3_writephy(tp, MII_BMCR, bmcr); | |
5281 | ||
5282 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 5283 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 5284 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5285 | |
5286 | return err; | |
5287 | } | |
5288 | } else { | |
5289 | u32 new_bmcr; | |
5290 | ||
5291 | bmcr &= ~BMCR_SPEED1000; | |
5292 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
5293 | ||
5294 | if (tp->link_config.duplex == DUPLEX_FULL) | |
5295 | new_bmcr |= BMCR_FULLDPLX; | |
5296 | ||
5297 | if (new_bmcr != bmcr) { | |
5298 | /* BMCR_SPEED1000 is a reserved bit that needs | |
5299 | * to be set on write. | |
5300 | */ | |
5301 | new_bmcr |= BMCR_SPEED1000; | |
5302 | ||
5303 | /* Force a linkdown */ | |
f4a46d1f | 5304 | if (tp->link_up) { |
747e8f8b MC |
5305 | u32 adv; |
5306 | ||
5307 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
5308 | adv &= ~(ADVERTISE_1000XFULL | | |
5309 | ADVERTISE_1000XHALF | | |
5310 | ADVERTISE_SLCT); | |
5311 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
5312 | tg3_writephy(tp, MII_BMCR, bmcr | | |
5313 | BMCR_ANRESTART | | |
5314 | BMCR_ANENABLE); | |
5315 | udelay(10); | |
f4a46d1f | 5316 | tg3_carrier_off(tp); |
747e8f8b MC |
5317 | } |
5318 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
5319 | bmcr = new_bmcr; | |
5320 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
5321 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
5322 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
5323 | ASIC_REV_5714) { | |
5324 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
5325 | bmsr |= BMSR_LSTATUS; | |
5326 | else | |
5327 | bmsr &= ~BMSR_LSTATUS; | |
5328 | } | |
f07e9af3 | 5329 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5330 | } |
5331 | } | |
5332 | ||
5333 | if (bmsr & BMSR_LSTATUS) { | |
5334 | current_speed = SPEED_1000; | |
5335 | current_link_up = 1; | |
5336 | if (bmcr & BMCR_FULLDPLX) | |
5337 | current_duplex = DUPLEX_FULL; | |
5338 | else | |
5339 | current_duplex = DUPLEX_HALF; | |
5340 | ||
ef167e27 MC |
5341 | local_adv = 0; |
5342 | remote_adv = 0; | |
5343 | ||
747e8f8b | 5344 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 5345 | u32 common; |
747e8f8b MC |
5346 | |
5347 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
5348 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
5349 | common = local_adv & remote_adv; | |
5350 | if (common & (ADVERTISE_1000XHALF | | |
5351 | ADVERTISE_1000XFULL)) { | |
5352 | if (common & ADVERTISE_1000XFULL) | |
5353 | current_duplex = DUPLEX_FULL; | |
5354 | else | |
5355 | current_duplex = DUPLEX_HALF; | |
859edb26 MC |
5356 | |
5357 | tp->link_config.rmt_adv = | |
5358 | mii_adv_to_ethtool_adv_x(remote_adv); | |
63c3a66f | 5359 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
57d8b880 | 5360 | /* Link is up via parallel detect */ |
859a5887 | 5361 | } else { |
747e8f8b | 5362 | current_link_up = 0; |
859a5887 | 5363 | } |
747e8f8b MC |
5364 | } |
5365 | } | |
5366 | ||
ef167e27 MC |
5367 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
5368 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
5369 | ||
747e8f8b MC |
5370 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
5371 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
5372 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
5373 | ||
5374 | tw32_f(MAC_MODE, tp->mac_mode); | |
5375 | udelay(40); | |
5376 | ||
5377 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
5378 | ||
5379 | tp->link_config.active_speed = current_speed; | |
5380 | tp->link_config.active_duplex = current_duplex; | |
5381 | ||
f4a46d1f | 5382 | tg3_test_and_report_link_chg(tp, current_link_up); |
747e8f8b MC |
5383 | return err; |
5384 | } | |
5385 | ||
5386 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
5387 | { | |
3d3ebe74 | 5388 | if (tp->serdes_counter) { |
747e8f8b | 5389 | /* Give autoneg time to complete. */ |
3d3ebe74 | 5390 | tp->serdes_counter--; |
747e8f8b MC |
5391 | return; |
5392 | } | |
c6cdf436 | 5393 | |
f4a46d1f | 5394 | if (!tp->link_up && |
747e8f8b MC |
5395 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { |
5396 | u32 bmcr; | |
5397 | ||
5398 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
5399 | if (bmcr & BMCR_ANENABLE) { | |
5400 | u32 phy1, phy2; | |
5401 | ||
5402 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
5403 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
5404 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
5405 | |
5406 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
5407 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
5408 | MII_TG3_DSP_EXP1_INT_STAT); | |
5409 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
5410 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
5411 | |
5412 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
5413 | /* We have signal detect and not receiving | |
5414 | * config code words, link is up by parallel | |
5415 | * detection. | |
5416 | */ | |
5417 | ||
5418 | bmcr &= ~BMCR_ANENABLE; | |
5419 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
5420 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 5421 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5422 | } |
5423 | } | |
f4a46d1f | 5424 | } else if (tp->link_up && |
859a5887 | 5425 | (tp->link_config.autoneg == AUTONEG_ENABLE) && |
f07e9af3 | 5426 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
5427 | u32 phy2; |
5428 | ||
5429 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
5430 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
5431 | MII_TG3_DSP_EXP1_INT_STAT); | |
5432 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
5433 | if (phy2 & 0x20) { |
5434 | u32 bmcr; | |
5435 | ||
5436 | /* Config code words received, turn on autoneg. */ | |
5437 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
5438 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
5439 | ||
f07e9af3 | 5440 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
5441 | |
5442 | } | |
5443 | } | |
5444 | } | |
5445 | ||
1da177e4 LT |
5446 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
5447 | { | |
f2096f94 | 5448 | u32 val; |
1da177e4 LT |
5449 | int err; |
5450 | ||
f07e9af3 | 5451 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 5452 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 5453 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 5454 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 5455 | else |
1da177e4 | 5456 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 5457 | |
bcb37f6c | 5458 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
f2096f94 | 5459 | u32 scale; |
aa6c91fe MC |
5460 | |
5461 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
5462 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
5463 | scale = 65; | |
5464 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
5465 | scale = 6; | |
5466 | else | |
5467 | scale = 12; | |
5468 | ||
5469 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
5470 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
5471 | tw32(GRC_MISC_CFG, val); | |
5472 | } | |
5473 | ||
f2096f94 MC |
5474 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
5475 | (6 << TX_LENGTHS_IPG_SHIFT); | |
5476 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
5477 | val |= tr32(MAC_TX_LENGTHS) & | |
5478 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
5479 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
5480 | ||
1da177e4 LT |
5481 | if (tp->link_config.active_speed == SPEED_1000 && |
5482 | tp->link_config.active_duplex == DUPLEX_HALF) | |
f2096f94 MC |
5483 | tw32(MAC_TX_LENGTHS, val | |
5484 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 5485 | else |
f2096f94 MC |
5486 | tw32(MAC_TX_LENGTHS, val | |
5487 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 5488 | |
63c3a66f | 5489 | if (!tg3_flag(tp, 5705_PLUS)) { |
f4a46d1f | 5490 | if (tp->link_up) { |
1da177e4 | 5491 | tw32(HOSTCC_STAT_COAL_TICKS, |
15f9850d | 5492 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
5493 | } else { |
5494 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
5495 | } | |
5496 | } | |
5497 | ||
63c3a66f | 5498 | if (tg3_flag(tp, ASPM_WORKAROUND)) { |
f2096f94 | 5499 | val = tr32(PCIE_PWR_MGMT_THRESH); |
f4a46d1f | 5500 | if (!tp->link_up) |
8ed5d97e MC |
5501 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | |
5502 | tp->pwrmgmt_thresh; | |
5503 | else | |
5504 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
5505 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
5506 | } | |
5507 | ||
1da177e4 LT |
5508 | return err; |
5509 | } | |
5510 | ||
66cfd1bd MC |
5511 | static inline int tg3_irq_sync(struct tg3 *tp) |
5512 | { | |
5513 | return tp->irq_sync; | |
5514 | } | |
5515 | ||
97bd8e49 MC |
5516 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
5517 | { | |
5518 | int i; | |
5519 | ||
5520 | dst = (u32 *)((u8 *)dst + off); | |
5521 | for (i = 0; i < len; i += sizeof(u32)) | |
5522 | *dst++ = tr32(off + i); | |
5523 | } | |
5524 | ||
5525 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
5526 | { | |
5527 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
5528 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
5529 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
5530 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
5531 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
5532 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
5533 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
5534 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
5535 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
5536 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
5537 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
5538 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
5539 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
5540 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
5541 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
5542 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
5543 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
5544 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
5545 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
5546 | ||
63c3a66f | 5547 | if (tg3_flag(tp, SUPPORT_MSIX)) |
97bd8e49 MC |
5548 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); |
5549 | ||
5550 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
5551 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
5552 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
5553 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
5554 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
5555 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
5556 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
5557 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
5558 | ||
63c3a66f | 5559 | if (!tg3_flag(tp, 5705_PLUS)) { |
97bd8e49 MC |
5560 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); |
5561 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
5562 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
5563 | } | |
5564 | ||
5565 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
5566 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
5567 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
5568 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
5569 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
5570 | ||
63c3a66f | 5571 | if (tg3_flag(tp, NVRAM)) |
97bd8e49 MC |
5572 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); |
5573 | } | |
5574 | ||
5575 | static void tg3_dump_state(struct tg3 *tp) | |
5576 | { | |
5577 | int i; | |
5578 | u32 *regs; | |
5579 | ||
5580 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
5581 | if (!regs) { | |
5582 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
5583 | return; | |
5584 | } | |
5585 | ||
63c3a66f | 5586 | if (tg3_flag(tp, PCI_EXPRESS)) { |
97bd8e49 MC |
5587 | /* Read up to but not including private PCI registers */ |
5588 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
5589 | regs[i / sizeof(u32)] = tr32(i); | |
5590 | } else | |
5591 | tg3_dump_legacy_regs(tp, regs); | |
5592 | ||
5593 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
5594 | if (!regs[i + 0] && !regs[i + 1] && | |
5595 | !regs[i + 2] && !regs[i + 3]) | |
5596 | continue; | |
5597 | ||
5598 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
5599 | i * 4, | |
5600 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
5601 | } | |
5602 | ||
5603 | kfree(regs); | |
5604 | ||
5605 | for (i = 0; i < tp->irq_cnt; i++) { | |
5606 | struct tg3_napi *tnapi = &tp->napi[i]; | |
5607 | ||
5608 | /* SW status block */ | |
5609 | netdev_err(tp->dev, | |
5610 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
5611 | i, | |
5612 | tnapi->hw_status->status, | |
5613 | tnapi->hw_status->status_tag, | |
5614 | tnapi->hw_status->rx_jumbo_consumer, | |
5615 | tnapi->hw_status->rx_consumer, | |
5616 | tnapi->hw_status->rx_mini_consumer, | |
5617 | tnapi->hw_status->idx[0].rx_producer, | |
5618 | tnapi->hw_status->idx[0].tx_consumer); | |
5619 | ||
5620 | netdev_err(tp->dev, | |
5621 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
5622 | i, | |
5623 | tnapi->last_tag, tnapi->last_irq_tag, | |
5624 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
5625 | tnapi->rx_rcb_ptr, | |
5626 | tnapi->prodring.rx_std_prod_idx, | |
5627 | tnapi->prodring.rx_std_cons_idx, | |
5628 | tnapi->prodring.rx_jmb_prod_idx, | |
5629 | tnapi->prodring.rx_jmb_cons_idx); | |
5630 | } | |
5631 | } | |
5632 | ||
df3e6548 MC |
5633 | /* This is called whenever we suspect that the system chipset is re- |
5634 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
5635 | * is bogus tx completions. We try to recover by setting the | |
5636 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
5637 | * in the workqueue. | |
5638 | */ | |
5639 | static void tg3_tx_recover(struct tg3 *tp) | |
5640 | { | |
63c3a66f | 5641 | BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || |
df3e6548 MC |
5642 | tp->write32_tx_mbox == tg3_write_indirect_mbox); |
5643 | ||
5129c3a3 MC |
5644 | netdev_warn(tp->dev, |
5645 | "The system may be re-ordering memory-mapped I/O " | |
5646 | "cycles to the network device, attempting to recover. " | |
5647 | "Please report the problem to the driver maintainer " | |
5648 | "and include system chipset information.\n"); | |
df3e6548 MC |
5649 | |
5650 | spin_lock(&tp->lock); | |
63c3a66f | 5651 | tg3_flag_set(tp, TX_RECOVERY_PENDING); |
df3e6548 MC |
5652 | spin_unlock(&tp->lock); |
5653 | } | |
5654 | ||
f3f3f27e | 5655 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 5656 | { |
f65aac16 MC |
5657 | /* Tell compiler to fetch tx indices from memory. */ |
5658 | barrier(); | |
f3f3f27e MC |
5659 | return tnapi->tx_pending - |
5660 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
5661 | } |
5662 | ||
1da177e4 LT |
5663 | /* Tigon3 never reports partial packet sends. So we do not |
5664 | * need special logic to handle SKBs that have not had all | |
5665 | * of their frags sent yet, like SunGEM does. | |
5666 | */ | |
17375d25 | 5667 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 5668 | { |
17375d25 | 5669 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 5670 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 5671 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
5672 | struct netdev_queue *txq; |
5673 | int index = tnapi - tp->napi; | |
298376d3 | 5674 | unsigned int pkts_compl = 0, bytes_compl = 0; |
fe5f5787 | 5675 | |
63c3a66f | 5676 | if (tg3_flag(tp, ENABLE_TSS)) |
fe5f5787 MC |
5677 | index--; |
5678 | ||
5679 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
5680 | |
5681 | while (sw_idx != hw_idx) { | |
df8944cf | 5682 | struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 5683 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
5684 | int i, tx_bug = 0; |
5685 | ||
5686 | if (unlikely(skb == NULL)) { | |
5687 | tg3_tx_recover(tp); | |
5688 | return; | |
5689 | } | |
1da177e4 | 5690 | |
f4188d8a | 5691 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 5692 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
5693 | skb_headlen(skb), |
5694 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
5695 | |
5696 | ri->skb = NULL; | |
5697 | ||
e01ee14d MC |
5698 | while (ri->fragmented) { |
5699 | ri->fragmented = false; | |
5700 | sw_idx = NEXT_TX(sw_idx); | |
5701 | ri = &tnapi->tx_buffers[sw_idx]; | |
5702 | } | |
5703 | ||
1da177e4 LT |
5704 | sw_idx = NEXT_TX(sw_idx); |
5705 | ||
5706 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 5707 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
5708 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
5709 | tx_bug = 1; | |
f4188d8a AD |
5710 | |
5711 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 5712 | dma_unmap_addr(ri, mapping), |
9e903e08 | 5713 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
f4188d8a | 5714 | PCI_DMA_TODEVICE); |
e01ee14d MC |
5715 | |
5716 | while (ri->fragmented) { | |
5717 | ri->fragmented = false; | |
5718 | sw_idx = NEXT_TX(sw_idx); | |
5719 | ri = &tnapi->tx_buffers[sw_idx]; | |
5720 | } | |
5721 | ||
1da177e4 LT |
5722 | sw_idx = NEXT_TX(sw_idx); |
5723 | } | |
5724 | ||
298376d3 TH |
5725 | pkts_compl++; |
5726 | bytes_compl += skb->len; | |
5727 | ||
f47c11ee | 5728 | dev_kfree_skb(skb); |
df3e6548 MC |
5729 | |
5730 | if (unlikely(tx_bug)) { | |
5731 | tg3_tx_recover(tp); | |
5732 | return; | |
5733 | } | |
1da177e4 LT |
5734 | } |
5735 | ||
5cb917bc | 5736 | netdev_tx_completed_queue(txq, pkts_compl, bytes_compl); |
298376d3 | 5737 | |
f3f3f27e | 5738 | tnapi->tx_cons = sw_idx; |
1da177e4 | 5739 | |
1b2a7205 MC |
5740 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
5741 | * before checking for netif_queue_stopped(). Without the | |
5742 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
5743 | * will miss it and cause the queue to be stopped forever. | |
5744 | */ | |
5745 | smp_mb(); | |
5746 | ||
fe5f5787 | 5747 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 5748 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
5749 | __netif_tx_lock(txq, smp_processor_id()); |
5750 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 5751 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
5752 | netif_tx_wake_queue(txq); |
5753 | __netif_tx_unlock(txq); | |
51b91468 | 5754 | } |
1da177e4 LT |
5755 | } |
5756 | ||
8d4057a9 ED |
5757 | static void tg3_frag_free(bool is_frag, void *data) |
5758 | { | |
5759 | if (is_frag) | |
5760 | put_page(virt_to_head_page(data)); | |
5761 | else | |
5762 | kfree(data); | |
5763 | } | |
5764 | ||
9205fd9c | 5765 | static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
2b2cdb65 | 5766 | { |
8d4057a9 ED |
5767 | unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) + |
5768 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
5769 | ||
9205fd9c | 5770 | if (!ri->data) |
2b2cdb65 MC |
5771 | return; |
5772 | ||
4e5e4f0d | 5773 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 | 5774 | map_sz, PCI_DMA_FROMDEVICE); |
a1e8b307 | 5775 | tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); |
9205fd9c | 5776 | ri->data = NULL; |
2b2cdb65 MC |
5777 | } |
5778 | ||
8d4057a9 | 5779 | |
1da177e4 LT |
5780 | /* Returns size of skb allocated or < 0 on error. |
5781 | * | |
5782 | * We only need to fill in the address because the other members | |
5783 | * of the RX descriptor are invariant, see tg3_init_rings. | |
5784 | * | |
5785 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
5786 | * posting buffers we only dirty the first cache line of the RX | |
5787 | * descriptor (containing the address). Whereas for the RX status | |
5788 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
5789 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
5790 | */ | |
9205fd9c | 5791 | static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
8d4057a9 ED |
5792 | u32 opaque_key, u32 dest_idx_unmasked, |
5793 | unsigned int *frag_size) | |
1da177e4 LT |
5794 | { |
5795 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 5796 | struct ring_info *map; |
9205fd9c | 5797 | u8 *data; |
1da177e4 | 5798 | dma_addr_t mapping; |
9205fd9c | 5799 | int skb_size, data_size, dest_idx; |
1da177e4 | 5800 | |
1da177e4 LT |
5801 | switch (opaque_key) { |
5802 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 5803 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
5804 | desc = &tpr->rx_std[dest_idx]; |
5805 | map = &tpr->rx_std_buffers[dest_idx]; | |
9205fd9c | 5806 | data_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
5807 | break; |
5808 | ||
5809 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 5810 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 5811 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 5812 | map = &tpr->rx_jmb_buffers[dest_idx]; |
9205fd9c | 5813 | data_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
5814 | break; |
5815 | ||
5816 | default: | |
5817 | return -EINVAL; | |
855e1111 | 5818 | } |
1da177e4 LT |
5819 | |
5820 | /* Do not overwrite any of the map or rp information | |
5821 | * until we are sure we can commit to a new buffer. | |
5822 | * | |
5823 | * Callers depend upon this behavior and assume that | |
5824 | * we leave everything unchanged if we fail. | |
5825 | */ | |
9205fd9c ED |
5826 | skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + |
5827 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
a1e8b307 ED |
5828 | if (skb_size <= PAGE_SIZE) { |
5829 | data = netdev_alloc_frag(skb_size); | |
5830 | *frag_size = skb_size; | |
8d4057a9 ED |
5831 | } else { |
5832 | data = kmalloc(skb_size, GFP_ATOMIC); | |
5833 | *frag_size = 0; | |
5834 | } | |
9205fd9c | 5835 | if (!data) |
1da177e4 LT |
5836 | return -ENOMEM; |
5837 | ||
9205fd9c ED |
5838 | mapping = pci_map_single(tp->pdev, |
5839 | data + TG3_RX_OFFSET(tp), | |
5840 | data_size, | |
1da177e4 | 5841 | PCI_DMA_FROMDEVICE); |
8d4057a9 | 5842 | if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) { |
a1e8b307 | 5843 | tg3_frag_free(skb_size <= PAGE_SIZE, data); |
a21771dd MC |
5844 | return -EIO; |
5845 | } | |
1da177e4 | 5846 | |
9205fd9c | 5847 | map->data = data; |
4e5e4f0d | 5848 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 5849 | |
1da177e4 LT |
5850 | desc->addr_hi = ((u64)mapping >> 32); |
5851 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
5852 | ||
9205fd9c | 5853 | return data_size; |
1da177e4 LT |
5854 | } |
5855 | ||
5856 | /* We only need to move over in the address because the other | |
5857 | * members of the RX descriptor are invariant. See notes above | |
9205fd9c | 5858 | * tg3_alloc_rx_data for full details. |
1da177e4 | 5859 | */ |
a3896167 MC |
5860 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
5861 | struct tg3_rx_prodring_set *dpr, | |
5862 | u32 opaque_key, int src_idx, | |
5863 | u32 dest_idx_unmasked) | |
1da177e4 | 5864 | { |
17375d25 | 5865 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
5866 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
5867 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 5868 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 5869 | int dest_idx; |
1da177e4 LT |
5870 | |
5871 | switch (opaque_key) { | |
5872 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 5873 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
5874 | dest_desc = &dpr->rx_std[dest_idx]; |
5875 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
5876 | src_desc = &spr->rx_std[src_idx]; | |
5877 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
5878 | break; |
5879 | ||
5880 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 5881 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
5882 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
5883 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
5884 | src_desc = &spr->rx_jmb[src_idx].std; | |
5885 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
5886 | break; |
5887 | ||
5888 | default: | |
5889 | return; | |
855e1111 | 5890 | } |
1da177e4 | 5891 | |
9205fd9c | 5892 | dest_map->data = src_map->data; |
4e5e4f0d FT |
5893 | dma_unmap_addr_set(dest_map, mapping, |
5894 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
5895 | dest_desc->addr_hi = src_desc->addr_hi; |
5896 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
5897 | |
5898 | /* Ensure that the update to the skb happens after the physical | |
5899 | * addresses have been transferred to the new BD location. | |
5900 | */ | |
5901 | smp_wmb(); | |
5902 | ||
9205fd9c | 5903 | src_map->data = NULL; |
1da177e4 LT |
5904 | } |
5905 | ||
1da177e4 LT |
5906 | /* The RX ring scheme is composed of multiple rings which post fresh |
5907 | * buffers to the chip, and one special ring the chip uses to report | |
5908 | * status back to the host. | |
5909 | * | |
5910 | * The special ring reports the status of received packets to the | |
5911 | * host. The chip does not write into the original descriptor the | |
5912 | * RX buffer was obtained from. The chip simply takes the original | |
5913 | * descriptor as provided by the host, updates the status and length | |
5914 | * field, then writes this into the next status ring entry. | |
5915 | * | |
5916 | * Each ring the host uses to post buffers to the chip is described | |
5917 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
5918 | * it is first placed into the on-chip ram. When the packet's length | |
5919 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
5920 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
5921 | * which is within the range of the new packet's length is chosen. | |
5922 | * | |
5923 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
5924 | * sense from a cache coherency perspective. If only the host writes | |
5925 | * to the buffer post rings, and only the chip writes to the rx status | |
5926 | * rings, then cache lines never move beyond shared-modified state. | |
5927 | * If both the host and chip were to write into the same ring, cache line | |
5928 | * eviction could occur since both entities want it in an exclusive state. | |
5929 | */ | |
17375d25 | 5930 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 5931 | { |
17375d25 | 5932 | struct tg3 *tp = tnapi->tp; |
f92905de | 5933 | u32 work_mask, rx_std_posted = 0; |
4361935a | 5934 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 5935 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 5936 | u16 hw_idx; |
1da177e4 | 5937 | int received; |
8fea32b9 | 5938 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 5939 | |
8d9d7cfc | 5940 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
5941 | /* |
5942 | * We need to order the read of hw_idx and the read of | |
5943 | * the opaque cookie. | |
5944 | */ | |
5945 | rmb(); | |
1da177e4 LT |
5946 | work_mask = 0; |
5947 | received = 0; | |
4361935a MC |
5948 | std_prod_idx = tpr->rx_std_prod_idx; |
5949 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 5950 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 5951 | struct ring_info *ri; |
72334482 | 5952 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
5953 | unsigned int len; |
5954 | struct sk_buff *skb; | |
5955 | dma_addr_t dma_addr; | |
5956 | u32 opaque_key, desc_idx, *post_ptr; | |
9205fd9c | 5957 | u8 *data; |
1da177e4 LT |
5958 | |
5959 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
5960 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
5961 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 5962 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 5963 | dma_addr = dma_unmap_addr(ri, mapping); |
9205fd9c | 5964 | data = ri->data; |
4361935a | 5965 | post_ptr = &std_prod_idx; |
f92905de | 5966 | rx_std_posted++; |
1da177e4 | 5967 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 5968 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 5969 | dma_addr = dma_unmap_addr(ri, mapping); |
9205fd9c | 5970 | data = ri->data; |
4361935a | 5971 | post_ptr = &jmb_prod_idx; |
21f581a5 | 5972 | } else |
1da177e4 | 5973 | goto next_pkt_nopost; |
1da177e4 LT |
5974 | |
5975 | work_mask |= opaque_key; | |
5976 | ||
5977 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
5978 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
5979 | drop_it: | |
a3896167 | 5980 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
5981 | desc_idx, *post_ptr); |
5982 | drop_it_no_recycle: | |
5983 | /* Other statistics kept track of by card. */ | |
b0057c51 | 5984 | tp->rx_dropped++; |
1da177e4 LT |
5985 | goto next_pkt; |
5986 | } | |
5987 | ||
9205fd9c | 5988 | prefetch(data + TG3_RX_OFFSET(tp)); |
ad829268 MC |
5989 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
5990 | ETH_FCS_LEN; | |
1da177e4 | 5991 | |
d2757fc4 | 5992 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 | 5993 | int skb_size; |
8d4057a9 | 5994 | unsigned int frag_size; |
1da177e4 | 5995 | |
9205fd9c | 5996 | skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, |
8d4057a9 | 5997 | *post_ptr, &frag_size); |
1da177e4 LT |
5998 | if (skb_size < 0) |
5999 | goto drop_it; | |
6000 | ||
287be12e | 6001 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
6002 | PCI_DMA_FROMDEVICE); |
6003 | ||
8d4057a9 | 6004 | skb = build_skb(data, frag_size); |
9205fd9c | 6005 | if (!skb) { |
8d4057a9 | 6006 | tg3_frag_free(frag_size != 0, data); |
9205fd9c ED |
6007 | goto drop_it_no_recycle; |
6008 | } | |
6009 | skb_reserve(skb, TG3_RX_OFFSET(tp)); | |
6010 | /* Ensure that the update to the data happens | |
61e800cf MC |
6011 | * after the usage of the old DMA mapping. |
6012 | */ | |
6013 | smp_wmb(); | |
6014 | ||
9205fd9c | 6015 | ri->data = NULL; |
61e800cf | 6016 | |
1da177e4 | 6017 | } else { |
a3896167 | 6018 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
6019 | desc_idx, *post_ptr); |
6020 | ||
9205fd9c ED |
6021 | skb = netdev_alloc_skb(tp->dev, |
6022 | len + TG3_RAW_IP_ALIGN); | |
6023 | if (skb == NULL) | |
1da177e4 LT |
6024 | goto drop_it_no_recycle; |
6025 | ||
9205fd9c | 6026 | skb_reserve(skb, TG3_RAW_IP_ALIGN); |
1da177e4 | 6027 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
9205fd9c ED |
6028 | memcpy(skb->data, |
6029 | data + TG3_RX_OFFSET(tp), | |
6030 | len); | |
1da177e4 | 6031 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
6032 | } |
6033 | ||
9205fd9c | 6034 | skb_put(skb, len); |
dc668910 | 6035 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
1da177e4 LT |
6036 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
6037 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
6038 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
6039 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
6040 | else | |
bc8acf2c | 6041 | skb_checksum_none_assert(skb); |
1da177e4 LT |
6042 | |
6043 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
6044 | |
6045 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
6046 | skb->protocol != htons(ETH_P_8021Q)) { | |
6047 | dev_kfree_skb(skb); | |
b0057c51 | 6048 | goto drop_it_no_recycle; |
f7b493e0 MC |
6049 | } |
6050 | ||
9dc7a113 | 6051 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
6052 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
6053 | __vlan_hwaccel_put_tag(skb, | |
6054 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 6055 | |
bf933c80 | 6056 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 6057 | |
1da177e4 LT |
6058 | received++; |
6059 | budget--; | |
6060 | ||
6061 | next_pkt: | |
6062 | (*post_ptr)++; | |
f92905de MC |
6063 | |
6064 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
6065 | tpr->rx_std_prod_idx = std_prod_idx & |
6066 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
6067 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
6068 | tpr->rx_std_prod_idx); | |
f92905de MC |
6069 | work_mask &= ~RXD_OPAQUE_RING_STD; |
6070 | rx_std_posted = 0; | |
6071 | } | |
1da177e4 | 6072 | next_pkt_nopost: |
483ba50b | 6073 | sw_idx++; |
7cb32cf2 | 6074 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
6075 | |
6076 | /* Refresh hw_idx to see if there is new work */ | |
6077 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 6078 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
6079 | rmb(); |
6080 | } | |
1da177e4 LT |
6081 | } |
6082 | ||
6083 | /* ACK the status ring. */ | |
72334482 MC |
6084 | tnapi->rx_rcb_ptr = sw_idx; |
6085 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
6086 | |
6087 | /* Refill RX ring(s). */ | |
63c3a66f | 6088 | if (!tg3_flag(tp, ENABLE_RSS)) { |
6541b806 MC |
6089 | /* Sync BD data before updating mailbox */ |
6090 | wmb(); | |
6091 | ||
b196c7e4 | 6092 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
6093 | tpr->rx_std_prod_idx = std_prod_idx & |
6094 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
6095 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
6096 | tpr->rx_std_prod_idx); | |
6097 | } | |
6098 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
6099 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
6100 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
6101 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
6102 | tpr->rx_jmb_prod_idx); | |
6103 | } | |
6104 | mmiowb(); | |
6105 | } else if (work_mask) { | |
6106 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
6107 | * updated before the producer indices can be updated. | |
6108 | */ | |
6109 | smp_wmb(); | |
6110 | ||
2c49a44d MC |
6111 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
6112 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 6113 | |
7ae52890 MC |
6114 | if (tnapi != &tp->napi[1]) { |
6115 | tp->rx_refill = true; | |
e4af1af9 | 6116 | napi_schedule(&tp->napi[1].napi); |
7ae52890 | 6117 | } |
1da177e4 | 6118 | } |
1da177e4 LT |
6119 | |
6120 | return received; | |
6121 | } | |
6122 | ||
35f2d7d0 | 6123 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 6124 | { |
1da177e4 | 6125 | /* handle link change and other phy events */ |
63c3a66f | 6126 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
35f2d7d0 MC |
6127 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
6128 | ||
1da177e4 LT |
6129 | if (sblk->status & SD_STATUS_LINK_CHG) { |
6130 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 6131 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 6132 | spin_lock(&tp->lock); |
63c3a66f | 6133 | if (tg3_flag(tp, USE_PHYLIB)) { |
dd477003 MC |
6134 | tw32_f(MAC_STATUS, |
6135 | (MAC_STATUS_SYNC_CHANGED | | |
6136 | MAC_STATUS_CFG_CHANGED | | |
6137 | MAC_STATUS_MI_COMPLETION | | |
6138 | MAC_STATUS_LNKSTATE_CHANGED)); | |
6139 | udelay(40); | |
6140 | } else | |
6141 | tg3_setup_phy(tp, 0); | |
f47c11ee | 6142 | spin_unlock(&tp->lock); |
1da177e4 LT |
6143 | } |
6144 | } | |
35f2d7d0 MC |
6145 | } |
6146 | ||
f89f38b8 MC |
6147 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
6148 | struct tg3_rx_prodring_set *dpr, | |
6149 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
6150 | { |
6151 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 6152 | int i, err = 0; |
b196c7e4 MC |
6153 | |
6154 | while (1) { | |
6155 | src_prod_idx = spr->rx_std_prod_idx; | |
6156 | ||
6157 | /* Make sure updates to the rx_std_buffers[] entries and the | |
6158 | * standard producer index are seen in the correct order. | |
6159 | */ | |
6160 | smp_rmb(); | |
6161 | ||
6162 | if (spr->rx_std_cons_idx == src_prod_idx) | |
6163 | break; | |
6164 | ||
6165 | if (spr->rx_std_cons_idx < src_prod_idx) | |
6166 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
6167 | else | |
2c49a44d MC |
6168 | cpycnt = tp->rx_std_ring_mask + 1 - |
6169 | spr->rx_std_cons_idx; | |
b196c7e4 | 6170 | |
2c49a44d MC |
6171 | cpycnt = min(cpycnt, |
6172 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
6173 | |
6174 | si = spr->rx_std_cons_idx; | |
6175 | di = dpr->rx_std_prod_idx; | |
6176 | ||
e92967bf | 6177 | for (i = di; i < di + cpycnt; i++) { |
9205fd9c | 6178 | if (dpr->rx_std_buffers[i].data) { |
e92967bf | 6179 | cpycnt = i - di; |
f89f38b8 | 6180 | err = -ENOSPC; |
e92967bf MC |
6181 | break; |
6182 | } | |
6183 | } | |
6184 | ||
6185 | if (!cpycnt) | |
6186 | break; | |
6187 | ||
6188 | /* Ensure that updates to the rx_std_buffers ring and the | |
6189 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
6190 | * ordered correctly WRT the skb check above. | |
6191 | */ | |
6192 | smp_rmb(); | |
6193 | ||
b196c7e4 MC |
6194 | memcpy(&dpr->rx_std_buffers[di], |
6195 | &spr->rx_std_buffers[si], | |
6196 | cpycnt * sizeof(struct ring_info)); | |
6197 | ||
6198 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
6199 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
6200 | sbd = &spr->rx_std[si]; | |
6201 | dbd = &dpr->rx_std[di]; | |
6202 | dbd->addr_hi = sbd->addr_hi; | |
6203 | dbd->addr_lo = sbd->addr_lo; | |
6204 | } | |
6205 | ||
2c49a44d MC |
6206 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
6207 | tp->rx_std_ring_mask; | |
6208 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
6209 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
6210 | } |
6211 | ||
6212 | while (1) { | |
6213 | src_prod_idx = spr->rx_jmb_prod_idx; | |
6214 | ||
6215 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
6216 | * the jumbo producer index are seen in the correct order. | |
6217 | */ | |
6218 | smp_rmb(); | |
6219 | ||
6220 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
6221 | break; | |
6222 | ||
6223 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
6224 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
6225 | else | |
2c49a44d MC |
6226 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
6227 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
6228 | |
6229 | cpycnt = min(cpycnt, | |
2c49a44d | 6230 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
6231 | |
6232 | si = spr->rx_jmb_cons_idx; | |
6233 | di = dpr->rx_jmb_prod_idx; | |
6234 | ||
e92967bf | 6235 | for (i = di; i < di + cpycnt; i++) { |
9205fd9c | 6236 | if (dpr->rx_jmb_buffers[i].data) { |
e92967bf | 6237 | cpycnt = i - di; |
f89f38b8 | 6238 | err = -ENOSPC; |
e92967bf MC |
6239 | break; |
6240 | } | |
6241 | } | |
6242 | ||
6243 | if (!cpycnt) | |
6244 | break; | |
6245 | ||
6246 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
6247 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
6248 | * ordered correctly WRT the skb check above. | |
6249 | */ | |
6250 | smp_rmb(); | |
6251 | ||
b196c7e4 MC |
6252 | memcpy(&dpr->rx_jmb_buffers[di], |
6253 | &spr->rx_jmb_buffers[si], | |
6254 | cpycnt * sizeof(struct ring_info)); | |
6255 | ||
6256 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
6257 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
6258 | sbd = &spr->rx_jmb[si].std; | |
6259 | dbd = &dpr->rx_jmb[di].std; | |
6260 | dbd->addr_hi = sbd->addr_hi; | |
6261 | dbd->addr_lo = sbd->addr_lo; | |
6262 | } | |
6263 | ||
2c49a44d MC |
6264 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
6265 | tp->rx_jmb_ring_mask; | |
6266 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
6267 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 6268 | } |
f89f38b8 MC |
6269 | |
6270 | return err; | |
b196c7e4 MC |
6271 | } |
6272 | ||
35f2d7d0 MC |
6273 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
6274 | { | |
6275 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
6276 | |
6277 | /* run TX completion thread */ | |
f3f3f27e | 6278 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 6279 | tg3_tx(tnapi); |
63c3a66f | 6280 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
4fd7ab59 | 6281 | return work_done; |
1da177e4 LT |
6282 | } |
6283 | ||
f891ea16 MC |
6284 | if (!tnapi->rx_rcb_prod_idx) |
6285 | return work_done; | |
6286 | ||
1da177e4 LT |
6287 | /* run RX thread, within the bounds set by NAPI. |
6288 | * All RX "locking" is done by ensuring outside | |
bea3348e | 6289 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 6290 | */ |
8d9d7cfc | 6291 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 6292 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 6293 | |
63c3a66f | 6294 | if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 6295 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 6296 | int i, err = 0; |
e4af1af9 MC |
6297 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
6298 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 6299 | |
7ae52890 | 6300 | tp->rx_refill = false; |
9102426a | 6301 | for (i = 1; i <= tp->rxq_cnt; i++) |
f89f38b8 | 6302 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 6303 | &tp->napi[i].prodring); |
b196c7e4 MC |
6304 | |
6305 | wmb(); | |
6306 | ||
e4af1af9 MC |
6307 | if (std_prod_idx != dpr->rx_std_prod_idx) |
6308 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
6309 | dpr->rx_std_prod_idx); | |
b196c7e4 | 6310 | |
e4af1af9 MC |
6311 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
6312 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
6313 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
6314 | |
6315 | mmiowb(); | |
f89f38b8 MC |
6316 | |
6317 | if (err) | |
6318 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
6319 | } |
6320 | ||
6f535763 DM |
6321 | return work_done; |
6322 | } | |
6323 | ||
db219973 MC |
6324 | static inline void tg3_reset_task_schedule(struct tg3 *tp) |
6325 | { | |
6326 | if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) | |
6327 | schedule_work(&tp->reset_task); | |
6328 | } | |
6329 | ||
6330 | static inline void tg3_reset_task_cancel(struct tg3 *tp) | |
6331 | { | |
6332 | cancel_work_sync(&tp->reset_task); | |
6333 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
c7101359 | 6334 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); |
db219973 MC |
6335 | } |
6336 | ||
35f2d7d0 MC |
6337 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
6338 | { | |
6339 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
6340 | struct tg3 *tp = tnapi->tp; | |
6341 | int work_done = 0; | |
6342 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
6343 | ||
6344 | while (1) { | |
6345 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
6346 | ||
63c3a66f | 6347 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
35f2d7d0 MC |
6348 | goto tx_recovery; |
6349 | ||
6350 | if (unlikely(work_done >= budget)) | |
6351 | break; | |
6352 | ||
c6cdf436 | 6353 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
6354 | * to tell the hw how much work has been processed, |
6355 | * so we must read it before checking for more work. | |
6356 | */ | |
6357 | tnapi->last_tag = sblk->status_tag; | |
6358 | tnapi->last_irq_tag = tnapi->last_tag; | |
6359 | rmb(); | |
6360 | ||
6361 | /* check for RX/TX work to do */ | |
6d40db7b MC |
6362 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
6363 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
7ae52890 MC |
6364 | |
6365 | /* This test here is not race free, but will reduce | |
6366 | * the number of interrupts by looping again. | |
6367 | */ | |
6368 | if (tnapi == &tp->napi[1] && tp->rx_refill) | |
6369 | continue; | |
6370 | ||
35f2d7d0 MC |
6371 | napi_complete(napi); |
6372 | /* Reenable interrupts. */ | |
6373 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
7ae52890 MC |
6374 | |
6375 | /* This test here is synchronized by napi_schedule() | |
6376 | * and napi_complete() to close the race condition. | |
6377 | */ | |
6378 | if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { | |
6379 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
6380 | HOSTCC_MODE_ENABLE | | |
6381 | tnapi->coal_now); | |
6382 | } | |
35f2d7d0 MC |
6383 | mmiowb(); |
6384 | break; | |
6385 | } | |
6386 | } | |
6387 | ||
6388 | return work_done; | |
6389 | ||
6390 | tx_recovery: | |
6391 | /* work_done is guaranteed to be less than budget. */ | |
6392 | napi_complete(napi); | |
db219973 | 6393 | tg3_reset_task_schedule(tp); |
35f2d7d0 MC |
6394 | return work_done; |
6395 | } | |
6396 | ||
e64de4e6 MC |
6397 | static void tg3_process_error(struct tg3 *tp) |
6398 | { | |
6399 | u32 val; | |
6400 | bool real_error = false; | |
6401 | ||
63c3a66f | 6402 | if (tg3_flag(tp, ERROR_PROCESSED)) |
e64de4e6 MC |
6403 | return; |
6404 | ||
6405 | /* Check Flow Attention register */ | |
6406 | val = tr32(HOSTCC_FLOW_ATTN); | |
6407 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
6408 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
6409 | real_error = true; | |
6410 | } | |
6411 | ||
6412 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
6413 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
6414 | real_error = true; | |
6415 | } | |
6416 | ||
6417 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
6418 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
6419 | real_error = true; | |
6420 | } | |
6421 | ||
6422 | if (!real_error) | |
6423 | return; | |
6424 | ||
6425 | tg3_dump_state(tp); | |
6426 | ||
63c3a66f | 6427 | tg3_flag_set(tp, ERROR_PROCESSED); |
db219973 | 6428 | tg3_reset_task_schedule(tp); |
e64de4e6 MC |
6429 | } |
6430 | ||
6f535763 DM |
6431 | static int tg3_poll(struct napi_struct *napi, int budget) |
6432 | { | |
8ef0442f MC |
6433 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
6434 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 6435 | int work_done = 0; |
898a56f8 | 6436 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
6437 | |
6438 | while (1) { | |
e64de4e6 MC |
6439 | if (sblk->status & SD_STATUS_ERROR) |
6440 | tg3_process_error(tp); | |
6441 | ||
35f2d7d0 MC |
6442 | tg3_poll_link(tp); |
6443 | ||
17375d25 | 6444 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 | 6445 | |
63c3a66f | 6446 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
6f535763 DM |
6447 | goto tx_recovery; |
6448 | ||
6449 | if (unlikely(work_done >= budget)) | |
6450 | break; | |
6451 | ||
63c3a66f | 6452 | if (tg3_flag(tp, TAGGED_STATUS)) { |
17375d25 | 6453 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
6454 | * to tell the hw how much work has been processed, |
6455 | * so we must read it before checking for more work. | |
6456 | */ | |
898a56f8 MC |
6457 | tnapi->last_tag = sblk->status_tag; |
6458 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
6459 | rmb(); |
6460 | } else | |
6461 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 6462 | |
17375d25 | 6463 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 6464 | napi_complete(napi); |
17375d25 | 6465 | tg3_int_reenable(tnapi); |
6f535763 DM |
6466 | break; |
6467 | } | |
1da177e4 LT |
6468 | } |
6469 | ||
bea3348e | 6470 | return work_done; |
6f535763 DM |
6471 | |
6472 | tx_recovery: | |
4fd7ab59 | 6473 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 6474 | napi_complete(napi); |
db219973 | 6475 | tg3_reset_task_schedule(tp); |
4fd7ab59 | 6476 | return work_done; |
1da177e4 LT |
6477 | } |
6478 | ||
66cfd1bd MC |
6479 | static void tg3_napi_disable(struct tg3 *tp) |
6480 | { | |
6481 | int i; | |
6482 | ||
6483 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
6484 | napi_disable(&tp->napi[i].napi); | |
6485 | } | |
6486 | ||
6487 | static void tg3_napi_enable(struct tg3 *tp) | |
6488 | { | |
6489 | int i; | |
6490 | ||
6491 | for (i = 0; i < tp->irq_cnt; i++) | |
6492 | napi_enable(&tp->napi[i].napi); | |
6493 | } | |
6494 | ||
6495 | static void tg3_napi_init(struct tg3 *tp) | |
6496 | { | |
6497 | int i; | |
6498 | ||
6499 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
6500 | for (i = 1; i < tp->irq_cnt; i++) | |
6501 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
6502 | } | |
6503 | ||
6504 | static void tg3_napi_fini(struct tg3 *tp) | |
6505 | { | |
6506 | int i; | |
6507 | ||
6508 | for (i = 0; i < tp->irq_cnt; i++) | |
6509 | netif_napi_del(&tp->napi[i].napi); | |
6510 | } | |
6511 | ||
6512 | static inline void tg3_netif_stop(struct tg3 *tp) | |
6513 | { | |
6514 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
6515 | tg3_napi_disable(tp); | |
f4a46d1f | 6516 | netif_carrier_off(tp->dev); |
66cfd1bd MC |
6517 | netif_tx_disable(tp->dev); |
6518 | } | |
6519 | ||
6520 | static inline void tg3_netif_start(struct tg3 *tp) | |
6521 | { | |
6522 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
6523 | * appropriate so long as all callers are assured to | |
6524 | * have free tx slots (such as after tg3_init_hw) | |
6525 | */ | |
6526 | netif_tx_wake_all_queues(tp->dev); | |
6527 | ||
f4a46d1f NNS |
6528 | if (tp->link_up) |
6529 | netif_carrier_on(tp->dev); | |
6530 | ||
66cfd1bd MC |
6531 | tg3_napi_enable(tp); |
6532 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
6533 | tg3_enable_ints(tp); | |
6534 | } | |
6535 | ||
f47c11ee DM |
6536 | static void tg3_irq_quiesce(struct tg3 *tp) |
6537 | { | |
4f125f42 MC |
6538 | int i; |
6539 | ||
f47c11ee DM |
6540 | BUG_ON(tp->irq_sync); |
6541 | ||
6542 | tp->irq_sync = 1; | |
6543 | smp_mb(); | |
6544 | ||
4f125f42 MC |
6545 | for (i = 0; i < tp->irq_cnt; i++) |
6546 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
6547 | } |
6548 | ||
f47c11ee DM |
6549 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
6550 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
6551 | * with as well. Most of the time, this is not necessary except when | |
6552 | * shutting down the device. | |
6553 | */ | |
6554 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
6555 | { | |
46966545 | 6556 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
6557 | if (irq_sync) |
6558 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
6559 | } |
6560 | ||
6561 | static inline void tg3_full_unlock(struct tg3 *tp) | |
6562 | { | |
f47c11ee DM |
6563 | spin_unlock_bh(&tp->lock); |
6564 | } | |
6565 | ||
fcfa0a32 MC |
6566 | /* One-shot MSI handler - Chip automatically disables interrupt |
6567 | * after sending MSI so driver doesn't have to do it. | |
6568 | */ | |
7d12e780 | 6569 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 6570 | { |
09943a18 MC |
6571 | struct tg3_napi *tnapi = dev_id; |
6572 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 6573 | |
898a56f8 | 6574 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
6575 | if (tnapi->rx_rcb) |
6576 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
6577 | |
6578 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 6579 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
6580 | |
6581 | return IRQ_HANDLED; | |
6582 | } | |
6583 | ||
88b06bc2 MC |
6584 | /* MSI ISR - No need to check for interrupt sharing and no need to |
6585 | * flush status block and interrupt mailbox. PCI ordering rules | |
6586 | * guarantee that MSI will arrive after the status block. | |
6587 | */ | |
7d12e780 | 6588 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 6589 | { |
09943a18 MC |
6590 | struct tg3_napi *tnapi = dev_id; |
6591 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 6592 | |
898a56f8 | 6593 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
6594 | if (tnapi->rx_rcb) |
6595 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 6596 | /* |
fac9b83e | 6597 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 6598 | * chip-internal interrupt pending events. |
fac9b83e | 6599 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
6600 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
6601 | * event coalescing. | |
6602 | */ | |
5b39de91 | 6603 | tw32_mailbox(tnapi->int_mbox, 0x00000001); |
61487480 | 6604 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 6605 | napi_schedule(&tnapi->napi); |
61487480 | 6606 | |
88b06bc2 MC |
6607 | return IRQ_RETVAL(1); |
6608 | } | |
6609 | ||
7d12e780 | 6610 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 6611 | { |
09943a18 MC |
6612 | struct tg3_napi *tnapi = dev_id; |
6613 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6614 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
6615 | unsigned int handled = 1; |
6616 | ||
1da177e4 LT |
6617 | /* In INTx mode, it is possible for the interrupt to arrive at |
6618 | * the CPU before the status block posted prior to the interrupt. | |
6619 | * Reading the PCI State register will confirm whether the | |
6620 | * interrupt is ours and will flush the status block. | |
6621 | */ | |
d18edcb2 | 6622 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
63c3a66f | 6623 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
6624 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
6625 | handled = 0; | |
f47c11ee | 6626 | goto out; |
fac9b83e | 6627 | } |
d18edcb2 MC |
6628 | } |
6629 | ||
6630 | /* | |
6631 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
6632 | * chip-internal interrupt pending events. | |
6633 | * Writing non-zero to intr-mbox-0 additional tells the | |
6634 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
6635 | * event coalescing. | |
c04cb347 MC |
6636 | * |
6637 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
6638 | * spurious interrupts. The flush impacts performance but | |
6639 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 6640 | */ |
c04cb347 | 6641 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
6642 | if (tg3_irq_sync(tp)) |
6643 | goto out; | |
6644 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 6645 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 6646 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 6647 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
6648 | } else { |
6649 | /* No work, shared interrupt perhaps? re-enable | |
6650 | * interrupts, and flush that PCI write | |
6651 | */ | |
6652 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
6653 | 0x00000000); | |
fac9b83e | 6654 | } |
f47c11ee | 6655 | out: |
fac9b83e DM |
6656 | return IRQ_RETVAL(handled); |
6657 | } | |
6658 | ||
7d12e780 | 6659 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 6660 | { |
09943a18 MC |
6661 | struct tg3_napi *tnapi = dev_id; |
6662 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6663 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
6664 | unsigned int handled = 1; |
6665 | ||
fac9b83e DM |
6666 | /* In INTx mode, it is possible for the interrupt to arrive at |
6667 | * the CPU before the status block posted prior to the interrupt. | |
6668 | * Reading the PCI State register will confirm whether the | |
6669 | * interrupt is ours and will flush the status block. | |
6670 | */ | |
898a56f8 | 6671 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
63c3a66f | 6672 | if (tg3_flag(tp, CHIP_RESETTING) || |
d18edcb2 MC |
6673 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
6674 | handled = 0; | |
f47c11ee | 6675 | goto out; |
1da177e4 | 6676 | } |
d18edcb2 MC |
6677 | } |
6678 | ||
6679 | /* | |
6680 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
6681 | * chip-internal interrupt pending events. | |
6682 | * writing non-zero to intr-mbox-0 additional tells the | |
6683 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
6684 | * event coalescing. | |
c04cb347 MC |
6685 | * |
6686 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
6687 | * spurious interrupts. The flush impacts performance but | |
6688 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 6689 | */ |
c04cb347 | 6690 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
6691 | |
6692 | /* | |
6693 | * In a shared interrupt configuration, sometimes other devices' | |
6694 | * interrupts will scream. We record the current status tag here | |
6695 | * so that the above check can report that the screaming interrupts | |
6696 | * are unhandled. Eventually they will be silenced. | |
6697 | */ | |
898a56f8 | 6698 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 6699 | |
d18edcb2 MC |
6700 | if (tg3_irq_sync(tp)) |
6701 | goto out; | |
624f8e50 | 6702 | |
72334482 | 6703 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 6704 | |
09943a18 | 6705 | napi_schedule(&tnapi->napi); |
624f8e50 | 6706 | |
f47c11ee | 6707 | out: |
1da177e4 LT |
6708 | return IRQ_RETVAL(handled); |
6709 | } | |
6710 | ||
7938109f | 6711 | /* ISR for interrupt test */ |
7d12e780 | 6712 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 6713 | { |
09943a18 MC |
6714 | struct tg3_napi *tnapi = dev_id; |
6715 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 6716 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 6717 | |
f9804ddb MC |
6718 | if ((sblk->status & SD_STATUS_UPDATED) || |
6719 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 6720 | tg3_disable_ints(tp); |
7938109f MC |
6721 | return IRQ_RETVAL(1); |
6722 | } | |
6723 | return IRQ_RETVAL(0); | |
6724 | } | |
6725 | ||
1da177e4 LT |
6726 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6727 | static void tg3_poll_controller(struct net_device *dev) | |
6728 | { | |
4f125f42 | 6729 | int i; |
88b06bc2 MC |
6730 | struct tg3 *tp = netdev_priv(dev); |
6731 | ||
4f125f42 | 6732 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 6733 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
6734 | } |
6735 | #endif | |
6736 | ||
1da177e4 LT |
6737 | static void tg3_tx_timeout(struct net_device *dev) |
6738 | { | |
6739 | struct tg3 *tp = netdev_priv(dev); | |
6740 | ||
b0408751 | 6741 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 6742 | netdev_err(dev, "transmit timed out, resetting\n"); |
97bd8e49 | 6743 | tg3_dump_state(tp); |
b0408751 | 6744 | } |
1da177e4 | 6745 | |
db219973 | 6746 | tg3_reset_task_schedule(tp); |
1da177e4 LT |
6747 | } |
6748 | ||
c58ec932 MC |
6749 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
6750 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
6751 | { | |
6752 | u32 base = (u32) mapping & 0xffffffff; | |
6753 | ||
807540ba | 6754 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
6755 | } |
6756 | ||
72f2afb8 MC |
6757 | /* Test for DMA addresses > 40-bit */ |
6758 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
6759 | int len) | |
6760 | { | |
6761 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
63c3a66f | 6762 | if (tg3_flag(tp, 40BIT_DMA_BUG)) |
807540ba | 6763 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
6764 | return 0; |
6765 | #else | |
6766 | return 0; | |
6767 | #endif | |
6768 | } | |
6769 | ||
d1a3b737 | 6770 | static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd, |
92cd3a17 MC |
6771 | dma_addr_t mapping, u32 len, u32 flags, |
6772 | u32 mss, u32 vlan) | |
2ffcc981 | 6773 | { |
92cd3a17 MC |
6774 | txbd->addr_hi = ((u64) mapping >> 32); |
6775 | txbd->addr_lo = ((u64) mapping & 0xffffffff); | |
6776 | txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); | |
6777 | txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); | |
2ffcc981 | 6778 | } |
1da177e4 | 6779 | |
84b67b27 | 6780 | static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget, |
d1a3b737 MC |
6781 | dma_addr_t map, u32 len, u32 flags, |
6782 | u32 mss, u32 vlan) | |
6783 | { | |
6784 | struct tg3 *tp = tnapi->tp; | |
6785 | bool hwbug = false; | |
6786 | ||
6787 | if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) | |
3db1cd5c | 6788 | hwbug = true; |
d1a3b737 MC |
6789 | |
6790 | if (tg3_4g_overflow_test(map, len)) | |
3db1cd5c | 6791 | hwbug = true; |
d1a3b737 MC |
6792 | |
6793 | if (tg3_40bit_overflow_test(tp, map, len)) | |
3db1cd5c | 6794 | hwbug = true; |
d1a3b737 | 6795 | |
a4cb428d | 6796 | if (tp->dma_limit) { |
b9e45482 | 6797 | u32 prvidx = *entry; |
e31aa987 | 6798 | u32 tmp_flag = flags & ~TXD_FLAG_END; |
a4cb428d MC |
6799 | while (len > tp->dma_limit && *budget) { |
6800 | u32 frag_len = tp->dma_limit; | |
6801 | len -= tp->dma_limit; | |
e31aa987 | 6802 | |
b9e45482 MC |
6803 | /* Avoid the 8byte DMA problem */ |
6804 | if (len <= 8) { | |
a4cb428d MC |
6805 | len += tp->dma_limit / 2; |
6806 | frag_len = tp->dma_limit / 2; | |
e31aa987 MC |
6807 | } |
6808 | ||
b9e45482 MC |
6809 | tnapi->tx_buffers[*entry].fragmented = true; |
6810 | ||
6811 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
6812 | frag_len, tmp_flag, mss, vlan); | |
6813 | *budget -= 1; | |
6814 | prvidx = *entry; | |
6815 | *entry = NEXT_TX(*entry); | |
6816 | ||
e31aa987 MC |
6817 | map += frag_len; |
6818 | } | |
6819 | ||
6820 | if (len) { | |
6821 | if (*budget) { | |
6822 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, | |
6823 | len, flags, mss, vlan); | |
b9e45482 | 6824 | *budget -= 1; |
e31aa987 MC |
6825 | *entry = NEXT_TX(*entry); |
6826 | } else { | |
3db1cd5c | 6827 | hwbug = true; |
b9e45482 | 6828 | tnapi->tx_buffers[prvidx].fragmented = false; |
e31aa987 MC |
6829 | } |
6830 | } | |
6831 | } else { | |
84b67b27 MC |
6832 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, |
6833 | len, flags, mss, vlan); | |
e31aa987 MC |
6834 | *entry = NEXT_TX(*entry); |
6835 | } | |
d1a3b737 MC |
6836 | |
6837 | return hwbug; | |
6838 | } | |
6839 | ||
0d681b27 | 6840 | static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last) |
432aa7ed MC |
6841 | { |
6842 | int i; | |
0d681b27 | 6843 | struct sk_buff *skb; |
df8944cf | 6844 | struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; |
432aa7ed | 6845 | |
0d681b27 MC |
6846 | skb = txb->skb; |
6847 | txb->skb = NULL; | |
6848 | ||
432aa7ed MC |
6849 | pci_unmap_single(tnapi->tp->pdev, |
6850 | dma_unmap_addr(txb, mapping), | |
6851 | skb_headlen(skb), | |
6852 | PCI_DMA_TODEVICE); | |
e01ee14d MC |
6853 | |
6854 | while (txb->fragmented) { | |
6855 | txb->fragmented = false; | |
6856 | entry = NEXT_TX(entry); | |
6857 | txb = &tnapi->tx_buffers[entry]; | |
6858 | } | |
6859 | ||
ba1142e4 | 6860 | for (i = 0; i <= last; i++) { |
9e903e08 | 6861 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
432aa7ed MC |
6862 | |
6863 | entry = NEXT_TX(entry); | |
6864 | txb = &tnapi->tx_buffers[entry]; | |
6865 | ||
6866 | pci_unmap_page(tnapi->tp->pdev, | |
6867 | dma_unmap_addr(txb, mapping), | |
9e903e08 | 6868 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
e01ee14d MC |
6869 | |
6870 | while (txb->fragmented) { | |
6871 | txb->fragmented = false; | |
6872 | entry = NEXT_TX(entry); | |
6873 | txb = &tnapi->tx_buffers[entry]; | |
6874 | } | |
432aa7ed MC |
6875 | } |
6876 | } | |
6877 | ||
72f2afb8 | 6878 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 | 6879 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
f7ff1987 | 6880 | struct sk_buff **pskb, |
84b67b27 | 6881 | u32 *entry, u32 *budget, |
92cd3a17 | 6882 | u32 base_flags, u32 mss, u32 vlan) |
1da177e4 | 6883 | { |
24f4efd4 | 6884 | struct tg3 *tp = tnapi->tp; |
f7ff1987 | 6885 | struct sk_buff *new_skb, *skb = *pskb; |
c58ec932 | 6886 | dma_addr_t new_addr = 0; |
432aa7ed | 6887 | int ret = 0; |
1da177e4 | 6888 | |
41588ba1 MC |
6889 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
6890 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
6891 | else { | |
6892 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
6893 | ||
6894 | new_skb = skb_copy_expand(skb, | |
6895 | skb_headroom(skb) + more_headroom, | |
6896 | skb_tailroom(skb), GFP_ATOMIC); | |
6897 | } | |
6898 | ||
1da177e4 | 6899 | if (!new_skb) { |
c58ec932 MC |
6900 | ret = -1; |
6901 | } else { | |
6902 | /* New SKB is guaranteed to be linear. */ | |
f4188d8a AD |
6903 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
6904 | PCI_DMA_TODEVICE); | |
6905 | /* Make sure the mapping succeeded */ | |
6906 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
f4188d8a | 6907 | dev_kfree_skb(new_skb); |
c58ec932 | 6908 | ret = -1; |
c58ec932 | 6909 | } else { |
b9e45482 MC |
6910 | u32 save_entry = *entry; |
6911 | ||
92cd3a17 MC |
6912 | base_flags |= TXD_FLAG_END; |
6913 | ||
84b67b27 MC |
6914 | tnapi->tx_buffers[*entry].skb = new_skb; |
6915 | dma_unmap_addr_set(&tnapi->tx_buffers[*entry], | |
432aa7ed MC |
6916 | mapping, new_addr); |
6917 | ||
84b67b27 | 6918 | if (tg3_tx_frag_set(tnapi, entry, budget, new_addr, |
d1a3b737 MC |
6919 | new_skb->len, base_flags, |
6920 | mss, vlan)) { | |
ba1142e4 | 6921 | tg3_tx_skb_unmap(tnapi, save_entry, -1); |
d1a3b737 MC |
6922 | dev_kfree_skb(new_skb); |
6923 | ret = -1; | |
6924 | } | |
f4188d8a | 6925 | } |
1da177e4 LT |
6926 | } |
6927 | ||
6928 | dev_kfree_skb(skb); | |
f7ff1987 | 6929 | *pskb = new_skb; |
c58ec932 | 6930 | return ret; |
1da177e4 LT |
6931 | } |
6932 | ||
2ffcc981 | 6933 | static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *); |
52c0fd83 MC |
6934 | |
6935 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
6936 | * TSO header is greater than 80 bytes. | |
6937 | */ | |
6938 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
6939 | { | |
6940 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 6941 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
6942 | |
6943 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 6944 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 6945 | netif_stop_queue(tp->dev); |
f65aac16 MC |
6946 | |
6947 | /* netif_tx_stop_queue() must be done before checking | |
6948 | * checking tx index in tg3_tx_avail() below, because in | |
6949 | * tg3_tx(), we update tx index before checking for | |
6950 | * netif_tx_queue_stopped(). | |
6951 | */ | |
6952 | smp_mb(); | |
f3f3f27e | 6953 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
6954 | return NETDEV_TX_BUSY; |
6955 | ||
6956 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
6957 | } |
6958 | ||
6959 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 6960 | if (IS_ERR(segs)) |
52c0fd83 MC |
6961 | goto tg3_tso_bug_end; |
6962 | ||
6963 | do { | |
6964 | nskb = segs; | |
6965 | segs = segs->next; | |
6966 | nskb->next = NULL; | |
2ffcc981 | 6967 | tg3_start_xmit(nskb, tp->dev); |
52c0fd83 MC |
6968 | } while (segs); |
6969 | ||
6970 | tg3_tso_bug_end: | |
6971 | dev_kfree_skb(skb); | |
6972 | ||
6973 | return NETDEV_TX_OK; | |
6974 | } | |
52c0fd83 | 6975 | |
5a6f3074 | 6976 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
63c3a66f | 6977 | * support TG3_FLAG_HW_TSO_1 or firmware TSO only. |
5a6f3074 | 6978 | */ |
2ffcc981 | 6979 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
6980 | { |
6981 | struct tg3 *tp = netdev_priv(dev); | |
92cd3a17 | 6982 | u32 len, entry, base_flags, mss, vlan = 0; |
84b67b27 | 6983 | u32 budget; |
432aa7ed | 6984 | int i = -1, would_hit_hwbug; |
90079ce8 | 6985 | dma_addr_t mapping; |
24f4efd4 MC |
6986 | struct tg3_napi *tnapi; |
6987 | struct netdev_queue *txq; | |
432aa7ed | 6988 | unsigned int last; |
f4188d8a | 6989 | |
24f4efd4 MC |
6990 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
6991 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
63c3a66f | 6992 | if (tg3_flag(tp, ENABLE_TSS)) |
24f4efd4 | 6993 | tnapi++; |
1da177e4 | 6994 | |
84b67b27 MC |
6995 | budget = tg3_tx_avail(tnapi); |
6996 | ||
00b70504 | 6997 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 6998 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
6999 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
7000 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 7001 | */ |
84b67b27 | 7002 | if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
7003 | if (!netif_tx_queue_stopped(txq)) { |
7004 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
7005 | |
7006 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
7007 | netdev_err(dev, |
7008 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 7009 | } |
1da177e4 LT |
7010 | return NETDEV_TX_BUSY; |
7011 | } | |
7012 | ||
f3f3f27e | 7013 | entry = tnapi->tx_prod; |
1da177e4 | 7014 | base_flags = 0; |
84fa7933 | 7015 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 7016 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 7017 | |
be98da6a MC |
7018 | mss = skb_shinfo(skb)->gso_size; |
7019 | if (mss) { | |
eddc9ec5 | 7020 | struct iphdr *iph; |
34195c3d | 7021 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
7022 | |
7023 | if (skb_header_cloned(skb) && | |
48855432 ED |
7024 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) |
7025 | goto drop; | |
1da177e4 | 7026 | |
34195c3d | 7027 | iph = ip_hdr(skb); |
ab6a5bb6 | 7028 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 7029 | |
a5a11955 | 7030 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN; |
34195c3d | 7031 | |
a5a11955 | 7032 | if (!skb_is_gso_v6(skb)) { |
34195c3d MC |
7033 | iph->check = 0; |
7034 | iph->tot_len = htons(mss + hdr_len); | |
7035 | } | |
7036 | ||
52c0fd83 | 7037 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
63c3a66f | 7038 | tg3_flag(tp, TSO_BUG)) |
de6f31eb | 7039 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 7040 | |
1da177e4 LT |
7041 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
7042 | TXD_FLAG_CPU_POST_DMA); | |
7043 | ||
63c3a66f JP |
7044 | if (tg3_flag(tp, HW_TSO_1) || |
7045 | tg3_flag(tp, HW_TSO_2) || | |
7046 | tg3_flag(tp, HW_TSO_3)) { | |
aa8223c7 | 7047 | tcp_hdr(skb)->check = 0; |
1da177e4 | 7048 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
7049 | } else |
7050 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
7051 | iph->daddr, 0, | |
7052 | IPPROTO_TCP, | |
7053 | 0); | |
1da177e4 | 7054 | |
63c3a66f | 7055 | if (tg3_flag(tp, HW_TSO_3)) { |
615774fe MC |
7056 | mss |= (hdr_len & 0xc) << 12; |
7057 | if (hdr_len & 0x10) | |
7058 | base_flags |= 0x00000010; | |
7059 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 7060 | } else if (tg3_flag(tp, HW_TSO_2)) |
92c6b8d1 | 7061 | mss |= hdr_len << 9; |
63c3a66f | 7062 | else if (tg3_flag(tp, HW_TSO_1) || |
92c6b8d1 | 7063 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
eddc9ec5 | 7064 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
7065 | int tsflags; |
7066 | ||
eddc9ec5 | 7067 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
7068 | mss |= (tsflags << 11); |
7069 | } | |
7070 | } else { | |
eddc9ec5 | 7071 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
7072 | int tsflags; |
7073 | ||
eddc9ec5 | 7074 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
7075 | base_flags |= tsflags << 12; |
7076 | } | |
7077 | } | |
7078 | } | |
bf933c80 | 7079 | |
93a700a9 MC |
7080 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && |
7081 | !mss && skb->len > VLAN_ETH_FRAME_LEN) | |
7082 | base_flags |= TXD_FLAG_JMB_PKT; | |
7083 | ||
92cd3a17 MC |
7084 | if (vlan_tx_tag_present(skb)) { |
7085 | base_flags |= TXD_FLAG_VLAN; | |
7086 | vlan = vlan_tx_tag_get(skb); | |
7087 | } | |
1da177e4 | 7088 | |
f4188d8a AD |
7089 | len = skb_headlen(skb); |
7090 | ||
7091 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
48855432 ED |
7092 | if (pci_dma_mapping_error(tp->pdev, mapping)) |
7093 | goto drop; | |
7094 | ||
90079ce8 | 7095 | |
f3f3f27e | 7096 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 7097 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
7098 | |
7099 | would_hit_hwbug = 0; | |
7100 | ||
63c3a66f | 7101 | if (tg3_flag(tp, 5701_DMA_BUG)) |
c58ec932 | 7102 | would_hit_hwbug = 1; |
1da177e4 | 7103 | |
84b67b27 | 7104 | if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags | |
d1a3b737 | 7105 | ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), |
ba1142e4 | 7106 | mss, vlan)) { |
d1a3b737 | 7107 | would_hit_hwbug = 1; |
ba1142e4 | 7108 | } else if (skb_shinfo(skb)->nr_frags > 0) { |
92cd3a17 MC |
7109 | u32 tmp_mss = mss; |
7110 | ||
7111 | if (!tg3_flag(tp, HW_TSO_1) && | |
7112 | !tg3_flag(tp, HW_TSO_2) && | |
7113 | !tg3_flag(tp, HW_TSO_3)) | |
7114 | tmp_mss = 0; | |
7115 | ||
c5665a53 MC |
7116 | /* Now loop through additional data |
7117 | * fragments, and queue them. | |
7118 | */ | |
1da177e4 LT |
7119 | last = skb_shinfo(skb)->nr_frags - 1; |
7120 | for (i = 0; i <= last; i++) { | |
7121 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
7122 | ||
9e903e08 | 7123 | len = skb_frag_size(frag); |
dc234d0b | 7124 | mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, |
5d6bcdfe | 7125 | len, DMA_TO_DEVICE); |
1da177e4 | 7126 | |
f3f3f27e | 7127 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 7128 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a | 7129 | mapping); |
5d6bcdfe | 7130 | if (dma_mapping_error(&tp->pdev->dev, mapping)) |
f4188d8a | 7131 | goto dma_error; |
1da177e4 | 7132 | |
b9e45482 MC |
7133 | if (!budget || |
7134 | tg3_tx_frag_set(tnapi, &entry, &budget, mapping, | |
84b67b27 MC |
7135 | len, base_flags | |
7136 | ((i == last) ? TXD_FLAG_END : 0), | |
b9e45482 | 7137 | tmp_mss, vlan)) { |
72f2afb8 | 7138 | would_hit_hwbug = 1; |
b9e45482 MC |
7139 | break; |
7140 | } | |
1da177e4 LT |
7141 | } |
7142 | } | |
7143 | ||
7144 | if (would_hit_hwbug) { | |
0d681b27 | 7145 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); |
1da177e4 LT |
7146 | |
7147 | /* If the workaround fails due to memory/mapping | |
7148 | * failure, silently drop this packet. | |
7149 | */ | |
84b67b27 MC |
7150 | entry = tnapi->tx_prod; |
7151 | budget = tg3_tx_avail(tnapi); | |
f7ff1987 | 7152 | if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget, |
84b67b27 | 7153 | base_flags, mss, vlan)) |
48855432 | 7154 | goto drop_nofree; |
1da177e4 LT |
7155 | } |
7156 | ||
d515b450 | 7157 | skb_tx_timestamp(skb); |
5cb917bc | 7158 | netdev_tx_sent_queue(txq, skb->len); |
d515b450 | 7159 | |
6541b806 MC |
7160 | /* Sync BD data before updating mailbox */ |
7161 | wmb(); | |
7162 | ||
1da177e4 | 7163 | /* Packets are ready, update Tx producer idx local and on card. */ |
24f4efd4 | 7164 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 7165 | |
f3f3f27e MC |
7166 | tnapi->tx_prod = entry; |
7167 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 7168 | netif_tx_stop_queue(txq); |
f65aac16 MC |
7169 | |
7170 | /* netif_tx_stop_queue() must be done before checking | |
7171 | * checking tx index in tg3_tx_avail() below, because in | |
7172 | * tg3_tx(), we update tx index before checking for | |
7173 | * netif_tx_queue_stopped(). | |
7174 | */ | |
7175 | smp_mb(); | |
f3f3f27e | 7176 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 7177 | netif_tx_wake_queue(txq); |
51b91468 | 7178 | } |
1da177e4 | 7179 | |
cdd0db05 | 7180 | mmiowb(); |
1da177e4 | 7181 | return NETDEV_TX_OK; |
f4188d8a AD |
7182 | |
7183 | dma_error: | |
ba1142e4 | 7184 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); |
432aa7ed | 7185 | tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; |
48855432 ED |
7186 | drop: |
7187 | dev_kfree_skb(skb); | |
7188 | drop_nofree: | |
7189 | tp->tx_dropped++; | |
f4188d8a | 7190 | return NETDEV_TX_OK; |
1da177e4 LT |
7191 | } |
7192 | ||
6e01b20b MC |
7193 | static void tg3_mac_loopback(struct tg3 *tp, bool enable) |
7194 | { | |
7195 | if (enable) { | |
7196 | tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | | |
7197 | MAC_MODE_PORT_MODE_MASK); | |
7198 | ||
7199 | tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
7200 | ||
7201 | if (!tg3_flag(tp, 5705_PLUS)) | |
7202 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
7203 | ||
7204 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
7205 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
7206 | else | |
7207 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
7208 | } else { | |
7209 | tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; | |
7210 | ||
7211 | if (tg3_flag(tp, 5705_PLUS) || | |
7212 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || | |
7213 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
7214 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
7215 | } | |
7216 | ||
7217 | tw32(MAC_MODE, tp->mac_mode); | |
7218 | udelay(40); | |
7219 | } | |
7220 | ||
941ec90f | 7221 | static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) |
5e5a7f37 | 7222 | { |
941ec90f | 7223 | u32 val, bmcr, mac_mode, ptest = 0; |
5e5a7f37 MC |
7224 | |
7225 | tg3_phy_toggle_apd(tp, false); | |
7226 | tg3_phy_toggle_automdix(tp, 0); | |
7227 | ||
941ec90f MC |
7228 | if (extlpbk && tg3_phy_set_extloopbk(tp)) |
7229 | return -EIO; | |
7230 | ||
7231 | bmcr = BMCR_FULLDPLX; | |
5e5a7f37 MC |
7232 | switch (speed) { |
7233 | case SPEED_10: | |
7234 | break; | |
7235 | case SPEED_100: | |
7236 | bmcr |= BMCR_SPEED100; | |
7237 | break; | |
7238 | case SPEED_1000: | |
7239 | default: | |
7240 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
7241 | speed = SPEED_100; | |
7242 | bmcr |= BMCR_SPEED100; | |
7243 | } else { | |
7244 | speed = SPEED_1000; | |
7245 | bmcr |= BMCR_SPEED1000; | |
7246 | } | |
7247 | } | |
7248 | ||
941ec90f MC |
7249 | if (extlpbk) { |
7250 | if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
7251 | tg3_readphy(tp, MII_CTRL1000, &val); | |
7252 | val |= CTL1000_AS_MASTER | | |
7253 | CTL1000_ENABLE_MASTER; | |
7254 | tg3_writephy(tp, MII_CTRL1000, val); | |
7255 | } else { | |
7256 | ptest = MII_TG3_FET_PTEST_TRIM_SEL | | |
7257 | MII_TG3_FET_PTEST_TRIM_2; | |
7258 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); | |
7259 | } | |
7260 | } else | |
7261 | bmcr |= BMCR_LOOPBACK; | |
7262 | ||
5e5a7f37 MC |
7263 | tg3_writephy(tp, MII_BMCR, bmcr); |
7264 | ||
7265 | /* The write needs to be flushed for the FETs */ | |
7266 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
7267 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
7268 | ||
7269 | udelay(40); | |
7270 | ||
7271 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && | |
7272 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
941ec90f | 7273 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | |
5e5a7f37 MC |
7274 | MII_TG3_FET_PTEST_FRC_TX_LINK | |
7275 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
7276 | ||
7277 | /* The write needs to be flushed for the AC131 */ | |
7278 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
7279 | } | |
7280 | ||
7281 | /* Reset to prevent losing 1st rx packet intermittently */ | |
7282 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && | |
7283 | tg3_flag(tp, 5780_CLASS)) { | |
7284 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
7285 | udelay(10); | |
7286 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7287 | } | |
7288 | ||
7289 | mac_mode = tp->mac_mode & | |
7290 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
7291 | if (speed == SPEED_1000) | |
7292 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
7293 | else | |
7294 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
7295 | ||
7296 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
7297 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; | |
7298 | ||
7299 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
7300 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
7301 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) | |
7302 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
7303 | ||
7304 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
7305 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
7306 | } | |
7307 | ||
7308 | tw32(MAC_MODE, mac_mode); | |
7309 | udelay(40); | |
941ec90f MC |
7310 | |
7311 | return 0; | |
5e5a7f37 MC |
7312 | } |
7313 | ||
c8f44aff | 7314 | static void tg3_set_loopback(struct net_device *dev, netdev_features_t features) |
06c03c02 MB |
7315 | { |
7316 | struct tg3 *tp = netdev_priv(dev); | |
7317 | ||
7318 | if (features & NETIF_F_LOOPBACK) { | |
7319 | if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) | |
7320 | return; | |
7321 | ||
06c03c02 | 7322 | spin_lock_bh(&tp->lock); |
6e01b20b | 7323 | tg3_mac_loopback(tp, true); |
06c03c02 MB |
7324 | netif_carrier_on(tp->dev); |
7325 | spin_unlock_bh(&tp->lock); | |
7326 | netdev_info(dev, "Internal MAC loopback mode enabled.\n"); | |
7327 | } else { | |
7328 | if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
7329 | return; | |
7330 | ||
06c03c02 | 7331 | spin_lock_bh(&tp->lock); |
6e01b20b | 7332 | tg3_mac_loopback(tp, false); |
06c03c02 MB |
7333 | /* Force link status check */ |
7334 | tg3_setup_phy(tp, 1); | |
7335 | spin_unlock_bh(&tp->lock); | |
7336 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | |
7337 | } | |
7338 | } | |
7339 | ||
c8f44aff MM |
7340 | static netdev_features_t tg3_fix_features(struct net_device *dev, |
7341 | netdev_features_t features) | |
dc668910 MM |
7342 | { |
7343 | struct tg3 *tp = netdev_priv(dev); | |
7344 | ||
63c3a66f | 7345 | if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) |
dc668910 MM |
7346 | features &= ~NETIF_F_ALL_TSO; |
7347 | ||
7348 | return features; | |
7349 | } | |
7350 | ||
c8f44aff | 7351 | static int tg3_set_features(struct net_device *dev, netdev_features_t features) |
06c03c02 | 7352 | { |
c8f44aff | 7353 | netdev_features_t changed = dev->features ^ features; |
06c03c02 MB |
7354 | |
7355 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) | |
7356 | tg3_set_loopback(dev, features); | |
7357 | ||
7358 | return 0; | |
7359 | } | |
7360 | ||
21f581a5 MC |
7361 | static void tg3_rx_prodring_free(struct tg3 *tp, |
7362 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7363 | { |
1da177e4 LT |
7364 | int i; |
7365 | ||
8fea32b9 | 7366 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 7367 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 7368 | i = (i + 1) & tp->rx_std_ring_mask) |
9205fd9c | 7369 | tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], |
b196c7e4 MC |
7370 | tp->rx_pkt_map_sz); |
7371 | ||
63c3a66f | 7372 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
b196c7e4 MC |
7373 | for (i = tpr->rx_jmb_cons_idx; |
7374 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 7375 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
9205fd9c | 7376 | tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], |
b196c7e4 MC |
7377 | TG3_RX_JMB_MAP_SZ); |
7378 | } | |
7379 | } | |
7380 | ||
2b2cdb65 | 7381 | return; |
b196c7e4 | 7382 | } |
1da177e4 | 7383 | |
2c49a44d | 7384 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
9205fd9c | 7385 | tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], |
2b2cdb65 | 7386 | tp->rx_pkt_map_sz); |
1da177e4 | 7387 | |
63c3a66f | 7388 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 7389 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
9205fd9c | 7390 | tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], |
2b2cdb65 | 7391 | TG3_RX_JMB_MAP_SZ); |
1da177e4 LT |
7392 | } |
7393 | } | |
7394 | ||
c6cdf436 | 7395 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
7396 | * |
7397 | * The chip has been shut down and the driver detached from | |
7398 | * the networking, so no interrupts or new tx packets will | |
7399 | * end up in the driver. tp->{tx,}lock are held and thus | |
7400 | * we may not sleep. | |
7401 | */ | |
21f581a5 MC |
7402 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
7403 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7404 | { |
287be12e | 7405 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 7406 | |
b196c7e4 MC |
7407 | tpr->rx_std_cons_idx = 0; |
7408 | tpr->rx_std_prod_idx = 0; | |
7409 | tpr->rx_jmb_cons_idx = 0; | |
7410 | tpr->rx_jmb_prod_idx = 0; | |
7411 | ||
8fea32b9 | 7412 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
7413 | memset(&tpr->rx_std_buffers[0], 0, |
7414 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 7415 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 7416 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 7417 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
7418 | goto done; |
7419 | } | |
7420 | ||
1da177e4 | 7421 | /* Zero out all descriptors. */ |
2c49a44d | 7422 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 7423 | |
287be12e | 7424 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
63c3a66f | 7425 | if (tg3_flag(tp, 5780_CLASS) && |
287be12e MC |
7426 | tp->dev->mtu > ETH_DATA_LEN) |
7427 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
7428 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 7429 | |
1da177e4 LT |
7430 | /* Initialize invariants of the rings, we only set this |
7431 | * stuff once. This works because the card does not | |
7432 | * write into the rx buffer posting rings. | |
7433 | */ | |
2c49a44d | 7434 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
7435 | struct tg3_rx_buffer_desc *rxd; |
7436 | ||
21f581a5 | 7437 | rxd = &tpr->rx_std[i]; |
287be12e | 7438 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
7439 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
7440 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
7441 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
7442 | } | |
7443 | ||
1da177e4 LT |
7444 | /* Now allocate fresh SKBs for each rx ring. */ |
7445 | for (i = 0; i < tp->rx_pending; i++) { | |
8d4057a9 ED |
7446 | unsigned int frag_size; |
7447 | ||
7448 | if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i, | |
7449 | &frag_size) < 0) { | |
5129c3a3 MC |
7450 | netdev_warn(tp->dev, |
7451 | "Using a smaller RX standard ring. Only " | |
7452 | "%d out of %d buffers were allocated " | |
7453 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 7454 | if (i == 0) |
cf7a7298 | 7455 | goto initfail; |
32d8c572 | 7456 | tp->rx_pending = i; |
1da177e4 | 7457 | break; |
32d8c572 | 7458 | } |
1da177e4 LT |
7459 | } |
7460 | ||
63c3a66f | 7461 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
cf7a7298 MC |
7462 | goto done; |
7463 | ||
2c49a44d | 7464 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 7465 | |
63c3a66f | 7466 | if (!tg3_flag(tp, JUMBO_RING_ENABLE)) |
0d86df80 | 7467 | goto done; |
cf7a7298 | 7468 | |
2c49a44d | 7469 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
7470 | struct tg3_rx_buffer_desc *rxd; |
7471 | ||
7472 | rxd = &tpr->rx_jmb[i].std; | |
7473 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
7474 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
7475 | RXD_FLAG_JUMBO; | |
7476 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
7477 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
7478 | } | |
7479 | ||
7480 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
8d4057a9 ED |
7481 | unsigned int frag_size; |
7482 | ||
7483 | if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i, | |
7484 | &frag_size) < 0) { | |
5129c3a3 MC |
7485 | netdev_warn(tp->dev, |
7486 | "Using a smaller RX jumbo ring. Only %d " | |
7487 | "out of %d buffers were allocated " | |
7488 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
7489 | if (i == 0) |
7490 | goto initfail; | |
7491 | tp->rx_jumbo_pending = i; | |
7492 | break; | |
1da177e4 LT |
7493 | } |
7494 | } | |
cf7a7298 MC |
7495 | |
7496 | done: | |
32d8c572 | 7497 | return 0; |
cf7a7298 MC |
7498 | |
7499 | initfail: | |
21f581a5 | 7500 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 7501 | return -ENOMEM; |
1da177e4 LT |
7502 | } |
7503 | ||
21f581a5 MC |
7504 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
7505 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 7506 | { |
21f581a5 MC |
7507 | kfree(tpr->rx_std_buffers); |
7508 | tpr->rx_std_buffers = NULL; | |
7509 | kfree(tpr->rx_jmb_buffers); | |
7510 | tpr->rx_jmb_buffers = NULL; | |
7511 | if (tpr->rx_std) { | |
4bae65c8 MC |
7512 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
7513 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 7514 | tpr->rx_std = NULL; |
1da177e4 | 7515 | } |
21f581a5 | 7516 | if (tpr->rx_jmb) { |
4bae65c8 MC |
7517 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
7518 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 7519 | tpr->rx_jmb = NULL; |
1da177e4 | 7520 | } |
cf7a7298 MC |
7521 | } |
7522 | ||
21f581a5 MC |
7523 | static int tg3_rx_prodring_init(struct tg3 *tp, |
7524 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 7525 | { |
2c49a44d MC |
7526 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
7527 | GFP_KERNEL); | |
21f581a5 | 7528 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
7529 | return -ENOMEM; |
7530 | ||
4bae65c8 MC |
7531 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
7532 | TG3_RX_STD_RING_BYTES(tp), | |
7533 | &tpr->rx_std_mapping, | |
7534 | GFP_KERNEL); | |
21f581a5 | 7535 | if (!tpr->rx_std) |
cf7a7298 MC |
7536 | goto err_out; |
7537 | ||
63c3a66f | 7538 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
2c49a44d | 7539 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
7540 | GFP_KERNEL); |
7541 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
7542 | goto err_out; |
7543 | ||
4bae65c8 MC |
7544 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
7545 | TG3_RX_JMB_RING_BYTES(tp), | |
7546 | &tpr->rx_jmb_mapping, | |
7547 | GFP_KERNEL); | |
21f581a5 | 7548 | if (!tpr->rx_jmb) |
cf7a7298 MC |
7549 | goto err_out; |
7550 | } | |
7551 | ||
7552 | return 0; | |
7553 | ||
7554 | err_out: | |
21f581a5 | 7555 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
7556 | return -ENOMEM; |
7557 | } | |
7558 | ||
7559 | /* Free up pending packets in all rx/tx rings. | |
7560 | * | |
7561 | * The chip has been shut down and the driver detached from | |
7562 | * the networking, so no interrupts or new tx packets will | |
7563 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
7564 | * in an interrupt context and thus may sleep. | |
7565 | */ | |
7566 | static void tg3_free_rings(struct tg3 *tp) | |
7567 | { | |
f77a6a8e | 7568 | int i, j; |
cf7a7298 | 7569 | |
f77a6a8e MC |
7570 | for (j = 0; j < tp->irq_cnt; j++) { |
7571 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 7572 | |
8fea32b9 | 7573 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 7574 | |
0c1d0e2b MC |
7575 | if (!tnapi->tx_buffers) |
7576 | continue; | |
7577 | ||
0d681b27 MC |
7578 | for (i = 0; i < TG3_TX_RING_SIZE; i++) { |
7579 | struct sk_buff *skb = tnapi->tx_buffers[i].skb; | |
cf7a7298 | 7580 | |
0d681b27 | 7581 | if (!skb) |
f77a6a8e | 7582 | continue; |
cf7a7298 | 7583 | |
ba1142e4 MC |
7584 | tg3_tx_skb_unmap(tnapi, i, |
7585 | skb_shinfo(skb)->nr_frags - 1); | |
f77a6a8e MC |
7586 | |
7587 | dev_kfree_skb_any(skb); | |
7588 | } | |
5cb917bc | 7589 | netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); |
2b2cdb65 | 7590 | } |
cf7a7298 MC |
7591 | } |
7592 | ||
7593 | /* Initialize tx/rx rings for packet processing. | |
7594 | * | |
7595 | * The chip has been shut down and the driver detached from | |
7596 | * the networking, so no interrupts or new tx packets will | |
7597 | * end up in the driver. tp->{tx,}lock are held and thus | |
7598 | * we may not sleep. | |
7599 | */ | |
7600 | static int tg3_init_rings(struct tg3 *tp) | |
7601 | { | |
f77a6a8e | 7602 | int i; |
72334482 | 7603 | |
cf7a7298 MC |
7604 | /* Free up all the SKBs. */ |
7605 | tg3_free_rings(tp); | |
7606 | ||
f77a6a8e MC |
7607 | for (i = 0; i < tp->irq_cnt; i++) { |
7608 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7609 | ||
7610 | tnapi->last_tag = 0; | |
7611 | tnapi->last_irq_tag = 0; | |
7612 | tnapi->hw_status->status = 0; | |
7613 | tnapi->hw_status->status_tag = 0; | |
7614 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 7615 | |
f77a6a8e MC |
7616 | tnapi->tx_prod = 0; |
7617 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
7618 | if (tnapi->tx_ring) |
7619 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
7620 | |
7621 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
7622 | if (tnapi->rx_rcb) |
7623 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 7624 | |
8fea32b9 | 7625 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 7626 | tg3_free_rings(tp); |
2b2cdb65 | 7627 | return -ENOMEM; |
e4af1af9 | 7628 | } |
f77a6a8e | 7629 | } |
72334482 | 7630 | |
2b2cdb65 | 7631 | return 0; |
cf7a7298 MC |
7632 | } |
7633 | ||
49a359e3 | 7634 | static void tg3_mem_tx_release(struct tg3 *tp) |
cf7a7298 | 7635 | { |
f77a6a8e | 7636 | int i; |
898a56f8 | 7637 | |
49a359e3 | 7638 | for (i = 0; i < tp->irq_max; i++) { |
f77a6a8e MC |
7639 | struct tg3_napi *tnapi = &tp->napi[i]; |
7640 | ||
7641 | if (tnapi->tx_ring) { | |
4bae65c8 | 7642 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
7643 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
7644 | tnapi->tx_ring = NULL; | |
7645 | } | |
7646 | ||
7647 | kfree(tnapi->tx_buffers); | |
7648 | tnapi->tx_buffers = NULL; | |
49a359e3 MC |
7649 | } |
7650 | } | |
f77a6a8e | 7651 | |
49a359e3 MC |
7652 | static int tg3_mem_tx_acquire(struct tg3 *tp) |
7653 | { | |
7654 | int i; | |
7655 | struct tg3_napi *tnapi = &tp->napi[0]; | |
7656 | ||
7657 | /* If multivector TSS is enabled, vector 0 does not handle | |
7658 | * tx interrupts. Don't allocate any resources for it. | |
7659 | */ | |
7660 | if (tg3_flag(tp, ENABLE_TSS)) | |
7661 | tnapi++; | |
7662 | ||
7663 | for (i = 0; i < tp->txq_cnt; i++, tnapi++) { | |
7664 | tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) * | |
7665 | TG3_TX_RING_SIZE, GFP_KERNEL); | |
7666 | if (!tnapi->tx_buffers) | |
7667 | goto err_out; | |
7668 | ||
7669 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, | |
7670 | TG3_TX_RING_BYTES, | |
7671 | &tnapi->tx_desc_mapping, | |
7672 | GFP_KERNEL); | |
7673 | if (!tnapi->tx_ring) | |
7674 | goto err_out; | |
7675 | } | |
7676 | ||
7677 | return 0; | |
7678 | ||
7679 | err_out: | |
7680 | tg3_mem_tx_release(tp); | |
7681 | return -ENOMEM; | |
7682 | } | |
7683 | ||
7684 | static void tg3_mem_rx_release(struct tg3 *tp) | |
7685 | { | |
7686 | int i; | |
7687 | ||
7688 | for (i = 0; i < tp->irq_max; i++) { | |
7689 | struct tg3_napi *tnapi = &tp->napi[i]; | |
f77a6a8e | 7690 | |
8fea32b9 MC |
7691 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
7692 | ||
49a359e3 MC |
7693 | if (!tnapi->rx_rcb) |
7694 | continue; | |
7695 | ||
7696 | dma_free_coherent(&tp->pdev->dev, | |
7697 | TG3_RX_RCB_RING_BYTES(tp), | |
7698 | tnapi->rx_rcb, | |
7699 | tnapi->rx_rcb_mapping); | |
7700 | tnapi->rx_rcb = NULL; | |
7701 | } | |
7702 | } | |
7703 | ||
7704 | static int tg3_mem_rx_acquire(struct tg3 *tp) | |
7705 | { | |
7706 | unsigned int i, limit; | |
7707 | ||
7708 | limit = tp->rxq_cnt; | |
7709 | ||
7710 | /* If RSS is enabled, we need a (dummy) producer ring | |
7711 | * set on vector zero. This is the true hw prodring. | |
7712 | */ | |
7713 | if (tg3_flag(tp, ENABLE_RSS)) | |
7714 | limit++; | |
7715 | ||
7716 | for (i = 0; i < limit; i++) { | |
7717 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7718 | ||
7719 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) | |
7720 | goto err_out; | |
7721 | ||
7722 | /* If multivector RSS is enabled, vector 0 | |
7723 | * does not handle rx or tx interrupts. | |
7724 | * Don't allocate any resources for it. | |
7725 | */ | |
7726 | if (!i && tg3_flag(tp, ENABLE_RSS)) | |
7727 | continue; | |
7728 | ||
7729 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, | |
7730 | TG3_RX_RCB_RING_BYTES(tp), | |
7731 | &tnapi->rx_rcb_mapping, | |
7732 | GFP_KERNEL); | |
7733 | if (!tnapi->rx_rcb) | |
7734 | goto err_out; | |
7735 | ||
7736 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
7737 | } | |
7738 | ||
7739 | return 0; | |
7740 | ||
7741 | err_out: | |
7742 | tg3_mem_rx_release(tp); | |
7743 | return -ENOMEM; | |
7744 | } | |
7745 | ||
7746 | /* | |
7747 | * Must not be invoked with interrupt sources disabled and | |
7748 | * the hardware shutdown down. | |
7749 | */ | |
7750 | static void tg3_free_consistent(struct tg3 *tp) | |
7751 | { | |
7752 | int i; | |
7753 | ||
7754 | for (i = 0; i < tp->irq_cnt; i++) { | |
7755 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7756 | ||
f77a6a8e | 7757 | if (tnapi->hw_status) { |
4bae65c8 MC |
7758 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
7759 | tnapi->hw_status, | |
7760 | tnapi->status_mapping); | |
f77a6a8e MC |
7761 | tnapi->hw_status = NULL; |
7762 | } | |
1da177e4 | 7763 | } |
f77a6a8e | 7764 | |
49a359e3 MC |
7765 | tg3_mem_rx_release(tp); |
7766 | tg3_mem_tx_release(tp); | |
7767 | ||
1da177e4 | 7768 | if (tp->hw_stats) { |
4bae65c8 MC |
7769 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
7770 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
7771 | tp->hw_stats = NULL; |
7772 | } | |
7773 | } | |
7774 | ||
7775 | /* | |
7776 | * Must not be invoked with interrupt sources disabled and | |
7777 | * the hardware shutdown down. Can sleep. | |
7778 | */ | |
7779 | static int tg3_alloc_consistent(struct tg3 *tp) | |
7780 | { | |
f77a6a8e | 7781 | int i; |
898a56f8 | 7782 | |
4bae65c8 MC |
7783 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
7784 | sizeof(struct tg3_hw_stats), | |
7785 | &tp->stats_mapping, | |
7786 | GFP_KERNEL); | |
f77a6a8e | 7787 | if (!tp->hw_stats) |
1da177e4 LT |
7788 | goto err_out; |
7789 | ||
f77a6a8e | 7790 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 7791 | |
f77a6a8e MC |
7792 | for (i = 0; i < tp->irq_cnt; i++) { |
7793 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 7794 | struct tg3_hw_status *sblk; |
1da177e4 | 7795 | |
4bae65c8 MC |
7796 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
7797 | TG3_HW_STATUS_SIZE, | |
7798 | &tnapi->status_mapping, | |
7799 | GFP_KERNEL); | |
f77a6a8e MC |
7800 | if (!tnapi->hw_status) |
7801 | goto err_out; | |
898a56f8 | 7802 | |
f77a6a8e | 7803 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
7804 | sblk = tnapi->hw_status; |
7805 | ||
49a359e3 | 7806 | if (tg3_flag(tp, ENABLE_RSS)) { |
86449944 | 7807 | u16 *prodptr = NULL; |
8fea32b9 | 7808 | |
49a359e3 MC |
7809 | /* |
7810 | * When RSS is enabled, the status block format changes | |
7811 | * slightly. The "rx_jumbo_consumer", "reserved", | |
7812 | * and "rx_mini_consumer" members get mapped to the | |
7813 | * other three rx return ring producer indexes. | |
7814 | */ | |
7815 | switch (i) { | |
7816 | case 1: | |
7817 | prodptr = &sblk->idx[0].rx_producer; | |
7818 | break; | |
7819 | case 2: | |
7820 | prodptr = &sblk->rx_jumbo_consumer; | |
7821 | break; | |
7822 | case 3: | |
7823 | prodptr = &sblk->reserved; | |
7824 | break; | |
7825 | case 4: | |
7826 | prodptr = &sblk->rx_mini_consumer; | |
f891ea16 MC |
7827 | break; |
7828 | } | |
49a359e3 MC |
7829 | tnapi->rx_rcb_prod_idx = prodptr; |
7830 | } else { | |
8d9d7cfc | 7831 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; |
8d9d7cfc | 7832 | } |
f77a6a8e | 7833 | } |
1da177e4 | 7834 | |
49a359e3 MC |
7835 | if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp)) |
7836 | goto err_out; | |
7837 | ||
1da177e4 LT |
7838 | return 0; |
7839 | ||
7840 | err_out: | |
7841 | tg3_free_consistent(tp); | |
7842 | return -ENOMEM; | |
7843 | } | |
7844 | ||
7845 | #define MAX_WAIT_CNT 1000 | |
7846 | ||
7847 | /* To stop a block, clear the enable bit and poll till it | |
7848 | * clears. tp->lock is held. | |
7849 | */ | |
b3b7d6be | 7850 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
7851 | { |
7852 | unsigned int i; | |
7853 | u32 val; | |
7854 | ||
63c3a66f | 7855 | if (tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
7856 | switch (ofs) { |
7857 | case RCVLSC_MODE: | |
7858 | case DMAC_MODE: | |
7859 | case MBFREE_MODE: | |
7860 | case BUFMGR_MODE: | |
7861 | case MEMARB_MODE: | |
7862 | /* We can't enable/disable these bits of the | |
7863 | * 5705/5750, just say success. | |
7864 | */ | |
7865 | return 0; | |
7866 | ||
7867 | default: | |
7868 | break; | |
855e1111 | 7869 | } |
1da177e4 LT |
7870 | } |
7871 | ||
7872 | val = tr32(ofs); | |
7873 | val &= ~enable_bit; | |
7874 | tw32_f(ofs, val); | |
7875 | ||
7876 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
7877 | udelay(100); | |
7878 | val = tr32(ofs); | |
7879 | if ((val & enable_bit) == 0) | |
7880 | break; | |
7881 | } | |
7882 | ||
b3b7d6be | 7883 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
7884 | dev_err(&tp->pdev->dev, |
7885 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
7886 | ofs, enable_bit); | |
1da177e4 LT |
7887 | return -ENODEV; |
7888 | } | |
7889 | ||
7890 | return 0; | |
7891 | } | |
7892 | ||
7893 | /* tp->lock is held. */ | |
b3b7d6be | 7894 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
7895 | { |
7896 | int i, err; | |
7897 | ||
7898 | tg3_disable_ints(tp); | |
7899 | ||
7900 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
7901 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7902 | udelay(10); | |
7903 | ||
b3b7d6be DM |
7904 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
7905 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
7906 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
7907 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
7908 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
7909 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
7910 | ||
7911 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
7912 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
7913 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
7914 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
7915 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
7916 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
7917 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
7918 | |
7919 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
7920 | tw32_f(MAC_MODE, tp->mac_mode); | |
7921 | udelay(40); | |
7922 | ||
7923 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
7924 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
7925 | ||
7926 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
7927 | udelay(100); | |
7928 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
7929 | break; | |
7930 | } | |
7931 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
7932 | dev_err(&tp->pdev->dev, |
7933 | "%s timed out, TX_MODE_ENABLE will not clear " | |
7934 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 7935 | err |= -ENODEV; |
1da177e4 LT |
7936 | } |
7937 | ||
e6de8ad1 | 7938 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
7939 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
7940 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
7941 | |
7942 | tw32(FTQ_RESET, 0xffffffff); | |
7943 | tw32(FTQ_RESET, 0x00000000); | |
7944 | ||
b3b7d6be DM |
7945 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
7946 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 7947 | |
f77a6a8e MC |
7948 | for (i = 0; i < tp->irq_cnt; i++) { |
7949 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7950 | if (tnapi->hw_status) | |
7951 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7952 | } | |
1da177e4 | 7953 | |
1da177e4 LT |
7954 | return err; |
7955 | } | |
7956 | ||
ee6a99b5 MC |
7957 | /* Save PCI command register before chip reset */ |
7958 | static void tg3_save_pci_state(struct tg3 *tp) | |
7959 | { | |
8a6eac90 | 7960 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
7961 | } |
7962 | ||
7963 | /* Restore PCI state after chip reset */ | |
7964 | static void tg3_restore_pci_state(struct tg3 *tp) | |
7965 | { | |
7966 | u32 val; | |
7967 | ||
7968 | /* Re-enable indirect register accesses. */ | |
7969 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
7970 | tp->misc_host_ctrl); | |
7971 | ||
7972 | /* Set MAX PCI retry to zero. */ | |
7973 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
7974 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 7975 | tg3_flag(tp, PCIX_MODE)) |
ee6a99b5 | 7976 | val |= PCISTATE_RETRY_SAME_DMA; |
0d3031d9 | 7977 | /* Allow reads and writes to the APE register and memory space. */ |
63c3a66f | 7978 | if (tg3_flag(tp, ENABLE_APE)) |
0d3031d9 | 7979 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
f92d9dc1 MC |
7980 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7981 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
7982 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
7983 | ||
8a6eac90 | 7984 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 7985 | |
2c55a3d0 MC |
7986 | if (!tg3_flag(tp, PCI_EXPRESS)) { |
7987 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
7988 | tp->pci_cacheline_sz); | |
7989 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
7990 | tp->pci_lat_timer); | |
114342f2 | 7991 | } |
5f5c51e3 | 7992 | |
ee6a99b5 | 7993 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
63c3a66f | 7994 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
7995 | u16 pcix_cmd; |
7996 | ||
7997 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7998 | &pcix_cmd); | |
7999 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
8000 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8001 | pcix_cmd); | |
8002 | } | |
ee6a99b5 | 8003 | |
63c3a66f | 8004 | if (tg3_flag(tp, 5780_CLASS)) { |
ee6a99b5 MC |
8005 | |
8006 | /* Chip reset on 5780 will reset MSI enable bit, | |
8007 | * so need to restore it. | |
8008 | */ | |
63c3a66f | 8009 | if (tg3_flag(tp, USING_MSI)) { |
ee6a99b5 MC |
8010 | u16 ctrl; |
8011 | ||
8012 | pci_read_config_word(tp->pdev, | |
8013 | tp->msi_cap + PCI_MSI_FLAGS, | |
8014 | &ctrl); | |
8015 | pci_write_config_word(tp->pdev, | |
8016 | tp->msi_cap + PCI_MSI_FLAGS, | |
8017 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
8018 | val = tr32(MSGINT_MODE); | |
8019 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
8020 | } | |
8021 | } | |
8022 | } | |
8023 | ||
1da177e4 LT |
8024 | /* tp->lock is held. */ |
8025 | static int tg3_chip_reset(struct tg3 *tp) | |
8026 | { | |
8027 | u32 val; | |
1ee582d8 | 8028 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 8029 | int i, err; |
1da177e4 | 8030 | |
f49639e6 DM |
8031 | tg3_nvram_lock(tp); |
8032 | ||
77b483f1 MC |
8033 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
8034 | ||
f49639e6 DM |
8035 | /* No matching tg3_nvram_unlock() after this because |
8036 | * chip reset below will undo the nvram lock. | |
8037 | */ | |
8038 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 8039 | |
ee6a99b5 MC |
8040 | /* GRC_MISC_CFG core clock reset will clear the memory |
8041 | * enable bit in PCI register 4 and the MSI enable bit | |
8042 | * on some chips, so we save relevant registers here. | |
8043 | */ | |
8044 | tg3_save_pci_state(tp); | |
8045 | ||
d9ab5ad1 | 8046 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
63c3a66f | 8047 | tg3_flag(tp, 5755_PLUS)) |
d9ab5ad1 MC |
8048 | tw32(GRC_FASTBOOT_PC, 0); |
8049 | ||
1da177e4 LT |
8050 | /* |
8051 | * We must avoid the readl() that normally takes place. | |
8052 | * It locks machines, causes machine checks, and other | |
8053 | * fun things. So, temporarily disable the 5701 | |
8054 | * hardware workaround, while we do the reset. | |
8055 | */ | |
1ee582d8 MC |
8056 | write_op = tp->write32; |
8057 | if (write_op == tg3_write_flush_reg32) | |
8058 | tp->write32 = tg3_write32; | |
1da177e4 | 8059 | |
d18edcb2 MC |
8060 | /* Prevent the irq handler from reading or writing PCI registers |
8061 | * during chip reset when the memory enable bit in the PCI command | |
8062 | * register may be cleared. The chip does not generate interrupt | |
8063 | * at this time, but the irq handler may still be called due to irq | |
8064 | * sharing or irqpoll. | |
8065 | */ | |
63c3a66f | 8066 | tg3_flag_set(tp, CHIP_RESETTING); |
f77a6a8e MC |
8067 | for (i = 0; i < tp->irq_cnt; i++) { |
8068 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8069 | if (tnapi->hw_status) { | |
8070 | tnapi->hw_status->status = 0; | |
8071 | tnapi->hw_status->status_tag = 0; | |
8072 | } | |
8073 | tnapi->last_tag = 0; | |
8074 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 8075 | } |
d18edcb2 | 8076 | smp_mb(); |
4f125f42 MC |
8077 | |
8078 | for (i = 0; i < tp->irq_cnt; i++) | |
8079 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 8080 | |
255ca311 MC |
8081 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8082 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
8083 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
8084 | } | |
8085 | ||
1da177e4 LT |
8086 | /* do the reset */ |
8087 | val = GRC_MISC_CFG_CORECLK_RESET; | |
8088 | ||
63c3a66f | 8089 | if (tg3_flag(tp, PCI_EXPRESS)) { |
88075d91 MC |
8090 | /* Force PCIe 1.0a mode */ |
8091 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 8092 | !tg3_flag(tp, 57765_PLUS) && |
88075d91 MC |
8093 | tr32(TG3_PCIE_PHY_TSTCTL) == |
8094 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
8095 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
8096 | ||
1da177e4 LT |
8097 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
8098 | tw32(GRC_MISC_CFG, (1 << 29)); | |
8099 | val |= (1 << 29); | |
8100 | } | |
8101 | } | |
8102 | ||
b5d3772c MC |
8103 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
8104 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
8105 | tw32(GRC_VCPU_EXT_CTRL, | |
8106 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
8107 | } | |
8108 | ||
f37500d3 | 8109 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
63c3a66f | 8110 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) |
1da177e4 | 8111 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 8112 | |
1da177e4 LT |
8113 | tw32(GRC_MISC_CFG, val); |
8114 | ||
1ee582d8 MC |
8115 | /* restore 5701 hardware bug workaround write method */ |
8116 | tp->write32 = write_op; | |
1da177e4 LT |
8117 | |
8118 | /* Unfortunately, we have to delay before the PCI read back. | |
8119 | * Some 575X chips even will not respond to a PCI cfg access | |
8120 | * when the reset command is given to the chip. | |
8121 | * | |
8122 | * How do these hardware designers expect things to work | |
8123 | * properly if the PCI write is posted for a long period | |
8124 | * of time? It is always necessary to have some method by | |
8125 | * which a register read back can occur to push the write | |
8126 | * out which does the reset. | |
8127 | * | |
8128 | * For most tg3 variants the trick below was working. | |
8129 | * Ho hum... | |
8130 | */ | |
8131 | udelay(120); | |
8132 | ||
8133 | /* Flush PCI posted writes. The normal MMIO registers | |
8134 | * are inaccessible at this time so this is the only | |
8135 | * way to make this reliably (actually, this is no longer | |
8136 | * the case, see above). I tried to use indirect | |
8137 | * register read/write but this upset some 5701 variants. | |
8138 | */ | |
8139 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
8140 | ||
8141 | udelay(120); | |
8142 | ||
0f49bfbd | 8143 | if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { |
e7126997 MC |
8144 | u16 val16; |
8145 | ||
1da177e4 | 8146 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
86449944 | 8147 | int j; |
1da177e4 LT |
8148 | u32 cfg_val; |
8149 | ||
8150 | /* Wait for link training to complete. */ | |
86449944 | 8151 | for (j = 0; j < 5000; j++) |
1da177e4 LT |
8152 | udelay(100); |
8153 | ||
8154 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
8155 | pci_write_config_dword(tp->pdev, 0xc4, | |
8156 | cfg_val | (1 << 15)); | |
8157 | } | |
5e7dfd0f | 8158 | |
e7126997 | 8159 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
0f49bfbd | 8160 | val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN; |
e7126997 MC |
8161 | /* |
8162 | * Older PCIe devices only support the 128 byte | |
8163 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 8164 | */ |
63c3a66f | 8165 | if (!tg3_flag(tp, CPMU_PRESENT)) |
0f49bfbd JL |
8166 | val16 |= PCI_EXP_DEVCTL_PAYLOAD; |
8167 | pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); | |
5e7dfd0f | 8168 | |
5e7dfd0f | 8169 | /* Clear error status */ |
0f49bfbd | 8170 | pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, |
5e7dfd0f MC |
8171 | PCI_EXP_DEVSTA_CED | |
8172 | PCI_EXP_DEVSTA_NFED | | |
8173 | PCI_EXP_DEVSTA_FED | | |
8174 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
8175 | } |
8176 | ||
ee6a99b5 | 8177 | tg3_restore_pci_state(tp); |
1da177e4 | 8178 | |
63c3a66f JP |
8179 | tg3_flag_clear(tp, CHIP_RESETTING); |
8180 | tg3_flag_clear(tp, ERROR_PROCESSED); | |
d18edcb2 | 8181 | |
ee6a99b5 | 8182 | val = 0; |
63c3a66f | 8183 | if (tg3_flag(tp, 5780_CLASS)) |
4cf78e4f | 8184 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 8185 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
8186 | |
8187 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
8188 | tg3_stop_fw(tp); | |
8189 | tw32(0x5000, 0x400); | |
8190 | } | |
8191 | ||
8192 | tw32(GRC_MODE, tp->grc_mode); | |
8193 | ||
8194 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 8195 | val = tr32(0xc4); |
1da177e4 LT |
8196 | |
8197 | tw32(0xc4, val | (1 << 15)); | |
8198 | } | |
8199 | ||
8200 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
8201 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
8202 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
8203 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
8204 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
8205 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8206 | } | |
8207 | ||
f07e9af3 | 8208 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
9e975cc2 | 8209 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; |
d2394e6b | 8210 | val = tp->mac_mode; |
f07e9af3 | 8211 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
9e975cc2 | 8212 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; |
d2394e6b | 8213 | val = tp->mac_mode; |
1da177e4 | 8214 | } else |
d2394e6b MC |
8215 | val = 0; |
8216 | ||
8217 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
8218 | udelay(40); |
8219 | ||
77b483f1 MC |
8220 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
8221 | ||
7a6f4369 MC |
8222 | err = tg3_poll_fw(tp); |
8223 | if (err) | |
8224 | return err; | |
1da177e4 | 8225 | |
0a9140cf MC |
8226 | tg3_mdio_start(tp); |
8227 | ||
63c3a66f | 8228 | if (tg3_flag(tp, PCI_EXPRESS) && |
f6eb9b1f MC |
8229 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
8230 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
63c3a66f | 8231 | !tg3_flag(tp, 57765_PLUS)) { |
ab0049b4 | 8232 | val = tr32(0x7c00); |
1da177e4 LT |
8233 | |
8234 | tw32(0x7c00, val | (1 << 25)); | |
8235 | } | |
8236 | ||
d78b59f5 MC |
8237 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
8238 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
8239 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
8240 | } | |
8241 | ||
1da177e4 | 8242 | /* Reprobe ASF enable state. */ |
63c3a66f JP |
8243 | tg3_flag_clear(tp, ENABLE_ASF); |
8244 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
8245 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
8246 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
8247 | u32 nic_cfg; | |
8248 | ||
8249 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
8250 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f | 8251 | tg3_flag_set(tp, ENABLE_ASF); |
4ba526ce | 8252 | tp->last_event_jiffies = jiffies; |
63c3a66f JP |
8253 | if (tg3_flag(tp, 5750_PLUS)) |
8254 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 LT |
8255 | } |
8256 | } | |
8257 | ||
8258 | return 0; | |
8259 | } | |
8260 | ||
65ec698d MC |
8261 | static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *); |
8262 | static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *); | |
92feeabf | 8263 | |
1da177e4 | 8264 | /* tp->lock is held. */ |
944d980e | 8265 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
8266 | { |
8267 | int err; | |
8268 | ||
8269 | tg3_stop_fw(tp); | |
8270 | ||
944d980e | 8271 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 8272 | |
b3b7d6be | 8273 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
8274 | err = tg3_chip_reset(tp); |
8275 | ||
daba2a63 MC |
8276 | __tg3_set_mac_addr(tp, 0); |
8277 | ||
944d980e MC |
8278 | tg3_write_sig_legacy(tp, kind); |
8279 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 | 8280 | |
92feeabf MC |
8281 | if (tp->hw_stats) { |
8282 | /* Save the stats across chip resets... */ | |
b4017c53 | 8283 | tg3_get_nstats(tp, &tp->net_stats_prev); |
92feeabf MC |
8284 | tg3_get_estats(tp, &tp->estats_prev); |
8285 | ||
8286 | /* And make sure the next sample is new data */ | |
8287 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
8288 | } | |
8289 | ||
1da177e4 LT |
8290 | if (err) |
8291 | return err; | |
8292 | ||
8293 | return 0; | |
8294 | } | |
8295 | ||
1da177e4 LT |
8296 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
8297 | { | |
8298 | struct tg3 *tp = netdev_priv(dev); | |
8299 | struct sockaddr *addr = p; | |
986e0aeb | 8300 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 8301 | |
f9804ddb | 8302 | if (!is_valid_ether_addr(addr->sa_data)) |
504f9b5a | 8303 | return -EADDRNOTAVAIL; |
f9804ddb | 8304 | |
1da177e4 LT |
8305 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
8306 | ||
e75f7c90 MC |
8307 | if (!netif_running(dev)) |
8308 | return 0; | |
8309 | ||
63c3a66f | 8310 | if (tg3_flag(tp, ENABLE_ASF)) { |
986e0aeb | 8311 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 8312 | |
986e0aeb MC |
8313 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
8314 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
8315 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
8316 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
8317 | ||
8318 | /* Skip MAC addr 1 if ASF is using it. */ | |
8319 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
8320 | !(addr1_high == 0 && addr1_low == 0)) | |
8321 | skip_mac_1 = 1; | |
58712ef9 | 8322 | } |
986e0aeb MC |
8323 | spin_lock_bh(&tp->lock); |
8324 | __tg3_set_mac_addr(tp, skip_mac_1); | |
8325 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 8326 | |
b9ec6c1b | 8327 | return err; |
1da177e4 LT |
8328 | } |
8329 | ||
8330 | /* tp->lock is held. */ | |
8331 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
8332 | dma_addr_t mapping, u32 maxlen_flags, | |
8333 | u32 nic_addr) | |
8334 | { | |
8335 | tg3_write_mem(tp, | |
8336 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
8337 | ((u64) mapping >> 32)); | |
8338 | tg3_write_mem(tp, | |
8339 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
8340 | ((u64) mapping & 0xffffffff)); | |
8341 | tg3_write_mem(tp, | |
8342 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
8343 | maxlen_flags); | |
8344 | ||
63c3a66f | 8345 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
8346 | tg3_write_mem(tp, |
8347 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
8348 | nic_addr); | |
8349 | } | |
8350 | ||
a489b6d9 MC |
8351 | |
8352 | static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec) | |
15f9850d | 8353 | { |
a489b6d9 | 8354 | int i = 0; |
b6080e12 | 8355 | |
63c3a66f | 8356 | if (!tg3_flag(tp, ENABLE_TSS)) { |
b6080e12 MC |
8357 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
8358 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
8359 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
8360 | } else { |
8361 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
8362 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
8363 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
a489b6d9 MC |
8364 | |
8365 | for (; i < tp->txq_cnt; i++) { | |
8366 | u32 reg; | |
8367 | ||
8368 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; | |
8369 | tw32(reg, ec->tx_coalesce_usecs); | |
8370 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
8371 | tw32(reg, ec->tx_max_coalesced_frames); | |
8372 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
8373 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
8374 | } | |
19cfaecc | 8375 | } |
b6080e12 | 8376 | |
a489b6d9 MC |
8377 | for (; i < tp->irq_max - 1; i++) { |
8378 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); | |
8379 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
8380 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
8381 | } | |
8382 | } | |
8383 | ||
8384 | static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec) | |
8385 | { | |
8386 | int i = 0; | |
8387 | u32 limit = tp->rxq_cnt; | |
8388 | ||
63c3a66f | 8389 | if (!tg3_flag(tp, ENABLE_RSS)) { |
19cfaecc MC |
8390 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
8391 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
8392 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
a489b6d9 | 8393 | limit--; |
19cfaecc | 8394 | } else { |
b6080e12 MC |
8395 | tw32(HOSTCC_RXCOL_TICKS, 0); |
8396 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
8397 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 8398 | } |
b6080e12 | 8399 | |
a489b6d9 | 8400 | for (; i < limit; i++) { |
b6080e12 MC |
8401 | u32 reg; |
8402 | ||
8403 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
8404 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
8405 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
8406 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
8407 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
8408 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
b6080e12 MC |
8409 | } |
8410 | ||
8411 | for (; i < tp->irq_max - 1; i++) { | |
8412 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 8413 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 8414 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
a489b6d9 MC |
8415 | } |
8416 | } | |
19cfaecc | 8417 | |
a489b6d9 MC |
8418 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
8419 | { | |
8420 | tg3_coal_tx_init(tp, ec); | |
8421 | tg3_coal_rx_init(tp, ec); | |
8422 | ||
8423 | if (!tg3_flag(tp, 5705_PLUS)) { | |
8424 | u32 val = ec->stats_block_coalesce_usecs; | |
8425 | ||
8426 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); | |
8427 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
8428 | ||
f4a46d1f | 8429 | if (!tp->link_up) |
a489b6d9 MC |
8430 | val = 0; |
8431 | ||
8432 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
b6080e12 | 8433 | } |
15f9850d | 8434 | } |
1da177e4 | 8435 | |
2d31ecaf MC |
8436 | /* tp->lock is held. */ |
8437 | static void tg3_rings_reset(struct tg3 *tp) | |
8438 | { | |
8439 | int i; | |
f77a6a8e | 8440 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
8441 | struct tg3_napi *tnapi = &tp->napi[0]; |
8442 | ||
8443 | /* Disable all transmit rings but the first. */ | |
63c3a66f | 8444 | if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 8445 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; |
63c3a66f | 8446 | else if (tg3_flag(tp, 5717_PLUS)) |
3d37728b | 8447 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
55086ad9 | 8448 | else if (tg3_flag(tp, 57765_CLASS)) |
b703df6f | 8449 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; |
2d31ecaf MC |
8450 | else |
8451 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
8452 | ||
8453 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
8454 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
8455 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
8456 | BDINFO_FLAGS_DISABLED); | |
8457 | ||
8458 | ||
8459 | /* Disable all receive return rings but the first. */ | |
63c3a66f | 8460 | if (tg3_flag(tp, 5717_PLUS)) |
f6eb9b1f | 8461 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
63c3a66f | 8462 | else if (!tg3_flag(tp, 5705_PLUS)) |
2d31ecaf | 8463 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f | 8464 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
55086ad9 | 8465 | tg3_flag(tp, 57765_CLASS)) |
2d31ecaf MC |
8466 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
8467 | else | |
8468 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
8469 | ||
8470 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
8471 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
8472 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
8473 | BDINFO_FLAGS_DISABLED); | |
8474 | ||
8475 | /* Disable interrupts */ | |
8476 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
0e6cf6a9 MC |
8477 | tp->napi[0].chk_msi_cnt = 0; |
8478 | tp->napi[0].last_rx_cons = 0; | |
8479 | tp->napi[0].last_tx_cons = 0; | |
2d31ecaf MC |
8480 | |
8481 | /* Zero mailbox registers. */ | |
63c3a66f | 8482 | if (tg3_flag(tp, SUPPORT_MSIX)) { |
6fd45cb8 | 8483 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
8484 | tp->napi[i].tx_prod = 0; |
8485 | tp->napi[i].tx_cons = 0; | |
63c3a66f | 8486 | if (tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 8487 | tw32_mailbox(tp->napi[i].prodmbox, 0); |
f77a6a8e MC |
8488 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
8489 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7f230735 | 8490 | tp->napi[i].chk_msi_cnt = 0; |
0e6cf6a9 MC |
8491 | tp->napi[i].last_rx_cons = 0; |
8492 | tp->napi[i].last_tx_cons = 0; | |
f77a6a8e | 8493 | } |
63c3a66f | 8494 | if (!tg3_flag(tp, ENABLE_TSS)) |
c2353a32 | 8495 | tw32_mailbox(tp->napi[0].prodmbox, 0); |
f77a6a8e MC |
8496 | } else { |
8497 | tp->napi[0].tx_prod = 0; | |
8498 | tp->napi[0].tx_cons = 0; | |
8499 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
8500 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
8501 | } | |
2d31ecaf MC |
8502 | |
8503 | /* Make sure the NIC-based send BD rings are disabled. */ | |
63c3a66f | 8504 | if (!tg3_flag(tp, 5705_PLUS)) { |
2d31ecaf MC |
8505 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
8506 | for (i = 0; i < 16; i++) | |
8507 | tw32_tx_mbox(mbox + i * 8, 0); | |
8508 | } | |
8509 | ||
8510 | txrcb = NIC_SRAM_SEND_RCB; | |
8511 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
8512 | ||
8513 | /* Clear status block in ram. */ | |
8514 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8515 | ||
8516 | /* Set status block DMA address */ | |
8517 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
8518 | ((u64) tnapi->status_mapping >> 32)); | |
8519 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8520 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
8521 | ||
f77a6a8e MC |
8522 | if (tnapi->tx_ring) { |
8523 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8524 | (TG3_TX_RING_SIZE << | |
8525 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8526 | NIC_SRAM_TX_BUFFER_DESC); | |
8527 | txrcb += TG3_BDINFO_SIZE; | |
8528 | } | |
8529 | ||
8530 | if (tnapi->rx_rcb) { | |
8531 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
8532 | (tp->rx_ret_ring_mask + 1) << |
8533 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
8534 | rxrcb += TG3_BDINFO_SIZE; |
8535 | } | |
8536 | ||
8537 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 8538 | |
f77a6a8e MC |
8539 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
8540 | u64 mapping = (u64)tnapi->status_mapping; | |
8541 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
8542 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
8543 | ||
8544 | /* Clear status block in ram. */ | |
8545 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
8546 | ||
19cfaecc MC |
8547 | if (tnapi->tx_ring) { |
8548 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
8549 | (TG3_TX_RING_SIZE << | |
8550 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
8551 | NIC_SRAM_TX_BUFFER_DESC); | |
8552 | txrcb += TG3_BDINFO_SIZE; | |
8553 | } | |
f77a6a8e MC |
8554 | |
8555 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 8556 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
8557 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
8558 | ||
8559 | stblk += 8; | |
f77a6a8e MC |
8560 | rxrcb += TG3_BDINFO_SIZE; |
8561 | } | |
2d31ecaf MC |
8562 | } |
8563 | ||
eb07a940 MC |
8564 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
8565 | { | |
8566 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
8567 | ||
63c3a66f JP |
8568 | if (!tg3_flag(tp, 5750_PLUS) || |
8569 | tg3_flag(tp, 5780_CLASS) || | |
eb07a940 | 8570 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
513aa6ea MC |
8571 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
8572 | tg3_flag(tp, 57765_PLUS)) | |
eb07a940 MC |
8573 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; |
8574 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
8575 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
8576 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
8577 | else | |
8578 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
8579 | ||
8580 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
8581 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
8582 | ||
8583 | val = min(nic_rep_thresh, host_rep_thresh); | |
8584 | tw32(RCVBDI_STD_THRESH, val); | |
8585 | ||
63c3a66f | 8586 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8587 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); |
8588 | ||
63c3a66f | 8589 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
eb07a940 MC |
8590 | return; |
8591 | ||
513aa6ea | 8592 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; |
eb07a940 MC |
8593 | |
8594 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
8595 | ||
8596 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
8597 | tw32(RCVBDI_JUMBO_THRESH, val); | |
8598 | ||
63c3a66f | 8599 | if (tg3_flag(tp, 57765_PLUS)) |
eb07a940 MC |
8600 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); |
8601 | } | |
8602 | ||
ccd5ba9d MC |
8603 | static inline u32 calc_crc(unsigned char *buf, int len) |
8604 | { | |
8605 | u32 reg; | |
8606 | u32 tmp; | |
8607 | int j, k; | |
8608 | ||
8609 | reg = 0xffffffff; | |
8610 | ||
8611 | for (j = 0; j < len; j++) { | |
8612 | reg ^= buf[j]; | |
8613 | ||
8614 | for (k = 0; k < 8; k++) { | |
8615 | tmp = reg & 0x01; | |
8616 | ||
8617 | reg >>= 1; | |
8618 | ||
8619 | if (tmp) | |
8620 | reg ^= 0xedb88320; | |
8621 | } | |
8622 | } | |
8623 | ||
8624 | return ~reg; | |
8625 | } | |
8626 | ||
8627 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
8628 | { | |
8629 | /* accept or reject all multicast frames */ | |
8630 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
8631 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
8632 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
8633 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
8634 | } | |
8635 | ||
8636 | static void __tg3_set_rx_mode(struct net_device *dev) | |
8637 | { | |
8638 | struct tg3 *tp = netdev_priv(dev); | |
8639 | u32 rx_mode; | |
8640 | ||
8641 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
8642 | RX_MODE_KEEP_VLAN_TAG); | |
8643 | ||
8644 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) | |
8645 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG | |
8646 | * flag clear. | |
8647 | */ | |
8648 | if (!tg3_flag(tp, ENABLE_ASF)) | |
8649 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
8650 | #endif | |
8651 | ||
8652 | if (dev->flags & IFF_PROMISC) { | |
8653 | /* Promiscuous mode. */ | |
8654 | rx_mode |= RX_MODE_PROMISC; | |
8655 | } else if (dev->flags & IFF_ALLMULTI) { | |
8656 | /* Accept all multicast. */ | |
8657 | tg3_set_multi(tp, 1); | |
8658 | } else if (netdev_mc_empty(dev)) { | |
8659 | /* Reject all multicast. */ | |
8660 | tg3_set_multi(tp, 0); | |
8661 | } else { | |
8662 | /* Accept one or more multicast(s). */ | |
8663 | struct netdev_hw_addr *ha; | |
8664 | u32 mc_filter[4] = { 0, }; | |
8665 | u32 regidx; | |
8666 | u32 bit; | |
8667 | u32 crc; | |
8668 | ||
8669 | netdev_for_each_mc_addr(ha, dev) { | |
8670 | crc = calc_crc(ha->addr, ETH_ALEN); | |
8671 | bit = ~crc & 0x7f; | |
8672 | regidx = (bit & 0x60) >> 5; | |
8673 | bit &= 0x1f; | |
8674 | mc_filter[regidx] |= (1 << bit); | |
8675 | } | |
8676 | ||
8677 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
8678 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
8679 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
8680 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
8681 | } | |
8682 | ||
8683 | if (rx_mode != tp->rx_mode) { | |
8684 | tp->rx_mode = rx_mode; | |
8685 | tw32_f(MAC_RX_MODE, rx_mode); | |
8686 | udelay(10); | |
8687 | } | |
8688 | } | |
8689 | ||
9102426a | 8690 | static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt) |
90415477 MC |
8691 | { |
8692 | int i; | |
8693 | ||
8694 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) | |
9102426a | 8695 | tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); |
90415477 MC |
8696 | } |
8697 | ||
8698 | static void tg3_rss_check_indir_tbl(struct tg3 *tp) | |
bcebcc46 MC |
8699 | { |
8700 | int i; | |
8701 | ||
8702 | if (!tg3_flag(tp, SUPPORT_MSIX)) | |
8703 | return; | |
8704 | ||
90415477 | 8705 | if (tp->irq_cnt <= 2) { |
bcebcc46 | 8706 | memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); |
90415477 MC |
8707 | return; |
8708 | } | |
8709 | ||
8710 | /* Validate table against current IRQ count */ | |
8711 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8712 | if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1) | |
8713 | break; | |
8714 | } | |
8715 | ||
8716 | if (i != TG3_RSS_INDIR_TBL_SIZE) | |
9102426a | 8717 | tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); |
bcebcc46 MC |
8718 | } |
8719 | ||
90415477 | 8720 | static void tg3_rss_write_indir_tbl(struct tg3 *tp) |
bcebcc46 MC |
8721 | { |
8722 | int i = 0; | |
8723 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8724 | ||
8725 | while (i < TG3_RSS_INDIR_TBL_SIZE) { | |
8726 | u32 val = tp->rss_ind_tbl[i]; | |
8727 | i++; | |
8728 | for (; i % 8; i++) { | |
8729 | val <<= 4; | |
8730 | val |= tp->rss_ind_tbl[i]; | |
8731 | } | |
8732 | tw32(reg, val); | |
8733 | reg += 4; | |
8734 | } | |
8735 | } | |
8736 | ||
1da177e4 | 8737 | /* tp->lock is held. */ |
8e7a22e3 | 8738 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
8739 | { |
8740 | u32 val, rdmac_mode; | |
8741 | int i, err, limit; | |
8fea32b9 | 8742 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
8743 | |
8744 | tg3_disable_ints(tp); | |
8745 | ||
8746 | tg3_stop_fw(tp); | |
8747 | ||
8748 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
8749 | ||
63c3a66f | 8750 | if (tg3_flag(tp, INIT_COMPLETE)) |
e6de8ad1 | 8751 | tg3_abort_hw(tp, 1); |
1da177e4 | 8752 | |
699c0193 MC |
8753 | /* Enable MAC control of LPI */ |
8754 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
8755 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
8756 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
8757 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
8758 | ||
8759 | tw32_f(TG3_CPMU_EEE_CTRL, | |
8760 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
8761 | ||
a386b901 MC |
8762 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
8763 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
8764 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
8765 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
8766 | ||
8767 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8768 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
8769 | ||
63c3a66f | 8770 | if (tg3_flag(tp, ENABLE_APE)) |
a386b901 MC |
8771 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; |
8772 | ||
8773 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
8774 | ||
8775 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
8776 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
8777 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
8778 | ||
8779 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 8780 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 8781 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
8782 | } |
8783 | ||
603f1173 | 8784 | if (reset_phy) |
d4d2c558 MC |
8785 | tg3_phy_reset(tp); |
8786 | ||
1da177e4 LT |
8787 | err = tg3_chip_reset(tp); |
8788 | if (err) | |
8789 | return err; | |
8790 | ||
8791 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
8792 | ||
bcb37f6c | 8793 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
8794 | val = tr32(TG3_CPMU_CTRL); |
8795 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
8796 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
8797 | |
8798 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8799 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8800 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8801 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8802 | ||
8803 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
8804 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
8805 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
8806 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
8807 | ||
8808 | val = tr32(TG3_CPMU_HST_ACC); | |
8809 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
8810 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
8811 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
8812 | } |
8813 | ||
33466d93 MC |
8814 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8815 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
8816 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
8817 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
8818 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
8819 | |
8820 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
8821 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
8822 | ||
8823 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 8824 | |
f40386c8 MC |
8825 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
8826 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
8827 | } |
8828 | ||
63c3a66f | 8829 | if (tg3_flag(tp, L1PLLPD_EN)) { |
614b0590 MC |
8830 | u32 grc_mode = tr32(GRC_MODE); |
8831 | ||
8832 | /* Access the lower 1K of PL PCIE block registers. */ | |
8833 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8834 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
8835 | ||
8836 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
8837 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
8838 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
8839 | ||
8840 | tw32(GRC_MODE, grc_mode); | |
8841 | } | |
8842 | ||
55086ad9 | 8843 | if (tg3_flag(tp, 57765_CLASS)) { |
5093eedc MC |
8844 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
8845 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 8846 | |
5093eedc MC |
8847 | /* Access the lower 1K of PL PCIE block registers. */ |
8848 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8849 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 8850 | |
5093eedc MC |
8851 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
8852 | TG3_PCIE_PL_LO_PHYCTL5); | |
8853 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
8854 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 8855 | |
5093eedc MC |
8856 | tw32(GRC_MODE, grc_mode); |
8857 | } | |
a977dbe8 | 8858 | |
1ff30a59 MC |
8859 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { |
8860 | u32 grc_mode = tr32(GRC_MODE); | |
8861 | ||
8862 | /* Access the lower 1K of DL PCIE block registers. */ | |
8863 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8864 | tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); | |
8865 | ||
8866 | val = tr32(TG3_PCIE_TLDLPL_PORT + | |
8867 | TG3_PCIE_DL_LO_FTSMAX); | |
8868 | val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; | |
8869 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, | |
8870 | val | TG3_PCIE_DL_LO_FTSMAX_VAL); | |
8871 | ||
8872 | tw32(GRC_MODE, grc_mode); | |
8873 | } | |
8874 | ||
a977dbe8 MC |
8875 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
8876 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8877 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8878 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
8879 | } |
8880 | ||
1da177e4 LT |
8881 | /* This works around an issue with Athlon chipsets on |
8882 | * B3 tigon3 silicon. This bit has no effect on any | |
8883 | * other revision. But do not set this on PCI Express | |
795d01c5 | 8884 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 8885 | */ |
63c3a66f JP |
8886 | if (!tg3_flag(tp, CPMU_PRESENT)) { |
8887 | if (!tg3_flag(tp, PCI_EXPRESS)) | |
795d01c5 MC |
8888 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; |
8889 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8890 | } | |
1da177e4 LT |
8891 | |
8892 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
63c3a66f | 8893 | tg3_flag(tp, PCIX_MODE)) { |
1da177e4 LT |
8894 | val = tr32(TG3PCI_PCISTATE); |
8895 | val |= PCISTATE_RETRY_SAME_DMA; | |
8896 | tw32(TG3PCI_PCISTATE, val); | |
8897 | } | |
8898 | ||
63c3a66f | 8899 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
8900 | /* Allow reads and writes to the |
8901 | * APE register and memory space. | |
8902 | */ | |
8903 | val = tr32(TG3PCI_PCISTATE); | |
8904 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
8905 | PCISTATE_ALLOW_APE_SHMEM_WR | |
8906 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
8907 | tw32(TG3PCI_PCISTATE, val); |
8908 | } | |
8909 | ||
1da177e4 LT |
8910 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
8911 | /* Enable some hw fixes. */ | |
8912 | val = tr32(TG3PCI_MSI_DATA); | |
8913 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
8914 | tw32(TG3PCI_MSI_DATA, val); | |
8915 | } | |
8916 | ||
8917 | /* Descriptor ring init may make accesses to the | |
8918 | * NIC SRAM area to setup the TX descriptors, so we | |
8919 | * can only do this after the hardware has been | |
8920 | * successfully reset. | |
8921 | */ | |
32d8c572 MC |
8922 | err = tg3_init_rings(tp); |
8923 | if (err) | |
8924 | return err; | |
1da177e4 | 8925 | |
63c3a66f | 8926 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
8927 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
8928 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
8929 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
8930 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
55086ad9 | 8931 | if (!tg3_flag(tp, 57765_CLASS) && |
0aebff48 MC |
8932 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) |
8933 | val |= DMA_RWCTRL_TAGGED_STAT_WA; | |
cbf9ca6c MC |
8934 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
8935 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
8936 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
8937 | /* This value is determined during the probe time DMA |
8938 | * engine test, tg3_test_dma. | |
8939 | */ | |
8940 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
8941 | } | |
1da177e4 LT |
8942 | |
8943 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
8944 | GRC_MODE_4X_NIC_SEND_RINGS | | |
8945 | GRC_MODE_NO_TX_PHDR_CSUM | | |
8946 | GRC_MODE_NO_RX_PHDR_CSUM); | |
8947 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
8948 | |
8949 | /* Pseudo-header checksum is done by hardware logic and not | |
8950 | * the offload processers, so make the chip do the pseudo- | |
8951 | * header checksums on receive. For transmit it is more | |
8952 | * convenient to do the pseudo-header checksum in software | |
8953 | * as Linux does that on transmit for us in all cases. | |
8954 | */ | |
8955 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
8956 | |
8957 | tw32(GRC_MODE, | |
8958 | tp->grc_mode | | |
8959 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
8960 | ||
8961 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
8962 | val = tr32(GRC_MISC_CFG); | |
8963 | val &= ~0xff; | |
8964 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
8965 | tw32(GRC_MISC_CFG, val); | |
8966 | ||
8967 | /* Initialize MBUF/DESC pool. */ | |
63c3a66f | 8968 | if (tg3_flag(tp, 5750_PLUS)) { |
1da177e4 LT |
8969 | /* Do nothing. */ |
8970 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8971 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8972 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8973 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8974 | else | |
8975 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8976 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8977 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
63c3a66f | 8978 | } else if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
8979 | int fw_len; |
8980 | ||
077f849d | 8981 | fw_len = tp->fw_len; |
1da177e4 LT |
8982 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
8983 | tw32(BUFMGR_MB_POOL_ADDR, | |
8984 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8985 | tw32(BUFMGR_MB_POOL_SIZE, | |
8986 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8987 | } | |
1da177e4 | 8988 | |
0f893dc6 | 8989 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
8990 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
8991 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8992 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8993 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8994 | tw32(BUFMGR_MB_HIGH_WATER, | |
8995 | tp->bufmgr_config.mbuf_high_water); | |
8996 | } else { | |
8997 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8998 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8999 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
9000 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
9001 | tw32(BUFMGR_MB_HIGH_WATER, | |
9002 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
9003 | } | |
9004 | tw32(BUFMGR_DMA_LOW_WATER, | |
9005 | tp->bufmgr_config.dma_low_water); | |
9006 | tw32(BUFMGR_DMA_HIGH_WATER, | |
9007 | tp->bufmgr_config.dma_high_water); | |
9008 | ||
d309a46e MC |
9009 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
9010 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
9011 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
4d958473 MC |
9012 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
9013 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
9014 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
9015 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
d309a46e | 9016 | tw32(BUFMGR_MODE, val); |
1da177e4 LT |
9017 | for (i = 0; i < 2000; i++) { |
9018 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
9019 | break; | |
9020 | udelay(10); | |
9021 | } | |
9022 | if (i >= 2000) { | |
05dbe005 | 9023 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
9024 | return -ENODEV; |
9025 | } | |
9026 | ||
eb07a940 MC |
9027 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
9028 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
b5d3772c | 9029 | |
eb07a940 | 9030 | tg3_setup_rxbd_thresholds(tp); |
1da177e4 LT |
9031 | |
9032 | /* Initialize TG3_BDINFO's at: | |
9033 | * RCVDBDI_STD_BD: standard eth size rx ring | |
9034 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
9035 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
9036 | * | |
9037 | * like so: | |
9038 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
9039 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
9040 | * ring attribute flags | |
9041 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
9042 | * | |
9043 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
9044 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
9045 | * | |
9046 | * The size of each ring is fixed in the firmware, but the location is | |
9047 | * configurable. | |
9048 | */ | |
9049 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 9050 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 9051 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 9052 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
63c3a66f | 9053 | if (!tg3_flag(tp, 5717_PLUS)) |
87668d35 MC |
9054 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
9055 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 9056 | |
fdb72b38 | 9057 | /* Disable the mini ring */ |
63c3a66f | 9058 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
9059 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
9060 | BDINFO_FLAGS_DISABLED); | |
9061 | ||
fdb72b38 MC |
9062 | /* Program the jumbo buffer descriptor ring control |
9063 | * blocks on those devices that have them. | |
9064 | */ | |
a0512944 | 9065 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
63c3a66f | 9066 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { |
1da177e4 | 9067 | |
63c3a66f | 9068 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { |
1da177e4 | 9069 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 9070 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 9071 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 9072 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
9073 | val = TG3_RX_JMB_RING_SIZE(tp) << |
9074 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 9075 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 9076 | val | BDINFO_FLAGS_USE_EXT_RECV); |
63c3a66f | 9077 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || |
55086ad9 | 9078 | tg3_flag(tp, 57765_CLASS)) |
87668d35 MC |
9079 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
9080 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
9081 | } else { |
9082 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
9083 | BDINFO_FLAGS_DISABLED); | |
9084 | } | |
9085 | ||
63c3a66f | 9086 | if (tg3_flag(tp, 57765_PLUS)) { |
fa6b2aae | 9087 | val = TG3_RX_STD_RING_SIZE(tp); |
7cb32cf2 MC |
9088 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
9089 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
9090 | } else | |
04380d40 | 9091 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 9092 | } else |
de9f5230 | 9093 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
9094 | |
9095 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 9096 | |
411da640 | 9097 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 9098 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 9099 | |
63c3a66f JP |
9100 | tpr->rx_jmb_prod_idx = |
9101 | tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; | |
66711e66 | 9102 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 9103 | |
2d31ecaf MC |
9104 | tg3_rings_reset(tp); |
9105 | ||
1da177e4 | 9106 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 9107 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
9108 | |
9109 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
9110 | tw32(MAC_RX_MTU_SIZE, |
9111 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
9112 | |
9113 | /* The slot time is changed by tg3_setup_phy if we | |
9114 | * run at gigabit with half duplex. | |
9115 | */ | |
f2096f94 MC |
9116 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
9117 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
9118 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
9119 | ||
9120 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
9121 | val |= tr32(MAC_TX_LENGTHS) & | |
9122 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
9123 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
9124 | ||
9125 | tw32(MAC_TX_LENGTHS, val); | |
1da177e4 LT |
9126 | |
9127 | /* Receive rules. */ | |
9128 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
9129 | tw32(RCVLPC_CONFIG, 0x0181); | |
9130 | ||
9131 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
9132 | * the RCVLPC_STATE_ENABLE mask. | |
9133 | */ | |
9134 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
9135 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
9136 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
9137 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
9138 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 9139 | |
deabaac8 | 9140 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
9141 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
9142 | ||
57e6983c | 9143 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
9144 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
9145 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
9146 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
9147 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
9148 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
9149 | ||
c5908939 MC |
9150 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
9151 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 9152 | if (tg3_flag(tp, TSO_CAPABLE) && |
c13e3713 | 9153 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
9154 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
9155 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 9156 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
9157 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
9158 | } | |
9159 | } | |
9160 | ||
63c3a66f | 9161 | if (tg3_flag(tp, PCI_EXPRESS)) |
85e94ced MC |
9162 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
9163 | ||
63c3a66f JP |
9164 | if (tg3_flag(tp, HW_TSO_1) || |
9165 | tg3_flag(tp, HW_TSO_2) || | |
9166 | tg3_flag(tp, HW_TSO_3)) | |
027455ad MC |
9167 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
9168 | ||
108a6c16 | 9169 | if (tg3_flag(tp, 57765_PLUS) || |
e849cdc3 | 9170 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
027455ad MC |
9171 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
9172 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 9173 | |
f2096f94 MC |
9174 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
9175 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
9176 | ||
41a8a7ee MC |
9177 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9178 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
9179 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
9180 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
63c3a66f | 9181 | tg3_flag(tp, 57765_PLUS)) { |
41a8a7ee | 9182 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
10ce95d6 | 9183 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) { |
b4495ed8 MC |
9184 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
9185 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
9186 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
9187 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
9188 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
9189 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 9190 | } |
41a8a7ee MC |
9191 | tw32(TG3_RDMA_RSRVCTRL_REG, |
9192 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
9193 | } | |
9194 | ||
d78b59f5 MC |
9195 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
9196 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
9197 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
9198 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
9199 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
9200 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
9201 | } | |
9202 | ||
1da177e4 | 9203 | /* Receive/send statistics. */ |
63c3a66f | 9204 | if (tg3_flag(tp, 5750_PLUS)) { |
1661394e MC |
9205 | val = tr32(RCVLPC_STATS_ENABLE); |
9206 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
9207 | tw32(RCVLPC_STATS_ENABLE, val); | |
9208 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
63c3a66f | 9209 | tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
9210 | val = tr32(RCVLPC_STATS_ENABLE); |
9211 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
9212 | tw32(RCVLPC_STATS_ENABLE, val); | |
9213 | } else { | |
9214 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
9215 | } | |
9216 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
9217 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
9218 | tw32(SNDDATAI_STATSCTRL, | |
9219 | (SNDDATAI_SCTRL_ENABLE | | |
9220 | SNDDATAI_SCTRL_FASTUPD)); | |
9221 | ||
9222 | /* Setup host coalescing engine. */ | |
9223 | tw32(HOSTCC_MODE, 0); | |
9224 | for (i = 0; i < 2000; i++) { | |
9225 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
9226 | break; | |
9227 | udelay(10); | |
9228 | } | |
9229 | ||
d244c892 | 9230 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 9231 | |
63c3a66f | 9232 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
9233 | /* Status/statistics block address. See tg3_timer, |
9234 | * the tg3_periodic_fetch_stats call there, and | |
9235 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
9236 | */ | |
1da177e4 LT |
9237 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
9238 | ((u64) tp->stats_mapping >> 32)); | |
9239 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
9240 | ((u64) tp->stats_mapping & 0xffffffff)); | |
9241 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 9242 | |
1da177e4 | 9243 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
9244 | |
9245 | /* Clear statistics and status block memory areas */ | |
9246 | for (i = NIC_SRAM_STATS_BLK; | |
9247 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
9248 | i += sizeof(u32)) { | |
9249 | tg3_write_mem(tp, i, 0); | |
9250 | udelay(40); | |
9251 | } | |
1da177e4 LT |
9252 | } |
9253 | ||
9254 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
9255 | ||
9256 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
9257 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
63c3a66f | 9258 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 LT |
9259 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); |
9260 | ||
f07e9af3 MC |
9261 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
9262 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
9263 | /* reset to prevent losing 1st rx packet intermittently */ |
9264 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
9265 | udelay(10); | |
9266 | } | |
9267 | ||
3bda1258 | 9268 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | |
9e975cc2 MC |
9269 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | |
9270 | MAC_MODE_FHDE_ENABLE; | |
9271 | if (tg3_flag(tp, ENABLE_APE)) | |
9272 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
63c3a66f | 9273 | if (!tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 9274 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
9275 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
9276 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
9277 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
9278 | udelay(40); | |
9279 | ||
314fba34 | 9280 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
63c3a66f | 9281 | * If TG3_FLAG_IS_NIC is zero, we should read the |
314fba34 MC |
9282 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
9283 | * whether used as inputs or outputs, are set by boot code after | |
9284 | * reset. | |
9285 | */ | |
63c3a66f | 9286 | if (!tg3_flag(tp, IS_NIC)) { |
314fba34 MC |
9287 | u32 gpio_mask; |
9288 | ||
9d26e213 MC |
9289 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
9290 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
9291 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
9292 | |
9293 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
9294 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
9295 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
9296 | ||
af36e6b6 MC |
9297 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
9298 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
9299 | ||
aaf84465 | 9300 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
9301 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
9302 | ||
9303 | /* GPIO1 must be driven high for eeprom write protect */ | |
63c3a66f | 9304 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) |
9d26e213 MC |
9305 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
9306 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 9307 | } |
1da177e4 LT |
9308 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
9309 | udelay(100); | |
9310 | ||
c3b5003b | 9311 | if (tg3_flag(tp, USING_MSIX)) { |
baf8a94a | 9312 | val = tr32(MSGINT_MODE); |
c3b5003b MC |
9313 | val |= MSGINT_MODE_ENABLE; |
9314 | if (tp->irq_cnt > 1) | |
9315 | val |= MSGINT_MODE_MULTIVEC_EN; | |
5b39de91 MC |
9316 | if (!tg3_flag(tp, 1SHOT_MSI)) |
9317 | val |= MSGINT_MODE_ONE_SHOT_DISABLE; | |
baf8a94a MC |
9318 | tw32(MSGINT_MODE, val); |
9319 | } | |
9320 | ||
63c3a66f | 9321 | if (!tg3_flag(tp, 5705_PLUS)) { |
1da177e4 LT |
9322 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); |
9323 | udelay(40); | |
9324 | } | |
9325 | ||
9326 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
9327 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
9328 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
9329 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
9330 | WDMAC_MODE_LNGREAD_ENAB); | |
9331 | ||
c5908939 MC |
9332 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
9333 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 9334 | if (tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 LT |
9335 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
9336 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
9337 | /* nothing */ | |
9338 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
63c3a66f | 9339 | !tg3_flag(tp, IS_5788)) { |
1da177e4 LT |
9340 | val |= WDMAC_MODE_RX_ACCEL; |
9341 | } | |
9342 | } | |
9343 | ||
d9ab5ad1 | 9344 | /* Enable host coalescing bug fix */ |
63c3a66f | 9345 | if (tg3_flag(tp, 5755_PLUS)) |
f51f3562 | 9346 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 9347 | |
788a035e MC |
9348 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
9349 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
9350 | ||
1da177e4 LT |
9351 | tw32_f(WDMAC_MODE, val); |
9352 | udelay(40); | |
9353 | ||
63c3a66f | 9354 | if (tg3_flag(tp, PCIX_MODE)) { |
9974a356 MC |
9355 | u16 pcix_cmd; |
9356 | ||
9357 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
9358 | &pcix_cmd); | |
1da177e4 | 9359 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
9360 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
9361 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 9362 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
9363 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
9364 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 9365 | } |
9974a356 MC |
9366 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
9367 | pcix_cmd); | |
1da177e4 LT |
9368 | } |
9369 | ||
9370 | tw32_f(RDMAC_MODE, rdmac_mode); | |
9371 | udelay(40); | |
9372 | ||
091f0ea3 MC |
9373 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { |
9374 | for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) { | |
9375 | if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) | |
9376 | break; | |
9377 | } | |
9378 | if (i < TG3_NUM_RDMA_CHANNELS) { | |
9379 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); | |
9380 | val |= TG3_LSO_RD_DMA_TX_LENGTH_WA; | |
9381 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); | |
9382 | tg3_flag_set(tp, 5719_RDMA_BUG); | |
9383 | } | |
9384 | } | |
9385 | ||
1da177e4 | 9386 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); |
63c3a66f | 9387 | if (!tg3_flag(tp, 5705_PLUS)) |
1da177e4 | 9388 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); |
9936bcf6 MC |
9389 | |
9390 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
9391 | tw32(SNDDATAC_MODE, | |
9392 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
9393 | else | |
9394 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
9395 | ||
1da177e4 LT |
9396 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
9397 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 9398 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
63c3a66f | 9399 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
7cb32cf2 MC |
9400 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
9401 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 9402 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
63c3a66f JP |
9403 | if (tg3_flag(tp, HW_TSO_1) || |
9404 | tg3_flag(tp, HW_TSO_2) || | |
9405 | tg3_flag(tp, HW_TSO_3)) | |
1da177e4 | 9406 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); |
baf8a94a | 9407 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
63c3a66f | 9408 | if (tg3_flag(tp, ENABLE_TSS)) |
baf8a94a MC |
9409 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
9410 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
9411 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
9412 | ||
9413 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9414 | err = tg3_load_5701_a0_firmware_fix(tp); | |
9415 | if (err) | |
9416 | return err; | |
9417 | } | |
9418 | ||
63c3a66f | 9419 | if (tg3_flag(tp, TSO_CAPABLE)) { |
1da177e4 LT |
9420 | err = tg3_load_tso_firmware(tp); |
9421 | if (err) | |
9422 | return err; | |
9423 | } | |
1da177e4 LT |
9424 | |
9425 | tp->tx_mode = TX_MODE_ENABLE; | |
f2096f94 | 9426 | |
63c3a66f | 9427 | if (tg3_flag(tp, 5755_PLUS) || |
b1d05210 MC |
9428 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
9429 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
f2096f94 MC |
9430 | |
9431 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
9432 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
9433 | tp->tx_mode &= ~val; | |
9434 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
9435 | } | |
9436 | ||
1da177e4 LT |
9437 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
9438 | udelay(100); | |
9439 | ||
63c3a66f | 9440 | if (tg3_flag(tp, ENABLE_RSS)) { |
bcebcc46 | 9441 | tg3_rss_write_indir_tbl(tp); |
baf8a94a MC |
9442 | |
9443 | /* Setup the "secret" hash key. */ | |
9444 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
9445 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
9446 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
9447 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
9448 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
9449 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
9450 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
9451 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
9452 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
9453 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
9454 | } | |
9455 | ||
1da177e4 | 9456 | tp->rx_mode = RX_MODE_ENABLE; |
63c3a66f | 9457 | if (tg3_flag(tp, 5755_PLUS)) |
af36e6b6 MC |
9458 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
9459 | ||
63c3a66f | 9460 | if (tg3_flag(tp, ENABLE_RSS)) |
baf8a94a MC |
9461 | tp->rx_mode |= RX_MODE_RSS_ENABLE | |
9462 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
9463 | RX_MODE_RSS_IPV6_HASH_EN | | |
9464 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
9465 | RX_MODE_RSS_IPV4_HASH_EN | | |
9466 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
9467 | ||
1da177e4 LT |
9468 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
9469 | udelay(10); | |
9470 | ||
1da177e4 LT |
9471 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
9472 | ||
9473 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 9474 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
9475 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
9476 | udelay(10); | |
9477 | } | |
9478 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
9479 | udelay(10); | |
9480 | ||
f07e9af3 | 9481 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 9482 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 9483 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
9484 | /* Set drive transmission level to 1.2V */ |
9485 | /* only if the signal pre-emphasis bit is not set */ | |
9486 | val = tr32(MAC_SERDES_CFG); | |
9487 | val &= 0xfffff000; | |
9488 | val |= 0x880; | |
9489 | tw32(MAC_SERDES_CFG, val); | |
9490 | } | |
9491 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
9492 | tw32(MAC_SERDES_CFG, 0x616000); | |
9493 | } | |
9494 | ||
9495 | /* Prevent chip from dropping frames when flow control | |
9496 | * is enabled. | |
9497 | */ | |
55086ad9 | 9498 | if (tg3_flag(tp, 57765_CLASS)) |
666bc831 MC |
9499 | val = 1; |
9500 | else | |
9501 | val = 2; | |
9502 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
9503 | |
9504 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 9505 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 | 9506 | /* Use hardware link auto-negotiation */ |
63c3a66f | 9507 | tg3_flag_set(tp, HW_AUTONEG); |
1da177e4 LT |
9508 | } |
9509 | ||
f07e9af3 | 9510 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
6ff6f81d | 9511 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
d4d2c558 MC |
9512 | u32 tmp; |
9513 | ||
9514 | tmp = tr32(SERDES_RX_CTRL); | |
9515 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
9516 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
9517 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
9518 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
9519 | } | |
9520 | ||
63c3a66f | 9521 | if (!tg3_flag(tp, USE_PHYLIB)) { |
c6700ce2 | 9522 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
80096068 | 9523 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; |
1da177e4 | 9524 | |
dd477003 MC |
9525 | err = tg3_setup_phy(tp, 0); |
9526 | if (err) | |
9527 | return err; | |
1da177e4 | 9528 | |
f07e9af3 MC |
9529 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
9530 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
9531 | u32 tmp; |
9532 | ||
9533 | /* Clear CRC stats. */ | |
9534 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
9535 | tg3_writephy(tp, MII_TG3_TEST1, | |
9536 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9537 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 9538 | } |
1da177e4 LT |
9539 | } |
9540 | } | |
9541 | ||
9542 | __tg3_set_rx_mode(tp->dev); | |
9543 | ||
9544 | /* Initialize receive rules. */ | |
9545 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
9546 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
9547 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
9548 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
9549 | ||
63c3a66f | 9550 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) |
1da177e4 LT |
9551 | limit = 8; |
9552 | else | |
9553 | limit = 16; | |
63c3a66f | 9554 | if (tg3_flag(tp, ENABLE_ASF)) |
1da177e4 LT |
9555 | limit -= 4; |
9556 | switch (limit) { | |
9557 | case 16: | |
9558 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
9559 | case 15: | |
9560 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
9561 | case 14: | |
9562 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
9563 | case 13: | |
9564 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
9565 | case 12: | |
9566 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
9567 | case 11: | |
9568 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
9569 | case 10: | |
9570 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
9571 | case 9: | |
9572 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
9573 | case 8: | |
9574 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
9575 | case 7: | |
9576 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
9577 | case 6: | |
9578 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
9579 | case 5: | |
9580 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
9581 | case 4: | |
9582 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
9583 | case 3: | |
9584 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
9585 | case 2: | |
9586 | case 1: | |
9587 | ||
9588 | default: | |
9589 | break; | |
855e1111 | 9590 | } |
1da177e4 | 9591 | |
63c3a66f | 9592 | if (tg3_flag(tp, ENABLE_APE)) |
9ce768ea MC |
9593 | /* Write our heartbeat update interval to APE. */ |
9594 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
9595 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 9596 | |
1da177e4 LT |
9597 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
9598 | ||
1da177e4 LT |
9599 | return 0; |
9600 | } | |
9601 | ||
9602 | /* Called at device open time to get the chip ready for | |
9603 | * packet processing. Invoked with tp->lock held. | |
9604 | */ | |
8e7a22e3 | 9605 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 9606 | { |
1da177e4 LT |
9607 | tg3_switch_clocks(tp); |
9608 | ||
9609 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
9610 | ||
2f751b67 | 9611 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
9612 | } |
9613 | ||
aed93e0b MC |
9614 | static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir) |
9615 | { | |
9616 | int i; | |
9617 | ||
9618 | for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) { | |
9619 | u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN; | |
9620 | ||
9621 | tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len); | |
9622 | off += len; | |
9623 | ||
9624 | if (ocir->signature != TG3_OCIR_SIG_MAGIC || | |
9625 | !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE)) | |
9626 | memset(ocir, 0, TG3_OCIR_LEN); | |
9627 | } | |
9628 | } | |
9629 | ||
9630 | /* sysfs attributes for hwmon */ | |
9631 | static ssize_t tg3_show_temp(struct device *dev, | |
9632 | struct device_attribute *devattr, char *buf) | |
9633 | { | |
9634 | struct pci_dev *pdev = to_pci_dev(dev); | |
9635 | struct net_device *netdev = pci_get_drvdata(pdev); | |
9636 | struct tg3 *tp = netdev_priv(netdev); | |
9637 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
9638 | u32 temperature; | |
9639 | ||
9640 | spin_lock_bh(&tp->lock); | |
9641 | tg3_ape_scratchpad_read(tp, &temperature, attr->index, | |
9642 | sizeof(temperature)); | |
9643 | spin_unlock_bh(&tp->lock); | |
9644 | return sprintf(buf, "%u\n", temperature); | |
9645 | } | |
9646 | ||
9647 | ||
9648 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL, | |
9649 | TG3_TEMP_SENSOR_OFFSET); | |
9650 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL, | |
9651 | TG3_TEMP_CAUTION_OFFSET); | |
9652 | static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL, | |
9653 | TG3_TEMP_MAX_OFFSET); | |
9654 | ||
9655 | static struct attribute *tg3_attributes[] = { | |
9656 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
9657 | &sensor_dev_attr_temp1_crit.dev_attr.attr, | |
9658 | &sensor_dev_attr_temp1_max.dev_attr.attr, | |
9659 | NULL | |
9660 | }; | |
9661 | ||
9662 | static const struct attribute_group tg3_group = { | |
9663 | .attrs = tg3_attributes, | |
9664 | }; | |
9665 | ||
aed93e0b MC |
9666 | static void tg3_hwmon_close(struct tg3 *tp) |
9667 | { | |
aed93e0b MC |
9668 | if (tp->hwmon_dev) { |
9669 | hwmon_device_unregister(tp->hwmon_dev); | |
9670 | tp->hwmon_dev = NULL; | |
9671 | sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group); | |
9672 | } | |
aed93e0b MC |
9673 | } |
9674 | ||
9675 | static void tg3_hwmon_open(struct tg3 *tp) | |
9676 | { | |
aed93e0b MC |
9677 | int i, err; |
9678 | u32 size = 0; | |
9679 | struct pci_dev *pdev = tp->pdev; | |
9680 | struct tg3_ocir ocirs[TG3_SD_NUM_RECS]; | |
9681 | ||
9682 | tg3_sd_scan_scratchpad(tp, ocirs); | |
9683 | ||
9684 | for (i = 0; i < TG3_SD_NUM_RECS; i++) { | |
9685 | if (!ocirs[i].src_data_length) | |
9686 | continue; | |
9687 | ||
9688 | size += ocirs[i].src_hdr_length; | |
9689 | size += ocirs[i].src_data_length; | |
9690 | } | |
9691 | ||
9692 | if (!size) | |
9693 | return; | |
9694 | ||
9695 | /* Register hwmon sysfs hooks */ | |
9696 | err = sysfs_create_group(&pdev->dev.kobj, &tg3_group); | |
9697 | if (err) { | |
9698 | dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n"); | |
9699 | return; | |
9700 | } | |
9701 | ||
9702 | tp->hwmon_dev = hwmon_device_register(&pdev->dev); | |
9703 | if (IS_ERR(tp->hwmon_dev)) { | |
9704 | tp->hwmon_dev = NULL; | |
9705 | dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); | |
9706 | sysfs_remove_group(&pdev->dev.kobj, &tg3_group); | |
9707 | } | |
aed93e0b MC |
9708 | } |
9709 | ||
9710 | ||
1da177e4 LT |
9711 | #define TG3_STAT_ADD32(PSTAT, REG) \ |
9712 | do { u32 __val = tr32(REG); \ | |
9713 | (PSTAT)->low += __val; \ | |
9714 | if ((PSTAT)->low < __val) \ | |
9715 | (PSTAT)->high += 1; \ | |
9716 | } while (0) | |
9717 | ||
9718 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
9719 | { | |
9720 | struct tg3_hw_stats *sp = tp->hw_stats; | |
9721 | ||
f4a46d1f | 9722 | if (!tp->link_up) |
1da177e4 LT |
9723 | return; |
9724 | ||
9725 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
9726 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
9727 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
9728 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
9729 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
9730 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
9731 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
9732 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
9733 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
9734 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
9735 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
9736 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
9737 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
091f0ea3 MC |
9738 | if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) && |
9739 | (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + | |
9740 | sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { | |
9741 | u32 val; | |
9742 | ||
9743 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); | |
9744 | val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA; | |
9745 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); | |
9746 | tg3_flag_clear(tp, 5719_RDMA_BUG); | |
9747 | } | |
1da177e4 LT |
9748 | |
9749 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
9750 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
9751 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
9752 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
9753 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
9754 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
9755 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
9756 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
9757 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
9758 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
9759 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
9760 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
9761 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
9762 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
9763 | |
9764 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
310050fa MC |
9765 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
9766 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && | |
9767 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { | |
4d958473 MC |
9768 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); |
9769 | } else { | |
9770 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
9771 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
9772 | if (val) { | |
9773 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
9774 | sp->rx_discards.low += val; | |
9775 | if (sp->rx_discards.low < val) | |
9776 | sp->rx_discards.high += 1; | |
9777 | } | |
9778 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
9779 | } | |
463d305b | 9780 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
1da177e4 LT |
9781 | } |
9782 | ||
0e6cf6a9 MC |
9783 | static void tg3_chk_missed_msi(struct tg3 *tp) |
9784 | { | |
9785 | u32 i; | |
9786 | ||
9787 | for (i = 0; i < tp->irq_cnt; i++) { | |
9788 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9789 | ||
9790 | if (tg3_has_work(tnapi)) { | |
9791 | if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && | |
9792 | tnapi->last_tx_cons == tnapi->tx_cons) { | |
9793 | if (tnapi->chk_msi_cnt < 1) { | |
9794 | tnapi->chk_msi_cnt++; | |
9795 | return; | |
9796 | } | |
7f230735 | 9797 | tg3_msi(0, tnapi); |
0e6cf6a9 MC |
9798 | } |
9799 | } | |
9800 | tnapi->chk_msi_cnt = 0; | |
9801 | tnapi->last_rx_cons = tnapi->rx_rcb_ptr; | |
9802 | tnapi->last_tx_cons = tnapi->tx_cons; | |
9803 | } | |
9804 | } | |
9805 | ||
1da177e4 LT |
9806 | static void tg3_timer(unsigned long __opaque) |
9807 | { | |
9808 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 9809 | |
5b190624 | 9810 | if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) |
f475f163 MC |
9811 | goto restart_timer; |
9812 | ||
f47c11ee | 9813 | spin_lock(&tp->lock); |
1da177e4 | 9814 | |
0e6cf6a9 | 9815 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
55086ad9 | 9816 | tg3_flag(tp, 57765_CLASS)) |
0e6cf6a9 MC |
9817 | tg3_chk_missed_msi(tp); |
9818 | ||
63c3a66f | 9819 | if (!tg3_flag(tp, TAGGED_STATUS)) { |
fac9b83e DM |
9820 | /* All of this garbage is because when using non-tagged |
9821 | * IRQ status the mailbox/status_block protocol the chip | |
9822 | * uses with the cpu is race prone. | |
9823 | */ | |
898a56f8 | 9824 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
9825 | tw32(GRC_LOCAL_CTRL, |
9826 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
9827 | } else { | |
9828 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 9829 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 9830 | } |
1da177e4 | 9831 | |
fac9b83e | 9832 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
f47c11ee | 9833 | spin_unlock(&tp->lock); |
db219973 | 9834 | tg3_reset_task_schedule(tp); |
5b190624 | 9835 | goto restart_timer; |
fac9b83e | 9836 | } |
1da177e4 LT |
9837 | } |
9838 | ||
1da177e4 LT |
9839 | /* This part only runs once per second. */ |
9840 | if (!--tp->timer_counter) { | |
63c3a66f | 9841 | if (tg3_flag(tp, 5705_PLUS)) |
fac9b83e DM |
9842 | tg3_periodic_fetch_stats(tp); |
9843 | ||
b0c5943f MC |
9844 | if (tp->setlpicnt && !--tp->setlpicnt) |
9845 | tg3_phy_eee_enable(tp); | |
52b02d04 | 9846 | |
63c3a66f | 9847 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
1da177e4 LT |
9848 | u32 mac_stat; |
9849 | int phy_event; | |
9850 | ||
9851 | mac_stat = tr32(MAC_STATUS); | |
9852 | ||
9853 | phy_event = 0; | |
f07e9af3 | 9854 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
9855 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
9856 | phy_event = 1; | |
9857 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
9858 | phy_event = 1; | |
9859 | ||
9860 | if (phy_event) | |
9861 | tg3_setup_phy(tp, 0); | |
63c3a66f | 9862 | } else if (tg3_flag(tp, POLL_SERDES)) { |
1da177e4 LT |
9863 | u32 mac_stat = tr32(MAC_STATUS); |
9864 | int need_setup = 0; | |
9865 | ||
f4a46d1f | 9866 | if (tp->link_up && |
1da177e4 LT |
9867 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { |
9868 | need_setup = 1; | |
9869 | } | |
f4a46d1f | 9870 | if (!tp->link_up && |
1da177e4 LT |
9871 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
9872 | MAC_STATUS_SIGNAL_DET))) { | |
9873 | need_setup = 1; | |
9874 | } | |
9875 | if (need_setup) { | |
3d3ebe74 MC |
9876 | if (!tp->serdes_counter) { |
9877 | tw32_f(MAC_MODE, | |
9878 | (tp->mac_mode & | |
9879 | ~MAC_MODE_PORT_MODE_MASK)); | |
9880 | udelay(40); | |
9881 | tw32_f(MAC_MODE, tp->mac_mode); | |
9882 | udelay(40); | |
9883 | } | |
1da177e4 LT |
9884 | tg3_setup_phy(tp, 0); |
9885 | } | |
f07e9af3 | 9886 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
63c3a66f | 9887 | tg3_flag(tp, 5780_CLASS)) { |
747e8f8b | 9888 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 9889 | } |
1da177e4 LT |
9890 | |
9891 | tp->timer_counter = tp->timer_multiplier; | |
9892 | } | |
9893 | ||
130b8e4d MC |
9894 | /* Heartbeat is only sent once every 2 seconds. |
9895 | * | |
9896 | * The heartbeat is to tell the ASF firmware that the host | |
9897 | * driver is still alive. In the event that the OS crashes, | |
9898 | * ASF needs to reset the hardware to free up the FIFO space | |
9899 | * that may be filled with rx packets destined for the host. | |
9900 | * If the FIFO is full, ASF will no longer function properly. | |
9901 | * | |
9902 | * Unintended resets have been reported on real time kernels | |
9903 | * where the timer doesn't run on time. Netpoll will also have | |
9904 | * same problem. | |
9905 | * | |
9906 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
9907 | * to check the ring condition when the heartbeat is expiring | |
9908 | * before doing the reset. This will prevent most unintended | |
9909 | * resets. | |
9910 | */ | |
1da177e4 | 9911 | if (!--tp->asf_counter) { |
63c3a66f | 9912 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
7c5026aa MC |
9913 | tg3_wait_for_event_ack(tp); |
9914 | ||
bbadf503 | 9915 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 9916 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 9917 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
9918 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
9919 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
9920 | |
9921 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
9922 | } |
9923 | tp->asf_counter = tp->asf_multiplier; | |
9924 | } | |
9925 | ||
f47c11ee | 9926 | spin_unlock(&tp->lock); |
1da177e4 | 9927 | |
f475f163 | 9928 | restart_timer: |
1da177e4 LT |
9929 | tp->timer.expires = jiffies + tp->timer_offset; |
9930 | add_timer(&tp->timer); | |
9931 | } | |
9932 | ||
21f7638e MC |
9933 | static void __devinit tg3_timer_init(struct tg3 *tp) |
9934 | { | |
9935 | if (tg3_flag(tp, TAGGED_STATUS) && | |
9936 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
9937 | !tg3_flag(tp, 57765_CLASS)) | |
9938 | tp->timer_offset = HZ; | |
9939 | else | |
9940 | tp->timer_offset = HZ / 10; | |
9941 | ||
9942 | BUG_ON(tp->timer_offset > HZ); | |
9943 | ||
9944 | tp->timer_multiplier = (HZ / tp->timer_offset); | |
9945 | tp->asf_multiplier = (HZ / tp->timer_offset) * | |
9946 | TG3_FW_UPDATE_FREQ_SEC; | |
9947 | ||
9948 | init_timer(&tp->timer); | |
9949 | tp->timer.data = (unsigned long) tp; | |
9950 | tp->timer.function = tg3_timer; | |
9951 | } | |
9952 | ||
9953 | static void tg3_timer_start(struct tg3 *tp) | |
9954 | { | |
9955 | tp->asf_counter = tp->asf_multiplier; | |
9956 | tp->timer_counter = tp->timer_multiplier; | |
9957 | ||
9958 | tp->timer.expires = jiffies + tp->timer_offset; | |
9959 | add_timer(&tp->timer); | |
9960 | } | |
9961 | ||
9962 | static void tg3_timer_stop(struct tg3 *tp) | |
9963 | { | |
9964 | del_timer_sync(&tp->timer); | |
9965 | } | |
9966 | ||
9967 | /* Restart hardware after configuration changes, self-test, etc. | |
9968 | * Invoked with tp->lock held. | |
9969 | */ | |
9970 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
9971 | __releases(tp->lock) | |
9972 | __acquires(tp->lock) | |
9973 | { | |
9974 | int err; | |
9975 | ||
9976 | err = tg3_init_hw(tp, reset_phy); | |
9977 | if (err) { | |
9978 | netdev_err(tp->dev, | |
9979 | "Failed to re-initialize device, aborting\n"); | |
9980 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9981 | tg3_full_unlock(tp); | |
9982 | tg3_timer_stop(tp); | |
9983 | tp->irq_sync = 0; | |
9984 | tg3_napi_enable(tp); | |
9985 | dev_close(tp->dev); | |
9986 | tg3_full_lock(tp, 0); | |
9987 | } | |
9988 | return err; | |
9989 | } | |
9990 | ||
9991 | static void tg3_reset_task(struct work_struct *work) | |
9992 | { | |
9993 | struct tg3 *tp = container_of(work, struct tg3, reset_task); | |
9994 | int err; | |
9995 | ||
9996 | tg3_full_lock(tp, 0); | |
9997 | ||
9998 | if (!netif_running(tp->dev)) { | |
9999 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
10000 | tg3_full_unlock(tp); | |
10001 | return; | |
10002 | } | |
10003 | ||
10004 | tg3_full_unlock(tp); | |
10005 | ||
10006 | tg3_phy_stop(tp); | |
10007 | ||
10008 | tg3_netif_stop(tp); | |
10009 | ||
10010 | tg3_full_lock(tp, 1); | |
10011 | ||
10012 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { | |
10013 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
10014 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
10015 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
10016 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | |
10017 | } | |
10018 | ||
10019 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
10020 | err = tg3_init_hw(tp, 1); | |
10021 | if (err) | |
10022 | goto out; | |
10023 | ||
10024 | tg3_netif_start(tp); | |
10025 | ||
10026 | out: | |
10027 | tg3_full_unlock(tp); | |
10028 | ||
10029 | if (!err) | |
10030 | tg3_phy_start(tp); | |
10031 | ||
10032 | tg3_flag_clear(tp, RESET_TASK_PENDING); | |
10033 | } | |
10034 | ||
4f125f42 | 10035 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 10036 | { |
7d12e780 | 10037 | irq_handler_t fn; |
fcfa0a32 | 10038 | unsigned long flags; |
4f125f42 MC |
10039 | char *name; |
10040 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
10041 | ||
10042 | if (tp->irq_cnt == 1) | |
10043 | name = tp->dev->name; | |
10044 | else { | |
10045 | name = &tnapi->irq_lbl[0]; | |
10046 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
10047 | name[IFNAMSIZ-1] = 0; | |
10048 | } | |
fcfa0a32 | 10049 | |
63c3a66f | 10050 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
fcfa0a32 | 10051 | fn = tg3_msi; |
63c3a66f | 10052 | if (tg3_flag(tp, 1SHOT_MSI)) |
fcfa0a32 | 10053 | fn = tg3_msi_1shot; |
ab392d2d | 10054 | flags = 0; |
fcfa0a32 MC |
10055 | } else { |
10056 | fn = tg3_interrupt; | |
63c3a66f | 10057 | if (tg3_flag(tp, TAGGED_STATUS)) |
fcfa0a32 | 10058 | fn = tg3_interrupt_tagged; |
ab392d2d | 10059 | flags = IRQF_SHARED; |
fcfa0a32 | 10060 | } |
4f125f42 MC |
10061 | |
10062 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
10063 | } |
10064 | ||
7938109f MC |
10065 | static int tg3_test_interrupt(struct tg3 *tp) |
10066 | { | |
09943a18 | 10067 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 10068 | struct net_device *dev = tp->dev; |
b16250e3 | 10069 | int err, i, intr_ok = 0; |
f6eb9b1f | 10070 | u32 val; |
7938109f | 10071 | |
d4bc3927 MC |
10072 | if (!netif_running(dev)) |
10073 | return -ENODEV; | |
10074 | ||
7938109f MC |
10075 | tg3_disable_ints(tp); |
10076 | ||
4f125f42 | 10077 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 10078 | |
f6eb9b1f MC |
10079 | /* |
10080 | * Turn off MSI one shot mode. Otherwise this test has no | |
10081 | * observable way to know whether the interrupt was delivered. | |
10082 | */ | |
3aa1cdf8 | 10083 | if (tg3_flag(tp, 57765_PLUS)) { |
f6eb9b1f MC |
10084 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; |
10085 | tw32(MSGINT_MODE, val); | |
10086 | } | |
10087 | ||
4f125f42 | 10088 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
f274fd9a | 10089 | IRQF_SHARED, dev->name, tnapi); |
7938109f MC |
10090 | if (err) |
10091 | return err; | |
10092 | ||
898a56f8 | 10093 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
10094 | tg3_enable_ints(tp); |
10095 | ||
10096 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 10097 | tnapi->coal_now); |
7938109f MC |
10098 | |
10099 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
10100 | u32 int_mbox, misc_host_ctrl; |
10101 | ||
898a56f8 | 10102 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
10103 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
10104 | ||
10105 | if ((int_mbox != 0) || | |
10106 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
10107 | intr_ok = 1; | |
7938109f | 10108 | break; |
b16250e3 MC |
10109 | } |
10110 | ||
3aa1cdf8 MC |
10111 | if (tg3_flag(tp, 57765_PLUS) && |
10112 | tnapi->hw_status->status_tag != tnapi->last_tag) | |
10113 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
10114 | ||
7938109f MC |
10115 | msleep(10); |
10116 | } | |
10117 | ||
10118 | tg3_disable_ints(tp); | |
10119 | ||
4f125f42 | 10120 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 10121 | |
4f125f42 | 10122 | err = tg3_request_irq(tp, 0); |
7938109f MC |
10123 | |
10124 | if (err) | |
10125 | return err; | |
10126 | ||
f6eb9b1f MC |
10127 | if (intr_ok) { |
10128 | /* Reenable MSI one shot mode. */ | |
5b39de91 | 10129 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { |
f6eb9b1f MC |
10130 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; |
10131 | tw32(MSGINT_MODE, val); | |
10132 | } | |
7938109f | 10133 | return 0; |
f6eb9b1f | 10134 | } |
7938109f MC |
10135 | |
10136 | return -EIO; | |
10137 | } | |
10138 | ||
10139 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
10140 | * successfully restored | |
10141 | */ | |
10142 | static int tg3_test_msi(struct tg3 *tp) | |
10143 | { | |
7938109f MC |
10144 | int err; |
10145 | u16 pci_cmd; | |
10146 | ||
63c3a66f | 10147 | if (!tg3_flag(tp, USING_MSI)) |
7938109f MC |
10148 | return 0; |
10149 | ||
10150 | /* Turn off SERR reporting in case MSI terminates with Master | |
10151 | * Abort. | |
10152 | */ | |
10153 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
10154 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
10155 | pci_cmd & ~PCI_COMMAND_SERR); | |
10156 | ||
10157 | err = tg3_test_interrupt(tp); | |
10158 | ||
10159 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
10160 | ||
10161 | if (!err) | |
10162 | return 0; | |
10163 | ||
10164 | /* other failures */ | |
10165 | if (err != -EIO) | |
10166 | return err; | |
10167 | ||
10168 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
10169 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
10170 | "to INTx mode. Please report this failure to the PCI " | |
10171 | "maintainer and include system chipset information\n"); | |
7938109f | 10172 | |
4f125f42 | 10173 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 10174 | |
7938109f MC |
10175 | pci_disable_msi(tp->pdev); |
10176 | ||
63c3a66f | 10177 | tg3_flag_clear(tp, USING_MSI); |
dc8bf1b1 | 10178 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 10179 | |
4f125f42 | 10180 | err = tg3_request_irq(tp, 0); |
7938109f MC |
10181 | if (err) |
10182 | return err; | |
10183 | ||
10184 | /* Need to reset the chip because the MSI cycle may have terminated | |
10185 | * with Master Abort. | |
10186 | */ | |
f47c11ee | 10187 | tg3_full_lock(tp, 1); |
7938109f | 10188 | |
944d980e | 10189 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 10190 | err = tg3_init_hw(tp, 1); |
7938109f | 10191 | |
f47c11ee | 10192 | tg3_full_unlock(tp); |
7938109f MC |
10193 | |
10194 | if (err) | |
4f125f42 | 10195 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
10196 | |
10197 | return err; | |
10198 | } | |
10199 | ||
9e9fd12d MC |
10200 | static int tg3_request_firmware(struct tg3 *tp) |
10201 | { | |
10202 | const __be32 *fw_data; | |
10203 | ||
10204 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
10205 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
10206 | tp->fw_needed); | |
9e9fd12d MC |
10207 | return -ENOENT; |
10208 | } | |
10209 | ||
10210 | fw_data = (void *)tp->fw->data; | |
10211 | ||
10212 | /* Firmware blob starts with version numbers, followed by | |
10213 | * start address and _full_ length including BSS sections | |
10214 | * (which must be longer than the actual data, of course | |
10215 | */ | |
10216 | ||
10217 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
10218 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
10219 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
10220 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
10221 | release_firmware(tp->fw); |
10222 | tp->fw = NULL; | |
10223 | return -EINVAL; | |
10224 | } | |
10225 | ||
10226 | /* We no longer need firmware; we have it. */ | |
10227 | tp->fw_needed = NULL; | |
10228 | return 0; | |
10229 | } | |
10230 | ||
9102426a | 10231 | static u32 tg3_irq_count(struct tg3 *tp) |
679563f4 | 10232 | { |
9102426a | 10233 | u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); |
679563f4 | 10234 | |
9102426a | 10235 | if (irq_cnt > 1) { |
c3b5003b MC |
10236 | /* We want as many rx rings enabled as there are cpus. |
10237 | * In multiqueue MSI-X mode, the first MSI-X vector | |
10238 | * only deals with link interrupts, etc, so we add | |
10239 | * one to the number of vectors we are requesting. | |
10240 | */ | |
9102426a | 10241 | irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); |
c3b5003b | 10242 | } |
679563f4 | 10243 | |
9102426a MC |
10244 | return irq_cnt; |
10245 | } | |
10246 | ||
10247 | static bool tg3_enable_msix(struct tg3 *tp) | |
10248 | { | |
10249 | int i, rc; | |
86449944 | 10250 | struct msix_entry msix_ent[TG3_IRQ_MAX_VECS]; |
9102426a | 10251 | |
0968169c MC |
10252 | tp->txq_cnt = tp->txq_req; |
10253 | tp->rxq_cnt = tp->rxq_req; | |
10254 | if (!tp->rxq_cnt) | |
10255 | tp->rxq_cnt = netif_get_num_default_rss_queues(); | |
9102426a MC |
10256 | if (tp->rxq_cnt > tp->rxq_max) |
10257 | tp->rxq_cnt = tp->rxq_max; | |
cf6d6ea6 MC |
10258 | |
10259 | /* Disable multiple TX rings by default. Simple round-robin hardware | |
10260 | * scheduling of the TX rings can cause starvation of rings with | |
10261 | * small packets when other rings have TSO or jumbo packets. | |
10262 | */ | |
10263 | if (!tp->txq_req) | |
10264 | tp->txq_cnt = 1; | |
9102426a MC |
10265 | |
10266 | tp->irq_cnt = tg3_irq_count(tp); | |
10267 | ||
679563f4 MC |
10268 | for (i = 0; i < tp->irq_max; i++) { |
10269 | msix_ent[i].entry = i; | |
10270 | msix_ent[i].vector = 0; | |
10271 | } | |
10272 | ||
10273 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
10274 | if (rc < 0) { |
10275 | return false; | |
10276 | } else if (rc != 0) { | |
679563f4 MC |
10277 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
10278 | return false; | |
05dbe005 JP |
10279 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
10280 | tp->irq_cnt, rc); | |
679563f4 | 10281 | tp->irq_cnt = rc; |
49a359e3 | 10282 | tp->rxq_cnt = max(rc - 1, 1); |
9102426a MC |
10283 | if (tp->txq_cnt) |
10284 | tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); | |
679563f4 MC |
10285 | } |
10286 | ||
10287 | for (i = 0; i < tp->irq_max; i++) | |
10288 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
10289 | ||
49a359e3 | 10290 | if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { |
2ddaad39 BH |
10291 | pci_disable_msix(tp->pdev); |
10292 | return false; | |
10293 | } | |
b92b9040 | 10294 | |
9102426a MC |
10295 | if (tp->irq_cnt == 1) |
10296 | return true; | |
d78b59f5 | 10297 | |
9102426a MC |
10298 | tg3_flag_set(tp, ENABLE_RSS); |
10299 | ||
10300 | if (tp->txq_cnt > 1) | |
10301 | tg3_flag_set(tp, ENABLE_TSS); | |
10302 | ||
10303 | netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); | |
2430b031 | 10304 | |
679563f4 MC |
10305 | return true; |
10306 | } | |
10307 | ||
07b0173c MC |
10308 | static void tg3_ints_init(struct tg3 *tp) |
10309 | { | |
63c3a66f JP |
10310 | if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && |
10311 | !tg3_flag(tp, TAGGED_STATUS)) { | |
07b0173c MC |
10312 | /* All MSI supporting chips should support tagged |
10313 | * status. Assert that this is the case. | |
10314 | */ | |
5129c3a3 MC |
10315 | netdev_warn(tp->dev, |
10316 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 10317 | goto defcfg; |
07b0173c | 10318 | } |
4f125f42 | 10319 | |
63c3a66f JP |
10320 | if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) |
10321 | tg3_flag_set(tp, USING_MSIX); | |
10322 | else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) | |
10323 | tg3_flag_set(tp, USING_MSI); | |
679563f4 | 10324 | |
63c3a66f | 10325 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
679563f4 | 10326 | u32 msi_mode = tr32(MSGINT_MODE); |
63c3a66f | 10327 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) |
baf8a94a | 10328 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
5b39de91 MC |
10329 | if (!tg3_flag(tp, 1SHOT_MSI)) |
10330 | msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE; | |
679563f4 MC |
10331 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
10332 | } | |
10333 | defcfg: | |
63c3a66f | 10334 | if (!tg3_flag(tp, USING_MSIX)) { |
679563f4 MC |
10335 | tp->irq_cnt = 1; |
10336 | tp->napi[0].irq_vec = tp->pdev->irq; | |
49a359e3 MC |
10337 | } |
10338 | ||
10339 | if (tp->irq_cnt == 1) { | |
10340 | tp->txq_cnt = 1; | |
10341 | tp->rxq_cnt = 1; | |
2ddaad39 | 10342 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 10343 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 10344 | } |
07b0173c MC |
10345 | } |
10346 | ||
10347 | static void tg3_ints_fini(struct tg3 *tp) | |
10348 | { | |
63c3a66f | 10349 | if (tg3_flag(tp, USING_MSIX)) |
679563f4 | 10350 | pci_disable_msix(tp->pdev); |
63c3a66f | 10351 | else if (tg3_flag(tp, USING_MSI)) |
679563f4 | 10352 | pci_disable_msi(tp->pdev); |
63c3a66f JP |
10353 | tg3_flag_clear(tp, USING_MSI); |
10354 | tg3_flag_clear(tp, USING_MSIX); | |
10355 | tg3_flag_clear(tp, ENABLE_RSS); | |
10356 | tg3_flag_clear(tp, ENABLE_TSS); | |
07b0173c MC |
10357 | } |
10358 | ||
d8f4cd38 | 10359 | static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq) |
1da177e4 | 10360 | { |
d8f4cd38 | 10361 | struct net_device *dev = tp->dev; |
4f125f42 | 10362 | int i, err; |
1da177e4 | 10363 | |
679563f4 MC |
10364 | /* |
10365 | * Setup interrupts first so we know how | |
10366 | * many NAPI resources to allocate | |
10367 | */ | |
10368 | tg3_ints_init(tp); | |
10369 | ||
90415477 | 10370 | tg3_rss_check_indir_tbl(tp); |
bcebcc46 | 10371 | |
1da177e4 LT |
10372 | /* The placement of this call is tied |
10373 | * to the setup and use of Host TX descriptors. | |
10374 | */ | |
10375 | err = tg3_alloc_consistent(tp); | |
10376 | if (err) | |
679563f4 | 10377 | goto err_out1; |
88b06bc2 | 10378 | |
66cfd1bd MC |
10379 | tg3_napi_init(tp); |
10380 | ||
fed97810 | 10381 | tg3_napi_enable(tp); |
1da177e4 | 10382 | |
4f125f42 MC |
10383 | for (i = 0; i < tp->irq_cnt; i++) { |
10384 | struct tg3_napi *tnapi = &tp->napi[i]; | |
10385 | err = tg3_request_irq(tp, i); | |
10386 | if (err) { | |
5bc09186 MC |
10387 | for (i--; i >= 0; i--) { |
10388 | tnapi = &tp->napi[i]; | |
4f125f42 | 10389 | free_irq(tnapi->irq_vec, tnapi); |
5bc09186 MC |
10390 | } |
10391 | goto err_out2; | |
4f125f42 MC |
10392 | } |
10393 | } | |
1da177e4 | 10394 | |
f47c11ee | 10395 | tg3_full_lock(tp, 0); |
1da177e4 | 10396 | |
d8f4cd38 | 10397 | err = tg3_init_hw(tp, reset_phy); |
1da177e4 | 10398 | if (err) { |
944d980e | 10399 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 10400 | tg3_free_rings(tp); |
1da177e4 LT |
10401 | } |
10402 | ||
f47c11ee | 10403 | tg3_full_unlock(tp); |
1da177e4 | 10404 | |
07b0173c | 10405 | if (err) |
679563f4 | 10406 | goto err_out3; |
1da177e4 | 10407 | |
d8f4cd38 | 10408 | if (test_irq && tg3_flag(tp, USING_MSI)) { |
7938109f | 10409 | err = tg3_test_msi(tp); |
fac9b83e | 10410 | |
7938109f | 10411 | if (err) { |
f47c11ee | 10412 | tg3_full_lock(tp, 0); |
944d980e | 10413 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 10414 | tg3_free_rings(tp); |
f47c11ee | 10415 | tg3_full_unlock(tp); |
7938109f | 10416 | |
679563f4 | 10417 | goto err_out2; |
7938109f | 10418 | } |
fcfa0a32 | 10419 | |
63c3a66f | 10420 | if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
f6eb9b1f | 10421 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 10422 | |
f6eb9b1f MC |
10423 | tw32(PCIE_TRANSACTION_CFG, |
10424 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 10425 | } |
7938109f MC |
10426 | } |
10427 | ||
b02fd9e3 MC |
10428 | tg3_phy_start(tp); |
10429 | ||
aed93e0b MC |
10430 | tg3_hwmon_open(tp); |
10431 | ||
f47c11ee | 10432 | tg3_full_lock(tp, 0); |
1da177e4 | 10433 | |
21f7638e | 10434 | tg3_timer_start(tp); |
63c3a66f | 10435 | tg3_flag_set(tp, INIT_COMPLETE); |
1da177e4 LT |
10436 | tg3_enable_ints(tp); |
10437 | ||
f47c11ee | 10438 | tg3_full_unlock(tp); |
1da177e4 | 10439 | |
fe5f5787 | 10440 | netif_tx_start_all_queues(dev); |
1da177e4 | 10441 | |
06c03c02 MB |
10442 | /* |
10443 | * Reset loopback feature if it was turned on while the device was down | |
10444 | * make sure that it's installed properly now. | |
10445 | */ | |
10446 | if (dev->features & NETIF_F_LOOPBACK) | |
10447 | tg3_set_loopback(dev, dev->features); | |
10448 | ||
1da177e4 | 10449 | return 0; |
07b0173c | 10450 | |
679563f4 | 10451 | err_out3: |
4f125f42 MC |
10452 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
10453 | struct tg3_napi *tnapi = &tp->napi[i]; | |
10454 | free_irq(tnapi->irq_vec, tnapi); | |
10455 | } | |
07b0173c | 10456 | |
679563f4 | 10457 | err_out2: |
fed97810 | 10458 | tg3_napi_disable(tp); |
66cfd1bd | 10459 | tg3_napi_fini(tp); |
07b0173c | 10460 | tg3_free_consistent(tp); |
679563f4 MC |
10461 | |
10462 | err_out1: | |
10463 | tg3_ints_fini(tp); | |
d8f4cd38 | 10464 | |
07b0173c | 10465 | return err; |
1da177e4 LT |
10466 | } |
10467 | ||
65138594 | 10468 | static void tg3_stop(struct tg3 *tp) |
1da177e4 | 10469 | { |
4f125f42 | 10470 | int i; |
1da177e4 | 10471 | |
db219973 | 10472 | tg3_reset_task_cancel(tp); |
bd473da3 | 10473 | tg3_netif_stop(tp); |
1da177e4 | 10474 | |
21f7638e | 10475 | tg3_timer_stop(tp); |
1da177e4 | 10476 | |
aed93e0b MC |
10477 | tg3_hwmon_close(tp); |
10478 | ||
24bb4fb6 MC |
10479 | tg3_phy_stop(tp); |
10480 | ||
f47c11ee | 10481 | tg3_full_lock(tp, 1); |
1da177e4 LT |
10482 | |
10483 | tg3_disable_ints(tp); | |
10484 | ||
944d980e | 10485 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 10486 | tg3_free_rings(tp); |
63c3a66f | 10487 | tg3_flag_clear(tp, INIT_COMPLETE); |
1da177e4 | 10488 | |
f47c11ee | 10489 | tg3_full_unlock(tp); |
1da177e4 | 10490 | |
4f125f42 MC |
10491 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
10492 | struct tg3_napi *tnapi = &tp->napi[i]; | |
10493 | free_irq(tnapi->irq_vec, tnapi); | |
10494 | } | |
07b0173c MC |
10495 | |
10496 | tg3_ints_fini(tp); | |
1da177e4 | 10497 | |
66cfd1bd MC |
10498 | tg3_napi_fini(tp); |
10499 | ||
1da177e4 | 10500 | tg3_free_consistent(tp); |
65138594 MC |
10501 | } |
10502 | ||
d8f4cd38 MC |
10503 | static int tg3_open(struct net_device *dev) |
10504 | { | |
10505 | struct tg3 *tp = netdev_priv(dev); | |
10506 | int err; | |
10507 | ||
10508 | if (tp->fw_needed) { | |
10509 | err = tg3_request_firmware(tp); | |
10510 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
10511 | if (err) | |
10512 | return err; | |
10513 | } else if (err) { | |
10514 | netdev_warn(tp->dev, "TSO capability disabled\n"); | |
10515 | tg3_flag_clear(tp, TSO_CAPABLE); | |
10516 | } else if (!tg3_flag(tp, TSO_CAPABLE)) { | |
10517 | netdev_notice(tp->dev, "TSO capability restored\n"); | |
10518 | tg3_flag_set(tp, TSO_CAPABLE); | |
10519 | } | |
10520 | } | |
10521 | ||
f4a46d1f | 10522 | tg3_carrier_off(tp); |
d8f4cd38 MC |
10523 | |
10524 | err = tg3_power_up(tp); | |
10525 | if (err) | |
10526 | return err; | |
10527 | ||
10528 | tg3_full_lock(tp, 0); | |
10529 | ||
10530 | tg3_disable_ints(tp); | |
10531 | tg3_flag_clear(tp, INIT_COMPLETE); | |
10532 | ||
10533 | tg3_full_unlock(tp); | |
10534 | ||
10535 | err = tg3_start(tp, true, true); | |
10536 | if (err) { | |
10537 | tg3_frob_aux_power(tp, false); | |
10538 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
10539 | } | |
07b0173c | 10540 | return err; |
1da177e4 LT |
10541 | } |
10542 | ||
1da177e4 LT |
10543 | static int tg3_close(struct net_device *dev) |
10544 | { | |
10545 | struct tg3 *tp = netdev_priv(dev); | |
10546 | ||
65138594 | 10547 | tg3_stop(tp); |
1da177e4 | 10548 | |
92feeabf MC |
10549 | /* Clear stats across close / open calls */ |
10550 | memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev)); | |
10551 | memset(&tp->estats_prev, 0, sizeof(tp->estats_prev)); | |
1da177e4 | 10552 | |
c866b7ea | 10553 | tg3_power_down(tp); |
bc1c7567 | 10554 | |
f4a46d1f | 10555 | tg3_carrier_off(tp); |
bc1c7567 | 10556 | |
1da177e4 LT |
10557 | return 0; |
10558 | } | |
10559 | ||
511d2224 | 10560 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
10561 | { |
10562 | return ((u64)val->high << 32) | ((u64)val->low); | |
10563 | } | |
10564 | ||
65ec698d | 10565 | static u64 tg3_calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
10566 | { |
10567 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
10568 | ||
f07e9af3 | 10569 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
10570 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
10571 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
10572 | u32 val; |
10573 | ||
569a5df8 MC |
10574 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
10575 | tg3_writephy(tp, MII_TG3_TEST1, | |
10576 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 10577 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
10578 | } else |
10579 | val = 0; | |
1da177e4 LT |
10580 | |
10581 | tp->phy_crc_errors += val; | |
10582 | ||
10583 | return tp->phy_crc_errors; | |
10584 | } | |
10585 | ||
10586 | return get_stat64(&hw_stats->rx_fcs_errors); | |
10587 | } | |
10588 | ||
10589 | #define ESTAT_ADD(member) \ | |
10590 | estats->member = old_estats->member + \ | |
511d2224 | 10591 | get_stat64(&hw_stats->member) |
1da177e4 | 10592 | |
65ec698d | 10593 | static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats) |
1da177e4 | 10594 | { |
1da177e4 LT |
10595 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; |
10596 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
10597 | ||
1da177e4 LT |
10598 | ESTAT_ADD(rx_octets); |
10599 | ESTAT_ADD(rx_fragments); | |
10600 | ESTAT_ADD(rx_ucast_packets); | |
10601 | ESTAT_ADD(rx_mcast_packets); | |
10602 | ESTAT_ADD(rx_bcast_packets); | |
10603 | ESTAT_ADD(rx_fcs_errors); | |
10604 | ESTAT_ADD(rx_align_errors); | |
10605 | ESTAT_ADD(rx_xon_pause_rcvd); | |
10606 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
10607 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
10608 | ESTAT_ADD(rx_xoff_entered); | |
10609 | ESTAT_ADD(rx_frame_too_long_errors); | |
10610 | ESTAT_ADD(rx_jabbers); | |
10611 | ESTAT_ADD(rx_undersize_packets); | |
10612 | ESTAT_ADD(rx_in_length_errors); | |
10613 | ESTAT_ADD(rx_out_length_errors); | |
10614 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
10615 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
10616 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
10617 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
10618 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
10619 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
10620 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
10621 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
10622 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
10623 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
10624 | ||
10625 | ESTAT_ADD(tx_octets); | |
10626 | ESTAT_ADD(tx_collisions); | |
10627 | ESTAT_ADD(tx_xon_sent); | |
10628 | ESTAT_ADD(tx_xoff_sent); | |
10629 | ESTAT_ADD(tx_flow_control); | |
10630 | ESTAT_ADD(tx_mac_errors); | |
10631 | ESTAT_ADD(tx_single_collisions); | |
10632 | ESTAT_ADD(tx_mult_collisions); | |
10633 | ESTAT_ADD(tx_deferred); | |
10634 | ESTAT_ADD(tx_excessive_collisions); | |
10635 | ESTAT_ADD(tx_late_collisions); | |
10636 | ESTAT_ADD(tx_collide_2times); | |
10637 | ESTAT_ADD(tx_collide_3times); | |
10638 | ESTAT_ADD(tx_collide_4times); | |
10639 | ESTAT_ADD(tx_collide_5times); | |
10640 | ESTAT_ADD(tx_collide_6times); | |
10641 | ESTAT_ADD(tx_collide_7times); | |
10642 | ESTAT_ADD(tx_collide_8times); | |
10643 | ESTAT_ADD(tx_collide_9times); | |
10644 | ESTAT_ADD(tx_collide_10times); | |
10645 | ESTAT_ADD(tx_collide_11times); | |
10646 | ESTAT_ADD(tx_collide_12times); | |
10647 | ESTAT_ADD(tx_collide_13times); | |
10648 | ESTAT_ADD(tx_collide_14times); | |
10649 | ESTAT_ADD(tx_collide_15times); | |
10650 | ESTAT_ADD(tx_ucast_packets); | |
10651 | ESTAT_ADD(tx_mcast_packets); | |
10652 | ESTAT_ADD(tx_bcast_packets); | |
10653 | ESTAT_ADD(tx_carrier_sense_errors); | |
10654 | ESTAT_ADD(tx_discards); | |
10655 | ESTAT_ADD(tx_errors); | |
10656 | ||
10657 | ESTAT_ADD(dma_writeq_full); | |
10658 | ESTAT_ADD(dma_write_prioq_full); | |
10659 | ESTAT_ADD(rxbds_empty); | |
10660 | ESTAT_ADD(rx_discards); | |
10661 | ESTAT_ADD(rx_errors); | |
10662 | ESTAT_ADD(rx_threshold_hit); | |
10663 | ||
10664 | ESTAT_ADD(dma_readq_full); | |
10665 | ESTAT_ADD(dma_read_prioq_full); | |
10666 | ESTAT_ADD(tx_comp_queue_full); | |
10667 | ||
10668 | ESTAT_ADD(ring_set_send_prod_index); | |
10669 | ESTAT_ADD(ring_status_update); | |
10670 | ESTAT_ADD(nic_irqs); | |
10671 | ESTAT_ADD(nic_avoided_irqs); | |
10672 | ESTAT_ADD(nic_tx_threshold_hit); | |
10673 | ||
4452d099 | 10674 | ESTAT_ADD(mbuf_lwm_thresh_hit); |
1da177e4 LT |
10675 | } |
10676 | ||
65ec698d | 10677 | static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats) |
1da177e4 | 10678 | { |
511d2224 | 10679 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
10680 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
10681 | ||
1da177e4 LT |
10682 | stats->rx_packets = old_stats->rx_packets + |
10683 | get_stat64(&hw_stats->rx_ucast_packets) + | |
10684 | get_stat64(&hw_stats->rx_mcast_packets) + | |
10685 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 10686 | |
1da177e4 LT |
10687 | stats->tx_packets = old_stats->tx_packets + |
10688 | get_stat64(&hw_stats->tx_ucast_packets) + | |
10689 | get_stat64(&hw_stats->tx_mcast_packets) + | |
10690 | get_stat64(&hw_stats->tx_bcast_packets); | |
10691 | ||
10692 | stats->rx_bytes = old_stats->rx_bytes + | |
10693 | get_stat64(&hw_stats->rx_octets); | |
10694 | stats->tx_bytes = old_stats->tx_bytes + | |
10695 | get_stat64(&hw_stats->tx_octets); | |
10696 | ||
10697 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 10698 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
10699 | stats->tx_errors = old_stats->tx_errors + |
10700 | get_stat64(&hw_stats->tx_errors) + | |
10701 | get_stat64(&hw_stats->tx_mac_errors) + | |
10702 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
10703 | get_stat64(&hw_stats->tx_discards); | |
10704 | ||
10705 | stats->multicast = old_stats->multicast + | |
10706 | get_stat64(&hw_stats->rx_mcast_packets); | |
10707 | stats->collisions = old_stats->collisions + | |
10708 | get_stat64(&hw_stats->tx_collisions); | |
10709 | ||
10710 | stats->rx_length_errors = old_stats->rx_length_errors + | |
10711 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
10712 | get_stat64(&hw_stats->rx_undersize_packets); | |
10713 | ||
10714 | stats->rx_over_errors = old_stats->rx_over_errors + | |
10715 | get_stat64(&hw_stats->rxbds_empty); | |
10716 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
10717 | get_stat64(&hw_stats->rx_align_errors); | |
10718 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
10719 | get_stat64(&hw_stats->tx_discards); | |
10720 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
10721 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
10722 | ||
10723 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
65ec698d | 10724 | tg3_calc_crc_errors(tp); |
1da177e4 | 10725 | |
4f63b877 JL |
10726 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
10727 | get_stat64(&hw_stats->rx_discards); | |
10728 | ||
b0057c51 | 10729 | stats->rx_dropped = tp->rx_dropped; |
48855432 | 10730 | stats->tx_dropped = tp->tx_dropped; |
1da177e4 LT |
10731 | } |
10732 | ||
1da177e4 LT |
10733 | static int tg3_get_regs_len(struct net_device *dev) |
10734 | { | |
97bd8e49 | 10735 | return TG3_REG_BLK_SIZE; |
1da177e4 LT |
10736 | } |
10737 | ||
10738 | static void tg3_get_regs(struct net_device *dev, | |
10739 | struct ethtool_regs *regs, void *_p) | |
10740 | { | |
1da177e4 | 10741 | struct tg3 *tp = netdev_priv(dev); |
1da177e4 LT |
10742 | |
10743 | regs->version = 0; | |
10744 | ||
97bd8e49 | 10745 | memset(_p, 0, TG3_REG_BLK_SIZE); |
1da177e4 | 10746 | |
80096068 | 10747 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10748 | return; |
10749 | ||
f47c11ee | 10750 | tg3_full_lock(tp, 0); |
1da177e4 | 10751 | |
97bd8e49 | 10752 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
1da177e4 | 10753 | |
f47c11ee | 10754 | tg3_full_unlock(tp); |
1da177e4 LT |
10755 | } |
10756 | ||
10757 | static int tg3_get_eeprom_len(struct net_device *dev) | |
10758 | { | |
10759 | struct tg3 *tp = netdev_priv(dev); | |
10760 | ||
10761 | return tp->nvram_size; | |
10762 | } | |
10763 | ||
1da177e4 LT |
10764 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
10765 | { | |
10766 | struct tg3 *tp = netdev_priv(dev); | |
10767 | int ret; | |
10768 | u8 *pd; | |
b9fc7dc5 | 10769 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 10770 | __be32 val; |
1da177e4 | 10771 | |
63c3a66f | 10772 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
10773 | return -EINVAL; |
10774 | ||
80096068 | 10775 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10776 | return -EAGAIN; |
10777 | ||
1da177e4 LT |
10778 | offset = eeprom->offset; |
10779 | len = eeprom->len; | |
10780 | eeprom->len = 0; | |
10781 | ||
10782 | eeprom->magic = TG3_EEPROM_MAGIC; | |
10783 | ||
10784 | if (offset & 3) { | |
10785 | /* adjustments to start on required 4 byte boundary */ | |
10786 | b_offset = offset & 3; | |
10787 | b_count = 4 - b_offset; | |
10788 | if (b_count > len) { | |
10789 | /* i.e. offset=1 len=2 */ | |
10790 | b_count = len; | |
10791 | } | |
a9dc529d | 10792 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
10793 | if (ret) |
10794 | return ret; | |
be98da6a | 10795 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
10796 | len -= b_count; |
10797 | offset += b_count; | |
c6cdf436 | 10798 | eeprom->len += b_count; |
1da177e4 LT |
10799 | } |
10800 | ||
25985edc | 10801 | /* read bytes up to the last 4 byte boundary */ |
1da177e4 LT |
10802 | pd = &data[eeprom->len]; |
10803 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 10804 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
10805 | if (ret) { |
10806 | eeprom->len += i; | |
10807 | return ret; | |
10808 | } | |
1da177e4 LT |
10809 | memcpy(pd + i, &val, 4); |
10810 | } | |
10811 | eeprom->len += i; | |
10812 | ||
10813 | if (len & 3) { | |
10814 | /* read last bytes not ending on 4 byte boundary */ | |
10815 | pd = &data[eeprom->len]; | |
10816 | b_count = len & 3; | |
10817 | b_offset = offset + len - b_count; | |
a9dc529d | 10818 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
10819 | if (ret) |
10820 | return ret; | |
b9fc7dc5 | 10821 | memcpy(pd, &val, b_count); |
1da177e4 LT |
10822 | eeprom->len += b_count; |
10823 | } | |
10824 | return 0; | |
10825 | } | |
10826 | ||
1da177e4 LT |
10827 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
10828 | { | |
10829 | struct tg3 *tp = netdev_priv(dev); | |
10830 | int ret; | |
b9fc7dc5 | 10831 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 10832 | u8 *buf; |
a9dc529d | 10833 | __be32 start, end; |
1da177e4 | 10834 | |
80096068 | 10835 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
10836 | return -EAGAIN; |
10837 | ||
63c3a66f | 10838 | if (tg3_flag(tp, NO_NVRAM) || |
df259d8c | 10839 | eeprom->magic != TG3_EEPROM_MAGIC) |
1da177e4 LT |
10840 | return -EINVAL; |
10841 | ||
10842 | offset = eeprom->offset; | |
10843 | len = eeprom->len; | |
10844 | ||
10845 | if ((b_offset = (offset & 3))) { | |
10846 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 10847 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
10848 | if (ret) |
10849 | return ret; | |
1da177e4 LT |
10850 | len += b_offset; |
10851 | offset &= ~3; | |
1c8594b4 MC |
10852 | if (len < 4) |
10853 | len = 4; | |
1da177e4 LT |
10854 | } |
10855 | ||
10856 | odd_len = 0; | |
1c8594b4 | 10857 | if (len & 3) { |
1da177e4 LT |
10858 | /* adjustments to end on required 4 byte boundary */ |
10859 | odd_len = 1; | |
10860 | len = (len + 3) & ~3; | |
a9dc529d | 10861 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
10862 | if (ret) |
10863 | return ret; | |
1da177e4 LT |
10864 | } |
10865 | ||
10866 | buf = data; | |
10867 | if (b_offset || odd_len) { | |
10868 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 10869 | if (!buf) |
1da177e4 LT |
10870 | return -ENOMEM; |
10871 | if (b_offset) | |
10872 | memcpy(buf, &start, 4); | |
10873 | if (odd_len) | |
10874 | memcpy(buf+len-4, &end, 4); | |
10875 | memcpy(buf + b_offset, data, eeprom->len); | |
10876 | } | |
10877 | ||
10878 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
10879 | ||
10880 | if (buf != data) | |
10881 | kfree(buf); | |
10882 | ||
10883 | return ret; | |
10884 | } | |
10885 | ||
10886 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
10887 | { | |
b02fd9e3 MC |
10888 | struct tg3 *tp = netdev_priv(dev); |
10889 | ||
63c3a66f | 10890 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10891 | struct phy_device *phydev; |
f07e9af3 | 10892 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10893 | return -EAGAIN; |
3f0e3ad7 MC |
10894 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10895 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 10896 | } |
6aa20a22 | 10897 | |
1da177e4 LT |
10898 | cmd->supported = (SUPPORTED_Autoneg); |
10899 | ||
f07e9af3 | 10900 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
10901 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
10902 | SUPPORTED_1000baseT_Full); | |
10903 | ||
f07e9af3 | 10904 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
10905 | cmd->supported |= (SUPPORTED_100baseT_Half | |
10906 | SUPPORTED_100baseT_Full | | |
10907 | SUPPORTED_10baseT_Half | | |
10908 | SUPPORTED_10baseT_Full | | |
3bebab59 | 10909 | SUPPORTED_TP); |
ef348144 KK |
10910 | cmd->port = PORT_TP; |
10911 | } else { | |
1da177e4 | 10912 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
10913 | cmd->port = PORT_FIBRE; |
10914 | } | |
6aa20a22 | 10915 | |
1da177e4 | 10916 | cmd->advertising = tp->link_config.advertising; |
5bb09778 MC |
10917 | if (tg3_flag(tp, PAUSE_AUTONEG)) { |
10918 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) { | |
10919 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10920 | cmd->advertising |= ADVERTISED_Pause; | |
10921 | } else { | |
10922 | cmd->advertising |= ADVERTISED_Pause | | |
10923 | ADVERTISED_Asym_Pause; | |
10924 | } | |
10925 | } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
10926 | cmd->advertising |= ADVERTISED_Asym_Pause; | |
10927 | } | |
10928 | } | |
f4a46d1f | 10929 | if (netif_running(dev) && tp->link_up) { |
70739497 | 10930 | ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); |
1da177e4 | 10931 | cmd->duplex = tp->link_config.active_duplex; |
859edb26 | 10932 | cmd->lp_advertising = tp->link_config.rmt_adv; |
e348c5e7 MC |
10933 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
10934 | if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) | |
10935 | cmd->eth_tp_mdix = ETH_TP_MDI_X; | |
10936 | else | |
10937 | cmd->eth_tp_mdix = ETH_TP_MDI; | |
10938 | } | |
64c22182 | 10939 | } else { |
e740522e MC |
10940 | ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); |
10941 | cmd->duplex = DUPLEX_UNKNOWN; | |
e348c5e7 | 10942 | cmd->eth_tp_mdix = ETH_TP_MDI_INVALID; |
1da177e4 | 10943 | } |
882e9793 | 10944 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 10945 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
10946 | cmd->autoneg = tp->link_config.autoneg; |
10947 | cmd->maxtxpkt = 0; | |
10948 | cmd->maxrxpkt = 0; | |
10949 | return 0; | |
10950 | } | |
6aa20a22 | 10951 | |
1da177e4 LT |
10952 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
10953 | { | |
10954 | struct tg3 *tp = netdev_priv(dev); | |
25db0338 | 10955 | u32 speed = ethtool_cmd_speed(cmd); |
6aa20a22 | 10956 | |
63c3a66f | 10957 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 10958 | struct phy_device *phydev; |
f07e9af3 | 10959 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10960 | return -EAGAIN; |
3f0e3ad7 MC |
10961 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10962 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
10963 | } |
10964 | ||
7e5856bd MC |
10965 | if (cmd->autoneg != AUTONEG_ENABLE && |
10966 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 10967 | return -EINVAL; |
7e5856bd MC |
10968 | |
10969 | if (cmd->autoneg == AUTONEG_DISABLE && | |
10970 | cmd->duplex != DUPLEX_FULL && | |
10971 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 10972 | return -EINVAL; |
1da177e4 | 10973 | |
7e5856bd MC |
10974 | if (cmd->autoneg == AUTONEG_ENABLE) { |
10975 | u32 mask = ADVERTISED_Autoneg | | |
10976 | ADVERTISED_Pause | | |
10977 | ADVERTISED_Asym_Pause; | |
10978 | ||
f07e9af3 | 10979 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
10980 | mask |= ADVERTISED_1000baseT_Half | |
10981 | ADVERTISED_1000baseT_Full; | |
10982 | ||
f07e9af3 | 10983 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
10984 | mask |= ADVERTISED_100baseT_Half | |
10985 | ADVERTISED_100baseT_Full | | |
10986 | ADVERTISED_10baseT_Half | | |
10987 | ADVERTISED_10baseT_Full | | |
10988 | ADVERTISED_TP; | |
10989 | else | |
10990 | mask |= ADVERTISED_FIBRE; | |
10991 | ||
10992 | if (cmd->advertising & ~mask) | |
10993 | return -EINVAL; | |
10994 | ||
10995 | mask &= (ADVERTISED_1000baseT_Half | | |
10996 | ADVERTISED_1000baseT_Full | | |
10997 | ADVERTISED_100baseT_Half | | |
10998 | ADVERTISED_100baseT_Full | | |
10999 | ADVERTISED_10baseT_Half | | |
11000 | ADVERTISED_10baseT_Full); | |
11001 | ||
11002 | cmd->advertising &= mask; | |
11003 | } else { | |
f07e9af3 | 11004 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
25db0338 | 11005 | if (speed != SPEED_1000) |
7e5856bd MC |
11006 | return -EINVAL; |
11007 | ||
11008 | if (cmd->duplex != DUPLEX_FULL) | |
11009 | return -EINVAL; | |
11010 | } else { | |
25db0338 DD |
11011 | if (speed != SPEED_100 && |
11012 | speed != SPEED_10) | |
7e5856bd MC |
11013 | return -EINVAL; |
11014 | } | |
11015 | } | |
11016 | ||
f47c11ee | 11017 | tg3_full_lock(tp, 0); |
1da177e4 LT |
11018 | |
11019 | tp->link_config.autoneg = cmd->autoneg; | |
11020 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
11021 | tp->link_config.advertising = (cmd->advertising | |
11022 | ADVERTISED_Autoneg); | |
e740522e MC |
11023 | tp->link_config.speed = SPEED_UNKNOWN; |
11024 | tp->link_config.duplex = DUPLEX_UNKNOWN; | |
1da177e4 LT |
11025 | } else { |
11026 | tp->link_config.advertising = 0; | |
25db0338 | 11027 | tp->link_config.speed = speed; |
1da177e4 | 11028 | tp->link_config.duplex = cmd->duplex; |
b02fd9e3 | 11029 | } |
6aa20a22 | 11030 | |
1da177e4 LT |
11031 | if (netif_running(dev)) |
11032 | tg3_setup_phy(tp, 1); | |
11033 | ||
f47c11ee | 11034 | tg3_full_unlock(tp); |
6aa20a22 | 11035 | |
1da177e4 LT |
11036 | return 0; |
11037 | } | |
6aa20a22 | 11038 | |
1da177e4 LT |
11039 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
11040 | { | |
11041 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 11042 | |
68aad78c RJ |
11043 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
11044 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); | |
11045 | strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); | |
11046 | strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); | |
1da177e4 | 11047 | } |
6aa20a22 | 11048 | |
1da177e4 LT |
11049 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
11050 | { | |
11051 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 11052 | |
63c3a66f | 11053 | if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) |
a85feb8c GZ |
11054 | wol->supported = WAKE_MAGIC; |
11055 | else | |
11056 | wol->supported = 0; | |
1da177e4 | 11057 | wol->wolopts = 0; |
63c3a66f | 11058 | if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) |
1da177e4 LT |
11059 | wol->wolopts = WAKE_MAGIC; |
11060 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
11061 | } | |
6aa20a22 | 11062 | |
1da177e4 LT |
11063 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
11064 | { | |
11065 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 11066 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 11067 | |
1da177e4 LT |
11068 | if (wol->wolopts & ~WAKE_MAGIC) |
11069 | return -EINVAL; | |
11070 | if ((wol->wolopts & WAKE_MAGIC) && | |
63c3a66f | 11071 | !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 11072 | return -EINVAL; |
6aa20a22 | 11073 | |
f2dc0d18 RW |
11074 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
11075 | ||
f47c11ee | 11076 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 11077 | if (device_may_wakeup(dp)) |
63c3a66f | 11078 | tg3_flag_set(tp, WOL_ENABLE); |
f2dc0d18 | 11079 | else |
63c3a66f | 11080 | tg3_flag_clear(tp, WOL_ENABLE); |
f47c11ee | 11081 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 11082 | |
1da177e4 LT |
11083 | return 0; |
11084 | } | |
6aa20a22 | 11085 | |
1da177e4 LT |
11086 | static u32 tg3_get_msglevel(struct net_device *dev) |
11087 | { | |
11088 | struct tg3 *tp = netdev_priv(dev); | |
11089 | return tp->msg_enable; | |
11090 | } | |
6aa20a22 | 11091 | |
1da177e4 LT |
11092 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
11093 | { | |
11094 | struct tg3 *tp = netdev_priv(dev); | |
11095 | tp->msg_enable = value; | |
11096 | } | |
6aa20a22 | 11097 | |
1da177e4 LT |
11098 | static int tg3_nway_reset(struct net_device *dev) |
11099 | { | |
11100 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 11101 | int r; |
6aa20a22 | 11102 | |
1da177e4 LT |
11103 | if (!netif_running(dev)) |
11104 | return -EAGAIN; | |
11105 | ||
f07e9af3 | 11106 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
11107 | return -EINVAL; |
11108 | ||
63c3a66f | 11109 | if (tg3_flag(tp, USE_PHYLIB)) { |
f07e9af3 | 11110 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11111 | return -EAGAIN; |
3f0e3ad7 | 11112 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
11113 | } else { |
11114 | u32 bmcr; | |
11115 | ||
11116 | spin_lock_bh(&tp->lock); | |
11117 | r = -EINVAL; | |
11118 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
11119 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
11120 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 11121 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
11122 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
11123 | BMCR_ANENABLE); | |
11124 | r = 0; | |
11125 | } | |
11126 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 11127 | } |
6aa20a22 | 11128 | |
1da177e4 LT |
11129 | return r; |
11130 | } | |
6aa20a22 | 11131 | |
1da177e4 LT |
11132 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
11133 | { | |
11134 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 11135 | |
2c49a44d | 11136 | ering->rx_max_pending = tp->rx_std_ring_mask; |
63c3a66f | 11137 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
2c49a44d | 11138 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
11139 | else |
11140 | ering->rx_jumbo_max_pending = 0; | |
11141 | ||
11142 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
11143 | |
11144 | ering->rx_pending = tp->rx_pending; | |
63c3a66f | 11145 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
4f81c32b MC |
11146 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; |
11147 | else | |
11148 | ering->rx_jumbo_pending = 0; | |
11149 | ||
f3f3f27e | 11150 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 11151 | } |
6aa20a22 | 11152 | |
1da177e4 LT |
11153 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
11154 | { | |
11155 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 11156 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 11157 | |
2c49a44d MC |
11158 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
11159 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
11160 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
11161 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
63c3a66f | 11162 | (tg3_flag(tp, TSO_BUG) && |
bc3a9254 | 11163 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 11164 | return -EINVAL; |
6aa20a22 | 11165 | |
bbe832c0 | 11166 | if (netif_running(dev)) { |
b02fd9e3 | 11167 | tg3_phy_stop(tp); |
1da177e4 | 11168 | tg3_netif_stop(tp); |
bbe832c0 MC |
11169 | irq_sync = 1; |
11170 | } | |
1da177e4 | 11171 | |
bbe832c0 | 11172 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 11173 | |
1da177e4 LT |
11174 | tp->rx_pending = ering->rx_pending; |
11175 | ||
63c3a66f | 11176 | if (tg3_flag(tp, MAX_RXPEND_64) && |
1da177e4 LT |
11177 | tp->rx_pending > 63) |
11178 | tp->rx_pending = 63; | |
11179 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 11180 | |
6fd45cb8 | 11181 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 11182 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
11183 | |
11184 | if (netif_running(dev)) { | |
944d980e | 11185 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
11186 | err = tg3_restart_hw(tp, 1); |
11187 | if (!err) | |
11188 | tg3_netif_start(tp); | |
1da177e4 LT |
11189 | } |
11190 | ||
f47c11ee | 11191 | tg3_full_unlock(tp); |
6aa20a22 | 11192 | |
b02fd9e3 MC |
11193 | if (irq_sync && !err) |
11194 | tg3_phy_start(tp); | |
11195 | ||
b9ec6c1b | 11196 | return err; |
1da177e4 | 11197 | } |
6aa20a22 | 11198 | |
1da177e4 LT |
11199 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
11200 | { | |
11201 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 11202 | |
63c3a66f | 11203 | epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); |
8d018621 | 11204 | |
4a2db503 | 11205 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
11206 | epause->rx_pause = 1; |
11207 | else | |
11208 | epause->rx_pause = 0; | |
11209 | ||
4a2db503 | 11210 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
11211 | epause->tx_pause = 1; |
11212 | else | |
11213 | epause->tx_pause = 0; | |
1da177e4 | 11214 | } |
6aa20a22 | 11215 | |
1da177e4 LT |
11216 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
11217 | { | |
11218 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 11219 | int err = 0; |
6aa20a22 | 11220 | |
63c3a66f | 11221 | if (tg3_flag(tp, USE_PHYLIB)) { |
2712168f MC |
11222 | u32 newadv; |
11223 | struct phy_device *phydev; | |
1da177e4 | 11224 | |
2712168f | 11225 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 11226 | |
2712168f MC |
11227 | if (!(phydev->supported & SUPPORTED_Pause) || |
11228 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 11229 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 11230 | return -EINVAL; |
1da177e4 | 11231 | |
2712168f MC |
11232 | tp->link_config.flowctrl = 0; |
11233 | if (epause->rx_pause) { | |
11234 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
11235 | ||
11236 | if (epause->tx_pause) { | |
11237 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
11238 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 11239 | } else |
2712168f MC |
11240 | newadv = ADVERTISED_Pause | |
11241 | ADVERTISED_Asym_Pause; | |
11242 | } else if (epause->tx_pause) { | |
11243 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
11244 | newadv = ADVERTISED_Asym_Pause; | |
11245 | } else | |
11246 | newadv = 0; | |
11247 | ||
11248 | if (epause->autoneg) | |
63c3a66f | 11249 | tg3_flag_set(tp, PAUSE_AUTONEG); |
2712168f | 11250 | else |
63c3a66f | 11251 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
2712168f | 11252 | |
f07e9af3 | 11253 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
11254 | u32 oldadv = phydev->advertising & |
11255 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
11256 | if (oldadv != newadv) { | |
11257 | phydev->advertising &= | |
11258 | ~(ADVERTISED_Pause | | |
11259 | ADVERTISED_Asym_Pause); | |
11260 | phydev->advertising |= newadv; | |
11261 | if (phydev->autoneg) { | |
11262 | /* | |
11263 | * Always renegotiate the link to | |
11264 | * inform our link partner of our | |
11265 | * flow control settings, even if the | |
11266 | * flow control is forced. Let | |
11267 | * tg3_adjust_link() do the final | |
11268 | * flow control setup. | |
11269 | */ | |
11270 | return phy_start_aneg(phydev); | |
b02fd9e3 | 11271 | } |
b02fd9e3 | 11272 | } |
b02fd9e3 | 11273 | |
2712168f | 11274 | if (!epause->autoneg) |
b02fd9e3 | 11275 | tg3_setup_flow_control(tp, 0, 0); |
2712168f | 11276 | } else { |
c6700ce2 | 11277 | tp->link_config.advertising &= |
2712168f MC |
11278 | ~(ADVERTISED_Pause | |
11279 | ADVERTISED_Asym_Pause); | |
c6700ce2 | 11280 | tp->link_config.advertising |= newadv; |
b02fd9e3 MC |
11281 | } |
11282 | } else { | |
11283 | int irq_sync = 0; | |
11284 | ||
11285 | if (netif_running(dev)) { | |
11286 | tg3_netif_stop(tp); | |
11287 | irq_sync = 1; | |
11288 | } | |
11289 | ||
11290 | tg3_full_lock(tp, irq_sync); | |
11291 | ||
11292 | if (epause->autoneg) | |
63c3a66f | 11293 | tg3_flag_set(tp, PAUSE_AUTONEG); |
b02fd9e3 | 11294 | else |
63c3a66f | 11295 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
b02fd9e3 | 11296 | if (epause->rx_pause) |
e18ce346 | 11297 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 11298 | else |
e18ce346 | 11299 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 11300 | if (epause->tx_pause) |
e18ce346 | 11301 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 11302 | else |
e18ce346 | 11303 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
11304 | |
11305 | if (netif_running(dev)) { | |
11306 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
11307 | err = tg3_restart_hw(tp, 1); | |
11308 | if (!err) | |
11309 | tg3_netif_start(tp); | |
11310 | } | |
11311 | ||
11312 | tg3_full_unlock(tp); | |
11313 | } | |
6aa20a22 | 11314 | |
b9ec6c1b | 11315 | return err; |
1da177e4 | 11316 | } |
6aa20a22 | 11317 | |
de6f31eb | 11318 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 11319 | { |
b9f2c044 JG |
11320 | switch (sset) { |
11321 | case ETH_SS_TEST: | |
11322 | return TG3_NUM_TEST; | |
11323 | case ETH_SS_STATS: | |
11324 | return TG3_NUM_STATS; | |
11325 | default: | |
11326 | return -EOPNOTSUPP; | |
11327 | } | |
4cafd3f5 MC |
11328 | } |
11329 | ||
90415477 MC |
11330 | static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, |
11331 | u32 *rules __always_unused) | |
11332 | { | |
11333 | struct tg3 *tp = netdev_priv(dev); | |
11334 | ||
11335 | if (!tg3_flag(tp, SUPPORT_MSIX)) | |
11336 | return -EOPNOTSUPP; | |
11337 | ||
11338 | switch (info->cmd) { | |
11339 | case ETHTOOL_GRXRINGS: | |
11340 | if (netif_running(tp->dev)) | |
9102426a | 11341 | info->data = tp->rxq_cnt; |
90415477 MC |
11342 | else { |
11343 | info->data = num_online_cpus(); | |
9102426a MC |
11344 | if (info->data > TG3_RSS_MAX_NUM_QS) |
11345 | info->data = TG3_RSS_MAX_NUM_QS; | |
90415477 MC |
11346 | } |
11347 | ||
11348 | /* The first interrupt vector only | |
11349 | * handles link interrupts. | |
11350 | */ | |
11351 | info->data -= 1; | |
11352 | return 0; | |
11353 | ||
11354 | default: | |
11355 | return -EOPNOTSUPP; | |
11356 | } | |
11357 | } | |
11358 | ||
11359 | static u32 tg3_get_rxfh_indir_size(struct net_device *dev) | |
11360 | { | |
11361 | u32 size = 0; | |
11362 | struct tg3 *tp = netdev_priv(dev); | |
11363 | ||
11364 | if (tg3_flag(tp, SUPPORT_MSIX)) | |
11365 | size = TG3_RSS_INDIR_TBL_SIZE; | |
11366 | ||
11367 | return size; | |
11368 | } | |
11369 | ||
11370 | static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir) | |
11371 | { | |
11372 | struct tg3 *tp = netdev_priv(dev); | |
11373 | int i; | |
11374 | ||
11375 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) | |
11376 | indir[i] = tp->rss_ind_tbl[i]; | |
11377 | ||
11378 | return 0; | |
11379 | } | |
11380 | ||
11381 | static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir) | |
11382 | { | |
11383 | struct tg3 *tp = netdev_priv(dev); | |
11384 | size_t i; | |
11385 | ||
11386 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) | |
11387 | tp->rss_ind_tbl[i] = indir[i]; | |
11388 | ||
11389 | if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) | |
11390 | return 0; | |
11391 | ||
11392 | /* It is legal to write the indirection | |
11393 | * table while the device is running. | |
11394 | */ | |
11395 | tg3_full_lock(tp, 0); | |
11396 | tg3_rss_write_indir_tbl(tp); | |
11397 | tg3_full_unlock(tp); | |
11398 | ||
11399 | return 0; | |
11400 | } | |
11401 | ||
0968169c MC |
11402 | static void tg3_get_channels(struct net_device *dev, |
11403 | struct ethtool_channels *channel) | |
11404 | { | |
11405 | struct tg3 *tp = netdev_priv(dev); | |
11406 | u32 deflt_qs = netif_get_num_default_rss_queues(); | |
11407 | ||
11408 | channel->max_rx = tp->rxq_max; | |
11409 | channel->max_tx = tp->txq_max; | |
11410 | ||
11411 | if (netif_running(dev)) { | |
11412 | channel->rx_count = tp->rxq_cnt; | |
11413 | channel->tx_count = tp->txq_cnt; | |
11414 | } else { | |
11415 | if (tp->rxq_req) | |
11416 | channel->rx_count = tp->rxq_req; | |
11417 | else | |
11418 | channel->rx_count = min(deflt_qs, tp->rxq_max); | |
11419 | ||
11420 | if (tp->txq_req) | |
11421 | channel->tx_count = tp->txq_req; | |
11422 | else | |
11423 | channel->tx_count = min(deflt_qs, tp->txq_max); | |
11424 | } | |
11425 | } | |
11426 | ||
11427 | static int tg3_set_channels(struct net_device *dev, | |
11428 | struct ethtool_channels *channel) | |
11429 | { | |
11430 | struct tg3 *tp = netdev_priv(dev); | |
11431 | ||
11432 | if (!tg3_flag(tp, SUPPORT_MSIX)) | |
11433 | return -EOPNOTSUPP; | |
11434 | ||
11435 | if (channel->rx_count > tp->rxq_max || | |
11436 | channel->tx_count > tp->txq_max) | |
11437 | return -EINVAL; | |
11438 | ||
11439 | tp->rxq_req = channel->rx_count; | |
11440 | tp->txq_req = channel->tx_count; | |
11441 | ||
11442 | if (!netif_running(dev)) | |
11443 | return 0; | |
11444 | ||
11445 | tg3_stop(tp); | |
11446 | ||
f4a46d1f | 11447 | tg3_carrier_off(tp); |
0968169c MC |
11448 | |
11449 | tg3_start(tp, true, false); | |
11450 | ||
11451 | return 0; | |
11452 | } | |
11453 | ||
de6f31eb | 11454 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
11455 | { |
11456 | switch (stringset) { | |
11457 | case ETH_SS_STATS: | |
11458 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
11459 | break; | |
4cafd3f5 MC |
11460 | case ETH_SS_TEST: |
11461 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
11462 | break; | |
1da177e4 LT |
11463 | default: |
11464 | WARN_ON(1); /* we need a WARN() */ | |
11465 | break; | |
11466 | } | |
11467 | } | |
11468 | ||
81b8709c | 11469 | static int tg3_set_phys_id(struct net_device *dev, |
11470 | enum ethtool_phys_id_state state) | |
4009a93d MC |
11471 | { |
11472 | struct tg3 *tp = netdev_priv(dev); | |
4009a93d MC |
11473 | |
11474 | if (!netif_running(tp->dev)) | |
11475 | return -EAGAIN; | |
11476 | ||
81b8709c | 11477 | switch (state) { |
11478 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 11479 | return 1; /* cycle on/off once per second */ |
4009a93d | 11480 | |
81b8709c | 11481 | case ETHTOOL_ID_ON: |
11482 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
11483 | LED_CTRL_1000MBPS_ON | | |
11484 | LED_CTRL_100MBPS_ON | | |
11485 | LED_CTRL_10MBPS_ON | | |
11486 | LED_CTRL_TRAFFIC_OVERRIDE | | |
11487 | LED_CTRL_TRAFFIC_BLINK | | |
11488 | LED_CTRL_TRAFFIC_LED); | |
11489 | break; | |
6aa20a22 | 11490 | |
81b8709c | 11491 | case ETHTOOL_ID_OFF: |
11492 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
11493 | LED_CTRL_TRAFFIC_OVERRIDE); | |
11494 | break; | |
4009a93d | 11495 | |
81b8709c | 11496 | case ETHTOOL_ID_INACTIVE: |
11497 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
11498 | break; | |
4009a93d | 11499 | } |
81b8709c | 11500 | |
4009a93d MC |
11501 | return 0; |
11502 | } | |
11503 | ||
de6f31eb | 11504 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
11505 | struct ethtool_stats *estats, u64 *tmp_stats) |
11506 | { | |
11507 | struct tg3 *tp = netdev_priv(dev); | |
0e6c9da3 | 11508 | |
b546e46f MC |
11509 | if (tp->hw_stats) |
11510 | tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); | |
11511 | else | |
11512 | memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats)); | |
1da177e4 LT |
11513 | } |
11514 | ||
535a490e | 11515 | static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen) |
c3e94500 MC |
11516 | { |
11517 | int i; | |
11518 | __be32 *buf; | |
11519 | u32 offset = 0, len = 0; | |
11520 | u32 magic, val; | |
11521 | ||
63c3a66f | 11522 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) |
c3e94500 MC |
11523 | return NULL; |
11524 | ||
11525 | if (magic == TG3_EEPROM_MAGIC) { | |
11526 | for (offset = TG3_NVM_DIR_START; | |
11527 | offset < TG3_NVM_DIR_END; | |
11528 | offset += TG3_NVM_DIRENT_SIZE) { | |
11529 | if (tg3_nvram_read(tp, offset, &val)) | |
11530 | return NULL; | |
11531 | ||
11532 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
11533 | TG3_NVM_DIRTYPE_EXTVPD) | |
11534 | break; | |
11535 | } | |
11536 | ||
11537 | if (offset != TG3_NVM_DIR_END) { | |
11538 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
11539 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
11540 | return NULL; | |
11541 | ||
11542 | offset = tg3_nvram_logical_addr(tp, offset); | |
11543 | } | |
11544 | } | |
11545 | ||
11546 | if (!offset || !len) { | |
11547 | offset = TG3_NVM_VPD_OFF; | |
11548 | len = TG3_NVM_VPD_LEN; | |
11549 | } | |
11550 | ||
11551 | buf = kmalloc(len, GFP_KERNEL); | |
11552 | if (buf == NULL) | |
11553 | return NULL; | |
11554 | ||
11555 | if (magic == TG3_EEPROM_MAGIC) { | |
11556 | for (i = 0; i < len; i += 4) { | |
11557 | /* The data is in little-endian format in NVRAM. | |
11558 | * Use the big-endian read routines to preserve | |
11559 | * the byte order as it exists in NVRAM. | |
11560 | */ | |
11561 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
11562 | goto error; | |
11563 | } | |
11564 | } else { | |
11565 | u8 *ptr; | |
11566 | ssize_t cnt; | |
11567 | unsigned int pos = 0; | |
11568 | ||
11569 | ptr = (u8 *)&buf[0]; | |
11570 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
11571 | cnt = pci_read_vpd(tp->pdev, pos, | |
11572 | len - pos, ptr); | |
11573 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
11574 | cnt = 0; | |
11575 | else if (cnt < 0) | |
11576 | goto error; | |
11577 | } | |
11578 | if (pos != len) | |
11579 | goto error; | |
11580 | } | |
11581 | ||
535a490e MC |
11582 | *vpdlen = len; |
11583 | ||
c3e94500 MC |
11584 | return buf; |
11585 | ||
11586 | error: | |
11587 | kfree(buf); | |
11588 | return NULL; | |
11589 | } | |
11590 | ||
566f86ad | 11591 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
11592 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
11593 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
11594 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
727a6d9f MC |
11595 | #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 |
11596 | #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 | |
bda18faf | 11597 | #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50 |
b16250e3 MC |
11598 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
11599 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
11600 | |
11601 | static int tg3_test_nvram(struct tg3 *tp) | |
11602 | { | |
535a490e | 11603 | u32 csum, magic, len; |
a9dc529d | 11604 | __be32 *buf; |
ab0049b4 | 11605 | int i, j, k, err = 0, size; |
566f86ad | 11606 | |
63c3a66f | 11607 | if (tg3_flag(tp, NO_NVRAM)) |
df259d8c MC |
11608 | return 0; |
11609 | ||
e4f34110 | 11610 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
11611 | return -EIO; |
11612 | ||
1b27777a MC |
11613 | if (magic == TG3_EEPROM_MAGIC) |
11614 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 11615 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
11616 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
11617 | TG3_EEPROM_SB_FORMAT_1) { | |
11618 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
11619 | case TG3_EEPROM_SB_REVISION_0: | |
11620 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
11621 | break; | |
11622 | case TG3_EEPROM_SB_REVISION_2: | |
11623 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
11624 | break; | |
11625 | case TG3_EEPROM_SB_REVISION_3: | |
11626 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
11627 | break; | |
727a6d9f MC |
11628 | case TG3_EEPROM_SB_REVISION_4: |
11629 | size = NVRAM_SELFBOOT_FORMAT1_4_SIZE; | |
11630 | break; | |
11631 | case TG3_EEPROM_SB_REVISION_5: | |
11632 | size = NVRAM_SELFBOOT_FORMAT1_5_SIZE; | |
11633 | break; | |
11634 | case TG3_EEPROM_SB_REVISION_6: | |
11635 | size = NVRAM_SELFBOOT_FORMAT1_6_SIZE; | |
11636 | break; | |
a5767dec | 11637 | default: |
727a6d9f | 11638 | return -EIO; |
a5767dec MC |
11639 | } |
11640 | } else | |
1b27777a | 11641 | return 0; |
b16250e3 MC |
11642 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
11643 | size = NVRAM_SELFBOOT_HW_SIZE; | |
11644 | else | |
1b27777a MC |
11645 | return -EIO; |
11646 | ||
11647 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
11648 | if (buf == NULL) |
11649 | return -ENOMEM; | |
11650 | ||
1b27777a MC |
11651 | err = -EIO; |
11652 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
11653 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
11654 | if (err) | |
566f86ad | 11655 | break; |
566f86ad | 11656 | } |
1b27777a | 11657 | if (i < size) |
566f86ad MC |
11658 | goto out; |
11659 | ||
1b27777a | 11660 | /* Selfboot format */ |
a9dc529d | 11661 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 11662 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 11663 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
11664 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
11665 | ||
b9fc7dc5 | 11666 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
11667 | TG3_EEPROM_SB_REVISION_2) { |
11668 | /* For rev 2, the csum doesn't include the MBA. */ | |
11669 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
11670 | csum8 += buf8[i]; | |
11671 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
11672 | csum8 += buf8[i]; | |
11673 | } else { | |
11674 | for (i = 0; i < size; i++) | |
11675 | csum8 += buf8[i]; | |
11676 | } | |
1b27777a | 11677 | |
ad96b485 AB |
11678 | if (csum8 == 0) { |
11679 | err = 0; | |
11680 | goto out; | |
11681 | } | |
11682 | ||
11683 | err = -EIO; | |
11684 | goto out; | |
1b27777a | 11685 | } |
566f86ad | 11686 | |
b9fc7dc5 | 11687 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
11688 | TG3_EEPROM_MAGIC_HW) { |
11689 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 11690 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 11691 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
11692 | |
11693 | /* Separate the parity bits and the data bytes. */ | |
11694 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
11695 | if ((i == 0) || (i == 8)) { | |
11696 | int l; | |
11697 | u8 msk; | |
11698 | ||
11699 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
11700 | parity[k++] = buf8[i] & msk; | |
11701 | i++; | |
859a5887 | 11702 | } else if (i == 16) { |
b16250e3 MC |
11703 | int l; |
11704 | u8 msk; | |
11705 | ||
11706 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
11707 | parity[k++] = buf8[i] & msk; | |
11708 | i++; | |
11709 | ||
11710 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
11711 | parity[k++] = buf8[i] & msk; | |
11712 | i++; | |
11713 | } | |
11714 | data[j++] = buf8[i]; | |
11715 | } | |
11716 | ||
11717 | err = -EIO; | |
11718 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
11719 | u8 hw8 = hweight8(data[i]); | |
11720 | ||
11721 | if ((hw8 & 0x1) && parity[i]) | |
11722 | goto out; | |
11723 | else if (!(hw8 & 0x1) && !parity[i]) | |
11724 | goto out; | |
11725 | } | |
11726 | err = 0; | |
11727 | goto out; | |
11728 | } | |
11729 | ||
01c3a392 MC |
11730 | err = -EIO; |
11731 | ||
566f86ad MC |
11732 | /* Bootstrap checksum at offset 0x10 */ |
11733 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 11734 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
11735 | goto out; |
11736 | ||
11737 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
11738 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 11739 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 11740 | goto out; |
566f86ad | 11741 | |
c3e94500 MC |
11742 | kfree(buf); |
11743 | ||
535a490e | 11744 | buf = tg3_vpd_readblock(tp, &len); |
c3e94500 MC |
11745 | if (!buf) |
11746 | return -ENOMEM; | |
d4894f3e | 11747 | |
535a490e | 11748 | i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA); |
d4894f3e MC |
11749 | if (i > 0) { |
11750 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
11751 | if (j < 0) | |
11752 | goto out; | |
11753 | ||
535a490e | 11754 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > len) |
d4894f3e MC |
11755 | goto out; |
11756 | ||
11757 | i += PCI_VPD_LRDT_TAG_SIZE; | |
11758 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
11759 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
11760 | if (j > 0) { | |
11761 | u8 csum8 = 0; | |
11762 | ||
11763 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11764 | ||
11765 | for (i = 0; i <= j; i++) | |
11766 | csum8 += ((u8 *)buf)[i]; | |
11767 | ||
11768 | if (csum8) | |
11769 | goto out; | |
11770 | } | |
11771 | } | |
11772 | ||
566f86ad MC |
11773 | err = 0; |
11774 | ||
11775 | out: | |
11776 | kfree(buf); | |
11777 | return err; | |
11778 | } | |
11779 | ||
ca43007a MC |
11780 | #define TG3_SERDES_TIMEOUT_SEC 2 |
11781 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
11782 | ||
11783 | static int tg3_test_link(struct tg3 *tp) | |
11784 | { | |
11785 | int i, max; | |
11786 | ||
11787 | if (!netif_running(tp->dev)) | |
11788 | return -ENODEV; | |
11789 | ||
f07e9af3 | 11790 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
11791 | max = TG3_SERDES_TIMEOUT_SEC; |
11792 | else | |
11793 | max = TG3_COPPER_TIMEOUT_SEC; | |
11794 | ||
11795 | for (i = 0; i < max; i++) { | |
f4a46d1f | 11796 | if (tp->link_up) |
ca43007a MC |
11797 | return 0; |
11798 | ||
11799 | if (msleep_interruptible(1000)) | |
11800 | break; | |
11801 | } | |
11802 | ||
11803 | return -EIO; | |
11804 | } | |
11805 | ||
a71116d1 | 11806 | /* Only test the commonly used registers */ |
30ca3e37 | 11807 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 11808 | { |
b16250e3 | 11809 | int i, is_5705, is_5750; |
a71116d1 MC |
11810 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
11811 | static struct { | |
11812 | u16 offset; | |
11813 | u16 flags; | |
11814 | #define TG3_FL_5705 0x1 | |
11815 | #define TG3_FL_NOT_5705 0x2 | |
11816 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 11817 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
11818 | u32 read_mask; |
11819 | u32 write_mask; | |
11820 | } reg_tbl[] = { | |
11821 | /* MAC Control Registers */ | |
11822 | { MAC_MODE, TG3_FL_NOT_5705, | |
11823 | 0x00000000, 0x00ef6f8c }, | |
11824 | { MAC_MODE, TG3_FL_5705, | |
11825 | 0x00000000, 0x01ef6b8c }, | |
11826 | { MAC_STATUS, TG3_FL_NOT_5705, | |
11827 | 0x03800107, 0x00000000 }, | |
11828 | { MAC_STATUS, TG3_FL_5705, | |
11829 | 0x03800100, 0x00000000 }, | |
11830 | { MAC_ADDR_0_HIGH, 0x0000, | |
11831 | 0x00000000, 0x0000ffff }, | |
11832 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 11833 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
11834 | { MAC_RX_MTU_SIZE, 0x0000, |
11835 | 0x00000000, 0x0000ffff }, | |
11836 | { MAC_TX_MODE, 0x0000, | |
11837 | 0x00000000, 0x00000070 }, | |
11838 | { MAC_TX_LENGTHS, 0x0000, | |
11839 | 0x00000000, 0x00003fff }, | |
11840 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
11841 | 0x00000000, 0x000007fc }, | |
11842 | { MAC_RX_MODE, TG3_FL_5705, | |
11843 | 0x00000000, 0x000007dc }, | |
11844 | { MAC_HASH_REG_0, 0x0000, | |
11845 | 0x00000000, 0xffffffff }, | |
11846 | { MAC_HASH_REG_1, 0x0000, | |
11847 | 0x00000000, 0xffffffff }, | |
11848 | { MAC_HASH_REG_2, 0x0000, | |
11849 | 0x00000000, 0xffffffff }, | |
11850 | { MAC_HASH_REG_3, 0x0000, | |
11851 | 0x00000000, 0xffffffff }, | |
11852 | ||
11853 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
11854 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
11855 | 0x00000000, 0xffffffff }, | |
11856 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
11857 | 0x00000000, 0xffffffff }, | |
11858 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
11859 | 0x00000000, 0x00000003 }, | |
11860 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
11861 | 0x00000000, 0xffffffff }, | |
11862 | { RCVDBDI_STD_BD+0, 0x0000, | |
11863 | 0x00000000, 0xffffffff }, | |
11864 | { RCVDBDI_STD_BD+4, 0x0000, | |
11865 | 0x00000000, 0xffffffff }, | |
11866 | { RCVDBDI_STD_BD+8, 0x0000, | |
11867 | 0x00000000, 0xffff0002 }, | |
11868 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
11869 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 11870 | |
a71116d1 MC |
11871 | /* Receive BD Initiator Control Registers. */ |
11872 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
11873 | 0x00000000, 0xffffffff }, | |
11874 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
11875 | 0x00000000, 0x000003ff }, | |
11876 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
11877 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 11878 | |
a71116d1 MC |
11879 | /* Host Coalescing Control Registers. */ |
11880 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
11881 | 0x00000000, 0x00000004 }, | |
11882 | { HOSTCC_MODE, TG3_FL_5705, | |
11883 | 0x00000000, 0x000000f6 }, | |
11884 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
11885 | 0x00000000, 0xffffffff }, | |
11886 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
11887 | 0x00000000, 0x000003ff }, | |
11888 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
11889 | 0x00000000, 0xffffffff }, | |
11890 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
11891 | 0x00000000, 0x000003ff }, | |
11892 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
11893 | 0x00000000, 0xffffffff }, | |
11894 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11895 | 0x00000000, 0x000000ff }, | |
11896 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
11897 | 0x00000000, 0xffffffff }, | |
11898 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11899 | 0x00000000, 0x000000ff }, | |
11900 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
11901 | 0x00000000, 0xffffffff }, | |
11902 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
11903 | 0x00000000, 0xffffffff }, | |
11904 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
11905 | 0x00000000, 0xffffffff }, | |
11906 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11907 | 0x00000000, 0x000000ff }, | |
11908 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
11909 | 0x00000000, 0xffffffff }, | |
11910 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
11911 | 0x00000000, 0x000000ff }, | |
11912 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
11913 | 0x00000000, 0xffffffff }, | |
11914 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
11915 | 0x00000000, 0xffffffff }, | |
11916 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
11917 | 0x00000000, 0xffffffff }, | |
11918 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
11919 | 0x00000000, 0xffffffff }, | |
11920 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
11921 | 0x00000000, 0xffffffff }, | |
11922 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
11923 | 0xffffffff, 0x00000000 }, | |
11924 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
11925 | 0xffffffff, 0x00000000 }, | |
11926 | ||
11927 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 11928 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 11929 | 0x00000000, 0x007fff80 }, |
b16250e3 | 11930 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
11931 | 0x00000000, 0x007fffff }, |
11932 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
11933 | 0x00000000, 0x0000003f }, | |
11934 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
11935 | 0x00000000, 0x000001ff }, | |
11936 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
11937 | 0x00000000, 0x000001ff }, | |
11938 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
11939 | 0xffffffff, 0x00000000 }, | |
11940 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
11941 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 11942 | |
a71116d1 MC |
11943 | /* Mailbox Registers */ |
11944 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
11945 | 0x00000000, 0x000001ff }, | |
11946 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
11947 | 0x00000000, 0x000001ff }, | |
11948 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
11949 | 0x00000000, 0x000007ff }, | |
11950 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
11951 | 0x00000000, 0x000001ff }, | |
11952 | ||
11953 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
11954 | }; | |
11955 | ||
b16250e3 | 11956 | is_5705 = is_5750 = 0; |
63c3a66f | 11957 | if (tg3_flag(tp, 5705_PLUS)) { |
a71116d1 | 11958 | is_5705 = 1; |
63c3a66f | 11959 | if (tg3_flag(tp, 5750_PLUS)) |
b16250e3 MC |
11960 | is_5750 = 1; |
11961 | } | |
a71116d1 MC |
11962 | |
11963 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
11964 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
11965 | continue; | |
11966 | ||
11967 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
11968 | continue; | |
11969 | ||
63c3a66f | 11970 | if (tg3_flag(tp, IS_5788) && |
a71116d1 MC |
11971 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) |
11972 | continue; | |
11973 | ||
b16250e3 MC |
11974 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
11975 | continue; | |
11976 | ||
a71116d1 MC |
11977 | offset = (u32) reg_tbl[i].offset; |
11978 | read_mask = reg_tbl[i].read_mask; | |
11979 | write_mask = reg_tbl[i].write_mask; | |
11980 | ||
11981 | /* Save the original register content */ | |
11982 | save_val = tr32(offset); | |
11983 | ||
11984 | /* Determine the read-only value. */ | |
11985 | read_val = save_val & read_mask; | |
11986 | ||
11987 | /* Write zero to the register, then make sure the read-only bits | |
11988 | * are not changed and the read/write bits are all zeros. | |
11989 | */ | |
11990 | tw32(offset, 0); | |
11991 | ||
11992 | val = tr32(offset); | |
11993 | ||
11994 | /* Test the read-only and read/write bits. */ | |
11995 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
11996 | goto out; | |
11997 | ||
11998 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
11999 | * make sure the read-only bits are not changed and the | |
12000 | * read/write bits are all ones. | |
12001 | */ | |
12002 | tw32(offset, read_mask | write_mask); | |
12003 | ||
12004 | val = tr32(offset); | |
12005 | ||
12006 | /* Test the read-only bits. */ | |
12007 | if ((val & read_mask) != read_val) | |
12008 | goto out; | |
12009 | ||
12010 | /* Test the read/write bits. */ | |
12011 | if ((val & write_mask) != write_mask) | |
12012 | goto out; | |
12013 | ||
12014 | tw32(offset, save_val); | |
12015 | } | |
12016 | ||
12017 | return 0; | |
12018 | ||
12019 | out: | |
9f88f29f | 12020 | if (netif_msg_hw(tp)) |
2445e461 MC |
12021 | netdev_err(tp->dev, |
12022 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
12023 | tw32(offset, save_val); |
12024 | return -EIO; | |
12025 | } | |
12026 | ||
7942e1db MC |
12027 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
12028 | { | |
f71e1309 | 12029 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
12030 | int i; |
12031 | u32 j; | |
12032 | ||
e9edda69 | 12033 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
12034 | for (j = 0; j < len; j += 4) { |
12035 | u32 val; | |
12036 | ||
12037 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
12038 | tg3_read_mem(tp, offset + j, &val); | |
12039 | if (val != test_pattern[i]) | |
12040 | return -EIO; | |
12041 | } | |
12042 | } | |
12043 | return 0; | |
12044 | } | |
12045 | ||
12046 | static int tg3_test_memory(struct tg3 *tp) | |
12047 | { | |
12048 | static struct mem_entry { | |
12049 | u32 offset; | |
12050 | u32 len; | |
12051 | } mem_tbl_570x[] = { | |
38690194 | 12052 | { 0x00000000, 0x00b50}, |
7942e1db MC |
12053 | { 0x00002000, 0x1c000}, |
12054 | { 0xffffffff, 0x00000} | |
12055 | }, mem_tbl_5705[] = { | |
12056 | { 0x00000100, 0x0000c}, | |
12057 | { 0x00000200, 0x00008}, | |
7942e1db MC |
12058 | { 0x00004000, 0x00800}, |
12059 | { 0x00006000, 0x01000}, | |
12060 | { 0x00008000, 0x02000}, | |
12061 | { 0x00010000, 0x0e000}, | |
12062 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
12063 | }, mem_tbl_5755[] = { |
12064 | { 0x00000200, 0x00008}, | |
12065 | { 0x00004000, 0x00800}, | |
12066 | { 0x00006000, 0x00800}, | |
12067 | { 0x00008000, 0x02000}, | |
12068 | { 0x00010000, 0x0c000}, | |
12069 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
12070 | }, mem_tbl_5906[] = { |
12071 | { 0x00000200, 0x00008}, | |
12072 | { 0x00004000, 0x00400}, | |
12073 | { 0x00006000, 0x00400}, | |
12074 | { 0x00008000, 0x01000}, | |
12075 | { 0x00010000, 0x01000}, | |
12076 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
12077 | }, mem_tbl_5717[] = { |
12078 | { 0x00000200, 0x00008}, | |
12079 | { 0x00010000, 0x0a000}, | |
12080 | { 0x00020000, 0x13c00}, | |
12081 | { 0xffffffff, 0x00000} | |
12082 | }, mem_tbl_57765[] = { | |
12083 | { 0x00000200, 0x00008}, | |
12084 | { 0x00004000, 0x00800}, | |
12085 | { 0x00006000, 0x09800}, | |
12086 | { 0x00010000, 0x0a000}, | |
12087 | { 0xffffffff, 0x00000} | |
7942e1db MC |
12088 | }; |
12089 | struct mem_entry *mem_tbl; | |
12090 | int err = 0; | |
12091 | int i; | |
12092 | ||
63c3a66f | 12093 | if (tg3_flag(tp, 5717_PLUS)) |
8b5a6c42 | 12094 | mem_tbl = mem_tbl_5717; |
55086ad9 | 12095 | else if (tg3_flag(tp, 57765_CLASS)) |
8b5a6c42 | 12096 | mem_tbl = mem_tbl_57765; |
63c3a66f | 12097 | else if (tg3_flag(tp, 5755_PLUS)) |
321d32a0 MC |
12098 | mem_tbl = mem_tbl_5755; |
12099 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
12100 | mem_tbl = mem_tbl_5906; | |
63c3a66f | 12101 | else if (tg3_flag(tp, 5705_PLUS)) |
321d32a0 MC |
12102 | mem_tbl = mem_tbl_5705; |
12103 | else | |
7942e1db MC |
12104 | mem_tbl = mem_tbl_570x; |
12105 | ||
12106 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
12107 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
12108 | if (err) | |
7942e1db MC |
12109 | break; |
12110 | } | |
6aa20a22 | 12111 | |
7942e1db MC |
12112 | return err; |
12113 | } | |
12114 | ||
bb158d69 MC |
12115 | #define TG3_TSO_MSS 500 |
12116 | ||
12117 | #define TG3_TSO_IP_HDR_LEN 20 | |
12118 | #define TG3_TSO_TCP_HDR_LEN 20 | |
12119 | #define TG3_TSO_TCP_OPT_LEN 12 | |
12120 | ||
12121 | static const u8 tg3_tso_header[] = { | |
12122 | 0x08, 0x00, | |
12123 | 0x45, 0x00, 0x00, 0x00, | |
12124 | 0x00, 0x00, 0x40, 0x00, | |
12125 | 0x40, 0x06, 0x00, 0x00, | |
12126 | 0x0a, 0x00, 0x00, 0x01, | |
12127 | 0x0a, 0x00, 0x00, 0x02, | |
12128 | 0x0d, 0x00, 0xe0, 0x00, | |
12129 | 0x00, 0x00, 0x01, 0x00, | |
12130 | 0x00, 0x00, 0x02, 0x00, | |
12131 | 0x80, 0x10, 0x10, 0x00, | |
12132 | 0x14, 0x09, 0x00, 0x00, | |
12133 | 0x01, 0x01, 0x08, 0x0a, | |
12134 | 0x11, 0x11, 0x11, 0x11, | |
12135 | 0x11, 0x11, 0x11, 0x11, | |
12136 | }; | |
9f40dead | 12137 | |
28a45957 | 12138 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) |
c76949a6 | 12139 | { |
5e5a7f37 | 12140 | u32 rx_start_idx, rx_idx, tx_idx, opaque_key; |
bb158d69 | 12141 | u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; |
84b67b27 | 12142 | u32 budget; |
9205fd9c ED |
12143 | struct sk_buff *skb; |
12144 | u8 *tx_data, *rx_data; | |
c76949a6 MC |
12145 | dma_addr_t map; |
12146 | int num_pkts, tx_len, rx_len, i, err; | |
12147 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 12148 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 12149 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 12150 | |
c8873405 MC |
12151 | tnapi = &tp->napi[0]; |
12152 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 12153 | if (tp->irq_cnt > 1) { |
63c3a66f | 12154 | if (tg3_flag(tp, ENABLE_RSS)) |
1da85aa3 | 12155 | rnapi = &tp->napi[1]; |
63c3a66f | 12156 | if (tg3_flag(tp, ENABLE_TSS)) |
c8873405 | 12157 | tnapi = &tp->napi[1]; |
0c1d0e2b | 12158 | } |
fd2ce37f | 12159 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 12160 | |
c76949a6 MC |
12161 | err = -EIO; |
12162 | ||
4852a861 | 12163 | tx_len = pktsz; |
a20e9c62 | 12164 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
12165 | if (!skb) |
12166 | return -ENOMEM; | |
12167 | ||
c76949a6 MC |
12168 | tx_data = skb_put(skb, tx_len); |
12169 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
12170 | memset(tx_data + 6, 0x0, 8); | |
12171 | ||
4852a861 | 12172 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
c76949a6 | 12173 | |
28a45957 | 12174 | if (tso_loopback) { |
bb158d69 MC |
12175 | struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN]; |
12176 | ||
12177 | u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN + | |
12178 | TG3_TSO_TCP_OPT_LEN; | |
12179 | ||
12180 | memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header, | |
12181 | sizeof(tg3_tso_header)); | |
12182 | mss = TG3_TSO_MSS; | |
12183 | ||
12184 | val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); | |
12185 | num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); | |
12186 | ||
12187 | /* Set the total length field in the IP header */ | |
12188 | iph->tot_len = htons((u16)(mss + hdr_len)); | |
12189 | ||
12190 | base_flags = (TXD_FLAG_CPU_PRE_DMA | | |
12191 | TXD_FLAG_CPU_POST_DMA); | |
12192 | ||
63c3a66f JP |
12193 | if (tg3_flag(tp, HW_TSO_1) || |
12194 | tg3_flag(tp, HW_TSO_2) || | |
12195 | tg3_flag(tp, HW_TSO_3)) { | |
bb158d69 MC |
12196 | struct tcphdr *th; |
12197 | val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; | |
12198 | th = (struct tcphdr *)&tx_data[val]; | |
12199 | th->check = 0; | |
12200 | } else | |
12201 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
12202 | ||
63c3a66f | 12203 | if (tg3_flag(tp, HW_TSO_3)) { |
bb158d69 MC |
12204 | mss |= (hdr_len & 0xc) << 12; |
12205 | if (hdr_len & 0x10) | |
12206 | base_flags |= 0x00000010; | |
12207 | base_flags |= (hdr_len & 0x3e0) << 5; | |
63c3a66f | 12208 | } else if (tg3_flag(tp, HW_TSO_2)) |
bb158d69 | 12209 | mss |= hdr_len << 9; |
63c3a66f | 12210 | else if (tg3_flag(tp, HW_TSO_1) || |
bb158d69 MC |
12211 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
12212 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); | |
12213 | } else { | |
12214 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); | |
12215 | } | |
12216 | ||
12217 | data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header); | |
12218 | } else { | |
12219 | num_pkts = 1; | |
12220 | data_off = ETH_HLEN; | |
c441b456 MC |
12221 | |
12222 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && | |
12223 | tx_len > VLAN_ETH_FRAME_LEN) | |
12224 | base_flags |= TXD_FLAG_JMB_PKT; | |
bb158d69 MC |
12225 | } |
12226 | ||
12227 | for (i = data_off; i < tx_len; i++) | |
c76949a6 MC |
12228 | tx_data[i] = (u8) (i & 0xff); |
12229 | ||
f4188d8a AD |
12230 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
12231 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
12232 | dev_kfree_skb(skb); |
12233 | return -EIO; | |
12234 | } | |
c76949a6 | 12235 | |
0d681b27 MC |
12236 | val = tnapi->tx_prod; |
12237 | tnapi->tx_buffers[val].skb = skb; | |
12238 | dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); | |
12239 | ||
c76949a6 | 12240 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 12241 | rnapi->coal_now); |
c76949a6 MC |
12242 | |
12243 | udelay(10); | |
12244 | ||
898a56f8 | 12245 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 12246 | |
84b67b27 MC |
12247 | budget = tg3_tx_avail(tnapi); |
12248 | if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len, | |
d1a3b737 MC |
12249 | base_flags | TXD_FLAG_END, mss, 0)) { |
12250 | tnapi->tx_buffers[val].skb = NULL; | |
12251 | dev_kfree_skb(skb); | |
12252 | return -EIO; | |
12253 | } | |
c76949a6 | 12254 | |
f3f3f27e | 12255 | tnapi->tx_prod++; |
c76949a6 | 12256 | |
6541b806 MC |
12257 | /* Sync BD data before updating mailbox */ |
12258 | wmb(); | |
12259 | ||
f3f3f27e MC |
12260 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
12261 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
12262 | |
12263 | udelay(10); | |
12264 | ||
303fc921 MC |
12265 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
12266 | for (i = 0; i < 35; i++) { | |
c76949a6 | 12267 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 12268 | coal_now); |
c76949a6 MC |
12269 | |
12270 | udelay(10); | |
12271 | ||
898a56f8 MC |
12272 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
12273 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 12274 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
12275 | (rx_idx == (rx_start_idx + num_pkts))) |
12276 | break; | |
12277 | } | |
12278 | ||
ba1142e4 | 12279 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); |
c76949a6 MC |
12280 | dev_kfree_skb(skb); |
12281 | ||
f3f3f27e | 12282 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
12283 | goto out; |
12284 | ||
12285 | if (rx_idx != rx_start_idx + num_pkts) | |
12286 | goto out; | |
12287 | ||
bb158d69 MC |
12288 | val = data_off; |
12289 | while (rx_idx != rx_start_idx) { | |
12290 | desc = &rnapi->rx_rcb[rx_start_idx++]; | |
12291 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
12292 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
c76949a6 | 12293 | |
bb158d69 MC |
12294 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && |
12295 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
12296 | goto out; | |
c76949a6 | 12297 | |
bb158d69 MC |
12298 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) |
12299 | - ETH_FCS_LEN; | |
c76949a6 | 12300 | |
28a45957 | 12301 | if (!tso_loopback) { |
bb158d69 MC |
12302 | if (rx_len != tx_len) |
12303 | goto out; | |
4852a861 | 12304 | |
bb158d69 MC |
12305 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
12306 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
12307 | goto out; | |
12308 | } else { | |
12309 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
12310 | goto out; | |
12311 | } | |
12312 | } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
12313 | (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
54e0a67f | 12314 | >> RXD_TCPCSUM_SHIFT != 0xffff) { |
4852a861 | 12315 | goto out; |
bb158d69 | 12316 | } |
4852a861 | 12317 | |
bb158d69 | 12318 | if (opaque_key == RXD_OPAQUE_RING_STD) { |
9205fd9c | 12319 | rx_data = tpr->rx_std_buffers[desc_idx].data; |
bb158d69 MC |
12320 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], |
12321 | mapping); | |
12322 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
9205fd9c | 12323 | rx_data = tpr->rx_jmb_buffers[desc_idx].data; |
bb158d69 MC |
12324 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], |
12325 | mapping); | |
12326 | } else | |
12327 | goto out; | |
c76949a6 | 12328 | |
bb158d69 MC |
12329 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, |
12330 | PCI_DMA_FROMDEVICE); | |
c76949a6 | 12331 | |
9205fd9c | 12332 | rx_data += TG3_RX_OFFSET(tp); |
bb158d69 | 12333 | for (i = data_off; i < rx_len; i++, val++) { |
9205fd9c | 12334 | if (*(rx_data + i) != (u8) (val & 0xff)) |
bb158d69 MC |
12335 | goto out; |
12336 | } | |
c76949a6 | 12337 | } |
bb158d69 | 12338 | |
c76949a6 | 12339 | err = 0; |
6aa20a22 | 12340 | |
9205fd9c | 12341 | /* tg3_free_rings will unmap and free the rx_data */ |
c76949a6 MC |
12342 | out: |
12343 | return err; | |
12344 | } | |
12345 | ||
00c266b7 MC |
12346 | #define TG3_STD_LOOPBACK_FAILED 1 |
12347 | #define TG3_JMB_LOOPBACK_FAILED 2 | |
bb158d69 | 12348 | #define TG3_TSO_LOOPBACK_FAILED 4 |
28a45957 MC |
12349 | #define TG3_LOOPBACK_FAILED \ |
12350 | (TG3_STD_LOOPBACK_FAILED | \ | |
12351 | TG3_JMB_LOOPBACK_FAILED | \ | |
12352 | TG3_TSO_LOOPBACK_FAILED) | |
00c266b7 | 12353 | |
941ec90f | 12354 | static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) |
9f40dead | 12355 | { |
28a45957 | 12356 | int err = -EIO; |
2215e24c | 12357 | u32 eee_cap; |
c441b456 MC |
12358 | u32 jmb_pkt_sz = 9000; |
12359 | ||
12360 | if (tp->dma_limit) | |
12361 | jmb_pkt_sz = tp->dma_limit - ETH_HLEN; | |
9f40dead | 12362 | |
ab789046 MC |
12363 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
12364 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
12365 | ||
28a45957 MC |
12366 | if (!netif_running(tp->dev)) { |
12367 | data[0] = TG3_LOOPBACK_FAILED; | |
12368 | data[1] = TG3_LOOPBACK_FAILED; | |
941ec90f MC |
12369 | if (do_extlpbk) |
12370 | data[2] = TG3_LOOPBACK_FAILED; | |
28a45957 MC |
12371 | goto done; |
12372 | } | |
12373 | ||
b9ec6c1b | 12374 | err = tg3_reset_hw(tp, 1); |
ab789046 | 12375 | if (err) { |
28a45957 MC |
12376 | data[0] = TG3_LOOPBACK_FAILED; |
12377 | data[1] = TG3_LOOPBACK_FAILED; | |
941ec90f MC |
12378 | if (do_extlpbk) |
12379 | data[2] = TG3_LOOPBACK_FAILED; | |
ab789046 MC |
12380 | goto done; |
12381 | } | |
9f40dead | 12382 | |
63c3a66f | 12383 | if (tg3_flag(tp, ENABLE_RSS)) { |
4a85f098 MC |
12384 | int i; |
12385 | ||
12386 | /* Reroute all rx packets to the 1st queue */ | |
12387 | for (i = MAC_RSS_INDIR_TBL_0; | |
12388 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
12389 | tw32(i, 0x0); | |
12390 | } | |
12391 | ||
6e01b20b MC |
12392 | /* HW errata - mac loopback fails in some cases on 5780. |
12393 | * Normal traffic and PHY loopback are not affected by | |
12394 | * errata. Also, the MAC loopback test is deprecated for | |
12395 | * all newer ASIC revisions. | |
12396 | */ | |
12397 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
12398 | !tg3_flag(tp, CPMU_PRESENT)) { | |
12399 | tg3_mac_loopback(tp, true); | |
9936bcf6 | 12400 | |
28a45957 MC |
12401 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
12402 | data[0] |= TG3_STD_LOOPBACK_FAILED; | |
6e01b20b MC |
12403 | |
12404 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
c441b456 | 12405 | tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) |
28a45957 | 12406 | data[0] |= TG3_JMB_LOOPBACK_FAILED; |
6e01b20b MC |
12407 | |
12408 | tg3_mac_loopback(tp, false); | |
12409 | } | |
4852a861 | 12410 | |
f07e9af3 | 12411 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
63c3a66f | 12412 | !tg3_flag(tp, USE_PHYLIB)) { |
5e5a7f37 MC |
12413 | int i; |
12414 | ||
941ec90f | 12415 | tg3_phy_lpbk_set(tp, 0, false); |
5e5a7f37 MC |
12416 | |
12417 | /* Wait for link */ | |
12418 | for (i = 0; i < 100; i++) { | |
12419 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
12420 | break; | |
12421 | mdelay(1); | |
12422 | } | |
12423 | ||
28a45957 MC |
12424 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
12425 | data[1] |= TG3_STD_LOOPBACK_FAILED; | |
63c3a66f | 12426 | if (tg3_flag(tp, TSO_CAPABLE) && |
28a45957 MC |
12427 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) |
12428 | data[1] |= TG3_TSO_LOOPBACK_FAILED; | |
63c3a66f | 12429 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
c441b456 | 12430 | tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) |
28a45957 | 12431 | data[1] |= TG3_JMB_LOOPBACK_FAILED; |
9f40dead | 12432 | |
941ec90f MC |
12433 | if (do_extlpbk) { |
12434 | tg3_phy_lpbk_set(tp, 0, true); | |
12435 | ||
12436 | /* All link indications report up, but the hardware | |
12437 | * isn't really ready for about 20 msec. Double it | |
12438 | * to be sure. | |
12439 | */ | |
12440 | mdelay(40); | |
12441 | ||
12442 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) | |
12443 | data[2] |= TG3_STD_LOOPBACK_FAILED; | |
12444 | if (tg3_flag(tp, TSO_CAPABLE) && | |
12445 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) | |
12446 | data[2] |= TG3_TSO_LOOPBACK_FAILED; | |
12447 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
c441b456 | 12448 | tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) |
941ec90f MC |
12449 | data[2] |= TG3_JMB_LOOPBACK_FAILED; |
12450 | } | |
12451 | ||
5e5a7f37 MC |
12452 | /* Re-enable gphy autopowerdown. */ |
12453 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) | |
12454 | tg3_phy_toggle_apd(tp, true); | |
12455 | } | |
6833c043 | 12456 | |
941ec90f | 12457 | err = (data[0] | data[1] | data[2]) ? -EIO : 0; |
28a45957 | 12458 | |
ab789046 MC |
12459 | done: |
12460 | tp->phy_flags |= eee_cap; | |
12461 | ||
9f40dead MC |
12462 | return err; |
12463 | } | |
12464 | ||
4cafd3f5 MC |
12465 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
12466 | u64 *data) | |
12467 | { | |
566f86ad | 12468 | struct tg3 *tp = netdev_priv(dev); |
941ec90f | 12469 | bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; |
566f86ad | 12470 | |
bed9829f MC |
12471 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && |
12472 | tg3_power_up(tp)) { | |
12473 | etest->flags |= ETH_TEST_FL_FAILED; | |
12474 | memset(data, 1, sizeof(u64) * TG3_NUM_TEST); | |
12475 | return; | |
12476 | } | |
bc1c7567 | 12477 | |
566f86ad MC |
12478 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
12479 | ||
12480 | if (tg3_test_nvram(tp) != 0) { | |
12481 | etest->flags |= ETH_TEST_FL_FAILED; | |
12482 | data[0] = 1; | |
12483 | } | |
941ec90f | 12484 | if (!doextlpbk && tg3_test_link(tp)) { |
ca43007a MC |
12485 | etest->flags |= ETH_TEST_FL_FAILED; |
12486 | data[1] = 1; | |
12487 | } | |
a71116d1 | 12488 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 12489 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
12490 | |
12491 | if (netif_running(dev)) { | |
b02fd9e3 | 12492 | tg3_phy_stop(tp); |
a71116d1 | 12493 | tg3_netif_stop(tp); |
bbe832c0 MC |
12494 | irq_sync = 1; |
12495 | } | |
a71116d1 | 12496 | |
bbe832c0 | 12497 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
12498 | |
12499 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 12500 | err = tg3_nvram_lock(tp); |
a71116d1 | 12501 | tg3_halt_cpu(tp, RX_CPU_BASE); |
63c3a66f | 12502 | if (!tg3_flag(tp, 5705_PLUS)) |
a71116d1 | 12503 | tg3_halt_cpu(tp, TX_CPU_BASE); |
ec41c7df MC |
12504 | if (!err) |
12505 | tg3_nvram_unlock(tp); | |
a71116d1 | 12506 | |
f07e9af3 | 12507 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
12508 | tg3_phy_reset(tp); |
12509 | ||
a71116d1 MC |
12510 | if (tg3_test_registers(tp) != 0) { |
12511 | etest->flags |= ETH_TEST_FL_FAILED; | |
12512 | data[2] = 1; | |
12513 | } | |
28a45957 | 12514 | |
7942e1db MC |
12515 | if (tg3_test_memory(tp) != 0) { |
12516 | etest->flags |= ETH_TEST_FL_FAILED; | |
12517 | data[3] = 1; | |
12518 | } | |
28a45957 | 12519 | |
941ec90f MC |
12520 | if (doextlpbk) |
12521 | etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; | |
12522 | ||
12523 | if (tg3_test_loopback(tp, &data[4], doextlpbk)) | |
c76949a6 | 12524 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 12525 | |
f47c11ee DM |
12526 | tg3_full_unlock(tp); |
12527 | ||
d4bc3927 MC |
12528 | if (tg3_test_interrupt(tp) != 0) { |
12529 | etest->flags |= ETH_TEST_FL_FAILED; | |
941ec90f | 12530 | data[7] = 1; |
d4bc3927 | 12531 | } |
f47c11ee DM |
12532 | |
12533 | tg3_full_lock(tp, 0); | |
d4bc3927 | 12534 | |
a71116d1 MC |
12535 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
12536 | if (netif_running(dev)) { | |
63c3a66f | 12537 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
12538 | err2 = tg3_restart_hw(tp, 1); |
12539 | if (!err2) | |
b9ec6c1b | 12540 | tg3_netif_start(tp); |
a71116d1 | 12541 | } |
f47c11ee DM |
12542 | |
12543 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
12544 | |
12545 | if (irq_sync && !err2) | |
12546 | tg3_phy_start(tp); | |
a71116d1 | 12547 | } |
80096068 | 12548 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 12549 | tg3_power_down(tp); |
bc1c7567 | 12550 | |
4cafd3f5 MC |
12551 | } |
12552 | ||
1da177e4 LT |
12553 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
12554 | { | |
12555 | struct mii_ioctl_data *data = if_mii(ifr); | |
12556 | struct tg3 *tp = netdev_priv(dev); | |
12557 | int err; | |
12558 | ||
63c3a66f | 12559 | if (tg3_flag(tp, USE_PHYLIB)) { |
3f0e3ad7 | 12560 | struct phy_device *phydev; |
f07e9af3 | 12561 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 12562 | return -EAGAIN; |
3f0e3ad7 | 12563 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 12564 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
12565 | } |
12566 | ||
33f401ae | 12567 | switch (cmd) { |
1da177e4 | 12568 | case SIOCGMIIPHY: |
882e9793 | 12569 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
12570 | |
12571 | /* fallthru */ | |
12572 | case SIOCGMIIREG: { | |
12573 | u32 mii_regval; | |
12574 | ||
f07e9af3 | 12575 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
12576 | break; /* We have no PHY */ |
12577 | ||
34eea5ac | 12578 | if (!netif_running(dev)) |
bc1c7567 MC |
12579 | return -EAGAIN; |
12580 | ||
f47c11ee | 12581 | spin_lock_bh(&tp->lock); |
1da177e4 | 12582 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 12583 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
12584 | |
12585 | data->val_out = mii_regval; | |
12586 | ||
12587 | return err; | |
12588 | } | |
12589 | ||
12590 | case SIOCSMIIREG: | |
f07e9af3 | 12591 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
12592 | break; /* We have no PHY */ |
12593 | ||
34eea5ac | 12594 | if (!netif_running(dev)) |
bc1c7567 MC |
12595 | return -EAGAIN; |
12596 | ||
f47c11ee | 12597 | spin_lock_bh(&tp->lock); |
1da177e4 | 12598 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 12599 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
12600 | |
12601 | return err; | |
12602 | ||
12603 | default: | |
12604 | /* do nothing */ | |
12605 | break; | |
12606 | } | |
12607 | return -EOPNOTSUPP; | |
12608 | } | |
12609 | ||
15f9850d DM |
12610 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
12611 | { | |
12612 | struct tg3 *tp = netdev_priv(dev); | |
12613 | ||
12614 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
12615 | return 0; | |
12616 | } | |
12617 | ||
d244c892 MC |
12618 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
12619 | { | |
12620 | struct tg3 *tp = netdev_priv(dev); | |
12621 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
12622 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
12623 | ||
63c3a66f | 12624 | if (!tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
12625 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; |
12626 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
12627 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
12628 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
12629 | } | |
12630 | ||
12631 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
12632 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
12633 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
12634 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
12635 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
12636 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
12637 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
12638 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
12639 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
12640 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
12641 | return -EINVAL; | |
12642 | ||
12643 | /* No rx interrupts will be generated if both are zero */ | |
12644 | if ((ec->rx_coalesce_usecs == 0) && | |
12645 | (ec->rx_max_coalesced_frames == 0)) | |
12646 | return -EINVAL; | |
12647 | ||
12648 | /* No tx interrupts will be generated if both are zero */ | |
12649 | if ((ec->tx_coalesce_usecs == 0) && | |
12650 | (ec->tx_max_coalesced_frames == 0)) | |
12651 | return -EINVAL; | |
12652 | ||
12653 | /* Only copy relevant parameters, ignore all others. */ | |
12654 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
12655 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
12656 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
12657 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
12658 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
12659 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
12660 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
12661 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
12662 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
12663 | ||
12664 | if (netif_running(dev)) { | |
12665 | tg3_full_lock(tp, 0); | |
12666 | __tg3_set_coalesce(tp, &tp->coal); | |
12667 | tg3_full_unlock(tp); | |
12668 | } | |
12669 | return 0; | |
12670 | } | |
12671 | ||
7282d491 | 12672 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
12673 | .get_settings = tg3_get_settings, |
12674 | .set_settings = tg3_set_settings, | |
12675 | .get_drvinfo = tg3_get_drvinfo, | |
12676 | .get_regs_len = tg3_get_regs_len, | |
12677 | .get_regs = tg3_get_regs, | |
12678 | .get_wol = tg3_get_wol, | |
12679 | .set_wol = tg3_set_wol, | |
12680 | .get_msglevel = tg3_get_msglevel, | |
12681 | .set_msglevel = tg3_set_msglevel, | |
12682 | .nway_reset = tg3_nway_reset, | |
12683 | .get_link = ethtool_op_get_link, | |
12684 | .get_eeprom_len = tg3_get_eeprom_len, | |
12685 | .get_eeprom = tg3_get_eeprom, | |
12686 | .set_eeprom = tg3_set_eeprom, | |
12687 | .get_ringparam = tg3_get_ringparam, | |
12688 | .set_ringparam = tg3_set_ringparam, | |
12689 | .get_pauseparam = tg3_get_pauseparam, | |
12690 | .set_pauseparam = tg3_set_pauseparam, | |
4cafd3f5 | 12691 | .self_test = tg3_self_test, |
1da177e4 | 12692 | .get_strings = tg3_get_strings, |
81b8709c | 12693 | .set_phys_id = tg3_set_phys_id, |
1da177e4 | 12694 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 12695 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 12696 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 12697 | .get_sset_count = tg3_get_sset_count, |
90415477 MC |
12698 | .get_rxnfc = tg3_get_rxnfc, |
12699 | .get_rxfh_indir_size = tg3_get_rxfh_indir_size, | |
12700 | .get_rxfh_indir = tg3_get_rxfh_indir, | |
12701 | .set_rxfh_indir = tg3_set_rxfh_indir, | |
0968169c MC |
12702 | .get_channels = tg3_get_channels, |
12703 | .set_channels = tg3_set_channels, | |
3f847490 | 12704 | .get_ts_info = ethtool_op_get_ts_info, |
1da177e4 LT |
12705 | }; |
12706 | ||
b4017c53 DM |
12707 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
12708 | struct rtnl_link_stats64 *stats) | |
12709 | { | |
12710 | struct tg3 *tp = netdev_priv(dev); | |
12711 | ||
0f566b20 MC |
12712 | spin_lock_bh(&tp->lock); |
12713 | if (!tp->hw_stats) { | |
12714 | spin_unlock_bh(&tp->lock); | |
b4017c53 | 12715 | return &tp->net_stats_prev; |
0f566b20 | 12716 | } |
b4017c53 | 12717 | |
b4017c53 DM |
12718 | tg3_get_nstats(tp, stats); |
12719 | spin_unlock_bh(&tp->lock); | |
12720 | ||
12721 | return stats; | |
12722 | } | |
12723 | ||
ccd5ba9d MC |
12724 | static void tg3_set_rx_mode(struct net_device *dev) |
12725 | { | |
12726 | struct tg3 *tp = netdev_priv(dev); | |
12727 | ||
12728 | if (!netif_running(dev)) | |
12729 | return; | |
12730 | ||
12731 | tg3_full_lock(tp, 0); | |
12732 | __tg3_set_rx_mode(dev); | |
12733 | tg3_full_unlock(tp); | |
12734 | } | |
12735 | ||
faf1627a MC |
12736 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
12737 | int new_mtu) | |
12738 | { | |
12739 | dev->mtu = new_mtu; | |
12740 | ||
12741 | if (new_mtu > ETH_DATA_LEN) { | |
12742 | if (tg3_flag(tp, 5780_CLASS)) { | |
12743 | netdev_update_features(dev); | |
12744 | tg3_flag_clear(tp, TSO_CAPABLE); | |
12745 | } else { | |
12746 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
12747 | } | |
12748 | } else { | |
12749 | if (tg3_flag(tp, 5780_CLASS)) { | |
12750 | tg3_flag_set(tp, TSO_CAPABLE); | |
12751 | netdev_update_features(dev); | |
12752 | } | |
12753 | tg3_flag_clear(tp, JUMBO_RING_ENABLE); | |
12754 | } | |
12755 | } | |
12756 | ||
12757 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
12758 | { | |
12759 | struct tg3 *tp = netdev_priv(dev); | |
2fae5e36 | 12760 | int err, reset_phy = 0; |
faf1627a MC |
12761 | |
12762 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
12763 | return -EINVAL; | |
12764 | ||
12765 | if (!netif_running(dev)) { | |
12766 | /* We'll just catch it later when the | |
12767 | * device is up'd. | |
12768 | */ | |
12769 | tg3_set_mtu(dev, tp, new_mtu); | |
12770 | return 0; | |
12771 | } | |
12772 | ||
12773 | tg3_phy_stop(tp); | |
12774 | ||
12775 | tg3_netif_stop(tp); | |
12776 | ||
12777 | tg3_full_lock(tp, 1); | |
12778 | ||
12779 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
12780 | ||
12781 | tg3_set_mtu(dev, tp, new_mtu); | |
12782 | ||
2fae5e36 MC |
12783 | /* Reset PHY, otherwise the read DMA engine will be in a mode that |
12784 | * breaks all requests to 256 bytes. | |
12785 | */ | |
12786 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) | |
12787 | reset_phy = 1; | |
12788 | ||
12789 | err = tg3_restart_hw(tp, reset_phy); | |
faf1627a MC |
12790 | |
12791 | if (!err) | |
12792 | tg3_netif_start(tp); | |
12793 | ||
12794 | tg3_full_unlock(tp); | |
12795 | ||
12796 | if (!err) | |
12797 | tg3_phy_start(tp); | |
12798 | ||
12799 | return err; | |
12800 | } | |
12801 | ||
12802 | static const struct net_device_ops tg3_netdev_ops = { | |
12803 | .ndo_open = tg3_open, | |
12804 | .ndo_stop = tg3_close, | |
12805 | .ndo_start_xmit = tg3_start_xmit, | |
12806 | .ndo_get_stats64 = tg3_get_stats64, | |
12807 | .ndo_validate_addr = eth_validate_addr, | |
12808 | .ndo_set_rx_mode = tg3_set_rx_mode, | |
12809 | .ndo_set_mac_address = tg3_set_mac_addr, | |
12810 | .ndo_do_ioctl = tg3_ioctl, | |
12811 | .ndo_tx_timeout = tg3_tx_timeout, | |
12812 | .ndo_change_mtu = tg3_change_mtu, | |
12813 | .ndo_fix_features = tg3_fix_features, | |
12814 | .ndo_set_features = tg3_set_features, | |
12815 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
12816 | .ndo_poll_controller = tg3_poll_controller, | |
12817 | #endif | |
12818 | }; | |
12819 | ||
1da177e4 LT |
12820 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) |
12821 | { | |
1b27777a | 12822 | u32 cursize, val, magic; |
1da177e4 LT |
12823 | |
12824 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
12825 | ||
e4f34110 | 12826 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
12827 | return; |
12828 | ||
b16250e3 MC |
12829 | if ((magic != TG3_EEPROM_MAGIC) && |
12830 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
12831 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
12832 | return; |
12833 | ||
12834 | /* | |
12835 | * Size the chip by reading offsets at increasing powers of two. | |
12836 | * When we encounter our validation signature, we know the addressing | |
12837 | * has wrapped around, and thus have our chip size. | |
12838 | */ | |
1b27777a | 12839 | cursize = 0x10; |
1da177e4 LT |
12840 | |
12841 | while (cursize < tp->nvram_size) { | |
e4f34110 | 12842 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
12843 | return; |
12844 | ||
1820180b | 12845 | if (val == magic) |
1da177e4 LT |
12846 | break; |
12847 | ||
12848 | cursize <<= 1; | |
12849 | } | |
12850 | ||
12851 | tp->nvram_size = cursize; | |
12852 | } | |
6aa20a22 | 12853 | |
1da177e4 LT |
12854 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
12855 | { | |
12856 | u32 val; | |
12857 | ||
63c3a66f | 12858 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) |
1b27777a MC |
12859 | return; |
12860 | ||
12861 | /* Selfboot format */ | |
1820180b | 12862 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
12863 | tg3_get_eeprom_size(tp); |
12864 | return; | |
12865 | } | |
12866 | ||
6d348f2c | 12867 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 12868 | if (val != 0) { |
6d348f2c MC |
12869 | /* This is confusing. We want to operate on the |
12870 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
12871 | * call will read from NVRAM and byteswap the data | |
12872 | * according to the byteswapping settings for all | |
12873 | * other register accesses. This ensures the data we | |
12874 | * want will always reside in the lower 16-bits. | |
12875 | * However, the data in NVRAM is in LE format, which | |
12876 | * means the data from the NVRAM read will always be | |
12877 | * opposite the endianness of the CPU. The 16-bit | |
12878 | * byteswap then brings the data to CPU endianness. | |
12879 | */ | |
12880 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
12881 | return; |
12882 | } | |
12883 | } | |
fd1122a2 | 12884 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
12885 | } |
12886 | ||
12887 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
12888 | { | |
12889 | u32 nvcfg1; | |
12890 | ||
12891 | nvcfg1 = tr32(NVRAM_CFG1); | |
12892 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
63c3a66f | 12893 | tg3_flag_set(tp, FLASH); |
8590a603 | 12894 | } else { |
1da177e4 LT |
12895 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
12896 | tw32(NVRAM_CFG1, nvcfg1); | |
12897 | } | |
12898 | ||
6ff6f81d | 12899 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
63c3a66f | 12900 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 | 12901 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
12902 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
12903 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12904 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 12905 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12906 | break; |
12907 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
12908 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12909 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
12910 | break; | |
12911 | case FLASH_VENDOR_ATMEL_EEPROM: | |
12912 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12913 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
63c3a66f | 12914 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12915 | break; |
12916 | case FLASH_VENDOR_ST: | |
12917 | tp->nvram_jedecnum = JEDEC_ST; | |
12918 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
63c3a66f | 12919 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12920 | break; |
12921 | case FLASH_VENDOR_SAIFUN: | |
12922 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
12923 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
12924 | break; | |
12925 | case FLASH_VENDOR_SST_SMALL: | |
12926 | case FLASH_VENDOR_SST_LARGE: | |
12927 | tp->nvram_jedecnum = JEDEC_SST; | |
12928 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
12929 | break; | |
1da177e4 | 12930 | } |
8590a603 | 12931 | } else { |
1da177e4 LT |
12932 | tp->nvram_jedecnum = JEDEC_ATMEL; |
12933 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
63c3a66f | 12934 | tg3_flag_set(tp, NVRAM_BUFFERED); |
1da177e4 LT |
12935 | } |
12936 | } | |
12937 | ||
a1b950d5 MC |
12938 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
12939 | { | |
12940 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
12941 | case FLASH_5752PAGE_SIZE_256: | |
12942 | tp->nvram_pagesize = 256; | |
12943 | break; | |
12944 | case FLASH_5752PAGE_SIZE_512: | |
12945 | tp->nvram_pagesize = 512; | |
12946 | break; | |
12947 | case FLASH_5752PAGE_SIZE_1K: | |
12948 | tp->nvram_pagesize = 1024; | |
12949 | break; | |
12950 | case FLASH_5752PAGE_SIZE_2K: | |
12951 | tp->nvram_pagesize = 2048; | |
12952 | break; | |
12953 | case FLASH_5752PAGE_SIZE_4K: | |
12954 | tp->nvram_pagesize = 4096; | |
12955 | break; | |
12956 | case FLASH_5752PAGE_SIZE_264: | |
12957 | tp->nvram_pagesize = 264; | |
12958 | break; | |
12959 | case FLASH_5752PAGE_SIZE_528: | |
12960 | tp->nvram_pagesize = 528; | |
12961 | break; | |
12962 | } | |
12963 | } | |
12964 | ||
361b4ac2 MC |
12965 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
12966 | { | |
12967 | u32 nvcfg1; | |
12968 | ||
12969 | nvcfg1 = tr32(NVRAM_CFG1); | |
12970 | ||
e6af301b MC |
12971 | /* NVRAM protection for TPM */ |
12972 | if (nvcfg1 & (1 << 27)) | |
63c3a66f | 12973 | tg3_flag_set(tp, PROTECTED_NVRAM); |
e6af301b | 12974 | |
361b4ac2 | 12975 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
12976 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
12977 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
12978 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 12979 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 MC |
12980 | break; |
12981 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12982 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
12983 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12984 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
12985 | break; |
12986 | case FLASH_5752VENDOR_ST_M45PE10: | |
12987 | case FLASH_5752VENDOR_ST_M45PE20: | |
12988 | case FLASH_5752VENDOR_ST_M45PE40: | |
12989 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
12990 | tg3_flag_set(tp, NVRAM_BUFFERED); |
12991 | tg3_flag_set(tp, FLASH); | |
8590a603 | 12992 | break; |
361b4ac2 MC |
12993 | } |
12994 | ||
63c3a66f | 12995 | if (tg3_flag(tp, FLASH)) { |
a1b950d5 | 12996 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 12997 | } else { |
361b4ac2 MC |
12998 | /* For eeprom, set pagesize to maximum eeprom size */ |
12999 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
13000 | ||
13001 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
13002 | tw32(NVRAM_CFG1, nvcfg1); | |
13003 | } | |
13004 | } | |
13005 | ||
d3c7b886 MC |
13006 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
13007 | { | |
989a9d23 | 13008 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
13009 | |
13010 | nvcfg1 = tr32(NVRAM_CFG1); | |
13011 | ||
13012 | /* NVRAM protection for TPM */ | |
989a9d23 | 13013 | if (nvcfg1 & (1 << 27)) { |
63c3a66f | 13014 | tg3_flag_set(tp, PROTECTED_NVRAM); |
989a9d23 MC |
13015 | protect = 1; |
13016 | } | |
d3c7b886 | 13017 | |
989a9d23 MC |
13018 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
13019 | switch (nvcfg1) { | |
8590a603 MC |
13020 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
13021 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
13022 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
13023 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
13024 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13025 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13026 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13027 | tp->nvram_pagesize = 264; |
13028 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
13029 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
13030 | tp->nvram_size = (protect ? 0x3e200 : | |
13031 | TG3_NVRAM_SIZE_512KB); | |
13032 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
13033 | tp->nvram_size = (protect ? 0x1f200 : | |
13034 | TG3_NVRAM_SIZE_256KB); | |
13035 | else | |
13036 | tp->nvram_size = (protect ? 0x1f200 : | |
13037 | TG3_NVRAM_SIZE_128KB); | |
13038 | break; | |
13039 | case FLASH_5752VENDOR_ST_M45PE10: | |
13040 | case FLASH_5752VENDOR_ST_M45PE20: | |
13041 | case FLASH_5752VENDOR_ST_M45PE40: | |
13042 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13043 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13044 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13045 | tp->nvram_pagesize = 256; |
13046 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
13047 | tp->nvram_size = (protect ? | |
13048 | TG3_NVRAM_SIZE_64KB : | |
13049 | TG3_NVRAM_SIZE_128KB); | |
13050 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
13051 | tp->nvram_size = (protect ? | |
13052 | TG3_NVRAM_SIZE_64KB : | |
13053 | TG3_NVRAM_SIZE_256KB); | |
13054 | else | |
13055 | tp->nvram_size = (protect ? | |
13056 | TG3_NVRAM_SIZE_128KB : | |
13057 | TG3_NVRAM_SIZE_512KB); | |
13058 | break; | |
d3c7b886 MC |
13059 | } |
13060 | } | |
13061 | ||
1b27777a MC |
13062 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
13063 | { | |
13064 | u32 nvcfg1; | |
13065 | ||
13066 | nvcfg1 = tr32(NVRAM_CFG1); | |
13067 | ||
13068 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
13069 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
13070 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
13071 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
13072 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
13073 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13074 | tg3_flag_set(tp, NVRAM_BUFFERED); |
8590a603 | 13075 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
1b27777a | 13076 | |
8590a603 MC |
13077 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
13078 | tw32(NVRAM_CFG1, nvcfg1); | |
13079 | break; | |
13080 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
13081 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
13082 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
13083 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
13084 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13085 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13086 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13087 | tp->nvram_pagesize = 264; |
13088 | break; | |
13089 | case FLASH_5752VENDOR_ST_M45PE10: | |
13090 | case FLASH_5752VENDOR_ST_M45PE20: | |
13091 | case FLASH_5752VENDOR_ST_M45PE40: | |
13092 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13093 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13094 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13095 | tp->nvram_pagesize = 256; |
13096 | break; | |
1b27777a MC |
13097 | } |
13098 | } | |
13099 | ||
6b91fa02 MC |
13100 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
13101 | { | |
13102 | u32 nvcfg1, protect = 0; | |
13103 | ||
13104 | nvcfg1 = tr32(NVRAM_CFG1); | |
13105 | ||
13106 | /* NVRAM protection for TPM */ | |
13107 | if (nvcfg1 & (1 << 27)) { | |
63c3a66f | 13108 | tg3_flag_set(tp, PROTECTED_NVRAM); |
6b91fa02 MC |
13109 | protect = 1; |
13110 | } | |
13111 | ||
13112 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
13113 | switch (nvcfg1) { | |
8590a603 MC |
13114 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
13115 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
13116 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
13117 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
13118 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
13119 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
13120 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
13121 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
13122 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13123 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13124 | tg3_flag_set(tp, FLASH); | |
13125 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
8590a603 MC |
13126 | tp->nvram_pagesize = 256; |
13127 | break; | |
13128 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
13129 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
13130 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
13131 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
13132 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
13133 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
13134 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
13135 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
13136 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13137 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13138 | tg3_flag_set(tp, FLASH); | |
8590a603 MC |
13139 | tp->nvram_pagesize = 256; |
13140 | break; | |
6b91fa02 MC |
13141 | } |
13142 | ||
13143 | if (protect) { | |
13144 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
13145 | } else { | |
13146 | switch (nvcfg1) { | |
8590a603 MC |
13147 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
13148 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
13149 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
13150 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
13151 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
13152 | break; | |
13153 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
13154 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
13155 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
13156 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
13157 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
13158 | break; | |
13159 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
13160 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
13161 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
13162 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
13163 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
13164 | break; | |
13165 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
13166 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
13167 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
13168 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
13169 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13170 | break; | |
6b91fa02 MC |
13171 | } |
13172 | } | |
13173 | } | |
13174 | ||
b5d3772c MC |
13175 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
13176 | { | |
13177 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13178 | tg3_flag_set(tp, NVRAM_BUFFERED); |
b5d3772c MC |
13179 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
13180 | } | |
13181 | ||
321d32a0 MC |
13182 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
13183 | { | |
13184 | u32 nvcfg1; | |
13185 | ||
13186 | nvcfg1 = tr32(NVRAM_CFG1); | |
13187 | ||
13188 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13189 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
13190 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
13191 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13192 | tg3_flag_set(tp, NVRAM_BUFFERED); |
321d32a0 MC |
13193 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
13194 | ||
13195 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
13196 | tw32(NVRAM_CFG1, nvcfg1); | |
13197 | return; | |
13198 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
13199 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
13200 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
13201 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
13202 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
13203 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
13204 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
13205 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13206 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13207 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
13208 | |
13209 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13210 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
13211 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
13212 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
13213 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13214 | break; | |
13215 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
13216 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
13217 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13218 | break; | |
13219 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
13220 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
13221 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
13222 | break; | |
13223 | } | |
13224 | break; | |
13225 | case FLASH_5752VENDOR_ST_M45PE10: | |
13226 | case FLASH_5752VENDOR_ST_M45PE20: | |
13227 | case FLASH_5752VENDOR_ST_M45PE40: | |
13228 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13229 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13230 | tg3_flag_set(tp, FLASH); | |
321d32a0 MC |
13231 | |
13232 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13233 | case FLASH_5752VENDOR_ST_M45PE10: | |
13234 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13235 | break; | |
13236 | case FLASH_5752VENDOR_ST_M45PE20: | |
13237 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13238 | break; | |
13239 | case FLASH_5752VENDOR_ST_M45PE40: | |
13240 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
13241 | break; | |
13242 | } | |
13243 | break; | |
13244 | default: | |
63c3a66f | 13245 | tg3_flag_set(tp, NO_NVRAM); |
321d32a0 MC |
13246 | return; |
13247 | } | |
13248 | ||
a1b950d5 MC |
13249 | tg3_nvram_get_pagesize(tp, nvcfg1); |
13250 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 13251 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
a1b950d5 MC |
13252 | } |
13253 | ||
13254 | ||
13255 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
13256 | { | |
13257 | u32 nvcfg1; | |
13258 | ||
13259 | nvcfg1 = tr32(NVRAM_CFG1); | |
13260 | ||
13261 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13262 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
13263 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
13264 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13265 | tg3_flag_set(tp, NVRAM_BUFFERED); |
a1b950d5 MC |
13266 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
13267 | ||
13268 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
13269 | tw32(NVRAM_CFG1, nvcfg1); | |
13270 | return; | |
13271 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
13272 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
13273 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
13274 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
13275 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
13276 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
13277 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
13278 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13279 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13280 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
13281 | |
13282 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13283 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
66ee33bf MC |
13284 | /* Detect size with tg3_nvram_get_size() */ |
13285 | break; | |
a1b950d5 MC |
13286 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
13287 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
13288 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13289 | break; | |
13290 | default: | |
13291 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13292 | break; | |
13293 | } | |
321d32a0 | 13294 | break; |
a1b950d5 MC |
13295 | case FLASH_5717VENDOR_ST_M_M25PE10: |
13296 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
13297 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
13298 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
13299 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
13300 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
13301 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
13302 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
13303 | case FLASH_5717VENDOR_ST_25USPT: | |
13304 | case FLASH_5717VENDOR_ST_45USPT: | |
13305 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13306 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13307 | tg3_flag_set(tp, FLASH); | |
a1b950d5 MC |
13308 | |
13309 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
13310 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
a1b950d5 | 13311 | case FLASH_5717VENDOR_ST_M_M45PE20: |
66ee33bf MC |
13312 | /* Detect size with tg3_nvram_get_size() */ |
13313 | break; | |
13314 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
a1b950d5 MC |
13315 | case FLASH_5717VENDOR_ST_A_M45PE20: |
13316 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13317 | break; | |
13318 | default: | |
13319 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13320 | break; | |
13321 | } | |
321d32a0 | 13322 | break; |
a1b950d5 | 13323 | default: |
63c3a66f | 13324 | tg3_flag_set(tp, NO_NVRAM); |
a1b950d5 | 13325 | return; |
321d32a0 | 13326 | } |
a1b950d5 MC |
13327 | |
13328 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
13329 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 13330 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
321d32a0 MC |
13331 | } |
13332 | ||
9b91b5f1 MC |
13333 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
13334 | { | |
13335 | u32 nvcfg1, nvmpinstrp; | |
13336 | ||
13337 | nvcfg1 = tr32(NVRAM_CFG1); | |
13338 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
13339 | ||
13340 | switch (nvmpinstrp) { | |
13341 | case FLASH_5720_EEPROM_HD: | |
13342 | case FLASH_5720_EEPROM_LD: | |
13343 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f | 13344 | tg3_flag_set(tp, NVRAM_BUFFERED); |
9b91b5f1 MC |
13345 | |
13346 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
13347 | tw32(NVRAM_CFG1, nvcfg1); | |
13348 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
13349 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
13350 | else | |
13351 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
13352 | return; | |
13353 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
13354 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
13355 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
13356 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
13357 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
13358 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
13359 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
13360 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
13361 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
13362 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
13363 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
13364 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
13365 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
63c3a66f JP |
13366 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13367 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
13368 | |
13369 | switch (nvmpinstrp) { | |
13370 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
13371 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
13372 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
13373 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13374 | break; | |
13375 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
13376 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
13377 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
13378 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
13379 | break; | |
13380 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
13381 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
13382 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
13383 | break; | |
13384 | default: | |
13385 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13386 | break; | |
13387 | } | |
13388 | break; | |
13389 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
13390 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
13391 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
13392 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
13393 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
13394 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
13395 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
13396 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
13397 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
13398 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
13399 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
13400 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
13401 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
13402 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
13403 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
13404 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
13405 | case FLASH_5720VENDOR_ST_25USPT: | |
13406 | case FLASH_5720VENDOR_ST_45USPT: | |
13407 | tp->nvram_jedecnum = JEDEC_ST; | |
63c3a66f JP |
13408 | tg3_flag_set(tp, NVRAM_BUFFERED); |
13409 | tg3_flag_set(tp, FLASH); | |
9b91b5f1 MC |
13410 | |
13411 | switch (nvmpinstrp) { | |
13412 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
13413 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
13414 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
13415 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
13416 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
13417 | break; | |
13418 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
13419 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
13420 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
13421 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
13422 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
13423 | break; | |
13424 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
13425 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
13426 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
13427 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
13428 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
13429 | break; | |
13430 | default: | |
13431 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
13432 | break; | |
13433 | } | |
13434 | break; | |
13435 | default: | |
63c3a66f | 13436 | tg3_flag_set(tp, NO_NVRAM); |
9b91b5f1 MC |
13437 | return; |
13438 | } | |
13439 | ||
13440 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
13441 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
63c3a66f | 13442 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
9b91b5f1 MC |
13443 | } |
13444 | ||
1da177e4 LT |
13445 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
13446 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
13447 | { | |
1da177e4 LT |
13448 | tw32_f(GRC_EEPROM_ADDR, |
13449 | (EEPROM_ADDR_FSM_RESET | | |
13450 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
13451 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
13452 | ||
9d57f01c | 13453 | msleep(1); |
1da177e4 LT |
13454 | |
13455 | /* Enable seeprom accesses. */ | |
13456 | tw32_f(GRC_LOCAL_CTRL, | |
13457 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
13458 | udelay(100); | |
13459 | ||
13460 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13461 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
63c3a66f | 13462 | tg3_flag_set(tp, NVRAM); |
1da177e4 | 13463 | |
ec41c7df | 13464 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
13465 | netdev_warn(tp->dev, |
13466 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 13467 | __func__); |
ec41c7df MC |
13468 | return; |
13469 | } | |
e6af301b | 13470 | tg3_enable_nvram_access(tp); |
1da177e4 | 13471 | |
989a9d23 MC |
13472 | tp->nvram_size = 0; |
13473 | ||
361b4ac2 MC |
13474 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
13475 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
13476 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
13477 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 13478 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
13479 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
13480 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 13481 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
13482 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
13483 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
13484 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
13485 | tg3_get_5906_nvram_info(tp); | |
b703df6f | 13486 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
55086ad9 | 13487 | tg3_flag(tp, 57765_CLASS)) |
321d32a0 | 13488 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
13489 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13490 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 13491 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
13492 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
13493 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
13494 | else |
13495 | tg3_get_nvram_info(tp); | |
13496 | ||
989a9d23 MC |
13497 | if (tp->nvram_size == 0) |
13498 | tg3_get_nvram_size(tp); | |
1da177e4 | 13499 | |
e6af301b | 13500 | tg3_disable_nvram_access(tp); |
381291b7 | 13501 | tg3_nvram_unlock(tp); |
1da177e4 LT |
13502 | |
13503 | } else { | |
63c3a66f JP |
13504 | tg3_flag_clear(tp, NVRAM); |
13505 | tg3_flag_clear(tp, NVRAM_BUFFERED); | |
1da177e4 LT |
13506 | |
13507 | tg3_get_eeprom_size(tp); | |
13508 | } | |
13509 | } | |
13510 | ||
1da177e4 LT |
13511 | struct subsys_tbl_ent { |
13512 | u16 subsys_vendor, subsys_devid; | |
13513 | u32 phy_id; | |
13514 | }; | |
13515 | ||
24daf2b0 | 13516 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 13517 | /* Broadcom boards. */ |
24daf2b0 | 13518 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13519 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13520 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13521 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13522 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13523 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
13524 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
13525 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
13526 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 13527 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13528 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13529 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
13530 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
13531 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
13532 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 13533 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13534 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13535 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13536 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13537 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 13538 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 13539 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
13540 | |
13541 | /* 3com boards. */ | |
24daf2b0 | 13542 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 13543 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13544 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 13545 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
13546 | { TG3PCI_SUBVENDOR_ID_3COM, |
13547 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
13548 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 13549 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13550 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 13551 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
13552 | |
13553 | /* DELL boards. */ | |
24daf2b0 | 13554 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13555 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13556 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13557 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 13558 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13559 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 13560 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 13561 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
13562 | |
13563 | /* Compaq boards. */ | |
24daf2b0 | 13564 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 13565 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13566 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 13567 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
13568 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
13569 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
13570 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 13571 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 13572 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 13573 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
13574 | |
13575 | /* IBM boards. */ | |
24daf2b0 MC |
13576 | { TG3PCI_SUBVENDOR_ID_IBM, |
13577 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
13578 | }; |
13579 | ||
24daf2b0 | 13580 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
13581 | { |
13582 | int i; | |
13583 | ||
13584 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
13585 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
13586 | tp->pdev->subsystem_vendor) && | |
13587 | (subsys_id_to_phy_id[i].subsys_devid == | |
13588 | tp->pdev->subsystem_device)) | |
13589 | return &subsys_id_to_phy_id[i]; | |
13590 | } | |
13591 | return NULL; | |
13592 | } | |
13593 | ||
7d0c41ef | 13594 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 13595 | { |
1da177e4 | 13596 | u32 val; |
f49639e6 | 13597 | |
79eb6904 | 13598 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
13599 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
13600 | ||
a85feb8c | 13601 | /* Assume an onboard device and WOL capable by default. */ |
63c3a66f JP |
13602 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
13603 | tg3_flag_set(tp, WOL_CAP); | |
72b845e0 | 13604 | |
b5d3772c | 13605 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 13606 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
63c3a66f JP |
13607 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
13608 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 13609 | } |
0527ba35 MC |
13610 | val = tr32(VCPU_CFGSHDW); |
13611 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
63c3a66f | 13612 | tg3_flag_set(tp, ASPM_WORKAROUND); |
0527ba35 | 13613 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
6fdbab9d | 13614 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) { |
63c3a66f | 13615 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
13616 | device_set_wakeup_enable(&tp->pdev->dev, true); |
13617 | } | |
05ac4cb7 | 13618 | goto done; |
b5d3772c MC |
13619 | } |
13620 | ||
1da177e4 LT |
13621 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
13622 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
13623 | u32 nic_cfg, led_cfg; | |
a9daf367 | 13624 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 13625 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
13626 | |
13627 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
13628 | tp->nic_sram_data_cfg = nic_cfg; | |
13629 | ||
13630 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
13631 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
6ff6f81d MC |
13632 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
13633 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13634 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && | |
1da177e4 LT |
13635 | (ver > 0) && (ver < 0x100)) |
13636 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
13637 | ||
a9daf367 MC |
13638 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
13639 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
13640 | ||
1da177e4 LT |
13641 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
13642 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
13643 | eeprom_phy_serdes = 1; | |
13644 | ||
13645 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
13646 | if (nic_phy_id != 0) { | |
13647 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
13648 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
13649 | ||
13650 | eeprom_phy_id = (id1 >> 16) << 10; | |
13651 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
13652 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
13653 | } else | |
13654 | eeprom_phy_id = 0; | |
13655 | ||
7d0c41ef | 13656 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 13657 | if (eeprom_phy_serdes) { |
63c3a66f | 13658 | if (!tg3_flag(tp, 5705_PLUS)) |
f07e9af3 | 13659 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 13660 | else |
f07e9af3 | 13661 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 13662 | } |
7d0c41ef | 13663 | |
63c3a66f | 13664 | if (tg3_flag(tp, 5750_PLUS)) |
1da177e4 LT |
13665 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
13666 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 13667 | else |
1da177e4 LT |
13668 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
13669 | ||
13670 | switch (led_cfg) { | |
13671 | default: | |
13672 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
13673 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
13674 | break; | |
13675 | ||
13676 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
13677 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
13678 | break; | |
13679 | ||
13680 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
13681 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
13682 | |
13683 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
13684 | * read on some older 5700/5701 bootcode. | |
13685 | */ | |
13686 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13687 | ASIC_REV_5700 || | |
13688 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13689 | ASIC_REV_5701) | |
13690 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
13691 | ||
1da177e4 LT |
13692 | break; |
13693 | ||
13694 | case SHASTA_EXT_LED_SHARED: | |
13695 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
13696 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
13697 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
13698 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
13699 | LED_CTRL_MODE_PHY_2); | |
13700 | break; | |
13701 | ||
13702 | case SHASTA_EXT_LED_MAC: | |
13703 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
13704 | break; | |
13705 | ||
13706 | case SHASTA_EXT_LED_COMBO: | |
13707 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
13708 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
13709 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
13710 | LED_CTRL_MODE_PHY_2); | |
13711 | break; | |
13712 | ||
855e1111 | 13713 | } |
1da177e4 LT |
13714 | |
13715 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13716 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
13717 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
13718 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
13719 | ||
b2a5c19c MC |
13720 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
13721 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 13722 | |
9d26e213 | 13723 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
63c3a66f | 13724 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
9d26e213 MC |
13725 | if ((tp->pdev->subsystem_vendor == |
13726 | PCI_VENDOR_ID_ARIMA) && | |
13727 | (tp->pdev->subsystem_device == 0x205a || | |
13728 | tp->pdev->subsystem_device == 0x2063)) | |
63c3a66f | 13729 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
9d26e213 | 13730 | } else { |
63c3a66f JP |
13731 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
13732 | tg3_flag_set(tp, IS_NIC); | |
9d26e213 | 13733 | } |
1da177e4 LT |
13734 | |
13735 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
63c3a66f JP |
13736 | tg3_flag_set(tp, ENABLE_ASF); |
13737 | if (tg3_flag(tp, 5750_PLUS)) | |
13738 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
1da177e4 | 13739 | } |
b2b98d4a MC |
13740 | |
13741 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
63c3a66f JP |
13742 | tg3_flag(tp, 5750_PLUS)) |
13743 | tg3_flag_set(tp, ENABLE_APE); | |
b2b98d4a | 13744 | |
f07e9af3 | 13745 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c | 13746 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
63c3a66f | 13747 | tg3_flag_clear(tp, WOL_CAP); |
1da177e4 | 13748 | |
63c3a66f | 13749 | if (tg3_flag(tp, WOL_CAP) && |
6fdbab9d | 13750 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) { |
63c3a66f | 13751 | tg3_flag_set(tp, WOL_ENABLE); |
6fdbab9d RW |
13752 | device_set_wakeup_enable(&tp->pdev->dev, true); |
13753 | } | |
0527ba35 | 13754 | |
1da177e4 | 13755 | if (cfg2 & (1 << 17)) |
f07e9af3 | 13756 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
13757 | |
13758 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
13759 | /* bootcode if bit 18 is set */ | |
13760 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 13761 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 13762 | |
63c3a66f JP |
13763 | if ((tg3_flag(tp, 57765_PLUS) || |
13764 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
13765 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 | 13766 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 13767 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 13768 | |
63c3a66f | 13769 | if (tg3_flag(tp, PCI_EXPRESS) && |
8c69b1e7 | 13770 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
63c3a66f | 13771 | !tg3_flag(tp, 57765_PLUS)) { |
8ed5d97e MC |
13772 | u32 cfg3; |
13773 | ||
13774 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
13775 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
63c3a66f | 13776 | tg3_flag_set(tp, ASPM_WORKAROUND); |
8ed5d97e | 13777 | } |
a9daf367 | 13778 | |
14417063 | 13779 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
63c3a66f | 13780 | tg3_flag_set(tp, RGMII_INBAND_DISABLE); |
a9daf367 | 13781 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
63c3a66f | 13782 | tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); |
a9daf367 | 13783 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) |
63c3a66f | 13784 | tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); |
1da177e4 | 13785 | } |
05ac4cb7 | 13786 | done: |
63c3a66f | 13787 | if (tg3_flag(tp, WOL_CAP)) |
43067ed8 | 13788 | device_set_wakeup_enable(&tp->pdev->dev, |
63c3a66f | 13789 | tg3_flag(tp, WOL_ENABLE)); |
43067ed8 RW |
13790 | else |
13791 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
13792 | } |
13793 | ||
b2a5c19c MC |
13794 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
13795 | { | |
13796 | int i; | |
13797 | u32 val; | |
13798 | ||
13799 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
13800 | tw32(OTP_CTRL, cmd); | |
13801 | ||
13802 | /* Wait for up to 1 ms for command to execute. */ | |
13803 | for (i = 0; i < 100; i++) { | |
13804 | val = tr32(OTP_STATUS); | |
13805 | if (val & OTP_STATUS_CMD_DONE) | |
13806 | break; | |
13807 | udelay(10); | |
13808 | } | |
13809 | ||
13810 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
13811 | } | |
13812 | ||
13813 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
13814 | * configuration is a 32-bit value that straddles the alignment boundary. | |
13815 | * We do two 32-bit reads and then shift and merge the results. | |
13816 | */ | |
13817 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
13818 | { | |
13819 | u32 bhalf_otp, thalf_otp; | |
13820 | ||
13821 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
13822 | ||
13823 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
13824 | return 0; | |
13825 | ||
13826 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
13827 | ||
13828 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13829 | return 0; | |
13830 | ||
13831 | thalf_otp = tr32(OTP_READ_DATA); | |
13832 | ||
13833 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
13834 | ||
13835 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
13836 | return 0; | |
13837 | ||
13838 | bhalf_otp = tr32(OTP_READ_DATA); | |
13839 | ||
13840 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
13841 | } | |
13842 | ||
e256f8a3 MC |
13843 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
13844 | { | |
202ff1c2 | 13845 | u32 adv = ADVERTISED_Autoneg; |
e256f8a3 MC |
13846 | |
13847 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
13848 | adv |= ADVERTISED_1000baseT_Half | | |
13849 | ADVERTISED_1000baseT_Full; | |
13850 | ||
13851 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
13852 | adv |= ADVERTISED_100baseT_Half | | |
13853 | ADVERTISED_100baseT_Full | | |
13854 | ADVERTISED_10baseT_Half | | |
13855 | ADVERTISED_10baseT_Full | | |
13856 | ADVERTISED_TP; | |
13857 | else | |
13858 | adv |= ADVERTISED_FIBRE; | |
13859 | ||
13860 | tp->link_config.advertising = adv; | |
e740522e MC |
13861 | tp->link_config.speed = SPEED_UNKNOWN; |
13862 | tp->link_config.duplex = DUPLEX_UNKNOWN; | |
e256f8a3 | 13863 | tp->link_config.autoneg = AUTONEG_ENABLE; |
e740522e MC |
13864 | tp->link_config.active_speed = SPEED_UNKNOWN; |
13865 | tp->link_config.active_duplex = DUPLEX_UNKNOWN; | |
34655ad6 MC |
13866 | |
13867 | tp->old_link = -1; | |
e256f8a3 MC |
13868 | } |
13869 | ||
7d0c41ef MC |
13870 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
13871 | { | |
13872 | u32 hw_phy_id_1, hw_phy_id_2; | |
13873 | u32 hw_phy_id, hw_phy_id_masked; | |
13874 | int err; | |
1da177e4 | 13875 | |
e256f8a3 | 13876 | /* flow control autonegotiation is default behavior */ |
63c3a66f | 13877 | tg3_flag_set(tp, PAUSE_AUTONEG); |
e256f8a3 MC |
13878 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
13879 | ||
8151ad57 MC |
13880 | if (tg3_flag(tp, ENABLE_APE)) { |
13881 | switch (tp->pci_fn) { | |
13882 | case 0: | |
13883 | tp->phy_ape_lock = TG3_APE_LOCK_PHY0; | |
13884 | break; | |
13885 | case 1: | |
13886 | tp->phy_ape_lock = TG3_APE_LOCK_PHY1; | |
13887 | break; | |
13888 | case 2: | |
13889 | tp->phy_ape_lock = TG3_APE_LOCK_PHY2; | |
13890 | break; | |
13891 | case 3: | |
13892 | tp->phy_ape_lock = TG3_APE_LOCK_PHY3; | |
13893 | break; | |
13894 | } | |
13895 | } | |
13896 | ||
63c3a66f | 13897 | if (tg3_flag(tp, USE_PHYLIB)) |
b02fd9e3 MC |
13898 | return tg3_phy_init(tp); |
13899 | ||
1da177e4 | 13900 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 13901 | * firmware access to the PHY hardware. |
1da177e4 LT |
13902 | */ |
13903 | err = 0; | |
63c3a66f | 13904 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { |
79eb6904 | 13905 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
13906 | } else { |
13907 | /* Now read the physical PHY_ID from the chip and verify | |
13908 | * that it is sane. If it doesn't look good, we fall back | |
13909 | * to either the hard-coded table based PHY_ID and failing | |
13910 | * that the value found in the eeprom area. | |
13911 | */ | |
13912 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
13913 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
13914 | ||
13915 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
13916 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
13917 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
13918 | ||
79eb6904 | 13919 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
13920 | } |
13921 | ||
79eb6904 | 13922 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 13923 | tp->phy_id = hw_phy_id; |
79eb6904 | 13924 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13925 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 13926 | else |
f07e9af3 | 13927 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 13928 | } else { |
79eb6904 | 13929 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
13930 | /* Do nothing, phy ID already set up in |
13931 | * tg3_get_eeprom_hw_cfg(). | |
13932 | */ | |
1da177e4 LT |
13933 | } else { |
13934 | struct subsys_tbl_ent *p; | |
13935 | ||
13936 | /* No eeprom signature? Try the hardcoded | |
13937 | * subsys device table. | |
13938 | */ | |
24daf2b0 | 13939 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
13940 | if (!p) |
13941 | return -ENODEV; | |
13942 | ||
13943 | tp->phy_id = p->phy_id; | |
13944 | if (!tp->phy_id || | |
79eb6904 | 13945 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 13946 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
13947 | } |
13948 | } | |
13949 | ||
a6b68dab | 13950 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
5baa5e9a MC |
13951 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13952 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | |
13953 | (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
a6b68dab MC |
13954 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || |
13955 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
13956 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
13957 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
13958 | ||
e256f8a3 MC |
13959 | tg3_phy_init_link_config(tp); |
13960 | ||
f07e9af3 | 13961 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
63c3a66f JP |
13962 | !tg3_flag(tp, ENABLE_APE) && |
13963 | !tg3_flag(tp, ENABLE_ASF)) { | |
e2bf73e7 | 13964 | u32 bmsr, dummy; |
1da177e4 LT |
13965 | |
13966 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
13967 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
13968 | (bmsr & BMSR_LSTATUS)) | |
13969 | goto skip_phy_reset; | |
6aa20a22 | 13970 | |
1da177e4 LT |
13971 | err = tg3_phy_reset(tp); |
13972 | if (err) | |
13973 | return err; | |
13974 | ||
42b64a45 | 13975 | tg3_phy_set_wirespeed(tp); |
1da177e4 | 13976 | |
e2bf73e7 | 13977 | if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { |
42b64a45 MC |
13978 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, |
13979 | tp->link_config.flowctrl); | |
1da177e4 LT |
13980 | |
13981 | tg3_writephy(tp, MII_BMCR, | |
13982 | BMCR_ANENABLE | BMCR_ANRESTART); | |
13983 | } | |
1da177e4 LT |
13984 | } |
13985 | ||
13986 | skip_phy_reset: | |
79eb6904 | 13987 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
13988 | err = tg3_init_5401phy_dsp(tp); |
13989 | if (err) | |
13990 | return err; | |
1da177e4 | 13991 | |
1da177e4 LT |
13992 | err = tg3_init_5401phy_dsp(tp); |
13993 | } | |
13994 | ||
1da177e4 LT |
13995 | return err; |
13996 | } | |
13997 | ||
184b8904 | 13998 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 13999 | { |
a4a8bb15 | 14000 | u8 *vpd_data; |
4181b2c8 | 14001 | unsigned int block_end, rosize, len; |
535a490e | 14002 | u32 vpdlen; |
184b8904 | 14003 | int j, i = 0; |
a4a8bb15 | 14004 | |
535a490e | 14005 | vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); |
a4a8bb15 MC |
14006 | if (!vpd_data) |
14007 | goto out_no_vpd; | |
1da177e4 | 14008 | |
535a490e | 14009 | i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA); |
4181b2c8 MC |
14010 | if (i < 0) |
14011 | goto out_not_found; | |
1da177e4 | 14012 | |
4181b2c8 MC |
14013 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
14014 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
14015 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 14016 | |
535a490e | 14017 | if (block_end > vpdlen) |
4181b2c8 | 14018 | goto out_not_found; |
af2c6a4a | 14019 | |
184b8904 MC |
14020 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
14021 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
14022 | if (j > 0) { | |
14023 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
14024 | ||
14025 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
14026 | if (j + len > block_end || len != 4 || | |
14027 | memcmp(&vpd_data[j], "1028", 4)) | |
14028 | goto partno; | |
14029 | ||
14030 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
14031 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
14032 | if (j < 0) | |
14033 | goto partno; | |
14034 | ||
14035 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
14036 | ||
14037 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
14038 | if (j + len > block_end) | |
14039 | goto partno; | |
14040 | ||
14041 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
535a490e | 14042 | strncat(tp->fw_ver, " bc ", vpdlen - len - 1); |
184b8904 MC |
14043 | } |
14044 | ||
14045 | partno: | |
4181b2c8 MC |
14046 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
14047 | PCI_VPD_RO_KEYWORD_PARTNO); | |
14048 | if (i < 0) | |
14049 | goto out_not_found; | |
af2c6a4a | 14050 | |
4181b2c8 | 14051 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 14052 | |
4181b2c8 MC |
14053 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
14054 | if (len > TG3_BPN_SIZE || | |
535a490e | 14055 | (len + i) > vpdlen) |
4181b2c8 | 14056 | goto out_not_found; |
1da177e4 | 14057 | |
4181b2c8 | 14058 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 14059 | |
1da177e4 | 14060 | out_not_found: |
a4a8bb15 | 14061 | kfree(vpd_data); |
37a949c5 | 14062 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
14063 | return; |
14064 | ||
14065 | out_no_vpd: | |
37a949c5 | 14066 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
79d49695 MC |
14067 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
14068 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) | |
37a949c5 MC |
14069 | strcpy(tp->board_part_number, "BCM5717"); |
14070 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
14071 | strcpy(tp->board_part_number, "BCM5718"); | |
14072 | else | |
14073 | goto nomatch; | |
14074 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
14075 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
14076 | strcpy(tp->board_part_number, "BCM57780"); | |
14077 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
14078 | strcpy(tp->board_part_number, "BCM57760"); | |
14079 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
14080 | strcpy(tp->board_part_number, "BCM57790"); | |
14081 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
14082 | strcpy(tp->board_part_number, "BCM57788"); | |
14083 | else | |
14084 | goto nomatch; | |
14085 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
14086 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
14087 | strcpy(tp->board_part_number, "BCM57761"); | |
14088 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
14089 | strcpy(tp->board_part_number, "BCM57765"); | |
14090 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
14091 | strcpy(tp->board_part_number, "BCM57781"); | |
14092 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
14093 | strcpy(tp->board_part_number, "BCM57785"); | |
14094 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
14095 | strcpy(tp->board_part_number, "BCM57791"); | |
14096 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
14097 | strcpy(tp->board_part_number, "BCM57795"); | |
14098 | else | |
14099 | goto nomatch; | |
55086ad9 MC |
14100 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) { |
14101 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) | |
14102 | strcpy(tp->board_part_number, "BCM57762"); | |
14103 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) | |
14104 | strcpy(tp->board_part_number, "BCM57766"); | |
14105 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) | |
14106 | strcpy(tp->board_part_number, "BCM57782"); | |
14107 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) | |
14108 | strcpy(tp->board_part_number, "BCM57786"); | |
14109 | else | |
14110 | goto nomatch; | |
37a949c5 | 14111 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
b5d3772c | 14112 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
14113 | } else { |
14114 | nomatch: | |
b5d3772c | 14115 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 14116 | } |
1da177e4 LT |
14117 | } |
14118 | ||
9c8a620e MC |
14119 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
14120 | { | |
14121 | u32 val; | |
14122 | ||
e4f34110 | 14123 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 14124 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 14125 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
14126 | val != 0) |
14127 | return 0; | |
14128 | ||
14129 | return 1; | |
14130 | } | |
14131 | ||
acd9c119 MC |
14132 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
14133 | { | |
ff3a7cb2 | 14134 | u32 val, offset, start, ver_offset; |
75f9936e | 14135 | int i, dst_off; |
ff3a7cb2 | 14136 | bool newver = false; |
acd9c119 MC |
14137 | |
14138 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
14139 | tg3_nvram_read(tp, 0x4, &start)) | |
14140 | return; | |
14141 | ||
14142 | offset = tg3_nvram_logical_addr(tp, offset); | |
14143 | ||
ff3a7cb2 | 14144 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
14145 | return; |
14146 | ||
ff3a7cb2 MC |
14147 | if ((val & 0xfc000000) == 0x0c000000) { |
14148 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
14149 | return; |
14150 | ||
ff3a7cb2 MC |
14151 | if (val == 0) |
14152 | newver = true; | |
14153 | } | |
14154 | ||
75f9936e MC |
14155 | dst_off = strlen(tp->fw_ver); |
14156 | ||
ff3a7cb2 | 14157 | if (newver) { |
75f9936e MC |
14158 | if (TG3_VER_SIZE - dst_off < 16 || |
14159 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
14160 | return; |
14161 | ||
14162 | offset = offset + ver_offset - start; | |
14163 | for (i = 0; i < 16; i += 4) { | |
14164 | __be32 v; | |
14165 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
14166 | return; | |
14167 | ||
75f9936e | 14168 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
14169 | } |
14170 | } else { | |
14171 | u32 major, minor; | |
14172 | ||
14173 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
14174 | return; | |
14175 | ||
14176 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
14177 | TG3_NVM_BCVER_MAJSFT; | |
14178 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
14179 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
14180 | "v%d.%02d", major, minor); | |
acd9c119 MC |
14181 | } |
14182 | } | |
14183 | ||
a6f6cb1c MC |
14184 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
14185 | { | |
14186 | u32 val, major, minor; | |
14187 | ||
14188 | /* Use native endian representation */ | |
14189 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
14190 | return; | |
14191 | ||
14192 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
14193 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
14194 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
14195 | TG3_NVM_HWSB_CFG1_MINSFT; | |
14196 | ||
14197 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
14198 | } | |
14199 | ||
dfe00d7d MC |
14200 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
14201 | { | |
14202 | u32 offset, major, minor, build; | |
14203 | ||
75f9936e | 14204 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
14205 | |
14206 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
14207 | return; | |
14208 | ||
14209 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
14210 | case TG3_EEPROM_SB_REVISION_0: | |
14211 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
14212 | break; | |
14213 | case TG3_EEPROM_SB_REVISION_2: | |
14214 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
14215 | break; | |
14216 | case TG3_EEPROM_SB_REVISION_3: | |
14217 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
14218 | break; | |
a4153d40 MC |
14219 | case TG3_EEPROM_SB_REVISION_4: |
14220 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
14221 | break; | |
14222 | case TG3_EEPROM_SB_REVISION_5: | |
14223 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
14224 | break; | |
bba226ac MC |
14225 | case TG3_EEPROM_SB_REVISION_6: |
14226 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
14227 | break; | |
dfe00d7d MC |
14228 | default: |
14229 | return; | |
14230 | } | |
14231 | ||
e4f34110 | 14232 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
14233 | return; |
14234 | ||
14235 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
14236 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
14237 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
14238 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
14239 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
14240 | ||
14241 | if (minor > 99 || build > 26) | |
14242 | return; | |
14243 | ||
75f9936e MC |
14244 | offset = strlen(tp->fw_ver); |
14245 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
14246 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
14247 | |
14248 | if (build > 0) { | |
75f9936e MC |
14249 | offset = strlen(tp->fw_ver); |
14250 | if (offset < TG3_VER_SIZE - 1) | |
14251 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
14252 | } |
14253 | } | |
14254 | ||
acd9c119 | 14255 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
14256 | { |
14257 | u32 val, offset, start; | |
acd9c119 | 14258 | int i, vlen; |
9c8a620e MC |
14259 | |
14260 | for (offset = TG3_NVM_DIR_START; | |
14261 | offset < TG3_NVM_DIR_END; | |
14262 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 14263 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
14264 | return; |
14265 | ||
9c8a620e MC |
14266 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
14267 | break; | |
14268 | } | |
14269 | ||
14270 | if (offset == TG3_NVM_DIR_END) | |
14271 | return; | |
14272 | ||
63c3a66f | 14273 | if (!tg3_flag(tp, 5705_PLUS)) |
9c8a620e | 14274 | start = 0x08000000; |
e4f34110 | 14275 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
14276 | return; |
14277 | ||
e4f34110 | 14278 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 14279 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 14280 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
14281 | return; |
14282 | ||
14283 | offset += val - start; | |
14284 | ||
acd9c119 | 14285 | vlen = strlen(tp->fw_ver); |
9c8a620e | 14286 | |
acd9c119 MC |
14287 | tp->fw_ver[vlen++] = ','; |
14288 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
14289 | |
14290 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
14291 | __be32 v; |
14292 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
14293 | return; |
14294 | ||
b9fc7dc5 | 14295 | offset += sizeof(v); |
c4e6575c | 14296 | |
acd9c119 MC |
14297 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
14298 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 14299 | break; |
c4e6575c | 14300 | } |
9c8a620e | 14301 | |
acd9c119 MC |
14302 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
14303 | vlen += sizeof(v); | |
c4e6575c | 14304 | } |
acd9c119 MC |
14305 | } |
14306 | ||
165f4d1c | 14307 | static void __devinit tg3_probe_ncsi(struct tg3 *tp) |
7fd76445 | 14308 | { |
7fd76445 | 14309 | u32 apedata; |
7fd76445 MC |
14310 | |
14311 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
14312 | if (apedata != APE_SEG_SIG_MAGIC) | |
14313 | return; | |
14314 | ||
14315 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
14316 | if (!(apedata & APE_FW_STATUS_READY)) | |
14317 | return; | |
14318 | ||
165f4d1c MC |
14319 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) |
14320 | tg3_flag_set(tp, APE_HAS_NCSI); | |
14321 | } | |
14322 | ||
14323 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) | |
14324 | { | |
14325 | int vlen; | |
14326 | u32 apedata; | |
14327 | char *fwtype; | |
14328 | ||
7fd76445 MC |
14329 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); |
14330 | ||
165f4d1c | 14331 | if (tg3_flag(tp, APE_HAS_NCSI)) |
ecc79648 | 14332 | fwtype = "NCSI"; |
165f4d1c | 14333 | else |
ecc79648 MC |
14334 | fwtype = "DASH"; |
14335 | ||
7fd76445 MC |
14336 | vlen = strlen(tp->fw_ver); |
14337 | ||
ecc79648 MC |
14338 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
14339 | fwtype, | |
7fd76445 MC |
14340 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
14341 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
14342 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
14343 | (apedata & APE_FW_VERSION_BLDMSK)); | |
14344 | } | |
14345 | ||
acd9c119 MC |
14346 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
14347 | { | |
14348 | u32 val; | |
75f9936e | 14349 | bool vpd_vers = false; |
acd9c119 | 14350 | |
75f9936e MC |
14351 | if (tp->fw_ver[0] != 0) |
14352 | vpd_vers = true; | |
df259d8c | 14353 | |
63c3a66f | 14354 | if (tg3_flag(tp, NO_NVRAM)) { |
75f9936e | 14355 | strcat(tp->fw_ver, "sb"); |
df259d8c MC |
14356 | return; |
14357 | } | |
14358 | ||
acd9c119 MC |
14359 | if (tg3_nvram_read(tp, 0, &val)) |
14360 | return; | |
14361 | ||
14362 | if (val == TG3_EEPROM_MAGIC) | |
14363 | tg3_read_bc_ver(tp); | |
14364 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
14365 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
14366 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
14367 | tg3_read_hwsb_ver(tp); | |
acd9c119 | 14368 | |
165f4d1c MC |
14369 | if (tg3_flag(tp, ENABLE_ASF)) { |
14370 | if (tg3_flag(tp, ENABLE_APE)) { | |
14371 | tg3_probe_ncsi(tp); | |
14372 | if (!vpd_vers) | |
14373 | tg3_read_dash_ver(tp); | |
14374 | } else if (!vpd_vers) { | |
14375 | tg3_read_mgmtfw_ver(tp); | |
14376 | } | |
c9cab24e | 14377 | } |
9c8a620e MC |
14378 | |
14379 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; | |
c4e6575c MC |
14380 | } |
14381 | ||
7cb32cf2 MC |
14382 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
14383 | { | |
63c3a66f | 14384 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
de9f5230 | 14385 | return TG3_RX_RET_MAX_SIZE_5717; |
63c3a66f | 14386 | else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) |
de9f5230 | 14387 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 14388 | else |
de9f5230 | 14389 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
14390 | } |
14391 | ||
4143470c | 14392 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
14393 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
14394 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
14395 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
14396 | { }, | |
14397 | }; | |
14398 | ||
16c7fa7d MC |
14399 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
14400 | { | |
14401 | struct pci_dev *peer; | |
14402 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
14403 | ||
14404 | for (func = 0; func < 8; func++) { | |
14405 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
14406 | if (peer && peer != tp->pdev) | |
14407 | break; | |
14408 | pci_dev_put(peer); | |
14409 | } | |
14410 | /* 5704 can be configured in single-port mode, set peer to | |
14411 | * tp->pdev in that case. | |
14412 | */ | |
14413 | if (!peer) { | |
14414 | peer = tp->pdev; | |
14415 | return peer; | |
14416 | } | |
14417 | ||
14418 | /* | |
14419 | * We don't need to keep the refcount elevated; there's no way | |
14420 | * to remove one half of this device without removing the other | |
14421 | */ | |
14422 | pci_dev_put(peer); | |
14423 | ||
14424 | return peer; | |
14425 | } | |
14426 | ||
42b123b1 MC |
14427 | static void __devinit tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) |
14428 | { | |
14429 | tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; | |
14430 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { | |
14431 | u32 reg; | |
14432 | ||
14433 | /* All devices that use the alternate | |
14434 | * ASIC REV location have a CPMU. | |
14435 | */ | |
14436 | tg3_flag_set(tp, CPMU_PRESENT); | |
14437 | ||
14438 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
79d49695 | 14439 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || |
42b123b1 MC |
14440 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || |
14441 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
14442 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
14443 | reg = TG3PCI_GEN2_PRODID_ASICREV; | |
14444 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || | |
14445 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
14446 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
14447 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
14448 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
14449 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
14450 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || | |
14451 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || | |
14452 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || | |
14453 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) | |
14454 | reg = TG3PCI_GEN15_PRODID_ASICREV; | |
14455 | else | |
14456 | reg = TG3PCI_PRODID_ASICREV; | |
14457 | ||
14458 | pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); | |
14459 | } | |
14460 | ||
14461 | /* Wrong chip ID in 5752 A0. This code can be removed later | |
14462 | * as A0 is not in production. | |
14463 | */ | |
14464 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
14465 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
14466 | ||
79d49695 MC |
14467 | if (tp->pci_chip_rev_id == CHIPREV_ID_5717_C0) |
14468 | tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; | |
14469 | ||
42b123b1 MC |
14470 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
14471 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14472 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
14473 | tg3_flag_set(tp, 5717_PLUS); | |
14474 | ||
14475 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
14476 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) | |
14477 | tg3_flag_set(tp, 57765_CLASS); | |
14478 | ||
14479 | if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS)) | |
14480 | tg3_flag_set(tp, 57765_PLUS); | |
14481 | ||
14482 | /* Intentionally exclude ASIC_REV_5906 */ | |
14483 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
14484 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
14485 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
14486 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
14487 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
14488 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
14489 | tg3_flag(tp, 57765_PLUS)) | |
14490 | tg3_flag_set(tp, 5755_PLUS); | |
14491 | ||
14492 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || | |
14493 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) | |
14494 | tg3_flag_set(tp, 5780_CLASS); | |
14495 | ||
14496 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14497 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14498 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || | |
14499 | tg3_flag(tp, 5755_PLUS) || | |
14500 | tg3_flag(tp, 5780_CLASS)) | |
14501 | tg3_flag_set(tp, 5750_PLUS); | |
14502 | ||
14503 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || | |
14504 | tg3_flag(tp, 5750_PLUS)) | |
14505 | tg3_flag_set(tp, 5705_PLUS); | |
14506 | } | |
14507 | ||
3d567e0e NNS |
14508 | static bool tg3_10_100_only_device(struct tg3 *tp, |
14509 | const struct pci_device_id *ent) | |
14510 | { | |
14511 | u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK; | |
14512 | ||
14513 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14514 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14515 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) | |
14516 | return true; | |
14517 | ||
14518 | if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { | |
14519 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
14520 | if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) | |
14521 | return true; | |
14522 | } else { | |
14523 | return true; | |
14524 | } | |
14525 | } | |
14526 | ||
14527 | return false; | |
14528 | } | |
14529 | ||
14530 | static int __devinit tg3_get_invariants(struct tg3 *tp, | |
14531 | const struct pci_device_id *ent) | |
1da177e4 | 14532 | { |
1da177e4 | 14533 | u32 misc_ctrl_reg; |
1da177e4 LT |
14534 | u32 pci_state_reg, grc_misc_cfg; |
14535 | u32 val; | |
14536 | u16 pci_cmd; | |
5e7dfd0f | 14537 | int err; |
1da177e4 | 14538 | |
1da177e4 LT |
14539 | /* Force memory write invalidate off. If we leave it on, |
14540 | * then on 5700_BX chips we have to enable a workaround. | |
14541 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
14542 | * to match the cacheline size. The Broadcom driver have this | |
14543 | * workaround but turns MWI off all the times so never uses | |
14544 | * it. This seems to suggest that the workaround is insufficient. | |
14545 | */ | |
14546 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14547 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
14548 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14549 | ||
16821285 MC |
14550 | /* Important! -- Make sure register accesses are byteswapped |
14551 | * correctly. Also, for those chips that require it, make | |
14552 | * sure that indirect register accesses are enabled before | |
14553 | * the first operation. | |
1da177e4 LT |
14554 | */ |
14555 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14556 | &misc_ctrl_reg); | |
16821285 MC |
14557 | tp->misc_host_ctrl |= (misc_ctrl_reg & |
14558 | MISC_HOST_CTRL_CHIPREV); | |
14559 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14560 | tp->misc_host_ctrl); | |
1da177e4 | 14561 | |
42b123b1 | 14562 | tg3_detect_asic_rev(tp, misc_ctrl_reg); |
ff645bec | 14563 | |
6892914f MC |
14564 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
14565 | * we need to disable memory and use config. cycles | |
14566 | * only to access all registers. The 5702/03 chips | |
14567 | * can mistakenly decode the special cycles from the | |
14568 | * ICH chipsets as memory write cycles, causing corruption | |
14569 | * of register and memory space. Only certain ICH bridges | |
14570 | * will drive special cycles with non-zero data during the | |
14571 | * address phase which can fall within the 5703's address | |
14572 | * range. This is not an ICH bug as the PCI spec allows | |
14573 | * non-zero address during special cycles. However, only | |
14574 | * these ICH bridges are known to drive non-zero addresses | |
14575 | * during special cycles. | |
14576 | * | |
14577 | * Since special cycles do not cross PCI bridges, we only | |
14578 | * enable this workaround if the 5703 is on the secondary | |
14579 | * bus of these ICH bridges. | |
14580 | */ | |
14581 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
14582 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
14583 | static struct tg3_dev_id { | |
14584 | u32 vendor; | |
14585 | u32 device; | |
14586 | u32 rev; | |
14587 | } ich_chipsets[] = { | |
14588 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
14589 | PCI_ANY_ID }, | |
14590 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
14591 | PCI_ANY_ID }, | |
14592 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
14593 | 0xa }, | |
14594 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
14595 | PCI_ANY_ID }, | |
14596 | { }, | |
14597 | }; | |
14598 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
14599 | struct pci_dev *bridge = NULL; | |
14600 | ||
14601 | while (pci_id->vendor != 0) { | |
14602 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
14603 | bridge); | |
14604 | if (!bridge) { | |
14605 | pci_id++; | |
14606 | continue; | |
14607 | } | |
14608 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 14609 | if (bridge->revision > pci_id->rev) |
6892914f MC |
14610 | continue; |
14611 | } | |
14612 | if (bridge->subordinate && | |
14613 | (bridge->subordinate->number == | |
14614 | tp->pdev->bus->number)) { | |
63c3a66f | 14615 | tg3_flag_set(tp, ICH_WORKAROUND); |
6892914f MC |
14616 | pci_dev_put(bridge); |
14617 | break; | |
14618 | } | |
14619 | } | |
14620 | } | |
14621 | ||
6ff6f81d | 14622 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
41588ba1 MC |
14623 | static struct tg3_dev_id { |
14624 | u32 vendor; | |
14625 | u32 device; | |
14626 | } bridge_chipsets[] = { | |
14627 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
14628 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
14629 | { }, | |
14630 | }; | |
14631 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
14632 | struct pci_dev *bridge = NULL; | |
14633 | ||
14634 | while (pci_id->vendor != 0) { | |
14635 | bridge = pci_get_device(pci_id->vendor, | |
14636 | pci_id->device, | |
14637 | bridge); | |
14638 | if (!bridge) { | |
14639 | pci_id++; | |
14640 | continue; | |
14641 | } | |
14642 | if (bridge->subordinate && | |
14643 | (bridge->subordinate->number <= | |
14644 | tp->pdev->bus->number) && | |
b918c62e | 14645 | (bridge->subordinate->busn_res.end >= |
41588ba1 | 14646 | tp->pdev->bus->number)) { |
63c3a66f | 14647 | tg3_flag_set(tp, 5701_DMA_BUG); |
41588ba1 MC |
14648 | pci_dev_put(bridge); |
14649 | break; | |
14650 | } | |
14651 | } | |
14652 | } | |
14653 | ||
4a29cc2e MC |
14654 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
14655 | * DMA addresses > 40-bit. This bridge may have other additional | |
14656 | * 57xx devices behind it in some 4-port NIC designs for example. | |
14657 | * Any tg3 device found behind the bridge will also need the 40-bit | |
14658 | * DMA workaround. | |
14659 | */ | |
42b123b1 | 14660 | if (tg3_flag(tp, 5780_CLASS)) { |
63c3a66f | 14661 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4cf78e4f | 14662 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 14663 | } else { |
4a29cc2e MC |
14664 | struct pci_dev *bridge = NULL; |
14665 | ||
14666 | do { | |
14667 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
14668 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
14669 | bridge); | |
14670 | if (bridge && bridge->subordinate && | |
14671 | (bridge->subordinate->number <= | |
14672 | tp->pdev->bus->number) && | |
b918c62e | 14673 | (bridge->subordinate->busn_res.end >= |
4a29cc2e | 14674 | tp->pdev->bus->number)) { |
63c3a66f | 14675 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
4a29cc2e MC |
14676 | pci_dev_put(bridge); |
14677 | break; | |
14678 | } | |
14679 | } while (bridge); | |
14680 | } | |
4cf78e4f | 14681 | |
f6eb9b1f | 14682 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
3a1e19d3 | 14683 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) |
7544b097 MC |
14684 | tp->pdev_peer = tg3_find_peer(tp); |
14685 | ||
507399f1 | 14686 | /* Determine TSO capabilities */ |
a0512944 | 14687 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) |
4d163b75 | 14688 | ; /* Do nothing. HW bug. */ |
63c3a66f JP |
14689 | else if (tg3_flag(tp, 57765_PLUS)) |
14690 | tg3_flag_set(tp, HW_TSO_3); | |
14691 | else if (tg3_flag(tp, 5755_PLUS) || | |
e849cdc3 | 14692 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
63c3a66f JP |
14693 | tg3_flag_set(tp, HW_TSO_2); |
14694 | else if (tg3_flag(tp, 5750_PLUS)) { | |
14695 | tg3_flag_set(tp, HW_TSO_1); | |
14696 | tg3_flag_set(tp, TSO_BUG); | |
507399f1 MC |
14697 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && |
14698 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
63c3a66f | 14699 | tg3_flag_clear(tp, TSO_BUG); |
507399f1 MC |
14700 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14701 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
14702 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
63c3a66f | 14703 | tg3_flag_set(tp, TSO_BUG); |
507399f1 MC |
14704 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) |
14705 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
14706 | else | |
14707 | tp->fw_needed = FIRMWARE_TG3TSO; | |
14708 | } | |
14709 | ||
dabc5c67 | 14710 | /* Selectively allow TSO based on operating conditions */ |
6ff6f81d MC |
14711 | if (tg3_flag(tp, HW_TSO_1) || |
14712 | tg3_flag(tp, HW_TSO_2) || | |
14713 | tg3_flag(tp, HW_TSO_3) || | |
cf9ecf4b MC |
14714 | tp->fw_needed) { |
14715 | /* For firmware TSO, assume ASF is disabled. | |
14716 | * We'll disable TSO later if we discover ASF | |
14717 | * is enabled in tg3_get_eeprom_hw_cfg(). | |
14718 | */ | |
dabc5c67 | 14719 | tg3_flag_set(tp, TSO_CAPABLE); |
cf9ecf4b | 14720 | } else { |
dabc5c67 MC |
14721 | tg3_flag_clear(tp, TSO_CAPABLE); |
14722 | tg3_flag_clear(tp, TSO_BUG); | |
14723 | tp->fw_needed = NULL; | |
14724 | } | |
14725 | ||
14726 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
14727 | tp->fw_needed = FIRMWARE_TG3; | |
14728 | ||
507399f1 MC |
14729 | tp->irq_max = 1; |
14730 | ||
63c3a66f JP |
14731 | if (tg3_flag(tp, 5750_PLUS)) { |
14732 | tg3_flag_set(tp, SUPPORT_MSI); | |
7544b097 MC |
14733 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || |
14734 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
14735 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
14736 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
14737 | tp->pdev_peer == tp->pdev)) | |
63c3a66f | 14738 | tg3_flag_clear(tp, SUPPORT_MSI); |
7544b097 | 14739 | |
63c3a66f | 14740 | if (tg3_flag(tp, 5755_PLUS) || |
b5d3772c | 14741 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
63c3a66f | 14742 | tg3_flag_set(tp, 1SHOT_MSI); |
52c0fd83 | 14743 | } |
4f125f42 | 14744 | |
63c3a66f JP |
14745 | if (tg3_flag(tp, 57765_PLUS)) { |
14746 | tg3_flag_set(tp, SUPPORT_MSIX); | |
507399f1 MC |
14747 | tp->irq_max = TG3_IRQ_MAX_VECS; |
14748 | } | |
f6eb9b1f | 14749 | } |
0e1406dd | 14750 | |
9102426a MC |
14751 | tp->txq_max = 1; |
14752 | tp->rxq_max = 1; | |
14753 | if (tp->irq_max > 1) { | |
14754 | tp->rxq_max = TG3_RSS_MAX_NUM_QS; | |
14755 | tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS); | |
14756 | ||
14757 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14758 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
14759 | tp->txq_max = tp->irq_max - 1; | |
14760 | } | |
14761 | ||
b7abee6e MC |
14762 | if (tg3_flag(tp, 5755_PLUS) || |
14763 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
63c3a66f | 14764 | tg3_flag_set(tp, SHORT_DMA_BUG); |
f6eb9b1f | 14765 | |
e31aa987 | 14766 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
a4cb428d | 14767 | tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; |
e31aa987 | 14768 | |
fa6b2aae MC |
14769 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
14770 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14771 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
63c3a66f | 14772 | tg3_flag_set(tp, LRG_PROD_RING_CAP); |
de9f5230 | 14773 | |
63c3a66f | 14774 | if (tg3_flag(tp, 57765_PLUS) && |
a0512944 | 14775 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0) |
63c3a66f | 14776 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); |
b703df6f | 14777 | |
63c3a66f JP |
14778 | if (!tg3_flag(tp, 5705_PLUS) || |
14779 | tg3_flag(tp, 5780_CLASS) || | |
14780 | tg3_flag(tp, USE_JUMBO_BDFLAG)) | |
14781 | tg3_flag_set(tp, JUMBO_CAPABLE); | |
0f893dc6 | 14782 | |
52f4490c MC |
14783 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
14784 | &pci_state_reg); | |
14785 | ||
708ebb3a | 14786 | if (pci_is_pcie(tp->pdev)) { |
5e7dfd0f MC |
14787 | u16 lnkctl; |
14788 | ||
63c3a66f | 14789 | tg3_flag_set(tp, PCI_EXPRESS); |
5f5c51e3 | 14790 | |
0f49bfbd | 14791 | pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); |
5e7dfd0f | 14792 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { |
7196cd6c MC |
14793 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
14794 | ASIC_REV_5906) { | |
63c3a66f | 14795 | tg3_flag_clear(tp, HW_TSO_2); |
dabc5c67 | 14796 | tg3_flag_clear(tp, TSO_CAPABLE); |
7196cd6c | 14797 | } |
5e7dfd0f | 14798 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 14799 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
14800 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
14801 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
63c3a66f | 14802 | tg3_flag_set(tp, CLKREQ_BUG); |
614b0590 | 14803 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
63c3a66f | 14804 | tg3_flag_set(tp, L1PLLPD_EN); |
c7835a77 | 14805 | } |
52f4490c | 14806 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
708ebb3a JM |
14807 | /* BCM5785 devices are effectively PCIe devices, and should |
14808 | * follow PCIe codepaths, but do not have a PCIe capabilities | |
14809 | * section. | |
93a700a9 | 14810 | */ |
63c3a66f JP |
14811 | tg3_flag_set(tp, PCI_EXPRESS); |
14812 | } else if (!tg3_flag(tp, 5705_PLUS) || | |
14813 | tg3_flag(tp, 5780_CLASS)) { | |
52f4490c MC |
14814 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); |
14815 | if (!tp->pcix_cap) { | |
2445e461 MC |
14816 | dev_err(&tp->pdev->dev, |
14817 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
14818 | return -EIO; |
14819 | } | |
14820 | ||
14821 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
63c3a66f | 14822 | tg3_flag_set(tp, PCIX_MODE); |
52f4490c | 14823 | } |
1da177e4 | 14824 | |
399de50b MC |
14825 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
14826 | * reordering to the mailbox registers done by the host | |
14827 | * controller can cause major troubles. We read back from | |
14828 | * every mailbox register write to force the writes to be | |
14829 | * posted to the chip in order. | |
14830 | */ | |
4143470c | 14831 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
63c3a66f JP |
14832 | !tg3_flag(tp, PCI_EXPRESS)) |
14833 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
399de50b | 14834 | |
69fc4053 MC |
14835 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
14836 | &tp->pci_cacheline_sz); | |
14837 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
14838 | &tp->pci_lat_timer); | |
1da177e4 LT |
14839 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
14840 | tp->pci_lat_timer < 64) { | |
14841 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
14842 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
14843 | tp->pci_lat_timer); | |
1da177e4 LT |
14844 | } |
14845 | ||
16821285 MC |
14846 | /* Important! -- It is critical that the PCI-X hw workaround |
14847 | * situation is decided before the first MMIO register access. | |
14848 | */ | |
52f4490c MC |
14849 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
14850 | /* 5700 BX chips need to have their TX producer index | |
14851 | * mailboxes written twice to workaround a bug. | |
14852 | */ | |
63c3a66f | 14853 | tg3_flag_set(tp, TXD_MBOX_HWBUG); |
1da177e4 | 14854 | |
52f4490c | 14855 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
14856 | * |
14857 | * The workaround is to use indirect register accesses | |
14858 | * for all chip writes not to mailbox registers. | |
14859 | */ | |
63c3a66f | 14860 | if (tg3_flag(tp, PCIX_MODE)) { |
1da177e4 | 14861 | u32 pm_reg; |
1da177e4 | 14862 | |
63c3a66f | 14863 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
14864 | |
14865 | /* The chip can have it's power management PCI config | |
14866 | * space registers clobbered due to this bug. | |
14867 | * So explicitly force the chip into D0 here. | |
14868 | */ | |
9974a356 MC |
14869 | pci_read_config_dword(tp->pdev, |
14870 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
14871 | &pm_reg); |
14872 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
14873 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
14874 | pci_write_config_dword(tp->pdev, |
14875 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
14876 | pm_reg); |
14877 | ||
14878 | /* Also, force SERR#/PERR# in PCI command. */ | |
14879 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14880 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
14881 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14882 | } | |
14883 | } | |
14884 | ||
1da177e4 | 14885 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
63c3a66f | 14886 | tg3_flag_set(tp, PCI_HIGH_SPEED); |
1da177e4 | 14887 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) |
63c3a66f | 14888 | tg3_flag_set(tp, PCI_32BIT); |
1da177e4 LT |
14889 | |
14890 | /* Chip-specific fixup from Broadcom driver */ | |
14891 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
14892 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
14893 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
14894 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
14895 | } | |
14896 | ||
1ee582d8 | 14897 | /* Default fast path register access methods */ |
20094930 | 14898 | tp->read32 = tg3_read32; |
1ee582d8 | 14899 | tp->write32 = tg3_write32; |
09ee929c | 14900 | tp->read32_mbox = tg3_read32; |
20094930 | 14901 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
14902 | tp->write32_tx_mbox = tg3_write32; |
14903 | tp->write32_rx_mbox = tg3_write32; | |
14904 | ||
14905 | /* Various workaround register access methods */ | |
63c3a66f | 14906 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) |
1ee582d8 | 14907 | tp->write32 = tg3_write_indirect_reg32; |
98efd8a6 | 14908 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
63c3a66f | 14909 | (tg3_flag(tp, PCI_EXPRESS) && |
98efd8a6 MC |
14910 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { |
14911 | /* | |
14912 | * Back to back register writes can cause problems on these | |
14913 | * chips, the workaround is to read back all reg writes | |
14914 | * except those to mailbox regs. | |
14915 | * | |
14916 | * See tg3_write_indirect_reg32(). | |
14917 | */ | |
1ee582d8 | 14918 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
14919 | } |
14920 | ||
63c3a66f | 14921 | if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { |
1ee582d8 | 14922 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
63c3a66f | 14923 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
1ee582d8 MC |
14924 | tp->write32_rx_mbox = tg3_write_flush_reg32; |
14925 | } | |
20094930 | 14926 | |
63c3a66f | 14927 | if (tg3_flag(tp, ICH_WORKAROUND)) { |
6892914f MC |
14928 | tp->read32 = tg3_read_indirect_reg32; |
14929 | tp->write32 = tg3_write_indirect_reg32; | |
14930 | tp->read32_mbox = tg3_read_indirect_mbox; | |
14931 | tp->write32_mbox = tg3_write_indirect_mbox; | |
14932 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
14933 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
14934 | ||
14935 | iounmap(tp->regs); | |
22abe310 | 14936 | tp->regs = NULL; |
6892914f MC |
14937 | |
14938 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
14939 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
14940 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
14941 | } | |
b5d3772c MC |
14942 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14943 | tp->read32_mbox = tg3_read32_mbox_5906; | |
14944 | tp->write32_mbox = tg3_write32_mbox_5906; | |
14945 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
14946 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
14947 | } | |
6892914f | 14948 | |
bbadf503 | 14949 | if (tp->write32 == tg3_write_indirect_reg32 || |
63c3a66f | 14950 | (tg3_flag(tp, PCIX_MODE) && |
bbadf503 | 14951 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
f49639e6 | 14952 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
63c3a66f | 14953 | tg3_flag_set(tp, SRAM_USE_CONFIG); |
bbadf503 | 14954 | |
16821285 MC |
14955 | /* The memory arbiter has to be enabled in order for SRAM accesses |
14956 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
14957 | * sure it is enabled, but other entities such as system netboot | |
14958 | * code might disable it. | |
14959 | */ | |
14960 | val = tr32(MEMARB_MODE); | |
14961 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
14962 | ||
9dc5e342 MC |
14963 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; |
14964 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
14965 | tg3_flag(tp, 5780_CLASS)) { | |
14966 | if (tg3_flag(tp, PCIX_MODE)) { | |
14967 | pci_read_config_dword(tp->pdev, | |
14968 | tp->pcix_cap + PCI_X_STATUS, | |
14969 | &val); | |
14970 | tp->pci_fn = val & 0x7; | |
14971 | } | |
14972 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
14973 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | |
14974 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == | |
14975 | NIC_SRAM_CPMUSTAT_SIG) { | |
14976 | tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717; | |
14977 | tp->pci_fn = tp->pci_fn ? 1 : 0; | |
14978 | } | |
14979 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
14980 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
14981 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | |
14982 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == | |
14983 | NIC_SRAM_CPMUSTAT_SIG) { | |
14984 | tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> | |
14985 | TG3_CPMU_STATUS_FSHFT_5719; | |
14986 | } | |
69f11c99 MC |
14987 | } |
14988 | ||
7d0c41ef | 14989 | /* Get eeprom hw config before calling tg3_set_power_state(). |
63c3a66f | 14990 | * In particular, the TG3_FLAG_IS_NIC flag must be |
7d0c41ef MC |
14991 | * determined before calling tg3_set_power_state() so that |
14992 | * we know whether or not to switch out of Vaux power. | |
14993 | * When the flag is set, it means that GPIO1 is used for eeprom | |
14994 | * write protect and also implies that it is a LOM where GPIOs | |
14995 | * are not used to switch power. | |
6aa20a22 | 14996 | */ |
7d0c41ef MC |
14997 | tg3_get_eeprom_hw_cfg(tp); |
14998 | ||
cf9ecf4b MC |
14999 | if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) { |
15000 | tg3_flag_clear(tp, TSO_CAPABLE); | |
15001 | tg3_flag_clear(tp, TSO_BUG); | |
15002 | tp->fw_needed = NULL; | |
15003 | } | |
15004 | ||
63c3a66f | 15005 | if (tg3_flag(tp, ENABLE_APE)) { |
0d3031d9 MC |
15006 | /* Allow reads and writes to the |
15007 | * APE register and memory space. | |
15008 | */ | |
15009 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
15010 | PCISTATE_ALLOW_APE_SHMEM_WR | |
15011 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
15012 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
15013 | pci_state_reg); | |
c9cab24e MC |
15014 | |
15015 | tg3_ape_lock_init(tp); | |
0d3031d9 MC |
15016 | } |
15017 | ||
16821285 MC |
15018 | /* Set up tp->grc_local_ctrl before calling |
15019 | * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high | |
15020 | * will bring 5700's external PHY out of reset. | |
314fba34 MC |
15021 | * It is also used as eeprom write protect on LOMs. |
15022 | */ | |
15023 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
6ff6f81d | 15024 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
63c3a66f | 15025 | tg3_flag(tp, EEPROM_WRITE_PROT)) |
314fba34 MC |
15026 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
15027 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
15028 | /* Unused GPIO3 must be driven as output on 5752 because there |
15029 | * are no pull-up resistors on unused GPIO pins. | |
15030 | */ | |
15031 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
15032 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 15033 | |
321d32a0 | 15034 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd | 15035 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
55086ad9 | 15036 | tg3_flag(tp, 57765_CLASS)) |
af36e6b6 MC |
15037 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
15038 | ||
8d519ab2 MC |
15039 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
15040 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
15041 | /* Turn off the debug UART. */ |
15042 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
63c3a66f | 15043 | if (tg3_flag(tp, IS_NIC)) |
5f0c4a3c MC |
15044 | /* Keep VMain power. */ |
15045 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
15046 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
15047 | } | |
15048 | ||
16821285 MC |
15049 | /* Switch out of Vaux if it is a NIC */ |
15050 | tg3_pwrsrc_switch_to_vmain(tp); | |
1da177e4 | 15051 | |
1da177e4 LT |
15052 | /* Derive initial jumbo mode from MTU assigned in |
15053 | * ether_setup() via the alloc_etherdev() call | |
15054 | */ | |
63c3a66f JP |
15055 | if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) |
15056 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
1da177e4 LT |
15057 | |
15058 | /* Determine WakeOnLan speed to use. */ | |
15059 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
15060 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
15061 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
15062 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
63c3a66f | 15063 | tg3_flag_clear(tp, WOL_SPEED_100MB); |
1da177e4 | 15064 | } else { |
63c3a66f | 15065 | tg3_flag_set(tp, WOL_SPEED_100MB); |
1da177e4 LT |
15066 | } |
15067 | ||
7f97a4bd | 15068 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 15069 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 15070 | |
1da177e4 | 15071 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
6ff6f81d MC |
15072 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
15073 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
1da177e4 | 15074 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && |
747e8f8b | 15075 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
15076 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
15077 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
15078 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
15079 | |
15080 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
15081 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 15082 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 15083 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 15084 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 15085 | |
63c3a66f | 15086 | if (tg3_flag(tp, 5705_PLUS) && |
f07e9af3 | 15087 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 15088 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 15089 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
63c3a66f | 15090 | !tg3_flag(tp, 57765_PLUS)) { |
c424cb24 | 15091 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 15092 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
15093 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
15094 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
15095 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
15096 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 15097 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 15098 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 15099 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 15100 | } else |
f07e9af3 | 15101 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 15102 | } |
1da177e4 | 15103 | |
b2a5c19c MC |
15104 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
15105 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
15106 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
15107 | if (tp->phy_otp == 0) | |
15108 | tp->phy_otp = TG3_OTP_DEFAULT; | |
15109 | } | |
15110 | ||
63c3a66f | 15111 | if (tg3_flag(tp, CPMU_PRESENT)) |
8ef21428 MC |
15112 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
15113 | else | |
15114 | tp->mi_mode = MAC_MI_MODE_BASE; | |
15115 | ||
1da177e4 | 15116 | tp->coalesce_mode = 0; |
1da177e4 LT |
15117 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
15118 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
15119 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
15120 | ||
4d958473 MC |
15121 | /* Set these bits to enable statistics workaround. */ |
15122 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
15123 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
15124 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
15125 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
15126 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
15127 | } | |
15128 | ||
321d32a0 MC |
15129 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
15130 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
63c3a66f | 15131 | tg3_flag_set(tp, USE_PHYLIB); |
57e6983c | 15132 | |
158d7abd MC |
15133 | err = tg3_mdio_init(tp); |
15134 | if (err) | |
15135 | return err; | |
1da177e4 LT |
15136 | |
15137 | /* Initialize data/descriptor byte/word swapping. */ | |
15138 | val = tr32(GRC_MODE); | |
f2096f94 MC |
15139 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
15140 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
15141 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
15142 | GRC_MODE_B2HRX_ENABLE | | |
15143 | GRC_MODE_HTX2B_ENABLE | | |
15144 | GRC_MODE_HOST_STACKUP); | |
15145 | else | |
15146 | val &= GRC_MODE_HOST_STACKUP; | |
15147 | ||
1da177e4 LT |
15148 | tw32(GRC_MODE, val | tp->grc_mode); |
15149 | ||
15150 | tg3_switch_clocks(tp); | |
15151 | ||
15152 | /* Clear this out for sanity. */ | |
15153 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
15154 | ||
15155 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
15156 | &pci_state_reg); | |
15157 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
63c3a66f | 15158 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { |
1da177e4 LT |
15159 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); |
15160 | ||
15161 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
15162 | chiprevid == CHIPREV_ID_5701_B0 || | |
15163 | chiprevid == CHIPREV_ID_5701_B2 || | |
15164 | chiprevid == CHIPREV_ID_5701_B5) { | |
15165 | void __iomem *sram_base; | |
15166 | ||
15167 | /* Write some dummy words into the SRAM status block | |
15168 | * area, see if it reads back correctly. If the return | |
15169 | * value is bad, force enable the PCIX workaround. | |
15170 | */ | |
15171 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
15172 | ||
15173 | writel(0x00000000, sram_base); | |
15174 | writel(0x00000000, sram_base + 4); | |
15175 | writel(0xffffffff, sram_base + 4); | |
15176 | if (readl(sram_base) != 0x00000000) | |
63c3a66f | 15177 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
1da177e4 LT |
15178 | } |
15179 | } | |
15180 | ||
15181 | udelay(50); | |
15182 | tg3_nvram_init(tp); | |
15183 | ||
15184 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
15185 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
15186 | ||
1da177e4 LT |
15187 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
15188 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
15189 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
63c3a66f | 15190 | tg3_flag_set(tp, IS_5788); |
1da177e4 | 15191 | |
63c3a66f | 15192 | if (!tg3_flag(tp, IS_5788) && |
6ff6f81d | 15193 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
63c3a66f JP |
15194 | tg3_flag_set(tp, TAGGED_STATUS); |
15195 | if (tg3_flag(tp, TAGGED_STATUS)) { | |
fac9b83e DM |
15196 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | |
15197 | HOSTCC_MODE_CLRTICK_TXBD); | |
15198 | ||
15199 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
15200 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
15201 | tp->misc_host_ctrl); | |
15202 | } | |
15203 | ||
3bda1258 | 15204 | /* Preserve the APE MAC_MODE bits */ |
63c3a66f | 15205 | if (tg3_flag(tp, ENABLE_APE)) |
d2394e6b | 15206 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 | 15207 | else |
6e01b20b | 15208 | tp->mac_mode = 0; |
3bda1258 | 15209 | |
3d567e0e | 15210 | if (tg3_10_100_only_device(tp, ent)) |
f07e9af3 | 15211 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; |
1da177e4 LT |
15212 | |
15213 | err = tg3_phy_probe(tp); | |
15214 | if (err) { | |
2445e461 | 15215 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 15216 | /* ... but do not return immediately ... */ |
b02fd9e3 | 15217 | tg3_mdio_fini(tp); |
1da177e4 LT |
15218 | } |
15219 | ||
184b8904 | 15220 | tg3_read_vpd(tp); |
c4e6575c | 15221 | tg3_read_fw_ver(tp); |
1da177e4 | 15222 | |
f07e9af3 MC |
15223 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
15224 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
15225 | } else { |
15226 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 15227 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 15228 | else |
f07e9af3 | 15229 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
15230 | } |
15231 | ||
15232 | /* 5700 {AX,BX} chips have a broken status block link | |
15233 | * change bit implementation, so we must use the | |
15234 | * status register in those cases. | |
15235 | */ | |
15236 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
63c3a66f | 15237 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 | 15238 | else |
63c3a66f | 15239 | tg3_flag_clear(tp, USE_LINKCHG_REG); |
1da177e4 LT |
15240 | |
15241 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
15242 | * have to force the link status polling mechanism based | |
15243 | * upon subsystem IDs. | |
15244 | */ | |
15245 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 15246 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
15247 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
15248 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
63c3a66f | 15249 | tg3_flag_set(tp, USE_LINKCHG_REG); |
1da177e4 LT |
15250 | } |
15251 | ||
15252 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 15253 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
63c3a66f | 15254 | tg3_flag_set(tp, POLL_SERDES); |
1da177e4 | 15255 | else |
63c3a66f | 15256 | tg3_flag_clear(tp, POLL_SERDES); |
1da177e4 | 15257 | |
9205fd9c | 15258 | tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; |
d2757fc4 | 15259 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 15260 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
63c3a66f | 15261 | tg3_flag(tp, PCIX_MODE)) { |
9205fd9c | 15262 | tp->rx_offset = NET_SKB_PAD; |
d2757fc4 | 15263 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 15264 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
15265 | #endif |
15266 | } | |
1da177e4 | 15267 | |
2c49a44d MC |
15268 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
15269 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
15270 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
15271 | ||
2c49a44d | 15272 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
15273 | |
15274 | /* Increment the rx prod index on the rx std ring by at most | |
15275 | * 8 for these chips to workaround hw errata. | |
15276 | */ | |
15277 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
15278 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
15279 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
15280 | tp->rx_std_max_post = 8; | |
15281 | ||
63c3a66f | 15282 | if (tg3_flag(tp, ASPM_WORKAROUND)) |
8ed5d97e MC |
15283 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & |
15284 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
15285 | ||
1da177e4 LT |
15286 | return err; |
15287 | } | |
15288 | ||
49b6e95f | 15289 | #ifdef CONFIG_SPARC |
1da177e4 LT |
15290 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
15291 | { | |
15292 | struct net_device *dev = tp->dev; | |
15293 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 15294 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 15295 | const unsigned char *addr; |
49b6e95f DM |
15296 | int len; |
15297 | ||
15298 | addr = of_get_property(dp, "local-mac-address", &len); | |
15299 | if (addr && len == 6) { | |
15300 | memcpy(dev->dev_addr, addr, 6); | |
15301 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
15302 | return 0; | |
1da177e4 LT |
15303 | } |
15304 | return -ENODEV; | |
15305 | } | |
15306 | ||
15307 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
15308 | { | |
15309 | struct net_device *dev = tp->dev; | |
15310 | ||
15311 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 15312 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
15313 | return 0; |
15314 | } | |
15315 | #endif | |
15316 | ||
15317 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
15318 | { | |
15319 | struct net_device *dev = tp->dev; | |
15320 | u32 hi, lo, mac_offset; | |
008652b3 | 15321 | int addr_ok = 0; |
1da177e4 | 15322 | |
49b6e95f | 15323 | #ifdef CONFIG_SPARC |
1da177e4 LT |
15324 | if (!tg3_get_macaddr_sparc(tp)) |
15325 | return 0; | |
15326 | #endif | |
15327 | ||
15328 | mac_offset = 0x7c; | |
6ff6f81d | 15329 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
63c3a66f | 15330 | tg3_flag(tp, 5780_CLASS)) { |
1da177e4 LT |
15331 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
15332 | mac_offset = 0xcc; | |
15333 | if (tg3_nvram_lock(tp)) | |
15334 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
15335 | else | |
15336 | tg3_nvram_unlock(tp); | |
63c3a66f | 15337 | } else if (tg3_flag(tp, 5717_PLUS)) { |
69f11c99 | 15338 | if (tp->pci_fn & 1) |
a1b950d5 | 15339 | mac_offset = 0xcc; |
69f11c99 | 15340 | if (tp->pci_fn > 1) |
a50d0796 | 15341 | mac_offset += 0x18c; |
a1b950d5 | 15342 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 15343 | mac_offset = 0x10; |
1da177e4 LT |
15344 | |
15345 | /* First try to get it from MAC address mailbox. */ | |
15346 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
15347 | if ((hi >> 16) == 0x484b) { | |
15348 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
15349 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
15350 | ||
15351 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
15352 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
15353 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
15354 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
15355 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 15356 | |
008652b3 MC |
15357 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
15358 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
15359 | } | |
15360 | if (!addr_ok) { | |
15361 | /* Next, try NVRAM. */ | |
63c3a66f | 15362 | if (!tg3_flag(tp, NO_NVRAM) && |
df259d8c | 15363 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && |
6d348f2c | 15364 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
15365 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
15366 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
15367 | } |
15368 | /* Finally just fetch it out of the MAC control regs. */ | |
15369 | else { | |
15370 | hi = tr32(MAC_ADDR_0_HIGH); | |
15371 | lo = tr32(MAC_ADDR_0_LOW); | |
15372 | ||
15373 | dev->dev_addr[5] = lo & 0xff; | |
15374 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
15375 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
15376 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
15377 | dev->dev_addr[1] = hi & 0xff; | |
15378 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
15379 | } | |
1da177e4 LT |
15380 | } |
15381 | ||
15382 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 15383 | #ifdef CONFIG_SPARC |
1da177e4 LT |
15384 | if (!tg3_get_default_macaddr_sparc(tp)) |
15385 | return 0; | |
15386 | #endif | |
15387 | return -EINVAL; | |
15388 | } | |
2ff43697 | 15389 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
15390 | return 0; |
15391 | } | |
15392 | ||
59e6b434 DM |
15393 | #define BOUNDARY_SINGLE_CACHELINE 1 |
15394 | #define BOUNDARY_MULTI_CACHELINE 2 | |
15395 | ||
15396 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
15397 | { | |
15398 | int cacheline_size; | |
15399 | u8 byte; | |
15400 | int goal; | |
15401 | ||
15402 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
15403 | if (byte == 0) | |
15404 | cacheline_size = 1024; | |
15405 | else | |
15406 | cacheline_size = (int) byte * 4; | |
15407 | ||
15408 | /* On 5703 and later chips, the boundary bits have no | |
15409 | * effect. | |
15410 | */ | |
15411 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
15412 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
63c3a66f | 15413 | !tg3_flag(tp, PCI_EXPRESS)) |
59e6b434 DM |
15414 | goto out; |
15415 | ||
15416 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
15417 | goal = BOUNDARY_MULTI_CACHELINE; | |
15418 | #else | |
15419 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
15420 | goal = BOUNDARY_SINGLE_CACHELINE; | |
15421 | #else | |
15422 | goal = 0; | |
15423 | #endif | |
15424 | #endif | |
15425 | ||
63c3a66f | 15426 | if (tg3_flag(tp, 57765_PLUS)) { |
cbf9ca6c MC |
15427 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
15428 | goto out; | |
15429 | } | |
15430 | ||
59e6b434 DM |
15431 | if (!goal) |
15432 | goto out; | |
15433 | ||
15434 | /* PCI controllers on most RISC systems tend to disconnect | |
15435 | * when a device tries to burst across a cache-line boundary. | |
15436 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
15437 | * | |
15438 | * Unfortunately, for PCI-E there are only limited | |
15439 | * write-side controls for this, and thus for reads | |
15440 | * we will still get the disconnects. We'll also waste | |
15441 | * these PCI cycles for both read and write for chips | |
15442 | * other than 5700 and 5701 which do not implement the | |
15443 | * boundary bits. | |
15444 | */ | |
63c3a66f | 15445 | if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
15446 | switch (cacheline_size) { |
15447 | case 16: | |
15448 | case 32: | |
15449 | case 64: | |
15450 | case 128: | |
15451 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15452 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
15453 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
15454 | } else { | |
15455 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
15456 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
15457 | } | |
15458 | break; | |
15459 | ||
15460 | case 256: | |
15461 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
15462 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
15463 | break; | |
15464 | ||
15465 | default: | |
15466 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
15467 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
15468 | break; | |
855e1111 | 15469 | } |
63c3a66f | 15470 | } else if (tg3_flag(tp, PCI_EXPRESS)) { |
59e6b434 DM |
15471 | switch (cacheline_size) { |
15472 | case 16: | |
15473 | case 32: | |
15474 | case 64: | |
15475 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15476 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
15477 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
15478 | break; | |
15479 | } | |
15480 | /* fallthrough */ | |
15481 | case 128: | |
15482 | default: | |
15483 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
15484 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
15485 | break; | |
855e1111 | 15486 | } |
59e6b434 DM |
15487 | } else { |
15488 | switch (cacheline_size) { | |
15489 | case 16: | |
15490 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15491 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
15492 | DMA_RWCTRL_WRITE_BNDRY_16); | |
15493 | break; | |
15494 | } | |
15495 | /* fallthrough */ | |
15496 | case 32: | |
15497 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15498 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
15499 | DMA_RWCTRL_WRITE_BNDRY_32); | |
15500 | break; | |
15501 | } | |
15502 | /* fallthrough */ | |
15503 | case 64: | |
15504 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15505 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
15506 | DMA_RWCTRL_WRITE_BNDRY_64); | |
15507 | break; | |
15508 | } | |
15509 | /* fallthrough */ | |
15510 | case 128: | |
15511 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
15512 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
15513 | DMA_RWCTRL_WRITE_BNDRY_128); | |
15514 | break; | |
15515 | } | |
15516 | /* fallthrough */ | |
15517 | case 256: | |
15518 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
15519 | DMA_RWCTRL_WRITE_BNDRY_256); | |
15520 | break; | |
15521 | case 512: | |
15522 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
15523 | DMA_RWCTRL_WRITE_BNDRY_512); | |
15524 | break; | |
15525 | case 1024: | |
15526 | default: | |
15527 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
15528 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
15529 | break; | |
855e1111 | 15530 | } |
59e6b434 DM |
15531 | } |
15532 | ||
15533 | out: | |
15534 | return val; | |
15535 | } | |
15536 | ||
1da177e4 LT |
15537 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
15538 | { | |
15539 | struct tg3_internal_buffer_desc test_desc; | |
15540 | u32 sram_dma_descs; | |
15541 | int i, ret; | |
15542 | ||
15543 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
15544 | ||
15545 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
15546 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
15547 | tw32(RDMAC_STATUS, 0); | |
15548 | tw32(WDMAC_STATUS, 0); | |
15549 | ||
15550 | tw32(BUFMGR_MODE, 0); | |
15551 | tw32(FTQ_RESET, 0); | |
15552 | ||
15553 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
15554 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
15555 | test_desc.nic_mbuf = 0x00002100; | |
15556 | test_desc.len = size; | |
15557 | ||
15558 | /* | |
15559 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
15560 | * the *second* time the tg3 driver was getting loaded after an | |
15561 | * initial scan. | |
15562 | * | |
15563 | * Broadcom tells me: | |
15564 | * ...the DMA engine is connected to the GRC block and a DMA | |
15565 | * reset may affect the GRC block in some unpredictable way... | |
15566 | * The behavior of resets to individual blocks has not been tested. | |
15567 | * | |
15568 | * Broadcom noted the GRC reset will also reset all sub-components. | |
15569 | */ | |
15570 | if (to_device) { | |
15571 | test_desc.cqid_sqid = (13 << 8) | 2; | |
15572 | ||
15573 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
15574 | udelay(40); | |
15575 | } else { | |
15576 | test_desc.cqid_sqid = (16 << 8) | 7; | |
15577 | ||
15578 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
15579 | udelay(40); | |
15580 | } | |
15581 | test_desc.flags = 0x00000005; | |
15582 | ||
15583 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
15584 | u32 val; | |
15585 | ||
15586 | val = *(((u32 *)&test_desc) + i); | |
15587 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
15588 | sram_dma_descs + (i * sizeof(u32))); | |
15589 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
15590 | } | |
15591 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
15592 | ||
859a5887 | 15593 | if (to_device) |
1da177e4 | 15594 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 15595 | else |
1da177e4 | 15596 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
15597 | |
15598 | ret = -ENODEV; | |
15599 | for (i = 0; i < 40; i++) { | |
15600 | u32 val; | |
15601 | ||
15602 | if (to_device) | |
15603 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
15604 | else | |
15605 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
15606 | if ((val & 0xffff) == sram_dma_descs) { | |
15607 | ret = 0; | |
15608 | break; | |
15609 | } | |
15610 | ||
15611 | udelay(100); | |
15612 | } | |
15613 | ||
15614 | return ret; | |
15615 | } | |
15616 | ||
ded7340d | 15617 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 15618 | |
4143470c | 15619 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
15620 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
15621 | { }, | |
15622 | }; | |
15623 | ||
1da177e4 LT |
15624 | static int __devinit tg3_test_dma(struct tg3 *tp) |
15625 | { | |
15626 | dma_addr_t buf_dma; | |
59e6b434 | 15627 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 15628 | int ret = 0; |
1da177e4 | 15629 | |
4bae65c8 MC |
15630 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
15631 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
15632 | if (!buf) { |
15633 | ret = -ENOMEM; | |
15634 | goto out_nofree; | |
15635 | } | |
15636 | ||
15637 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
15638 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
15639 | ||
59e6b434 | 15640 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 15641 | |
63c3a66f | 15642 | if (tg3_flag(tp, 57765_PLUS)) |
cbf9ca6c MC |
15643 | goto out; |
15644 | ||
63c3a66f | 15645 | if (tg3_flag(tp, PCI_EXPRESS)) { |
1da177e4 LT |
15646 | /* DMA read watermark not used on PCIE */ |
15647 | tp->dma_rwctrl |= 0x00180000; | |
63c3a66f | 15648 | } else if (!tg3_flag(tp, PCIX_MODE)) { |
85e94ced MC |
15649 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
15650 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
15651 | tp->dma_rwctrl |= 0x003f0000; |
15652 | else | |
15653 | tp->dma_rwctrl |= 0x003f000f; | |
15654 | } else { | |
15655 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
15656 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
15657 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 15658 | u32 read_water = 0x7; |
1da177e4 | 15659 | |
4a29cc2e MC |
15660 | /* If the 5704 is behind the EPB bridge, we can |
15661 | * do the less restrictive ONE_DMA workaround for | |
15662 | * better performance. | |
15663 | */ | |
63c3a66f | 15664 | if (tg3_flag(tp, 40BIT_DMA_BUG) && |
4a29cc2e MC |
15665 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
15666 | tp->dma_rwctrl |= 0x8000; | |
15667 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
15668 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
15669 | ||
49afdeb6 MC |
15670 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
15671 | read_water = 4; | |
59e6b434 | 15672 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
15673 | tp->dma_rwctrl |= |
15674 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
15675 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
15676 | (1 << 23); | |
4cf78e4f MC |
15677 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
15678 | /* 5780 always in PCIX mode */ | |
15679 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
15680 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
15681 | /* 5714 always in PCIX mode */ | |
15682 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
15683 | } else { |
15684 | tp->dma_rwctrl |= 0x001b000f; | |
15685 | } | |
15686 | } | |
15687 | ||
15688 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
15689 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
15690 | tp->dma_rwctrl &= 0xfffffff0; | |
15691 | ||
15692 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
15693 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
15694 | /* Remove this if it causes problems for some boards. */ | |
15695 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
15696 | ||
15697 | /* On 5700/5701 chips, we need to set this bit. | |
15698 | * Otherwise the chip will issue cacheline transactions | |
15699 | * to streamable DMA memory with not all the byte | |
15700 | * enables turned on. This is an error on several | |
15701 | * RISC PCI controllers, in particular sparc64. | |
15702 | * | |
15703 | * On 5703/5704 chips, this bit has been reassigned | |
15704 | * a different meaning. In particular, it is used | |
15705 | * on those chips to enable a PCI-X workaround. | |
15706 | */ | |
15707 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
15708 | } | |
15709 | ||
15710 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15711 | ||
15712 | #if 0 | |
15713 | /* Unneeded, already done by tg3_get_invariants. */ | |
15714 | tg3_switch_clocks(tp); | |
15715 | #endif | |
15716 | ||
1da177e4 LT |
15717 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
15718 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
15719 | goto out; | |
15720 | ||
59e6b434 DM |
15721 | /* It is best to perform DMA test with maximum write burst size |
15722 | * to expose the 5700/5701 write DMA bug. | |
15723 | */ | |
15724 | saved_dma_rwctrl = tp->dma_rwctrl; | |
15725 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
15726 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15727 | ||
1da177e4 LT |
15728 | while (1) { |
15729 | u32 *p = buf, i; | |
15730 | ||
15731 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
15732 | p[i] = i; | |
15733 | ||
15734 | /* Send the buffer to the chip. */ | |
15735 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
15736 | if (ret) { | |
2445e461 MC |
15737 | dev_err(&tp->pdev->dev, |
15738 | "%s: Buffer write failed. err = %d\n", | |
15739 | __func__, ret); | |
1da177e4 LT |
15740 | break; |
15741 | } | |
15742 | ||
15743 | #if 0 | |
15744 | /* validate data reached card RAM correctly. */ | |
15745 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
15746 | u32 val; | |
15747 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
15748 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
15749 | dev_err(&tp->pdev->dev, |
15750 | "%s: Buffer corrupted on device! " | |
15751 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
15752 | /* ret = -ENODEV here? */ |
15753 | } | |
15754 | p[i] = 0; | |
15755 | } | |
15756 | #endif | |
15757 | /* Now read it back. */ | |
15758 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
15759 | if (ret) { | |
5129c3a3 MC |
15760 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
15761 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
15762 | break; |
15763 | } | |
15764 | ||
15765 | /* Verify it. */ | |
15766 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
15767 | if (p[i] == i) | |
15768 | continue; | |
15769 | ||
59e6b434 DM |
15770 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
15771 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
15772 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
15773 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
15774 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
15775 | break; | |
15776 | } else { | |
2445e461 MC |
15777 | dev_err(&tp->pdev->dev, |
15778 | "%s: Buffer corrupted on read back! " | |
15779 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
15780 | ret = -ENODEV; |
15781 | goto out; | |
15782 | } | |
15783 | } | |
15784 | ||
15785 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
15786 | /* Success. */ | |
15787 | ret = 0; | |
15788 | break; | |
15789 | } | |
15790 | } | |
59e6b434 DM |
15791 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
15792 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
15793 | /* DMA test passed without adjusting DMA boundary, | |
6d1cfbab MC |
15794 | * now look for chipsets that are known to expose the |
15795 | * DMA bug without failing the test. | |
59e6b434 | 15796 | */ |
4143470c | 15797 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
15798 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
15799 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 15800 | } else { |
6d1cfbab MC |
15801 | /* Safe to use the calculated DMA boundary. */ |
15802 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 15803 | } |
6d1cfbab | 15804 | |
59e6b434 DM |
15805 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
15806 | } | |
1da177e4 LT |
15807 | |
15808 | out: | |
4bae65c8 | 15809 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
15810 | out_nofree: |
15811 | return ret; | |
15812 | } | |
15813 | ||
1da177e4 LT |
15814 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
15815 | { | |
63c3a66f | 15816 | if (tg3_flag(tp, 57765_PLUS)) { |
666bc831 MC |
15817 | tp->bufmgr_config.mbuf_read_dma_low_water = |
15818 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15819 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15820 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
15821 | tp->bufmgr_config.mbuf_high_water = | |
15822 | DEFAULT_MB_HIGH_WATER_57765; | |
15823 | ||
15824 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15825 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15826 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15827 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
15828 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15829 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
63c3a66f | 15830 | } else if (tg3_flag(tp, 5705_PLUS)) { |
fdfec172 MC |
15831 | tp->bufmgr_config.mbuf_read_dma_low_water = |
15832 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
15833 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15834 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
15835 | tp->bufmgr_config.mbuf_high_water = | |
15836 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
15837 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
15838 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15839 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
15840 | tp->bufmgr_config.mbuf_high_water = | |
15841 | DEFAULT_MB_HIGH_WATER_5906; | |
15842 | } | |
fdfec172 MC |
15843 | |
15844 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15845 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
15846 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15847 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
15848 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15849 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
15850 | } else { | |
15851 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
15852 | DEFAULT_MB_RDMA_LOW_WATER; | |
15853 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
15854 | DEFAULT_MB_MACRX_LOW_WATER; | |
15855 | tp->bufmgr_config.mbuf_high_water = | |
15856 | DEFAULT_MB_HIGH_WATER; | |
15857 | ||
15858 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
15859 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
15860 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
15861 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
15862 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
15863 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
15864 | } | |
1da177e4 LT |
15865 | |
15866 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
15867 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
15868 | } | |
15869 | ||
15870 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
15871 | { | |
79eb6904 MC |
15872 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
15873 | case TG3_PHY_ID_BCM5400: return "5400"; | |
15874 | case TG3_PHY_ID_BCM5401: return "5401"; | |
15875 | case TG3_PHY_ID_BCM5411: return "5411"; | |
15876 | case TG3_PHY_ID_BCM5701: return "5701"; | |
15877 | case TG3_PHY_ID_BCM5703: return "5703"; | |
15878 | case TG3_PHY_ID_BCM5704: return "5704"; | |
15879 | case TG3_PHY_ID_BCM5705: return "5705"; | |
15880 | case TG3_PHY_ID_BCM5750: return "5750"; | |
15881 | case TG3_PHY_ID_BCM5752: return "5752"; | |
15882 | case TG3_PHY_ID_BCM5714: return "5714"; | |
15883 | case TG3_PHY_ID_BCM5780: return "5780"; | |
15884 | case TG3_PHY_ID_BCM5755: return "5755"; | |
15885 | case TG3_PHY_ID_BCM5787: return "5787"; | |
15886 | case TG3_PHY_ID_BCM5784: return "5784"; | |
15887 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
15888 | case TG3_PHY_ID_BCM5906: return "5906"; | |
15889 | case TG3_PHY_ID_BCM5761: return "5761"; | |
15890 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
15891 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
15892 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 15893 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
6418f2c1 | 15894 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
79eb6904 | 15895 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
15896 | case 0: return "serdes"; |
15897 | default: return "unknown"; | |
855e1111 | 15898 | } |
1da177e4 LT |
15899 | } |
15900 | ||
f9804ddb MC |
15901 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
15902 | { | |
63c3a66f | 15903 | if (tg3_flag(tp, PCI_EXPRESS)) { |
f9804ddb MC |
15904 | strcpy(str, "PCI Express"); |
15905 | return str; | |
63c3a66f | 15906 | } else if (tg3_flag(tp, PCIX_MODE)) { |
f9804ddb MC |
15907 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; |
15908 | ||
15909 | strcpy(str, "PCIX:"); | |
15910 | ||
15911 | if ((clock_ctrl == 7) || | |
15912 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
15913 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
15914 | strcat(str, "133MHz"); | |
15915 | else if (clock_ctrl == 0) | |
15916 | strcat(str, "33MHz"); | |
15917 | else if (clock_ctrl == 2) | |
15918 | strcat(str, "50MHz"); | |
15919 | else if (clock_ctrl == 4) | |
15920 | strcat(str, "66MHz"); | |
15921 | else if (clock_ctrl == 6) | |
15922 | strcat(str, "100MHz"); | |
f9804ddb MC |
15923 | } else { |
15924 | strcpy(str, "PCI:"); | |
63c3a66f | 15925 | if (tg3_flag(tp, PCI_HIGH_SPEED)) |
f9804ddb MC |
15926 | strcat(str, "66MHz"); |
15927 | else | |
15928 | strcat(str, "33MHz"); | |
15929 | } | |
63c3a66f | 15930 | if (tg3_flag(tp, PCI_32BIT)) |
f9804ddb MC |
15931 | strcat(str, ":32-bit"); |
15932 | else | |
15933 | strcat(str, ":64-bit"); | |
15934 | return str; | |
15935 | } | |
15936 | ||
15f9850d DM |
15937 | static void __devinit tg3_init_coal(struct tg3 *tp) |
15938 | { | |
15939 | struct ethtool_coalesce *ec = &tp->coal; | |
15940 | ||
15941 | memset(ec, 0, sizeof(*ec)); | |
15942 | ec->cmd = ETHTOOL_GCOALESCE; | |
15943 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
15944 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
15945 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
15946 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
15947 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
15948 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
15949 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
15950 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
15951 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
15952 | ||
15953 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
15954 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
15955 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
15956 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
15957 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
15958 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
15959 | } | |
d244c892 | 15960 | |
63c3a66f | 15961 | if (tg3_flag(tp, 5705_PLUS)) { |
d244c892 MC |
15962 | ec->rx_coalesce_usecs_irq = 0; |
15963 | ec->tx_coalesce_usecs_irq = 0; | |
15964 | ec->stats_block_coalesce_usecs = 0; | |
15965 | } | |
15f9850d DM |
15966 | } |
15967 | ||
1da177e4 LT |
15968 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
15969 | const struct pci_device_id *ent) | |
15970 | { | |
1da177e4 LT |
15971 | struct net_device *dev; |
15972 | struct tg3 *tp; | |
646c9edd MC |
15973 | int i, err, pm_cap; |
15974 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 15975 | char str[40]; |
72f2afb8 | 15976 | u64 dma_mask, persist_dma_mask; |
c8f44aff | 15977 | netdev_features_t features = 0; |
1da177e4 | 15978 | |
05dbe005 | 15979 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
15980 | |
15981 | err = pci_enable_device(pdev); | |
15982 | if (err) { | |
2445e461 | 15983 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
15984 | return err; |
15985 | } | |
15986 | ||
1da177e4 LT |
15987 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
15988 | if (err) { | |
2445e461 | 15989 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
15990 | goto err_out_disable_pdev; |
15991 | } | |
15992 | ||
15993 | pci_set_master(pdev); | |
15994 | ||
15995 | /* Find power-management capability. */ | |
15996 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
15997 | if (pm_cap == 0) { | |
2445e461 MC |
15998 | dev_err(&pdev->dev, |
15999 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
16000 | err = -EIO; |
16001 | goto err_out_free_res; | |
16002 | } | |
16003 | ||
16821285 MC |
16004 | err = pci_set_power_state(pdev, PCI_D0); |
16005 | if (err) { | |
16006 | dev_err(&pdev->dev, "Transition to D0 failed, aborting\n"); | |
16007 | goto err_out_free_res; | |
16008 | } | |
16009 | ||
fe5f5787 | 16010 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 16011 | if (!dev) { |
1da177e4 | 16012 | err = -ENOMEM; |
16821285 | 16013 | goto err_out_power_down; |
1da177e4 LT |
16014 | } |
16015 | ||
1da177e4 LT |
16016 | SET_NETDEV_DEV(dev, &pdev->dev); |
16017 | ||
1da177e4 LT |
16018 | tp = netdev_priv(dev); |
16019 | tp->pdev = pdev; | |
16020 | tp->dev = dev; | |
16021 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
16022 | tp->rx_mode = TG3_DEF_RX_MODE; |
16023 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 16024 | |
1da177e4 LT |
16025 | if (tg3_debug > 0) |
16026 | tp->msg_enable = tg3_debug; | |
16027 | else | |
16028 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
16029 | ||
16030 | /* The word/byte swap controls here control register access byte | |
16031 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
16032 | * setting below. | |
16033 | */ | |
16034 | tp->misc_host_ctrl = | |
16035 | MISC_HOST_CTRL_MASK_PCI_INT | | |
16036 | MISC_HOST_CTRL_WORD_SWAP | | |
16037 | MISC_HOST_CTRL_INDIR_ACCESS | | |
16038 | MISC_HOST_CTRL_PCISTATE_RW; | |
16039 | ||
16040 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
16041 | * on descriptor entries, anything which isn't packet data. | |
16042 | * | |
16043 | * The StrongARM chips on the board (one for tx, one for rx) | |
16044 | * are running in big-endian mode. | |
16045 | */ | |
16046 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
16047 | GRC_MODE_WSWAP_NONFRM_DATA); | |
16048 | #ifdef __BIG_ENDIAN | |
16049 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
16050 | #endif | |
16051 | spin_lock_init(&tp->lock); | |
1da177e4 | 16052 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 16053 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 16054 | |
d5fe488a | 16055 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 16056 | if (!tp->regs) { |
ab96b241 | 16057 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
16058 | err = -ENOMEM; |
16059 | goto err_out_free_dev; | |
16060 | } | |
16061 | ||
c9cab24e MC |
16062 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
16063 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || | |
16064 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || | |
16065 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || | |
16066 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
79d49695 | 16067 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || |
c9cab24e MC |
16068 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || |
16069 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
16070 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) { | |
16071 | tg3_flag_set(tp, ENABLE_APE); | |
16072 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
16073 | if (!tp->aperegs) { | |
16074 | dev_err(&pdev->dev, | |
16075 | "Cannot map APE registers, aborting\n"); | |
16076 | err = -ENOMEM; | |
16077 | goto err_out_iounmap; | |
16078 | } | |
16079 | } | |
16080 | ||
1da177e4 LT |
16081 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
16082 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 16083 | |
1da177e4 | 16084 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 16085 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
2ffcc981 | 16086 | dev->netdev_ops = &tg3_netdev_ops; |
1da177e4 | 16087 | dev->irq = pdev->irq; |
1da177e4 | 16088 | |
3d567e0e | 16089 | err = tg3_get_invariants(tp, ent); |
1da177e4 | 16090 | if (err) { |
ab96b241 MC |
16091 | dev_err(&pdev->dev, |
16092 | "Problem fetching invariants of chip, aborting\n"); | |
c9cab24e | 16093 | goto err_out_apeunmap; |
1da177e4 LT |
16094 | } |
16095 | ||
4a29cc2e MC |
16096 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
16097 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
16098 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
16099 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
16100 | * do DMA address check in tg3_start_xmit(). | |
16101 | */ | |
63c3a66f | 16102 | if (tg3_flag(tp, IS_5788)) |
284901a9 | 16103 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
63c3a66f | 16104 | else if (tg3_flag(tp, 40BIT_DMA_BUG)) { |
50cf156a | 16105 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 16106 | #ifdef CONFIG_HIGHMEM |
6a35528a | 16107 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 16108 | #endif |
4a29cc2e | 16109 | } else |
6a35528a | 16110 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
16111 | |
16112 | /* Configure DMA attributes. */ | |
284901a9 | 16113 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
16114 | err = pci_set_dma_mask(pdev, dma_mask); |
16115 | if (!err) { | |
0da0606f | 16116 | features |= NETIF_F_HIGHDMA; |
72f2afb8 MC |
16117 | err = pci_set_consistent_dma_mask(pdev, |
16118 | persist_dma_mask); | |
16119 | if (err < 0) { | |
ab96b241 MC |
16120 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
16121 | "DMA for consistent allocations\n"); | |
c9cab24e | 16122 | goto err_out_apeunmap; |
72f2afb8 MC |
16123 | } |
16124 | } | |
16125 | } | |
284901a9 YH |
16126 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
16127 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 16128 | if (err) { |
ab96b241 MC |
16129 | dev_err(&pdev->dev, |
16130 | "No usable DMA configuration, aborting\n"); | |
c9cab24e | 16131 | goto err_out_apeunmap; |
72f2afb8 MC |
16132 | } |
16133 | } | |
16134 | ||
fdfec172 | 16135 | tg3_init_bufmgr_config(tp); |
1da177e4 | 16136 | |
0da0606f MC |
16137 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
16138 | ||
16139 | /* 5700 B0 chips do not support checksumming correctly due | |
16140 | * to hardware bugs. | |
16141 | */ | |
16142 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { | |
16143 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
16144 | ||
16145 | if (tg3_flag(tp, 5755_PLUS)) | |
16146 | features |= NETIF_F_IPV6_CSUM; | |
16147 | } | |
16148 | ||
4e3a7aaa MC |
16149 | /* TSO is on by default on chips that support hardware TSO. |
16150 | * Firmware TSO on older chips gives lower performance, so it | |
16151 | * is off by default, but can be enabled using ethtool. | |
16152 | */ | |
63c3a66f JP |
16153 | if ((tg3_flag(tp, HW_TSO_1) || |
16154 | tg3_flag(tp, HW_TSO_2) || | |
16155 | tg3_flag(tp, HW_TSO_3)) && | |
0da0606f MC |
16156 | (features & NETIF_F_IP_CSUM)) |
16157 | features |= NETIF_F_TSO; | |
63c3a66f | 16158 | if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { |
0da0606f MC |
16159 | if (features & NETIF_F_IPV6_CSUM) |
16160 | features |= NETIF_F_TSO6; | |
63c3a66f | 16161 | if (tg3_flag(tp, HW_TSO_3) || |
e849cdc3 | 16162 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c MC |
16163 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
16164 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
63c3a66f | 16165 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
dc668910 | 16166 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
0da0606f | 16167 | features |= NETIF_F_TSO_ECN; |
b0026624 | 16168 | } |
1da177e4 | 16169 | |
d542fe27 MC |
16170 | dev->features |= features; |
16171 | dev->vlan_features |= features; | |
16172 | ||
06c03c02 MB |
16173 | /* |
16174 | * Add loopback capability only for a subset of devices that support | |
16175 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY | |
16176 | * loopback for the remaining devices. | |
16177 | */ | |
16178 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
16179 | !tg3_flag(tp, CPMU_PRESENT)) | |
16180 | /* Add the loopback capability */ | |
0da0606f MC |
16181 | features |= NETIF_F_LOOPBACK; |
16182 | ||
0da0606f | 16183 | dev->hw_features |= features; |
06c03c02 | 16184 | |
1da177e4 | 16185 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
63c3a66f | 16186 | !tg3_flag(tp, TSO_CAPABLE) && |
1da177e4 | 16187 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { |
63c3a66f | 16188 | tg3_flag_set(tp, MAX_RXPEND_64); |
1da177e4 LT |
16189 | tp->rx_pending = 63; |
16190 | } | |
16191 | ||
1da177e4 LT |
16192 | err = tg3_get_device_address(tp); |
16193 | if (err) { | |
ab96b241 MC |
16194 | dev_err(&pdev->dev, |
16195 | "Could not obtain valid ethernet address, aborting\n"); | |
c9cab24e | 16196 | goto err_out_apeunmap; |
c88864df MC |
16197 | } |
16198 | ||
1da177e4 LT |
16199 | /* |
16200 | * Reset chip in case UNDI or EFI driver did not shutdown | |
16201 | * DMA self test will enable WDMAC and we'll see (spurious) | |
16202 | * pending DMA on the PCI bus at that point. | |
16203 | */ | |
16204 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
16205 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 16206 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 16207 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
16208 | } |
16209 | ||
16210 | err = tg3_test_dma(tp); | |
16211 | if (err) { | |
ab96b241 | 16212 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 16213 | goto err_out_apeunmap; |
1da177e4 LT |
16214 | } |
16215 | ||
78f90dcf MC |
16216 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
16217 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
16218 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 16219 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
16220 | struct tg3_napi *tnapi = &tp->napi[i]; |
16221 | ||
16222 | tnapi->tp = tp; | |
16223 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
16224 | ||
16225 | tnapi->int_mbox = intmbx; | |
93a700a9 | 16226 | if (i <= 4) |
78f90dcf MC |
16227 | intmbx += 0x8; |
16228 | else | |
16229 | intmbx += 0x4; | |
16230 | ||
16231 | tnapi->consmbox = rcvmbx; | |
16232 | tnapi->prodmbox = sndmbx; | |
16233 | ||
66cfd1bd | 16234 | if (i) |
78f90dcf | 16235 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 16236 | else |
78f90dcf | 16237 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf | 16238 | |
63c3a66f | 16239 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
78f90dcf MC |
16240 | break; |
16241 | ||
16242 | /* | |
16243 | * If we support MSIX, we'll be using RSS. If we're using | |
16244 | * RSS, the first vector only handles link interrupts and the | |
16245 | * remaining vectors handle rx and tx interrupts. Reuse the | |
16246 | * mailbox values for the next iteration. The values we setup | |
16247 | * above are still useful for the single vectored mode. | |
16248 | */ | |
16249 | if (!i) | |
16250 | continue; | |
16251 | ||
16252 | rcvmbx += 0x8; | |
16253 | ||
16254 | if (sndmbx & 0x4) | |
16255 | sndmbx -= 0x4; | |
16256 | else | |
16257 | sndmbx += 0xc; | |
16258 | } | |
16259 | ||
15f9850d DM |
16260 | tg3_init_coal(tp); |
16261 | ||
c49a1561 MC |
16262 | pci_set_drvdata(pdev, dev); |
16263 | ||
cd0d7228 MC |
16264 | if (tg3_flag(tp, 5717_PLUS)) { |
16265 | /* Resume a low-power mode */ | |
16266 | tg3_frob_aux_power(tp, false); | |
16267 | } | |
16268 | ||
21f7638e MC |
16269 | tg3_timer_init(tp); |
16270 | ||
1da177e4 LT |
16271 | err = register_netdev(dev); |
16272 | if (err) { | |
ab96b241 | 16273 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 16274 | goto err_out_apeunmap; |
1da177e4 LT |
16275 | } |
16276 | ||
05dbe005 JP |
16277 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
16278 | tp->board_part_number, | |
16279 | tp->pci_chip_rev_id, | |
16280 | tg3_bus_string(tp, str), | |
16281 | dev->dev_addr); | |
1da177e4 | 16282 | |
f07e9af3 | 16283 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
16284 | struct phy_device *phydev; |
16285 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
16286 | netdev_info(dev, |
16287 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 16288 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
16289 | } else { |
16290 | char *ethtype; | |
16291 | ||
16292 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
16293 | ethtype = "10/100Base-TX"; | |
16294 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
16295 | ethtype = "1000Base-SX"; | |
16296 | else | |
16297 | ethtype = "10/100/1000Base-T"; | |
16298 | ||
5129c3a3 | 16299 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
47007831 MC |
16300 | "(WireSpeed[%d], EEE[%d])\n", |
16301 | tg3_phy_string(tp), ethtype, | |
16302 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, | |
16303 | (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); | |
f07e9af3 | 16304 | } |
05dbe005 JP |
16305 | |
16306 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
dc668910 | 16307 | (dev->features & NETIF_F_RXCSUM) != 0, |
63c3a66f | 16308 | tg3_flag(tp, USE_LINKCHG_REG) != 0, |
f07e9af3 | 16309 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
63c3a66f JP |
16310 | tg3_flag(tp, ENABLE_ASF) != 0, |
16311 | tg3_flag(tp, TSO_CAPABLE) != 0); | |
05dbe005 JP |
16312 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
16313 | tp->dma_rwctrl, | |
16314 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
16315 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 | 16316 | |
b45aa2f6 MC |
16317 | pci_save_state(pdev); |
16318 | ||
1da177e4 LT |
16319 | return 0; |
16320 | ||
0d3031d9 MC |
16321 | err_out_apeunmap: |
16322 | if (tp->aperegs) { | |
16323 | iounmap(tp->aperegs); | |
16324 | tp->aperegs = NULL; | |
16325 | } | |
16326 | ||
1da177e4 | 16327 | err_out_iounmap: |
6892914f MC |
16328 | if (tp->regs) { |
16329 | iounmap(tp->regs); | |
22abe310 | 16330 | tp->regs = NULL; |
6892914f | 16331 | } |
1da177e4 LT |
16332 | |
16333 | err_out_free_dev: | |
16334 | free_netdev(dev); | |
16335 | ||
16821285 MC |
16336 | err_out_power_down: |
16337 | pci_set_power_state(pdev, PCI_D3hot); | |
16338 | ||
1da177e4 LT |
16339 | err_out_free_res: |
16340 | pci_release_regions(pdev); | |
16341 | ||
16342 | err_out_disable_pdev: | |
16343 | pci_disable_device(pdev); | |
16344 | pci_set_drvdata(pdev, NULL); | |
16345 | return err; | |
16346 | } | |
16347 | ||
16348 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
16349 | { | |
16350 | struct net_device *dev = pci_get_drvdata(pdev); | |
16351 | ||
16352 | if (dev) { | |
16353 | struct tg3 *tp = netdev_priv(dev); | |
16354 | ||
e3c5530b | 16355 | release_firmware(tp->fw); |
077f849d | 16356 | |
db219973 | 16357 | tg3_reset_task_cancel(tp); |
158d7abd | 16358 | |
e730c823 | 16359 | if (tg3_flag(tp, USE_PHYLIB)) { |
b02fd9e3 | 16360 | tg3_phy_fini(tp); |
158d7abd | 16361 | tg3_mdio_fini(tp); |
b02fd9e3 | 16362 | } |
158d7abd | 16363 | |
1da177e4 | 16364 | unregister_netdev(dev); |
0d3031d9 MC |
16365 | if (tp->aperegs) { |
16366 | iounmap(tp->aperegs); | |
16367 | tp->aperegs = NULL; | |
16368 | } | |
6892914f MC |
16369 | if (tp->regs) { |
16370 | iounmap(tp->regs); | |
22abe310 | 16371 | tp->regs = NULL; |
6892914f | 16372 | } |
1da177e4 LT |
16373 | free_netdev(dev); |
16374 | pci_release_regions(pdev); | |
16375 | pci_disable_device(pdev); | |
16376 | pci_set_drvdata(pdev, NULL); | |
16377 | } | |
16378 | } | |
16379 | ||
aa6027ca | 16380 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 16381 | static int tg3_suspend(struct device *device) |
1da177e4 | 16382 | { |
c866b7ea | 16383 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
16384 | struct net_device *dev = pci_get_drvdata(pdev); |
16385 | struct tg3 *tp = netdev_priv(dev); | |
16386 | int err; | |
16387 | ||
16388 | if (!netif_running(dev)) | |
16389 | return 0; | |
16390 | ||
db219973 | 16391 | tg3_reset_task_cancel(tp); |
b02fd9e3 | 16392 | tg3_phy_stop(tp); |
1da177e4 LT |
16393 | tg3_netif_stop(tp); |
16394 | ||
21f7638e | 16395 | tg3_timer_stop(tp); |
1da177e4 | 16396 | |
f47c11ee | 16397 | tg3_full_lock(tp, 1); |
1da177e4 | 16398 | tg3_disable_ints(tp); |
f47c11ee | 16399 | tg3_full_unlock(tp); |
1da177e4 LT |
16400 | |
16401 | netif_device_detach(dev); | |
16402 | ||
f47c11ee | 16403 | tg3_full_lock(tp, 0); |
944d980e | 16404 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
63c3a66f | 16405 | tg3_flag_clear(tp, INIT_COMPLETE); |
f47c11ee | 16406 | tg3_full_unlock(tp); |
1da177e4 | 16407 | |
c866b7ea | 16408 | err = tg3_power_down_prepare(tp); |
1da177e4 | 16409 | if (err) { |
b02fd9e3 MC |
16410 | int err2; |
16411 | ||
f47c11ee | 16412 | tg3_full_lock(tp, 0); |
1da177e4 | 16413 | |
63c3a66f | 16414 | tg3_flag_set(tp, INIT_COMPLETE); |
b02fd9e3 MC |
16415 | err2 = tg3_restart_hw(tp, 1); |
16416 | if (err2) | |
b9ec6c1b | 16417 | goto out; |
1da177e4 | 16418 | |
21f7638e | 16419 | tg3_timer_start(tp); |
1da177e4 LT |
16420 | |
16421 | netif_device_attach(dev); | |
16422 | tg3_netif_start(tp); | |
16423 | ||
b9ec6c1b | 16424 | out: |
f47c11ee | 16425 | tg3_full_unlock(tp); |
b02fd9e3 MC |
16426 | |
16427 | if (!err2) | |
16428 | tg3_phy_start(tp); | |
1da177e4 LT |
16429 | } |
16430 | ||
16431 | return err; | |
16432 | } | |
16433 | ||
c866b7ea | 16434 | static int tg3_resume(struct device *device) |
1da177e4 | 16435 | { |
c866b7ea | 16436 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
16437 | struct net_device *dev = pci_get_drvdata(pdev); |
16438 | struct tg3 *tp = netdev_priv(dev); | |
16439 | int err; | |
16440 | ||
16441 | if (!netif_running(dev)) | |
16442 | return 0; | |
16443 | ||
1da177e4 LT |
16444 | netif_device_attach(dev); |
16445 | ||
f47c11ee | 16446 | tg3_full_lock(tp, 0); |
1da177e4 | 16447 | |
63c3a66f | 16448 | tg3_flag_set(tp, INIT_COMPLETE); |
b9ec6c1b MC |
16449 | err = tg3_restart_hw(tp, 1); |
16450 | if (err) | |
16451 | goto out; | |
1da177e4 | 16452 | |
21f7638e | 16453 | tg3_timer_start(tp); |
1da177e4 | 16454 | |
1da177e4 LT |
16455 | tg3_netif_start(tp); |
16456 | ||
b9ec6c1b | 16457 | out: |
f47c11ee | 16458 | tg3_full_unlock(tp); |
1da177e4 | 16459 | |
b02fd9e3 MC |
16460 | if (!err) |
16461 | tg3_phy_start(tp); | |
16462 | ||
b9ec6c1b | 16463 | return err; |
1da177e4 LT |
16464 | } |
16465 | ||
c866b7ea | 16466 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
16467 | #define TG3_PM_OPS (&tg3_pm_ops) |
16468 | ||
16469 | #else | |
16470 | ||
16471 | #define TG3_PM_OPS NULL | |
16472 | ||
16473 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 16474 | |
b45aa2f6 MC |
16475 | /** |
16476 | * tg3_io_error_detected - called when PCI error is detected | |
16477 | * @pdev: Pointer to PCI device | |
16478 | * @state: The current pci connection state | |
16479 | * | |
16480 | * This function is called after a PCI bus error affecting | |
16481 | * this device has been detected. | |
16482 | */ | |
16483 | static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |
16484 | pci_channel_state_t state) | |
16485 | { | |
16486 | struct net_device *netdev = pci_get_drvdata(pdev); | |
16487 | struct tg3 *tp = netdev_priv(netdev); | |
16488 | pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET; | |
16489 | ||
16490 | netdev_info(netdev, "PCI I/O error detected\n"); | |
16491 | ||
16492 | rtnl_lock(); | |
16493 | ||
16494 | if (!netif_running(netdev)) | |
16495 | goto done; | |
16496 | ||
16497 | tg3_phy_stop(tp); | |
16498 | ||
16499 | tg3_netif_stop(tp); | |
16500 | ||
21f7638e | 16501 | tg3_timer_stop(tp); |
b45aa2f6 MC |
16502 | |
16503 | /* Want to make sure that the reset task doesn't run */ | |
db219973 | 16504 | tg3_reset_task_cancel(tp); |
b45aa2f6 MC |
16505 | |
16506 | netif_device_detach(netdev); | |
16507 | ||
16508 | /* Clean up software state, even if MMIO is blocked */ | |
16509 | tg3_full_lock(tp, 0); | |
16510 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
16511 | tg3_full_unlock(tp); | |
16512 | ||
16513 | done: | |
16514 | if (state == pci_channel_io_perm_failure) | |
16515 | err = PCI_ERS_RESULT_DISCONNECT; | |
16516 | else | |
16517 | pci_disable_device(pdev); | |
16518 | ||
16519 | rtnl_unlock(); | |
16520 | ||
16521 | return err; | |
16522 | } | |
16523 | ||
16524 | /** | |
16525 | * tg3_io_slot_reset - called after the pci bus has been reset. | |
16526 | * @pdev: Pointer to PCI device | |
16527 | * | |
16528 | * Restart the card from scratch, as if from a cold-boot. | |
16529 | * At this point, the card has exprienced a hard reset, | |
16530 | * followed by fixups by BIOS, and has its config space | |
16531 | * set up identically to what it was at cold boot. | |
16532 | */ | |
16533 | static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) | |
16534 | { | |
16535 | struct net_device *netdev = pci_get_drvdata(pdev); | |
16536 | struct tg3 *tp = netdev_priv(netdev); | |
16537 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; | |
16538 | int err; | |
16539 | ||
16540 | rtnl_lock(); | |
16541 | ||
16542 | if (pci_enable_device(pdev)) { | |
16543 | netdev_err(netdev, "Cannot re-enable PCI device after reset.\n"); | |
16544 | goto done; | |
16545 | } | |
16546 | ||
16547 | pci_set_master(pdev); | |
16548 | pci_restore_state(pdev); | |
16549 | pci_save_state(pdev); | |
16550 | ||
16551 | if (!netif_running(netdev)) { | |
16552 | rc = PCI_ERS_RESULT_RECOVERED; | |
16553 | goto done; | |
16554 | } | |
16555 | ||
16556 | err = tg3_power_up(tp); | |
bed9829f | 16557 | if (err) |
b45aa2f6 | 16558 | goto done; |
b45aa2f6 MC |
16559 | |
16560 | rc = PCI_ERS_RESULT_RECOVERED; | |
16561 | ||
16562 | done: | |
16563 | rtnl_unlock(); | |
16564 | ||
16565 | return rc; | |
16566 | } | |
16567 | ||
16568 | /** | |
16569 | * tg3_io_resume - called when traffic can start flowing again. | |
16570 | * @pdev: Pointer to PCI device | |
16571 | * | |
16572 | * This callback is called when the error recovery driver tells | |
16573 | * us that its OK to resume normal operation. | |
16574 | */ | |
16575 | static void tg3_io_resume(struct pci_dev *pdev) | |
16576 | { | |
16577 | struct net_device *netdev = pci_get_drvdata(pdev); | |
16578 | struct tg3 *tp = netdev_priv(netdev); | |
16579 | int err; | |
16580 | ||
16581 | rtnl_lock(); | |
16582 | ||
16583 | if (!netif_running(netdev)) | |
16584 | goto done; | |
16585 | ||
16586 | tg3_full_lock(tp, 0); | |
63c3a66f | 16587 | tg3_flag_set(tp, INIT_COMPLETE); |
b45aa2f6 MC |
16588 | err = tg3_restart_hw(tp, 1); |
16589 | tg3_full_unlock(tp); | |
16590 | if (err) { | |
16591 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); | |
16592 | goto done; | |
16593 | } | |
16594 | ||
16595 | netif_device_attach(netdev); | |
16596 | ||
21f7638e | 16597 | tg3_timer_start(tp); |
b45aa2f6 MC |
16598 | |
16599 | tg3_netif_start(tp); | |
16600 | ||
16601 | tg3_phy_start(tp); | |
16602 | ||
16603 | done: | |
16604 | rtnl_unlock(); | |
16605 | } | |
16606 | ||
3646f0e5 | 16607 | static const struct pci_error_handlers tg3_err_handler = { |
b45aa2f6 MC |
16608 | .error_detected = tg3_io_error_detected, |
16609 | .slot_reset = tg3_io_slot_reset, | |
16610 | .resume = tg3_io_resume | |
16611 | }; | |
16612 | ||
1da177e4 LT |
16613 | static struct pci_driver tg3_driver = { |
16614 | .name = DRV_MODULE_NAME, | |
16615 | .id_table = tg3_pci_tbl, | |
16616 | .probe = tg3_init_one, | |
16617 | .remove = __devexit_p(tg3_remove_one), | |
b45aa2f6 | 16618 | .err_handler = &tg3_err_handler, |
aa6027ca | 16619 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
16620 | }; |
16621 | ||
16622 | static int __init tg3_init(void) | |
16623 | { | |
29917620 | 16624 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
16625 | } |
16626 | ||
16627 | static void __exit tg3_cleanup(void) | |
16628 | { | |
16629 | pci_unregister_driver(&tg3_driver); | |
16630 | } | |
16631 | ||
16632 | module_init(tg3_init); | |
16633 | module_exit(tg3_cleanup); |