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bna: tx rx cleanup fix
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / brocade / bna / bnad.c
CommitLineData
8b230ed8
RM		 1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
f859d7cb 18#include <linux/bitops.h>
8b230ed8
RM		 19#include <linux/netdevice.h>
20#include <linux/skbuff.h>
21#include <linux/etherdevice.h>
22#include <linux/in.h>
23#include <linux/ethtool.h>
24#include <linux/if_vlan.h>
25#include <linux/if_ether.h>
26#include <linux/ip.h>
70c71606 27#include <linux/prefetch.h>
9d9779e7 28#include <linux/module.h>
8b230ed8
RM		 29
30#include "bnad.h"
31#include "bna.h"
32#include "cna.h"
33
b7ee31c5 34static DEFINE_MUTEX(bnad_fwimg_mutex);
8b230ed8
RM		 35
36/*
37 * Module params
38 */
39static uint bnad_msix_disable;
40module_param(bnad_msix_disable, uint, 0444);
41MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
42
43static uint bnad_ioc_auto_recover = 1;
44module_param(bnad_ioc_auto_recover, uint, 0444);
45MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
46
7afc5dbd
KG		 47static uint bna_debugfs_enable = 1;
48module_param(bna_debugfs_enable, uint, S_IRUGO | S_IWUSR);
49MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1,"
50 " Range[false:0|true:1]");
51
8b230ed8
RM		 52/*
53 * Global variables
54 */
55u32 bnad_rxqs_per_cq = 2;
e1e0918f 56static u32 bna_id;
57static struct mutex bnad_list_mutex;
58static LIST_HEAD(bnad_list);
b7ee31c5 59static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
8b230ed8
RM		 60
61/*
62 * Local MACROS
63 */
64#define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
65
66#define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
67
68#define BNAD_GET_MBOX_IRQ(_bnad) \
69 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
8811e267 70 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
8b230ed8
RM		 71 ((_bnad)->pcidev->irq))
72
73#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
74do { \
75 (_res_info)->res_type = BNA_RES_T_MEM; \
76 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
77 (_res_info)->res_u.mem_info.num = (_num); \
78 (_res_info)->res_u.mem_info.len = \
79 sizeof(struct bnad_unmap_q) + \
80 (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
81} while (0)
82
72a9730b
KG		 83static void
84bnad_add_to_list(struct bnad *bnad)
85{
86 mutex_lock(&bnad_list_mutex);
87 list_add_tail(&bnad->list_entry, &bnad_list);
88 bnad->id = bna_id++;
89 mutex_unlock(&bnad_list_mutex);
90}
91
92static void
93bnad_remove_from_list(struct bnad *bnad)
94{
95 mutex_lock(&bnad_list_mutex);
96 list_del(&bnad->list_entry);
97 mutex_unlock(&bnad_list_mutex);
98}
99
8b230ed8
RM		 100/*
101 * Reinitialize completions in CQ, once Rx is taken down
102 */
103static void
104bnad_cq_cmpl_init(struct bnad *bnad, struct bna_ccb *ccb)
105{
106 struct bna_cq_entry *cmpl, *next_cmpl;
107 unsigned int wi_range, wis = 0, ccb_prod = 0;
108 int i;
109
110 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, cmpl,
111 wi_range);
112
113 for (i = 0; i < ccb->q_depth; i++) {
114 wis++;
115 if (likely(--wi_range))
116 next_cmpl = cmpl + 1;
117 else {
118 BNA_QE_INDX_ADD(ccb_prod, wis, ccb->q_depth);
119 wis = 0;
120 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt,
121 next_cmpl, wi_range);
122 }
123 cmpl->valid = 0;
124 cmpl = next_cmpl;
125 }
126}
127
271e8b79
RM		 128static u32
129bnad_pci_unmap_skb(struct device *pdev, struct bnad_skb_unmap *array,
130 u32 index, u32 depth, struct sk_buff *skb, u32 frag)
131{
132 int j;
133 array[index].skb = NULL;
134
135 dma_unmap_single(pdev, dma_unmap_addr(&array[index], dma_addr),
136 skb_headlen(skb), DMA_TO_DEVICE);
137 dma_unmap_addr_set(&array[index], dma_addr, 0);
138 BNA_QE_INDX_ADD(index, 1, depth);
139
140 for (j = 0; j < frag; j++) {
141 dma_unmap_page(pdev, dma_unmap_addr(&array[index], dma_addr),
01b54b14
JH		 142 skb_frag_size(&skb_shinfo(skb)->frags[j]),
143 DMA_TO_DEVICE);
271e8b79
RM		 144 dma_unmap_addr_set(&array[index], dma_addr, 0);
145 BNA_QE_INDX_ADD(index, 1, depth);
146 }
147
148 return index;
149}
150
8b230ed8
RM		 151/*
152 * Frees all pending Tx Bufs
153 * At this point no activity is expected on the Q,
154 * so DMA unmap & freeing is fine.
155 */
156static void
157bnad_free_all_txbufs(struct bnad *bnad,
158 struct bna_tcb *tcb)
159{
0120b99c 160 u32 unmap_cons;
8b230ed8
RM		 161 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
162 struct bnad_skb_unmap *unmap_array;
0120b99c 163 struct sk_buff *skb = NULL;
938fa488 164 int q;
8b230ed8
RM		 165
166 unmap_array = unmap_q->unmap_array;
167
938fa488
RM		 168 for (q = 0; q < unmap_q->q_depth; q++) {
169 skb = unmap_array[q].skb;
170 if (!skb)
8b230ed8 171 continue;
938fa488
RM		 172
173 unmap_cons = q;
174 unmap_cons = bnad_pci_unmap_skb(&bnad->pcidev->dev, unmap_array,
175 unmap_cons, unmap_q->q_depth, skb,
176 skb_shinfo(skb)->nr_frags);
177
8b230ed8
RM		 178 dev_kfree_skb_any(skb);
179 }
180}
181
182/* Data Path Handlers */
183
184/*
185 * bnad_free_txbufs : Frees the Tx bufs on Tx completion
186 * Can be called in a) Interrupt context
187 * b) Sending context
188 * c) Tasklet context
189 */
190static u32
191bnad_free_txbufs(struct bnad *bnad,
192 struct bna_tcb *tcb)
193{
271e8b79
RM		 194 u32 unmap_cons, sent_packets = 0, sent_bytes = 0;
195 u16 wis, updated_hw_cons;
8b230ed8
RM		 196 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
197 struct bnad_skb_unmap *unmap_array;
0120b99c 198 struct sk_buff *skb;
8b230ed8
RM		 199
200 /*
201 * Just return if TX is stopped. This check is useful
202 * when bnad_free_txbufs() runs out of a tasklet scheduled
be7fa326 203 * before bnad_cb_tx_cleanup() cleared BNAD_TXQ_TX_STARTED bit
8b230ed8
RM		 204 * but this routine runs actually after the cleanup has been
205 * executed.
206 */
be7fa326 207 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
8b230ed8
RM		 208 return 0;
209
210 updated_hw_cons = *(tcb->hw_consumer_index);
211
212 wis = BNA_Q_INDEX_CHANGE(tcb->consumer_index,
213 updated_hw_cons, tcb->q_depth);
214
215 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
216
217 unmap_array = unmap_q->unmap_array;
218 unmap_cons = unmap_q->consumer_index;
219
220 prefetch(&unmap_array[unmap_cons + 1]);
221 while (wis) {
222 skb = unmap_array[unmap_cons].skb;
223
8b230ed8
RM		 224 sent_packets++;
225 sent_bytes += skb->len;
226 wis -= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags);
227
271e8b79
RM		 228 unmap_cons = bnad_pci_unmap_skb(&bnad->pcidev->dev, unmap_array,
229 unmap_cons, unmap_q->q_depth, skb,
230 skb_shinfo(skb)->nr_frags);
8b230ed8 231
8b230ed8
RM		 232 dev_kfree_skb_any(skb);
233 }
234
235 /* Update consumer pointers. */
236 tcb->consumer_index = updated_hw_cons;
237 unmap_q->consumer_index = unmap_cons;
238
239 tcb->txq->tx_packets += sent_packets;
240 tcb->txq->tx_bytes += sent_bytes;
241
242 return sent_packets;
243}
244
245/* Tx Free Tasklet function */
246/* Frees for all the tcb's in all the Tx's */
247/*
248 * Scheduled from sending context, so that
249 * the fat Tx lock is not held for too long
250 * in the sending context.
251 */
252static void
253bnad_tx_free_tasklet(unsigned long bnad_ptr)
254{
255 struct bnad *bnad = (struct bnad *)bnad_ptr;
256 struct bna_tcb *tcb;
0120b99c 257 u32 acked = 0;
8b230ed8
RM		 258 int i, j;
259
260 for (i = 0; i < bnad->num_tx; i++) {
261 for (j = 0; j < bnad->num_txq_per_tx; j++) {
262 tcb = bnad->tx_info[i].tcb[j];
263 if (!tcb)
264 continue;
265 if (((u16) (*tcb->hw_consumer_index) !=
266 tcb->consumer_index) &&
267 (!test_and_set_bit(BNAD_TXQ_FREE_SENT,
268 &tcb->flags))) {
269 acked = bnad_free_txbufs(bnad, tcb);
be7fa326
RM		 270 if (likely(test_bit(BNAD_TXQ_TX_STARTED,
271 &tcb->flags)))
272 bna_ib_ack(tcb->i_dbell, acked);
8b230ed8
RM		 273 smp_mb__before_clear_bit();
274 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
275 }
f7c0fa4c
RM		 276 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED,
277 &tcb->flags)))
278 continue;
279 if (netif_queue_stopped(bnad->netdev)) {
280 if (acked && netif_carrier_ok(bnad->netdev) &&
281 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
282 BNAD_NETIF_WAKE_THRESHOLD) {
283 netif_wake_queue(bnad->netdev);
284 /* TODO */
285 /* Counters for individual TxQs? */
286 BNAD_UPDATE_CTR(bnad,
287 netif_queue_wakeup);
288 }
289 }
8b230ed8
RM		 290 }
291 }
292}
293
294static u32
295bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
296{
297 struct net_device *netdev = bnad->netdev;
be7fa326 298 u32 sent = 0;
8b230ed8
RM		 299
300 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
301 return 0;
302
303 sent = bnad_free_txbufs(bnad, tcb);
304 if (sent) {
305 if (netif_queue_stopped(netdev) &&
306 netif_carrier_ok(netdev) &&
307 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
308 BNAD_NETIF_WAKE_THRESHOLD) {
be7fa326
RM		 309 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
310 netif_wake_queue(netdev);
311 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
312 }
8b230ed8 313 }
be7fa326
RM		 314 }
315
316 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
8b230ed8 317 bna_ib_ack(tcb->i_dbell, sent);
8b230ed8
RM		 318
319 smp_mb__before_clear_bit();
320 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
321
322 return sent;
323}
324
325/* MSIX Tx Completion Handler */
326static irqreturn_t
327bnad_msix_tx(int irq, void *data)
328{
329 struct bna_tcb *tcb = (struct bna_tcb *)data;
330 struct bnad *bnad = tcb->bnad;
331
332 bnad_tx(bnad, tcb);
333
334 return IRQ_HANDLED;
335}
336
337static void
338bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb)
339{
340 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
341
342 rcb->producer_index = 0;
343 rcb->consumer_index = 0;
344
345 unmap_q->producer_index = 0;
346 unmap_q->consumer_index = 0;
347}
348
349static void
be7fa326 350bnad_free_all_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
8b230ed8
RM		 351{
352 struct bnad_unmap_q *unmap_q;
5ea74318 353 struct bnad_skb_unmap *unmap_array;
8b230ed8 354 struct sk_buff *skb;
be7fa326 355 int unmap_cons;
8b230ed8
RM		 356
357 unmap_q = rcb->unmap_q;
5ea74318 358 unmap_array = unmap_q->unmap_array;
be7fa326 359 for (unmap_cons = 0; unmap_cons < unmap_q->q_depth; unmap_cons++) {
5ea74318 360 skb = unmap_array[unmap_cons].skb;
be7fa326
RM		 361 if (!skb)
362 continue;
5ea74318
IV		 363 unmap_array[unmap_cons].skb = NULL;
364 dma_unmap_single(&bnad->pcidev->dev,
365 dma_unmap_addr(&unmap_array[unmap_cons],
366 dma_addr),
367 rcb->rxq->buffer_size,
368 DMA_FROM_DEVICE);
8b230ed8 369 dev_kfree_skb(skb);
8b230ed8 370 }
8b230ed8
RM		 371 bnad_reset_rcb(bnad, rcb);
372}
373
374static void
375bnad_alloc_n_post_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
376{
377 u16 to_alloc, alloced, unmap_prod, wi_range;
378 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
379 struct bnad_skb_unmap *unmap_array;
380 struct bna_rxq_entry *rxent;
381 struct sk_buff *skb;
382 dma_addr_t dma_addr;
383
384 alloced = 0;
385 to_alloc =
386 BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth);
387
388 unmap_array = unmap_q->unmap_array;
389 unmap_prod = unmap_q->producer_index;
390
391 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, wi_range);
392
393 while (to_alloc--) {
19dbff9f 394 if (!wi_range)
8b230ed8
RM		 395 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent,
396 wi_range);
0a0e2344
ED		 397 skb = netdev_alloc_skb_ip_align(bnad->netdev,
398 rcb->rxq->buffer_size);
8b230ed8
RM		 399 if (unlikely(!skb)) {
400 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
3caa1e95 401 rcb->rxq->rxbuf_alloc_failed++;
8b230ed8
RM		 402 goto finishing;
403 }
8b230ed8 404 unmap_array[unmap_prod].skb = skb;
5ea74318
IV		 405 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
406 rcb->rxq->buffer_size,
407 DMA_FROM_DEVICE);
408 dma_unmap_addr_set(&unmap_array[unmap_prod], dma_addr,
8b230ed8
RM		 409 dma_addr);
410 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
411 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
412
413 rxent++;
414 wi_range--;
415 alloced++;
416 }
417
418finishing:
419 if (likely(alloced)) {
420 unmap_q->producer_index = unmap_prod;
421 rcb->producer_index = unmap_prod;
422 smp_mb();
5bcf6ac0 423 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
be7fa326 424 bna_rxq_prod_indx_doorbell(rcb);
8b230ed8 425 }
8b230ed8
RM		 426}
427
428static inline void
429bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb)
430{
431 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
432
433 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
434 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
435 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
436 bnad_alloc_n_post_rxbufs(bnad, rcb);
437 smp_mb__before_clear_bit();
438 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
439 }
440}
441
442static u32
443bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget)
444{
445 struct bna_cq_entry *cmpl, *next_cmpl;
446 struct bna_rcb *rcb = NULL;
447 unsigned int wi_range, packets = 0, wis = 0;
448 struct bnad_unmap_q *unmap_q;
5ea74318 449 struct bnad_skb_unmap *unmap_array;
8b230ed8 450 struct sk_buff *skb;
5ea74318 451 u32 flags, unmap_cons;
8b230ed8 452 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
078086f3
RM		 453 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
454
01b54b14 455 if (!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))
be7fa326
RM		 456 return 0;
457
8b230ed8
RM		 458 prefetch(bnad->netdev);
459 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
460 wi_range);
461 BUG_ON(!(wi_range <= ccb->q_depth));
462 while (cmpl->valid && packets < budget) {
463 packets++;
464 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
465
078086f3 466 if (bna_is_small_rxq(cmpl->rxq_id))
8b230ed8 467 rcb = ccb->rcb[1];
078086f3
RM		 468 else
469 rcb = ccb->rcb[0];
8b230ed8
RM		 470
471 unmap_q = rcb->unmap_q;
5ea74318
IV		 472 unmap_array = unmap_q->unmap_array;
473 unmap_cons = unmap_q->consumer_index;
8b230ed8 474
5ea74318 475 skb = unmap_array[unmap_cons].skb;
8b230ed8 476 BUG_ON(!(skb));
5ea74318
IV		 477 unmap_array[unmap_cons].skb = NULL;
478 dma_unmap_single(&bnad->pcidev->dev,
479 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8 480 dma_addr),
5ea74318
IV		 481 rcb->rxq->buffer_size,
482 DMA_FROM_DEVICE);
8b230ed8
RM		 483 BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
484
485 /* Should be more efficient ? Performance ? */
486 BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
487
488 wis++;
489 if (likely(--wi_range))
490 next_cmpl = cmpl + 1;
491 else {
492 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
493 wis = 0;
494 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt,
495 next_cmpl, wi_range);
496 BUG_ON(!(wi_range <= ccb->q_depth));
497 }
498 prefetch(next_cmpl);
499
500 flags = ntohl(cmpl->flags);
501 if (unlikely
502 (flags &
503 (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR |
504 BNA_CQ_EF_TOO_LONG))) {
505 dev_kfree_skb_any(skb);
506 rcb->rxq->rx_packets_with_error++;
507 goto next;
508 }
509
510 skb_put(skb, ntohs(cmpl->length));
511 if (likely
e5ee20e7 512 ((bnad->netdev->features & NETIF_F_RXCSUM) &&
8b230ed8
RM		 513 (((flags & BNA_CQ_EF_IPV4) &&
514 (flags & BNA_CQ_EF_L3_CKSUM_OK)) ||
515 (flags & BNA_CQ_EF_IPV6)) &&
516 (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) &&
517 (flags & BNA_CQ_EF_L4_CKSUM_OK)))
518 skb->ip_summed = CHECKSUM_UNNECESSARY;
519 else
bc8acf2c 520 skb_checksum_none_assert(skb);
8b230ed8
RM		 521
522 rcb->rxq->rx_packets++;
523 rcb->rxq->rx_bytes += skb->len;
524 skb->protocol = eth_type_trans(skb, bnad->netdev);
525
f859d7cb
JP		 526 if (flags & BNA_CQ_EF_VLAN)
527 __vlan_hwaccel_put_tag(skb, ntohs(cmpl->vlan_tag));
528
078086f3 529 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
f859d7cb 530 napi_gro_receive(&rx_ctrl->napi, skb);
01b54b14 531 else
f859d7cb 532 netif_receive_skb(skb);
8b230ed8
RM		 533
534next:
535 cmpl->valid = 0;
536 cmpl = next_cmpl;
537 }
538
539 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
540
2be67144 541 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
271e8b79
RM		 542 bna_ib_ack_disable_irq(ccb->i_dbell, packets);
543
2be67144
RM		 544 bnad_refill_rxq(bnad, ccb->rcb[0]);
545 if (ccb->rcb[1])
546 bnad_refill_rxq(bnad, ccb->rcb[1]);
8b230ed8 547
078086f3
RM		 548 clear_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags);
549
8b230ed8
RM		 550 return packets;
551}
552
8b230ed8
RM		 553static void
554bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
555{
556 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
be7fa326
RM		 557 struct napi_struct *napi = &rx_ctrl->napi;
558
559 if (likely(napi_schedule_prep(napi))) {
be7fa326 560 __napi_schedule(napi);
271e8b79 561 rx_ctrl->rx_schedule++;
8b230ed8 562 }
8b230ed8
RM		 563}
564
565/* MSIX Rx Path Handler */
566static irqreturn_t
567bnad_msix_rx(int irq, void *data)
568{
569 struct bna_ccb *ccb = (struct bna_ccb *)data;
8b230ed8 570
271e8b79
RM		 571 if (ccb) {
572 ((struct bnad_rx_ctrl *)(ccb->ctrl))->rx_intr_ctr++;
2be67144 573 bnad_netif_rx_schedule_poll(ccb->bnad, ccb);
271e8b79 574 }
8b230ed8
RM		 575
576 return IRQ_HANDLED;
577}
578
579/* Interrupt handlers */
580
581/* Mbox Interrupt Handlers */
582static irqreturn_t
583bnad_msix_mbox_handler(int irq, void *data)
584{
585 u32 intr_status;
e2fa6f2e 586 unsigned long flags;
be7fa326 587 struct bnad *bnad = (struct bnad *)data;
8b230ed8 588
8b230ed8 589 spin_lock_irqsave(&bnad->bna_lock, flags);
dfee325a
RM		 590 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
591 spin_unlock_irqrestore(&bnad->bna_lock, flags);
592 return IRQ_HANDLED;
593 }
8b230ed8
RM		 594
595 bna_intr_status_get(&bnad->bna, intr_status);
596
078086f3 597 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
8b230ed8
RM		 598 bna_mbox_handler(&bnad->bna, intr_status);
599
600 spin_unlock_irqrestore(&bnad->bna_lock, flags);
601
8b230ed8
RM		 602 return IRQ_HANDLED;
603}
604
605static irqreturn_t
606bnad_isr(int irq, void *data)
607{
608 int i, j;
609 u32 intr_status;
610 unsigned long flags;
be7fa326 611 struct bnad *bnad = (struct bnad *)data;
8b230ed8
RM		 612 struct bnad_rx_info *rx_info;
613 struct bnad_rx_ctrl *rx_ctrl;
078086f3 614 struct bna_tcb *tcb = NULL;
8b230ed8 615
dfee325a
RM		 616 spin_lock_irqsave(&bnad->bna_lock, flags);
617 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
618 spin_unlock_irqrestore(&bnad->bna_lock, flags);
e2fa6f2e 619 return IRQ_NONE;
dfee325a 620 }
8b230ed8
RM		 621
622 bna_intr_status_get(&bnad->bna, intr_status);
e2fa6f2e 623
dfee325a
RM		 624 if (unlikely(!intr_status)) {
625 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 626 return IRQ_NONE;
dfee325a 627 }
8b230ed8 628
078086f3 629 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
8b230ed8 630 bna_mbox_handler(&bnad->bna, intr_status);
be7fa326 631
8b230ed8
RM		 632 spin_unlock_irqrestore(&bnad->bna_lock, flags);
633
be7fa326
RM		 634 if (!BNA_IS_INTX_DATA_INTR(intr_status))
635 return IRQ_HANDLED;
636
8b230ed8 637 /* Process data interrupts */
be7fa326
RM		 638 /* Tx processing */
639 for (i = 0; i < bnad->num_tx; i++) {
078086f3
RM		 640 for (j = 0; j < bnad->num_txq_per_tx; j++) {
641 tcb = bnad->tx_info[i].tcb[j];
642 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
643 bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
644 }
be7fa326
RM		 645 }
646 /* Rx processing */
8b230ed8
RM		 647 for (i = 0; i < bnad->num_rx; i++) {
648 rx_info = &bnad->rx_info[i];
649 if (!rx_info->rx)
650 continue;
651 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
652 rx_ctrl = &rx_info->rx_ctrl[j];
653 if (rx_ctrl->ccb)
654 bnad_netif_rx_schedule_poll(bnad,
655 rx_ctrl->ccb);
656 }
657 }
8b230ed8
RM		 658 return IRQ_HANDLED;
659}
660
661/*
662 * Called in interrupt / callback context
663 * with bna_lock held, so cfg_flags access is OK
664 */
665static void
666bnad_enable_mbox_irq(struct bnad *bnad)
667{
be7fa326 668 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
e2fa6f2e 669
8b230ed8
RM		 670 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
671}
672
673/*
674 * Called with bnad->bna_lock held b'cos of
675 * bnad->cfg_flags access.
676 */
b7ee31c5 677static void
8b230ed8
RM		 678bnad_disable_mbox_irq(struct bnad *bnad)
679{
be7fa326 680 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
8b230ed8 681
be7fa326
RM		 682 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
683}
8b230ed8 684
be7fa326
RM		 685static void
686bnad_set_netdev_perm_addr(struct bnad *bnad)
687{
688 struct net_device *netdev = bnad->netdev;
e2fa6f2e 689
be7fa326
RM		 690 memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
691 if (is_zero_ether_addr(netdev->dev_addr))
692 memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
8b230ed8
RM		 693}
694
695/* Control Path Handlers */
696
697/* Callbacks */
698void
078086f3 699bnad_cb_mbox_intr_enable(struct bnad *bnad)
8b230ed8
RM		 700{
701 bnad_enable_mbox_irq(bnad);
702}
703
704void
078086f3 705bnad_cb_mbox_intr_disable(struct bnad *bnad)
8b230ed8
RM		 706{
707 bnad_disable_mbox_irq(bnad);
708}
709
710void
078086f3
RM		 711bnad_cb_ioceth_ready(struct bnad *bnad)
712{
713 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
714 complete(&bnad->bnad_completions.ioc_comp);
715}
716
717void
718bnad_cb_ioceth_failed(struct bnad *bnad)
8b230ed8 719{
078086f3 720 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL;
8b230ed8 721 complete(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 722}
723
724void
078086f3 725bnad_cb_ioceth_disabled(struct bnad *bnad)
8b230ed8 726{
078086f3 727 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
8b230ed8 728 complete(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 729}
730
731static void
078086f3 732bnad_cb_enet_disabled(void *arg)
8b230ed8
RM		 733{
734 struct bnad *bnad = (struct bnad *)arg;
735
8b230ed8 736 netif_carrier_off(bnad->netdev);
078086f3 737 complete(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 738}
739
740void
078086f3 741bnad_cb_ethport_link_status(struct bnad *bnad,
8b230ed8
RM		 742 enum bna_link_status link_status)
743{
3db1cd5c 744 bool link_up = false;
8b230ed8
RM		 745
746 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
747
748 if (link_status == BNA_CEE_UP) {
078086f3
RM		 749 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
750 BNAD_UPDATE_CTR(bnad, cee_toggle);
8b230ed8 751 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
078086f3
RM		 752 } else {
753 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
754 BNAD_UPDATE_CTR(bnad, cee_toggle);
8b230ed8 755 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
078086f3 756 }
8b230ed8
RM		 757
758 if (link_up) {
759 if (!netif_carrier_ok(bnad->netdev)) {
078086f3
RM		 760 uint tx_id, tcb_id;
761 printk(KERN_WARNING "bna: %s link up\n",
8b230ed8
RM		 762 bnad->netdev->name);
763 netif_carrier_on(bnad->netdev);
764 BNAD_UPDATE_CTR(bnad, link_toggle);
078086f3
RM		 765 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
766 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx;
767 tcb_id++) {
768 struct bna_tcb *tcb =
769 bnad->tx_info[tx_id].tcb[tcb_id];
770 u32 txq_id;
771 if (!tcb)
772 continue;
773
774 txq_id = tcb->id;
775
776 if (test_bit(BNAD_TXQ_TX_STARTED,
777 &tcb->flags)) {
778 /*
779 * Force an immediate
780 * Transmit Schedule */
781 printk(KERN_INFO "bna: %s %d "
782 "TXQ_STARTED\n",
783 bnad->netdev->name,
784 txq_id);
785 netif_wake_subqueue(
786 bnad->netdev,
787 txq_id);
788 BNAD_UPDATE_CTR(bnad,
789 netif_queue_wakeup);
790 } else {
791 netif_stop_subqueue(
792 bnad->netdev,
793 txq_id);
794 BNAD_UPDATE_CTR(bnad,
795 netif_queue_stop);
796 }
797 }
8b230ed8
RM		 798 }
799 }
800 } else {
801 if (netif_carrier_ok(bnad->netdev)) {
078086f3 802 printk(KERN_WARNING "bna: %s link down\n",
8b230ed8
RM		 803 bnad->netdev->name);
804 netif_carrier_off(bnad->netdev);
805 BNAD_UPDATE_CTR(bnad, link_toggle);
806 }
807 }
808}
809
810static void
078086f3 811bnad_cb_tx_disabled(void *arg, struct bna_tx *tx)
8b230ed8
RM		 812{
813 struct bnad *bnad = (struct bnad *)arg;
814
815 complete(&bnad->bnad_completions.tx_comp);
816}
817
818static void
819bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
820{
821 struct bnad_tx_info *tx_info =
822 (struct bnad_tx_info *)tcb->txq->tx->priv;
823 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
824
825 tx_info->tcb[tcb->id] = tcb;
826 unmap_q->producer_index = 0;
827 unmap_q->consumer_index = 0;
828 unmap_q->q_depth = BNAD_TX_UNMAPQ_DEPTH;
829}
830
831static void
832bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
833{
834 struct bnad_tx_info *tx_info =
835 (struct bnad_tx_info *)tcb->txq->tx->priv;
836
837 tx_info->tcb[tcb->id] = NULL;
01b54b14 838 tcb->priv = NULL;
8b230ed8
RM		 839}
840
841static void
842bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb)
843{
844 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
845
846 unmap_q->producer_index = 0;
847 unmap_q->consumer_index = 0;
848 unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH;
849}
850
851static void
852bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
853{
854 struct bnad_rx_info *rx_info =
855 (struct bnad_rx_info *)ccb->cq->rx->priv;
856
857 rx_info->rx_ctrl[ccb->id].ccb = ccb;
858 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
859}
860
861static void
862bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
863{
864 struct bnad_rx_info *rx_info =
865 (struct bnad_rx_info *)ccb->cq->rx->priv;
866
867 rx_info->rx_ctrl[ccb->id].ccb = NULL;
868}
869
870static void
078086f3 871bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
8b230ed8
RM		 872{
873 struct bnad_tx_info *tx_info =
078086f3
RM		 874 (struct bnad_tx_info *)tx->priv;
875 struct bna_tcb *tcb;
876 u32 txq_id;
877 int i;
8b230ed8 878
078086f3
RM		 879 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
880 tcb = tx_info->tcb[i];
881 if (!tcb)
882 continue;
883 txq_id = tcb->id;
884 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
885 netif_stop_subqueue(bnad->netdev, txq_id);
886 printk(KERN_INFO "bna: %s %d TXQ_STOPPED\n",
887 bnad->netdev->name, txq_id);
888 }
8b230ed8
RM		 889}
890
891static void
078086f3 892bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
8b230ed8 893{
078086f3
RM		 894 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
895 struct bna_tcb *tcb;
078086f3
RM		 896 u32 txq_id;
897 int i;
8b230ed8 898
078086f3
RM		 899 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
900 tcb = tx_info->tcb[i];
901 if (!tcb)
902 continue;
903 txq_id = tcb->id;
8b230ed8 904
01b54b14 905 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags));
078086f3 906 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
01b54b14 907 BUG_ON(*(tcb->hw_consumer_index) != 0);
078086f3
RM		 908
909 if (netif_carrier_ok(bnad->netdev)) {
910 printk(KERN_INFO "bna: %s %d TXQ_STARTED\n",
911 bnad->netdev->name, txq_id);
912 netif_wake_subqueue(bnad->netdev, txq_id);
913 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
914 }
915 }
be7fa326
RM		 916
917 /*
078086f3 918 * Workaround for first ioceth enable failure & we
be7fa326
RM		 919 * get a 0 MAC address. We try to get the MAC address
920 * again here.
921 */
922 if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
078086f3 923 bna_enet_perm_mac_get(&bnad->bna.enet, &bnad->perm_addr);
be7fa326
RM		 924 bnad_set_netdev_perm_addr(bnad);
925 }
be7fa326
RM		 926}
927
01b54b14
JH		 928/*
929 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
930 */
931static void
932bnad_tx_cleanup(struct delayed_work *work)
933{
934 struct bnad_tx_info *tx_info =
935 container_of(work, struct bnad_tx_info, tx_cleanup_work);
936 struct bnad *bnad = NULL;
937 struct bnad_unmap_q *unmap_q;
938 struct bna_tcb *tcb;
939 unsigned long flags;
940 uint32_t i, pending = 0;
941
942 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
943 tcb = tx_info->tcb[i];
944 if (!tcb)
945 continue;
946
947 bnad = tcb->bnad;
948
949 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
950 pending++;
951 continue;
952 }
953
954 bnad_free_all_txbufs(bnad, tcb);
955
956 unmap_q = tcb->unmap_q;
957 unmap_q->producer_index = 0;
958 unmap_q->consumer_index = 0;
959
960 smp_mb__before_clear_bit();
961 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
962 }
963
964 if (pending) {
965 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work,
966 msecs_to_jiffies(1));
967 return;
968 }
969
970 spin_lock_irqsave(&bnad->bna_lock, flags);
971 bna_tx_cleanup_complete(tx_info->tx);
972 spin_unlock_irqrestore(&bnad->bna_lock, flags);
973}
974
975
be7fa326 976static void
078086f3 977bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
be7fa326 978{
078086f3
RM		 979 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
980 struct bna_tcb *tcb;
981 int i;
982
983 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
984 tcb = tx_info->tcb[i];
985 if (!tcb)
986 continue;
987 }
988
01b54b14 989 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0);
8b230ed8
RM		 990}
991
5bcf6ac0
RM		 992static void
993bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx)
994{
995 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
996 struct bna_ccb *ccb;
997 struct bnad_rx_ctrl *rx_ctrl;
998 int i;
999
1000 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1001 rx_ctrl = &rx_info->rx_ctrl[i];
1002 ccb = rx_ctrl->ccb;
1003 if (!ccb)
1004 continue;
1005
1006 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags);
1007
1008 if (ccb->rcb[1])
1009 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags);
1010 }
1011}
1012
01b54b14
JH		 1013/*
1014 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
1015 */
1016static void
1017bnad_rx_cleanup(void *work)
1018{
1019 struct bnad_rx_info *rx_info =
1020 container_of(work, struct bnad_rx_info, rx_cleanup_work);
1021 struct bnad_rx_ctrl *rx_ctrl;
1022 struct bnad *bnad = NULL;
1023 unsigned long flags;
1024 uint32_t i;
1025
1026 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1027 rx_ctrl = &rx_info->rx_ctrl[i];
1028
1029 if (!rx_ctrl->ccb)
1030 continue;
1031
1032 bnad = rx_ctrl->ccb->bnad;
1033
1034 /*
1035 * Wait till the poll handler has exited
1036 * and nothing can be scheduled anymore
1037 */
1038 napi_disable(&rx_ctrl->napi);
1039
1040 bnad_cq_cmpl_init(bnad, rx_ctrl->ccb);
1041 bnad_free_all_rxbufs(bnad, rx_ctrl->ccb->rcb[0]);
1042 if (rx_ctrl->ccb->rcb[1])
1043 bnad_free_all_rxbufs(bnad, rx_ctrl->ccb->rcb[1]);
1044 }
1045
1046 spin_lock_irqsave(&bnad->bna_lock, flags);
1047 bna_rx_cleanup_complete(rx_info->rx);
1048 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1049}
1050
8b230ed8 1051static void
078086f3 1052bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1053{
078086f3
RM		 1054 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1055 struct bna_ccb *ccb;
1056 struct bnad_rx_ctrl *rx_ctrl;
1057 int i;
1058
772b5235 1059 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
078086f3
RM		 1060 rx_ctrl = &rx_info->rx_ctrl[i];
1061 ccb = rx_ctrl->ccb;
1062 if (!ccb)
1063 continue;
1064
1065 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
1066
1067 if (ccb->rcb[1])
1068 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
078086f3 1069 }
be7fa326 1070
01b54b14 1071 queue_work(bnad->work_q, &rx_info->rx_cleanup_work);
8b230ed8
RM		 1072}
1073
1074static void
078086f3 1075bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1076{
078086f3
RM		 1077 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1078 struct bna_ccb *ccb;
1079 struct bna_rcb *rcb;
1080 struct bnad_rx_ctrl *rx_ctrl;
1081 struct bnad_unmap_q *unmap_q;
1082 int i;
1083 int j;
be7fa326 1084
772b5235 1085 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
078086f3
RM		 1086 rx_ctrl = &rx_info->rx_ctrl[i];
1087 ccb = rx_ctrl->ccb;
1088 if (!ccb)
1089 continue;
be7fa326 1090
01b54b14 1091 napi_enable(&rx_ctrl->napi);
8b230ed8 1092
078086f3
RM		 1093 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
1094 rcb = ccb->rcb[j];
1095 if (!rcb)
1096 continue;
078086f3
RM		 1097
1098 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
5bcf6ac0 1099 set_bit(BNAD_RXQ_POST_OK, &rcb->flags);
078086f3
RM		 1100 unmap_q = rcb->unmap_q;
1101
1102 /* Now allocate & post buffers for this RCB */
1103 /* !!Allocation in callback context */
1104 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
1105 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
1106 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
1107 bnad_alloc_n_post_rxbufs(bnad, rcb);
1108 smp_mb__before_clear_bit();
1109 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
1110 }
1111 }
8b230ed8
RM		 1112 }
1113}
1114
1115static void
078086f3 1116bnad_cb_rx_disabled(void *arg, struct bna_rx *rx)
8b230ed8
RM		 1117{
1118 struct bnad *bnad = (struct bnad *)arg;
1119
1120 complete(&bnad->bnad_completions.rx_comp);
1121}
1122
1123static void
078086f3 1124bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1125{
078086f3 1126 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS;
8b230ed8
RM		 1127 complete(&bnad->bnad_completions.mcast_comp);
1128}
1129
1130void
1131bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
1132 struct bna_stats *stats)
1133{
1134 if (status == BNA_CB_SUCCESS)
1135 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
1136
1137 if (!netif_running(bnad->netdev) ||
1138 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1139 return;
1140
1141 mod_timer(&bnad->stats_timer,
1142 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1143}
1144
078086f3
RM		 1145static void
1146bnad_cb_enet_mtu_set(struct bnad *bnad)
1147{
1148 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS;
1149 complete(&bnad->bnad_completions.mtu_comp);
1150}
1151
72a9730b
KG		 1152void
1153bnad_cb_completion(void *arg, enum bfa_status status)
1154{
1155 struct bnad_iocmd_comp *iocmd_comp =
1156 (struct bnad_iocmd_comp *)arg;
1157
1158 iocmd_comp->comp_status = (u32) status;
1159 complete(&iocmd_comp->comp);
1160}
1161
8b230ed8
RM		 1162/* Resource allocation, free functions */
1163
1164static void
1165bnad_mem_free(struct bnad *bnad,
1166 struct bna_mem_info *mem_info)
1167{
1168 int i;
1169 dma_addr_t dma_pa;
1170
1171 if (mem_info->mdl == NULL)
1172 return;
1173
1174 for (i = 0; i < mem_info->num; i++) {
1175 if (mem_info->mdl[i].kva != NULL) {
1176 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1177 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1178 dma_pa);
5ea74318
IV		 1179 dma_free_coherent(&bnad->pcidev->dev,
1180 mem_info->mdl[i].len,
1181 mem_info->mdl[i].kva, dma_pa);
8b230ed8
RM		 1182 } else
1183 kfree(mem_info->mdl[i].kva);
1184 }
1185 }
1186 kfree(mem_info->mdl);
1187 mem_info->mdl = NULL;
1188}
1189
1190static int
1191bnad_mem_alloc(struct bnad *bnad,
1192 struct bna_mem_info *mem_info)
1193{
1194 int i;
1195 dma_addr_t dma_pa;
1196
1197 if ((mem_info->num == 0) || (mem_info->len == 0)) {
1198 mem_info->mdl = NULL;
1199 return 0;
1200 }
1201
1202 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1203 GFP_KERNEL);
1204 if (mem_info->mdl == NULL)
1205 return -ENOMEM;
1206
1207 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1208 for (i = 0; i < mem_info->num; i++) {
1209 mem_info->mdl[i].len = mem_info->len;
1210 mem_info->mdl[i].kva =
5ea74318
IV		 1211 dma_alloc_coherent(&bnad->pcidev->dev,
1212 mem_info->len, &dma_pa,
1213 GFP_KERNEL);
8b230ed8
RM		 1214
1215 if (mem_info->mdl[i].kva == NULL)
1216 goto err_return;
1217
1218 BNA_SET_DMA_ADDR(dma_pa,
1219 &(mem_info->mdl[i].dma));
1220 }
1221 } else {
1222 for (i = 0; i < mem_info->num; i++) {
1223 mem_info->mdl[i].len = mem_info->len;
1224 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1225 GFP_KERNEL);
1226 if (mem_info->mdl[i].kva == NULL)
1227 goto err_return;
1228 }
1229 }
1230
1231 return 0;
1232
1233err_return:
1234 bnad_mem_free(bnad, mem_info);
1235 return -ENOMEM;
1236}
1237
1238/* Free IRQ for Mailbox */
1239static void
078086f3 1240bnad_mbox_irq_free(struct bnad *bnad)
8b230ed8
RM		 1241{
1242 int irq;
1243 unsigned long flags;
1244
8b230ed8 1245 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 1246 bnad_disable_mbox_irq(bnad);
e2fa6f2e 1247 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1248
1249 irq = BNAD_GET_MBOX_IRQ(bnad);
be7fa326 1250 free_irq(irq, bnad);
8b230ed8
RM		 1251}
1252
1253/*
1254 * Allocates IRQ for Mailbox, but keep it disabled
1255 * This will be enabled once we get the mbox enable callback
1256 * from bna
1257 */
1258static int
078086f3 1259bnad_mbox_irq_alloc(struct bnad *bnad)
8b230ed8 1260{
0120b99c
RM		 1261 int err = 0;
1262 unsigned long irq_flags, flags;
8b230ed8 1263 u32 irq;
0120b99c 1264 irq_handler_t irq_handler;
8b230ed8 1265
8b230ed8
RM		 1266 spin_lock_irqsave(&bnad->bna_lock, flags);
1267 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1268 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
8811e267 1269 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
8279171a 1270 irq_flags = 0;
8b230ed8
RM		 1271 } else {
1272 irq_handler = (irq_handler_t)bnad_isr;
1273 irq = bnad->pcidev->irq;
5f77898d 1274 irq_flags = IRQF_SHARED;
8b230ed8 1275 }
8811e267 1276
8b230ed8 1277 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1278 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1279
e2fa6f2e
RM		 1280 /*
1281 * Set the Mbox IRQ disable flag, so that the IRQ handler
1282 * called from request_irq() for SHARED IRQs do not execute
1283 */
1284 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1285
be7fa326
RM		 1286 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1287
8279171a 1288 err = request_irq(irq, irq_handler, irq_flags,
be7fa326 1289 bnad->mbox_irq_name, bnad);
e2fa6f2e 1290
be7fa326 1291 return err;
8b230ed8
RM		 1292}
1293
1294static void
1295bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1296{
1297 kfree(intr_info->idl);
1298 intr_info->idl = NULL;
1299}
1300
1301/* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1302static int
1303bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
078086f3 1304 u32 txrx_id, struct bna_intr_info *intr_info)
8b230ed8
RM		 1305{
1306 int i, vector_start = 0;
1307 u32 cfg_flags;
1308 unsigned long flags;
1309
1310 spin_lock_irqsave(&bnad->bna_lock, flags);
1311 cfg_flags = bnad->cfg_flags;
1312 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1313
1314 if (cfg_flags & BNAD_CF_MSIX) {
1315 intr_info->intr_type = BNA_INTR_T_MSIX;
1316 intr_info->idl = kcalloc(intr_info->num,
1317 sizeof(struct bna_intr_descr),
1318 GFP_KERNEL);
1319 if (!intr_info->idl)
1320 return -ENOMEM;
1321
1322 switch (src) {
1323 case BNAD_INTR_TX:
8811e267 1324 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id;
8b230ed8
RM		 1325 break;
1326
1327 case BNAD_INTR_RX:
8811e267
RM		 1328 vector_start = BNAD_MAILBOX_MSIX_VECTORS +
1329 (bnad->num_tx * bnad->num_txq_per_tx) +
8b230ed8
RM		 1330 txrx_id;
1331 break;
1332
1333 default:
1334 BUG();
1335 }
1336
1337 for (i = 0; i < intr_info->num; i++)
1338 intr_info->idl[i].vector = vector_start + i;
1339 } else {
1340 intr_info->intr_type = BNA_INTR_T_INTX;
1341 intr_info->num = 1;
1342 intr_info->idl = kcalloc(intr_info->num,
1343 sizeof(struct bna_intr_descr),
1344 GFP_KERNEL);
1345 if (!intr_info->idl)
1346 return -ENOMEM;
1347
1348 switch (src) {
1349 case BNAD_INTR_TX:
8811e267 1350 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK;
8b230ed8
RM		 1351 break;
1352
1353 case BNAD_INTR_RX:
8811e267 1354 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK;
8b230ed8
RM		 1355 break;
1356 }
1357 }
1358 return 0;
1359}
1360
1361/**
1362 * NOTE: Should be called for MSIX only
1363 * Unregisters Tx MSIX vector(s) from the kernel
1364 */
1365static void
1366bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1367 int num_txqs)
1368{
1369 int i;
1370 int vector_num;
1371
1372 for (i = 0; i < num_txqs; i++) {
1373 if (tx_info->tcb[i] == NULL)
1374 continue;
1375
1376 vector_num = tx_info->tcb[i]->intr_vector;
1377 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1378 }
1379}
1380
1381/**
1382 * NOTE: Should be called for MSIX only
1383 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1384 */
1385static int
1386bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
078086f3 1387 u32 tx_id, int num_txqs)
8b230ed8
RM		 1388{
1389 int i;
1390 int err;
1391 int vector_num;
1392
1393 for (i = 0; i < num_txqs; i++) {
1394 vector_num = tx_info->tcb[i]->intr_vector;
1395 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1396 tx_id + tx_info->tcb[i]->id);
1397 err = request_irq(bnad->msix_table[vector_num].vector,
1398 (irq_handler_t)bnad_msix_tx, 0,
1399 tx_info->tcb[i]->name,
1400 tx_info->tcb[i]);
1401 if (err)
1402 goto err_return;
1403 }
1404
1405 return 0;
1406
1407err_return:
1408 if (i > 0)
1409 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1410 return -1;
1411}
1412
1413/**
1414 * NOTE: Should be called for MSIX only
1415 * Unregisters Rx MSIX vector(s) from the kernel
1416 */
1417static void
1418bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1419 int num_rxps)
1420{
1421 int i;
1422 int vector_num;
1423
1424 for (i = 0; i < num_rxps; i++) {
1425 if (rx_info->rx_ctrl[i].ccb == NULL)
1426 continue;
1427
1428 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1429 free_irq(bnad->msix_table[vector_num].vector,
1430 rx_info->rx_ctrl[i].ccb);
1431 }
1432}
1433
1434/**
1435 * NOTE: Should be called for MSIX only
1436 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1437 */
1438static int
1439bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
078086f3 1440 u32 rx_id, int num_rxps)
8b230ed8
RM		 1441{
1442 int i;
1443 int err;
1444 int vector_num;
1445
1446 for (i = 0; i < num_rxps; i++) {
1447 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1448 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1449 bnad->netdev->name,
1450 rx_id + rx_info->rx_ctrl[i].ccb->id);
1451 err = request_irq(bnad->msix_table[vector_num].vector,
1452 (irq_handler_t)bnad_msix_rx, 0,
1453 rx_info->rx_ctrl[i].ccb->name,
1454 rx_info->rx_ctrl[i].ccb);
1455 if (err)
1456 goto err_return;
1457 }
1458
1459 return 0;
1460
1461err_return:
1462 if (i > 0)
1463 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1464 return -1;
1465}
1466
1467/* Free Tx object Resources */
1468static void
1469bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1470{
1471 int i;
1472
1473 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1474 if (res_info[i].res_type == BNA_RES_T_MEM)
1475 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1476 else if (res_info[i].res_type == BNA_RES_T_INTR)
1477 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1478 }
1479}
1480
1481/* Allocates memory and interrupt resources for Tx object */
1482static int
1483bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
078086f3 1484 u32 tx_id)
8b230ed8
RM		 1485{
1486 int i, err = 0;
1487
1488 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1489 if (res_info[i].res_type == BNA_RES_T_MEM)
1490 err = bnad_mem_alloc(bnad,
1491 &res_info[i].res_u.mem_info);
1492 else if (res_info[i].res_type == BNA_RES_T_INTR)
1493 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1494 &res_info[i].res_u.intr_info);
1495 if (err)
1496 goto err_return;
1497 }
1498 return 0;
1499
1500err_return:
1501 bnad_tx_res_free(bnad, res_info);
1502 return err;
1503}
1504
1505/* Free Rx object Resources */
1506static void
1507bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1508{
1509 int i;
1510
1511 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1512 if (res_info[i].res_type == BNA_RES_T_MEM)
1513 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1514 else if (res_info[i].res_type == BNA_RES_T_INTR)
1515 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1516 }
1517}
1518
1519/* Allocates memory and interrupt resources for Rx object */
1520static int
1521bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1522 uint rx_id)
1523{
1524 int i, err = 0;
1525
1526 /* All memory needs to be allocated before setup_ccbs */
1527 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1528 if (res_info[i].res_type == BNA_RES_T_MEM)
1529 err = bnad_mem_alloc(bnad,
1530 &res_info[i].res_u.mem_info);
1531 else if (res_info[i].res_type == BNA_RES_T_INTR)
1532 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1533 &res_info[i].res_u.intr_info);
1534 if (err)
1535 goto err_return;
1536 }
1537 return 0;
1538
1539err_return:
1540 bnad_rx_res_free(bnad, res_info);
1541 return err;
1542}
1543
1544/* Timer callbacks */
1545/* a) IOC timer */
1546static void
1547bnad_ioc_timeout(unsigned long data)
1548{
1549 struct bnad *bnad = (struct bnad *)data;
1550 unsigned long flags;
1551
1552 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1553 bfa_nw_ioc_timeout((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1554 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1555}
1556
1557static void
1558bnad_ioc_hb_check(unsigned long data)
1559{
1560 struct bnad *bnad = (struct bnad *)data;
1561 unsigned long flags;
1562
1563 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1564 bfa_nw_ioc_hb_check((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1565 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1566}
1567
1568static void
1d32f769 1569bnad_iocpf_timeout(unsigned long data)
8b230ed8
RM		 1570{
1571 struct bnad *bnad = (struct bnad *)data;
1572 unsigned long flags;
1573
1574 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1575 bfa_nw_iocpf_timeout((void *) &bnad->bna.ioceth.ioc);
1d32f769
RM		 1576 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1577}
1578
1579static void
1580bnad_iocpf_sem_timeout(unsigned long data)
1581{
1582 struct bnad *bnad = (struct bnad *)data;
1583 unsigned long flags;
1584
1585 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1586 bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1587 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1588}
1589
1590/*
1591 * All timer routines use bnad->bna_lock to protect against
1592 * the following race, which may occur in case of no locking:
0120b99c 1593 * Time CPU m CPU n
8b230ed8
RM		 1594 * 0 1 = test_bit
1595 * 1 clear_bit
1596 * 2 del_timer_sync
1597 * 3 mod_timer
1598 */
1599
1600/* b) Dynamic Interrupt Moderation Timer */
1601static void
1602bnad_dim_timeout(unsigned long data)
1603{
1604 struct bnad *bnad = (struct bnad *)data;
1605 struct bnad_rx_info *rx_info;
1606 struct bnad_rx_ctrl *rx_ctrl;
1607 int i, j;
1608 unsigned long flags;
1609
1610 if (!netif_carrier_ok(bnad->netdev))
1611 return;
1612
1613 spin_lock_irqsave(&bnad->bna_lock, flags);
1614 for (i = 0; i < bnad->num_rx; i++) {
1615 rx_info = &bnad->rx_info[i];
1616 if (!rx_info->rx)
1617 continue;
1618 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1619 rx_ctrl = &rx_info->rx_ctrl[j];
1620 if (!rx_ctrl->ccb)
1621 continue;
1622 bna_rx_dim_update(rx_ctrl->ccb);
1623 }
1624 }
1625
1626 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1627 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1628 mod_timer(&bnad->dim_timer,
1629 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1630 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1631}
1632
1633/* c) Statistics Timer */
1634static void
1635bnad_stats_timeout(unsigned long data)
1636{
1637 struct bnad *bnad = (struct bnad *)data;
1638 unsigned long flags;
1639
1640 if (!netif_running(bnad->netdev) ||
1641 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1642 return;
1643
1644 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1645 bna_hw_stats_get(&bnad->bna);
8b230ed8
RM		 1646 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1647}
1648
1649/*
1650 * Set up timer for DIM
1651 * Called with bnad->bna_lock held
1652 */
1653void
1654bnad_dim_timer_start(struct bnad *bnad)
1655{
1656 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1657 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1658 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1659 (unsigned long)bnad);
1660 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1661 mod_timer(&bnad->dim_timer,
1662 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1663 }
1664}
1665
1666/*
1667 * Set up timer for statistics
1668 * Called with mutex_lock(&bnad->conf_mutex) held
1669 */
1670static void
1671bnad_stats_timer_start(struct bnad *bnad)
1672{
1673 unsigned long flags;
1674
1675 spin_lock_irqsave(&bnad->bna_lock, flags);
1676 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1677 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1678 (unsigned long)bnad);
1679 mod_timer(&bnad->stats_timer,
1680 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1681 }
1682 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1683}
1684
1685/*
1686 * Stops the stats timer
1687 * Called with mutex_lock(&bnad->conf_mutex) held
1688 */
1689static void
1690bnad_stats_timer_stop(struct bnad *bnad)
1691{
1692 int to_del = 0;
1693 unsigned long flags;
1694
1695 spin_lock_irqsave(&bnad->bna_lock, flags);
1696 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1697 to_del = 1;
1698 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1699 if (to_del)
1700 del_timer_sync(&bnad->stats_timer);
1701}
1702
1703/* Utilities */
1704
1705static void
1706bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1707{
1708 int i = 1; /* Index 0 has broadcast address */
1709 struct netdev_hw_addr *mc_addr;
1710
1711 netdev_for_each_mc_addr(mc_addr, netdev) {
1712 memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
1713 ETH_ALEN);
1714 i++;
1715 }
1716}
1717
1718static int
1719bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1720{
1721 struct bnad_rx_ctrl *rx_ctrl =
1722 container_of(napi, struct bnad_rx_ctrl, napi);
2be67144 1723 struct bnad *bnad = rx_ctrl->bnad;
8b230ed8
RM		 1724 int rcvd = 0;
1725
271e8b79 1726 rx_ctrl->rx_poll_ctr++;
8b230ed8
RM		 1727
1728 if (!netif_carrier_ok(bnad->netdev))
1729 goto poll_exit;
1730
2be67144 1731 rcvd = bnad_poll_cq(bnad, rx_ctrl->ccb, budget);
271e8b79 1732 if (rcvd >= budget)
8b230ed8
RM		 1733 return rcvd;
1734
1735poll_exit:
19dbff9f 1736 napi_complete(napi);
8b230ed8 1737
271e8b79 1738 rx_ctrl->rx_complete++;
2be67144
RM		 1739
1740 if (rx_ctrl->ccb)
271e8b79
RM		 1741 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb);
1742
8b230ed8
RM		 1743 return rcvd;
1744}
1745
2be67144 1746#define BNAD_NAPI_POLL_QUOTA 64
8b230ed8 1747static void
01b54b14 1748bnad_napi_add(struct bnad *bnad, u32 rx_id)
8b230ed8 1749{
8b230ed8
RM		 1750 struct bnad_rx_ctrl *rx_ctrl;
1751 int i;
8b230ed8
RM		 1752
1753 /* Initialize & enable NAPI */
1754 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1755 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1756 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
2be67144
RM		 1757 bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA);
1758 }
1759}
1760
1761static void
01b54b14 1762bnad_napi_delete(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 1763{
1764 int i;
1765
1766 /* First disable and then clean up */
01b54b14 1767 for (i = 0; i < bnad->num_rxp_per_rx; i++)
8b230ed8 1768 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
8b230ed8
RM		 1769}
1770
1771/* Should be held with conf_lock held */
1772void
078086f3 1773bnad_cleanup_tx(struct bnad *bnad, u32 tx_id)
8b230ed8
RM		 1774{
1775 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1776 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1777 unsigned long flags;
1778
1779 if (!tx_info->tx)
1780 return;
1781
1782 init_completion(&bnad->bnad_completions.tx_comp);
1783 spin_lock_irqsave(&bnad->bna_lock, flags);
1784 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1785 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1786 wait_for_completion(&bnad->bnad_completions.tx_comp);
1787
1788 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1789 bnad_tx_msix_unregister(bnad, tx_info,
1790 bnad->num_txq_per_tx);
1791
2be67144
RM		 1792 if (0 == tx_id)
1793 tasklet_kill(&bnad->tx_free_tasklet);
1794
8b230ed8
RM		 1795 spin_lock_irqsave(&bnad->bna_lock, flags);
1796 bna_tx_destroy(tx_info->tx);
1797 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1798
1799 tx_info->tx = NULL;
078086f3 1800 tx_info->tx_id = 0;
8b230ed8 1801
8b230ed8
RM		 1802 bnad_tx_res_free(bnad, res_info);
1803}
1804
1805/* Should be held with conf_lock held */
1806int
078086f3 1807bnad_setup_tx(struct bnad *bnad, u32 tx_id)
8b230ed8
RM		 1808{
1809 int err;
1810 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1811 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1812 struct bna_intr_info *intr_info =
1813 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1814 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
d91d25d5 1815 static const struct bna_tx_event_cbfn tx_cbfn = {
1816 .tcb_setup_cbfn = bnad_cb_tcb_setup,
1817 .tcb_destroy_cbfn = bnad_cb_tcb_destroy,
1818 .tx_stall_cbfn = bnad_cb_tx_stall,
1819 .tx_resume_cbfn = bnad_cb_tx_resume,
1820 .tx_cleanup_cbfn = bnad_cb_tx_cleanup,
1821 };
1822
8b230ed8
RM		 1823 struct bna_tx *tx;
1824 unsigned long flags;
1825
078086f3
RM		 1826 tx_info->tx_id = tx_id;
1827
8b230ed8
RM		 1828 /* Initialize the Tx object configuration */
1829 tx_config->num_txq = bnad->num_txq_per_tx;
1830 tx_config->txq_depth = bnad->txq_depth;
1831 tx_config->tx_type = BNA_TX_T_REGULAR;
078086f3 1832 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo;
8b230ed8 1833
8b230ed8
RM		 1834 /* Get BNA's resource requirement for one tx object */
1835 spin_lock_irqsave(&bnad->bna_lock, flags);
1836 bna_tx_res_req(bnad->num_txq_per_tx,
1837 bnad->txq_depth, res_info);
1838 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1839
1840 /* Fill Unmap Q memory requirements */
1841 BNAD_FILL_UNMAPQ_MEM_REQ(
1842 &res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1843 bnad->num_txq_per_tx,
1844 BNAD_TX_UNMAPQ_DEPTH);
1845
1846 /* Allocate resources */
1847 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1848 if (err)
1849 return err;
1850
1851 /* Ask BNA to create one Tx object, supplying required resources */
1852 spin_lock_irqsave(&bnad->bna_lock, flags);
1853 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
1854 tx_info);
1855 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1856 if (!tx)
1857 goto err_return;
1858 tx_info->tx = tx;
1859
01b54b14
JH		 1860 INIT_DELAYED_WORK(&tx_info->tx_cleanup_work,
1861 (work_func_t)bnad_tx_cleanup);
1862
8b230ed8
RM		 1863 /* Register ISR for the Tx object */
1864 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1865 err = bnad_tx_msix_register(bnad, tx_info,
1866 tx_id, bnad->num_txq_per_tx);
1867 if (err)
1868 goto err_return;
1869 }
1870
1871 spin_lock_irqsave(&bnad->bna_lock, flags);
1872 bna_tx_enable(tx);
1873 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1874
1875 return 0;
1876
1877err_return:
1878 bnad_tx_res_free(bnad, res_info);
1879 return err;
1880}
1881
1882/* Setup the rx config for bna_rx_create */
1883/* bnad decides the configuration */
1884static void
1885bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
1886{
1887 rx_config->rx_type = BNA_RX_T_REGULAR;
1888 rx_config->num_paths = bnad->num_rxp_per_rx;
078086f3 1889 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo;
8b230ed8
RM		 1890
1891 if (bnad->num_rxp_per_rx > 1) {
1892 rx_config->rss_status = BNA_STATUS_T_ENABLED;
1893 rx_config->rss_config.hash_type =
078086f3
RM		 1894 (BFI_ENET_RSS_IPV6 |
1895 BFI_ENET_RSS_IPV6_TCP |
1896 BFI_ENET_RSS_IPV4 |
1897 BFI_ENET_RSS_IPV4_TCP);
8b230ed8
RM		 1898 rx_config->rss_config.hash_mask =
1899 bnad->num_rxp_per_rx - 1;
1900 get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
1901 sizeof(rx_config->rss_config.toeplitz_hash_key));
1902 } else {
1903 rx_config->rss_status = BNA_STATUS_T_DISABLED;
1904 memset(&rx_config->rss_config, 0,
1905 sizeof(rx_config->rss_config));
1906 }
1907 rx_config->rxp_type = BNA_RXP_SLR;
1908 rx_config->q_depth = bnad->rxq_depth;
1909
1910 rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE;
1911
1912 rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED;
1913}
1914
2be67144
RM		 1915static void
1916bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id)
1917{
1918 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1919 int i;
1920
1921 for (i = 0; i < bnad->num_rxp_per_rx; i++)
1922 rx_info->rx_ctrl[i].bnad = bnad;
1923}
1924
8b230ed8
RM		 1925/* Called with mutex_lock(&bnad->conf_mutex) held */
1926void
078086f3 1927bnad_cleanup_rx(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 1928{
1929 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1930 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1931 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1932 unsigned long flags;
271e8b79 1933 int to_del = 0;
8b230ed8
RM		 1934
1935 if (!rx_info->rx)
1936 return;
1937
1938 if (0 == rx_id) {
1939 spin_lock_irqsave(&bnad->bna_lock, flags);
271e8b79
RM		 1940 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1941 test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
8b230ed8 1942 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
271e8b79
RM		 1943 to_del = 1;
1944 }
8b230ed8 1945 spin_unlock_irqrestore(&bnad->bna_lock, flags);
271e8b79 1946 if (to_del)
8b230ed8
RM		 1947 del_timer_sync(&bnad->dim_timer);
1948 }
1949
8b230ed8
RM		 1950 init_completion(&bnad->bnad_completions.rx_comp);
1951 spin_lock_irqsave(&bnad->bna_lock, flags);
1952 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
1953 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1954 wait_for_completion(&bnad->bnad_completions.rx_comp);
1955
1956 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
1957 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
1958
01b54b14 1959 bnad_napi_delete(bnad, rx_id);
2be67144 1960
8b230ed8
RM		 1961 spin_lock_irqsave(&bnad->bna_lock, flags);
1962 bna_rx_destroy(rx_info->rx);
8b230ed8
RM		 1963
1964 rx_info->rx = NULL;
3caa1e95 1965 rx_info->rx_id = 0;
b9fa1fbf 1966 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1967
1968 bnad_rx_res_free(bnad, res_info);
1969}
1970
1971/* Called with mutex_lock(&bnad->conf_mutex) held */
1972int
078086f3 1973bnad_setup_rx(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 1974{
1975 int err;
1976 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1977 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1978 struct bna_intr_info *intr_info =
1979 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
1980 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
d91d25d5 1981 static const struct bna_rx_event_cbfn rx_cbfn = {
1982 .rcb_setup_cbfn = bnad_cb_rcb_setup,
01b54b14 1983 .rcb_destroy_cbfn = NULL,
d91d25d5 1984 .ccb_setup_cbfn = bnad_cb_ccb_setup,
1985 .ccb_destroy_cbfn = bnad_cb_ccb_destroy,
5bcf6ac0 1986 .rx_stall_cbfn = bnad_cb_rx_stall,
d91d25d5 1987 .rx_cleanup_cbfn = bnad_cb_rx_cleanup,
1988 .rx_post_cbfn = bnad_cb_rx_post,
1989 };
8b230ed8
RM		 1990 struct bna_rx *rx;
1991 unsigned long flags;
1992
078086f3
RM		 1993 rx_info->rx_id = rx_id;
1994
8b230ed8
RM		 1995 /* Initialize the Rx object configuration */
1996 bnad_init_rx_config(bnad, rx_config);
1997
8b230ed8
RM		 1998 /* Get BNA's resource requirement for one Rx object */
1999 spin_lock_irqsave(&bnad->bna_lock, flags);
2000 bna_rx_res_req(rx_config, res_info);
2001 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2002
2003 /* Fill Unmap Q memory requirements */
2004 BNAD_FILL_UNMAPQ_MEM_REQ(
2005 &res_info[BNA_RX_RES_MEM_T_UNMAPQ],
2006 rx_config->num_paths +
2007 ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 0 :
2008 rx_config->num_paths), BNAD_RX_UNMAPQ_DEPTH);
2009
2010 /* Allocate resource */
2011 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
2012 if (err)
2013 return err;
2014
2be67144
RM		 2015 bnad_rx_ctrl_init(bnad, rx_id);
2016
8b230ed8
RM		 2017 /* Ask BNA to create one Rx object, supplying required resources */
2018 spin_lock_irqsave(&bnad->bna_lock, flags);
2019 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
2020 rx_info);
3caa1e95
RM		 2021 if (!rx) {
2022 err = -ENOMEM;
b9fa1fbf 2023 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 2024 goto err_return;
3caa1e95 2025 }
8b230ed8 2026 rx_info->rx = rx;
b9fa1fbf 2027 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 2028
01b54b14
JH		 2029 INIT_WORK(&rx_info->rx_cleanup_work,
2030 (work_func_t)(bnad_rx_cleanup));
2031
2be67144
RM		 2032 /*
2033 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
2034 * so that IRQ handler cannot schedule NAPI at this point.
2035 */
01b54b14 2036 bnad_napi_add(bnad, rx_id);
2be67144 2037
8b230ed8
RM		 2038 /* Register ISR for the Rx object */
2039 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2040 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
2041 rx_config->num_paths);
2042 if (err)
2043 goto err_return;
2044 }
2045
8b230ed8
RM		 2046 spin_lock_irqsave(&bnad->bna_lock, flags);
2047 if (0 == rx_id) {
2048 /* Set up Dynamic Interrupt Moderation Vector */
2049 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
2050 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
2051
2052 /* Enable VLAN filtering only on the default Rx */
2053 bna_rx_vlanfilter_enable(rx);
2054
2055 /* Start the DIM timer */
2056 bnad_dim_timer_start(bnad);
2057 }
2058
2059 bna_rx_enable(rx);
2060 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2061
2062 return 0;
2063
2064err_return:
2065 bnad_cleanup_rx(bnad, rx_id);
2066 return err;
2067}
2068
2069/* Called with conf_lock & bnad->bna_lock held */
2070void
2071bnad_tx_coalescing_timeo_set(struct bnad *bnad)
2072{
2073 struct bnad_tx_info *tx_info;
2074
2075 tx_info = &bnad->tx_info[0];
2076 if (!tx_info->tx)
2077 return;
2078
2079 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
2080}
2081
2082/* Called with conf_lock & bnad->bna_lock held */
2083void
2084bnad_rx_coalescing_timeo_set(struct bnad *bnad)
2085{
2086 struct bnad_rx_info *rx_info;
0120b99c 2087 int i;
8b230ed8
RM		 2088
2089 for (i = 0; i < bnad->num_rx; i++) {
2090 rx_info = &bnad->rx_info[i];
2091 if (!rx_info->rx)
2092 continue;
2093 bna_rx_coalescing_timeo_set(rx_info->rx,
2094 bnad->rx_coalescing_timeo);
2095 }
2096}
2097
2098/*
2099 * Called with bnad->bna_lock held
2100 */
a2122d95 2101int
8b230ed8
RM		 2102bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
2103{
2104 int ret;
2105
2106 if (!is_valid_ether_addr(mac_addr))
2107 return -EADDRNOTAVAIL;
2108
2109 /* If datapath is down, pretend everything went through */
2110 if (!bnad->rx_info[0].rx)
2111 return 0;
2112
2113 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
2114 if (ret != BNA_CB_SUCCESS)
2115 return -EADDRNOTAVAIL;
2116
2117 return 0;
2118}
2119
2120/* Should be called with conf_lock held */
a2122d95 2121int
8b230ed8
RM		 2122bnad_enable_default_bcast(struct bnad *bnad)
2123{
2124 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
2125 int ret;
2126 unsigned long flags;
2127
2128 init_completion(&bnad->bnad_completions.mcast_comp);
2129
2130 spin_lock_irqsave(&bnad->bna_lock, flags);
2131 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
2132 bnad_cb_rx_mcast_add);
2133 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2134
2135 if (ret == BNA_CB_SUCCESS)
2136 wait_for_completion(&bnad->bnad_completions.mcast_comp);
2137 else
2138 return -ENODEV;
2139
2140 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
2141 return -ENODEV;
2142
2143 return 0;
2144}
2145
19dbff9f 2146/* Called with mutex_lock(&bnad->conf_mutex) held */
a2122d95 2147void
aad75b66
RM		 2148bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
2149{
f859d7cb 2150 u16 vid;
aad75b66
RM		 2151 unsigned long flags;
2152
f859d7cb 2153 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) {
aad75b66 2154 spin_lock_irqsave(&bnad->bna_lock, flags);
f859d7cb 2155 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid);
aad75b66
RM		 2156 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2157 }
2158}
2159
8b230ed8
RM		 2160/* Statistics utilities */
2161void
250e061e 2162bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 2163{
8b230ed8
RM		 2164 int i, j;
2165
2166 for (i = 0; i < bnad->num_rx; i++) {
2167 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2168 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
250e061e 2169 stats->rx_packets += bnad->rx_info[i].
8b230ed8 2170 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
250e061e 2171 stats->rx_bytes += bnad->rx_info[i].
8b230ed8
RM		 2172 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2173 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2174 bnad->rx_info[i].rx_ctrl[j].ccb->
2175 rcb[1]->rxq) {
250e061e 2176 stats->rx_packets +=
8b230ed8
RM		 2177 bnad->rx_info[i].rx_ctrl[j].
2178 ccb->rcb[1]->rxq->rx_packets;
250e061e 2179 stats->rx_bytes +=
8b230ed8
RM		 2180 bnad->rx_info[i].rx_ctrl[j].
2181 ccb->rcb[1]->rxq->rx_bytes;
2182 }
2183 }
2184 }
2185 }
2186 for (i = 0; i < bnad->num_tx; i++) {
2187 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2188 if (bnad->tx_info[i].tcb[j]) {
250e061e 2189 stats->tx_packets +=
8b230ed8 2190 bnad->tx_info[i].tcb[j]->txq->tx_packets;
250e061e 2191 stats->tx_bytes +=
8b230ed8
RM		 2192 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2193 }
2194 }
2195 }
2196}
2197
2198/*
2199 * Must be called with the bna_lock held.
2200 */
2201void
250e061e 2202bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 2203{
078086f3
RM		 2204 struct bfi_enet_stats_mac *mac_stats;
2205 u32 bmap;
8b230ed8
RM		 2206 int i;
2207
078086f3 2208 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats;
250e061e 2209 stats->rx_errors =
8b230ed8
RM		 2210 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2211 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2212 mac_stats->rx_undersize;
250e061e 2213 stats->tx_errors = mac_stats->tx_fcs_error +
8b230ed8 2214 mac_stats->tx_undersize;
250e061e
ED		 2215 stats->rx_dropped = mac_stats->rx_drop;
2216 stats->tx_dropped = mac_stats->tx_drop;
2217 stats->multicast = mac_stats->rx_multicast;
2218 stats->collisions = mac_stats->tx_total_collision;
8b230ed8 2219
250e061e 2220 stats->rx_length_errors = mac_stats->rx_frame_length_error;
8b230ed8
RM		 2221
2222 /* receive ring buffer overflow ?? */
2223
250e061e
ED		 2224 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2225 stats->rx_frame_errors = mac_stats->rx_alignment_error;
8b230ed8 2226 /* recv'r fifo overrun */
078086f3
RM		 2227 bmap = bna_rx_rid_mask(&bnad->bna);
2228 for (i = 0; bmap; i++) {
8b230ed8 2229 if (bmap & 1) {
250e061e 2230 stats->rx_fifo_errors +=
8b230ed8 2231 bnad->stats.bna_stats->
078086f3 2232 hw_stats.rxf_stats[i].frame_drops;
8b230ed8
RM		 2233 break;
2234 }
2235 bmap >>= 1;
2236 }
2237}
2238
2239static void
2240bnad_mbox_irq_sync(struct bnad *bnad)
2241{
2242 u32 irq;
2243 unsigned long flags;
2244
2245 spin_lock_irqsave(&bnad->bna_lock, flags);
2246 if (bnad->cfg_flags & BNAD_CF_MSIX)
8811e267 2247 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
8b230ed8
RM		 2248 else
2249 irq = bnad->pcidev->irq;
2250 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2251
2252 synchronize_irq(irq);
2253}
2254
2255/* Utility used by bnad_start_xmit, for doing TSO */
2256static int
2257bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2258{
2259 int err;
2260
8b230ed8
RM		 2261 if (skb_header_cloned(skb)) {
2262 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2263 if (err) {
2264 BNAD_UPDATE_CTR(bnad, tso_err);
2265 return err;
2266 }
2267 }
2268
2269 /*
2270 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2271 * excluding the length field.
2272 */
2273 if (skb->protocol == htons(ETH_P_IP)) {
2274 struct iphdr *iph = ip_hdr(skb);
2275
2276 /* Do we really need these? */
2277 iph->tot_len = 0;
2278 iph->check = 0;
2279
2280 tcp_hdr(skb)->check =
2281 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2282 IPPROTO_TCP, 0);
2283 BNAD_UPDATE_CTR(bnad, tso4);
2284 } else {
2285 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2286
8b230ed8
RM		 2287 ipv6h->payload_len = 0;
2288 tcp_hdr(skb)->check =
2289 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2290 IPPROTO_TCP, 0);
2291 BNAD_UPDATE_CTR(bnad, tso6);
2292 }
2293
2294 return 0;
2295}
2296
2297/*
2298 * Initialize Q numbers depending on Rx Paths
2299 * Called with bnad->bna_lock held, because of cfg_flags
2300 * access.
2301 */
2302static void
2303bnad_q_num_init(struct bnad *bnad)
2304{
2305 int rxps;
2306
2307 rxps = min((uint)num_online_cpus(),
772b5235 2308 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX));
8b230ed8
RM		 2309
2310 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2311 rxps = 1; /* INTx */
2312
2313 bnad->num_rx = 1;
2314 bnad->num_tx = 1;
2315 bnad->num_rxp_per_rx = rxps;
2316 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2317}
2318
2319/*
2320 * Adjusts the Q numbers, given a number of msix vectors
2321 * Give preference to RSS as opposed to Tx priority Queues,
2322 * in such a case, just use 1 Tx Q
2323 * Called with bnad->bna_lock held b'cos of cfg_flags access
2324 */
2325static void
078086f3 2326bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp)
8b230ed8
RM		 2327{
2328 bnad->num_txq_per_tx = 1;
2329 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2330 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2331 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2332 bnad->num_rxp_per_rx = msix_vectors -
2333 (bnad->num_tx * bnad->num_txq_per_tx) -
2334 BNAD_MAILBOX_MSIX_VECTORS;
2335 } else
2336 bnad->num_rxp_per_rx = 1;
2337}
2338
078086f3
RM		 2339/* Enable / disable ioceth */
2340static int
2341bnad_ioceth_disable(struct bnad *bnad)
8b230ed8
RM		 2342{
2343 unsigned long flags;
078086f3 2344 int err = 0;
8b230ed8
RM		 2345
2346 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2347 init_completion(&bnad->bnad_completions.ioc_comp);
2348 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP);
8b230ed8
RM		 2349 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2350
078086f3
RM		 2351 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2352 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2353
2354 err = bnad->bnad_completions.ioc_comp_status;
2355 return err;
8b230ed8
RM		 2356}
2357
2358static int
078086f3 2359bnad_ioceth_enable(struct bnad *bnad)
8b230ed8
RM		 2360{
2361 int err = 0;
2362 unsigned long flags;
2363
8b230ed8 2364 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2365 init_completion(&bnad->bnad_completions.ioc_comp);
2366 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING;
2367 bna_ioceth_enable(&bnad->bna.ioceth);
8b230ed8
RM		 2368 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2369
078086f3
RM		 2370 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2371 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
8b230ed8 2372
078086f3 2373 err = bnad->bnad_completions.ioc_comp_status;
8b230ed8
RM		 2374
2375 return err;
2376}
2377
2378/* Free BNA resources */
2379static void
078086f3
RM		 2380bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info,
2381 u32 res_val_max)
8b230ed8
RM		 2382{
2383 int i;
8b230ed8 2384
078086f3
RM		 2385 for (i = 0; i < res_val_max; i++)
2386 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
8b230ed8
RM		 2387}
2388
2389/* Allocates memory and interrupt resources for BNA */
2390static int
078086f3
RM		 2391bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
2392 u32 res_val_max)
8b230ed8
RM		 2393{
2394 int i, err;
8b230ed8 2395
078086f3
RM		 2396 for (i = 0; i < res_val_max; i++) {
2397 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
8b230ed8
RM		 2398 if (err)
2399 goto err_return;
2400 }
2401 return 0;
2402
2403err_return:
078086f3 2404 bnad_res_free(bnad, res_info, res_val_max);
8b230ed8
RM		 2405 return err;
2406}
2407
2408/* Interrupt enable / disable */
2409static void
2410bnad_enable_msix(struct bnad *bnad)
2411{
2412 int i, ret;
8b230ed8
RM		 2413 unsigned long flags;
2414
2415 spin_lock_irqsave(&bnad->bna_lock, flags);
2416 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2417 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2418 return;
2419 }
2420 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2421
2422 if (bnad->msix_table)
2423 return;
2424
8b230ed8 2425 bnad->msix_table =
b7ee31c5 2426 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
8b230ed8
RM		 2427
2428 if (!bnad->msix_table)
2429 goto intx_mode;
2430
b7ee31c5 2431 for (i = 0; i < bnad->msix_num; i++)
8b230ed8
RM		 2432 bnad->msix_table[i].entry = i;
2433
b7ee31c5 2434 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num);
8b230ed8
RM		 2435 if (ret > 0) {
2436 /* Not enough MSI-X vectors. */
19dbff9f
RM		 2437 pr_warn("BNA: %d MSI-X vectors allocated < %d requested\n",
2438 ret, bnad->msix_num);
8b230ed8
RM		 2439
2440 spin_lock_irqsave(&bnad->bna_lock, flags);
2441 /* ret = #of vectors that we got */
271e8b79
RM		 2442 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2,
2443 (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2);
8b230ed8
RM		 2444 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2445
271e8b79 2446 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP +
8b230ed8 2447 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8 2448
078086f3
RM		 2449 if (bnad->msix_num > ret)
2450 goto intx_mode;
2451
8b230ed8
RM		 2452 /* Try once more with adjusted numbers */
2453 /* If this fails, fall back to INTx */
2454 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
b7ee31c5 2455 bnad->msix_num);
8b230ed8
RM		 2456 if (ret)
2457 goto intx_mode;
2458
2459 } else if (ret < 0)
2460 goto intx_mode;
078086f3
RM		 2461
2462 pci_intx(bnad->pcidev, 0);
2463
8b230ed8
RM		 2464 return;
2465
2466intx_mode:
19dbff9f 2467 pr_warn("BNA: MSI-X enable failed - operating in INTx mode\n");
8b230ed8
RM		 2468
2469 kfree(bnad->msix_table);
2470 bnad->msix_table = NULL;
2471 bnad->msix_num = 0;
8b230ed8
RM		 2472 spin_lock_irqsave(&bnad->bna_lock, flags);
2473 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2474 bnad_q_num_init(bnad);
2475 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2476}
2477
2478static void
2479bnad_disable_msix(struct bnad *bnad)
2480{
2481 u32 cfg_flags;
2482 unsigned long flags;
2483
2484 spin_lock_irqsave(&bnad->bna_lock, flags);
2485 cfg_flags = bnad->cfg_flags;
2486 if (bnad->cfg_flags & BNAD_CF_MSIX)
2487 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2488 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2489
2490 if (cfg_flags & BNAD_CF_MSIX) {
2491 pci_disable_msix(bnad->pcidev);
2492 kfree(bnad->msix_table);
2493 bnad->msix_table = NULL;
2494 }
2495}
2496
2497/* Netdev entry points */
2498static int
2499bnad_open(struct net_device *netdev)
2500{
2501 int err;
2502 struct bnad *bnad = netdev_priv(netdev);
2503 struct bna_pause_config pause_config;
2504 int mtu;
2505 unsigned long flags;
2506
2507 mutex_lock(&bnad->conf_mutex);
2508
2509 /* Tx */
2510 err = bnad_setup_tx(bnad, 0);
2511 if (err)
2512 goto err_return;
2513
2514 /* Rx */
2515 err = bnad_setup_rx(bnad, 0);
2516 if (err)
2517 goto cleanup_tx;
2518
2519 /* Port */
2520 pause_config.tx_pause = 0;
2521 pause_config.rx_pause = 0;
2522
078086f3 2523 mtu = ETH_HLEN + VLAN_HLEN + bnad->netdev->mtu + ETH_FCS_LEN;
8b230ed8
RM		 2524
2525 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2526 bna_enet_mtu_set(&bnad->bna.enet, mtu, NULL);
2527 bna_enet_pause_config(&bnad->bna.enet, &pause_config, NULL);
2528 bna_enet_enable(&bnad->bna.enet);
8b230ed8
RM		 2529 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2530
2531 /* Enable broadcast */
2532 bnad_enable_default_bcast(bnad);
2533
aad75b66
RM		 2534 /* Restore VLANs, if any */
2535 bnad_restore_vlans(bnad, 0);
2536
8b230ed8
RM		 2537 /* Set the UCAST address */
2538 spin_lock_irqsave(&bnad->bna_lock, flags);
2539 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2540 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2541
2542 /* Start the stats timer */
2543 bnad_stats_timer_start(bnad);
2544
2545 mutex_unlock(&bnad->conf_mutex);
2546
2547 return 0;
2548
2549cleanup_tx:
2550 bnad_cleanup_tx(bnad, 0);
2551
2552err_return:
2553 mutex_unlock(&bnad->conf_mutex);
2554 return err;
2555}
2556
2557static int
2558bnad_stop(struct net_device *netdev)
2559{
2560 struct bnad *bnad = netdev_priv(netdev);
2561 unsigned long flags;
2562
2563 mutex_lock(&bnad->conf_mutex);
2564
2565 /* Stop the stats timer */
2566 bnad_stats_timer_stop(bnad);
2567
078086f3 2568 init_completion(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 2569
2570 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2571 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP,
2572 bnad_cb_enet_disabled);
8b230ed8
RM		 2573 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2574
078086f3 2575 wait_for_completion(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 2576
2577 bnad_cleanup_tx(bnad, 0);
2578 bnad_cleanup_rx(bnad, 0);
2579
2580 /* Synchronize mailbox IRQ */
2581 bnad_mbox_irq_sync(bnad);
2582
2583 mutex_unlock(&bnad->conf_mutex);
2584
2585 return 0;
2586}
2587
2588/* TX */
2589/*
2590 * bnad_start_xmit : Netdev entry point for Transmit
2591 * Called under lock held by net_device
2592 */
2593static netdev_tx_t
2594bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2595{
2596 struct bnad *bnad = netdev_priv(netdev);
078086f3
RM		 2597 u32 txq_id = 0;
2598 struct bna_tcb *tcb = bnad->tx_info[0].tcb[txq_id];
8b230ed8 2599
0120b99c
RM		 2600 u16 txq_prod, vlan_tag = 0;
2601 u32 unmap_prod, wis, wis_used, wi_range;
2602 u32 vectors, vect_id, i, acked;
0120b99c 2603 int err;
271e8b79
RM		 2604 unsigned int len;
2605 u32 gso_size;
8b230ed8 2606
078086f3 2607 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
0120b99c 2608 dma_addr_t dma_addr;
8b230ed8 2609 struct bna_txq_entry *txqent;
078086f3 2610 u16 flags;
8b230ed8 2611
271e8b79
RM		 2612 if (unlikely(skb->len <= ETH_HLEN)) {
2613 dev_kfree_skb(skb);
2614 BNAD_UPDATE_CTR(bnad, tx_skb_too_short);
2615 return NETDEV_TX_OK;
2616 }
2617 if (unlikely(skb_headlen(skb) > BFI_TX_MAX_DATA_PER_VECTOR)) {
8b230ed8 2618 dev_kfree_skb(skb);
271e8b79
RM		 2619 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_too_long);
2620 return NETDEV_TX_OK;
2621 }
2622 if (unlikely(skb_headlen(skb) == 0)) {
2623 dev_kfree_skb(skb);
2624 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
8b230ed8
RM		 2625 return NETDEV_TX_OK;
2626 }
2627
2628 /*
2629 * Takes care of the Tx that is scheduled between clearing the flag
19dbff9f 2630 * and the netif_tx_stop_all_queues() call.
8b230ed8 2631 */
be7fa326 2632 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
8b230ed8 2633 dev_kfree_skb(skb);
271e8b79 2634 BNAD_UPDATE_CTR(bnad, tx_skb_stopping);
8b230ed8
RM		 2635 return NETDEV_TX_OK;
2636 }
2637
8b230ed8 2638 vectors = 1 + skb_shinfo(skb)->nr_frags;
271e8b79 2639 if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) {
8b230ed8 2640 dev_kfree_skb(skb);
271e8b79 2641 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors);
8b230ed8
RM		 2642 return NETDEV_TX_OK;
2643 }
2644 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2645 acked = 0;
078086f3
RM		 2646 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2647 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
8b230ed8
RM		 2648 if ((u16) (*tcb->hw_consumer_index) !=
2649 tcb->consumer_index &&
2650 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2651 acked = bnad_free_txbufs(bnad, tcb);
be7fa326
RM		 2652 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2653 bna_ib_ack(tcb->i_dbell, acked);
8b230ed8
RM		 2654 smp_mb__before_clear_bit();
2655 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2656 } else {
2657 netif_stop_queue(netdev);
2658 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2659 }
2660
2661 smp_mb();
2662 /*
2663 * Check again to deal with race condition between
2664 * netif_stop_queue here, and netif_wake_queue in
2665 * interrupt handler which is not inside netif tx lock.
2666 */
2667 if (likely
2668 (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2669 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2670 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2671 return NETDEV_TX_BUSY;
2672 } else {
2673 netif_wake_queue(netdev);
2674 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
2675 }
2676 }
2677
2678 unmap_prod = unmap_q->producer_index;
8b230ed8
RM		 2679 flags = 0;
2680
2681 txq_prod = tcb->producer_index;
2682 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, txqent, wi_range);
8b230ed8
RM		 2683 txqent->hdr.wi.reserved = 0;
2684 txqent->hdr.wi.num_vectors = vectors;
8b230ed8 2685
eab6d18d 2686 if (vlan_tx_tag_present(skb)) {
8b230ed8
RM		 2687 vlan_tag = (u16) vlan_tx_tag_get(skb);
2688 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2689 }
2690 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2691 vlan_tag =
2692 (tcb->priority & 0x7) << 13 | (vlan_tag & 0x1fff);
2693 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2694 }
2695
2696 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2697
2698 if (skb_is_gso(skb)) {
271e8b79
RM		 2699 gso_size = skb_shinfo(skb)->gso_size;
2700
2701 if (unlikely(gso_size > netdev->mtu)) {
2702 dev_kfree_skb(skb);
2703 BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long);
2704 return NETDEV_TX_OK;
2705 }
2706 if (unlikely((gso_size + skb_transport_offset(skb) +
2707 tcp_hdrlen(skb)) >= skb->len)) {
2708 txqent->hdr.wi.opcode =
2709 __constant_htons(BNA_TXQ_WI_SEND);
2710 txqent->hdr.wi.lso_mss = 0;
2711 BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short);
2712 } else {
2713 txqent->hdr.wi.opcode =
2714 __constant_htons(BNA_TXQ_WI_SEND_LSO);
2715 txqent->hdr.wi.lso_mss = htons(gso_size);
2716 }
2717
8b230ed8 2718 err = bnad_tso_prepare(bnad, skb);
271e8b79 2719 if (unlikely(err)) {
8b230ed8 2720 dev_kfree_skb(skb);
271e8b79 2721 BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare);
8b230ed8
RM		 2722 return NETDEV_TX_OK;
2723 }
8b230ed8
RM		 2724 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2725 txqent->hdr.wi.l4_hdr_size_n_offset =
2726 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2727 (tcp_hdrlen(skb) >> 2,
2728 skb_transport_offset(skb)));
271e8b79
RM		 2729 } else {
2730 txqent->hdr.wi.opcode = __constant_htons(BNA_TXQ_WI_SEND);
8b230ed8
RM		 2731 txqent->hdr.wi.lso_mss = 0;
2732
271e8b79
RM		 2733 if (unlikely(skb->len > (netdev->mtu + ETH_HLEN))) {
2734 dev_kfree_skb(skb);
2735 BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long);
2736 return NETDEV_TX_OK;
8b230ed8 2737 }
8b230ed8 2738
271e8b79
RM		 2739 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2740 u8 proto = 0;
8b230ed8 2741
271e8b79
RM		 2742 if (skb->protocol == __constant_htons(ETH_P_IP))
2743 proto = ip_hdr(skb)->protocol;
2744 else if (skb->protocol ==
2745 __constant_htons(ETH_P_IPV6)) {
2746 /* nexthdr may not be TCP immediately. */
2747 proto = ipv6_hdr(skb)->nexthdr;
2748 }
2749 if (proto == IPPROTO_TCP) {
2750 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2751 txqent->hdr.wi.l4_hdr_size_n_offset =
2752 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2753 (0, skb_transport_offset(skb)));
2754
2755 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2756
2757 if (unlikely(skb_headlen(skb) <
2758 skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2759 dev_kfree_skb(skb);
2760 BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr);
2761 return NETDEV_TX_OK;
2762 }
8b230ed8 2763
271e8b79
RM		 2764 } else if (proto == IPPROTO_UDP) {
2765 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2766 txqent->hdr.wi.l4_hdr_size_n_offset =
2767 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2768 (0, skb_transport_offset(skb)));
2769
2770 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2771 if (unlikely(skb_headlen(skb) <
2772 skb_transport_offset(skb) +
2773 sizeof(struct udphdr))) {
2774 dev_kfree_skb(skb);
2775 BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr);
2776 return NETDEV_TX_OK;
2777 }
2778 } else {
8b230ed8 2779 dev_kfree_skb(skb);
271e8b79 2780 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err);
8b230ed8
RM		 2781 return NETDEV_TX_OK;
2782 }
271e8b79
RM		 2783 } else {
2784 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
8b230ed8 2785 }
8b230ed8
RM		 2786 }
2787
2788 txqent->hdr.wi.flags = htons(flags);
2789
2790 txqent->hdr.wi.frame_length = htonl(skb->len);
2791
2792 unmap_q->unmap_array[unmap_prod].skb = skb;
271e8b79
RM		 2793 len = skb_headlen(skb);
2794 txqent->vector[0].length = htons(len);
5ea74318
IV		 2795 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
2796 skb_headlen(skb), DMA_TO_DEVICE);
2797 dma_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
8b230ed8
RM		 2798 dma_addr);
2799
271e8b79 2800 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr);
8b230ed8
RM		 2801 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2802
271e8b79
RM		 2803 vect_id = 0;
2804 wis_used = 1;
2805
8b230ed8 2806 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08
ED		 2807 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
2808 u16 size = skb_frag_size(frag);
8b230ed8 2809
271e8b79
RM		 2810 if (unlikely(size == 0)) {
2811 unmap_prod = unmap_q->producer_index;
2812
2813 unmap_prod = bnad_pci_unmap_skb(&bnad->pcidev->dev,
2814 unmap_q->unmap_array,
2815 unmap_prod, unmap_q->q_depth, skb,
2816 i);
2817 dev_kfree_skb(skb);
2818 BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero);
2819 return NETDEV_TX_OK;
2820 }
2821
2822 len += size;
2823
8b230ed8
RM		 2824 if (++vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
2825 vect_id = 0;
2826 if (--wi_range)
2827 txqent++;
2828 else {
2829 BNA_QE_INDX_ADD(txq_prod, wis_used,
2830 tcb->q_depth);
2831 wis_used = 0;
2832 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt,
2833 txqent, wi_range);
8b230ed8
RM		 2834 }
2835 wis_used++;
271e8b79
RM		 2836 txqent->hdr.wi_ext.opcode =
2837 __constant_htons(BNA_TXQ_WI_EXTENSION);
8b230ed8
RM		 2838 }
2839
2840 BUG_ON(!(size <= BFI_TX_MAX_DATA_PER_VECTOR));
2841 txqent->vector[vect_id].length = htons(size);
4d5b1a67
IC		 2842 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag,
2843 0, size, DMA_TO_DEVICE);
5ea74318 2844 dma_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
8b230ed8
RM		 2845 dma_addr);
2846 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2847 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2848 }
2849
271e8b79
RM		 2850 if (unlikely(len != skb->len)) {
2851 unmap_prod = unmap_q->producer_index;
2852
2853 unmap_prod = bnad_pci_unmap_skb(&bnad->pcidev->dev,
2854 unmap_q->unmap_array, unmap_prod,
2855 unmap_q->q_depth, skb,
2856 skb_shinfo(skb)->nr_frags);
2857 dev_kfree_skb(skb);
2858 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch);
2859 return NETDEV_TX_OK;
2860 }
2861
8b230ed8
RM		 2862 unmap_q->producer_index = unmap_prod;
2863 BNA_QE_INDX_ADD(txq_prod, wis_used, tcb->q_depth);
2864 tcb->producer_index = txq_prod;
2865
2866 smp_mb();
be7fa326
RM		 2867
2868 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2869 return NETDEV_TX_OK;
2870
8b230ed8 2871 bna_txq_prod_indx_doorbell(tcb);
271e8b79 2872 smp_mb();
8b230ed8
RM		 2873
2874 if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index)
2875 tasklet_schedule(&bnad->tx_free_tasklet);
2876
2877 return NETDEV_TX_OK;
2878}
2879
2880/*
2881 * Used spin_lock to synchronize reading of stats structures, which
2882 * is written by BNA under the same lock.
2883 */
250e061e
ED		 2884static struct rtnl_link_stats64 *
2885bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
8b230ed8
RM		 2886{
2887 struct bnad *bnad = netdev_priv(netdev);
2888 unsigned long flags;
2889
2890 spin_lock_irqsave(&bnad->bna_lock, flags);
2891
250e061e
ED		 2892 bnad_netdev_qstats_fill(bnad, stats);
2893 bnad_netdev_hwstats_fill(bnad, stats);
8b230ed8
RM		 2894
2895 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2896
250e061e 2897 return stats;
8b230ed8
RM		 2898}
2899
a2122d95 2900void
8b230ed8
RM		 2901bnad_set_rx_mode(struct net_device *netdev)
2902{
2903 struct bnad *bnad = netdev_priv(netdev);
2904 u32 new_mask, valid_mask;
2905 unsigned long flags;
2906
2907 spin_lock_irqsave(&bnad->bna_lock, flags);
2908
2909 new_mask = valid_mask = 0;
2910
2911 if (netdev->flags & IFF_PROMISC) {
2912 if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) {
2913 new_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2914 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2915 bnad->cfg_flags |= BNAD_CF_PROMISC;
2916 }
2917 } else {
2918 if (bnad->cfg_flags & BNAD_CF_PROMISC) {
2919 new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT;
2920 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2921 bnad->cfg_flags &= ~BNAD_CF_PROMISC;
2922 }
2923 }
2924
2925 if (netdev->flags & IFF_ALLMULTI) {
2926 if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) {
2927 new_mask |= BNA_RXMODE_ALLMULTI;
2928 valid_mask |= BNA_RXMODE_ALLMULTI;
2929 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
2930 }
2931 } else {
2932 if (bnad->cfg_flags & BNAD_CF_ALLMULTI) {
2933 new_mask &= ~BNA_RXMODE_ALLMULTI;
2934 valid_mask |= BNA_RXMODE_ALLMULTI;
2935 bnad->cfg_flags &= ~BNAD_CF_ALLMULTI;
2936 }
2937 }
2938
271e8b79
RM		 2939 if (bnad->rx_info[0].rx == NULL)
2940 goto unlock;
2941
8b230ed8
RM		 2942 bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL);
2943
2944 if (!netdev_mc_empty(netdev)) {
2945 u8 *mcaddr_list;
2946 int mc_count = netdev_mc_count(netdev);
2947
2948 /* Index 0 holds the broadcast address */
2949 mcaddr_list =
2950 kzalloc((mc_count + 1) * ETH_ALEN,
2951 GFP_ATOMIC);
2952 if (!mcaddr_list)
ca1cef3a 2953 goto unlock;
8b230ed8
RM		 2954
2955 memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN);
2956
2957 /* Copy rest of the MC addresses */
2958 bnad_netdev_mc_list_get(netdev, mcaddr_list);
2959
2960 bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
2961 mcaddr_list, NULL);
2962
2963 /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
2964 kfree(mcaddr_list);
2965 }
ca1cef3a 2966unlock:
8b230ed8
RM		 2967 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2968}
2969
2970/*
2971 * bna_lock is used to sync writes to netdev->addr
2972 * conf_lock cannot be used since this call may be made
2973 * in a non-blocking context.
2974 */
2975static int
2976bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
2977{
2978 int err;
2979 struct bnad *bnad = netdev_priv(netdev);
2980 struct sockaddr *sa = (struct sockaddr *)mac_addr;
2981 unsigned long flags;
2982
2983 spin_lock_irqsave(&bnad->bna_lock, flags);
2984
2985 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
2986
2987 if (!err)
2988 memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
2989
2990 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2991
2992 return err;
2993}
2994
2995static int
078086f3 2996bnad_mtu_set(struct bnad *bnad, int mtu)
8b230ed8 2997{
8b230ed8
RM		 2998 unsigned long flags;
2999
078086f3
RM		 3000 init_completion(&bnad->bnad_completions.mtu_comp);
3001
3002 spin_lock_irqsave(&bnad->bna_lock, flags);
3003 bna_enet_mtu_set(&bnad->bna.enet, mtu, bnad_cb_enet_mtu_set);
3004 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3005
3006 wait_for_completion(&bnad->bnad_completions.mtu_comp);
3007
3008 return bnad->bnad_completions.mtu_comp_status;
3009}
3010
3011static int
3012bnad_change_mtu(struct net_device *netdev, int new_mtu)
3013{
3014 int err, mtu = netdev->mtu;
8b230ed8
RM		 3015 struct bnad *bnad = netdev_priv(netdev);
3016
3017 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
3018 return -EINVAL;
3019
3020 mutex_lock(&bnad->conf_mutex);
3021
3022 netdev->mtu = new_mtu;
3023
078086f3
RM		 3024 mtu = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
3025 err = bnad_mtu_set(bnad, mtu);
3026 if (err)
3027 err = -EBUSY;
8b230ed8
RM		 3028
3029 mutex_unlock(&bnad->conf_mutex);
3030 return err;
3031}
3032
8e586137 3033static int
8b230ed8
RM		 3034bnad_vlan_rx_add_vid(struct net_device *netdev,
3035 unsigned short vid)
3036{
3037 struct bnad *bnad = netdev_priv(netdev);
3038 unsigned long flags;
3039
3040 if (!bnad->rx_info[0].rx)
8e586137 3041 return 0;
8b230ed8
RM		 3042
3043 mutex_lock(&bnad->conf_mutex);
3044
3045 spin_lock_irqsave(&bnad->bna_lock, flags);
3046 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
f859d7cb 3047 set_bit(vid, bnad->active_vlans);
8b230ed8
RM		 3048 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3049
3050 mutex_unlock(&bnad->conf_mutex);
8e586137
JP		 3051
3052 return 0;
8b230ed8
RM		 3053}
3054
8e586137 3055static int
8b230ed8
RM		 3056bnad_vlan_rx_kill_vid(struct net_device *netdev,
3057 unsigned short vid)
3058{
3059 struct bnad *bnad = netdev_priv(netdev);
3060 unsigned long flags;
3061
3062 if (!bnad->rx_info[0].rx)
8e586137 3063 return 0;
8b230ed8
RM		 3064
3065 mutex_lock(&bnad->conf_mutex);
3066
3067 spin_lock_irqsave(&bnad->bna_lock, flags);
f859d7cb 3068 clear_bit(vid, bnad->active_vlans);
8b230ed8
RM		 3069 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
3070 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3071
3072 mutex_unlock(&bnad->conf_mutex);
8e586137
JP		 3073
3074 return 0;
8b230ed8
RM		 3075}
3076
3077#ifdef CONFIG_NET_POLL_CONTROLLER
3078static void
3079bnad_netpoll(struct net_device *netdev)
3080{
3081 struct bnad *bnad = netdev_priv(netdev);
3082 struct bnad_rx_info *rx_info;
3083 struct bnad_rx_ctrl *rx_ctrl;
3084 u32 curr_mask;
3085 int i, j;
3086
3087 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
3088 bna_intx_disable(&bnad->bna, curr_mask);
3089 bnad_isr(bnad->pcidev->irq, netdev);
3090 bna_intx_enable(&bnad->bna, curr_mask);
3091 } else {
19dbff9f
RM		 3092 /*
3093 * Tx processing may happen in sending context, so no need
3094 * to explicitly process completions here
3095 */
3096
3097 /* Rx processing */
8b230ed8
RM		 3098 for (i = 0; i < bnad->num_rx; i++) {
3099 rx_info = &bnad->rx_info[i];
3100 if (!rx_info->rx)
3101 continue;
3102 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
3103 rx_ctrl = &rx_info->rx_ctrl[j];
271e8b79 3104 if (rx_ctrl->ccb)
8b230ed8
RM		 3105 bnad_netif_rx_schedule_poll(bnad,
3106 rx_ctrl->ccb);
8b230ed8
RM		 3107 }
3108 }
3109 }
3110}
3111#endif
3112
3113static const struct net_device_ops bnad_netdev_ops = {
3114 .ndo_open = bnad_open,
3115 .ndo_stop = bnad_stop,
3116 .ndo_start_xmit = bnad_start_xmit,
250e061e 3117 .ndo_get_stats64 = bnad_get_stats64,
8b230ed8 3118 .ndo_set_rx_mode = bnad_set_rx_mode,
8b230ed8
RM		 3119 .ndo_validate_addr = eth_validate_addr,
3120 .ndo_set_mac_address = bnad_set_mac_address,
3121 .ndo_change_mtu = bnad_change_mtu,
8b230ed8
RM		 3122 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
3123 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
3124#ifdef CONFIG_NET_POLL_CONTROLLER
3125 .ndo_poll_controller = bnad_netpoll
3126#endif
3127};
3128
3129static void
3130bnad_netdev_init(struct bnad *bnad, bool using_dac)
3131{
3132 struct net_device *netdev = bnad->netdev;
3133
e5ee20e7
MM		 3134 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3135 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3136 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_TX;
8b230ed8 3137
e5ee20e7
MM		 3138 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
3139 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3140 NETIF_F_TSO | NETIF_F_TSO6;
8b230ed8 3141
e5ee20e7
MM		 3142 netdev->features |= netdev->hw_features |
3143 NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
8b230ed8
RM		 3144
3145 if (using_dac)
3146 netdev->features |= NETIF_F_HIGHDMA;
3147
8b230ed8
RM		 3148 netdev->mem_start = bnad->mmio_start;
3149 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
3150
3151 netdev->netdev_ops = &bnad_netdev_ops;
3152 bnad_set_ethtool_ops(netdev);
3153}
3154
3155/*
3156 * 1. Initialize the bnad structure
3157 * 2. Setup netdev pointer in pci_dev
3158 * 3. Initialze Tx free tasklet
3159 * 4. Initialize no. of TxQ & CQs & MSIX vectors
01b54b14 3160 * 5. Initialize work queue.
8b230ed8
RM		 3161 */
3162static int
3163bnad_init(struct bnad *bnad,
3164 struct pci_dev *pdev, struct net_device *netdev)
3165{
3166 unsigned long flags;
3167
3168 SET_NETDEV_DEV(netdev, &pdev->dev);
3169 pci_set_drvdata(pdev, netdev);
3170
3171 bnad->netdev = netdev;
3172 bnad->pcidev = pdev;
3173 bnad->mmio_start = pci_resource_start(pdev, 0);
3174 bnad->mmio_len = pci_resource_len(pdev, 0);
3175 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
3176 if (!bnad->bar0) {
3177 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
3178 pci_set_drvdata(pdev, NULL);
3179 return -ENOMEM;
3180 }
3181 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
3182 (unsigned long long) bnad->mmio_len);
3183
3184 spin_lock_irqsave(&bnad->bna_lock, flags);
3185 if (!bnad_msix_disable)
3186 bnad->cfg_flags = BNAD_CF_MSIX;
3187
3188 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
3189
3190 bnad_q_num_init(bnad);
3191 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3192
3193 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
3194 (bnad->num_rx * bnad->num_rxp_per_rx) +
3195 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8
RM		 3196
3197 bnad->txq_depth = BNAD_TXQ_DEPTH;
3198 bnad->rxq_depth = BNAD_RXQ_DEPTH;
8b230ed8
RM		 3199
3200 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3201 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
3202
3203 tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet,
3204 (unsigned long)bnad);
3205
01b54b14
JH		 3206 sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id);
3207 bnad->work_q = create_singlethread_workqueue(bnad->wq_name);
3208
3209 if (!bnad->work_q)
3210 return -ENOMEM;
3211
8b230ed8
RM		 3212 return 0;
3213}
3214
3215/*
3216 * Must be called after bnad_pci_uninit()
3217 * so that iounmap() and pci_set_drvdata(NULL)
3218 * happens only after PCI uninitialization.
3219 */
3220static void
3221bnad_uninit(struct bnad *bnad)
3222{
01b54b14
JH		 3223 if (bnad->work_q) {
3224 flush_workqueue(bnad->work_q);
3225 destroy_workqueue(bnad->work_q);
3226 bnad->work_q = NULL;
3227 }
3228
8b230ed8
RM		 3229 if (bnad->bar0)
3230 iounmap(bnad->bar0);
3231 pci_set_drvdata(bnad->pcidev, NULL);
3232}
3233
3234/*
3235 * Initialize locks
078086f3 3236 a) Per ioceth mutes used for serializing configuration
8b230ed8
RM		 3237 changes from OS interface
3238 b) spin lock used to protect bna state machine
3239 */
3240static void
3241bnad_lock_init(struct bnad *bnad)
3242{
3243 spin_lock_init(&bnad->bna_lock);
3244 mutex_init(&bnad->conf_mutex);
72a9730b 3245 mutex_init(&bnad_list_mutex);
8b230ed8
RM		 3246}
3247
3248static void
3249bnad_lock_uninit(struct bnad *bnad)
3250{
3251 mutex_destroy(&bnad->conf_mutex);
72a9730b 3252 mutex_destroy(&bnad_list_mutex);
8b230ed8
RM		 3253}
3254
3255/* PCI Initialization */
3256static int
3257bnad_pci_init(struct bnad *bnad,
3258 struct pci_dev *pdev, bool *using_dac)
3259{
3260 int err;
3261
3262 err = pci_enable_device(pdev);
3263 if (err)
3264 return err;
3265 err = pci_request_regions(pdev, BNAD_NAME);
3266 if (err)
3267 goto disable_device;
5ea74318
IV		 3268 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
3269 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
3db1cd5c 3270 *using_dac = true;
8b230ed8 3271 } else {
5ea74318 3272 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
8b230ed8 3273 if (err) {
5ea74318
IV		 3274 err = dma_set_coherent_mask(&pdev->dev,
3275 DMA_BIT_MASK(32));
8b230ed8
RM		 3276 if (err)
3277 goto release_regions;
3278 }
3db1cd5c 3279 *using_dac = false;
8b230ed8
RM		 3280 }
3281 pci_set_master(pdev);
3282 return 0;
3283
3284release_regions:
3285 pci_release_regions(pdev);
3286disable_device:
3287 pci_disable_device(pdev);
3288
3289 return err;
3290}
3291
3292static void
3293bnad_pci_uninit(struct pci_dev *pdev)
3294{
3295 pci_release_regions(pdev);
3296 pci_disable_device(pdev);
3297}
3298
3299static int __devinit
3300bnad_pci_probe(struct pci_dev *pdev,
3301 const struct pci_device_id *pcidev_id)
3302{
3caa1e95 3303 bool using_dac;
0120b99c 3304 int err;
8b230ed8
RM		 3305 struct bnad *bnad;
3306 struct bna *bna;
3307 struct net_device *netdev;
3308 struct bfa_pcidev pcidev_info;
3309 unsigned long flags;
3310
3311 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3312 pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3313
3314 mutex_lock(&bnad_fwimg_mutex);
3315 if (!cna_get_firmware_buf(pdev)) {
3316 mutex_unlock(&bnad_fwimg_mutex);
3317 pr_warn("Failed to load Firmware Image!\n");
3318 return -ENODEV;
3319 }
3320 mutex_unlock(&bnad_fwimg_mutex);
3321
3322 /*
3323 * Allocates sizeof(struct net_device + struct bnad)
3324 * bnad = netdev->priv
3325 */
3326 netdev = alloc_etherdev(sizeof(struct bnad));
3327 if (!netdev) {
8b230ed8
RM		 3328 err = -ENOMEM;
3329 return err;
3330 }
3331 bnad = netdev_priv(netdev);
078086f3 3332 bnad_lock_init(bnad);
72a9730b 3333 bnad_add_to_list(bnad);
078086f3
RM		 3334
3335 mutex_lock(&bnad->conf_mutex);
8b230ed8
RM		 3336 /*
3337 * PCI initialization
0120b99c 3338 * Output : using_dac = 1 for 64 bit DMA
be7fa326 3339 * = 0 for 32 bit DMA
8b230ed8
RM		 3340 */
3341 err = bnad_pci_init(bnad, pdev, &using_dac);
3342 if (err)
44861f44 3343 goto unlock_mutex;
8b230ed8 3344
8b230ed8
RM		 3345 /*
3346 * Initialize bnad structure
3347 * Setup relation between pci_dev & netdev
3348 * Init Tx free tasklet
3349 */
3350 err = bnad_init(bnad, pdev, netdev);
3351 if (err)
3352 goto pci_uninit;
078086f3 3353
8b230ed8
RM		 3354 /* Initialize netdev structure, set up ethtool ops */
3355 bnad_netdev_init(bnad, using_dac);
3356
815f41e7
RM		 3357 /* Set link to down state */
3358 netif_carrier_off(netdev);
3359
7afc5dbd
KG		 3360 /* Setup the debugfs node for this bfad */
3361 if (bna_debugfs_enable)
3362 bnad_debugfs_init(bnad);
3363
8b230ed8 3364 /* Get resource requirement form bna */
078086f3 3365 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 3366 bna_res_req(&bnad->res_info[0]);
078086f3 3367 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 3368
3369 /* Allocate resources from bna */
078086f3 3370 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
8b230ed8 3371 if (err)
078086f3 3372 goto drv_uninit;
8b230ed8
RM		 3373
3374 bna = &bnad->bna;
3375
3376 /* Setup pcidev_info for bna_init() */
3377 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3378 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3379 pcidev_info.device_id = bnad->pcidev->device;
3380 pcidev_info.pci_bar_kva = bnad->bar0;
3381
8b230ed8
RM		 3382 spin_lock_irqsave(&bnad->bna_lock, flags);
3383 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
8b230ed8
RM		 3384 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3385
3386 bnad->stats.bna_stats = &bna->stats;
3387
078086f3
RM		 3388 bnad_enable_msix(bnad);
3389 err = bnad_mbox_irq_alloc(bnad);
3390 if (err)
3391 goto res_free;
3392
3393
8b230ed8 3394 /* Set up timers */
078086f3 3395 setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
8b230ed8 3396 ((unsigned long)bnad));
078086f3 3397 setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
8b230ed8 3398 ((unsigned long)bnad));
078086f3 3399 setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
1d32f769 3400 ((unsigned long)bnad));
078086f3 3401 setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
8b230ed8
RM		 3402 ((unsigned long)bnad));
3403
3404 /* Now start the timer before calling IOC */
078086f3 3405 mod_timer(&bnad->bna.ioceth.ioc.iocpf_timer,
8b230ed8
RM		 3406 jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
3407
3408 /*
3409 * Start the chip
078086f3
RM		 3410 * If the call back comes with error, we bail out.
3411 * This is a catastrophic error.
8b230ed8 3412 */
078086f3
RM		 3413 err = bnad_ioceth_enable(bnad);
3414 if (err) {
3415 pr_err("BNA: Initialization failed err=%d\n",
3416 err);
3417 goto probe_success;
3418 }
3419
3420 spin_lock_irqsave(&bnad->bna_lock, flags);
3421 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3422 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) {
3423 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1,
3424 bna_attr(bna)->num_rxp - 1);
3425 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3426 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1))
3427 err = -EIO;
3428 }
3caa1e95
RM		 3429 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3430 if (err)
3431 goto disable_ioceth;
3432
3433 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 3434 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]);
3435 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3436
3437 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
0caa9aae
RM		 3438 if (err) {
3439 err = -EIO;
078086f3 3440 goto disable_ioceth;
0caa9aae 3441 }
078086f3
RM		 3442
3443 spin_lock_irqsave(&bnad->bna_lock, flags);
3444 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]);
3445 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 3446
3447 /* Get the burnt-in mac */
3448 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 3449 bna_enet_perm_mac_get(&bna->enet, &bnad->perm_addr);
8b230ed8
RM		 3450 bnad_set_netdev_perm_addr(bnad);
3451 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3452
0caa9aae
RM		 3453 mutex_unlock(&bnad->conf_mutex);
3454
8b230ed8
RM		 3455 /* Finally, reguister with net_device layer */
3456 err = register_netdev(netdev);
3457 if (err) {
3458 pr_err("BNA : Registering with netdev failed\n");
078086f3 3459 goto probe_uninit;
8b230ed8 3460 }
078086f3 3461 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
8b230ed8 3462
0caa9aae
RM		 3463 return 0;
3464
078086f3
RM		 3465probe_success:
3466 mutex_unlock(&bnad->conf_mutex);
8b230ed8
RM		 3467 return 0;
3468
078086f3 3469probe_uninit:
3fc72370 3470 mutex_lock(&bnad->conf_mutex);
078086f3
RM		 3471 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3472disable_ioceth:
3473 bnad_ioceth_disable(bnad);
3474 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3475 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3476 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
8b230ed8
RM		 3477 spin_lock_irqsave(&bnad->bna_lock, flags);
3478 bna_uninit(bna);
3479 spin_unlock_irqrestore(&bnad->bna_lock, flags);
078086f3 3480 bnad_mbox_irq_free(bnad);
8b230ed8 3481 bnad_disable_msix(bnad);
078086f3
RM		 3482res_free:
3483 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3484drv_uninit:
7afc5dbd
KG		 3485 /* Remove the debugfs node for this bnad */
3486 kfree(bnad->regdata);
3487 bnad_debugfs_uninit(bnad);
078086f3 3488 bnad_uninit(bnad);
8b230ed8
RM		 3489pci_uninit:
3490 bnad_pci_uninit(pdev);
44861f44 3491unlock_mutex:
078086f3 3492 mutex_unlock(&bnad->conf_mutex);
72a9730b 3493 bnad_remove_from_list(bnad);
8b230ed8 3494 bnad_lock_uninit(bnad);
8b230ed8
RM		 3495 free_netdev(netdev);
3496 return err;
3497}
3498
3499static void __devexit
3500bnad_pci_remove(struct pci_dev *pdev)
3501{
3502 struct net_device *netdev = pci_get_drvdata(pdev);
3503 struct bnad *bnad;
3504 struct bna *bna;
3505 unsigned long flags;
3506
3507 if (!netdev)
3508 return;
3509
3510 pr_info("%s bnad_pci_remove\n", netdev->name);
3511 bnad = netdev_priv(netdev);
3512 bna = &bnad->bna;
3513
078086f3
RM		 3514 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags))
3515 unregister_netdev(netdev);
8b230ed8
RM		 3516
3517 mutex_lock(&bnad->conf_mutex);
078086f3
RM		 3518 bnad_ioceth_disable(bnad);
3519 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3520 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3521 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
8b230ed8
RM		 3522 spin_lock_irqsave(&bnad->bna_lock, flags);
3523 bna_uninit(bna);
3524 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 3525
078086f3
RM		 3526 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3527 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3528 bnad_mbox_irq_free(bnad);
8b230ed8
RM		 3529 bnad_disable_msix(bnad);
3530 bnad_pci_uninit(pdev);
078086f3 3531 mutex_unlock(&bnad->conf_mutex);
72a9730b 3532 bnad_remove_from_list(bnad);
8b230ed8 3533 bnad_lock_uninit(bnad);
7afc5dbd
KG		 3534 /* Remove the debugfs node for this bnad */
3535 kfree(bnad->regdata);
3536 bnad_debugfs_uninit(bnad);
8b230ed8
RM		 3537 bnad_uninit(bnad);
3538 free_netdev(netdev);
3539}
3540
0120b99c 3541static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table) = {
8b230ed8
RM		 3542 {
3543 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3544 PCI_DEVICE_ID_BROCADE_CT),
3545 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3546 .class_mask = 0xffff00
586b2816
RM		 3547 },
3548 {
3549 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3550 BFA_PCI_DEVICE_ID_CT2),
3551 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3552 .class_mask = 0xffff00
3553 },
3554 {0, },
8b230ed8
RM		 3555};
3556
3557MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3558
3559static struct pci_driver bnad_pci_driver = {
3560 .name = BNAD_NAME,
3561 .id_table = bnad_pci_id_table,
3562 .probe = bnad_pci_probe,
3563 .remove = __devexit_p(bnad_pci_remove),
3564};
3565
3566static int __init
3567bnad_module_init(void)
3568{
3569 int err;
3570
5aad0011
RM		 3571 pr_info("Brocade 10G Ethernet driver - version: %s\n",
3572 BNAD_VERSION);
8b230ed8 3573
8a891429 3574 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
8b230ed8
RM		 3575
3576 err = pci_register_driver(&bnad_pci_driver);
3577 if (err < 0) {
3578 pr_err("bna : PCI registration failed in module init "
3579 "(%d)\n", err);
3580 return err;
3581 }
3582
3583 return 0;
3584}
3585
3586static void __exit
3587bnad_module_exit(void)
3588{
3589 pci_unregister_driver(&bnad_pci_driver);
3590
3591 if (bfi_fw)
3592 release_firmware(bfi_fw);
3593}
3594
3595module_init(bnad_module_init);
3596module_exit(bnad_module_exit);
3597
3598MODULE_AUTHOR("Brocade");
3599MODULE_LICENSE("GPL");
3600MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3601MODULE_VERSION(BNAD_VERSION);
3602MODULE_FIRMWARE(CNA_FW_FILE_CT);
1bf9fd70 3603MODULE_FIRMWARE(CNA_FW_FILE_CT2);
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