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bna: PCI Probe Fix
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / brocade / bna / bnad.c
CommitLineData
8b230ed8
RM		 1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
f859d7cb 18#include <linux/bitops.h>
8b230ed8
RM		 19#include <linux/netdevice.h>
20#include <linux/skbuff.h>
21#include <linux/etherdevice.h>
22#include <linux/in.h>
23#include <linux/ethtool.h>
24#include <linux/if_vlan.h>
25#include <linux/if_ether.h>
26#include <linux/ip.h>
70c71606 27#include <linux/prefetch.h>
8b230ed8
RM		 28
29#include "bnad.h"
30#include "bna.h"
31#include "cna.h"
32
b7ee31c5 33static DEFINE_MUTEX(bnad_fwimg_mutex);
8b230ed8
RM		 34
35/*
36 * Module params
37 */
38static uint bnad_msix_disable;
39module_param(bnad_msix_disable, uint, 0444);
40MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
41
42static uint bnad_ioc_auto_recover = 1;
43module_param(bnad_ioc_auto_recover, uint, 0444);
44MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
45
46/*
47 * Global variables
48 */
49u32 bnad_rxqs_per_cq = 2;
50
b7ee31c5 51static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
8b230ed8
RM		 52
53/*
54 * Local MACROS
55 */
56#define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
57
58#define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
59
60#define BNAD_GET_MBOX_IRQ(_bnad) \
61 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
8811e267 62 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
8b230ed8
RM		 63 ((_bnad)->pcidev->irq))
64
65#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
66do { \
67 (_res_info)->res_type = BNA_RES_T_MEM; \
68 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
69 (_res_info)->res_u.mem_info.num = (_num); \
70 (_res_info)->res_u.mem_info.len = \
71 sizeof(struct bnad_unmap_q) + \
72 (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
73} while (0)
74
be7fa326
RM		 75#define BNAD_TXRX_SYNC_MDELAY 250 /* 250 msecs */
76
8b230ed8
RM		 77/*
78 * Reinitialize completions in CQ, once Rx is taken down
79 */
80static void
81bnad_cq_cmpl_init(struct bnad *bnad, struct bna_ccb *ccb)
82{
83 struct bna_cq_entry *cmpl, *next_cmpl;
84 unsigned int wi_range, wis = 0, ccb_prod = 0;
85 int i;
86
87 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, cmpl,
88 wi_range);
89
90 for (i = 0; i < ccb->q_depth; i++) {
91 wis++;
92 if (likely(--wi_range))
93 next_cmpl = cmpl + 1;
94 else {
95 BNA_QE_INDX_ADD(ccb_prod, wis, ccb->q_depth);
96 wis = 0;
97 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt,
98 next_cmpl, wi_range);
99 }
100 cmpl->valid = 0;
101 cmpl = next_cmpl;
102 }
103}
104
105/*
106 * Frees all pending Tx Bufs
107 * At this point no activity is expected on the Q,
108 * so DMA unmap & freeing is fine.
109 */
110static void
111bnad_free_all_txbufs(struct bnad *bnad,
112 struct bna_tcb *tcb)
113{
0120b99c 114 u32 unmap_cons;
8b230ed8
RM		 115 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
116 struct bnad_skb_unmap *unmap_array;
0120b99c 117 struct sk_buff *skb = NULL;
8b230ed8
RM		 118 int i;
119
120 unmap_array = unmap_q->unmap_array;
121
122 unmap_cons = 0;
123 while (unmap_cons < unmap_q->q_depth) {
124 skb = unmap_array[unmap_cons].skb;
125 if (!skb) {
126 unmap_cons++;
127 continue;
128 }
129 unmap_array[unmap_cons].skb = NULL;
130
5ea74318
IV		 131 dma_unmap_single(&bnad->pcidev->dev,
132 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8 133 dma_addr), skb_headlen(skb),
5ea74318 134 DMA_TO_DEVICE);
8b230ed8 135
5ea74318 136 dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
be7fa326
RM		 137 if (++unmap_cons >= unmap_q->q_depth)
138 break;
139
8b230ed8 140 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5ea74318
IV		 141 dma_unmap_page(&bnad->pcidev->dev,
142 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8
RM		 143 dma_addr),
144 skb_shinfo(skb)->frags[i].size,
5ea74318
IV		 145 DMA_TO_DEVICE);
146 dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
8b230ed8 147 0);
be7fa326
RM		 148 if (++unmap_cons >= unmap_q->q_depth)
149 break;
8b230ed8
RM		 150 }
151 dev_kfree_skb_any(skb);
152 }
153}
154
155/* Data Path Handlers */
156
157/*
158 * bnad_free_txbufs : Frees the Tx bufs on Tx completion
159 * Can be called in a) Interrupt context
160 * b) Sending context
161 * c) Tasklet context
162 */
163static u32
164bnad_free_txbufs(struct bnad *bnad,
165 struct bna_tcb *tcb)
166{
0120b99c
RM		 167 u32 sent_packets = 0, sent_bytes = 0;
168 u16 wis, unmap_cons, updated_hw_cons;
8b230ed8
RM		 169 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
170 struct bnad_skb_unmap *unmap_array;
0120b99c 171 struct sk_buff *skb;
8b230ed8
RM		 172 int i;
173
174 /*
175 * Just return if TX is stopped. This check is useful
176 * when bnad_free_txbufs() runs out of a tasklet scheduled
be7fa326 177 * before bnad_cb_tx_cleanup() cleared BNAD_TXQ_TX_STARTED bit
8b230ed8
RM		 178 * but this routine runs actually after the cleanup has been
179 * executed.
180 */
be7fa326 181 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
8b230ed8
RM		 182 return 0;
183
184 updated_hw_cons = *(tcb->hw_consumer_index);
185
186 wis = BNA_Q_INDEX_CHANGE(tcb->consumer_index,
187 updated_hw_cons, tcb->q_depth);
188
189 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
190
191 unmap_array = unmap_q->unmap_array;
192 unmap_cons = unmap_q->consumer_index;
193
194 prefetch(&unmap_array[unmap_cons + 1]);
195 while (wis) {
196 skb = unmap_array[unmap_cons].skb;
197
198 unmap_array[unmap_cons].skb = NULL;
199
200 sent_packets++;
201 sent_bytes += skb->len;
202 wis -= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags);
203
5ea74318
IV		 204 dma_unmap_single(&bnad->pcidev->dev,
205 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8 206 dma_addr), skb_headlen(skb),
5ea74318
IV		 207 DMA_TO_DEVICE);
208 dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
8b230ed8
RM		 209 BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
210
211 prefetch(&unmap_array[unmap_cons + 1]);
212 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
213 prefetch(&unmap_array[unmap_cons + 1]);
214
5ea74318
IV		 215 dma_unmap_page(&bnad->pcidev->dev,
216 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8
RM		 217 dma_addr),
218 skb_shinfo(skb)->frags[i].size,
5ea74318
IV		 219 DMA_TO_DEVICE);
220 dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
8b230ed8
RM		 221 0);
222 BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
223 }
224 dev_kfree_skb_any(skb);
225 }
226
227 /* Update consumer pointers. */
228 tcb->consumer_index = updated_hw_cons;
229 unmap_q->consumer_index = unmap_cons;
230
231 tcb->txq->tx_packets += sent_packets;
232 tcb->txq->tx_bytes += sent_bytes;
233
234 return sent_packets;
235}
236
237/* Tx Free Tasklet function */
238/* Frees for all the tcb's in all the Tx's */
239/*
240 * Scheduled from sending context, so that
241 * the fat Tx lock is not held for too long
242 * in the sending context.
243 */
244static void
245bnad_tx_free_tasklet(unsigned long bnad_ptr)
246{
247 struct bnad *bnad = (struct bnad *)bnad_ptr;
248 struct bna_tcb *tcb;
0120b99c 249 u32 acked = 0;
8b230ed8
RM		 250 int i, j;
251
252 for (i = 0; i < bnad->num_tx; i++) {
253 for (j = 0; j < bnad->num_txq_per_tx; j++) {
254 tcb = bnad->tx_info[i].tcb[j];
255 if (!tcb)
256 continue;
257 if (((u16) (*tcb->hw_consumer_index) !=
258 tcb->consumer_index) &&
259 (!test_and_set_bit(BNAD_TXQ_FREE_SENT,
260 &tcb->flags))) {
261 acked = bnad_free_txbufs(bnad, tcb);
be7fa326
RM		 262 if (likely(test_bit(BNAD_TXQ_TX_STARTED,
263 &tcb->flags)))
264 bna_ib_ack(tcb->i_dbell, acked);
8b230ed8
RM		 265 smp_mb__before_clear_bit();
266 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
267 }
f7c0fa4c
RM		 268 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED,
269 &tcb->flags)))
270 continue;
271 if (netif_queue_stopped(bnad->netdev)) {
272 if (acked && netif_carrier_ok(bnad->netdev) &&
273 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
274 BNAD_NETIF_WAKE_THRESHOLD) {
275 netif_wake_queue(bnad->netdev);
276 /* TODO */
277 /* Counters for individual TxQs? */
278 BNAD_UPDATE_CTR(bnad,
279 netif_queue_wakeup);
280 }
281 }
8b230ed8
RM		 282 }
283 }
284}
285
286static u32
287bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
288{
289 struct net_device *netdev = bnad->netdev;
be7fa326 290 u32 sent = 0;
8b230ed8
RM		 291
292 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
293 return 0;
294
295 sent = bnad_free_txbufs(bnad, tcb);
296 if (sent) {
297 if (netif_queue_stopped(netdev) &&
298 netif_carrier_ok(netdev) &&
299 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
300 BNAD_NETIF_WAKE_THRESHOLD) {
be7fa326
RM		 301 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
302 netif_wake_queue(netdev);
303 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
304 }
8b230ed8 305 }
be7fa326
RM		 306 }
307
308 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
8b230ed8 309 bna_ib_ack(tcb->i_dbell, sent);
8b230ed8
RM		 310
311 smp_mb__before_clear_bit();
312 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
313
314 return sent;
315}
316
317/* MSIX Tx Completion Handler */
318static irqreturn_t
319bnad_msix_tx(int irq, void *data)
320{
321 struct bna_tcb *tcb = (struct bna_tcb *)data;
322 struct bnad *bnad = tcb->bnad;
323
324 bnad_tx(bnad, tcb);
325
326 return IRQ_HANDLED;
327}
328
329static void
330bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb)
331{
332 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
333
334 rcb->producer_index = 0;
335 rcb->consumer_index = 0;
336
337 unmap_q->producer_index = 0;
338 unmap_q->consumer_index = 0;
339}
340
341static void
be7fa326 342bnad_free_all_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
8b230ed8
RM		 343{
344 struct bnad_unmap_q *unmap_q;
5ea74318 345 struct bnad_skb_unmap *unmap_array;
8b230ed8 346 struct sk_buff *skb;
be7fa326 347 int unmap_cons;
8b230ed8
RM		 348
349 unmap_q = rcb->unmap_q;
5ea74318 350 unmap_array = unmap_q->unmap_array;
be7fa326 351 for (unmap_cons = 0; unmap_cons < unmap_q->q_depth; unmap_cons++) {
5ea74318 352 skb = unmap_array[unmap_cons].skb;
be7fa326
RM		 353 if (!skb)
354 continue;
5ea74318
IV		 355 unmap_array[unmap_cons].skb = NULL;
356 dma_unmap_single(&bnad->pcidev->dev,
357 dma_unmap_addr(&unmap_array[unmap_cons],
358 dma_addr),
359 rcb->rxq->buffer_size,
360 DMA_FROM_DEVICE);
8b230ed8 361 dev_kfree_skb(skb);
8b230ed8 362 }
8b230ed8
RM		 363 bnad_reset_rcb(bnad, rcb);
364}
365
366static void
367bnad_alloc_n_post_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
368{
369 u16 to_alloc, alloced, unmap_prod, wi_range;
370 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
371 struct bnad_skb_unmap *unmap_array;
372 struct bna_rxq_entry *rxent;
373 struct sk_buff *skb;
374 dma_addr_t dma_addr;
375
376 alloced = 0;
377 to_alloc =
378 BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth);
379
380 unmap_array = unmap_q->unmap_array;
381 unmap_prod = unmap_q->producer_index;
382
383 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, wi_range);
384
385 while (to_alloc--) {
386 if (!wi_range) {
387 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent,
388 wi_range);
389 }
0a0e2344
ED		 390 skb = netdev_alloc_skb_ip_align(bnad->netdev,
391 rcb->rxq->buffer_size);
8b230ed8
RM		 392 if (unlikely(!skb)) {
393 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
394 goto finishing;
395 }
8b230ed8 396 unmap_array[unmap_prod].skb = skb;
5ea74318
IV		 397 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
398 rcb->rxq->buffer_size,
399 DMA_FROM_DEVICE);
400 dma_unmap_addr_set(&unmap_array[unmap_prod], dma_addr,
8b230ed8
RM		 401 dma_addr);
402 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
403 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
404
405 rxent++;
406 wi_range--;
407 alloced++;
408 }
409
410finishing:
411 if (likely(alloced)) {
412 unmap_q->producer_index = unmap_prod;
413 rcb->producer_index = unmap_prod;
414 smp_mb();
be7fa326
RM		 415 if (likely(test_bit(BNAD_RXQ_STARTED, &rcb->flags)))
416 bna_rxq_prod_indx_doorbell(rcb);
8b230ed8 417 }
8b230ed8
RM		 418}
419
420static inline void
421bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb)
422{
423 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
424
425 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
426 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
427 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
428 bnad_alloc_n_post_rxbufs(bnad, rcb);
429 smp_mb__before_clear_bit();
430 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
431 }
432}
433
434static u32
435bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget)
436{
437 struct bna_cq_entry *cmpl, *next_cmpl;
438 struct bna_rcb *rcb = NULL;
439 unsigned int wi_range, packets = 0, wis = 0;
440 struct bnad_unmap_q *unmap_q;
5ea74318 441 struct bnad_skb_unmap *unmap_array;
8b230ed8 442 struct sk_buff *skb;
5ea74318 443 u32 flags, unmap_cons;
8b230ed8 444 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
078086f3
RM		 445 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
446
447 set_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags);
8b230ed8 448
078086f3
RM		 449 if (!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)) {
450 clear_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags);
be7fa326 451 return 0;
078086f3 452 }
be7fa326 453
8b230ed8
RM		 454 prefetch(bnad->netdev);
455 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
456 wi_range);
457 BUG_ON(!(wi_range <= ccb->q_depth));
458 while (cmpl->valid && packets < budget) {
459 packets++;
460 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
461
078086f3 462 if (bna_is_small_rxq(cmpl->rxq_id))
8b230ed8 463 rcb = ccb->rcb[1];
078086f3
RM		 464 else
465 rcb = ccb->rcb[0];
8b230ed8
RM		 466
467 unmap_q = rcb->unmap_q;
5ea74318
IV		 468 unmap_array = unmap_q->unmap_array;
469 unmap_cons = unmap_q->consumer_index;
8b230ed8 470
5ea74318 471 skb = unmap_array[unmap_cons].skb;
8b230ed8 472 BUG_ON(!(skb));
5ea74318
IV		 473 unmap_array[unmap_cons].skb = NULL;
474 dma_unmap_single(&bnad->pcidev->dev,
475 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8 476 dma_addr),
5ea74318
IV		 477 rcb->rxq->buffer_size,
478 DMA_FROM_DEVICE);
8b230ed8
RM		 479 BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
480
481 /* Should be more efficient ? Performance ? */
482 BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
483
484 wis++;
485 if (likely(--wi_range))
486 next_cmpl = cmpl + 1;
487 else {
488 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
489 wis = 0;
490 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt,
491 next_cmpl, wi_range);
492 BUG_ON(!(wi_range <= ccb->q_depth));
493 }
494 prefetch(next_cmpl);
495
496 flags = ntohl(cmpl->flags);
497 if (unlikely
498 (flags &
499 (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR |
500 BNA_CQ_EF_TOO_LONG))) {
501 dev_kfree_skb_any(skb);
502 rcb->rxq->rx_packets_with_error++;
503 goto next;
504 }
505
506 skb_put(skb, ntohs(cmpl->length));
507 if (likely
e5ee20e7 508 ((bnad->netdev->features & NETIF_F_RXCSUM) &&
8b230ed8
RM		 509 (((flags & BNA_CQ_EF_IPV4) &&
510 (flags & BNA_CQ_EF_L3_CKSUM_OK)) ||
511 (flags & BNA_CQ_EF_IPV6)) &&
512 (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) &&
513 (flags & BNA_CQ_EF_L4_CKSUM_OK)))
514 skb->ip_summed = CHECKSUM_UNNECESSARY;
515 else
bc8acf2c 516 skb_checksum_none_assert(skb);
8b230ed8
RM		 517
518 rcb->rxq->rx_packets++;
519 rcb->rxq->rx_bytes += skb->len;
520 skb->protocol = eth_type_trans(skb, bnad->netdev);
521
f859d7cb
JP		 522 if (flags & BNA_CQ_EF_VLAN)
523 __vlan_hwaccel_put_tag(skb, ntohs(cmpl->vlan_tag));
524
078086f3 525 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
f859d7cb 526 napi_gro_receive(&rx_ctrl->napi, skb);
078086f3 527 else {
f859d7cb 528 netif_receive_skb(skb);
8b230ed8
RM		 529 }
530
531next:
532 cmpl->valid = 0;
533 cmpl = next_cmpl;
534 }
535
536 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
537
538 if (likely(ccb)) {
be7fa326
RM		 539 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
540 bna_ib_ack(ccb->i_dbell, packets);
8b230ed8
RM		 541 bnad_refill_rxq(bnad, ccb->rcb[0]);
542 if (ccb->rcb[1])
543 bnad_refill_rxq(bnad, ccb->rcb[1]);
be7fa326
RM		 544 } else {
545 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
546 bna_ib_ack(ccb->i_dbell, 0);
547 }
8b230ed8 548
078086f3
RM		 549 clear_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags);
550
8b230ed8
RM		 551 return packets;
552}
553
554static void
555bnad_disable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
556{
be7fa326
RM		 557 if (unlikely(!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
558 return;
559
8b230ed8
RM		 560 bna_ib_coalescing_timer_set(ccb->i_dbell, 0);
561 bna_ib_ack(ccb->i_dbell, 0);
562}
563
564static void
565bnad_enable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
566{
e2fa6f2e
RM		 567 unsigned long flags;
568
aad75b66
RM		 569 /* Because of polling context */
570 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 571 bnad_enable_rx_irq_unsafe(ccb);
e2fa6f2e 572 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 573}
574
575static void
576bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
577{
578 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
be7fa326
RM		 579 struct napi_struct *napi = &rx_ctrl->napi;
580
581 if (likely(napi_schedule_prep(napi))) {
8b230ed8 582 bnad_disable_rx_irq(bnad, ccb);
be7fa326 583 __napi_schedule(napi);
8b230ed8
RM		 584 }
585 BNAD_UPDATE_CTR(bnad, netif_rx_schedule);
586}
587
588/* MSIX Rx Path Handler */
589static irqreturn_t
590bnad_msix_rx(int irq, void *data)
591{
592 struct bna_ccb *ccb = (struct bna_ccb *)data;
593 struct bnad *bnad = ccb->bnad;
594
595 bnad_netif_rx_schedule_poll(bnad, ccb);
596
597 return IRQ_HANDLED;
598}
599
600/* Interrupt handlers */
601
602/* Mbox Interrupt Handlers */
603static irqreturn_t
604bnad_msix_mbox_handler(int irq, void *data)
605{
606 u32 intr_status;
e2fa6f2e 607 unsigned long flags;
be7fa326 608 struct bnad *bnad = (struct bnad *)data;
8b230ed8 609
be7fa326
RM		 610 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
611 return IRQ_HANDLED;
8b230ed8 612
8b230ed8
RM		 613 spin_lock_irqsave(&bnad->bna_lock, flags);
614
615 bna_intr_status_get(&bnad->bna, intr_status);
616
078086f3 617 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
8b230ed8
RM		 618 bna_mbox_handler(&bnad->bna, intr_status);
619
620 spin_unlock_irqrestore(&bnad->bna_lock, flags);
621
8b230ed8
RM		 622 return IRQ_HANDLED;
623}
624
625static irqreturn_t
626bnad_isr(int irq, void *data)
627{
628 int i, j;
629 u32 intr_status;
630 unsigned long flags;
be7fa326 631 struct bnad *bnad = (struct bnad *)data;
8b230ed8
RM		 632 struct bnad_rx_info *rx_info;
633 struct bnad_rx_ctrl *rx_ctrl;
078086f3 634 struct bna_tcb *tcb = NULL;
8b230ed8 635
e2fa6f2e
RM		 636 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
637 return IRQ_NONE;
8b230ed8
RM		 638
639 bna_intr_status_get(&bnad->bna, intr_status);
e2fa6f2e
RM		 640
641 if (unlikely(!intr_status))
8b230ed8 642 return IRQ_NONE;
e2fa6f2e
RM		 643
644 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 645
078086f3 646 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
8b230ed8 647 bna_mbox_handler(&bnad->bna, intr_status);
be7fa326 648
8b230ed8
RM		 649 spin_unlock_irqrestore(&bnad->bna_lock, flags);
650
be7fa326
RM		 651 if (!BNA_IS_INTX_DATA_INTR(intr_status))
652 return IRQ_HANDLED;
653
8b230ed8 654 /* Process data interrupts */
be7fa326
RM		 655 /* Tx processing */
656 for (i = 0; i < bnad->num_tx; i++) {
078086f3
RM		 657 for (j = 0; j < bnad->num_txq_per_tx; j++) {
658 tcb = bnad->tx_info[i].tcb[j];
659 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
660 bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
661 }
be7fa326
RM		 662 }
663 /* Rx processing */
8b230ed8
RM		 664 for (i = 0; i < bnad->num_rx; i++) {
665 rx_info = &bnad->rx_info[i];
666 if (!rx_info->rx)
667 continue;
668 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
669 rx_ctrl = &rx_info->rx_ctrl[j];
670 if (rx_ctrl->ccb)
671 bnad_netif_rx_schedule_poll(bnad,
672 rx_ctrl->ccb);
673 }
674 }
8b230ed8
RM		 675 return IRQ_HANDLED;
676}
677
678/*
679 * Called in interrupt / callback context
680 * with bna_lock held, so cfg_flags access is OK
681 */
682static void
683bnad_enable_mbox_irq(struct bnad *bnad)
684{
be7fa326 685 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
e2fa6f2e 686
8b230ed8
RM		 687 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
688}
689
690/*
691 * Called with bnad->bna_lock held b'cos of
692 * bnad->cfg_flags access.
693 */
b7ee31c5 694static void
8b230ed8
RM		 695bnad_disable_mbox_irq(struct bnad *bnad)
696{
be7fa326 697 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
8b230ed8 698
be7fa326
RM		 699 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
700}
8b230ed8 701
be7fa326
RM		 702static void
703bnad_set_netdev_perm_addr(struct bnad *bnad)
704{
705 struct net_device *netdev = bnad->netdev;
e2fa6f2e 706
be7fa326
RM		 707 memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
708 if (is_zero_ether_addr(netdev->dev_addr))
709 memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
8b230ed8
RM		 710}
711
712/* Control Path Handlers */
713
714/* Callbacks */
715void
078086f3 716bnad_cb_mbox_intr_enable(struct bnad *bnad)
8b230ed8
RM		 717{
718 bnad_enable_mbox_irq(bnad);
719}
720
721void
078086f3 722bnad_cb_mbox_intr_disable(struct bnad *bnad)
8b230ed8
RM		 723{
724 bnad_disable_mbox_irq(bnad);
725}
726
727void
078086f3
RM		 728bnad_cb_ioceth_ready(struct bnad *bnad)
729{
730 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
731 complete(&bnad->bnad_completions.ioc_comp);
732}
733
734void
735bnad_cb_ioceth_failed(struct bnad *bnad)
8b230ed8 736{
078086f3 737 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL;
8b230ed8 738 complete(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 739}
740
741void
078086f3 742bnad_cb_ioceth_disabled(struct bnad *bnad)
8b230ed8 743{
078086f3 744 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
8b230ed8 745 complete(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 746}
747
748static void
078086f3 749bnad_cb_enet_disabled(void *arg)
8b230ed8
RM		 750{
751 struct bnad *bnad = (struct bnad *)arg;
752
8b230ed8 753 netif_carrier_off(bnad->netdev);
078086f3 754 complete(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 755}
756
757void
078086f3 758bnad_cb_ethport_link_status(struct bnad *bnad,
8b230ed8
RM		 759 enum bna_link_status link_status)
760{
761 bool link_up = 0;
762
763 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
764
765 if (link_status == BNA_CEE_UP) {
078086f3
RM		 766 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
767 BNAD_UPDATE_CTR(bnad, cee_toggle);
8b230ed8 768 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
078086f3
RM		 769 } else {
770 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
771 BNAD_UPDATE_CTR(bnad, cee_toggle);
8b230ed8 772 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
078086f3 773 }
8b230ed8
RM		 774
775 if (link_up) {
776 if (!netif_carrier_ok(bnad->netdev)) {
078086f3
RM		 777 uint tx_id, tcb_id;
778 printk(KERN_WARNING "bna: %s link up\n",
8b230ed8
RM		 779 bnad->netdev->name);
780 netif_carrier_on(bnad->netdev);
781 BNAD_UPDATE_CTR(bnad, link_toggle);
078086f3
RM		 782 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
783 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx;
784 tcb_id++) {
785 struct bna_tcb *tcb =
786 bnad->tx_info[tx_id].tcb[tcb_id];
787 u32 txq_id;
788 if (!tcb)
789 continue;
790
791 txq_id = tcb->id;
792
793 if (test_bit(BNAD_TXQ_TX_STARTED,
794 &tcb->flags)) {
795 /*
796 * Force an immediate
797 * Transmit Schedule */
798 printk(KERN_INFO "bna: %s %d "
799 "TXQ_STARTED\n",
800 bnad->netdev->name,
801 txq_id);
802 netif_wake_subqueue(
803 bnad->netdev,
804 txq_id);
805 BNAD_UPDATE_CTR(bnad,
806 netif_queue_wakeup);
807 } else {
808 netif_stop_subqueue(
809 bnad->netdev,
810 txq_id);
811 BNAD_UPDATE_CTR(bnad,
812 netif_queue_stop);
813 }
814 }
8b230ed8
RM		 815 }
816 }
817 } else {
818 if (netif_carrier_ok(bnad->netdev)) {
078086f3 819 printk(KERN_WARNING "bna: %s link down\n",
8b230ed8
RM		 820 bnad->netdev->name);
821 netif_carrier_off(bnad->netdev);
822 BNAD_UPDATE_CTR(bnad, link_toggle);
823 }
824 }
825}
826
827static void
078086f3 828bnad_cb_tx_disabled(void *arg, struct bna_tx *tx)
8b230ed8
RM		 829{
830 struct bnad *bnad = (struct bnad *)arg;
831
832 complete(&bnad->bnad_completions.tx_comp);
833}
834
835static void
836bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
837{
838 struct bnad_tx_info *tx_info =
839 (struct bnad_tx_info *)tcb->txq->tx->priv;
840 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
841
842 tx_info->tcb[tcb->id] = tcb;
843 unmap_q->producer_index = 0;
844 unmap_q->consumer_index = 0;
845 unmap_q->q_depth = BNAD_TX_UNMAPQ_DEPTH;
846}
847
848static void
849bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
850{
851 struct bnad_tx_info *tx_info =
852 (struct bnad_tx_info *)tcb->txq->tx->priv;
be7fa326
RM		 853 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
854
855 while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
856 cpu_relax();
857
858 bnad_free_all_txbufs(bnad, tcb);
859
860 unmap_q->producer_index = 0;
861 unmap_q->consumer_index = 0;
862
863 smp_mb__before_clear_bit();
864 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
8b230ed8
RM		 865
866 tx_info->tcb[tcb->id] = NULL;
867}
868
869static void
870bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb)
871{
872 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
873
874 unmap_q->producer_index = 0;
875 unmap_q->consumer_index = 0;
876 unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH;
877}
878
be7fa326
RM		 879static void
880bnad_cb_rcb_destroy(struct bnad *bnad, struct bna_rcb *rcb)
881{
882 bnad_free_all_rxbufs(bnad, rcb);
883}
884
8b230ed8
RM		 885static void
886bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
887{
888 struct bnad_rx_info *rx_info =
889 (struct bnad_rx_info *)ccb->cq->rx->priv;
890
891 rx_info->rx_ctrl[ccb->id].ccb = ccb;
892 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
893}
894
895static void
896bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
897{
898 struct bnad_rx_info *rx_info =
899 (struct bnad_rx_info *)ccb->cq->rx->priv;
900
901 rx_info->rx_ctrl[ccb->id].ccb = NULL;
902}
903
904static void
078086f3 905bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
8b230ed8
RM		 906{
907 struct bnad_tx_info *tx_info =
078086f3
RM		 908 (struct bnad_tx_info *)tx->priv;
909 struct bna_tcb *tcb;
910 u32 txq_id;
911 int i;
8b230ed8 912
078086f3
RM		 913 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
914 tcb = tx_info->tcb[i];
915 if (!tcb)
916 continue;
917 txq_id = tcb->id;
918 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
919 netif_stop_subqueue(bnad->netdev, txq_id);
920 printk(KERN_INFO "bna: %s %d TXQ_STOPPED\n",
921 bnad->netdev->name, txq_id);
922 }
8b230ed8
RM		 923}
924
925static void
078086f3 926bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
8b230ed8 927{
078086f3
RM		 928 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
929 struct bna_tcb *tcb;
930 struct bnad_unmap_q *unmap_q;
931 u32 txq_id;
932 int i;
8b230ed8 933
078086f3
RM		 934 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
935 tcb = tx_info->tcb[i];
936 if (!tcb)
937 continue;
938 txq_id = tcb->id;
8b230ed8 939
078086f3 940 unmap_q = tcb->unmap_q;
8b230ed8 941
078086f3
RM		 942 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
943 continue;
8b230ed8 944
078086f3
RM		 945 while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
946 cpu_relax();
8b230ed8 947
078086f3 948 bnad_free_all_txbufs(bnad, tcb);
8b230ed8 949
078086f3
RM		 950 unmap_q->producer_index = 0;
951 unmap_q->consumer_index = 0;
952
953 smp_mb__before_clear_bit();
954 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
955
956 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
957
958 if (netif_carrier_ok(bnad->netdev)) {
959 printk(KERN_INFO "bna: %s %d TXQ_STARTED\n",
960 bnad->netdev->name, txq_id);
961 netif_wake_subqueue(bnad->netdev, txq_id);
962 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
963 }
964 }
be7fa326
RM		 965
966 /*
078086f3 967 * Workaround for first ioceth enable failure & we
be7fa326
RM		 968 * get a 0 MAC address. We try to get the MAC address
969 * again here.
970 */
971 if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
078086f3 972 bna_enet_perm_mac_get(&bnad->bna.enet, &bnad->perm_addr);
be7fa326
RM		 973 bnad_set_netdev_perm_addr(bnad);
974 }
be7fa326
RM		 975}
976
977static void
078086f3 978bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
be7fa326 979{
078086f3
RM		 980 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
981 struct bna_tcb *tcb;
982 int i;
983
984 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
985 tcb = tx_info->tcb[i];
986 if (!tcb)
987 continue;
988 }
989
990 mdelay(BNAD_TXRX_SYNC_MDELAY);
991 bna_tx_cleanup_complete(tx);
8b230ed8
RM		 992}
993
994static void
078086f3 995bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 996{
078086f3
RM		 997 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
998 struct bna_ccb *ccb;
999 struct bnad_rx_ctrl *rx_ctrl;
1000 int i;
1001
1002 mdelay(BNAD_TXRX_SYNC_MDELAY);
1003
772b5235 1004 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
078086f3
RM		 1005 rx_ctrl = &rx_info->rx_ctrl[i];
1006 ccb = rx_ctrl->ccb;
1007 if (!ccb)
1008 continue;
1009
1010 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
1011
1012 if (ccb->rcb[1])
1013 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
8b230ed8 1014
078086f3
RM		 1015 while (test_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags))
1016 cpu_relax();
1017 }
be7fa326 1018
078086f3 1019 bna_rx_cleanup_complete(rx);
8b230ed8
RM		 1020}
1021
1022static void
078086f3 1023bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1024{
078086f3
RM		 1025 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1026 struct bna_ccb *ccb;
1027 struct bna_rcb *rcb;
1028 struct bnad_rx_ctrl *rx_ctrl;
1029 struct bnad_unmap_q *unmap_q;
1030 int i;
1031 int j;
be7fa326 1032
772b5235 1033 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
078086f3
RM		 1034 rx_ctrl = &rx_info->rx_ctrl[i];
1035 ccb = rx_ctrl->ccb;
1036 if (!ccb)
1037 continue;
be7fa326 1038
078086f3 1039 bnad_cq_cmpl_init(bnad, ccb);
8b230ed8 1040
078086f3
RM		 1041 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
1042 rcb = ccb->rcb[j];
1043 if (!rcb)
1044 continue;
1045 bnad_free_all_rxbufs(bnad, rcb);
1046
1047 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
1048 unmap_q = rcb->unmap_q;
1049
1050 /* Now allocate & post buffers for this RCB */
1051 /* !!Allocation in callback context */
1052 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
1053 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
1054 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
1055 bnad_alloc_n_post_rxbufs(bnad, rcb);
1056 smp_mb__before_clear_bit();
1057 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
1058 }
1059 }
8b230ed8
RM		 1060 }
1061}
1062
1063static void
078086f3 1064bnad_cb_rx_disabled(void *arg, struct bna_rx *rx)
8b230ed8
RM		 1065{
1066 struct bnad *bnad = (struct bnad *)arg;
1067
1068 complete(&bnad->bnad_completions.rx_comp);
1069}
1070
1071static void
078086f3 1072bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1073{
078086f3 1074 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS;
8b230ed8
RM		 1075 complete(&bnad->bnad_completions.mcast_comp);
1076}
1077
1078void
1079bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
1080 struct bna_stats *stats)
1081{
1082 if (status == BNA_CB_SUCCESS)
1083 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
1084
1085 if (!netif_running(bnad->netdev) ||
1086 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1087 return;
1088
1089 mod_timer(&bnad->stats_timer,
1090 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1091}
1092
078086f3
RM		 1093static void
1094bnad_cb_enet_mtu_set(struct bnad *bnad)
1095{
1096 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS;
1097 complete(&bnad->bnad_completions.mtu_comp);
1098}
1099
8b230ed8
RM		 1100/* Resource allocation, free functions */
1101
1102static void
1103bnad_mem_free(struct bnad *bnad,
1104 struct bna_mem_info *mem_info)
1105{
1106 int i;
1107 dma_addr_t dma_pa;
1108
1109 if (mem_info->mdl == NULL)
1110 return;
1111
1112 for (i = 0; i < mem_info->num; i++) {
1113 if (mem_info->mdl[i].kva != NULL) {
1114 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1115 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1116 dma_pa);
5ea74318
IV		 1117 dma_free_coherent(&bnad->pcidev->dev,
1118 mem_info->mdl[i].len,
1119 mem_info->mdl[i].kva, dma_pa);
8b230ed8
RM		 1120 } else
1121 kfree(mem_info->mdl[i].kva);
1122 }
1123 }
1124 kfree(mem_info->mdl);
1125 mem_info->mdl = NULL;
1126}
1127
1128static int
1129bnad_mem_alloc(struct bnad *bnad,
1130 struct bna_mem_info *mem_info)
1131{
1132 int i;
1133 dma_addr_t dma_pa;
1134
1135 if ((mem_info->num == 0) || (mem_info->len == 0)) {
1136 mem_info->mdl = NULL;
1137 return 0;
1138 }
1139
1140 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1141 GFP_KERNEL);
1142 if (mem_info->mdl == NULL)
1143 return -ENOMEM;
1144
1145 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1146 for (i = 0; i < mem_info->num; i++) {
1147 mem_info->mdl[i].len = mem_info->len;
1148 mem_info->mdl[i].kva =
5ea74318
IV		 1149 dma_alloc_coherent(&bnad->pcidev->dev,
1150 mem_info->len, &dma_pa,
1151 GFP_KERNEL);
8b230ed8
RM		 1152
1153 if (mem_info->mdl[i].kva == NULL)
1154 goto err_return;
1155
1156 BNA_SET_DMA_ADDR(dma_pa,
1157 &(mem_info->mdl[i].dma));
1158 }
1159 } else {
1160 for (i = 0; i < mem_info->num; i++) {
1161 mem_info->mdl[i].len = mem_info->len;
1162 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1163 GFP_KERNEL);
1164 if (mem_info->mdl[i].kva == NULL)
1165 goto err_return;
1166 }
1167 }
1168
1169 return 0;
1170
1171err_return:
1172 bnad_mem_free(bnad, mem_info);
1173 return -ENOMEM;
1174}
1175
1176/* Free IRQ for Mailbox */
1177static void
078086f3 1178bnad_mbox_irq_free(struct bnad *bnad)
8b230ed8
RM		 1179{
1180 int irq;
1181 unsigned long flags;
1182
8b230ed8 1183 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 1184 bnad_disable_mbox_irq(bnad);
e2fa6f2e 1185 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1186
1187 irq = BNAD_GET_MBOX_IRQ(bnad);
be7fa326 1188 free_irq(irq, bnad);
8b230ed8
RM		 1189}
1190
1191/*
1192 * Allocates IRQ for Mailbox, but keep it disabled
1193 * This will be enabled once we get the mbox enable callback
1194 * from bna
1195 */
1196static int
078086f3 1197bnad_mbox_irq_alloc(struct bnad *bnad)
8b230ed8 1198{
0120b99c
RM		 1199 int err = 0;
1200 unsigned long irq_flags, flags;
8b230ed8 1201 u32 irq;
0120b99c 1202 irq_handler_t irq_handler;
8b230ed8 1203
8b230ed8
RM		 1204 spin_lock_irqsave(&bnad->bna_lock, flags);
1205 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1206 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
8811e267 1207 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
8279171a 1208 irq_flags = 0;
8b230ed8
RM		 1209 } else {
1210 irq_handler = (irq_handler_t)bnad_isr;
1211 irq = bnad->pcidev->irq;
5f77898d 1212 irq_flags = IRQF_SHARED;
8b230ed8 1213 }
8811e267 1214
8b230ed8 1215 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1216 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1217
e2fa6f2e
RM		 1218 /*
1219 * Set the Mbox IRQ disable flag, so that the IRQ handler
1220 * called from request_irq() for SHARED IRQs do not execute
1221 */
1222 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1223
be7fa326
RM		 1224 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1225
8279171a 1226 err = request_irq(irq, irq_handler, irq_flags,
be7fa326 1227 bnad->mbox_irq_name, bnad);
e2fa6f2e 1228
be7fa326 1229 return err;
8b230ed8
RM		 1230}
1231
1232static void
1233bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1234{
1235 kfree(intr_info->idl);
1236 intr_info->idl = NULL;
1237}
1238
1239/* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1240static int
1241bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
078086f3 1242 u32 txrx_id, struct bna_intr_info *intr_info)
8b230ed8
RM		 1243{
1244 int i, vector_start = 0;
1245 u32 cfg_flags;
1246 unsigned long flags;
1247
1248 spin_lock_irqsave(&bnad->bna_lock, flags);
1249 cfg_flags = bnad->cfg_flags;
1250 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1251
1252 if (cfg_flags & BNAD_CF_MSIX) {
1253 intr_info->intr_type = BNA_INTR_T_MSIX;
1254 intr_info->idl = kcalloc(intr_info->num,
1255 sizeof(struct bna_intr_descr),
1256 GFP_KERNEL);
1257 if (!intr_info->idl)
1258 return -ENOMEM;
1259
1260 switch (src) {
1261 case BNAD_INTR_TX:
8811e267 1262 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id;
8b230ed8
RM		 1263 break;
1264
1265 case BNAD_INTR_RX:
8811e267
RM		 1266 vector_start = BNAD_MAILBOX_MSIX_VECTORS +
1267 (bnad->num_tx * bnad->num_txq_per_tx) +
8b230ed8
RM		 1268 txrx_id;
1269 break;
1270
1271 default:
1272 BUG();
1273 }
1274
1275 for (i = 0; i < intr_info->num; i++)
1276 intr_info->idl[i].vector = vector_start + i;
1277 } else {
1278 intr_info->intr_type = BNA_INTR_T_INTX;
1279 intr_info->num = 1;
1280 intr_info->idl = kcalloc(intr_info->num,
1281 sizeof(struct bna_intr_descr),
1282 GFP_KERNEL);
1283 if (!intr_info->idl)
1284 return -ENOMEM;
1285
1286 switch (src) {
1287 case BNAD_INTR_TX:
8811e267 1288 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK;
8b230ed8
RM		 1289 break;
1290
1291 case BNAD_INTR_RX:
8811e267 1292 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK;
8b230ed8
RM		 1293 break;
1294 }
1295 }
1296 return 0;
1297}
1298
1299/**
1300 * NOTE: Should be called for MSIX only
1301 * Unregisters Tx MSIX vector(s) from the kernel
1302 */
1303static void
1304bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1305 int num_txqs)
1306{
1307 int i;
1308 int vector_num;
1309
1310 for (i = 0; i < num_txqs; i++) {
1311 if (tx_info->tcb[i] == NULL)
1312 continue;
1313
1314 vector_num = tx_info->tcb[i]->intr_vector;
1315 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1316 }
1317}
1318
1319/**
1320 * NOTE: Should be called for MSIX only
1321 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1322 */
1323static int
1324bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
078086f3 1325 u32 tx_id, int num_txqs)
8b230ed8
RM		 1326{
1327 int i;
1328 int err;
1329 int vector_num;
1330
1331 for (i = 0; i < num_txqs; i++) {
1332 vector_num = tx_info->tcb[i]->intr_vector;
1333 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1334 tx_id + tx_info->tcb[i]->id);
1335 err = request_irq(bnad->msix_table[vector_num].vector,
1336 (irq_handler_t)bnad_msix_tx, 0,
1337 tx_info->tcb[i]->name,
1338 tx_info->tcb[i]);
1339 if (err)
1340 goto err_return;
1341 }
1342
1343 return 0;
1344
1345err_return:
1346 if (i > 0)
1347 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1348 return -1;
1349}
1350
1351/**
1352 * NOTE: Should be called for MSIX only
1353 * Unregisters Rx MSIX vector(s) from the kernel
1354 */
1355static void
1356bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1357 int num_rxps)
1358{
1359 int i;
1360 int vector_num;
1361
1362 for (i = 0; i < num_rxps; i++) {
1363 if (rx_info->rx_ctrl[i].ccb == NULL)
1364 continue;
1365
1366 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1367 free_irq(bnad->msix_table[vector_num].vector,
1368 rx_info->rx_ctrl[i].ccb);
1369 }
1370}
1371
1372/**
1373 * NOTE: Should be called for MSIX only
1374 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1375 */
1376static int
1377bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
078086f3 1378 u32 rx_id, int num_rxps)
8b230ed8
RM		 1379{
1380 int i;
1381 int err;
1382 int vector_num;
1383
1384 for (i = 0; i < num_rxps; i++) {
1385 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1386 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1387 bnad->netdev->name,
1388 rx_id + rx_info->rx_ctrl[i].ccb->id);
1389 err = request_irq(bnad->msix_table[vector_num].vector,
1390 (irq_handler_t)bnad_msix_rx, 0,
1391 rx_info->rx_ctrl[i].ccb->name,
1392 rx_info->rx_ctrl[i].ccb);
1393 if (err)
1394 goto err_return;
1395 }
1396
1397 return 0;
1398
1399err_return:
1400 if (i > 0)
1401 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1402 return -1;
1403}
1404
1405/* Free Tx object Resources */
1406static void
1407bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1408{
1409 int i;
1410
1411 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1412 if (res_info[i].res_type == BNA_RES_T_MEM)
1413 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1414 else if (res_info[i].res_type == BNA_RES_T_INTR)
1415 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1416 }
1417}
1418
1419/* Allocates memory and interrupt resources for Tx object */
1420static int
1421bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
078086f3 1422 u32 tx_id)
8b230ed8
RM		 1423{
1424 int i, err = 0;
1425
1426 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1427 if (res_info[i].res_type == BNA_RES_T_MEM)
1428 err = bnad_mem_alloc(bnad,
1429 &res_info[i].res_u.mem_info);
1430 else if (res_info[i].res_type == BNA_RES_T_INTR)
1431 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1432 &res_info[i].res_u.intr_info);
1433 if (err)
1434 goto err_return;
1435 }
1436 return 0;
1437
1438err_return:
1439 bnad_tx_res_free(bnad, res_info);
1440 return err;
1441}
1442
1443/* Free Rx object Resources */
1444static void
1445bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1446{
1447 int i;
1448
1449 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1450 if (res_info[i].res_type == BNA_RES_T_MEM)
1451 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1452 else if (res_info[i].res_type == BNA_RES_T_INTR)
1453 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1454 }
1455}
1456
1457/* Allocates memory and interrupt resources for Rx object */
1458static int
1459bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1460 uint rx_id)
1461{
1462 int i, err = 0;
1463
1464 /* All memory needs to be allocated before setup_ccbs */
1465 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1466 if (res_info[i].res_type == BNA_RES_T_MEM)
1467 err = bnad_mem_alloc(bnad,
1468 &res_info[i].res_u.mem_info);
1469 else if (res_info[i].res_type == BNA_RES_T_INTR)
1470 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1471 &res_info[i].res_u.intr_info);
1472 if (err)
1473 goto err_return;
1474 }
1475 return 0;
1476
1477err_return:
1478 bnad_rx_res_free(bnad, res_info);
1479 return err;
1480}
1481
1482/* Timer callbacks */
1483/* a) IOC timer */
1484static void
1485bnad_ioc_timeout(unsigned long data)
1486{
1487 struct bnad *bnad = (struct bnad *)data;
1488 unsigned long flags;
1489
1490 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1491 bfa_nw_ioc_timeout((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1492 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1493}
1494
1495static void
1496bnad_ioc_hb_check(unsigned long data)
1497{
1498 struct bnad *bnad = (struct bnad *)data;
1499 unsigned long flags;
1500
1501 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1502 bfa_nw_ioc_hb_check((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1503 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1504}
1505
1506static void
1d32f769 1507bnad_iocpf_timeout(unsigned long data)
8b230ed8
RM		 1508{
1509 struct bnad *bnad = (struct bnad *)data;
1510 unsigned long flags;
1511
1512 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1513 bfa_nw_iocpf_timeout((void *) &bnad->bna.ioceth.ioc);
1d32f769
RM		 1514 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1515}
1516
1517static void
1518bnad_iocpf_sem_timeout(unsigned long data)
1519{
1520 struct bnad *bnad = (struct bnad *)data;
1521 unsigned long flags;
1522
1523 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1524 bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1525 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1526}
1527
1528/*
1529 * All timer routines use bnad->bna_lock to protect against
1530 * the following race, which may occur in case of no locking:
0120b99c 1531 * Time CPU m CPU n
8b230ed8
RM		 1532 * 0 1 = test_bit
1533 * 1 clear_bit
1534 * 2 del_timer_sync
1535 * 3 mod_timer
1536 */
1537
1538/* b) Dynamic Interrupt Moderation Timer */
1539static void
1540bnad_dim_timeout(unsigned long data)
1541{
1542 struct bnad *bnad = (struct bnad *)data;
1543 struct bnad_rx_info *rx_info;
1544 struct bnad_rx_ctrl *rx_ctrl;
1545 int i, j;
1546 unsigned long flags;
1547
1548 if (!netif_carrier_ok(bnad->netdev))
1549 return;
1550
1551 spin_lock_irqsave(&bnad->bna_lock, flags);
1552 for (i = 0; i < bnad->num_rx; i++) {
1553 rx_info = &bnad->rx_info[i];
1554 if (!rx_info->rx)
1555 continue;
1556 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1557 rx_ctrl = &rx_info->rx_ctrl[j];
1558 if (!rx_ctrl->ccb)
1559 continue;
1560 bna_rx_dim_update(rx_ctrl->ccb);
1561 }
1562 }
1563
1564 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1565 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1566 mod_timer(&bnad->dim_timer,
1567 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1568 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1569}
1570
1571/* c) Statistics Timer */
1572static void
1573bnad_stats_timeout(unsigned long data)
1574{
1575 struct bnad *bnad = (struct bnad *)data;
1576 unsigned long flags;
1577
1578 if (!netif_running(bnad->netdev) ||
1579 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1580 return;
1581
1582 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1583 bna_hw_stats_get(&bnad->bna);
8b230ed8
RM		 1584 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1585}
1586
1587/*
1588 * Set up timer for DIM
1589 * Called with bnad->bna_lock held
1590 */
1591void
1592bnad_dim_timer_start(struct bnad *bnad)
1593{
1594 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1595 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1596 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1597 (unsigned long)bnad);
1598 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1599 mod_timer(&bnad->dim_timer,
1600 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1601 }
1602}
1603
1604/*
1605 * Set up timer for statistics
1606 * Called with mutex_lock(&bnad->conf_mutex) held
1607 */
1608static void
1609bnad_stats_timer_start(struct bnad *bnad)
1610{
1611 unsigned long flags;
1612
1613 spin_lock_irqsave(&bnad->bna_lock, flags);
1614 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1615 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1616 (unsigned long)bnad);
1617 mod_timer(&bnad->stats_timer,
1618 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1619 }
1620 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1621}
1622
1623/*
1624 * Stops the stats timer
1625 * Called with mutex_lock(&bnad->conf_mutex) held
1626 */
1627static void
1628bnad_stats_timer_stop(struct bnad *bnad)
1629{
1630 int to_del = 0;
1631 unsigned long flags;
1632
1633 spin_lock_irqsave(&bnad->bna_lock, flags);
1634 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1635 to_del = 1;
1636 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1637 if (to_del)
1638 del_timer_sync(&bnad->stats_timer);
1639}
1640
1641/* Utilities */
1642
1643static void
1644bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1645{
1646 int i = 1; /* Index 0 has broadcast address */
1647 struct netdev_hw_addr *mc_addr;
1648
1649 netdev_for_each_mc_addr(mc_addr, netdev) {
1650 memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
1651 ETH_ALEN);
1652 i++;
1653 }
1654}
1655
1656static int
1657bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1658{
1659 struct bnad_rx_ctrl *rx_ctrl =
1660 container_of(napi, struct bnad_rx_ctrl, napi);
1661 struct bna_ccb *ccb;
1662 struct bnad *bnad;
1663 int rcvd = 0;
1664
1665 ccb = rx_ctrl->ccb;
1666
1667 bnad = ccb->bnad;
1668
1669 if (!netif_carrier_ok(bnad->netdev))
1670 goto poll_exit;
1671
1672 rcvd = bnad_poll_cq(bnad, ccb, budget);
1673 if (rcvd == budget)
1674 return rcvd;
1675
1676poll_exit:
1677 napi_complete((napi));
1678
1679 BNAD_UPDATE_CTR(bnad, netif_rx_complete);
1680
1681 bnad_enable_rx_irq(bnad, ccb);
1682 return rcvd;
1683}
1684
8b230ed8
RM		 1685static void
1686bnad_napi_enable(struct bnad *bnad, u32 rx_id)
1687{
8b230ed8
RM		 1688 struct bnad_rx_ctrl *rx_ctrl;
1689 int i;
8b230ed8
RM		 1690
1691 /* Initialize & enable NAPI */
1692 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1693 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
be7fa326 1694
8b230ed8 1695 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
be7fa326
RM		 1696 bnad_napi_poll_rx, 64);
1697
8b230ed8
RM		 1698 napi_enable(&rx_ctrl->napi);
1699 }
1700}
1701
1702static void
1703bnad_napi_disable(struct bnad *bnad, u32 rx_id)
1704{
1705 int i;
1706
1707 /* First disable and then clean up */
1708 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1709 napi_disable(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1710 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1711 }
1712}
1713
1714/* Should be held with conf_lock held */
1715void
078086f3 1716bnad_cleanup_tx(struct bnad *bnad, u32 tx_id)
8b230ed8
RM		 1717{
1718 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1719 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1720 unsigned long flags;
1721
1722 if (!tx_info->tx)
1723 return;
1724
1725 init_completion(&bnad->bnad_completions.tx_comp);
1726 spin_lock_irqsave(&bnad->bna_lock, flags);
1727 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1728 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1729 wait_for_completion(&bnad->bnad_completions.tx_comp);
1730
1731 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1732 bnad_tx_msix_unregister(bnad, tx_info,
1733 bnad->num_txq_per_tx);
1734
1735 spin_lock_irqsave(&bnad->bna_lock, flags);
1736 bna_tx_destroy(tx_info->tx);
1737 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1738
1739 tx_info->tx = NULL;
078086f3 1740 tx_info->tx_id = 0;
8b230ed8
RM		 1741
1742 if (0 == tx_id)
1743 tasklet_kill(&bnad->tx_free_tasklet);
1744
1745 bnad_tx_res_free(bnad, res_info);
1746}
1747
1748/* Should be held with conf_lock held */
1749int
078086f3 1750bnad_setup_tx(struct bnad *bnad, u32 tx_id)
8b230ed8
RM		 1751{
1752 int err;
1753 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1754 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1755 struct bna_intr_info *intr_info =
1756 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1757 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
1758 struct bna_tx_event_cbfn tx_cbfn;
1759 struct bna_tx *tx;
1760 unsigned long flags;
1761
078086f3
RM		 1762 tx_info->tx_id = tx_id;
1763
8b230ed8
RM		 1764 /* Initialize the Tx object configuration */
1765 tx_config->num_txq = bnad->num_txq_per_tx;
1766 tx_config->txq_depth = bnad->txq_depth;
1767 tx_config->tx_type = BNA_TX_T_REGULAR;
078086f3 1768 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo;
8b230ed8
RM		 1769
1770 /* Initialize the tx event handlers */
1771 tx_cbfn.tcb_setup_cbfn = bnad_cb_tcb_setup;
1772 tx_cbfn.tcb_destroy_cbfn = bnad_cb_tcb_destroy;
1773 tx_cbfn.tx_stall_cbfn = bnad_cb_tx_stall;
1774 tx_cbfn.tx_resume_cbfn = bnad_cb_tx_resume;
1775 tx_cbfn.tx_cleanup_cbfn = bnad_cb_tx_cleanup;
1776
1777 /* Get BNA's resource requirement for one tx object */
1778 spin_lock_irqsave(&bnad->bna_lock, flags);
1779 bna_tx_res_req(bnad->num_txq_per_tx,
1780 bnad->txq_depth, res_info);
1781 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1782
1783 /* Fill Unmap Q memory requirements */
1784 BNAD_FILL_UNMAPQ_MEM_REQ(
1785 &res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1786 bnad->num_txq_per_tx,
1787 BNAD_TX_UNMAPQ_DEPTH);
1788
1789 /* Allocate resources */
1790 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1791 if (err)
1792 return err;
1793
1794 /* Ask BNA to create one Tx object, supplying required resources */
1795 spin_lock_irqsave(&bnad->bna_lock, flags);
1796 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
1797 tx_info);
1798 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1799 if (!tx)
1800 goto err_return;
1801 tx_info->tx = tx;
1802
1803 /* Register ISR for the Tx object */
1804 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1805 err = bnad_tx_msix_register(bnad, tx_info,
1806 tx_id, bnad->num_txq_per_tx);
1807 if (err)
1808 goto err_return;
1809 }
1810
1811 spin_lock_irqsave(&bnad->bna_lock, flags);
1812 bna_tx_enable(tx);
1813 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1814
1815 return 0;
1816
1817err_return:
1818 bnad_tx_res_free(bnad, res_info);
1819 return err;
1820}
1821
1822/* Setup the rx config for bna_rx_create */
1823/* bnad decides the configuration */
1824static void
1825bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
1826{
1827 rx_config->rx_type = BNA_RX_T_REGULAR;
1828 rx_config->num_paths = bnad->num_rxp_per_rx;
078086f3 1829 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo;
8b230ed8
RM		 1830
1831 if (bnad->num_rxp_per_rx > 1) {
1832 rx_config->rss_status = BNA_STATUS_T_ENABLED;
1833 rx_config->rss_config.hash_type =
078086f3
RM		 1834 (BFI_ENET_RSS_IPV6 |
1835 BFI_ENET_RSS_IPV6_TCP |
1836 BFI_ENET_RSS_IPV4 |
1837 BFI_ENET_RSS_IPV4_TCP);
8b230ed8
RM		 1838 rx_config->rss_config.hash_mask =
1839 bnad->num_rxp_per_rx - 1;
1840 get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
1841 sizeof(rx_config->rss_config.toeplitz_hash_key));
1842 } else {
1843 rx_config->rss_status = BNA_STATUS_T_DISABLED;
1844 memset(&rx_config->rss_config, 0,
1845 sizeof(rx_config->rss_config));
1846 }
1847 rx_config->rxp_type = BNA_RXP_SLR;
1848 rx_config->q_depth = bnad->rxq_depth;
1849
1850 rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE;
1851
1852 rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED;
1853}
1854
1855/* Called with mutex_lock(&bnad->conf_mutex) held */
1856void
078086f3 1857bnad_cleanup_rx(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 1858{
1859 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1860 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1861 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1862 unsigned long flags;
1863 int dim_timer_del = 0;
1864
1865 if (!rx_info->rx)
1866 return;
1867
1868 if (0 == rx_id) {
1869 spin_lock_irqsave(&bnad->bna_lock, flags);
1870 dim_timer_del = bnad_dim_timer_running(bnad);
1871 if (dim_timer_del)
1872 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1873 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1874 if (dim_timer_del)
1875 del_timer_sync(&bnad->dim_timer);
1876 }
1877
1878 bnad_napi_disable(bnad, rx_id);
1879
1880 init_completion(&bnad->bnad_completions.rx_comp);
1881 spin_lock_irqsave(&bnad->bna_lock, flags);
1882 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
1883 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1884 wait_for_completion(&bnad->bnad_completions.rx_comp);
1885
1886 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
1887 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
1888
1889 spin_lock_irqsave(&bnad->bna_lock, flags);
1890 bna_rx_destroy(rx_info->rx);
1891 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1892
1893 rx_info->rx = NULL;
1894
1895 bnad_rx_res_free(bnad, res_info);
1896}
1897
1898/* Called with mutex_lock(&bnad->conf_mutex) held */
1899int
078086f3 1900bnad_setup_rx(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 1901{
1902 int err;
1903 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1904 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1905 struct bna_intr_info *intr_info =
1906 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
1907 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1908 struct bna_rx_event_cbfn rx_cbfn;
1909 struct bna_rx *rx;
1910 unsigned long flags;
1911
078086f3
RM		 1912 rx_info->rx_id = rx_id;
1913
8b230ed8
RM		 1914 /* Initialize the Rx object configuration */
1915 bnad_init_rx_config(bnad, rx_config);
1916
1917 /* Initialize the Rx event handlers */
1918 rx_cbfn.rcb_setup_cbfn = bnad_cb_rcb_setup;
be7fa326 1919 rx_cbfn.rcb_destroy_cbfn = bnad_cb_rcb_destroy;
8b230ed8
RM		 1920 rx_cbfn.ccb_setup_cbfn = bnad_cb_ccb_setup;
1921 rx_cbfn.ccb_destroy_cbfn = bnad_cb_ccb_destroy;
1922 rx_cbfn.rx_cleanup_cbfn = bnad_cb_rx_cleanup;
1923 rx_cbfn.rx_post_cbfn = bnad_cb_rx_post;
1924
1925 /* Get BNA's resource requirement for one Rx object */
1926 spin_lock_irqsave(&bnad->bna_lock, flags);
1927 bna_rx_res_req(rx_config, res_info);
1928 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1929
1930 /* Fill Unmap Q memory requirements */
1931 BNAD_FILL_UNMAPQ_MEM_REQ(
1932 &res_info[BNA_RX_RES_MEM_T_UNMAPQ],
1933 rx_config->num_paths +
1934 ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 0 :
1935 rx_config->num_paths), BNAD_RX_UNMAPQ_DEPTH);
1936
1937 /* Allocate resource */
1938 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
1939 if (err)
1940 return err;
1941
1942 /* Ask BNA to create one Rx object, supplying required resources */
1943 spin_lock_irqsave(&bnad->bna_lock, flags);
1944 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
1945 rx_info);
1946 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1947 if (!rx)
1948 goto err_return;
1949 rx_info->rx = rx;
1950
1951 /* Register ISR for the Rx object */
1952 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1953 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
1954 rx_config->num_paths);
1955 if (err)
1956 goto err_return;
1957 }
1958
1959 /* Enable NAPI */
1960 bnad_napi_enable(bnad, rx_id);
1961
1962 spin_lock_irqsave(&bnad->bna_lock, flags);
1963 if (0 == rx_id) {
1964 /* Set up Dynamic Interrupt Moderation Vector */
1965 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
1966 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
1967
1968 /* Enable VLAN filtering only on the default Rx */
1969 bna_rx_vlanfilter_enable(rx);
1970
1971 /* Start the DIM timer */
1972 bnad_dim_timer_start(bnad);
1973 }
1974
1975 bna_rx_enable(rx);
1976 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1977
1978 return 0;
1979
1980err_return:
1981 bnad_cleanup_rx(bnad, rx_id);
1982 return err;
1983}
1984
1985/* Called with conf_lock & bnad->bna_lock held */
1986void
1987bnad_tx_coalescing_timeo_set(struct bnad *bnad)
1988{
1989 struct bnad_tx_info *tx_info;
1990
1991 tx_info = &bnad->tx_info[0];
1992 if (!tx_info->tx)
1993 return;
1994
1995 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
1996}
1997
1998/* Called with conf_lock & bnad->bna_lock held */
1999void
2000bnad_rx_coalescing_timeo_set(struct bnad *bnad)
2001{
2002 struct bnad_rx_info *rx_info;
0120b99c 2003 int i;
8b230ed8
RM		 2004
2005 for (i = 0; i < bnad->num_rx; i++) {
2006 rx_info = &bnad->rx_info[i];
2007 if (!rx_info->rx)
2008 continue;
2009 bna_rx_coalescing_timeo_set(rx_info->rx,
2010 bnad->rx_coalescing_timeo);
2011 }
2012}
2013
2014/*
2015 * Called with bnad->bna_lock held
2016 */
2017static int
2018bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
2019{
2020 int ret;
2021
2022 if (!is_valid_ether_addr(mac_addr))
2023 return -EADDRNOTAVAIL;
2024
2025 /* If datapath is down, pretend everything went through */
2026 if (!bnad->rx_info[0].rx)
2027 return 0;
2028
2029 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
2030 if (ret != BNA_CB_SUCCESS)
2031 return -EADDRNOTAVAIL;
2032
2033 return 0;
2034}
2035
2036/* Should be called with conf_lock held */
2037static int
2038bnad_enable_default_bcast(struct bnad *bnad)
2039{
2040 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
2041 int ret;
2042 unsigned long flags;
2043
2044 init_completion(&bnad->bnad_completions.mcast_comp);
2045
2046 spin_lock_irqsave(&bnad->bna_lock, flags);
2047 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
2048 bnad_cb_rx_mcast_add);
2049 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2050
2051 if (ret == BNA_CB_SUCCESS)
2052 wait_for_completion(&bnad->bnad_completions.mcast_comp);
2053 else
2054 return -ENODEV;
2055
2056 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
2057 return -ENODEV;
2058
2059 return 0;
2060}
2061
aad75b66
RM		 2062/* Called with bnad_conf_lock() held */
2063static void
2064bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
2065{
f859d7cb 2066 u16 vid;
aad75b66
RM		 2067 unsigned long flags;
2068
078086f3 2069 BUG_ON(!(VLAN_N_VID == BFI_ENET_VLAN_ID_MAX));
aad75b66 2070
f859d7cb 2071 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) {
aad75b66 2072 spin_lock_irqsave(&bnad->bna_lock, flags);
f859d7cb 2073 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid);
aad75b66
RM		 2074 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2075 }
2076}
2077
8b230ed8
RM		 2078/* Statistics utilities */
2079void
250e061e 2080bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 2081{
8b230ed8
RM		 2082 int i, j;
2083
2084 for (i = 0; i < bnad->num_rx; i++) {
2085 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2086 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
250e061e 2087 stats->rx_packets += bnad->rx_info[i].
8b230ed8 2088 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
250e061e 2089 stats->rx_bytes += bnad->rx_info[i].
8b230ed8
RM		 2090 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2091 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2092 bnad->rx_info[i].rx_ctrl[j].ccb->
2093 rcb[1]->rxq) {
250e061e 2094 stats->rx_packets +=
8b230ed8
RM		 2095 bnad->rx_info[i].rx_ctrl[j].
2096 ccb->rcb[1]->rxq->rx_packets;
250e061e 2097 stats->rx_bytes +=
8b230ed8
RM		 2098 bnad->rx_info[i].rx_ctrl[j].
2099 ccb->rcb[1]->rxq->rx_bytes;
2100 }
2101 }
2102 }
2103 }
2104 for (i = 0; i < bnad->num_tx; i++) {
2105 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2106 if (bnad->tx_info[i].tcb[j]) {
250e061e 2107 stats->tx_packets +=
8b230ed8 2108 bnad->tx_info[i].tcb[j]->txq->tx_packets;
250e061e 2109 stats->tx_bytes +=
8b230ed8
RM		 2110 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2111 }
2112 }
2113 }
2114}
2115
2116/*
2117 * Must be called with the bna_lock held.
2118 */
2119void
250e061e 2120bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 2121{
078086f3
RM		 2122 struct bfi_enet_stats_mac *mac_stats;
2123 u32 bmap;
8b230ed8
RM		 2124 int i;
2125
078086f3 2126 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats;
250e061e 2127 stats->rx_errors =
8b230ed8
RM		 2128 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2129 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2130 mac_stats->rx_undersize;
250e061e 2131 stats->tx_errors = mac_stats->tx_fcs_error +
8b230ed8 2132 mac_stats->tx_undersize;
250e061e
ED		 2133 stats->rx_dropped = mac_stats->rx_drop;
2134 stats->tx_dropped = mac_stats->tx_drop;
2135 stats->multicast = mac_stats->rx_multicast;
2136 stats->collisions = mac_stats->tx_total_collision;
8b230ed8 2137
250e061e 2138 stats->rx_length_errors = mac_stats->rx_frame_length_error;
8b230ed8
RM		 2139
2140 /* receive ring buffer overflow ?? */
2141
250e061e
ED		 2142 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2143 stats->rx_frame_errors = mac_stats->rx_alignment_error;
8b230ed8 2144 /* recv'r fifo overrun */
078086f3
RM		 2145 bmap = bna_rx_rid_mask(&bnad->bna);
2146 for (i = 0; bmap; i++) {
8b230ed8 2147 if (bmap & 1) {
250e061e 2148 stats->rx_fifo_errors +=
8b230ed8 2149 bnad->stats.bna_stats->
078086f3 2150 hw_stats.rxf_stats[i].frame_drops;
8b230ed8
RM		 2151 break;
2152 }
2153 bmap >>= 1;
2154 }
2155}
2156
2157static void
2158bnad_mbox_irq_sync(struct bnad *bnad)
2159{
2160 u32 irq;
2161 unsigned long flags;
2162
2163 spin_lock_irqsave(&bnad->bna_lock, flags);
2164 if (bnad->cfg_flags & BNAD_CF_MSIX)
8811e267 2165 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
8b230ed8
RM		 2166 else
2167 irq = bnad->pcidev->irq;
2168 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2169
2170 synchronize_irq(irq);
2171}
2172
2173/* Utility used by bnad_start_xmit, for doing TSO */
2174static int
2175bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2176{
2177 int err;
2178
2179 /* SKB_GSO_TCPV4 and SKB_GSO_TCPV6 is defined since 2.6.18. */
2180 BUG_ON(!(skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4 ||
2181 skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6));
2182 if (skb_header_cloned(skb)) {
2183 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2184 if (err) {
2185 BNAD_UPDATE_CTR(bnad, tso_err);
2186 return err;
2187 }
2188 }
2189
2190 /*
2191 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2192 * excluding the length field.
2193 */
2194 if (skb->protocol == htons(ETH_P_IP)) {
2195 struct iphdr *iph = ip_hdr(skb);
2196
2197 /* Do we really need these? */
2198 iph->tot_len = 0;
2199 iph->check = 0;
2200
2201 tcp_hdr(skb)->check =
2202 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2203 IPPROTO_TCP, 0);
2204 BNAD_UPDATE_CTR(bnad, tso4);
2205 } else {
2206 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2207
2208 BUG_ON(!(skb->protocol == htons(ETH_P_IPV6)));
2209 ipv6h->payload_len = 0;
2210 tcp_hdr(skb)->check =
2211 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2212 IPPROTO_TCP, 0);
2213 BNAD_UPDATE_CTR(bnad, tso6);
2214 }
2215
2216 return 0;
2217}
2218
2219/*
2220 * Initialize Q numbers depending on Rx Paths
2221 * Called with bnad->bna_lock held, because of cfg_flags
2222 * access.
2223 */
2224static void
2225bnad_q_num_init(struct bnad *bnad)
2226{
2227 int rxps;
2228
2229 rxps = min((uint)num_online_cpus(),
772b5235 2230 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX));
8b230ed8
RM		 2231
2232 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2233 rxps = 1; /* INTx */
2234
2235 bnad->num_rx = 1;
2236 bnad->num_tx = 1;
2237 bnad->num_rxp_per_rx = rxps;
2238 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2239}
2240
2241/*
2242 * Adjusts the Q numbers, given a number of msix vectors
2243 * Give preference to RSS as opposed to Tx priority Queues,
2244 * in such a case, just use 1 Tx Q
2245 * Called with bnad->bna_lock held b'cos of cfg_flags access
2246 */
2247static void
078086f3 2248bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp)
8b230ed8
RM		 2249{
2250 bnad->num_txq_per_tx = 1;
2251 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2252 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2253 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2254 bnad->num_rxp_per_rx = msix_vectors -
2255 (bnad->num_tx * bnad->num_txq_per_tx) -
2256 BNAD_MAILBOX_MSIX_VECTORS;
2257 } else
2258 bnad->num_rxp_per_rx = 1;
2259}
2260
078086f3
RM		 2261/* Enable / disable ioceth */
2262static int
2263bnad_ioceth_disable(struct bnad *bnad)
8b230ed8
RM		 2264{
2265 unsigned long flags;
078086f3 2266 int err = 0;
8b230ed8
RM		 2267
2268 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2269 init_completion(&bnad->bnad_completions.ioc_comp);
2270 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP);
8b230ed8
RM		 2271 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2272
078086f3
RM		 2273 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2274 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2275
2276 err = bnad->bnad_completions.ioc_comp_status;
2277 return err;
8b230ed8
RM		 2278}
2279
2280static int
078086f3 2281bnad_ioceth_enable(struct bnad *bnad)
8b230ed8
RM		 2282{
2283 int err = 0;
2284 unsigned long flags;
2285
8b230ed8 2286 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2287 init_completion(&bnad->bnad_completions.ioc_comp);
2288 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING;
2289 bna_ioceth_enable(&bnad->bna.ioceth);
8b230ed8
RM		 2290 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2291
078086f3
RM		 2292 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2293 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
8b230ed8 2294
078086f3 2295 err = bnad->bnad_completions.ioc_comp_status;
8b230ed8
RM		 2296
2297 return err;
2298}
2299
2300/* Free BNA resources */
2301static void
078086f3
RM		 2302bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info,
2303 u32 res_val_max)
8b230ed8
RM		 2304{
2305 int i;
8b230ed8 2306
078086f3
RM		 2307 for (i = 0; i < res_val_max; i++)
2308 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
8b230ed8
RM		 2309}
2310
2311/* Allocates memory and interrupt resources for BNA */
2312static int
078086f3
RM		 2313bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
2314 u32 res_val_max)
8b230ed8
RM		 2315{
2316 int i, err;
8b230ed8 2317
078086f3
RM		 2318 for (i = 0; i < res_val_max; i++) {
2319 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
8b230ed8
RM		 2320 if (err)
2321 goto err_return;
2322 }
2323 return 0;
2324
2325err_return:
078086f3 2326 bnad_res_free(bnad, res_info, res_val_max);
8b230ed8
RM		 2327 return err;
2328}
2329
2330/* Interrupt enable / disable */
2331static void
2332bnad_enable_msix(struct bnad *bnad)
2333{
2334 int i, ret;
8b230ed8
RM		 2335 unsigned long flags;
2336
2337 spin_lock_irqsave(&bnad->bna_lock, flags);
2338 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2339 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2340 return;
2341 }
2342 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2343
2344 if (bnad->msix_table)
2345 return;
2346
8b230ed8 2347 bnad->msix_table =
b7ee31c5 2348 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
8b230ed8
RM		 2349
2350 if (!bnad->msix_table)
2351 goto intx_mode;
2352
b7ee31c5 2353 for (i = 0; i < bnad->msix_num; i++)
8b230ed8
RM		 2354 bnad->msix_table[i].entry = i;
2355
b7ee31c5 2356 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num);
8b230ed8
RM		 2357 if (ret > 0) {
2358 /* Not enough MSI-X vectors. */
2359
2360 spin_lock_irqsave(&bnad->bna_lock, flags);
2361 /* ret = #of vectors that we got */
078086f3 2362 bnad_q_num_adjust(bnad, ret, 0);
8b230ed8
RM		 2363 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2364
2365 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx)
2366 + (bnad->num_rx
2367 * bnad->num_rxp_per_rx) +
2368 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8 2369
078086f3
RM		 2370 if (bnad->msix_num > ret)
2371 goto intx_mode;
2372
8b230ed8
RM		 2373 /* Try once more with adjusted numbers */
2374 /* If this fails, fall back to INTx */
2375 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
b7ee31c5 2376 bnad->msix_num);
8b230ed8
RM		 2377 if (ret)
2378 goto intx_mode;
2379
2380 } else if (ret < 0)
2381 goto intx_mode;
078086f3
RM		 2382
2383 pci_intx(bnad->pcidev, 0);
2384
8b230ed8
RM		 2385 return;
2386
2387intx_mode:
2388
2389 kfree(bnad->msix_table);
2390 bnad->msix_table = NULL;
2391 bnad->msix_num = 0;
8b230ed8
RM		 2392 spin_lock_irqsave(&bnad->bna_lock, flags);
2393 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2394 bnad_q_num_init(bnad);
2395 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2396}
2397
2398static void
2399bnad_disable_msix(struct bnad *bnad)
2400{
2401 u32 cfg_flags;
2402 unsigned long flags;
2403
2404 spin_lock_irqsave(&bnad->bna_lock, flags);
2405 cfg_flags = bnad->cfg_flags;
2406 if (bnad->cfg_flags & BNAD_CF_MSIX)
2407 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2408 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2409
2410 if (cfg_flags & BNAD_CF_MSIX) {
2411 pci_disable_msix(bnad->pcidev);
2412 kfree(bnad->msix_table);
2413 bnad->msix_table = NULL;
2414 }
2415}
2416
2417/* Netdev entry points */
2418static int
2419bnad_open(struct net_device *netdev)
2420{
2421 int err;
2422 struct bnad *bnad = netdev_priv(netdev);
2423 struct bna_pause_config pause_config;
2424 int mtu;
2425 unsigned long flags;
2426
2427 mutex_lock(&bnad->conf_mutex);
2428
2429 /* Tx */
2430 err = bnad_setup_tx(bnad, 0);
2431 if (err)
2432 goto err_return;
2433
2434 /* Rx */
2435 err = bnad_setup_rx(bnad, 0);
2436 if (err)
2437 goto cleanup_tx;
2438
2439 /* Port */
2440 pause_config.tx_pause = 0;
2441 pause_config.rx_pause = 0;
2442
078086f3 2443 mtu = ETH_HLEN + VLAN_HLEN + bnad->netdev->mtu + ETH_FCS_LEN;
8b230ed8
RM		 2444
2445 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2446 bna_enet_mtu_set(&bnad->bna.enet, mtu, NULL);
2447 bna_enet_pause_config(&bnad->bna.enet, &pause_config, NULL);
2448 bna_enet_enable(&bnad->bna.enet);
8b230ed8
RM		 2449 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2450
2451 /* Enable broadcast */
2452 bnad_enable_default_bcast(bnad);
2453
aad75b66
RM		 2454 /* Restore VLANs, if any */
2455 bnad_restore_vlans(bnad, 0);
2456
8b230ed8
RM		 2457 /* Set the UCAST address */
2458 spin_lock_irqsave(&bnad->bna_lock, flags);
2459 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2460 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2461
2462 /* Start the stats timer */
2463 bnad_stats_timer_start(bnad);
2464
2465 mutex_unlock(&bnad->conf_mutex);
2466
2467 return 0;
2468
2469cleanup_tx:
2470 bnad_cleanup_tx(bnad, 0);
2471
2472err_return:
2473 mutex_unlock(&bnad->conf_mutex);
2474 return err;
2475}
2476
2477static int
2478bnad_stop(struct net_device *netdev)
2479{
2480 struct bnad *bnad = netdev_priv(netdev);
2481 unsigned long flags;
2482
2483 mutex_lock(&bnad->conf_mutex);
2484
2485 /* Stop the stats timer */
2486 bnad_stats_timer_stop(bnad);
2487
078086f3 2488 init_completion(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 2489
2490 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2491 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP,
2492 bnad_cb_enet_disabled);
8b230ed8
RM		 2493 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2494
078086f3 2495 wait_for_completion(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 2496
2497 bnad_cleanup_tx(bnad, 0);
2498 bnad_cleanup_rx(bnad, 0);
2499
2500 /* Synchronize mailbox IRQ */
2501 bnad_mbox_irq_sync(bnad);
2502
2503 mutex_unlock(&bnad->conf_mutex);
2504
2505 return 0;
2506}
2507
2508/* TX */
2509/*
2510 * bnad_start_xmit : Netdev entry point for Transmit
2511 * Called under lock held by net_device
2512 */
2513static netdev_tx_t
2514bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2515{
2516 struct bnad *bnad = netdev_priv(netdev);
078086f3
RM		 2517 u32 txq_id = 0;
2518 struct bna_tcb *tcb = bnad->tx_info[0].tcb[txq_id];
8b230ed8 2519
0120b99c
RM		 2520 u16 txq_prod, vlan_tag = 0;
2521 u32 unmap_prod, wis, wis_used, wi_range;
2522 u32 vectors, vect_id, i, acked;
0120b99c 2523 int err;
8b230ed8 2524
078086f3 2525 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
0120b99c 2526 dma_addr_t dma_addr;
8b230ed8 2527 struct bna_txq_entry *txqent;
078086f3 2528 u16 flags;
8b230ed8
RM		 2529
2530 if (unlikely
2531 (skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) {
2532 dev_kfree_skb(skb);
2533 return NETDEV_TX_OK;
2534 }
2535
2536 /*
2537 * Takes care of the Tx that is scheduled between clearing the flag
078086f3 2538 * and the netif_stop_all_queue() call.
8b230ed8 2539 */
be7fa326 2540 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
8b230ed8
RM		 2541 dev_kfree_skb(skb);
2542 return NETDEV_TX_OK;
2543 }
2544
8b230ed8
RM		 2545 vectors = 1 + skb_shinfo(skb)->nr_frags;
2546 if (vectors > BFI_TX_MAX_VECTORS_PER_PKT) {
2547 dev_kfree_skb(skb);
2548 return NETDEV_TX_OK;
2549 }
2550 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2551 acked = 0;
078086f3
RM		 2552 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2553 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
8b230ed8
RM		 2554 if ((u16) (*tcb->hw_consumer_index) !=
2555 tcb->consumer_index &&
2556 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2557 acked = bnad_free_txbufs(bnad, tcb);
be7fa326
RM		 2558 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2559 bna_ib_ack(tcb->i_dbell, acked);
8b230ed8
RM		 2560 smp_mb__before_clear_bit();
2561 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2562 } else {
2563 netif_stop_queue(netdev);
2564 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2565 }
2566
2567 smp_mb();
2568 /*
2569 * Check again to deal with race condition between
2570 * netif_stop_queue here, and netif_wake_queue in
2571 * interrupt handler which is not inside netif tx lock.
2572 */
2573 if (likely
2574 (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2575 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2576 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2577 return NETDEV_TX_BUSY;
2578 } else {
2579 netif_wake_queue(netdev);
2580 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
2581 }
2582 }
2583
2584 unmap_prod = unmap_q->producer_index;
2585 wis_used = 1;
2586 vect_id = 0;
2587 flags = 0;
2588
2589 txq_prod = tcb->producer_index;
2590 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, txqent, wi_range);
2591 BUG_ON(!(wi_range <= tcb->q_depth));
2592 txqent->hdr.wi.reserved = 0;
2593 txqent->hdr.wi.num_vectors = vectors;
2594 txqent->hdr.wi.opcode =
2595 htons((skb_is_gso(skb) ? BNA_TXQ_WI_SEND_LSO :
2596 BNA_TXQ_WI_SEND));
2597
eab6d18d 2598 if (vlan_tx_tag_present(skb)) {
8b230ed8
RM		 2599 vlan_tag = (u16) vlan_tx_tag_get(skb);
2600 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2601 }
2602 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2603 vlan_tag =
2604 (tcb->priority & 0x7) << 13 | (vlan_tag & 0x1fff);
2605 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2606 }
2607
2608 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2609
2610 if (skb_is_gso(skb)) {
2611 err = bnad_tso_prepare(bnad, skb);
2612 if (err) {
2613 dev_kfree_skb(skb);
2614 return NETDEV_TX_OK;
2615 }
2616 txqent->hdr.wi.lso_mss = htons(skb_is_gso(skb));
2617 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2618 txqent->hdr.wi.l4_hdr_size_n_offset =
2619 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2620 (tcp_hdrlen(skb) >> 2,
2621 skb_transport_offset(skb)));
2622 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2623 u8 proto = 0;
2624
2625 txqent->hdr.wi.lso_mss = 0;
2626
2627 if (skb->protocol == htons(ETH_P_IP))
2628 proto = ip_hdr(skb)->protocol;
2629 else if (skb->protocol == htons(ETH_P_IPV6)) {
2630 /* nexthdr may not be TCP immediately. */
2631 proto = ipv6_hdr(skb)->nexthdr;
2632 }
2633 if (proto == IPPROTO_TCP) {
2634 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2635 txqent->hdr.wi.l4_hdr_size_n_offset =
2636 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2637 (0, skb_transport_offset(skb)));
2638
2639 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2640
2641 BUG_ON(!(skb_headlen(skb) >=
2642 skb_transport_offset(skb) + tcp_hdrlen(skb)));
2643
2644 } else if (proto == IPPROTO_UDP) {
2645 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2646 txqent->hdr.wi.l4_hdr_size_n_offset =
2647 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2648 (0, skb_transport_offset(skb)));
2649
2650 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2651
2652 BUG_ON(!(skb_headlen(skb) >=
2653 skb_transport_offset(skb) +
2654 sizeof(struct udphdr)));
2655 } else {
2656 err = skb_checksum_help(skb);
2657 BNAD_UPDATE_CTR(bnad, csum_help);
2658 if (err) {
2659 dev_kfree_skb(skb);
2660 BNAD_UPDATE_CTR(bnad, csum_help_err);
2661 return NETDEV_TX_OK;
2662 }
2663 }
2664 } else {
2665 txqent->hdr.wi.lso_mss = 0;
2666 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
2667 }
2668
2669 txqent->hdr.wi.flags = htons(flags);
2670
2671 txqent->hdr.wi.frame_length = htonl(skb->len);
2672
2673 unmap_q->unmap_array[unmap_prod].skb = skb;
2674 BUG_ON(!(skb_headlen(skb) <= BFI_TX_MAX_DATA_PER_VECTOR));
2675 txqent->vector[vect_id].length = htons(skb_headlen(skb));
5ea74318
IV		 2676 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
2677 skb_headlen(skb), DMA_TO_DEVICE);
2678 dma_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
8b230ed8
RM		 2679 dma_addr);
2680
2681 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2682 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2683
2684 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2685 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
078086f3 2686 u16 size = frag->size;
8b230ed8
RM		 2687
2688 if (++vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
2689 vect_id = 0;
2690 if (--wi_range)
2691 txqent++;
2692 else {
2693 BNA_QE_INDX_ADD(txq_prod, wis_used,
2694 tcb->q_depth);
2695 wis_used = 0;
2696 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt,
2697 txqent, wi_range);
2698 BUG_ON(!(wi_range <= tcb->q_depth));
2699 }
2700 wis_used++;
2701 txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
2702 }
2703
2704 BUG_ON(!(size <= BFI_TX_MAX_DATA_PER_VECTOR));
2705 txqent->vector[vect_id].length = htons(size);
5ea74318
IV		 2706 dma_addr = dma_map_page(&bnad->pcidev->dev, frag->page,
2707 frag->page_offset, size, DMA_TO_DEVICE);
2708 dma_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
8b230ed8
RM		 2709 dma_addr);
2710 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2711 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2712 }
2713
2714 unmap_q->producer_index = unmap_prod;
2715 BNA_QE_INDX_ADD(txq_prod, wis_used, tcb->q_depth);
2716 tcb->producer_index = txq_prod;
2717
2718 smp_mb();
be7fa326
RM		 2719
2720 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2721 return NETDEV_TX_OK;
2722
8b230ed8
RM		 2723 bna_txq_prod_indx_doorbell(tcb);
2724
2725 if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index)
2726 tasklet_schedule(&bnad->tx_free_tasklet);
2727
2728 return NETDEV_TX_OK;
2729}
2730
2731/*
2732 * Used spin_lock to synchronize reading of stats structures, which
2733 * is written by BNA under the same lock.
2734 */
250e061e
ED		 2735static struct rtnl_link_stats64 *
2736bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
8b230ed8
RM		 2737{
2738 struct bnad *bnad = netdev_priv(netdev);
2739 unsigned long flags;
2740
2741 spin_lock_irqsave(&bnad->bna_lock, flags);
2742
250e061e
ED		 2743 bnad_netdev_qstats_fill(bnad, stats);
2744 bnad_netdev_hwstats_fill(bnad, stats);
8b230ed8
RM		 2745
2746 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2747
250e061e 2748 return stats;
8b230ed8
RM		 2749}
2750
2751static void
2752bnad_set_rx_mode(struct net_device *netdev)
2753{
2754 struct bnad *bnad = netdev_priv(netdev);
2755 u32 new_mask, valid_mask;
2756 unsigned long flags;
2757
2758 spin_lock_irqsave(&bnad->bna_lock, flags);
2759
2760 new_mask = valid_mask = 0;
2761
2762 if (netdev->flags & IFF_PROMISC) {
2763 if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) {
2764 new_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2765 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2766 bnad->cfg_flags |= BNAD_CF_PROMISC;
2767 }
2768 } else {
2769 if (bnad->cfg_flags & BNAD_CF_PROMISC) {
2770 new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT;
2771 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2772 bnad->cfg_flags &= ~BNAD_CF_PROMISC;
2773 }
2774 }
2775
2776 if (netdev->flags & IFF_ALLMULTI) {
2777 if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) {
2778 new_mask |= BNA_RXMODE_ALLMULTI;
2779 valid_mask |= BNA_RXMODE_ALLMULTI;
2780 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
2781 }
2782 } else {
2783 if (bnad->cfg_flags & BNAD_CF_ALLMULTI) {
2784 new_mask &= ~BNA_RXMODE_ALLMULTI;
2785 valid_mask |= BNA_RXMODE_ALLMULTI;
2786 bnad->cfg_flags &= ~BNAD_CF_ALLMULTI;
2787 }
2788 }
2789
2790 bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL);
2791
2792 if (!netdev_mc_empty(netdev)) {
2793 u8 *mcaddr_list;
2794 int mc_count = netdev_mc_count(netdev);
2795
2796 /* Index 0 holds the broadcast address */
2797 mcaddr_list =
2798 kzalloc((mc_count + 1) * ETH_ALEN,
2799 GFP_ATOMIC);
2800 if (!mcaddr_list)
ca1cef3a 2801 goto unlock;
8b230ed8
RM		 2802
2803 memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN);
2804
2805 /* Copy rest of the MC addresses */
2806 bnad_netdev_mc_list_get(netdev, mcaddr_list);
2807
2808 bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
2809 mcaddr_list, NULL);
2810
2811 /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
2812 kfree(mcaddr_list);
2813 }
ca1cef3a 2814unlock:
8b230ed8
RM		 2815 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2816}
2817
2818/*
2819 * bna_lock is used to sync writes to netdev->addr
2820 * conf_lock cannot be used since this call may be made
2821 * in a non-blocking context.
2822 */
2823static int
2824bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
2825{
2826 int err;
2827 struct bnad *bnad = netdev_priv(netdev);
2828 struct sockaddr *sa = (struct sockaddr *)mac_addr;
2829 unsigned long flags;
2830
2831 spin_lock_irqsave(&bnad->bna_lock, flags);
2832
2833 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
2834
2835 if (!err)
2836 memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
2837
2838 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2839
2840 return err;
2841}
2842
2843static int
078086f3 2844bnad_mtu_set(struct bnad *bnad, int mtu)
8b230ed8 2845{
8b230ed8
RM		 2846 unsigned long flags;
2847
078086f3
RM		 2848 init_completion(&bnad->bnad_completions.mtu_comp);
2849
2850 spin_lock_irqsave(&bnad->bna_lock, flags);
2851 bna_enet_mtu_set(&bnad->bna.enet, mtu, bnad_cb_enet_mtu_set);
2852 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2853
2854 wait_for_completion(&bnad->bnad_completions.mtu_comp);
2855
2856 return bnad->bnad_completions.mtu_comp_status;
2857}
2858
2859static int
2860bnad_change_mtu(struct net_device *netdev, int new_mtu)
2861{
2862 int err, mtu = netdev->mtu;
8b230ed8
RM		 2863 struct bnad *bnad = netdev_priv(netdev);
2864
2865 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
2866 return -EINVAL;
2867
2868 mutex_lock(&bnad->conf_mutex);
2869
2870 netdev->mtu = new_mtu;
2871
078086f3
RM		 2872 mtu = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
2873 err = bnad_mtu_set(bnad, mtu);
2874 if (err)
2875 err = -EBUSY;
8b230ed8
RM		 2876
2877 mutex_unlock(&bnad->conf_mutex);
2878 return err;
2879}
2880
8b230ed8
RM		 2881static void
2882bnad_vlan_rx_add_vid(struct net_device *netdev,
2883 unsigned short vid)
2884{
2885 struct bnad *bnad = netdev_priv(netdev);
2886 unsigned long flags;
2887
2888 if (!bnad->rx_info[0].rx)
2889 return;
2890
2891 mutex_lock(&bnad->conf_mutex);
2892
2893 spin_lock_irqsave(&bnad->bna_lock, flags);
2894 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
f859d7cb 2895 set_bit(vid, bnad->active_vlans);
8b230ed8
RM		 2896 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2897
2898 mutex_unlock(&bnad->conf_mutex);
2899}
2900
2901static void
2902bnad_vlan_rx_kill_vid(struct net_device *netdev,
2903 unsigned short vid)
2904{
2905 struct bnad *bnad = netdev_priv(netdev);
2906 unsigned long flags;
2907
2908 if (!bnad->rx_info[0].rx)
2909 return;
2910
2911 mutex_lock(&bnad->conf_mutex);
2912
2913 spin_lock_irqsave(&bnad->bna_lock, flags);
f859d7cb 2914 clear_bit(vid, bnad->active_vlans);
8b230ed8
RM		 2915 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
2916 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2917
2918 mutex_unlock(&bnad->conf_mutex);
2919}
2920
2921#ifdef CONFIG_NET_POLL_CONTROLLER
2922static void
2923bnad_netpoll(struct net_device *netdev)
2924{
2925 struct bnad *bnad = netdev_priv(netdev);
2926 struct bnad_rx_info *rx_info;
2927 struct bnad_rx_ctrl *rx_ctrl;
2928 u32 curr_mask;
2929 int i, j;
2930
2931 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2932 bna_intx_disable(&bnad->bna, curr_mask);
2933 bnad_isr(bnad->pcidev->irq, netdev);
2934 bna_intx_enable(&bnad->bna, curr_mask);
2935 } else {
2936 for (i = 0; i < bnad->num_rx; i++) {
2937 rx_info = &bnad->rx_info[i];
2938 if (!rx_info->rx)
2939 continue;
2940 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2941 rx_ctrl = &rx_info->rx_ctrl[j];
2942 if (rx_ctrl->ccb) {
2943 bnad_disable_rx_irq(bnad,
2944 rx_ctrl->ccb);
2945 bnad_netif_rx_schedule_poll(bnad,
2946 rx_ctrl->ccb);
2947 }
2948 }
2949 }
2950 }
2951}
2952#endif
2953
2954static const struct net_device_ops bnad_netdev_ops = {
2955 .ndo_open = bnad_open,
2956 .ndo_stop = bnad_stop,
2957 .ndo_start_xmit = bnad_start_xmit,
250e061e 2958 .ndo_get_stats64 = bnad_get_stats64,
8b230ed8 2959 .ndo_set_rx_mode = bnad_set_rx_mode,
8b230ed8
RM		 2960 .ndo_validate_addr = eth_validate_addr,
2961 .ndo_set_mac_address = bnad_set_mac_address,
2962 .ndo_change_mtu = bnad_change_mtu,
8b230ed8
RM		 2963 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
2964 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
2965#ifdef CONFIG_NET_POLL_CONTROLLER
2966 .ndo_poll_controller = bnad_netpoll
2967#endif
2968};
2969
2970static void
2971bnad_netdev_init(struct bnad *bnad, bool using_dac)
2972{
2973 struct net_device *netdev = bnad->netdev;
2974
e5ee20e7
MM		 2975 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
2976 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2977 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_TX;
8b230ed8 2978
e5ee20e7
MM		 2979 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
2980 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2981 NETIF_F_TSO | NETIF_F_TSO6;
8b230ed8 2982
e5ee20e7
MM		 2983 netdev->features |= netdev->hw_features |
2984 NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
8b230ed8
RM		 2985
2986 if (using_dac)
2987 netdev->features |= NETIF_F_HIGHDMA;
2988
8b230ed8
RM		 2989 netdev->mem_start = bnad->mmio_start;
2990 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
2991
2992 netdev->netdev_ops = &bnad_netdev_ops;
2993 bnad_set_ethtool_ops(netdev);
2994}
2995
2996/*
2997 * 1. Initialize the bnad structure
2998 * 2. Setup netdev pointer in pci_dev
2999 * 3. Initialze Tx free tasklet
3000 * 4. Initialize no. of TxQ & CQs & MSIX vectors
3001 */
3002static int
3003bnad_init(struct bnad *bnad,
3004 struct pci_dev *pdev, struct net_device *netdev)
3005{
3006 unsigned long flags;
3007
3008 SET_NETDEV_DEV(netdev, &pdev->dev);
3009 pci_set_drvdata(pdev, netdev);
3010
3011 bnad->netdev = netdev;
3012 bnad->pcidev = pdev;
3013 bnad->mmio_start = pci_resource_start(pdev, 0);
3014 bnad->mmio_len = pci_resource_len(pdev, 0);
3015 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
3016 if (!bnad->bar0) {
3017 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
3018 pci_set_drvdata(pdev, NULL);
3019 return -ENOMEM;
3020 }
3021 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
3022 (unsigned long long) bnad->mmio_len);
3023
3024 spin_lock_irqsave(&bnad->bna_lock, flags);
3025 if (!bnad_msix_disable)
3026 bnad->cfg_flags = BNAD_CF_MSIX;
3027
3028 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
3029
3030 bnad_q_num_init(bnad);
3031 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3032
3033 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
3034 (bnad->num_rx * bnad->num_rxp_per_rx) +
3035 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8
RM		 3036
3037 bnad->txq_depth = BNAD_TXQ_DEPTH;
3038 bnad->rxq_depth = BNAD_RXQ_DEPTH;
8b230ed8
RM		 3039
3040 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3041 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
3042
3043 tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet,
3044 (unsigned long)bnad);
3045
3046 return 0;
3047}
3048
3049/*
3050 * Must be called after bnad_pci_uninit()
3051 * so that iounmap() and pci_set_drvdata(NULL)
3052 * happens only after PCI uninitialization.
3053 */
3054static void
3055bnad_uninit(struct bnad *bnad)
3056{
3057 if (bnad->bar0)
3058 iounmap(bnad->bar0);
3059 pci_set_drvdata(bnad->pcidev, NULL);
3060}
3061
3062/*
3063 * Initialize locks
078086f3 3064 a) Per ioceth mutes used for serializing configuration
8b230ed8
RM		 3065 changes from OS interface
3066 b) spin lock used to protect bna state machine
3067 */
3068static void
3069bnad_lock_init(struct bnad *bnad)
3070{
3071 spin_lock_init(&bnad->bna_lock);
3072 mutex_init(&bnad->conf_mutex);
3073}
3074
3075static void
3076bnad_lock_uninit(struct bnad *bnad)
3077{
3078 mutex_destroy(&bnad->conf_mutex);
3079}
3080
3081/* PCI Initialization */
3082static int
3083bnad_pci_init(struct bnad *bnad,
3084 struct pci_dev *pdev, bool *using_dac)
3085{
3086 int err;
3087
3088 err = pci_enable_device(pdev);
3089 if (err)
3090 return err;
3091 err = pci_request_regions(pdev, BNAD_NAME);
3092 if (err)
3093 goto disable_device;
5ea74318
IV		 3094 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
3095 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
8b230ed8
RM		 3096 *using_dac = 1;
3097 } else {
5ea74318 3098 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
8b230ed8 3099 if (err) {
5ea74318
IV		 3100 err = dma_set_coherent_mask(&pdev->dev,
3101 DMA_BIT_MASK(32));
8b230ed8
RM		 3102 if (err)
3103 goto release_regions;
3104 }
3105 *using_dac = 0;
3106 }
3107 pci_set_master(pdev);
3108 return 0;
3109
3110release_regions:
3111 pci_release_regions(pdev);
3112disable_device:
3113 pci_disable_device(pdev);
3114
3115 return err;
3116}
3117
3118static void
3119bnad_pci_uninit(struct pci_dev *pdev)
3120{
3121 pci_release_regions(pdev);
3122 pci_disable_device(pdev);
3123}
3124
3125static int __devinit
3126bnad_pci_probe(struct pci_dev *pdev,
3127 const struct pci_device_id *pcidev_id)
3128{
0120b99c
RM		 3129 bool using_dac = false;
3130 int err;
8b230ed8
RM		 3131 struct bnad *bnad;
3132 struct bna *bna;
3133 struct net_device *netdev;
3134 struct bfa_pcidev pcidev_info;
3135 unsigned long flags;
3136
3137 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3138 pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3139
3140 mutex_lock(&bnad_fwimg_mutex);
3141 if (!cna_get_firmware_buf(pdev)) {
3142 mutex_unlock(&bnad_fwimg_mutex);
3143 pr_warn("Failed to load Firmware Image!\n");
3144 return -ENODEV;
3145 }
3146 mutex_unlock(&bnad_fwimg_mutex);
3147
3148 /*
3149 * Allocates sizeof(struct net_device + struct bnad)
3150 * bnad = netdev->priv
3151 */
3152 netdev = alloc_etherdev(sizeof(struct bnad));
3153 if (!netdev) {
078086f3 3154 dev_err(&pdev->dev, "netdev allocation failed\n");
8b230ed8
RM		 3155 err = -ENOMEM;
3156 return err;
3157 }
3158 bnad = netdev_priv(netdev);
3159
078086f3
RM		 3160 bnad_lock_init(bnad);
3161
3162 mutex_lock(&bnad->conf_mutex);
8b230ed8
RM		 3163 /*
3164 * PCI initialization
0120b99c 3165 * Output : using_dac = 1 for 64 bit DMA
be7fa326 3166 * = 0 for 32 bit DMA
8b230ed8
RM		 3167 */
3168 err = bnad_pci_init(bnad, pdev, &using_dac);
3169 if (err)
44861f44 3170 goto unlock_mutex;
8b230ed8 3171
8b230ed8
RM		 3172 /*
3173 * Initialize bnad structure
3174 * Setup relation between pci_dev & netdev
3175 * Init Tx free tasklet
3176 */
3177 err = bnad_init(bnad, pdev, netdev);
3178 if (err)
3179 goto pci_uninit;
078086f3 3180
8b230ed8
RM		 3181 /* Initialize netdev structure, set up ethtool ops */
3182 bnad_netdev_init(bnad, using_dac);
3183
815f41e7
RM		 3184 /* Set link to down state */
3185 netif_carrier_off(netdev);
3186
8b230ed8 3187 /* Get resource requirement form bna */
078086f3 3188 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 3189 bna_res_req(&bnad->res_info[0]);
078086f3 3190 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 3191
3192 /* Allocate resources from bna */
078086f3 3193 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
8b230ed8 3194 if (err)
078086f3 3195 goto drv_uninit;
8b230ed8
RM		 3196
3197 bna = &bnad->bna;
3198
3199 /* Setup pcidev_info for bna_init() */
3200 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3201 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3202 pcidev_info.device_id = bnad->pcidev->device;
3203 pcidev_info.pci_bar_kva = bnad->bar0;
3204
8b230ed8
RM		 3205 spin_lock_irqsave(&bnad->bna_lock, flags);
3206 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
8b230ed8
RM		 3207 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3208
3209 bnad->stats.bna_stats = &bna->stats;
3210
078086f3
RM		 3211 bnad_enable_msix(bnad);
3212 err = bnad_mbox_irq_alloc(bnad);
3213 if (err)
3214 goto res_free;
3215
3216
8b230ed8 3217 /* Set up timers */
078086f3 3218 setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
8b230ed8 3219 ((unsigned long)bnad));
078086f3 3220 setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
8b230ed8 3221 ((unsigned long)bnad));
078086f3 3222 setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
1d32f769 3223 ((unsigned long)bnad));
078086f3 3224 setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
8b230ed8
RM		 3225 ((unsigned long)bnad));
3226
3227 /* Now start the timer before calling IOC */
078086f3 3228 mod_timer(&bnad->bna.ioceth.ioc.iocpf_timer,
8b230ed8
RM		 3229 jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
3230
3231 /*
3232 * Start the chip
078086f3
RM		 3233 * If the call back comes with error, we bail out.
3234 * This is a catastrophic error.
8b230ed8 3235 */
078086f3
RM		 3236 err = bnad_ioceth_enable(bnad);
3237 if (err) {
3238 pr_err("BNA: Initialization failed err=%d\n",
3239 err);
3240 goto probe_success;
3241 }
3242
3243 spin_lock_irqsave(&bnad->bna_lock, flags);
3244 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3245 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) {
3246 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1,
3247 bna_attr(bna)->num_rxp - 1);
3248 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3249 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1))
3250 err = -EIO;
3251 }
3252 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]);
3253 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3254
3255 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
0caa9aae
RM		 3256 if (err) {
3257 err = -EIO;
078086f3 3258 goto disable_ioceth;
0caa9aae 3259 }
078086f3
RM		 3260
3261 spin_lock_irqsave(&bnad->bna_lock, flags);
3262 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]);
3263 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 3264
3265 /* Get the burnt-in mac */
3266 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 3267 bna_enet_perm_mac_get(&bna->enet, &bnad->perm_addr);
8b230ed8
RM		 3268 bnad_set_netdev_perm_addr(bnad);
3269 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3270
0caa9aae
RM		 3271 mutex_unlock(&bnad->conf_mutex);
3272
8b230ed8
RM		 3273 /* Finally, reguister with net_device layer */
3274 err = register_netdev(netdev);
3275 if (err) {
3276 pr_err("BNA : Registering with netdev failed\n");
078086f3 3277 goto probe_uninit;
8b230ed8 3278 }
078086f3 3279 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
8b230ed8 3280
0caa9aae
RM		 3281 return 0;
3282
078086f3
RM		 3283probe_success:
3284 mutex_unlock(&bnad->conf_mutex);
8b230ed8
RM		 3285 return 0;
3286
078086f3
RM		 3287probe_uninit:
3288 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3289disable_ioceth:
3290 bnad_ioceth_disable(bnad);
3291 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3292 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3293 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
8b230ed8
RM		 3294 spin_lock_irqsave(&bnad->bna_lock, flags);
3295 bna_uninit(bna);
3296 spin_unlock_irqrestore(&bnad->bna_lock, flags);
078086f3 3297 bnad_mbox_irq_free(bnad);
8b230ed8 3298 bnad_disable_msix(bnad);
078086f3
RM		 3299res_free:
3300 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3301drv_uninit:
3302 bnad_uninit(bnad);
8b230ed8
RM		 3303pci_uninit:
3304 bnad_pci_uninit(pdev);
44861f44 3305unlock_mutex:
078086f3 3306 mutex_unlock(&bnad->conf_mutex);
8b230ed8 3307 bnad_lock_uninit(bnad);
8b230ed8
RM		 3308 free_netdev(netdev);
3309 return err;
3310}
3311
3312static void __devexit
3313bnad_pci_remove(struct pci_dev *pdev)
3314{
3315 struct net_device *netdev = pci_get_drvdata(pdev);
3316 struct bnad *bnad;
3317 struct bna *bna;
3318 unsigned long flags;
3319
3320 if (!netdev)
3321 return;
3322
3323 pr_info("%s bnad_pci_remove\n", netdev->name);
3324 bnad = netdev_priv(netdev);
3325 bna = &bnad->bna;
3326
078086f3
RM		 3327 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags))
3328 unregister_netdev(netdev);
8b230ed8
RM		 3329
3330 mutex_lock(&bnad->conf_mutex);
078086f3
RM		 3331 bnad_ioceth_disable(bnad);
3332 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3333 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3334 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
8b230ed8
RM		 3335 spin_lock_irqsave(&bnad->bna_lock, flags);
3336 bna_uninit(bna);
3337 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 3338
078086f3
RM		 3339 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3340 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3341 bnad_mbox_irq_free(bnad);
8b230ed8
RM		 3342 bnad_disable_msix(bnad);
3343 bnad_pci_uninit(pdev);
078086f3 3344 mutex_unlock(&bnad->conf_mutex);
8b230ed8
RM		 3345 bnad_lock_uninit(bnad);
3346 bnad_uninit(bnad);
3347 free_netdev(netdev);
3348}
3349
0120b99c 3350static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table) = {
8b230ed8
RM		 3351 {
3352 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3353 PCI_DEVICE_ID_BROCADE_CT),
3354 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3355 .class_mask = 0xffff00
3356 }, {0, }
3357};
3358
3359MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3360
3361static struct pci_driver bnad_pci_driver = {
3362 .name = BNAD_NAME,
3363 .id_table = bnad_pci_id_table,
3364 .probe = bnad_pci_probe,
3365 .remove = __devexit_p(bnad_pci_remove),
3366};
3367
3368static int __init
3369bnad_module_init(void)
3370{
3371 int err;
3372
5aad0011
RM		 3373 pr_info("Brocade 10G Ethernet driver - version: %s\n",
3374 BNAD_VERSION);
8b230ed8 3375
8a891429 3376 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
8b230ed8
RM		 3377
3378 err = pci_register_driver(&bnad_pci_driver);
3379 if (err < 0) {
3380 pr_err("bna : PCI registration failed in module init "
3381 "(%d)\n", err);
3382 return err;
3383 }
3384
3385 return 0;
3386}
3387
3388static void __exit
3389bnad_module_exit(void)
3390{
3391 pci_unregister_driver(&bnad_pci_driver);
3392
3393 if (bfi_fw)
3394 release_firmware(bfi_fw);
3395}
3396
3397module_init(bnad_module_init);
3398module_exit(bnad_module_exit);
3399
3400MODULE_AUTHOR("Brocade");
3401MODULE_LICENSE("GPL");
3402MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3403MODULE_VERSION(BNAD_VERSION);
3404MODULE_FIRMWARE(CNA_FW_FILE_CT);
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