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bna: Interrupt Polling and NAPI Init Changes
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / brocade / bna / bnad.c
CommitLineData
8b230ed8
RM		 1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
f859d7cb 18#include <linux/bitops.h>
8b230ed8
RM		 19#include <linux/netdevice.h>
20#include <linux/skbuff.h>
21#include <linux/etherdevice.h>
22#include <linux/in.h>
23#include <linux/ethtool.h>
24#include <linux/if_vlan.h>
25#include <linux/if_ether.h>
26#include <linux/ip.h>
70c71606 27#include <linux/prefetch.h>
8b230ed8
RM		 28
29#include "bnad.h"
30#include "bna.h"
31#include "cna.h"
32
b7ee31c5 33static DEFINE_MUTEX(bnad_fwimg_mutex);
8b230ed8
RM		 34
35/*
36 * Module params
37 */
38static uint bnad_msix_disable;
39module_param(bnad_msix_disable, uint, 0444);
40MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
41
42static uint bnad_ioc_auto_recover = 1;
43module_param(bnad_ioc_auto_recover, uint, 0444);
44MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
45
46/*
47 * Global variables
48 */
49u32 bnad_rxqs_per_cq = 2;
50
b7ee31c5 51static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
8b230ed8
RM		 52
53/*
54 * Local MACROS
55 */
56#define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
57
58#define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
59
60#define BNAD_GET_MBOX_IRQ(_bnad) \
61 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
8811e267 62 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
8b230ed8
RM		 63 ((_bnad)->pcidev->irq))
64
65#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
66do { \
67 (_res_info)->res_type = BNA_RES_T_MEM; \
68 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
69 (_res_info)->res_u.mem_info.num = (_num); \
70 (_res_info)->res_u.mem_info.len = \
71 sizeof(struct bnad_unmap_q) + \
72 (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
73} while (0)
74
be7fa326
RM		 75#define BNAD_TXRX_SYNC_MDELAY 250 /* 250 msecs */
76
8b230ed8
RM		 77/*
78 * Reinitialize completions in CQ, once Rx is taken down
79 */
80static void
81bnad_cq_cmpl_init(struct bnad *bnad, struct bna_ccb *ccb)
82{
83 struct bna_cq_entry *cmpl, *next_cmpl;
84 unsigned int wi_range, wis = 0, ccb_prod = 0;
85 int i;
86
87 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, cmpl,
88 wi_range);
89
90 for (i = 0; i < ccb->q_depth; i++) {
91 wis++;
92 if (likely(--wi_range))
93 next_cmpl = cmpl + 1;
94 else {
95 BNA_QE_INDX_ADD(ccb_prod, wis, ccb->q_depth);
96 wis = 0;
97 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt,
98 next_cmpl, wi_range);
99 }
100 cmpl->valid = 0;
101 cmpl = next_cmpl;
102 }
103}
104
105/*
106 * Frees all pending Tx Bufs
107 * At this point no activity is expected on the Q,
108 * so DMA unmap & freeing is fine.
109 */
110static void
111bnad_free_all_txbufs(struct bnad *bnad,
112 struct bna_tcb *tcb)
113{
0120b99c 114 u32 unmap_cons;
8b230ed8
RM		 115 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
116 struct bnad_skb_unmap *unmap_array;
0120b99c 117 struct sk_buff *skb = NULL;
8b230ed8
RM		 118 int i;
119
120 unmap_array = unmap_q->unmap_array;
121
122 unmap_cons = 0;
123 while (unmap_cons < unmap_q->q_depth) {
124 skb = unmap_array[unmap_cons].skb;
125 if (!skb) {
126 unmap_cons++;
127 continue;
128 }
129 unmap_array[unmap_cons].skb = NULL;
130
5ea74318
IV		 131 dma_unmap_single(&bnad->pcidev->dev,
132 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8 133 dma_addr), skb_headlen(skb),
5ea74318 134 DMA_TO_DEVICE);
8b230ed8 135
5ea74318 136 dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
be7fa326
RM		 137 if (++unmap_cons >= unmap_q->q_depth)
138 break;
139
8b230ed8 140 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5ea74318
IV		 141 dma_unmap_page(&bnad->pcidev->dev,
142 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8
RM		 143 dma_addr),
144 skb_shinfo(skb)->frags[i].size,
5ea74318
IV		 145 DMA_TO_DEVICE);
146 dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
8b230ed8 147 0);
be7fa326
RM		 148 if (++unmap_cons >= unmap_q->q_depth)
149 break;
8b230ed8
RM		 150 }
151 dev_kfree_skb_any(skb);
152 }
153}
154
155/* Data Path Handlers */
156
157/*
158 * bnad_free_txbufs : Frees the Tx bufs on Tx completion
159 * Can be called in a) Interrupt context
160 * b) Sending context
161 * c) Tasklet context
162 */
163static u32
164bnad_free_txbufs(struct bnad *bnad,
165 struct bna_tcb *tcb)
166{
0120b99c
RM		 167 u32 sent_packets = 0, sent_bytes = 0;
168 u16 wis, unmap_cons, updated_hw_cons;
8b230ed8
RM		 169 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
170 struct bnad_skb_unmap *unmap_array;
0120b99c 171 struct sk_buff *skb;
8b230ed8
RM		 172 int i;
173
174 /*
175 * Just return if TX is stopped. This check is useful
176 * when bnad_free_txbufs() runs out of a tasklet scheduled
be7fa326 177 * before bnad_cb_tx_cleanup() cleared BNAD_TXQ_TX_STARTED bit
8b230ed8
RM		 178 * but this routine runs actually after the cleanup has been
179 * executed.
180 */
be7fa326 181 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
8b230ed8
RM		 182 return 0;
183
184 updated_hw_cons = *(tcb->hw_consumer_index);
185
186 wis = BNA_Q_INDEX_CHANGE(tcb->consumer_index,
187 updated_hw_cons, tcb->q_depth);
188
189 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
190
191 unmap_array = unmap_q->unmap_array;
192 unmap_cons = unmap_q->consumer_index;
193
194 prefetch(&unmap_array[unmap_cons + 1]);
195 while (wis) {
196 skb = unmap_array[unmap_cons].skb;
197
198 unmap_array[unmap_cons].skb = NULL;
199
200 sent_packets++;
201 sent_bytes += skb->len;
202 wis -= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags);
203
5ea74318
IV		 204 dma_unmap_single(&bnad->pcidev->dev,
205 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8 206 dma_addr), skb_headlen(skb),
5ea74318
IV		 207 DMA_TO_DEVICE);
208 dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
8b230ed8
RM		 209 BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
210
211 prefetch(&unmap_array[unmap_cons + 1]);
212 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
213 prefetch(&unmap_array[unmap_cons + 1]);
214
5ea74318
IV		 215 dma_unmap_page(&bnad->pcidev->dev,
216 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8
RM		 217 dma_addr),
218 skb_shinfo(skb)->frags[i].size,
5ea74318
IV		 219 DMA_TO_DEVICE);
220 dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
8b230ed8
RM		 221 0);
222 BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
223 }
224 dev_kfree_skb_any(skb);
225 }
226
227 /* Update consumer pointers. */
228 tcb->consumer_index = updated_hw_cons;
229 unmap_q->consumer_index = unmap_cons;
230
231 tcb->txq->tx_packets += sent_packets;
232 tcb->txq->tx_bytes += sent_bytes;
233
234 return sent_packets;
235}
236
237/* Tx Free Tasklet function */
238/* Frees for all the tcb's in all the Tx's */
239/*
240 * Scheduled from sending context, so that
241 * the fat Tx lock is not held for too long
242 * in the sending context.
243 */
244static void
245bnad_tx_free_tasklet(unsigned long bnad_ptr)
246{
247 struct bnad *bnad = (struct bnad *)bnad_ptr;
248 struct bna_tcb *tcb;
0120b99c 249 u32 acked = 0;
8b230ed8
RM		 250 int i, j;
251
252 for (i = 0; i < bnad->num_tx; i++) {
253 for (j = 0; j < bnad->num_txq_per_tx; j++) {
254 tcb = bnad->tx_info[i].tcb[j];
255 if (!tcb)
256 continue;
257 if (((u16) (*tcb->hw_consumer_index) !=
258 tcb->consumer_index) &&
259 (!test_and_set_bit(BNAD_TXQ_FREE_SENT,
260 &tcb->flags))) {
261 acked = bnad_free_txbufs(bnad, tcb);
be7fa326
RM		 262 if (likely(test_bit(BNAD_TXQ_TX_STARTED,
263 &tcb->flags)))
264 bna_ib_ack(tcb->i_dbell, acked);
8b230ed8
RM		 265 smp_mb__before_clear_bit();
266 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
267 }
f7c0fa4c
RM		 268 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED,
269 &tcb->flags)))
270 continue;
271 if (netif_queue_stopped(bnad->netdev)) {
272 if (acked && netif_carrier_ok(bnad->netdev) &&
273 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
274 BNAD_NETIF_WAKE_THRESHOLD) {
275 netif_wake_queue(bnad->netdev);
276 /* TODO */
277 /* Counters for individual TxQs? */
278 BNAD_UPDATE_CTR(bnad,
279 netif_queue_wakeup);
280 }
281 }
8b230ed8
RM		 282 }
283 }
284}
285
286static u32
287bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
288{
289 struct net_device *netdev = bnad->netdev;
be7fa326 290 u32 sent = 0;
8b230ed8
RM		 291
292 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
293 return 0;
294
295 sent = bnad_free_txbufs(bnad, tcb);
296 if (sent) {
297 if (netif_queue_stopped(netdev) &&
298 netif_carrier_ok(netdev) &&
299 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
300 BNAD_NETIF_WAKE_THRESHOLD) {
be7fa326
RM		 301 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
302 netif_wake_queue(netdev);
303 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
304 }
8b230ed8 305 }
be7fa326
RM		 306 }
307
308 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
8b230ed8 309 bna_ib_ack(tcb->i_dbell, sent);
8b230ed8
RM		 310
311 smp_mb__before_clear_bit();
312 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
313
314 return sent;
315}
316
317/* MSIX Tx Completion Handler */
318static irqreturn_t
319bnad_msix_tx(int irq, void *data)
320{
321 struct bna_tcb *tcb = (struct bna_tcb *)data;
322 struct bnad *bnad = tcb->bnad;
323
324 bnad_tx(bnad, tcb);
325
326 return IRQ_HANDLED;
327}
328
329static void
330bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb)
331{
332 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
333
334 rcb->producer_index = 0;
335 rcb->consumer_index = 0;
336
337 unmap_q->producer_index = 0;
338 unmap_q->consumer_index = 0;
339}
340
341static void
be7fa326 342bnad_free_all_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
8b230ed8
RM		 343{
344 struct bnad_unmap_q *unmap_q;
5ea74318 345 struct bnad_skb_unmap *unmap_array;
8b230ed8 346 struct sk_buff *skb;
be7fa326 347 int unmap_cons;
8b230ed8
RM		 348
349 unmap_q = rcb->unmap_q;
5ea74318 350 unmap_array = unmap_q->unmap_array;
be7fa326 351 for (unmap_cons = 0; unmap_cons < unmap_q->q_depth; unmap_cons++) {
5ea74318 352 skb = unmap_array[unmap_cons].skb;
be7fa326
RM		 353 if (!skb)
354 continue;
5ea74318
IV		 355 unmap_array[unmap_cons].skb = NULL;
356 dma_unmap_single(&bnad->pcidev->dev,
357 dma_unmap_addr(&unmap_array[unmap_cons],
358 dma_addr),
359 rcb->rxq->buffer_size,
360 DMA_FROM_DEVICE);
8b230ed8 361 dev_kfree_skb(skb);
8b230ed8 362 }
8b230ed8
RM		 363 bnad_reset_rcb(bnad, rcb);
364}
365
366static void
367bnad_alloc_n_post_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
368{
369 u16 to_alloc, alloced, unmap_prod, wi_range;
370 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
371 struct bnad_skb_unmap *unmap_array;
372 struct bna_rxq_entry *rxent;
373 struct sk_buff *skb;
374 dma_addr_t dma_addr;
375
376 alloced = 0;
377 to_alloc =
378 BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth);
379
380 unmap_array = unmap_q->unmap_array;
381 unmap_prod = unmap_q->producer_index;
382
383 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, wi_range);
384
385 while (to_alloc--) {
386 if (!wi_range) {
387 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent,
388 wi_range);
389 }
0a0e2344
ED		 390 skb = netdev_alloc_skb_ip_align(bnad->netdev,
391 rcb->rxq->buffer_size);
8b230ed8
RM		 392 if (unlikely(!skb)) {
393 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
394 goto finishing;
395 }
8b230ed8 396 unmap_array[unmap_prod].skb = skb;
5ea74318
IV		 397 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
398 rcb->rxq->buffer_size,
399 DMA_FROM_DEVICE);
400 dma_unmap_addr_set(&unmap_array[unmap_prod], dma_addr,
8b230ed8
RM		 401 dma_addr);
402 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
403 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
404
405 rxent++;
406 wi_range--;
407 alloced++;
408 }
409
410finishing:
411 if (likely(alloced)) {
412 unmap_q->producer_index = unmap_prod;
413 rcb->producer_index = unmap_prod;
414 smp_mb();
be7fa326
RM		 415 if (likely(test_bit(BNAD_RXQ_STARTED, &rcb->flags)))
416 bna_rxq_prod_indx_doorbell(rcb);
8b230ed8 417 }
8b230ed8
RM		 418}
419
420static inline void
421bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb)
422{
423 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
424
425 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
426 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
427 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
428 bnad_alloc_n_post_rxbufs(bnad, rcb);
429 smp_mb__before_clear_bit();
430 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
431 }
432}
433
434static u32
435bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget)
436{
437 struct bna_cq_entry *cmpl, *next_cmpl;
438 struct bna_rcb *rcb = NULL;
439 unsigned int wi_range, packets = 0, wis = 0;
440 struct bnad_unmap_q *unmap_q;
5ea74318 441 struct bnad_skb_unmap *unmap_array;
8b230ed8 442 struct sk_buff *skb;
5ea74318 443 u32 flags, unmap_cons;
8b230ed8 444 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
078086f3
RM		 445 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
446
447 set_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags);
8b230ed8 448
078086f3
RM		 449 if (!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)) {
450 clear_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags);
be7fa326 451 return 0;
078086f3 452 }
be7fa326 453
8b230ed8
RM		 454 prefetch(bnad->netdev);
455 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
456 wi_range);
457 BUG_ON(!(wi_range <= ccb->q_depth));
458 while (cmpl->valid && packets < budget) {
459 packets++;
460 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
461
078086f3 462 if (bna_is_small_rxq(cmpl->rxq_id))
8b230ed8 463 rcb = ccb->rcb[1];
078086f3
RM		 464 else
465 rcb = ccb->rcb[0];
8b230ed8
RM		 466
467 unmap_q = rcb->unmap_q;
5ea74318
IV		 468 unmap_array = unmap_q->unmap_array;
469 unmap_cons = unmap_q->consumer_index;
8b230ed8 470
5ea74318 471 skb = unmap_array[unmap_cons].skb;
8b230ed8 472 BUG_ON(!(skb));
5ea74318
IV		 473 unmap_array[unmap_cons].skb = NULL;
474 dma_unmap_single(&bnad->pcidev->dev,
475 dma_unmap_addr(&unmap_array[unmap_cons],
8b230ed8 476 dma_addr),
5ea74318
IV		 477 rcb->rxq->buffer_size,
478 DMA_FROM_DEVICE);
8b230ed8
RM		 479 BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
480
481 /* Should be more efficient ? Performance ? */
482 BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
483
484 wis++;
485 if (likely(--wi_range))
486 next_cmpl = cmpl + 1;
487 else {
488 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
489 wis = 0;
490 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt,
491 next_cmpl, wi_range);
492 BUG_ON(!(wi_range <= ccb->q_depth));
493 }
494 prefetch(next_cmpl);
495
496 flags = ntohl(cmpl->flags);
497 if (unlikely
498 (flags &
499 (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR |
500 BNA_CQ_EF_TOO_LONG))) {
501 dev_kfree_skb_any(skb);
502 rcb->rxq->rx_packets_with_error++;
503 goto next;
504 }
505
506 skb_put(skb, ntohs(cmpl->length));
507 if (likely
e5ee20e7 508 ((bnad->netdev->features & NETIF_F_RXCSUM) &&
8b230ed8
RM		 509 (((flags & BNA_CQ_EF_IPV4) &&
510 (flags & BNA_CQ_EF_L3_CKSUM_OK)) ||
511 (flags & BNA_CQ_EF_IPV6)) &&
512 (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) &&
513 (flags & BNA_CQ_EF_L4_CKSUM_OK)))
514 skb->ip_summed = CHECKSUM_UNNECESSARY;
515 else
bc8acf2c 516 skb_checksum_none_assert(skb);
8b230ed8
RM		 517
518 rcb->rxq->rx_packets++;
519 rcb->rxq->rx_bytes += skb->len;
520 skb->protocol = eth_type_trans(skb, bnad->netdev);
521
f859d7cb
JP		 522 if (flags & BNA_CQ_EF_VLAN)
523 __vlan_hwaccel_put_tag(skb, ntohs(cmpl->vlan_tag));
524
078086f3 525 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
f859d7cb 526 napi_gro_receive(&rx_ctrl->napi, skb);
078086f3 527 else {
f859d7cb 528 netif_receive_skb(skb);
8b230ed8
RM		 529 }
530
531next:
532 cmpl->valid = 0;
533 cmpl = next_cmpl;
534 }
535
536 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
537
2be67144
RM		 538 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
539 bna_ib_ack(ccb->i_dbell, packets);
540 bnad_refill_rxq(bnad, ccb->rcb[0]);
541 if (ccb->rcb[1])
542 bnad_refill_rxq(bnad, ccb->rcb[1]);
8b230ed8 543
078086f3
RM		 544 clear_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags);
545
8b230ed8
RM		 546 return packets;
547}
548
549static void
550bnad_disable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
551{
be7fa326
RM		 552 if (unlikely(!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
553 return;
554
8b230ed8
RM		 555 bna_ib_coalescing_timer_set(ccb->i_dbell, 0);
556 bna_ib_ack(ccb->i_dbell, 0);
557}
558
559static void
560bnad_enable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
561{
e2fa6f2e
RM		 562 unsigned long flags;
563
aad75b66
RM		 564 /* Because of polling context */
565 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 566 bnad_enable_rx_irq_unsafe(ccb);
e2fa6f2e 567 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 568}
569
570static void
571bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
572{
573 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
be7fa326
RM		 574 struct napi_struct *napi = &rx_ctrl->napi;
575
576 if (likely(napi_schedule_prep(napi))) {
8b230ed8 577 bnad_disable_rx_irq(bnad, ccb);
be7fa326 578 __napi_schedule(napi);
8b230ed8
RM		 579 }
580 BNAD_UPDATE_CTR(bnad, netif_rx_schedule);
581}
582
583/* MSIX Rx Path Handler */
584static irqreturn_t
585bnad_msix_rx(int irq, void *data)
586{
587 struct bna_ccb *ccb = (struct bna_ccb *)data;
8b230ed8 588
2be67144
RM		 589 if (ccb)
590 bnad_netif_rx_schedule_poll(ccb->bnad, ccb);
8b230ed8
RM		 591
592 return IRQ_HANDLED;
593}
594
595/* Interrupt handlers */
596
597/* Mbox Interrupt Handlers */
598static irqreturn_t
599bnad_msix_mbox_handler(int irq, void *data)
600{
601 u32 intr_status;
e2fa6f2e 602 unsigned long flags;
be7fa326 603 struct bnad *bnad = (struct bnad *)data;
8b230ed8 604
be7fa326
RM		 605 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
606 return IRQ_HANDLED;
8b230ed8 607
8b230ed8
RM		 608 spin_lock_irqsave(&bnad->bna_lock, flags);
609
610 bna_intr_status_get(&bnad->bna, intr_status);
611
078086f3 612 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
8b230ed8
RM		 613 bna_mbox_handler(&bnad->bna, intr_status);
614
615 spin_unlock_irqrestore(&bnad->bna_lock, flags);
616
8b230ed8
RM		 617 return IRQ_HANDLED;
618}
619
620static irqreturn_t
621bnad_isr(int irq, void *data)
622{
623 int i, j;
624 u32 intr_status;
625 unsigned long flags;
be7fa326 626 struct bnad *bnad = (struct bnad *)data;
8b230ed8
RM		 627 struct bnad_rx_info *rx_info;
628 struct bnad_rx_ctrl *rx_ctrl;
078086f3 629 struct bna_tcb *tcb = NULL;
8b230ed8 630
e2fa6f2e
RM		 631 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
632 return IRQ_NONE;
8b230ed8
RM		 633
634 bna_intr_status_get(&bnad->bna, intr_status);
e2fa6f2e
RM		 635
636 if (unlikely(!intr_status))
8b230ed8 637 return IRQ_NONE;
e2fa6f2e
RM		 638
639 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 640
078086f3 641 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
8b230ed8 642 bna_mbox_handler(&bnad->bna, intr_status);
be7fa326 643
8b230ed8
RM		 644 spin_unlock_irqrestore(&bnad->bna_lock, flags);
645
be7fa326
RM		 646 if (!BNA_IS_INTX_DATA_INTR(intr_status))
647 return IRQ_HANDLED;
648
8b230ed8 649 /* Process data interrupts */
be7fa326
RM		 650 /* Tx processing */
651 for (i = 0; i < bnad->num_tx; i++) {
078086f3
RM		 652 for (j = 0; j < bnad->num_txq_per_tx; j++) {
653 tcb = bnad->tx_info[i].tcb[j];
654 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
655 bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
656 }
be7fa326
RM		 657 }
658 /* Rx processing */
8b230ed8
RM		 659 for (i = 0; i < bnad->num_rx; i++) {
660 rx_info = &bnad->rx_info[i];
661 if (!rx_info->rx)
662 continue;
663 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
664 rx_ctrl = &rx_info->rx_ctrl[j];
665 if (rx_ctrl->ccb)
666 bnad_netif_rx_schedule_poll(bnad,
667 rx_ctrl->ccb);
668 }
669 }
8b230ed8
RM		 670 return IRQ_HANDLED;
671}
672
673/*
674 * Called in interrupt / callback context
675 * with bna_lock held, so cfg_flags access is OK
676 */
677static void
678bnad_enable_mbox_irq(struct bnad *bnad)
679{
be7fa326 680 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
e2fa6f2e 681
8b230ed8
RM		 682 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
683}
684
685/*
686 * Called with bnad->bna_lock held b'cos of
687 * bnad->cfg_flags access.
688 */
b7ee31c5 689static void
8b230ed8
RM		 690bnad_disable_mbox_irq(struct bnad *bnad)
691{
be7fa326 692 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
8b230ed8 693
be7fa326
RM		 694 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
695}
8b230ed8 696
be7fa326
RM		 697static void
698bnad_set_netdev_perm_addr(struct bnad *bnad)
699{
700 struct net_device *netdev = bnad->netdev;
e2fa6f2e 701
be7fa326
RM		 702 memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
703 if (is_zero_ether_addr(netdev->dev_addr))
704 memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
8b230ed8
RM		 705}
706
707/* Control Path Handlers */
708
709/* Callbacks */
710void
078086f3 711bnad_cb_mbox_intr_enable(struct bnad *bnad)
8b230ed8
RM		 712{
713 bnad_enable_mbox_irq(bnad);
714}
715
716void
078086f3 717bnad_cb_mbox_intr_disable(struct bnad *bnad)
8b230ed8
RM		 718{
719 bnad_disable_mbox_irq(bnad);
720}
721
722void
078086f3
RM		 723bnad_cb_ioceth_ready(struct bnad *bnad)
724{
725 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
726 complete(&bnad->bnad_completions.ioc_comp);
727}
728
729void
730bnad_cb_ioceth_failed(struct bnad *bnad)
8b230ed8 731{
078086f3 732 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL;
8b230ed8 733 complete(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 734}
735
736void
078086f3 737bnad_cb_ioceth_disabled(struct bnad *bnad)
8b230ed8 738{
078086f3 739 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
8b230ed8 740 complete(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 741}
742
743static void
078086f3 744bnad_cb_enet_disabled(void *arg)
8b230ed8
RM		 745{
746 struct bnad *bnad = (struct bnad *)arg;
747
8b230ed8 748 netif_carrier_off(bnad->netdev);
078086f3 749 complete(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 750}
751
752void
078086f3 753bnad_cb_ethport_link_status(struct bnad *bnad,
8b230ed8
RM		 754 enum bna_link_status link_status)
755{
756 bool link_up = 0;
757
758 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
759
760 if (link_status == BNA_CEE_UP) {
078086f3
RM		 761 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
762 BNAD_UPDATE_CTR(bnad, cee_toggle);
8b230ed8 763 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
078086f3
RM		 764 } else {
765 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
766 BNAD_UPDATE_CTR(bnad, cee_toggle);
8b230ed8 767 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
078086f3 768 }
8b230ed8
RM		 769
770 if (link_up) {
771 if (!netif_carrier_ok(bnad->netdev)) {
078086f3
RM		 772 uint tx_id, tcb_id;
773 printk(KERN_WARNING "bna: %s link up\n",
8b230ed8
RM		 774 bnad->netdev->name);
775 netif_carrier_on(bnad->netdev);
776 BNAD_UPDATE_CTR(bnad, link_toggle);
078086f3
RM		 777 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
778 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx;
779 tcb_id++) {
780 struct bna_tcb *tcb =
781 bnad->tx_info[tx_id].tcb[tcb_id];
782 u32 txq_id;
783 if (!tcb)
784 continue;
785
786 txq_id = tcb->id;
787
788 if (test_bit(BNAD_TXQ_TX_STARTED,
789 &tcb->flags)) {
790 /*
791 * Force an immediate
792 * Transmit Schedule */
793 printk(KERN_INFO "bna: %s %d "
794 "TXQ_STARTED\n",
795 bnad->netdev->name,
796 txq_id);
797 netif_wake_subqueue(
798 bnad->netdev,
799 txq_id);
800 BNAD_UPDATE_CTR(bnad,
801 netif_queue_wakeup);
802 } else {
803 netif_stop_subqueue(
804 bnad->netdev,
805 txq_id);
806 BNAD_UPDATE_CTR(bnad,
807 netif_queue_stop);
808 }
809 }
8b230ed8
RM		 810 }
811 }
812 } else {
813 if (netif_carrier_ok(bnad->netdev)) {
078086f3 814 printk(KERN_WARNING "bna: %s link down\n",
8b230ed8
RM		 815 bnad->netdev->name);
816 netif_carrier_off(bnad->netdev);
817 BNAD_UPDATE_CTR(bnad, link_toggle);
818 }
819 }
820}
821
822static void
078086f3 823bnad_cb_tx_disabled(void *arg, struct bna_tx *tx)
8b230ed8
RM		 824{
825 struct bnad *bnad = (struct bnad *)arg;
826
827 complete(&bnad->bnad_completions.tx_comp);
828}
829
830static void
831bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
832{
833 struct bnad_tx_info *tx_info =
834 (struct bnad_tx_info *)tcb->txq->tx->priv;
835 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
836
837 tx_info->tcb[tcb->id] = tcb;
838 unmap_q->producer_index = 0;
839 unmap_q->consumer_index = 0;
840 unmap_q->q_depth = BNAD_TX_UNMAPQ_DEPTH;
841}
842
843static void
844bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
845{
846 struct bnad_tx_info *tx_info =
847 (struct bnad_tx_info *)tcb->txq->tx->priv;
be7fa326
RM		 848 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
849
850 while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
851 cpu_relax();
852
853 bnad_free_all_txbufs(bnad, tcb);
854
855 unmap_q->producer_index = 0;
856 unmap_q->consumer_index = 0;
857
858 smp_mb__before_clear_bit();
859 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
8b230ed8
RM		 860
861 tx_info->tcb[tcb->id] = NULL;
862}
863
864static void
865bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb)
866{
867 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
868
869 unmap_q->producer_index = 0;
870 unmap_q->consumer_index = 0;
871 unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH;
872}
873
be7fa326
RM		 874static void
875bnad_cb_rcb_destroy(struct bnad *bnad, struct bna_rcb *rcb)
876{
877 bnad_free_all_rxbufs(bnad, rcb);
878}
879
8b230ed8
RM		 880static void
881bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
882{
883 struct bnad_rx_info *rx_info =
884 (struct bnad_rx_info *)ccb->cq->rx->priv;
885
886 rx_info->rx_ctrl[ccb->id].ccb = ccb;
887 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
888}
889
890static void
891bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
892{
893 struct bnad_rx_info *rx_info =
894 (struct bnad_rx_info *)ccb->cq->rx->priv;
895
896 rx_info->rx_ctrl[ccb->id].ccb = NULL;
897}
898
899static void
078086f3 900bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
8b230ed8
RM		 901{
902 struct bnad_tx_info *tx_info =
078086f3
RM		 903 (struct bnad_tx_info *)tx->priv;
904 struct bna_tcb *tcb;
905 u32 txq_id;
906 int i;
8b230ed8 907
078086f3
RM		 908 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
909 tcb = tx_info->tcb[i];
910 if (!tcb)
911 continue;
912 txq_id = tcb->id;
913 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
914 netif_stop_subqueue(bnad->netdev, txq_id);
915 printk(KERN_INFO "bna: %s %d TXQ_STOPPED\n",
916 bnad->netdev->name, txq_id);
917 }
8b230ed8
RM		 918}
919
920static void
078086f3 921bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
8b230ed8 922{
078086f3
RM		 923 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
924 struct bna_tcb *tcb;
925 struct bnad_unmap_q *unmap_q;
926 u32 txq_id;
927 int i;
8b230ed8 928
078086f3
RM		 929 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
930 tcb = tx_info->tcb[i];
931 if (!tcb)
932 continue;
933 txq_id = tcb->id;
8b230ed8 934
078086f3 935 unmap_q = tcb->unmap_q;
8b230ed8 936
078086f3
RM		 937 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
938 continue;
8b230ed8 939
078086f3
RM		 940 while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
941 cpu_relax();
8b230ed8 942
078086f3 943 bnad_free_all_txbufs(bnad, tcb);
8b230ed8 944
078086f3
RM		 945 unmap_q->producer_index = 0;
946 unmap_q->consumer_index = 0;
947
948 smp_mb__before_clear_bit();
949 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
950
951 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
952
953 if (netif_carrier_ok(bnad->netdev)) {
954 printk(KERN_INFO "bna: %s %d TXQ_STARTED\n",
955 bnad->netdev->name, txq_id);
956 netif_wake_subqueue(bnad->netdev, txq_id);
957 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
958 }
959 }
be7fa326
RM		 960
961 /*
078086f3 962 * Workaround for first ioceth enable failure & we
be7fa326
RM		 963 * get a 0 MAC address. We try to get the MAC address
964 * again here.
965 */
966 if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
078086f3 967 bna_enet_perm_mac_get(&bnad->bna.enet, &bnad->perm_addr);
be7fa326
RM		 968 bnad_set_netdev_perm_addr(bnad);
969 }
be7fa326
RM		 970}
971
972static void
078086f3 973bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
be7fa326 974{
078086f3
RM		 975 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
976 struct bna_tcb *tcb;
977 int i;
978
979 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
980 tcb = tx_info->tcb[i];
981 if (!tcb)
982 continue;
983 }
984
985 mdelay(BNAD_TXRX_SYNC_MDELAY);
986 bna_tx_cleanup_complete(tx);
8b230ed8
RM		 987}
988
989static void
078086f3 990bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 991{
078086f3
RM		 992 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
993 struct bna_ccb *ccb;
994 struct bnad_rx_ctrl *rx_ctrl;
995 int i;
996
997 mdelay(BNAD_TXRX_SYNC_MDELAY);
998
772b5235 999 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
078086f3
RM		 1000 rx_ctrl = &rx_info->rx_ctrl[i];
1001 ccb = rx_ctrl->ccb;
1002 if (!ccb)
1003 continue;
1004
1005 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
1006
1007 if (ccb->rcb[1])
1008 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
8b230ed8 1009
078086f3
RM		 1010 while (test_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags))
1011 cpu_relax();
1012 }
be7fa326 1013
078086f3 1014 bna_rx_cleanup_complete(rx);
8b230ed8
RM		 1015}
1016
1017static void
078086f3 1018bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1019{
078086f3
RM		 1020 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1021 struct bna_ccb *ccb;
1022 struct bna_rcb *rcb;
1023 struct bnad_rx_ctrl *rx_ctrl;
1024 struct bnad_unmap_q *unmap_q;
1025 int i;
1026 int j;
be7fa326 1027
772b5235 1028 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
078086f3
RM		 1029 rx_ctrl = &rx_info->rx_ctrl[i];
1030 ccb = rx_ctrl->ccb;
1031 if (!ccb)
1032 continue;
be7fa326 1033
078086f3 1034 bnad_cq_cmpl_init(bnad, ccb);
8b230ed8 1035
078086f3
RM		 1036 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
1037 rcb = ccb->rcb[j];
1038 if (!rcb)
1039 continue;
1040 bnad_free_all_rxbufs(bnad, rcb);
1041
1042 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
1043 unmap_q = rcb->unmap_q;
1044
1045 /* Now allocate & post buffers for this RCB */
1046 /* !!Allocation in callback context */
1047 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
1048 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
1049 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
1050 bnad_alloc_n_post_rxbufs(bnad, rcb);
1051 smp_mb__before_clear_bit();
1052 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
1053 }
1054 }
8b230ed8
RM		 1055 }
1056}
1057
1058static void
078086f3 1059bnad_cb_rx_disabled(void *arg, struct bna_rx *rx)
8b230ed8
RM		 1060{
1061 struct bnad *bnad = (struct bnad *)arg;
1062
1063 complete(&bnad->bnad_completions.rx_comp);
1064}
1065
1066static void
078086f3 1067bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1068{
078086f3 1069 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS;
8b230ed8
RM		 1070 complete(&bnad->bnad_completions.mcast_comp);
1071}
1072
1073void
1074bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
1075 struct bna_stats *stats)
1076{
1077 if (status == BNA_CB_SUCCESS)
1078 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
1079
1080 if (!netif_running(bnad->netdev) ||
1081 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1082 return;
1083
1084 mod_timer(&bnad->stats_timer,
1085 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1086}
1087
078086f3
RM		 1088static void
1089bnad_cb_enet_mtu_set(struct bnad *bnad)
1090{
1091 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS;
1092 complete(&bnad->bnad_completions.mtu_comp);
1093}
1094
8b230ed8
RM		 1095/* Resource allocation, free functions */
1096
1097static void
1098bnad_mem_free(struct bnad *bnad,
1099 struct bna_mem_info *mem_info)
1100{
1101 int i;
1102 dma_addr_t dma_pa;
1103
1104 if (mem_info->mdl == NULL)
1105 return;
1106
1107 for (i = 0; i < mem_info->num; i++) {
1108 if (mem_info->mdl[i].kva != NULL) {
1109 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1110 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1111 dma_pa);
5ea74318
IV		 1112 dma_free_coherent(&bnad->pcidev->dev,
1113 mem_info->mdl[i].len,
1114 mem_info->mdl[i].kva, dma_pa);
8b230ed8
RM		 1115 } else
1116 kfree(mem_info->mdl[i].kva);
1117 }
1118 }
1119 kfree(mem_info->mdl);
1120 mem_info->mdl = NULL;
1121}
1122
1123static int
1124bnad_mem_alloc(struct bnad *bnad,
1125 struct bna_mem_info *mem_info)
1126{
1127 int i;
1128 dma_addr_t dma_pa;
1129
1130 if ((mem_info->num == 0) || (mem_info->len == 0)) {
1131 mem_info->mdl = NULL;
1132 return 0;
1133 }
1134
1135 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1136 GFP_KERNEL);
1137 if (mem_info->mdl == NULL)
1138 return -ENOMEM;
1139
1140 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1141 for (i = 0; i < mem_info->num; i++) {
1142 mem_info->mdl[i].len = mem_info->len;
1143 mem_info->mdl[i].kva =
5ea74318
IV		 1144 dma_alloc_coherent(&bnad->pcidev->dev,
1145 mem_info->len, &dma_pa,
1146 GFP_KERNEL);
8b230ed8
RM		 1147
1148 if (mem_info->mdl[i].kva == NULL)
1149 goto err_return;
1150
1151 BNA_SET_DMA_ADDR(dma_pa,
1152 &(mem_info->mdl[i].dma));
1153 }
1154 } else {
1155 for (i = 0; i < mem_info->num; i++) {
1156 mem_info->mdl[i].len = mem_info->len;
1157 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1158 GFP_KERNEL);
1159 if (mem_info->mdl[i].kva == NULL)
1160 goto err_return;
1161 }
1162 }
1163
1164 return 0;
1165
1166err_return:
1167 bnad_mem_free(bnad, mem_info);
1168 return -ENOMEM;
1169}
1170
1171/* Free IRQ for Mailbox */
1172static void
078086f3 1173bnad_mbox_irq_free(struct bnad *bnad)
8b230ed8
RM		 1174{
1175 int irq;
1176 unsigned long flags;
1177
8b230ed8 1178 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 1179 bnad_disable_mbox_irq(bnad);
e2fa6f2e 1180 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1181
1182 irq = BNAD_GET_MBOX_IRQ(bnad);
be7fa326 1183 free_irq(irq, bnad);
8b230ed8
RM		 1184}
1185
1186/*
1187 * Allocates IRQ for Mailbox, but keep it disabled
1188 * This will be enabled once we get the mbox enable callback
1189 * from bna
1190 */
1191static int
078086f3 1192bnad_mbox_irq_alloc(struct bnad *bnad)
8b230ed8 1193{
0120b99c
RM		 1194 int err = 0;
1195 unsigned long irq_flags, flags;
8b230ed8 1196 u32 irq;
0120b99c 1197 irq_handler_t irq_handler;
8b230ed8 1198
8b230ed8
RM		 1199 spin_lock_irqsave(&bnad->bna_lock, flags);
1200 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1201 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
8811e267 1202 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
8279171a 1203 irq_flags = 0;
8b230ed8
RM		 1204 } else {
1205 irq_handler = (irq_handler_t)bnad_isr;
1206 irq = bnad->pcidev->irq;
5f77898d 1207 irq_flags = IRQF_SHARED;
8b230ed8 1208 }
8811e267 1209
8b230ed8 1210 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1211 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1212
e2fa6f2e
RM		 1213 /*
1214 * Set the Mbox IRQ disable flag, so that the IRQ handler
1215 * called from request_irq() for SHARED IRQs do not execute
1216 */
1217 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1218
be7fa326
RM		 1219 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1220
8279171a 1221 err = request_irq(irq, irq_handler, irq_flags,
be7fa326 1222 bnad->mbox_irq_name, bnad);
e2fa6f2e 1223
be7fa326 1224 return err;
8b230ed8
RM		 1225}
1226
1227static void
1228bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1229{
1230 kfree(intr_info->idl);
1231 intr_info->idl = NULL;
1232}
1233
1234/* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1235static int
1236bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
078086f3 1237 u32 txrx_id, struct bna_intr_info *intr_info)
8b230ed8
RM		 1238{
1239 int i, vector_start = 0;
1240 u32 cfg_flags;
1241 unsigned long flags;
1242
1243 spin_lock_irqsave(&bnad->bna_lock, flags);
1244 cfg_flags = bnad->cfg_flags;
1245 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1246
1247 if (cfg_flags & BNAD_CF_MSIX) {
1248 intr_info->intr_type = BNA_INTR_T_MSIX;
1249 intr_info->idl = kcalloc(intr_info->num,
1250 sizeof(struct bna_intr_descr),
1251 GFP_KERNEL);
1252 if (!intr_info->idl)
1253 return -ENOMEM;
1254
1255 switch (src) {
1256 case BNAD_INTR_TX:
8811e267 1257 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id;
8b230ed8
RM		 1258 break;
1259
1260 case BNAD_INTR_RX:
8811e267
RM		 1261 vector_start = BNAD_MAILBOX_MSIX_VECTORS +
1262 (bnad->num_tx * bnad->num_txq_per_tx) +
8b230ed8
RM		 1263 txrx_id;
1264 break;
1265
1266 default:
1267 BUG();
1268 }
1269
1270 for (i = 0; i < intr_info->num; i++)
1271 intr_info->idl[i].vector = vector_start + i;
1272 } else {
1273 intr_info->intr_type = BNA_INTR_T_INTX;
1274 intr_info->num = 1;
1275 intr_info->idl = kcalloc(intr_info->num,
1276 sizeof(struct bna_intr_descr),
1277 GFP_KERNEL);
1278 if (!intr_info->idl)
1279 return -ENOMEM;
1280
1281 switch (src) {
1282 case BNAD_INTR_TX:
8811e267 1283 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK;
8b230ed8
RM		 1284 break;
1285
1286 case BNAD_INTR_RX:
8811e267 1287 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK;
8b230ed8
RM		 1288 break;
1289 }
1290 }
1291 return 0;
1292}
1293
1294/**
1295 * NOTE: Should be called for MSIX only
1296 * Unregisters Tx MSIX vector(s) from the kernel
1297 */
1298static void
1299bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1300 int num_txqs)
1301{
1302 int i;
1303 int vector_num;
1304
1305 for (i = 0; i < num_txqs; i++) {
1306 if (tx_info->tcb[i] == NULL)
1307 continue;
1308
1309 vector_num = tx_info->tcb[i]->intr_vector;
1310 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1311 }
1312}
1313
1314/**
1315 * NOTE: Should be called for MSIX only
1316 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1317 */
1318static int
1319bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
078086f3 1320 u32 tx_id, int num_txqs)
8b230ed8
RM		 1321{
1322 int i;
1323 int err;
1324 int vector_num;
1325
1326 for (i = 0; i < num_txqs; i++) {
1327 vector_num = tx_info->tcb[i]->intr_vector;
1328 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1329 tx_id + tx_info->tcb[i]->id);
1330 err = request_irq(bnad->msix_table[vector_num].vector,
1331 (irq_handler_t)bnad_msix_tx, 0,
1332 tx_info->tcb[i]->name,
1333 tx_info->tcb[i]);
1334 if (err)
1335 goto err_return;
1336 }
1337
1338 return 0;
1339
1340err_return:
1341 if (i > 0)
1342 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1343 return -1;
1344}
1345
1346/**
1347 * NOTE: Should be called for MSIX only
1348 * Unregisters Rx MSIX vector(s) from the kernel
1349 */
1350static void
1351bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1352 int num_rxps)
1353{
1354 int i;
1355 int vector_num;
1356
1357 for (i = 0; i < num_rxps; i++) {
1358 if (rx_info->rx_ctrl[i].ccb == NULL)
1359 continue;
1360
1361 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1362 free_irq(bnad->msix_table[vector_num].vector,
1363 rx_info->rx_ctrl[i].ccb);
1364 }
1365}
1366
1367/**
1368 * NOTE: Should be called for MSIX only
1369 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1370 */
1371static int
1372bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
078086f3 1373 u32 rx_id, int num_rxps)
8b230ed8
RM		 1374{
1375 int i;
1376 int err;
1377 int vector_num;
1378
1379 for (i = 0; i < num_rxps; i++) {
1380 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1381 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1382 bnad->netdev->name,
1383 rx_id + rx_info->rx_ctrl[i].ccb->id);
1384 err = request_irq(bnad->msix_table[vector_num].vector,
1385 (irq_handler_t)bnad_msix_rx, 0,
1386 rx_info->rx_ctrl[i].ccb->name,
1387 rx_info->rx_ctrl[i].ccb);
1388 if (err)
1389 goto err_return;
1390 }
1391
1392 return 0;
1393
1394err_return:
1395 if (i > 0)
1396 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1397 return -1;
1398}
1399
1400/* Free Tx object Resources */
1401static void
1402bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1403{
1404 int i;
1405
1406 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1407 if (res_info[i].res_type == BNA_RES_T_MEM)
1408 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1409 else if (res_info[i].res_type == BNA_RES_T_INTR)
1410 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1411 }
1412}
1413
1414/* Allocates memory and interrupt resources for Tx object */
1415static int
1416bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
078086f3 1417 u32 tx_id)
8b230ed8
RM		 1418{
1419 int i, err = 0;
1420
1421 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1422 if (res_info[i].res_type == BNA_RES_T_MEM)
1423 err = bnad_mem_alloc(bnad,
1424 &res_info[i].res_u.mem_info);
1425 else if (res_info[i].res_type == BNA_RES_T_INTR)
1426 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1427 &res_info[i].res_u.intr_info);
1428 if (err)
1429 goto err_return;
1430 }
1431 return 0;
1432
1433err_return:
1434 bnad_tx_res_free(bnad, res_info);
1435 return err;
1436}
1437
1438/* Free Rx object Resources */
1439static void
1440bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1441{
1442 int i;
1443
1444 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1445 if (res_info[i].res_type == BNA_RES_T_MEM)
1446 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1447 else if (res_info[i].res_type == BNA_RES_T_INTR)
1448 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1449 }
1450}
1451
1452/* Allocates memory and interrupt resources for Rx object */
1453static int
1454bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1455 uint rx_id)
1456{
1457 int i, err = 0;
1458
1459 /* All memory needs to be allocated before setup_ccbs */
1460 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1461 if (res_info[i].res_type == BNA_RES_T_MEM)
1462 err = bnad_mem_alloc(bnad,
1463 &res_info[i].res_u.mem_info);
1464 else if (res_info[i].res_type == BNA_RES_T_INTR)
1465 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1466 &res_info[i].res_u.intr_info);
1467 if (err)
1468 goto err_return;
1469 }
1470 return 0;
1471
1472err_return:
1473 bnad_rx_res_free(bnad, res_info);
1474 return err;
1475}
1476
1477/* Timer callbacks */
1478/* a) IOC timer */
1479static void
1480bnad_ioc_timeout(unsigned long data)
1481{
1482 struct bnad *bnad = (struct bnad *)data;
1483 unsigned long flags;
1484
1485 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1486 bfa_nw_ioc_timeout((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1487 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1488}
1489
1490static void
1491bnad_ioc_hb_check(unsigned long data)
1492{
1493 struct bnad *bnad = (struct bnad *)data;
1494 unsigned long flags;
1495
1496 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1497 bfa_nw_ioc_hb_check((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1498 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1499}
1500
1501static void
1d32f769 1502bnad_iocpf_timeout(unsigned long data)
8b230ed8
RM		 1503{
1504 struct bnad *bnad = (struct bnad *)data;
1505 unsigned long flags;
1506
1507 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1508 bfa_nw_iocpf_timeout((void *) &bnad->bna.ioceth.ioc);
1d32f769
RM		 1509 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1510}
1511
1512static void
1513bnad_iocpf_sem_timeout(unsigned long data)
1514{
1515 struct bnad *bnad = (struct bnad *)data;
1516 unsigned long flags;
1517
1518 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1519 bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1520 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1521}
1522
1523/*
1524 * All timer routines use bnad->bna_lock to protect against
1525 * the following race, which may occur in case of no locking:
0120b99c 1526 * Time CPU m CPU n
8b230ed8
RM		 1527 * 0 1 = test_bit
1528 * 1 clear_bit
1529 * 2 del_timer_sync
1530 * 3 mod_timer
1531 */
1532
1533/* b) Dynamic Interrupt Moderation Timer */
1534static void
1535bnad_dim_timeout(unsigned long data)
1536{
1537 struct bnad *bnad = (struct bnad *)data;
1538 struct bnad_rx_info *rx_info;
1539 struct bnad_rx_ctrl *rx_ctrl;
1540 int i, j;
1541 unsigned long flags;
1542
1543 if (!netif_carrier_ok(bnad->netdev))
1544 return;
1545
1546 spin_lock_irqsave(&bnad->bna_lock, flags);
1547 for (i = 0; i < bnad->num_rx; i++) {
1548 rx_info = &bnad->rx_info[i];
1549 if (!rx_info->rx)
1550 continue;
1551 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1552 rx_ctrl = &rx_info->rx_ctrl[j];
1553 if (!rx_ctrl->ccb)
1554 continue;
1555 bna_rx_dim_update(rx_ctrl->ccb);
1556 }
1557 }
1558
1559 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1560 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1561 mod_timer(&bnad->dim_timer,
1562 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1563 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1564}
1565
1566/* c) Statistics Timer */
1567static void
1568bnad_stats_timeout(unsigned long data)
1569{
1570 struct bnad *bnad = (struct bnad *)data;
1571 unsigned long flags;
1572
1573 if (!netif_running(bnad->netdev) ||
1574 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1575 return;
1576
1577 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1578 bna_hw_stats_get(&bnad->bna);
8b230ed8
RM		 1579 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1580}
1581
1582/*
1583 * Set up timer for DIM
1584 * Called with bnad->bna_lock held
1585 */
1586void
1587bnad_dim_timer_start(struct bnad *bnad)
1588{
1589 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1590 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1591 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1592 (unsigned long)bnad);
1593 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1594 mod_timer(&bnad->dim_timer,
1595 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1596 }
1597}
1598
1599/*
1600 * Set up timer for statistics
1601 * Called with mutex_lock(&bnad->conf_mutex) held
1602 */
1603static void
1604bnad_stats_timer_start(struct bnad *bnad)
1605{
1606 unsigned long flags;
1607
1608 spin_lock_irqsave(&bnad->bna_lock, flags);
1609 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1610 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1611 (unsigned long)bnad);
1612 mod_timer(&bnad->stats_timer,
1613 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1614 }
1615 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1616}
1617
1618/*
1619 * Stops the stats timer
1620 * Called with mutex_lock(&bnad->conf_mutex) held
1621 */
1622static void
1623bnad_stats_timer_stop(struct bnad *bnad)
1624{
1625 int to_del = 0;
1626 unsigned long flags;
1627
1628 spin_lock_irqsave(&bnad->bna_lock, flags);
1629 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1630 to_del = 1;
1631 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1632 if (to_del)
1633 del_timer_sync(&bnad->stats_timer);
1634}
1635
1636/* Utilities */
1637
1638static void
1639bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1640{
1641 int i = 1; /* Index 0 has broadcast address */
1642 struct netdev_hw_addr *mc_addr;
1643
1644 netdev_for_each_mc_addr(mc_addr, netdev) {
1645 memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
1646 ETH_ALEN);
1647 i++;
1648 }
1649}
1650
1651static int
1652bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1653{
1654 struct bnad_rx_ctrl *rx_ctrl =
1655 container_of(napi, struct bnad_rx_ctrl, napi);
2be67144 1656 struct bnad *bnad = rx_ctrl->bnad;
8b230ed8
RM		 1657 int rcvd = 0;
1658
8b230ed8
RM		 1659
1660 if (!netif_carrier_ok(bnad->netdev))
1661 goto poll_exit;
1662
2be67144 1663 rcvd = bnad_poll_cq(bnad, rx_ctrl->ccb, budget);
8b230ed8
RM		 1664 if (rcvd == budget)
1665 return rcvd;
1666
1667poll_exit:
1668 napi_complete((napi));
1669
1670 BNAD_UPDATE_CTR(bnad, netif_rx_complete);
1671
2be67144
RM		 1672
1673 if (rx_ctrl->ccb)
1674 bnad_enable_rx_irq(bnad, rx_ctrl->ccb);
8b230ed8
RM		 1675 return rcvd;
1676}
1677
2be67144 1678#define BNAD_NAPI_POLL_QUOTA 64
8b230ed8 1679static void
2be67144 1680bnad_napi_init(struct bnad *bnad, u32 rx_id)
8b230ed8 1681{
8b230ed8
RM		 1682 struct bnad_rx_ctrl *rx_ctrl;
1683 int i;
8b230ed8
RM		 1684
1685 /* Initialize & enable NAPI */
1686 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1687 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1688 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
2be67144
RM		 1689 bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA);
1690 }
1691}
1692
1693static void
1694bnad_napi_enable(struct bnad *bnad, u32 rx_id)
1695{
1696 struct bnad_rx_ctrl *rx_ctrl;
1697 int i;
1698
1699 /* Initialize & enable NAPI */
1700 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1701 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
be7fa326 1702
8b230ed8
RM		 1703 napi_enable(&rx_ctrl->napi);
1704 }
1705}
1706
1707static void
1708bnad_napi_disable(struct bnad *bnad, u32 rx_id)
1709{
1710 int i;
1711
1712 /* First disable and then clean up */
1713 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1714 napi_disable(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1715 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1716 }
1717}
1718
1719/* Should be held with conf_lock held */
1720void
078086f3 1721bnad_cleanup_tx(struct bnad *bnad, u32 tx_id)
8b230ed8
RM		 1722{
1723 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1724 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1725 unsigned long flags;
1726
1727 if (!tx_info->tx)
1728 return;
1729
1730 init_completion(&bnad->bnad_completions.tx_comp);
1731 spin_lock_irqsave(&bnad->bna_lock, flags);
1732 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1733 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1734 wait_for_completion(&bnad->bnad_completions.tx_comp);
1735
1736 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1737 bnad_tx_msix_unregister(bnad, tx_info,
1738 bnad->num_txq_per_tx);
1739
2be67144
RM		 1740 if (0 == tx_id)
1741 tasklet_kill(&bnad->tx_free_tasklet);
1742
8b230ed8
RM		 1743 spin_lock_irqsave(&bnad->bna_lock, flags);
1744 bna_tx_destroy(tx_info->tx);
1745 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1746
1747 tx_info->tx = NULL;
078086f3 1748 tx_info->tx_id = 0;
8b230ed8 1749
8b230ed8
RM		 1750 bnad_tx_res_free(bnad, res_info);
1751}
1752
1753/* Should be held with conf_lock held */
1754int
078086f3 1755bnad_setup_tx(struct bnad *bnad, u32 tx_id)
8b230ed8
RM		 1756{
1757 int err;
1758 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1759 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1760 struct bna_intr_info *intr_info =
1761 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1762 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
1763 struct bna_tx_event_cbfn tx_cbfn;
1764 struct bna_tx *tx;
1765 unsigned long flags;
1766
078086f3
RM		 1767 tx_info->tx_id = tx_id;
1768
8b230ed8
RM		 1769 /* Initialize the Tx object configuration */
1770 tx_config->num_txq = bnad->num_txq_per_tx;
1771 tx_config->txq_depth = bnad->txq_depth;
1772 tx_config->tx_type = BNA_TX_T_REGULAR;
078086f3 1773 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo;
8b230ed8
RM		 1774
1775 /* Initialize the tx event handlers */
1776 tx_cbfn.tcb_setup_cbfn = bnad_cb_tcb_setup;
1777 tx_cbfn.tcb_destroy_cbfn = bnad_cb_tcb_destroy;
1778 tx_cbfn.tx_stall_cbfn = bnad_cb_tx_stall;
1779 tx_cbfn.tx_resume_cbfn = bnad_cb_tx_resume;
1780 tx_cbfn.tx_cleanup_cbfn = bnad_cb_tx_cleanup;
1781
1782 /* Get BNA's resource requirement for one tx object */
1783 spin_lock_irqsave(&bnad->bna_lock, flags);
1784 bna_tx_res_req(bnad->num_txq_per_tx,
1785 bnad->txq_depth, res_info);
1786 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1787
1788 /* Fill Unmap Q memory requirements */
1789 BNAD_FILL_UNMAPQ_MEM_REQ(
1790 &res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1791 bnad->num_txq_per_tx,
1792 BNAD_TX_UNMAPQ_DEPTH);
1793
1794 /* Allocate resources */
1795 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1796 if (err)
1797 return err;
1798
1799 /* Ask BNA to create one Tx object, supplying required resources */
1800 spin_lock_irqsave(&bnad->bna_lock, flags);
1801 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
1802 tx_info);
1803 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1804 if (!tx)
1805 goto err_return;
1806 tx_info->tx = tx;
1807
1808 /* Register ISR for the Tx object */
1809 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1810 err = bnad_tx_msix_register(bnad, tx_info,
1811 tx_id, bnad->num_txq_per_tx);
1812 if (err)
1813 goto err_return;
1814 }
1815
1816 spin_lock_irqsave(&bnad->bna_lock, flags);
1817 bna_tx_enable(tx);
1818 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1819
1820 return 0;
1821
1822err_return:
1823 bnad_tx_res_free(bnad, res_info);
1824 return err;
1825}
1826
1827/* Setup the rx config for bna_rx_create */
1828/* bnad decides the configuration */
1829static void
1830bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
1831{
1832 rx_config->rx_type = BNA_RX_T_REGULAR;
1833 rx_config->num_paths = bnad->num_rxp_per_rx;
078086f3 1834 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo;
8b230ed8
RM		 1835
1836 if (bnad->num_rxp_per_rx > 1) {
1837 rx_config->rss_status = BNA_STATUS_T_ENABLED;
1838 rx_config->rss_config.hash_type =
078086f3
RM		 1839 (BFI_ENET_RSS_IPV6 |
1840 BFI_ENET_RSS_IPV6_TCP |
1841 BFI_ENET_RSS_IPV4 |
1842 BFI_ENET_RSS_IPV4_TCP);
8b230ed8
RM		 1843 rx_config->rss_config.hash_mask =
1844 bnad->num_rxp_per_rx - 1;
1845 get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
1846 sizeof(rx_config->rss_config.toeplitz_hash_key));
1847 } else {
1848 rx_config->rss_status = BNA_STATUS_T_DISABLED;
1849 memset(&rx_config->rss_config, 0,
1850 sizeof(rx_config->rss_config));
1851 }
1852 rx_config->rxp_type = BNA_RXP_SLR;
1853 rx_config->q_depth = bnad->rxq_depth;
1854
1855 rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE;
1856
1857 rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED;
1858}
1859
2be67144
RM		 1860static void
1861bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id)
1862{
1863 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1864 int i;
1865
1866 for (i = 0; i < bnad->num_rxp_per_rx; i++)
1867 rx_info->rx_ctrl[i].bnad = bnad;
1868}
1869
8b230ed8
RM		 1870/* Called with mutex_lock(&bnad->conf_mutex) held */
1871void
078086f3 1872bnad_cleanup_rx(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 1873{
1874 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1875 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1876 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1877 unsigned long flags;
1878 int dim_timer_del = 0;
1879
1880 if (!rx_info->rx)
1881 return;
1882
1883 if (0 == rx_id) {
1884 spin_lock_irqsave(&bnad->bna_lock, flags);
1885 dim_timer_del = bnad_dim_timer_running(bnad);
1886 if (dim_timer_del)
1887 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1888 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1889 if (dim_timer_del)
1890 del_timer_sync(&bnad->dim_timer);
1891 }
1892
8b230ed8
RM		 1893 init_completion(&bnad->bnad_completions.rx_comp);
1894 spin_lock_irqsave(&bnad->bna_lock, flags);
1895 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
1896 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1897 wait_for_completion(&bnad->bnad_completions.rx_comp);
1898
1899 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
1900 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
1901
2be67144
RM		 1902 bnad_napi_disable(bnad, rx_id);
1903
8b230ed8
RM		 1904 spin_lock_irqsave(&bnad->bna_lock, flags);
1905 bna_rx_destroy(rx_info->rx);
1906 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1907
1908 rx_info->rx = NULL;
1909
1910 bnad_rx_res_free(bnad, res_info);
1911}
1912
1913/* Called with mutex_lock(&bnad->conf_mutex) held */
1914int
078086f3 1915bnad_setup_rx(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 1916{
1917 int err;
1918 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1919 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1920 struct bna_intr_info *intr_info =
1921 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
1922 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1923 struct bna_rx_event_cbfn rx_cbfn;
1924 struct bna_rx *rx;
1925 unsigned long flags;
1926
078086f3
RM		 1927 rx_info->rx_id = rx_id;
1928
8b230ed8
RM		 1929 /* Initialize the Rx object configuration */
1930 bnad_init_rx_config(bnad, rx_config);
1931
1932 /* Initialize the Rx event handlers */
1933 rx_cbfn.rcb_setup_cbfn = bnad_cb_rcb_setup;
be7fa326 1934 rx_cbfn.rcb_destroy_cbfn = bnad_cb_rcb_destroy;
8b230ed8
RM		 1935 rx_cbfn.ccb_setup_cbfn = bnad_cb_ccb_setup;
1936 rx_cbfn.ccb_destroy_cbfn = bnad_cb_ccb_destroy;
1937 rx_cbfn.rx_cleanup_cbfn = bnad_cb_rx_cleanup;
1938 rx_cbfn.rx_post_cbfn = bnad_cb_rx_post;
1939
1940 /* Get BNA's resource requirement for one Rx object */
1941 spin_lock_irqsave(&bnad->bna_lock, flags);
1942 bna_rx_res_req(rx_config, res_info);
1943 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1944
1945 /* Fill Unmap Q memory requirements */
1946 BNAD_FILL_UNMAPQ_MEM_REQ(
1947 &res_info[BNA_RX_RES_MEM_T_UNMAPQ],
1948 rx_config->num_paths +
1949 ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 0 :
1950 rx_config->num_paths), BNAD_RX_UNMAPQ_DEPTH);
1951
1952 /* Allocate resource */
1953 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
1954 if (err)
1955 return err;
1956
2be67144
RM		 1957 bnad_rx_ctrl_init(bnad, rx_id);
1958
8b230ed8
RM		 1959 /* Ask BNA to create one Rx object, supplying required resources */
1960 spin_lock_irqsave(&bnad->bna_lock, flags);
1961 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
1962 rx_info);
1963 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1964 if (!rx)
1965 goto err_return;
1966 rx_info->rx = rx;
1967
2be67144
RM		 1968 /*
1969 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
1970 * so that IRQ handler cannot schedule NAPI at this point.
1971 */
1972 bnad_napi_init(bnad, rx_id);
1973
8b230ed8
RM		 1974 /* Register ISR for the Rx object */
1975 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1976 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
1977 rx_config->num_paths);
1978 if (err)
1979 goto err_return;
1980 }
1981
8b230ed8
RM		 1982 spin_lock_irqsave(&bnad->bna_lock, flags);
1983 if (0 == rx_id) {
1984 /* Set up Dynamic Interrupt Moderation Vector */
1985 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
1986 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
1987
1988 /* Enable VLAN filtering only on the default Rx */
1989 bna_rx_vlanfilter_enable(rx);
1990
1991 /* Start the DIM timer */
1992 bnad_dim_timer_start(bnad);
1993 }
1994
1995 bna_rx_enable(rx);
1996 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1997
2be67144
RM		 1998 /* Enable scheduling of NAPI */
1999 bnad_napi_enable(bnad, rx_id);
2000
8b230ed8
RM		 2001 return 0;
2002
2003err_return:
2004 bnad_cleanup_rx(bnad, rx_id);
2005 return err;
2006}
2007
2008/* Called with conf_lock & bnad->bna_lock held */
2009void
2010bnad_tx_coalescing_timeo_set(struct bnad *bnad)
2011{
2012 struct bnad_tx_info *tx_info;
2013
2014 tx_info = &bnad->tx_info[0];
2015 if (!tx_info->tx)
2016 return;
2017
2018 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
2019}
2020
2021/* Called with conf_lock & bnad->bna_lock held */
2022void
2023bnad_rx_coalescing_timeo_set(struct bnad *bnad)
2024{
2025 struct bnad_rx_info *rx_info;
0120b99c 2026 int i;
8b230ed8
RM		 2027
2028 for (i = 0; i < bnad->num_rx; i++) {
2029 rx_info = &bnad->rx_info[i];
2030 if (!rx_info->rx)
2031 continue;
2032 bna_rx_coalescing_timeo_set(rx_info->rx,
2033 bnad->rx_coalescing_timeo);
2034 }
2035}
2036
2037/*
2038 * Called with bnad->bna_lock held
2039 */
2040static int
2041bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
2042{
2043 int ret;
2044
2045 if (!is_valid_ether_addr(mac_addr))
2046 return -EADDRNOTAVAIL;
2047
2048 /* If datapath is down, pretend everything went through */
2049 if (!bnad->rx_info[0].rx)
2050 return 0;
2051
2052 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
2053 if (ret != BNA_CB_SUCCESS)
2054 return -EADDRNOTAVAIL;
2055
2056 return 0;
2057}
2058
2059/* Should be called with conf_lock held */
2060static int
2061bnad_enable_default_bcast(struct bnad *bnad)
2062{
2063 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
2064 int ret;
2065 unsigned long flags;
2066
2067 init_completion(&bnad->bnad_completions.mcast_comp);
2068
2069 spin_lock_irqsave(&bnad->bna_lock, flags);
2070 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
2071 bnad_cb_rx_mcast_add);
2072 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2073
2074 if (ret == BNA_CB_SUCCESS)
2075 wait_for_completion(&bnad->bnad_completions.mcast_comp);
2076 else
2077 return -ENODEV;
2078
2079 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
2080 return -ENODEV;
2081
2082 return 0;
2083}
2084
aad75b66
RM		 2085/* Called with bnad_conf_lock() held */
2086static void
2087bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
2088{
f859d7cb 2089 u16 vid;
aad75b66
RM		 2090 unsigned long flags;
2091
078086f3 2092 BUG_ON(!(VLAN_N_VID == BFI_ENET_VLAN_ID_MAX));
aad75b66 2093
f859d7cb 2094 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) {
aad75b66 2095 spin_lock_irqsave(&bnad->bna_lock, flags);
f859d7cb 2096 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid);
aad75b66
RM		 2097 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2098 }
2099}
2100
8b230ed8
RM		 2101/* Statistics utilities */
2102void
250e061e 2103bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 2104{
8b230ed8
RM		 2105 int i, j;
2106
2107 for (i = 0; i < bnad->num_rx; i++) {
2108 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2109 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
250e061e 2110 stats->rx_packets += bnad->rx_info[i].
8b230ed8 2111 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
250e061e 2112 stats->rx_bytes += bnad->rx_info[i].
8b230ed8
RM		 2113 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2114 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2115 bnad->rx_info[i].rx_ctrl[j].ccb->
2116 rcb[1]->rxq) {
250e061e 2117 stats->rx_packets +=
8b230ed8
RM		 2118 bnad->rx_info[i].rx_ctrl[j].
2119 ccb->rcb[1]->rxq->rx_packets;
250e061e 2120 stats->rx_bytes +=
8b230ed8
RM		 2121 bnad->rx_info[i].rx_ctrl[j].
2122 ccb->rcb[1]->rxq->rx_bytes;
2123 }
2124 }
2125 }
2126 }
2127 for (i = 0; i < bnad->num_tx; i++) {
2128 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2129 if (bnad->tx_info[i].tcb[j]) {
250e061e 2130 stats->tx_packets +=
8b230ed8 2131 bnad->tx_info[i].tcb[j]->txq->tx_packets;
250e061e 2132 stats->tx_bytes +=
8b230ed8
RM		 2133 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2134 }
2135 }
2136 }
2137}
2138
2139/*
2140 * Must be called with the bna_lock held.
2141 */
2142void
250e061e 2143bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 2144{
078086f3
RM		 2145 struct bfi_enet_stats_mac *mac_stats;
2146 u32 bmap;
8b230ed8
RM		 2147 int i;
2148
078086f3 2149 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats;
250e061e 2150 stats->rx_errors =
8b230ed8
RM		 2151 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2152 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2153 mac_stats->rx_undersize;
250e061e 2154 stats->tx_errors = mac_stats->tx_fcs_error +
8b230ed8 2155 mac_stats->tx_undersize;
250e061e
ED		 2156 stats->rx_dropped = mac_stats->rx_drop;
2157 stats->tx_dropped = mac_stats->tx_drop;
2158 stats->multicast = mac_stats->rx_multicast;
2159 stats->collisions = mac_stats->tx_total_collision;
8b230ed8 2160
250e061e 2161 stats->rx_length_errors = mac_stats->rx_frame_length_error;
8b230ed8
RM		 2162
2163 /* receive ring buffer overflow ?? */
2164
250e061e
ED		 2165 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2166 stats->rx_frame_errors = mac_stats->rx_alignment_error;
8b230ed8 2167 /* recv'r fifo overrun */
078086f3
RM		 2168 bmap = bna_rx_rid_mask(&bnad->bna);
2169 for (i = 0; bmap; i++) {
8b230ed8 2170 if (bmap & 1) {
250e061e 2171 stats->rx_fifo_errors +=
8b230ed8 2172 bnad->stats.bna_stats->
078086f3 2173 hw_stats.rxf_stats[i].frame_drops;
8b230ed8
RM		 2174 break;
2175 }
2176 bmap >>= 1;
2177 }
2178}
2179
2180static void
2181bnad_mbox_irq_sync(struct bnad *bnad)
2182{
2183 u32 irq;
2184 unsigned long flags;
2185
2186 spin_lock_irqsave(&bnad->bna_lock, flags);
2187 if (bnad->cfg_flags & BNAD_CF_MSIX)
8811e267 2188 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
8b230ed8
RM		 2189 else
2190 irq = bnad->pcidev->irq;
2191 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2192
2193 synchronize_irq(irq);
2194}
2195
2196/* Utility used by bnad_start_xmit, for doing TSO */
2197static int
2198bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2199{
2200 int err;
2201
2202 /* SKB_GSO_TCPV4 and SKB_GSO_TCPV6 is defined since 2.6.18. */
2203 BUG_ON(!(skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4 ||
2204 skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6));
2205 if (skb_header_cloned(skb)) {
2206 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2207 if (err) {
2208 BNAD_UPDATE_CTR(bnad, tso_err);
2209 return err;
2210 }
2211 }
2212
2213 /*
2214 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2215 * excluding the length field.
2216 */
2217 if (skb->protocol == htons(ETH_P_IP)) {
2218 struct iphdr *iph = ip_hdr(skb);
2219
2220 /* Do we really need these? */
2221 iph->tot_len = 0;
2222 iph->check = 0;
2223
2224 tcp_hdr(skb)->check =
2225 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2226 IPPROTO_TCP, 0);
2227 BNAD_UPDATE_CTR(bnad, tso4);
2228 } else {
2229 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2230
2231 BUG_ON(!(skb->protocol == htons(ETH_P_IPV6)));
2232 ipv6h->payload_len = 0;
2233 tcp_hdr(skb)->check =
2234 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2235 IPPROTO_TCP, 0);
2236 BNAD_UPDATE_CTR(bnad, tso6);
2237 }
2238
2239 return 0;
2240}
2241
2242/*
2243 * Initialize Q numbers depending on Rx Paths
2244 * Called with bnad->bna_lock held, because of cfg_flags
2245 * access.
2246 */
2247static void
2248bnad_q_num_init(struct bnad *bnad)
2249{
2250 int rxps;
2251
2252 rxps = min((uint)num_online_cpus(),
772b5235 2253 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX));
8b230ed8
RM		 2254
2255 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2256 rxps = 1; /* INTx */
2257
2258 bnad->num_rx = 1;
2259 bnad->num_tx = 1;
2260 bnad->num_rxp_per_rx = rxps;
2261 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2262}
2263
2264/*
2265 * Adjusts the Q numbers, given a number of msix vectors
2266 * Give preference to RSS as opposed to Tx priority Queues,
2267 * in such a case, just use 1 Tx Q
2268 * Called with bnad->bna_lock held b'cos of cfg_flags access
2269 */
2270static void
078086f3 2271bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp)
8b230ed8
RM		 2272{
2273 bnad->num_txq_per_tx = 1;
2274 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2275 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2276 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2277 bnad->num_rxp_per_rx = msix_vectors -
2278 (bnad->num_tx * bnad->num_txq_per_tx) -
2279 BNAD_MAILBOX_MSIX_VECTORS;
2280 } else
2281 bnad->num_rxp_per_rx = 1;
2282}
2283
078086f3
RM		 2284/* Enable / disable ioceth */
2285static int
2286bnad_ioceth_disable(struct bnad *bnad)
8b230ed8
RM		 2287{
2288 unsigned long flags;
078086f3 2289 int err = 0;
8b230ed8
RM		 2290
2291 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2292 init_completion(&bnad->bnad_completions.ioc_comp);
2293 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP);
8b230ed8
RM		 2294 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2295
078086f3
RM		 2296 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2297 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2298
2299 err = bnad->bnad_completions.ioc_comp_status;
2300 return err;
8b230ed8
RM		 2301}
2302
2303static int
078086f3 2304bnad_ioceth_enable(struct bnad *bnad)
8b230ed8
RM		 2305{
2306 int err = 0;
2307 unsigned long flags;
2308
8b230ed8 2309 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2310 init_completion(&bnad->bnad_completions.ioc_comp);
2311 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING;
2312 bna_ioceth_enable(&bnad->bna.ioceth);
8b230ed8
RM		 2313 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2314
078086f3
RM		 2315 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2316 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
8b230ed8 2317
078086f3 2318 err = bnad->bnad_completions.ioc_comp_status;
8b230ed8
RM		 2319
2320 return err;
2321}
2322
2323/* Free BNA resources */
2324static void
078086f3
RM		 2325bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info,
2326 u32 res_val_max)
8b230ed8
RM		 2327{
2328 int i;
8b230ed8 2329
078086f3
RM		 2330 for (i = 0; i < res_val_max; i++)
2331 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
8b230ed8
RM		 2332}
2333
2334/* Allocates memory and interrupt resources for BNA */
2335static int
078086f3
RM		 2336bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
2337 u32 res_val_max)
8b230ed8
RM		 2338{
2339 int i, err;
8b230ed8 2340
078086f3
RM		 2341 for (i = 0; i < res_val_max; i++) {
2342 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
8b230ed8
RM		 2343 if (err)
2344 goto err_return;
2345 }
2346 return 0;
2347
2348err_return:
078086f3 2349 bnad_res_free(bnad, res_info, res_val_max);
8b230ed8
RM		 2350 return err;
2351}
2352
2353/* Interrupt enable / disable */
2354static void
2355bnad_enable_msix(struct bnad *bnad)
2356{
2357 int i, ret;
8b230ed8
RM		 2358 unsigned long flags;
2359
2360 spin_lock_irqsave(&bnad->bna_lock, flags);
2361 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2362 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2363 return;
2364 }
2365 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2366
2367 if (bnad->msix_table)
2368 return;
2369
8b230ed8 2370 bnad->msix_table =
b7ee31c5 2371 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
8b230ed8
RM		 2372
2373 if (!bnad->msix_table)
2374 goto intx_mode;
2375
b7ee31c5 2376 for (i = 0; i < bnad->msix_num; i++)
8b230ed8
RM		 2377 bnad->msix_table[i].entry = i;
2378
b7ee31c5 2379 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num);
8b230ed8
RM		 2380 if (ret > 0) {
2381 /* Not enough MSI-X vectors. */
2382
2383 spin_lock_irqsave(&bnad->bna_lock, flags);
2384 /* ret = #of vectors that we got */
078086f3 2385 bnad_q_num_adjust(bnad, ret, 0);
8b230ed8
RM		 2386 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2387
2388 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx)
2389 + (bnad->num_rx
2390 * bnad->num_rxp_per_rx) +
2391 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8 2392
078086f3
RM		 2393 if (bnad->msix_num > ret)
2394 goto intx_mode;
2395
8b230ed8
RM		 2396 /* Try once more with adjusted numbers */
2397 /* If this fails, fall back to INTx */
2398 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
b7ee31c5 2399 bnad->msix_num);
8b230ed8
RM		 2400 if (ret)
2401 goto intx_mode;
2402
2403 } else if (ret < 0)
2404 goto intx_mode;
078086f3
RM		 2405
2406 pci_intx(bnad->pcidev, 0);
2407
8b230ed8
RM		 2408 return;
2409
2410intx_mode:
2411
2412 kfree(bnad->msix_table);
2413 bnad->msix_table = NULL;
2414 bnad->msix_num = 0;
8b230ed8
RM		 2415 spin_lock_irqsave(&bnad->bna_lock, flags);
2416 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2417 bnad_q_num_init(bnad);
2418 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2419}
2420
2421static void
2422bnad_disable_msix(struct bnad *bnad)
2423{
2424 u32 cfg_flags;
2425 unsigned long flags;
2426
2427 spin_lock_irqsave(&bnad->bna_lock, flags);
2428 cfg_flags = bnad->cfg_flags;
2429 if (bnad->cfg_flags & BNAD_CF_MSIX)
2430 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2431 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2432
2433 if (cfg_flags & BNAD_CF_MSIX) {
2434 pci_disable_msix(bnad->pcidev);
2435 kfree(bnad->msix_table);
2436 bnad->msix_table = NULL;
2437 }
2438}
2439
2440/* Netdev entry points */
2441static int
2442bnad_open(struct net_device *netdev)
2443{
2444 int err;
2445 struct bnad *bnad = netdev_priv(netdev);
2446 struct bna_pause_config pause_config;
2447 int mtu;
2448 unsigned long flags;
2449
2450 mutex_lock(&bnad->conf_mutex);
2451
2452 /* Tx */
2453 err = bnad_setup_tx(bnad, 0);
2454 if (err)
2455 goto err_return;
2456
2457 /* Rx */
2458 err = bnad_setup_rx(bnad, 0);
2459 if (err)
2460 goto cleanup_tx;
2461
2462 /* Port */
2463 pause_config.tx_pause = 0;
2464 pause_config.rx_pause = 0;
2465
078086f3 2466 mtu = ETH_HLEN + VLAN_HLEN + bnad->netdev->mtu + ETH_FCS_LEN;
8b230ed8
RM		 2467
2468 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2469 bna_enet_mtu_set(&bnad->bna.enet, mtu, NULL);
2470 bna_enet_pause_config(&bnad->bna.enet, &pause_config, NULL);
2471 bna_enet_enable(&bnad->bna.enet);
8b230ed8
RM		 2472 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2473
2474 /* Enable broadcast */
2475 bnad_enable_default_bcast(bnad);
2476
aad75b66
RM		 2477 /* Restore VLANs, if any */
2478 bnad_restore_vlans(bnad, 0);
2479
8b230ed8
RM		 2480 /* Set the UCAST address */
2481 spin_lock_irqsave(&bnad->bna_lock, flags);
2482 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2483 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2484
2485 /* Start the stats timer */
2486 bnad_stats_timer_start(bnad);
2487
2488 mutex_unlock(&bnad->conf_mutex);
2489
2490 return 0;
2491
2492cleanup_tx:
2493 bnad_cleanup_tx(bnad, 0);
2494
2495err_return:
2496 mutex_unlock(&bnad->conf_mutex);
2497 return err;
2498}
2499
2500static int
2501bnad_stop(struct net_device *netdev)
2502{
2503 struct bnad *bnad = netdev_priv(netdev);
2504 unsigned long flags;
2505
2506 mutex_lock(&bnad->conf_mutex);
2507
2508 /* Stop the stats timer */
2509 bnad_stats_timer_stop(bnad);
2510
078086f3 2511 init_completion(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 2512
2513 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2514 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP,
2515 bnad_cb_enet_disabled);
8b230ed8
RM		 2516 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2517
078086f3 2518 wait_for_completion(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 2519
2520 bnad_cleanup_tx(bnad, 0);
2521 bnad_cleanup_rx(bnad, 0);
2522
2523 /* Synchronize mailbox IRQ */
2524 bnad_mbox_irq_sync(bnad);
2525
2526 mutex_unlock(&bnad->conf_mutex);
2527
2528 return 0;
2529}
2530
2531/* TX */
2532/*
2533 * bnad_start_xmit : Netdev entry point for Transmit
2534 * Called under lock held by net_device
2535 */
2536static netdev_tx_t
2537bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2538{
2539 struct bnad *bnad = netdev_priv(netdev);
078086f3
RM		 2540 u32 txq_id = 0;
2541 struct bna_tcb *tcb = bnad->tx_info[0].tcb[txq_id];
8b230ed8 2542
0120b99c
RM		 2543 u16 txq_prod, vlan_tag = 0;
2544 u32 unmap_prod, wis, wis_used, wi_range;
2545 u32 vectors, vect_id, i, acked;
0120b99c 2546 int err;
8b230ed8 2547
078086f3 2548 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
0120b99c 2549 dma_addr_t dma_addr;
8b230ed8 2550 struct bna_txq_entry *txqent;
078086f3 2551 u16 flags;
8b230ed8
RM		 2552
2553 if (unlikely
2554 (skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) {
2555 dev_kfree_skb(skb);
2556 return NETDEV_TX_OK;
2557 }
2558
2559 /*
2560 * Takes care of the Tx that is scheduled between clearing the flag
078086f3 2561 * and the netif_stop_all_queue() call.
8b230ed8 2562 */
be7fa326 2563 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
8b230ed8
RM		 2564 dev_kfree_skb(skb);
2565 return NETDEV_TX_OK;
2566 }
2567
8b230ed8
RM		 2568 vectors = 1 + skb_shinfo(skb)->nr_frags;
2569 if (vectors > BFI_TX_MAX_VECTORS_PER_PKT) {
2570 dev_kfree_skb(skb);
2571 return NETDEV_TX_OK;
2572 }
2573 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2574 acked = 0;
078086f3
RM		 2575 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2576 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
8b230ed8
RM		 2577 if ((u16) (*tcb->hw_consumer_index) !=
2578 tcb->consumer_index &&
2579 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2580 acked = bnad_free_txbufs(bnad, tcb);
be7fa326
RM		 2581 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2582 bna_ib_ack(tcb->i_dbell, acked);
8b230ed8
RM		 2583 smp_mb__before_clear_bit();
2584 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2585 } else {
2586 netif_stop_queue(netdev);
2587 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2588 }
2589
2590 smp_mb();
2591 /*
2592 * Check again to deal with race condition between
2593 * netif_stop_queue here, and netif_wake_queue in
2594 * interrupt handler which is not inside netif tx lock.
2595 */
2596 if (likely
2597 (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2598 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2599 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2600 return NETDEV_TX_BUSY;
2601 } else {
2602 netif_wake_queue(netdev);
2603 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
2604 }
2605 }
2606
2607 unmap_prod = unmap_q->producer_index;
2608 wis_used = 1;
2609 vect_id = 0;
2610 flags = 0;
2611
2612 txq_prod = tcb->producer_index;
2613 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, txqent, wi_range);
2614 BUG_ON(!(wi_range <= tcb->q_depth));
2615 txqent->hdr.wi.reserved = 0;
2616 txqent->hdr.wi.num_vectors = vectors;
2617 txqent->hdr.wi.opcode =
2618 htons((skb_is_gso(skb) ? BNA_TXQ_WI_SEND_LSO :
2619 BNA_TXQ_WI_SEND));
2620
eab6d18d 2621 if (vlan_tx_tag_present(skb)) {
8b230ed8
RM		 2622 vlan_tag = (u16) vlan_tx_tag_get(skb);
2623 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2624 }
2625 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2626 vlan_tag =
2627 (tcb->priority & 0x7) << 13 | (vlan_tag & 0x1fff);
2628 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2629 }
2630
2631 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2632
2633 if (skb_is_gso(skb)) {
2634 err = bnad_tso_prepare(bnad, skb);
2635 if (err) {
2636 dev_kfree_skb(skb);
2637 return NETDEV_TX_OK;
2638 }
2639 txqent->hdr.wi.lso_mss = htons(skb_is_gso(skb));
2640 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2641 txqent->hdr.wi.l4_hdr_size_n_offset =
2642 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2643 (tcp_hdrlen(skb) >> 2,
2644 skb_transport_offset(skb)));
2645 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2646 u8 proto = 0;
2647
2648 txqent->hdr.wi.lso_mss = 0;
2649
2650 if (skb->protocol == htons(ETH_P_IP))
2651 proto = ip_hdr(skb)->protocol;
2652 else if (skb->protocol == htons(ETH_P_IPV6)) {
2653 /* nexthdr may not be TCP immediately. */
2654 proto = ipv6_hdr(skb)->nexthdr;
2655 }
2656 if (proto == IPPROTO_TCP) {
2657 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2658 txqent->hdr.wi.l4_hdr_size_n_offset =
2659 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2660 (0, skb_transport_offset(skb)));
2661
2662 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2663
2664 BUG_ON(!(skb_headlen(skb) >=
2665 skb_transport_offset(skb) + tcp_hdrlen(skb)));
2666
2667 } else if (proto == IPPROTO_UDP) {
2668 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2669 txqent->hdr.wi.l4_hdr_size_n_offset =
2670 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2671 (0, skb_transport_offset(skb)));
2672
2673 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2674
2675 BUG_ON(!(skb_headlen(skb) >=
2676 skb_transport_offset(skb) +
2677 sizeof(struct udphdr)));
2678 } else {
2679 err = skb_checksum_help(skb);
2680 BNAD_UPDATE_CTR(bnad, csum_help);
2681 if (err) {
2682 dev_kfree_skb(skb);
2683 BNAD_UPDATE_CTR(bnad, csum_help_err);
2684 return NETDEV_TX_OK;
2685 }
2686 }
2687 } else {
2688 txqent->hdr.wi.lso_mss = 0;
2689 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
2690 }
2691
2692 txqent->hdr.wi.flags = htons(flags);
2693
2694 txqent->hdr.wi.frame_length = htonl(skb->len);
2695
2696 unmap_q->unmap_array[unmap_prod].skb = skb;
2697 BUG_ON(!(skb_headlen(skb) <= BFI_TX_MAX_DATA_PER_VECTOR));
2698 txqent->vector[vect_id].length = htons(skb_headlen(skb));
5ea74318
IV		 2699 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
2700 skb_headlen(skb), DMA_TO_DEVICE);
2701 dma_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
8b230ed8
RM		 2702 dma_addr);
2703
2704 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2705 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2706
2707 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2708 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
078086f3 2709 u16 size = frag->size;
8b230ed8
RM		 2710
2711 if (++vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
2712 vect_id = 0;
2713 if (--wi_range)
2714 txqent++;
2715 else {
2716 BNA_QE_INDX_ADD(txq_prod, wis_used,
2717 tcb->q_depth);
2718 wis_used = 0;
2719 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt,
2720 txqent, wi_range);
2721 BUG_ON(!(wi_range <= tcb->q_depth));
2722 }
2723 wis_used++;
2724 txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
2725 }
2726
2727 BUG_ON(!(size <= BFI_TX_MAX_DATA_PER_VECTOR));
2728 txqent->vector[vect_id].length = htons(size);
5ea74318
IV		 2729 dma_addr = dma_map_page(&bnad->pcidev->dev, frag->page,
2730 frag->page_offset, size, DMA_TO_DEVICE);
2731 dma_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
8b230ed8
RM		 2732 dma_addr);
2733 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2734 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2735 }
2736
2737 unmap_q->producer_index = unmap_prod;
2738 BNA_QE_INDX_ADD(txq_prod, wis_used, tcb->q_depth);
2739 tcb->producer_index = txq_prod;
2740
2741 smp_mb();
be7fa326
RM		 2742
2743 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2744 return NETDEV_TX_OK;
2745
8b230ed8
RM		 2746 bna_txq_prod_indx_doorbell(tcb);
2747
2748 if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index)
2749 tasklet_schedule(&bnad->tx_free_tasklet);
2750
2751 return NETDEV_TX_OK;
2752}
2753
2754/*
2755 * Used spin_lock to synchronize reading of stats structures, which
2756 * is written by BNA under the same lock.
2757 */
250e061e
ED		 2758static struct rtnl_link_stats64 *
2759bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
8b230ed8
RM		 2760{
2761 struct bnad *bnad = netdev_priv(netdev);
2762 unsigned long flags;
2763
2764 spin_lock_irqsave(&bnad->bna_lock, flags);
2765
250e061e
ED		 2766 bnad_netdev_qstats_fill(bnad, stats);
2767 bnad_netdev_hwstats_fill(bnad, stats);
8b230ed8
RM		 2768
2769 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2770
250e061e 2771 return stats;
8b230ed8
RM		 2772}
2773
2774static void
2775bnad_set_rx_mode(struct net_device *netdev)
2776{
2777 struct bnad *bnad = netdev_priv(netdev);
2778 u32 new_mask, valid_mask;
2779 unsigned long flags;
2780
2781 spin_lock_irqsave(&bnad->bna_lock, flags);
2782
2783 new_mask = valid_mask = 0;
2784
2785 if (netdev->flags & IFF_PROMISC) {
2786 if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) {
2787 new_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2788 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2789 bnad->cfg_flags |= BNAD_CF_PROMISC;
2790 }
2791 } else {
2792 if (bnad->cfg_flags & BNAD_CF_PROMISC) {
2793 new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT;
2794 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2795 bnad->cfg_flags &= ~BNAD_CF_PROMISC;
2796 }
2797 }
2798
2799 if (netdev->flags & IFF_ALLMULTI) {
2800 if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) {
2801 new_mask |= BNA_RXMODE_ALLMULTI;
2802 valid_mask |= BNA_RXMODE_ALLMULTI;
2803 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
2804 }
2805 } else {
2806 if (bnad->cfg_flags & BNAD_CF_ALLMULTI) {
2807 new_mask &= ~BNA_RXMODE_ALLMULTI;
2808 valid_mask |= BNA_RXMODE_ALLMULTI;
2809 bnad->cfg_flags &= ~BNAD_CF_ALLMULTI;
2810 }
2811 }
2812
2813 bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL);
2814
2815 if (!netdev_mc_empty(netdev)) {
2816 u8 *mcaddr_list;
2817 int mc_count = netdev_mc_count(netdev);
2818
2819 /* Index 0 holds the broadcast address */
2820 mcaddr_list =
2821 kzalloc((mc_count + 1) * ETH_ALEN,
2822 GFP_ATOMIC);
2823 if (!mcaddr_list)
ca1cef3a 2824 goto unlock;
8b230ed8
RM		 2825
2826 memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN);
2827
2828 /* Copy rest of the MC addresses */
2829 bnad_netdev_mc_list_get(netdev, mcaddr_list);
2830
2831 bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
2832 mcaddr_list, NULL);
2833
2834 /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
2835 kfree(mcaddr_list);
2836 }
ca1cef3a 2837unlock:
8b230ed8
RM		 2838 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2839}
2840
2841/*
2842 * bna_lock is used to sync writes to netdev->addr
2843 * conf_lock cannot be used since this call may be made
2844 * in a non-blocking context.
2845 */
2846static int
2847bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
2848{
2849 int err;
2850 struct bnad *bnad = netdev_priv(netdev);
2851 struct sockaddr *sa = (struct sockaddr *)mac_addr;
2852 unsigned long flags;
2853
2854 spin_lock_irqsave(&bnad->bna_lock, flags);
2855
2856 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
2857
2858 if (!err)
2859 memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
2860
2861 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2862
2863 return err;
2864}
2865
2866static int
078086f3 2867bnad_mtu_set(struct bnad *bnad, int mtu)
8b230ed8 2868{
8b230ed8
RM		 2869 unsigned long flags;
2870
078086f3
RM		 2871 init_completion(&bnad->bnad_completions.mtu_comp);
2872
2873 spin_lock_irqsave(&bnad->bna_lock, flags);
2874 bna_enet_mtu_set(&bnad->bna.enet, mtu, bnad_cb_enet_mtu_set);
2875 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2876
2877 wait_for_completion(&bnad->bnad_completions.mtu_comp);
2878
2879 return bnad->bnad_completions.mtu_comp_status;
2880}
2881
2882static int
2883bnad_change_mtu(struct net_device *netdev, int new_mtu)
2884{
2885 int err, mtu = netdev->mtu;
8b230ed8
RM		 2886 struct bnad *bnad = netdev_priv(netdev);
2887
2888 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
2889 return -EINVAL;
2890
2891 mutex_lock(&bnad->conf_mutex);
2892
2893 netdev->mtu = new_mtu;
2894
078086f3
RM		 2895 mtu = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
2896 err = bnad_mtu_set(bnad, mtu);
2897 if (err)
2898 err = -EBUSY;
8b230ed8
RM		 2899
2900 mutex_unlock(&bnad->conf_mutex);
2901 return err;
2902}
2903
8b230ed8
RM		 2904static void
2905bnad_vlan_rx_add_vid(struct net_device *netdev,
2906 unsigned short vid)
2907{
2908 struct bnad *bnad = netdev_priv(netdev);
2909 unsigned long flags;
2910
2911 if (!bnad->rx_info[0].rx)
2912 return;
2913
2914 mutex_lock(&bnad->conf_mutex);
2915
2916 spin_lock_irqsave(&bnad->bna_lock, flags);
2917 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
f859d7cb 2918 set_bit(vid, bnad->active_vlans);
8b230ed8
RM		 2919 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2920
2921 mutex_unlock(&bnad->conf_mutex);
2922}
2923
2924static void
2925bnad_vlan_rx_kill_vid(struct net_device *netdev,
2926 unsigned short vid)
2927{
2928 struct bnad *bnad = netdev_priv(netdev);
2929 unsigned long flags;
2930
2931 if (!bnad->rx_info[0].rx)
2932 return;
2933
2934 mutex_lock(&bnad->conf_mutex);
2935
2936 spin_lock_irqsave(&bnad->bna_lock, flags);
f859d7cb 2937 clear_bit(vid, bnad->active_vlans);
8b230ed8
RM		 2938 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
2939 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2940
2941 mutex_unlock(&bnad->conf_mutex);
2942}
2943
2944#ifdef CONFIG_NET_POLL_CONTROLLER
2945static void
2946bnad_netpoll(struct net_device *netdev)
2947{
2948 struct bnad *bnad = netdev_priv(netdev);
2949 struct bnad_rx_info *rx_info;
2950 struct bnad_rx_ctrl *rx_ctrl;
2951 u32 curr_mask;
2952 int i, j;
2953
2954 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2955 bna_intx_disable(&bnad->bna, curr_mask);
2956 bnad_isr(bnad->pcidev->irq, netdev);
2957 bna_intx_enable(&bnad->bna, curr_mask);
2958 } else {
2959 for (i = 0; i < bnad->num_rx; i++) {
2960 rx_info = &bnad->rx_info[i];
2961 if (!rx_info->rx)
2962 continue;
2963 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2964 rx_ctrl = &rx_info->rx_ctrl[j];
2965 if (rx_ctrl->ccb) {
2966 bnad_disable_rx_irq(bnad,
2967 rx_ctrl->ccb);
2968 bnad_netif_rx_schedule_poll(bnad,
2969 rx_ctrl->ccb);
2970 }
2971 }
2972 }
2973 }
2974}
2975#endif
2976
2977static const struct net_device_ops bnad_netdev_ops = {
2978 .ndo_open = bnad_open,
2979 .ndo_stop = bnad_stop,
2980 .ndo_start_xmit = bnad_start_xmit,
250e061e 2981 .ndo_get_stats64 = bnad_get_stats64,
8b230ed8 2982 .ndo_set_rx_mode = bnad_set_rx_mode,
8b230ed8
RM		 2983 .ndo_validate_addr = eth_validate_addr,
2984 .ndo_set_mac_address = bnad_set_mac_address,
2985 .ndo_change_mtu = bnad_change_mtu,
8b230ed8
RM		 2986 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
2987 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
2988#ifdef CONFIG_NET_POLL_CONTROLLER
2989 .ndo_poll_controller = bnad_netpoll
2990#endif
2991};
2992
2993static void
2994bnad_netdev_init(struct bnad *bnad, bool using_dac)
2995{
2996 struct net_device *netdev = bnad->netdev;
2997
e5ee20e7
MM		 2998 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
2999 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3000 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_TX;
8b230ed8 3001
e5ee20e7
MM		 3002 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
3003 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3004 NETIF_F_TSO | NETIF_F_TSO6;
8b230ed8 3005
e5ee20e7
MM		 3006 netdev->features |= netdev->hw_features |
3007 NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
8b230ed8
RM		 3008
3009 if (using_dac)
3010 netdev->features |= NETIF_F_HIGHDMA;
3011
8b230ed8
RM		 3012 netdev->mem_start = bnad->mmio_start;
3013 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
3014
3015 netdev->netdev_ops = &bnad_netdev_ops;
3016 bnad_set_ethtool_ops(netdev);
3017}
3018
3019/*
3020 * 1. Initialize the bnad structure
3021 * 2. Setup netdev pointer in pci_dev
3022 * 3. Initialze Tx free tasklet
3023 * 4. Initialize no. of TxQ & CQs & MSIX vectors
3024 */
3025static int
3026bnad_init(struct bnad *bnad,
3027 struct pci_dev *pdev, struct net_device *netdev)
3028{
3029 unsigned long flags;
3030
3031 SET_NETDEV_DEV(netdev, &pdev->dev);
3032 pci_set_drvdata(pdev, netdev);
3033
3034 bnad->netdev = netdev;
3035 bnad->pcidev = pdev;
3036 bnad->mmio_start = pci_resource_start(pdev, 0);
3037 bnad->mmio_len = pci_resource_len(pdev, 0);
3038 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
3039 if (!bnad->bar0) {
3040 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
3041 pci_set_drvdata(pdev, NULL);
3042 return -ENOMEM;
3043 }
3044 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
3045 (unsigned long long) bnad->mmio_len);
3046
3047 spin_lock_irqsave(&bnad->bna_lock, flags);
3048 if (!bnad_msix_disable)
3049 bnad->cfg_flags = BNAD_CF_MSIX;
3050
3051 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
3052
3053 bnad_q_num_init(bnad);
3054 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3055
3056 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
3057 (bnad->num_rx * bnad->num_rxp_per_rx) +
3058 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8
RM		 3059
3060 bnad->txq_depth = BNAD_TXQ_DEPTH;
3061 bnad->rxq_depth = BNAD_RXQ_DEPTH;
8b230ed8
RM		 3062
3063 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3064 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
3065
3066 tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet,
3067 (unsigned long)bnad);
3068
3069 return 0;
3070}
3071
3072/*
3073 * Must be called after bnad_pci_uninit()
3074 * so that iounmap() and pci_set_drvdata(NULL)
3075 * happens only after PCI uninitialization.
3076 */
3077static void
3078bnad_uninit(struct bnad *bnad)
3079{
3080 if (bnad->bar0)
3081 iounmap(bnad->bar0);
3082 pci_set_drvdata(bnad->pcidev, NULL);
3083}
3084
3085/*
3086 * Initialize locks
078086f3 3087 a) Per ioceth mutes used for serializing configuration
8b230ed8
RM		 3088 changes from OS interface
3089 b) spin lock used to protect bna state machine
3090 */
3091static void
3092bnad_lock_init(struct bnad *bnad)
3093{
3094 spin_lock_init(&bnad->bna_lock);
3095 mutex_init(&bnad->conf_mutex);
3096}
3097
3098static void
3099bnad_lock_uninit(struct bnad *bnad)
3100{
3101 mutex_destroy(&bnad->conf_mutex);
3102}
3103
3104/* PCI Initialization */
3105static int
3106bnad_pci_init(struct bnad *bnad,
3107 struct pci_dev *pdev, bool *using_dac)
3108{
3109 int err;
3110
3111 err = pci_enable_device(pdev);
3112 if (err)
3113 return err;
3114 err = pci_request_regions(pdev, BNAD_NAME);
3115 if (err)
3116 goto disable_device;
5ea74318
IV		 3117 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
3118 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
8b230ed8
RM		 3119 *using_dac = 1;
3120 } else {
5ea74318 3121 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
8b230ed8 3122 if (err) {
5ea74318
IV		 3123 err = dma_set_coherent_mask(&pdev->dev,
3124 DMA_BIT_MASK(32));
8b230ed8
RM		 3125 if (err)
3126 goto release_regions;
3127 }
3128 *using_dac = 0;
3129 }
3130 pci_set_master(pdev);
3131 return 0;
3132
3133release_regions:
3134 pci_release_regions(pdev);
3135disable_device:
3136 pci_disable_device(pdev);
3137
3138 return err;
3139}
3140
3141static void
3142bnad_pci_uninit(struct pci_dev *pdev)
3143{
3144 pci_release_regions(pdev);
3145 pci_disable_device(pdev);
3146}
3147
3148static int __devinit
3149bnad_pci_probe(struct pci_dev *pdev,
3150 const struct pci_device_id *pcidev_id)
3151{
0120b99c
RM		 3152 bool using_dac = false;
3153 int err;
8b230ed8
RM		 3154 struct bnad *bnad;
3155 struct bna *bna;
3156 struct net_device *netdev;
3157 struct bfa_pcidev pcidev_info;
3158 unsigned long flags;
3159
3160 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3161 pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3162
3163 mutex_lock(&bnad_fwimg_mutex);
3164 if (!cna_get_firmware_buf(pdev)) {
3165 mutex_unlock(&bnad_fwimg_mutex);
3166 pr_warn("Failed to load Firmware Image!\n");
3167 return -ENODEV;
3168 }
3169 mutex_unlock(&bnad_fwimg_mutex);
3170
3171 /*
3172 * Allocates sizeof(struct net_device + struct bnad)
3173 * bnad = netdev->priv
3174 */
3175 netdev = alloc_etherdev(sizeof(struct bnad));
3176 if (!netdev) {
078086f3 3177 dev_err(&pdev->dev, "netdev allocation failed\n");
8b230ed8
RM		 3178 err = -ENOMEM;
3179 return err;
3180 }
3181 bnad = netdev_priv(netdev);
3182
078086f3
RM		 3183 bnad_lock_init(bnad);
3184
3185 mutex_lock(&bnad->conf_mutex);
8b230ed8
RM		 3186 /*
3187 * PCI initialization
0120b99c 3188 * Output : using_dac = 1 for 64 bit DMA
be7fa326 3189 * = 0 for 32 bit DMA
8b230ed8
RM		 3190 */
3191 err = bnad_pci_init(bnad, pdev, &using_dac);
3192 if (err)
44861f44 3193 goto unlock_mutex;
8b230ed8 3194
8b230ed8
RM		 3195 /*
3196 * Initialize bnad structure
3197 * Setup relation between pci_dev & netdev
3198 * Init Tx free tasklet
3199 */
3200 err = bnad_init(bnad, pdev, netdev);
3201 if (err)
3202 goto pci_uninit;
078086f3 3203
8b230ed8
RM		 3204 /* Initialize netdev structure, set up ethtool ops */
3205 bnad_netdev_init(bnad, using_dac);
3206
815f41e7
RM		 3207 /* Set link to down state */
3208 netif_carrier_off(netdev);
3209
8b230ed8 3210 /* Get resource requirement form bna */
078086f3 3211 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 3212 bna_res_req(&bnad->res_info[0]);
078086f3 3213 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 3214
3215 /* Allocate resources from bna */
078086f3 3216 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
8b230ed8 3217 if (err)
078086f3 3218 goto drv_uninit;
8b230ed8
RM		 3219
3220 bna = &bnad->bna;
3221
3222 /* Setup pcidev_info for bna_init() */
3223 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3224 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3225 pcidev_info.device_id = bnad->pcidev->device;
3226 pcidev_info.pci_bar_kva = bnad->bar0;
3227
8b230ed8
RM		 3228 spin_lock_irqsave(&bnad->bna_lock, flags);
3229 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
8b230ed8
RM		 3230 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3231
3232 bnad->stats.bna_stats = &bna->stats;
3233
078086f3
RM		 3234 bnad_enable_msix(bnad);
3235 err = bnad_mbox_irq_alloc(bnad);
3236 if (err)
3237 goto res_free;
3238
3239
8b230ed8 3240 /* Set up timers */
078086f3 3241 setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
8b230ed8 3242 ((unsigned long)bnad));
078086f3 3243 setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
8b230ed8 3244 ((unsigned long)bnad));
078086f3 3245 setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
1d32f769 3246 ((unsigned long)bnad));
078086f3 3247 setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
8b230ed8
RM		 3248 ((unsigned long)bnad));
3249
3250 /* Now start the timer before calling IOC */
078086f3 3251 mod_timer(&bnad->bna.ioceth.ioc.iocpf_timer,
8b230ed8
RM		 3252 jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
3253
3254 /*
3255 * Start the chip
078086f3
RM		 3256 * If the call back comes with error, we bail out.
3257 * This is a catastrophic error.
8b230ed8 3258 */
078086f3
RM		 3259 err = bnad_ioceth_enable(bnad);
3260 if (err) {
3261 pr_err("BNA: Initialization failed err=%d\n",
3262 err);
3263 goto probe_success;
3264 }
3265
3266 spin_lock_irqsave(&bnad->bna_lock, flags);
3267 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3268 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) {
3269 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1,
3270 bna_attr(bna)->num_rxp - 1);
3271 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3272 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1))
3273 err = -EIO;
3274 }
3275 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]);
3276 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3277
3278 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
0caa9aae
RM		 3279 if (err) {
3280 err = -EIO;
078086f3 3281 goto disable_ioceth;
0caa9aae 3282 }
078086f3
RM		 3283
3284 spin_lock_irqsave(&bnad->bna_lock, flags);
3285 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]);
3286 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 3287
3288 /* Get the burnt-in mac */
3289 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 3290 bna_enet_perm_mac_get(&bna->enet, &bnad->perm_addr);
8b230ed8
RM		 3291 bnad_set_netdev_perm_addr(bnad);
3292 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3293
0caa9aae
RM		 3294 mutex_unlock(&bnad->conf_mutex);
3295
8b230ed8
RM		 3296 /* Finally, reguister with net_device layer */
3297 err = register_netdev(netdev);
3298 if (err) {
3299 pr_err("BNA : Registering with netdev failed\n");
078086f3 3300 goto probe_uninit;
8b230ed8 3301 }
078086f3 3302 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
8b230ed8 3303
0caa9aae
RM		 3304 return 0;
3305
078086f3
RM		 3306probe_success:
3307 mutex_unlock(&bnad->conf_mutex);
8b230ed8
RM		 3308 return 0;
3309
078086f3
RM		 3310probe_uninit:
3311 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3312disable_ioceth:
3313 bnad_ioceth_disable(bnad);
3314 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3315 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3316 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
8b230ed8
RM		 3317 spin_lock_irqsave(&bnad->bna_lock, flags);
3318 bna_uninit(bna);
3319 spin_unlock_irqrestore(&bnad->bna_lock, flags);
078086f3 3320 bnad_mbox_irq_free(bnad);
8b230ed8 3321 bnad_disable_msix(bnad);
078086f3
RM		 3322res_free:
3323 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3324drv_uninit:
3325 bnad_uninit(bnad);
8b230ed8
RM		 3326pci_uninit:
3327 bnad_pci_uninit(pdev);
44861f44 3328unlock_mutex:
078086f3 3329 mutex_unlock(&bnad->conf_mutex);
8b230ed8 3330 bnad_lock_uninit(bnad);
8b230ed8
RM		 3331 free_netdev(netdev);
3332 return err;
3333}
3334
3335static void __devexit
3336bnad_pci_remove(struct pci_dev *pdev)
3337{
3338 struct net_device *netdev = pci_get_drvdata(pdev);
3339 struct bnad *bnad;
3340 struct bna *bna;
3341 unsigned long flags;
3342
3343 if (!netdev)
3344 return;
3345
3346 pr_info("%s bnad_pci_remove\n", netdev->name);
3347 bnad = netdev_priv(netdev);
3348 bna = &bnad->bna;
3349
078086f3
RM		 3350 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags))
3351 unregister_netdev(netdev);
8b230ed8
RM		 3352
3353 mutex_lock(&bnad->conf_mutex);
078086f3
RM		 3354 bnad_ioceth_disable(bnad);
3355 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3356 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3357 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
8b230ed8
RM		 3358 spin_lock_irqsave(&bnad->bna_lock, flags);
3359 bna_uninit(bna);
3360 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 3361
078086f3
RM		 3362 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3363 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3364 bnad_mbox_irq_free(bnad);
8b230ed8
RM		 3365 bnad_disable_msix(bnad);
3366 bnad_pci_uninit(pdev);
078086f3 3367 mutex_unlock(&bnad->conf_mutex);
8b230ed8
RM		 3368 bnad_lock_uninit(bnad);
3369 bnad_uninit(bnad);
3370 free_netdev(netdev);
3371}
3372
0120b99c 3373static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table) = {
8b230ed8
RM		 3374 {
3375 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3376 PCI_DEVICE_ID_BROCADE_CT),
3377 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3378 .class_mask = 0xffff00
3379 }, {0, }
3380};
3381
3382MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3383
3384static struct pci_driver bnad_pci_driver = {
3385 .name = BNAD_NAME,
3386 .id_table = bnad_pci_id_table,
3387 .probe = bnad_pci_probe,
3388 .remove = __devexit_p(bnad_pci_remove),
3389};
3390
3391static int __init
3392bnad_module_init(void)
3393{
3394 int err;
3395
5aad0011
RM		 3396 pr_info("Brocade 10G Ethernet driver - version: %s\n",
3397 BNAD_VERSION);
8b230ed8 3398
8a891429 3399 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
8b230ed8
RM		 3400
3401 err = pci_register_driver(&bnad_pci_driver);
3402 if (err < 0) {
3403 pr_err("bna : PCI registration failed in module init "
3404 "(%d)\n", err);
3405 return err;
3406 }
3407
3408 return 0;
3409}
3410
3411static void __exit
3412bnad_module_exit(void)
3413{
3414 pci_unregister_driver(&bnad_pci_driver);
3415
3416 if (bfi_fw)
3417 release_firmware(bfi_fw);
3418}
3419
3420module_init(bnad_module_init);
3421module_exit(bnad_module_exit);
3422
3423MODULE_AUTHOR("Brocade");
3424MODULE_LICENSE("GPL");
3425MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3426MODULE_VERSION(BNAD_VERSION);
3427MODULE_FIRMWARE(CNA_FW_FILE_CT);
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