]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/ethernet/brocade/bna/bnad.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branches 'spi/topic/s3c64xx', 'spi/topic/sc18is602', 'spi/topic...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / brocade / bna / bnad.c
CommitLineData
8b230ed8
RM		 1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
f859d7cb 18#include <linux/bitops.h>
8b230ed8
RM		 19#include <linux/netdevice.h>
20#include <linux/skbuff.h>
21#include <linux/etherdevice.h>
22#include <linux/in.h>
23#include <linux/ethtool.h>
24#include <linux/if_vlan.h>
25#include <linux/if_ether.h>
26#include <linux/ip.h>
70c71606 27#include <linux/prefetch.h>
9d9779e7 28#include <linux/module.h>
8b230ed8
RM		 29
30#include "bnad.h"
31#include "bna.h"
32#include "cna.h"
33
b7ee31c5 34static DEFINE_MUTEX(bnad_fwimg_mutex);
8b230ed8
RM		 35
36/*
37 * Module params
38 */
39static uint bnad_msix_disable;
40module_param(bnad_msix_disable, uint, 0444);
41MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
42
43static uint bnad_ioc_auto_recover = 1;
44module_param(bnad_ioc_auto_recover, uint, 0444);
45MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
46
7afc5dbd
KG		 47static uint bna_debugfs_enable = 1;
48module_param(bna_debugfs_enable, uint, S_IRUGO | S_IWUSR);
49MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1,"
50 " Range[false:0|true:1]");
51
8b230ed8
RM		 52/*
53 * Global variables
54 */
482da0fa 55static u32 bnad_rxqs_per_cq = 2;
e1e0918f 56static u32 bna_id;
57static struct mutex bnad_list_mutex;
58static LIST_HEAD(bnad_list);
b7ee31c5 59static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
8b230ed8
RM		 60
61/*
62 * Local MACROS
63 */
8b230ed8
RM		 64#define BNAD_GET_MBOX_IRQ(_bnad) \
65 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
8811e267 66 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
8b230ed8
RM		 67 ((_bnad)->pcidev->irq))
68
5216562a 69#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \
8b230ed8
RM		 70do { \
71 (_res_info)->res_type = BNA_RES_T_MEM; \
72 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
73 (_res_info)->res_u.mem_info.num = (_num); \
5216562a 74 (_res_info)->res_u.mem_info.len = (_size); \
8b230ed8
RM		 75} while (0)
76
72a9730b
KG		 77static void
78bnad_add_to_list(struct bnad *bnad)
79{
80 mutex_lock(&bnad_list_mutex);
81 list_add_tail(&bnad->list_entry, &bnad_list);
82 bnad->id = bna_id++;
83 mutex_unlock(&bnad_list_mutex);
84}
85
86static void
87bnad_remove_from_list(struct bnad *bnad)
88{
89 mutex_lock(&bnad_list_mutex);
90 list_del(&bnad->list_entry);
91 mutex_unlock(&bnad_list_mutex);
92}
93
8b230ed8
RM		 94/*
95 * Reinitialize completions in CQ, once Rx is taken down
96 */
97static void
b3cc6e88 98bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb)
8b230ed8 99{
5216562a 100 struct bna_cq_entry *cmpl;
8b230ed8
RM		 101 int i;
102
8b230ed8 103 for (i = 0; i < ccb->q_depth; i++) {
5216562a 104 cmpl = &((struct bna_cq_entry *)ccb->sw_q)[i];
8b230ed8 105 cmpl->valid = 0;
8b230ed8
RM		 106 }
107}
108
5216562a
RM		 109/* Tx Datapath functions */
110
111
112/* Caller should ensure that the entry at unmap_q[index] is valid */
271e8b79 113static u32
5216562a
RM		 114bnad_tx_buff_unmap(struct bnad *bnad,
115 struct bnad_tx_unmap *unmap_q,
116 u32 q_depth, u32 index)
271e8b79 117{
5216562a
RM		 118 struct bnad_tx_unmap *unmap;
119 struct sk_buff *skb;
120 int vector, nvecs;
121
122 unmap = &unmap_q[index];
123 nvecs = unmap->nvecs;
124
125 skb = unmap->skb;
126 unmap->skb = NULL;
127 unmap->nvecs = 0;
128 dma_unmap_single(&bnad->pcidev->dev,
129 dma_unmap_addr(&unmap->vectors[0], dma_addr),
130 skb_headlen(skb), DMA_TO_DEVICE);
131 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, 0);
132 nvecs--;
133
134 vector = 0;
135 while (nvecs) {
136 vector++;
137 if (vector == BFI_TX_MAX_VECTORS_PER_WI) {
138 vector = 0;
139 BNA_QE_INDX_INC(index, q_depth);
140 unmap = &unmap_q[index];
141 }
271e8b79 142
5216562a
RM		 143 dma_unmap_page(&bnad->pcidev->dev,
144 dma_unmap_addr(&unmap->vectors[vector], dma_addr),
24f5d33d
RM		 145 dma_unmap_len(&unmap->vectors[vector], dma_len),
146 DMA_TO_DEVICE);
5216562a
RM		 147 dma_unmap_addr_set(&unmap->vectors[vector], dma_addr, 0);
148 nvecs--;
271e8b79
RM		 149 }
150
5216562a
RM		 151 BNA_QE_INDX_INC(index, q_depth);
152
271e8b79
RM		 153 return index;
154}
155
8b230ed8
RM		 156/*
157 * Frees all pending Tx Bufs
158 * At this point no activity is expected on the Q,
159 * so DMA unmap & freeing is fine.
160 */
161static void
5216562a 162bnad_txq_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
8b230ed8 163{
5216562a
RM		 164 struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
165 struct sk_buff *skb;
166 int i;
8b230ed8 167
5216562a
RM		 168 for (i = 0; i < tcb->q_depth; i++) {
169 skb = unmap_q[i].skb;
938fa488 170 if (!skb)
8b230ed8 171 continue;
5216562a 172 bnad_tx_buff_unmap(bnad, unmap_q, tcb->q_depth, i);
938fa488 173
8b230ed8
RM		 174 dev_kfree_skb_any(skb);
175 }
176}
177
8b230ed8 178/*
b3cc6e88 179 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion
8b230ed8
RM		 180 * Can be called in a) Interrupt context
181 * b) Sending context
8b230ed8
RM		 182 */
183static u32
5216562a 184bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb)
8b230ed8 185{
5216562a
RM		 186 u32 sent_packets = 0, sent_bytes = 0;
187 u32 wis, unmap_wis, hw_cons, cons, q_depth;
188 struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
189 struct bnad_tx_unmap *unmap;
190 struct sk_buff *skb;
8b230ed8 191
d95d1081 192 /* Just return if TX is stopped */
be7fa326 193 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
8b230ed8
RM		 194 return 0;
195
5216562a
RM		 196 hw_cons = *(tcb->hw_consumer_index);
197 cons = tcb->consumer_index;
198 q_depth = tcb->q_depth;
8b230ed8 199
5216562a 200 wis = BNA_Q_INDEX_CHANGE(cons, hw_cons, q_depth);
8b230ed8
RM		 201 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
202
8b230ed8 203 while (wis) {
5216562a
RM		 204 unmap = &unmap_q[cons];
205
206 skb = unmap->skb;
8b230ed8 207
8b230ed8
RM		 208 sent_packets++;
209 sent_bytes += skb->len;
8b230ed8 210
5216562a
RM		 211 unmap_wis = BNA_TXQ_WI_NEEDED(unmap->nvecs);
212 wis -= unmap_wis;
8b230ed8 213
5216562a 214 cons = bnad_tx_buff_unmap(bnad, unmap_q, q_depth, cons);
8b230ed8
RM		 215 dev_kfree_skb_any(skb);
216 }
217
218 /* Update consumer pointers. */
5216562a 219 tcb->consumer_index = hw_cons;
8b230ed8
RM		 220
221 tcb->txq->tx_packets += sent_packets;
222 tcb->txq->tx_bytes += sent_bytes;
223
224 return sent_packets;
225}
226
8b230ed8 227static u32
b3cc6e88 228bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb)
8b230ed8
RM		 229{
230 struct net_device *netdev = bnad->netdev;
be7fa326 231 u32 sent = 0;
8b230ed8
RM		 232
233 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
234 return 0;
235
b3cc6e88 236 sent = bnad_txcmpl_process(bnad, tcb);
8b230ed8
RM		 237 if (sent) {
238 if (netif_queue_stopped(netdev) &&
239 netif_carrier_ok(netdev) &&
240 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
241 BNAD_NETIF_WAKE_THRESHOLD) {
be7fa326
RM		 242 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
243 netif_wake_queue(netdev);
244 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
245 }
8b230ed8 246 }
be7fa326
RM		 247 }
248
249 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
8b230ed8 250 bna_ib_ack(tcb->i_dbell, sent);
8b230ed8
RM		 251
252 smp_mb__before_clear_bit();
253 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
254
255 return sent;
256}
257
258/* MSIX Tx Completion Handler */
259static irqreturn_t
260bnad_msix_tx(int irq, void *data)
261{
262 struct bna_tcb *tcb = (struct bna_tcb *)data;
263 struct bnad *bnad = tcb->bnad;
264
b3cc6e88 265 bnad_tx_complete(bnad, tcb);
8b230ed8
RM		 266
267 return IRQ_HANDLED;
268}
269
30f9fc94
RM		 270static inline void
271bnad_rxq_alloc_uninit(struct bnad *bnad, struct bna_rcb *rcb)
272{
273 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
274
275 unmap_q->reuse_pi = -1;
276 unmap_q->alloc_order = -1;
277 unmap_q->map_size = 0;
278 unmap_q->type = BNAD_RXBUF_NONE;
279}
280
281/* Default is page-based allocation. Multi-buffer support - TBD */
282static int
283bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb)
284{
285 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
e29aa339 286 int order;
30f9fc94
RM		 287
288 bnad_rxq_alloc_uninit(bnad, rcb);
289
e29aa339
RM		 290 order = get_order(rcb->rxq->buffer_size);
291
292 unmap_q->type = BNAD_RXBUF_PAGE;
30f9fc94
RM		 293
294 if (bna_is_small_rxq(rcb->id)) {
295 unmap_q->alloc_order = 0;
296 unmap_q->map_size = rcb->rxq->buffer_size;
297 } else {
e29aa339
RM		 298 if (rcb->rxq->multi_buffer) {
299 unmap_q->alloc_order = 0;
300 unmap_q->map_size = rcb->rxq->buffer_size;
301 unmap_q->type = BNAD_RXBUF_MULTI_BUFF;
302 } else {
303 unmap_q->alloc_order = order;
304 unmap_q->map_size =
305 (rcb->rxq->buffer_size > 2048) ?
306 PAGE_SIZE << order : 2048;
307 }
30f9fc94
RM		 308 }
309
310 BUG_ON(((PAGE_SIZE << order) % unmap_q->map_size));
311
30f9fc94
RM		 312 return 0;
313}
314
315static inline void
316bnad_rxq_cleanup_page(struct bnad *bnad, struct bnad_rx_unmap *unmap)
317{
318 if (!unmap->page)
319 return;
320
321 dma_unmap_page(&bnad->pcidev->dev,
322 dma_unmap_addr(&unmap->vector, dma_addr),
323 unmap->vector.len, DMA_FROM_DEVICE);
324 put_page(unmap->page);
325 unmap->page = NULL;
326 dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
327 unmap->vector.len = 0;
328}
329
330static inline void
331bnad_rxq_cleanup_skb(struct bnad *bnad, struct bnad_rx_unmap *unmap)
332{
333 if (!unmap->skb)
334 return;
335
336 dma_unmap_single(&bnad->pcidev->dev,
337 dma_unmap_addr(&unmap->vector, dma_addr),
338 unmap->vector.len, DMA_FROM_DEVICE);
339 dev_kfree_skb_any(unmap->skb);
340 unmap->skb = NULL;
341 dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
342 unmap->vector.len = 0;
343}
344
8b230ed8 345static void
b3cc6e88 346bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb)
8b230ed8 347{
30f9fc94 348 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
5216562a
RM		 349 int i;
350
351 for (i = 0; i < rcb->q_depth; i++) {
30f9fc94 352 struct bnad_rx_unmap *unmap = &unmap_q->unmap[i];
8b230ed8 353
e29aa339 354 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
30f9fc94 355 bnad_rxq_cleanup_skb(bnad, unmap);
e29aa339
RM		 356 else
357 bnad_rxq_cleanup_page(bnad, unmap);
30f9fc94
RM		 358 }
359 bnad_rxq_alloc_uninit(bnad, rcb);
360}
5216562a 361
30f9fc94
RM		 362static u32
363bnad_rxq_refill_page(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
364{
365 u32 alloced, prod, q_depth;
366 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
367 struct bnad_rx_unmap *unmap, *prev;
368 struct bna_rxq_entry *rxent;
369 struct page *page;
370 u32 page_offset, alloc_size;
371 dma_addr_t dma_addr;
372
373 prod = rcb->producer_index;
374 q_depth = rcb->q_depth;
375
376 alloc_size = PAGE_SIZE << unmap_q->alloc_order;
377 alloced = 0;
378
379 while (nalloc--) {
380 unmap = &unmap_q->unmap[prod];
381
382 if (unmap_q->reuse_pi < 0) {
383 page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
384 unmap_q->alloc_order);
385 page_offset = 0;
386 } else {
387 prev = &unmap_q->unmap[unmap_q->reuse_pi];
388 page = prev->page;
389 page_offset = prev->page_offset + unmap_q->map_size;
390 get_page(page);
391 }
392
393 if (unlikely(!page)) {
394 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
395 rcb->rxq->rxbuf_alloc_failed++;
396 goto finishing;
397 }
398
399 dma_addr = dma_map_page(&bnad->pcidev->dev, page, page_offset,
400 unmap_q->map_size, DMA_FROM_DEVICE);
401
402 unmap->page = page;
403 unmap->page_offset = page_offset;
404 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
405 unmap->vector.len = unmap_q->map_size;
406 page_offset += unmap_q->map_size;
407
408 if (page_offset < alloc_size)
409 unmap_q->reuse_pi = prod;
410 else
411 unmap_q->reuse_pi = -1;
412
413 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
414 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
415 BNA_QE_INDX_INC(prod, q_depth);
416 alloced++;
417 }
418
419finishing:
420 if (likely(alloced)) {
421 rcb->producer_index = prod;
422 smp_mb();
423 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
424 bna_rxq_prod_indx_doorbell(rcb);
8b230ed8 425 }
30f9fc94
RM		 426
427 return alloced;
8b230ed8
RM		 428}
429
30f9fc94
RM		 430static u32
431bnad_rxq_refill_skb(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
8b230ed8 432{
30f9fc94
RM		 433 u32 alloced, prod, q_depth, buff_sz;
434 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
5216562a 435 struct bnad_rx_unmap *unmap;
8b230ed8
RM		 436 struct bna_rxq_entry *rxent;
437 struct sk_buff *skb;
438 dma_addr_t dma_addr;
439
5216562a 440 buff_sz = rcb->rxq->buffer_size;
5216562a
RM		 441 prod = rcb->producer_index;
442 q_depth = rcb->q_depth;
8b230ed8 443
30f9fc94
RM		 444 alloced = 0;
445 while (nalloc--) {
446 unmap = &unmap_q->unmap[prod];
447
448 skb = netdev_alloc_skb_ip_align(bnad->netdev, buff_sz);
449
8b230ed8
RM		 450 if (unlikely(!skb)) {
451 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
3caa1e95 452 rcb->rxq->rxbuf_alloc_failed++;
8b230ed8
RM		 453 goto finishing;
454 }
5ea74318 455 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
5216562a 456 buff_sz, DMA_FROM_DEVICE);
8b230ed8 457
5216562a
RM		 458 unmap->skb = skb;
459 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
460 unmap->vector.len = buff_sz;
30f9fc94
RM		 461
462 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
463 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
5216562a 464 BNA_QE_INDX_INC(prod, q_depth);
8b230ed8
RM		 465 alloced++;
466 }
467
468finishing:
469 if (likely(alloced)) {
5216562a 470 rcb->producer_index = prod;
8b230ed8 471 smp_mb();
5bcf6ac0 472 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
be7fa326 473 bna_rxq_prod_indx_doorbell(rcb);
8b230ed8 474 }
30f9fc94
RM		 475
476 return alloced;
477}
478
479static inline void
480bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb)
481{
482 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
483 u32 to_alloc;
484
485 to_alloc = BNA_QE_FREE_CNT(rcb, rcb->q_depth);
486 if (!(to_alloc >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT))
487 return;
488
e29aa339 489 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
30f9fc94 490 bnad_rxq_refill_skb(bnad, rcb, to_alloc);
e29aa339
RM		 491 else
492 bnad_rxq_refill_page(bnad, rcb, to_alloc);
8b230ed8
RM		 493}
494
5e46631f
RM		 495#define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
496 BNA_CQ_EF_IPV6 | \
497 BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \
498 BNA_CQ_EF_L4_CKSUM_OK)
499
500#define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
501 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
502#define flags_tcp6 (BNA_CQ_EF_IPV6 | \
503 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
504#define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
505 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
506#define flags_udp6 (BNA_CQ_EF_IPV6 | \
507 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
508
e29aa339
RM		 509static void
510bnad_cq_drop_packet(struct bnad *bnad, struct bna_rcb *rcb,
511 u32 sop_ci, u32 nvecs)
30f9fc94 512{
e29aa339
RM		 513 struct bnad_rx_unmap_q *unmap_q;
514 struct bnad_rx_unmap *unmap;
515 u32 ci, vec;
30f9fc94 516
e29aa339
RM		 517 unmap_q = rcb->unmap_q;
518 for (vec = 0, ci = sop_ci; vec < nvecs; vec++) {
519 unmap = &unmap_q->unmap[ci];
520 BNA_QE_INDX_INC(ci, rcb->q_depth);
521
522 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
523 bnad_rxq_cleanup_skb(bnad, unmap);
524 else
525 bnad_rxq_cleanup_page(bnad, unmap);
526 }
527}
528
529static void
530bnad_cq_setup_skb_frags(struct bna_rcb *rcb, struct sk_buff *skb,
531 u32 sop_ci, u32 nvecs, u32 last_fraglen)
532{
533 struct bnad *bnad;
534 u32 ci, vec, len, totlen = 0;
535 struct bnad_rx_unmap_q *unmap_q;
536 struct bnad_rx_unmap *unmap;
537
538 unmap_q = rcb->unmap_q;
539 bnad = rcb->bnad;
66f9513a
RM		 540
541 /* prefetch header */
542 prefetch(page_address(unmap_q->unmap[sop_ci].page) +
543 unmap_q->unmap[sop_ci].page_offset);
544
e29aa339
RM		 545 for (vec = 1, ci = sop_ci; vec <= nvecs; vec++) {
546 unmap = &unmap_q->unmap[ci];
547 BNA_QE_INDX_INC(ci, rcb->q_depth);
30f9fc94
RM		 548
549 dma_unmap_page(&bnad->pcidev->dev,
550 dma_unmap_addr(&unmap->vector, dma_addr),
551 unmap->vector.len, DMA_FROM_DEVICE);
e29aa339
RM		 552
553 len = (vec == nvecs) ?
554 last_fraglen : unmap->vector.len;
555 totlen += len;
556
30f9fc94 557 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e29aa339 558 unmap->page, unmap->page_offset, len);
30f9fc94
RM		 559
560 unmap->page = NULL;
561 unmap->vector.len = 0;
30f9fc94
RM		 562 }
563
e29aa339
RM		 564 skb->len += totlen;
565 skb->data_len += totlen;
566 skb->truesize += totlen;
567}
568
569static inline void
570bnad_cq_setup_skb(struct bnad *bnad, struct sk_buff *skb,
571 struct bnad_rx_unmap *unmap, u32 len)
572{
573 prefetch(skb->data);
30f9fc94
RM		 574
575 dma_unmap_single(&bnad->pcidev->dev,
576 dma_unmap_addr(&unmap->vector, dma_addr),
577 unmap->vector.len, DMA_FROM_DEVICE);
578
e29aa339 579 skb_put(skb, len);
30f9fc94
RM		 580 skb->protocol = eth_type_trans(skb, bnad->netdev);
581
582 unmap->skb = NULL;
583 unmap->vector.len = 0;
30f9fc94
RM		 584}
585
8b230ed8 586static u32
b3cc6e88 587bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget)
8b230ed8 588{
e29aa339 589 struct bna_cq_entry *cq, *cmpl, *next_cmpl;
8b230ed8 590 struct bna_rcb *rcb = NULL;
30f9fc94 591 struct bnad_rx_unmap_q *unmap_q;
e29aa339
RM		 592 struct bnad_rx_unmap *unmap = NULL;
593 struct sk_buff *skb = NULL;
8b230ed8 594 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
30f9fc94 595 struct bnad_rx_ctrl *rx_ctrl = ccb->ctrl;
e29aa339
RM		 596 u32 packets = 0, len = 0, totlen = 0;
597 u32 pi, vec, sop_ci = 0, nvecs = 0;
598 u32 flags, masked_flags;
078086f3 599
8b230ed8 600 prefetch(bnad->netdev);
5216562a
RM		 601
602 cq = ccb->sw_q;
603 cmpl = &cq[ccb->producer_index];
604
17a30a14
RM		 605 while (packets < budget) {
606 if (!cmpl->valid)
607 break;
608 /* The 'valid' field is set by the adapter, only after writing
609 * the other fields of completion entry. Hence, do not load
610 * other fields of completion entry *before* the 'valid' is
611 * loaded. Adding the rmb() here prevents the compiler and/or
612 * CPU from reordering the reads which would potentially result
613 * in reading stale values in completion entry.
614 */
615 rmb();
616
8b230ed8
RM		 617 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
618
078086f3 619 if (bna_is_small_rxq(cmpl->rxq_id))
8b230ed8 620 rcb = ccb->rcb[1];
078086f3
RM		 621 else
622 rcb = ccb->rcb[0];
8b230ed8
RM		 623
624 unmap_q = rcb->unmap_q;
625
e29aa339
RM		 626 /* start of packet ci */
627 sop_ci = rcb->consumer_index;
628
629 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) {
630 unmap = &unmap_q->unmap[sop_ci];
631 skb = unmap->skb;
632 } else {
633 skb = napi_get_frags(&rx_ctrl->napi);
634 if (unlikely(!skb))
635 break;
636 }
637 prefetch(skb);
638
639 flags = ntohl(cmpl->flags);
640 len = ntohs(cmpl->length);
641 totlen = len;
642 nvecs = 1;
643
644 /* Check all the completions for this frame.
645 * busy-wait doesn't help much, break here.
646 */
647 if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q->type) &&
648 (flags & BNA_CQ_EF_EOP) == 0) {
649 pi = ccb->producer_index;
650 do {
651 BNA_QE_INDX_INC(pi, ccb->q_depth);
652 next_cmpl = &cq[pi];
653
654 if (!next_cmpl->valid)
655 break;
17a30a14
RM		 656 /* The 'valid' field is set by the adapter, only
657 * after writing the other fields of completion
658 * entry. Hence, do not load other fields of
659 * completion entry *before* the 'valid' is
660 * loaded. Adding the rmb() here prevents the
661 * compiler and/or CPU from reordering the reads
662 * which would potentially result in reading
663 * stale values in completion entry.
664 */
665 rmb();
5216562a 666
e29aa339
RM		 667 len = ntohs(next_cmpl->length);
668 flags = ntohl(next_cmpl->flags);
669
670 nvecs++;
671 totlen += len;
672 } while ((flags & BNA_CQ_EF_EOP) == 0);
673
674 if (!next_cmpl->valid)
675 break;
676 }
677
678 /* TODO: BNA_CQ_EF_LOCAL ? */
679 if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR |
680 BNA_CQ_EF_FCS_ERROR |
681 BNA_CQ_EF_TOO_LONG))) {
682 bnad_cq_drop_packet(bnad, rcb, sop_ci, nvecs);
8b230ed8 683 rcb->rxq->rx_packets_with_error++;
e29aa339 684
8b230ed8
RM		 685 goto next;
686 }
687
e29aa339
RM		 688 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
689 bnad_cq_setup_skb(bnad, skb, unmap, len);
690 else
691 bnad_cq_setup_skb_frags(rcb, skb, sop_ci, nvecs, len);
30f9fc94 692
e29aa339
RM		 693 packets++;
694 rcb->rxq->rx_packets++;
695 rcb->rxq->rx_bytes += totlen;
696 ccb->bytes_per_intr += totlen;
5e46631f
RM		 697
698 masked_flags = flags & flags_cksum_prot_mask;
699
8b230ed8 700 if (likely
e5ee20e7 701 ((bnad->netdev->features & NETIF_F_RXCSUM) &&
5e46631f
RM		 702 ((masked_flags == flags_tcp4) ||
703 (masked_flags == flags_udp4) ||
704 (masked_flags == flags_tcp6) ||
705 (masked_flags == flags_udp6))))
8b230ed8
RM		 706 skb->ip_summed = CHECKSUM_UNNECESSARY;
707 else
bc8acf2c 708 skb_checksum_none_assert(skb);
8b230ed8 709
877767dc
IV		 710 if ((flags & BNA_CQ_EF_VLAN) &&
711 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX))
86a9bad3 712 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cmpl->vlan_tag));
f859d7cb 713
e29aa339 714 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
f859d7cb 715 netif_receive_skb(skb);
e29aa339
RM		 716 else
717 napi_gro_frags(&rx_ctrl->napi);
8b230ed8
RM		 718
719next:
e29aa339
RM		 720 BNA_QE_INDX_ADD(rcb->consumer_index, nvecs, rcb->q_depth);
721 for (vec = 0; vec < nvecs; vec++) {
722 cmpl = &cq[ccb->producer_index];
723 cmpl->valid = 0;
724 BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth);
725 }
30f9fc94 726 cmpl = &cq[ccb->producer_index];
8b230ed8
RM		 727 }
728
30f9fc94 729 napi_gro_flush(&rx_ctrl->napi, false);
2be67144 730 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
271e8b79
RM		 731 bna_ib_ack_disable_irq(ccb->i_dbell, packets);
732
5216562a 733 bnad_rxq_post(bnad, ccb->rcb[0]);
2be67144 734 if (ccb->rcb[1])
5216562a 735 bnad_rxq_post(bnad, ccb->rcb[1]);
078086f3 736
8b230ed8
RM		 737 return packets;
738}
739
8b230ed8
RM		 740static void
741bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
742{
743 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
be7fa326
RM		 744 struct napi_struct *napi = &rx_ctrl->napi;
745
746 if (likely(napi_schedule_prep(napi))) {
be7fa326 747 __napi_schedule(napi);
271e8b79 748 rx_ctrl->rx_schedule++;
8b230ed8 749 }
8b230ed8
RM		 750}
751
752/* MSIX Rx Path Handler */
753static irqreturn_t
754bnad_msix_rx(int irq, void *data)
755{
756 struct bna_ccb *ccb = (struct bna_ccb *)data;
8b230ed8 757
271e8b79
RM		 758 if (ccb) {
759 ((struct bnad_rx_ctrl *)(ccb->ctrl))->rx_intr_ctr++;
2be67144 760 bnad_netif_rx_schedule_poll(ccb->bnad, ccb);
271e8b79 761 }
8b230ed8
RM		 762
763 return IRQ_HANDLED;
764}
765
766/* Interrupt handlers */
767
768/* Mbox Interrupt Handlers */
769static irqreturn_t
770bnad_msix_mbox_handler(int irq, void *data)
771{
772 u32 intr_status;
e2fa6f2e 773 unsigned long flags;
be7fa326 774 struct bnad *bnad = (struct bnad *)data;
8b230ed8 775
8b230ed8 776 spin_lock_irqsave(&bnad->bna_lock, flags);
dfee325a
RM		 777 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
778 spin_unlock_irqrestore(&bnad->bna_lock, flags);
779 return IRQ_HANDLED;
780 }
8b230ed8
RM		 781
782 bna_intr_status_get(&bnad->bna, intr_status);
783
078086f3 784 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
8b230ed8
RM		 785 bna_mbox_handler(&bnad->bna, intr_status);
786
787 spin_unlock_irqrestore(&bnad->bna_lock, flags);
788
8b230ed8
RM		 789 return IRQ_HANDLED;
790}
791
792static irqreturn_t
793bnad_isr(int irq, void *data)
794{
795 int i, j;
796 u32 intr_status;
797 unsigned long flags;
be7fa326 798 struct bnad *bnad = (struct bnad *)data;
8b230ed8
RM		 799 struct bnad_rx_info *rx_info;
800 struct bnad_rx_ctrl *rx_ctrl;
078086f3 801 struct bna_tcb *tcb = NULL;
8b230ed8 802
dfee325a
RM		 803 spin_lock_irqsave(&bnad->bna_lock, flags);
804 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
805 spin_unlock_irqrestore(&bnad->bna_lock, flags);
e2fa6f2e 806 return IRQ_NONE;
dfee325a 807 }
8b230ed8
RM		 808
809 bna_intr_status_get(&bnad->bna, intr_status);
e2fa6f2e 810
dfee325a
RM		 811 if (unlikely(!intr_status)) {
812 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 813 return IRQ_NONE;
dfee325a 814 }
8b230ed8 815
078086f3 816 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
8b230ed8 817 bna_mbox_handler(&bnad->bna, intr_status);
be7fa326 818
8b230ed8
RM		 819 spin_unlock_irqrestore(&bnad->bna_lock, flags);
820
be7fa326
RM		 821 if (!BNA_IS_INTX_DATA_INTR(intr_status))
822 return IRQ_HANDLED;
823
8b230ed8 824 /* Process data interrupts */
be7fa326
RM		 825 /* Tx processing */
826 for (i = 0; i < bnad->num_tx; i++) {
078086f3
RM		 827 for (j = 0; j < bnad->num_txq_per_tx; j++) {
828 tcb = bnad->tx_info[i].tcb[j];
829 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
b3cc6e88 830 bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]);
078086f3 831 }
be7fa326
RM		 832 }
833 /* Rx processing */
8b230ed8
RM		 834 for (i = 0; i < bnad->num_rx; i++) {
835 rx_info = &bnad->rx_info[i];
836 if (!rx_info->rx)
837 continue;
838 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
839 rx_ctrl = &rx_info->rx_ctrl[j];
840 if (rx_ctrl->ccb)
841 bnad_netif_rx_schedule_poll(bnad,
842 rx_ctrl->ccb);
843 }
844 }
8b230ed8
RM		 845 return IRQ_HANDLED;
846}
847
848/*
849 * Called in interrupt / callback context
850 * with bna_lock held, so cfg_flags access is OK
851 */
852static void
853bnad_enable_mbox_irq(struct bnad *bnad)
854{
be7fa326 855 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
e2fa6f2e 856
8b230ed8
RM		 857 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
858}
859
860/*
861 * Called with bnad->bna_lock held b'cos of
862 * bnad->cfg_flags access.
863 */
b7ee31c5 864static void
8b230ed8
RM		 865bnad_disable_mbox_irq(struct bnad *bnad)
866{
be7fa326 867 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
8b230ed8 868
be7fa326
RM		 869 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
870}
8b230ed8 871
be7fa326
RM		 872static void
873bnad_set_netdev_perm_addr(struct bnad *bnad)
874{
875 struct net_device *netdev = bnad->netdev;
e2fa6f2e 876
be7fa326
RM		 877 memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
878 if (is_zero_ether_addr(netdev->dev_addr))
879 memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
8b230ed8
RM		 880}
881
882/* Control Path Handlers */
883
884/* Callbacks */
885void
078086f3 886bnad_cb_mbox_intr_enable(struct bnad *bnad)
8b230ed8
RM		 887{
888 bnad_enable_mbox_irq(bnad);
889}
890
891void
078086f3 892bnad_cb_mbox_intr_disable(struct bnad *bnad)
8b230ed8
RM		 893{
894 bnad_disable_mbox_irq(bnad);
895}
896
897void
078086f3
RM		 898bnad_cb_ioceth_ready(struct bnad *bnad)
899{
900 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
901 complete(&bnad->bnad_completions.ioc_comp);
902}
903
904void
905bnad_cb_ioceth_failed(struct bnad *bnad)
8b230ed8 906{
078086f3 907 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL;
8b230ed8 908 complete(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 909}
910
911void
078086f3 912bnad_cb_ioceth_disabled(struct bnad *bnad)
8b230ed8 913{
078086f3 914 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
8b230ed8 915 complete(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 916}
917
918static void
078086f3 919bnad_cb_enet_disabled(void *arg)
8b230ed8
RM		 920{
921 struct bnad *bnad = (struct bnad *)arg;
922
8b230ed8 923 netif_carrier_off(bnad->netdev);
078086f3 924 complete(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 925}
926
927void
078086f3 928bnad_cb_ethport_link_status(struct bnad *bnad,
8b230ed8
RM		 929 enum bna_link_status link_status)
930{
3db1cd5c 931 bool link_up = false;
8b230ed8
RM		 932
933 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
934
935 if (link_status == BNA_CEE_UP) {
078086f3
RM		 936 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
937 BNAD_UPDATE_CTR(bnad, cee_toggle);
8b230ed8 938 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
078086f3
RM		 939 } else {
940 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
941 BNAD_UPDATE_CTR(bnad, cee_toggle);
8b230ed8 942 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
078086f3 943 }
8b230ed8
RM		 944
945 if (link_up) {
946 if (!netif_carrier_ok(bnad->netdev)) {
078086f3
RM		 947 uint tx_id, tcb_id;
948 printk(KERN_WARNING "bna: %s link up\n",
8b230ed8
RM		 949 bnad->netdev->name);
950 netif_carrier_on(bnad->netdev);
951 BNAD_UPDATE_CTR(bnad, link_toggle);
078086f3
RM		 952 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
953 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx;
954 tcb_id++) {
955 struct bna_tcb *tcb =
956 bnad->tx_info[tx_id].tcb[tcb_id];
957 u32 txq_id;
958 if (!tcb)
959 continue;
960
961 txq_id = tcb->id;
962
963 if (test_bit(BNAD_TXQ_TX_STARTED,
964 &tcb->flags)) {
965 /*
966 * Force an immediate
967 * Transmit Schedule */
968 printk(KERN_INFO "bna: %s %d "
969 "TXQ_STARTED\n",
970 bnad->netdev->name,
971 txq_id);
972 netif_wake_subqueue(
973 bnad->netdev,
974 txq_id);
975 BNAD_UPDATE_CTR(bnad,
976 netif_queue_wakeup);
977 } else {
978 netif_stop_subqueue(
979 bnad->netdev,
980 txq_id);
981 BNAD_UPDATE_CTR(bnad,
982 netif_queue_stop);
983 }
984 }
8b230ed8
RM		 985 }
986 }
987 } else {
988 if (netif_carrier_ok(bnad->netdev)) {
078086f3 989 printk(KERN_WARNING "bna: %s link down\n",
8b230ed8
RM		 990 bnad->netdev->name);
991 netif_carrier_off(bnad->netdev);
992 BNAD_UPDATE_CTR(bnad, link_toggle);
993 }
994 }
995}
996
997static void
078086f3 998bnad_cb_tx_disabled(void *arg, struct bna_tx *tx)
8b230ed8
RM		 999{
1000 struct bnad *bnad = (struct bnad *)arg;
1001
1002 complete(&bnad->bnad_completions.tx_comp);
1003}
1004
1005static void
1006bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
1007{
1008 struct bnad_tx_info *tx_info =
1009 (struct bnad_tx_info *)tcb->txq->tx->priv;
8b230ed8 1010
5216562a 1011 tcb->priv = tcb;
8b230ed8 1012 tx_info->tcb[tcb->id] = tcb;
8b230ed8
RM		 1013}
1014
1015static void
1016bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
1017{
1018 struct bnad_tx_info *tx_info =
1019 (struct bnad_tx_info *)tcb->txq->tx->priv;
1020
1021 tx_info->tcb[tcb->id] = NULL;
01b54b14 1022 tcb->priv = NULL;
8b230ed8
RM		 1023}
1024
8b230ed8
RM		 1025static void
1026bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
1027{
1028 struct bnad_rx_info *rx_info =
1029 (struct bnad_rx_info *)ccb->cq->rx->priv;
1030
1031 rx_info->rx_ctrl[ccb->id].ccb = ccb;
1032 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
1033}
1034
1035static void
1036bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
1037{
1038 struct bnad_rx_info *rx_info =
1039 (struct bnad_rx_info *)ccb->cq->rx->priv;
1040
1041 rx_info->rx_ctrl[ccb->id].ccb = NULL;
1042}
1043
1044static void
078086f3 1045bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
8b230ed8
RM		 1046{
1047 struct bnad_tx_info *tx_info =
078086f3
RM		 1048 (struct bnad_tx_info *)tx->priv;
1049 struct bna_tcb *tcb;
1050 u32 txq_id;
1051 int i;
8b230ed8 1052
078086f3
RM		 1053 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1054 tcb = tx_info->tcb[i];
1055 if (!tcb)
1056 continue;
1057 txq_id = tcb->id;
1058 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
1059 netif_stop_subqueue(bnad->netdev, txq_id);
1060 printk(KERN_INFO "bna: %s %d TXQ_STOPPED\n",
1061 bnad->netdev->name, txq_id);
1062 }
8b230ed8
RM		 1063}
1064
1065static void
078086f3 1066bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
8b230ed8 1067{
078086f3
RM		 1068 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1069 struct bna_tcb *tcb;
078086f3
RM		 1070 u32 txq_id;
1071 int i;
8b230ed8 1072
078086f3
RM		 1073 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1074 tcb = tx_info->tcb[i];
1075 if (!tcb)
1076 continue;
1077 txq_id = tcb->id;
8b230ed8 1078
01b54b14 1079 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags));
078086f3 1080 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
01b54b14 1081 BUG_ON(*(tcb->hw_consumer_index) != 0);
078086f3
RM		 1082
1083 if (netif_carrier_ok(bnad->netdev)) {
1084 printk(KERN_INFO "bna: %s %d TXQ_STARTED\n",
1085 bnad->netdev->name, txq_id);
1086 netif_wake_subqueue(bnad->netdev, txq_id);
1087 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
1088 }
1089 }
be7fa326
RM		 1090
1091 /*
078086f3 1092 * Workaround for first ioceth enable failure & we
be7fa326
RM		 1093 * get a 0 MAC address. We try to get the MAC address
1094 * again here.
1095 */
1096 if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
078086f3 1097 bna_enet_perm_mac_get(&bnad->bna.enet, &bnad->perm_addr);
be7fa326
RM		 1098 bnad_set_netdev_perm_addr(bnad);
1099 }
be7fa326
RM		 1100}
1101
01b54b14
JH		 1102/*
1103 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
1104 */
1105static void
1106bnad_tx_cleanup(struct delayed_work *work)
1107{
1108 struct bnad_tx_info *tx_info =
1109 container_of(work, struct bnad_tx_info, tx_cleanup_work);
1110 struct bnad *bnad = NULL;
01b54b14
JH		 1111 struct bna_tcb *tcb;
1112 unsigned long flags;
5216562a 1113 u32 i, pending = 0;
01b54b14
JH		 1114
1115 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1116 tcb = tx_info->tcb[i];
1117 if (!tcb)
1118 continue;
1119
1120 bnad = tcb->bnad;
1121
1122 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
1123 pending++;
1124 continue;
1125 }
1126
b3cc6e88 1127 bnad_txq_cleanup(bnad, tcb);
01b54b14 1128
01b54b14
JH		 1129 smp_mb__before_clear_bit();
1130 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
1131 }
1132
1133 if (pending) {
1134 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work,
1135 msecs_to_jiffies(1));
1136 return;
1137 }
1138
1139 spin_lock_irqsave(&bnad->bna_lock, flags);
1140 bna_tx_cleanup_complete(tx_info->tx);
1141 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1142}
1143
be7fa326 1144static void
078086f3 1145bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
be7fa326 1146{
078086f3
RM		 1147 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1148 struct bna_tcb *tcb;
1149 int i;
1150
1151 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1152 tcb = tx_info->tcb[i];
1153 if (!tcb)
1154 continue;
1155 }
1156
01b54b14 1157 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0);
8b230ed8
RM		 1158}
1159
5bcf6ac0
RM		 1160static void
1161bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx)
1162{
1163 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1164 struct bna_ccb *ccb;
1165 struct bnad_rx_ctrl *rx_ctrl;
1166 int i;
1167
1168 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1169 rx_ctrl = &rx_info->rx_ctrl[i];
1170 ccb = rx_ctrl->ccb;
1171 if (!ccb)
1172 continue;
1173
1174 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags);
1175
1176 if (ccb->rcb[1])
1177 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags);
1178 }
1179}
1180
01b54b14
JH		 1181/*
1182 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
1183 */
1184static void
1185bnad_rx_cleanup(void *work)
1186{
1187 struct bnad_rx_info *rx_info =
1188 container_of(work, struct bnad_rx_info, rx_cleanup_work);
1189 struct bnad_rx_ctrl *rx_ctrl;
1190 struct bnad *bnad = NULL;
1191 unsigned long flags;
5216562a 1192 u32 i;
01b54b14
JH		 1193
1194 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1195 rx_ctrl = &rx_info->rx_ctrl[i];
1196
1197 if (!rx_ctrl->ccb)
1198 continue;
1199
1200 bnad = rx_ctrl->ccb->bnad;
1201
1202 /*
1203 * Wait till the poll handler has exited
1204 * and nothing can be scheduled anymore
1205 */
1206 napi_disable(&rx_ctrl->napi);
1207
b3cc6e88
JH		 1208 bnad_cq_cleanup(bnad, rx_ctrl->ccb);
1209 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]);
01b54b14 1210 if (rx_ctrl->ccb->rcb[1])
b3cc6e88 1211 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]);
01b54b14
JH		 1212 }
1213
1214 spin_lock_irqsave(&bnad->bna_lock, flags);
1215 bna_rx_cleanup_complete(rx_info->rx);
1216 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1217}
1218
8b230ed8 1219static void
078086f3 1220bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1221{
078086f3
RM		 1222 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1223 struct bna_ccb *ccb;
1224 struct bnad_rx_ctrl *rx_ctrl;
1225 int i;
1226
772b5235 1227 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
078086f3
RM		 1228 rx_ctrl = &rx_info->rx_ctrl[i];
1229 ccb = rx_ctrl->ccb;
1230 if (!ccb)
1231 continue;
1232
1233 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
1234
1235 if (ccb->rcb[1])
1236 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
078086f3 1237 }
be7fa326 1238
01b54b14 1239 queue_work(bnad->work_q, &rx_info->rx_cleanup_work);
8b230ed8
RM		 1240}
1241
1242static void
078086f3 1243bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1244{
078086f3
RM		 1245 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1246 struct bna_ccb *ccb;
1247 struct bna_rcb *rcb;
1248 struct bnad_rx_ctrl *rx_ctrl;
30f9fc94 1249 int i, j;
be7fa326 1250
772b5235 1251 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
078086f3
RM		 1252 rx_ctrl = &rx_info->rx_ctrl[i];
1253 ccb = rx_ctrl->ccb;
1254 if (!ccb)
1255 continue;
be7fa326 1256
01b54b14 1257 napi_enable(&rx_ctrl->napi);
8b230ed8 1258
078086f3
RM		 1259 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
1260 rcb = ccb->rcb[j];
1261 if (!rcb)
1262 continue;
078086f3 1263
30f9fc94 1264 bnad_rxq_alloc_init(bnad, rcb);
078086f3 1265 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
5bcf6ac0 1266 set_bit(BNAD_RXQ_POST_OK, &rcb->flags);
5216562a 1267 bnad_rxq_post(bnad, rcb);
078086f3 1268 }
8b230ed8
RM		 1269 }
1270}
1271
1272static void
078086f3 1273bnad_cb_rx_disabled(void *arg, struct bna_rx *rx)
8b230ed8
RM		 1274{
1275 struct bnad *bnad = (struct bnad *)arg;
1276
1277 complete(&bnad->bnad_completions.rx_comp);
1278}
1279
1280static void
078086f3 1281bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1282{
078086f3 1283 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS;
8b230ed8
RM		 1284 complete(&bnad->bnad_completions.mcast_comp);
1285}
1286
1287void
1288bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
1289 struct bna_stats *stats)
1290{
1291 if (status == BNA_CB_SUCCESS)
1292 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
1293
1294 if (!netif_running(bnad->netdev) ||
1295 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1296 return;
1297
1298 mod_timer(&bnad->stats_timer,
1299 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1300}
1301
078086f3
RM		 1302static void
1303bnad_cb_enet_mtu_set(struct bnad *bnad)
1304{
1305 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS;
1306 complete(&bnad->bnad_completions.mtu_comp);
1307}
1308
72a9730b
KG		 1309void
1310bnad_cb_completion(void *arg, enum bfa_status status)
1311{
1312 struct bnad_iocmd_comp *iocmd_comp =
1313 (struct bnad_iocmd_comp *)arg;
1314
1315 iocmd_comp->comp_status = (u32) status;
1316 complete(&iocmd_comp->comp);
1317}
1318
8b230ed8
RM		 1319/* Resource allocation, free functions */
1320
1321static void
1322bnad_mem_free(struct bnad *bnad,
1323 struct bna_mem_info *mem_info)
1324{
1325 int i;
1326 dma_addr_t dma_pa;
1327
1328 if (mem_info->mdl == NULL)
1329 return;
1330
1331 for (i = 0; i < mem_info->num; i++) {
1332 if (mem_info->mdl[i].kva != NULL) {
1333 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1334 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1335 dma_pa);
5ea74318
IV		 1336 dma_free_coherent(&bnad->pcidev->dev,
1337 mem_info->mdl[i].len,
1338 mem_info->mdl[i].kva, dma_pa);
8b230ed8
RM		 1339 } else
1340 kfree(mem_info->mdl[i].kva);
1341 }
1342 }
1343 kfree(mem_info->mdl);
1344 mem_info->mdl = NULL;
1345}
1346
1347static int
1348bnad_mem_alloc(struct bnad *bnad,
1349 struct bna_mem_info *mem_info)
1350{
1351 int i;
1352 dma_addr_t dma_pa;
1353
1354 if ((mem_info->num == 0) || (mem_info->len == 0)) {
1355 mem_info->mdl = NULL;
1356 return 0;
1357 }
1358
1359 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1360 GFP_KERNEL);
1361 if (mem_info->mdl == NULL)
1362 return -ENOMEM;
1363
1364 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1365 for (i = 0; i < mem_info->num; i++) {
1366 mem_info->mdl[i].len = mem_info->len;
1367 mem_info->mdl[i].kva =
5ea74318 1368 dma_alloc_coherent(&bnad->pcidev->dev,
1f9061d2
JP		 1369 mem_info->len, &dma_pa,
1370 GFP_KERNEL);
8b230ed8
RM		 1371 if (mem_info->mdl[i].kva == NULL)
1372 goto err_return;
1373
1374 BNA_SET_DMA_ADDR(dma_pa,
1375 &(mem_info->mdl[i].dma));
1376 }
1377 } else {
1378 for (i = 0; i < mem_info->num; i++) {
1379 mem_info->mdl[i].len = mem_info->len;
1380 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1381 GFP_KERNEL);
1382 if (mem_info->mdl[i].kva == NULL)
1383 goto err_return;
1384 }
1385 }
1386
1387 return 0;
1388
1389err_return:
1390 bnad_mem_free(bnad, mem_info);
1391 return -ENOMEM;
1392}
1393
1394/* Free IRQ for Mailbox */
1395static void
078086f3 1396bnad_mbox_irq_free(struct bnad *bnad)
8b230ed8
RM		 1397{
1398 int irq;
1399 unsigned long flags;
1400
8b230ed8 1401 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 1402 bnad_disable_mbox_irq(bnad);
e2fa6f2e 1403 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1404
1405 irq = BNAD_GET_MBOX_IRQ(bnad);
be7fa326 1406 free_irq(irq, bnad);
8b230ed8
RM		 1407}
1408
1409/*
1410 * Allocates IRQ for Mailbox, but keep it disabled
1411 * This will be enabled once we get the mbox enable callback
1412 * from bna
1413 */
1414static int
078086f3 1415bnad_mbox_irq_alloc(struct bnad *bnad)
8b230ed8 1416{
0120b99c
RM		 1417 int err = 0;
1418 unsigned long irq_flags, flags;
8b230ed8 1419 u32 irq;
0120b99c 1420 irq_handler_t irq_handler;
8b230ed8 1421
8b230ed8
RM		 1422 spin_lock_irqsave(&bnad->bna_lock, flags);
1423 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1424 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
8811e267 1425 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
8279171a 1426 irq_flags = 0;
8b230ed8
RM		 1427 } else {
1428 irq_handler = (irq_handler_t)bnad_isr;
1429 irq = bnad->pcidev->irq;
5f77898d 1430 irq_flags = IRQF_SHARED;
8b230ed8 1431 }
8811e267 1432
8b230ed8 1433 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1434 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1435
e2fa6f2e
RM		 1436 /*
1437 * Set the Mbox IRQ disable flag, so that the IRQ handler
1438 * called from request_irq() for SHARED IRQs do not execute
1439 */
1440 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1441
be7fa326
RM		 1442 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1443
8279171a 1444 err = request_irq(irq, irq_handler, irq_flags,
be7fa326 1445 bnad->mbox_irq_name, bnad);
e2fa6f2e 1446
be7fa326 1447 return err;
8b230ed8
RM		 1448}
1449
1450static void
1451bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1452{
1453 kfree(intr_info->idl);
1454 intr_info->idl = NULL;
1455}
1456
1457/* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1458static int
1459bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
078086f3 1460 u32 txrx_id, struct bna_intr_info *intr_info)
8b230ed8
RM		 1461{
1462 int i, vector_start = 0;
1463 u32 cfg_flags;
1464 unsigned long flags;
1465
1466 spin_lock_irqsave(&bnad->bna_lock, flags);
1467 cfg_flags = bnad->cfg_flags;
1468 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1469
1470 if (cfg_flags & BNAD_CF_MSIX) {
1471 intr_info->intr_type = BNA_INTR_T_MSIX;
1472 intr_info->idl = kcalloc(intr_info->num,
1473 sizeof(struct bna_intr_descr),
1474 GFP_KERNEL);
1475 if (!intr_info->idl)
1476 return -ENOMEM;
1477
1478 switch (src) {
1479 case BNAD_INTR_TX:
8811e267 1480 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id;
8b230ed8
RM		 1481 break;
1482
1483 case BNAD_INTR_RX:
8811e267
RM		 1484 vector_start = BNAD_MAILBOX_MSIX_VECTORS +
1485 (bnad->num_tx * bnad->num_txq_per_tx) +
8b230ed8
RM		 1486 txrx_id;
1487 break;
1488
1489 default:
1490 BUG();
1491 }
1492
1493 for (i = 0; i < intr_info->num; i++)
1494 intr_info->idl[i].vector = vector_start + i;
1495 } else {
1496 intr_info->intr_type = BNA_INTR_T_INTX;
1497 intr_info->num = 1;
1498 intr_info->idl = kcalloc(intr_info->num,
1499 sizeof(struct bna_intr_descr),
1500 GFP_KERNEL);
1501 if (!intr_info->idl)
1502 return -ENOMEM;
1503
1504 switch (src) {
1505 case BNAD_INTR_TX:
8811e267 1506 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK;
8b230ed8
RM		 1507 break;
1508
1509 case BNAD_INTR_RX:
8811e267 1510 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK;
8b230ed8
RM		 1511 break;
1512 }
1513 }
1514 return 0;
1515}
1516
1aa8b471 1517/* NOTE: Should be called for MSIX only
8b230ed8
RM		 1518 * Unregisters Tx MSIX vector(s) from the kernel
1519 */
1520static void
1521bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1522 int num_txqs)
1523{
1524 int i;
1525 int vector_num;
1526
1527 for (i = 0; i < num_txqs; i++) {
1528 if (tx_info->tcb[i] == NULL)
1529 continue;
1530
1531 vector_num = tx_info->tcb[i]->intr_vector;
1532 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1533 }
1534}
1535
1aa8b471 1536/* NOTE: Should be called for MSIX only
8b230ed8
RM		 1537 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1538 */
1539static int
1540bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
078086f3 1541 u32 tx_id, int num_txqs)
8b230ed8
RM		 1542{
1543 int i;
1544 int err;
1545 int vector_num;
1546
1547 for (i = 0; i < num_txqs; i++) {
1548 vector_num = tx_info->tcb[i]->intr_vector;
1549 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1550 tx_id + tx_info->tcb[i]->id);
1551 err = request_irq(bnad->msix_table[vector_num].vector,
1552 (irq_handler_t)bnad_msix_tx, 0,
1553 tx_info->tcb[i]->name,
1554 tx_info->tcb[i]);
1555 if (err)
1556 goto err_return;
1557 }
1558
1559 return 0;
1560
1561err_return:
1562 if (i > 0)
1563 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1564 return -1;
1565}
1566
1aa8b471 1567/* NOTE: Should be called for MSIX only
8b230ed8
RM		 1568 * Unregisters Rx MSIX vector(s) from the kernel
1569 */
1570static void
1571bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1572 int num_rxps)
1573{
1574 int i;
1575 int vector_num;
1576
1577 for (i = 0; i < num_rxps; i++) {
1578 if (rx_info->rx_ctrl[i].ccb == NULL)
1579 continue;
1580
1581 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1582 free_irq(bnad->msix_table[vector_num].vector,
1583 rx_info->rx_ctrl[i].ccb);
1584 }
1585}
1586
1aa8b471 1587/* NOTE: Should be called for MSIX only
8b230ed8
RM		 1588 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1589 */
1590static int
1591bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
078086f3 1592 u32 rx_id, int num_rxps)
8b230ed8
RM		 1593{
1594 int i;
1595 int err;
1596 int vector_num;
1597
1598 for (i = 0; i < num_rxps; i++) {
1599 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1600 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1601 bnad->netdev->name,
1602 rx_id + rx_info->rx_ctrl[i].ccb->id);
1603 err = request_irq(bnad->msix_table[vector_num].vector,
1604 (irq_handler_t)bnad_msix_rx, 0,
1605 rx_info->rx_ctrl[i].ccb->name,
1606 rx_info->rx_ctrl[i].ccb);
1607 if (err)
1608 goto err_return;
1609 }
1610
1611 return 0;
1612
1613err_return:
1614 if (i > 0)
1615 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1616 return -1;
1617}
1618
1619/* Free Tx object Resources */
1620static void
1621bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1622{
1623 int i;
1624
1625 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1626 if (res_info[i].res_type == BNA_RES_T_MEM)
1627 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1628 else if (res_info[i].res_type == BNA_RES_T_INTR)
1629 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1630 }
1631}
1632
1633/* Allocates memory and interrupt resources for Tx object */
1634static int
1635bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
078086f3 1636 u32 tx_id)
8b230ed8
RM		 1637{
1638 int i, err = 0;
1639
1640 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1641 if (res_info[i].res_type == BNA_RES_T_MEM)
1642 err = bnad_mem_alloc(bnad,
1643 &res_info[i].res_u.mem_info);
1644 else if (res_info[i].res_type == BNA_RES_T_INTR)
1645 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1646 &res_info[i].res_u.intr_info);
1647 if (err)
1648 goto err_return;
1649 }
1650 return 0;
1651
1652err_return:
1653 bnad_tx_res_free(bnad, res_info);
1654 return err;
1655}
1656
1657/* Free Rx object Resources */
1658static void
1659bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1660{
1661 int i;
1662
1663 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1664 if (res_info[i].res_type == BNA_RES_T_MEM)
1665 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1666 else if (res_info[i].res_type == BNA_RES_T_INTR)
1667 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1668 }
1669}
1670
1671/* Allocates memory and interrupt resources for Rx object */
1672static int
1673bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1674 uint rx_id)
1675{
1676 int i, err = 0;
1677
1678 /* All memory needs to be allocated before setup_ccbs */
1679 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1680 if (res_info[i].res_type == BNA_RES_T_MEM)
1681 err = bnad_mem_alloc(bnad,
1682 &res_info[i].res_u.mem_info);
1683 else if (res_info[i].res_type == BNA_RES_T_INTR)
1684 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1685 &res_info[i].res_u.intr_info);
1686 if (err)
1687 goto err_return;
1688 }
1689 return 0;
1690
1691err_return:
1692 bnad_rx_res_free(bnad, res_info);
1693 return err;
1694}
1695
1696/* Timer callbacks */
1697/* a) IOC timer */
1698static void
1699bnad_ioc_timeout(unsigned long data)
1700{
1701 struct bnad *bnad = (struct bnad *)data;
1702 unsigned long flags;
1703
1704 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1705 bfa_nw_ioc_timeout((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1706 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1707}
1708
1709static void
1710bnad_ioc_hb_check(unsigned long data)
1711{
1712 struct bnad *bnad = (struct bnad *)data;
1713 unsigned long flags;
1714
1715 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1716 bfa_nw_ioc_hb_check((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1717 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1718}
1719
1720static void
1d32f769 1721bnad_iocpf_timeout(unsigned long data)
8b230ed8
RM		 1722{
1723 struct bnad *bnad = (struct bnad *)data;
1724 unsigned long flags;
1725
1726 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1727 bfa_nw_iocpf_timeout((void *) &bnad->bna.ioceth.ioc);
1d32f769
RM		 1728 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1729}
1730
1731static void
1732bnad_iocpf_sem_timeout(unsigned long data)
1733{
1734 struct bnad *bnad = (struct bnad *)data;
1735 unsigned long flags;
1736
1737 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1738 bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.ioceth.ioc);
8b230ed8
RM		 1739 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1740}
1741
1742/*
1743 * All timer routines use bnad->bna_lock to protect against
1744 * the following race, which may occur in case of no locking:
0120b99c 1745 * Time CPU m CPU n
8b230ed8
RM		 1746 * 0 1 = test_bit
1747 * 1 clear_bit
1748 * 2 del_timer_sync
1749 * 3 mod_timer
1750 */
1751
1752/* b) Dynamic Interrupt Moderation Timer */
1753static void
1754bnad_dim_timeout(unsigned long data)
1755{
1756 struct bnad *bnad = (struct bnad *)data;
1757 struct bnad_rx_info *rx_info;
1758 struct bnad_rx_ctrl *rx_ctrl;
1759 int i, j;
1760 unsigned long flags;
1761
1762 if (!netif_carrier_ok(bnad->netdev))
1763 return;
1764
1765 spin_lock_irqsave(&bnad->bna_lock, flags);
1766 for (i = 0; i < bnad->num_rx; i++) {
1767 rx_info = &bnad->rx_info[i];
1768 if (!rx_info->rx)
1769 continue;
1770 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1771 rx_ctrl = &rx_info->rx_ctrl[j];
1772 if (!rx_ctrl->ccb)
1773 continue;
1774 bna_rx_dim_update(rx_ctrl->ccb);
1775 }
1776 }
1777
1778 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1779 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1780 mod_timer(&bnad->dim_timer,
1781 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1782 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1783}
1784
1785/* c) Statistics Timer */
1786static void
1787bnad_stats_timeout(unsigned long data)
1788{
1789 struct bnad *bnad = (struct bnad *)data;
1790 unsigned long flags;
1791
1792 if (!netif_running(bnad->netdev) ||
1793 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1794 return;
1795
1796 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1797 bna_hw_stats_get(&bnad->bna);
8b230ed8
RM		 1798 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1799}
1800
1801/*
1802 * Set up timer for DIM
1803 * Called with bnad->bna_lock held
1804 */
1805void
1806bnad_dim_timer_start(struct bnad *bnad)
1807{
1808 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1809 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1810 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1811 (unsigned long)bnad);
1812 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1813 mod_timer(&bnad->dim_timer,
1814 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1815 }
1816}
1817
1818/*
1819 * Set up timer for statistics
1820 * Called with mutex_lock(&bnad->conf_mutex) held
1821 */
1822static void
1823bnad_stats_timer_start(struct bnad *bnad)
1824{
1825 unsigned long flags;
1826
1827 spin_lock_irqsave(&bnad->bna_lock, flags);
1828 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1829 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1830 (unsigned long)bnad);
1831 mod_timer(&bnad->stats_timer,
1832 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1833 }
1834 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1835}
1836
1837/*
1838 * Stops the stats timer
1839 * Called with mutex_lock(&bnad->conf_mutex) held
1840 */
1841static void
1842bnad_stats_timer_stop(struct bnad *bnad)
1843{
1844 int to_del = 0;
1845 unsigned long flags;
1846
1847 spin_lock_irqsave(&bnad->bna_lock, flags);
1848 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1849 to_del = 1;
1850 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1851 if (to_del)
1852 del_timer_sync(&bnad->stats_timer);
1853}
1854
1855/* Utilities */
1856
1857static void
1858bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1859{
1860 int i = 1; /* Index 0 has broadcast address */
1861 struct netdev_hw_addr *mc_addr;
1862
1863 netdev_for_each_mc_addr(mc_addr, netdev) {
1864 memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
1865 ETH_ALEN);
1866 i++;
1867 }
1868}
1869
1870static int
1871bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1872{
1873 struct bnad_rx_ctrl *rx_ctrl =
1874 container_of(napi, struct bnad_rx_ctrl, napi);
2be67144 1875 struct bnad *bnad = rx_ctrl->bnad;
8b230ed8
RM		 1876 int rcvd = 0;
1877
271e8b79 1878 rx_ctrl->rx_poll_ctr++;
8b230ed8
RM		 1879
1880 if (!netif_carrier_ok(bnad->netdev))
1881 goto poll_exit;
1882
b3cc6e88 1883 rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget);
271e8b79 1884 if (rcvd >= budget)
8b230ed8
RM		 1885 return rcvd;
1886
1887poll_exit:
19dbff9f 1888 napi_complete(napi);
8b230ed8 1889
271e8b79 1890 rx_ctrl->rx_complete++;
2be67144
RM		 1891
1892 if (rx_ctrl->ccb)
271e8b79
RM		 1893 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb);
1894
8b230ed8
RM		 1895 return rcvd;
1896}
1897
2be67144 1898#define BNAD_NAPI_POLL_QUOTA 64
8b230ed8 1899static void
01b54b14 1900bnad_napi_add(struct bnad *bnad, u32 rx_id)
8b230ed8 1901{
8b230ed8
RM		 1902 struct bnad_rx_ctrl *rx_ctrl;
1903 int i;
8b230ed8
RM		 1904
1905 /* Initialize & enable NAPI */
1906 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1907 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1908 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
2be67144
RM		 1909 bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA);
1910 }
1911}
1912
1913static void
01b54b14 1914bnad_napi_delete(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 1915{
1916 int i;
1917
1918 /* First disable and then clean up */
01b54b14 1919 for (i = 0; i < bnad->num_rxp_per_rx; i++)
8b230ed8 1920 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
8b230ed8
RM		 1921}
1922
1923/* Should be held with conf_lock held */
1924void
b3cc6e88 1925bnad_destroy_tx(struct bnad *bnad, u32 tx_id)
8b230ed8
RM		 1926{
1927 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1928 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1929 unsigned long flags;
1930
1931 if (!tx_info->tx)
1932 return;
1933
1934 init_completion(&bnad->bnad_completions.tx_comp);
1935 spin_lock_irqsave(&bnad->bna_lock, flags);
1936 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1937 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1938 wait_for_completion(&bnad->bnad_completions.tx_comp);
1939
1940 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1941 bnad_tx_msix_unregister(bnad, tx_info,
1942 bnad->num_txq_per_tx);
1943
1944 spin_lock_irqsave(&bnad->bna_lock, flags);
1945 bna_tx_destroy(tx_info->tx);
1946 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1947
1948 tx_info->tx = NULL;
078086f3 1949 tx_info->tx_id = 0;
8b230ed8 1950
8b230ed8
RM		 1951 bnad_tx_res_free(bnad, res_info);
1952}
1953
1954/* Should be held with conf_lock held */
1955int
078086f3 1956bnad_setup_tx(struct bnad *bnad, u32 tx_id)
8b230ed8
RM		 1957{
1958 int err;
1959 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1960 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1961 struct bna_intr_info *intr_info =
1962 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1963 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
d91d25d5 1964 static const struct bna_tx_event_cbfn tx_cbfn = {
1965 .tcb_setup_cbfn = bnad_cb_tcb_setup,
1966 .tcb_destroy_cbfn = bnad_cb_tcb_destroy,
1967 .tx_stall_cbfn = bnad_cb_tx_stall,
1968 .tx_resume_cbfn = bnad_cb_tx_resume,
1969 .tx_cleanup_cbfn = bnad_cb_tx_cleanup,
1970 };
1971
8b230ed8
RM		 1972 struct bna_tx *tx;
1973 unsigned long flags;
1974
078086f3
RM		 1975 tx_info->tx_id = tx_id;
1976
8b230ed8
RM		 1977 /* Initialize the Tx object configuration */
1978 tx_config->num_txq = bnad->num_txq_per_tx;
1979 tx_config->txq_depth = bnad->txq_depth;
1980 tx_config->tx_type = BNA_TX_T_REGULAR;
078086f3 1981 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo;
8b230ed8 1982
8b230ed8
RM		 1983 /* Get BNA's resource requirement for one tx object */
1984 spin_lock_irqsave(&bnad->bna_lock, flags);
1985 bna_tx_res_req(bnad->num_txq_per_tx,
1986 bnad->txq_depth, res_info);
1987 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1988
1989 /* Fill Unmap Q memory requirements */
5216562a
RM		 1990 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1991 bnad->num_txq_per_tx, (sizeof(struct bnad_tx_unmap) *
1992 bnad->txq_depth));
8b230ed8
RM		 1993
1994 /* Allocate resources */
1995 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1996 if (err)
1997 return err;
1998
1999 /* Ask BNA to create one Tx object, supplying required resources */
2000 spin_lock_irqsave(&bnad->bna_lock, flags);
2001 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
2002 tx_info);
2003 spin_unlock_irqrestore(&bnad->bna_lock, flags);
f29eeb79
RM		 2004 if (!tx) {
2005 err = -ENOMEM;
8b230ed8 2006 goto err_return;
f29eeb79 2007 }
8b230ed8
RM		 2008 tx_info->tx = tx;
2009
01b54b14
JH		 2010 INIT_DELAYED_WORK(&tx_info->tx_cleanup_work,
2011 (work_func_t)bnad_tx_cleanup);
2012
8b230ed8
RM		 2013 /* Register ISR for the Tx object */
2014 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2015 err = bnad_tx_msix_register(bnad, tx_info,
2016 tx_id, bnad->num_txq_per_tx);
2017 if (err)
f29eeb79 2018 goto cleanup_tx;
8b230ed8
RM		 2019 }
2020
2021 spin_lock_irqsave(&bnad->bna_lock, flags);
2022 bna_tx_enable(tx);
2023 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2024
2025 return 0;
2026
f29eeb79
RM		 2027cleanup_tx:
2028 spin_lock_irqsave(&bnad->bna_lock, flags);
2029 bna_tx_destroy(tx_info->tx);
2030 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2031 tx_info->tx = NULL;
2032 tx_info->tx_id = 0;
8b230ed8
RM		 2033err_return:
2034 bnad_tx_res_free(bnad, res_info);
2035 return err;
2036}
2037
2038/* Setup the rx config for bna_rx_create */
2039/* bnad decides the configuration */
2040static void
2041bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
2042{
e29aa339 2043 memset(rx_config, 0, sizeof(*rx_config));
8b230ed8
RM		 2044 rx_config->rx_type = BNA_RX_T_REGULAR;
2045 rx_config->num_paths = bnad->num_rxp_per_rx;
078086f3 2046 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo;
8b230ed8
RM		 2047
2048 if (bnad->num_rxp_per_rx > 1) {
2049 rx_config->rss_status = BNA_STATUS_T_ENABLED;
2050 rx_config->rss_config.hash_type =
078086f3
RM		 2051 (BFI_ENET_RSS_IPV6 |
2052 BFI_ENET_RSS_IPV6_TCP |
2053 BFI_ENET_RSS_IPV4 |
2054 BFI_ENET_RSS_IPV4_TCP);
8b230ed8
RM		 2055 rx_config->rss_config.hash_mask =
2056 bnad->num_rxp_per_rx - 1;
2057 get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
2058 sizeof(rx_config->rss_config.toeplitz_hash_key));
2059 } else {
2060 rx_config->rss_status = BNA_STATUS_T_DISABLED;
2061 memset(&rx_config->rss_config, 0,
2062 sizeof(rx_config->rss_config));
2063 }
e29aa339
RM		 2064
2065 rx_config->frame_size = BNAD_FRAME_SIZE(bnad->netdev->mtu);
2066 rx_config->q0_multi_buf = BNA_STATUS_T_DISABLED;
2067
2068 /* BNA_RXP_SINGLE - one data-buffer queue
2069 * BNA_RXP_SLR - one small-buffer and one large-buffer queues
2070 * BNA_RXP_HDS - one header-buffer and one data-buffer queues
2071 */
2072 /* TODO: configurable param for queue type */
8b230ed8 2073 rx_config->rxp_type = BNA_RXP_SLR;
8b230ed8 2074
e29aa339
RM		 2075 if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
2076 rx_config->frame_size > 4096) {
2077 /* though size_routing_enable is set in SLR,
2078 * small packets may get routed to same rxq.
2079 * set buf_size to 2048 instead of PAGE_SIZE.
2080 */
2081 rx_config->q0_buf_size = 2048;
2082 /* this should be in multiples of 2 */
2083 rx_config->q0_num_vecs = 4;
2084 rx_config->q0_depth = bnad->rxq_depth * rx_config->q0_num_vecs;
2085 rx_config->q0_multi_buf = BNA_STATUS_T_ENABLED;
2086 } else {
2087 rx_config->q0_buf_size = rx_config->frame_size;
2088 rx_config->q0_num_vecs = 1;
2089 rx_config->q0_depth = bnad->rxq_depth;
2090 }
2091
2092 /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */
2093 if (rx_config->rxp_type == BNA_RXP_SLR) {
2094 rx_config->q1_depth = bnad->rxq_depth;
2095 rx_config->q1_buf_size = BFI_SMALL_RXBUF_SIZE;
2096 }
8b230ed8 2097
877767dc
IV		 2098 rx_config->vlan_strip_status =
2099 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) ?
2100 BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
8b230ed8
RM		 2101}
2102
2be67144
RM		 2103static void
2104bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id)
2105{
2106 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2107 int i;
2108
2109 for (i = 0; i < bnad->num_rxp_per_rx; i++)
2110 rx_info->rx_ctrl[i].bnad = bnad;
2111}
2112
8b230ed8 2113/* Called with mutex_lock(&bnad->conf_mutex) held */
2fd888a5 2114static u32
e29aa339
RM		 2115bnad_reinit_rx(struct bnad *bnad)
2116{
2117 struct net_device *netdev = bnad->netdev;
2118 u32 err = 0, current_err = 0;
2119 u32 rx_id = 0, count = 0;
2120 unsigned long flags;
2121
2122 /* destroy and create new rx objects */
2123 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2124 if (!bnad->rx_info[rx_id].rx)
2125 continue;
2126 bnad_destroy_rx(bnad, rx_id);
2127 }
2128
2129 spin_lock_irqsave(&bnad->bna_lock, flags);
2130 bna_enet_mtu_set(&bnad->bna.enet,
2131 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
2132 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2133
2134 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2135 count++;
2136 current_err = bnad_setup_rx(bnad, rx_id);
2137 if (current_err && !err) {
2138 err = current_err;
2139 pr_err("RXQ:%u setup failed\n", rx_id);
2140 }
2141 }
2142
2143 /* restore rx configuration */
2144 if (bnad->rx_info[0].rx && !err) {
2145 bnad_restore_vlans(bnad, 0);
2146 bnad_enable_default_bcast(bnad);
2147 spin_lock_irqsave(&bnad->bna_lock, flags);
2148 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2149 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2150 bnad_set_rx_mode(netdev);
2151 }
2152
2153 return count;
2154}
2155
2156/* Called with bnad_conf_lock() held */
8b230ed8 2157void
b3cc6e88 2158bnad_destroy_rx(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 2159{
2160 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2161 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
2162 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2163 unsigned long flags;
271e8b79 2164 int to_del = 0;
8b230ed8
RM		 2165
2166 if (!rx_info->rx)
2167 return;
2168
2169 if (0 == rx_id) {
2170 spin_lock_irqsave(&bnad->bna_lock, flags);
271e8b79
RM		 2171 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
2172 test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
8b230ed8 2173 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
271e8b79
RM		 2174 to_del = 1;
2175 }
8b230ed8 2176 spin_unlock_irqrestore(&bnad->bna_lock, flags);
271e8b79 2177 if (to_del)
8b230ed8
RM		 2178 del_timer_sync(&bnad->dim_timer);
2179 }
2180
8b230ed8
RM		 2181 init_completion(&bnad->bnad_completions.rx_comp);
2182 spin_lock_irqsave(&bnad->bna_lock, flags);
2183 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
2184 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2185 wait_for_completion(&bnad->bnad_completions.rx_comp);
2186
2187 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
2188 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
2189
01b54b14 2190 bnad_napi_delete(bnad, rx_id);
2be67144 2191
8b230ed8
RM		 2192 spin_lock_irqsave(&bnad->bna_lock, flags);
2193 bna_rx_destroy(rx_info->rx);
8b230ed8
RM		 2194
2195 rx_info->rx = NULL;
3caa1e95 2196 rx_info->rx_id = 0;
b9fa1fbf 2197 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 2198
2199 bnad_rx_res_free(bnad, res_info);
2200}
2201
2202/* Called with mutex_lock(&bnad->conf_mutex) held */
2203int
078086f3 2204bnad_setup_rx(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 2205{
2206 int err;
2207 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2208 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2209 struct bna_intr_info *intr_info =
2210 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
2211 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
d91d25d5 2212 static const struct bna_rx_event_cbfn rx_cbfn = {
5216562a 2213 .rcb_setup_cbfn = NULL,
01b54b14 2214 .rcb_destroy_cbfn = NULL,
d91d25d5 2215 .ccb_setup_cbfn = bnad_cb_ccb_setup,
2216 .ccb_destroy_cbfn = bnad_cb_ccb_destroy,
5bcf6ac0 2217 .rx_stall_cbfn = bnad_cb_rx_stall,
d91d25d5 2218 .rx_cleanup_cbfn = bnad_cb_rx_cleanup,
2219 .rx_post_cbfn = bnad_cb_rx_post,
2220 };
8b230ed8
RM		 2221 struct bna_rx *rx;
2222 unsigned long flags;
2223
078086f3
RM		 2224 rx_info->rx_id = rx_id;
2225
8b230ed8
RM		 2226 /* Initialize the Rx object configuration */
2227 bnad_init_rx_config(bnad, rx_config);
2228
8b230ed8
RM		 2229 /* Get BNA's resource requirement for one Rx object */
2230 spin_lock_irqsave(&bnad->bna_lock, flags);
2231 bna_rx_res_req(rx_config, res_info);
2232 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2233
2234 /* Fill Unmap Q memory requirements */
e29aa339
RM		 2235 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPDQ],
2236 rx_config->num_paths,
2237 (rx_config->q0_depth *
2238 sizeof(struct bnad_rx_unmap)) +
2239 sizeof(struct bnad_rx_unmap_q));
2240
2241 if (rx_config->rxp_type != BNA_RXP_SINGLE) {
2242 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPHQ],
2243 rx_config->num_paths,
2244 (rx_config->q1_depth *
2245 sizeof(struct bnad_rx_unmap) +
2246 sizeof(struct bnad_rx_unmap_q)));
2247 }
8b230ed8
RM		 2248 /* Allocate resource */
2249 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
2250 if (err)
2251 return err;
2252
2be67144
RM		 2253 bnad_rx_ctrl_init(bnad, rx_id);
2254
8b230ed8
RM		 2255 /* Ask BNA to create one Rx object, supplying required resources */
2256 spin_lock_irqsave(&bnad->bna_lock, flags);
2257 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
2258 rx_info);
3caa1e95
RM		 2259 if (!rx) {
2260 err = -ENOMEM;
b9fa1fbf 2261 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 2262 goto err_return;
3caa1e95 2263 }
8b230ed8 2264 rx_info->rx = rx;
b9fa1fbf 2265 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 2266
01b54b14
JH		 2267 INIT_WORK(&rx_info->rx_cleanup_work,
2268 (work_func_t)(bnad_rx_cleanup));
2269
2be67144
RM		 2270 /*
2271 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
2272 * so that IRQ handler cannot schedule NAPI at this point.
2273 */
01b54b14 2274 bnad_napi_add(bnad, rx_id);
2be67144 2275
8b230ed8
RM		 2276 /* Register ISR for the Rx object */
2277 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2278 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
2279 rx_config->num_paths);
2280 if (err)
2281 goto err_return;
2282 }
2283
8b230ed8
RM		 2284 spin_lock_irqsave(&bnad->bna_lock, flags);
2285 if (0 == rx_id) {
2286 /* Set up Dynamic Interrupt Moderation Vector */
2287 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
2288 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
2289
2290 /* Enable VLAN filtering only on the default Rx */
2291 bna_rx_vlanfilter_enable(rx);
2292
2293 /* Start the DIM timer */
2294 bnad_dim_timer_start(bnad);
2295 }
2296
2297 bna_rx_enable(rx);
2298 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2299
2300 return 0;
2301
2302err_return:
b3cc6e88 2303 bnad_destroy_rx(bnad, rx_id);
8b230ed8
RM		 2304 return err;
2305}
2306
2307/* Called with conf_lock & bnad->bna_lock held */
2308void
2309bnad_tx_coalescing_timeo_set(struct bnad *bnad)
2310{
2311 struct bnad_tx_info *tx_info;
2312
2313 tx_info = &bnad->tx_info[0];
2314 if (!tx_info->tx)
2315 return;
2316
2317 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
2318}
2319
2320/* Called with conf_lock & bnad->bna_lock held */
2321void
2322bnad_rx_coalescing_timeo_set(struct bnad *bnad)
2323{
2324 struct bnad_rx_info *rx_info;
0120b99c 2325 int i;
8b230ed8
RM		 2326
2327 for (i = 0; i < bnad->num_rx; i++) {
2328 rx_info = &bnad->rx_info[i];
2329 if (!rx_info->rx)
2330 continue;
2331 bna_rx_coalescing_timeo_set(rx_info->rx,
2332 bnad->rx_coalescing_timeo);
2333 }
2334}
2335
2336/*
2337 * Called with bnad->bna_lock held
2338 */
a2122d95 2339int
8b230ed8
RM		 2340bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
2341{
2342 int ret;
2343
2344 if (!is_valid_ether_addr(mac_addr))
2345 return -EADDRNOTAVAIL;
2346
2347 /* If datapath is down, pretend everything went through */
2348 if (!bnad->rx_info[0].rx)
2349 return 0;
2350
2351 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
2352 if (ret != BNA_CB_SUCCESS)
2353 return -EADDRNOTAVAIL;
2354
2355 return 0;
2356}
2357
2358/* Should be called with conf_lock held */
a2122d95 2359int
8b230ed8
RM		 2360bnad_enable_default_bcast(struct bnad *bnad)
2361{
2362 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
2363 int ret;
2364 unsigned long flags;
2365
2366 init_completion(&bnad->bnad_completions.mcast_comp);
2367
2368 spin_lock_irqsave(&bnad->bna_lock, flags);
2369 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
2370 bnad_cb_rx_mcast_add);
2371 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2372
2373 if (ret == BNA_CB_SUCCESS)
2374 wait_for_completion(&bnad->bnad_completions.mcast_comp);
2375 else
2376 return -ENODEV;
2377
2378 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
2379 return -ENODEV;
2380
2381 return 0;
2382}
2383
19dbff9f 2384/* Called with mutex_lock(&bnad->conf_mutex) held */
a2122d95 2385void
aad75b66
RM		 2386bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
2387{
f859d7cb 2388 u16 vid;
aad75b66
RM		 2389 unsigned long flags;
2390
f859d7cb 2391 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) {
aad75b66 2392 spin_lock_irqsave(&bnad->bna_lock, flags);
f859d7cb 2393 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid);
aad75b66
RM		 2394 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2395 }
2396}
2397
8b230ed8
RM		 2398/* Statistics utilities */
2399void
250e061e 2400bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 2401{
8b230ed8
RM		 2402 int i, j;
2403
2404 for (i = 0; i < bnad->num_rx; i++) {
2405 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2406 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
250e061e 2407 stats->rx_packets += bnad->rx_info[i].
8b230ed8 2408 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
250e061e 2409 stats->rx_bytes += bnad->rx_info[i].
8b230ed8
RM		 2410 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2411 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2412 bnad->rx_info[i].rx_ctrl[j].ccb->
2413 rcb[1]->rxq) {
250e061e 2414 stats->rx_packets +=
8b230ed8
RM		 2415 bnad->rx_info[i].rx_ctrl[j].
2416 ccb->rcb[1]->rxq->rx_packets;
250e061e 2417 stats->rx_bytes +=
8b230ed8
RM		 2418 bnad->rx_info[i].rx_ctrl[j].
2419 ccb->rcb[1]->rxq->rx_bytes;
2420 }
2421 }
2422 }
2423 }
2424 for (i = 0; i < bnad->num_tx; i++) {
2425 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2426 if (bnad->tx_info[i].tcb[j]) {
250e061e 2427 stats->tx_packets +=
8b230ed8 2428 bnad->tx_info[i].tcb[j]->txq->tx_packets;
250e061e 2429 stats->tx_bytes +=
8b230ed8
RM		 2430 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2431 }
2432 }
2433 }
2434}
2435
2436/*
2437 * Must be called with the bna_lock held.
2438 */
2439void
250e061e 2440bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 2441{
078086f3
RM		 2442 struct bfi_enet_stats_mac *mac_stats;
2443 u32 bmap;
8b230ed8
RM		 2444 int i;
2445
078086f3 2446 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats;
250e061e 2447 stats->rx_errors =
8b230ed8
RM		 2448 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2449 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2450 mac_stats->rx_undersize;
250e061e 2451 stats->tx_errors = mac_stats->tx_fcs_error +
8b230ed8 2452 mac_stats->tx_undersize;
250e061e
ED		 2453 stats->rx_dropped = mac_stats->rx_drop;
2454 stats->tx_dropped = mac_stats->tx_drop;
2455 stats->multicast = mac_stats->rx_multicast;
2456 stats->collisions = mac_stats->tx_total_collision;
8b230ed8 2457
250e061e 2458 stats->rx_length_errors = mac_stats->rx_frame_length_error;
8b230ed8
RM		 2459
2460 /* receive ring buffer overflow ?? */
2461
250e061e
ED		 2462 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2463 stats->rx_frame_errors = mac_stats->rx_alignment_error;
8b230ed8 2464 /* recv'r fifo overrun */
078086f3
RM		 2465 bmap = bna_rx_rid_mask(&bnad->bna);
2466 for (i = 0; bmap; i++) {
8b230ed8 2467 if (bmap & 1) {
250e061e 2468 stats->rx_fifo_errors +=
8b230ed8 2469 bnad->stats.bna_stats->
078086f3 2470 hw_stats.rxf_stats[i].frame_drops;
8b230ed8
RM		 2471 break;
2472 }
2473 bmap >>= 1;
2474 }
2475}
2476
2477static void
2478bnad_mbox_irq_sync(struct bnad *bnad)
2479{
2480 u32 irq;
2481 unsigned long flags;
2482
2483 spin_lock_irqsave(&bnad->bna_lock, flags);
2484 if (bnad->cfg_flags & BNAD_CF_MSIX)
8811e267 2485 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
8b230ed8
RM		 2486 else
2487 irq = bnad->pcidev->irq;
2488 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2489
2490 synchronize_irq(irq);
2491}
2492
2493/* Utility used by bnad_start_xmit, for doing TSO */
2494static int
2495bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2496{
2497 int err;
2498
8b230ed8
RM		 2499 if (skb_header_cloned(skb)) {
2500 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2501 if (err) {
2502 BNAD_UPDATE_CTR(bnad, tso_err);
2503 return err;
2504 }
2505 }
2506
2507 /*
2508 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2509 * excluding the length field.
2510 */
2511 if (skb->protocol == htons(ETH_P_IP)) {
2512 struct iphdr *iph = ip_hdr(skb);
2513
2514 /* Do we really need these? */
2515 iph->tot_len = 0;
2516 iph->check = 0;
2517
2518 tcp_hdr(skb)->check =
2519 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2520 IPPROTO_TCP, 0);
2521 BNAD_UPDATE_CTR(bnad, tso4);
2522 } else {
2523 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2524
8b230ed8
RM		 2525 ipv6h->payload_len = 0;
2526 tcp_hdr(skb)->check =
2527 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2528 IPPROTO_TCP, 0);
2529 BNAD_UPDATE_CTR(bnad, tso6);
2530 }
2531
2532 return 0;
2533}
2534
2535/*
2536 * Initialize Q numbers depending on Rx Paths
2537 * Called with bnad->bna_lock held, because of cfg_flags
2538 * access.
2539 */
2540static void
2541bnad_q_num_init(struct bnad *bnad)
2542{
2543 int rxps;
2544
2545 rxps = min((uint)num_online_cpus(),
772b5235 2546 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX));
8b230ed8
RM		 2547
2548 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2549 rxps = 1; /* INTx */
2550
2551 bnad->num_rx = 1;
2552 bnad->num_tx = 1;
2553 bnad->num_rxp_per_rx = rxps;
2554 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2555}
2556
2557/*
2558 * Adjusts the Q numbers, given a number of msix vectors
2559 * Give preference to RSS as opposed to Tx priority Queues,
2560 * in such a case, just use 1 Tx Q
2561 * Called with bnad->bna_lock held b'cos of cfg_flags access
2562 */
2563static void
078086f3 2564bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp)
8b230ed8
RM		 2565{
2566 bnad->num_txq_per_tx = 1;
2567 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2568 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2569 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2570 bnad->num_rxp_per_rx = msix_vectors -
2571 (bnad->num_tx * bnad->num_txq_per_tx) -
2572 BNAD_MAILBOX_MSIX_VECTORS;
2573 } else
2574 bnad->num_rxp_per_rx = 1;
2575}
2576
078086f3
RM		 2577/* Enable / disable ioceth */
2578static int
2579bnad_ioceth_disable(struct bnad *bnad)
8b230ed8
RM		 2580{
2581 unsigned long flags;
078086f3 2582 int err = 0;
8b230ed8
RM		 2583
2584 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2585 init_completion(&bnad->bnad_completions.ioc_comp);
2586 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP);
8b230ed8
RM		 2587 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2588
078086f3
RM		 2589 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2590 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2591
2592 err = bnad->bnad_completions.ioc_comp_status;
2593 return err;
8b230ed8
RM		 2594}
2595
2596static int
078086f3 2597bnad_ioceth_enable(struct bnad *bnad)
8b230ed8
RM		 2598{
2599 int err = 0;
2600 unsigned long flags;
2601
8b230ed8 2602 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2603 init_completion(&bnad->bnad_completions.ioc_comp);
2604 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING;
2605 bna_ioceth_enable(&bnad->bna.ioceth);
8b230ed8
RM		 2606 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2607
078086f3
RM		 2608 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2609 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
8b230ed8 2610
078086f3 2611 err = bnad->bnad_completions.ioc_comp_status;
8b230ed8
RM		 2612
2613 return err;
2614}
2615
2616/* Free BNA resources */
2617static void
078086f3
RM		 2618bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info,
2619 u32 res_val_max)
8b230ed8
RM		 2620{
2621 int i;
8b230ed8 2622
078086f3
RM		 2623 for (i = 0; i < res_val_max; i++)
2624 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
8b230ed8
RM		 2625}
2626
2627/* Allocates memory and interrupt resources for BNA */
2628static int
078086f3
RM		 2629bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
2630 u32 res_val_max)
8b230ed8
RM		 2631{
2632 int i, err;
8b230ed8 2633
078086f3
RM		 2634 for (i = 0; i < res_val_max; i++) {
2635 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
8b230ed8
RM		 2636 if (err)
2637 goto err_return;
2638 }
2639 return 0;
2640
2641err_return:
078086f3 2642 bnad_res_free(bnad, res_info, res_val_max);
8b230ed8
RM		 2643 return err;
2644}
2645
2646/* Interrupt enable / disable */
2647static void
2648bnad_enable_msix(struct bnad *bnad)
2649{
2650 int i, ret;
8b230ed8
RM		 2651 unsigned long flags;
2652
2653 spin_lock_irqsave(&bnad->bna_lock, flags);
2654 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2655 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2656 return;
2657 }
2658 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2659
2660 if (bnad->msix_table)
2661 return;
2662
8b230ed8 2663 bnad->msix_table =
b7ee31c5 2664 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
8b230ed8
RM		 2665
2666 if (!bnad->msix_table)
2667 goto intx_mode;
2668
b7ee31c5 2669 for (i = 0; i < bnad->msix_num; i++)
8b230ed8
RM		 2670 bnad->msix_table[i].entry = i;
2671
b7ee31c5 2672 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num);
8b230ed8
RM		 2673 if (ret > 0) {
2674 /* Not enough MSI-X vectors. */
19dbff9f
RM		 2675 pr_warn("BNA: %d MSI-X vectors allocated < %d requested\n",
2676 ret, bnad->msix_num);
8b230ed8
RM		 2677
2678 spin_lock_irqsave(&bnad->bna_lock, flags);
2679 /* ret = #of vectors that we got */
271e8b79
RM		 2680 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2,
2681 (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2);
8b230ed8
RM		 2682 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2683
271e8b79 2684 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP +
8b230ed8 2685 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8 2686
078086f3
RM		 2687 if (bnad->msix_num > ret)
2688 goto intx_mode;
2689
8b230ed8
RM		 2690 /* Try once more with adjusted numbers */
2691 /* If this fails, fall back to INTx */
2692 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
b7ee31c5 2693 bnad->msix_num);
8b230ed8
RM		 2694 if (ret)
2695 goto intx_mode;
2696
2697 } else if (ret < 0)
2698 goto intx_mode;
078086f3
RM		 2699
2700 pci_intx(bnad->pcidev, 0);
2701
8b230ed8
RM		 2702 return;
2703
2704intx_mode:
19dbff9f 2705 pr_warn("BNA: MSI-X enable failed - operating in INTx mode\n");
8b230ed8
RM		 2706
2707 kfree(bnad->msix_table);
2708 bnad->msix_table = NULL;
2709 bnad->msix_num = 0;
8b230ed8
RM		 2710 spin_lock_irqsave(&bnad->bna_lock, flags);
2711 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2712 bnad_q_num_init(bnad);
2713 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2714}
2715
2716static void
2717bnad_disable_msix(struct bnad *bnad)
2718{
2719 u32 cfg_flags;
2720 unsigned long flags;
2721
2722 spin_lock_irqsave(&bnad->bna_lock, flags);
2723 cfg_flags = bnad->cfg_flags;
2724 if (bnad->cfg_flags & BNAD_CF_MSIX)
2725 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2726 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2727
2728 if (cfg_flags & BNAD_CF_MSIX) {
2729 pci_disable_msix(bnad->pcidev);
2730 kfree(bnad->msix_table);
2731 bnad->msix_table = NULL;
2732 }
2733}
2734
2735/* Netdev entry points */
2736static int
2737bnad_open(struct net_device *netdev)
2738{
2739 int err;
2740 struct bnad *bnad = netdev_priv(netdev);
2741 struct bna_pause_config pause_config;
8b230ed8
RM		 2742 unsigned long flags;
2743
2744 mutex_lock(&bnad->conf_mutex);
2745
2746 /* Tx */
2747 err = bnad_setup_tx(bnad, 0);
2748 if (err)
2749 goto err_return;
2750
2751 /* Rx */
2752 err = bnad_setup_rx(bnad, 0);
2753 if (err)
2754 goto cleanup_tx;
2755
2756 /* Port */
2757 pause_config.tx_pause = 0;
2758 pause_config.rx_pause = 0;
2759
8b230ed8 2760 spin_lock_irqsave(&bnad->bna_lock, flags);
e29aa339
RM		 2761 bna_enet_mtu_set(&bnad->bna.enet,
2762 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
078086f3
RM		 2763 bna_enet_pause_config(&bnad->bna.enet, &pause_config, NULL);
2764 bna_enet_enable(&bnad->bna.enet);
8b230ed8
RM		 2765 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2766
2767 /* Enable broadcast */
2768 bnad_enable_default_bcast(bnad);
2769
aad75b66
RM		 2770 /* Restore VLANs, if any */
2771 bnad_restore_vlans(bnad, 0);
2772
8b230ed8
RM		 2773 /* Set the UCAST address */
2774 spin_lock_irqsave(&bnad->bna_lock, flags);
2775 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2776 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2777
2778 /* Start the stats timer */
2779 bnad_stats_timer_start(bnad);
2780
2781 mutex_unlock(&bnad->conf_mutex);
2782
2783 return 0;
2784
2785cleanup_tx:
b3cc6e88 2786 bnad_destroy_tx(bnad, 0);
8b230ed8
RM		 2787
2788err_return:
2789 mutex_unlock(&bnad->conf_mutex);
2790 return err;
2791}
2792
2793static int
2794bnad_stop(struct net_device *netdev)
2795{
2796 struct bnad *bnad = netdev_priv(netdev);
2797 unsigned long flags;
2798
2799 mutex_lock(&bnad->conf_mutex);
2800
2801 /* Stop the stats timer */
2802 bnad_stats_timer_stop(bnad);
2803
078086f3 2804 init_completion(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 2805
2806 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2807 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP,
2808 bnad_cb_enet_disabled);
8b230ed8
RM		 2809 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2810
078086f3 2811 wait_for_completion(&bnad->bnad_completions.enet_comp);
8b230ed8 2812
b3cc6e88
JH		 2813 bnad_destroy_tx(bnad, 0);
2814 bnad_destroy_rx(bnad, 0);
8b230ed8
RM		 2815
2816 /* Synchronize mailbox IRQ */
2817 bnad_mbox_irq_sync(bnad);
2818
2819 mutex_unlock(&bnad->conf_mutex);
2820
2821 return 0;
2822}
2823
2824/* TX */
5216562a
RM		 2825/* Returns 0 for success */
2826static int
2827bnad_txq_wi_prepare(struct bnad *bnad, struct bna_tcb *tcb,
2828 struct sk_buff *skb, struct bna_txq_entry *txqent)
8b230ed8 2829{
5216562a
RM		 2830 u16 flags = 0;
2831 u32 gso_size;
2832 u16 vlan_tag = 0;
8b230ed8 2833
eab6d18d 2834 if (vlan_tx_tag_present(skb)) {
5216562a 2835 vlan_tag = (u16)vlan_tx_tag_get(skb);
8b230ed8
RM		 2836 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2837 }
2838 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
5216562a
RM		 2839 vlan_tag = ((tcb->priority & 0x7) << VLAN_PRIO_SHIFT)
2840 | (vlan_tag & 0x1fff);
8b230ed8
RM		 2841 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2842 }
8b230ed8
RM		 2843 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2844
2845 if (skb_is_gso(skb)) {
271e8b79 2846 gso_size = skb_shinfo(skb)->gso_size;
5216562a 2847 if (unlikely(gso_size > bnad->netdev->mtu)) {
271e8b79 2848 BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long);
5216562a 2849 return -EINVAL;
271e8b79
RM		 2850 }
2851 if (unlikely((gso_size + skb_transport_offset(skb) +
5216562a 2852 tcp_hdrlen(skb)) >= skb->len)) {
271e8b79
RM		 2853 txqent->hdr.wi.opcode =
2854 __constant_htons(BNA_TXQ_WI_SEND);
2855 txqent->hdr.wi.lso_mss = 0;
2856 BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short);
2857 } else {
2858 txqent->hdr.wi.opcode =
2859 __constant_htons(BNA_TXQ_WI_SEND_LSO);
2860 txqent->hdr.wi.lso_mss = htons(gso_size);
2861 }
2862
5216562a 2863 if (bnad_tso_prepare(bnad, skb)) {
271e8b79 2864 BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare);
5216562a 2865 return -EINVAL;
8b230ed8 2866 }
5216562a 2867
8b230ed8
RM		 2868 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2869 txqent->hdr.wi.l4_hdr_size_n_offset =
5216562a
RM		 2870 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET(
2871 tcp_hdrlen(skb) >> 2, skb_transport_offset(skb)));
2872 } else {
271e8b79 2873 txqent->hdr.wi.opcode = __constant_htons(BNA_TXQ_WI_SEND);
8b230ed8
RM		 2874 txqent->hdr.wi.lso_mss = 0;
2875
5216562a 2876 if (unlikely(skb->len > (bnad->netdev->mtu + ETH_HLEN))) {
271e8b79 2877 BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long);
5216562a 2878 return -EINVAL;
8b230ed8 2879 }
8b230ed8 2880
271e8b79
RM		 2881 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2882 u8 proto = 0;
8b230ed8 2883
271e8b79
RM		 2884 if (skb->protocol == __constant_htons(ETH_P_IP))
2885 proto = ip_hdr(skb)->protocol;
5216562a 2886#ifdef NETIF_F_IPV6_CSUM
271e8b79
RM		 2887 else if (skb->protocol ==
2888 __constant_htons(ETH_P_IPV6)) {
2889 /* nexthdr may not be TCP immediately. */
2890 proto = ipv6_hdr(skb)->nexthdr;
2891 }
5216562a 2892#endif
271e8b79
RM		 2893 if (proto == IPPROTO_TCP) {
2894 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2895 txqent->hdr.wi.l4_hdr_size_n_offset =
2896 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2897 (0, skb_transport_offset(skb)));
2898
2899 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2900
2901 if (unlikely(skb_headlen(skb) <
5216562a
RM		 2902 skb_transport_offset(skb) +
2903 tcp_hdrlen(skb))) {
271e8b79 2904 BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr);
5216562a 2905 return -EINVAL;
271e8b79 2906 }
271e8b79
RM		 2907 } else if (proto == IPPROTO_UDP) {
2908 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2909 txqent->hdr.wi.l4_hdr_size_n_offset =
2910 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2911 (0, skb_transport_offset(skb)));
2912
2913 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2914 if (unlikely(skb_headlen(skb) <
5216562a 2915 skb_transport_offset(skb) +
271e8b79 2916 sizeof(struct udphdr))) {
271e8b79 2917 BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr);
5216562a 2918 return -EINVAL;
271e8b79
RM		 2919 }
2920 } else {
5216562a 2921
271e8b79 2922 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err);
5216562a 2923 return -EINVAL;
8b230ed8 2924 }
5216562a 2925 } else
271e8b79 2926 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
8b230ed8
RM		 2927 }
2928
2929 txqent->hdr.wi.flags = htons(flags);
8b230ed8
RM		 2930 txqent->hdr.wi.frame_length = htonl(skb->len);
2931
5216562a
RM		 2932 return 0;
2933}
2934
2935/*
2936 * bnad_start_xmit : Netdev entry point for Transmit
2937 * Called under lock held by net_device
2938 */
2939static netdev_tx_t
2940bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2941{
2942 struct bnad *bnad = netdev_priv(netdev);
2943 u32 txq_id = 0;
2944 struct bna_tcb *tcb = NULL;
2945 struct bnad_tx_unmap *unmap_q, *unmap, *head_unmap;
2946 u32 prod, q_depth, vect_id;
2947 u32 wis, vectors, len;
2948 int i;
2949 dma_addr_t dma_addr;
2950 struct bna_txq_entry *txqent;
2951
271e8b79 2952 len = skb_headlen(skb);
8b230ed8 2953
5216562a
RM		 2954 /* Sanity checks for the skb */
2955
2956 if (unlikely(skb->len <= ETH_HLEN)) {
2957 dev_kfree_skb(skb);
2958 BNAD_UPDATE_CTR(bnad, tx_skb_too_short);
2959 return NETDEV_TX_OK;
2960 }
2961 if (unlikely(len > BFI_TX_MAX_DATA_PER_VECTOR)) {
2962 dev_kfree_skb(skb);
2963 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2964 return NETDEV_TX_OK;
2965 }
2966 if (unlikely(len == 0)) {
2967 dev_kfree_skb(skb);
2968 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2969 return NETDEV_TX_OK;
2970 }
2971
2972 tcb = bnad->tx_info[0].tcb[txq_id];
271e8b79 2973
5216562a
RM		 2974 /*
2975 * Takes care of the Tx that is scheduled between clearing the flag
2976 * and the netif_tx_stop_all_queues() call.
2977 */
96e31adf 2978 if (unlikely(!tcb || !test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
5216562a
RM		 2979 dev_kfree_skb(skb);
2980 BNAD_UPDATE_CTR(bnad, tx_skb_stopping);
2981 return NETDEV_TX_OK;
2982 }
2983
96e31adf
RM		 2984 q_depth = tcb->q_depth;
2985 prod = tcb->producer_index;
2986 unmap_q = tcb->unmap_q;
2987
5216562a
RM		 2988 vectors = 1 + skb_shinfo(skb)->nr_frags;
2989 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2990
2991 if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) {
2992 dev_kfree_skb(skb);
2993 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors);
2994 return NETDEV_TX_OK;
2995 }
2996
2997 /* Check for available TxQ resources */
2998 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
2999 if ((*tcb->hw_consumer_index != tcb->consumer_index) &&
3000 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
3001 u32 sent;
3002 sent = bnad_txcmpl_process(bnad, tcb);
3003 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
3004 bna_ib_ack(tcb->i_dbell, sent);
3005 smp_mb__before_clear_bit();
3006 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
3007 } else {
3008 netif_stop_queue(netdev);
3009 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
3010 }
3011
3012 smp_mb();
3013 /*
3014 * Check again to deal with race condition between
3015 * netif_stop_queue here, and netif_wake_queue in
3016 * interrupt handler which is not inside netif tx lock.
3017 */
3018 if (likely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
3019 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
3020 return NETDEV_TX_BUSY;
3021 } else {
3022 netif_wake_queue(netdev);
3023 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
3024 }
3025 }
3026
3027 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
3028 head_unmap = &unmap_q[prod];
3029
3030 /* Program the opcode, flags, frame_len, num_vectors in WI */
3031 if (bnad_txq_wi_prepare(bnad, tcb, skb, txqent)) {
3032 dev_kfree_skb(skb);
3033 return NETDEV_TX_OK;
3034 }
3035 txqent->hdr.wi.reserved = 0;
3036 txqent->hdr.wi.num_vectors = vectors;
3037
3038 head_unmap->skb = skb;
3039 head_unmap->nvecs = 0;
3040
3041 /* Program the vectors */
3042 unmap = head_unmap;
3043 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
3044 len, DMA_TO_DEVICE);
3045 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr);
3046 txqent->vector[0].length = htons(len);
3047 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, dma_addr);
3048 head_unmap->nvecs++;
3049
3050 for (i = 0, vect_id = 0; i < vectors - 1; i++) {
9e903e08 3051 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
24f5d33d 3052 u32 size = skb_frag_size(frag);
8b230ed8 3053
271e8b79 3054 if (unlikely(size == 0)) {
5216562a
RM		 3055 /* Undo the changes starting at tcb->producer_index */
3056 bnad_tx_buff_unmap(bnad, unmap_q, q_depth,
3057 tcb->producer_index);
271e8b79
RM		 3058 dev_kfree_skb(skb);
3059 BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero);
3060 return NETDEV_TX_OK;
3061 }
3062
3063 len += size;
3064
5216562a
RM		 3065 vect_id++;
3066 if (vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
8b230ed8 3067 vect_id = 0;
5216562a
RM		 3068 BNA_QE_INDX_INC(prod, q_depth);
3069 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
271e8b79
RM		 3070 txqent->hdr.wi_ext.opcode =
3071 __constant_htons(BNA_TXQ_WI_EXTENSION);
5216562a 3072 unmap = &unmap_q[prod];
8b230ed8
RM		 3073 }
3074
4d5b1a67
IC		 3075 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag,
3076 0, size, DMA_TO_DEVICE);
ecca6a96 3077 dma_unmap_len_set(&unmap->vectors[vect_id], dma_len, size);
8b230ed8 3078 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
5216562a
RM		 3079 txqent->vector[vect_id].length = htons(size);
3080 dma_unmap_addr_set(&unmap->vectors[vect_id], dma_addr,
ecca6a96 3081 dma_addr);
5216562a 3082 head_unmap->nvecs++;
8b230ed8
RM		 3083 }
3084
271e8b79 3085 if (unlikely(len != skb->len)) {
5216562a
RM		 3086 /* Undo the changes starting at tcb->producer_index */
3087 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, tcb->producer_index);
271e8b79
RM		 3088 dev_kfree_skb(skb);
3089 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch);
3090 return NETDEV_TX_OK;
3091 }
3092
5216562a
RM		 3093 BNA_QE_INDX_INC(prod, q_depth);
3094 tcb->producer_index = prod;
8b230ed8
RM		 3095
3096 smp_mb();
be7fa326
RM		 3097
3098 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
3099 return NETDEV_TX_OK;
3100
fee1253e
RM		 3101 skb_tx_timestamp(skb);
3102
8b230ed8 3103 bna_txq_prod_indx_doorbell(tcb);
271e8b79 3104 smp_mb();
8b230ed8 3105
8b230ed8
RM		 3106 return NETDEV_TX_OK;
3107}
3108
3109/*
3110 * Used spin_lock to synchronize reading of stats structures, which
3111 * is written by BNA under the same lock.
3112 */
250e061e
ED		 3113static struct rtnl_link_stats64 *
3114bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
8b230ed8
RM		 3115{
3116 struct bnad *bnad = netdev_priv(netdev);
3117 unsigned long flags;
3118
3119 spin_lock_irqsave(&bnad->bna_lock, flags);
3120
250e061e
ED		 3121 bnad_netdev_qstats_fill(bnad, stats);
3122 bnad_netdev_hwstats_fill(bnad, stats);
8b230ed8
RM		 3123
3124 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3125
250e061e 3126 return stats;
8b230ed8
RM		 3127}
3128
fe1624cf
RM		 3129static void
3130bnad_set_rx_ucast_fltr(struct bnad *bnad)
3131{
3132 struct net_device *netdev = bnad->netdev;
3133 int uc_count = netdev_uc_count(netdev);
3134 enum bna_cb_status ret;
3135 u8 *mac_list;
3136 struct netdev_hw_addr *ha;
3137 int entry;
3138
3139 if (netdev_uc_empty(bnad->netdev)) {
3140 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL, NULL);
3141 return;
3142 }
3143
3144 if (uc_count > bna_attr(&bnad->bna)->num_ucmac)
3145 goto mode_default;
3146
3147 mac_list = kzalloc(uc_count * ETH_ALEN, GFP_ATOMIC);
3148 if (mac_list == NULL)
3149 goto mode_default;
3150
3151 entry = 0;
3152 netdev_for_each_uc_addr(ha, netdev) {
3153 memcpy(&mac_list[entry * ETH_ALEN],
3154 &ha->addr[0], ETH_ALEN);
3155 entry++;
3156 }
3157
3158 ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry,
3159 mac_list, NULL);
3160 kfree(mac_list);
3161
3162 if (ret != BNA_CB_SUCCESS)
3163 goto mode_default;
3164
3165 return;
3166
3167 /* ucast packets not in UCAM are routed to default function */
3168mode_default:
3169 bnad->cfg_flags |= BNAD_CF_DEFAULT;
3170 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL, NULL);
3171}
3172
3173static void
3174bnad_set_rx_mcast_fltr(struct bnad *bnad)
3175{
3176 struct net_device *netdev = bnad->netdev;
3177 int mc_count = netdev_mc_count(netdev);
3178 enum bna_cb_status ret;
3179 u8 *mac_list;
3180
3181 if (netdev->flags & IFF_ALLMULTI)
3182 goto mode_allmulti;
3183
3184 if (netdev_mc_empty(netdev))
3185 return;
3186
3187 if (mc_count > bna_attr(&bnad->bna)->num_mcmac)
3188 goto mode_allmulti;
3189
3190 mac_list = kzalloc((mc_count + 1) * ETH_ALEN, GFP_ATOMIC);
3191
3192 if (mac_list == NULL)
3193 goto mode_allmulti;
3194
3195 memcpy(&mac_list[0], &bnad_bcast_addr[0], ETH_ALEN);
3196
3197 /* copy rest of the MCAST addresses */
3198 bnad_netdev_mc_list_get(netdev, mac_list);
3199 ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
3200 mac_list, NULL);
3201 kfree(mac_list);
3202
3203 if (ret != BNA_CB_SUCCESS)
3204 goto mode_allmulti;
3205
3206 return;
3207
3208mode_allmulti:
3209 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
3210 bna_rx_mcast_delall(bnad->rx_info[0].rx, NULL);
3211}
3212
a2122d95 3213void
8b230ed8
RM		 3214bnad_set_rx_mode(struct net_device *netdev)
3215{
3216 struct bnad *bnad = netdev_priv(netdev);
fe1624cf 3217 enum bna_rxmode new_mode, mode_mask;
8b230ed8
RM		 3218 unsigned long flags;
3219
3220 spin_lock_irqsave(&bnad->bna_lock, flags);
3221
fe1624cf
RM		 3222 if (bnad->rx_info[0].rx == NULL) {
3223 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3224 return;
8b230ed8
RM		 3225 }
3226
fe1624cf
RM		 3227 /* clear bnad flags to update it with new settings */
3228 bnad->cfg_flags &= ~(BNAD_CF_PROMISC | BNAD_CF_DEFAULT |
3229 BNAD_CF_ALLMULTI);
271e8b79 3230
fe1624cf
RM		 3231 new_mode = 0;
3232 if (netdev->flags & IFF_PROMISC) {
3233 new_mode |= BNAD_RXMODE_PROMISC_DEFAULT;
3234 bnad->cfg_flags |= BNAD_CF_PROMISC;
3235 } else {
3236 bnad_set_rx_mcast_fltr(bnad);
8b230ed8 3237
fe1624cf
RM		 3238 if (bnad->cfg_flags & BNAD_CF_ALLMULTI)
3239 new_mode |= BNA_RXMODE_ALLMULTI;
8b230ed8 3240
fe1624cf 3241 bnad_set_rx_ucast_fltr(bnad);
8b230ed8 3242
fe1624cf
RM		 3243 if (bnad->cfg_flags & BNAD_CF_DEFAULT)
3244 new_mode |= BNA_RXMODE_DEFAULT;
3245 }
8b230ed8 3246
fe1624cf
RM		 3247 mode_mask = BNA_RXMODE_PROMISC | BNA_RXMODE_DEFAULT |
3248 BNA_RXMODE_ALLMULTI;
3249 bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask, NULL);
8b230ed8 3250
8b230ed8
RM		 3251 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3252}
3253
3254/*
3255 * bna_lock is used to sync writes to netdev->addr
3256 * conf_lock cannot be used since this call may be made
3257 * in a non-blocking context.
3258 */
3259static int
3260bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
3261{
3262 int err;
3263 struct bnad *bnad = netdev_priv(netdev);
3264 struct sockaddr *sa = (struct sockaddr *)mac_addr;
3265 unsigned long flags;
3266
3267 spin_lock_irqsave(&bnad->bna_lock, flags);
3268
3269 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
3270
3271 if (!err)
3272 memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
3273
3274 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3275
3276 return err;
3277}
3278
3279static int
e29aa339 3280bnad_mtu_set(struct bnad *bnad, int frame_size)
8b230ed8 3281{
8b230ed8
RM		 3282 unsigned long flags;
3283
078086f3
RM		 3284 init_completion(&bnad->bnad_completions.mtu_comp);
3285
3286 spin_lock_irqsave(&bnad->bna_lock, flags);
e29aa339 3287 bna_enet_mtu_set(&bnad->bna.enet, frame_size, bnad_cb_enet_mtu_set);
078086f3
RM		 3288 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3289
3290 wait_for_completion(&bnad->bnad_completions.mtu_comp);
3291
3292 return bnad->bnad_completions.mtu_comp_status;
3293}
3294
3295static int
3296bnad_change_mtu(struct net_device *netdev, int new_mtu)
3297{
e29aa339 3298 int err, mtu;
8b230ed8 3299 struct bnad *bnad = netdev_priv(netdev);
e29aa339 3300 u32 rx_count = 0, frame, new_frame;
8b230ed8
RM		 3301
3302 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
3303 return -EINVAL;
3304
3305 mutex_lock(&bnad->conf_mutex);
3306
e29aa339 3307 mtu = netdev->mtu;
8b230ed8
RM		 3308 netdev->mtu = new_mtu;
3309
e29aa339
RM		 3310 frame = BNAD_FRAME_SIZE(mtu);
3311 new_frame = BNAD_FRAME_SIZE(new_mtu);
3312
3313 /* check if multi-buffer needs to be enabled */
3314 if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
3315 netif_running(bnad->netdev)) {
3316 /* only when transition is over 4K */
3317 if ((frame <= 4096 && new_frame > 4096) ||
3318 (frame > 4096 && new_frame <= 4096))
3319 rx_count = bnad_reinit_rx(bnad);
3320 }
3321
3322 /* rx_count > 0 - new rx created
3323 * - Linux set err = 0 and return
3324 */
3325 err = bnad_mtu_set(bnad, new_frame);
078086f3
RM		 3326 if (err)
3327 err = -EBUSY;
8b230ed8
RM		 3328
3329 mutex_unlock(&bnad->conf_mutex);
3330 return err;
3331}
3332
8e586137 3333static int
80d5c368 3334bnad_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
8b230ed8
RM		 3335{
3336 struct bnad *bnad = netdev_priv(netdev);
3337 unsigned long flags;
3338
3339 if (!bnad->rx_info[0].rx)
8e586137 3340 return 0;
8b230ed8
RM		 3341
3342 mutex_lock(&bnad->conf_mutex);
3343
3344 spin_lock_irqsave(&bnad->bna_lock, flags);
3345 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
f859d7cb 3346 set_bit(vid, bnad->active_vlans);
8b230ed8
RM		 3347 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3348
3349 mutex_unlock(&bnad->conf_mutex);
8e586137
JP		 3350
3351 return 0;
8b230ed8
RM		 3352}
3353
8e586137 3354static int
80d5c368 3355bnad_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
8b230ed8
RM		 3356{
3357 struct bnad *bnad = netdev_priv(netdev);
3358 unsigned long flags;
3359
3360 if (!bnad->rx_info[0].rx)
8e586137 3361 return 0;
8b230ed8
RM		 3362
3363 mutex_lock(&bnad->conf_mutex);
3364
3365 spin_lock_irqsave(&bnad->bna_lock, flags);
f859d7cb 3366 clear_bit(vid, bnad->active_vlans);
8b230ed8
RM		 3367 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
3368 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3369
3370 mutex_unlock(&bnad->conf_mutex);
8e586137
JP		 3371
3372 return 0;
8b230ed8
RM		 3373}
3374
877767dc
IV		 3375static int bnad_set_features(struct net_device *dev, netdev_features_t features)
3376{
3377 struct bnad *bnad = netdev_priv(dev);
3378 netdev_features_t changed = features ^ dev->features;
3379
3380 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(dev)) {
3381 unsigned long flags;
3382
3383 spin_lock_irqsave(&bnad->bna_lock, flags);
3384
3385 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3386 bna_rx_vlan_strip_enable(bnad->rx_info[0].rx);
3387 else
3388 bna_rx_vlan_strip_disable(bnad->rx_info[0].rx);
3389
3390 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3391 }
3392
3393 return 0;
3394}
3395
8b230ed8
RM		 3396#ifdef CONFIG_NET_POLL_CONTROLLER
3397static void
3398bnad_netpoll(struct net_device *netdev)
3399{
3400 struct bnad *bnad = netdev_priv(netdev);
3401 struct bnad_rx_info *rx_info;
3402 struct bnad_rx_ctrl *rx_ctrl;
3403 u32 curr_mask;
3404 int i, j;
3405
3406 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
3407 bna_intx_disable(&bnad->bna, curr_mask);
3408 bnad_isr(bnad->pcidev->irq, netdev);
3409 bna_intx_enable(&bnad->bna, curr_mask);
3410 } else {
19dbff9f
RM		 3411 /*
3412 * Tx processing may happen in sending context, so no need
3413 * to explicitly process completions here
3414 */
3415
3416 /* Rx processing */
8b230ed8
RM		 3417 for (i = 0; i < bnad->num_rx; i++) {
3418 rx_info = &bnad->rx_info[i];
3419 if (!rx_info->rx)
3420 continue;
3421 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
3422 rx_ctrl = &rx_info->rx_ctrl[j];
271e8b79 3423 if (rx_ctrl->ccb)
8b230ed8
RM		 3424 bnad_netif_rx_schedule_poll(bnad,
3425 rx_ctrl->ccb);
8b230ed8
RM		 3426 }
3427 }
3428 }
3429}
3430#endif
3431
3432static const struct net_device_ops bnad_netdev_ops = {
3433 .ndo_open = bnad_open,
3434 .ndo_stop = bnad_stop,
3435 .ndo_start_xmit = bnad_start_xmit,
250e061e 3436 .ndo_get_stats64 = bnad_get_stats64,
8b230ed8 3437 .ndo_set_rx_mode = bnad_set_rx_mode,
8b230ed8
RM		 3438 .ndo_validate_addr = eth_validate_addr,
3439 .ndo_set_mac_address = bnad_set_mac_address,
3440 .ndo_change_mtu = bnad_change_mtu,
8b230ed8
RM		 3441 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
3442 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
877767dc 3443 .ndo_set_features = bnad_set_features,
8b230ed8
RM		 3444#ifdef CONFIG_NET_POLL_CONTROLLER
3445 .ndo_poll_controller = bnad_netpoll
3446#endif
3447};
3448
3449static void
3450bnad_netdev_init(struct bnad *bnad, bool using_dac)
3451{
3452 struct net_device *netdev = bnad->netdev;
3453
e5ee20e7
MM		 3454 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3455 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
877767dc
IV		 3456 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_TX |
3457 NETIF_F_HW_VLAN_CTAG_RX;
8b230ed8 3458
e5ee20e7
MM		 3459 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
3460 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3461 NETIF_F_TSO | NETIF_F_TSO6;
8b230ed8 3462
877767dc 3463 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
8b230ed8
RM		 3464
3465 if (using_dac)
3466 netdev->features |= NETIF_F_HIGHDMA;
3467
8b230ed8
RM		 3468 netdev->mem_start = bnad->mmio_start;
3469 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
3470
3471 netdev->netdev_ops = &bnad_netdev_ops;
3472 bnad_set_ethtool_ops(netdev);
3473}
3474
3475/*
3476 * 1. Initialize the bnad structure
3477 * 2. Setup netdev pointer in pci_dev
d95d1081
JH		 3478 * 3. Initialize no. of TxQ & CQs & MSIX vectors
3479 * 4. Initialize work queue.
8b230ed8
RM		 3480 */
3481static int
3482bnad_init(struct bnad *bnad,
3483 struct pci_dev *pdev, struct net_device *netdev)
3484{
3485 unsigned long flags;
3486
3487 SET_NETDEV_DEV(netdev, &pdev->dev);
3488 pci_set_drvdata(pdev, netdev);
3489
3490 bnad->netdev = netdev;
3491 bnad->pcidev = pdev;
3492 bnad->mmio_start = pci_resource_start(pdev, 0);
3493 bnad->mmio_len = pci_resource_len(pdev, 0);
3494 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
3495 if (!bnad->bar0) {
3496 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
8b230ed8
RM		 3497 return -ENOMEM;
3498 }
3499 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
3500 (unsigned long long) bnad->mmio_len);
3501
3502 spin_lock_irqsave(&bnad->bna_lock, flags);
3503 if (!bnad_msix_disable)
3504 bnad->cfg_flags = BNAD_CF_MSIX;
3505
3506 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
3507
3508 bnad_q_num_init(bnad);
3509 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3510
3511 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
3512 (bnad->num_rx * bnad->num_rxp_per_rx) +
3513 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8
RM		 3514
3515 bnad->txq_depth = BNAD_TXQ_DEPTH;
3516 bnad->rxq_depth = BNAD_RXQ_DEPTH;
8b230ed8
RM		 3517
3518 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3519 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
3520
01b54b14
JH		 3521 sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id);
3522 bnad->work_q = create_singlethread_workqueue(bnad->wq_name);
ba21fc69
WY		 3523 if (!bnad->work_q) {
3524 iounmap(bnad->bar0);
01b54b14 3525 return -ENOMEM;
ba21fc69 3526 }
01b54b14 3527
8b230ed8
RM		 3528 return 0;
3529}
3530
3531/*
3532 * Must be called after bnad_pci_uninit()
3533 * so that iounmap() and pci_set_drvdata(NULL)
3534 * happens only after PCI uninitialization.
3535 */
3536static void
3537bnad_uninit(struct bnad *bnad)
3538{
01b54b14
JH		 3539 if (bnad->work_q) {
3540 flush_workqueue(bnad->work_q);
3541 destroy_workqueue(bnad->work_q);
3542 bnad->work_q = NULL;
3543 }
3544
8b230ed8
RM		 3545 if (bnad->bar0)
3546 iounmap(bnad->bar0);
8b230ed8
RM		 3547}
3548
3549/*
3550 * Initialize locks
078086f3 3551 a) Per ioceth mutes used for serializing configuration
8b230ed8
RM		 3552 changes from OS interface
3553 b) spin lock used to protect bna state machine
3554 */
3555static void
3556bnad_lock_init(struct bnad *bnad)
3557{
3558 spin_lock_init(&bnad->bna_lock);
3559 mutex_init(&bnad->conf_mutex);
72a9730b 3560 mutex_init(&bnad_list_mutex);
8b230ed8
RM		 3561}
3562
3563static void
3564bnad_lock_uninit(struct bnad *bnad)
3565{
3566 mutex_destroy(&bnad->conf_mutex);
72a9730b 3567 mutex_destroy(&bnad_list_mutex);
8b230ed8
RM		 3568}
3569
3570/* PCI Initialization */
3571static int
3572bnad_pci_init(struct bnad *bnad,
3573 struct pci_dev *pdev, bool *using_dac)
3574{
3575 int err;
3576
3577 err = pci_enable_device(pdev);
3578 if (err)
3579 return err;
3580 err = pci_request_regions(pdev, BNAD_NAME);
3581 if (err)
3582 goto disable_device;
3e548079 3583 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
3db1cd5c 3584 *using_dac = true;
8b230ed8 3585 } else {
3e548079
RK		 3586 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3587 if (err)
3588 goto release_regions;
3db1cd5c 3589 *using_dac = false;
8b230ed8
RM		 3590 }
3591 pci_set_master(pdev);
3592 return 0;
3593
3594release_regions:
3595 pci_release_regions(pdev);
3596disable_device:
3597 pci_disable_device(pdev);
3598
3599 return err;
3600}
3601
3602static void
3603bnad_pci_uninit(struct pci_dev *pdev)
3604{
3605 pci_release_regions(pdev);
3606 pci_disable_device(pdev);
3607}
3608
c4eef189 3609static int
8b230ed8
RM		 3610bnad_pci_probe(struct pci_dev *pdev,
3611 const struct pci_device_id *pcidev_id)
3612{
3caa1e95 3613 bool using_dac;
0120b99c 3614 int err;
8b230ed8
RM		 3615 struct bnad *bnad;
3616 struct bna *bna;
3617 struct net_device *netdev;
3618 struct bfa_pcidev pcidev_info;
3619 unsigned long flags;
3620
3621 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3622 pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3623
3624 mutex_lock(&bnad_fwimg_mutex);
3625 if (!cna_get_firmware_buf(pdev)) {
3626 mutex_unlock(&bnad_fwimg_mutex);
3627 pr_warn("Failed to load Firmware Image!\n");
3628 return -ENODEV;
3629 }
3630 mutex_unlock(&bnad_fwimg_mutex);
3631
3632 /*
3633 * Allocates sizeof(struct net_device + struct bnad)
3634 * bnad = netdev->priv
3635 */
3636 netdev = alloc_etherdev(sizeof(struct bnad));
3637 if (!netdev) {
8b230ed8
RM		 3638 err = -ENOMEM;
3639 return err;
3640 }
3641 bnad = netdev_priv(netdev);
078086f3 3642 bnad_lock_init(bnad);
72a9730b 3643 bnad_add_to_list(bnad);
078086f3
RM		 3644
3645 mutex_lock(&bnad->conf_mutex);
8b230ed8
RM		 3646 /*
3647 * PCI initialization
0120b99c 3648 * Output : using_dac = 1 for 64 bit DMA
be7fa326 3649 * = 0 for 32 bit DMA
8b230ed8 3650 */
e905ed57 3651 using_dac = false;
8b230ed8
RM		 3652 err = bnad_pci_init(bnad, pdev, &using_dac);
3653 if (err)
44861f44 3654 goto unlock_mutex;
8b230ed8 3655
8b230ed8
RM		 3656 /*
3657 * Initialize bnad structure
3658 * Setup relation between pci_dev & netdev
8b230ed8
RM		 3659 */
3660 err = bnad_init(bnad, pdev, netdev);
3661 if (err)
3662 goto pci_uninit;
078086f3 3663
8b230ed8
RM		 3664 /* Initialize netdev structure, set up ethtool ops */
3665 bnad_netdev_init(bnad, using_dac);
3666
815f41e7
RM		 3667 /* Set link to down state */
3668 netif_carrier_off(netdev);
3669
7afc5dbd
KG		 3670 /* Setup the debugfs node for this bfad */
3671 if (bna_debugfs_enable)
3672 bnad_debugfs_init(bnad);
3673
8b230ed8 3674 /* Get resource requirement form bna */
078086f3 3675 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 3676 bna_res_req(&bnad->res_info[0]);
078086f3 3677 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 3678
3679 /* Allocate resources from bna */
078086f3 3680 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
8b230ed8 3681 if (err)
078086f3 3682 goto drv_uninit;
8b230ed8
RM		 3683
3684 bna = &bnad->bna;
3685
3686 /* Setup pcidev_info for bna_init() */
3687 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3688 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3689 pcidev_info.device_id = bnad->pcidev->device;
3690 pcidev_info.pci_bar_kva = bnad->bar0;
3691
8b230ed8
RM		 3692 spin_lock_irqsave(&bnad->bna_lock, flags);
3693 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
8b230ed8
RM		 3694 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3695
3696 bnad->stats.bna_stats = &bna->stats;
3697
078086f3
RM		 3698 bnad_enable_msix(bnad);
3699 err = bnad_mbox_irq_alloc(bnad);
3700 if (err)
3701 goto res_free;
3702
8b230ed8 3703 /* Set up timers */
078086f3 3704 setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
8b230ed8 3705 ((unsigned long)bnad));
078086f3 3706 setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
8b230ed8 3707 ((unsigned long)bnad));
078086f3 3708 setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
1d32f769 3709 ((unsigned long)bnad));
078086f3 3710 setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
8b230ed8
RM		 3711 ((unsigned long)bnad));
3712
3713 /* Now start the timer before calling IOC */
078086f3 3714 mod_timer(&bnad->bna.ioceth.ioc.iocpf_timer,
8b230ed8
RM		 3715 jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
3716
3717 /*
3718 * Start the chip
078086f3
RM		 3719 * If the call back comes with error, we bail out.
3720 * This is a catastrophic error.
8b230ed8 3721 */
078086f3
RM		 3722 err = bnad_ioceth_enable(bnad);
3723 if (err) {
3724 pr_err("BNA: Initialization failed err=%d\n",
3725 err);
3726 goto probe_success;
3727 }
3728
3729 spin_lock_irqsave(&bnad->bna_lock, flags);
3730 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3731 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) {
3732 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1,
3733 bna_attr(bna)->num_rxp - 1);
3734 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3735 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1))
3736 err = -EIO;
3737 }
3caa1e95
RM		 3738 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3739 if (err)
3740 goto disable_ioceth;
3741
3742 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 3743 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]);
3744 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3745
3746 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
0caa9aae
RM		 3747 if (err) {
3748 err = -EIO;
078086f3 3749 goto disable_ioceth;
0caa9aae 3750 }
078086f3
RM		 3751
3752 spin_lock_irqsave(&bnad->bna_lock, flags);
3753 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]);
3754 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 3755
3756 /* Get the burnt-in mac */
3757 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 3758 bna_enet_perm_mac_get(&bna->enet, &bnad->perm_addr);
8b230ed8
RM		 3759 bnad_set_netdev_perm_addr(bnad);
3760 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3761
0caa9aae
RM		 3762 mutex_unlock(&bnad->conf_mutex);
3763
8b230ed8
RM		 3764 /* Finally, reguister with net_device layer */
3765 err = register_netdev(netdev);
3766 if (err) {
3767 pr_err("BNA : Registering with netdev failed\n");
078086f3 3768 goto probe_uninit;
8b230ed8 3769 }
078086f3 3770 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
8b230ed8 3771
0caa9aae
RM		 3772 return 0;
3773
078086f3
RM		 3774probe_success:
3775 mutex_unlock(&bnad->conf_mutex);
8b230ed8
RM		 3776 return 0;
3777
078086f3 3778probe_uninit:
3fc72370 3779 mutex_lock(&bnad->conf_mutex);
078086f3
RM		 3780 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3781disable_ioceth:
3782 bnad_ioceth_disable(bnad);
3783 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3784 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3785 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
8b230ed8
RM		 3786 spin_lock_irqsave(&bnad->bna_lock, flags);
3787 bna_uninit(bna);
3788 spin_unlock_irqrestore(&bnad->bna_lock, flags);
078086f3 3789 bnad_mbox_irq_free(bnad);
8b230ed8 3790 bnad_disable_msix(bnad);
078086f3
RM		 3791res_free:
3792 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3793drv_uninit:
7afc5dbd
KG		 3794 /* Remove the debugfs node for this bnad */
3795 kfree(bnad->regdata);
3796 bnad_debugfs_uninit(bnad);
078086f3 3797 bnad_uninit(bnad);
8b230ed8
RM		 3798pci_uninit:
3799 bnad_pci_uninit(pdev);
44861f44 3800unlock_mutex:
078086f3 3801 mutex_unlock(&bnad->conf_mutex);
72a9730b 3802 bnad_remove_from_list(bnad);
8b230ed8 3803 bnad_lock_uninit(bnad);
8b230ed8
RM		 3804 free_netdev(netdev);
3805 return err;
3806}
3807
c4eef189 3808static void
8b230ed8
RM		 3809bnad_pci_remove(struct pci_dev *pdev)
3810{
3811 struct net_device *netdev = pci_get_drvdata(pdev);
3812 struct bnad *bnad;
3813 struct bna *bna;
3814 unsigned long flags;
3815
3816 if (!netdev)
3817 return;
3818
3819 pr_info("%s bnad_pci_remove\n", netdev->name);
3820 bnad = netdev_priv(netdev);
3821 bna = &bnad->bna;
3822
078086f3
RM		 3823 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags))
3824 unregister_netdev(netdev);
8b230ed8
RM		 3825
3826 mutex_lock(&bnad->conf_mutex);
078086f3
RM		 3827 bnad_ioceth_disable(bnad);
3828 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3829 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3830 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
8b230ed8
RM		 3831 spin_lock_irqsave(&bnad->bna_lock, flags);
3832 bna_uninit(bna);
3833 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 3834
078086f3
RM		 3835 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3836 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3837 bnad_mbox_irq_free(bnad);
8b230ed8
RM		 3838 bnad_disable_msix(bnad);
3839 bnad_pci_uninit(pdev);
078086f3 3840 mutex_unlock(&bnad->conf_mutex);
72a9730b 3841 bnad_remove_from_list(bnad);
8b230ed8 3842 bnad_lock_uninit(bnad);
7afc5dbd
KG		 3843 /* Remove the debugfs node for this bnad */
3844 kfree(bnad->regdata);
3845 bnad_debugfs_uninit(bnad);
8b230ed8
RM		 3846 bnad_uninit(bnad);
3847 free_netdev(netdev);
3848}
3849
0120b99c 3850static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table) = {
8b230ed8
RM		 3851 {
3852 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3853 PCI_DEVICE_ID_BROCADE_CT),
3854 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3855 .class_mask = 0xffff00
586b2816
RM		 3856 },
3857 {
3858 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3859 BFA_PCI_DEVICE_ID_CT2),
3860 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3861 .class_mask = 0xffff00
3862 },
3863 {0, },
8b230ed8
RM		 3864};
3865
3866MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3867
3868static struct pci_driver bnad_pci_driver = {
3869 .name = BNAD_NAME,
3870 .id_table = bnad_pci_id_table,
3871 .probe = bnad_pci_probe,
c4eef189 3872 .remove = bnad_pci_remove,
8b230ed8
RM		 3873};
3874
3875static int __init
3876bnad_module_init(void)
3877{
3878 int err;
3879
5aad0011
RM		 3880 pr_info("Brocade 10G Ethernet driver - version: %s\n",
3881 BNAD_VERSION);
8b230ed8 3882
8a891429 3883 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
8b230ed8
RM		 3884
3885 err = pci_register_driver(&bnad_pci_driver);
3886 if (err < 0) {
3887 pr_err("bna : PCI registration failed in module init "
3888 "(%d)\n", err);
3889 return err;
3890 }
3891
3892 return 0;
3893}
3894
3895static void __exit
3896bnad_module_exit(void)
3897{
3898 pci_unregister_driver(&bnad_pci_driver);
294ca868 3899 release_firmware(bfi_fw);
8b230ed8
RM		 3900}
3901
3902module_init(bnad_module_init);
3903module_exit(bnad_module_exit);
3904
3905MODULE_AUTHOR("Brocade");
3906MODULE_LICENSE("GPL");
3907MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3908MODULE_VERSION(BNAD_VERSION);
3909MODULE_FIRMWARE(CNA_FW_FILE_CT);
1bf9fd70 3910MODULE_FIRMWARE(CNA_FW_FILE_CT2);
Ubuntu Jammy Linux kernel mirror