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Commit | Line | Data |
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8b230ed8 | 1 | /* |
2732ba56 | 2 | * Linux network driver for QLogic BR-series Converged Network Adapter. |
8b230ed8 RM |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License (GPL) Version 2 as | |
6 | * published by the Free Software Foundation | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | */ | |
13 | /* | |
2732ba56 RM |
14 | * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. |
15 | * Copyright (c) 2014-2015 QLogic Corporation | |
8b230ed8 | 16 | * All rights reserved |
2732ba56 | 17 | * www.qlogic.com |
8b230ed8 | 18 | */ |
f859d7cb | 19 | #include <linux/bitops.h> |
8b230ed8 RM |
20 | #include <linux/netdevice.h> |
21 | #include <linux/skbuff.h> | |
22 | #include <linux/etherdevice.h> | |
23 | #include <linux/in.h> | |
24 | #include <linux/ethtool.h> | |
25 | #include <linux/if_vlan.h> | |
26 | #include <linux/if_ether.h> | |
27 | #include <linux/ip.h> | |
70c71606 | 28 | #include <linux/prefetch.h> |
9d9779e7 | 29 | #include <linux/module.h> |
8b230ed8 RM |
30 | |
31 | #include "bnad.h" | |
32 | #include "bna.h" | |
33 | #include "cna.h" | |
34 | ||
b7ee31c5 | 35 | static DEFINE_MUTEX(bnad_fwimg_mutex); |
8b230ed8 RM |
36 | |
37 | /* | |
38 | * Module params | |
39 | */ | |
40 | static uint bnad_msix_disable; | |
41 | module_param(bnad_msix_disable, uint, 0444); | |
42 | MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode"); | |
43 | ||
44 | static uint bnad_ioc_auto_recover = 1; | |
45 | module_param(bnad_ioc_auto_recover, uint, 0444); | |
46 | MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery"); | |
47 | ||
7afc5dbd KG |
48 | static uint bna_debugfs_enable = 1; |
49 | module_param(bna_debugfs_enable, uint, S_IRUGO | S_IWUSR); | |
50 | MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1," | |
51 | " Range[false:0|true:1]"); | |
52 | ||
8b230ed8 RM |
53 | /* |
54 | * Global variables | |
55 | */ | |
482da0fa | 56 | static u32 bnad_rxqs_per_cq = 2; |
285eb9c3 | 57 | static atomic_t bna_id; |
e2f9ecfc IV |
58 | static const u8 bnad_bcast_addr[] __aligned(2) = |
59 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
8b230ed8 RM |
60 | |
61 | /* | |
62 | * Local MACROS | |
63 | */ | |
8b230ed8 RM |
64 | #define BNAD_GET_MBOX_IRQ(_bnad) \ |
65 | (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \ | |
8811e267 | 66 | ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \ |
8b230ed8 RM |
67 | ((_bnad)->pcidev->irq)) |
68 | ||
5216562a | 69 | #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \ |
8b230ed8 RM |
70 | do { \ |
71 | (_res_info)->res_type = BNA_RES_T_MEM; \ | |
72 | (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \ | |
73 | (_res_info)->res_u.mem_info.num = (_num); \ | |
5216562a | 74 | (_res_info)->res_u.mem_info.len = (_size); \ |
8b230ed8 RM |
75 | } while (0) |
76 | ||
77 | /* | |
78 | * Reinitialize completions in CQ, once Rx is taken down | |
79 | */ | |
80 | static void | |
b3cc6e88 | 81 | bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb) |
8b230ed8 | 82 | { |
5216562a | 83 | struct bna_cq_entry *cmpl; |
8b230ed8 RM |
84 | int i; |
85 | ||
8b230ed8 | 86 | for (i = 0; i < ccb->q_depth; i++) { |
5216562a | 87 | cmpl = &((struct bna_cq_entry *)ccb->sw_q)[i]; |
8b230ed8 | 88 | cmpl->valid = 0; |
8b230ed8 RM |
89 | } |
90 | } | |
91 | ||
5216562a RM |
92 | /* Tx Datapath functions */ |
93 | ||
94 | ||
95 | /* Caller should ensure that the entry at unmap_q[index] is valid */ | |
271e8b79 | 96 | static u32 |
5216562a RM |
97 | bnad_tx_buff_unmap(struct bnad *bnad, |
98 | struct bnad_tx_unmap *unmap_q, | |
99 | u32 q_depth, u32 index) | |
271e8b79 | 100 | { |
5216562a RM |
101 | struct bnad_tx_unmap *unmap; |
102 | struct sk_buff *skb; | |
103 | int vector, nvecs; | |
104 | ||
105 | unmap = &unmap_q[index]; | |
106 | nvecs = unmap->nvecs; | |
107 | ||
108 | skb = unmap->skb; | |
109 | unmap->skb = NULL; | |
110 | unmap->nvecs = 0; | |
111 | dma_unmap_single(&bnad->pcidev->dev, | |
112 | dma_unmap_addr(&unmap->vectors[0], dma_addr), | |
113 | skb_headlen(skb), DMA_TO_DEVICE); | |
114 | dma_unmap_addr_set(&unmap->vectors[0], dma_addr, 0); | |
115 | nvecs--; | |
116 | ||
117 | vector = 0; | |
118 | while (nvecs) { | |
119 | vector++; | |
120 | if (vector == BFI_TX_MAX_VECTORS_PER_WI) { | |
121 | vector = 0; | |
122 | BNA_QE_INDX_INC(index, q_depth); | |
123 | unmap = &unmap_q[index]; | |
124 | } | |
271e8b79 | 125 | |
5216562a RM |
126 | dma_unmap_page(&bnad->pcidev->dev, |
127 | dma_unmap_addr(&unmap->vectors[vector], dma_addr), | |
24f5d33d RM |
128 | dma_unmap_len(&unmap->vectors[vector], dma_len), |
129 | DMA_TO_DEVICE); | |
5216562a RM |
130 | dma_unmap_addr_set(&unmap->vectors[vector], dma_addr, 0); |
131 | nvecs--; | |
271e8b79 RM |
132 | } |
133 | ||
5216562a RM |
134 | BNA_QE_INDX_INC(index, q_depth); |
135 | ||
271e8b79 RM |
136 | return index; |
137 | } | |
138 | ||
8b230ed8 RM |
139 | /* |
140 | * Frees all pending Tx Bufs | |
141 | * At this point no activity is expected on the Q, | |
142 | * so DMA unmap & freeing is fine. | |
143 | */ | |
144 | static void | |
5216562a | 145 | bnad_txq_cleanup(struct bnad *bnad, struct bna_tcb *tcb) |
8b230ed8 | 146 | { |
5216562a RM |
147 | struct bnad_tx_unmap *unmap_q = tcb->unmap_q; |
148 | struct sk_buff *skb; | |
149 | int i; | |
8b230ed8 | 150 | |
5216562a RM |
151 | for (i = 0; i < tcb->q_depth; i++) { |
152 | skb = unmap_q[i].skb; | |
938fa488 | 153 | if (!skb) |
8b230ed8 | 154 | continue; |
5216562a | 155 | bnad_tx_buff_unmap(bnad, unmap_q, tcb->q_depth, i); |
938fa488 | 156 | |
8b230ed8 RM |
157 | dev_kfree_skb_any(skb); |
158 | } | |
159 | } | |
160 | ||
8b230ed8 | 161 | /* |
b3cc6e88 | 162 | * bnad_txcmpl_process : Frees the Tx bufs on Tx completion |
8b230ed8 RM |
163 | * Can be called in a) Interrupt context |
164 | * b) Sending context | |
8b230ed8 RM |
165 | */ |
166 | static u32 | |
5216562a | 167 | bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb) |
8b230ed8 | 168 | { |
5216562a RM |
169 | u32 sent_packets = 0, sent_bytes = 0; |
170 | u32 wis, unmap_wis, hw_cons, cons, q_depth; | |
171 | struct bnad_tx_unmap *unmap_q = tcb->unmap_q; | |
172 | struct bnad_tx_unmap *unmap; | |
173 | struct sk_buff *skb; | |
8b230ed8 | 174 | |
d95d1081 | 175 | /* Just return if TX is stopped */ |
be7fa326 | 176 | if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) |
8b230ed8 RM |
177 | return 0; |
178 | ||
5216562a | 179 | hw_cons = *(tcb->hw_consumer_index); |
d667f785 | 180 | rmb(); |
5216562a RM |
181 | cons = tcb->consumer_index; |
182 | q_depth = tcb->q_depth; | |
8b230ed8 | 183 | |
5216562a | 184 | wis = BNA_Q_INDEX_CHANGE(cons, hw_cons, q_depth); |
8b230ed8 RM |
185 | BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth))); |
186 | ||
8b230ed8 | 187 | while (wis) { |
5216562a RM |
188 | unmap = &unmap_q[cons]; |
189 | ||
190 | skb = unmap->skb; | |
8b230ed8 | 191 | |
8b230ed8 RM |
192 | sent_packets++; |
193 | sent_bytes += skb->len; | |
8b230ed8 | 194 | |
5216562a RM |
195 | unmap_wis = BNA_TXQ_WI_NEEDED(unmap->nvecs); |
196 | wis -= unmap_wis; | |
8b230ed8 | 197 | |
5216562a | 198 | cons = bnad_tx_buff_unmap(bnad, unmap_q, q_depth, cons); |
8b230ed8 RM |
199 | dev_kfree_skb_any(skb); |
200 | } | |
201 | ||
202 | /* Update consumer pointers. */ | |
5216562a | 203 | tcb->consumer_index = hw_cons; |
8b230ed8 RM |
204 | |
205 | tcb->txq->tx_packets += sent_packets; | |
206 | tcb->txq->tx_bytes += sent_bytes; | |
207 | ||
208 | return sent_packets; | |
209 | } | |
210 | ||
8b230ed8 | 211 | static u32 |
b3cc6e88 | 212 | bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb) |
8b230ed8 RM |
213 | { |
214 | struct net_device *netdev = bnad->netdev; | |
be7fa326 | 215 | u32 sent = 0; |
8b230ed8 RM |
216 | |
217 | if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) | |
218 | return 0; | |
219 | ||
b3cc6e88 | 220 | sent = bnad_txcmpl_process(bnad, tcb); |
8b230ed8 RM |
221 | if (sent) { |
222 | if (netif_queue_stopped(netdev) && | |
223 | netif_carrier_ok(netdev) && | |
224 | BNA_QE_FREE_CNT(tcb, tcb->q_depth) >= | |
225 | BNAD_NETIF_WAKE_THRESHOLD) { | |
be7fa326 RM |
226 | if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) { |
227 | netif_wake_queue(netdev); | |
228 | BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); | |
229 | } | |
8b230ed8 | 230 | } |
be7fa326 RM |
231 | } |
232 | ||
233 | if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) | |
8b230ed8 | 234 | bna_ib_ack(tcb->i_dbell, sent); |
8b230ed8 | 235 | |
4e857c58 | 236 | smp_mb__before_atomic(); |
8b230ed8 RM |
237 | clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); |
238 | ||
239 | return sent; | |
240 | } | |
241 | ||
242 | /* MSIX Tx Completion Handler */ | |
243 | static irqreturn_t | |
244 | bnad_msix_tx(int irq, void *data) | |
245 | { | |
246 | struct bna_tcb *tcb = (struct bna_tcb *)data; | |
247 | struct bnad *bnad = tcb->bnad; | |
248 | ||
b3cc6e88 | 249 | bnad_tx_complete(bnad, tcb); |
8b230ed8 RM |
250 | |
251 | return IRQ_HANDLED; | |
252 | } | |
253 | ||
30f9fc94 RM |
254 | static inline void |
255 | bnad_rxq_alloc_uninit(struct bnad *bnad, struct bna_rcb *rcb) | |
256 | { | |
257 | struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; | |
258 | ||
259 | unmap_q->reuse_pi = -1; | |
260 | unmap_q->alloc_order = -1; | |
261 | unmap_q->map_size = 0; | |
262 | unmap_q->type = BNAD_RXBUF_NONE; | |
263 | } | |
264 | ||
265 | /* Default is page-based allocation. Multi-buffer support - TBD */ | |
266 | static int | |
267 | bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb) | |
268 | { | |
269 | struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; | |
e29aa339 | 270 | int order; |
30f9fc94 RM |
271 | |
272 | bnad_rxq_alloc_uninit(bnad, rcb); | |
273 | ||
e29aa339 RM |
274 | order = get_order(rcb->rxq->buffer_size); |
275 | ||
276 | unmap_q->type = BNAD_RXBUF_PAGE; | |
30f9fc94 RM |
277 | |
278 | if (bna_is_small_rxq(rcb->id)) { | |
279 | unmap_q->alloc_order = 0; | |
280 | unmap_q->map_size = rcb->rxq->buffer_size; | |
281 | } else { | |
e29aa339 RM |
282 | if (rcb->rxq->multi_buffer) { |
283 | unmap_q->alloc_order = 0; | |
284 | unmap_q->map_size = rcb->rxq->buffer_size; | |
285 | unmap_q->type = BNAD_RXBUF_MULTI_BUFF; | |
286 | } else { | |
287 | unmap_q->alloc_order = order; | |
288 | unmap_q->map_size = | |
289 | (rcb->rxq->buffer_size > 2048) ? | |
290 | PAGE_SIZE << order : 2048; | |
291 | } | |
30f9fc94 RM |
292 | } |
293 | ||
ebb56d37 | 294 | BUG_ON((PAGE_SIZE << order) % unmap_q->map_size); |
30f9fc94 | 295 | |
30f9fc94 RM |
296 | return 0; |
297 | } | |
298 | ||
299 | static inline void | |
300 | bnad_rxq_cleanup_page(struct bnad *bnad, struct bnad_rx_unmap *unmap) | |
301 | { | |
302 | if (!unmap->page) | |
303 | return; | |
304 | ||
305 | dma_unmap_page(&bnad->pcidev->dev, | |
306 | dma_unmap_addr(&unmap->vector, dma_addr), | |
307 | unmap->vector.len, DMA_FROM_DEVICE); | |
308 | put_page(unmap->page); | |
309 | unmap->page = NULL; | |
310 | dma_unmap_addr_set(&unmap->vector, dma_addr, 0); | |
311 | unmap->vector.len = 0; | |
312 | } | |
313 | ||
314 | static inline void | |
315 | bnad_rxq_cleanup_skb(struct bnad *bnad, struct bnad_rx_unmap *unmap) | |
316 | { | |
317 | if (!unmap->skb) | |
318 | return; | |
319 | ||
320 | dma_unmap_single(&bnad->pcidev->dev, | |
321 | dma_unmap_addr(&unmap->vector, dma_addr), | |
322 | unmap->vector.len, DMA_FROM_DEVICE); | |
323 | dev_kfree_skb_any(unmap->skb); | |
324 | unmap->skb = NULL; | |
325 | dma_unmap_addr_set(&unmap->vector, dma_addr, 0); | |
326 | unmap->vector.len = 0; | |
327 | } | |
328 | ||
8b230ed8 | 329 | static void |
b3cc6e88 | 330 | bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb) |
8b230ed8 | 331 | { |
30f9fc94 | 332 | struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; |
5216562a RM |
333 | int i; |
334 | ||
335 | for (i = 0; i < rcb->q_depth; i++) { | |
30f9fc94 | 336 | struct bnad_rx_unmap *unmap = &unmap_q->unmap[i]; |
8b230ed8 | 337 | |
e29aa339 | 338 | if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) |
30f9fc94 | 339 | bnad_rxq_cleanup_skb(bnad, unmap); |
e29aa339 RM |
340 | else |
341 | bnad_rxq_cleanup_page(bnad, unmap); | |
30f9fc94 RM |
342 | } |
343 | bnad_rxq_alloc_uninit(bnad, rcb); | |
344 | } | |
5216562a | 345 | |
30f9fc94 RM |
346 | static u32 |
347 | bnad_rxq_refill_page(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc) | |
348 | { | |
349 | u32 alloced, prod, q_depth; | |
350 | struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; | |
351 | struct bnad_rx_unmap *unmap, *prev; | |
352 | struct bna_rxq_entry *rxent; | |
353 | struct page *page; | |
354 | u32 page_offset, alloc_size; | |
355 | dma_addr_t dma_addr; | |
356 | ||
357 | prod = rcb->producer_index; | |
358 | q_depth = rcb->q_depth; | |
359 | ||
360 | alloc_size = PAGE_SIZE << unmap_q->alloc_order; | |
361 | alloced = 0; | |
362 | ||
363 | while (nalloc--) { | |
364 | unmap = &unmap_q->unmap[prod]; | |
365 | ||
366 | if (unmap_q->reuse_pi < 0) { | |
367 | page = alloc_pages(GFP_ATOMIC | __GFP_COMP, | |
368 | unmap_q->alloc_order); | |
369 | page_offset = 0; | |
370 | } else { | |
371 | prev = &unmap_q->unmap[unmap_q->reuse_pi]; | |
372 | page = prev->page; | |
373 | page_offset = prev->page_offset + unmap_q->map_size; | |
374 | get_page(page); | |
375 | } | |
376 | ||
377 | if (unlikely(!page)) { | |
378 | BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed); | |
379 | rcb->rxq->rxbuf_alloc_failed++; | |
380 | goto finishing; | |
381 | } | |
382 | ||
383 | dma_addr = dma_map_page(&bnad->pcidev->dev, page, page_offset, | |
ba5ca784 IV |
384 | unmap_q->map_size, DMA_FROM_DEVICE); |
385 | if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { | |
386 | put_page(page); | |
387 | BNAD_UPDATE_CTR(bnad, rxbuf_map_failed); | |
388 | rcb->rxq->rxbuf_map_failed++; | |
389 | goto finishing; | |
390 | } | |
30f9fc94 RM |
391 | |
392 | unmap->page = page; | |
393 | unmap->page_offset = page_offset; | |
394 | dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr); | |
395 | unmap->vector.len = unmap_q->map_size; | |
396 | page_offset += unmap_q->map_size; | |
397 | ||
398 | if (page_offset < alloc_size) | |
399 | unmap_q->reuse_pi = prod; | |
400 | else | |
401 | unmap_q->reuse_pi = -1; | |
402 | ||
403 | rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod]; | |
404 | BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr); | |
405 | BNA_QE_INDX_INC(prod, q_depth); | |
406 | alloced++; | |
407 | } | |
408 | ||
409 | finishing: | |
410 | if (likely(alloced)) { | |
411 | rcb->producer_index = prod; | |
412 | smp_mb(); | |
413 | if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags))) | |
414 | bna_rxq_prod_indx_doorbell(rcb); | |
8b230ed8 | 415 | } |
30f9fc94 RM |
416 | |
417 | return alloced; | |
8b230ed8 RM |
418 | } |
419 | ||
30f9fc94 RM |
420 | static u32 |
421 | bnad_rxq_refill_skb(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc) | |
8b230ed8 | 422 | { |
30f9fc94 RM |
423 | u32 alloced, prod, q_depth, buff_sz; |
424 | struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; | |
5216562a | 425 | struct bnad_rx_unmap *unmap; |
8b230ed8 RM |
426 | struct bna_rxq_entry *rxent; |
427 | struct sk_buff *skb; | |
428 | dma_addr_t dma_addr; | |
429 | ||
5216562a | 430 | buff_sz = rcb->rxq->buffer_size; |
5216562a RM |
431 | prod = rcb->producer_index; |
432 | q_depth = rcb->q_depth; | |
8b230ed8 | 433 | |
30f9fc94 RM |
434 | alloced = 0; |
435 | while (nalloc--) { | |
436 | unmap = &unmap_q->unmap[prod]; | |
437 | ||
438 | skb = netdev_alloc_skb_ip_align(bnad->netdev, buff_sz); | |
439 | ||
8b230ed8 RM |
440 | if (unlikely(!skb)) { |
441 | BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed); | |
3caa1e95 | 442 | rcb->rxq->rxbuf_alloc_failed++; |
8b230ed8 RM |
443 | goto finishing; |
444 | } | |
ba5ca784 | 445 | |
5ea74318 | 446 | dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data, |
5216562a | 447 | buff_sz, DMA_FROM_DEVICE); |
ba5ca784 IV |
448 | if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { |
449 | dev_kfree_skb_any(skb); | |
450 | BNAD_UPDATE_CTR(bnad, rxbuf_map_failed); | |
451 | rcb->rxq->rxbuf_map_failed++; | |
452 | goto finishing; | |
453 | } | |
8b230ed8 | 454 | |
5216562a RM |
455 | unmap->skb = skb; |
456 | dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr); | |
457 | unmap->vector.len = buff_sz; | |
30f9fc94 RM |
458 | |
459 | rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod]; | |
460 | BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr); | |
5216562a | 461 | BNA_QE_INDX_INC(prod, q_depth); |
8b230ed8 RM |
462 | alloced++; |
463 | } | |
464 | ||
465 | finishing: | |
466 | if (likely(alloced)) { | |
5216562a | 467 | rcb->producer_index = prod; |
8b230ed8 | 468 | smp_mb(); |
5bcf6ac0 | 469 | if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags))) |
be7fa326 | 470 | bna_rxq_prod_indx_doorbell(rcb); |
8b230ed8 | 471 | } |
30f9fc94 RM |
472 | |
473 | return alloced; | |
474 | } | |
475 | ||
476 | static inline void | |
477 | bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb) | |
478 | { | |
479 | struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; | |
480 | u32 to_alloc; | |
481 | ||
482 | to_alloc = BNA_QE_FREE_CNT(rcb, rcb->q_depth); | |
483 | if (!(to_alloc >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)) | |
484 | return; | |
485 | ||
e29aa339 | 486 | if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) |
30f9fc94 | 487 | bnad_rxq_refill_skb(bnad, rcb, to_alloc); |
e29aa339 RM |
488 | else |
489 | bnad_rxq_refill_page(bnad, rcb, to_alloc); | |
8b230ed8 RM |
490 | } |
491 | ||
5e46631f RM |
492 | #define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ |
493 | BNA_CQ_EF_IPV6 | \ | |
494 | BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \ | |
495 | BNA_CQ_EF_L4_CKSUM_OK) | |
496 | ||
497 | #define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ | |
498 | BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK) | |
499 | #define flags_tcp6 (BNA_CQ_EF_IPV6 | \ | |
500 | BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK) | |
501 | #define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ | |
502 | BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK) | |
503 | #define flags_udp6 (BNA_CQ_EF_IPV6 | \ | |
504 | BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK) | |
505 | ||
e29aa339 RM |
506 | static void |
507 | bnad_cq_drop_packet(struct bnad *bnad, struct bna_rcb *rcb, | |
508 | u32 sop_ci, u32 nvecs) | |
30f9fc94 | 509 | { |
e29aa339 RM |
510 | struct bnad_rx_unmap_q *unmap_q; |
511 | struct bnad_rx_unmap *unmap; | |
512 | u32 ci, vec; | |
30f9fc94 | 513 | |
e29aa339 RM |
514 | unmap_q = rcb->unmap_q; |
515 | for (vec = 0, ci = sop_ci; vec < nvecs; vec++) { | |
516 | unmap = &unmap_q->unmap[ci]; | |
517 | BNA_QE_INDX_INC(ci, rcb->q_depth); | |
518 | ||
519 | if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) | |
520 | bnad_rxq_cleanup_skb(bnad, unmap); | |
521 | else | |
522 | bnad_rxq_cleanup_page(bnad, unmap); | |
523 | } | |
524 | } | |
525 | ||
526 | static void | |
6c3f5aef | 527 | bnad_cq_setup_skb_frags(struct bna_ccb *ccb, struct sk_buff *skb, u32 nvecs) |
e29aa339 | 528 | { |
6c3f5aef | 529 | struct bna_rcb *rcb; |
e29aa339 | 530 | struct bnad *bnad; |
e29aa339 | 531 | struct bnad_rx_unmap_q *unmap_q; |
6c3f5aef IV |
532 | struct bna_cq_entry *cq, *cmpl; |
533 | u32 ci, pi, totlen = 0; | |
534 | ||
535 | cq = ccb->sw_q; | |
536 | pi = ccb->producer_index; | |
537 | cmpl = &cq[pi]; | |
e29aa339 | 538 | |
6c3f5aef | 539 | rcb = bna_is_small_rxq(cmpl->rxq_id) ? ccb->rcb[1] : ccb->rcb[0]; |
e29aa339 RM |
540 | unmap_q = rcb->unmap_q; |
541 | bnad = rcb->bnad; | |
6c3f5aef | 542 | ci = rcb->consumer_index; |
66f9513a RM |
543 | |
544 | /* prefetch header */ | |
6c3f5aef IV |
545 | prefetch(page_address(unmap_q->unmap[ci].page) + |
546 | unmap_q->unmap[ci].page_offset); | |
547 | ||
548 | while (nvecs--) { | |
549 | struct bnad_rx_unmap *unmap; | |
550 | u32 len; | |
66f9513a | 551 | |
e29aa339 RM |
552 | unmap = &unmap_q->unmap[ci]; |
553 | BNA_QE_INDX_INC(ci, rcb->q_depth); | |
30f9fc94 RM |
554 | |
555 | dma_unmap_page(&bnad->pcidev->dev, | |
6c3f5aef IV |
556 | dma_unmap_addr(&unmap->vector, dma_addr), |
557 | unmap->vector.len, DMA_FROM_DEVICE); | |
e29aa339 | 558 | |
6c3f5aef | 559 | len = ntohs(cmpl->length); |
f2d9da1a | 560 | skb->truesize += unmap->vector.len; |
e29aa339 RM |
561 | totlen += len; |
562 | ||
30f9fc94 | 563 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, |
6c3f5aef | 564 | unmap->page, unmap->page_offset, len); |
30f9fc94 RM |
565 | |
566 | unmap->page = NULL; | |
567 | unmap->vector.len = 0; | |
6c3f5aef IV |
568 | |
569 | BNA_QE_INDX_INC(pi, ccb->q_depth); | |
570 | cmpl = &cq[pi]; | |
30f9fc94 RM |
571 | } |
572 | ||
e29aa339 RM |
573 | skb->len += totlen; |
574 | skb->data_len += totlen; | |
e29aa339 RM |
575 | } |
576 | ||
577 | static inline void | |
578 | bnad_cq_setup_skb(struct bnad *bnad, struct sk_buff *skb, | |
579 | struct bnad_rx_unmap *unmap, u32 len) | |
580 | { | |
581 | prefetch(skb->data); | |
30f9fc94 RM |
582 | |
583 | dma_unmap_single(&bnad->pcidev->dev, | |
584 | dma_unmap_addr(&unmap->vector, dma_addr), | |
585 | unmap->vector.len, DMA_FROM_DEVICE); | |
586 | ||
e29aa339 | 587 | skb_put(skb, len); |
30f9fc94 RM |
588 | skb->protocol = eth_type_trans(skb, bnad->netdev); |
589 | ||
590 | unmap->skb = NULL; | |
591 | unmap->vector.len = 0; | |
30f9fc94 RM |
592 | } |
593 | ||
8b230ed8 | 594 | static u32 |
b3cc6e88 | 595 | bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget) |
8b230ed8 | 596 | { |
e29aa339 | 597 | struct bna_cq_entry *cq, *cmpl, *next_cmpl; |
8b230ed8 | 598 | struct bna_rcb *rcb = NULL; |
30f9fc94 | 599 | struct bnad_rx_unmap_q *unmap_q; |
e29aa339 RM |
600 | struct bnad_rx_unmap *unmap = NULL; |
601 | struct sk_buff *skb = NULL; | |
8b230ed8 | 602 | struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate; |
30f9fc94 | 603 | struct bnad_rx_ctrl *rx_ctrl = ccb->ctrl; |
e29aa339 RM |
604 | u32 packets = 0, len = 0, totlen = 0; |
605 | u32 pi, vec, sop_ci = 0, nvecs = 0; | |
606 | u32 flags, masked_flags; | |
078086f3 | 607 | |
8b230ed8 | 608 | prefetch(bnad->netdev); |
5216562a RM |
609 | |
610 | cq = ccb->sw_q; | |
5216562a | 611 | |
17a30a14 | 612 | while (packets < budget) { |
c36c9d50 | 613 | cmpl = &cq[ccb->producer_index]; |
17a30a14 RM |
614 | if (!cmpl->valid) |
615 | break; | |
616 | /* The 'valid' field is set by the adapter, only after writing | |
617 | * the other fields of completion entry. Hence, do not load | |
618 | * other fields of completion entry *before* the 'valid' is | |
619 | * loaded. Adding the rmb() here prevents the compiler and/or | |
620 | * CPU from reordering the reads which would potentially result | |
621 | * in reading stale values in completion entry. | |
622 | */ | |
623 | rmb(); | |
624 | ||
8b230ed8 RM |
625 | BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length)); |
626 | ||
078086f3 | 627 | if (bna_is_small_rxq(cmpl->rxq_id)) |
8b230ed8 | 628 | rcb = ccb->rcb[1]; |
078086f3 RM |
629 | else |
630 | rcb = ccb->rcb[0]; | |
8b230ed8 RM |
631 | |
632 | unmap_q = rcb->unmap_q; | |
633 | ||
e29aa339 RM |
634 | /* start of packet ci */ |
635 | sop_ci = rcb->consumer_index; | |
636 | ||
637 | if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) { | |
638 | unmap = &unmap_q->unmap[sop_ci]; | |
639 | skb = unmap->skb; | |
640 | } else { | |
641 | skb = napi_get_frags(&rx_ctrl->napi); | |
642 | if (unlikely(!skb)) | |
643 | break; | |
644 | } | |
645 | prefetch(skb); | |
646 | ||
647 | flags = ntohl(cmpl->flags); | |
648 | len = ntohs(cmpl->length); | |
649 | totlen = len; | |
650 | nvecs = 1; | |
651 | ||
652 | /* Check all the completions for this frame. | |
653 | * busy-wait doesn't help much, break here. | |
654 | */ | |
655 | if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q->type) && | |
656 | (flags & BNA_CQ_EF_EOP) == 0) { | |
657 | pi = ccb->producer_index; | |
658 | do { | |
659 | BNA_QE_INDX_INC(pi, ccb->q_depth); | |
660 | next_cmpl = &cq[pi]; | |
661 | ||
662 | if (!next_cmpl->valid) | |
663 | break; | |
17a30a14 RM |
664 | /* The 'valid' field is set by the adapter, only |
665 | * after writing the other fields of completion | |
666 | * entry. Hence, do not load other fields of | |
667 | * completion entry *before* the 'valid' is | |
668 | * loaded. Adding the rmb() here prevents the | |
669 | * compiler and/or CPU from reordering the reads | |
670 | * which would potentially result in reading | |
671 | * stale values in completion entry. | |
672 | */ | |
673 | rmb(); | |
5216562a | 674 | |
e29aa339 RM |
675 | len = ntohs(next_cmpl->length); |
676 | flags = ntohl(next_cmpl->flags); | |
677 | ||
678 | nvecs++; | |
679 | totlen += len; | |
680 | } while ((flags & BNA_CQ_EF_EOP) == 0); | |
681 | ||
682 | if (!next_cmpl->valid) | |
683 | break; | |
684 | } | |
ade4dc3e | 685 | packets++; |
e29aa339 RM |
686 | |
687 | /* TODO: BNA_CQ_EF_LOCAL ? */ | |
688 | if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR | | |
689 | BNA_CQ_EF_FCS_ERROR | | |
690 | BNA_CQ_EF_TOO_LONG))) { | |
691 | bnad_cq_drop_packet(bnad, rcb, sop_ci, nvecs); | |
8b230ed8 | 692 | rcb->rxq->rx_packets_with_error++; |
e29aa339 | 693 | |
8b230ed8 RM |
694 | goto next; |
695 | } | |
696 | ||
e29aa339 RM |
697 | if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) |
698 | bnad_cq_setup_skb(bnad, skb, unmap, len); | |
699 | else | |
6c3f5aef | 700 | bnad_cq_setup_skb_frags(ccb, skb, nvecs); |
30f9fc94 | 701 | |
e29aa339 RM |
702 | rcb->rxq->rx_packets++; |
703 | rcb->rxq->rx_bytes += totlen; | |
704 | ccb->bytes_per_intr += totlen; | |
5e46631f RM |
705 | |
706 | masked_flags = flags & flags_cksum_prot_mask; | |
707 | ||
8b230ed8 | 708 | if (likely |
e5ee20e7 | 709 | ((bnad->netdev->features & NETIF_F_RXCSUM) && |
5e46631f RM |
710 | ((masked_flags == flags_tcp4) || |
711 | (masked_flags == flags_udp4) || | |
712 | (masked_flags == flags_tcp6) || | |
713 | (masked_flags == flags_udp6)))) | |
8b230ed8 RM |
714 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
715 | else | |
bc8acf2c | 716 | skb_checksum_none_assert(skb); |
8b230ed8 | 717 | |
877767dc IV |
718 | if ((flags & BNA_CQ_EF_VLAN) && |
719 | (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) | |
86a9bad3 | 720 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cmpl->vlan_tag)); |
f859d7cb | 721 | |
e29aa339 | 722 | if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) |
f859d7cb | 723 | netif_receive_skb(skb); |
e29aa339 RM |
724 | else |
725 | napi_gro_frags(&rx_ctrl->napi); | |
8b230ed8 RM |
726 | |
727 | next: | |
e29aa339 RM |
728 | BNA_QE_INDX_ADD(rcb->consumer_index, nvecs, rcb->q_depth); |
729 | for (vec = 0; vec < nvecs; vec++) { | |
730 | cmpl = &cq[ccb->producer_index]; | |
731 | cmpl->valid = 0; | |
732 | BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth); | |
733 | } | |
8b230ed8 RM |
734 | } |
735 | ||
30f9fc94 | 736 | napi_gro_flush(&rx_ctrl->napi, false); |
2be67144 | 737 | if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))) |
271e8b79 RM |
738 | bna_ib_ack_disable_irq(ccb->i_dbell, packets); |
739 | ||
5216562a | 740 | bnad_rxq_post(bnad, ccb->rcb[0]); |
2be67144 | 741 | if (ccb->rcb[1]) |
5216562a | 742 | bnad_rxq_post(bnad, ccb->rcb[1]); |
078086f3 | 743 | |
8b230ed8 RM |
744 | return packets; |
745 | } | |
746 | ||
8b230ed8 RM |
747 | static void |
748 | bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb) | |
749 | { | |
750 | struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl); | |
be7fa326 RM |
751 | struct napi_struct *napi = &rx_ctrl->napi; |
752 | ||
753 | if (likely(napi_schedule_prep(napi))) { | |
be7fa326 | 754 | __napi_schedule(napi); |
271e8b79 | 755 | rx_ctrl->rx_schedule++; |
8b230ed8 | 756 | } |
8b230ed8 RM |
757 | } |
758 | ||
759 | /* MSIX Rx Path Handler */ | |
760 | static irqreturn_t | |
761 | bnad_msix_rx(int irq, void *data) | |
762 | { | |
763 | struct bna_ccb *ccb = (struct bna_ccb *)data; | |
8b230ed8 | 764 | |
271e8b79 | 765 | if (ccb) { |
ebb56d37 | 766 | ((struct bnad_rx_ctrl *)ccb->ctrl)->rx_intr_ctr++; |
2be67144 | 767 | bnad_netif_rx_schedule_poll(ccb->bnad, ccb); |
271e8b79 | 768 | } |
8b230ed8 RM |
769 | |
770 | return IRQ_HANDLED; | |
771 | } | |
772 | ||
773 | /* Interrupt handlers */ | |
774 | ||
775 | /* Mbox Interrupt Handlers */ | |
776 | static irqreturn_t | |
777 | bnad_msix_mbox_handler(int irq, void *data) | |
778 | { | |
779 | u32 intr_status; | |
e2fa6f2e | 780 | unsigned long flags; |
be7fa326 | 781 | struct bnad *bnad = (struct bnad *)data; |
8b230ed8 | 782 | |
8b230ed8 | 783 | spin_lock_irqsave(&bnad->bna_lock, flags); |
dfee325a RM |
784 | if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) { |
785 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
786 | return IRQ_HANDLED; | |
787 | } | |
8b230ed8 RM |
788 | |
789 | bna_intr_status_get(&bnad->bna, intr_status); | |
790 | ||
078086f3 | 791 | if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status)) |
8b230ed8 RM |
792 | bna_mbox_handler(&bnad->bna, intr_status); |
793 | ||
794 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
795 | ||
8b230ed8 RM |
796 | return IRQ_HANDLED; |
797 | } | |
798 | ||
799 | static irqreturn_t | |
800 | bnad_isr(int irq, void *data) | |
801 | { | |
802 | int i, j; | |
803 | u32 intr_status; | |
804 | unsigned long flags; | |
be7fa326 | 805 | struct bnad *bnad = (struct bnad *)data; |
8b230ed8 RM |
806 | struct bnad_rx_info *rx_info; |
807 | struct bnad_rx_ctrl *rx_ctrl; | |
078086f3 | 808 | struct bna_tcb *tcb = NULL; |
8b230ed8 | 809 | |
dfee325a RM |
810 | spin_lock_irqsave(&bnad->bna_lock, flags); |
811 | if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) { | |
812 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
e2fa6f2e | 813 | return IRQ_NONE; |
dfee325a | 814 | } |
8b230ed8 RM |
815 | |
816 | bna_intr_status_get(&bnad->bna, intr_status); | |
e2fa6f2e | 817 | |
dfee325a RM |
818 | if (unlikely(!intr_status)) { |
819 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
8b230ed8 | 820 | return IRQ_NONE; |
dfee325a | 821 | } |
8b230ed8 | 822 | |
078086f3 | 823 | if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status)) |
8b230ed8 | 824 | bna_mbox_handler(&bnad->bna, intr_status); |
be7fa326 | 825 | |
8b230ed8 RM |
826 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
827 | ||
be7fa326 RM |
828 | if (!BNA_IS_INTX_DATA_INTR(intr_status)) |
829 | return IRQ_HANDLED; | |
830 | ||
8b230ed8 | 831 | /* Process data interrupts */ |
be7fa326 RM |
832 | /* Tx processing */ |
833 | for (i = 0; i < bnad->num_tx; i++) { | |
078086f3 RM |
834 | for (j = 0; j < bnad->num_txq_per_tx; j++) { |
835 | tcb = bnad->tx_info[i].tcb[j]; | |
836 | if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) | |
b3cc6e88 | 837 | bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]); |
078086f3 | 838 | } |
be7fa326 RM |
839 | } |
840 | /* Rx processing */ | |
8b230ed8 RM |
841 | for (i = 0; i < bnad->num_rx; i++) { |
842 | rx_info = &bnad->rx_info[i]; | |
843 | if (!rx_info->rx) | |
844 | continue; | |
845 | for (j = 0; j < bnad->num_rxp_per_rx; j++) { | |
846 | rx_ctrl = &rx_info->rx_ctrl[j]; | |
847 | if (rx_ctrl->ccb) | |
848 | bnad_netif_rx_schedule_poll(bnad, | |
849 | rx_ctrl->ccb); | |
850 | } | |
851 | } | |
8b230ed8 RM |
852 | return IRQ_HANDLED; |
853 | } | |
854 | ||
855 | /* | |
856 | * Called in interrupt / callback context | |
857 | * with bna_lock held, so cfg_flags access is OK | |
858 | */ | |
859 | static void | |
860 | bnad_enable_mbox_irq(struct bnad *bnad) | |
861 | { | |
be7fa326 | 862 | clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); |
e2fa6f2e | 863 | |
8b230ed8 RM |
864 | BNAD_UPDATE_CTR(bnad, mbox_intr_enabled); |
865 | } | |
866 | ||
867 | /* | |
868 | * Called with bnad->bna_lock held b'cos of | |
869 | * bnad->cfg_flags access. | |
870 | */ | |
b7ee31c5 | 871 | static void |
8b230ed8 RM |
872 | bnad_disable_mbox_irq(struct bnad *bnad) |
873 | { | |
be7fa326 | 874 | set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); |
8b230ed8 | 875 | |
be7fa326 RM |
876 | BNAD_UPDATE_CTR(bnad, mbox_intr_disabled); |
877 | } | |
8b230ed8 | 878 | |
be7fa326 RM |
879 | static void |
880 | bnad_set_netdev_perm_addr(struct bnad *bnad) | |
881 | { | |
882 | struct net_device *netdev = bnad->netdev; | |
e2fa6f2e | 883 | |
d6b30598 | 884 | ether_addr_copy(netdev->perm_addr, bnad->perm_addr); |
be7fa326 | 885 | if (is_zero_ether_addr(netdev->dev_addr)) |
d6b30598 | 886 | ether_addr_copy(netdev->dev_addr, bnad->perm_addr); |
8b230ed8 RM |
887 | } |
888 | ||
889 | /* Control Path Handlers */ | |
890 | ||
891 | /* Callbacks */ | |
892 | void | |
078086f3 | 893 | bnad_cb_mbox_intr_enable(struct bnad *bnad) |
8b230ed8 RM |
894 | { |
895 | bnad_enable_mbox_irq(bnad); | |
896 | } | |
897 | ||
898 | void | |
078086f3 | 899 | bnad_cb_mbox_intr_disable(struct bnad *bnad) |
8b230ed8 RM |
900 | { |
901 | bnad_disable_mbox_irq(bnad); | |
902 | } | |
903 | ||
904 | void | |
078086f3 RM |
905 | bnad_cb_ioceth_ready(struct bnad *bnad) |
906 | { | |
907 | bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS; | |
908 | complete(&bnad->bnad_completions.ioc_comp); | |
909 | } | |
910 | ||
911 | void | |
912 | bnad_cb_ioceth_failed(struct bnad *bnad) | |
8b230ed8 | 913 | { |
078086f3 | 914 | bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL; |
8b230ed8 | 915 | complete(&bnad->bnad_completions.ioc_comp); |
8b230ed8 RM |
916 | } |
917 | ||
918 | void | |
078086f3 | 919 | bnad_cb_ioceth_disabled(struct bnad *bnad) |
8b230ed8 | 920 | { |
078086f3 | 921 | bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS; |
8b230ed8 | 922 | complete(&bnad->bnad_completions.ioc_comp); |
8b230ed8 RM |
923 | } |
924 | ||
925 | static void | |
078086f3 | 926 | bnad_cb_enet_disabled(void *arg) |
8b230ed8 RM |
927 | { |
928 | struct bnad *bnad = (struct bnad *)arg; | |
929 | ||
8b230ed8 | 930 | netif_carrier_off(bnad->netdev); |
078086f3 | 931 | complete(&bnad->bnad_completions.enet_comp); |
8b230ed8 RM |
932 | } |
933 | ||
934 | void | |
078086f3 | 935 | bnad_cb_ethport_link_status(struct bnad *bnad, |
8b230ed8 RM |
936 | enum bna_link_status link_status) |
937 | { | |
3db1cd5c | 938 | bool link_up = false; |
8b230ed8 RM |
939 | |
940 | link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP); | |
941 | ||
942 | if (link_status == BNA_CEE_UP) { | |
078086f3 RM |
943 | if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) |
944 | BNAD_UPDATE_CTR(bnad, cee_toggle); | |
8b230ed8 | 945 | set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags); |
078086f3 RM |
946 | } else { |
947 | if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) | |
948 | BNAD_UPDATE_CTR(bnad, cee_toggle); | |
8b230ed8 | 949 | clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags); |
078086f3 | 950 | } |
8b230ed8 RM |
951 | |
952 | if (link_up) { | |
953 | if (!netif_carrier_ok(bnad->netdev)) { | |
078086f3 | 954 | uint tx_id, tcb_id; |
ecc46789 | 955 | netdev_info(bnad->netdev, "link up\n"); |
8b230ed8 RM |
956 | netif_carrier_on(bnad->netdev); |
957 | BNAD_UPDATE_CTR(bnad, link_toggle); | |
078086f3 RM |
958 | for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) { |
959 | for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx; | |
960 | tcb_id++) { | |
961 | struct bna_tcb *tcb = | |
962 | bnad->tx_info[tx_id].tcb[tcb_id]; | |
963 | u32 txq_id; | |
964 | if (!tcb) | |
965 | continue; | |
966 | ||
967 | txq_id = tcb->id; | |
968 | ||
969 | if (test_bit(BNAD_TXQ_TX_STARTED, | |
970 | &tcb->flags)) { | |
971 | /* | |
972 | * Force an immediate | |
973 | * Transmit Schedule */ | |
078086f3 RM |
974 | netif_wake_subqueue( |
975 | bnad->netdev, | |
976 | txq_id); | |
977 | BNAD_UPDATE_CTR(bnad, | |
978 | netif_queue_wakeup); | |
979 | } else { | |
980 | netif_stop_subqueue( | |
981 | bnad->netdev, | |
982 | txq_id); | |
983 | BNAD_UPDATE_CTR(bnad, | |
984 | netif_queue_stop); | |
985 | } | |
986 | } | |
8b230ed8 RM |
987 | } |
988 | } | |
989 | } else { | |
990 | if (netif_carrier_ok(bnad->netdev)) { | |
ecc46789 | 991 | netdev_info(bnad->netdev, "link down\n"); |
8b230ed8 RM |
992 | netif_carrier_off(bnad->netdev); |
993 | BNAD_UPDATE_CTR(bnad, link_toggle); | |
994 | } | |
995 | } | |
996 | } | |
997 | ||
998 | static void | |
078086f3 | 999 | bnad_cb_tx_disabled(void *arg, struct bna_tx *tx) |
8b230ed8 RM |
1000 | { |
1001 | struct bnad *bnad = (struct bnad *)arg; | |
1002 | ||
1003 | complete(&bnad->bnad_completions.tx_comp); | |
1004 | } | |
1005 | ||
1006 | static void | |
1007 | bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb) | |
1008 | { | |
1009 | struct bnad_tx_info *tx_info = | |
1010 | (struct bnad_tx_info *)tcb->txq->tx->priv; | |
8b230ed8 | 1011 | |
5216562a | 1012 | tcb->priv = tcb; |
8b230ed8 | 1013 | tx_info->tcb[tcb->id] = tcb; |
8b230ed8 RM |
1014 | } |
1015 | ||
1016 | static void | |
1017 | bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb) | |
1018 | { | |
1019 | struct bnad_tx_info *tx_info = | |
1020 | (struct bnad_tx_info *)tcb->txq->tx->priv; | |
1021 | ||
1022 | tx_info->tcb[tcb->id] = NULL; | |
01b54b14 | 1023 | tcb->priv = NULL; |
8b230ed8 RM |
1024 | } |
1025 | ||
8b230ed8 RM |
1026 | static void |
1027 | bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb) | |
1028 | { | |
1029 | struct bnad_rx_info *rx_info = | |
1030 | (struct bnad_rx_info *)ccb->cq->rx->priv; | |
1031 | ||
1032 | rx_info->rx_ctrl[ccb->id].ccb = ccb; | |
1033 | ccb->ctrl = &rx_info->rx_ctrl[ccb->id]; | |
1034 | } | |
1035 | ||
1036 | static void | |
1037 | bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb) | |
1038 | { | |
1039 | struct bnad_rx_info *rx_info = | |
1040 | (struct bnad_rx_info *)ccb->cq->rx->priv; | |
1041 | ||
1042 | rx_info->rx_ctrl[ccb->id].ccb = NULL; | |
1043 | } | |
1044 | ||
1045 | static void | |
078086f3 | 1046 | bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx) |
8b230ed8 RM |
1047 | { |
1048 | struct bnad_tx_info *tx_info = | |
078086f3 RM |
1049 | (struct bnad_tx_info *)tx->priv; |
1050 | struct bna_tcb *tcb; | |
1051 | u32 txq_id; | |
1052 | int i; | |
8b230ed8 | 1053 | |
078086f3 RM |
1054 | for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { |
1055 | tcb = tx_info->tcb[i]; | |
1056 | if (!tcb) | |
1057 | continue; | |
1058 | txq_id = tcb->id; | |
1059 | clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags); | |
1060 | netif_stop_subqueue(bnad->netdev, txq_id); | |
078086f3 | 1061 | } |
8b230ed8 RM |
1062 | } |
1063 | ||
1064 | static void | |
078086f3 | 1065 | bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx) |
8b230ed8 | 1066 | { |
078086f3 RM |
1067 | struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv; |
1068 | struct bna_tcb *tcb; | |
078086f3 RM |
1069 | u32 txq_id; |
1070 | int i; | |
8b230ed8 | 1071 | |
078086f3 RM |
1072 | for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { |
1073 | tcb = tx_info->tcb[i]; | |
1074 | if (!tcb) | |
1075 | continue; | |
1076 | txq_id = tcb->id; | |
8b230ed8 | 1077 | |
01b54b14 | 1078 | BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)); |
078086f3 | 1079 | set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags); |
01b54b14 | 1080 | BUG_ON(*(tcb->hw_consumer_index) != 0); |
078086f3 RM |
1081 | |
1082 | if (netif_carrier_ok(bnad->netdev)) { | |
078086f3 RM |
1083 | netif_wake_subqueue(bnad->netdev, txq_id); |
1084 | BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); | |
1085 | } | |
1086 | } | |
be7fa326 RM |
1087 | |
1088 | /* | |
078086f3 | 1089 | * Workaround for first ioceth enable failure & we |
be7fa326 RM |
1090 | * get a 0 MAC address. We try to get the MAC address |
1091 | * again here. | |
1092 | */ | |
d6b30598 IV |
1093 | if (is_zero_ether_addr(bnad->perm_addr)) { |
1094 | bna_enet_perm_mac_get(&bnad->bna.enet, bnad->perm_addr); | |
be7fa326 RM |
1095 | bnad_set_netdev_perm_addr(bnad); |
1096 | } | |
be7fa326 RM |
1097 | } |
1098 | ||
01b54b14 JH |
1099 | /* |
1100 | * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm. | |
1101 | */ | |
1102 | static void | |
1103 | bnad_tx_cleanup(struct delayed_work *work) | |
1104 | { | |
1105 | struct bnad_tx_info *tx_info = | |
1106 | container_of(work, struct bnad_tx_info, tx_cleanup_work); | |
1107 | struct bnad *bnad = NULL; | |
01b54b14 JH |
1108 | struct bna_tcb *tcb; |
1109 | unsigned long flags; | |
5216562a | 1110 | u32 i, pending = 0; |
01b54b14 JH |
1111 | |
1112 | for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { | |
1113 | tcb = tx_info->tcb[i]; | |
1114 | if (!tcb) | |
1115 | continue; | |
1116 | ||
1117 | bnad = tcb->bnad; | |
1118 | ||
1119 | if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) { | |
1120 | pending++; | |
1121 | continue; | |
1122 | } | |
1123 | ||
b3cc6e88 | 1124 | bnad_txq_cleanup(bnad, tcb); |
01b54b14 | 1125 | |
4e857c58 | 1126 | smp_mb__before_atomic(); |
01b54b14 JH |
1127 | clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); |
1128 | } | |
1129 | ||
1130 | if (pending) { | |
1131 | queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, | |
1132 | msecs_to_jiffies(1)); | |
1133 | return; | |
1134 | } | |
1135 | ||
1136 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1137 | bna_tx_cleanup_complete(tx_info->tx); | |
1138 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1139 | } | |
1140 | ||
be7fa326 | 1141 | static void |
078086f3 | 1142 | bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx) |
be7fa326 | 1143 | { |
078086f3 RM |
1144 | struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv; |
1145 | struct bna_tcb *tcb; | |
1146 | int i; | |
1147 | ||
1148 | for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { | |
1149 | tcb = tx_info->tcb[i]; | |
1150 | if (!tcb) | |
1151 | continue; | |
1152 | } | |
1153 | ||
01b54b14 | 1154 | queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0); |
8b230ed8 RM |
1155 | } |
1156 | ||
5bcf6ac0 RM |
1157 | static void |
1158 | bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx) | |
1159 | { | |
1160 | struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv; | |
1161 | struct bna_ccb *ccb; | |
1162 | struct bnad_rx_ctrl *rx_ctrl; | |
1163 | int i; | |
1164 | ||
1165 | for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { | |
1166 | rx_ctrl = &rx_info->rx_ctrl[i]; | |
1167 | ccb = rx_ctrl->ccb; | |
1168 | if (!ccb) | |
1169 | continue; | |
1170 | ||
1171 | clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags); | |
1172 | ||
1173 | if (ccb->rcb[1]) | |
1174 | clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags); | |
1175 | } | |
1176 | } | |
1177 | ||
01b54b14 JH |
1178 | /* |
1179 | * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm. | |
1180 | */ | |
1181 | static void | |
1182 | bnad_rx_cleanup(void *work) | |
1183 | { | |
1184 | struct bnad_rx_info *rx_info = | |
1185 | container_of(work, struct bnad_rx_info, rx_cleanup_work); | |
1186 | struct bnad_rx_ctrl *rx_ctrl; | |
1187 | struct bnad *bnad = NULL; | |
1188 | unsigned long flags; | |
5216562a | 1189 | u32 i; |
01b54b14 JH |
1190 | |
1191 | for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { | |
1192 | rx_ctrl = &rx_info->rx_ctrl[i]; | |
1193 | ||
1194 | if (!rx_ctrl->ccb) | |
1195 | continue; | |
1196 | ||
1197 | bnad = rx_ctrl->ccb->bnad; | |
1198 | ||
1199 | /* | |
1200 | * Wait till the poll handler has exited | |
1201 | * and nothing can be scheduled anymore | |
1202 | */ | |
1203 | napi_disable(&rx_ctrl->napi); | |
1204 | ||
b3cc6e88 JH |
1205 | bnad_cq_cleanup(bnad, rx_ctrl->ccb); |
1206 | bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]); | |
01b54b14 | 1207 | if (rx_ctrl->ccb->rcb[1]) |
b3cc6e88 | 1208 | bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]); |
01b54b14 JH |
1209 | } |
1210 | ||
1211 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1212 | bna_rx_cleanup_complete(rx_info->rx); | |
1213 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1214 | } | |
1215 | ||
8b230ed8 | 1216 | static void |
078086f3 | 1217 | bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx) |
8b230ed8 | 1218 | { |
078086f3 RM |
1219 | struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv; |
1220 | struct bna_ccb *ccb; | |
1221 | struct bnad_rx_ctrl *rx_ctrl; | |
1222 | int i; | |
1223 | ||
772b5235 | 1224 | for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { |
078086f3 RM |
1225 | rx_ctrl = &rx_info->rx_ctrl[i]; |
1226 | ccb = rx_ctrl->ccb; | |
1227 | if (!ccb) | |
1228 | continue; | |
1229 | ||
1230 | clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags); | |
1231 | ||
1232 | if (ccb->rcb[1]) | |
1233 | clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags); | |
078086f3 | 1234 | } |
be7fa326 | 1235 | |
01b54b14 | 1236 | queue_work(bnad->work_q, &rx_info->rx_cleanup_work); |
8b230ed8 RM |
1237 | } |
1238 | ||
1239 | static void | |
078086f3 | 1240 | bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx) |
8b230ed8 | 1241 | { |
078086f3 RM |
1242 | struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv; |
1243 | struct bna_ccb *ccb; | |
1244 | struct bna_rcb *rcb; | |
1245 | struct bnad_rx_ctrl *rx_ctrl; | |
30f9fc94 | 1246 | int i, j; |
be7fa326 | 1247 | |
772b5235 | 1248 | for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { |
078086f3 RM |
1249 | rx_ctrl = &rx_info->rx_ctrl[i]; |
1250 | ccb = rx_ctrl->ccb; | |
1251 | if (!ccb) | |
1252 | continue; | |
be7fa326 | 1253 | |
01b54b14 | 1254 | napi_enable(&rx_ctrl->napi); |
8b230ed8 | 1255 | |
078086f3 RM |
1256 | for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) { |
1257 | rcb = ccb->rcb[j]; | |
1258 | if (!rcb) | |
1259 | continue; | |
078086f3 | 1260 | |
30f9fc94 | 1261 | bnad_rxq_alloc_init(bnad, rcb); |
078086f3 | 1262 | set_bit(BNAD_RXQ_STARTED, &rcb->flags); |
5bcf6ac0 | 1263 | set_bit(BNAD_RXQ_POST_OK, &rcb->flags); |
5216562a | 1264 | bnad_rxq_post(bnad, rcb); |
078086f3 | 1265 | } |
8b230ed8 RM |
1266 | } |
1267 | } | |
1268 | ||
1269 | static void | |
078086f3 | 1270 | bnad_cb_rx_disabled(void *arg, struct bna_rx *rx) |
8b230ed8 RM |
1271 | { |
1272 | struct bnad *bnad = (struct bnad *)arg; | |
1273 | ||
1274 | complete(&bnad->bnad_completions.rx_comp); | |
1275 | } | |
1276 | ||
1277 | static void | |
078086f3 | 1278 | bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx) |
8b230ed8 | 1279 | { |
078086f3 | 1280 | bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS; |
8b230ed8 RM |
1281 | complete(&bnad->bnad_completions.mcast_comp); |
1282 | } | |
1283 | ||
1284 | void | |
1285 | bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status, | |
1286 | struct bna_stats *stats) | |
1287 | { | |
1288 | if (status == BNA_CB_SUCCESS) | |
1289 | BNAD_UPDATE_CTR(bnad, hw_stats_updates); | |
1290 | ||
1291 | if (!netif_running(bnad->netdev) || | |
1292 | !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) | |
1293 | return; | |
1294 | ||
1295 | mod_timer(&bnad->stats_timer, | |
1296 | jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ)); | |
1297 | } | |
1298 | ||
078086f3 RM |
1299 | static void |
1300 | bnad_cb_enet_mtu_set(struct bnad *bnad) | |
1301 | { | |
1302 | bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS; | |
1303 | complete(&bnad->bnad_completions.mtu_comp); | |
1304 | } | |
1305 | ||
72a9730b KG |
1306 | void |
1307 | bnad_cb_completion(void *arg, enum bfa_status status) | |
1308 | { | |
1309 | struct bnad_iocmd_comp *iocmd_comp = | |
1310 | (struct bnad_iocmd_comp *)arg; | |
1311 | ||
1312 | iocmd_comp->comp_status = (u32) status; | |
1313 | complete(&iocmd_comp->comp); | |
1314 | } | |
1315 | ||
8b230ed8 RM |
1316 | /* Resource allocation, free functions */ |
1317 | ||
1318 | static void | |
1319 | bnad_mem_free(struct bnad *bnad, | |
1320 | struct bna_mem_info *mem_info) | |
1321 | { | |
1322 | int i; | |
1323 | dma_addr_t dma_pa; | |
1324 | ||
1325 | if (mem_info->mdl == NULL) | |
1326 | return; | |
1327 | ||
1328 | for (i = 0; i < mem_info->num; i++) { | |
1329 | if (mem_info->mdl[i].kva != NULL) { | |
1330 | if (mem_info->mem_type == BNA_MEM_T_DMA) { | |
1331 | BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma), | |
1332 | dma_pa); | |
5ea74318 IV |
1333 | dma_free_coherent(&bnad->pcidev->dev, |
1334 | mem_info->mdl[i].len, | |
1335 | mem_info->mdl[i].kva, dma_pa); | |
8b230ed8 RM |
1336 | } else |
1337 | kfree(mem_info->mdl[i].kva); | |
1338 | } | |
1339 | } | |
1340 | kfree(mem_info->mdl); | |
1341 | mem_info->mdl = NULL; | |
1342 | } | |
1343 | ||
1344 | static int | |
1345 | bnad_mem_alloc(struct bnad *bnad, | |
1346 | struct bna_mem_info *mem_info) | |
1347 | { | |
1348 | int i; | |
1349 | dma_addr_t dma_pa; | |
1350 | ||
1351 | if ((mem_info->num == 0) || (mem_info->len == 0)) { | |
1352 | mem_info->mdl = NULL; | |
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr), | |
1357 | GFP_KERNEL); | |
1358 | if (mem_info->mdl == NULL) | |
1359 | return -ENOMEM; | |
1360 | ||
1361 | if (mem_info->mem_type == BNA_MEM_T_DMA) { | |
1362 | for (i = 0; i < mem_info->num; i++) { | |
1363 | mem_info->mdl[i].len = mem_info->len; | |
1364 | mem_info->mdl[i].kva = | |
5ea74318 | 1365 | dma_alloc_coherent(&bnad->pcidev->dev, |
1f9061d2 JP |
1366 | mem_info->len, &dma_pa, |
1367 | GFP_KERNEL); | |
8b230ed8 RM |
1368 | if (mem_info->mdl[i].kva == NULL) |
1369 | goto err_return; | |
1370 | ||
1371 | BNA_SET_DMA_ADDR(dma_pa, | |
1372 | &(mem_info->mdl[i].dma)); | |
1373 | } | |
1374 | } else { | |
1375 | for (i = 0; i < mem_info->num; i++) { | |
1376 | mem_info->mdl[i].len = mem_info->len; | |
1377 | mem_info->mdl[i].kva = kzalloc(mem_info->len, | |
1378 | GFP_KERNEL); | |
1379 | if (mem_info->mdl[i].kva == NULL) | |
1380 | goto err_return; | |
1381 | } | |
1382 | } | |
1383 | ||
1384 | return 0; | |
1385 | ||
1386 | err_return: | |
1387 | bnad_mem_free(bnad, mem_info); | |
1388 | return -ENOMEM; | |
1389 | } | |
1390 | ||
1391 | /* Free IRQ for Mailbox */ | |
1392 | static void | |
078086f3 | 1393 | bnad_mbox_irq_free(struct bnad *bnad) |
8b230ed8 RM |
1394 | { |
1395 | int irq; | |
1396 | unsigned long flags; | |
1397 | ||
8b230ed8 | 1398 | spin_lock_irqsave(&bnad->bna_lock, flags); |
8b230ed8 | 1399 | bnad_disable_mbox_irq(bnad); |
e2fa6f2e | 1400 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
8b230ed8 RM |
1401 | |
1402 | irq = BNAD_GET_MBOX_IRQ(bnad); | |
be7fa326 | 1403 | free_irq(irq, bnad); |
8b230ed8 RM |
1404 | } |
1405 | ||
1406 | /* | |
1407 | * Allocates IRQ for Mailbox, but keep it disabled | |
1408 | * This will be enabled once we get the mbox enable callback | |
1409 | * from bna | |
1410 | */ | |
1411 | static int | |
078086f3 | 1412 | bnad_mbox_irq_alloc(struct bnad *bnad) |
8b230ed8 | 1413 | { |
0120b99c RM |
1414 | int err = 0; |
1415 | unsigned long irq_flags, flags; | |
8b230ed8 | 1416 | u32 irq; |
0120b99c | 1417 | irq_handler_t irq_handler; |
8b230ed8 | 1418 | |
8b230ed8 RM |
1419 | spin_lock_irqsave(&bnad->bna_lock, flags); |
1420 | if (bnad->cfg_flags & BNAD_CF_MSIX) { | |
1421 | irq_handler = (irq_handler_t)bnad_msix_mbox_handler; | |
8811e267 | 1422 | irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector; |
8279171a | 1423 | irq_flags = 0; |
8b230ed8 RM |
1424 | } else { |
1425 | irq_handler = (irq_handler_t)bnad_isr; | |
1426 | irq = bnad->pcidev->irq; | |
5f77898d | 1427 | irq_flags = IRQF_SHARED; |
8b230ed8 | 1428 | } |
8811e267 | 1429 | |
8b230ed8 | 1430 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
8b230ed8 RM |
1431 | sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME); |
1432 | ||
e2fa6f2e RM |
1433 | /* |
1434 | * Set the Mbox IRQ disable flag, so that the IRQ handler | |
1435 | * called from request_irq() for SHARED IRQs do not execute | |
1436 | */ | |
1437 | set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); | |
1438 | ||
be7fa326 RM |
1439 | BNAD_UPDATE_CTR(bnad, mbox_intr_disabled); |
1440 | ||
8279171a | 1441 | err = request_irq(irq, irq_handler, irq_flags, |
be7fa326 | 1442 | bnad->mbox_irq_name, bnad); |
e2fa6f2e | 1443 | |
be7fa326 | 1444 | return err; |
8b230ed8 RM |
1445 | } |
1446 | ||
1447 | static void | |
1448 | bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info) | |
1449 | { | |
1450 | kfree(intr_info->idl); | |
1451 | intr_info->idl = NULL; | |
1452 | } | |
1453 | ||
1454 | /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */ | |
1455 | static int | |
1456 | bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src, | |
078086f3 | 1457 | u32 txrx_id, struct bna_intr_info *intr_info) |
8b230ed8 RM |
1458 | { |
1459 | int i, vector_start = 0; | |
1460 | u32 cfg_flags; | |
1461 | unsigned long flags; | |
1462 | ||
1463 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1464 | cfg_flags = bnad->cfg_flags; | |
1465 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1466 | ||
1467 | if (cfg_flags & BNAD_CF_MSIX) { | |
1468 | intr_info->intr_type = BNA_INTR_T_MSIX; | |
1469 | intr_info->idl = kcalloc(intr_info->num, | |
1470 | sizeof(struct bna_intr_descr), | |
1471 | GFP_KERNEL); | |
1472 | if (!intr_info->idl) | |
1473 | return -ENOMEM; | |
1474 | ||
1475 | switch (src) { | |
1476 | case BNAD_INTR_TX: | |
8811e267 | 1477 | vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id; |
8b230ed8 RM |
1478 | break; |
1479 | ||
1480 | case BNAD_INTR_RX: | |
8811e267 RM |
1481 | vector_start = BNAD_MAILBOX_MSIX_VECTORS + |
1482 | (bnad->num_tx * bnad->num_txq_per_tx) + | |
8b230ed8 RM |
1483 | txrx_id; |
1484 | break; | |
1485 | ||
1486 | default: | |
1487 | BUG(); | |
1488 | } | |
1489 | ||
1490 | for (i = 0; i < intr_info->num; i++) | |
1491 | intr_info->idl[i].vector = vector_start + i; | |
1492 | } else { | |
1493 | intr_info->intr_type = BNA_INTR_T_INTX; | |
1494 | intr_info->num = 1; | |
1495 | intr_info->idl = kcalloc(intr_info->num, | |
1496 | sizeof(struct bna_intr_descr), | |
1497 | GFP_KERNEL); | |
1498 | if (!intr_info->idl) | |
1499 | return -ENOMEM; | |
1500 | ||
1501 | switch (src) { | |
1502 | case BNAD_INTR_TX: | |
8811e267 | 1503 | intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK; |
8b230ed8 RM |
1504 | break; |
1505 | ||
1506 | case BNAD_INTR_RX: | |
8811e267 | 1507 | intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK; |
8b230ed8 RM |
1508 | break; |
1509 | } | |
1510 | } | |
1511 | return 0; | |
1512 | } | |
1513 | ||
1aa8b471 | 1514 | /* NOTE: Should be called for MSIX only |
8b230ed8 RM |
1515 | * Unregisters Tx MSIX vector(s) from the kernel |
1516 | */ | |
1517 | static void | |
1518 | bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info, | |
1519 | int num_txqs) | |
1520 | { | |
1521 | int i; | |
1522 | int vector_num; | |
1523 | ||
1524 | for (i = 0; i < num_txqs; i++) { | |
1525 | if (tx_info->tcb[i] == NULL) | |
1526 | continue; | |
1527 | ||
1528 | vector_num = tx_info->tcb[i]->intr_vector; | |
1529 | free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]); | |
1530 | } | |
1531 | } | |
1532 | ||
1aa8b471 | 1533 | /* NOTE: Should be called for MSIX only |
8b230ed8 RM |
1534 | * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel |
1535 | */ | |
1536 | static int | |
1537 | bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info, | |
078086f3 | 1538 | u32 tx_id, int num_txqs) |
8b230ed8 RM |
1539 | { |
1540 | int i; | |
1541 | int err; | |
1542 | int vector_num; | |
1543 | ||
1544 | for (i = 0; i < num_txqs; i++) { | |
1545 | vector_num = tx_info->tcb[i]->intr_vector; | |
1546 | sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name, | |
1547 | tx_id + tx_info->tcb[i]->id); | |
1548 | err = request_irq(bnad->msix_table[vector_num].vector, | |
1549 | (irq_handler_t)bnad_msix_tx, 0, | |
1550 | tx_info->tcb[i]->name, | |
1551 | tx_info->tcb[i]); | |
1552 | if (err) | |
1553 | goto err_return; | |
1554 | } | |
1555 | ||
1556 | return 0; | |
1557 | ||
1558 | err_return: | |
1559 | if (i > 0) | |
1560 | bnad_tx_msix_unregister(bnad, tx_info, (i - 1)); | |
1561 | return -1; | |
1562 | } | |
1563 | ||
1aa8b471 | 1564 | /* NOTE: Should be called for MSIX only |
8b230ed8 RM |
1565 | * Unregisters Rx MSIX vector(s) from the kernel |
1566 | */ | |
1567 | static void | |
1568 | bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info, | |
1569 | int num_rxps) | |
1570 | { | |
1571 | int i; | |
1572 | int vector_num; | |
1573 | ||
1574 | for (i = 0; i < num_rxps; i++) { | |
1575 | if (rx_info->rx_ctrl[i].ccb == NULL) | |
1576 | continue; | |
1577 | ||
1578 | vector_num = rx_info->rx_ctrl[i].ccb->intr_vector; | |
1579 | free_irq(bnad->msix_table[vector_num].vector, | |
1580 | rx_info->rx_ctrl[i].ccb); | |
1581 | } | |
1582 | } | |
1583 | ||
1aa8b471 | 1584 | /* NOTE: Should be called for MSIX only |
8b230ed8 RM |
1585 | * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel |
1586 | */ | |
1587 | static int | |
1588 | bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info, | |
078086f3 | 1589 | u32 rx_id, int num_rxps) |
8b230ed8 RM |
1590 | { |
1591 | int i; | |
1592 | int err; | |
1593 | int vector_num; | |
1594 | ||
1595 | for (i = 0; i < num_rxps; i++) { | |
1596 | vector_num = rx_info->rx_ctrl[i].ccb->intr_vector; | |
1597 | sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d", | |
1598 | bnad->netdev->name, | |
1599 | rx_id + rx_info->rx_ctrl[i].ccb->id); | |
1600 | err = request_irq(bnad->msix_table[vector_num].vector, | |
1601 | (irq_handler_t)bnad_msix_rx, 0, | |
1602 | rx_info->rx_ctrl[i].ccb->name, | |
1603 | rx_info->rx_ctrl[i].ccb); | |
1604 | if (err) | |
1605 | goto err_return; | |
1606 | } | |
1607 | ||
1608 | return 0; | |
1609 | ||
1610 | err_return: | |
1611 | if (i > 0) | |
1612 | bnad_rx_msix_unregister(bnad, rx_info, (i - 1)); | |
1613 | return -1; | |
1614 | } | |
1615 | ||
1616 | /* Free Tx object Resources */ | |
1617 | static void | |
1618 | bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info) | |
1619 | { | |
1620 | int i; | |
1621 | ||
1622 | for (i = 0; i < BNA_TX_RES_T_MAX; i++) { | |
1623 | if (res_info[i].res_type == BNA_RES_T_MEM) | |
1624 | bnad_mem_free(bnad, &res_info[i].res_u.mem_info); | |
1625 | else if (res_info[i].res_type == BNA_RES_T_INTR) | |
1626 | bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info); | |
1627 | } | |
1628 | } | |
1629 | ||
1630 | /* Allocates memory and interrupt resources for Tx object */ | |
1631 | static int | |
1632 | bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, | |
078086f3 | 1633 | u32 tx_id) |
8b230ed8 RM |
1634 | { |
1635 | int i, err = 0; | |
1636 | ||
1637 | for (i = 0; i < BNA_TX_RES_T_MAX; i++) { | |
1638 | if (res_info[i].res_type == BNA_RES_T_MEM) | |
1639 | err = bnad_mem_alloc(bnad, | |
1640 | &res_info[i].res_u.mem_info); | |
1641 | else if (res_info[i].res_type == BNA_RES_T_INTR) | |
1642 | err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id, | |
1643 | &res_info[i].res_u.intr_info); | |
1644 | if (err) | |
1645 | goto err_return; | |
1646 | } | |
1647 | return 0; | |
1648 | ||
1649 | err_return: | |
1650 | bnad_tx_res_free(bnad, res_info); | |
1651 | return err; | |
1652 | } | |
1653 | ||
1654 | /* Free Rx object Resources */ | |
1655 | static void | |
1656 | bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info) | |
1657 | { | |
1658 | int i; | |
1659 | ||
1660 | for (i = 0; i < BNA_RX_RES_T_MAX; i++) { | |
1661 | if (res_info[i].res_type == BNA_RES_T_MEM) | |
1662 | bnad_mem_free(bnad, &res_info[i].res_u.mem_info); | |
1663 | else if (res_info[i].res_type == BNA_RES_T_INTR) | |
1664 | bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info); | |
1665 | } | |
1666 | } | |
1667 | ||
1668 | /* Allocates memory and interrupt resources for Rx object */ | |
1669 | static int | |
1670 | bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, | |
1671 | uint rx_id) | |
1672 | { | |
1673 | int i, err = 0; | |
1674 | ||
1675 | /* All memory needs to be allocated before setup_ccbs */ | |
1676 | for (i = 0; i < BNA_RX_RES_T_MAX; i++) { | |
1677 | if (res_info[i].res_type == BNA_RES_T_MEM) | |
1678 | err = bnad_mem_alloc(bnad, | |
1679 | &res_info[i].res_u.mem_info); | |
1680 | else if (res_info[i].res_type == BNA_RES_T_INTR) | |
1681 | err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id, | |
1682 | &res_info[i].res_u.intr_info); | |
1683 | if (err) | |
1684 | goto err_return; | |
1685 | } | |
1686 | return 0; | |
1687 | ||
1688 | err_return: | |
1689 | bnad_rx_res_free(bnad, res_info); | |
1690 | return err; | |
1691 | } | |
1692 | ||
1693 | /* Timer callbacks */ | |
1694 | /* a) IOC timer */ | |
1695 | static void | |
1696 | bnad_ioc_timeout(unsigned long data) | |
1697 | { | |
1698 | struct bnad *bnad = (struct bnad *)data; | |
1699 | unsigned long flags; | |
1700 | ||
1701 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
ad24d6f0 | 1702 | bfa_nw_ioc_timeout(&bnad->bna.ioceth.ioc); |
8b230ed8 RM |
1703 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
1704 | } | |
1705 | ||
1706 | static void | |
1707 | bnad_ioc_hb_check(unsigned long data) | |
1708 | { | |
1709 | struct bnad *bnad = (struct bnad *)data; | |
1710 | unsigned long flags; | |
1711 | ||
1712 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
ad24d6f0 | 1713 | bfa_nw_ioc_hb_check(&bnad->bna.ioceth.ioc); |
8b230ed8 RM |
1714 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
1715 | } | |
1716 | ||
1717 | static void | |
1d32f769 | 1718 | bnad_iocpf_timeout(unsigned long data) |
8b230ed8 RM |
1719 | { |
1720 | struct bnad *bnad = (struct bnad *)data; | |
1721 | unsigned long flags; | |
1722 | ||
1723 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
ad24d6f0 | 1724 | bfa_nw_iocpf_timeout(&bnad->bna.ioceth.ioc); |
1d32f769 RM |
1725 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
1726 | } | |
1727 | ||
1728 | static void | |
1729 | bnad_iocpf_sem_timeout(unsigned long data) | |
1730 | { | |
1731 | struct bnad *bnad = (struct bnad *)data; | |
1732 | unsigned long flags; | |
1733 | ||
1734 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
ad24d6f0 | 1735 | bfa_nw_iocpf_sem_timeout(&bnad->bna.ioceth.ioc); |
8b230ed8 RM |
1736 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
1737 | } | |
1738 | ||
1739 | /* | |
1740 | * All timer routines use bnad->bna_lock to protect against | |
1741 | * the following race, which may occur in case of no locking: | |
0120b99c | 1742 | * Time CPU m CPU n |
8b230ed8 RM |
1743 | * 0 1 = test_bit |
1744 | * 1 clear_bit | |
1745 | * 2 del_timer_sync | |
1746 | * 3 mod_timer | |
1747 | */ | |
1748 | ||
1749 | /* b) Dynamic Interrupt Moderation Timer */ | |
1750 | static void | |
1751 | bnad_dim_timeout(unsigned long data) | |
1752 | { | |
1753 | struct bnad *bnad = (struct bnad *)data; | |
1754 | struct bnad_rx_info *rx_info; | |
1755 | struct bnad_rx_ctrl *rx_ctrl; | |
1756 | int i, j; | |
1757 | unsigned long flags; | |
1758 | ||
1759 | if (!netif_carrier_ok(bnad->netdev)) | |
1760 | return; | |
1761 | ||
1762 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1763 | for (i = 0; i < bnad->num_rx; i++) { | |
1764 | rx_info = &bnad->rx_info[i]; | |
1765 | if (!rx_info->rx) | |
1766 | continue; | |
1767 | for (j = 0; j < bnad->num_rxp_per_rx; j++) { | |
1768 | rx_ctrl = &rx_info->rx_ctrl[j]; | |
1769 | if (!rx_ctrl->ccb) | |
1770 | continue; | |
1771 | bna_rx_dim_update(rx_ctrl->ccb); | |
1772 | } | |
1773 | } | |
1774 | ||
1775 | /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */ | |
1776 | if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) | |
1777 | mod_timer(&bnad->dim_timer, | |
1778 | jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ)); | |
1779 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1780 | } | |
1781 | ||
1782 | /* c) Statistics Timer */ | |
1783 | static void | |
1784 | bnad_stats_timeout(unsigned long data) | |
1785 | { | |
1786 | struct bnad *bnad = (struct bnad *)data; | |
1787 | unsigned long flags; | |
1788 | ||
1789 | if (!netif_running(bnad->netdev) || | |
1790 | !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) | |
1791 | return; | |
1792 | ||
1793 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
078086f3 | 1794 | bna_hw_stats_get(&bnad->bna); |
8b230ed8 RM |
1795 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
1796 | } | |
1797 | ||
1798 | /* | |
1799 | * Set up timer for DIM | |
1800 | * Called with bnad->bna_lock held | |
1801 | */ | |
1802 | void | |
1803 | bnad_dim_timer_start(struct bnad *bnad) | |
1804 | { | |
1805 | if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED && | |
1806 | !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) { | |
1807 | setup_timer(&bnad->dim_timer, bnad_dim_timeout, | |
1808 | (unsigned long)bnad); | |
1809 | set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags); | |
1810 | mod_timer(&bnad->dim_timer, | |
1811 | jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ)); | |
1812 | } | |
1813 | } | |
1814 | ||
1815 | /* | |
1816 | * Set up timer for statistics | |
1817 | * Called with mutex_lock(&bnad->conf_mutex) held | |
1818 | */ | |
1819 | static void | |
1820 | bnad_stats_timer_start(struct bnad *bnad) | |
1821 | { | |
1822 | unsigned long flags; | |
1823 | ||
1824 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1825 | if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) { | |
1826 | setup_timer(&bnad->stats_timer, bnad_stats_timeout, | |
1827 | (unsigned long)bnad); | |
1828 | mod_timer(&bnad->stats_timer, | |
1829 | jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ)); | |
1830 | } | |
1831 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
8b230ed8 RM |
1832 | } |
1833 | ||
1834 | /* | |
1835 | * Stops the stats timer | |
1836 | * Called with mutex_lock(&bnad->conf_mutex) held | |
1837 | */ | |
1838 | static void | |
1839 | bnad_stats_timer_stop(struct bnad *bnad) | |
1840 | { | |
1841 | int to_del = 0; | |
1842 | unsigned long flags; | |
1843 | ||
1844 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1845 | if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) | |
1846 | to_del = 1; | |
1847 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1848 | if (to_del) | |
1849 | del_timer_sync(&bnad->stats_timer); | |
1850 | } | |
1851 | ||
1852 | /* Utilities */ | |
1853 | ||
1854 | static void | |
1855 | bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list) | |
1856 | { | |
1857 | int i = 1; /* Index 0 has broadcast address */ | |
1858 | struct netdev_hw_addr *mc_addr; | |
1859 | ||
1860 | netdev_for_each_mc_addr(mc_addr, netdev) { | |
e2f9ecfc | 1861 | ether_addr_copy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0]); |
8b230ed8 RM |
1862 | i++; |
1863 | } | |
1864 | } | |
1865 | ||
1866 | static int | |
1867 | bnad_napi_poll_rx(struct napi_struct *napi, int budget) | |
1868 | { | |
1869 | struct bnad_rx_ctrl *rx_ctrl = | |
1870 | container_of(napi, struct bnad_rx_ctrl, napi); | |
2be67144 | 1871 | struct bnad *bnad = rx_ctrl->bnad; |
8b230ed8 RM |
1872 | int rcvd = 0; |
1873 | ||
271e8b79 | 1874 | rx_ctrl->rx_poll_ctr++; |
8b230ed8 RM |
1875 | |
1876 | if (!netif_carrier_ok(bnad->netdev)) | |
1877 | goto poll_exit; | |
1878 | ||
b3cc6e88 | 1879 | rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget); |
271e8b79 | 1880 | if (rcvd >= budget) |
8b230ed8 RM |
1881 | return rcvd; |
1882 | ||
1883 | poll_exit: | |
19dbff9f | 1884 | napi_complete(napi); |
8b230ed8 | 1885 | |
271e8b79 | 1886 | rx_ctrl->rx_complete++; |
2be67144 RM |
1887 | |
1888 | if (rx_ctrl->ccb) | |
271e8b79 RM |
1889 | bnad_enable_rx_irq_unsafe(rx_ctrl->ccb); |
1890 | ||
8b230ed8 RM |
1891 | return rcvd; |
1892 | } | |
1893 | ||
2be67144 | 1894 | #define BNAD_NAPI_POLL_QUOTA 64 |
8b230ed8 | 1895 | static void |
01b54b14 | 1896 | bnad_napi_add(struct bnad *bnad, u32 rx_id) |
8b230ed8 | 1897 | { |
8b230ed8 RM |
1898 | struct bnad_rx_ctrl *rx_ctrl; |
1899 | int i; | |
8b230ed8 RM |
1900 | |
1901 | /* Initialize & enable NAPI */ | |
1902 | for (i = 0; i < bnad->num_rxp_per_rx; i++) { | |
1903 | rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i]; | |
1904 | netif_napi_add(bnad->netdev, &rx_ctrl->napi, | |
2be67144 RM |
1905 | bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA); |
1906 | } | |
1907 | } | |
1908 | ||
1909 | static void | |
01b54b14 | 1910 | bnad_napi_delete(struct bnad *bnad, u32 rx_id) |
8b230ed8 RM |
1911 | { |
1912 | int i; | |
1913 | ||
1914 | /* First disable and then clean up */ | |
01b54b14 | 1915 | for (i = 0; i < bnad->num_rxp_per_rx; i++) |
8b230ed8 | 1916 | netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi); |
8b230ed8 RM |
1917 | } |
1918 | ||
1919 | /* Should be held with conf_lock held */ | |
1920 | void | |
b3cc6e88 | 1921 | bnad_destroy_tx(struct bnad *bnad, u32 tx_id) |
8b230ed8 RM |
1922 | { |
1923 | struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id]; | |
1924 | struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0]; | |
1925 | unsigned long flags; | |
1926 | ||
1927 | if (!tx_info->tx) | |
1928 | return; | |
1929 | ||
1930 | init_completion(&bnad->bnad_completions.tx_comp); | |
1931 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1932 | bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled); | |
1933 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1934 | wait_for_completion(&bnad->bnad_completions.tx_comp); | |
1935 | ||
1936 | if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX) | |
1937 | bnad_tx_msix_unregister(bnad, tx_info, | |
1938 | bnad->num_txq_per_tx); | |
1939 | ||
1940 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1941 | bna_tx_destroy(tx_info->tx); | |
1942 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1943 | ||
1944 | tx_info->tx = NULL; | |
078086f3 | 1945 | tx_info->tx_id = 0; |
8b230ed8 | 1946 | |
8b230ed8 RM |
1947 | bnad_tx_res_free(bnad, res_info); |
1948 | } | |
1949 | ||
1950 | /* Should be held with conf_lock held */ | |
1951 | int | |
078086f3 | 1952 | bnad_setup_tx(struct bnad *bnad, u32 tx_id) |
8b230ed8 RM |
1953 | { |
1954 | int err; | |
1955 | struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id]; | |
1956 | struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0]; | |
1957 | struct bna_intr_info *intr_info = | |
1958 | &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info; | |
1959 | struct bna_tx_config *tx_config = &bnad->tx_config[tx_id]; | |
d91d25d5 | 1960 | static const struct bna_tx_event_cbfn tx_cbfn = { |
1961 | .tcb_setup_cbfn = bnad_cb_tcb_setup, | |
1962 | .tcb_destroy_cbfn = bnad_cb_tcb_destroy, | |
1963 | .tx_stall_cbfn = bnad_cb_tx_stall, | |
1964 | .tx_resume_cbfn = bnad_cb_tx_resume, | |
1965 | .tx_cleanup_cbfn = bnad_cb_tx_cleanup, | |
1966 | }; | |
1967 | ||
8b230ed8 RM |
1968 | struct bna_tx *tx; |
1969 | unsigned long flags; | |
1970 | ||
078086f3 RM |
1971 | tx_info->tx_id = tx_id; |
1972 | ||
8b230ed8 RM |
1973 | /* Initialize the Tx object configuration */ |
1974 | tx_config->num_txq = bnad->num_txq_per_tx; | |
1975 | tx_config->txq_depth = bnad->txq_depth; | |
1976 | tx_config->tx_type = BNA_TX_T_REGULAR; | |
078086f3 | 1977 | tx_config->coalescing_timeo = bnad->tx_coalescing_timeo; |
8b230ed8 | 1978 | |
8b230ed8 RM |
1979 | /* Get BNA's resource requirement for one tx object */ |
1980 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1981 | bna_tx_res_req(bnad->num_txq_per_tx, | |
1982 | bnad->txq_depth, res_info); | |
1983 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1984 | ||
1985 | /* Fill Unmap Q memory requirements */ | |
5216562a RM |
1986 | BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_TX_RES_MEM_T_UNMAPQ], |
1987 | bnad->num_txq_per_tx, (sizeof(struct bnad_tx_unmap) * | |
1988 | bnad->txq_depth)); | |
8b230ed8 RM |
1989 | |
1990 | /* Allocate resources */ | |
1991 | err = bnad_tx_res_alloc(bnad, res_info, tx_id); | |
1992 | if (err) | |
1993 | return err; | |
1994 | ||
1995 | /* Ask BNA to create one Tx object, supplying required resources */ | |
1996 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1997 | tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info, | |
1998 | tx_info); | |
1999 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
f29eeb79 RM |
2000 | if (!tx) { |
2001 | err = -ENOMEM; | |
8b230ed8 | 2002 | goto err_return; |
f29eeb79 | 2003 | } |
8b230ed8 RM |
2004 | tx_info->tx = tx; |
2005 | ||
01b54b14 JH |
2006 | INIT_DELAYED_WORK(&tx_info->tx_cleanup_work, |
2007 | (work_func_t)bnad_tx_cleanup); | |
2008 | ||
8b230ed8 RM |
2009 | /* Register ISR for the Tx object */ |
2010 | if (intr_info->intr_type == BNA_INTR_T_MSIX) { | |
2011 | err = bnad_tx_msix_register(bnad, tx_info, | |
2012 | tx_id, bnad->num_txq_per_tx); | |
2013 | if (err) | |
f29eeb79 | 2014 | goto cleanup_tx; |
8b230ed8 RM |
2015 | } |
2016 | ||
2017 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2018 | bna_tx_enable(tx); | |
2019 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2020 | ||
2021 | return 0; | |
2022 | ||
f29eeb79 RM |
2023 | cleanup_tx: |
2024 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2025 | bna_tx_destroy(tx_info->tx); | |
2026 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2027 | tx_info->tx = NULL; | |
2028 | tx_info->tx_id = 0; | |
8b230ed8 RM |
2029 | err_return: |
2030 | bnad_tx_res_free(bnad, res_info); | |
2031 | return err; | |
2032 | } | |
2033 | ||
2034 | /* Setup the rx config for bna_rx_create */ | |
2035 | /* bnad decides the configuration */ | |
2036 | static void | |
2037 | bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config) | |
2038 | { | |
e29aa339 | 2039 | memset(rx_config, 0, sizeof(*rx_config)); |
8b230ed8 RM |
2040 | rx_config->rx_type = BNA_RX_T_REGULAR; |
2041 | rx_config->num_paths = bnad->num_rxp_per_rx; | |
078086f3 | 2042 | rx_config->coalescing_timeo = bnad->rx_coalescing_timeo; |
8b230ed8 RM |
2043 | |
2044 | if (bnad->num_rxp_per_rx > 1) { | |
2045 | rx_config->rss_status = BNA_STATUS_T_ENABLED; | |
2046 | rx_config->rss_config.hash_type = | |
078086f3 RM |
2047 | (BFI_ENET_RSS_IPV6 | |
2048 | BFI_ENET_RSS_IPV6_TCP | | |
2049 | BFI_ENET_RSS_IPV4 | | |
2050 | BFI_ENET_RSS_IPV4_TCP); | |
8b230ed8 RM |
2051 | rx_config->rss_config.hash_mask = |
2052 | bnad->num_rxp_per_rx - 1; | |
0fa6aa4a | 2053 | netdev_rss_key_fill(rx_config->rss_config.toeplitz_hash_key, |
8b230ed8 RM |
2054 | sizeof(rx_config->rss_config.toeplitz_hash_key)); |
2055 | } else { | |
2056 | rx_config->rss_status = BNA_STATUS_T_DISABLED; | |
2057 | memset(&rx_config->rss_config, 0, | |
2058 | sizeof(rx_config->rss_config)); | |
2059 | } | |
e29aa339 RM |
2060 | |
2061 | rx_config->frame_size = BNAD_FRAME_SIZE(bnad->netdev->mtu); | |
2062 | rx_config->q0_multi_buf = BNA_STATUS_T_DISABLED; | |
2063 | ||
2064 | /* BNA_RXP_SINGLE - one data-buffer queue | |
2065 | * BNA_RXP_SLR - one small-buffer and one large-buffer queues | |
2066 | * BNA_RXP_HDS - one header-buffer and one data-buffer queues | |
2067 | */ | |
2068 | /* TODO: configurable param for queue type */ | |
8b230ed8 | 2069 | rx_config->rxp_type = BNA_RXP_SLR; |
8b230ed8 | 2070 | |
e29aa339 RM |
2071 | if (BNAD_PCI_DEV_IS_CAT2(bnad) && |
2072 | rx_config->frame_size > 4096) { | |
2073 | /* though size_routing_enable is set in SLR, | |
2074 | * small packets may get routed to same rxq. | |
2075 | * set buf_size to 2048 instead of PAGE_SIZE. | |
2076 | */ | |
2077 | rx_config->q0_buf_size = 2048; | |
2078 | /* this should be in multiples of 2 */ | |
2079 | rx_config->q0_num_vecs = 4; | |
2080 | rx_config->q0_depth = bnad->rxq_depth * rx_config->q0_num_vecs; | |
2081 | rx_config->q0_multi_buf = BNA_STATUS_T_ENABLED; | |
2082 | } else { | |
2083 | rx_config->q0_buf_size = rx_config->frame_size; | |
2084 | rx_config->q0_num_vecs = 1; | |
2085 | rx_config->q0_depth = bnad->rxq_depth; | |
2086 | } | |
2087 | ||
2088 | /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */ | |
2089 | if (rx_config->rxp_type == BNA_RXP_SLR) { | |
2090 | rx_config->q1_depth = bnad->rxq_depth; | |
2091 | rx_config->q1_buf_size = BFI_SMALL_RXBUF_SIZE; | |
2092 | } | |
8b230ed8 | 2093 | |
877767dc IV |
2094 | rx_config->vlan_strip_status = |
2095 | (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) ? | |
2096 | BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED; | |
8b230ed8 RM |
2097 | } |
2098 | ||
2be67144 RM |
2099 | static void |
2100 | bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id) | |
2101 | { | |
2102 | struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; | |
2103 | int i; | |
2104 | ||
2105 | for (i = 0; i < bnad->num_rxp_per_rx; i++) | |
2106 | rx_info->rx_ctrl[i].bnad = bnad; | |
2107 | } | |
2108 | ||
8b230ed8 | 2109 | /* Called with mutex_lock(&bnad->conf_mutex) held */ |
2fd888a5 | 2110 | static u32 |
e29aa339 RM |
2111 | bnad_reinit_rx(struct bnad *bnad) |
2112 | { | |
2113 | struct net_device *netdev = bnad->netdev; | |
2114 | u32 err = 0, current_err = 0; | |
2115 | u32 rx_id = 0, count = 0; | |
2116 | unsigned long flags; | |
2117 | ||
2118 | /* destroy and create new rx objects */ | |
2119 | for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) { | |
2120 | if (!bnad->rx_info[rx_id].rx) | |
2121 | continue; | |
2122 | bnad_destroy_rx(bnad, rx_id); | |
2123 | } | |
2124 | ||
2125 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2126 | bna_enet_mtu_set(&bnad->bna.enet, | |
2127 | BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL); | |
2128 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2129 | ||
2130 | for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) { | |
2131 | count++; | |
2132 | current_err = bnad_setup_rx(bnad, rx_id); | |
2133 | if (current_err && !err) { | |
2134 | err = current_err; | |
ecc46789 | 2135 | netdev_err(netdev, "RXQ:%u setup failed\n", rx_id); |
e29aa339 RM |
2136 | } |
2137 | } | |
2138 | ||
2139 | /* restore rx configuration */ | |
2140 | if (bnad->rx_info[0].rx && !err) { | |
2141 | bnad_restore_vlans(bnad, 0); | |
2142 | bnad_enable_default_bcast(bnad); | |
2143 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2144 | bnad_mac_addr_set_locked(bnad, netdev->dev_addr); | |
2145 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2146 | bnad_set_rx_mode(netdev); | |
2147 | } | |
2148 | ||
2149 | return count; | |
2150 | } | |
2151 | ||
2152 | /* Called with bnad_conf_lock() held */ | |
8b230ed8 | 2153 | void |
b3cc6e88 | 2154 | bnad_destroy_rx(struct bnad *bnad, u32 rx_id) |
8b230ed8 RM |
2155 | { |
2156 | struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; | |
2157 | struct bna_rx_config *rx_config = &bnad->rx_config[rx_id]; | |
2158 | struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0]; | |
2159 | unsigned long flags; | |
271e8b79 | 2160 | int to_del = 0; |
8b230ed8 RM |
2161 | |
2162 | if (!rx_info->rx) | |
2163 | return; | |
2164 | ||
2165 | if (0 == rx_id) { | |
2166 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
271e8b79 RM |
2167 | if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED && |
2168 | test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) { | |
8b230ed8 | 2169 | clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags); |
271e8b79 RM |
2170 | to_del = 1; |
2171 | } | |
8b230ed8 | 2172 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
271e8b79 | 2173 | if (to_del) |
8b230ed8 RM |
2174 | del_timer_sync(&bnad->dim_timer); |
2175 | } | |
2176 | ||
8b230ed8 RM |
2177 | init_completion(&bnad->bnad_completions.rx_comp); |
2178 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2179 | bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled); | |
2180 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2181 | wait_for_completion(&bnad->bnad_completions.rx_comp); | |
2182 | ||
2183 | if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX) | |
2184 | bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths); | |
2185 | ||
01b54b14 | 2186 | bnad_napi_delete(bnad, rx_id); |
2be67144 | 2187 | |
8b230ed8 RM |
2188 | spin_lock_irqsave(&bnad->bna_lock, flags); |
2189 | bna_rx_destroy(rx_info->rx); | |
8b230ed8 RM |
2190 | |
2191 | rx_info->rx = NULL; | |
3caa1e95 | 2192 | rx_info->rx_id = 0; |
b9fa1fbf | 2193 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
8b230ed8 RM |
2194 | |
2195 | bnad_rx_res_free(bnad, res_info); | |
2196 | } | |
2197 | ||
2198 | /* Called with mutex_lock(&bnad->conf_mutex) held */ | |
2199 | int | |
078086f3 | 2200 | bnad_setup_rx(struct bnad *bnad, u32 rx_id) |
8b230ed8 RM |
2201 | { |
2202 | int err; | |
2203 | struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; | |
2204 | struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0]; | |
2205 | struct bna_intr_info *intr_info = | |
2206 | &res_info[BNA_RX_RES_T_INTR].res_u.intr_info; | |
2207 | struct bna_rx_config *rx_config = &bnad->rx_config[rx_id]; | |
d91d25d5 | 2208 | static const struct bna_rx_event_cbfn rx_cbfn = { |
5216562a | 2209 | .rcb_setup_cbfn = NULL, |
01b54b14 | 2210 | .rcb_destroy_cbfn = NULL, |
d91d25d5 | 2211 | .ccb_setup_cbfn = bnad_cb_ccb_setup, |
2212 | .ccb_destroy_cbfn = bnad_cb_ccb_destroy, | |
5bcf6ac0 | 2213 | .rx_stall_cbfn = bnad_cb_rx_stall, |
d91d25d5 | 2214 | .rx_cleanup_cbfn = bnad_cb_rx_cleanup, |
2215 | .rx_post_cbfn = bnad_cb_rx_post, | |
2216 | }; | |
8b230ed8 RM |
2217 | struct bna_rx *rx; |
2218 | unsigned long flags; | |
2219 | ||
078086f3 RM |
2220 | rx_info->rx_id = rx_id; |
2221 | ||
8b230ed8 RM |
2222 | /* Initialize the Rx object configuration */ |
2223 | bnad_init_rx_config(bnad, rx_config); | |
2224 | ||
8b230ed8 RM |
2225 | /* Get BNA's resource requirement for one Rx object */ |
2226 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2227 | bna_rx_res_req(rx_config, res_info); | |
2228 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2229 | ||
2230 | /* Fill Unmap Q memory requirements */ | |
e29aa339 RM |
2231 | BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPDQ], |
2232 | rx_config->num_paths, | |
2233 | (rx_config->q0_depth * | |
2234 | sizeof(struct bnad_rx_unmap)) + | |
2235 | sizeof(struct bnad_rx_unmap_q)); | |
2236 | ||
2237 | if (rx_config->rxp_type != BNA_RXP_SINGLE) { | |
2238 | BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPHQ], | |
2239 | rx_config->num_paths, | |
2240 | (rx_config->q1_depth * | |
2241 | sizeof(struct bnad_rx_unmap) + | |
2242 | sizeof(struct bnad_rx_unmap_q))); | |
2243 | } | |
8b230ed8 RM |
2244 | /* Allocate resource */ |
2245 | err = bnad_rx_res_alloc(bnad, res_info, rx_id); | |
2246 | if (err) | |
2247 | return err; | |
2248 | ||
2be67144 RM |
2249 | bnad_rx_ctrl_init(bnad, rx_id); |
2250 | ||
8b230ed8 RM |
2251 | /* Ask BNA to create one Rx object, supplying required resources */ |
2252 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2253 | rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info, | |
2254 | rx_info); | |
3caa1e95 RM |
2255 | if (!rx) { |
2256 | err = -ENOMEM; | |
b9fa1fbf | 2257 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
8b230ed8 | 2258 | goto err_return; |
3caa1e95 | 2259 | } |
8b230ed8 | 2260 | rx_info->rx = rx; |
b9fa1fbf | 2261 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
8b230ed8 | 2262 | |
01b54b14 JH |
2263 | INIT_WORK(&rx_info->rx_cleanup_work, |
2264 | (work_func_t)(bnad_rx_cleanup)); | |
2265 | ||
2be67144 RM |
2266 | /* |
2267 | * Init NAPI, so that state is set to NAPI_STATE_SCHED, | |
2268 | * so that IRQ handler cannot schedule NAPI at this point. | |
2269 | */ | |
01b54b14 | 2270 | bnad_napi_add(bnad, rx_id); |
2be67144 | 2271 | |
8b230ed8 RM |
2272 | /* Register ISR for the Rx object */ |
2273 | if (intr_info->intr_type == BNA_INTR_T_MSIX) { | |
2274 | err = bnad_rx_msix_register(bnad, rx_info, rx_id, | |
2275 | rx_config->num_paths); | |
2276 | if (err) | |
2277 | goto err_return; | |
2278 | } | |
2279 | ||
8b230ed8 RM |
2280 | spin_lock_irqsave(&bnad->bna_lock, flags); |
2281 | if (0 == rx_id) { | |
2282 | /* Set up Dynamic Interrupt Moderation Vector */ | |
2283 | if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED) | |
2284 | bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector); | |
2285 | ||
2286 | /* Enable VLAN filtering only on the default Rx */ | |
2287 | bna_rx_vlanfilter_enable(rx); | |
2288 | ||
2289 | /* Start the DIM timer */ | |
2290 | bnad_dim_timer_start(bnad); | |
2291 | } | |
2292 | ||
2293 | bna_rx_enable(rx); | |
2294 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2295 | ||
2296 | return 0; | |
2297 | ||
2298 | err_return: | |
b3cc6e88 | 2299 | bnad_destroy_rx(bnad, rx_id); |
8b230ed8 RM |
2300 | return err; |
2301 | } | |
2302 | ||
2303 | /* Called with conf_lock & bnad->bna_lock held */ | |
2304 | void | |
2305 | bnad_tx_coalescing_timeo_set(struct bnad *bnad) | |
2306 | { | |
2307 | struct bnad_tx_info *tx_info; | |
2308 | ||
2309 | tx_info = &bnad->tx_info[0]; | |
2310 | if (!tx_info->tx) | |
2311 | return; | |
2312 | ||
2313 | bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo); | |
2314 | } | |
2315 | ||
2316 | /* Called with conf_lock & bnad->bna_lock held */ | |
2317 | void | |
2318 | bnad_rx_coalescing_timeo_set(struct bnad *bnad) | |
2319 | { | |
2320 | struct bnad_rx_info *rx_info; | |
0120b99c | 2321 | int i; |
8b230ed8 RM |
2322 | |
2323 | for (i = 0; i < bnad->num_rx; i++) { | |
2324 | rx_info = &bnad->rx_info[i]; | |
2325 | if (!rx_info->rx) | |
2326 | continue; | |
2327 | bna_rx_coalescing_timeo_set(rx_info->rx, | |
2328 | bnad->rx_coalescing_timeo); | |
2329 | } | |
2330 | } | |
2331 | ||
2332 | /* | |
2333 | * Called with bnad->bna_lock held | |
2334 | */ | |
a2122d95 | 2335 | int |
558caad7 | 2336 | bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr) |
8b230ed8 RM |
2337 | { |
2338 | int ret; | |
2339 | ||
2340 | if (!is_valid_ether_addr(mac_addr)) | |
2341 | return -EADDRNOTAVAIL; | |
2342 | ||
2343 | /* If datapath is down, pretend everything went through */ | |
2344 | if (!bnad->rx_info[0].rx) | |
2345 | return 0; | |
2346 | ||
1f9883e0 | 2347 | ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr); |
8b230ed8 RM |
2348 | if (ret != BNA_CB_SUCCESS) |
2349 | return -EADDRNOTAVAIL; | |
2350 | ||
2351 | return 0; | |
2352 | } | |
2353 | ||
2354 | /* Should be called with conf_lock held */ | |
a2122d95 | 2355 | int |
8b230ed8 RM |
2356 | bnad_enable_default_bcast(struct bnad *bnad) |
2357 | { | |
2358 | struct bnad_rx_info *rx_info = &bnad->rx_info[0]; | |
2359 | int ret; | |
2360 | unsigned long flags; | |
2361 | ||
2362 | init_completion(&bnad->bnad_completions.mcast_comp); | |
2363 | ||
2364 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
558caad7 IV |
2365 | ret = bna_rx_mcast_add(rx_info->rx, bnad_bcast_addr, |
2366 | bnad_cb_rx_mcast_add); | |
8b230ed8 RM |
2367 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
2368 | ||
2369 | if (ret == BNA_CB_SUCCESS) | |
2370 | wait_for_completion(&bnad->bnad_completions.mcast_comp); | |
2371 | else | |
2372 | return -ENODEV; | |
2373 | ||
2374 | if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS) | |
2375 | return -ENODEV; | |
2376 | ||
2377 | return 0; | |
2378 | } | |
2379 | ||
19dbff9f | 2380 | /* Called with mutex_lock(&bnad->conf_mutex) held */ |
a2122d95 | 2381 | void |
aad75b66 RM |
2382 | bnad_restore_vlans(struct bnad *bnad, u32 rx_id) |
2383 | { | |
f859d7cb | 2384 | u16 vid; |
aad75b66 RM |
2385 | unsigned long flags; |
2386 | ||
f859d7cb | 2387 | for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) { |
aad75b66 | 2388 | spin_lock_irqsave(&bnad->bna_lock, flags); |
f859d7cb | 2389 | bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid); |
aad75b66 RM |
2390 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
2391 | } | |
2392 | } | |
2393 | ||
8b230ed8 RM |
2394 | /* Statistics utilities */ |
2395 | void | |
250e061e | 2396 | bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats) |
8b230ed8 | 2397 | { |
8b230ed8 RM |
2398 | int i, j; |
2399 | ||
2400 | for (i = 0; i < bnad->num_rx; i++) { | |
2401 | for (j = 0; j < bnad->num_rxp_per_rx; j++) { | |
2402 | if (bnad->rx_info[i].rx_ctrl[j].ccb) { | |
250e061e | 2403 | stats->rx_packets += bnad->rx_info[i]. |
8b230ed8 | 2404 | rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets; |
250e061e | 2405 | stats->rx_bytes += bnad->rx_info[i]. |
8b230ed8 RM |
2406 | rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes; |
2407 | if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] && | |
2408 | bnad->rx_info[i].rx_ctrl[j].ccb-> | |
2409 | rcb[1]->rxq) { | |
250e061e | 2410 | stats->rx_packets += |
8b230ed8 RM |
2411 | bnad->rx_info[i].rx_ctrl[j]. |
2412 | ccb->rcb[1]->rxq->rx_packets; | |
250e061e | 2413 | stats->rx_bytes += |
8b230ed8 RM |
2414 | bnad->rx_info[i].rx_ctrl[j]. |
2415 | ccb->rcb[1]->rxq->rx_bytes; | |
2416 | } | |
2417 | } | |
2418 | } | |
2419 | } | |
2420 | for (i = 0; i < bnad->num_tx; i++) { | |
2421 | for (j = 0; j < bnad->num_txq_per_tx; j++) { | |
2422 | if (bnad->tx_info[i].tcb[j]) { | |
250e061e | 2423 | stats->tx_packets += |
8b230ed8 | 2424 | bnad->tx_info[i].tcb[j]->txq->tx_packets; |
250e061e | 2425 | stats->tx_bytes += |
8b230ed8 RM |
2426 | bnad->tx_info[i].tcb[j]->txq->tx_bytes; |
2427 | } | |
2428 | } | |
2429 | } | |
2430 | } | |
2431 | ||
2432 | /* | |
2433 | * Must be called with the bna_lock held. | |
2434 | */ | |
2435 | void | |
250e061e | 2436 | bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats) |
8b230ed8 | 2437 | { |
078086f3 RM |
2438 | struct bfi_enet_stats_mac *mac_stats; |
2439 | u32 bmap; | |
8b230ed8 RM |
2440 | int i; |
2441 | ||
078086f3 | 2442 | mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats; |
250e061e | 2443 | stats->rx_errors = |
8b230ed8 RM |
2444 | mac_stats->rx_fcs_error + mac_stats->rx_alignment_error + |
2445 | mac_stats->rx_frame_length_error + mac_stats->rx_code_error + | |
2446 | mac_stats->rx_undersize; | |
250e061e | 2447 | stats->tx_errors = mac_stats->tx_fcs_error + |
8b230ed8 | 2448 | mac_stats->tx_undersize; |
250e061e ED |
2449 | stats->rx_dropped = mac_stats->rx_drop; |
2450 | stats->tx_dropped = mac_stats->tx_drop; | |
2451 | stats->multicast = mac_stats->rx_multicast; | |
2452 | stats->collisions = mac_stats->tx_total_collision; | |
8b230ed8 | 2453 | |
250e061e | 2454 | stats->rx_length_errors = mac_stats->rx_frame_length_error; |
8b230ed8 RM |
2455 | |
2456 | /* receive ring buffer overflow ?? */ | |
2457 | ||
250e061e ED |
2458 | stats->rx_crc_errors = mac_stats->rx_fcs_error; |
2459 | stats->rx_frame_errors = mac_stats->rx_alignment_error; | |
8b230ed8 | 2460 | /* recv'r fifo overrun */ |
078086f3 RM |
2461 | bmap = bna_rx_rid_mask(&bnad->bna); |
2462 | for (i = 0; bmap; i++) { | |
8b230ed8 | 2463 | if (bmap & 1) { |
250e061e | 2464 | stats->rx_fifo_errors += |
8b230ed8 | 2465 | bnad->stats.bna_stats-> |
078086f3 | 2466 | hw_stats.rxf_stats[i].frame_drops; |
8b230ed8 RM |
2467 | break; |
2468 | } | |
2469 | bmap >>= 1; | |
2470 | } | |
2471 | } | |
2472 | ||
2473 | static void | |
2474 | bnad_mbox_irq_sync(struct bnad *bnad) | |
2475 | { | |
2476 | u32 irq; | |
2477 | unsigned long flags; | |
2478 | ||
2479 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2480 | if (bnad->cfg_flags & BNAD_CF_MSIX) | |
8811e267 | 2481 | irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector; |
8b230ed8 RM |
2482 | else |
2483 | irq = bnad->pcidev->irq; | |
2484 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2485 | ||
2486 | synchronize_irq(irq); | |
2487 | } | |
2488 | ||
2489 | /* Utility used by bnad_start_xmit, for doing TSO */ | |
2490 | static int | |
2491 | bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb) | |
2492 | { | |
2493 | int err; | |
2494 | ||
b13a8a99 | 2495 | err = skb_cow_head(skb, 0); |
2496 | if (err < 0) { | |
2497 | BNAD_UPDATE_CTR(bnad, tso_err); | |
2498 | return err; | |
8b230ed8 RM |
2499 | } |
2500 | ||
2501 | /* | |
2502 | * For TSO, the TCP checksum field is seeded with pseudo-header sum | |
2503 | * excluding the length field. | |
2504 | */ | |
1c53730a | 2505 | if (vlan_get_protocol(skb) == htons(ETH_P_IP)) { |
8b230ed8 RM |
2506 | struct iphdr *iph = ip_hdr(skb); |
2507 | ||
2508 | /* Do we really need these? */ | |
2509 | iph->tot_len = 0; | |
2510 | iph->check = 0; | |
2511 | ||
2512 | tcp_hdr(skb)->check = | |
2513 | ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, | |
2514 | IPPROTO_TCP, 0); | |
2515 | BNAD_UPDATE_CTR(bnad, tso4); | |
2516 | } else { | |
2517 | struct ipv6hdr *ipv6h = ipv6_hdr(skb); | |
2518 | ||
8b230ed8 RM |
2519 | ipv6h->payload_len = 0; |
2520 | tcp_hdr(skb)->check = | |
2521 | ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0, | |
2522 | IPPROTO_TCP, 0); | |
2523 | BNAD_UPDATE_CTR(bnad, tso6); | |
2524 | } | |
2525 | ||
2526 | return 0; | |
2527 | } | |
2528 | ||
2529 | /* | |
2530 | * Initialize Q numbers depending on Rx Paths | |
2531 | * Called with bnad->bna_lock held, because of cfg_flags | |
2532 | * access. | |
2533 | */ | |
2534 | static void | |
2535 | bnad_q_num_init(struct bnad *bnad) | |
2536 | { | |
2537 | int rxps; | |
2538 | ||
2539 | rxps = min((uint)num_online_cpus(), | |
772b5235 | 2540 | (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX)); |
8b230ed8 RM |
2541 | |
2542 | if (!(bnad->cfg_flags & BNAD_CF_MSIX)) | |
2543 | rxps = 1; /* INTx */ | |
2544 | ||
2545 | bnad->num_rx = 1; | |
2546 | bnad->num_tx = 1; | |
2547 | bnad->num_rxp_per_rx = rxps; | |
2548 | bnad->num_txq_per_tx = BNAD_TXQ_NUM; | |
2549 | } | |
2550 | ||
2551 | /* | |
2552 | * Adjusts the Q numbers, given a number of msix vectors | |
2553 | * Give preference to RSS as opposed to Tx priority Queues, | |
2554 | * in such a case, just use 1 Tx Q | |
2555 | * Called with bnad->bna_lock held b'cos of cfg_flags access | |
2556 | */ | |
2557 | static void | |
078086f3 | 2558 | bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp) |
8b230ed8 RM |
2559 | { |
2560 | bnad->num_txq_per_tx = 1; | |
2561 | if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) + | |
2562 | bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) && | |
2563 | (bnad->cfg_flags & BNAD_CF_MSIX)) { | |
2564 | bnad->num_rxp_per_rx = msix_vectors - | |
2565 | (bnad->num_tx * bnad->num_txq_per_tx) - | |
2566 | BNAD_MAILBOX_MSIX_VECTORS; | |
2567 | } else | |
2568 | bnad->num_rxp_per_rx = 1; | |
2569 | } | |
2570 | ||
078086f3 RM |
2571 | /* Enable / disable ioceth */ |
2572 | static int | |
2573 | bnad_ioceth_disable(struct bnad *bnad) | |
8b230ed8 RM |
2574 | { |
2575 | unsigned long flags; | |
078086f3 | 2576 | int err = 0; |
8b230ed8 RM |
2577 | |
2578 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
078086f3 RM |
2579 | init_completion(&bnad->bnad_completions.ioc_comp); |
2580 | bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP); | |
8b230ed8 RM |
2581 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
2582 | ||
078086f3 RM |
2583 | wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp, |
2584 | msecs_to_jiffies(BNAD_IOCETH_TIMEOUT)); | |
2585 | ||
2586 | err = bnad->bnad_completions.ioc_comp_status; | |
2587 | return err; | |
8b230ed8 RM |
2588 | } |
2589 | ||
2590 | static int | |
078086f3 | 2591 | bnad_ioceth_enable(struct bnad *bnad) |
8b230ed8 RM |
2592 | { |
2593 | int err = 0; | |
2594 | unsigned long flags; | |
2595 | ||
8b230ed8 | 2596 | spin_lock_irqsave(&bnad->bna_lock, flags); |
078086f3 RM |
2597 | init_completion(&bnad->bnad_completions.ioc_comp); |
2598 | bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING; | |
2599 | bna_ioceth_enable(&bnad->bna.ioceth); | |
8b230ed8 RM |
2600 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
2601 | ||
078086f3 RM |
2602 | wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp, |
2603 | msecs_to_jiffies(BNAD_IOCETH_TIMEOUT)); | |
8b230ed8 | 2604 | |
078086f3 | 2605 | err = bnad->bnad_completions.ioc_comp_status; |
8b230ed8 RM |
2606 | |
2607 | return err; | |
2608 | } | |
2609 | ||
2610 | /* Free BNA resources */ | |
2611 | static void | |
078086f3 RM |
2612 | bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info, |
2613 | u32 res_val_max) | |
8b230ed8 RM |
2614 | { |
2615 | int i; | |
8b230ed8 | 2616 | |
078086f3 RM |
2617 | for (i = 0; i < res_val_max; i++) |
2618 | bnad_mem_free(bnad, &res_info[i].res_u.mem_info); | |
8b230ed8 RM |
2619 | } |
2620 | ||
2621 | /* Allocates memory and interrupt resources for BNA */ | |
2622 | static int | |
078086f3 RM |
2623 | bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, |
2624 | u32 res_val_max) | |
8b230ed8 RM |
2625 | { |
2626 | int i, err; | |
8b230ed8 | 2627 | |
078086f3 RM |
2628 | for (i = 0; i < res_val_max; i++) { |
2629 | err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info); | |
8b230ed8 RM |
2630 | if (err) |
2631 | goto err_return; | |
2632 | } | |
2633 | return 0; | |
2634 | ||
2635 | err_return: | |
078086f3 | 2636 | bnad_res_free(bnad, res_info, res_val_max); |
8b230ed8 RM |
2637 | return err; |
2638 | } | |
2639 | ||
2640 | /* Interrupt enable / disable */ | |
2641 | static void | |
2642 | bnad_enable_msix(struct bnad *bnad) | |
2643 | { | |
2644 | int i, ret; | |
8b230ed8 RM |
2645 | unsigned long flags; |
2646 | ||
2647 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2648 | if (!(bnad->cfg_flags & BNAD_CF_MSIX)) { | |
2649 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2650 | return; | |
2651 | } | |
2652 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2653 | ||
2654 | if (bnad->msix_table) | |
2655 | return; | |
2656 | ||
8b230ed8 | 2657 | bnad->msix_table = |
b7ee31c5 | 2658 | kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL); |
8b230ed8 RM |
2659 | |
2660 | if (!bnad->msix_table) | |
2661 | goto intx_mode; | |
2662 | ||
b7ee31c5 | 2663 | for (i = 0; i < bnad->msix_num; i++) |
8b230ed8 RM |
2664 | bnad->msix_table[i].entry = i; |
2665 | ||
43c20200 AG |
2666 | ret = pci_enable_msix_range(bnad->pcidev, bnad->msix_table, |
2667 | 1, bnad->msix_num); | |
2668 | if (ret < 0) { | |
2669 | goto intx_mode; | |
2670 | } else if (ret < bnad->msix_num) { | |
ecc46789 IV |
2671 | dev_warn(&bnad->pcidev->dev, |
2672 | "%d MSI-X vectors allocated < %d requested\n", | |
2673 | ret, bnad->msix_num); | |
8b230ed8 RM |
2674 | |
2675 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2676 | /* ret = #of vectors that we got */ | |
271e8b79 RM |
2677 | bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2, |
2678 | (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2); | |
8b230ed8 RM |
2679 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
2680 | ||
271e8b79 | 2681 | bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP + |
8b230ed8 | 2682 | BNAD_MAILBOX_MSIX_VECTORS; |
8b230ed8 | 2683 | |
43c20200 AG |
2684 | if (bnad->msix_num > ret) { |
2685 | pci_disable_msix(bnad->pcidev); | |
8b230ed8 | 2686 | goto intx_mode; |
43c20200 AG |
2687 | } |
2688 | } | |
078086f3 RM |
2689 | |
2690 | pci_intx(bnad->pcidev, 0); | |
2691 | ||
8b230ed8 RM |
2692 | return; |
2693 | ||
2694 | intx_mode: | |
ecc46789 IV |
2695 | dev_warn(&bnad->pcidev->dev, |
2696 | "MSI-X enable failed - operating in INTx mode\n"); | |
8b230ed8 RM |
2697 | |
2698 | kfree(bnad->msix_table); | |
2699 | bnad->msix_table = NULL; | |
2700 | bnad->msix_num = 0; | |
8b230ed8 RM |
2701 | spin_lock_irqsave(&bnad->bna_lock, flags); |
2702 | bnad->cfg_flags &= ~BNAD_CF_MSIX; | |
2703 | bnad_q_num_init(bnad); | |
2704 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2705 | } | |
2706 | ||
2707 | static void | |
2708 | bnad_disable_msix(struct bnad *bnad) | |
2709 | { | |
2710 | u32 cfg_flags; | |
2711 | unsigned long flags; | |
2712 | ||
2713 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2714 | cfg_flags = bnad->cfg_flags; | |
2715 | if (bnad->cfg_flags & BNAD_CF_MSIX) | |
2716 | bnad->cfg_flags &= ~BNAD_CF_MSIX; | |
2717 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2718 | ||
2719 | if (cfg_flags & BNAD_CF_MSIX) { | |
2720 | pci_disable_msix(bnad->pcidev); | |
2721 | kfree(bnad->msix_table); | |
2722 | bnad->msix_table = NULL; | |
2723 | } | |
2724 | } | |
2725 | ||
2726 | /* Netdev entry points */ | |
2727 | static int | |
2728 | bnad_open(struct net_device *netdev) | |
2729 | { | |
2730 | int err; | |
2731 | struct bnad *bnad = netdev_priv(netdev); | |
2732 | struct bna_pause_config pause_config; | |
8b230ed8 RM |
2733 | unsigned long flags; |
2734 | ||
2735 | mutex_lock(&bnad->conf_mutex); | |
2736 | ||
2737 | /* Tx */ | |
2738 | err = bnad_setup_tx(bnad, 0); | |
2739 | if (err) | |
2740 | goto err_return; | |
2741 | ||
2742 | /* Rx */ | |
2743 | err = bnad_setup_rx(bnad, 0); | |
2744 | if (err) | |
2745 | goto cleanup_tx; | |
2746 | ||
2747 | /* Port */ | |
2748 | pause_config.tx_pause = 0; | |
2749 | pause_config.rx_pause = 0; | |
2750 | ||
8b230ed8 | 2751 | spin_lock_irqsave(&bnad->bna_lock, flags); |
e29aa339 RM |
2752 | bna_enet_mtu_set(&bnad->bna.enet, |
2753 | BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL); | |
1f9883e0 | 2754 | bna_enet_pause_config(&bnad->bna.enet, &pause_config); |
078086f3 | 2755 | bna_enet_enable(&bnad->bna.enet); |
8b230ed8 RM |
2756 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
2757 | ||
2758 | /* Enable broadcast */ | |
2759 | bnad_enable_default_bcast(bnad); | |
2760 | ||
aad75b66 RM |
2761 | /* Restore VLANs, if any */ |
2762 | bnad_restore_vlans(bnad, 0); | |
2763 | ||
8b230ed8 RM |
2764 | /* Set the UCAST address */ |
2765 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2766 | bnad_mac_addr_set_locked(bnad, netdev->dev_addr); | |
2767 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2768 | ||
2769 | /* Start the stats timer */ | |
2770 | bnad_stats_timer_start(bnad); | |
2771 | ||
2772 | mutex_unlock(&bnad->conf_mutex); | |
2773 | ||
2774 | return 0; | |
2775 | ||
2776 | cleanup_tx: | |
b3cc6e88 | 2777 | bnad_destroy_tx(bnad, 0); |
8b230ed8 RM |
2778 | |
2779 | err_return: | |
2780 | mutex_unlock(&bnad->conf_mutex); | |
2781 | return err; | |
2782 | } | |
2783 | ||
2784 | static int | |
2785 | bnad_stop(struct net_device *netdev) | |
2786 | { | |
2787 | struct bnad *bnad = netdev_priv(netdev); | |
2788 | unsigned long flags; | |
2789 | ||
2790 | mutex_lock(&bnad->conf_mutex); | |
2791 | ||
2792 | /* Stop the stats timer */ | |
2793 | bnad_stats_timer_stop(bnad); | |
2794 | ||
078086f3 | 2795 | init_completion(&bnad->bnad_completions.enet_comp); |
8b230ed8 RM |
2796 | |
2797 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
078086f3 RM |
2798 | bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP, |
2799 | bnad_cb_enet_disabled); | |
8b230ed8 RM |
2800 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
2801 | ||
078086f3 | 2802 | wait_for_completion(&bnad->bnad_completions.enet_comp); |
8b230ed8 | 2803 | |
b3cc6e88 JH |
2804 | bnad_destroy_tx(bnad, 0); |
2805 | bnad_destroy_rx(bnad, 0); | |
8b230ed8 RM |
2806 | |
2807 | /* Synchronize mailbox IRQ */ | |
2808 | bnad_mbox_irq_sync(bnad); | |
2809 | ||
2810 | mutex_unlock(&bnad->conf_mutex); | |
2811 | ||
2812 | return 0; | |
2813 | } | |
2814 | ||
2815 | /* TX */ | |
5216562a RM |
2816 | /* Returns 0 for success */ |
2817 | static int | |
2818 | bnad_txq_wi_prepare(struct bnad *bnad, struct bna_tcb *tcb, | |
2819 | struct sk_buff *skb, struct bna_txq_entry *txqent) | |
8b230ed8 | 2820 | { |
5216562a RM |
2821 | u16 flags = 0; |
2822 | u32 gso_size; | |
2823 | u16 vlan_tag = 0; | |
8b230ed8 | 2824 | |
df8a39de JP |
2825 | if (skb_vlan_tag_present(skb)) { |
2826 | vlan_tag = (u16)skb_vlan_tag_get(skb); | |
8b230ed8 RM |
2827 | flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN); |
2828 | } | |
2829 | if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) { | |
5216562a RM |
2830 | vlan_tag = ((tcb->priority & 0x7) << VLAN_PRIO_SHIFT) |
2831 | | (vlan_tag & 0x1fff); | |
8b230ed8 RM |
2832 | flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN); |
2833 | } | |
8b230ed8 RM |
2834 | txqent->hdr.wi.vlan_tag = htons(vlan_tag); |
2835 | ||
2836 | if (skb_is_gso(skb)) { | |
271e8b79 | 2837 | gso_size = skb_shinfo(skb)->gso_size; |
5216562a | 2838 | if (unlikely(gso_size > bnad->netdev->mtu)) { |
271e8b79 | 2839 | BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long); |
5216562a | 2840 | return -EINVAL; |
271e8b79 RM |
2841 | } |
2842 | if (unlikely((gso_size + skb_transport_offset(skb) + | |
5216562a | 2843 | tcp_hdrlen(skb)) >= skb->len)) { |
b779d0af | 2844 | txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND); |
271e8b79 RM |
2845 | txqent->hdr.wi.lso_mss = 0; |
2846 | BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short); | |
2847 | } else { | |
b779d0af | 2848 | txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND_LSO); |
271e8b79 RM |
2849 | txqent->hdr.wi.lso_mss = htons(gso_size); |
2850 | } | |
2851 | ||
5216562a | 2852 | if (bnad_tso_prepare(bnad, skb)) { |
271e8b79 | 2853 | BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare); |
5216562a | 2854 | return -EINVAL; |
8b230ed8 | 2855 | } |
5216562a | 2856 | |
8b230ed8 RM |
2857 | flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM); |
2858 | txqent->hdr.wi.l4_hdr_size_n_offset = | |
5216562a RM |
2859 | htons(BNA_TXQ_WI_L4_HDR_N_OFFSET( |
2860 | tcp_hdrlen(skb) >> 2, skb_transport_offset(skb))); | |
2861 | } else { | |
b779d0af | 2862 | txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND); |
8b230ed8 RM |
2863 | txqent->hdr.wi.lso_mss = 0; |
2864 | ||
6654cf60 | 2865 | if (unlikely(skb->len > (bnad->netdev->mtu + VLAN_ETH_HLEN))) { |
271e8b79 | 2866 | BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long); |
5216562a | 2867 | return -EINVAL; |
8b230ed8 | 2868 | } |
8b230ed8 | 2869 | |
271e8b79 | 2870 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
1c53730a | 2871 | __be16 net_proto = vlan_get_protocol(skb); |
271e8b79 | 2872 | u8 proto = 0; |
8b230ed8 | 2873 | |
1c53730a | 2874 | if (net_proto == htons(ETH_P_IP)) |
271e8b79 | 2875 | proto = ip_hdr(skb)->protocol; |
5216562a | 2876 | #ifdef NETIF_F_IPV6_CSUM |
1c53730a | 2877 | else if (net_proto == htons(ETH_P_IPV6)) { |
271e8b79 RM |
2878 | /* nexthdr may not be TCP immediately. */ |
2879 | proto = ipv6_hdr(skb)->nexthdr; | |
2880 | } | |
5216562a | 2881 | #endif |
271e8b79 RM |
2882 | if (proto == IPPROTO_TCP) { |
2883 | flags |= BNA_TXQ_WI_CF_TCP_CKSUM; | |
2884 | txqent->hdr.wi.l4_hdr_size_n_offset = | |
2885 | htons(BNA_TXQ_WI_L4_HDR_N_OFFSET | |
2886 | (0, skb_transport_offset(skb))); | |
2887 | ||
2888 | BNAD_UPDATE_CTR(bnad, tcpcsum_offload); | |
2889 | ||
2890 | if (unlikely(skb_headlen(skb) < | |
5216562a RM |
2891 | skb_transport_offset(skb) + |
2892 | tcp_hdrlen(skb))) { | |
271e8b79 | 2893 | BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr); |
5216562a | 2894 | return -EINVAL; |
271e8b79 | 2895 | } |
271e8b79 RM |
2896 | } else if (proto == IPPROTO_UDP) { |
2897 | flags |= BNA_TXQ_WI_CF_UDP_CKSUM; | |
2898 | txqent->hdr.wi.l4_hdr_size_n_offset = | |
2899 | htons(BNA_TXQ_WI_L4_HDR_N_OFFSET | |
2900 | (0, skb_transport_offset(skb))); | |
2901 | ||
2902 | BNAD_UPDATE_CTR(bnad, udpcsum_offload); | |
2903 | if (unlikely(skb_headlen(skb) < | |
5216562a | 2904 | skb_transport_offset(skb) + |
271e8b79 | 2905 | sizeof(struct udphdr))) { |
271e8b79 | 2906 | BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr); |
5216562a | 2907 | return -EINVAL; |
271e8b79 RM |
2908 | } |
2909 | } else { | |
5216562a | 2910 | |
271e8b79 | 2911 | BNAD_UPDATE_CTR(bnad, tx_skb_csum_err); |
5216562a | 2912 | return -EINVAL; |
8b230ed8 | 2913 | } |
5216562a | 2914 | } else |
271e8b79 | 2915 | txqent->hdr.wi.l4_hdr_size_n_offset = 0; |
8b230ed8 RM |
2916 | } |
2917 | ||
2918 | txqent->hdr.wi.flags = htons(flags); | |
8b230ed8 RM |
2919 | txqent->hdr.wi.frame_length = htonl(skb->len); |
2920 | ||
5216562a RM |
2921 | return 0; |
2922 | } | |
2923 | ||
2924 | /* | |
2925 | * bnad_start_xmit : Netdev entry point for Transmit | |
2926 | * Called under lock held by net_device | |
2927 | */ | |
2928 | static netdev_tx_t | |
2929 | bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev) | |
2930 | { | |
2931 | struct bnad *bnad = netdev_priv(netdev); | |
2932 | u32 txq_id = 0; | |
2933 | struct bna_tcb *tcb = NULL; | |
2934 | struct bnad_tx_unmap *unmap_q, *unmap, *head_unmap; | |
2935 | u32 prod, q_depth, vect_id; | |
2936 | u32 wis, vectors, len; | |
2937 | int i; | |
2938 | dma_addr_t dma_addr; | |
2939 | struct bna_txq_entry *txqent; | |
2940 | ||
271e8b79 | 2941 | len = skb_headlen(skb); |
8b230ed8 | 2942 | |
5216562a RM |
2943 | /* Sanity checks for the skb */ |
2944 | ||
2945 | if (unlikely(skb->len <= ETH_HLEN)) { | |
27400df8 | 2946 | dev_kfree_skb_any(skb); |
5216562a RM |
2947 | BNAD_UPDATE_CTR(bnad, tx_skb_too_short); |
2948 | return NETDEV_TX_OK; | |
2949 | } | |
2950 | if (unlikely(len > BFI_TX_MAX_DATA_PER_VECTOR)) { | |
27400df8 | 2951 | dev_kfree_skb_any(skb); |
5216562a RM |
2952 | BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero); |
2953 | return NETDEV_TX_OK; | |
2954 | } | |
2955 | if (unlikely(len == 0)) { | |
27400df8 | 2956 | dev_kfree_skb_any(skb); |
5216562a RM |
2957 | BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero); |
2958 | return NETDEV_TX_OK; | |
2959 | } | |
2960 | ||
2961 | tcb = bnad->tx_info[0].tcb[txq_id]; | |
271e8b79 | 2962 | |
5216562a RM |
2963 | /* |
2964 | * Takes care of the Tx that is scheduled between clearing the flag | |
2965 | * and the netif_tx_stop_all_queues() call. | |
2966 | */ | |
96e31adf | 2967 | if (unlikely(!tcb || !test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) { |
27400df8 | 2968 | dev_kfree_skb_any(skb); |
5216562a RM |
2969 | BNAD_UPDATE_CTR(bnad, tx_skb_stopping); |
2970 | return NETDEV_TX_OK; | |
2971 | } | |
2972 | ||
96e31adf RM |
2973 | q_depth = tcb->q_depth; |
2974 | prod = tcb->producer_index; | |
2975 | unmap_q = tcb->unmap_q; | |
2976 | ||
5216562a RM |
2977 | vectors = 1 + skb_shinfo(skb)->nr_frags; |
2978 | wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */ | |
2979 | ||
2980 | if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) { | |
27400df8 | 2981 | dev_kfree_skb_any(skb); |
5216562a RM |
2982 | BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors); |
2983 | return NETDEV_TX_OK; | |
2984 | } | |
2985 | ||
2986 | /* Check for available TxQ resources */ | |
2987 | if (unlikely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) { | |
2988 | if ((*tcb->hw_consumer_index != tcb->consumer_index) && | |
2989 | !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) { | |
2990 | u32 sent; | |
2991 | sent = bnad_txcmpl_process(bnad, tcb); | |
2992 | if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) | |
2993 | bna_ib_ack(tcb->i_dbell, sent); | |
4e857c58 | 2994 | smp_mb__before_atomic(); |
5216562a RM |
2995 | clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); |
2996 | } else { | |
2997 | netif_stop_queue(netdev); | |
2998 | BNAD_UPDATE_CTR(bnad, netif_queue_stop); | |
2999 | } | |
3000 | ||
3001 | smp_mb(); | |
3002 | /* | |
3003 | * Check again to deal with race condition between | |
3004 | * netif_stop_queue here, and netif_wake_queue in | |
3005 | * interrupt handler which is not inside netif tx lock. | |
3006 | */ | |
3007 | if (likely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) { | |
3008 | BNAD_UPDATE_CTR(bnad, netif_queue_stop); | |
3009 | return NETDEV_TX_BUSY; | |
3010 | } else { | |
3011 | netif_wake_queue(netdev); | |
3012 | BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); | |
3013 | } | |
3014 | } | |
3015 | ||
3016 | txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod]; | |
3017 | head_unmap = &unmap_q[prod]; | |
3018 | ||
3019 | /* Program the opcode, flags, frame_len, num_vectors in WI */ | |
3020 | if (bnad_txq_wi_prepare(bnad, tcb, skb, txqent)) { | |
27400df8 | 3021 | dev_kfree_skb_any(skb); |
5216562a RM |
3022 | return NETDEV_TX_OK; |
3023 | } | |
3024 | txqent->hdr.wi.reserved = 0; | |
3025 | txqent->hdr.wi.num_vectors = vectors; | |
3026 | ||
3027 | head_unmap->skb = skb; | |
3028 | head_unmap->nvecs = 0; | |
3029 | ||
3030 | /* Program the vectors */ | |
3031 | unmap = head_unmap; | |
3032 | dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data, | |
3033 | len, DMA_TO_DEVICE); | |
ba5ca784 IV |
3034 | if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { |
3035 | dev_kfree_skb_any(skb); | |
3036 | BNAD_UPDATE_CTR(bnad, tx_skb_map_failed); | |
3037 | return NETDEV_TX_OK; | |
3038 | } | |
5216562a RM |
3039 | BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr); |
3040 | txqent->vector[0].length = htons(len); | |
3041 | dma_unmap_addr_set(&unmap->vectors[0], dma_addr, dma_addr); | |
3042 | head_unmap->nvecs++; | |
3043 | ||
3044 | for (i = 0, vect_id = 0; i < vectors - 1; i++) { | |
9e903e08 | 3045 | const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; |
24f5d33d | 3046 | u32 size = skb_frag_size(frag); |
8b230ed8 | 3047 | |
271e8b79 | 3048 | if (unlikely(size == 0)) { |
5216562a RM |
3049 | /* Undo the changes starting at tcb->producer_index */ |
3050 | bnad_tx_buff_unmap(bnad, unmap_q, q_depth, | |
3051 | tcb->producer_index); | |
27400df8 | 3052 | dev_kfree_skb_any(skb); |
271e8b79 RM |
3053 | BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero); |
3054 | return NETDEV_TX_OK; | |
3055 | } | |
3056 | ||
3057 | len += size; | |
3058 | ||
5216562a RM |
3059 | vect_id++; |
3060 | if (vect_id == BFI_TX_MAX_VECTORS_PER_WI) { | |
8b230ed8 | 3061 | vect_id = 0; |
5216562a RM |
3062 | BNA_QE_INDX_INC(prod, q_depth); |
3063 | txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod]; | |
b779d0af | 3064 | txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION); |
5216562a | 3065 | unmap = &unmap_q[prod]; |
8b230ed8 RM |
3066 | } |
3067 | ||
4d5b1a67 IC |
3068 | dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag, |
3069 | 0, size, DMA_TO_DEVICE); | |
ba5ca784 IV |
3070 | if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { |
3071 | /* Undo the changes starting at tcb->producer_index */ | |
3072 | bnad_tx_buff_unmap(bnad, unmap_q, q_depth, | |
3073 | tcb->producer_index); | |
3074 | dev_kfree_skb_any(skb); | |
3075 | BNAD_UPDATE_CTR(bnad, tx_skb_map_failed); | |
3076 | return NETDEV_TX_OK; | |
3077 | } | |
3078 | ||
ecca6a96 | 3079 | dma_unmap_len_set(&unmap->vectors[vect_id], dma_len, size); |
8b230ed8 | 3080 | BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr); |
5216562a RM |
3081 | txqent->vector[vect_id].length = htons(size); |
3082 | dma_unmap_addr_set(&unmap->vectors[vect_id], dma_addr, | |
ecca6a96 | 3083 | dma_addr); |
5216562a | 3084 | head_unmap->nvecs++; |
8b230ed8 RM |
3085 | } |
3086 | ||
271e8b79 | 3087 | if (unlikely(len != skb->len)) { |
5216562a RM |
3088 | /* Undo the changes starting at tcb->producer_index */ |
3089 | bnad_tx_buff_unmap(bnad, unmap_q, q_depth, tcb->producer_index); | |
27400df8 | 3090 | dev_kfree_skb_any(skb); |
271e8b79 RM |
3091 | BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch); |
3092 | return NETDEV_TX_OK; | |
3093 | } | |
3094 | ||
5216562a RM |
3095 | BNA_QE_INDX_INC(prod, q_depth); |
3096 | tcb->producer_index = prod; | |
8b230ed8 | 3097 | |
d667f785 | 3098 | wmb(); |
be7fa326 RM |
3099 | |
3100 | if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) | |
3101 | return NETDEV_TX_OK; | |
3102 | ||
fee1253e RM |
3103 | skb_tx_timestamp(skb); |
3104 | ||
8b230ed8 RM |
3105 | bna_txq_prod_indx_doorbell(tcb); |
3106 | ||
8b230ed8 RM |
3107 | return NETDEV_TX_OK; |
3108 | } | |
3109 | ||
3110 | /* | |
3111 | * Used spin_lock to synchronize reading of stats structures, which | |
3112 | * is written by BNA under the same lock. | |
3113 | */ | |
250e061e ED |
3114 | static struct rtnl_link_stats64 * |
3115 | bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats) | |
8b230ed8 RM |
3116 | { |
3117 | struct bnad *bnad = netdev_priv(netdev); | |
3118 | unsigned long flags; | |
3119 | ||
3120 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3121 | ||
250e061e ED |
3122 | bnad_netdev_qstats_fill(bnad, stats); |
3123 | bnad_netdev_hwstats_fill(bnad, stats); | |
8b230ed8 RM |
3124 | |
3125 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3126 | ||
250e061e | 3127 | return stats; |
8b230ed8 RM |
3128 | } |
3129 | ||
fe1624cf RM |
3130 | static void |
3131 | bnad_set_rx_ucast_fltr(struct bnad *bnad) | |
3132 | { | |
3133 | struct net_device *netdev = bnad->netdev; | |
3134 | int uc_count = netdev_uc_count(netdev); | |
3135 | enum bna_cb_status ret; | |
3136 | u8 *mac_list; | |
3137 | struct netdev_hw_addr *ha; | |
3138 | int entry; | |
3139 | ||
3140 | if (netdev_uc_empty(bnad->netdev)) { | |
1f9883e0 | 3141 | bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL); |
fe1624cf RM |
3142 | return; |
3143 | } | |
3144 | ||
3145 | if (uc_count > bna_attr(&bnad->bna)->num_ucmac) | |
3146 | goto mode_default; | |
3147 | ||
3148 | mac_list = kzalloc(uc_count * ETH_ALEN, GFP_ATOMIC); | |
3149 | if (mac_list == NULL) | |
3150 | goto mode_default; | |
3151 | ||
3152 | entry = 0; | |
3153 | netdev_for_each_uc_addr(ha, netdev) { | |
e2f9ecfc | 3154 | ether_addr_copy(&mac_list[entry * ETH_ALEN], &ha->addr[0]); |
fe1624cf RM |
3155 | entry++; |
3156 | } | |
3157 | ||
1f9883e0 | 3158 | ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry, mac_list); |
fe1624cf RM |
3159 | kfree(mac_list); |
3160 | ||
3161 | if (ret != BNA_CB_SUCCESS) | |
3162 | goto mode_default; | |
3163 | ||
3164 | return; | |
3165 | ||
3166 | /* ucast packets not in UCAM are routed to default function */ | |
3167 | mode_default: | |
3168 | bnad->cfg_flags |= BNAD_CF_DEFAULT; | |
1f9883e0 | 3169 | bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL); |
fe1624cf RM |
3170 | } |
3171 | ||
3172 | static void | |
3173 | bnad_set_rx_mcast_fltr(struct bnad *bnad) | |
3174 | { | |
3175 | struct net_device *netdev = bnad->netdev; | |
3176 | int mc_count = netdev_mc_count(netdev); | |
3177 | enum bna_cb_status ret; | |
3178 | u8 *mac_list; | |
3179 | ||
3180 | if (netdev->flags & IFF_ALLMULTI) | |
3181 | goto mode_allmulti; | |
3182 | ||
3183 | if (netdev_mc_empty(netdev)) | |
3184 | return; | |
3185 | ||
3186 | if (mc_count > bna_attr(&bnad->bna)->num_mcmac) | |
3187 | goto mode_allmulti; | |
3188 | ||
3189 | mac_list = kzalloc((mc_count + 1) * ETH_ALEN, GFP_ATOMIC); | |
3190 | ||
3191 | if (mac_list == NULL) | |
3192 | goto mode_allmulti; | |
3193 | ||
e2f9ecfc | 3194 | ether_addr_copy(&mac_list[0], &bnad_bcast_addr[0]); |
fe1624cf RM |
3195 | |
3196 | /* copy rest of the MCAST addresses */ | |
3197 | bnad_netdev_mc_list_get(netdev, mac_list); | |
1f9883e0 | 3198 | ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1, mac_list); |
fe1624cf RM |
3199 | kfree(mac_list); |
3200 | ||
3201 | if (ret != BNA_CB_SUCCESS) | |
3202 | goto mode_allmulti; | |
3203 | ||
3204 | return; | |
3205 | ||
3206 | mode_allmulti: | |
3207 | bnad->cfg_flags |= BNAD_CF_ALLMULTI; | |
1f9883e0 | 3208 | bna_rx_mcast_delall(bnad->rx_info[0].rx); |
fe1624cf RM |
3209 | } |
3210 | ||
a2122d95 | 3211 | void |
8b230ed8 RM |
3212 | bnad_set_rx_mode(struct net_device *netdev) |
3213 | { | |
3214 | struct bnad *bnad = netdev_priv(netdev); | |
fe1624cf | 3215 | enum bna_rxmode new_mode, mode_mask; |
8b230ed8 RM |
3216 | unsigned long flags; |
3217 | ||
3218 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3219 | ||
fe1624cf RM |
3220 | if (bnad->rx_info[0].rx == NULL) { |
3221 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3222 | return; | |
8b230ed8 RM |
3223 | } |
3224 | ||
fe1624cf RM |
3225 | /* clear bnad flags to update it with new settings */ |
3226 | bnad->cfg_flags &= ~(BNAD_CF_PROMISC | BNAD_CF_DEFAULT | | |
3227 | BNAD_CF_ALLMULTI); | |
271e8b79 | 3228 | |
fe1624cf RM |
3229 | new_mode = 0; |
3230 | if (netdev->flags & IFF_PROMISC) { | |
3231 | new_mode |= BNAD_RXMODE_PROMISC_DEFAULT; | |
3232 | bnad->cfg_flags |= BNAD_CF_PROMISC; | |
3233 | } else { | |
3234 | bnad_set_rx_mcast_fltr(bnad); | |
8b230ed8 | 3235 | |
fe1624cf RM |
3236 | if (bnad->cfg_flags & BNAD_CF_ALLMULTI) |
3237 | new_mode |= BNA_RXMODE_ALLMULTI; | |
8b230ed8 | 3238 | |
fe1624cf | 3239 | bnad_set_rx_ucast_fltr(bnad); |
8b230ed8 | 3240 | |
fe1624cf RM |
3241 | if (bnad->cfg_flags & BNAD_CF_DEFAULT) |
3242 | new_mode |= BNA_RXMODE_DEFAULT; | |
3243 | } | |
8b230ed8 | 3244 | |
fe1624cf RM |
3245 | mode_mask = BNA_RXMODE_PROMISC | BNA_RXMODE_DEFAULT | |
3246 | BNA_RXMODE_ALLMULTI; | |
1f9883e0 | 3247 | bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask); |
8b230ed8 | 3248 | |
8b230ed8 RM |
3249 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
3250 | } | |
3251 | ||
3252 | /* | |
3253 | * bna_lock is used to sync writes to netdev->addr | |
3254 | * conf_lock cannot be used since this call may be made | |
3255 | * in a non-blocking context. | |
3256 | */ | |
3257 | static int | |
e2f9ecfc | 3258 | bnad_set_mac_address(struct net_device *netdev, void *addr) |
8b230ed8 RM |
3259 | { |
3260 | int err; | |
3261 | struct bnad *bnad = netdev_priv(netdev); | |
e2f9ecfc | 3262 | struct sockaddr *sa = (struct sockaddr *)addr; |
8b230ed8 RM |
3263 | unsigned long flags; |
3264 | ||
3265 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3266 | ||
3267 | err = bnad_mac_addr_set_locked(bnad, sa->sa_data); | |
8b230ed8 | 3268 | if (!err) |
e2f9ecfc | 3269 | ether_addr_copy(netdev->dev_addr, sa->sa_data); |
8b230ed8 RM |
3270 | |
3271 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3272 | ||
3273 | return err; | |
3274 | } | |
3275 | ||
3276 | static int | |
e29aa339 | 3277 | bnad_mtu_set(struct bnad *bnad, int frame_size) |
8b230ed8 | 3278 | { |
8b230ed8 RM |
3279 | unsigned long flags; |
3280 | ||
078086f3 RM |
3281 | init_completion(&bnad->bnad_completions.mtu_comp); |
3282 | ||
3283 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
e29aa339 | 3284 | bna_enet_mtu_set(&bnad->bna.enet, frame_size, bnad_cb_enet_mtu_set); |
078086f3 RM |
3285 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
3286 | ||
3287 | wait_for_completion(&bnad->bnad_completions.mtu_comp); | |
3288 | ||
3289 | return bnad->bnad_completions.mtu_comp_status; | |
3290 | } | |
3291 | ||
3292 | static int | |
3293 | bnad_change_mtu(struct net_device *netdev, int new_mtu) | |
3294 | { | |
e29aa339 | 3295 | int err, mtu; |
8b230ed8 | 3296 | struct bnad *bnad = netdev_priv(netdev); |
e29aa339 | 3297 | u32 rx_count = 0, frame, new_frame; |
8b230ed8 RM |
3298 | |
3299 | if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU) | |
3300 | return -EINVAL; | |
3301 | ||
3302 | mutex_lock(&bnad->conf_mutex); | |
3303 | ||
e29aa339 | 3304 | mtu = netdev->mtu; |
8b230ed8 RM |
3305 | netdev->mtu = new_mtu; |
3306 | ||
e29aa339 RM |
3307 | frame = BNAD_FRAME_SIZE(mtu); |
3308 | new_frame = BNAD_FRAME_SIZE(new_mtu); | |
3309 | ||
3310 | /* check if multi-buffer needs to be enabled */ | |
3311 | if (BNAD_PCI_DEV_IS_CAT2(bnad) && | |
3312 | netif_running(bnad->netdev)) { | |
3313 | /* only when transition is over 4K */ | |
3314 | if ((frame <= 4096 && new_frame > 4096) || | |
3315 | (frame > 4096 && new_frame <= 4096)) | |
3316 | rx_count = bnad_reinit_rx(bnad); | |
3317 | } | |
3318 | ||
3319 | /* rx_count > 0 - new rx created | |
3320 | * - Linux set err = 0 and return | |
3321 | */ | |
3322 | err = bnad_mtu_set(bnad, new_frame); | |
078086f3 RM |
3323 | if (err) |
3324 | err = -EBUSY; | |
8b230ed8 RM |
3325 | |
3326 | mutex_unlock(&bnad->conf_mutex); | |
3327 | return err; | |
3328 | } | |
3329 | ||
8e586137 | 3330 | static int |
80d5c368 | 3331 | bnad_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid) |
8b230ed8 RM |
3332 | { |
3333 | struct bnad *bnad = netdev_priv(netdev); | |
3334 | unsigned long flags; | |
3335 | ||
3336 | if (!bnad->rx_info[0].rx) | |
8e586137 | 3337 | return 0; |
8b230ed8 RM |
3338 | |
3339 | mutex_lock(&bnad->conf_mutex); | |
3340 | ||
3341 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3342 | bna_rx_vlan_add(bnad->rx_info[0].rx, vid); | |
f859d7cb | 3343 | set_bit(vid, bnad->active_vlans); |
8b230ed8 RM |
3344 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
3345 | ||
3346 | mutex_unlock(&bnad->conf_mutex); | |
8e586137 JP |
3347 | |
3348 | return 0; | |
8b230ed8 RM |
3349 | } |
3350 | ||
8e586137 | 3351 | static int |
80d5c368 | 3352 | bnad_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) |
8b230ed8 RM |
3353 | { |
3354 | struct bnad *bnad = netdev_priv(netdev); | |
3355 | unsigned long flags; | |
3356 | ||
3357 | if (!bnad->rx_info[0].rx) | |
8e586137 | 3358 | return 0; |
8b230ed8 RM |
3359 | |
3360 | mutex_lock(&bnad->conf_mutex); | |
3361 | ||
3362 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
f859d7cb | 3363 | clear_bit(vid, bnad->active_vlans); |
8b230ed8 RM |
3364 | bna_rx_vlan_del(bnad->rx_info[0].rx, vid); |
3365 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3366 | ||
3367 | mutex_unlock(&bnad->conf_mutex); | |
8e586137 JP |
3368 | |
3369 | return 0; | |
8b230ed8 RM |
3370 | } |
3371 | ||
877767dc IV |
3372 | static int bnad_set_features(struct net_device *dev, netdev_features_t features) |
3373 | { | |
3374 | struct bnad *bnad = netdev_priv(dev); | |
3375 | netdev_features_t changed = features ^ dev->features; | |
3376 | ||
3377 | if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(dev)) { | |
3378 | unsigned long flags; | |
3379 | ||
3380 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3381 | ||
3382 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
3383 | bna_rx_vlan_strip_enable(bnad->rx_info[0].rx); | |
3384 | else | |
3385 | bna_rx_vlan_strip_disable(bnad->rx_info[0].rx); | |
3386 | ||
3387 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3388 | } | |
3389 | ||
3390 | return 0; | |
3391 | } | |
3392 | ||
8b230ed8 RM |
3393 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3394 | static void | |
3395 | bnad_netpoll(struct net_device *netdev) | |
3396 | { | |
3397 | struct bnad *bnad = netdev_priv(netdev); | |
3398 | struct bnad_rx_info *rx_info; | |
3399 | struct bnad_rx_ctrl *rx_ctrl; | |
3400 | u32 curr_mask; | |
3401 | int i, j; | |
3402 | ||
3403 | if (!(bnad->cfg_flags & BNAD_CF_MSIX)) { | |
3404 | bna_intx_disable(&bnad->bna, curr_mask); | |
3405 | bnad_isr(bnad->pcidev->irq, netdev); | |
3406 | bna_intx_enable(&bnad->bna, curr_mask); | |
3407 | } else { | |
19dbff9f RM |
3408 | /* |
3409 | * Tx processing may happen in sending context, so no need | |
3410 | * to explicitly process completions here | |
3411 | */ | |
3412 | ||
3413 | /* Rx processing */ | |
8b230ed8 RM |
3414 | for (i = 0; i < bnad->num_rx; i++) { |
3415 | rx_info = &bnad->rx_info[i]; | |
3416 | if (!rx_info->rx) | |
3417 | continue; | |
3418 | for (j = 0; j < bnad->num_rxp_per_rx; j++) { | |
3419 | rx_ctrl = &rx_info->rx_ctrl[j]; | |
271e8b79 | 3420 | if (rx_ctrl->ccb) |
8b230ed8 RM |
3421 | bnad_netif_rx_schedule_poll(bnad, |
3422 | rx_ctrl->ccb); | |
8b230ed8 RM |
3423 | } |
3424 | } | |
3425 | } | |
3426 | } | |
3427 | #endif | |
3428 | ||
3429 | static const struct net_device_ops bnad_netdev_ops = { | |
3430 | .ndo_open = bnad_open, | |
3431 | .ndo_stop = bnad_stop, | |
3432 | .ndo_start_xmit = bnad_start_xmit, | |
250e061e | 3433 | .ndo_get_stats64 = bnad_get_stats64, |
8b230ed8 | 3434 | .ndo_set_rx_mode = bnad_set_rx_mode, |
8b230ed8 RM |
3435 | .ndo_validate_addr = eth_validate_addr, |
3436 | .ndo_set_mac_address = bnad_set_mac_address, | |
3437 | .ndo_change_mtu = bnad_change_mtu, | |
8b230ed8 RM |
3438 | .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid, |
3439 | .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid, | |
877767dc | 3440 | .ndo_set_features = bnad_set_features, |
8b230ed8 RM |
3441 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3442 | .ndo_poll_controller = bnad_netpoll | |
3443 | #endif | |
3444 | }; | |
3445 | ||
3446 | static void | |
3447 | bnad_netdev_init(struct bnad *bnad, bool using_dac) | |
3448 | { | |
3449 | struct net_device *netdev = bnad->netdev; | |
3450 | ||
e5ee20e7 MM |
3451 | netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | |
3452 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
877767dc IV |
3453 | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_TX | |
3454 | NETIF_F_HW_VLAN_CTAG_RX; | |
8b230ed8 | 3455 | |
e5ee20e7 MM |
3456 | netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA | |
3457 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
3458 | NETIF_F_TSO | NETIF_F_TSO6; | |
8b230ed8 | 3459 | |
877767dc | 3460 | netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; |
8b230ed8 RM |
3461 | |
3462 | if (using_dac) | |
3463 | netdev->features |= NETIF_F_HIGHDMA; | |
3464 | ||
8b230ed8 RM |
3465 | netdev->mem_start = bnad->mmio_start; |
3466 | netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1; | |
3467 | ||
3468 | netdev->netdev_ops = &bnad_netdev_ops; | |
3469 | bnad_set_ethtool_ops(netdev); | |
3470 | } | |
3471 | ||
3472 | /* | |
3473 | * 1. Initialize the bnad structure | |
3474 | * 2. Setup netdev pointer in pci_dev | |
d95d1081 JH |
3475 | * 3. Initialize no. of TxQ & CQs & MSIX vectors |
3476 | * 4. Initialize work queue. | |
8b230ed8 RM |
3477 | */ |
3478 | static int | |
3479 | bnad_init(struct bnad *bnad, | |
3480 | struct pci_dev *pdev, struct net_device *netdev) | |
3481 | { | |
3482 | unsigned long flags; | |
3483 | ||
3484 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
3485 | pci_set_drvdata(pdev, netdev); | |
3486 | ||
3487 | bnad->netdev = netdev; | |
3488 | bnad->pcidev = pdev; | |
3489 | bnad->mmio_start = pci_resource_start(pdev, 0); | |
3490 | bnad->mmio_len = pci_resource_len(pdev, 0); | |
3491 | bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len); | |
3492 | if (!bnad->bar0) { | |
3493 | dev_err(&pdev->dev, "ioremap for bar0 failed\n"); | |
8b230ed8 RM |
3494 | return -ENOMEM; |
3495 | } | |
ecc46789 IV |
3496 | dev_info(&pdev->dev, "bar0 mapped to %p, len %llu\n", bnad->bar0, |
3497 | (unsigned long long) bnad->mmio_len); | |
8b230ed8 RM |
3498 | |
3499 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3500 | if (!bnad_msix_disable) | |
3501 | bnad->cfg_flags = BNAD_CF_MSIX; | |
3502 | ||
3503 | bnad->cfg_flags |= BNAD_CF_DIM_ENABLED; | |
3504 | ||
3505 | bnad_q_num_init(bnad); | |
3506 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3507 | ||
3508 | bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) + | |
3509 | (bnad->num_rx * bnad->num_rxp_per_rx) + | |
3510 | BNAD_MAILBOX_MSIX_VECTORS; | |
8b230ed8 RM |
3511 | |
3512 | bnad->txq_depth = BNAD_TXQ_DEPTH; | |
3513 | bnad->rxq_depth = BNAD_RXQ_DEPTH; | |
8b230ed8 RM |
3514 | |
3515 | bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO; | |
3516 | bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO; | |
3517 | ||
01b54b14 JH |
3518 | sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id); |
3519 | bnad->work_q = create_singlethread_workqueue(bnad->wq_name); | |
ba21fc69 WY |
3520 | if (!bnad->work_q) { |
3521 | iounmap(bnad->bar0); | |
01b54b14 | 3522 | return -ENOMEM; |
ba21fc69 | 3523 | } |
01b54b14 | 3524 | |
8b230ed8 RM |
3525 | return 0; |
3526 | } | |
3527 | ||
3528 | /* | |
3529 | * Must be called after bnad_pci_uninit() | |
3530 | * so that iounmap() and pci_set_drvdata(NULL) | |
3531 | * happens only after PCI uninitialization. | |
3532 | */ | |
3533 | static void | |
3534 | bnad_uninit(struct bnad *bnad) | |
3535 | { | |
01b54b14 JH |
3536 | if (bnad->work_q) { |
3537 | flush_workqueue(bnad->work_q); | |
3538 | destroy_workqueue(bnad->work_q); | |
3539 | bnad->work_q = NULL; | |
3540 | } | |
3541 | ||
8b230ed8 RM |
3542 | if (bnad->bar0) |
3543 | iounmap(bnad->bar0); | |
8b230ed8 RM |
3544 | } |
3545 | ||
3546 | /* | |
3547 | * Initialize locks | |
078086f3 | 3548 | a) Per ioceth mutes used for serializing configuration |
8b230ed8 RM |
3549 | changes from OS interface |
3550 | b) spin lock used to protect bna state machine | |
3551 | */ | |
3552 | static void | |
3553 | bnad_lock_init(struct bnad *bnad) | |
3554 | { | |
3555 | spin_lock_init(&bnad->bna_lock); | |
3556 | mutex_init(&bnad->conf_mutex); | |
3557 | } | |
3558 | ||
3559 | static void | |
3560 | bnad_lock_uninit(struct bnad *bnad) | |
3561 | { | |
3562 | mutex_destroy(&bnad->conf_mutex); | |
3563 | } | |
3564 | ||
3565 | /* PCI Initialization */ | |
3566 | static int | |
3567 | bnad_pci_init(struct bnad *bnad, | |
3568 | struct pci_dev *pdev, bool *using_dac) | |
3569 | { | |
3570 | int err; | |
3571 | ||
3572 | err = pci_enable_device(pdev); | |
3573 | if (err) | |
3574 | return err; | |
3575 | err = pci_request_regions(pdev, BNAD_NAME); | |
3576 | if (err) | |
3577 | goto disable_device; | |
3e548079 | 3578 | if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { |
3db1cd5c | 3579 | *using_dac = true; |
8b230ed8 | 3580 | } else { |
3e548079 RK |
3581 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
3582 | if (err) | |
3583 | goto release_regions; | |
3db1cd5c | 3584 | *using_dac = false; |
8b230ed8 RM |
3585 | } |
3586 | pci_set_master(pdev); | |
3587 | return 0; | |
3588 | ||
3589 | release_regions: | |
3590 | pci_release_regions(pdev); | |
3591 | disable_device: | |
3592 | pci_disable_device(pdev); | |
3593 | ||
3594 | return err; | |
3595 | } | |
3596 | ||
3597 | static void | |
3598 | bnad_pci_uninit(struct pci_dev *pdev) | |
3599 | { | |
3600 | pci_release_regions(pdev); | |
3601 | pci_disable_device(pdev); | |
3602 | } | |
3603 | ||
c4eef189 | 3604 | static int |
8b230ed8 RM |
3605 | bnad_pci_probe(struct pci_dev *pdev, |
3606 | const struct pci_device_id *pcidev_id) | |
3607 | { | |
3caa1e95 | 3608 | bool using_dac; |
0120b99c | 3609 | int err; |
8b230ed8 RM |
3610 | struct bnad *bnad; |
3611 | struct bna *bna; | |
3612 | struct net_device *netdev; | |
3613 | struct bfa_pcidev pcidev_info; | |
3614 | unsigned long flags; | |
3615 | ||
8b230ed8 RM |
3616 | mutex_lock(&bnad_fwimg_mutex); |
3617 | if (!cna_get_firmware_buf(pdev)) { | |
3618 | mutex_unlock(&bnad_fwimg_mutex); | |
ecc46789 | 3619 | dev_err(&pdev->dev, "failed to load firmware image!\n"); |
8b230ed8 RM |
3620 | return -ENODEV; |
3621 | } | |
3622 | mutex_unlock(&bnad_fwimg_mutex); | |
3623 | ||
3624 | /* | |
3625 | * Allocates sizeof(struct net_device + struct bnad) | |
3626 | * bnad = netdev->priv | |
3627 | */ | |
3628 | netdev = alloc_etherdev(sizeof(struct bnad)); | |
3629 | if (!netdev) { | |
8b230ed8 RM |
3630 | err = -ENOMEM; |
3631 | return err; | |
3632 | } | |
3633 | bnad = netdev_priv(netdev); | |
078086f3 | 3634 | bnad_lock_init(bnad); |
285eb9c3 | 3635 | bnad->id = atomic_inc_return(&bna_id) - 1; |
078086f3 RM |
3636 | |
3637 | mutex_lock(&bnad->conf_mutex); | |
8b230ed8 RM |
3638 | /* |
3639 | * PCI initialization | |
0120b99c | 3640 | * Output : using_dac = 1 for 64 bit DMA |
be7fa326 | 3641 | * = 0 for 32 bit DMA |
8b230ed8 | 3642 | */ |
e905ed57 | 3643 | using_dac = false; |
8b230ed8 RM |
3644 | err = bnad_pci_init(bnad, pdev, &using_dac); |
3645 | if (err) | |
44861f44 | 3646 | goto unlock_mutex; |
8b230ed8 | 3647 | |
8b230ed8 RM |
3648 | /* |
3649 | * Initialize bnad structure | |
3650 | * Setup relation between pci_dev & netdev | |
8b230ed8 RM |
3651 | */ |
3652 | err = bnad_init(bnad, pdev, netdev); | |
3653 | if (err) | |
3654 | goto pci_uninit; | |
078086f3 | 3655 | |
8b230ed8 RM |
3656 | /* Initialize netdev structure, set up ethtool ops */ |
3657 | bnad_netdev_init(bnad, using_dac); | |
3658 | ||
815f41e7 RM |
3659 | /* Set link to down state */ |
3660 | netif_carrier_off(netdev); | |
3661 | ||
7afc5dbd KG |
3662 | /* Setup the debugfs node for this bfad */ |
3663 | if (bna_debugfs_enable) | |
3664 | bnad_debugfs_init(bnad); | |
3665 | ||
8b230ed8 | 3666 | /* Get resource requirement form bna */ |
078086f3 | 3667 | spin_lock_irqsave(&bnad->bna_lock, flags); |
8b230ed8 | 3668 | bna_res_req(&bnad->res_info[0]); |
078086f3 | 3669 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
8b230ed8 RM |
3670 | |
3671 | /* Allocate resources from bna */ | |
078086f3 | 3672 | err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX); |
8b230ed8 | 3673 | if (err) |
078086f3 | 3674 | goto drv_uninit; |
8b230ed8 RM |
3675 | |
3676 | bna = &bnad->bna; | |
3677 | ||
3678 | /* Setup pcidev_info for bna_init() */ | |
3679 | pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn); | |
3680 | pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn); | |
3681 | pcidev_info.device_id = bnad->pcidev->device; | |
3682 | pcidev_info.pci_bar_kva = bnad->bar0; | |
3683 | ||
8b230ed8 RM |
3684 | spin_lock_irqsave(&bnad->bna_lock, flags); |
3685 | bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]); | |
8b230ed8 RM |
3686 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
3687 | ||
3688 | bnad->stats.bna_stats = &bna->stats; | |
3689 | ||
078086f3 RM |
3690 | bnad_enable_msix(bnad); |
3691 | err = bnad_mbox_irq_alloc(bnad); | |
3692 | if (err) | |
3693 | goto res_free; | |
3694 | ||
8b230ed8 | 3695 | /* Set up timers */ |
078086f3 | 3696 | setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout, |
ebb56d37 | 3697 | (unsigned long)bnad); |
078086f3 | 3698 | setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check, |
ebb56d37 | 3699 | (unsigned long)bnad); |
078086f3 | 3700 | setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout, |
ebb56d37 | 3701 | (unsigned long)bnad); |
078086f3 | 3702 | setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout, |
ebb56d37 | 3703 | (unsigned long)bnad); |
8b230ed8 | 3704 | |
8b230ed8 RM |
3705 | /* |
3706 | * Start the chip | |
078086f3 RM |
3707 | * If the call back comes with error, we bail out. |
3708 | * This is a catastrophic error. | |
8b230ed8 | 3709 | */ |
078086f3 RM |
3710 | err = bnad_ioceth_enable(bnad); |
3711 | if (err) { | |
ecc46789 | 3712 | dev_err(&pdev->dev, "initialization failed err=%d\n", err); |
078086f3 RM |
3713 | goto probe_success; |
3714 | } | |
3715 | ||
3716 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3717 | if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) || | |
3718 | bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) { | |
3719 | bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1, | |
3720 | bna_attr(bna)->num_rxp - 1); | |
3721 | if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) || | |
3722 | bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) | |
3723 | err = -EIO; | |
3724 | } | |
3caa1e95 RM |
3725 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
3726 | if (err) | |
3727 | goto disable_ioceth; | |
3728 | ||
3729 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
078086f3 RM |
3730 | bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]); |
3731 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3732 | ||
3733 | err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); | |
0caa9aae RM |
3734 | if (err) { |
3735 | err = -EIO; | |
078086f3 | 3736 | goto disable_ioceth; |
0caa9aae | 3737 | } |
078086f3 RM |
3738 | |
3739 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3740 | bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]); | |
3741 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
8b230ed8 RM |
3742 | |
3743 | /* Get the burnt-in mac */ | |
3744 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
d6b30598 | 3745 | bna_enet_perm_mac_get(&bna->enet, bnad->perm_addr); |
8b230ed8 RM |
3746 | bnad_set_netdev_perm_addr(bnad); |
3747 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3748 | ||
0caa9aae RM |
3749 | mutex_unlock(&bnad->conf_mutex); |
3750 | ||
8b230ed8 RM |
3751 | /* Finally, reguister with net_device layer */ |
3752 | err = register_netdev(netdev); | |
3753 | if (err) { | |
ecc46789 | 3754 | dev_err(&pdev->dev, "registering net device failed\n"); |
078086f3 | 3755 | goto probe_uninit; |
8b230ed8 | 3756 | } |
078086f3 | 3757 | set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags); |
8b230ed8 | 3758 | |
0caa9aae RM |
3759 | return 0; |
3760 | ||
078086f3 RM |
3761 | probe_success: |
3762 | mutex_unlock(&bnad->conf_mutex); | |
8b230ed8 RM |
3763 | return 0; |
3764 | ||
078086f3 | 3765 | probe_uninit: |
3fc72370 | 3766 | mutex_lock(&bnad->conf_mutex); |
078086f3 RM |
3767 | bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); |
3768 | disable_ioceth: | |
3769 | bnad_ioceth_disable(bnad); | |
3770 | del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer); | |
3771 | del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer); | |
3772 | del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer); | |
8b230ed8 RM |
3773 | spin_lock_irqsave(&bnad->bna_lock, flags); |
3774 | bna_uninit(bna); | |
3775 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
078086f3 | 3776 | bnad_mbox_irq_free(bnad); |
8b230ed8 | 3777 | bnad_disable_msix(bnad); |
078086f3 RM |
3778 | res_free: |
3779 | bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX); | |
3780 | drv_uninit: | |
7afc5dbd KG |
3781 | /* Remove the debugfs node for this bnad */ |
3782 | kfree(bnad->regdata); | |
3783 | bnad_debugfs_uninit(bnad); | |
078086f3 | 3784 | bnad_uninit(bnad); |
8b230ed8 RM |
3785 | pci_uninit: |
3786 | bnad_pci_uninit(pdev); | |
44861f44 | 3787 | unlock_mutex: |
078086f3 | 3788 | mutex_unlock(&bnad->conf_mutex); |
8b230ed8 | 3789 | bnad_lock_uninit(bnad); |
8b230ed8 RM |
3790 | free_netdev(netdev); |
3791 | return err; | |
3792 | } | |
3793 | ||
c4eef189 | 3794 | static void |
8b230ed8 RM |
3795 | bnad_pci_remove(struct pci_dev *pdev) |
3796 | { | |
3797 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3798 | struct bnad *bnad; | |
3799 | struct bna *bna; | |
3800 | unsigned long flags; | |
3801 | ||
3802 | if (!netdev) | |
3803 | return; | |
3804 | ||
8b230ed8 RM |
3805 | bnad = netdev_priv(netdev); |
3806 | bna = &bnad->bna; | |
3807 | ||
078086f3 RM |
3808 | if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags)) |
3809 | unregister_netdev(netdev); | |
8b230ed8 RM |
3810 | |
3811 | mutex_lock(&bnad->conf_mutex); | |
078086f3 RM |
3812 | bnad_ioceth_disable(bnad); |
3813 | del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer); | |
3814 | del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer); | |
3815 | del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer); | |
8b230ed8 RM |
3816 | spin_lock_irqsave(&bnad->bna_lock, flags); |
3817 | bna_uninit(bna); | |
3818 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
8b230ed8 | 3819 | |
078086f3 RM |
3820 | bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); |
3821 | bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX); | |
3822 | bnad_mbox_irq_free(bnad); | |
8b230ed8 RM |
3823 | bnad_disable_msix(bnad); |
3824 | bnad_pci_uninit(pdev); | |
078086f3 | 3825 | mutex_unlock(&bnad->conf_mutex); |
8b230ed8 | 3826 | bnad_lock_uninit(bnad); |
7afc5dbd KG |
3827 | /* Remove the debugfs node for this bnad */ |
3828 | kfree(bnad->regdata); | |
3829 | bnad_debugfs_uninit(bnad); | |
8b230ed8 RM |
3830 | bnad_uninit(bnad); |
3831 | free_netdev(netdev); | |
3832 | } | |
3833 | ||
9baa3c34 | 3834 | static const struct pci_device_id bnad_pci_id_table[] = { |
8b230ed8 RM |
3835 | { |
3836 | PCI_DEVICE(PCI_VENDOR_ID_BROCADE, | |
3837 | PCI_DEVICE_ID_BROCADE_CT), | |
3838 | .class = PCI_CLASS_NETWORK_ETHERNET << 8, | |
3839 | .class_mask = 0xffff00 | |
586b2816 RM |
3840 | }, |
3841 | { | |
3842 | PCI_DEVICE(PCI_VENDOR_ID_BROCADE, | |
3843 | BFA_PCI_DEVICE_ID_CT2), | |
3844 | .class = PCI_CLASS_NETWORK_ETHERNET << 8, | |
3845 | .class_mask = 0xffff00 | |
3846 | }, | |
3847 | {0, }, | |
8b230ed8 RM |
3848 | }; |
3849 | ||
3850 | MODULE_DEVICE_TABLE(pci, bnad_pci_id_table); | |
3851 | ||
3852 | static struct pci_driver bnad_pci_driver = { | |
3853 | .name = BNAD_NAME, | |
3854 | .id_table = bnad_pci_id_table, | |
3855 | .probe = bnad_pci_probe, | |
c4eef189 | 3856 | .remove = bnad_pci_remove, |
8b230ed8 RM |
3857 | }; |
3858 | ||
3859 | static int __init | |
3860 | bnad_module_init(void) | |
3861 | { | |
3862 | int err; | |
3863 | ||
ecc46789 IV |
3864 | pr_info("bna: QLogic BR-series 10G Ethernet driver - version: %s\n", |
3865 | BNAD_VERSION); | |
8b230ed8 | 3866 | |
8a891429 | 3867 | bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover); |
8b230ed8 RM |
3868 | |
3869 | err = pci_register_driver(&bnad_pci_driver); | |
3870 | if (err < 0) { | |
ecc46789 | 3871 | pr_err("bna: PCI driver registration failed err=%d\n", err); |
8b230ed8 RM |
3872 | return err; |
3873 | } | |
3874 | ||
3875 | return 0; | |
3876 | } | |
3877 | ||
3878 | static void __exit | |
3879 | bnad_module_exit(void) | |
3880 | { | |
3881 | pci_unregister_driver(&bnad_pci_driver); | |
294ca868 | 3882 | release_firmware(bfi_fw); |
8b230ed8 RM |
3883 | } |
3884 | ||
3885 | module_init(bnad_module_init); | |
3886 | module_exit(bnad_module_exit); | |
3887 | ||
3888 | MODULE_AUTHOR("Brocade"); | |
3889 | MODULE_LICENSE("GPL"); | |
2732ba56 | 3890 | MODULE_DESCRIPTION("QLogic BR-series 10G PCIe Ethernet driver"); |
8b230ed8 RM |
3891 | MODULE_VERSION(BNAD_VERSION); |
3892 | MODULE_FIRMWARE(CNA_FW_FILE_CT); | |
1bf9fd70 | 3893 | MODULE_FIRMWARE(CNA_FW_FILE_CT2); |