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Commit | Line | Data |
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89e5785f | 1 | /* |
f75ba50b | 2 | * Cadence MACB/GEM Ethernet Controller driver |
89e5785f HS |
3 | * |
4 | * Copyright (C) 2004-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
c220f8cd | 11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
89e5785f HS |
12 | #include <linux/clk.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/types.h> | |
909a8583 | 17 | #include <linux/circ_buf.h> |
89e5785f HS |
18 | #include <linux/slab.h> |
19 | #include <linux/init.h> | |
60fe716f | 20 | #include <linux/io.h> |
2dbfdbb9 | 21 | #include <linux/gpio.h> |
a6b7a407 | 22 | #include <linux/interrupt.h> |
89e5785f HS |
23 | #include <linux/netdevice.h> |
24 | #include <linux/etherdevice.h> | |
89e5785f | 25 | #include <linux/dma-mapping.h> |
84e0cdb0 | 26 | #include <linux/platform_data/macb.h> |
89e5785f | 27 | #include <linux/platform_device.h> |
6c36a707 | 28 | #include <linux/phy.h> |
b17471f5 | 29 | #include <linux/of.h> |
fb97a846 | 30 | #include <linux/of_device.h> |
148cbb53 | 31 | #include <linux/of_mdio.h> |
fb97a846 | 32 | #include <linux/of_net.h> |
89e5785f | 33 | |
89e5785f HS |
34 | #include "macb.h" |
35 | ||
1b44791a | 36 | #define MACB_RX_BUFFER_SIZE 128 |
1b44791a | 37 | #define RX_BUFFER_MULTIPLE 64 /* bytes */ |
55054a16 HS |
38 | #define RX_RING_SIZE 512 /* must be power of 2 */ |
39 | #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE) | |
89e5785f | 40 | |
55054a16 HS |
41 | #define TX_RING_SIZE 128 /* must be power of 2 */ |
42 | #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE) | |
89e5785f | 43 | |
909a8583 NF |
44 | /* level of occupied TX descriptors under which we wake up TX process */ |
45 | #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4) | |
89e5785f HS |
46 | |
47 | #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ | |
48 | | MACB_BIT(ISR_ROVR)) | |
e86cd53a NF |
49 | #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ |
50 | | MACB_BIT(ISR_RLE) \ | |
51 | | MACB_BIT(TXERR)) | |
52 | #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP)) | |
53 | ||
a4c35ed3 CP |
54 | #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1)) |
55 | #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1)) | |
56 | ||
e86cd53a NF |
57 | /* |
58 | * Graceful stop timeouts in us. We should allow up to | |
59 | * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) | |
60 | */ | |
61 | #define MACB_HALT_TIMEOUT 1230 | |
89e5785f | 62 | |
55054a16 HS |
63 | /* Ring buffer accessors */ |
64 | static unsigned int macb_tx_ring_wrap(unsigned int index) | |
65 | { | |
66 | return index & (TX_RING_SIZE - 1); | |
67 | } | |
68 | ||
02c958dd CP |
69 | static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue, |
70 | unsigned int index) | |
55054a16 | 71 | { |
02c958dd | 72 | return &queue->tx_ring[macb_tx_ring_wrap(index)]; |
55054a16 HS |
73 | } |
74 | ||
02c958dd CP |
75 | static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue, |
76 | unsigned int index) | |
55054a16 | 77 | { |
02c958dd | 78 | return &queue->tx_skb[macb_tx_ring_wrap(index)]; |
55054a16 HS |
79 | } |
80 | ||
02c958dd | 81 | static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index) |
55054a16 HS |
82 | { |
83 | dma_addr_t offset; | |
84 | ||
85 | offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc); | |
86 | ||
02c958dd | 87 | return queue->tx_ring_dma + offset; |
55054a16 HS |
88 | } |
89 | ||
90 | static unsigned int macb_rx_ring_wrap(unsigned int index) | |
91 | { | |
92 | return index & (RX_RING_SIZE - 1); | |
93 | } | |
94 | ||
95 | static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index) | |
96 | { | |
97 | return &bp->rx_ring[macb_rx_ring_wrap(index)]; | |
98 | } | |
99 | ||
100 | static void *macb_rx_buffer(struct macb *bp, unsigned int index) | |
101 | { | |
1b44791a | 102 | return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index); |
55054a16 HS |
103 | } |
104 | ||
314bccc4 | 105 | void macb_set_hwaddr(struct macb *bp) |
89e5785f HS |
106 | { |
107 | u32 bottom; | |
108 | u16 top; | |
109 | ||
110 | bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); | |
f75ba50b | 111 | macb_or_gem_writel(bp, SA1B, bottom); |
89e5785f | 112 | top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); |
f75ba50b | 113 | macb_or_gem_writel(bp, SA1T, top); |
3629a6ce JE |
114 | |
115 | /* Clear unused address register sets */ | |
116 | macb_or_gem_writel(bp, SA2B, 0); | |
117 | macb_or_gem_writel(bp, SA2T, 0); | |
118 | macb_or_gem_writel(bp, SA3B, 0); | |
119 | macb_or_gem_writel(bp, SA3T, 0); | |
120 | macb_or_gem_writel(bp, SA4B, 0); | |
121 | macb_or_gem_writel(bp, SA4T, 0); | |
89e5785f | 122 | } |
314bccc4 | 123 | EXPORT_SYMBOL_GPL(macb_set_hwaddr); |
89e5785f | 124 | |
314bccc4 | 125 | void macb_get_hwaddr(struct macb *bp) |
89e5785f | 126 | { |
d25e78aa | 127 | struct macb_platform_data *pdata; |
89e5785f HS |
128 | u32 bottom; |
129 | u16 top; | |
130 | u8 addr[6]; | |
17b8bb3e JE |
131 | int i; |
132 | ||
c607a0d9 | 133 | pdata = dev_get_platdata(&bp->pdev->dev); |
d25e78aa | 134 | |
17b8bb3e JE |
135 | /* Check all 4 address register for vaild address */ |
136 | for (i = 0; i < 4; i++) { | |
137 | bottom = macb_or_gem_readl(bp, SA1B + i * 8); | |
138 | top = macb_or_gem_readl(bp, SA1T + i * 8); | |
139 | ||
d25e78aa JE |
140 | if (pdata && pdata->rev_eth_addr) { |
141 | addr[5] = bottom & 0xff; | |
142 | addr[4] = (bottom >> 8) & 0xff; | |
143 | addr[3] = (bottom >> 16) & 0xff; | |
144 | addr[2] = (bottom >> 24) & 0xff; | |
145 | addr[1] = top & 0xff; | |
146 | addr[0] = (top & 0xff00) >> 8; | |
147 | } else { | |
148 | addr[0] = bottom & 0xff; | |
149 | addr[1] = (bottom >> 8) & 0xff; | |
150 | addr[2] = (bottom >> 16) & 0xff; | |
151 | addr[3] = (bottom >> 24) & 0xff; | |
152 | addr[4] = top & 0xff; | |
153 | addr[5] = (top >> 8) & 0xff; | |
154 | } | |
17b8bb3e JE |
155 | |
156 | if (is_valid_ether_addr(addr)) { | |
157 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); | |
158 | return; | |
159 | } | |
d1d5741d | 160 | } |
17b8bb3e JE |
161 | |
162 | netdev_info(bp->dev, "invalid hw address, using random\n"); | |
163 | eth_hw_addr_random(bp->dev); | |
89e5785f | 164 | } |
314bccc4 | 165 | EXPORT_SYMBOL_GPL(macb_get_hwaddr); |
89e5785f | 166 | |
6c36a707 | 167 | static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
89e5785f | 168 | { |
6c36a707 | 169 | struct macb *bp = bus->priv; |
89e5785f HS |
170 | int value; |
171 | ||
89e5785f HS |
172 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) |
173 | | MACB_BF(RW, MACB_MAN_READ) | |
6c36a707 R |
174 | | MACB_BF(PHYA, mii_id) |
175 | | MACB_BF(REGA, regnum) | |
89e5785f HS |
176 | | MACB_BF(CODE, MACB_MAN_CODE))); |
177 | ||
6c36a707 R |
178 | /* wait for end of transfer */ |
179 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
180 | cpu_relax(); | |
89e5785f HS |
181 | |
182 | value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); | |
89e5785f HS |
183 | |
184 | return value; | |
185 | } | |
186 | ||
6c36a707 R |
187 | static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
188 | u16 value) | |
89e5785f | 189 | { |
6c36a707 | 190 | struct macb *bp = bus->priv; |
89e5785f HS |
191 | |
192 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) | |
193 | | MACB_BF(RW, MACB_MAN_WRITE) | |
6c36a707 R |
194 | | MACB_BF(PHYA, mii_id) |
195 | | MACB_BF(REGA, regnum) | |
89e5785f | 196 | | MACB_BF(CODE, MACB_MAN_CODE) |
6c36a707 | 197 | | MACB_BF(DATA, value))); |
89e5785f | 198 | |
6c36a707 R |
199 | /* wait for end of transfer */ |
200 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
201 | cpu_relax(); | |
202 | ||
203 | return 0; | |
204 | } | |
89e5785f | 205 | |
e1824dfe SB |
206 | /** |
207 | * macb_set_tx_clk() - Set a clock to a new frequency | |
208 | * @clk Pointer to the clock to change | |
209 | * @rate New frequency in Hz | |
210 | * @dev Pointer to the struct net_device | |
211 | */ | |
212 | static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) | |
213 | { | |
214 | long ferr, rate, rate_rounded; | |
215 | ||
216 | switch (speed) { | |
217 | case SPEED_10: | |
218 | rate = 2500000; | |
219 | break; | |
220 | case SPEED_100: | |
221 | rate = 25000000; | |
222 | break; | |
223 | case SPEED_1000: | |
224 | rate = 125000000; | |
225 | break; | |
226 | default: | |
9319e47c | 227 | return; |
e1824dfe SB |
228 | } |
229 | ||
230 | rate_rounded = clk_round_rate(clk, rate); | |
231 | if (rate_rounded < 0) | |
232 | return; | |
233 | ||
234 | /* RGMII allows 50 ppm frequency error. Test and warn if this limit | |
235 | * is not satisfied. | |
236 | */ | |
237 | ferr = abs(rate_rounded - rate); | |
238 | ferr = DIV_ROUND_UP(ferr, rate / 100000); | |
239 | if (ferr > 5) | |
240 | netdev_warn(dev, "unable to generate target frequency: %ld Hz\n", | |
241 | rate); | |
242 | ||
243 | if (clk_set_rate(clk, rate_rounded)) | |
244 | netdev_err(dev, "adjusting tx_clk failed.\n"); | |
245 | } | |
246 | ||
6c36a707 | 247 | static void macb_handle_link_change(struct net_device *dev) |
89e5785f | 248 | { |
6c36a707 R |
249 | struct macb *bp = netdev_priv(dev); |
250 | struct phy_device *phydev = bp->phy_dev; | |
251 | unsigned long flags; | |
89e5785f | 252 | |
6c36a707 | 253 | int status_change = 0; |
89e5785f | 254 | |
6c36a707 R |
255 | spin_lock_irqsave(&bp->lock, flags); |
256 | ||
257 | if (phydev->link) { | |
258 | if ((bp->speed != phydev->speed) || | |
259 | (bp->duplex != phydev->duplex)) { | |
260 | u32 reg; | |
261 | ||
262 | reg = macb_readl(bp, NCFGR); | |
263 | reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); | |
140b7552 PV |
264 | if (macb_is_gem(bp)) |
265 | reg &= ~GEM_BIT(GBE); | |
6c36a707 R |
266 | |
267 | if (phydev->duplex) | |
268 | reg |= MACB_BIT(FD); | |
179956f4 | 269 | if (phydev->speed == SPEED_100) |
6c36a707 | 270 | reg |= MACB_BIT(SPD); |
e175587f NF |
271 | if (phydev->speed == SPEED_1000 && |
272 | bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) | |
140b7552 | 273 | reg |= GEM_BIT(GBE); |
6c36a707 | 274 | |
140b7552 | 275 | macb_or_gem_writel(bp, NCFGR, reg); |
6c36a707 R |
276 | |
277 | bp->speed = phydev->speed; | |
278 | bp->duplex = phydev->duplex; | |
279 | status_change = 1; | |
280 | } | |
89e5785f HS |
281 | } |
282 | ||
6c36a707 | 283 | if (phydev->link != bp->link) { |
c8f15686 | 284 | if (!phydev->link) { |
6c36a707 R |
285 | bp->speed = 0; |
286 | bp->duplex = -1; | |
287 | } | |
288 | bp->link = phydev->link; | |
89e5785f | 289 | |
6c36a707 R |
290 | status_change = 1; |
291 | } | |
89e5785f | 292 | |
6c36a707 R |
293 | spin_unlock_irqrestore(&bp->lock, flags); |
294 | ||
e1824dfe SB |
295 | if (!IS_ERR(bp->tx_clk)) |
296 | macb_set_tx_clk(bp->tx_clk, phydev->speed, dev); | |
297 | ||
6c36a707 | 298 | if (status_change) { |
03fc4721 NF |
299 | if (phydev->link) { |
300 | netif_carrier_on(dev); | |
c220f8cd JI |
301 | netdev_info(dev, "link up (%d/%s)\n", |
302 | phydev->speed, | |
303 | phydev->duplex == DUPLEX_FULL ? | |
304 | "Full" : "Half"); | |
03fc4721 NF |
305 | } else { |
306 | netif_carrier_off(dev); | |
c220f8cd | 307 | netdev_info(dev, "link down\n"); |
03fc4721 | 308 | } |
6c36a707 | 309 | } |
89e5785f HS |
310 | } |
311 | ||
6c36a707 R |
312 | /* based on au1000_eth. c*/ |
313 | static int macb_mii_probe(struct net_device *dev) | |
89e5785f | 314 | { |
6c36a707 | 315 | struct macb *bp = netdev_priv(dev); |
2dbfdbb9 | 316 | struct macb_platform_data *pdata; |
7455a76f | 317 | struct phy_device *phydev; |
2dbfdbb9 | 318 | int phy_irq; |
7455a76f | 319 | int ret; |
6c36a707 | 320 | |
7455a76f | 321 | phydev = phy_find_first(bp->mii_bus); |
6c36a707 | 322 | if (!phydev) { |
c220f8cd | 323 | netdev_err(dev, "no PHY found\n"); |
7daa78e3 | 324 | return -ENXIO; |
6c36a707 R |
325 | } |
326 | ||
2dbfdbb9 JE |
327 | pdata = dev_get_platdata(&bp->pdev->dev); |
328 | if (pdata && gpio_is_valid(pdata->phy_irq_pin)) { | |
329 | ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int"); | |
330 | if (!ret) { | |
331 | phy_irq = gpio_to_irq(pdata->phy_irq_pin); | |
332 | phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq; | |
333 | } | |
334 | } | |
6c36a707 R |
335 | |
336 | /* attach the mac to the phy */ | |
f9a8f83b | 337 | ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, |
fb97a846 | 338 | bp->phy_interface); |
7455a76f | 339 | if (ret) { |
c220f8cd | 340 | netdev_err(dev, "Could not attach to PHY\n"); |
7455a76f | 341 | return ret; |
6c36a707 R |
342 | } |
343 | ||
344 | /* mask with MAC supported features */ | |
e175587f | 345 | if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) |
140b7552 PV |
346 | phydev->supported &= PHY_GBIT_FEATURES; |
347 | else | |
348 | phydev->supported &= PHY_BASIC_FEATURES; | |
6c36a707 R |
349 | |
350 | phydev->advertising = phydev->supported; | |
351 | ||
352 | bp->link = 0; | |
353 | bp->speed = 0; | |
354 | bp->duplex = -1; | |
355 | bp->phy_dev = phydev; | |
356 | ||
357 | return 0; | |
89e5785f HS |
358 | } |
359 | ||
0005f541 | 360 | int macb_mii_init(struct macb *bp) |
89e5785f | 361 | { |
84e0cdb0 | 362 | struct macb_platform_data *pdata; |
148cbb53 | 363 | struct device_node *np; |
6c36a707 | 364 | int err = -ENXIO, i; |
89e5785f | 365 | |
3dbda77e | 366 | /* Enable management port */ |
6c36a707 | 367 | macb_writel(bp, NCR, MACB_BIT(MPE)); |
89e5785f | 368 | |
298cf9be LB |
369 | bp->mii_bus = mdiobus_alloc(); |
370 | if (bp->mii_bus == NULL) { | |
371 | err = -ENOMEM; | |
372 | goto err_out; | |
373 | } | |
374 | ||
375 | bp->mii_bus->name = "MACB_mii_bus"; | |
376 | bp->mii_bus->read = &macb_mdio_read; | |
377 | bp->mii_bus->write = &macb_mdio_write; | |
98d5e57e FF |
378 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
379 | bp->pdev->name, bp->pdev->id); | |
298cf9be LB |
380 | bp->mii_bus->priv = bp; |
381 | bp->mii_bus->parent = &bp->dev->dev; | |
c607a0d9 | 382 | pdata = dev_get_platdata(&bp->pdev->dev); |
89e5785f | 383 | |
298cf9be LB |
384 | bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
385 | if (!bp->mii_bus->irq) { | |
6c36a707 | 386 | err = -ENOMEM; |
298cf9be | 387 | goto err_out_free_mdiobus; |
89e5785f HS |
388 | } |
389 | ||
91523947 | 390 | dev_set_drvdata(&bp->dev->dev, bp->mii_bus); |
89e5785f | 391 | |
148cbb53 BB |
392 | np = bp->pdev->dev.of_node; |
393 | if (np) { | |
394 | /* try dt phy registration */ | |
395 | err = of_mdiobus_register(bp->mii_bus, np); | |
396 | ||
397 | /* fallback to standard phy registration if no phy were | |
398 | found during dt phy registration */ | |
399 | if (!err && !phy_find_first(bp->mii_bus)) { | |
400 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
401 | struct phy_device *phydev; | |
402 | ||
403 | phydev = mdiobus_scan(bp->mii_bus, i); | |
404 | if (IS_ERR(phydev)) { | |
405 | err = PTR_ERR(phydev); | |
406 | break; | |
407 | } | |
408 | } | |
409 | ||
410 | if (err) | |
411 | goto err_out_unregister_bus; | |
412 | } | |
413 | } else { | |
414 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
415 | bp->mii_bus->irq[i] = PHY_POLL; | |
416 | ||
417 | if (pdata) | |
418 | bp->mii_bus->phy_mask = pdata->phy_mask; | |
419 | ||
420 | err = mdiobus_register(bp->mii_bus); | |
421 | } | |
422 | ||
423 | if (err) | |
6c36a707 | 424 | goto err_out_free_mdio_irq; |
89e5785f | 425 | |
7daa78e3 BB |
426 | err = macb_mii_probe(bp->dev); |
427 | if (err) | |
6c36a707 | 428 | goto err_out_unregister_bus; |
89e5785f | 429 | |
6c36a707 | 430 | return 0; |
89e5785f | 431 | |
6c36a707 | 432 | err_out_unregister_bus: |
298cf9be | 433 | mdiobus_unregister(bp->mii_bus); |
6c36a707 | 434 | err_out_free_mdio_irq: |
298cf9be LB |
435 | kfree(bp->mii_bus->irq); |
436 | err_out_free_mdiobus: | |
437 | mdiobus_free(bp->mii_bus); | |
6c36a707 R |
438 | err_out: |
439 | return err; | |
89e5785f | 440 | } |
0005f541 | 441 | EXPORT_SYMBOL_GPL(macb_mii_init); |
89e5785f HS |
442 | |
443 | static void macb_update_stats(struct macb *bp) | |
444 | { | |
445 | u32 __iomem *reg = bp->regs + MACB_PFR; | |
a494ed8e JI |
446 | u32 *p = &bp->hw_stats.macb.rx_pause_frames; |
447 | u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; | |
89e5785f HS |
448 | |
449 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | |
450 | ||
451 | for(; p < end; p++, reg++) | |
0f0d84e5 | 452 | *p += __raw_readl(reg); |
89e5785f HS |
453 | } |
454 | ||
e86cd53a | 455 | static int macb_halt_tx(struct macb *bp) |
89e5785f | 456 | { |
e86cd53a NF |
457 | unsigned long halt_time, timeout; |
458 | u32 status; | |
89e5785f | 459 | |
e86cd53a | 460 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT)); |
89e5785f | 461 | |
e86cd53a NF |
462 | timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT); |
463 | do { | |
464 | halt_time = jiffies; | |
465 | status = macb_readl(bp, TSR); | |
466 | if (!(status & MACB_BIT(TGO))) | |
467 | return 0; | |
89e5785f | 468 | |
e86cd53a NF |
469 | usleep_range(10, 250); |
470 | } while (time_before(halt_time, timeout)); | |
bdcba151 | 471 | |
e86cd53a NF |
472 | return -ETIMEDOUT; |
473 | } | |
39eddb4c | 474 | |
a4c35ed3 CP |
475 | static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb) |
476 | { | |
477 | if (tx_skb->mapping) { | |
478 | if (tx_skb->mapped_as_page) | |
479 | dma_unmap_page(&bp->pdev->dev, tx_skb->mapping, | |
480 | tx_skb->size, DMA_TO_DEVICE); | |
481 | else | |
482 | dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, | |
483 | tx_skb->size, DMA_TO_DEVICE); | |
484 | tx_skb->mapping = 0; | |
485 | } | |
486 | ||
487 | if (tx_skb->skb) { | |
488 | dev_kfree_skb_any(tx_skb->skb); | |
489 | tx_skb->skb = NULL; | |
490 | } | |
491 | } | |
492 | ||
e86cd53a NF |
493 | static void macb_tx_error_task(struct work_struct *work) |
494 | { | |
02c958dd CP |
495 | struct macb_queue *queue = container_of(work, struct macb_queue, |
496 | tx_error_task); | |
497 | struct macb *bp = queue->bp; | |
e86cd53a | 498 | struct macb_tx_skb *tx_skb; |
02c958dd | 499 | struct macb_dma_desc *desc; |
e86cd53a NF |
500 | struct sk_buff *skb; |
501 | unsigned int tail; | |
02c958dd CP |
502 | unsigned long flags; |
503 | ||
504 | netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n", | |
505 | (unsigned int)(queue - bp->queues), | |
506 | queue->tx_tail, queue->tx_head); | |
bdcba151 | 507 | |
02c958dd CP |
508 | /* Prevent the queue IRQ handlers from running: each of them may call |
509 | * macb_tx_interrupt(), which in turn may call netif_wake_subqueue(). | |
510 | * As explained below, we have to halt the transmission before updating | |
511 | * TBQP registers so we call netif_tx_stop_all_queues() to notify the | |
512 | * network engine about the macb/gem being halted. | |
513 | */ | |
514 | spin_lock_irqsave(&bp->lock, flags); | |
bdcba151 | 515 | |
e86cd53a | 516 | /* Make sure nobody is trying to queue up new packets */ |
02c958dd | 517 | netif_tx_stop_all_queues(bp->dev); |
d3e61457 | 518 | |
e86cd53a NF |
519 | /* |
520 | * Stop transmission now | |
521 | * (in case we have just queued new packets) | |
02c958dd | 522 | * macb/gem must be halted to write TBQP register |
e86cd53a NF |
523 | */ |
524 | if (macb_halt_tx(bp)) | |
525 | /* Just complain for now, reinitializing TX path can be good */ | |
526 | netdev_err(bp->dev, "BUG: halt tx timed out\n"); | |
bdcba151 | 527 | |
e86cd53a NF |
528 | /* |
529 | * Treat frames in TX queue including the ones that caused the error. | |
530 | * Free transmit buffers in upper layer. | |
531 | */ | |
02c958dd CP |
532 | for (tail = queue->tx_tail; tail != queue->tx_head; tail++) { |
533 | u32 ctrl; | |
55054a16 | 534 | |
02c958dd | 535 | desc = macb_tx_desc(queue, tail); |
e86cd53a | 536 | ctrl = desc->ctrl; |
02c958dd | 537 | tx_skb = macb_tx_skb(queue, tail); |
e86cd53a | 538 | skb = tx_skb->skb; |
bdcba151 | 539 | |
e86cd53a | 540 | if (ctrl & MACB_BIT(TX_USED)) { |
a4c35ed3 CP |
541 | /* skb is set for the last buffer of the frame */ |
542 | while (!skb) { | |
543 | macb_tx_unmap(bp, tx_skb); | |
544 | tail++; | |
02c958dd | 545 | tx_skb = macb_tx_skb(queue, tail); |
a4c35ed3 CP |
546 | skb = tx_skb->skb; |
547 | } | |
548 | ||
549 | /* ctrl still refers to the first buffer descriptor | |
550 | * since it's the only one written back by the hardware | |
551 | */ | |
552 | if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) { | |
553 | netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n", | |
554 | macb_tx_ring_wrap(tail), skb->data); | |
555 | bp->stats.tx_packets++; | |
556 | bp->stats.tx_bytes += skb->len; | |
557 | } | |
e86cd53a NF |
558 | } else { |
559 | /* | |
560 | * "Buffers exhausted mid-frame" errors may only happen | |
561 | * if the driver is buggy, so complain loudly about those. | |
562 | * Statistics are updated by hardware. | |
563 | */ | |
564 | if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) | |
565 | netdev_err(bp->dev, | |
566 | "BUG: TX buffers exhausted mid-frame\n"); | |
39eddb4c | 567 | |
e86cd53a NF |
568 | desc->ctrl = ctrl | MACB_BIT(TX_USED); |
569 | } | |
570 | ||
a4c35ed3 | 571 | macb_tx_unmap(bp, tx_skb); |
89e5785f HS |
572 | } |
573 | ||
02c958dd CP |
574 | /* Set end of TX queue */ |
575 | desc = macb_tx_desc(queue, 0); | |
576 | desc->addr = 0; | |
577 | desc->ctrl = MACB_BIT(TX_USED); | |
578 | ||
e86cd53a NF |
579 | /* Make descriptor updates visible to hardware */ |
580 | wmb(); | |
581 | ||
582 | /* Reinitialize the TX desc queue */ | |
02c958dd | 583 | queue_writel(queue, TBQP, queue->tx_ring_dma); |
e86cd53a | 584 | /* Make TX ring reflect state of hardware */ |
02c958dd CP |
585 | queue->tx_head = 0; |
586 | queue->tx_tail = 0; | |
e86cd53a NF |
587 | |
588 | /* Housework before enabling TX IRQ */ | |
589 | macb_writel(bp, TSR, macb_readl(bp, TSR)); | |
02c958dd CP |
590 | queue_writel(queue, IER, MACB_TX_INT_FLAGS); |
591 | ||
592 | /* Now we are ready to start transmission again */ | |
593 | netif_tx_start_all_queues(bp->dev); | |
594 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); | |
595 | ||
596 | spin_unlock_irqrestore(&bp->lock, flags); | |
e86cd53a NF |
597 | } |
598 | ||
02c958dd | 599 | static void macb_tx_interrupt(struct macb_queue *queue) |
e86cd53a NF |
600 | { |
601 | unsigned int tail; | |
602 | unsigned int head; | |
603 | u32 status; | |
02c958dd CP |
604 | struct macb *bp = queue->bp; |
605 | u16 queue_index = queue - bp->queues; | |
e86cd53a NF |
606 | |
607 | status = macb_readl(bp, TSR); | |
608 | macb_writel(bp, TSR, status); | |
609 | ||
581df9e1 | 610 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
02c958dd | 611 | queue_writel(queue, ISR, MACB_BIT(TCOMP)); |
749a2b66 | 612 | |
e86cd53a NF |
613 | netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", |
614 | (unsigned long)status); | |
89e5785f | 615 | |
02c958dd CP |
616 | head = queue->tx_head; |
617 | for (tail = queue->tx_tail; tail != head; tail++) { | |
55054a16 HS |
618 | struct macb_tx_skb *tx_skb; |
619 | struct sk_buff *skb; | |
620 | struct macb_dma_desc *desc; | |
621 | u32 ctrl; | |
89e5785f | 622 | |
02c958dd | 623 | desc = macb_tx_desc(queue, tail); |
89e5785f | 624 | |
03dbe05f | 625 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 626 | rmb(); |
03dbe05f | 627 | |
55054a16 | 628 | ctrl = desc->ctrl; |
89e5785f | 629 | |
a4c35ed3 CP |
630 | /* TX_USED bit is only set by hardware on the very first buffer |
631 | * descriptor of the transmitted frame. | |
632 | */ | |
55054a16 | 633 | if (!(ctrl & MACB_BIT(TX_USED))) |
89e5785f HS |
634 | break; |
635 | ||
a4c35ed3 CP |
636 | /* Process all buffers of the current transmitted frame */ |
637 | for (;; tail++) { | |
02c958dd | 638 | tx_skb = macb_tx_skb(queue, tail); |
a4c35ed3 CP |
639 | skb = tx_skb->skb; |
640 | ||
641 | /* First, update TX stats if needed */ | |
642 | if (skb) { | |
643 | netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", | |
644 | macb_tx_ring_wrap(tail), skb->data); | |
645 | bp->stats.tx_packets++; | |
646 | bp->stats.tx_bytes += skb->len; | |
647 | } | |
55054a16 | 648 | |
a4c35ed3 CP |
649 | /* Now we can safely release resources */ |
650 | macb_tx_unmap(bp, tx_skb); | |
651 | ||
652 | /* skb is set only for the last buffer of the frame. | |
653 | * WARNING: at this point skb has been freed by | |
654 | * macb_tx_unmap(). | |
655 | */ | |
656 | if (skb) | |
657 | break; | |
658 | } | |
89e5785f HS |
659 | } |
660 | ||
02c958dd CP |
661 | queue->tx_tail = tail; |
662 | if (__netif_subqueue_stopped(bp->dev, queue_index) && | |
663 | CIRC_CNT(queue->tx_head, queue->tx_tail, | |
664 | TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH) | |
665 | netif_wake_subqueue(bp->dev, queue_index); | |
89e5785f HS |
666 | } |
667 | ||
4df95131 NF |
668 | static void gem_rx_refill(struct macb *bp) |
669 | { | |
670 | unsigned int entry; | |
671 | struct sk_buff *skb; | |
4df95131 NF |
672 | dma_addr_t paddr; |
673 | ||
674 | while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) { | |
4df95131 | 675 | entry = macb_rx_ring_wrap(bp->rx_prepared_head); |
4df95131 NF |
676 | |
677 | /* Make hw descriptor updates visible to CPU */ | |
678 | rmb(); | |
679 | ||
4df95131 NF |
680 | bp->rx_prepared_head++; |
681 | ||
4df95131 NF |
682 | if (bp->rx_skbuff[entry] == NULL) { |
683 | /* allocate sk_buff for this free entry in ring */ | |
684 | skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size); | |
685 | if (unlikely(skb == NULL)) { | |
686 | netdev_err(bp->dev, | |
687 | "Unable to allocate sk_buff\n"); | |
688 | break; | |
689 | } | |
4df95131 NF |
690 | |
691 | /* now fill corresponding descriptor entry */ | |
692 | paddr = dma_map_single(&bp->pdev->dev, skb->data, | |
693 | bp->rx_buffer_size, DMA_FROM_DEVICE); | |
92030908 SB |
694 | if (dma_mapping_error(&bp->pdev->dev, paddr)) { |
695 | dev_kfree_skb(skb); | |
696 | break; | |
697 | } | |
698 | ||
699 | bp->rx_skbuff[entry] = skb; | |
4df95131 NF |
700 | |
701 | if (entry == RX_RING_SIZE - 1) | |
702 | paddr |= MACB_BIT(RX_WRAP); | |
703 | bp->rx_ring[entry].addr = paddr; | |
704 | bp->rx_ring[entry].ctrl = 0; | |
705 | ||
706 | /* properly align Ethernet header */ | |
707 | skb_reserve(skb, NET_IP_ALIGN); | |
708 | } | |
709 | } | |
710 | ||
711 | /* Make descriptor updates visible to hardware */ | |
712 | wmb(); | |
713 | ||
714 | netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n", | |
715 | bp->rx_prepared_head, bp->rx_tail); | |
716 | } | |
717 | ||
718 | /* Mark DMA descriptors from begin up to and not including end as unused */ | |
719 | static void discard_partial_frame(struct macb *bp, unsigned int begin, | |
720 | unsigned int end) | |
721 | { | |
722 | unsigned int frag; | |
723 | ||
724 | for (frag = begin; frag != end; frag++) { | |
725 | struct macb_dma_desc *desc = macb_rx_desc(bp, frag); | |
726 | desc->addr &= ~MACB_BIT(RX_USED); | |
727 | } | |
728 | ||
729 | /* Make descriptor updates visible to hardware */ | |
730 | wmb(); | |
731 | ||
732 | /* | |
733 | * When this happens, the hardware stats registers for | |
734 | * whatever caused this is updated, so we don't have to record | |
735 | * anything. | |
736 | */ | |
737 | } | |
738 | ||
739 | static int gem_rx(struct macb *bp, int budget) | |
740 | { | |
741 | unsigned int len; | |
742 | unsigned int entry; | |
743 | struct sk_buff *skb; | |
744 | struct macb_dma_desc *desc; | |
745 | int count = 0; | |
746 | ||
747 | while (count < budget) { | |
748 | u32 addr, ctrl; | |
749 | ||
750 | entry = macb_rx_ring_wrap(bp->rx_tail); | |
751 | desc = &bp->rx_ring[entry]; | |
752 | ||
753 | /* Make hw descriptor updates visible to CPU */ | |
754 | rmb(); | |
755 | ||
756 | addr = desc->addr; | |
757 | ctrl = desc->ctrl; | |
758 | ||
759 | if (!(addr & MACB_BIT(RX_USED))) | |
760 | break; | |
761 | ||
4df95131 NF |
762 | bp->rx_tail++; |
763 | count++; | |
764 | ||
765 | if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) { | |
766 | netdev_err(bp->dev, | |
767 | "not whole frame pointed by descriptor\n"); | |
768 | bp->stats.rx_dropped++; | |
769 | break; | |
770 | } | |
771 | skb = bp->rx_skbuff[entry]; | |
772 | if (unlikely(!skb)) { | |
773 | netdev_err(bp->dev, | |
774 | "inconsistent Rx descriptor chain\n"); | |
775 | bp->stats.rx_dropped++; | |
776 | break; | |
777 | } | |
778 | /* now everything is ready for receiving packet */ | |
779 | bp->rx_skbuff[entry] = NULL; | |
780 | len = MACB_BFEXT(RX_FRMLEN, ctrl); | |
781 | ||
782 | netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len); | |
783 | ||
784 | skb_put(skb, len); | |
785 | addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr)); | |
786 | dma_unmap_single(&bp->pdev->dev, addr, | |
48330e08 | 787 | bp->rx_buffer_size, DMA_FROM_DEVICE); |
4df95131 NF |
788 | |
789 | skb->protocol = eth_type_trans(skb, bp->dev); | |
790 | skb_checksum_none_assert(skb); | |
924ec53c CP |
791 | if (bp->dev->features & NETIF_F_RXCSUM && |
792 | !(bp->dev->flags & IFF_PROMISC) && | |
793 | GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK) | |
794 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4df95131 NF |
795 | |
796 | bp->stats.rx_packets++; | |
797 | bp->stats.rx_bytes += skb->len; | |
798 | ||
799 | #if defined(DEBUG) && defined(VERBOSE_DEBUG) | |
800 | netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", | |
801 | skb->len, skb->csum); | |
802 | print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1, | |
51f83014 | 803 | skb_mac_header(skb), 16, true); |
4df95131 NF |
804 | print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1, |
805 | skb->data, 32, true); | |
806 | #endif | |
807 | ||
808 | netif_receive_skb(skb); | |
809 | } | |
810 | ||
811 | gem_rx_refill(bp); | |
812 | ||
813 | return count; | |
814 | } | |
815 | ||
89e5785f HS |
816 | static int macb_rx_frame(struct macb *bp, unsigned int first_frag, |
817 | unsigned int last_frag) | |
818 | { | |
819 | unsigned int len; | |
820 | unsigned int frag; | |
29bc2e1e | 821 | unsigned int offset; |
89e5785f | 822 | struct sk_buff *skb; |
55054a16 | 823 | struct macb_dma_desc *desc; |
89e5785f | 824 | |
55054a16 HS |
825 | desc = macb_rx_desc(bp, last_frag); |
826 | len = MACB_BFEXT(RX_FRMLEN, desc->ctrl); | |
89e5785f | 827 | |
a268adb1 | 828 | netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", |
55054a16 HS |
829 | macb_rx_ring_wrap(first_frag), |
830 | macb_rx_ring_wrap(last_frag), len); | |
89e5785f | 831 | |
29bc2e1e HS |
832 | /* |
833 | * The ethernet header starts NET_IP_ALIGN bytes into the | |
834 | * first buffer. Since the header is 14 bytes, this makes the | |
835 | * payload word-aligned. | |
836 | * | |
837 | * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy | |
838 | * the two padding bytes into the skb so that we avoid hitting | |
839 | * the slowpath in memcpy(), and pull them off afterwards. | |
840 | */ | |
841 | skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN); | |
89e5785f HS |
842 | if (!skb) { |
843 | bp->stats.rx_dropped++; | |
55054a16 HS |
844 | for (frag = first_frag; ; frag++) { |
845 | desc = macb_rx_desc(bp, frag); | |
846 | desc->addr &= ~MACB_BIT(RX_USED); | |
89e5785f HS |
847 | if (frag == last_frag) |
848 | break; | |
849 | } | |
03dbe05f HS |
850 | |
851 | /* Make descriptor updates visible to hardware */ | |
89e5785f | 852 | wmb(); |
03dbe05f | 853 | |
89e5785f HS |
854 | return 1; |
855 | } | |
856 | ||
29bc2e1e HS |
857 | offset = 0; |
858 | len += NET_IP_ALIGN; | |
bc8acf2c | 859 | skb_checksum_none_assert(skb); |
89e5785f HS |
860 | skb_put(skb, len); |
861 | ||
55054a16 | 862 | for (frag = first_frag; ; frag++) { |
1b44791a | 863 | unsigned int frag_len = bp->rx_buffer_size; |
89e5785f HS |
864 | |
865 | if (offset + frag_len > len) { | |
866 | BUG_ON(frag != last_frag); | |
867 | frag_len = len - offset; | |
868 | } | |
27d7ff46 | 869 | skb_copy_to_linear_data_offset(skb, offset, |
55054a16 | 870 | macb_rx_buffer(bp, frag), frag_len); |
1b44791a | 871 | offset += bp->rx_buffer_size; |
55054a16 HS |
872 | desc = macb_rx_desc(bp, frag); |
873 | desc->addr &= ~MACB_BIT(RX_USED); | |
89e5785f HS |
874 | |
875 | if (frag == last_frag) | |
876 | break; | |
877 | } | |
878 | ||
03dbe05f HS |
879 | /* Make descriptor updates visible to hardware */ |
880 | wmb(); | |
881 | ||
29bc2e1e | 882 | __skb_pull(skb, NET_IP_ALIGN); |
89e5785f HS |
883 | skb->protocol = eth_type_trans(skb, bp->dev); |
884 | ||
885 | bp->stats.rx_packets++; | |
29bc2e1e | 886 | bp->stats.rx_bytes += skb->len; |
a268adb1 | 887 | netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", |
c220f8cd | 888 | skb->len, skb->csum); |
89e5785f HS |
889 | netif_receive_skb(skb); |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
89e5785f HS |
894 | static int macb_rx(struct macb *bp, int budget) |
895 | { | |
896 | int received = 0; | |
55054a16 | 897 | unsigned int tail; |
89e5785f HS |
898 | int first_frag = -1; |
899 | ||
55054a16 HS |
900 | for (tail = bp->rx_tail; budget > 0; tail++) { |
901 | struct macb_dma_desc *desc = macb_rx_desc(bp, tail); | |
89e5785f HS |
902 | u32 addr, ctrl; |
903 | ||
03dbe05f | 904 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 905 | rmb(); |
03dbe05f | 906 | |
55054a16 HS |
907 | addr = desc->addr; |
908 | ctrl = desc->ctrl; | |
89e5785f HS |
909 | |
910 | if (!(addr & MACB_BIT(RX_USED))) | |
911 | break; | |
912 | ||
913 | if (ctrl & MACB_BIT(RX_SOF)) { | |
914 | if (first_frag != -1) | |
915 | discard_partial_frame(bp, first_frag, tail); | |
916 | first_frag = tail; | |
917 | } | |
918 | ||
919 | if (ctrl & MACB_BIT(RX_EOF)) { | |
920 | int dropped; | |
921 | BUG_ON(first_frag == -1); | |
922 | ||
923 | dropped = macb_rx_frame(bp, first_frag, tail); | |
924 | first_frag = -1; | |
925 | if (!dropped) { | |
926 | received++; | |
927 | budget--; | |
928 | } | |
929 | } | |
930 | } | |
931 | ||
932 | if (first_frag != -1) | |
933 | bp->rx_tail = first_frag; | |
934 | else | |
935 | bp->rx_tail = tail; | |
936 | ||
937 | return received; | |
938 | } | |
939 | ||
bea3348e | 940 | static int macb_poll(struct napi_struct *napi, int budget) |
89e5785f | 941 | { |
bea3348e | 942 | struct macb *bp = container_of(napi, struct macb, napi); |
bea3348e | 943 | int work_done; |
89e5785f HS |
944 | u32 status; |
945 | ||
946 | status = macb_readl(bp, RSR); | |
947 | macb_writel(bp, RSR, status); | |
948 | ||
bea3348e | 949 | work_done = 0; |
89e5785f | 950 | |
a268adb1 | 951 | netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n", |
c220f8cd | 952 | (unsigned long)status, budget); |
89e5785f | 953 | |
4df95131 | 954 | work_done = bp->macbgem_ops.mog_rx(bp, budget); |
b336369c | 955 | if (work_done < budget) { |
288379f0 | 956 | napi_complete(napi); |
89e5785f | 957 | |
8770e91a NF |
958 | /* Packets received while interrupts were disabled */ |
959 | status = macb_readl(bp, RSR); | |
504ad98d | 960 | if (status) { |
02f7a34f SB |
961 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
962 | macb_writel(bp, ISR, MACB_BIT(RCOMP)); | |
8770e91a | 963 | napi_reschedule(napi); |
02f7a34f SB |
964 | } else { |
965 | macb_writel(bp, IER, MACB_RX_INT_FLAGS); | |
966 | } | |
b336369c | 967 | } |
89e5785f HS |
968 | |
969 | /* TODO: Handle errors */ | |
970 | ||
bea3348e | 971 | return work_done; |
89e5785f HS |
972 | } |
973 | ||
974 | static irqreturn_t macb_interrupt(int irq, void *dev_id) | |
975 | { | |
02c958dd CP |
976 | struct macb_queue *queue = dev_id; |
977 | struct macb *bp = queue->bp; | |
978 | struct net_device *dev = bp->dev; | |
89e5785f HS |
979 | u32 status; |
980 | ||
02c958dd | 981 | status = queue_readl(queue, ISR); |
89e5785f HS |
982 | |
983 | if (unlikely(!status)) | |
984 | return IRQ_NONE; | |
985 | ||
986 | spin_lock(&bp->lock); | |
987 | ||
988 | while (status) { | |
89e5785f HS |
989 | /* close possible race with dev_close */ |
990 | if (unlikely(!netif_running(dev))) { | |
02c958dd | 991 | queue_writel(queue, IDR, -1); |
89e5785f HS |
992 | break; |
993 | } | |
994 | ||
02c958dd CP |
995 | netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n", |
996 | (unsigned int)(queue - bp->queues), | |
997 | (unsigned long)status); | |
a268adb1 | 998 | |
89e5785f | 999 | if (status & MACB_RX_INT_FLAGS) { |
b336369c JH |
1000 | /* |
1001 | * There's no point taking any more interrupts | |
1002 | * until we have processed the buffers. The | |
1003 | * scheduling call may fail if the poll routine | |
1004 | * is already scheduled, so disable interrupts | |
1005 | * now. | |
1006 | */ | |
02c958dd | 1007 | queue_writel(queue, IDR, MACB_RX_INT_FLAGS); |
581df9e1 | 1008 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
02c958dd | 1009 | queue_writel(queue, ISR, MACB_BIT(RCOMP)); |
b336369c | 1010 | |
288379f0 | 1011 | if (napi_schedule_prep(&bp->napi)) { |
a268adb1 | 1012 | netdev_vdbg(bp->dev, "scheduling RX softirq\n"); |
288379f0 | 1013 | __napi_schedule(&bp->napi); |
89e5785f HS |
1014 | } |
1015 | } | |
1016 | ||
e86cd53a | 1017 | if (unlikely(status & (MACB_TX_ERR_FLAGS))) { |
02c958dd CP |
1018 | queue_writel(queue, IDR, MACB_TX_INT_FLAGS); |
1019 | schedule_work(&queue->tx_error_task); | |
6a027b70 SB |
1020 | |
1021 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
02c958dd | 1022 | queue_writel(queue, ISR, MACB_TX_ERR_FLAGS); |
6a027b70 | 1023 | |
e86cd53a NF |
1024 | break; |
1025 | } | |
1026 | ||
1027 | if (status & MACB_BIT(TCOMP)) | |
02c958dd | 1028 | macb_tx_interrupt(queue); |
89e5785f HS |
1029 | |
1030 | /* | |
1031 | * Link change detection isn't possible with RMII, so we'll | |
1032 | * add that if/when we get our hands on a full-blown MII PHY. | |
1033 | */ | |
1034 | ||
b19f7f71 AS |
1035 | if (status & MACB_BIT(ISR_ROVR)) { |
1036 | /* We missed at least one packet */ | |
f75ba50b JI |
1037 | if (macb_is_gem(bp)) |
1038 | bp->hw_stats.gem.rx_overruns++; | |
1039 | else | |
1040 | bp->hw_stats.macb.rx_overruns++; | |
6a027b70 SB |
1041 | |
1042 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
02c958dd | 1043 | queue_writel(queue, ISR, MACB_BIT(ISR_ROVR)); |
b19f7f71 AS |
1044 | } |
1045 | ||
89e5785f HS |
1046 | if (status & MACB_BIT(HRESP)) { |
1047 | /* | |
c220f8cd JI |
1048 | * TODO: Reset the hardware, and maybe move the |
1049 | * netdev_err to a lower-priority context as well | |
1050 | * (work queue?) | |
89e5785f | 1051 | */ |
c220f8cd | 1052 | netdev_err(dev, "DMA bus error: HRESP not OK\n"); |
6a027b70 SB |
1053 | |
1054 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
02c958dd | 1055 | queue_writel(queue, ISR, MACB_BIT(HRESP)); |
89e5785f HS |
1056 | } |
1057 | ||
02c958dd | 1058 | status = queue_readl(queue, ISR); |
89e5785f HS |
1059 | } |
1060 | ||
1061 | spin_unlock(&bp->lock); | |
1062 | ||
1063 | return IRQ_HANDLED; | |
1064 | } | |
1065 | ||
6e8cf5c0 TP |
1066 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1067 | /* | |
1068 | * Polling receive - used by netconsole and other diagnostic tools | |
1069 | * to allow network i/o with interrupts disabled. | |
1070 | */ | |
1071 | static void macb_poll_controller(struct net_device *dev) | |
1072 | { | |
02c958dd CP |
1073 | struct macb *bp = netdev_priv(dev); |
1074 | struct macb_queue *queue; | |
6e8cf5c0 | 1075 | unsigned long flags; |
02c958dd | 1076 | unsigned int q; |
6e8cf5c0 TP |
1077 | |
1078 | local_irq_save(flags); | |
02c958dd CP |
1079 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) |
1080 | macb_interrupt(dev->irq, queue); | |
6e8cf5c0 TP |
1081 | local_irq_restore(flags); |
1082 | } | |
1083 | #endif | |
1084 | ||
a4c35ed3 CP |
1085 | static inline unsigned int macb_count_tx_descriptors(struct macb *bp, |
1086 | unsigned int len) | |
1087 | { | |
1088 | return (len + bp->max_tx_length - 1) / bp->max_tx_length; | |
1089 | } | |
1090 | ||
1091 | static unsigned int macb_tx_map(struct macb *bp, | |
02c958dd | 1092 | struct macb_queue *queue, |
a4c35ed3 | 1093 | struct sk_buff *skb) |
89e5785f | 1094 | { |
89e5785f | 1095 | dma_addr_t mapping; |
02c958dd | 1096 | unsigned int len, entry, i, tx_head = queue->tx_head; |
a4c35ed3 | 1097 | struct macb_tx_skb *tx_skb = NULL; |
55054a16 | 1098 | struct macb_dma_desc *desc; |
a4c35ed3 CP |
1099 | unsigned int offset, size, count = 0; |
1100 | unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags; | |
1101 | unsigned int eof = 1; | |
89e5785f | 1102 | u32 ctrl; |
a4c35ed3 CP |
1103 | |
1104 | /* First, map non-paged data */ | |
1105 | len = skb_headlen(skb); | |
1106 | offset = 0; | |
1107 | while (len) { | |
1108 | size = min(len, bp->max_tx_length); | |
1109 | entry = macb_tx_ring_wrap(tx_head); | |
02c958dd | 1110 | tx_skb = &queue->tx_skb[entry]; |
a4c35ed3 CP |
1111 | |
1112 | mapping = dma_map_single(&bp->pdev->dev, | |
1113 | skb->data + offset, | |
1114 | size, DMA_TO_DEVICE); | |
1115 | if (dma_mapping_error(&bp->pdev->dev, mapping)) | |
1116 | goto dma_error; | |
1117 | ||
1118 | /* Save info to properly release resources */ | |
1119 | tx_skb->skb = NULL; | |
1120 | tx_skb->mapping = mapping; | |
1121 | tx_skb->size = size; | |
1122 | tx_skb->mapped_as_page = false; | |
1123 | ||
1124 | len -= size; | |
1125 | offset += size; | |
1126 | count++; | |
1127 | tx_head++; | |
1128 | } | |
1129 | ||
1130 | /* Then, map paged data from fragments */ | |
1131 | for (f = 0; f < nr_frags; f++) { | |
1132 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; | |
1133 | ||
1134 | len = skb_frag_size(frag); | |
1135 | offset = 0; | |
1136 | while (len) { | |
1137 | size = min(len, bp->max_tx_length); | |
1138 | entry = macb_tx_ring_wrap(tx_head); | |
02c958dd | 1139 | tx_skb = &queue->tx_skb[entry]; |
a4c35ed3 CP |
1140 | |
1141 | mapping = skb_frag_dma_map(&bp->pdev->dev, frag, | |
1142 | offset, size, DMA_TO_DEVICE); | |
1143 | if (dma_mapping_error(&bp->pdev->dev, mapping)) | |
1144 | goto dma_error; | |
1145 | ||
1146 | /* Save info to properly release resources */ | |
1147 | tx_skb->skb = NULL; | |
1148 | tx_skb->mapping = mapping; | |
1149 | tx_skb->size = size; | |
1150 | tx_skb->mapped_as_page = true; | |
1151 | ||
1152 | len -= size; | |
1153 | offset += size; | |
1154 | count++; | |
1155 | tx_head++; | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | /* Should never happen */ | |
1160 | if (unlikely(tx_skb == NULL)) { | |
1161 | netdev_err(bp->dev, "BUG! empty skb!\n"); | |
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | /* This is the last buffer of the frame: save socket buffer */ | |
1166 | tx_skb->skb = skb; | |
1167 | ||
1168 | /* Update TX ring: update buffer descriptors in reverse order | |
1169 | * to avoid race condition | |
1170 | */ | |
1171 | ||
1172 | /* Set 'TX_USED' bit in buffer descriptor at tx_head position | |
1173 | * to set the end of TX queue | |
1174 | */ | |
1175 | i = tx_head; | |
1176 | entry = macb_tx_ring_wrap(i); | |
1177 | ctrl = MACB_BIT(TX_USED); | |
02c958dd | 1178 | desc = &queue->tx_ring[entry]; |
a4c35ed3 CP |
1179 | desc->ctrl = ctrl; |
1180 | ||
1181 | do { | |
1182 | i--; | |
1183 | entry = macb_tx_ring_wrap(i); | |
02c958dd CP |
1184 | tx_skb = &queue->tx_skb[entry]; |
1185 | desc = &queue->tx_ring[entry]; | |
a4c35ed3 CP |
1186 | |
1187 | ctrl = (u32)tx_skb->size; | |
1188 | if (eof) { | |
1189 | ctrl |= MACB_BIT(TX_LAST); | |
1190 | eof = 0; | |
1191 | } | |
1192 | if (unlikely(entry == (TX_RING_SIZE - 1))) | |
1193 | ctrl |= MACB_BIT(TX_WRAP); | |
1194 | ||
1195 | /* Set TX buffer descriptor */ | |
1196 | desc->addr = tx_skb->mapping; | |
1197 | /* desc->addr must be visible to hardware before clearing | |
1198 | * 'TX_USED' bit in desc->ctrl. | |
1199 | */ | |
1200 | wmb(); | |
1201 | desc->ctrl = ctrl; | |
02c958dd | 1202 | } while (i != queue->tx_head); |
a4c35ed3 | 1203 | |
02c958dd | 1204 | queue->tx_head = tx_head; |
a4c35ed3 CP |
1205 | |
1206 | return count; | |
1207 | ||
1208 | dma_error: | |
1209 | netdev_err(bp->dev, "TX DMA map failed\n"); | |
1210 | ||
02c958dd CP |
1211 | for (i = queue->tx_head; i != tx_head; i++) { |
1212 | tx_skb = macb_tx_skb(queue, i); | |
a4c35ed3 CP |
1213 | |
1214 | macb_tx_unmap(bp, tx_skb); | |
1215 | } | |
1216 | ||
1217 | return 0; | |
1218 | } | |
1219 | ||
1220 | static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1221 | { | |
02c958dd | 1222 | u16 queue_index = skb_get_queue_mapping(skb); |
a4c35ed3 | 1223 | struct macb *bp = netdev_priv(dev); |
02c958dd | 1224 | struct macb_queue *queue = &bp->queues[queue_index]; |
4871953c | 1225 | unsigned long flags; |
a4c35ed3 | 1226 | unsigned int count, nr_frags, frag_size, f; |
89e5785f | 1227 | |
a268adb1 HS |
1228 | #if defined(DEBUG) && defined(VERBOSE_DEBUG) |
1229 | netdev_vdbg(bp->dev, | |
02c958dd CP |
1230 | "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n", |
1231 | queue_index, skb->len, skb->head, skb->data, | |
c220f8cd JI |
1232 | skb_tail_pointer(skb), skb_end_pointer(skb)); |
1233 | print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, | |
1234 | skb->data, 16, true); | |
89e5785f HS |
1235 | #endif |
1236 | ||
a4c35ed3 CP |
1237 | /* Count how many TX buffer descriptors are needed to send this |
1238 | * socket buffer: skb fragments of jumbo frames may need to be | |
1239 | * splitted into many buffer descriptors. | |
1240 | */ | |
1241 | count = macb_count_tx_descriptors(bp, skb_headlen(skb)); | |
1242 | nr_frags = skb_shinfo(skb)->nr_frags; | |
1243 | for (f = 0; f < nr_frags; f++) { | |
1244 | frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); | |
1245 | count += macb_count_tx_descriptors(bp, frag_size); | |
1246 | } | |
1247 | ||
4871953c | 1248 | spin_lock_irqsave(&bp->lock, flags); |
89e5785f HS |
1249 | |
1250 | /* This is a hard error, log it. */ | |
02c958dd CP |
1251 | if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) { |
1252 | netif_stop_subqueue(dev, queue_index); | |
4871953c | 1253 | spin_unlock_irqrestore(&bp->lock, flags); |
c220f8cd | 1254 | netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", |
02c958dd | 1255 | queue->tx_head, queue->tx_tail); |
5b548140 | 1256 | return NETDEV_TX_BUSY; |
89e5785f HS |
1257 | } |
1258 | ||
a4c35ed3 | 1259 | /* Map socket buffer for DMA transfer */ |
02c958dd | 1260 | if (!macb_tx_map(bp, queue, skb)) { |
c88b5b6a | 1261 | dev_kfree_skb_any(skb); |
92030908 SB |
1262 | goto unlock; |
1263 | } | |
55054a16 | 1264 | |
03dbe05f | 1265 | /* Make newly initialized descriptor visible to hardware */ |
89e5785f HS |
1266 | wmb(); |
1267 | ||
e072092f RC |
1268 | skb_tx_timestamp(skb); |
1269 | ||
89e5785f HS |
1270 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); |
1271 | ||
02c958dd CP |
1272 | if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1) |
1273 | netif_stop_subqueue(dev, queue_index); | |
89e5785f | 1274 | |
92030908 | 1275 | unlock: |
4871953c | 1276 | spin_unlock_irqrestore(&bp->lock, flags); |
89e5785f | 1277 | |
6ed10654 | 1278 | return NETDEV_TX_OK; |
89e5785f HS |
1279 | } |
1280 | ||
4df95131 | 1281 | static void macb_init_rx_buffer_size(struct macb *bp, size_t size) |
1b44791a NF |
1282 | { |
1283 | if (!macb_is_gem(bp)) { | |
1284 | bp->rx_buffer_size = MACB_RX_BUFFER_SIZE; | |
1285 | } else { | |
4df95131 | 1286 | bp->rx_buffer_size = size; |
1b44791a | 1287 | |
1b44791a | 1288 | if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) { |
4df95131 NF |
1289 | netdev_dbg(bp->dev, |
1290 | "RX buffer must be multiple of %d bytes, expanding\n", | |
1b44791a NF |
1291 | RX_BUFFER_MULTIPLE); |
1292 | bp->rx_buffer_size = | |
4df95131 | 1293 | roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE); |
1b44791a | 1294 | } |
1b44791a | 1295 | } |
4df95131 NF |
1296 | |
1297 | netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n", | |
1298 | bp->dev->mtu, bp->rx_buffer_size); | |
1b44791a NF |
1299 | } |
1300 | ||
4df95131 NF |
1301 | static void gem_free_rx_buffers(struct macb *bp) |
1302 | { | |
1303 | struct sk_buff *skb; | |
1304 | struct macb_dma_desc *desc; | |
1305 | dma_addr_t addr; | |
1306 | int i; | |
1307 | ||
1308 | if (!bp->rx_skbuff) | |
1309 | return; | |
1310 | ||
1311 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1312 | skb = bp->rx_skbuff[i]; | |
1313 | ||
1314 | if (skb == NULL) | |
1315 | continue; | |
1316 | ||
1317 | desc = &bp->rx_ring[i]; | |
1318 | addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); | |
ccd6d0a9 | 1319 | dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size, |
4df95131 NF |
1320 | DMA_FROM_DEVICE); |
1321 | dev_kfree_skb_any(skb); | |
1322 | skb = NULL; | |
1323 | } | |
1324 | ||
1325 | kfree(bp->rx_skbuff); | |
1326 | bp->rx_skbuff = NULL; | |
1327 | } | |
1328 | ||
1329 | static void macb_free_rx_buffers(struct macb *bp) | |
1330 | { | |
1331 | if (bp->rx_buffers) { | |
1332 | dma_free_coherent(&bp->pdev->dev, | |
1333 | RX_RING_SIZE * bp->rx_buffer_size, | |
1334 | bp->rx_buffers, bp->rx_buffers_dma); | |
1335 | bp->rx_buffers = NULL; | |
1336 | } | |
1337 | } | |
1b44791a | 1338 | |
89e5785f HS |
1339 | static void macb_free_consistent(struct macb *bp) |
1340 | { | |
02c958dd CP |
1341 | struct macb_queue *queue; |
1342 | unsigned int q; | |
1343 | ||
4df95131 | 1344 | bp->macbgem_ops.mog_free_rx_buffers(bp); |
89e5785f HS |
1345 | if (bp->rx_ring) { |
1346 | dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, | |
1347 | bp->rx_ring, bp->rx_ring_dma); | |
1348 | bp->rx_ring = NULL; | |
1349 | } | |
02c958dd CP |
1350 | |
1351 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { | |
1352 | kfree(queue->tx_skb); | |
1353 | queue->tx_skb = NULL; | |
1354 | if (queue->tx_ring) { | |
1355 | dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, | |
1356 | queue->tx_ring, queue->tx_ring_dma); | |
1357 | queue->tx_ring = NULL; | |
1358 | } | |
89e5785f | 1359 | } |
4df95131 NF |
1360 | } |
1361 | ||
1362 | static int gem_alloc_rx_buffers(struct macb *bp) | |
1363 | { | |
1364 | int size; | |
1365 | ||
1366 | size = RX_RING_SIZE * sizeof(struct sk_buff *); | |
1367 | bp->rx_skbuff = kzalloc(size, GFP_KERNEL); | |
1368 | if (!bp->rx_skbuff) | |
1369 | return -ENOMEM; | |
1370 | else | |
1371 | netdev_dbg(bp->dev, | |
1372 | "Allocated %d RX struct sk_buff entries at %p\n", | |
1373 | RX_RING_SIZE, bp->rx_skbuff); | |
1374 | return 0; | |
1375 | } | |
1376 | ||
1377 | static int macb_alloc_rx_buffers(struct macb *bp) | |
1378 | { | |
1379 | int size; | |
1380 | ||
1381 | size = RX_RING_SIZE * bp->rx_buffer_size; | |
1382 | bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, | |
1383 | &bp->rx_buffers_dma, GFP_KERNEL); | |
1384 | if (!bp->rx_buffers) | |
1385 | return -ENOMEM; | |
1386 | else | |
1387 | netdev_dbg(bp->dev, | |
1388 | "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", | |
1389 | size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); | |
1390 | return 0; | |
89e5785f HS |
1391 | } |
1392 | ||
1393 | static int macb_alloc_consistent(struct macb *bp) | |
1394 | { | |
02c958dd CP |
1395 | struct macb_queue *queue; |
1396 | unsigned int q; | |
89e5785f HS |
1397 | int size; |
1398 | ||
02c958dd CP |
1399 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
1400 | size = TX_RING_BYTES; | |
1401 | queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
1402 | &queue->tx_ring_dma, | |
1403 | GFP_KERNEL); | |
1404 | if (!queue->tx_ring) | |
1405 | goto out_err; | |
1406 | netdev_dbg(bp->dev, | |
1407 | "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n", | |
1408 | q, size, (unsigned long)queue->tx_ring_dma, | |
1409 | queue->tx_ring); | |
1410 | ||
1411 | size = TX_RING_SIZE * sizeof(struct macb_tx_skb); | |
1412 | queue->tx_skb = kmalloc(size, GFP_KERNEL); | |
1413 | if (!queue->tx_skb) | |
1414 | goto out_err; | |
1415 | } | |
89e5785f HS |
1416 | |
1417 | size = RX_RING_BYTES; | |
1418 | bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
1419 | &bp->rx_ring_dma, GFP_KERNEL); | |
1420 | if (!bp->rx_ring) | |
1421 | goto out_err; | |
c220f8cd JI |
1422 | netdev_dbg(bp->dev, |
1423 | "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", | |
1424 | size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); | |
89e5785f | 1425 | |
4df95131 | 1426 | if (bp->macbgem_ops.mog_alloc_rx_buffers(bp)) |
89e5785f | 1427 | goto out_err; |
89e5785f HS |
1428 | |
1429 | return 0; | |
1430 | ||
1431 | out_err: | |
1432 | macb_free_consistent(bp); | |
1433 | return -ENOMEM; | |
1434 | } | |
1435 | ||
4df95131 NF |
1436 | static void gem_init_rings(struct macb *bp) |
1437 | { | |
02c958dd CP |
1438 | struct macb_queue *queue; |
1439 | unsigned int q; | |
4df95131 NF |
1440 | int i; |
1441 | ||
02c958dd CP |
1442 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
1443 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1444 | queue->tx_ring[i].addr = 0; | |
1445 | queue->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
1446 | } | |
1447 | queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
1448 | queue->tx_head = 0; | |
1449 | queue->tx_tail = 0; | |
4df95131 | 1450 | } |
4df95131 | 1451 | |
02c958dd CP |
1452 | bp->rx_tail = 0; |
1453 | bp->rx_prepared_head = 0; | |
4df95131 NF |
1454 | |
1455 | gem_rx_refill(bp); | |
1456 | } | |
1457 | ||
89e5785f HS |
1458 | static void macb_init_rings(struct macb *bp) |
1459 | { | |
1460 | int i; | |
1461 | dma_addr_t addr; | |
1462 | ||
1463 | addr = bp->rx_buffers_dma; | |
1464 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1465 | bp->rx_ring[i].addr = addr; | |
1466 | bp->rx_ring[i].ctrl = 0; | |
1b44791a | 1467 | addr += bp->rx_buffer_size; |
89e5785f HS |
1468 | } |
1469 | bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); | |
1470 | ||
1471 | for (i = 0; i < TX_RING_SIZE; i++) { | |
02c958dd CP |
1472 | bp->queues[0].tx_ring[i].addr = 0; |
1473 | bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
1474 | bp->queues[0].tx_head = 0; | |
1475 | bp->queues[0].tx_tail = 0; | |
89e5785f | 1476 | } |
02c958dd | 1477 | bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); |
89e5785f | 1478 | |
02c958dd | 1479 | bp->rx_tail = 0; |
89e5785f HS |
1480 | } |
1481 | ||
1482 | static void macb_reset_hw(struct macb *bp) | |
1483 | { | |
02c958dd CP |
1484 | struct macb_queue *queue; |
1485 | unsigned int q; | |
1486 | ||
89e5785f HS |
1487 | /* |
1488 | * Disable RX and TX (XXX: Should we halt the transmission | |
1489 | * more gracefully?) | |
1490 | */ | |
1491 | macb_writel(bp, NCR, 0); | |
1492 | ||
1493 | /* Clear the stats registers (XXX: Update stats first?) */ | |
1494 | macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); | |
1495 | ||
1496 | /* Clear all status flags */ | |
95ebcea6 JE |
1497 | macb_writel(bp, TSR, -1); |
1498 | macb_writel(bp, RSR, -1); | |
89e5785f HS |
1499 | |
1500 | /* Disable all interrupts */ | |
02c958dd CP |
1501 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
1502 | queue_writel(queue, IDR, -1); | |
1503 | queue_readl(queue, ISR); | |
1504 | } | |
89e5785f HS |
1505 | } |
1506 | ||
70c9f3d4 JI |
1507 | static u32 gem_mdc_clk_div(struct macb *bp) |
1508 | { | |
1509 | u32 config; | |
1510 | unsigned long pclk_hz = clk_get_rate(bp->pclk); | |
1511 | ||
1512 | if (pclk_hz <= 20000000) | |
1513 | config = GEM_BF(CLK, GEM_CLK_DIV8); | |
1514 | else if (pclk_hz <= 40000000) | |
1515 | config = GEM_BF(CLK, GEM_CLK_DIV16); | |
1516 | else if (pclk_hz <= 80000000) | |
1517 | config = GEM_BF(CLK, GEM_CLK_DIV32); | |
1518 | else if (pclk_hz <= 120000000) | |
1519 | config = GEM_BF(CLK, GEM_CLK_DIV48); | |
1520 | else if (pclk_hz <= 160000000) | |
1521 | config = GEM_BF(CLK, GEM_CLK_DIV64); | |
1522 | else | |
1523 | config = GEM_BF(CLK, GEM_CLK_DIV96); | |
1524 | ||
1525 | return config; | |
1526 | } | |
1527 | ||
1528 | static u32 macb_mdc_clk_div(struct macb *bp) | |
1529 | { | |
1530 | u32 config; | |
1531 | unsigned long pclk_hz; | |
1532 | ||
1533 | if (macb_is_gem(bp)) | |
1534 | return gem_mdc_clk_div(bp); | |
1535 | ||
1536 | pclk_hz = clk_get_rate(bp->pclk); | |
1537 | if (pclk_hz <= 20000000) | |
1538 | config = MACB_BF(CLK, MACB_CLK_DIV8); | |
1539 | else if (pclk_hz <= 40000000) | |
1540 | config = MACB_BF(CLK, MACB_CLK_DIV16); | |
1541 | else if (pclk_hz <= 80000000) | |
1542 | config = MACB_BF(CLK, MACB_CLK_DIV32); | |
1543 | else | |
1544 | config = MACB_BF(CLK, MACB_CLK_DIV64); | |
1545 | ||
1546 | return config; | |
1547 | } | |
1548 | ||
757a03c6 JI |
1549 | /* |
1550 | * Get the DMA bus width field of the network configuration register that we | |
1551 | * should program. We find the width from decoding the design configuration | |
1552 | * register to find the maximum supported data bus width. | |
1553 | */ | |
1554 | static u32 macb_dbw(struct macb *bp) | |
1555 | { | |
1556 | if (!macb_is_gem(bp)) | |
1557 | return 0; | |
1558 | ||
1559 | switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { | |
1560 | case 4: | |
1561 | return GEM_BF(DBW, GEM_DBW128); | |
1562 | case 2: | |
1563 | return GEM_BF(DBW, GEM_DBW64); | |
1564 | case 1: | |
1565 | default: | |
1566 | return GEM_BF(DBW, GEM_DBW32); | |
1567 | } | |
1568 | } | |
1569 | ||
0116da4f | 1570 | /* |
b3e3bd71 NF |
1571 | * Configure the receive DMA engine |
1572 | * - use the correct receive buffer size | |
e175587f | 1573 | * - set best burst length for DMA operations |
b3e3bd71 NF |
1574 | * (if not supported by FIFO, it will fallback to default) |
1575 | * - set both rx/tx packet buffers to full memory size | |
1576 | * These are configurable parameters for GEM. | |
0116da4f JI |
1577 | */ |
1578 | static void macb_configure_dma(struct macb *bp) | |
1579 | { | |
1580 | u32 dmacfg; | |
1581 | ||
1582 | if (macb_is_gem(bp)) { | |
1583 | dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); | |
1b44791a | 1584 | dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE); |
e175587f NF |
1585 | if (bp->dma_burst_length) |
1586 | dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); | |
b3e3bd71 | 1587 | dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); |
a1ae385d | 1588 | dmacfg &= ~GEM_BIT(ENDIA); |
85ff3d87 CP |
1589 | if (bp->dev->features & NETIF_F_HW_CSUM) |
1590 | dmacfg |= GEM_BIT(TXCOEN); | |
1591 | else | |
1592 | dmacfg &= ~GEM_BIT(TXCOEN); | |
e175587f NF |
1593 | netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n", |
1594 | dmacfg); | |
0116da4f JI |
1595 | gem_writel(bp, DMACFG, dmacfg); |
1596 | } | |
1597 | } | |
1598 | ||
89e5785f HS |
1599 | static void macb_init_hw(struct macb *bp) |
1600 | { | |
02c958dd CP |
1601 | struct macb_queue *queue; |
1602 | unsigned int q; | |
1603 | ||
89e5785f HS |
1604 | u32 config; |
1605 | ||
1606 | macb_reset_hw(bp); | |
314bccc4 | 1607 | macb_set_hwaddr(bp); |
89e5785f | 1608 | |
70c9f3d4 | 1609 | config = macb_mdc_clk_div(bp); |
29bc2e1e | 1610 | config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */ |
89e5785f HS |
1611 | config |= MACB_BIT(PAE); /* PAuse Enable */ |
1612 | config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ | |
8dd4bd00 | 1613 | config |= MACB_BIT(BIG); /* Receive oversized frames */ |
89e5785f HS |
1614 | if (bp->dev->flags & IFF_PROMISC) |
1615 | config |= MACB_BIT(CAF); /* Copy All Frames */ | |
924ec53c CP |
1616 | else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM) |
1617 | config |= GEM_BIT(RXCOEN); | |
89e5785f HS |
1618 | if (!(bp->dev->flags & IFF_BROADCAST)) |
1619 | config |= MACB_BIT(NBC); /* No BroadCast */ | |
757a03c6 | 1620 | config |= macb_dbw(bp); |
89e5785f | 1621 | macb_writel(bp, NCFGR, config); |
26cdfb49 VD |
1622 | bp->speed = SPEED_10; |
1623 | bp->duplex = DUPLEX_HALF; | |
89e5785f | 1624 | |
0116da4f JI |
1625 | macb_configure_dma(bp); |
1626 | ||
89e5785f HS |
1627 | /* Initialize TX and RX buffers */ |
1628 | macb_writel(bp, RBQP, bp->rx_ring_dma); | |
02c958dd CP |
1629 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
1630 | queue_writel(queue, TBQP, queue->tx_ring_dma); | |
1631 | ||
1632 | /* Enable interrupts */ | |
1633 | queue_writel(queue, IER, | |
1634 | MACB_RX_INT_FLAGS | | |
1635 | MACB_TX_INT_FLAGS | | |
1636 | MACB_BIT(HRESP)); | |
1637 | } | |
89e5785f HS |
1638 | |
1639 | /* Enable TX and RX */ | |
6c36a707 | 1640 | macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); |
89e5785f HS |
1641 | } |
1642 | ||
446ebd01 PV |
1643 | /* |
1644 | * The hash address register is 64 bits long and takes up two | |
1645 | * locations in the memory map. The least significant bits are stored | |
1646 | * in EMAC_HSL and the most significant bits in EMAC_HSH. | |
1647 | * | |
1648 | * The unicast hash enable and the multicast hash enable bits in the | |
1649 | * network configuration register enable the reception of hash matched | |
1650 | * frames. The destination address is reduced to a 6 bit index into | |
1651 | * the 64 bit hash register using the following hash function. The | |
1652 | * hash function is an exclusive or of every sixth bit of the | |
1653 | * destination address. | |
1654 | * | |
1655 | * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
1656 | * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
1657 | * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
1658 | * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
1659 | * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
1660 | * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
1661 | * | |
1662 | * da[0] represents the least significant bit of the first byte | |
1663 | * received, that is, the multicast/unicast indicator, and da[47] | |
1664 | * represents the most significant bit of the last byte received. If | |
1665 | * the hash index, hi[n], points to a bit that is set in the hash | |
1666 | * register then the frame will be matched according to whether the | |
1667 | * frame is multicast or unicast. A multicast match will be signalled | |
1668 | * if the multicast hash enable bit is set, da[0] is 1 and the hash | |
1669 | * index points to a bit set in the hash register. A unicast match | |
1670 | * will be signalled if the unicast hash enable bit is set, da[0] is 0 | |
1671 | * and the hash index points to a bit set in the hash register. To | |
1672 | * receive all multicast frames, the hash register should be set with | |
1673 | * all ones and the multicast hash enable bit should be set in the | |
1674 | * network configuration register. | |
1675 | */ | |
1676 | ||
1677 | static inline int hash_bit_value(int bitnr, __u8 *addr) | |
1678 | { | |
1679 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
1680 | return 1; | |
1681 | return 0; | |
1682 | } | |
1683 | ||
1684 | /* | |
1685 | * Return the hash index value for the specified address. | |
1686 | */ | |
1687 | static int hash_get_index(__u8 *addr) | |
1688 | { | |
1689 | int i, j, bitval; | |
1690 | int hash_index = 0; | |
1691 | ||
1692 | for (j = 0; j < 6; j++) { | |
1693 | for (i = 0, bitval = 0; i < 8; i++) | |
2fa45e22 | 1694 | bitval ^= hash_bit_value(i * 6 + j, addr); |
446ebd01 PV |
1695 | |
1696 | hash_index |= (bitval << j); | |
1697 | } | |
1698 | ||
1699 | return hash_index; | |
1700 | } | |
1701 | ||
1702 | /* | |
1703 | * Add multicast addresses to the internal multicast-hash table. | |
1704 | */ | |
1705 | static void macb_sethashtable(struct net_device *dev) | |
1706 | { | |
22bedad3 | 1707 | struct netdev_hw_addr *ha; |
446ebd01 | 1708 | unsigned long mc_filter[2]; |
f9dcbcc9 | 1709 | unsigned int bitnr; |
446ebd01 PV |
1710 | struct macb *bp = netdev_priv(dev); |
1711 | ||
1712 | mc_filter[0] = mc_filter[1] = 0; | |
1713 | ||
22bedad3 JP |
1714 | netdev_for_each_mc_addr(ha, dev) { |
1715 | bitnr = hash_get_index(ha->addr); | |
446ebd01 PV |
1716 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); |
1717 | } | |
1718 | ||
f75ba50b JI |
1719 | macb_or_gem_writel(bp, HRB, mc_filter[0]); |
1720 | macb_or_gem_writel(bp, HRT, mc_filter[1]); | |
446ebd01 PV |
1721 | } |
1722 | ||
1723 | /* | |
1724 | * Enable/Disable promiscuous and multicast modes. | |
1725 | */ | |
e0da1f14 | 1726 | void macb_set_rx_mode(struct net_device *dev) |
446ebd01 PV |
1727 | { |
1728 | unsigned long cfg; | |
1729 | struct macb *bp = netdev_priv(dev); | |
1730 | ||
1731 | cfg = macb_readl(bp, NCFGR); | |
1732 | ||
924ec53c | 1733 | if (dev->flags & IFF_PROMISC) { |
446ebd01 PV |
1734 | /* Enable promiscuous mode */ |
1735 | cfg |= MACB_BIT(CAF); | |
924ec53c CP |
1736 | |
1737 | /* Disable RX checksum offload */ | |
1738 | if (macb_is_gem(bp)) | |
1739 | cfg &= ~GEM_BIT(RXCOEN); | |
1740 | } else { | |
1741 | /* Disable promiscuous mode */ | |
446ebd01 PV |
1742 | cfg &= ~MACB_BIT(CAF); |
1743 | ||
924ec53c CP |
1744 | /* Enable RX checksum offload only if requested */ |
1745 | if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM) | |
1746 | cfg |= GEM_BIT(RXCOEN); | |
1747 | } | |
1748 | ||
446ebd01 PV |
1749 | if (dev->flags & IFF_ALLMULTI) { |
1750 | /* Enable all multicast mode */ | |
f75ba50b JI |
1751 | macb_or_gem_writel(bp, HRB, -1); |
1752 | macb_or_gem_writel(bp, HRT, -1); | |
446ebd01 | 1753 | cfg |= MACB_BIT(NCFGR_MTI); |
4cd24eaf | 1754 | } else if (!netdev_mc_empty(dev)) { |
446ebd01 PV |
1755 | /* Enable specific multicasts */ |
1756 | macb_sethashtable(dev); | |
1757 | cfg |= MACB_BIT(NCFGR_MTI); | |
1758 | } else if (dev->flags & (~IFF_ALLMULTI)) { | |
1759 | /* Disable all multicast mode */ | |
f75ba50b JI |
1760 | macb_or_gem_writel(bp, HRB, 0); |
1761 | macb_or_gem_writel(bp, HRT, 0); | |
446ebd01 PV |
1762 | cfg &= ~MACB_BIT(NCFGR_MTI); |
1763 | } | |
1764 | ||
1765 | macb_writel(bp, NCFGR, cfg); | |
1766 | } | |
e0da1f14 | 1767 | EXPORT_SYMBOL_GPL(macb_set_rx_mode); |
446ebd01 | 1768 | |
89e5785f HS |
1769 | static int macb_open(struct net_device *dev) |
1770 | { | |
1771 | struct macb *bp = netdev_priv(dev); | |
4df95131 | 1772 | size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN; |
89e5785f HS |
1773 | int err; |
1774 | ||
c220f8cd | 1775 | netdev_dbg(bp->dev, "open\n"); |
89e5785f | 1776 | |
03fc4721 NF |
1777 | /* carrier starts down */ |
1778 | netif_carrier_off(dev); | |
1779 | ||
6c36a707 R |
1780 | /* if the phy is not yet register, retry later*/ |
1781 | if (!bp->phy_dev) | |
1782 | return -EAGAIN; | |
1b44791a NF |
1783 | |
1784 | /* RX buffers initialization */ | |
4df95131 | 1785 | macb_init_rx_buffer_size(bp, bufsz); |
6c36a707 | 1786 | |
89e5785f HS |
1787 | err = macb_alloc_consistent(bp); |
1788 | if (err) { | |
c220f8cd JI |
1789 | netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", |
1790 | err); | |
89e5785f HS |
1791 | return err; |
1792 | } | |
1793 | ||
bea3348e SH |
1794 | napi_enable(&bp->napi); |
1795 | ||
4df95131 | 1796 | bp->macbgem_ops.mog_init_rings(bp); |
89e5785f | 1797 | macb_init_hw(bp); |
89e5785f | 1798 | |
6c36a707 R |
1799 | /* schedule a link state check */ |
1800 | phy_start(bp->phy_dev); | |
89e5785f | 1801 | |
02c958dd | 1802 | netif_tx_start_all_queues(dev); |
89e5785f HS |
1803 | |
1804 | return 0; | |
1805 | } | |
1806 | ||
1807 | static int macb_close(struct net_device *dev) | |
1808 | { | |
1809 | struct macb *bp = netdev_priv(dev); | |
1810 | unsigned long flags; | |
1811 | ||
02c958dd | 1812 | netif_tx_stop_all_queues(dev); |
bea3348e | 1813 | napi_disable(&bp->napi); |
89e5785f | 1814 | |
6c36a707 R |
1815 | if (bp->phy_dev) |
1816 | phy_stop(bp->phy_dev); | |
1817 | ||
89e5785f HS |
1818 | spin_lock_irqsave(&bp->lock, flags); |
1819 | macb_reset_hw(bp); | |
1820 | netif_carrier_off(dev); | |
1821 | spin_unlock_irqrestore(&bp->lock, flags); | |
1822 | ||
1823 | macb_free_consistent(bp); | |
1824 | ||
1825 | return 0; | |
1826 | } | |
1827 | ||
a494ed8e JI |
1828 | static void gem_update_stats(struct macb *bp) |
1829 | { | |
3ff13f1c | 1830 | int i; |
a494ed8e | 1831 | u32 *p = &bp->hw_stats.gem.tx_octets_31_0; |
a494ed8e | 1832 | |
3ff13f1c XH |
1833 | for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { |
1834 | u32 offset = gem_statistics[i].offset; | |
2fa45e22 | 1835 | u64 val = __raw_readl(bp->regs + offset); |
3ff13f1c XH |
1836 | |
1837 | bp->ethtool_stats[i] += val; | |
1838 | *p += val; | |
1839 | ||
1840 | if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { | |
1841 | /* Add GEM_OCTTXH, GEM_OCTRXH */ | |
2fa45e22 XH |
1842 | val = __raw_readl(bp->regs + offset + 4); |
1843 | bp->ethtool_stats[i] += ((u64)val) << 32; | |
3ff13f1c XH |
1844 | *(++p) += val; |
1845 | } | |
1846 | } | |
a494ed8e JI |
1847 | } |
1848 | ||
1849 | static struct net_device_stats *gem_get_stats(struct macb *bp) | |
1850 | { | |
1851 | struct gem_stats *hwstat = &bp->hw_stats.gem; | |
1852 | struct net_device_stats *nstat = &bp->stats; | |
1853 | ||
1854 | gem_update_stats(bp); | |
1855 | ||
1856 | nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + | |
1857 | hwstat->rx_alignment_errors + | |
1858 | hwstat->rx_resource_errors + | |
1859 | hwstat->rx_overruns + | |
1860 | hwstat->rx_oversize_frames + | |
1861 | hwstat->rx_jabbers + | |
1862 | hwstat->rx_undersized_frames + | |
1863 | hwstat->rx_length_field_frame_errors); | |
1864 | nstat->tx_errors = (hwstat->tx_late_collisions + | |
1865 | hwstat->tx_excessive_collisions + | |
1866 | hwstat->tx_underrun + | |
1867 | hwstat->tx_carrier_sense_errors); | |
1868 | nstat->multicast = hwstat->rx_multicast_frames; | |
1869 | nstat->collisions = (hwstat->tx_single_collision_frames + | |
1870 | hwstat->tx_multiple_collision_frames + | |
1871 | hwstat->tx_excessive_collisions); | |
1872 | nstat->rx_length_errors = (hwstat->rx_oversize_frames + | |
1873 | hwstat->rx_jabbers + | |
1874 | hwstat->rx_undersized_frames + | |
1875 | hwstat->rx_length_field_frame_errors); | |
1876 | nstat->rx_over_errors = hwstat->rx_resource_errors; | |
1877 | nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; | |
1878 | nstat->rx_frame_errors = hwstat->rx_alignment_errors; | |
1879 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1880 | nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; | |
1881 | nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; | |
1882 | nstat->tx_fifo_errors = hwstat->tx_underrun; | |
1883 | ||
1884 | return nstat; | |
1885 | } | |
1886 | ||
3ff13f1c XH |
1887 | static void gem_get_ethtool_stats(struct net_device *dev, |
1888 | struct ethtool_stats *stats, u64 *data) | |
1889 | { | |
1890 | struct macb *bp; | |
1891 | ||
1892 | bp = netdev_priv(dev); | |
1893 | gem_update_stats(bp); | |
2fa45e22 | 1894 | memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN); |
3ff13f1c XH |
1895 | } |
1896 | ||
1897 | static int gem_get_sset_count(struct net_device *dev, int sset) | |
1898 | { | |
1899 | switch (sset) { | |
1900 | case ETH_SS_STATS: | |
1901 | return GEM_STATS_LEN; | |
1902 | default: | |
1903 | return -EOPNOTSUPP; | |
1904 | } | |
1905 | } | |
1906 | ||
1907 | static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p) | |
1908 | { | |
1909 | int i; | |
1910 | ||
1911 | switch (sset) { | |
1912 | case ETH_SS_STATS: | |
1913 | for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN) | |
1914 | memcpy(p, gem_statistics[i].stat_string, | |
1915 | ETH_GSTRING_LEN); | |
1916 | break; | |
1917 | } | |
1918 | } | |
1919 | ||
2ea32eed | 1920 | struct net_device_stats *macb_get_stats(struct net_device *dev) |
89e5785f HS |
1921 | { |
1922 | struct macb *bp = netdev_priv(dev); | |
1923 | struct net_device_stats *nstat = &bp->stats; | |
a494ed8e JI |
1924 | struct macb_stats *hwstat = &bp->hw_stats.macb; |
1925 | ||
1926 | if (macb_is_gem(bp)) | |
1927 | return gem_get_stats(bp); | |
89e5785f | 1928 | |
6c36a707 R |
1929 | /* read stats from hardware */ |
1930 | macb_update_stats(bp); | |
1931 | ||
89e5785f HS |
1932 | /* Convert HW stats into netdevice stats */ |
1933 | nstat->rx_errors = (hwstat->rx_fcs_errors + | |
1934 | hwstat->rx_align_errors + | |
1935 | hwstat->rx_resource_errors + | |
1936 | hwstat->rx_overruns + | |
1937 | hwstat->rx_oversize_pkts + | |
1938 | hwstat->rx_jabbers + | |
1939 | hwstat->rx_undersize_pkts + | |
1940 | hwstat->sqe_test_errors + | |
1941 | hwstat->rx_length_mismatch); | |
1942 | nstat->tx_errors = (hwstat->tx_late_cols + | |
1943 | hwstat->tx_excessive_cols + | |
1944 | hwstat->tx_underruns + | |
1945 | hwstat->tx_carrier_errors); | |
1946 | nstat->collisions = (hwstat->tx_single_cols + | |
1947 | hwstat->tx_multiple_cols + | |
1948 | hwstat->tx_excessive_cols); | |
1949 | nstat->rx_length_errors = (hwstat->rx_oversize_pkts + | |
1950 | hwstat->rx_jabbers + | |
1951 | hwstat->rx_undersize_pkts + | |
1952 | hwstat->rx_length_mismatch); | |
b19f7f71 AS |
1953 | nstat->rx_over_errors = hwstat->rx_resource_errors + |
1954 | hwstat->rx_overruns; | |
89e5785f HS |
1955 | nstat->rx_crc_errors = hwstat->rx_fcs_errors; |
1956 | nstat->rx_frame_errors = hwstat->rx_align_errors; | |
1957 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1958 | /* XXX: What does "missed" mean? */ | |
1959 | nstat->tx_aborted_errors = hwstat->tx_excessive_cols; | |
1960 | nstat->tx_carrier_errors = hwstat->tx_carrier_errors; | |
1961 | nstat->tx_fifo_errors = hwstat->tx_underruns; | |
1962 | /* Don't know about heartbeat or window errors... */ | |
1963 | ||
1964 | return nstat; | |
1965 | } | |
2ea32eed | 1966 | EXPORT_SYMBOL_GPL(macb_get_stats); |
89e5785f HS |
1967 | |
1968 | static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1969 | { | |
1970 | struct macb *bp = netdev_priv(dev); | |
6c36a707 R |
1971 | struct phy_device *phydev = bp->phy_dev; |
1972 | ||
1973 | if (!phydev) | |
1974 | return -ENODEV; | |
89e5785f | 1975 | |
6c36a707 | 1976 | return phy_ethtool_gset(phydev, cmd); |
89e5785f HS |
1977 | } |
1978 | ||
1979 | static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1980 | { | |
1981 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1982 | struct phy_device *phydev = bp->phy_dev; |
89e5785f | 1983 | |
6c36a707 R |
1984 | if (!phydev) |
1985 | return -ENODEV; | |
1986 | ||
1987 | return phy_ethtool_sset(phydev, cmd); | |
89e5785f HS |
1988 | } |
1989 | ||
d1d1b53d NF |
1990 | static int macb_get_regs_len(struct net_device *netdev) |
1991 | { | |
1992 | return MACB_GREGS_NBR * sizeof(u32); | |
1993 | } | |
1994 | ||
1995 | static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1996 | void *p) | |
1997 | { | |
1998 | struct macb *bp = netdev_priv(dev); | |
1999 | unsigned int tail, head; | |
2000 | u32 *regs_buff = p; | |
2001 | ||
2002 | regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) | |
2003 | | MACB_GREGS_VERSION; | |
2004 | ||
02c958dd CP |
2005 | tail = macb_tx_ring_wrap(bp->queues[0].tx_tail); |
2006 | head = macb_tx_ring_wrap(bp->queues[0].tx_head); | |
d1d1b53d NF |
2007 | |
2008 | regs_buff[0] = macb_readl(bp, NCR); | |
2009 | regs_buff[1] = macb_or_gem_readl(bp, NCFGR); | |
2010 | regs_buff[2] = macb_readl(bp, NSR); | |
2011 | regs_buff[3] = macb_readl(bp, TSR); | |
2012 | regs_buff[4] = macb_readl(bp, RBQP); | |
2013 | regs_buff[5] = macb_readl(bp, TBQP); | |
2014 | regs_buff[6] = macb_readl(bp, RSR); | |
2015 | regs_buff[7] = macb_readl(bp, IMR); | |
2016 | ||
2017 | regs_buff[8] = tail; | |
2018 | regs_buff[9] = head; | |
02c958dd CP |
2019 | regs_buff[10] = macb_tx_dma(&bp->queues[0], tail); |
2020 | regs_buff[11] = macb_tx_dma(&bp->queues[0], head); | |
d1d1b53d NF |
2021 | |
2022 | if (macb_is_gem(bp)) { | |
2023 | regs_buff[12] = gem_readl(bp, USRIO); | |
2024 | regs_buff[13] = gem_readl(bp, DMACFG); | |
2025 | } | |
2026 | } | |
2027 | ||
0005f541 | 2028 | const struct ethtool_ops macb_ethtool_ops = { |
89e5785f HS |
2029 | .get_settings = macb_get_settings, |
2030 | .set_settings = macb_set_settings, | |
d1d1b53d NF |
2031 | .get_regs_len = macb_get_regs_len, |
2032 | .get_regs = macb_get_regs, | |
89e5785f | 2033 | .get_link = ethtool_op_get_link, |
17f393e8 | 2034 | .get_ts_info = ethtool_op_get_ts_info, |
3ff13f1c XH |
2035 | .get_ethtool_stats = gem_get_ethtool_stats, |
2036 | .get_strings = gem_get_ethtool_strings, | |
2037 | .get_sset_count = gem_get_sset_count, | |
89e5785f | 2038 | }; |
0005f541 | 2039 | EXPORT_SYMBOL_GPL(macb_ethtool_ops); |
89e5785f | 2040 | |
0005f541 | 2041 | int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
89e5785f HS |
2042 | { |
2043 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 2044 | struct phy_device *phydev = bp->phy_dev; |
89e5785f HS |
2045 | |
2046 | if (!netif_running(dev)) | |
2047 | return -EINVAL; | |
2048 | ||
6c36a707 R |
2049 | if (!phydev) |
2050 | return -ENODEV; | |
89e5785f | 2051 | |
28b04113 | 2052 | return phy_mii_ioctl(phydev, rq, cmd); |
89e5785f | 2053 | } |
0005f541 | 2054 | EXPORT_SYMBOL_GPL(macb_ioctl); |
89e5785f | 2055 | |
85ff3d87 CP |
2056 | static int macb_set_features(struct net_device *netdev, |
2057 | netdev_features_t features) | |
2058 | { | |
2059 | struct macb *bp = netdev_priv(netdev); | |
2060 | netdev_features_t changed = features ^ netdev->features; | |
2061 | ||
2062 | /* TX checksum offload */ | |
2063 | if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) { | |
2064 | u32 dmacfg; | |
2065 | ||
2066 | dmacfg = gem_readl(bp, DMACFG); | |
2067 | if (features & NETIF_F_HW_CSUM) | |
2068 | dmacfg |= GEM_BIT(TXCOEN); | |
2069 | else | |
2070 | dmacfg &= ~GEM_BIT(TXCOEN); | |
2071 | gem_writel(bp, DMACFG, dmacfg); | |
2072 | } | |
2073 | ||
924ec53c CP |
2074 | /* RX checksum offload */ |
2075 | if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) { | |
2076 | u32 netcfg; | |
2077 | ||
2078 | netcfg = gem_readl(bp, NCFGR); | |
2079 | if (features & NETIF_F_RXCSUM && | |
2080 | !(netdev->flags & IFF_PROMISC)) | |
2081 | netcfg |= GEM_BIT(RXCOEN); | |
2082 | else | |
2083 | netcfg &= ~GEM_BIT(RXCOEN); | |
2084 | gem_writel(bp, NCFGR, netcfg); | |
2085 | } | |
2086 | ||
85ff3d87 CP |
2087 | return 0; |
2088 | } | |
2089 | ||
5f1fa992 AB |
2090 | static const struct net_device_ops macb_netdev_ops = { |
2091 | .ndo_open = macb_open, | |
2092 | .ndo_stop = macb_close, | |
2093 | .ndo_start_xmit = macb_start_xmit, | |
afc4b13d | 2094 | .ndo_set_rx_mode = macb_set_rx_mode, |
5f1fa992 AB |
2095 | .ndo_get_stats = macb_get_stats, |
2096 | .ndo_do_ioctl = macb_ioctl, | |
2097 | .ndo_validate_addr = eth_validate_addr, | |
2098 | .ndo_change_mtu = eth_change_mtu, | |
2099 | .ndo_set_mac_address = eth_mac_addr, | |
6e8cf5c0 TP |
2100 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2101 | .ndo_poll_controller = macb_poll_controller, | |
2102 | #endif | |
85ff3d87 | 2103 | .ndo_set_features = macb_set_features, |
5f1fa992 AB |
2104 | }; |
2105 | ||
fb97a846 | 2106 | #if defined(CONFIG_OF) |
e175587f | 2107 | static struct macb_config pc302gem_config = { |
a4c35ed3 CP |
2108 | .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE, |
2109 | .dma_burst_length = 16, | |
2110 | }; | |
2111 | ||
2112 | static struct macb_config sama5d3_config = { | |
2113 | .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE, | |
e175587f NF |
2114 | .dma_burst_length = 16, |
2115 | }; | |
2116 | ||
4b7b0e4f CP |
2117 | static struct macb_config sama5d4_config = { |
2118 | .caps = 0, | |
2119 | .dma_burst_length = 4, | |
2120 | }; | |
2121 | ||
fb97a846 JCPV |
2122 | static const struct of_device_id macb_dt_ids[] = { |
2123 | { .compatible = "cdns,at32ap7000-macb" }, | |
2124 | { .compatible = "cdns,at91sam9260-macb" }, | |
2125 | { .compatible = "cdns,macb" }, | |
e175587f NF |
2126 | { .compatible = "cdns,pc302-gem", .data = &pc302gem_config }, |
2127 | { .compatible = "cdns,gem", .data = &pc302gem_config }, | |
a4c35ed3 | 2128 | { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config }, |
4b7b0e4f | 2129 | { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config }, |
fb97a846 JCPV |
2130 | { /* sentinel */ } |
2131 | }; | |
fb97a846 | 2132 | MODULE_DEVICE_TABLE(of, macb_dt_ids); |
fb97a846 JCPV |
2133 | #endif |
2134 | ||
e175587f NF |
2135 | /* |
2136 | * Configure peripheral capacities according to device tree | |
2137 | * and integration options used | |
2138 | */ | |
2139 | static void macb_configure_caps(struct macb *bp) | |
2140 | { | |
2141 | u32 dcfg; | |
2142 | const struct of_device_id *match; | |
2143 | const struct macb_config *config; | |
2144 | ||
2145 | if (bp->pdev->dev.of_node) { | |
2146 | match = of_match_node(macb_dt_ids, bp->pdev->dev.of_node); | |
2147 | if (match && match->data) { | |
2148 | config = (const struct macb_config *)match->data; | |
2149 | ||
2150 | bp->caps = config->caps; | |
2151 | /* | |
2152 | * As we have access to the matching node, configure | |
2153 | * DMA burst length as well | |
2154 | */ | |
2155 | bp->dma_burst_length = config->dma_burst_length; | |
2156 | } | |
2157 | } | |
2158 | ||
2159 | if (MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2) | |
2160 | bp->caps |= MACB_CAPS_MACB_IS_GEM; | |
2161 | ||
2162 | if (macb_is_gem(bp)) { | |
2163 | dcfg = gem_readl(bp, DCFG1); | |
2164 | if (GEM_BFEXT(IRQCOR, dcfg) == 0) | |
2165 | bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; | |
2166 | dcfg = gem_readl(bp, DCFG2); | |
2167 | if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) | |
2168 | bp->caps |= MACB_CAPS_FIFO_MODE; | |
2169 | } | |
2170 | ||
2171 | netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps); | |
2172 | } | |
2173 | ||
02c958dd CP |
2174 | static void macb_probe_queues(void __iomem *mem, |
2175 | unsigned int *queue_mask, | |
2176 | unsigned int *num_queues) | |
2177 | { | |
2178 | unsigned int hw_q; | |
2179 | u32 mid; | |
2180 | ||
2181 | *queue_mask = 0x1; | |
2182 | *num_queues = 1; | |
2183 | ||
2184 | /* is it macb or gem ? */ | |
2185 | mid = __raw_readl(mem + MACB_MID); | |
2186 | if (MACB_BFEXT(IDNUM, mid) != 0x2) | |
2187 | return; | |
2188 | ||
2189 | /* bit 0 is never set but queue 0 always exists */ | |
2190 | *queue_mask = __raw_readl(mem + GEM_DCFG6) & 0xff; | |
2191 | *queue_mask |= 0x1; | |
2192 | ||
2193 | for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q) | |
2194 | if (*queue_mask & (1 << hw_q)) | |
2195 | (*num_queues)++; | |
2196 | } | |
2197 | ||
06c3fd6a | 2198 | static int __init macb_probe(struct platform_device *pdev) |
89e5785f | 2199 | { |
84e0cdb0 | 2200 | struct macb_platform_data *pdata; |
89e5785f HS |
2201 | struct resource *regs; |
2202 | struct net_device *dev; | |
2203 | struct macb *bp; | |
02c958dd | 2204 | struct macb_queue *queue; |
6c36a707 | 2205 | struct phy_device *phydev; |
89e5785f HS |
2206 | u32 config; |
2207 | int err = -ENXIO; | |
50907043 | 2208 | const char *mac; |
02c958dd | 2209 | void __iomem *mem; |
cf250de0 | 2210 | unsigned int hw_q, queue_mask, q, num_queues; |
02c958dd | 2211 | struct clk *pclk, *hclk, *tx_clk; |
89e5785f HS |
2212 | |
2213 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2214 | if (!regs) { | |
2215 | dev_err(&pdev->dev, "no mmio resource defined\n"); | |
2216 | goto err_out; | |
2217 | } | |
2218 | ||
02c958dd CP |
2219 | pclk = devm_clk_get(&pdev->dev, "pclk"); |
2220 | if (IS_ERR(pclk)) { | |
2221 | err = PTR_ERR(pclk); | |
b48e0bab | 2222 | dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err); |
02c958dd | 2223 | goto err_out; |
0cc8674f | 2224 | } |
461845db | 2225 | |
02c958dd CP |
2226 | hclk = devm_clk_get(&pdev->dev, "hclk"); |
2227 | if (IS_ERR(hclk)) { | |
2228 | err = PTR_ERR(hclk); | |
b48e0bab | 2229 | dev_err(&pdev->dev, "failed to get hclk (%u)\n", err); |
02c958dd | 2230 | goto err_out; |
b48e0bab SB |
2231 | } |
2232 | ||
02c958dd | 2233 | tx_clk = devm_clk_get(&pdev->dev, "tx_clk"); |
e1824dfe | 2234 | |
02c958dd | 2235 | err = clk_prepare_enable(pclk); |
b48e0bab SB |
2236 | if (err) { |
2237 | dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err); | |
02c958dd | 2238 | goto err_out; |
b48e0bab SB |
2239 | } |
2240 | ||
02c958dd | 2241 | err = clk_prepare_enable(hclk); |
b48e0bab SB |
2242 | if (err) { |
2243 | dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err); | |
2244 | goto err_out_disable_pclk; | |
89e5785f | 2245 | } |
89e5785f | 2246 | |
02c958dd CP |
2247 | if (!IS_ERR(tx_clk)) { |
2248 | err = clk_prepare_enable(tx_clk); | |
e1824dfe SB |
2249 | if (err) { |
2250 | dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", | |
02c958dd | 2251 | err); |
e1824dfe SB |
2252 | goto err_out_disable_hclk; |
2253 | } | |
2254 | } | |
2255 | ||
02c958dd CP |
2256 | err = -ENOMEM; |
2257 | mem = devm_ioremap(&pdev->dev, regs->start, resource_size(regs)); | |
2258 | if (!mem) { | |
89e5785f | 2259 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); |
89e5785f HS |
2260 | goto err_out_disable_clocks; |
2261 | } | |
2262 | ||
02c958dd CP |
2263 | macb_probe_queues(mem, &queue_mask, &num_queues); |
2264 | dev = alloc_etherdev_mq(sizeof(*bp), num_queues); | |
2265 | if (!dev) | |
60fe716f | 2266 | goto err_out_disable_clocks; |
02c958dd CP |
2267 | |
2268 | SET_NETDEV_DEV(dev, &pdev->dev); | |
2269 | ||
2270 | bp = netdev_priv(dev); | |
2271 | bp->pdev = pdev; | |
2272 | bp->dev = dev; | |
2273 | bp->regs = mem; | |
2274 | bp->num_queues = num_queues; | |
2275 | bp->pclk = pclk; | |
2276 | bp->hclk = hclk; | |
2277 | bp->tx_clk = tx_clk; | |
2278 | ||
2279 | spin_lock_init(&bp->lock); | |
2280 | ||
2281 | /* set the queue register mapping once for all: queue0 has a special | |
2282 | * register mapping but we don't want to test the queue index then | |
2283 | * compute the corresponding register offset at run time. | |
2284 | */ | |
cf250de0 | 2285 | for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) { |
02c958dd CP |
2286 | if (!(queue_mask & (1 << hw_q))) |
2287 | continue; | |
2288 | ||
cf250de0 | 2289 | queue = &bp->queues[q]; |
02c958dd CP |
2290 | queue->bp = bp; |
2291 | if (hw_q) { | |
2292 | queue->ISR = GEM_ISR(hw_q - 1); | |
2293 | queue->IER = GEM_IER(hw_q - 1); | |
2294 | queue->IDR = GEM_IDR(hw_q - 1); | |
2295 | queue->IMR = GEM_IMR(hw_q - 1); | |
2296 | queue->TBQP = GEM_TBQP(hw_q - 1); | |
2297 | } else { | |
2298 | /* queue0 uses legacy registers */ | |
2299 | queue->ISR = MACB_ISR; | |
2300 | queue->IER = MACB_IER; | |
2301 | queue->IDR = MACB_IDR; | |
2302 | queue->IMR = MACB_IMR; | |
2303 | queue->TBQP = MACB_TBQP; | |
2304 | } | |
2305 | ||
2306 | /* get irq: here we use the linux queue index, not the hardware | |
2307 | * queue index. the queue irq definitions in the device tree | |
2308 | * must remove the optional gaps that could exist in the | |
2309 | * hardware queue mask. | |
2310 | */ | |
cf250de0 | 2311 | queue->irq = platform_get_irq(pdev, q); |
02c958dd CP |
2312 | err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt, |
2313 | 0, dev->name, queue); | |
2314 | if (err) { | |
2315 | dev_err(&pdev->dev, | |
2316 | "Unable to request IRQ %d (error %d)\n", | |
2317 | queue->irq, err); | |
cf250de0 | 2318 | goto err_out_free_netdev; |
02c958dd CP |
2319 | } |
2320 | ||
2321 | INIT_WORK(&queue->tx_error_task, macb_tx_error_task); | |
cf250de0 | 2322 | q++; |
89e5785f | 2323 | } |
02c958dd | 2324 | dev->irq = bp->queues[0].irq; |
89e5785f | 2325 | |
5f1fa992 | 2326 | dev->netdev_ops = &macb_netdev_ops; |
bea3348e | 2327 | netif_napi_add(dev, &bp->napi, macb_poll, 64); |
89e5785f HS |
2328 | dev->ethtool_ops = &macb_ethtool_ops; |
2329 | ||
2330 | dev->base_addr = regs->start; | |
2331 | ||
e175587f NF |
2332 | /* setup capacities */ |
2333 | macb_configure_caps(bp); | |
2334 | ||
4df95131 NF |
2335 | /* setup appropriated routines according to adapter type */ |
2336 | if (macb_is_gem(bp)) { | |
a4c35ed3 | 2337 | bp->max_tx_length = GEM_MAX_TX_LEN; |
4df95131 NF |
2338 | bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers; |
2339 | bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers; | |
2340 | bp->macbgem_ops.mog_init_rings = gem_init_rings; | |
2341 | bp->macbgem_ops.mog_rx = gem_rx; | |
2342 | } else { | |
a4c35ed3 | 2343 | bp->max_tx_length = MACB_MAX_TX_LEN; |
4df95131 NF |
2344 | bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers; |
2345 | bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers; | |
2346 | bp->macbgem_ops.mog_init_rings = macb_init_rings; | |
2347 | bp->macbgem_ops.mog_rx = macb_rx; | |
2348 | } | |
2349 | ||
a4c35ed3 CP |
2350 | /* Set features */ |
2351 | dev->hw_features = NETIF_F_SG; | |
85ff3d87 CP |
2352 | /* Checksum offload is only available on gem with packet buffer */ |
2353 | if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE)) | |
924ec53c | 2354 | dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM; |
a4c35ed3 CP |
2355 | if (bp->caps & MACB_CAPS_SG_DISABLED) |
2356 | dev->hw_features &= ~NETIF_F_SG; | |
2357 | dev->features = dev->hw_features; | |
2358 | ||
89e5785f | 2359 | /* Set MII management clock divider */ |
70c9f3d4 | 2360 | config = macb_mdc_clk_div(bp); |
757a03c6 | 2361 | config |= macb_dbw(bp); |
89e5785f HS |
2362 | macb_writel(bp, NCFGR, config); |
2363 | ||
50907043 GR |
2364 | mac = of_get_mac_address(pdev->dev.of_node); |
2365 | if (mac) | |
2366 | memcpy(bp->dev->dev_addr, mac, ETH_ALEN); | |
2367 | else | |
fb97a846 JCPV |
2368 | macb_get_hwaddr(bp); |
2369 | ||
50907043 | 2370 | err = of_get_phy_mode(pdev->dev.of_node); |
fb97a846 | 2371 | if (err < 0) { |
c607a0d9 | 2372 | pdata = dev_get_platdata(&pdev->dev); |
fb97a846 JCPV |
2373 | if (pdata && pdata->is_rmii) |
2374 | bp->phy_interface = PHY_INTERFACE_MODE_RMII; | |
2375 | else | |
2376 | bp->phy_interface = PHY_INTERFACE_MODE_MII; | |
2377 | } else { | |
2378 | bp->phy_interface = err; | |
2379 | } | |
6c36a707 | 2380 | |
140b7552 PV |
2381 | if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) |
2382 | macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII)); | |
2383 | else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) | |
0cc8674f | 2384 | #if defined(CONFIG_ARCH_AT91) |
f75ba50b JI |
2385 | macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) | |
2386 | MACB_BIT(CLKEN))); | |
0cc8674f | 2387 | #else |
f75ba50b | 2388 | macb_or_gem_writel(bp, USRIO, 0); |
0cc8674f | 2389 | #endif |
89e5785f | 2390 | else |
0cc8674f | 2391 | #if defined(CONFIG_ARCH_AT91) |
f75ba50b | 2392 | macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN)); |
0cc8674f | 2393 | #else |
f75ba50b | 2394 | macb_or_gem_writel(bp, USRIO, MACB_BIT(MII)); |
0cc8674f | 2395 | #endif |
89e5785f | 2396 | |
89e5785f HS |
2397 | err = register_netdev(dev); |
2398 | if (err) { | |
2399 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | |
cf250de0 | 2400 | goto err_out_free_netdev; |
89e5785f HS |
2401 | } |
2402 | ||
72ca820b NF |
2403 | err = macb_mii_init(bp); |
2404 | if (err) | |
6c36a707 | 2405 | goto err_out_unregister_netdev; |
89e5785f | 2406 | |
6c36a707 | 2407 | platform_set_drvdata(pdev, dev); |
89e5785f | 2408 | |
03fc4721 NF |
2409 | netif_carrier_off(dev); |
2410 | ||
5879823f BS |
2411 | netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n", |
2412 | macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID), | |
2413 | dev->base_addr, dev->irq, dev->dev_addr); | |
89e5785f | 2414 | |
6c36a707 | 2415 | phydev = bp->phy_dev; |
c220f8cd JI |
2416 | netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
2417 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
6c36a707 | 2418 | |
89e5785f HS |
2419 | return 0; |
2420 | ||
6c36a707 R |
2421 | err_out_unregister_netdev: |
2422 | unregister_netdev(dev); | |
cf250de0 | 2423 | err_out_free_netdev: |
02c958dd | 2424 | free_netdev(dev); |
89e5785f | 2425 | err_out_disable_clocks: |
02c958dd CP |
2426 | if (!IS_ERR(tx_clk)) |
2427 | clk_disable_unprepare(tx_clk); | |
e1824dfe | 2428 | err_out_disable_hclk: |
02c958dd | 2429 | clk_disable_unprepare(hclk); |
b48e0bab | 2430 | err_out_disable_pclk: |
02c958dd | 2431 | clk_disable_unprepare(pclk); |
89e5785f | 2432 | err_out: |
89e5785f HS |
2433 | return err; |
2434 | } | |
2435 | ||
06c3fd6a | 2436 | static int __exit macb_remove(struct platform_device *pdev) |
89e5785f HS |
2437 | { |
2438 | struct net_device *dev; | |
2439 | struct macb *bp; | |
2440 | ||
2441 | dev = platform_get_drvdata(pdev); | |
2442 | ||
2443 | if (dev) { | |
2444 | bp = netdev_priv(dev); | |
84b7901f AN |
2445 | if (bp->phy_dev) |
2446 | phy_disconnect(bp->phy_dev); | |
298cf9be LB |
2447 | mdiobus_unregister(bp->mii_bus); |
2448 | kfree(bp->mii_bus->irq); | |
2449 | mdiobus_free(bp->mii_bus); | |
89e5785f | 2450 | unregister_netdev(dev); |
e1824dfe SB |
2451 | if (!IS_ERR(bp->tx_clk)) |
2452 | clk_disable_unprepare(bp->tx_clk); | |
ace58010 | 2453 | clk_disable_unprepare(bp->hclk); |
ace58010 | 2454 | clk_disable_unprepare(bp->pclk); |
e965be7d | 2455 | free_netdev(dev); |
89e5785f HS |
2456 | } |
2457 | ||
2458 | return 0; | |
2459 | } | |
2460 | ||
c1f598fd | 2461 | #ifdef CONFIG_PM |
0dfc3e18 | 2462 | static int macb_suspend(struct device *dev) |
c1f598fd | 2463 | { |
0dfc3e18 | 2464 | struct platform_device *pdev = to_platform_device(dev); |
c1f598fd HS |
2465 | struct net_device *netdev = platform_get_drvdata(pdev); |
2466 | struct macb *bp = netdev_priv(netdev); | |
2467 | ||
03fc4721 | 2468 | netif_carrier_off(netdev); |
c1f598fd HS |
2469 | netif_device_detach(netdev); |
2470 | ||
e1824dfe SB |
2471 | if (!IS_ERR(bp->tx_clk)) |
2472 | clk_disable_unprepare(bp->tx_clk); | |
ace58010 ST |
2473 | clk_disable_unprepare(bp->hclk); |
2474 | clk_disable_unprepare(bp->pclk); | |
c1f598fd HS |
2475 | |
2476 | return 0; | |
2477 | } | |
2478 | ||
0dfc3e18 | 2479 | static int macb_resume(struct device *dev) |
c1f598fd | 2480 | { |
0dfc3e18 | 2481 | struct platform_device *pdev = to_platform_device(dev); |
c1f598fd HS |
2482 | struct net_device *netdev = platform_get_drvdata(pdev); |
2483 | struct macb *bp = netdev_priv(netdev); | |
2484 | ||
ace58010 ST |
2485 | clk_prepare_enable(bp->pclk); |
2486 | clk_prepare_enable(bp->hclk); | |
e1824dfe SB |
2487 | if (!IS_ERR(bp->tx_clk)) |
2488 | clk_prepare_enable(bp->tx_clk); | |
c1f598fd HS |
2489 | |
2490 | netif_device_attach(netdev); | |
2491 | ||
2492 | return 0; | |
2493 | } | |
c1f598fd HS |
2494 | #endif |
2495 | ||
0dfc3e18 SB |
2496 | static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume); |
2497 | ||
89e5785f | 2498 | static struct platform_driver macb_driver = { |
06c3fd6a | 2499 | .remove = __exit_p(macb_remove), |
89e5785f HS |
2500 | .driver = { |
2501 | .name = "macb", | |
fb97a846 | 2502 | .of_match_table = of_match_ptr(macb_dt_ids), |
0dfc3e18 | 2503 | .pm = &macb_pm_ops, |
89e5785f HS |
2504 | }, |
2505 | }; | |
2506 | ||
b543a8d8 | 2507 | module_platform_driver_probe(macb_driver, macb_probe); |
89e5785f HS |
2508 | |
2509 | MODULE_LICENSE("GPL"); | |
f75ba50b | 2510 | MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); |
e05503ef | 2511 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
72abb461 | 2512 | MODULE_ALIAS("platform:macb"); |