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Commit | Line | Data |
---|---|---|
89e5785f | 1 | /* |
f75ba50b | 2 | * Cadence MACB/GEM Ethernet Controller driver |
89e5785f HS |
3 | * |
4 | * Copyright (C) 2004-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
c220f8cd | 11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
89e5785f HS |
12 | #include <linux/clk.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/init.h> | |
a6b7a407 | 19 | #include <linux/interrupt.h> |
89e5785f HS |
20 | #include <linux/netdevice.h> |
21 | #include <linux/etherdevice.h> | |
89e5785f | 22 | #include <linux/dma-mapping.h> |
84e0cdb0 | 23 | #include <linux/platform_data/macb.h> |
89e5785f | 24 | #include <linux/platform_device.h> |
6c36a707 | 25 | #include <linux/phy.h> |
b17471f5 | 26 | #include <linux/of.h> |
fb97a846 JCPV |
27 | #include <linux/of_device.h> |
28 | #include <linux/of_net.h> | |
89e5785f | 29 | |
89e5785f HS |
30 | #include "macb.h" |
31 | ||
89e5785f | 32 | #define RX_BUFFER_SIZE 128 |
55054a16 HS |
33 | #define RX_RING_SIZE 512 /* must be power of 2 */ |
34 | #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE) | |
89e5785f HS |
35 | |
36 | /* Make the IP header word-aligned (the ethernet header is 14 bytes) */ | |
37 | #define RX_OFFSET 2 | |
38 | ||
55054a16 HS |
39 | #define TX_RING_SIZE 128 /* must be power of 2 */ |
40 | #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE) | |
89e5785f HS |
41 | |
42 | /* minimum number of free TX descriptors before waking up TX process */ | |
43 | #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4) | |
44 | ||
45 | #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ | |
46 | | MACB_BIT(ISR_ROVR)) | |
47 | ||
55054a16 HS |
48 | /* Ring buffer accessors */ |
49 | static unsigned int macb_tx_ring_wrap(unsigned int index) | |
50 | { | |
51 | return index & (TX_RING_SIZE - 1); | |
52 | } | |
53 | ||
54 | static unsigned int macb_tx_ring_avail(struct macb *bp) | |
55 | { | |
56 | return (bp->tx_tail - bp->tx_head) & (TX_RING_SIZE - 1); | |
57 | } | |
58 | ||
59 | static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index) | |
60 | { | |
61 | return &bp->tx_ring[macb_tx_ring_wrap(index)]; | |
62 | } | |
63 | ||
64 | static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index) | |
65 | { | |
66 | return &bp->tx_skb[macb_tx_ring_wrap(index)]; | |
67 | } | |
68 | ||
69 | static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index) | |
70 | { | |
71 | dma_addr_t offset; | |
72 | ||
73 | offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc); | |
74 | ||
75 | return bp->tx_ring_dma + offset; | |
76 | } | |
77 | ||
78 | static unsigned int macb_rx_ring_wrap(unsigned int index) | |
79 | { | |
80 | return index & (RX_RING_SIZE - 1); | |
81 | } | |
82 | ||
83 | static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index) | |
84 | { | |
85 | return &bp->rx_ring[macb_rx_ring_wrap(index)]; | |
86 | } | |
87 | ||
88 | static void *macb_rx_buffer(struct macb *bp, unsigned int index) | |
89 | { | |
90 | return bp->rx_buffers + RX_BUFFER_SIZE * macb_rx_ring_wrap(index); | |
91 | } | |
92 | ||
89e5785f HS |
93 | static void __macb_set_hwaddr(struct macb *bp) |
94 | { | |
95 | u32 bottom; | |
96 | u16 top; | |
97 | ||
98 | bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); | |
f75ba50b | 99 | macb_or_gem_writel(bp, SA1B, bottom); |
89e5785f | 100 | top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); |
f75ba50b | 101 | macb_or_gem_writel(bp, SA1T, top); |
89e5785f HS |
102 | } |
103 | ||
104 | static void __init macb_get_hwaddr(struct macb *bp) | |
105 | { | |
106 | u32 bottom; | |
107 | u16 top; | |
108 | u8 addr[6]; | |
109 | ||
f75ba50b JI |
110 | bottom = macb_or_gem_readl(bp, SA1B); |
111 | top = macb_or_gem_readl(bp, SA1T); | |
89e5785f HS |
112 | |
113 | addr[0] = bottom & 0xff; | |
114 | addr[1] = (bottom >> 8) & 0xff; | |
115 | addr[2] = (bottom >> 16) & 0xff; | |
116 | addr[3] = (bottom >> 24) & 0xff; | |
117 | addr[4] = top & 0xff; | |
118 | addr[5] = (top >> 8) & 0xff; | |
119 | ||
d1d5741d | 120 | if (is_valid_ether_addr(addr)) { |
89e5785f | 121 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); |
d1d5741d | 122 | } else { |
c220f8cd | 123 | netdev_info(bp->dev, "invalid hw address, using random\n"); |
f2cedb63 | 124 | eth_hw_addr_random(bp->dev); |
d1d5741d | 125 | } |
89e5785f HS |
126 | } |
127 | ||
6c36a707 | 128 | static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
89e5785f | 129 | { |
6c36a707 | 130 | struct macb *bp = bus->priv; |
89e5785f HS |
131 | int value; |
132 | ||
89e5785f HS |
133 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) |
134 | | MACB_BF(RW, MACB_MAN_READ) | |
6c36a707 R |
135 | | MACB_BF(PHYA, mii_id) |
136 | | MACB_BF(REGA, regnum) | |
89e5785f HS |
137 | | MACB_BF(CODE, MACB_MAN_CODE))); |
138 | ||
6c36a707 R |
139 | /* wait for end of transfer */ |
140 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
141 | cpu_relax(); | |
89e5785f HS |
142 | |
143 | value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); | |
89e5785f HS |
144 | |
145 | return value; | |
146 | } | |
147 | ||
6c36a707 R |
148 | static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
149 | u16 value) | |
89e5785f | 150 | { |
6c36a707 | 151 | struct macb *bp = bus->priv; |
89e5785f HS |
152 | |
153 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) | |
154 | | MACB_BF(RW, MACB_MAN_WRITE) | |
6c36a707 R |
155 | | MACB_BF(PHYA, mii_id) |
156 | | MACB_BF(REGA, regnum) | |
89e5785f | 157 | | MACB_BF(CODE, MACB_MAN_CODE) |
6c36a707 | 158 | | MACB_BF(DATA, value))); |
89e5785f | 159 | |
6c36a707 R |
160 | /* wait for end of transfer */ |
161 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
162 | cpu_relax(); | |
163 | ||
164 | return 0; | |
165 | } | |
89e5785f | 166 | |
6c36a707 R |
167 | static int macb_mdio_reset(struct mii_bus *bus) |
168 | { | |
169 | return 0; | |
89e5785f HS |
170 | } |
171 | ||
6c36a707 | 172 | static void macb_handle_link_change(struct net_device *dev) |
89e5785f | 173 | { |
6c36a707 R |
174 | struct macb *bp = netdev_priv(dev); |
175 | struct phy_device *phydev = bp->phy_dev; | |
176 | unsigned long flags; | |
89e5785f | 177 | |
6c36a707 | 178 | int status_change = 0; |
89e5785f | 179 | |
6c36a707 R |
180 | spin_lock_irqsave(&bp->lock, flags); |
181 | ||
182 | if (phydev->link) { | |
183 | if ((bp->speed != phydev->speed) || | |
184 | (bp->duplex != phydev->duplex)) { | |
185 | u32 reg; | |
186 | ||
187 | reg = macb_readl(bp, NCFGR); | |
188 | reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); | |
140b7552 PV |
189 | if (macb_is_gem(bp)) |
190 | reg &= ~GEM_BIT(GBE); | |
6c36a707 R |
191 | |
192 | if (phydev->duplex) | |
193 | reg |= MACB_BIT(FD); | |
179956f4 | 194 | if (phydev->speed == SPEED_100) |
6c36a707 | 195 | reg |= MACB_BIT(SPD); |
140b7552 PV |
196 | if (phydev->speed == SPEED_1000) |
197 | reg |= GEM_BIT(GBE); | |
6c36a707 | 198 | |
140b7552 | 199 | macb_or_gem_writel(bp, NCFGR, reg); |
6c36a707 R |
200 | |
201 | bp->speed = phydev->speed; | |
202 | bp->duplex = phydev->duplex; | |
203 | status_change = 1; | |
204 | } | |
89e5785f HS |
205 | } |
206 | ||
6c36a707 | 207 | if (phydev->link != bp->link) { |
c8f15686 | 208 | if (!phydev->link) { |
6c36a707 R |
209 | bp->speed = 0; |
210 | bp->duplex = -1; | |
211 | } | |
212 | bp->link = phydev->link; | |
89e5785f | 213 | |
6c36a707 R |
214 | status_change = 1; |
215 | } | |
89e5785f | 216 | |
6c36a707 R |
217 | spin_unlock_irqrestore(&bp->lock, flags); |
218 | ||
219 | if (status_change) { | |
03fc4721 NF |
220 | if (phydev->link) { |
221 | netif_carrier_on(dev); | |
c220f8cd JI |
222 | netdev_info(dev, "link up (%d/%s)\n", |
223 | phydev->speed, | |
224 | phydev->duplex == DUPLEX_FULL ? | |
225 | "Full" : "Half"); | |
03fc4721 NF |
226 | } else { |
227 | netif_carrier_off(dev); | |
c220f8cd | 228 | netdev_info(dev, "link down\n"); |
03fc4721 | 229 | } |
6c36a707 | 230 | } |
89e5785f HS |
231 | } |
232 | ||
6c36a707 R |
233 | /* based on au1000_eth. c*/ |
234 | static int macb_mii_probe(struct net_device *dev) | |
89e5785f | 235 | { |
6c36a707 | 236 | struct macb *bp = netdev_priv(dev); |
7455a76f | 237 | struct phy_device *phydev; |
7455a76f | 238 | int ret; |
6c36a707 | 239 | |
7455a76f | 240 | phydev = phy_find_first(bp->mii_bus); |
6c36a707 | 241 | if (!phydev) { |
c220f8cd | 242 | netdev_err(dev, "no PHY found\n"); |
6c36a707 R |
243 | return -1; |
244 | } | |
245 | ||
6c36a707 R |
246 | /* TODO : add pin_irq */ |
247 | ||
248 | /* attach the mac to the phy */ | |
7455a76f | 249 | ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0, |
fb97a846 | 250 | bp->phy_interface); |
7455a76f | 251 | if (ret) { |
c220f8cd | 252 | netdev_err(dev, "Could not attach to PHY\n"); |
7455a76f | 253 | return ret; |
6c36a707 R |
254 | } |
255 | ||
256 | /* mask with MAC supported features */ | |
140b7552 PV |
257 | if (macb_is_gem(bp)) |
258 | phydev->supported &= PHY_GBIT_FEATURES; | |
259 | else | |
260 | phydev->supported &= PHY_BASIC_FEATURES; | |
6c36a707 R |
261 | |
262 | phydev->advertising = phydev->supported; | |
263 | ||
264 | bp->link = 0; | |
265 | bp->speed = 0; | |
266 | bp->duplex = -1; | |
267 | bp->phy_dev = phydev; | |
268 | ||
269 | return 0; | |
89e5785f HS |
270 | } |
271 | ||
0005f541 | 272 | int macb_mii_init(struct macb *bp) |
89e5785f | 273 | { |
84e0cdb0 | 274 | struct macb_platform_data *pdata; |
6c36a707 | 275 | int err = -ENXIO, i; |
89e5785f | 276 | |
3dbda77e | 277 | /* Enable management port */ |
6c36a707 | 278 | macb_writel(bp, NCR, MACB_BIT(MPE)); |
89e5785f | 279 | |
298cf9be LB |
280 | bp->mii_bus = mdiobus_alloc(); |
281 | if (bp->mii_bus == NULL) { | |
282 | err = -ENOMEM; | |
283 | goto err_out; | |
284 | } | |
285 | ||
286 | bp->mii_bus->name = "MACB_mii_bus"; | |
287 | bp->mii_bus->read = &macb_mdio_read; | |
288 | bp->mii_bus->write = &macb_mdio_write; | |
289 | bp->mii_bus->reset = &macb_mdio_reset; | |
98d5e57e FF |
290 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
291 | bp->pdev->name, bp->pdev->id); | |
298cf9be LB |
292 | bp->mii_bus->priv = bp; |
293 | bp->mii_bus->parent = &bp->dev->dev; | |
6c36a707 | 294 | pdata = bp->pdev->dev.platform_data; |
89e5785f | 295 | |
6c36a707 | 296 | if (pdata) |
298cf9be | 297 | bp->mii_bus->phy_mask = pdata->phy_mask; |
89e5785f | 298 | |
298cf9be LB |
299 | bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
300 | if (!bp->mii_bus->irq) { | |
6c36a707 | 301 | err = -ENOMEM; |
298cf9be | 302 | goto err_out_free_mdiobus; |
89e5785f HS |
303 | } |
304 | ||
6c36a707 | 305 | for (i = 0; i < PHY_MAX_ADDR; i++) |
298cf9be | 306 | bp->mii_bus->irq[i] = PHY_POLL; |
89e5785f | 307 | |
91523947 | 308 | dev_set_drvdata(&bp->dev->dev, bp->mii_bus); |
89e5785f | 309 | |
298cf9be | 310 | if (mdiobus_register(bp->mii_bus)) |
6c36a707 | 311 | goto err_out_free_mdio_irq; |
89e5785f | 312 | |
6c36a707 R |
313 | if (macb_mii_probe(bp->dev) != 0) { |
314 | goto err_out_unregister_bus; | |
315 | } | |
89e5785f | 316 | |
6c36a707 | 317 | return 0; |
89e5785f | 318 | |
6c36a707 | 319 | err_out_unregister_bus: |
298cf9be | 320 | mdiobus_unregister(bp->mii_bus); |
6c36a707 | 321 | err_out_free_mdio_irq: |
298cf9be LB |
322 | kfree(bp->mii_bus->irq); |
323 | err_out_free_mdiobus: | |
324 | mdiobus_free(bp->mii_bus); | |
6c36a707 R |
325 | err_out: |
326 | return err; | |
89e5785f | 327 | } |
0005f541 | 328 | EXPORT_SYMBOL_GPL(macb_mii_init); |
89e5785f HS |
329 | |
330 | static void macb_update_stats(struct macb *bp) | |
331 | { | |
332 | u32 __iomem *reg = bp->regs + MACB_PFR; | |
a494ed8e JI |
333 | u32 *p = &bp->hw_stats.macb.rx_pause_frames; |
334 | u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; | |
89e5785f HS |
335 | |
336 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | |
337 | ||
338 | for(; p < end; p++, reg++) | |
0f0d84e5 | 339 | *p += __raw_readl(reg); |
89e5785f HS |
340 | } |
341 | ||
89e5785f HS |
342 | static void macb_tx(struct macb *bp) |
343 | { | |
344 | unsigned int tail; | |
345 | unsigned int head; | |
346 | u32 status; | |
347 | ||
348 | status = macb_readl(bp, TSR); | |
349 | macb_writel(bp, TSR, status); | |
350 | ||
cde30a85 | 351 | netdev_vdbg(bp->dev, "macb_tx status = 0x%03lx\n", (unsigned long)status); |
89e5785f | 352 | |
ee33c585 | 353 | if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) { |
bdcba151 | 354 | int i; |
c220f8cd JI |
355 | netdev_err(bp->dev, "TX %s, resetting buffers\n", |
356 | status & MACB_BIT(UND) ? | |
357 | "underrun" : "retry limit exceeded"); | |
bdcba151 | 358 | |
39eddb4c RR |
359 | /* Transfer ongoing, disable transmitter, to avoid confusion */ |
360 | if (status & MACB_BIT(TGO)) | |
361 | macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE)); | |
362 | ||
bdcba151 GC |
363 | head = bp->tx_head; |
364 | ||
365 | /*Mark all the buffer as used to avoid sending a lost buffer*/ | |
366 | for (i = 0; i < TX_RING_SIZE; i++) | |
367 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
368 | ||
d3e61457 TA |
369 | /* Add wrap bit */ |
370 | bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
371 | ||
bdcba151 | 372 | /* free transmit buffer in upper layer*/ |
55054a16 HS |
373 | for (tail = bp->tx_tail; tail != head; tail++) { |
374 | struct macb_tx_skb *tx_skb; | |
375 | struct sk_buff *skb; | |
bdcba151 GC |
376 | |
377 | rmb(); | |
378 | ||
55054a16 HS |
379 | tx_skb = macb_tx_skb(bp, tail); |
380 | skb = tx_skb->skb; | |
381 | ||
382 | dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, | |
383 | skb->len, DMA_TO_DEVICE); | |
384 | tx_skb->skb = NULL; | |
bdcba151 GC |
385 | dev_kfree_skb_irq(skb); |
386 | } | |
387 | ||
89e5785f | 388 | bp->tx_head = bp->tx_tail = 0; |
39eddb4c RR |
389 | |
390 | /* Enable the transmitter again */ | |
391 | if (status & MACB_BIT(TGO)) | |
392 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE)); | |
89e5785f HS |
393 | } |
394 | ||
395 | if (!(status & MACB_BIT(COMP))) | |
396 | /* | |
397 | * This may happen when a buffer becomes complete | |
398 | * between reading the ISR and scanning the | |
399 | * descriptors. Nothing to worry about. | |
400 | */ | |
401 | return; | |
402 | ||
403 | head = bp->tx_head; | |
55054a16 HS |
404 | for (tail = bp->tx_tail; tail != head; tail++) { |
405 | struct macb_tx_skb *tx_skb; | |
406 | struct sk_buff *skb; | |
407 | struct macb_dma_desc *desc; | |
408 | u32 ctrl; | |
89e5785f | 409 | |
55054a16 | 410 | desc = macb_tx_desc(bp, tail); |
89e5785f | 411 | |
03dbe05f | 412 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 413 | rmb(); |
03dbe05f | 414 | |
55054a16 | 415 | ctrl = desc->ctrl; |
89e5785f | 416 | |
55054a16 | 417 | if (!(ctrl & MACB_BIT(TX_USED))) |
89e5785f HS |
418 | break; |
419 | ||
55054a16 HS |
420 | tx_skb = macb_tx_skb(bp, tail); |
421 | skb = tx_skb->skb; | |
422 | ||
a268adb1 | 423 | netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", |
55054a16 HS |
424 | macb_tx_ring_wrap(tail), skb->data); |
425 | dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len, | |
89e5785f HS |
426 | DMA_TO_DEVICE); |
427 | bp->stats.tx_packets++; | |
428 | bp->stats.tx_bytes += skb->len; | |
55054a16 | 429 | tx_skb->skb = NULL; |
89e5785f HS |
430 | dev_kfree_skb_irq(skb); |
431 | } | |
432 | ||
433 | bp->tx_tail = tail; | |
55054a16 HS |
434 | if (netif_queue_stopped(bp->dev) |
435 | && macb_tx_ring_avail(bp) > MACB_TX_WAKEUP_THRESH) | |
89e5785f HS |
436 | netif_wake_queue(bp->dev); |
437 | } | |
438 | ||
439 | static int macb_rx_frame(struct macb *bp, unsigned int first_frag, | |
440 | unsigned int last_frag) | |
441 | { | |
442 | unsigned int len; | |
443 | unsigned int frag; | |
444 | unsigned int offset = 0; | |
445 | struct sk_buff *skb; | |
55054a16 | 446 | struct macb_dma_desc *desc; |
89e5785f | 447 | |
55054a16 HS |
448 | desc = macb_rx_desc(bp, last_frag); |
449 | len = MACB_BFEXT(RX_FRMLEN, desc->ctrl); | |
89e5785f | 450 | |
a268adb1 | 451 | netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", |
55054a16 HS |
452 | macb_rx_ring_wrap(first_frag), |
453 | macb_rx_ring_wrap(last_frag), len); | |
89e5785f | 454 | |
21a4e469 | 455 | skb = netdev_alloc_skb(bp->dev, len + RX_OFFSET); |
89e5785f HS |
456 | if (!skb) { |
457 | bp->stats.rx_dropped++; | |
55054a16 HS |
458 | for (frag = first_frag; ; frag++) { |
459 | desc = macb_rx_desc(bp, frag); | |
460 | desc->addr &= ~MACB_BIT(RX_USED); | |
89e5785f HS |
461 | if (frag == last_frag) |
462 | break; | |
463 | } | |
03dbe05f HS |
464 | |
465 | /* Make descriptor updates visible to hardware */ | |
89e5785f | 466 | wmb(); |
03dbe05f | 467 | |
89e5785f HS |
468 | return 1; |
469 | } | |
470 | ||
471 | skb_reserve(skb, RX_OFFSET); | |
bc8acf2c | 472 | skb_checksum_none_assert(skb); |
89e5785f HS |
473 | skb_put(skb, len); |
474 | ||
55054a16 | 475 | for (frag = first_frag; ; frag++) { |
89e5785f HS |
476 | unsigned int frag_len = RX_BUFFER_SIZE; |
477 | ||
478 | if (offset + frag_len > len) { | |
479 | BUG_ON(frag != last_frag); | |
480 | frag_len = len - offset; | |
481 | } | |
27d7ff46 | 482 | skb_copy_to_linear_data_offset(skb, offset, |
55054a16 | 483 | macb_rx_buffer(bp, frag), frag_len); |
89e5785f | 484 | offset += RX_BUFFER_SIZE; |
55054a16 HS |
485 | desc = macb_rx_desc(bp, frag); |
486 | desc->addr &= ~MACB_BIT(RX_USED); | |
89e5785f HS |
487 | |
488 | if (frag == last_frag) | |
489 | break; | |
490 | } | |
491 | ||
03dbe05f HS |
492 | /* Make descriptor updates visible to hardware */ |
493 | wmb(); | |
494 | ||
89e5785f HS |
495 | skb->protocol = eth_type_trans(skb, bp->dev); |
496 | ||
497 | bp->stats.rx_packets++; | |
498 | bp->stats.rx_bytes += len; | |
a268adb1 | 499 | netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", |
c220f8cd | 500 | skb->len, skb->csum); |
89e5785f HS |
501 | netif_receive_skb(skb); |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | /* Mark DMA descriptors from begin up to and not including end as unused */ | |
507 | static void discard_partial_frame(struct macb *bp, unsigned int begin, | |
508 | unsigned int end) | |
509 | { | |
510 | unsigned int frag; | |
511 | ||
55054a16 HS |
512 | for (frag = begin; frag != end; frag++) { |
513 | struct macb_dma_desc *desc = macb_rx_desc(bp, frag); | |
514 | desc->addr &= ~MACB_BIT(RX_USED); | |
515 | } | |
03dbe05f HS |
516 | |
517 | /* Make descriptor updates visible to hardware */ | |
89e5785f HS |
518 | wmb(); |
519 | ||
520 | /* | |
521 | * When this happens, the hardware stats registers for | |
522 | * whatever caused this is updated, so we don't have to record | |
523 | * anything. | |
524 | */ | |
525 | } | |
526 | ||
527 | static int macb_rx(struct macb *bp, int budget) | |
528 | { | |
529 | int received = 0; | |
55054a16 | 530 | unsigned int tail; |
89e5785f HS |
531 | int first_frag = -1; |
532 | ||
55054a16 HS |
533 | for (tail = bp->rx_tail; budget > 0; tail++) { |
534 | struct macb_dma_desc *desc = macb_rx_desc(bp, tail); | |
89e5785f HS |
535 | u32 addr, ctrl; |
536 | ||
03dbe05f | 537 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 538 | rmb(); |
03dbe05f | 539 | |
55054a16 HS |
540 | addr = desc->addr; |
541 | ctrl = desc->ctrl; | |
89e5785f HS |
542 | |
543 | if (!(addr & MACB_BIT(RX_USED))) | |
544 | break; | |
545 | ||
546 | if (ctrl & MACB_BIT(RX_SOF)) { | |
547 | if (first_frag != -1) | |
548 | discard_partial_frame(bp, first_frag, tail); | |
549 | first_frag = tail; | |
550 | } | |
551 | ||
552 | if (ctrl & MACB_BIT(RX_EOF)) { | |
553 | int dropped; | |
554 | BUG_ON(first_frag == -1); | |
555 | ||
556 | dropped = macb_rx_frame(bp, first_frag, tail); | |
557 | first_frag = -1; | |
558 | if (!dropped) { | |
559 | received++; | |
560 | budget--; | |
561 | } | |
562 | } | |
563 | } | |
564 | ||
565 | if (first_frag != -1) | |
566 | bp->rx_tail = first_frag; | |
567 | else | |
568 | bp->rx_tail = tail; | |
569 | ||
570 | return received; | |
571 | } | |
572 | ||
bea3348e | 573 | static int macb_poll(struct napi_struct *napi, int budget) |
89e5785f | 574 | { |
bea3348e | 575 | struct macb *bp = container_of(napi, struct macb, napi); |
bea3348e | 576 | int work_done; |
89e5785f HS |
577 | u32 status; |
578 | ||
579 | status = macb_readl(bp, RSR); | |
580 | macb_writel(bp, RSR, status); | |
581 | ||
bea3348e | 582 | work_done = 0; |
89e5785f | 583 | |
a268adb1 | 584 | netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n", |
c220f8cd | 585 | (unsigned long)status, budget); |
89e5785f | 586 | |
bea3348e | 587 | work_done = macb_rx(bp, budget); |
b336369c | 588 | if (work_done < budget) { |
288379f0 | 589 | napi_complete(napi); |
89e5785f | 590 | |
b336369c JH |
591 | /* |
592 | * We've done what we can to clean the buffers. Make sure we | |
593 | * get notified when new packets arrive. | |
594 | */ | |
595 | macb_writel(bp, IER, MACB_RX_INT_FLAGS); | |
596 | } | |
89e5785f HS |
597 | |
598 | /* TODO: Handle errors */ | |
599 | ||
bea3348e | 600 | return work_done; |
89e5785f HS |
601 | } |
602 | ||
603 | static irqreturn_t macb_interrupt(int irq, void *dev_id) | |
604 | { | |
605 | struct net_device *dev = dev_id; | |
606 | struct macb *bp = netdev_priv(dev); | |
607 | u32 status; | |
608 | ||
609 | status = macb_readl(bp, ISR); | |
610 | ||
611 | if (unlikely(!status)) | |
612 | return IRQ_NONE; | |
613 | ||
614 | spin_lock(&bp->lock); | |
615 | ||
616 | while (status) { | |
89e5785f HS |
617 | /* close possible race with dev_close */ |
618 | if (unlikely(!netif_running(dev))) { | |
95ebcea6 | 619 | macb_writel(bp, IDR, -1); |
89e5785f HS |
620 | break; |
621 | } | |
622 | ||
a268adb1 HS |
623 | netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status); |
624 | ||
89e5785f | 625 | if (status & MACB_RX_INT_FLAGS) { |
b336369c JH |
626 | /* |
627 | * There's no point taking any more interrupts | |
628 | * until we have processed the buffers. The | |
629 | * scheduling call may fail if the poll routine | |
630 | * is already scheduled, so disable interrupts | |
631 | * now. | |
632 | */ | |
633 | macb_writel(bp, IDR, MACB_RX_INT_FLAGS); | |
634 | ||
288379f0 | 635 | if (napi_schedule_prep(&bp->napi)) { |
a268adb1 | 636 | netdev_vdbg(bp->dev, "scheduling RX softirq\n"); |
288379f0 | 637 | __napi_schedule(&bp->napi); |
89e5785f HS |
638 | } |
639 | } | |
640 | ||
ee33c585 EW |
641 | if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | |
642 | MACB_BIT(ISR_RLE))) | |
89e5785f HS |
643 | macb_tx(bp); |
644 | ||
645 | /* | |
646 | * Link change detection isn't possible with RMII, so we'll | |
647 | * add that if/when we get our hands on a full-blown MII PHY. | |
648 | */ | |
649 | ||
b19f7f71 AS |
650 | if (status & MACB_BIT(ISR_ROVR)) { |
651 | /* We missed at least one packet */ | |
f75ba50b JI |
652 | if (macb_is_gem(bp)) |
653 | bp->hw_stats.gem.rx_overruns++; | |
654 | else | |
655 | bp->hw_stats.macb.rx_overruns++; | |
b19f7f71 AS |
656 | } |
657 | ||
89e5785f HS |
658 | if (status & MACB_BIT(HRESP)) { |
659 | /* | |
c220f8cd JI |
660 | * TODO: Reset the hardware, and maybe move the |
661 | * netdev_err to a lower-priority context as well | |
662 | * (work queue?) | |
89e5785f | 663 | */ |
c220f8cd | 664 | netdev_err(dev, "DMA bus error: HRESP not OK\n"); |
89e5785f HS |
665 | } |
666 | ||
667 | status = macb_readl(bp, ISR); | |
668 | } | |
669 | ||
670 | spin_unlock(&bp->lock); | |
671 | ||
672 | return IRQ_HANDLED; | |
673 | } | |
674 | ||
6e8cf5c0 TP |
675 | #ifdef CONFIG_NET_POLL_CONTROLLER |
676 | /* | |
677 | * Polling receive - used by netconsole and other diagnostic tools | |
678 | * to allow network i/o with interrupts disabled. | |
679 | */ | |
680 | static void macb_poll_controller(struct net_device *dev) | |
681 | { | |
682 | unsigned long flags; | |
683 | ||
684 | local_irq_save(flags); | |
685 | macb_interrupt(dev->irq, dev); | |
686 | local_irq_restore(flags); | |
687 | } | |
688 | #endif | |
689 | ||
89e5785f HS |
690 | static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) |
691 | { | |
692 | struct macb *bp = netdev_priv(dev); | |
693 | dma_addr_t mapping; | |
694 | unsigned int len, entry; | |
55054a16 HS |
695 | struct macb_dma_desc *desc; |
696 | struct macb_tx_skb *tx_skb; | |
89e5785f | 697 | u32 ctrl; |
4871953c | 698 | unsigned long flags; |
89e5785f | 699 | |
a268adb1 HS |
700 | #if defined(DEBUG) && defined(VERBOSE_DEBUG) |
701 | netdev_vdbg(bp->dev, | |
c220f8cd JI |
702 | "start_xmit: len %u head %p data %p tail %p end %p\n", |
703 | skb->len, skb->head, skb->data, | |
704 | skb_tail_pointer(skb), skb_end_pointer(skb)); | |
705 | print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, | |
706 | skb->data, 16, true); | |
89e5785f HS |
707 | #endif |
708 | ||
709 | len = skb->len; | |
4871953c | 710 | spin_lock_irqsave(&bp->lock, flags); |
89e5785f HS |
711 | |
712 | /* This is a hard error, log it. */ | |
55054a16 | 713 | if (macb_tx_ring_avail(bp) < 1) { |
89e5785f | 714 | netif_stop_queue(dev); |
4871953c | 715 | spin_unlock_irqrestore(&bp->lock, flags); |
c220f8cd JI |
716 | netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n"); |
717 | netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", | |
718 | bp->tx_head, bp->tx_tail); | |
5b548140 | 719 | return NETDEV_TX_BUSY; |
89e5785f HS |
720 | } |
721 | ||
55054a16 HS |
722 | entry = macb_tx_ring_wrap(bp->tx_head); |
723 | bp->tx_head++; | |
a268adb1 | 724 | netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry); |
89e5785f HS |
725 | mapping = dma_map_single(&bp->pdev->dev, skb->data, |
726 | len, DMA_TO_DEVICE); | |
55054a16 HS |
727 | |
728 | tx_skb = &bp->tx_skb[entry]; | |
729 | tx_skb->skb = skb; | |
730 | tx_skb->mapping = mapping; | |
a268adb1 | 731 | netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n", |
c220f8cd | 732 | skb->data, (unsigned long)mapping); |
89e5785f HS |
733 | |
734 | ctrl = MACB_BF(TX_FRMLEN, len); | |
735 | ctrl |= MACB_BIT(TX_LAST); | |
736 | if (entry == (TX_RING_SIZE - 1)) | |
737 | ctrl |= MACB_BIT(TX_WRAP); | |
738 | ||
55054a16 HS |
739 | desc = &bp->tx_ring[entry]; |
740 | desc->addr = mapping; | |
741 | desc->ctrl = ctrl; | |
03dbe05f HS |
742 | |
743 | /* Make newly initialized descriptor visible to hardware */ | |
89e5785f HS |
744 | wmb(); |
745 | ||
e072092f RC |
746 | skb_tx_timestamp(skb); |
747 | ||
89e5785f HS |
748 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); |
749 | ||
55054a16 | 750 | if (macb_tx_ring_avail(bp) < 1) |
89e5785f HS |
751 | netif_stop_queue(dev); |
752 | ||
4871953c | 753 | spin_unlock_irqrestore(&bp->lock, flags); |
89e5785f | 754 | |
6ed10654 | 755 | return NETDEV_TX_OK; |
89e5785f HS |
756 | } |
757 | ||
758 | static void macb_free_consistent(struct macb *bp) | |
759 | { | |
760 | if (bp->tx_skb) { | |
761 | kfree(bp->tx_skb); | |
762 | bp->tx_skb = NULL; | |
763 | } | |
764 | if (bp->rx_ring) { | |
765 | dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, | |
766 | bp->rx_ring, bp->rx_ring_dma); | |
767 | bp->rx_ring = NULL; | |
768 | } | |
769 | if (bp->tx_ring) { | |
770 | dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, | |
771 | bp->tx_ring, bp->tx_ring_dma); | |
772 | bp->tx_ring = NULL; | |
773 | } | |
774 | if (bp->rx_buffers) { | |
775 | dma_free_coherent(&bp->pdev->dev, | |
776 | RX_RING_SIZE * RX_BUFFER_SIZE, | |
777 | bp->rx_buffers, bp->rx_buffers_dma); | |
778 | bp->rx_buffers = NULL; | |
779 | } | |
780 | } | |
781 | ||
782 | static int macb_alloc_consistent(struct macb *bp) | |
783 | { | |
784 | int size; | |
785 | ||
55054a16 | 786 | size = TX_RING_SIZE * sizeof(struct macb_tx_skb); |
89e5785f HS |
787 | bp->tx_skb = kmalloc(size, GFP_KERNEL); |
788 | if (!bp->tx_skb) | |
789 | goto out_err; | |
790 | ||
791 | size = RX_RING_BYTES; | |
792 | bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
793 | &bp->rx_ring_dma, GFP_KERNEL); | |
794 | if (!bp->rx_ring) | |
795 | goto out_err; | |
c220f8cd JI |
796 | netdev_dbg(bp->dev, |
797 | "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", | |
798 | size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); | |
89e5785f HS |
799 | |
800 | size = TX_RING_BYTES; | |
801 | bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
802 | &bp->tx_ring_dma, GFP_KERNEL); | |
803 | if (!bp->tx_ring) | |
804 | goto out_err; | |
c220f8cd JI |
805 | netdev_dbg(bp->dev, |
806 | "Allocated TX ring of %d bytes at %08lx (mapped %p)\n", | |
807 | size, (unsigned long)bp->tx_ring_dma, bp->tx_ring); | |
89e5785f HS |
808 | |
809 | size = RX_RING_SIZE * RX_BUFFER_SIZE; | |
810 | bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, | |
811 | &bp->rx_buffers_dma, GFP_KERNEL); | |
812 | if (!bp->rx_buffers) | |
813 | goto out_err; | |
c220f8cd JI |
814 | netdev_dbg(bp->dev, |
815 | "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", | |
816 | size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); | |
89e5785f HS |
817 | |
818 | return 0; | |
819 | ||
820 | out_err: | |
821 | macb_free_consistent(bp); | |
822 | return -ENOMEM; | |
823 | } | |
824 | ||
825 | static void macb_init_rings(struct macb *bp) | |
826 | { | |
827 | int i; | |
828 | dma_addr_t addr; | |
829 | ||
830 | addr = bp->rx_buffers_dma; | |
831 | for (i = 0; i < RX_RING_SIZE; i++) { | |
832 | bp->rx_ring[i].addr = addr; | |
833 | bp->rx_ring[i].ctrl = 0; | |
834 | addr += RX_BUFFER_SIZE; | |
835 | } | |
836 | bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); | |
837 | ||
838 | for (i = 0; i < TX_RING_SIZE; i++) { | |
839 | bp->tx_ring[i].addr = 0; | |
840 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
841 | } | |
842 | bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
843 | ||
844 | bp->rx_tail = bp->tx_head = bp->tx_tail = 0; | |
845 | } | |
846 | ||
847 | static void macb_reset_hw(struct macb *bp) | |
848 | { | |
89e5785f HS |
849 | /* |
850 | * Disable RX and TX (XXX: Should we halt the transmission | |
851 | * more gracefully?) | |
852 | */ | |
853 | macb_writel(bp, NCR, 0); | |
854 | ||
855 | /* Clear the stats registers (XXX: Update stats first?) */ | |
856 | macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); | |
857 | ||
858 | /* Clear all status flags */ | |
95ebcea6 JE |
859 | macb_writel(bp, TSR, -1); |
860 | macb_writel(bp, RSR, -1); | |
89e5785f HS |
861 | |
862 | /* Disable all interrupts */ | |
95ebcea6 | 863 | macb_writel(bp, IDR, -1); |
89e5785f HS |
864 | macb_readl(bp, ISR); |
865 | } | |
866 | ||
70c9f3d4 JI |
867 | static u32 gem_mdc_clk_div(struct macb *bp) |
868 | { | |
869 | u32 config; | |
870 | unsigned long pclk_hz = clk_get_rate(bp->pclk); | |
871 | ||
872 | if (pclk_hz <= 20000000) | |
873 | config = GEM_BF(CLK, GEM_CLK_DIV8); | |
874 | else if (pclk_hz <= 40000000) | |
875 | config = GEM_BF(CLK, GEM_CLK_DIV16); | |
876 | else if (pclk_hz <= 80000000) | |
877 | config = GEM_BF(CLK, GEM_CLK_DIV32); | |
878 | else if (pclk_hz <= 120000000) | |
879 | config = GEM_BF(CLK, GEM_CLK_DIV48); | |
880 | else if (pclk_hz <= 160000000) | |
881 | config = GEM_BF(CLK, GEM_CLK_DIV64); | |
882 | else | |
883 | config = GEM_BF(CLK, GEM_CLK_DIV96); | |
884 | ||
885 | return config; | |
886 | } | |
887 | ||
888 | static u32 macb_mdc_clk_div(struct macb *bp) | |
889 | { | |
890 | u32 config; | |
891 | unsigned long pclk_hz; | |
892 | ||
893 | if (macb_is_gem(bp)) | |
894 | return gem_mdc_clk_div(bp); | |
895 | ||
896 | pclk_hz = clk_get_rate(bp->pclk); | |
897 | if (pclk_hz <= 20000000) | |
898 | config = MACB_BF(CLK, MACB_CLK_DIV8); | |
899 | else if (pclk_hz <= 40000000) | |
900 | config = MACB_BF(CLK, MACB_CLK_DIV16); | |
901 | else if (pclk_hz <= 80000000) | |
902 | config = MACB_BF(CLK, MACB_CLK_DIV32); | |
903 | else | |
904 | config = MACB_BF(CLK, MACB_CLK_DIV64); | |
905 | ||
906 | return config; | |
907 | } | |
908 | ||
757a03c6 JI |
909 | /* |
910 | * Get the DMA bus width field of the network configuration register that we | |
911 | * should program. We find the width from decoding the design configuration | |
912 | * register to find the maximum supported data bus width. | |
913 | */ | |
914 | static u32 macb_dbw(struct macb *bp) | |
915 | { | |
916 | if (!macb_is_gem(bp)) | |
917 | return 0; | |
918 | ||
919 | switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { | |
920 | case 4: | |
921 | return GEM_BF(DBW, GEM_DBW128); | |
922 | case 2: | |
923 | return GEM_BF(DBW, GEM_DBW64); | |
924 | case 1: | |
925 | default: | |
926 | return GEM_BF(DBW, GEM_DBW32); | |
927 | } | |
928 | } | |
929 | ||
0116da4f JI |
930 | /* |
931 | * Configure the receive DMA engine to use the correct receive buffer size. | |
932 | * This is a configurable parameter for GEM. | |
933 | */ | |
934 | static void macb_configure_dma(struct macb *bp) | |
935 | { | |
936 | u32 dmacfg; | |
937 | ||
938 | if (macb_is_gem(bp)) { | |
939 | dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); | |
940 | dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); | |
941 | gem_writel(bp, DMACFG, dmacfg); | |
942 | } | |
943 | } | |
944 | ||
89e5785f HS |
945 | static void macb_init_hw(struct macb *bp) |
946 | { | |
947 | u32 config; | |
948 | ||
949 | macb_reset_hw(bp); | |
950 | __macb_set_hwaddr(bp); | |
951 | ||
70c9f3d4 | 952 | config = macb_mdc_clk_div(bp); |
89e5785f HS |
953 | config |= MACB_BIT(PAE); /* PAuse Enable */ |
954 | config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ | |
8dd4bd00 | 955 | config |= MACB_BIT(BIG); /* Receive oversized frames */ |
89e5785f HS |
956 | if (bp->dev->flags & IFF_PROMISC) |
957 | config |= MACB_BIT(CAF); /* Copy All Frames */ | |
958 | if (!(bp->dev->flags & IFF_BROADCAST)) | |
959 | config |= MACB_BIT(NBC); /* No BroadCast */ | |
757a03c6 | 960 | config |= macb_dbw(bp); |
89e5785f HS |
961 | macb_writel(bp, NCFGR, config); |
962 | ||
0116da4f JI |
963 | macb_configure_dma(bp); |
964 | ||
89e5785f HS |
965 | /* Initialize TX and RX buffers */ |
966 | macb_writel(bp, RBQP, bp->rx_ring_dma); | |
967 | macb_writel(bp, TBQP, bp->tx_ring_dma); | |
968 | ||
969 | /* Enable TX and RX */ | |
6c36a707 | 970 | macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); |
89e5785f HS |
971 | |
972 | /* Enable interrupts */ | |
973 | macb_writel(bp, IER, (MACB_BIT(RCOMP) | |
974 | | MACB_BIT(RXUBR) | |
975 | | MACB_BIT(ISR_TUND) | |
976 | | MACB_BIT(ISR_RLE) | |
977 | | MACB_BIT(TXERR) | |
978 | | MACB_BIT(TCOMP) | |
979 | | MACB_BIT(ISR_ROVR) | |
980 | | MACB_BIT(HRESP))); | |
89e5785f | 981 | |
89e5785f HS |
982 | } |
983 | ||
446ebd01 PV |
984 | /* |
985 | * The hash address register is 64 bits long and takes up two | |
986 | * locations in the memory map. The least significant bits are stored | |
987 | * in EMAC_HSL and the most significant bits in EMAC_HSH. | |
988 | * | |
989 | * The unicast hash enable and the multicast hash enable bits in the | |
990 | * network configuration register enable the reception of hash matched | |
991 | * frames. The destination address is reduced to a 6 bit index into | |
992 | * the 64 bit hash register using the following hash function. The | |
993 | * hash function is an exclusive or of every sixth bit of the | |
994 | * destination address. | |
995 | * | |
996 | * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
997 | * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
998 | * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
999 | * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
1000 | * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
1001 | * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
1002 | * | |
1003 | * da[0] represents the least significant bit of the first byte | |
1004 | * received, that is, the multicast/unicast indicator, and da[47] | |
1005 | * represents the most significant bit of the last byte received. If | |
1006 | * the hash index, hi[n], points to a bit that is set in the hash | |
1007 | * register then the frame will be matched according to whether the | |
1008 | * frame is multicast or unicast. A multicast match will be signalled | |
1009 | * if the multicast hash enable bit is set, da[0] is 1 and the hash | |
1010 | * index points to a bit set in the hash register. A unicast match | |
1011 | * will be signalled if the unicast hash enable bit is set, da[0] is 0 | |
1012 | * and the hash index points to a bit set in the hash register. To | |
1013 | * receive all multicast frames, the hash register should be set with | |
1014 | * all ones and the multicast hash enable bit should be set in the | |
1015 | * network configuration register. | |
1016 | */ | |
1017 | ||
1018 | static inline int hash_bit_value(int bitnr, __u8 *addr) | |
1019 | { | |
1020 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
1021 | return 1; | |
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | /* | |
1026 | * Return the hash index value for the specified address. | |
1027 | */ | |
1028 | static int hash_get_index(__u8 *addr) | |
1029 | { | |
1030 | int i, j, bitval; | |
1031 | int hash_index = 0; | |
1032 | ||
1033 | for (j = 0; j < 6; j++) { | |
1034 | for (i = 0, bitval = 0; i < 8; i++) | |
1035 | bitval ^= hash_bit_value(i*6 + j, addr); | |
1036 | ||
1037 | hash_index |= (bitval << j); | |
1038 | } | |
1039 | ||
1040 | return hash_index; | |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * Add multicast addresses to the internal multicast-hash table. | |
1045 | */ | |
1046 | static void macb_sethashtable(struct net_device *dev) | |
1047 | { | |
22bedad3 | 1048 | struct netdev_hw_addr *ha; |
446ebd01 | 1049 | unsigned long mc_filter[2]; |
f9dcbcc9 | 1050 | unsigned int bitnr; |
446ebd01 PV |
1051 | struct macb *bp = netdev_priv(dev); |
1052 | ||
1053 | mc_filter[0] = mc_filter[1] = 0; | |
1054 | ||
22bedad3 JP |
1055 | netdev_for_each_mc_addr(ha, dev) { |
1056 | bitnr = hash_get_index(ha->addr); | |
446ebd01 PV |
1057 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); |
1058 | } | |
1059 | ||
f75ba50b JI |
1060 | macb_or_gem_writel(bp, HRB, mc_filter[0]); |
1061 | macb_or_gem_writel(bp, HRT, mc_filter[1]); | |
446ebd01 PV |
1062 | } |
1063 | ||
1064 | /* | |
1065 | * Enable/Disable promiscuous and multicast modes. | |
1066 | */ | |
e0da1f14 | 1067 | void macb_set_rx_mode(struct net_device *dev) |
446ebd01 PV |
1068 | { |
1069 | unsigned long cfg; | |
1070 | struct macb *bp = netdev_priv(dev); | |
1071 | ||
1072 | cfg = macb_readl(bp, NCFGR); | |
1073 | ||
1074 | if (dev->flags & IFF_PROMISC) | |
1075 | /* Enable promiscuous mode */ | |
1076 | cfg |= MACB_BIT(CAF); | |
1077 | else if (dev->flags & (~IFF_PROMISC)) | |
1078 | /* Disable promiscuous mode */ | |
1079 | cfg &= ~MACB_BIT(CAF); | |
1080 | ||
1081 | if (dev->flags & IFF_ALLMULTI) { | |
1082 | /* Enable all multicast mode */ | |
f75ba50b JI |
1083 | macb_or_gem_writel(bp, HRB, -1); |
1084 | macb_or_gem_writel(bp, HRT, -1); | |
446ebd01 | 1085 | cfg |= MACB_BIT(NCFGR_MTI); |
4cd24eaf | 1086 | } else if (!netdev_mc_empty(dev)) { |
446ebd01 PV |
1087 | /* Enable specific multicasts */ |
1088 | macb_sethashtable(dev); | |
1089 | cfg |= MACB_BIT(NCFGR_MTI); | |
1090 | } else if (dev->flags & (~IFF_ALLMULTI)) { | |
1091 | /* Disable all multicast mode */ | |
f75ba50b JI |
1092 | macb_or_gem_writel(bp, HRB, 0); |
1093 | macb_or_gem_writel(bp, HRT, 0); | |
446ebd01 PV |
1094 | cfg &= ~MACB_BIT(NCFGR_MTI); |
1095 | } | |
1096 | ||
1097 | macb_writel(bp, NCFGR, cfg); | |
1098 | } | |
e0da1f14 | 1099 | EXPORT_SYMBOL_GPL(macb_set_rx_mode); |
446ebd01 | 1100 | |
89e5785f HS |
1101 | static int macb_open(struct net_device *dev) |
1102 | { | |
1103 | struct macb *bp = netdev_priv(dev); | |
1104 | int err; | |
1105 | ||
c220f8cd | 1106 | netdev_dbg(bp->dev, "open\n"); |
89e5785f | 1107 | |
03fc4721 NF |
1108 | /* carrier starts down */ |
1109 | netif_carrier_off(dev); | |
1110 | ||
6c36a707 R |
1111 | /* if the phy is not yet register, retry later*/ |
1112 | if (!bp->phy_dev) | |
1113 | return -EAGAIN; | |
1114 | ||
89e5785f HS |
1115 | if (!is_valid_ether_addr(dev->dev_addr)) |
1116 | return -EADDRNOTAVAIL; | |
1117 | ||
1118 | err = macb_alloc_consistent(bp); | |
1119 | if (err) { | |
c220f8cd JI |
1120 | netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", |
1121 | err); | |
89e5785f HS |
1122 | return err; |
1123 | } | |
1124 | ||
bea3348e SH |
1125 | napi_enable(&bp->napi); |
1126 | ||
89e5785f HS |
1127 | macb_init_rings(bp); |
1128 | macb_init_hw(bp); | |
89e5785f | 1129 | |
6c36a707 R |
1130 | /* schedule a link state check */ |
1131 | phy_start(bp->phy_dev); | |
89e5785f | 1132 | |
6c36a707 | 1133 | netif_start_queue(dev); |
89e5785f HS |
1134 | |
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | static int macb_close(struct net_device *dev) | |
1139 | { | |
1140 | struct macb *bp = netdev_priv(dev); | |
1141 | unsigned long flags; | |
1142 | ||
89e5785f | 1143 | netif_stop_queue(dev); |
bea3348e | 1144 | napi_disable(&bp->napi); |
89e5785f | 1145 | |
6c36a707 R |
1146 | if (bp->phy_dev) |
1147 | phy_stop(bp->phy_dev); | |
1148 | ||
89e5785f HS |
1149 | spin_lock_irqsave(&bp->lock, flags); |
1150 | macb_reset_hw(bp); | |
1151 | netif_carrier_off(dev); | |
1152 | spin_unlock_irqrestore(&bp->lock, flags); | |
1153 | ||
1154 | macb_free_consistent(bp); | |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
a494ed8e JI |
1159 | static void gem_update_stats(struct macb *bp) |
1160 | { | |
1161 | u32 __iomem *reg = bp->regs + GEM_OTX; | |
1162 | u32 *p = &bp->hw_stats.gem.tx_octets_31_0; | |
1163 | u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1; | |
1164 | ||
1165 | for (; p < end; p++, reg++) | |
1166 | *p += __raw_readl(reg); | |
1167 | } | |
1168 | ||
1169 | static struct net_device_stats *gem_get_stats(struct macb *bp) | |
1170 | { | |
1171 | struct gem_stats *hwstat = &bp->hw_stats.gem; | |
1172 | struct net_device_stats *nstat = &bp->stats; | |
1173 | ||
1174 | gem_update_stats(bp); | |
1175 | ||
1176 | nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + | |
1177 | hwstat->rx_alignment_errors + | |
1178 | hwstat->rx_resource_errors + | |
1179 | hwstat->rx_overruns + | |
1180 | hwstat->rx_oversize_frames + | |
1181 | hwstat->rx_jabbers + | |
1182 | hwstat->rx_undersized_frames + | |
1183 | hwstat->rx_length_field_frame_errors); | |
1184 | nstat->tx_errors = (hwstat->tx_late_collisions + | |
1185 | hwstat->tx_excessive_collisions + | |
1186 | hwstat->tx_underrun + | |
1187 | hwstat->tx_carrier_sense_errors); | |
1188 | nstat->multicast = hwstat->rx_multicast_frames; | |
1189 | nstat->collisions = (hwstat->tx_single_collision_frames + | |
1190 | hwstat->tx_multiple_collision_frames + | |
1191 | hwstat->tx_excessive_collisions); | |
1192 | nstat->rx_length_errors = (hwstat->rx_oversize_frames + | |
1193 | hwstat->rx_jabbers + | |
1194 | hwstat->rx_undersized_frames + | |
1195 | hwstat->rx_length_field_frame_errors); | |
1196 | nstat->rx_over_errors = hwstat->rx_resource_errors; | |
1197 | nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; | |
1198 | nstat->rx_frame_errors = hwstat->rx_alignment_errors; | |
1199 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1200 | nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; | |
1201 | nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; | |
1202 | nstat->tx_fifo_errors = hwstat->tx_underrun; | |
1203 | ||
1204 | return nstat; | |
1205 | } | |
1206 | ||
89e5785f HS |
1207 | static struct net_device_stats *macb_get_stats(struct net_device *dev) |
1208 | { | |
1209 | struct macb *bp = netdev_priv(dev); | |
1210 | struct net_device_stats *nstat = &bp->stats; | |
a494ed8e JI |
1211 | struct macb_stats *hwstat = &bp->hw_stats.macb; |
1212 | ||
1213 | if (macb_is_gem(bp)) | |
1214 | return gem_get_stats(bp); | |
89e5785f | 1215 | |
6c36a707 R |
1216 | /* read stats from hardware */ |
1217 | macb_update_stats(bp); | |
1218 | ||
89e5785f HS |
1219 | /* Convert HW stats into netdevice stats */ |
1220 | nstat->rx_errors = (hwstat->rx_fcs_errors + | |
1221 | hwstat->rx_align_errors + | |
1222 | hwstat->rx_resource_errors + | |
1223 | hwstat->rx_overruns + | |
1224 | hwstat->rx_oversize_pkts + | |
1225 | hwstat->rx_jabbers + | |
1226 | hwstat->rx_undersize_pkts + | |
1227 | hwstat->sqe_test_errors + | |
1228 | hwstat->rx_length_mismatch); | |
1229 | nstat->tx_errors = (hwstat->tx_late_cols + | |
1230 | hwstat->tx_excessive_cols + | |
1231 | hwstat->tx_underruns + | |
1232 | hwstat->tx_carrier_errors); | |
1233 | nstat->collisions = (hwstat->tx_single_cols + | |
1234 | hwstat->tx_multiple_cols + | |
1235 | hwstat->tx_excessive_cols); | |
1236 | nstat->rx_length_errors = (hwstat->rx_oversize_pkts + | |
1237 | hwstat->rx_jabbers + | |
1238 | hwstat->rx_undersize_pkts + | |
1239 | hwstat->rx_length_mismatch); | |
b19f7f71 AS |
1240 | nstat->rx_over_errors = hwstat->rx_resource_errors + |
1241 | hwstat->rx_overruns; | |
89e5785f HS |
1242 | nstat->rx_crc_errors = hwstat->rx_fcs_errors; |
1243 | nstat->rx_frame_errors = hwstat->rx_align_errors; | |
1244 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1245 | /* XXX: What does "missed" mean? */ | |
1246 | nstat->tx_aborted_errors = hwstat->tx_excessive_cols; | |
1247 | nstat->tx_carrier_errors = hwstat->tx_carrier_errors; | |
1248 | nstat->tx_fifo_errors = hwstat->tx_underruns; | |
1249 | /* Don't know about heartbeat or window errors... */ | |
1250 | ||
1251 | return nstat; | |
1252 | } | |
1253 | ||
1254 | static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1255 | { | |
1256 | struct macb *bp = netdev_priv(dev); | |
6c36a707 R |
1257 | struct phy_device *phydev = bp->phy_dev; |
1258 | ||
1259 | if (!phydev) | |
1260 | return -ENODEV; | |
89e5785f | 1261 | |
6c36a707 | 1262 | return phy_ethtool_gset(phydev, cmd); |
89e5785f HS |
1263 | } |
1264 | ||
1265 | static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1266 | { | |
1267 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1268 | struct phy_device *phydev = bp->phy_dev; |
89e5785f | 1269 | |
6c36a707 R |
1270 | if (!phydev) |
1271 | return -ENODEV; | |
1272 | ||
1273 | return phy_ethtool_sset(phydev, cmd); | |
89e5785f HS |
1274 | } |
1275 | ||
0005f541 | 1276 | const struct ethtool_ops macb_ethtool_ops = { |
89e5785f HS |
1277 | .get_settings = macb_get_settings, |
1278 | .set_settings = macb_set_settings, | |
89e5785f | 1279 | .get_link = ethtool_op_get_link, |
17f393e8 | 1280 | .get_ts_info = ethtool_op_get_ts_info, |
89e5785f | 1281 | }; |
0005f541 | 1282 | EXPORT_SYMBOL_GPL(macb_ethtool_ops); |
89e5785f | 1283 | |
0005f541 | 1284 | int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
89e5785f HS |
1285 | { |
1286 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1287 | struct phy_device *phydev = bp->phy_dev; |
89e5785f HS |
1288 | |
1289 | if (!netif_running(dev)) | |
1290 | return -EINVAL; | |
1291 | ||
6c36a707 R |
1292 | if (!phydev) |
1293 | return -ENODEV; | |
89e5785f | 1294 | |
28b04113 | 1295 | return phy_mii_ioctl(phydev, rq, cmd); |
89e5785f | 1296 | } |
0005f541 | 1297 | EXPORT_SYMBOL_GPL(macb_ioctl); |
89e5785f | 1298 | |
5f1fa992 AB |
1299 | static const struct net_device_ops macb_netdev_ops = { |
1300 | .ndo_open = macb_open, | |
1301 | .ndo_stop = macb_close, | |
1302 | .ndo_start_xmit = macb_start_xmit, | |
afc4b13d | 1303 | .ndo_set_rx_mode = macb_set_rx_mode, |
5f1fa992 AB |
1304 | .ndo_get_stats = macb_get_stats, |
1305 | .ndo_do_ioctl = macb_ioctl, | |
1306 | .ndo_validate_addr = eth_validate_addr, | |
1307 | .ndo_change_mtu = eth_change_mtu, | |
1308 | .ndo_set_mac_address = eth_mac_addr, | |
6e8cf5c0 TP |
1309 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1310 | .ndo_poll_controller = macb_poll_controller, | |
1311 | #endif | |
5f1fa992 AB |
1312 | }; |
1313 | ||
fb97a846 JCPV |
1314 | #if defined(CONFIG_OF) |
1315 | static const struct of_device_id macb_dt_ids[] = { | |
1316 | { .compatible = "cdns,at32ap7000-macb" }, | |
1317 | { .compatible = "cdns,at91sam9260-macb" }, | |
1318 | { .compatible = "cdns,macb" }, | |
1319 | { .compatible = "cdns,pc302-gem" }, | |
1320 | { .compatible = "cdns,gem" }, | |
1321 | { /* sentinel */ } | |
1322 | }; | |
1323 | ||
1324 | MODULE_DEVICE_TABLE(of, macb_dt_ids); | |
1325 | ||
1326 | static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev) | |
1327 | { | |
1328 | struct device_node *np = pdev->dev.of_node; | |
1329 | ||
1330 | if (np) | |
1331 | return of_get_phy_mode(np); | |
1332 | ||
1333 | return -ENODEV; | |
1334 | } | |
1335 | ||
1336 | static int __devinit macb_get_hwaddr_dt(struct macb *bp) | |
1337 | { | |
1338 | struct device_node *np = bp->pdev->dev.of_node; | |
1339 | if (np) { | |
1340 | const char *mac = of_get_mac_address(np); | |
1341 | if (mac) { | |
1342 | memcpy(bp->dev->dev_addr, mac, ETH_ALEN); | |
1343 | return 0; | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | return -ENODEV; | |
1348 | } | |
1349 | #else | |
1350 | static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev) | |
1351 | { | |
1352 | return -ENODEV; | |
1353 | } | |
1354 | static int __devinit macb_get_hwaddr_dt(struct macb *bp) | |
1355 | { | |
1356 | return -ENODEV; | |
1357 | } | |
1358 | #endif | |
1359 | ||
06c3fd6a | 1360 | static int __init macb_probe(struct platform_device *pdev) |
89e5785f | 1361 | { |
84e0cdb0 | 1362 | struct macb_platform_data *pdata; |
89e5785f HS |
1363 | struct resource *regs; |
1364 | struct net_device *dev; | |
1365 | struct macb *bp; | |
6c36a707 | 1366 | struct phy_device *phydev; |
89e5785f HS |
1367 | u32 config; |
1368 | int err = -ENXIO; | |
1369 | ||
1370 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1371 | if (!regs) { | |
1372 | dev_err(&pdev->dev, "no mmio resource defined\n"); | |
1373 | goto err_out; | |
1374 | } | |
1375 | ||
1376 | err = -ENOMEM; | |
1377 | dev = alloc_etherdev(sizeof(*bp)); | |
41de8d4c | 1378 | if (!dev) |
89e5785f | 1379 | goto err_out; |
89e5785f | 1380 | |
89e5785f HS |
1381 | SET_NETDEV_DEV(dev, &pdev->dev); |
1382 | ||
1383 | /* TODO: Actually, we have some interesting features... */ | |
1384 | dev->features |= 0; | |
1385 | ||
1386 | bp = netdev_priv(dev); | |
1387 | bp->pdev = pdev; | |
1388 | bp->dev = dev; | |
1389 | ||
1390 | spin_lock_init(&bp->lock); | |
1391 | ||
461845db | 1392 | bp->pclk = clk_get(&pdev->dev, "pclk"); |
0cc8674f AV |
1393 | if (IS_ERR(bp->pclk)) { |
1394 | dev_err(&pdev->dev, "failed to get macb_clk\n"); | |
1395 | goto err_out_free_dev; | |
1396 | } | |
1397 | clk_enable(bp->pclk); | |
461845db | 1398 | |
89e5785f HS |
1399 | bp->hclk = clk_get(&pdev->dev, "hclk"); |
1400 | if (IS_ERR(bp->hclk)) { | |
1401 | dev_err(&pdev->dev, "failed to get hclk\n"); | |
1402 | goto err_out_put_pclk; | |
1403 | } | |
89e5785f HS |
1404 | clk_enable(bp->hclk); |
1405 | ||
28f65c11 | 1406 | bp->regs = ioremap(regs->start, resource_size(regs)); |
89e5785f HS |
1407 | if (!bp->regs) { |
1408 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | |
1409 | err = -ENOMEM; | |
1410 | goto err_out_disable_clocks; | |
1411 | } | |
1412 | ||
1413 | dev->irq = platform_get_irq(pdev, 0); | |
ab392d2d | 1414 | err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev); |
89e5785f | 1415 | if (err) { |
c220f8cd JI |
1416 | dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", |
1417 | dev->irq, err); | |
89e5785f HS |
1418 | goto err_out_iounmap; |
1419 | } | |
1420 | ||
5f1fa992 | 1421 | dev->netdev_ops = &macb_netdev_ops; |
bea3348e | 1422 | netif_napi_add(dev, &bp->napi, macb_poll, 64); |
89e5785f HS |
1423 | dev->ethtool_ops = &macb_ethtool_ops; |
1424 | ||
1425 | dev->base_addr = regs->start; | |
1426 | ||
89e5785f | 1427 | /* Set MII management clock divider */ |
70c9f3d4 | 1428 | config = macb_mdc_clk_div(bp); |
757a03c6 | 1429 | config |= macb_dbw(bp); |
89e5785f HS |
1430 | macb_writel(bp, NCFGR, config); |
1431 | ||
fb97a846 JCPV |
1432 | err = macb_get_hwaddr_dt(bp); |
1433 | if (err < 0) | |
1434 | macb_get_hwaddr(bp); | |
1435 | ||
1436 | err = macb_get_phy_mode_dt(pdev); | |
1437 | if (err < 0) { | |
1438 | pdata = pdev->dev.platform_data; | |
1439 | if (pdata && pdata->is_rmii) | |
1440 | bp->phy_interface = PHY_INTERFACE_MODE_RMII; | |
1441 | else | |
1442 | bp->phy_interface = PHY_INTERFACE_MODE_MII; | |
1443 | } else { | |
1444 | bp->phy_interface = err; | |
1445 | } | |
6c36a707 | 1446 | |
140b7552 PV |
1447 | if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) |
1448 | macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII)); | |
1449 | else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) | |
0cc8674f | 1450 | #if defined(CONFIG_ARCH_AT91) |
f75ba50b JI |
1451 | macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) | |
1452 | MACB_BIT(CLKEN))); | |
0cc8674f | 1453 | #else |
f75ba50b | 1454 | macb_or_gem_writel(bp, USRIO, 0); |
0cc8674f | 1455 | #endif |
89e5785f | 1456 | else |
0cc8674f | 1457 | #if defined(CONFIG_ARCH_AT91) |
f75ba50b | 1458 | macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN)); |
0cc8674f | 1459 | #else |
f75ba50b | 1460 | macb_or_gem_writel(bp, USRIO, MACB_BIT(MII)); |
0cc8674f | 1461 | #endif |
89e5785f | 1462 | |
89e5785f HS |
1463 | err = register_netdev(dev); |
1464 | if (err) { | |
1465 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | |
1466 | goto err_out_free_irq; | |
1467 | } | |
1468 | ||
6c36a707 R |
1469 | if (macb_mii_init(bp) != 0) { |
1470 | goto err_out_unregister_netdev; | |
1471 | } | |
89e5785f | 1472 | |
6c36a707 | 1473 | platform_set_drvdata(pdev, dev); |
89e5785f | 1474 | |
03fc4721 NF |
1475 | netif_carrier_off(dev); |
1476 | ||
f75ba50b JI |
1477 | netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n", |
1478 | macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr, | |
1479 | dev->irq, dev->dev_addr); | |
89e5785f | 1480 | |
6c36a707 | 1481 | phydev = bp->phy_dev; |
c220f8cd JI |
1482 | netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
1483 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
6c36a707 | 1484 | |
89e5785f HS |
1485 | return 0; |
1486 | ||
6c36a707 R |
1487 | err_out_unregister_netdev: |
1488 | unregister_netdev(dev); | |
89e5785f HS |
1489 | err_out_free_irq: |
1490 | free_irq(dev->irq, dev); | |
1491 | err_out_iounmap: | |
1492 | iounmap(bp->regs); | |
1493 | err_out_disable_clocks: | |
1494 | clk_disable(bp->hclk); | |
89e5785f | 1495 | clk_put(bp->hclk); |
0cc8674f | 1496 | clk_disable(bp->pclk); |
89e5785f HS |
1497 | err_out_put_pclk: |
1498 | clk_put(bp->pclk); | |
1499 | err_out_free_dev: | |
1500 | free_netdev(dev); | |
1501 | err_out: | |
1502 | platform_set_drvdata(pdev, NULL); | |
1503 | return err; | |
1504 | } | |
1505 | ||
06c3fd6a | 1506 | static int __exit macb_remove(struct platform_device *pdev) |
89e5785f HS |
1507 | { |
1508 | struct net_device *dev; | |
1509 | struct macb *bp; | |
1510 | ||
1511 | dev = platform_get_drvdata(pdev); | |
1512 | ||
1513 | if (dev) { | |
1514 | bp = netdev_priv(dev); | |
84b7901f AN |
1515 | if (bp->phy_dev) |
1516 | phy_disconnect(bp->phy_dev); | |
298cf9be LB |
1517 | mdiobus_unregister(bp->mii_bus); |
1518 | kfree(bp->mii_bus->irq); | |
1519 | mdiobus_free(bp->mii_bus); | |
89e5785f HS |
1520 | unregister_netdev(dev); |
1521 | free_irq(dev->irq, dev); | |
1522 | iounmap(bp->regs); | |
1523 | clk_disable(bp->hclk); | |
89e5785f | 1524 | clk_put(bp->hclk); |
0cc8674f | 1525 | clk_disable(bp->pclk); |
89e5785f HS |
1526 | clk_put(bp->pclk); |
1527 | free_netdev(dev); | |
1528 | platform_set_drvdata(pdev, NULL); | |
1529 | } | |
1530 | ||
1531 | return 0; | |
1532 | } | |
1533 | ||
c1f598fd HS |
1534 | #ifdef CONFIG_PM |
1535 | static int macb_suspend(struct platform_device *pdev, pm_message_t state) | |
1536 | { | |
1537 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1538 | struct macb *bp = netdev_priv(netdev); | |
1539 | ||
03fc4721 | 1540 | netif_carrier_off(netdev); |
c1f598fd HS |
1541 | netif_device_detach(netdev); |
1542 | ||
c1f598fd | 1543 | clk_disable(bp->hclk); |
c1f598fd HS |
1544 | clk_disable(bp->pclk); |
1545 | ||
1546 | return 0; | |
1547 | } | |
1548 | ||
1549 | static int macb_resume(struct platform_device *pdev) | |
1550 | { | |
1551 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1552 | struct macb *bp = netdev_priv(netdev); | |
1553 | ||
1554 | clk_enable(bp->pclk); | |
c1f598fd | 1555 | clk_enable(bp->hclk); |
c1f598fd HS |
1556 | |
1557 | netif_device_attach(netdev); | |
1558 | ||
1559 | return 0; | |
1560 | } | |
1561 | #else | |
1562 | #define macb_suspend NULL | |
1563 | #define macb_resume NULL | |
1564 | #endif | |
1565 | ||
89e5785f | 1566 | static struct platform_driver macb_driver = { |
06c3fd6a | 1567 | .remove = __exit_p(macb_remove), |
c1f598fd HS |
1568 | .suspend = macb_suspend, |
1569 | .resume = macb_resume, | |
89e5785f HS |
1570 | .driver = { |
1571 | .name = "macb", | |
72abb461 | 1572 | .owner = THIS_MODULE, |
fb97a846 | 1573 | .of_match_table = of_match_ptr(macb_dt_ids), |
89e5785f HS |
1574 | }, |
1575 | }; | |
1576 | ||
1577 | static int __init macb_init(void) | |
1578 | { | |
06c3fd6a | 1579 | return platform_driver_probe(&macb_driver, macb_probe); |
89e5785f HS |
1580 | } |
1581 | ||
1582 | static void __exit macb_exit(void) | |
1583 | { | |
1584 | platform_driver_unregister(&macb_driver); | |
1585 | } | |
1586 | ||
1587 | module_init(macb_init); | |
1588 | module_exit(macb_exit); | |
1589 | ||
1590 | MODULE_LICENSE("GPL"); | |
f75ba50b | 1591 | MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); |
e05503ef | 1592 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
72abb461 | 1593 | MODULE_ALIAS("platform:macb"); |