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Merge tag 'spi-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / cadence / macb.c
CommitLineData
89e5785f 1/*
f75ba50b 2 * Cadence MACB/GEM Ethernet Controller driver
89e5785f
HS		 3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
c220f8cd 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
89e5785f
HS		 12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
909a8583 17#include <linux/circ_buf.h>
89e5785f
HS		 18#include <linux/slab.h>
19#include <linux/init.h>
60fe716f 20#include <linux/io.h>
2dbfdbb9 21#include <linux/gpio.h>
270c499f 22#include <linux/gpio/consumer.h>
a6b7a407 23#include <linux/interrupt.h>
89e5785f
HS		 24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
89e5785f 26#include <linux/dma-mapping.h>
84e0cdb0 27#include <linux/platform_data/macb.h>
89e5785f 28#include <linux/platform_device.h>
6c36a707 29#include <linux/phy.h>
b17471f5 30#include <linux/of.h>
fb97a846 31#include <linux/of_device.h>
270c499f 32#include <linux/of_gpio.h>
148cbb53 33#include <linux/of_mdio.h>
fb97a846 34#include <linux/of_net.h>
1629dd4f
RO		 35#include <linux/ip.h>
36#include <linux/udp.h>
37#include <linux/tcp.h>
89e5785f
HS		 38#include "macb.h"
39
1b44791a 40#define MACB_RX_BUFFER_SIZE 128
1b44791a 41#define RX_BUFFER_MULTIPLE 64 /* bytes */
8441bb33 42
b410d13e 43#define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
8441bb33
ZB		 44#define MIN_RX_RING_SIZE 64
45#define MAX_RX_RING_SIZE 8192
dc97a89e 46#define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
b410d13e 47 * (bp)->rx_ring_size)
89e5785f 48
b410d13e 49#define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
8441bb33
ZB		 50#define MIN_TX_RING_SIZE 64
51#define MAX_TX_RING_SIZE 4096
dc97a89e 52#define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
b410d13e 53 * (bp)->tx_ring_size)
89e5785f 54
909a8583 55/* level of occupied TX descriptors under which we wake up TX process */
b410d13e 56#define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
89e5785f
HS		 57
58#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
59 | MACB_BIT(ISR_ROVR))
e86cd53a
NF		 60#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
61 | MACB_BIT(ISR_RLE) \
62 | MACB_BIT(TXERR))
63#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
64
1629dd4f
RO		 65/* Max length of transmit frame must be a multiple of 8 bytes */
66#define MACB_TX_LEN_ALIGN 8
67#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
68#define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
a4c35ed3 69
44770e11 70#define GEM_MTU_MIN_SIZE ETH_MIN_MTU
1629dd4f 71#define MACB_NETIF_LSO (NETIF_F_TSO | NETIF_F_UFO)
a5898ea0 72
3e2a5e15
SP		 73#define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
74#define MACB_WOL_ENABLED (0x1 << 1)
75
64ec42fe 76/* Graceful stop timeouts in us. We should allow up to
e86cd53a
NF		 77 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
78 */
79#define MACB_HALT_TIMEOUT 1230
89e5785f 80
dc97a89e
RO		 81/* DMA buffer descriptor might be different size
82 * depends on hardware configuration.
83 */
84static unsigned int macb_dma_desc_get_size(struct macb *bp)
85{
86#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
87 if (bp->hw_dma_cap == HW_DMA_CAP_64B)
88 return sizeof(struct macb_dma_desc) + sizeof(struct macb_dma_desc_64);
89#endif
90 return sizeof(struct macb_dma_desc);
91}
92
93static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int idx)
94{
95#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
96 /* Dma buffer descriptor is 4 words length (instead of 2 words)
97 * for 64b GEM.
98 */
99 if (bp->hw_dma_cap == HW_DMA_CAP_64B)
100 idx <<= 1;
101#endif
102 return idx;
103}
104
105#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
106static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
107{
108 return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc));
109}
110#endif
111
55054a16 112/* Ring buffer accessors */
b410d13e 113static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
55054a16 114{
b410d13e 115 return index & (bp->tx_ring_size - 1);
55054a16
HS		 116}
117
02c958dd
CP		 118static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
119 unsigned int index)
55054a16 120{
dc97a89e
RO		 121 index = macb_tx_ring_wrap(queue->bp, index);
122 index = macb_adj_dma_desc_idx(queue->bp, index);
123 return &queue->tx_ring[index];
55054a16
HS		 124}
125
02c958dd
CP		 126static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
127 unsigned int index)
55054a16 128{
b410d13e 129 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
55054a16
HS		 130}
131
02c958dd 132static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
55054a16
HS		 133{
134 dma_addr_t offset;
135
b410d13e 136 offset = macb_tx_ring_wrap(queue->bp, index) *
dc97a89e 137 macb_dma_desc_get_size(queue->bp);
55054a16 138
02c958dd 139 return queue->tx_ring_dma + offset;
55054a16
HS		 140}
141
b410d13e 142static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
55054a16 143{
b410d13e 144 return index & (bp->rx_ring_size - 1);
55054a16
HS		 145}
146
147static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
148{
dc97a89e
RO		 149 index = macb_rx_ring_wrap(bp, index);
150 index = macb_adj_dma_desc_idx(bp, index);
151 return &bp->rx_ring[index];
55054a16
HS		 152}
153
154static void *macb_rx_buffer(struct macb *bp, unsigned int index)
155{
b410d13e
ZB		 156 return bp->rx_buffers + bp->rx_buffer_size *
157 macb_rx_ring_wrap(bp, index);
55054a16
HS		 158}
159
f2ce8a9e
AS		 160/* I/O accessors */
161static u32 hw_readl_native(struct macb *bp, int offset)
162{
163 return __raw_readl(bp->regs + offset);
164}
165
166static void hw_writel_native(struct macb *bp, int offset, u32 value)
167{
168 __raw_writel(value, bp->regs + offset);
169}
170
171static u32 hw_readl(struct macb *bp, int offset)
172{
173 return readl_relaxed(bp->regs + offset);
174}
175
176static void hw_writel(struct macb *bp, int offset, u32 value)
177{
178 writel_relaxed(value, bp->regs + offset);
179}
180
64ec42fe 181/* Find the CPU endianness by using the loopback bit of NCR register. When the
88023beb 182 * CPU is in big endian we need to program swapped mode for management
f2ce8a9e
AS		 183 * descriptor access.
184 */
185static bool hw_is_native_io(void __iomem *addr)
186{
187 u32 value = MACB_BIT(LLB);
188
189 __raw_writel(value, addr + MACB_NCR);
190 value = __raw_readl(addr + MACB_NCR);
191
192 /* Write 0 back to disable everything */
193 __raw_writel(0, addr + MACB_NCR);
194
195 return value == MACB_BIT(LLB);
196}
197
198static bool hw_is_gem(void __iomem *addr, bool native_io)
199{
200 u32 id;
201
202 if (native_io)
203 id = __raw_readl(addr + MACB_MID);
204 else
205 id = readl_relaxed(addr + MACB_MID);
206
207 return MACB_BFEXT(IDNUM, id) >= 0x2;
208}
209
421d9df0 210static void macb_set_hwaddr(struct macb *bp)
89e5785f
HS		 211{
212 u32 bottom;
213 u16 top;
214
215 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
f75ba50b 216 macb_or_gem_writel(bp, SA1B, bottom);
89e5785f 217 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
f75ba50b 218 macb_or_gem_writel(bp, SA1T, top);
3629a6ce
JE		 219
220 /* Clear unused address register sets */
221 macb_or_gem_writel(bp, SA2B, 0);
222 macb_or_gem_writel(bp, SA2T, 0);
223 macb_or_gem_writel(bp, SA3B, 0);
224 macb_or_gem_writel(bp, SA3T, 0);
225 macb_or_gem_writel(bp, SA4B, 0);
226 macb_or_gem_writel(bp, SA4T, 0);
89e5785f
HS		 227}
228
421d9df0 229static void macb_get_hwaddr(struct macb *bp)
89e5785f 230{
d25e78aa 231 struct macb_platform_data *pdata;
89e5785f
HS		 232 u32 bottom;
233 u16 top;
234 u8 addr[6];
17b8bb3e
JE		 235 int i;
236
c607a0d9 237 pdata = dev_get_platdata(&bp->pdev->dev);
d25e78aa 238
aa50b552 239 /* Check all 4 address register for valid address */
17b8bb3e
JE		 240 for (i = 0; i < 4; i++) {
241 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
242 top = macb_or_gem_readl(bp, SA1T + i * 8);
243
d25e78aa
JE		 244 if (pdata && pdata->rev_eth_addr) {
245 addr[5] = bottom & 0xff;
246 addr[4] = (bottom >> 8) & 0xff;
247 addr[3] = (bottom >> 16) & 0xff;
248 addr[2] = (bottom >> 24) & 0xff;
249 addr[1] = top & 0xff;
250 addr[0] = (top & 0xff00) >> 8;
251 } else {
252 addr[0] = bottom & 0xff;
253 addr[1] = (bottom >> 8) & 0xff;
254 addr[2] = (bottom >> 16) & 0xff;
255 addr[3] = (bottom >> 24) & 0xff;
256 addr[4] = top & 0xff;
257 addr[5] = (top >> 8) & 0xff;
258 }
17b8bb3e
JE		 259
260 if (is_valid_ether_addr(addr)) {
261 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
262 return;
263 }
d1d5741d 264 }
17b8bb3e 265
a35919e1 266 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
17b8bb3e 267 eth_hw_addr_random(bp->dev);
89e5785f
HS		 268}
269
6c36a707 270static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 271{
6c36a707 272 struct macb *bp = bus->priv;
89e5785f
HS		 273 int value;
274
89e5785f
HS		 275 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
276 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R		 277 | MACB_BF(PHYA, mii_id)
278 | MACB_BF(REGA, regnum)
89e5785f
HS		 279 | MACB_BF(CODE, MACB_MAN_CODE)));
280
6c36a707
R		 281 /* wait for end of transfer */
282 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
283 cpu_relax();
89e5785f
HS		 284
285 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS		 286
287 return value;
288}
289
6c36a707
R		 290static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
291 u16 value)
89e5785f 292{
6c36a707 293 struct macb *bp = bus->priv;
89e5785f
HS		 294
295 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
296 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R		 297 | MACB_BF(PHYA, mii_id)
298 | MACB_BF(REGA, regnum)
89e5785f 299 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 300 | MACB_BF(DATA, value)));
89e5785f 301
6c36a707
R		 302 /* wait for end of transfer */
303 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
304 cpu_relax();
305
306 return 0;
307}
89e5785f 308
e1824dfe
SB		 309/**
310 * macb_set_tx_clk() - Set a clock to a new frequency
311 * @clk Pointer to the clock to change
312 * @rate New frequency in Hz
313 * @dev Pointer to the struct net_device
314 */
315static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
316{
317 long ferr, rate, rate_rounded;
318
93b31f48
CP		 319 if (!clk)
320 return;
321
e1824dfe
SB		 322 switch (speed) {
323 case SPEED_10:
324 rate = 2500000;
325 break;
326 case SPEED_100:
327 rate = 25000000;
328 break;
329 case SPEED_1000:
330 rate = 125000000;
331 break;
332 default:
9319e47c 333 return;
e1824dfe
SB		 334 }
335
336 rate_rounded = clk_round_rate(clk, rate);
337 if (rate_rounded < 0)
338 return;
339
340 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
341 * is not satisfied.
342 */
343 ferr = abs(rate_rounded - rate);
344 ferr = DIV_ROUND_UP(ferr, rate / 100000);
345 if (ferr > 5)
346 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
aa50b552 347 rate);
e1824dfe
SB		 348
349 if (clk_set_rate(clk, rate_rounded))
350 netdev_err(dev, "adjusting tx_clk failed.\n");
351}
352
6c36a707 353static void macb_handle_link_change(struct net_device *dev)
89e5785f 354{
6c36a707 355 struct macb *bp = netdev_priv(dev);
0a91281e 356 struct phy_device *phydev = dev->phydev;
6c36a707 357 unsigned long flags;
6c36a707 358 int status_change = 0;
89e5785f 359
6c36a707
R		 360 spin_lock_irqsave(&bp->lock, flags);
361
362 if (phydev->link) {
363 if ((bp->speed != phydev->speed) ||
364 (bp->duplex != phydev->duplex)) {
365 u32 reg;
366
367 reg = macb_readl(bp, NCFGR);
368 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
140b7552
PV		 369 if (macb_is_gem(bp))
370 reg &= ~GEM_BIT(GBE);
6c36a707
R		 371
372 if (phydev->duplex)
373 reg |= MACB_BIT(FD);
179956f4 374 if (phydev->speed == SPEED_100)
6c36a707 375 reg |= MACB_BIT(SPD);
e175587f
NF		 376 if (phydev->speed == SPEED_1000 &&
377 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
140b7552 378 reg |= GEM_BIT(GBE);
6c36a707 379
140b7552 380 macb_or_gem_writel(bp, NCFGR, reg);
6c36a707
R		 381
382 bp->speed = phydev->speed;
383 bp->duplex = phydev->duplex;
384 status_change = 1;
385 }
89e5785f
HS		 386 }
387
6c36a707 388 if (phydev->link != bp->link) {
c8f15686 389 if (!phydev->link) {
6c36a707
R		 390 bp->speed = 0;
391 bp->duplex = -1;
392 }
393 bp->link = phydev->link;
89e5785f 394
6c36a707
R		 395 status_change = 1;
396 }
89e5785f 397
6c36a707
R		 398 spin_unlock_irqrestore(&bp->lock, flags);
399
400 if (status_change) {
03fc4721 401 if (phydev->link) {
2c29b235
JA		 402 /* Update the TX clock rate if and only if the link is
403 * up and there has been a link change.
404 */
405 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
406
03fc4721 407 netif_carrier_on(dev);
c220f8cd
JI		 408 netdev_info(dev, "link up (%d/%s)\n",
409 phydev->speed,
410 phydev->duplex == DUPLEX_FULL ?
411 "Full" : "Half");
03fc4721
NF		 412 } else {
413 netif_carrier_off(dev);
c220f8cd 414 netdev_info(dev, "link down\n");
03fc4721 415 }
6c36a707 416 }
89e5785f
HS		 417}
418
6c36a707
R		 419/* based on au1000_eth. c*/
420static int macb_mii_probe(struct net_device *dev)
89e5785f 421{
6c36a707 422 struct macb *bp = netdev_priv(dev);
2dbfdbb9 423 struct macb_platform_data *pdata;
7455a76f 424 struct phy_device *phydev;
2dbfdbb9 425 int phy_irq;
7455a76f 426 int ret;
6c36a707 427
7455a76f 428 phydev = phy_find_first(bp->mii_bus);
6c36a707 429 if (!phydev) {
c220f8cd 430 netdev_err(dev, "no PHY found\n");
7daa78e3 431 return -ENXIO;
6c36a707
R		 432 }
433
2dbfdbb9
JE		 434 pdata = dev_get_platdata(&bp->pdev->dev);
435 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
64ec42fe
MF		 436 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin,
437 "phy int");
2dbfdbb9
JE		 438 if (!ret) {
439 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
440 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
441 }
83a77e9e
BF		 442 } else {
443 phydev->irq = PHY_POLL;
2dbfdbb9 444 }
6c36a707
R		 445
446 /* attach the mac to the phy */
f9a8f83b 447 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
fb97a846 448 bp->phy_interface);
7455a76f 449 if (ret) {
c220f8cd 450 netdev_err(dev, "Could not attach to PHY\n");
7455a76f 451 return ret;
6c36a707
R		 452 }
453
454 /* mask with MAC supported features */
e175587f 455 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
140b7552
PV		 456 phydev->supported &= PHY_GBIT_FEATURES;
457 else
458 phydev->supported &= PHY_BASIC_FEATURES;
6c36a707 459
222ca8e0
NS		 460 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
461 phydev->supported &= ~SUPPORTED_1000baseT_Half;
462
6c36a707
R		 463 phydev->advertising = phydev->supported;
464
465 bp->link = 0;
466 bp->speed = 0;
467 bp->duplex = -1;
6c36a707
R		 468
469 return 0;
89e5785f
HS		 470}
471
421d9df0 472static int macb_mii_init(struct macb *bp)
89e5785f 473{
84e0cdb0 474 struct macb_platform_data *pdata;
148cbb53 475 struct device_node *np;
6c36a707 476 int err = -ENXIO, i;
89e5785f 477
3dbda77e 478 /* Enable management port */
6c36a707 479 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 480
298cf9be 481 bp->mii_bus = mdiobus_alloc();
aa50b552 482 if (!bp->mii_bus) {
298cf9be
LB		 483 err = -ENOMEM;
484 goto err_out;
485 }
486
487 bp->mii_bus->name = "MACB_mii_bus";
488 bp->mii_bus->read = &macb_mdio_read;
489 bp->mii_bus->write = &macb_mdio_write;
98d5e57e 490 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
aa50b552 491 bp->pdev->name, bp->pdev->id);
298cf9be 492 bp->mii_bus->priv = bp;
cf669660 493 bp->mii_bus->parent = &bp->pdev->dev;
c607a0d9 494 pdata = dev_get_platdata(&bp->pdev->dev);
89e5785f 495
91523947 496 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
89e5785f 497
148cbb53
BB		 498 np = bp->pdev->dev.of_node;
499 if (np) {
500 /* try dt phy registration */
501 err = of_mdiobus_register(bp->mii_bus, np);
502
503 /* fallback to standard phy registration if no phy were
64ec42fe
MF		 504 * found during dt phy registration
505 */
148cbb53
BB		 506 if (!err && !phy_find_first(bp->mii_bus)) {
507 for (i = 0; i < PHY_MAX_ADDR; i++) {
508 struct phy_device *phydev;
509
510 phydev = mdiobus_scan(bp->mii_bus, i);
ce24c2b8
SS		 511 if (IS_ERR(phydev) &&
512 PTR_ERR(phydev) != -ENODEV) {
148cbb53
BB		 513 err = PTR_ERR(phydev);
514 break;
515 }
516 }
517
518 if (err)
519 goto err_out_unregister_bus;
520 }
521 } else {
83a77e9e
BF		 522 for (i = 0; i < PHY_MAX_ADDR; i++)
523 bp->mii_bus->irq[i] = PHY_POLL;
524
148cbb53
BB		 525 if (pdata)
526 bp->mii_bus->phy_mask = pdata->phy_mask;
527
528 err = mdiobus_register(bp->mii_bus);
529 }
530
531 if (err)
e7f4dc35 532 goto err_out_free_mdiobus;
89e5785f 533
7daa78e3
BB		 534 err = macb_mii_probe(bp->dev);
535 if (err)
6c36a707 536 goto err_out_unregister_bus;
89e5785f 537
6c36a707 538 return 0;
89e5785f 539
6c36a707 540err_out_unregister_bus:
298cf9be 541 mdiobus_unregister(bp->mii_bus);
298cf9be
LB		 542err_out_free_mdiobus:
543 mdiobus_free(bp->mii_bus);
6c36a707
R		 544err_out:
545 return err;
89e5785f
HS		 546}
547
548static void macb_update_stats(struct macb *bp)
549{
a494ed8e
JI		 550 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
551 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
f2ce8a9e 552 int offset = MACB_PFR;
89e5785f
HS		 553
554 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
555
96ec6310 556 for (; p < end; p++, offset += 4)
7a6e0706 557 *p += bp->macb_reg_readl(bp, offset);
89e5785f
HS		 558}
559
e86cd53a 560static int macb_halt_tx(struct macb *bp)
89e5785f 561{
e86cd53a
NF		 562 unsigned long halt_time, timeout;
563 u32 status;
89e5785f 564
e86cd53a 565 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
89e5785f 566
e86cd53a
NF		 567 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
568 do {
569 halt_time = jiffies;
570 status = macb_readl(bp, TSR);
571 if (!(status & MACB_BIT(TGO)))
572 return 0;
89e5785f 573
e86cd53a
NF		 574 usleep_range(10, 250);
575 } while (time_before(halt_time, timeout));
bdcba151 576
e86cd53a
NF		 577 return -ETIMEDOUT;
578}
39eddb4c 579
a4c35ed3
CP		 580static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
581{
582 if (tx_skb->mapping) {
583 if (tx_skb->mapped_as_page)
584 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
585 tx_skb->size, DMA_TO_DEVICE);
586 else
587 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
588 tx_skb->size, DMA_TO_DEVICE);
589 tx_skb->mapping = 0;
590 }
591
592 if (tx_skb->skb) {
593 dev_kfree_skb_any(tx_skb->skb);
594 tx_skb->skb = NULL;
595 }
596}
597
dc97a89e 598static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
fff8019a 599{
fff8019a 600#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
dc97a89e
RO		 601 struct macb_dma_desc_64 *desc_64;
602
603 if (bp->hw_dma_cap == HW_DMA_CAP_64B) {
604 desc_64 = macb_64b_desc(bp, desc);
605 desc_64->addrh = upper_32_bits(addr);
606 }
fff8019a 607#endif
dc97a89e
RO		 608 desc->addr = lower_32_bits(addr);
609}
610
611static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
612{
613 dma_addr_t addr = 0;
614#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
615 struct macb_dma_desc_64 *desc_64;
616
617 if (bp->hw_dma_cap == HW_DMA_CAP_64B) {
618 desc_64 = macb_64b_desc(bp, desc);
619 addr = ((u64)(desc_64->addrh) << 32);
620 }
621#endif
622 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
623 return addr;
fff8019a
HK		 624}
625
e86cd53a
NF		 626static void macb_tx_error_task(struct work_struct *work)
627{
02c958dd
CP		 628 struct macb_queue *queue = container_of(work, struct macb_queue,
629 tx_error_task);
630 struct macb *bp = queue->bp;
e86cd53a 631 struct macb_tx_skb *tx_skb;
02c958dd 632 struct macb_dma_desc *desc;
e86cd53a
NF		 633 struct sk_buff *skb;
634 unsigned int tail;
02c958dd
CP		 635 unsigned long flags;
636
637 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
638 (unsigned int)(queue - bp->queues),
639 queue->tx_tail, queue->tx_head);
bdcba151 640
02c958dd
CP		 641 /* Prevent the queue IRQ handlers from running: each of them may call
642 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
643 * As explained below, we have to halt the transmission before updating
644 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
645 * network engine about the macb/gem being halted.
646 */
647 spin_lock_irqsave(&bp->lock, flags);
bdcba151 648
e86cd53a 649 /* Make sure nobody is trying to queue up new packets */
02c958dd 650 netif_tx_stop_all_queues(bp->dev);
d3e61457 651
64ec42fe 652 /* Stop transmission now
e86cd53a 653 * (in case we have just queued new packets)
02c958dd 654 * macb/gem must be halted to write TBQP register
e86cd53a
NF		 655 */
656 if (macb_halt_tx(bp))
657 /* Just complain for now, reinitializing TX path can be good */
658 netdev_err(bp->dev, "BUG: halt tx timed out\n");
bdcba151 659
64ec42fe 660 /* Treat frames in TX queue including the ones that caused the error.
e86cd53a
NF		 661 * Free transmit buffers in upper layer.
662 */
02c958dd
CP		 663 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
664 u32 ctrl;
55054a16 665
02c958dd 666 desc = macb_tx_desc(queue, tail);
e86cd53a 667 ctrl = desc->ctrl;
02c958dd 668 tx_skb = macb_tx_skb(queue, tail);
e86cd53a 669 skb = tx_skb->skb;
bdcba151 670
e86cd53a 671 if (ctrl & MACB_BIT(TX_USED)) {
a4c35ed3
CP		 672 /* skb is set for the last buffer of the frame */
673 while (!skb) {
674 macb_tx_unmap(bp, tx_skb);
675 tail++;
02c958dd 676 tx_skb = macb_tx_skb(queue, tail);
a4c35ed3
CP		 677 skb = tx_skb->skb;
678 }
679
680 /* ctrl still refers to the first buffer descriptor
681 * since it's the only one written back by the hardware
682 */
683 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
684 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
b410d13e
ZB		 685 macb_tx_ring_wrap(bp, tail),
686 skb->data);
a4c35ed3
CP		 687 bp->stats.tx_packets++;
688 bp->stats.tx_bytes += skb->len;
689 }
e86cd53a 690 } else {
64ec42fe
MF		 691 /* "Buffers exhausted mid-frame" errors may only happen
692 * if the driver is buggy, so complain loudly about
693 * those. Statistics are updated by hardware.
e86cd53a
NF		 694 */
695 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
696 netdev_err(bp->dev,
697 "BUG: TX buffers exhausted mid-frame\n");
39eddb4c 698
e86cd53a
NF		 699 desc->ctrl = ctrl | MACB_BIT(TX_USED);
700 }
701
a4c35ed3 702 macb_tx_unmap(bp, tx_skb);
89e5785f
HS		 703 }
704
02c958dd
CP		 705 /* Set end of TX queue */
706 desc = macb_tx_desc(queue, 0);
dc97a89e 707 macb_set_addr(bp, desc, 0);
02c958dd
CP		 708 desc->ctrl = MACB_BIT(TX_USED);
709
e86cd53a
NF		 710 /* Make descriptor updates visible to hardware */
711 wmb();
712
713 /* Reinitialize the TX desc queue */
dc97a89e 714 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
fff8019a 715#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
dc97a89e
RO		 716 if (bp->hw_dma_cap == HW_DMA_CAP_64B)
717 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
fff8019a 718#endif
e86cd53a 719 /* Make TX ring reflect state of hardware */
02c958dd
CP		 720 queue->tx_head = 0;
721 queue->tx_tail = 0;
e86cd53a
NF		 722
723 /* Housework before enabling TX IRQ */
724 macb_writel(bp, TSR, macb_readl(bp, TSR));
02c958dd
CP		 725 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
726
727 /* Now we are ready to start transmission again */
728 netif_tx_start_all_queues(bp->dev);
729 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
730
731 spin_unlock_irqrestore(&bp->lock, flags);
e86cd53a
NF		 732}
733
02c958dd 734static void macb_tx_interrupt(struct macb_queue *queue)
e86cd53a
NF		 735{
736 unsigned int tail;
737 unsigned int head;
738 u32 status;
02c958dd
CP		 739 struct macb *bp = queue->bp;
740 u16 queue_index = queue - bp->queues;
e86cd53a
NF		 741
742 status = macb_readl(bp, TSR);
743 macb_writel(bp, TSR, status);
744
581df9e1 745 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
02c958dd 746 queue_writel(queue, ISR, MACB_BIT(TCOMP));
749a2b66 747
e86cd53a 748 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
aa50b552 749 (unsigned long)status);
89e5785f 750
02c958dd
CP		 751 head = queue->tx_head;
752 for (tail = queue->tx_tail; tail != head; tail++) {
55054a16
HS		 753 struct macb_tx_skb *tx_skb;
754 struct sk_buff *skb;
755 struct macb_dma_desc *desc;
756 u32 ctrl;
89e5785f 757
02c958dd 758 desc = macb_tx_desc(queue, tail);
89e5785f 759
03dbe05f 760 /* Make hw descriptor updates visible to CPU */
89e5785f 761 rmb();
03dbe05f 762
55054a16 763 ctrl = desc->ctrl;
89e5785f 764
a4c35ed3
CP		 765 /* TX_USED bit is only set by hardware on the very first buffer
766 * descriptor of the transmitted frame.
767 */
55054a16 768 if (!(ctrl & MACB_BIT(TX_USED)))
89e5785f
HS		 769 break;
770
a4c35ed3
CP		 771 /* Process all buffers of the current transmitted frame */
772 for (;; tail++) {
02c958dd 773 tx_skb = macb_tx_skb(queue, tail);
a4c35ed3
CP		 774 skb = tx_skb->skb;
775
776 /* First, update TX stats if needed */
777 if (skb) {
778 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
b410d13e
ZB		 779 macb_tx_ring_wrap(bp, tail),
780 skb->data);
a4c35ed3
CP		 781 bp->stats.tx_packets++;
782 bp->stats.tx_bytes += skb->len;
783 }
55054a16 784
a4c35ed3
CP		 785 /* Now we can safely release resources */
786 macb_tx_unmap(bp, tx_skb);
787
788 /* skb is set only for the last buffer of the frame.
789 * WARNING: at this point skb has been freed by
790 * macb_tx_unmap().
791 */
792 if (skb)
793 break;
794 }
89e5785f
HS		 795 }
796
02c958dd
CP		 797 queue->tx_tail = tail;
798 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
799 CIRC_CNT(queue->tx_head, queue->tx_tail,
b410d13e 800 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
02c958dd 801 netif_wake_subqueue(bp->dev, queue_index);
89e5785f
HS		 802}
803
4df95131
NF		 804static void gem_rx_refill(struct macb *bp)
805{
806 unsigned int entry;
807 struct sk_buff *skb;
4df95131 808 dma_addr_t paddr;
dc97a89e 809 struct macb_dma_desc *desc;
4df95131 810
64ec42fe 811 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail,
b410d13e
ZB		 812 bp->rx_ring_size) > 0) {
813 entry = macb_rx_ring_wrap(bp, bp->rx_prepared_head);
4df95131
NF		 814
815 /* Make hw descriptor updates visible to CPU */
816 rmb();
817
4df95131 818 bp->rx_prepared_head++;
dc97a89e 819 desc = macb_rx_desc(bp, entry);
4df95131 820
aa50b552 821 if (!bp->rx_skbuff[entry]) {
4df95131
NF		 822 /* allocate sk_buff for this free entry in ring */
823 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
aa50b552 824 if (unlikely(!skb)) {
4df95131
NF		 825 netdev_err(bp->dev,
826 "Unable to allocate sk_buff\n");
827 break;
828 }
4df95131
NF		 829
830 /* now fill corresponding descriptor entry */
831 paddr = dma_map_single(&bp->pdev->dev, skb->data,
64ec42fe
MF		 832 bp->rx_buffer_size,
833 DMA_FROM_DEVICE);
92030908
SB		 834 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
835 dev_kfree_skb(skb);
836 break;
837 }
838
839 bp->rx_skbuff[entry] = skb;
4df95131 840
b410d13e 841 if (entry == bp->rx_ring_size - 1)
4df95131 842 paddr |= MACB_BIT(RX_WRAP);
dc97a89e
RO		 843 macb_set_addr(bp, desc, paddr);
844 desc->ctrl = 0;
4df95131
NF		 845
846 /* properly align Ethernet header */
847 skb_reserve(skb, NET_IP_ALIGN);
d4c216c5 848 } else {
dc97a89e
RO		 849 desc->addr &= ~MACB_BIT(RX_USED);
850 desc->ctrl = 0;
4df95131
NF		 851 }
852 }
853
854 /* Make descriptor updates visible to hardware */
855 wmb();
856
857 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
aa50b552 858 bp->rx_prepared_head, bp->rx_tail);
4df95131
NF		 859}
860
861/* Mark DMA descriptors from begin up to and not including end as unused */
862static void discard_partial_frame(struct macb *bp, unsigned int begin,
863 unsigned int end)
864{
865 unsigned int frag;
866
867 for (frag = begin; frag != end; frag++) {
868 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
64ec42fe 869
4df95131
NF		 870 desc->addr &= ~MACB_BIT(RX_USED);
871 }
872
873 /* Make descriptor updates visible to hardware */
874 wmb();
875
64ec42fe 876 /* When this happens, the hardware stats registers for
4df95131
NF		 877 * whatever caused this is updated, so we don't have to record
878 * anything.
879 */
880}
881
882static int gem_rx(struct macb *bp, int budget)
883{
884 unsigned int len;
885 unsigned int entry;
886 struct sk_buff *skb;
887 struct macb_dma_desc *desc;
888 int count = 0;
889
890 while (count < budget) {
fff8019a
HK		 891 u32 ctrl;
892 dma_addr_t addr;
893 bool rxused;
4df95131 894
b410d13e 895 entry = macb_rx_ring_wrap(bp, bp->rx_tail);
dc97a89e 896 desc = macb_rx_desc(bp, entry);
4df95131
NF		 897
898 /* Make hw descriptor updates visible to CPU */
899 rmb();
900
fff8019a 901 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
dc97a89e 902 addr = macb_get_addr(bp, desc);
4df95131
NF		 903 ctrl = desc->ctrl;
904
fff8019a 905 if (!rxused)
4df95131
NF		 906 break;
907
4df95131
NF		 908 bp->rx_tail++;
909 count++;
910
911 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
912 netdev_err(bp->dev,
913 "not whole frame pointed by descriptor\n");
914 bp->stats.rx_dropped++;
915 break;
916 }
917 skb = bp->rx_skbuff[entry];
918 if (unlikely(!skb)) {
919 netdev_err(bp->dev,
920 "inconsistent Rx descriptor chain\n");
921 bp->stats.rx_dropped++;
922 break;
923 }
924 /* now everything is ready for receiving packet */
925 bp->rx_skbuff[entry] = NULL;
98b5a0f4 926 len = ctrl & bp->rx_frm_len_mask;
4df95131
NF		 927
928 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
929
930 skb_put(skb, len);
4df95131 931 dma_unmap_single(&bp->pdev->dev, addr,
48330e08 932 bp->rx_buffer_size, DMA_FROM_DEVICE);
4df95131
NF		 933
934 skb->protocol = eth_type_trans(skb, bp->dev);
935 skb_checksum_none_assert(skb);
924ec53c
CP		 936 if (bp->dev->features & NETIF_F_RXCSUM &&
937 !(bp->dev->flags & IFF_PROMISC) &&
938 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
939 skb->ip_summed = CHECKSUM_UNNECESSARY;
4df95131
NF		 940
941 bp->stats.rx_packets++;
942 bp->stats.rx_bytes += skb->len;
943
944#if defined(DEBUG) && defined(VERBOSE_DEBUG)
945 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
946 skb->len, skb->csum);
947 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
51f83014 948 skb_mac_header(skb), 16, true);
4df95131
NF		 949 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
950 skb->data, 32, true);
951#endif
952
953 netif_receive_skb(skb);
954 }
955
956 gem_rx_refill(bp);
957
958 return count;
959}
960
89e5785f
HS		 961static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
962 unsigned int last_frag)
963{
964 unsigned int len;
965 unsigned int frag;
29bc2e1e 966 unsigned int offset;
89e5785f 967 struct sk_buff *skb;
55054a16 968 struct macb_dma_desc *desc;
89e5785f 969
55054a16 970 desc = macb_rx_desc(bp, last_frag);
98b5a0f4 971 len = desc->ctrl & bp->rx_frm_len_mask;
89e5785f 972
a268adb1 973 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
b410d13e
ZB		 974 macb_rx_ring_wrap(bp, first_frag),
975 macb_rx_ring_wrap(bp, last_frag), len);
89e5785f 976
64ec42fe 977 /* The ethernet header starts NET_IP_ALIGN bytes into the
29bc2e1e
HS		 978 * first buffer. Since the header is 14 bytes, this makes the
979 * payload word-aligned.
980 *
981 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
982 * the two padding bytes into the skb so that we avoid hitting
983 * the slowpath in memcpy(), and pull them off afterwards.
984 */
985 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
89e5785f
HS		 986 if (!skb) {
987 bp->stats.rx_dropped++;
55054a16
HS		 988 for (frag = first_frag; ; frag++) {
989 desc = macb_rx_desc(bp, frag);
990 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS		 991 if (frag == last_frag)
992 break;
993 }
03dbe05f
HS		 994
995 /* Make descriptor updates visible to hardware */
89e5785f 996 wmb();
03dbe05f 997
89e5785f
HS		 998 return 1;
999 }
1000
29bc2e1e
HS		 1001 offset = 0;
1002 len += NET_IP_ALIGN;
bc8acf2c 1003 skb_checksum_none_assert(skb);
89e5785f
HS		 1004 skb_put(skb, len);
1005
55054a16 1006 for (frag = first_frag; ; frag++) {
1b44791a 1007 unsigned int frag_len = bp->rx_buffer_size;
89e5785f
HS		 1008
1009 if (offset + frag_len > len) {
9ba723b0
CP		 1010 if (unlikely(frag != last_frag)) {
1011 dev_kfree_skb_any(skb);
1012 return -1;
1013 }
89e5785f
HS		 1014 frag_len = len - offset;
1015 }
27d7ff46 1016 skb_copy_to_linear_data_offset(skb, offset,
aa50b552
MF		 1017 macb_rx_buffer(bp, frag),
1018 frag_len);
1b44791a 1019 offset += bp->rx_buffer_size;
55054a16
HS		 1020 desc = macb_rx_desc(bp, frag);
1021 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS		 1022
1023 if (frag == last_frag)
1024 break;
1025 }
1026
03dbe05f
HS		 1027 /* Make descriptor updates visible to hardware */
1028 wmb();
1029
29bc2e1e 1030 __skb_pull(skb, NET_IP_ALIGN);
89e5785f
HS		 1031 skb->protocol = eth_type_trans(skb, bp->dev);
1032
1033 bp->stats.rx_packets++;
29bc2e1e 1034 bp->stats.rx_bytes += skb->len;
a268adb1 1035 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
aa50b552 1036 skb->len, skb->csum);
89e5785f
HS		 1037 netif_receive_skb(skb);
1038
1039 return 0;
1040}
1041
9ba723b0
CP		 1042static inline void macb_init_rx_ring(struct macb *bp)
1043{
1044 dma_addr_t addr;
dc97a89e 1045 struct macb_dma_desc *desc = NULL;
9ba723b0
CP		 1046 int i;
1047
1048 addr = bp->rx_buffers_dma;
b410d13e 1049 for (i = 0; i < bp->rx_ring_size; i++) {
dc97a89e
RO		 1050 desc = macb_rx_desc(bp, i);
1051 macb_set_addr(bp, desc, addr);
1052 desc->ctrl = 0;
9ba723b0
CP		 1053 addr += bp->rx_buffer_size;
1054 }
dc97a89e 1055 desc->addr |= MACB_BIT(RX_WRAP);
a0b44eea 1056 bp->rx_tail = 0;
9ba723b0
CP		 1057}
1058
89e5785f
HS		 1059static int macb_rx(struct macb *bp, int budget)
1060{
9ba723b0 1061 bool reset_rx_queue = false;
89e5785f 1062 int received = 0;
55054a16 1063 unsigned int tail;
89e5785f
HS		 1064 int first_frag = -1;
1065
55054a16
HS		 1066 for (tail = bp->rx_tail; budget > 0; tail++) {
1067 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
dc97a89e 1068 u32 ctrl;
89e5785f 1069
03dbe05f 1070 /* Make hw descriptor updates visible to CPU */
89e5785f 1071 rmb();
03dbe05f 1072
55054a16 1073 ctrl = desc->ctrl;
89e5785f 1074
dc97a89e 1075 if (!(desc->addr & MACB_BIT(RX_USED)))
89e5785f
HS		 1076 break;
1077
1078 if (ctrl & MACB_BIT(RX_SOF)) {
1079 if (first_frag != -1)
1080 discard_partial_frame(bp, first_frag, tail);
1081 first_frag = tail;
1082 }
1083
1084 if (ctrl & MACB_BIT(RX_EOF)) {
1085 int dropped;
9ba723b0
CP		 1086
1087 if (unlikely(first_frag == -1)) {
1088 reset_rx_queue = true;
1089 continue;
1090 }
89e5785f
HS		 1091
1092 dropped = macb_rx_frame(bp, first_frag, tail);
1093 first_frag = -1;
9ba723b0
CP		 1094 if (unlikely(dropped < 0)) {
1095 reset_rx_queue = true;
1096 continue;
1097 }
89e5785f
HS		 1098 if (!dropped) {
1099 received++;
1100 budget--;
1101 }
1102 }
1103 }
1104
9ba723b0
CP		 1105 if (unlikely(reset_rx_queue)) {
1106 unsigned long flags;
1107 u32 ctrl;
1108
1109 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1110
1111 spin_lock_irqsave(&bp->lock, flags);
1112
1113 ctrl = macb_readl(bp, NCR);
1114 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1115
1116 macb_init_rx_ring(bp);
1117 macb_writel(bp, RBQP, bp->rx_ring_dma);
1118
1119 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1120
1121 spin_unlock_irqrestore(&bp->lock, flags);
1122 return received;
1123 }
1124
89e5785f
HS		 1125 if (first_frag != -1)
1126 bp->rx_tail = first_frag;
1127 else
1128 bp->rx_tail = tail;
1129
1130 return received;
1131}
1132
bea3348e 1133static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 1134{
bea3348e 1135 struct macb *bp = container_of(napi, struct macb, napi);
bea3348e 1136 int work_done;
89e5785f
HS		 1137 u32 status;
1138
1139 status = macb_readl(bp, RSR);
1140 macb_writel(bp, RSR, status);
1141
bea3348e 1142 work_done = 0;
89e5785f 1143
a268adb1 1144 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
aa50b552 1145 (unsigned long)status, budget);
89e5785f 1146
4df95131 1147 work_done = bp->macbgem_ops.mog_rx(bp, budget);
b336369c 1148 if (work_done < budget) {
288379f0 1149 napi_complete(napi);
89e5785f 1150
8770e91a
NF		 1151 /* Packets received while interrupts were disabled */
1152 status = macb_readl(bp, RSR);
504ad98d 1153 if (status) {
02f7a34f
SB		 1154 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1155 macb_writel(bp, ISR, MACB_BIT(RCOMP));
8770e91a 1156 napi_reschedule(napi);
02f7a34f
SB		 1157 } else {
1158 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
1159 }
b336369c 1160 }
89e5785f
HS		 1161
1162 /* TODO: Handle errors */
1163
bea3348e 1164 return work_done;
89e5785f
HS		 1165}
1166
1167static irqreturn_t macb_interrupt(int irq, void *dev_id)
1168{
02c958dd
CP		 1169 struct macb_queue *queue = dev_id;
1170 struct macb *bp = queue->bp;
1171 struct net_device *dev = bp->dev;
bfbb92c4 1172 u32 status, ctrl;
89e5785f 1173
02c958dd 1174 status = queue_readl(queue, ISR);
89e5785f
HS		 1175
1176 if (unlikely(!status))
1177 return IRQ_NONE;
1178
1179 spin_lock(&bp->lock);
1180
1181 while (status) {
89e5785f
HS		 1182 /* close possible race with dev_close */
1183 if (unlikely(!netif_running(dev))) {
02c958dd 1184 queue_writel(queue, IDR, -1);
24468374
NS		 1185 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1186 queue_writel(queue, ISR, -1);
89e5785f
HS		 1187 break;
1188 }
1189
02c958dd
CP		 1190 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1191 (unsigned int)(queue - bp->queues),
1192 (unsigned long)status);
a268adb1 1193
89e5785f 1194 if (status & MACB_RX_INT_FLAGS) {
64ec42fe 1195 /* There's no point taking any more interrupts
b336369c
JH		 1196 * until we have processed the buffers. The
1197 * scheduling call may fail if the poll routine
1198 * is already scheduled, so disable interrupts
1199 * now.
1200 */
02c958dd 1201 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
581df9e1 1202 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
02c958dd 1203 queue_writel(queue, ISR, MACB_BIT(RCOMP));
b336369c 1204
288379f0 1205 if (napi_schedule_prep(&bp->napi)) {
a268adb1 1206 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
288379f0 1207 __napi_schedule(&bp->napi);
89e5785f
HS		 1208 }
1209 }
1210
e86cd53a 1211 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
02c958dd
CP		 1212 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1213 schedule_work(&queue->tx_error_task);
6a027b70
SB		 1214
1215 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
02c958dd 1216 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
6a027b70 1217
e86cd53a
NF		 1218 break;
1219 }
1220
1221 if (status & MACB_BIT(TCOMP))
02c958dd 1222 macb_tx_interrupt(queue);
89e5785f 1223
64ec42fe 1224 /* Link change detection isn't possible with RMII, so we'll
89e5785f
HS		 1225 * add that if/when we get our hands on a full-blown MII PHY.
1226 */
1227
86b5e7de
NS		 1228 /* There is a hardware issue under heavy load where DMA can
1229 * stop, this causes endless "used buffer descriptor read"
1230 * interrupts but it can be cleared by re-enabling RX. See
1231 * the at91 manual, section 41.3.1 or the Zynq manual
1232 * section 16.7.4 for details.
1233 */
bfbb92c4
NS		 1234 if (status & MACB_BIT(RXUBR)) {
1235 ctrl = macb_readl(bp, NCR);
1236 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
ffac0e96 1237 wmb();
bfbb92c4
NS		 1238 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1239
1240 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
ba504994 1241 queue_writel(queue, ISR, MACB_BIT(RXUBR));
bfbb92c4
NS		 1242 }
1243
b19f7f71
AS		 1244 if (status & MACB_BIT(ISR_ROVR)) {
1245 /* We missed at least one packet */
f75ba50b
JI		 1246 if (macb_is_gem(bp))
1247 bp->hw_stats.gem.rx_overruns++;
1248 else
1249 bp->hw_stats.macb.rx_overruns++;
6a027b70
SB		 1250
1251 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
02c958dd 1252 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
b19f7f71
AS		 1253 }
1254
89e5785f 1255 if (status & MACB_BIT(HRESP)) {
64ec42fe 1256 /* TODO: Reset the hardware, and maybe move the
c220f8cd
JI		 1257 * netdev_err to a lower-priority context as well
1258 * (work queue?)
89e5785f 1259 */
c220f8cd 1260 netdev_err(dev, "DMA bus error: HRESP not OK\n");
6a027b70
SB		 1261
1262 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
02c958dd 1263 queue_writel(queue, ISR, MACB_BIT(HRESP));
89e5785f
HS		 1264 }
1265
02c958dd 1266 status = queue_readl(queue, ISR);
89e5785f
HS		 1267 }
1268
1269 spin_unlock(&bp->lock);
1270
1271 return IRQ_HANDLED;
1272}
1273
6e8cf5c0 1274#ifdef CONFIG_NET_POLL_CONTROLLER
64ec42fe 1275/* Polling receive - used by netconsole and other diagnostic tools
6e8cf5c0
TP		 1276 * to allow network i/o with interrupts disabled.
1277 */
1278static void macb_poll_controller(struct net_device *dev)
1279{
02c958dd
CP		 1280 struct macb *bp = netdev_priv(dev);
1281 struct macb_queue *queue;
6e8cf5c0 1282 unsigned long flags;
02c958dd 1283 unsigned int q;
6e8cf5c0
TP		 1284
1285 local_irq_save(flags);
02c958dd
CP		 1286 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1287 macb_interrupt(dev->irq, queue);
6e8cf5c0
TP		 1288 local_irq_restore(flags);
1289}
1290#endif
1291
a4c35ed3 1292static unsigned int macb_tx_map(struct macb *bp,
02c958dd 1293 struct macb_queue *queue,
1629dd4f
RO		 1294 struct sk_buff *skb,
1295 unsigned int hdrlen)
89e5785f 1296{
89e5785f 1297 dma_addr_t mapping;
02c958dd 1298 unsigned int len, entry, i, tx_head = queue->tx_head;
a4c35ed3 1299 struct macb_tx_skb *tx_skb = NULL;
55054a16 1300 struct macb_dma_desc *desc;
a4c35ed3
CP		 1301 unsigned int offset, size, count = 0;
1302 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1629dd4f
RO		 1303 unsigned int eof = 1, mss_mfs = 0;
1304 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1305
1306 /* LSO */
1307 if (skb_shinfo(skb)->gso_size != 0) {
1308 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1309 /* UDP - UFO */
1310 lso_ctrl = MACB_LSO_UFO_ENABLE;
1311 else
1312 /* TCP - TSO */
1313 lso_ctrl = MACB_LSO_TSO_ENABLE;
1314 }
a4c35ed3
CP		 1315
1316 /* First, map non-paged data */
1317 len = skb_headlen(skb);
1629dd4f
RO		 1318
1319 /* first buffer length */
1320 size = hdrlen;
1321
a4c35ed3
CP		 1322 offset = 0;
1323 while (len) {
b410d13e 1324 entry = macb_tx_ring_wrap(bp, tx_head);
02c958dd 1325 tx_skb = &queue->tx_skb[entry];
a4c35ed3
CP		 1326
1327 mapping = dma_map_single(&bp->pdev->dev,
1328 skb->data + offset,
1329 size, DMA_TO_DEVICE);
1330 if (dma_mapping_error(&bp->pdev->dev, mapping))
1331 goto dma_error;
1332
1333 /* Save info to properly release resources */
1334 tx_skb->skb = NULL;
1335 tx_skb->mapping = mapping;
1336 tx_skb->size = size;
1337 tx_skb->mapped_as_page = false;
1338
1339 len -= size;
1340 offset += size;
1341 count++;
1342 tx_head++;
1629dd4f
RO		 1343
1344 size = min(len, bp->max_tx_length);
a4c35ed3
CP		 1345 }
1346
1347 /* Then, map paged data from fragments */
1348 for (f = 0; f < nr_frags; f++) {
1349 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1350
1351 len = skb_frag_size(frag);
1352 offset = 0;
1353 while (len) {
1354 size = min(len, bp->max_tx_length);
b410d13e 1355 entry = macb_tx_ring_wrap(bp, tx_head);
02c958dd 1356 tx_skb = &queue->tx_skb[entry];
a4c35ed3
CP		 1357
1358 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1359 offset, size, DMA_TO_DEVICE);
1360 if (dma_mapping_error(&bp->pdev->dev, mapping))
1361 goto dma_error;
1362
1363 /* Save info to properly release resources */
1364 tx_skb->skb = NULL;
1365 tx_skb->mapping = mapping;
1366 tx_skb->size = size;
1367 tx_skb->mapped_as_page = true;
1368
1369 len -= size;
1370 offset += size;
1371 count++;
1372 tx_head++;
1373 }
1374 }
1375
1376 /* Should never happen */
aa50b552 1377 if (unlikely(!tx_skb)) {
a4c35ed3
CP		 1378 netdev_err(bp->dev, "BUG! empty skb!\n");
1379 return 0;
1380 }
1381
1382 /* This is the last buffer of the frame: save socket buffer */
1383 tx_skb->skb = skb;
1384
1385 /* Update TX ring: update buffer descriptors in reverse order
1386 * to avoid race condition
1387 */
1388
1389 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1390 * to set the end of TX queue
1391 */
1392 i = tx_head;
b410d13e 1393 entry = macb_tx_ring_wrap(bp, i);
a4c35ed3 1394 ctrl = MACB_BIT(TX_USED);
dc97a89e 1395 desc = macb_tx_desc(queue, entry);
a4c35ed3
CP		 1396 desc->ctrl = ctrl;
1397
1629dd4f
RO		 1398 if (lso_ctrl) {
1399 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1400 /* include header and FCS in value given to h/w */
1401 mss_mfs = skb_shinfo(skb)->gso_size +
1402 skb_transport_offset(skb) +
1403 ETH_FCS_LEN;
1404 else /* TSO */ {
1405 mss_mfs = skb_shinfo(skb)->gso_size;
1406 /* TCP Sequence Number Source Select
1407 * can be set only for TSO
1408 */
1409 seq_ctrl = 0;
1410 }
1411 }
1412
a4c35ed3
CP		 1413 do {
1414 i--;
b410d13e 1415 entry = macb_tx_ring_wrap(bp, i);
02c958dd 1416 tx_skb = &queue->tx_skb[entry];
dc97a89e 1417 desc = macb_tx_desc(queue, entry);
a4c35ed3
CP		 1418
1419 ctrl = (u32)tx_skb->size;
1420 if (eof) {
1421 ctrl |= MACB_BIT(TX_LAST);
1422 eof = 0;
1423 }
b410d13e 1424 if (unlikely(entry == (bp->tx_ring_size - 1)))
a4c35ed3
CP		 1425 ctrl |= MACB_BIT(TX_WRAP);
1426
1629dd4f
RO		 1427 /* First descriptor is header descriptor */
1428 if (i == queue->tx_head) {
1429 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1430 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1431 } else
1432 /* Only set MSS/MFS on payload descriptors
1433 * (second or later descriptor)
1434 */
1435 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1436
a4c35ed3 1437 /* Set TX buffer descriptor */
dc97a89e 1438 macb_set_addr(bp, desc, tx_skb->mapping);
a4c35ed3
CP		 1439 /* desc->addr must be visible to hardware before clearing
1440 * 'TX_USED' bit in desc->ctrl.
1441 */
1442 wmb();
1443 desc->ctrl = ctrl;
02c958dd 1444 } while (i != queue->tx_head);
a4c35ed3 1445
02c958dd 1446 queue->tx_head = tx_head;
a4c35ed3
CP		 1447
1448 return count;
1449
1450dma_error:
1451 netdev_err(bp->dev, "TX DMA map failed\n");
1452
02c958dd
CP		 1453 for (i = queue->tx_head; i != tx_head; i++) {
1454 tx_skb = macb_tx_skb(queue, i);
a4c35ed3
CP		 1455
1456 macb_tx_unmap(bp, tx_skb);
1457 }
1458
1459 return 0;
1460}
1461
1629dd4f
RO		 1462static netdev_features_t macb_features_check(struct sk_buff *skb,
1463 struct net_device *dev,
1464 netdev_features_t features)
1465{
1466 unsigned int nr_frags, f;
1467 unsigned int hdrlen;
1468
1469 /* Validate LSO compatibility */
1470
1471 /* there is only one buffer */
1472 if (!skb_is_nonlinear(skb))
1473 return features;
1474
1475 /* length of header */
1476 hdrlen = skb_transport_offset(skb);
1477 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
1478 hdrlen += tcp_hdrlen(skb);
1479
1480 /* For LSO:
1481 * When software supplies two or more payload buffers all payload buffers
1482 * apart from the last must be a multiple of 8 bytes in size.
1483 */
1484 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1485 return features & ~MACB_NETIF_LSO;
1486
1487 nr_frags = skb_shinfo(skb)->nr_frags;
1488 /* No need to check last fragment */
1489 nr_frags--;
1490 for (f = 0; f < nr_frags; f++) {
1491 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1492
1493 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1494 return features & ~MACB_NETIF_LSO;
1495 }
1496 return features;
1497}
1498
007e4ba3
HB		 1499static inline int macb_clear_csum(struct sk_buff *skb)
1500{
1501 /* no change for packets without checksum offloading */
1502 if (skb->ip_summed != CHECKSUM_PARTIAL)
1503 return 0;
1504
1505 /* make sure we can modify the header */
1506 if (unlikely(skb_cow_head(skb, 0)))
1507 return -1;
1508
1509 /* initialize checksum field
1510 * This is required - at least for Zynq, which otherwise calculates
1511 * wrong UDP header checksums for UDP packets with UDP data len <=2
1512 */
1513 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1514 return 0;
1515}
1516
a4c35ed3
CP		 1517static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1518{
02c958dd 1519 u16 queue_index = skb_get_queue_mapping(skb);
a4c35ed3 1520 struct macb *bp = netdev_priv(dev);
02c958dd 1521 struct macb_queue *queue = &bp->queues[queue_index];
4871953c 1522 unsigned long flags;
1629dd4f
RO		 1523 unsigned int desc_cnt, nr_frags, frag_size, f;
1524 unsigned int hdrlen;
1525 bool is_lso, is_udp = 0;
1526
1527 is_lso = (skb_shinfo(skb)->gso_size != 0);
1528
1529 if (is_lso) {
1530 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1531
1532 /* length of headers */
1533 if (is_udp)
1534 /* only queue eth + ip headers separately for UDP */
1535 hdrlen = skb_transport_offset(skb);
1536 else
1537 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1538 if (skb_headlen(skb) < hdrlen) {
1539 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1540 /* if this is required, would need to copy to single buffer */
1541 return NETDEV_TX_BUSY;
1542 }
1543 } else
1544 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
89e5785f 1545
a268adb1
HS		 1546#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1547 netdev_vdbg(bp->dev,
aa50b552
MF		 1548 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1549 queue_index, skb->len, skb->head, skb->data,
1550 skb_tail_pointer(skb), skb_end_pointer(skb));
c220f8cd
JI		 1551 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1552 skb->data, 16, true);
89e5785f
HS		 1553#endif
1554
a4c35ed3
CP		 1555 /* Count how many TX buffer descriptors are needed to send this
1556 * socket buffer: skb fragments of jumbo frames may need to be
aa50b552 1557 * split into many buffer descriptors.
a4c35ed3 1558 */
1629dd4f
RO		 1559 if (is_lso && (skb_headlen(skb) > hdrlen))
1560 /* extra header descriptor if also payload in first buffer */
1561 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1562 else
1563 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
a4c35ed3
CP		 1564 nr_frags = skb_shinfo(skb)->nr_frags;
1565 for (f = 0; f < nr_frags; f++) {
1566 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1629dd4f 1567 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
a4c35ed3
CP		 1568 }
1569
4871953c 1570 spin_lock_irqsave(&bp->lock, flags);
89e5785f
HS		 1571
1572 /* This is a hard error, log it. */
b410d13e 1573 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1629dd4f 1574 bp->tx_ring_size) < desc_cnt) {
02c958dd 1575 netif_stop_subqueue(dev, queue_index);
4871953c 1576 spin_unlock_irqrestore(&bp->lock, flags);
c220f8cd 1577 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
02c958dd 1578 queue->tx_head, queue->tx_tail);
5b548140 1579 return NETDEV_TX_BUSY;
89e5785f
HS		 1580 }
1581
007e4ba3
HB		 1582 if (macb_clear_csum(skb)) {
1583 dev_kfree_skb_any(skb);
a7c22bda 1584 goto unlock;
007e4ba3
HB		 1585 }
1586
a4c35ed3 1587 /* Map socket buffer for DMA transfer */
1629dd4f 1588 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
c88b5b6a 1589 dev_kfree_skb_any(skb);
92030908
SB		 1590 goto unlock;
1591 }
55054a16 1592
03dbe05f 1593 /* Make newly initialized descriptor visible to hardware */
89e5785f
HS		 1594 wmb();
1595
e072092f
RC		 1596 skb_tx_timestamp(skb);
1597
89e5785f
HS		 1598 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1599
b410d13e 1600 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
02c958dd 1601 netif_stop_subqueue(dev, queue_index);
89e5785f 1602
92030908 1603unlock:
4871953c 1604 spin_unlock_irqrestore(&bp->lock, flags);
89e5785f 1605
6ed10654 1606 return NETDEV_TX_OK;
89e5785f
HS		 1607}
1608
4df95131 1609static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1b44791a
NF		 1610{
1611 if (!macb_is_gem(bp)) {
1612 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1613 } else {
4df95131 1614 bp->rx_buffer_size = size;
1b44791a 1615
1b44791a 1616 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
4df95131 1617 netdev_dbg(bp->dev,
aa50b552
MF		 1618 "RX buffer must be multiple of %d bytes, expanding\n",
1619 RX_BUFFER_MULTIPLE);
1b44791a 1620 bp->rx_buffer_size =
4df95131 1621 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1b44791a 1622 }
1b44791a 1623 }
4df95131
NF		 1624
1625 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1626 bp->dev->mtu, bp->rx_buffer_size);
1b44791a
NF		 1627}
1628
4df95131
NF		 1629static void gem_free_rx_buffers(struct macb *bp)
1630{
1631 struct sk_buff *skb;
1632 struct macb_dma_desc *desc;
1633 dma_addr_t addr;
1634 int i;
1635
1636 if (!bp->rx_skbuff)
1637 return;
1638
b410d13e 1639 for (i = 0; i < bp->rx_ring_size; i++) {
4df95131
NF		 1640 skb = bp->rx_skbuff[i];
1641
aa50b552 1642 if (!skb)
4df95131
NF		 1643 continue;
1644
dc97a89e
RO		 1645 desc = macb_rx_desc(bp, i);
1646 addr = macb_get_addr(bp, desc);
1647
ccd6d0a9 1648 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
4df95131
NF		 1649 DMA_FROM_DEVICE);
1650 dev_kfree_skb_any(skb);
1651 skb = NULL;
1652 }
1653
1654 kfree(bp->rx_skbuff);
1655 bp->rx_skbuff = NULL;
1656}
1657
1658static void macb_free_rx_buffers(struct macb *bp)
1659{
1660 if (bp->rx_buffers) {
1661 dma_free_coherent(&bp->pdev->dev,
b410d13e 1662 bp->rx_ring_size * bp->rx_buffer_size,
4df95131
NF		 1663 bp->rx_buffers, bp->rx_buffers_dma);
1664 bp->rx_buffers = NULL;
1665 }
1666}
1b44791a 1667
89e5785f
HS		 1668static void macb_free_consistent(struct macb *bp)
1669{
02c958dd
CP		 1670 struct macb_queue *queue;
1671 unsigned int q;
1672
4df95131 1673 bp->macbgem_ops.mog_free_rx_buffers(bp);
89e5785f 1674 if (bp->rx_ring) {
b410d13e 1675 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES(bp),
89e5785f
HS		 1676 bp->rx_ring, bp->rx_ring_dma);
1677 bp->rx_ring = NULL;
1678 }
02c958dd
CP		 1679
1680 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1681 kfree(queue->tx_skb);
1682 queue->tx_skb = NULL;
1683 if (queue->tx_ring) {
b410d13e 1684 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES(bp),
02c958dd
CP		 1685 queue->tx_ring, queue->tx_ring_dma);
1686 queue->tx_ring = NULL;
1687 }
89e5785f 1688 }
4df95131
NF		 1689}
1690
1691static int gem_alloc_rx_buffers(struct macb *bp)
1692{
1693 int size;
1694
b410d13e 1695 size = bp->rx_ring_size * sizeof(struct sk_buff *);
4df95131
NF		 1696 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1697 if (!bp->rx_skbuff)
1698 return -ENOMEM;
b410d13e
ZB		 1699 else
1700 netdev_dbg(bp->dev,
1701 "Allocated %d RX struct sk_buff entries at %p\n",
1702 bp->rx_ring_size, bp->rx_skbuff);
4df95131
NF		 1703 return 0;
1704}
1705
1706static int macb_alloc_rx_buffers(struct macb *bp)
1707{
1708 int size;
1709
b410d13e 1710 size = bp->rx_ring_size * bp->rx_buffer_size;
4df95131
NF		 1711 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1712 &bp->rx_buffers_dma, GFP_KERNEL);
1713 if (!bp->rx_buffers)
1714 return -ENOMEM;
64ec42fe
MF		 1715
1716 netdev_dbg(bp->dev,
1717 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1718 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
4df95131 1719 return 0;
89e5785f
HS		 1720}
1721
1722static int macb_alloc_consistent(struct macb *bp)
1723{
02c958dd
CP		 1724 struct macb_queue *queue;
1725 unsigned int q;
89e5785f
HS		 1726 int size;
1727
02c958dd 1728 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
b410d13e 1729 size = TX_RING_BYTES(bp);
02c958dd
CP		 1730 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1731 &queue->tx_ring_dma,
1732 GFP_KERNEL);
1733 if (!queue->tx_ring)
1734 goto out_err;
1735 netdev_dbg(bp->dev,
1736 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1737 q, size, (unsigned long)queue->tx_ring_dma,
1738 queue->tx_ring);
1739
b410d13e 1740 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
02c958dd
CP		 1741 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1742 if (!queue->tx_skb)
1743 goto out_err;
1744 }
89e5785f 1745
b410d13e 1746 size = RX_RING_BYTES(bp);
89e5785f
HS		 1747 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1748 &bp->rx_ring_dma, GFP_KERNEL);
1749 if (!bp->rx_ring)
1750 goto out_err;
c220f8cd
JI		 1751 netdev_dbg(bp->dev,
1752 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1753 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
89e5785f 1754
4df95131 1755 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
89e5785f 1756 goto out_err;
89e5785f
HS		 1757
1758 return 0;
1759
1760out_err:
1761 macb_free_consistent(bp);
1762 return -ENOMEM;
1763}
1764
4df95131
NF		 1765static void gem_init_rings(struct macb *bp)
1766{
02c958dd 1767 struct macb_queue *queue;
dc97a89e 1768 struct macb_dma_desc *desc = NULL;
02c958dd 1769 unsigned int q;
4df95131
NF		 1770 int i;
1771
02c958dd 1772 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
b410d13e 1773 for (i = 0; i < bp->tx_ring_size; i++) {
dc97a89e
RO		 1774 desc = macb_tx_desc(queue, i);
1775 macb_set_addr(bp, desc, 0);
1776 desc->ctrl = MACB_BIT(TX_USED);
02c958dd 1777 }
dc97a89e 1778 desc->ctrl |= MACB_BIT(TX_WRAP);
02c958dd
CP		 1779 queue->tx_head = 0;
1780 queue->tx_tail = 0;
4df95131 1781 }
4df95131 1782
02c958dd
CP		 1783 bp->rx_tail = 0;
1784 bp->rx_prepared_head = 0;
4df95131
NF		 1785
1786 gem_rx_refill(bp);
1787}
1788
89e5785f
HS		 1789static void macb_init_rings(struct macb *bp)
1790{
1791 int i;
dc97a89e 1792 struct macb_dma_desc *desc = NULL;
89e5785f 1793
9ba723b0 1794 macb_init_rx_ring(bp);
89e5785f 1795
b410d13e 1796 for (i = 0; i < bp->tx_ring_size; i++) {
dc97a89e
RO		 1797 desc = macb_tx_desc(&bp->queues[0], i);
1798 macb_set_addr(bp, desc, 0);
1799 desc->ctrl = MACB_BIT(TX_USED);
89e5785f 1800 }
21d3515c
BS		 1801 bp->queues[0].tx_head = 0;
1802 bp->queues[0].tx_tail = 0;
dc97a89e 1803 desc->ctrl |= MACB_BIT(TX_WRAP);
89e5785f
HS		 1804}
1805
1806static void macb_reset_hw(struct macb *bp)
1807{
02c958dd
CP		 1808 struct macb_queue *queue;
1809 unsigned int q;
1810
64ec42fe 1811 /* Disable RX and TX (XXX: Should we halt the transmission
89e5785f
HS		 1812 * more gracefully?)
1813 */
1814 macb_writel(bp, NCR, 0);
1815
1816 /* Clear the stats registers (XXX: Update stats first?) */
1817 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1818
1819 /* Clear all status flags */
95ebcea6
JE		 1820 macb_writel(bp, TSR, -1);
1821 macb_writel(bp, RSR, -1);
89e5785f
HS		 1822
1823 /* Disable all interrupts */
02c958dd
CP		 1824 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1825 queue_writel(queue, IDR, -1);
1826 queue_readl(queue, ISR);
24468374
NS		 1827 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1828 queue_writel(queue, ISR, -1);
02c958dd 1829 }
89e5785f
HS		 1830}
1831
70c9f3d4
JI		 1832static u32 gem_mdc_clk_div(struct macb *bp)
1833{
1834 u32 config;
1835 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1836
1837 if (pclk_hz <= 20000000)
1838 config = GEM_BF(CLK, GEM_CLK_DIV8);
1839 else if (pclk_hz <= 40000000)
1840 config = GEM_BF(CLK, GEM_CLK_DIV16);
1841 else if (pclk_hz <= 80000000)
1842 config = GEM_BF(CLK, GEM_CLK_DIV32);
1843 else if (pclk_hz <= 120000000)
1844 config = GEM_BF(CLK, GEM_CLK_DIV48);
1845 else if (pclk_hz <= 160000000)
1846 config = GEM_BF(CLK, GEM_CLK_DIV64);
1847 else
1848 config = GEM_BF(CLK, GEM_CLK_DIV96);
1849
1850 return config;
1851}
1852
1853static u32 macb_mdc_clk_div(struct macb *bp)
1854{
1855 u32 config;
1856 unsigned long pclk_hz;
1857
1858 if (macb_is_gem(bp))
1859 return gem_mdc_clk_div(bp);
1860
1861 pclk_hz = clk_get_rate(bp->pclk);
1862 if (pclk_hz <= 20000000)
1863 config = MACB_BF(CLK, MACB_CLK_DIV8);
1864 else if (pclk_hz <= 40000000)
1865 config = MACB_BF(CLK, MACB_CLK_DIV16);
1866 else if (pclk_hz <= 80000000)
1867 config = MACB_BF(CLK, MACB_CLK_DIV32);
1868 else
1869 config = MACB_BF(CLK, MACB_CLK_DIV64);
1870
1871 return config;
1872}
1873
64ec42fe 1874/* Get the DMA bus width field of the network configuration register that we
757a03c6
JI		 1875 * should program. We find the width from decoding the design configuration
1876 * register to find the maximum supported data bus width.
1877 */
1878static u32 macb_dbw(struct macb *bp)
1879{
1880 if (!macb_is_gem(bp))
1881 return 0;
1882
1883 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1884 case 4:
1885 return GEM_BF(DBW, GEM_DBW128);
1886 case 2:
1887 return GEM_BF(DBW, GEM_DBW64);
1888 case 1:
1889 default:
1890 return GEM_BF(DBW, GEM_DBW32);
1891 }
1892}
1893
64ec42fe 1894/* Configure the receive DMA engine
b3e3bd71 1895 * - use the correct receive buffer size
e175587f 1896 * - set best burst length for DMA operations
b3e3bd71
NF		 1897 * (if not supported by FIFO, it will fallback to default)
1898 * - set both rx/tx packet buffers to full memory size
1899 * These are configurable parameters for GEM.
0116da4f
JI		 1900 */
1901static void macb_configure_dma(struct macb *bp)
1902{
1903 u32 dmacfg;
1904
1905 if (macb_is_gem(bp)) {
1906 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1b44791a 1907 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
e175587f
NF		 1908 if (bp->dma_burst_length)
1909 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
b3e3bd71 1910 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
a50dad35 1911 dmacfg &= ~GEM_BIT(ENDIA_PKT);
62f6924c 1912
f2ce8a9e 1913 if (bp->native_io)
62f6924c
AC		 1914 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1915 else
1916 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1917
85ff3d87
CP		 1918 if (bp->dev->features & NETIF_F_HW_CSUM)
1919 dmacfg |= GEM_BIT(TXCOEN);
1920 else
1921 dmacfg &= ~GEM_BIT(TXCOEN);
fff8019a
HK		 1922
1923#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
dc97a89e
RO		 1924 if (bp->hw_dma_cap == HW_DMA_CAP_64B)
1925 dmacfg |= GEM_BIT(ADDR64);
fff8019a 1926#endif
e175587f
NF		 1927 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1928 dmacfg);
0116da4f
JI		 1929 gem_writel(bp, DMACFG, dmacfg);
1930 }
1931}
1932
89e5785f
HS		 1933static void macb_init_hw(struct macb *bp)
1934{
02c958dd
CP		 1935 struct macb_queue *queue;
1936 unsigned int q;
1937
89e5785f
HS		 1938 u32 config;
1939
1940 macb_reset_hw(bp);
314bccc4 1941 macb_set_hwaddr(bp);
89e5785f 1942
70c9f3d4 1943 config = macb_mdc_clk_div(bp);
022be25c
PCK		 1944 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
1945 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
29bc2e1e 1946 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
89e5785f
HS		 1947 config |= MACB_BIT(PAE); /* PAuse Enable */
1948 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
a104a6b3 1949 if (bp->caps & MACB_CAPS_JUMBO)
98b5a0f4
HK		 1950 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
1951 else
1952 config |= MACB_BIT(BIG); /* Receive oversized frames */
89e5785f
HS		 1953 if (bp->dev->flags & IFF_PROMISC)
1954 config |= MACB_BIT(CAF); /* Copy All Frames */
924ec53c
CP		 1955 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1956 config |= GEM_BIT(RXCOEN);
89e5785f
HS		 1957 if (!(bp->dev->flags & IFF_BROADCAST))
1958 config |= MACB_BIT(NBC); /* No BroadCast */
757a03c6 1959 config |= macb_dbw(bp);
89e5785f 1960 macb_writel(bp, NCFGR, config);
a104a6b3 1961 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
98b5a0f4 1962 gem_writel(bp, JML, bp->jumbo_max_len);
26cdfb49
VD		 1963 bp->speed = SPEED_10;
1964 bp->duplex = DUPLEX_HALF;
98b5a0f4 1965 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
a104a6b3 1966 if (bp->caps & MACB_CAPS_JUMBO)
98b5a0f4 1967 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
89e5785f 1968
0116da4f
JI		 1969 macb_configure_dma(bp);
1970
89e5785f 1971 /* Initialize TX and RX buffers */
dc97a89e 1972 macb_writel(bp, RBQP, lower_32_bits(bp->rx_ring_dma));
fff8019a 1973#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
dc97a89e
RO		 1974 if (bp->hw_dma_cap == HW_DMA_CAP_64B)
1975 macb_writel(bp, RBQPH, upper_32_bits(bp->rx_ring_dma));
fff8019a 1976#endif
02c958dd 1977 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
dc97a89e 1978 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
fff8019a 1979#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
dc97a89e
RO		 1980 if (bp->hw_dma_cap == HW_DMA_CAP_64B)
1981 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
fff8019a 1982#endif
02c958dd
CP		 1983
1984 /* Enable interrupts */
1985 queue_writel(queue, IER,
1986 MACB_RX_INT_FLAGS |
1987 MACB_TX_INT_FLAGS |
1988 MACB_BIT(HRESP));
1989 }
89e5785f
HS		 1990
1991 /* Enable TX and RX */
6c36a707 1992 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS		 1993}
1994
64ec42fe 1995/* The hash address register is 64 bits long and takes up two
446ebd01
PV		 1996 * locations in the memory map. The least significant bits are stored
1997 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1998 *
1999 * The unicast hash enable and the multicast hash enable bits in the
2000 * network configuration register enable the reception of hash matched
2001 * frames. The destination address is reduced to a 6 bit index into
2002 * the 64 bit hash register using the following hash function. The
2003 * hash function is an exclusive or of every sixth bit of the
2004 * destination address.
2005 *
2006 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2007 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2008 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2009 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2010 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2011 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2012 *
2013 * da[0] represents the least significant bit of the first byte
2014 * received, that is, the multicast/unicast indicator, and da[47]
2015 * represents the most significant bit of the last byte received. If
2016 * the hash index, hi[n], points to a bit that is set in the hash
2017 * register then the frame will be matched according to whether the
2018 * frame is multicast or unicast. A multicast match will be signalled
2019 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2020 * index points to a bit set in the hash register. A unicast match
2021 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2022 * and the hash index points to a bit set in the hash register. To
2023 * receive all multicast frames, the hash register should be set with
2024 * all ones and the multicast hash enable bit should be set in the
2025 * network configuration register.
2026 */
2027
2028static inline int hash_bit_value(int bitnr, __u8 *addr)
2029{
2030 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2031 return 1;
2032 return 0;
2033}
2034
64ec42fe 2035/* Return the hash index value for the specified address. */
446ebd01
PV		 2036static int hash_get_index(__u8 *addr)
2037{
2038 int i, j, bitval;
2039 int hash_index = 0;
2040
2041 for (j = 0; j < 6; j++) {
2042 for (i = 0, bitval = 0; i < 8; i++)
2fa45e22 2043 bitval ^= hash_bit_value(i * 6 + j, addr);
446ebd01
PV		 2044
2045 hash_index |= (bitval << j);
2046 }
2047
2048 return hash_index;
2049}
2050
64ec42fe 2051/* Add multicast addresses to the internal multicast-hash table. */
446ebd01
PV		 2052static void macb_sethashtable(struct net_device *dev)
2053{
22bedad3 2054 struct netdev_hw_addr *ha;
446ebd01 2055 unsigned long mc_filter[2];
f9dcbcc9 2056 unsigned int bitnr;
446ebd01
PV		 2057 struct macb *bp = netdev_priv(dev);
2058
aa50b552
MF		 2059 mc_filter[0] = 0;
2060 mc_filter[1] = 0;
446ebd01 2061
22bedad3
JP		 2062 netdev_for_each_mc_addr(ha, dev) {
2063 bitnr = hash_get_index(ha->addr);
446ebd01
PV		 2064 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2065 }
2066
f75ba50b
JI		 2067 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2068 macb_or_gem_writel(bp, HRT, mc_filter[1]);
446ebd01
PV		 2069}
2070
64ec42fe 2071/* Enable/Disable promiscuous and multicast modes. */
421d9df0 2072static void macb_set_rx_mode(struct net_device *dev)
446ebd01
PV		 2073{
2074 unsigned long cfg;
2075 struct macb *bp = netdev_priv(dev);
2076
2077 cfg = macb_readl(bp, NCFGR);
2078
924ec53c 2079 if (dev->flags & IFF_PROMISC) {
446ebd01
PV		 2080 /* Enable promiscuous mode */
2081 cfg |= MACB_BIT(CAF);
924ec53c
CP		 2082
2083 /* Disable RX checksum offload */
2084 if (macb_is_gem(bp))
2085 cfg &= ~GEM_BIT(RXCOEN);
2086 } else {
2087 /* Disable promiscuous mode */
446ebd01
PV		 2088 cfg &= ~MACB_BIT(CAF);
2089
924ec53c
CP		 2090 /* Enable RX checksum offload only if requested */
2091 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2092 cfg |= GEM_BIT(RXCOEN);
2093 }
2094
446ebd01
PV		 2095 if (dev->flags & IFF_ALLMULTI) {
2096 /* Enable all multicast mode */
f75ba50b
JI		 2097 macb_or_gem_writel(bp, HRB, -1);
2098 macb_or_gem_writel(bp, HRT, -1);
446ebd01 2099 cfg |= MACB_BIT(NCFGR_MTI);
4cd24eaf 2100 } else if (!netdev_mc_empty(dev)) {
446ebd01
PV		 2101 /* Enable specific multicasts */
2102 macb_sethashtable(dev);
2103 cfg |= MACB_BIT(NCFGR_MTI);
2104 } else if (dev->flags & (~IFF_ALLMULTI)) {
2105 /* Disable all multicast mode */
f75ba50b
JI		 2106 macb_or_gem_writel(bp, HRB, 0);
2107 macb_or_gem_writel(bp, HRT, 0);
446ebd01
PV		 2108 cfg &= ~MACB_BIT(NCFGR_MTI);
2109 }
2110
2111 macb_writel(bp, NCFGR, cfg);
2112}
2113
89e5785f
HS		 2114static int macb_open(struct net_device *dev)
2115{
2116 struct macb *bp = netdev_priv(dev);
4df95131 2117 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
89e5785f
HS		 2118 int err;
2119
c220f8cd 2120 netdev_dbg(bp->dev, "open\n");
89e5785f 2121
03fc4721
NF		 2122 /* carrier starts down */
2123 netif_carrier_off(dev);
2124
6c36a707 2125 /* if the phy is not yet register, retry later*/
0a91281e 2126 if (!dev->phydev)
6c36a707 2127 return -EAGAIN;
1b44791a
NF		 2128
2129 /* RX buffers initialization */
4df95131 2130 macb_init_rx_buffer_size(bp, bufsz);
6c36a707 2131
89e5785f
HS		 2132 err = macb_alloc_consistent(bp);
2133 if (err) {
c220f8cd
JI		 2134 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2135 err);
89e5785f
HS		 2136 return err;
2137 }
2138
bea3348e
SH		 2139 napi_enable(&bp->napi);
2140
4df95131 2141 bp->macbgem_ops.mog_init_rings(bp);
89e5785f 2142 macb_init_hw(bp);
89e5785f 2143
6c36a707 2144 /* schedule a link state check */
0a91281e 2145 phy_start(dev->phydev);
89e5785f 2146
02c958dd 2147 netif_tx_start_all_queues(dev);
89e5785f
HS		 2148
2149 return 0;
2150}
2151
2152static int macb_close(struct net_device *dev)
2153{
2154 struct macb *bp = netdev_priv(dev);
2155 unsigned long flags;
2156
02c958dd 2157 netif_tx_stop_all_queues(dev);
bea3348e 2158 napi_disable(&bp->napi);
89e5785f 2159
0a91281e
PR		 2160 if (dev->phydev)
2161 phy_stop(dev->phydev);
6c36a707 2162
89e5785f
HS		 2163 spin_lock_irqsave(&bp->lock, flags);
2164 macb_reset_hw(bp);
2165 netif_carrier_off(dev);
2166 spin_unlock_irqrestore(&bp->lock, flags);
2167
2168 macb_free_consistent(bp);
2169
2170 return 0;
2171}
2172
a5898ea0
HK		 2173static int macb_change_mtu(struct net_device *dev, int new_mtu)
2174{
a5898ea0
HK		 2175 if (netif_running(dev))
2176 return -EBUSY;
2177
a5898ea0
HK		 2178 dev->mtu = new_mtu;
2179
2180 return 0;
2181}
2182
a494ed8e
JI		 2183static void gem_update_stats(struct macb *bp)
2184{
8bcbf82f 2185 unsigned int i;
a494ed8e 2186 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
a494ed8e 2187
3ff13f1c
XH		 2188 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2189 u32 offset = gem_statistics[i].offset;
7a6e0706 2190 u64 val = bp->macb_reg_readl(bp, offset);
3ff13f1c
XH		 2191
2192 bp->ethtool_stats[i] += val;
2193 *p += val;
2194
2195 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2196 /* Add GEM_OCTTXH, GEM_OCTRXH */
7a6e0706 2197 val = bp->macb_reg_readl(bp, offset + 4);
2fa45e22 2198 bp->ethtool_stats[i] += ((u64)val) << 32;
3ff13f1c
XH		 2199 *(++p) += val;
2200 }
2201 }
a494ed8e
JI		 2202}
2203
2204static struct net_device_stats *gem_get_stats(struct macb *bp)
2205{
2206 struct gem_stats *hwstat = &bp->hw_stats.gem;
2207 struct net_device_stats *nstat = &bp->stats;
2208
2209 gem_update_stats(bp);
2210
2211 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2212 hwstat->rx_alignment_errors +
2213 hwstat->rx_resource_errors +
2214 hwstat->rx_overruns +
2215 hwstat->rx_oversize_frames +
2216 hwstat->rx_jabbers +
2217 hwstat->rx_undersized_frames +
2218 hwstat->rx_length_field_frame_errors);
2219 nstat->tx_errors = (hwstat->tx_late_collisions +
2220 hwstat->tx_excessive_collisions +
2221 hwstat->tx_underrun +
2222 hwstat->tx_carrier_sense_errors);
2223 nstat->multicast = hwstat->rx_multicast_frames;
2224 nstat->collisions = (hwstat->tx_single_collision_frames +
2225 hwstat->tx_multiple_collision_frames +
2226 hwstat->tx_excessive_collisions);
2227 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2228 hwstat->rx_jabbers +
2229 hwstat->rx_undersized_frames +
2230 hwstat->rx_length_field_frame_errors);
2231 nstat->rx_over_errors = hwstat->rx_resource_errors;
2232 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2233 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2234 nstat->rx_fifo_errors = hwstat->rx_overruns;
2235 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2236 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2237 nstat->tx_fifo_errors = hwstat->tx_underrun;
2238
2239 return nstat;
2240}
2241
3ff13f1c
XH		 2242static void gem_get_ethtool_stats(struct net_device *dev,
2243 struct ethtool_stats *stats, u64 *data)
2244{
2245 struct macb *bp;
2246
2247 bp = netdev_priv(dev);
2248 gem_update_stats(bp);
2fa45e22 2249 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
3ff13f1c
XH		 2250}
2251
2252static int gem_get_sset_count(struct net_device *dev, int sset)
2253{
2254 switch (sset) {
2255 case ETH_SS_STATS:
2256 return GEM_STATS_LEN;
2257 default:
2258 return -EOPNOTSUPP;
2259 }
2260}
2261
2262static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2263{
8bcbf82f 2264 unsigned int i;
3ff13f1c
XH		 2265
2266 switch (sset) {
2267 case ETH_SS_STATS:
2268 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2269 memcpy(p, gem_statistics[i].stat_string,
2270 ETH_GSTRING_LEN);
2271 break;
2272 }
2273}
2274
421d9df0 2275static struct net_device_stats *macb_get_stats(struct net_device *dev)
89e5785f
HS		 2276{
2277 struct macb *bp = netdev_priv(dev);
2278 struct net_device_stats *nstat = &bp->stats;
a494ed8e
JI		 2279 struct macb_stats *hwstat = &bp->hw_stats.macb;
2280
2281 if (macb_is_gem(bp))
2282 return gem_get_stats(bp);
89e5785f 2283
6c36a707
R		 2284 /* read stats from hardware */
2285 macb_update_stats(bp);
2286
89e5785f
HS		 2287 /* Convert HW stats into netdevice stats */
2288 nstat->rx_errors = (hwstat->rx_fcs_errors +
2289 hwstat->rx_align_errors +
2290 hwstat->rx_resource_errors +
2291 hwstat->rx_overruns +
2292 hwstat->rx_oversize_pkts +
2293 hwstat->rx_jabbers +
2294 hwstat->rx_undersize_pkts +
89e5785f
HS		 2295 hwstat->rx_length_mismatch);
2296 nstat->tx_errors = (hwstat->tx_late_cols +
2297 hwstat->tx_excessive_cols +
2298 hwstat->tx_underruns +
716723c2
WS		 2299 hwstat->tx_carrier_errors +
2300 hwstat->sqe_test_errors);
89e5785f
HS		 2301 nstat->collisions = (hwstat->tx_single_cols +
2302 hwstat->tx_multiple_cols +
2303 hwstat->tx_excessive_cols);
2304 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2305 hwstat->rx_jabbers +
2306 hwstat->rx_undersize_pkts +
2307 hwstat->rx_length_mismatch);
b19f7f71
AS		 2308 nstat->rx_over_errors = hwstat->rx_resource_errors +
2309 hwstat->rx_overruns;
89e5785f
HS		 2310 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2311 nstat->rx_frame_errors = hwstat->rx_align_errors;
2312 nstat->rx_fifo_errors = hwstat->rx_overruns;
2313 /* XXX: What does "missed" mean? */
2314 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2315 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2316 nstat->tx_fifo_errors = hwstat->tx_underruns;
2317 /* Don't know about heartbeat or window errors... */
2318
2319 return nstat;
2320}
2321
d1d1b53d
NF		 2322static int macb_get_regs_len(struct net_device *netdev)
2323{
2324 return MACB_GREGS_NBR * sizeof(u32);
2325}
2326
2327static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2328 void *p)
2329{
2330 struct macb *bp = netdev_priv(dev);
2331 unsigned int tail, head;
2332 u32 *regs_buff = p;
2333
2334 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2335 | MACB_GREGS_VERSION;
2336
b410d13e
ZB		 2337 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2338 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
d1d1b53d
NF		 2339
2340 regs_buff[0] = macb_readl(bp, NCR);
2341 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2342 regs_buff[2] = macb_readl(bp, NSR);
2343 regs_buff[3] = macb_readl(bp, TSR);
2344 regs_buff[4] = macb_readl(bp, RBQP);
2345 regs_buff[5] = macb_readl(bp, TBQP);
2346 regs_buff[6] = macb_readl(bp, RSR);
2347 regs_buff[7] = macb_readl(bp, IMR);
2348
2349 regs_buff[8] = tail;
2350 regs_buff[9] = head;
02c958dd
CP		 2351 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2352 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
d1d1b53d 2353
ce721a70
NA		 2354 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2355 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
64ec42fe 2356 if (macb_is_gem(bp))
d1d1b53d 2357 regs_buff[13] = gem_readl(bp, DMACFG);
d1d1b53d
NF		 2358}
2359
3e2a5e15
SP		 2360static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2361{
2362 struct macb *bp = netdev_priv(netdev);
2363
2364 wol->supported = 0;
2365 wol->wolopts = 0;
2366
2367 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2368 wol->supported = WAKE_MAGIC;
2369
2370 if (bp->wol & MACB_WOL_ENABLED)
2371 wol->wolopts |= WAKE_MAGIC;
2372 }
2373}
2374
2375static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2376{
2377 struct macb *bp = netdev_priv(netdev);
2378
2379 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2380 (wol->wolopts & ~WAKE_MAGIC))
2381 return -EOPNOTSUPP;
2382
2383 if (wol->wolopts & WAKE_MAGIC)
2384 bp->wol |= MACB_WOL_ENABLED;
2385 else
2386 bp->wol &= ~MACB_WOL_ENABLED;
2387
2388 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2389
2390 return 0;
2391}
2392
8441bb33
ZB		 2393static void macb_get_ringparam(struct net_device *netdev,
2394 struct ethtool_ringparam *ring)
2395{
2396 struct macb *bp = netdev_priv(netdev);
2397
2398 ring->rx_max_pending = MAX_RX_RING_SIZE;
2399 ring->tx_max_pending = MAX_TX_RING_SIZE;
2400
2401 ring->rx_pending = bp->rx_ring_size;
2402 ring->tx_pending = bp->tx_ring_size;
2403}
2404
2405static int macb_set_ringparam(struct net_device *netdev,
2406 struct ethtool_ringparam *ring)
2407{
2408 struct macb *bp = netdev_priv(netdev);
2409 u32 new_rx_size, new_tx_size;
2410 unsigned int reset = 0;
2411
2412 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2413 return -EINVAL;
2414
2415 new_rx_size = clamp_t(u32, ring->rx_pending,
2416 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2417 new_rx_size = roundup_pow_of_two(new_rx_size);
2418
2419 new_tx_size = clamp_t(u32, ring->tx_pending,
2420 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2421 new_tx_size = roundup_pow_of_two(new_tx_size);
2422
2423 if ((new_tx_size == bp->tx_ring_size) &&
2424 (new_rx_size == bp->rx_ring_size)) {
2425 /* nothing to do */
2426 return 0;
2427 }
2428
2429 if (netif_running(bp->dev)) {
2430 reset = 1;
2431 macb_close(bp->dev);
2432 }
2433
2434 bp->rx_ring_size = new_rx_size;
2435 bp->tx_ring_size = new_tx_size;
2436
2437 if (reset)
2438 macb_open(bp->dev);
2439
2440 return 0;
2441}
2442
421d9df0 2443static const struct ethtool_ops macb_ethtool_ops = {
d1d1b53d
NF		 2444 .get_regs_len = macb_get_regs_len,
2445 .get_regs = macb_get_regs,
89e5785f 2446 .get_link = ethtool_op_get_link,
17f393e8 2447 .get_ts_info = ethtool_op_get_ts_info,
3e2a5e15
SP		 2448 .get_wol = macb_get_wol,
2449 .set_wol = macb_set_wol,
176275a2
PR		 2450 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2451 .set_link_ksettings = phy_ethtool_set_link_ksettings,
8441bb33
ZB		 2452 .get_ringparam = macb_get_ringparam,
2453 .set_ringparam = macb_set_ringparam,
8cd5a56c 2454};
8cd5a56c 2455
8093b1c3 2456static const struct ethtool_ops gem_ethtool_ops = {
8cd5a56c
XH		 2457 .get_regs_len = macb_get_regs_len,
2458 .get_regs = macb_get_regs,
2459 .get_link = ethtool_op_get_link,
2460 .get_ts_info = ethtool_op_get_ts_info,
3ff13f1c
XH		 2461 .get_ethtool_stats = gem_get_ethtool_stats,
2462 .get_strings = gem_get_ethtool_strings,
2463 .get_sset_count = gem_get_sset_count,
176275a2
PR		 2464 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2465 .set_link_ksettings = phy_ethtool_set_link_ksettings,
8441bb33
ZB		 2466 .get_ringparam = macb_get_ringparam,
2467 .set_ringparam = macb_set_ringparam,
89e5785f
HS		 2468};
2469
421d9df0 2470static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
89e5785f 2471{
0a91281e 2472 struct phy_device *phydev = dev->phydev;
89e5785f
HS		 2473
2474 if (!netif_running(dev))
2475 return -EINVAL;
2476
6c36a707
R		 2477 if (!phydev)
2478 return -ENODEV;
89e5785f 2479
28b04113 2480 return phy_mii_ioctl(phydev, rq, cmd);
89e5785f
HS		 2481}
2482
85ff3d87
CP		 2483static int macb_set_features(struct net_device *netdev,
2484 netdev_features_t features)
2485{
2486 struct macb *bp = netdev_priv(netdev);
2487 netdev_features_t changed = features ^ netdev->features;
2488
2489 /* TX checksum offload */
2490 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2491 u32 dmacfg;
2492
2493 dmacfg = gem_readl(bp, DMACFG);
2494 if (features & NETIF_F_HW_CSUM)
2495 dmacfg |= GEM_BIT(TXCOEN);
2496 else
2497 dmacfg &= ~GEM_BIT(TXCOEN);
2498 gem_writel(bp, DMACFG, dmacfg);
2499 }
2500
924ec53c
CP		 2501 /* RX checksum offload */
2502 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2503 u32 netcfg;
2504
2505 netcfg = gem_readl(bp, NCFGR);
2506 if (features & NETIF_F_RXCSUM &&
2507 !(netdev->flags & IFF_PROMISC))
2508 netcfg |= GEM_BIT(RXCOEN);
2509 else
2510 netcfg &= ~GEM_BIT(RXCOEN);
2511 gem_writel(bp, NCFGR, netcfg);
2512 }
2513
85ff3d87
CP		 2514 return 0;
2515}
2516
5f1fa992
AB		 2517static const struct net_device_ops macb_netdev_ops = {
2518 .ndo_open = macb_open,
2519 .ndo_stop = macb_close,
2520 .ndo_start_xmit = macb_start_xmit,
afc4b13d 2521 .ndo_set_rx_mode = macb_set_rx_mode,
5f1fa992
AB		 2522 .ndo_get_stats = macb_get_stats,
2523 .ndo_do_ioctl = macb_ioctl,
2524 .ndo_validate_addr = eth_validate_addr,
a5898ea0 2525 .ndo_change_mtu = macb_change_mtu,
5f1fa992 2526 .ndo_set_mac_address = eth_mac_addr,
6e8cf5c0
TP		 2527#ifdef CONFIG_NET_POLL_CONTROLLER
2528 .ndo_poll_controller = macb_poll_controller,
2529#endif
85ff3d87 2530 .ndo_set_features = macb_set_features,
1629dd4f 2531 .ndo_features_check = macb_features_check,
5f1fa992
AB		 2532};
2533
64ec42fe 2534/* Configure peripheral capabilities according to device tree
e175587f
NF		 2535 * and integration options used
2536 */
64ec42fe
MF		 2537static void macb_configure_caps(struct macb *bp,
2538 const struct macb_config *dt_conf)
e175587f
NF		 2539{
2540 u32 dcfg;
e175587f 2541
f6970505
NF		 2542 if (dt_conf)
2543 bp->caps = dt_conf->caps;
2544
f2ce8a9e 2545 if (hw_is_gem(bp->regs, bp->native_io)) {
e175587f
NF		 2546 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2547
e175587f
NF		 2548 dcfg = gem_readl(bp, DCFG1);
2549 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2550 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2551 dcfg = gem_readl(bp, DCFG2);
2552 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2553 bp->caps |= MACB_CAPS_FIFO_MODE;
2554 }
2555
a35919e1 2556 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
e175587f
NF		 2557}
2558
02c958dd 2559static void macb_probe_queues(void __iomem *mem,
f2ce8a9e 2560 bool native_io,
02c958dd
CP		 2561 unsigned int *queue_mask,
2562 unsigned int *num_queues)
2563{
2564 unsigned int hw_q;
02c958dd
CP		 2565
2566 *queue_mask = 0x1;
2567 *num_queues = 1;
2568
da120112
NF		 2569 /* is it macb or gem ?
2570 *
2571 * We need to read directly from the hardware here because
2572 * we are early in the probe process and don't have the
2573 * MACB_CAPS_MACB_IS_GEM flag positioned
2574 */
f2ce8a9e 2575 if (!hw_is_gem(mem, native_io))
02c958dd
CP		 2576 return;
2577
2578 /* bit 0 is never set but queue 0 always exists */
a50dad35
AC		 2579 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2580
02c958dd
CP		 2581 *queue_mask |= 0x1;
2582
2583 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2584 if (*queue_mask & (1 << hw_q))
2585 (*num_queues)++;
2586}
2587
c69618b3 2588static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
aead88bd 2589 struct clk **hclk, struct clk **tx_clk,
2590 struct clk **rx_clk)
89e5785f 2591{
83a77e9e 2592 struct macb_platform_data *pdata;
421d9df0 2593 int err;
89e5785f 2594
83a77e9e
BF		 2595 pdata = dev_get_platdata(&pdev->dev);
2596 if (pdata) {
2597 *pclk = pdata->pclk;
2598 *hclk = pdata->hclk;
2599 } else {
2600 *pclk = devm_clk_get(&pdev->dev, "pclk");
2601 *hclk = devm_clk_get(&pdev->dev, "hclk");
2602 }
2603
c69618b3
NF		 2604 if (IS_ERR(*pclk)) {
2605 err = PTR_ERR(*pclk);
b48e0bab 2606 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
421d9df0 2607 return err;
0cc8674f 2608 }
461845db 2609
c69618b3
NF		 2610 if (IS_ERR(*hclk)) {
2611 err = PTR_ERR(*hclk);
b48e0bab 2612 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
421d9df0 2613 return err;
b48e0bab
SB		 2614 }
2615
c69618b3
NF		 2616 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2617 if (IS_ERR(*tx_clk))
2618 *tx_clk = NULL;
e1824dfe 2619
aead88bd 2620 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
2621 if (IS_ERR(*rx_clk))
2622 *rx_clk = NULL;
2623
c69618b3 2624 err = clk_prepare_enable(*pclk);
b48e0bab
SB		 2625 if (err) {
2626 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
421d9df0 2627 return err;
b48e0bab
SB		 2628 }
2629
c69618b3 2630 err = clk_prepare_enable(*hclk);
b48e0bab
SB		 2631 if (err) {
2632 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
421d9df0 2633 goto err_disable_pclk;
89e5785f 2634 }
89e5785f 2635
c69618b3 2636 err = clk_prepare_enable(*tx_clk);
93b31f48
CP		 2637 if (err) {
2638 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
421d9df0 2639 goto err_disable_hclk;
e1824dfe
SB		 2640 }
2641
aead88bd 2642 err = clk_prepare_enable(*rx_clk);
2643 if (err) {
2644 dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err);
2645 goto err_disable_txclk;
2646 }
2647
c69618b3
NF		 2648 return 0;
2649
aead88bd 2650err_disable_txclk:
2651 clk_disable_unprepare(*tx_clk);
2652
c69618b3
NF		 2653err_disable_hclk:
2654 clk_disable_unprepare(*hclk);
2655
2656err_disable_pclk:
2657 clk_disable_unprepare(*pclk);
2658
2659 return err;
2660}
2661
2662static int macb_init(struct platform_device *pdev)
2663{
2664 struct net_device *dev = platform_get_drvdata(pdev);
2665 unsigned int hw_q, q;
2666 struct macb *bp = netdev_priv(dev);
2667 struct macb_queue *queue;
2668 int err;
2669 u32 val;
2670
b410d13e
ZB		 2671 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
2672 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
2673
02c958dd
CP		 2674 /* set the queue register mapping once for all: queue0 has a special
2675 * register mapping but we don't want to test the queue index then
2676 * compute the corresponding register offset at run time.
2677 */
cf250de0 2678 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
bfa0914a 2679 if (!(bp->queue_mask & (1 << hw_q)))
02c958dd
CP		 2680 continue;
2681
cf250de0 2682 queue = &bp->queues[q];
02c958dd
CP		 2683 queue->bp = bp;
2684 if (hw_q) {
2685 queue->ISR = GEM_ISR(hw_q - 1);
2686 queue->IER = GEM_IER(hw_q - 1);
2687 queue->IDR = GEM_IDR(hw_q - 1);
2688 queue->IMR = GEM_IMR(hw_q - 1);
2689 queue->TBQP = GEM_TBQP(hw_q - 1);
fff8019a 2690#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
dc97a89e
RO		 2691 if (bp->hw_dma_cap == HW_DMA_CAP_64B)
2692 queue->TBQPH = GEM_TBQPH(hw_q - 1);
fff8019a 2693#endif
02c958dd
CP		 2694 } else {
2695 /* queue0 uses legacy registers */
2696 queue->ISR = MACB_ISR;
2697 queue->IER = MACB_IER;
2698 queue->IDR = MACB_IDR;
2699 queue->IMR = MACB_IMR;
2700 queue->TBQP = MACB_TBQP;
fff8019a 2701#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
dc97a89e
RO		 2702 if (bp->hw_dma_cap == HW_DMA_CAP_64B)
2703 queue->TBQPH = MACB_TBQPH;
fff8019a 2704#endif
02c958dd
CP		 2705 }
2706
2707 /* get irq: here we use the linux queue index, not the hardware
2708 * queue index. the queue irq definitions in the device tree
2709 * must remove the optional gaps that could exist in the
2710 * hardware queue mask.
2711 */
cf250de0 2712 queue->irq = platform_get_irq(pdev, q);
02c958dd 2713 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
20488239 2714 IRQF_SHARED, dev->name, queue);
02c958dd
CP		 2715 if (err) {
2716 dev_err(&pdev->dev,
2717 "Unable to request IRQ %d (error %d)\n",
2718 queue->irq, err);
c69618b3 2719 return err;
02c958dd
CP		 2720 }
2721
2722 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
cf250de0 2723 q++;
89e5785f
HS		 2724 }
2725
5f1fa992 2726 dev->netdev_ops = &macb_netdev_ops;
bea3348e 2727 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f 2728
4df95131
NF		 2729 /* setup appropriated routines according to adapter type */
2730 if (macb_is_gem(bp)) {
a4c35ed3 2731 bp->max_tx_length = GEM_MAX_TX_LEN;
4df95131
NF		 2732 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2733 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2734 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2735 bp->macbgem_ops.mog_rx = gem_rx;
8cd5a56c 2736 dev->ethtool_ops = &gem_ethtool_ops;
4df95131 2737 } else {
a4c35ed3 2738 bp->max_tx_length = MACB_MAX_TX_LEN;
4df95131
NF		 2739 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2740 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2741 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2742 bp->macbgem_ops.mog_rx = macb_rx;
8cd5a56c 2743 dev->ethtool_ops = &macb_ethtool_ops;
4df95131
NF		 2744 }
2745
a4c35ed3
CP		 2746 /* Set features */
2747 dev->hw_features = NETIF_F_SG;
1629dd4f
RO		 2748
2749 /* Check LSO capability */
2750 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
2751 dev->hw_features |= MACB_NETIF_LSO;
2752
85ff3d87
CP		 2753 /* Checksum offload is only available on gem with packet buffer */
2754 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
924ec53c 2755 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
a4c35ed3
CP		 2756 if (bp->caps & MACB_CAPS_SG_DISABLED)
2757 dev->hw_features &= ~NETIF_F_SG;
2758 dev->features = dev->hw_features;
2759
ce721a70
NA		 2760 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
2761 val = 0;
2762 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2763 val = GEM_BIT(RGMII);
2764 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
6bdaa5e9 2765 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
ce721a70 2766 val = MACB_BIT(RMII);
6bdaa5e9 2767 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
ce721a70 2768 val = MACB_BIT(MII);
421d9df0 2769
ce721a70
NA		 2770 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2771 val |= MACB_BIT(CLKEN);
421d9df0 2772
ce721a70
NA		 2773 macb_or_gem_writel(bp, USRIO, val);
2774 }
421d9df0 2775
89e5785f 2776 /* Set MII management clock divider */
421d9df0
CP		 2777 val = macb_mdc_clk_div(bp);
2778 val |= macb_dbw(bp);
022be25c
PCK		 2779 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2780 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
421d9df0
CP		 2781 macb_writel(bp, NCFGR, val);
2782
2783 return 0;
421d9df0
CP		 2784}
2785
2786#if defined(CONFIG_OF)
2787/* 1518 rounded up */
2788#define AT91ETHER_MAX_RBUFF_SZ 0x600
2789/* max number of receive buffers */
2790#define AT91ETHER_MAX_RX_DESCR 9
2791
2792/* Initialize and start the Receiver and Transmit subsystems */
2793static int at91ether_start(struct net_device *dev)
2794{
2795 struct macb *lp = netdev_priv(dev);
dc97a89e 2796 struct macb_dma_desc *desc;
421d9df0
CP		 2797 dma_addr_t addr;
2798 u32 ctl;
2799 int i;
2800
2801 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2802 (AT91ETHER_MAX_RX_DESCR *
dc97a89e 2803 macb_dma_desc_get_size(lp)),
421d9df0
CP		 2804 &lp->rx_ring_dma, GFP_KERNEL);
2805 if (!lp->rx_ring)
2806 return -ENOMEM;
2807
2808 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2809 AT91ETHER_MAX_RX_DESCR *
2810 AT91ETHER_MAX_RBUFF_SZ,
2811 &lp->rx_buffers_dma, GFP_KERNEL);
2812 if (!lp->rx_buffers) {
2813 dma_free_coherent(&lp->pdev->dev,
2814 AT91ETHER_MAX_RX_DESCR *
dc97a89e 2815 macb_dma_desc_get_size(lp),
421d9df0
CP		 2816 lp->rx_ring, lp->rx_ring_dma);
2817 lp->rx_ring = NULL;
2818 return -ENOMEM;
2819 }
2820
2821 addr = lp->rx_buffers_dma;
2822 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
dc97a89e
RO		 2823 desc = macb_rx_desc(lp, i);
2824 macb_set_addr(lp, desc, addr);
2825 desc->ctrl = 0;
421d9df0
CP		 2826 addr += AT91ETHER_MAX_RBUFF_SZ;
2827 }
2828
2829 /* Set the Wrap bit on the last descriptor */
dc97a89e 2830 desc->addr |= MACB_BIT(RX_WRAP);
421d9df0
CP		 2831
2832 /* Reset buffer index */
2833 lp->rx_tail = 0;
2834
2835 /* Program address of descriptor list in Rx Buffer Queue register */
2836 macb_writel(lp, RBQP, lp->rx_ring_dma);
2837
2838 /* Enable Receive and Transmit */
2839 ctl = macb_readl(lp, NCR);
2840 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2841
2842 return 0;
2843}
2844
2845/* Open the ethernet interface */
2846static int at91ether_open(struct net_device *dev)
2847{
2848 struct macb *lp = netdev_priv(dev);
2849 u32 ctl;
2850 int ret;
2851
2852 /* Clear internal statistics */
2853 ctl = macb_readl(lp, NCR);
2854 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2855
2856 macb_set_hwaddr(lp);
2857
2858 ret = at91ether_start(dev);
2859 if (ret)
2860 return ret;
2861
2862 /* Enable MAC interrupts */
2863 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2864 MACB_BIT(RXUBR) |
2865 MACB_BIT(ISR_TUND) |
2866 MACB_BIT(ISR_RLE) |
2867 MACB_BIT(TCOMP) |
2868 MACB_BIT(ISR_ROVR) |
2869 MACB_BIT(HRESP));
2870
2871 /* schedule a link state check */
0a91281e 2872 phy_start(dev->phydev);
421d9df0
CP		 2873
2874 netif_start_queue(dev);
2875
2876 return 0;
2877}
2878
2879/* Close the interface */
2880static int at91ether_close(struct net_device *dev)
2881{
2882 struct macb *lp = netdev_priv(dev);
2883 u32 ctl;
2884
2885 /* Disable Receiver and Transmitter */
2886 ctl = macb_readl(lp, NCR);
2887 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2888
2889 /* Disable MAC interrupts */
2890 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2891 MACB_BIT(RXUBR) |
2892 MACB_BIT(ISR_TUND) |
2893 MACB_BIT(ISR_RLE) |
2894 MACB_BIT(TCOMP) |
2895 MACB_BIT(ISR_ROVR) |
2896 MACB_BIT(HRESP));
2897
2898 netif_stop_queue(dev);
2899
2900 dma_free_coherent(&lp->pdev->dev,
2901 AT91ETHER_MAX_RX_DESCR *
dc97a89e 2902 macb_dma_desc_get_size(lp),
421d9df0
CP		 2903 lp->rx_ring, lp->rx_ring_dma);
2904 lp->rx_ring = NULL;
2905
2906 dma_free_coherent(&lp->pdev->dev,
2907 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2908 lp->rx_buffers, lp->rx_buffers_dma);
2909 lp->rx_buffers = NULL;
2910
2911 return 0;
2912}
2913
2914/* Transmit packet */
2915static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2916{
2917 struct macb *lp = netdev_priv(dev);
2918
2919 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2920 netif_stop_queue(dev);
2921
2922 /* Store packet information (to free when Tx completed) */
2923 lp->skb = skb;
2924 lp->skb_length = skb->len;
2925 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2926 DMA_TO_DEVICE);
178c7ae9
AK		 2927 if (dma_mapping_error(NULL, lp->skb_physaddr)) {
2928 dev_kfree_skb_any(skb);
2929 dev->stats.tx_dropped++;
2930 netdev_err(dev, "%s: DMA mapping error\n", __func__);
2931 return NETDEV_TX_OK;
2932 }
421d9df0
CP		 2933
2934 /* Set address of the data in the Transmit Address register */
2935 macb_writel(lp, TAR, lp->skb_physaddr);
2936 /* Set length of the packet in the Transmit Control register */
2937 macb_writel(lp, TCR, skb->len);
89e5785f 2938
421d9df0
CP		 2939 } else {
2940 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2941 return NETDEV_TX_BUSY;
2942 }
2943
2944 return NETDEV_TX_OK;
2945}
2946
2947/* Extract received frame from buffer descriptors and sent to upper layers.
2948 * (Called from interrupt context)
2949 */
2950static void at91ether_rx(struct net_device *dev)
2951{
2952 struct macb *lp = netdev_priv(dev);
dc97a89e 2953 struct macb_dma_desc *desc;
421d9df0
CP		 2954 unsigned char *p_recv;
2955 struct sk_buff *skb;
2956 unsigned int pktlen;
2957
dc97a89e
RO		 2958 desc = macb_rx_desc(lp, lp->rx_tail);
2959 while (desc->addr & MACB_BIT(RX_USED)) {
421d9df0 2960 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
dc97a89e 2961 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
421d9df0
CP		 2962 skb = netdev_alloc_skb(dev, pktlen + 2);
2963 if (skb) {
2964 skb_reserve(skb, 2);
2965 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2966
2967 skb->protocol = eth_type_trans(skb, dev);
2968 lp->stats.rx_packets++;
2969 lp->stats.rx_bytes += pktlen;
2970 netif_rx(skb);
2971 } else {
2972 lp->stats.rx_dropped++;
2973 }
2974
dc97a89e 2975 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
421d9df0
CP		 2976 lp->stats.multicast++;
2977
2978 /* reset ownership bit */
dc97a89e 2979 desc->addr &= ~MACB_BIT(RX_USED);
421d9df0
CP		 2980
2981 /* wrap after last buffer */
2982 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2983 lp->rx_tail = 0;
2984 else
2985 lp->rx_tail++;
dc97a89e
RO		 2986
2987 desc = macb_rx_desc(lp, lp->rx_tail);
421d9df0
CP		 2988 }
2989}
2990
2991/* MAC interrupt handler */
2992static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2993{
2994 struct net_device *dev = dev_id;
2995 struct macb *lp = netdev_priv(dev);
2996 u32 intstatus, ctl;
2997
2998 /* MAC Interrupt Status register indicates what interrupts are pending.
2999 * It is automatically cleared once read.
3000 */
3001 intstatus = macb_readl(lp, ISR);
3002
3003 /* Receive complete */
3004 if (intstatus & MACB_BIT(RCOMP))
3005 at91ether_rx(dev);
3006
3007 /* Transmit complete */
3008 if (intstatus & MACB_BIT(TCOMP)) {
3009 /* The TCOM bit is set even if the transmission failed */
3010 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3011 lp->stats.tx_errors++;
3012
3013 if (lp->skb) {
3014 dev_kfree_skb_irq(lp->skb);
3015 lp->skb = NULL;
3016 dma_unmap_single(NULL, lp->skb_physaddr,
3017 lp->skb_length, DMA_TO_DEVICE);
3018 lp->stats.tx_packets++;
3019 lp->stats.tx_bytes += lp->skb_length;
3020 }
3021 netif_wake_queue(dev);
3022 }
3023
3024 /* Work-around for EMAC Errata section 41.3.1 */
3025 if (intstatus & MACB_BIT(RXUBR)) {
3026 ctl = macb_readl(lp, NCR);
3027 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
ffac0e96 3028 wmb();
421d9df0
CP		 3029 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3030 }
3031
3032 if (intstatus & MACB_BIT(ISR_ROVR))
3033 netdev_err(dev, "ROVR error\n");
3034
3035 return IRQ_HANDLED;
3036}
3037
3038#ifdef CONFIG_NET_POLL_CONTROLLER
3039static void at91ether_poll_controller(struct net_device *dev)
3040{
3041 unsigned long flags;
3042
3043 local_irq_save(flags);
3044 at91ether_interrupt(dev->irq, dev);
3045 local_irq_restore(flags);
3046}
3047#endif
3048
3049static const struct net_device_ops at91ether_netdev_ops = {
3050 .ndo_open = at91ether_open,
3051 .ndo_stop = at91ether_close,
3052 .ndo_start_xmit = at91ether_start_xmit,
3053 .ndo_get_stats = macb_get_stats,
3054 .ndo_set_rx_mode = macb_set_rx_mode,
3055 .ndo_set_mac_address = eth_mac_addr,
3056 .ndo_do_ioctl = macb_ioctl,
3057 .ndo_validate_addr = eth_validate_addr,
421d9df0
CP		 3058#ifdef CONFIG_NET_POLL_CONTROLLER
3059 .ndo_poll_controller = at91ether_poll_controller,
3060#endif
3061};
3062
c69618b3 3063static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
aead88bd 3064 struct clk **hclk, struct clk **tx_clk,
3065 struct clk **rx_clk)
421d9df0 3066{
421d9df0 3067 int err;
421d9df0 3068
c69618b3
NF		 3069 *hclk = NULL;
3070 *tx_clk = NULL;
aead88bd 3071 *rx_clk = NULL;
c69618b3
NF		 3072
3073 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3074 if (IS_ERR(*pclk))
3075 return PTR_ERR(*pclk);
421d9df0 3076
c69618b3 3077 err = clk_prepare_enable(*pclk);
421d9df0
CP		 3078 if (err) {
3079 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3080 return err;
3081 }
3082
c69618b3
NF		 3083 return 0;
3084}
3085
3086static int at91ether_init(struct platform_device *pdev)
3087{
3088 struct net_device *dev = platform_get_drvdata(pdev);
3089 struct macb *bp = netdev_priv(dev);
3090 int err;
3091 u32 reg;
3092
421d9df0
CP		 3093 dev->netdev_ops = &at91ether_netdev_ops;
3094 dev->ethtool_ops = &macb_ethtool_ops;
3095
3096 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
3097 0, dev->name, dev);
3098 if (err)
c69618b3 3099 return err;
421d9df0
CP		 3100
3101 macb_writel(bp, NCR, 0);
3102
3103 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
3104 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
3105 reg |= MACB_BIT(RM9200_RMII);
3106
3107 macb_writel(bp, NCFGR, reg);
3108
3109 return 0;
421d9df0
CP		 3110}
3111
3cef5c5b 3112static const struct macb_config at91sam9260_config = {
6bdaa5e9 3113 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
c69618b3 3114 .clk_init = macb_clk_init,
421d9df0
CP		 3115 .init = macb_init,
3116};
3117
3cef5c5b 3118static const struct macb_config pc302gem_config = {
421d9df0
CP		 3119 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
3120 .dma_burst_length = 16,
c69618b3 3121 .clk_init = macb_clk_init,
421d9df0
CP		 3122 .init = macb_init,
3123};
3124
5c8fe711 3125static const struct macb_config sama5d2_config = {
6bdaa5e9 3126 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
5c8fe711
CP		 3127 .dma_burst_length = 16,
3128 .clk_init = macb_clk_init,
3129 .init = macb_init,
3130};
3131
3cef5c5b 3132static const struct macb_config sama5d3_config = {
6bdaa5e9
NF		 3133 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
3134 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
421d9df0 3135 .dma_burst_length = 16,
c69618b3 3136 .clk_init = macb_clk_init,
421d9df0
CP		 3137 .init = macb_init,
3138};
3139
3cef5c5b 3140static const struct macb_config sama5d4_config = {
6bdaa5e9 3141 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
421d9df0 3142 .dma_burst_length = 4,
c69618b3 3143 .clk_init = macb_clk_init,
421d9df0
CP		 3144 .init = macb_init,
3145};
3146
3cef5c5b 3147static const struct macb_config emac_config = {
c69618b3 3148 .clk_init = at91ether_clk_init,
421d9df0
CP		 3149 .init = at91ether_init,
3150};
3151
e611b5b8
NA		 3152static const struct macb_config np4_config = {
3153 .caps = MACB_CAPS_USRIO_DISABLED,
3154 .clk_init = macb_clk_init,
3155 .init = macb_init,
3156};
36583eb5 3157
7b61f9c1 3158static const struct macb_config zynqmp_config = {
7baaa909 3159 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
7b61f9c1
HK		 3160 .dma_burst_length = 16,
3161 .clk_init = macb_clk_init,
3162 .init = macb_init,
98b5a0f4 3163 .jumbo_max_len = 10240,
7b61f9c1
HK		 3164};
3165
222ca8e0 3166static const struct macb_config zynq_config = {
7baaa909 3167 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
222ca8e0
NS		 3168 .dma_burst_length = 16,
3169 .clk_init = macb_clk_init,
3170 .init = macb_init,
3171};
3172
421d9df0
CP		 3173static const struct of_device_id macb_dt_ids[] = {
3174 { .compatible = "cdns,at32ap7000-macb" },
3175 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
3176 { .compatible = "cdns,macb" },
e611b5b8 3177 { .compatible = "cdns,np4-macb", .data = &np4_config },
421d9df0
CP		 3178 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
3179 { .compatible = "cdns,gem", .data = &pc302gem_config },
5c8fe711 3180 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
421d9df0
CP		 3181 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
3182 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
3183 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
3184 { .compatible = "cdns,emac", .data = &emac_config },
7b61f9c1 3185 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
222ca8e0 3186 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
421d9df0
CP		 3187 { /* sentinel */ }
3188};
3189MODULE_DEVICE_TABLE(of, macb_dt_ids);
3190#endif /* CONFIG_OF */
3191
83a77e9e
BF		 3192static const struct macb_config default_gem_config = {
3193 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
3194 .dma_burst_length = 16,
3195 .clk_init = macb_clk_init,
3196 .init = macb_init,
3197 .jumbo_max_len = 10240,
3198};
3199
421d9df0
CP		 3200static int macb_probe(struct platform_device *pdev)
3201{
83a77e9e 3202 const struct macb_config *macb_config = &default_gem_config;
c69618b3 3203 int (*clk_init)(struct platform_device *, struct clk **,
aead88bd 3204 struct clk **, struct clk **, struct clk **)
83a77e9e
BF		 3205 = macb_config->clk_init;
3206 int (*init)(struct platform_device *) = macb_config->init;
421d9df0 3207 struct device_node *np = pdev->dev.of_node;
270c499f 3208 struct device_node *phy_node;
aead88bd 3209 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
421d9df0
CP		 3210 unsigned int queue_mask, num_queues;
3211 struct macb_platform_data *pdata;
f2ce8a9e 3212 bool native_io;
421d9df0
CP		 3213 struct phy_device *phydev;
3214 struct net_device *dev;
3215 struct resource *regs;
3216 void __iomem *mem;
3217 const char *mac;
3218 struct macb *bp;
3219 int err;
3220
f2ce8a9e
AS		 3221 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3222 mem = devm_ioremap_resource(&pdev->dev, regs);
3223 if (IS_ERR(mem))
3224 return PTR_ERR(mem);
3225
c69618b3
NF		 3226 if (np) {
3227 const struct of_device_id *match;
3228
3229 match = of_match_node(macb_dt_ids, np);
3230 if (match && match->data) {
3231 macb_config = match->data;
3232 clk_init = macb_config->clk_init;
3233 init = macb_config->init;
3234 }
3235 }
3236
aead88bd 3237 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
c69618b3
NF		 3238 if (err)
3239 return err;
3240
f2ce8a9e 3241 native_io = hw_is_native_io(mem);
421d9df0 3242
f2ce8a9e 3243 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
421d9df0 3244 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
c69618b3
NF		 3245 if (!dev) {
3246 err = -ENOMEM;
3247 goto err_disable_clocks;
3248 }
421d9df0
CP		 3249
3250 dev->base_addr = regs->start;
3251
3252 SET_NETDEV_DEV(dev, &pdev->dev);
3253
3254 bp = netdev_priv(dev);
3255 bp->pdev = pdev;
3256 bp->dev = dev;
3257 bp->regs = mem;
f2ce8a9e
AS		 3258 bp->native_io = native_io;
3259 if (native_io) {
7a6e0706
DM		 3260 bp->macb_reg_readl = hw_readl_native;
3261 bp->macb_reg_writel = hw_writel_native;
f2ce8a9e 3262 } else {
7a6e0706
DM		 3263 bp->macb_reg_readl = hw_readl;
3264 bp->macb_reg_writel = hw_writel;
f2ce8a9e 3265 }
421d9df0 3266 bp->num_queues = num_queues;
bfa0914a 3267 bp->queue_mask = queue_mask;
c69618b3
NF		 3268 if (macb_config)
3269 bp->dma_burst_length = macb_config->dma_burst_length;
3270 bp->pclk = pclk;
3271 bp->hclk = hclk;
3272 bp->tx_clk = tx_clk;
aead88bd 3273 bp->rx_clk = rx_clk;
f36dbe6a 3274 if (macb_config)
98b5a0f4 3275 bp->jumbo_max_len = macb_config->jumbo_max_len;
98b5a0f4 3276
3e2a5e15 3277 bp->wol = 0;
7c4a1d0c 3278 if (of_get_property(np, "magic-packet", NULL))
3e2a5e15
SP		 3279 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
3280 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
3281
fff8019a 3282#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
dc97a89e 3283 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
fff8019a 3284 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
dc97a89e
RO		 3285 bp->hw_dma_cap = HW_DMA_CAP_64B;
3286 } else
3287 bp->hw_dma_cap = HW_DMA_CAP_32B;
fff8019a
HK		 3288#endif
3289
421d9df0
CP		 3290 spin_lock_init(&bp->lock);
3291
ad78347f 3292 /* setup capabilities */
f6970505
NF		 3293 macb_configure_caps(bp, macb_config);
3294
421d9df0
CP		 3295 platform_set_drvdata(pdev, dev);
3296
3297 dev->irq = platform_get_irq(pdev, 0);
c69618b3
NF		 3298 if (dev->irq < 0) {
3299 err = dev->irq;
b22ae0b4 3300 goto err_out_free_netdev;
c69618b3 3301 }
421d9df0 3302
44770e11
JW		 3303 /* MTU range: 68 - 1500 or 10240 */
3304 dev->min_mtu = GEM_MTU_MIN_SIZE;
3305 if (bp->caps & MACB_CAPS_JUMBO)
3306 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
3307 else
3308 dev->max_mtu = ETH_DATA_LEN;
3309
421d9df0 3310 mac = of_get_mac_address(np);
50907043 3311 if (mac)
eefb52d1 3312 ether_addr_copy(bp->dev->dev_addr, mac);
50907043 3313 else
fb97a846
JCPV		 3314 macb_get_hwaddr(bp);
3315
5833e052 3316 /* Power up the PHY if there is a GPIO reset */
270c499f
GC		 3317 phy_node = of_get_next_available_child(np, NULL);
3318 if (phy_node) {
3319 int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
64ec42fe 3320
0e3e7999 3321 if (gpio_is_valid(gpio)) {
270c499f 3322 bp->reset_gpio = gpio_to_desc(gpio);
0e3e7999
CK		 3323 gpiod_direction_output(bp->reset_gpio, 1);
3324 }
270c499f
GC		 3325 }
3326 of_node_put(phy_node);
5833e052 3327
421d9df0 3328 err = of_get_phy_mode(np);
fb97a846 3329 if (err < 0) {
c607a0d9 3330 pdata = dev_get_platdata(&pdev->dev);
fb97a846
JCPV		 3331 if (pdata && pdata->is_rmii)
3332 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
3333 else
3334 bp->phy_interface = PHY_INTERFACE_MODE_MII;
3335 } else {
3336 bp->phy_interface = err;
3337 }
6c36a707 3338
421d9df0
CP		 3339 /* IP specific init */
3340 err = init(pdev);
3341 if (err)
3342 goto err_out_free_netdev;
89e5785f 3343
cf669660
FF		 3344 err = macb_mii_init(bp);
3345 if (err)
3346 goto err_out_free_netdev;
3347
0a91281e 3348 phydev = dev->phydev;
cf669660
FF		 3349
3350 netif_carrier_off(dev);
3351
89e5785f
HS		 3352 err = register_netdev(dev);
3353 if (err) {
3354 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
cf669660 3355 goto err_out_unregister_mdio;
89e5785f
HS		 3356 }
3357
cf669660 3358 phy_attached_info(phydev);
03fc4721 3359
5879823f
BS		 3360 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
3361 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
3362 dev->base_addr, dev->irq, dev->dev_addr);
89e5785f
HS		 3363
3364 return 0;
3365
cf669660 3366err_out_unregister_mdio:
0a91281e 3367 phy_disconnect(dev->phydev);
cf669660
FF		 3368 mdiobus_unregister(bp->mii_bus);
3369 mdiobus_free(bp->mii_bus);
3370
3371 /* Shutdown the PHY if there is a GPIO reset */
3372 if (bp->reset_gpio)
3373 gpiod_set_value(bp->reset_gpio, 0);
421d9df0 3374
cf250de0 3375err_out_free_netdev:
02c958dd 3376 free_netdev(dev);
421d9df0 3377
c69618b3
NF		 3378err_disable_clocks:
3379 clk_disable_unprepare(tx_clk);
3380 clk_disable_unprepare(hclk);
3381 clk_disable_unprepare(pclk);
aead88bd 3382 clk_disable_unprepare(rx_clk);
c69618b3 3383
89e5785f
HS		 3384 return err;
3385}
3386
9e86d766 3387static int macb_remove(struct platform_device *pdev)
89e5785f
HS		 3388{
3389 struct net_device *dev;
3390 struct macb *bp;
3391
3392 dev = platform_get_drvdata(pdev);
3393
3394 if (dev) {
3395 bp = netdev_priv(dev);
0a91281e
PR		 3396 if (dev->phydev)
3397 phy_disconnect(dev->phydev);
298cf9be 3398 mdiobus_unregister(bp->mii_bus);
fa6114d4 3399 dev->phydev = NULL;
298cf9be 3400 mdiobus_free(bp->mii_bus);
5833e052
GC		 3401
3402 /* Shutdown the PHY if there is a GPIO reset */
0e3e7999
CK		 3403 if (bp->reset_gpio)
3404 gpiod_set_value(bp->reset_gpio, 0);
5833e052 3405
89e5785f 3406 unregister_netdev(dev);
93b31f48 3407 clk_disable_unprepare(bp->tx_clk);
ace58010 3408 clk_disable_unprepare(bp->hclk);
ace58010 3409 clk_disable_unprepare(bp->pclk);
aead88bd 3410 clk_disable_unprepare(bp->rx_clk);
e965be7d 3411 free_netdev(dev);
89e5785f
HS		 3412 }
3413
3414 return 0;
3415}
3416
d23823dd 3417static int __maybe_unused macb_suspend(struct device *dev)
c1f598fd 3418{
0dfc3e18 3419 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS		 3420 struct net_device *netdev = platform_get_drvdata(pdev);
3421 struct macb *bp = netdev_priv(netdev);
3422
03fc4721 3423 netif_carrier_off(netdev);
c1f598fd
HS		 3424 netif_device_detach(netdev);
3425
3e2a5e15
SP		 3426 if (bp->wol & MACB_WOL_ENABLED) {
3427 macb_writel(bp, IER, MACB_BIT(WOL));
3428 macb_writel(bp, WOL, MACB_BIT(MAG));
3429 enable_irq_wake(bp->queues[0].irq);
3430 } else {
3431 clk_disable_unprepare(bp->tx_clk);
3432 clk_disable_unprepare(bp->hclk);
3433 clk_disable_unprepare(bp->pclk);
aead88bd 3434 clk_disable_unprepare(bp->rx_clk);
3e2a5e15 3435 }
c1f598fd
HS		 3436
3437 return 0;
3438}
3439
d23823dd 3440static int __maybe_unused macb_resume(struct device *dev)
c1f598fd 3441{
0dfc3e18 3442 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS		 3443 struct net_device *netdev = platform_get_drvdata(pdev);
3444 struct macb *bp = netdev_priv(netdev);
3445
3e2a5e15
SP		 3446 if (bp->wol & MACB_WOL_ENABLED) {
3447 macb_writel(bp, IDR, MACB_BIT(WOL));
3448 macb_writel(bp, WOL, 0);
3449 disable_irq_wake(bp->queues[0].irq);
3450 } else {
3451 clk_prepare_enable(bp->pclk);
3452 clk_prepare_enable(bp->hclk);
3453 clk_prepare_enable(bp->tx_clk);
aead88bd 3454 clk_prepare_enable(bp->rx_clk);
3e2a5e15 3455 }
c1f598fd
HS		 3456
3457 netif_device_attach(netdev);
3458
3459 return 0;
3460}
c1f598fd 3461
0dfc3e18
SB		 3462static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
3463
89e5785f 3464static struct platform_driver macb_driver = {
9e86d766
NR		 3465 .probe = macb_probe,
3466 .remove = macb_remove,
89e5785f
HS		 3467 .driver = {
3468 .name = "macb",
fb97a846 3469 .of_match_table = of_match_ptr(macb_dt_ids),
0dfc3e18 3470 .pm = &macb_pm_ops,
89e5785f
HS		 3471 },
3472};
3473
9e86d766 3474module_platform_driver(macb_driver);
89e5785f
HS		 3475
3476MODULE_LICENSE("GPL");
f75ba50b 3477MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
e05503ef 3478MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
72abb461 3479MODULE_ALIAS("platform:macb");
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