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macb: convert printk to netdev_ and friends
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / cadence / macb.c
CommitLineData
89e5785f
HS
1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
c220f8cd 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
89e5785f
HS
12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/slab.h>
18#include <linux/init.h>
a6b7a407 19#include <linux/interrupt.h>
89e5785f
HS
20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
89e5785f 22#include <linux/dma-mapping.h>
84e0cdb0 23#include <linux/platform_data/macb.h>
89e5785f 24#include <linux/platform_device.h>
6c36a707 25#include <linux/phy.h>
89e5785f 26
89e5785f
HS
27#include "macb.h"
28
89e5785f
HS
29#define RX_BUFFER_SIZE 128
30#define RX_RING_SIZE 512
31#define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
32
33/* Make the IP header word-aligned (the ethernet header is 14 bytes) */
34#define RX_OFFSET 2
35
36#define TX_RING_SIZE 128
37#define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
38#define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
39
40#define TX_RING_GAP(bp) \
41 (TX_RING_SIZE - (bp)->tx_pending)
42#define TX_BUFFS_AVAIL(bp) \
43 (((bp)->tx_tail <= (bp)->tx_head) ? \
44 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
45 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
46#define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
47
48#define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
49
50/* minimum number of free TX descriptors before waking up TX process */
51#define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
52
53#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
54 | MACB_BIT(ISR_ROVR))
55
56static void __macb_set_hwaddr(struct macb *bp)
57{
58 u32 bottom;
59 u16 top;
60
61 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
62 macb_writel(bp, SA1B, bottom);
63 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
64 macb_writel(bp, SA1T, top);
65}
66
67static void __init macb_get_hwaddr(struct macb *bp)
68{
69 u32 bottom;
70 u16 top;
71 u8 addr[6];
72
73 bottom = macb_readl(bp, SA1B);
74 top = macb_readl(bp, SA1T);
75
76 addr[0] = bottom & 0xff;
77 addr[1] = (bottom >> 8) & 0xff;
78 addr[2] = (bottom >> 16) & 0xff;
79 addr[3] = (bottom >> 24) & 0xff;
80 addr[4] = top & 0xff;
81 addr[5] = (top >> 8) & 0xff;
82
d1d5741d 83 if (is_valid_ether_addr(addr)) {
89e5785f 84 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
d1d5741d 85 } else {
c220f8cd 86 netdev_info(bp->dev, "invalid hw address, using random\n");
d1d5741d
SS
87 random_ether_addr(bp->dev->dev_addr);
88 }
89e5785f
HS
89}
90
6c36a707 91static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 92{
6c36a707 93 struct macb *bp = bus->priv;
89e5785f
HS
94 int value;
95
89e5785f
HS
96 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
97 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R
98 | MACB_BF(PHYA, mii_id)
99 | MACB_BF(REGA, regnum)
89e5785f
HS
100 | MACB_BF(CODE, MACB_MAN_CODE)));
101
6c36a707
R
102 /* wait for end of transfer */
103 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
104 cpu_relax();
89e5785f
HS
105
106 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS
107
108 return value;
109}
110
6c36a707
R
111static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
112 u16 value)
89e5785f 113{
6c36a707 114 struct macb *bp = bus->priv;
89e5785f
HS
115
116 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
117 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R
118 | MACB_BF(PHYA, mii_id)
119 | MACB_BF(REGA, regnum)
89e5785f 120 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 121 | MACB_BF(DATA, value)));
89e5785f 122
6c36a707
R
123 /* wait for end of transfer */
124 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
125 cpu_relax();
126
127 return 0;
128}
89e5785f 129
6c36a707
R
130static int macb_mdio_reset(struct mii_bus *bus)
131{
132 return 0;
89e5785f
HS
133}
134
6c36a707 135static void macb_handle_link_change(struct net_device *dev)
89e5785f 136{
6c36a707
R
137 struct macb *bp = netdev_priv(dev);
138 struct phy_device *phydev = bp->phy_dev;
139 unsigned long flags;
89e5785f 140
6c36a707 141 int status_change = 0;
89e5785f 142
6c36a707
R
143 spin_lock_irqsave(&bp->lock, flags);
144
145 if (phydev->link) {
146 if ((bp->speed != phydev->speed) ||
147 (bp->duplex != phydev->duplex)) {
148 u32 reg;
149
150 reg = macb_readl(bp, NCFGR);
151 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
152
153 if (phydev->duplex)
154 reg |= MACB_BIT(FD);
179956f4 155 if (phydev->speed == SPEED_100)
6c36a707
R
156 reg |= MACB_BIT(SPD);
157
158 macb_writel(bp, NCFGR, reg);
159
160 bp->speed = phydev->speed;
161 bp->duplex = phydev->duplex;
162 status_change = 1;
163 }
89e5785f
HS
164 }
165
6c36a707 166 if (phydev->link != bp->link) {
c8f15686 167 if (!phydev->link) {
6c36a707
R
168 bp->speed = 0;
169 bp->duplex = -1;
170 }
171 bp->link = phydev->link;
89e5785f 172
6c36a707
R
173 status_change = 1;
174 }
89e5785f 175
6c36a707
R
176 spin_unlock_irqrestore(&bp->lock, flags);
177
178 if (status_change) {
179 if (phydev->link)
c220f8cd
JI
180 netdev_info(dev, "link up (%d/%s)\n",
181 phydev->speed,
182 phydev->duplex == DUPLEX_FULL ?
183 "Full" : "Half");
6c36a707 184 else
c220f8cd 185 netdev_info(dev, "link down\n");
6c36a707 186 }
89e5785f
HS
187}
188
6c36a707
R
189/* based on au1000_eth. c*/
190static int macb_mii_probe(struct net_device *dev)
89e5785f 191{
6c36a707 192 struct macb *bp = netdev_priv(dev);
7455a76f 193 struct phy_device *phydev;
84e0cdb0 194 struct macb_platform_data *pdata;
7455a76f 195 int ret;
6c36a707 196
7455a76f 197 phydev = phy_find_first(bp->mii_bus);
6c36a707 198 if (!phydev) {
c220f8cd 199 netdev_err(dev, "no PHY found\n");
6c36a707
R
200 return -1;
201 }
202
203 pdata = bp->pdev->dev.platform_data;
204 /* TODO : add pin_irq */
205
206 /* attach the mac to the phy */
7455a76f
JP
207 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
208 pdata && pdata->is_rmii ?
209 PHY_INTERFACE_MODE_RMII :
210 PHY_INTERFACE_MODE_MII);
211 if (ret) {
c220f8cd 212 netdev_err(dev, "Could not attach to PHY\n");
7455a76f 213 return ret;
6c36a707
R
214 }
215
216 /* mask with MAC supported features */
217 phydev->supported &= PHY_BASIC_FEATURES;
218
219 phydev->advertising = phydev->supported;
220
221 bp->link = 0;
222 bp->speed = 0;
223 bp->duplex = -1;
224 bp->phy_dev = phydev;
225
226 return 0;
89e5785f
HS
227}
228
6c36a707 229static int macb_mii_init(struct macb *bp)
89e5785f 230{
84e0cdb0 231 struct macb_platform_data *pdata;
6c36a707 232 int err = -ENXIO, i;
89e5785f 233
3dbda77e 234 /* Enable management port */
6c36a707 235 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 236
298cf9be
LB
237 bp->mii_bus = mdiobus_alloc();
238 if (bp->mii_bus == NULL) {
239 err = -ENOMEM;
240 goto err_out;
241 }
242
243 bp->mii_bus->name = "MACB_mii_bus";
244 bp->mii_bus->read = &macb_mdio_read;
245 bp->mii_bus->write = &macb_mdio_write;
246 bp->mii_bus->reset = &macb_mdio_reset;
247 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
248 bp->mii_bus->priv = bp;
249 bp->mii_bus->parent = &bp->dev->dev;
6c36a707 250 pdata = bp->pdev->dev.platform_data;
89e5785f 251
6c36a707 252 if (pdata)
298cf9be 253 bp->mii_bus->phy_mask = pdata->phy_mask;
89e5785f 254
298cf9be
LB
255 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
256 if (!bp->mii_bus->irq) {
6c36a707 257 err = -ENOMEM;
298cf9be 258 goto err_out_free_mdiobus;
89e5785f
HS
259 }
260
6c36a707 261 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 262 bp->mii_bus->irq[i] = PHY_POLL;
89e5785f 263
91523947 264 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
89e5785f 265
298cf9be 266 if (mdiobus_register(bp->mii_bus))
6c36a707 267 goto err_out_free_mdio_irq;
89e5785f 268
6c36a707
R
269 if (macb_mii_probe(bp->dev) != 0) {
270 goto err_out_unregister_bus;
271 }
89e5785f 272
6c36a707 273 return 0;
89e5785f 274
6c36a707 275err_out_unregister_bus:
298cf9be 276 mdiobus_unregister(bp->mii_bus);
6c36a707 277err_out_free_mdio_irq:
298cf9be
LB
278 kfree(bp->mii_bus->irq);
279err_out_free_mdiobus:
280 mdiobus_free(bp->mii_bus);
6c36a707
R
281err_out:
282 return err;
89e5785f
HS
283}
284
285static void macb_update_stats(struct macb *bp)
286{
287 u32 __iomem *reg = bp->regs + MACB_PFR;
288 u32 *p = &bp->hw_stats.rx_pause_frames;
289 u32 *end = &bp->hw_stats.tx_pause_frames + 1;
290
291 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
292
293 for(; p < end; p++, reg++)
0f0d84e5 294 *p += __raw_readl(reg);
89e5785f
HS
295}
296
89e5785f
HS
297static void macb_tx(struct macb *bp)
298{
299 unsigned int tail;
300 unsigned int head;
301 u32 status;
302
303 status = macb_readl(bp, TSR);
304 macb_writel(bp, TSR, status);
305
c220f8cd 306 netdev_dbg(bp->dev, "macb_tx status = %02lx\n", (unsigned long)status);
89e5785f 307
ee33c585 308 if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
bdcba151 309 int i;
c220f8cd
JI
310 netdev_err(bp->dev, "TX %s, resetting buffers\n",
311 status & MACB_BIT(UND) ?
312 "underrun" : "retry limit exceeded");
bdcba151 313
39eddb4c
RR
314 /* Transfer ongoing, disable transmitter, to avoid confusion */
315 if (status & MACB_BIT(TGO))
316 macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
317
bdcba151
GC
318 head = bp->tx_head;
319
320 /*Mark all the buffer as used to avoid sending a lost buffer*/
321 for (i = 0; i < TX_RING_SIZE; i++)
322 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
323
d3e61457
TA
324 /* Add wrap bit */
325 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
326
bdcba151
GC
327 /* free transmit buffer in upper layer*/
328 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
329 struct ring_info *rp = &bp->tx_skb[tail];
330 struct sk_buff *skb = rp->skb;
331
332 BUG_ON(skb == NULL);
333
334 rmb();
335
336 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
337 DMA_TO_DEVICE);
338 rp->skb = NULL;
339 dev_kfree_skb_irq(skb);
340 }
341
89e5785f 342 bp->tx_head = bp->tx_tail = 0;
39eddb4c
RR
343
344 /* Enable the transmitter again */
345 if (status & MACB_BIT(TGO))
346 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
89e5785f
HS
347 }
348
349 if (!(status & MACB_BIT(COMP)))
350 /*
351 * This may happen when a buffer becomes complete
352 * between reading the ISR and scanning the
353 * descriptors. Nothing to worry about.
354 */
355 return;
356
357 head = bp->tx_head;
358 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
359 struct ring_info *rp = &bp->tx_skb[tail];
360 struct sk_buff *skb = rp->skb;
361 u32 bufstat;
362
363 BUG_ON(skb == NULL);
364
365 rmb();
366 bufstat = bp->tx_ring[tail].ctrl;
367
368 if (!(bufstat & MACB_BIT(TX_USED)))
369 break;
370
c220f8cd
JI
371 netdev_dbg(bp->dev, "skb %u (data %p) TX complete\n",
372 tail, skb->data);
89e5785f
HS
373 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
374 DMA_TO_DEVICE);
375 bp->stats.tx_packets++;
376 bp->stats.tx_bytes += skb->len;
377 rp->skb = NULL;
378 dev_kfree_skb_irq(skb);
379 }
380
381 bp->tx_tail = tail;
382 if (netif_queue_stopped(bp->dev) &&
383 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
384 netif_wake_queue(bp->dev);
385}
386
387static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
388 unsigned int last_frag)
389{
390 unsigned int len;
391 unsigned int frag;
392 unsigned int offset = 0;
393 struct sk_buff *skb;
394
395 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
396
c220f8cd
JI
397 netdev_dbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
398 first_frag, last_frag, len);
89e5785f
HS
399
400 skb = dev_alloc_skb(len + RX_OFFSET);
401 if (!skb) {
402 bp->stats.rx_dropped++;
403 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
404 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
405 if (frag == last_frag)
406 break;
407 }
408 wmb();
409 return 1;
410 }
411
412 skb_reserve(skb, RX_OFFSET);
bc8acf2c 413 skb_checksum_none_assert(skb);
89e5785f
HS
414 skb_put(skb, len);
415
416 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
417 unsigned int frag_len = RX_BUFFER_SIZE;
418
419 if (offset + frag_len > len) {
420 BUG_ON(frag != last_frag);
421 frag_len = len - offset;
422 }
27d7ff46
ACM
423 skb_copy_to_linear_data_offset(skb, offset,
424 (bp->rx_buffers +
425 (RX_BUFFER_SIZE * frag)),
426 frag_len);
89e5785f
HS
427 offset += RX_BUFFER_SIZE;
428 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
429 wmb();
430
431 if (frag == last_frag)
432 break;
433 }
434
435 skb->protocol = eth_type_trans(skb, bp->dev);
436
437 bp->stats.rx_packets++;
438 bp->stats.rx_bytes += len;
c220f8cd
JI
439 netdev_dbg(bp->dev, "received skb of length %u, csum: %08x\n",
440 skb->len, skb->csum);
89e5785f
HS
441 netif_receive_skb(skb);
442
443 return 0;
444}
445
446/* Mark DMA descriptors from begin up to and not including end as unused */
447static void discard_partial_frame(struct macb *bp, unsigned int begin,
448 unsigned int end)
449{
450 unsigned int frag;
451
452 for (frag = begin; frag != end; frag = NEXT_RX(frag))
453 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
454 wmb();
455
456 /*
457 * When this happens, the hardware stats registers for
458 * whatever caused this is updated, so we don't have to record
459 * anything.
460 */
461}
462
463static int macb_rx(struct macb *bp, int budget)
464{
465 int received = 0;
466 unsigned int tail = bp->rx_tail;
467 int first_frag = -1;
468
469 for (; budget > 0; tail = NEXT_RX(tail)) {
470 u32 addr, ctrl;
471
472 rmb();
473 addr = bp->rx_ring[tail].addr;
474 ctrl = bp->rx_ring[tail].ctrl;
475
476 if (!(addr & MACB_BIT(RX_USED)))
477 break;
478
479 if (ctrl & MACB_BIT(RX_SOF)) {
480 if (first_frag != -1)
481 discard_partial_frame(bp, first_frag, tail);
482 first_frag = tail;
483 }
484
485 if (ctrl & MACB_BIT(RX_EOF)) {
486 int dropped;
487 BUG_ON(first_frag == -1);
488
489 dropped = macb_rx_frame(bp, first_frag, tail);
490 first_frag = -1;
491 if (!dropped) {
492 received++;
493 budget--;
494 }
495 }
496 }
497
498 if (first_frag != -1)
499 bp->rx_tail = first_frag;
500 else
501 bp->rx_tail = tail;
502
503 return received;
504}
505
bea3348e 506static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 507{
bea3348e 508 struct macb *bp = container_of(napi, struct macb, napi);
bea3348e 509 int work_done;
89e5785f
HS
510 u32 status;
511
512 status = macb_readl(bp, RSR);
513 macb_writel(bp, RSR, status);
514
bea3348e 515 work_done = 0;
89e5785f 516
c220f8cd
JI
517 netdev_dbg(bp->dev, "poll: status = %08lx, budget = %d\n",
518 (unsigned long)status, budget);
89e5785f 519
bea3348e 520 work_done = macb_rx(bp, budget);
b336369c 521 if (work_done < budget) {
288379f0 522 napi_complete(napi);
89e5785f 523
b336369c
JH
524 /*
525 * We've done what we can to clean the buffers. Make sure we
526 * get notified when new packets arrive.
527 */
528 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
529 }
89e5785f
HS
530
531 /* TODO: Handle errors */
532
bea3348e 533 return work_done;
89e5785f
HS
534}
535
536static irqreturn_t macb_interrupt(int irq, void *dev_id)
537{
538 struct net_device *dev = dev_id;
539 struct macb *bp = netdev_priv(dev);
540 u32 status;
541
542 status = macb_readl(bp, ISR);
543
544 if (unlikely(!status))
545 return IRQ_NONE;
546
547 spin_lock(&bp->lock);
548
549 while (status) {
89e5785f
HS
550 /* close possible race with dev_close */
551 if (unlikely(!netif_running(dev))) {
552 macb_writel(bp, IDR, ~0UL);
553 break;
554 }
555
556 if (status & MACB_RX_INT_FLAGS) {
b336369c
JH
557 /*
558 * There's no point taking any more interrupts
559 * until we have processed the buffers. The
560 * scheduling call may fail if the poll routine
561 * is already scheduled, so disable interrupts
562 * now.
563 */
564 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
565
288379f0 566 if (napi_schedule_prep(&bp->napi)) {
c220f8cd 567 netdev_dbg(bp->dev, "scheduling RX softirq\n");
288379f0 568 __napi_schedule(&bp->napi);
89e5785f
HS
569 }
570 }
571
ee33c585
EW
572 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
573 MACB_BIT(ISR_RLE)))
89e5785f
HS
574 macb_tx(bp);
575
576 /*
577 * Link change detection isn't possible with RMII, so we'll
578 * add that if/when we get our hands on a full-blown MII PHY.
579 */
580
b19f7f71
AS
581 if (status & MACB_BIT(ISR_ROVR)) {
582 /* We missed at least one packet */
583 bp->hw_stats.rx_overruns++;
584 }
585
89e5785f
HS
586 if (status & MACB_BIT(HRESP)) {
587 /*
c220f8cd
JI
588 * TODO: Reset the hardware, and maybe move the
589 * netdev_err to a lower-priority context as well
590 * (work queue?)
89e5785f 591 */
c220f8cd 592 netdev_err(dev, "DMA bus error: HRESP not OK\n");
89e5785f
HS
593 }
594
595 status = macb_readl(bp, ISR);
596 }
597
598 spin_unlock(&bp->lock);
599
600 return IRQ_HANDLED;
601}
602
6e8cf5c0
TP
603#ifdef CONFIG_NET_POLL_CONTROLLER
604/*
605 * Polling receive - used by netconsole and other diagnostic tools
606 * to allow network i/o with interrupts disabled.
607 */
608static void macb_poll_controller(struct net_device *dev)
609{
610 unsigned long flags;
611
612 local_irq_save(flags);
613 macb_interrupt(dev->irq, dev);
614 local_irq_restore(flags);
615}
616#endif
617
89e5785f
HS
618static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
619{
620 struct macb *bp = netdev_priv(dev);
621 dma_addr_t mapping;
622 unsigned int len, entry;
623 u32 ctrl;
4871953c 624 unsigned long flags;
89e5785f
HS
625
626#ifdef DEBUG
c220f8cd
JI
627 netdev_dbg(bp->dev,
628 "start_xmit: len %u head %p data %p tail %p end %p\n",
629 skb->len, skb->head, skb->data,
630 skb_tail_pointer(skb), skb_end_pointer(skb));
631 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
632 skb->data, 16, true);
89e5785f
HS
633#endif
634
635 len = skb->len;
4871953c 636 spin_lock_irqsave(&bp->lock, flags);
89e5785f
HS
637
638 /* This is a hard error, log it. */
639 if (TX_BUFFS_AVAIL(bp) < 1) {
640 netif_stop_queue(dev);
4871953c 641 spin_unlock_irqrestore(&bp->lock, flags);
c220f8cd
JI
642 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
643 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
644 bp->tx_head, bp->tx_tail);
5b548140 645 return NETDEV_TX_BUSY;
89e5785f
HS
646 }
647
648 entry = bp->tx_head;
c220f8cd 649 netdev_dbg(bp->dev, "Allocated ring entry %u\n", entry);
89e5785f
HS
650 mapping = dma_map_single(&bp->pdev->dev, skb->data,
651 len, DMA_TO_DEVICE);
652 bp->tx_skb[entry].skb = skb;
653 bp->tx_skb[entry].mapping = mapping;
c220f8cd
JI
654 netdev_dbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
655 skb->data, (unsigned long)mapping);
89e5785f
HS
656
657 ctrl = MACB_BF(TX_FRMLEN, len);
658 ctrl |= MACB_BIT(TX_LAST);
659 if (entry == (TX_RING_SIZE - 1))
660 ctrl |= MACB_BIT(TX_WRAP);
661
662 bp->tx_ring[entry].addr = mapping;
663 bp->tx_ring[entry].ctrl = ctrl;
664 wmb();
665
666 entry = NEXT_TX(entry);
667 bp->tx_head = entry;
668
e072092f
RC
669 skb_tx_timestamp(skb);
670
89e5785f
HS
671 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
672
673 if (TX_BUFFS_AVAIL(bp) < 1)
674 netif_stop_queue(dev);
675
4871953c 676 spin_unlock_irqrestore(&bp->lock, flags);
89e5785f 677
6ed10654 678 return NETDEV_TX_OK;
89e5785f
HS
679}
680
681static void macb_free_consistent(struct macb *bp)
682{
683 if (bp->tx_skb) {
684 kfree(bp->tx_skb);
685 bp->tx_skb = NULL;
686 }
687 if (bp->rx_ring) {
688 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
689 bp->rx_ring, bp->rx_ring_dma);
690 bp->rx_ring = NULL;
691 }
692 if (bp->tx_ring) {
693 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
694 bp->tx_ring, bp->tx_ring_dma);
695 bp->tx_ring = NULL;
696 }
697 if (bp->rx_buffers) {
698 dma_free_coherent(&bp->pdev->dev,
699 RX_RING_SIZE * RX_BUFFER_SIZE,
700 bp->rx_buffers, bp->rx_buffers_dma);
701 bp->rx_buffers = NULL;
702 }
703}
704
705static int macb_alloc_consistent(struct macb *bp)
706{
707 int size;
708
709 size = TX_RING_SIZE * sizeof(struct ring_info);
710 bp->tx_skb = kmalloc(size, GFP_KERNEL);
711 if (!bp->tx_skb)
712 goto out_err;
713
714 size = RX_RING_BYTES;
715 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
716 &bp->rx_ring_dma, GFP_KERNEL);
717 if (!bp->rx_ring)
718 goto out_err;
c220f8cd
JI
719 netdev_dbg(bp->dev,
720 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
721 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
89e5785f
HS
722
723 size = TX_RING_BYTES;
724 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
725 &bp->tx_ring_dma, GFP_KERNEL);
726 if (!bp->tx_ring)
727 goto out_err;
c220f8cd
JI
728 netdev_dbg(bp->dev,
729 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
730 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
89e5785f
HS
731
732 size = RX_RING_SIZE * RX_BUFFER_SIZE;
733 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
734 &bp->rx_buffers_dma, GFP_KERNEL);
735 if (!bp->rx_buffers)
736 goto out_err;
c220f8cd
JI
737 netdev_dbg(bp->dev,
738 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
739 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
89e5785f
HS
740
741 return 0;
742
743out_err:
744 macb_free_consistent(bp);
745 return -ENOMEM;
746}
747
748static void macb_init_rings(struct macb *bp)
749{
750 int i;
751 dma_addr_t addr;
752
753 addr = bp->rx_buffers_dma;
754 for (i = 0; i < RX_RING_SIZE; i++) {
755 bp->rx_ring[i].addr = addr;
756 bp->rx_ring[i].ctrl = 0;
757 addr += RX_BUFFER_SIZE;
758 }
759 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
760
761 for (i = 0; i < TX_RING_SIZE; i++) {
762 bp->tx_ring[i].addr = 0;
763 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
764 }
765 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
766
767 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
768}
769
770static void macb_reset_hw(struct macb *bp)
771{
772 /* Make sure we have the write buffer for ourselves */
773 wmb();
774
775 /*
776 * Disable RX and TX (XXX: Should we halt the transmission
777 * more gracefully?)
778 */
779 macb_writel(bp, NCR, 0);
780
781 /* Clear the stats registers (XXX: Update stats first?) */
782 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
783
784 /* Clear all status flags */
785 macb_writel(bp, TSR, ~0UL);
786 macb_writel(bp, RSR, ~0UL);
787
788 /* Disable all interrupts */
789 macb_writel(bp, IDR, ~0UL);
790 macb_readl(bp, ISR);
791}
792
793static void macb_init_hw(struct macb *bp)
794{
795 u32 config;
796
797 macb_reset_hw(bp);
798 __macb_set_hwaddr(bp);
799
800 config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
801 config |= MACB_BIT(PAE); /* PAuse Enable */
802 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
8dd4bd00 803 config |= MACB_BIT(BIG); /* Receive oversized frames */
89e5785f
HS
804 if (bp->dev->flags & IFF_PROMISC)
805 config |= MACB_BIT(CAF); /* Copy All Frames */
806 if (!(bp->dev->flags & IFF_BROADCAST))
807 config |= MACB_BIT(NBC); /* No BroadCast */
808 macb_writel(bp, NCFGR, config);
809
810 /* Initialize TX and RX buffers */
811 macb_writel(bp, RBQP, bp->rx_ring_dma);
812 macb_writel(bp, TBQP, bp->tx_ring_dma);
813
814 /* Enable TX and RX */
6c36a707 815 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS
816
817 /* Enable interrupts */
818 macb_writel(bp, IER, (MACB_BIT(RCOMP)
819 | MACB_BIT(RXUBR)
820 | MACB_BIT(ISR_TUND)
821 | MACB_BIT(ISR_RLE)
822 | MACB_BIT(TXERR)
823 | MACB_BIT(TCOMP)
824 | MACB_BIT(ISR_ROVR)
825 | MACB_BIT(HRESP)));
89e5785f 826
89e5785f
HS
827}
828
446ebd01
PV
829/*
830 * The hash address register is 64 bits long and takes up two
831 * locations in the memory map. The least significant bits are stored
832 * in EMAC_HSL and the most significant bits in EMAC_HSH.
833 *
834 * The unicast hash enable and the multicast hash enable bits in the
835 * network configuration register enable the reception of hash matched
836 * frames. The destination address is reduced to a 6 bit index into
837 * the 64 bit hash register using the following hash function. The
838 * hash function is an exclusive or of every sixth bit of the
839 * destination address.
840 *
841 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
842 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
843 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
844 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
845 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
846 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
847 *
848 * da[0] represents the least significant bit of the first byte
849 * received, that is, the multicast/unicast indicator, and da[47]
850 * represents the most significant bit of the last byte received. If
851 * the hash index, hi[n], points to a bit that is set in the hash
852 * register then the frame will be matched according to whether the
853 * frame is multicast or unicast. A multicast match will be signalled
854 * if the multicast hash enable bit is set, da[0] is 1 and the hash
855 * index points to a bit set in the hash register. A unicast match
856 * will be signalled if the unicast hash enable bit is set, da[0] is 0
857 * and the hash index points to a bit set in the hash register. To
858 * receive all multicast frames, the hash register should be set with
859 * all ones and the multicast hash enable bit should be set in the
860 * network configuration register.
861 */
862
863static inline int hash_bit_value(int bitnr, __u8 *addr)
864{
865 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
866 return 1;
867 return 0;
868}
869
870/*
871 * Return the hash index value for the specified address.
872 */
873static int hash_get_index(__u8 *addr)
874{
875 int i, j, bitval;
876 int hash_index = 0;
877
878 for (j = 0; j < 6; j++) {
879 for (i = 0, bitval = 0; i < 8; i++)
880 bitval ^= hash_bit_value(i*6 + j, addr);
881
882 hash_index |= (bitval << j);
883 }
884
885 return hash_index;
886}
887
888/*
889 * Add multicast addresses to the internal multicast-hash table.
890 */
891static void macb_sethashtable(struct net_device *dev)
892{
22bedad3 893 struct netdev_hw_addr *ha;
446ebd01 894 unsigned long mc_filter[2];
f9dcbcc9 895 unsigned int bitnr;
446ebd01
PV
896 struct macb *bp = netdev_priv(dev);
897
898 mc_filter[0] = mc_filter[1] = 0;
899
22bedad3
JP
900 netdev_for_each_mc_addr(ha, dev) {
901 bitnr = hash_get_index(ha->addr);
446ebd01
PV
902 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
903 }
904
905 macb_writel(bp, HRB, mc_filter[0]);
906 macb_writel(bp, HRT, mc_filter[1]);
907}
908
909/*
910 * Enable/Disable promiscuous and multicast modes.
911 */
912static void macb_set_rx_mode(struct net_device *dev)
913{
914 unsigned long cfg;
915 struct macb *bp = netdev_priv(dev);
916
917 cfg = macb_readl(bp, NCFGR);
918
919 if (dev->flags & IFF_PROMISC)
920 /* Enable promiscuous mode */
921 cfg |= MACB_BIT(CAF);
922 else if (dev->flags & (~IFF_PROMISC))
923 /* Disable promiscuous mode */
924 cfg &= ~MACB_BIT(CAF);
925
926 if (dev->flags & IFF_ALLMULTI) {
927 /* Enable all multicast mode */
928 macb_writel(bp, HRB, -1);
929 macb_writel(bp, HRT, -1);
930 cfg |= MACB_BIT(NCFGR_MTI);
4cd24eaf 931 } else if (!netdev_mc_empty(dev)) {
446ebd01
PV
932 /* Enable specific multicasts */
933 macb_sethashtable(dev);
934 cfg |= MACB_BIT(NCFGR_MTI);
935 } else if (dev->flags & (~IFF_ALLMULTI)) {
936 /* Disable all multicast mode */
937 macb_writel(bp, HRB, 0);
938 macb_writel(bp, HRT, 0);
939 cfg &= ~MACB_BIT(NCFGR_MTI);
940 }
941
942 macb_writel(bp, NCFGR, cfg);
943}
944
89e5785f
HS
945static int macb_open(struct net_device *dev)
946{
947 struct macb *bp = netdev_priv(dev);
948 int err;
949
c220f8cd 950 netdev_dbg(bp->dev, "open\n");
89e5785f 951
6c36a707
R
952 /* if the phy is not yet register, retry later*/
953 if (!bp->phy_dev)
954 return -EAGAIN;
955
89e5785f
HS
956 if (!is_valid_ether_addr(dev->dev_addr))
957 return -EADDRNOTAVAIL;
958
959 err = macb_alloc_consistent(bp);
960 if (err) {
c220f8cd
JI
961 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
962 err);
89e5785f
HS
963 return err;
964 }
965
bea3348e
SH
966 napi_enable(&bp->napi);
967
89e5785f
HS
968 macb_init_rings(bp);
969 macb_init_hw(bp);
89e5785f 970
6c36a707
R
971 /* schedule a link state check */
972 phy_start(bp->phy_dev);
89e5785f 973
6c36a707 974 netif_start_queue(dev);
89e5785f
HS
975
976 return 0;
977}
978
979static int macb_close(struct net_device *dev)
980{
981 struct macb *bp = netdev_priv(dev);
982 unsigned long flags;
983
89e5785f 984 netif_stop_queue(dev);
bea3348e 985 napi_disable(&bp->napi);
89e5785f 986
6c36a707
R
987 if (bp->phy_dev)
988 phy_stop(bp->phy_dev);
989
89e5785f
HS
990 spin_lock_irqsave(&bp->lock, flags);
991 macb_reset_hw(bp);
992 netif_carrier_off(dev);
993 spin_unlock_irqrestore(&bp->lock, flags);
994
995 macb_free_consistent(bp);
996
997 return 0;
998}
999
1000static struct net_device_stats *macb_get_stats(struct net_device *dev)
1001{
1002 struct macb *bp = netdev_priv(dev);
1003 struct net_device_stats *nstat = &bp->stats;
1004 struct macb_stats *hwstat = &bp->hw_stats;
1005
6c36a707
R
1006 /* read stats from hardware */
1007 macb_update_stats(bp);
1008
89e5785f
HS
1009 /* Convert HW stats into netdevice stats */
1010 nstat->rx_errors = (hwstat->rx_fcs_errors +
1011 hwstat->rx_align_errors +
1012 hwstat->rx_resource_errors +
1013 hwstat->rx_overruns +
1014 hwstat->rx_oversize_pkts +
1015 hwstat->rx_jabbers +
1016 hwstat->rx_undersize_pkts +
1017 hwstat->sqe_test_errors +
1018 hwstat->rx_length_mismatch);
1019 nstat->tx_errors = (hwstat->tx_late_cols +
1020 hwstat->tx_excessive_cols +
1021 hwstat->tx_underruns +
1022 hwstat->tx_carrier_errors);
1023 nstat->collisions = (hwstat->tx_single_cols +
1024 hwstat->tx_multiple_cols +
1025 hwstat->tx_excessive_cols);
1026 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1027 hwstat->rx_jabbers +
1028 hwstat->rx_undersize_pkts +
1029 hwstat->rx_length_mismatch);
b19f7f71
AS
1030 nstat->rx_over_errors = hwstat->rx_resource_errors +
1031 hwstat->rx_overruns;
89e5785f
HS
1032 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1033 nstat->rx_frame_errors = hwstat->rx_align_errors;
1034 nstat->rx_fifo_errors = hwstat->rx_overruns;
1035 /* XXX: What does "missed" mean? */
1036 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1037 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1038 nstat->tx_fifo_errors = hwstat->tx_underruns;
1039 /* Don't know about heartbeat or window errors... */
1040
1041 return nstat;
1042}
1043
1044static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1045{
1046 struct macb *bp = netdev_priv(dev);
6c36a707
R
1047 struct phy_device *phydev = bp->phy_dev;
1048
1049 if (!phydev)
1050 return -ENODEV;
89e5785f 1051
6c36a707 1052 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS
1053}
1054
1055static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1056{
1057 struct macb *bp = netdev_priv(dev);
6c36a707 1058 struct phy_device *phydev = bp->phy_dev;
89e5785f 1059
6c36a707
R
1060 if (!phydev)
1061 return -ENODEV;
1062
1063 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS
1064}
1065
6c36a707
R
1066static void macb_get_drvinfo(struct net_device *dev,
1067 struct ethtool_drvinfo *info)
89e5785f
HS
1068{
1069 struct macb *bp = netdev_priv(dev);
1070
1071 strcpy(info->driver, bp->pdev->dev.driver->name);
1072 strcpy(info->version, "$Revision: 1.14 $");
db1d7bf7 1073 strcpy(info->bus_info, dev_name(&bp->pdev->dev));
89e5785f
HS
1074}
1075
0fc0b732 1076static const struct ethtool_ops macb_ethtool_ops = {
89e5785f
HS
1077 .get_settings = macb_get_settings,
1078 .set_settings = macb_set_settings,
1079 .get_drvinfo = macb_get_drvinfo,
89e5785f
HS
1080 .get_link = ethtool_op_get_link,
1081};
1082
1083static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1084{
1085 struct macb *bp = netdev_priv(dev);
6c36a707 1086 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS
1087
1088 if (!netif_running(dev))
1089 return -EINVAL;
1090
6c36a707
R
1091 if (!phydev)
1092 return -ENODEV;
89e5785f 1093
28b04113 1094 return phy_mii_ioctl(phydev, rq, cmd);
89e5785f
HS
1095}
1096
5f1fa992
AB
1097static const struct net_device_ops macb_netdev_ops = {
1098 .ndo_open = macb_open,
1099 .ndo_stop = macb_close,
1100 .ndo_start_xmit = macb_start_xmit,
afc4b13d 1101 .ndo_set_rx_mode = macb_set_rx_mode,
5f1fa992
AB
1102 .ndo_get_stats = macb_get_stats,
1103 .ndo_do_ioctl = macb_ioctl,
1104 .ndo_validate_addr = eth_validate_addr,
1105 .ndo_change_mtu = eth_change_mtu,
1106 .ndo_set_mac_address = eth_mac_addr,
6e8cf5c0
TP
1107#ifdef CONFIG_NET_POLL_CONTROLLER
1108 .ndo_poll_controller = macb_poll_controller,
1109#endif
5f1fa992
AB
1110};
1111
06c3fd6a 1112static int __init macb_probe(struct platform_device *pdev)
89e5785f 1113{
84e0cdb0 1114 struct macb_platform_data *pdata;
89e5785f
HS
1115 struct resource *regs;
1116 struct net_device *dev;
1117 struct macb *bp;
6c36a707 1118 struct phy_device *phydev;
89e5785f
HS
1119 unsigned long pclk_hz;
1120 u32 config;
1121 int err = -ENXIO;
1122
1123 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1124 if (!regs) {
1125 dev_err(&pdev->dev, "no mmio resource defined\n");
1126 goto err_out;
1127 }
1128
1129 err = -ENOMEM;
1130 dev = alloc_etherdev(sizeof(*bp));
1131 if (!dev) {
1132 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
1133 goto err_out;
1134 }
1135
89e5785f
HS
1136 SET_NETDEV_DEV(dev, &pdev->dev);
1137
1138 /* TODO: Actually, we have some interesting features... */
1139 dev->features |= 0;
1140
1141 bp = netdev_priv(dev);
1142 bp->pdev = pdev;
1143 bp->dev = dev;
1144
1145 spin_lock_init(&bp->lock);
1146
461845db 1147 bp->pclk = clk_get(&pdev->dev, "pclk");
0cc8674f
AV
1148 if (IS_ERR(bp->pclk)) {
1149 dev_err(&pdev->dev, "failed to get macb_clk\n");
1150 goto err_out_free_dev;
1151 }
1152 clk_enable(bp->pclk);
461845db 1153
89e5785f
HS
1154 bp->hclk = clk_get(&pdev->dev, "hclk");
1155 if (IS_ERR(bp->hclk)) {
1156 dev_err(&pdev->dev, "failed to get hclk\n");
1157 goto err_out_put_pclk;
1158 }
89e5785f
HS
1159 clk_enable(bp->hclk);
1160
28f65c11 1161 bp->regs = ioremap(regs->start, resource_size(regs));
89e5785f
HS
1162 if (!bp->regs) {
1163 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1164 err = -ENOMEM;
1165 goto err_out_disable_clocks;
1166 }
1167
1168 dev->irq = platform_get_irq(pdev, 0);
ab392d2d 1169 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
89e5785f 1170 if (err) {
c220f8cd
JI
1171 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1172 dev->irq, err);
89e5785f
HS
1173 goto err_out_iounmap;
1174 }
1175
5f1fa992 1176 dev->netdev_ops = &macb_netdev_ops;
bea3348e 1177 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f
HS
1178 dev->ethtool_ops = &macb_ethtool_ops;
1179
1180 dev->base_addr = regs->start;
1181
89e5785f
HS
1182 /* Set MII management clock divider */
1183 pclk_hz = clk_get_rate(bp->pclk);
1184 if (pclk_hz <= 20000000)
1185 config = MACB_BF(CLK, MACB_CLK_DIV8);
1186 else if (pclk_hz <= 40000000)
1187 config = MACB_BF(CLK, MACB_CLK_DIV16);
1188 else if (pclk_hz <= 80000000)
1189 config = MACB_BF(CLK, MACB_CLK_DIV32);
1190 else
1191 config = MACB_BF(CLK, MACB_CLK_DIV64);
1192 macb_writel(bp, NCFGR, config);
1193
89e5785f 1194 macb_get_hwaddr(bp);
89e5785f 1195 pdata = pdev->dev.platform_data;
6c36a707 1196
89e5785f 1197 if (pdata && pdata->is_rmii)
0cc8674f
AV
1198#if defined(CONFIG_ARCH_AT91)
1199 macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
1200#else
89e5785f 1201 macb_writel(bp, USRIO, 0);
0cc8674f 1202#endif
89e5785f 1203 else
0cc8674f
AV
1204#if defined(CONFIG_ARCH_AT91)
1205 macb_writel(bp, USRIO, MACB_BIT(CLKEN));
1206#else
89e5785f 1207 macb_writel(bp, USRIO, MACB_BIT(MII));
0cc8674f 1208#endif
89e5785f
HS
1209
1210 bp->tx_pending = DEF_TX_RING_PENDING;
1211
1212 err = register_netdev(dev);
1213 if (err) {
1214 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1215 goto err_out_free_irq;
1216 }
1217
6c36a707
R
1218 if (macb_mii_init(bp) != 0) {
1219 goto err_out_unregister_netdev;
1220 }
89e5785f 1221
6c36a707 1222 platform_set_drvdata(pdev, dev);
89e5785f 1223
c220f8cd
JI
1224 netdev_info(dev, "Atmel MACB at 0x%08lx irq %d (%pM)\n",
1225 dev->base_addr, dev->irq, dev->dev_addr);
89e5785f 1226
6c36a707 1227 phydev = bp->phy_dev;
c220f8cd
JI
1228 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1229 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
6c36a707 1230
89e5785f
HS
1231 return 0;
1232
6c36a707
R
1233err_out_unregister_netdev:
1234 unregister_netdev(dev);
89e5785f
HS
1235err_out_free_irq:
1236 free_irq(dev->irq, dev);
1237err_out_iounmap:
1238 iounmap(bp->regs);
1239err_out_disable_clocks:
1240 clk_disable(bp->hclk);
89e5785f 1241 clk_put(bp->hclk);
0cc8674f 1242 clk_disable(bp->pclk);
89e5785f
HS
1243err_out_put_pclk:
1244 clk_put(bp->pclk);
1245err_out_free_dev:
1246 free_netdev(dev);
1247err_out:
1248 platform_set_drvdata(pdev, NULL);
1249 return err;
1250}
1251
06c3fd6a 1252static int __exit macb_remove(struct platform_device *pdev)
89e5785f
HS
1253{
1254 struct net_device *dev;
1255 struct macb *bp;
1256
1257 dev = platform_get_drvdata(pdev);
1258
1259 if (dev) {
1260 bp = netdev_priv(dev);
84b7901f
AN
1261 if (bp->phy_dev)
1262 phy_disconnect(bp->phy_dev);
298cf9be
LB
1263 mdiobus_unregister(bp->mii_bus);
1264 kfree(bp->mii_bus->irq);
1265 mdiobus_free(bp->mii_bus);
89e5785f
HS
1266 unregister_netdev(dev);
1267 free_irq(dev->irq, dev);
1268 iounmap(bp->regs);
1269 clk_disable(bp->hclk);
89e5785f 1270 clk_put(bp->hclk);
0cc8674f 1271 clk_disable(bp->pclk);
89e5785f
HS
1272 clk_put(bp->pclk);
1273 free_netdev(dev);
1274 platform_set_drvdata(pdev, NULL);
1275 }
1276
1277 return 0;
1278}
1279
c1f598fd
HS
1280#ifdef CONFIG_PM
1281static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1282{
1283 struct net_device *netdev = platform_get_drvdata(pdev);
1284 struct macb *bp = netdev_priv(netdev);
1285
1286 netif_device_detach(netdev);
1287
c1f598fd 1288 clk_disable(bp->hclk);
c1f598fd
HS
1289 clk_disable(bp->pclk);
1290
1291 return 0;
1292}
1293
1294static int macb_resume(struct platform_device *pdev)
1295{
1296 struct net_device *netdev = platform_get_drvdata(pdev);
1297 struct macb *bp = netdev_priv(netdev);
1298
1299 clk_enable(bp->pclk);
c1f598fd 1300 clk_enable(bp->hclk);
c1f598fd
HS
1301
1302 netif_device_attach(netdev);
1303
1304 return 0;
1305}
1306#else
1307#define macb_suspend NULL
1308#define macb_resume NULL
1309#endif
1310
89e5785f 1311static struct platform_driver macb_driver = {
06c3fd6a 1312 .remove = __exit_p(macb_remove),
c1f598fd
HS
1313 .suspend = macb_suspend,
1314 .resume = macb_resume,
89e5785f
HS
1315 .driver = {
1316 .name = "macb",
72abb461 1317 .owner = THIS_MODULE,
89e5785f
HS
1318 },
1319};
1320
1321static int __init macb_init(void)
1322{
06c3fd6a 1323 return platform_driver_probe(&macb_driver, macb_probe);
89e5785f
HS
1324}
1325
1326static void __exit macb_exit(void)
1327{
1328 platform_driver_unregister(&macb_driver);
1329}
1330
1331module_init(macb_init);
1332module_exit(macb_exit);
1333
1334MODULE_LICENSE("GPL");
1335MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
e05503ef 1336MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
72abb461 1337MODULE_ALIAS("platform:macb");