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net/macb: configure for FIFO mode and non-gigabit
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / cadence / macb.c
CommitLineData
89e5785f 1/*
f75ba50b 2 * Cadence MACB/GEM Ethernet Controller driver
89e5785f
HS		 3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
c220f8cd 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
89e5785f
HS		 12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
909a8583 17#include <linux/circ_buf.h>
89e5785f
HS		 18#include <linux/slab.h>
19#include <linux/init.h>
60fe716f 20#include <linux/io.h>
2dbfdbb9 21#include <linux/gpio.h>
a6b7a407 22#include <linux/interrupt.h>
89e5785f
HS		 23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
89e5785f 25#include <linux/dma-mapping.h>
84e0cdb0 26#include <linux/platform_data/macb.h>
89e5785f 27#include <linux/platform_device.h>
6c36a707 28#include <linux/phy.h>
b17471f5 29#include <linux/of.h>
fb97a846 30#include <linux/of_device.h>
148cbb53 31#include <linux/of_mdio.h>
fb97a846 32#include <linux/of_net.h>
8ef29f8a 33#include <linux/pinctrl/consumer.h>
89e5785f 34
89e5785f
HS		 35#include "macb.h"
36
1b44791a 37#define MACB_RX_BUFFER_SIZE 128
1b44791a 38#define RX_BUFFER_MULTIPLE 64 /* bytes */
55054a16
HS		 39#define RX_RING_SIZE 512 /* must be power of 2 */
40#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
89e5785f 41
55054a16
HS		 42#define TX_RING_SIZE 128 /* must be power of 2 */
43#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
89e5785f 44
909a8583
NF		 45/* level of occupied TX descriptors under which we wake up TX process */
46#define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
89e5785f
HS		 47
48#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 | MACB_BIT(ISR_ROVR))
e86cd53a
NF		 50#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
51 | MACB_BIT(ISR_RLE) \
52 | MACB_BIT(TXERR))
53#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
54
55/*
56 * Graceful stop timeouts in us. We should allow up to
57 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
58 */
59#define MACB_HALT_TIMEOUT 1230
89e5785f 60
55054a16
HS		 61/* Ring buffer accessors */
62static unsigned int macb_tx_ring_wrap(unsigned int index)
63{
64 return index & (TX_RING_SIZE - 1);
65}
66
55054a16
HS		 67static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
68{
69 return &bp->tx_ring[macb_tx_ring_wrap(index)];
70}
71
72static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
73{
74 return &bp->tx_skb[macb_tx_ring_wrap(index)];
75}
76
77static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
78{
79 dma_addr_t offset;
80
81 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
82
83 return bp->tx_ring_dma + offset;
84}
85
86static unsigned int macb_rx_ring_wrap(unsigned int index)
87{
88 return index & (RX_RING_SIZE - 1);
89}
90
91static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
92{
93 return &bp->rx_ring[macb_rx_ring_wrap(index)];
94}
95
96static void *macb_rx_buffer(struct macb *bp, unsigned int index)
97{
1b44791a 98 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
55054a16
HS		 99}
100
314bccc4 101void macb_set_hwaddr(struct macb *bp)
89e5785f
HS		 102{
103 u32 bottom;
104 u16 top;
105
106 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
f75ba50b 107 macb_or_gem_writel(bp, SA1B, bottom);
89e5785f 108 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
f75ba50b 109 macb_or_gem_writel(bp, SA1T, top);
3629a6ce
JE		 110
111 /* Clear unused address register sets */
112 macb_or_gem_writel(bp, SA2B, 0);
113 macb_or_gem_writel(bp, SA2T, 0);
114 macb_or_gem_writel(bp, SA3B, 0);
115 macb_or_gem_writel(bp, SA3T, 0);
116 macb_or_gem_writel(bp, SA4B, 0);
117 macb_or_gem_writel(bp, SA4T, 0);
89e5785f 118}
314bccc4 119EXPORT_SYMBOL_GPL(macb_set_hwaddr);
89e5785f 120
314bccc4 121void macb_get_hwaddr(struct macb *bp)
89e5785f 122{
d25e78aa 123 struct macb_platform_data *pdata;
89e5785f
HS		 124 u32 bottom;
125 u16 top;
126 u8 addr[6];
17b8bb3e
JE		 127 int i;
128
c607a0d9 129 pdata = dev_get_platdata(&bp->pdev->dev);
d25e78aa 130
17b8bb3e
JE		 131 /* Check all 4 address register for vaild address */
132 for (i = 0; i < 4; i++) {
133 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
134 top = macb_or_gem_readl(bp, SA1T + i * 8);
135
d25e78aa
JE		 136 if (pdata && pdata->rev_eth_addr) {
137 addr[5] = bottom & 0xff;
138 addr[4] = (bottom >> 8) & 0xff;
139 addr[3] = (bottom >> 16) & 0xff;
140 addr[2] = (bottom >> 24) & 0xff;
141 addr[1] = top & 0xff;
142 addr[0] = (top & 0xff00) >> 8;
143 } else {
144 addr[0] = bottom & 0xff;
145 addr[1] = (bottom >> 8) & 0xff;
146 addr[2] = (bottom >> 16) & 0xff;
147 addr[3] = (bottom >> 24) & 0xff;
148 addr[4] = top & 0xff;
149 addr[5] = (top >> 8) & 0xff;
150 }
17b8bb3e
JE		 151
152 if (is_valid_ether_addr(addr)) {
153 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
154 return;
155 }
d1d5741d 156 }
17b8bb3e
JE		 157
158 netdev_info(bp->dev, "invalid hw address, using random\n");
159 eth_hw_addr_random(bp->dev);
89e5785f 160}
314bccc4 161EXPORT_SYMBOL_GPL(macb_get_hwaddr);
89e5785f 162
6c36a707 163static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 164{
6c36a707 165 struct macb *bp = bus->priv;
89e5785f
HS		 166 int value;
167
89e5785f
HS		 168 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
169 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R		 170 | MACB_BF(PHYA, mii_id)
171 | MACB_BF(REGA, regnum)
89e5785f
HS		 172 | MACB_BF(CODE, MACB_MAN_CODE)));
173
6c36a707
R		 174 /* wait for end of transfer */
175 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
176 cpu_relax();
89e5785f
HS		 177
178 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS		 179
180 return value;
181}
182
6c36a707
R		 183static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
184 u16 value)
89e5785f 185{
6c36a707 186 struct macb *bp = bus->priv;
89e5785f
HS		 187
188 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
189 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R		 190 | MACB_BF(PHYA, mii_id)
191 | MACB_BF(REGA, regnum)
89e5785f 192 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 193 | MACB_BF(DATA, value)));
89e5785f 194
6c36a707
R		 195 /* wait for end of transfer */
196 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
197 cpu_relax();
198
199 return 0;
200}
89e5785f 201
e1824dfe
SB		 202/**
203 * macb_set_tx_clk() - Set a clock to a new frequency
204 * @clk Pointer to the clock to change
205 * @rate New frequency in Hz
206 * @dev Pointer to the struct net_device
207 */
208static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
209{
210 long ferr, rate, rate_rounded;
211
212 switch (speed) {
213 case SPEED_10:
214 rate = 2500000;
215 break;
216 case SPEED_100:
217 rate = 25000000;
218 break;
219 case SPEED_1000:
220 rate = 125000000;
221 break;
222 default:
9319e47c 223 return;
e1824dfe
SB		 224 }
225
226 rate_rounded = clk_round_rate(clk, rate);
227 if (rate_rounded < 0)
228 return;
229
230 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
231 * is not satisfied.
232 */
233 ferr = abs(rate_rounded - rate);
234 ferr = DIV_ROUND_UP(ferr, rate / 100000);
235 if (ferr > 5)
236 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
237 rate);
238
239 if (clk_set_rate(clk, rate_rounded))
240 netdev_err(dev, "adjusting tx_clk failed.\n");
241}
242
6c36a707 243static void macb_handle_link_change(struct net_device *dev)
89e5785f 244{
6c36a707
R		 245 struct macb *bp = netdev_priv(dev);
246 struct phy_device *phydev = bp->phy_dev;
247 unsigned long flags;
89e5785f 248
6c36a707 249 int status_change = 0;
89e5785f 250
6c36a707
R		 251 spin_lock_irqsave(&bp->lock, flags);
252
253 if (phydev->link) {
254 if ((bp->speed != phydev->speed) ||
255 (bp->duplex != phydev->duplex)) {
256 u32 reg;
257
258 reg = macb_readl(bp, NCFGR);
259 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
140b7552
PV		 260 if (macb_is_gem(bp))
261 reg &= ~GEM_BIT(GBE);
6c36a707
R		 262
263 if (phydev->duplex)
264 reg |= MACB_BIT(FD);
179956f4 265 if (phydev->speed == SPEED_100)
6c36a707 266 reg |= MACB_BIT(SPD);
e175587f
NF		 267 if (phydev->speed == SPEED_1000 &&
268 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
140b7552 269 reg |= GEM_BIT(GBE);
6c36a707 270
140b7552 271 macb_or_gem_writel(bp, NCFGR, reg);
6c36a707
R		 272
273 bp->speed = phydev->speed;
274 bp->duplex = phydev->duplex;
275 status_change = 1;
276 }
89e5785f
HS		 277 }
278
6c36a707 279 if (phydev->link != bp->link) {
c8f15686 280 if (!phydev->link) {
6c36a707
R		 281 bp->speed = 0;
282 bp->duplex = -1;
283 }
284 bp->link = phydev->link;
89e5785f 285
6c36a707
R		 286 status_change = 1;
287 }
89e5785f 288
6c36a707
R		 289 spin_unlock_irqrestore(&bp->lock, flags);
290
e1824dfe
SB		 291 if (!IS_ERR(bp->tx_clk))
292 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
293
6c36a707 294 if (status_change) {
03fc4721
NF		 295 if (phydev->link) {
296 netif_carrier_on(dev);
c220f8cd
JI		 297 netdev_info(dev, "link up (%d/%s)\n",
298 phydev->speed,
299 phydev->duplex == DUPLEX_FULL ?
300 "Full" : "Half");
03fc4721
NF		 301 } else {
302 netif_carrier_off(dev);
c220f8cd 303 netdev_info(dev, "link down\n");
03fc4721 304 }
6c36a707 305 }
89e5785f
HS		 306}
307
6c36a707
R		 308/* based on au1000_eth. c*/
309static int macb_mii_probe(struct net_device *dev)
89e5785f 310{
6c36a707 311 struct macb *bp = netdev_priv(dev);
2dbfdbb9 312 struct macb_platform_data *pdata;
7455a76f 313 struct phy_device *phydev;
2dbfdbb9 314 int phy_irq;
7455a76f 315 int ret;
6c36a707 316
7455a76f 317 phydev = phy_find_first(bp->mii_bus);
6c36a707 318 if (!phydev) {
c220f8cd 319 netdev_err(dev, "no PHY found\n");
7daa78e3 320 return -ENXIO;
6c36a707
R		 321 }
322
2dbfdbb9
JE		 323 pdata = dev_get_platdata(&bp->pdev->dev);
324 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
325 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
326 if (!ret) {
327 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
328 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
329 }
330 }
6c36a707
R		 331
332 /* attach the mac to the phy */
f9a8f83b 333 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
fb97a846 334 bp->phy_interface);
7455a76f 335 if (ret) {
c220f8cd 336 netdev_err(dev, "Could not attach to PHY\n");
7455a76f 337 return ret;
6c36a707
R		 338 }
339
340 /* mask with MAC supported features */
e175587f 341 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
140b7552
PV		 342 phydev->supported &= PHY_GBIT_FEATURES;
343 else
344 phydev->supported &= PHY_BASIC_FEATURES;
6c36a707
R		 345
346 phydev->advertising = phydev->supported;
347
348 bp->link = 0;
349 bp->speed = 0;
350 bp->duplex = -1;
351 bp->phy_dev = phydev;
352
353 return 0;
89e5785f
HS		 354}
355
0005f541 356int macb_mii_init(struct macb *bp)
89e5785f 357{
84e0cdb0 358 struct macb_platform_data *pdata;
148cbb53 359 struct device_node *np;
6c36a707 360 int err = -ENXIO, i;
89e5785f 361
3dbda77e 362 /* Enable management port */
6c36a707 363 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 364
298cf9be
LB		 365 bp->mii_bus = mdiobus_alloc();
366 if (bp->mii_bus == NULL) {
367 err = -ENOMEM;
368 goto err_out;
369 }
370
371 bp->mii_bus->name = "MACB_mii_bus";
372 bp->mii_bus->read = &macb_mdio_read;
373 bp->mii_bus->write = &macb_mdio_write;
98d5e57e
FF		 374 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
375 bp->pdev->name, bp->pdev->id);
298cf9be
LB		 376 bp->mii_bus->priv = bp;
377 bp->mii_bus->parent = &bp->dev->dev;
c607a0d9 378 pdata = dev_get_platdata(&bp->pdev->dev);
89e5785f 379
298cf9be
LB		 380 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
381 if (!bp->mii_bus->irq) {
6c36a707 382 err = -ENOMEM;
298cf9be 383 goto err_out_free_mdiobus;
89e5785f
HS		 384 }
385
91523947 386 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
89e5785f 387
148cbb53
BB		 388 np = bp->pdev->dev.of_node;
389 if (np) {
390 /* try dt phy registration */
391 err = of_mdiobus_register(bp->mii_bus, np);
392
393 /* fallback to standard phy registration if no phy were
394 found during dt phy registration */
395 if (!err && !phy_find_first(bp->mii_bus)) {
396 for (i = 0; i < PHY_MAX_ADDR; i++) {
397 struct phy_device *phydev;
398
399 phydev = mdiobus_scan(bp->mii_bus, i);
400 if (IS_ERR(phydev)) {
401 err = PTR_ERR(phydev);
402 break;
403 }
404 }
405
406 if (err)
407 goto err_out_unregister_bus;
408 }
409 } else {
410 for (i = 0; i < PHY_MAX_ADDR; i++)
411 bp->mii_bus->irq[i] = PHY_POLL;
412
413 if (pdata)
414 bp->mii_bus->phy_mask = pdata->phy_mask;
415
416 err = mdiobus_register(bp->mii_bus);
417 }
418
419 if (err)
6c36a707 420 goto err_out_free_mdio_irq;
89e5785f 421
7daa78e3
BB		 422 err = macb_mii_probe(bp->dev);
423 if (err)
6c36a707 424 goto err_out_unregister_bus;
89e5785f 425
6c36a707 426 return 0;
89e5785f 427
6c36a707 428err_out_unregister_bus:
298cf9be 429 mdiobus_unregister(bp->mii_bus);
6c36a707 430err_out_free_mdio_irq:
298cf9be
LB		 431 kfree(bp->mii_bus->irq);
432err_out_free_mdiobus:
433 mdiobus_free(bp->mii_bus);
6c36a707
R		 434err_out:
435 return err;
89e5785f 436}
0005f541 437EXPORT_SYMBOL_GPL(macb_mii_init);
89e5785f
HS		 438
439static void macb_update_stats(struct macb *bp)
440{
441 u32 __iomem *reg = bp->regs + MACB_PFR;
a494ed8e
JI		 442 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
443 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
89e5785f
HS		 444
445 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
446
447 for(; p < end; p++, reg++)
0f0d84e5 448 *p += __raw_readl(reg);
89e5785f
HS		 449}
450
e86cd53a 451static int macb_halt_tx(struct macb *bp)
89e5785f 452{
e86cd53a
NF		 453 unsigned long halt_time, timeout;
454 u32 status;
89e5785f 455
e86cd53a 456 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
89e5785f 457
e86cd53a
NF		 458 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
459 do {
460 halt_time = jiffies;
461 status = macb_readl(bp, TSR);
462 if (!(status & MACB_BIT(TGO)))
463 return 0;
89e5785f 464
e86cd53a
NF		 465 usleep_range(10, 250);
466 } while (time_before(halt_time, timeout));
bdcba151 467
e86cd53a
NF		 468 return -ETIMEDOUT;
469}
39eddb4c 470
e86cd53a
NF		 471static void macb_tx_error_task(struct work_struct *work)
472{
473 struct macb *bp = container_of(work, struct macb, tx_error_task);
474 struct macb_tx_skb *tx_skb;
475 struct sk_buff *skb;
476 unsigned int tail;
bdcba151 477
e86cd53a
NF		 478 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
479 bp->tx_tail, bp->tx_head);
bdcba151 480
e86cd53a
NF		 481 /* Make sure nobody is trying to queue up new packets */
482 netif_stop_queue(bp->dev);
d3e61457 483
e86cd53a
NF		 484 /*
485 * Stop transmission now
486 * (in case we have just queued new packets)
487 */
488 if (macb_halt_tx(bp))
489 /* Just complain for now, reinitializing TX path can be good */
490 netdev_err(bp->dev, "BUG: halt tx timed out\n");
bdcba151 491
e86cd53a 492 /* No need for the lock here as nobody will interrupt us anymore */
bdcba151 493
e86cd53a
NF		 494 /*
495 * Treat frames in TX queue including the ones that caused the error.
496 * Free transmit buffers in upper layer.
497 */
498 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
499 struct macb_dma_desc *desc;
500 u32 ctrl;
55054a16 501
e86cd53a
NF		 502 desc = macb_tx_desc(bp, tail);
503 ctrl = desc->ctrl;
504 tx_skb = macb_tx_skb(bp, tail);
505 skb = tx_skb->skb;
bdcba151 506
e86cd53a
NF		 507 if (ctrl & MACB_BIT(TX_USED)) {
508 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
509 macb_tx_ring_wrap(tail), skb->data);
510 bp->stats.tx_packets++;
511 bp->stats.tx_bytes += skb->len;
512 } else {
513 /*
514 * "Buffers exhausted mid-frame" errors may only happen
515 * if the driver is buggy, so complain loudly about those.
516 * Statistics are updated by hardware.
517 */
518 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
519 netdev_err(bp->dev,
520 "BUG: TX buffers exhausted mid-frame\n");
39eddb4c 521
e86cd53a
NF		 522 desc->ctrl = ctrl | MACB_BIT(TX_USED);
523 }
524
525 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
526 DMA_TO_DEVICE);
527 tx_skb->skb = NULL;
528 dev_kfree_skb(skb);
89e5785f
HS		 529 }
530
e86cd53a
NF		 531 /* Make descriptor updates visible to hardware */
532 wmb();
533
534 /* Reinitialize the TX desc queue */
535 macb_writel(bp, TBQP, bp->tx_ring_dma);
536 /* Make TX ring reflect state of hardware */
537 bp->tx_head = bp->tx_tail = 0;
538
539 /* Now we are ready to start transmission again */
540 netif_wake_queue(bp->dev);
541
542 /* Housework before enabling TX IRQ */
543 macb_writel(bp, TSR, macb_readl(bp, TSR));
544 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
545}
546
547static void macb_tx_interrupt(struct macb *bp)
548{
549 unsigned int tail;
550 unsigned int head;
551 u32 status;
552
553 status = macb_readl(bp, TSR);
554 macb_writel(bp, TSR, status);
555
581df9e1
NF		 556 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
557 macb_writel(bp, ISR, MACB_BIT(TCOMP));
749a2b66 558
e86cd53a
NF		 559 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
560 (unsigned long)status);
89e5785f
HS		 561
562 head = bp->tx_head;
55054a16
HS		 563 for (tail = bp->tx_tail; tail != head; tail++) {
564 struct macb_tx_skb *tx_skb;
565 struct sk_buff *skb;
566 struct macb_dma_desc *desc;
567 u32 ctrl;
89e5785f 568
55054a16 569 desc = macb_tx_desc(bp, tail);
89e5785f 570
03dbe05f 571 /* Make hw descriptor updates visible to CPU */
89e5785f 572 rmb();
03dbe05f 573
55054a16 574 ctrl = desc->ctrl;
89e5785f 575
55054a16 576 if (!(ctrl & MACB_BIT(TX_USED)))
89e5785f
HS		 577 break;
578
55054a16
HS		 579 tx_skb = macb_tx_skb(bp, tail);
580 skb = tx_skb->skb;
581
a268adb1 582 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
55054a16
HS		 583 macb_tx_ring_wrap(tail), skb->data);
584 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
89e5785f
HS		 585 DMA_TO_DEVICE);
586 bp->stats.tx_packets++;
587 bp->stats.tx_bytes += skb->len;
55054a16 588 tx_skb->skb = NULL;
89e5785f
HS		 589 dev_kfree_skb_irq(skb);
590 }
591
592 bp->tx_tail = tail;
55054a16 593 if (netif_queue_stopped(bp->dev)
909a8583
NF		 594 && CIRC_CNT(bp->tx_head, bp->tx_tail,
595 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
89e5785f
HS		 596 netif_wake_queue(bp->dev);
597}
598
4df95131
NF		 599static void gem_rx_refill(struct macb *bp)
600{
601 unsigned int entry;
602 struct sk_buff *skb;
4df95131
NF		 603 dma_addr_t paddr;
604
605 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
4df95131 606 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
4df95131
NF		 607
608 /* Make hw descriptor updates visible to CPU */
609 rmb();
610
4df95131
NF		 611 bp->rx_prepared_head++;
612
4df95131
NF		 613 if (bp->rx_skbuff[entry] == NULL) {
614 /* allocate sk_buff for this free entry in ring */
615 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
616 if (unlikely(skb == NULL)) {
617 netdev_err(bp->dev,
618 "Unable to allocate sk_buff\n");
619 break;
620 }
4df95131
NF		 621
622 /* now fill corresponding descriptor entry */
623 paddr = dma_map_single(&bp->pdev->dev, skb->data,
624 bp->rx_buffer_size, DMA_FROM_DEVICE);
92030908
SB		 625 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
626 dev_kfree_skb(skb);
627 break;
628 }
629
630 bp->rx_skbuff[entry] = skb;
4df95131
NF		 631
632 if (entry == RX_RING_SIZE - 1)
633 paddr |= MACB_BIT(RX_WRAP);
634 bp->rx_ring[entry].addr = paddr;
635 bp->rx_ring[entry].ctrl = 0;
636
637 /* properly align Ethernet header */
638 skb_reserve(skb, NET_IP_ALIGN);
639 }
640 }
641
642 /* Make descriptor updates visible to hardware */
643 wmb();
644
645 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
646 bp->rx_prepared_head, bp->rx_tail);
647}
648
649/* Mark DMA descriptors from begin up to and not including end as unused */
650static void discard_partial_frame(struct macb *bp, unsigned int begin,
651 unsigned int end)
652{
653 unsigned int frag;
654
655 for (frag = begin; frag != end; frag++) {
656 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
657 desc->addr &= ~MACB_BIT(RX_USED);
658 }
659
660 /* Make descriptor updates visible to hardware */
661 wmb();
662
663 /*
664 * When this happens, the hardware stats registers for
665 * whatever caused this is updated, so we don't have to record
666 * anything.
667 */
668}
669
670static int gem_rx(struct macb *bp, int budget)
671{
672 unsigned int len;
673 unsigned int entry;
674 struct sk_buff *skb;
675 struct macb_dma_desc *desc;
676 int count = 0;
677
678 while (count < budget) {
679 u32 addr, ctrl;
680
681 entry = macb_rx_ring_wrap(bp->rx_tail);
682 desc = &bp->rx_ring[entry];
683
684 /* Make hw descriptor updates visible to CPU */
685 rmb();
686
687 addr = desc->addr;
688 ctrl = desc->ctrl;
689
690 if (!(addr & MACB_BIT(RX_USED)))
691 break;
692
4df95131
NF		 693 bp->rx_tail++;
694 count++;
695
696 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
697 netdev_err(bp->dev,
698 "not whole frame pointed by descriptor\n");
699 bp->stats.rx_dropped++;
700 break;
701 }
702 skb = bp->rx_skbuff[entry];
703 if (unlikely(!skb)) {
704 netdev_err(bp->dev,
705 "inconsistent Rx descriptor chain\n");
706 bp->stats.rx_dropped++;
707 break;
708 }
709 /* now everything is ready for receiving packet */
710 bp->rx_skbuff[entry] = NULL;
711 len = MACB_BFEXT(RX_FRMLEN, ctrl);
712
713 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
714
715 skb_put(skb, len);
716 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
717 dma_unmap_single(&bp->pdev->dev, addr,
48330e08 718 bp->rx_buffer_size, DMA_FROM_DEVICE);
4df95131
NF		 719
720 skb->protocol = eth_type_trans(skb, bp->dev);
721 skb_checksum_none_assert(skb);
722
723 bp->stats.rx_packets++;
724 bp->stats.rx_bytes += skb->len;
725
726#if defined(DEBUG) && defined(VERBOSE_DEBUG)
727 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
728 skb->len, skb->csum);
729 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
730 skb->mac_header, 16, true);
731 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
732 skb->data, 32, true);
733#endif
734
735 netif_receive_skb(skb);
736 }
737
738 gem_rx_refill(bp);
739
740 return count;
741}
742
89e5785f
HS		 743static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
744 unsigned int last_frag)
745{
746 unsigned int len;
747 unsigned int frag;
29bc2e1e 748 unsigned int offset;
89e5785f 749 struct sk_buff *skb;
55054a16 750 struct macb_dma_desc *desc;
89e5785f 751
55054a16
HS		 752 desc = macb_rx_desc(bp, last_frag);
753 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
89e5785f 754
a268adb1 755 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
55054a16
HS		 756 macb_rx_ring_wrap(first_frag),
757 macb_rx_ring_wrap(last_frag), len);
89e5785f 758
29bc2e1e
HS		 759 /*
760 * The ethernet header starts NET_IP_ALIGN bytes into the
761 * first buffer. Since the header is 14 bytes, this makes the
762 * payload word-aligned.
763 *
764 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
765 * the two padding bytes into the skb so that we avoid hitting
766 * the slowpath in memcpy(), and pull them off afterwards.
767 */
768 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
89e5785f
HS		 769 if (!skb) {
770 bp->stats.rx_dropped++;
55054a16
HS		 771 for (frag = first_frag; ; frag++) {
772 desc = macb_rx_desc(bp, frag);
773 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS		 774 if (frag == last_frag)
775 break;
776 }
03dbe05f
HS		 777
778 /* Make descriptor updates visible to hardware */
89e5785f 779 wmb();
03dbe05f 780
89e5785f
HS		 781 return 1;
782 }
783
29bc2e1e
HS		 784 offset = 0;
785 len += NET_IP_ALIGN;
bc8acf2c 786 skb_checksum_none_assert(skb);
89e5785f
HS		 787 skb_put(skb, len);
788
55054a16 789 for (frag = first_frag; ; frag++) {
1b44791a 790 unsigned int frag_len = bp->rx_buffer_size;
89e5785f
HS		 791
792 if (offset + frag_len > len) {
793 BUG_ON(frag != last_frag);
794 frag_len = len - offset;
795 }
27d7ff46 796 skb_copy_to_linear_data_offset(skb, offset,
55054a16 797 macb_rx_buffer(bp, frag), frag_len);
1b44791a 798 offset += bp->rx_buffer_size;
55054a16
HS		 799 desc = macb_rx_desc(bp, frag);
800 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS		 801
802 if (frag == last_frag)
803 break;
804 }
805
03dbe05f
HS		 806 /* Make descriptor updates visible to hardware */
807 wmb();
808
29bc2e1e 809 __skb_pull(skb, NET_IP_ALIGN);
89e5785f
HS		 810 skb->protocol = eth_type_trans(skb, bp->dev);
811
812 bp->stats.rx_packets++;
29bc2e1e 813 bp->stats.rx_bytes += skb->len;
a268adb1 814 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
c220f8cd 815 skb->len, skb->csum);
89e5785f
HS		 816 netif_receive_skb(skb);
817
818 return 0;
819}
820
89e5785f
HS		 821static int macb_rx(struct macb *bp, int budget)
822{
823 int received = 0;
55054a16 824 unsigned int tail;
89e5785f
HS		 825 int first_frag = -1;
826
55054a16
HS		 827 for (tail = bp->rx_tail; budget > 0; tail++) {
828 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
89e5785f
HS		 829 u32 addr, ctrl;
830
03dbe05f 831 /* Make hw descriptor updates visible to CPU */
89e5785f 832 rmb();
03dbe05f 833
55054a16
HS		 834 addr = desc->addr;
835 ctrl = desc->ctrl;
89e5785f
HS		 836
837 if (!(addr & MACB_BIT(RX_USED)))
838 break;
839
840 if (ctrl & MACB_BIT(RX_SOF)) {
841 if (first_frag != -1)
842 discard_partial_frame(bp, first_frag, tail);
843 first_frag = tail;
844 }
845
846 if (ctrl & MACB_BIT(RX_EOF)) {
847 int dropped;
848 BUG_ON(first_frag == -1);
849
850 dropped = macb_rx_frame(bp, first_frag, tail);
851 first_frag = -1;
852 if (!dropped) {
853 received++;
854 budget--;
855 }
856 }
857 }
858
859 if (first_frag != -1)
860 bp->rx_tail = first_frag;
861 else
862 bp->rx_tail = tail;
863
864 return received;
865}
866
bea3348e 867static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 868{
bea3348e 869 struct macb *bp = container_of(napi, struct macb, napi);
bea3348e 870 int work_done;
89e5785f
HS		 871 u32 status;
872
873 status = macb_readl(bp, RSR);
874 macb_writel(bp, RSR, status);
875
bea3348e 876 work_done = 0;
89e5785f 877
a268adb1 878 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
c220f8cd 879 (unsigned long)status, budget);
89e5785f 880
4df95131 881 work_done = bp->macbgem_ops.mog_rx(bp, budget);
b336369c 882 if (work_done < budget) {
288379f0 883 napi_complete(napi);
89e5785f 884
8770e91a
NF		 885 /* Packets received while interrupts were disabled */
886 status = macb_readl(bp, RSR);
504ad98d 887 if (status) {
02f7a34f
SB		 888 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
889 macb_writel(bp, ISR, MACB_BIT(RCOMP));
8770e91a 890 napi_reschedule(napi);
02f7a34f
SB		 891 } else {
892 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
893 }
b336369c 894 }
89e5785f
HS		 895
896 /* TODO: Handle errors */
897
bea3348e 898 return work_done;
89e5785f
HS		 899}
900
901static irqreturn_t macb_interrupt(int irq, void *dev_id)
902{
903 struct net_device *dev = dev_id;
904 struct macb *bp = netdev_priv(dev);
905 u32 status;
906
907 status = macb_readl(bp, ISR);
908
909 if (unlikely(!status))
910 return IRQ_NONE;
911
912 spin_lock(&bp->lock);
913
914 while (status) {
89e5785f
HS		 915 /* close possible race with dev_close */
916 if (unlikely(!netif_running(dev))) {
95ebcea6 917 macb_writel(bp, IDR, -1);
89e5785f
HS		 918 break;
919 }
920
a268adb1
HS		 921 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
922
89e5785f 923 if (status & MACB_RX_INT_FLAGS) {
b336369c
JH		 924 /*
925 * There's no point taking any more interrupts
926 * until we have processed the buffers. The
927 * scheduling call may fail if the poll routine
928 * is already scheduled, so disable interrupts
929 * now.
930 */
931 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
581df9e1
NF		 932 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
933 macb_writel(bp, ISR, MACB_BIT(RCOMP));
b336369c 934
288379f0 935 if (napi_schedule_prep(&bp->napi)) {
a268adb1 936 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
288379f0 937 __napi_schedule(&bp->napi);
89e5785f
HS		 938 }
939 }
940
e86cd53a
NF		 941 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
942 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
943 schedule_work(&bp->tx_error_task);
6a027b70
SB		 944
945 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
946 macb_writel(bp, ISR, MACB_TX_ERR_FLAGS);
947
e86cd53a
NF		 948 break;
949 }
950
951 if (status & MACB_BIT(TCOMP))
952 macb_tx_interrupt(bp);
89e5785f
HS		 953
954 /*
955 * Link change detection isn't possible with RMII, so we'll
956 * add that if/when we get our hands on a full-blown MII PHY.
957 */
958
b19f7f71
AS		 959 if (status & MACB_BIT(ISR_ROVR)) {
960 /* We missed at least one packet */
f75ba50b
JI		 961 if (macb_is_gem(bp))
962 bp->hw_stats.gem.rx_overruns++;
963 else
964 bp->hw_stats.macb.rx_overruns++;
6a027b70
SB		 965
966 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
967 macb_writel(bp, ISR, MACB_BIT(ISR_ROVR));
b19f7f71
AS		 968 }
969
89e5785f
HS		 970 if (status & MACB_BIT(HRESP)) {
971 /*
c220f8cd
JI		 972 * TODO: Reset the hardware, and maybe move the
973 * netdev_err to a lower-priority context as well
974 * (work queue?)
89e5785f 975 */
c220f8cd 976 netdev_err(dev, "DMA bus error: HRESP not OK\n");
6a027b70
SB		 977
978 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
979 macb_writel(bp, ISR, MACB_BIT(HRESP));
89e5785f
HS		 980 }
981
982 status = macb_readl(bp, ISR);
983 }
984
985 spin_unlock(&bp->lock);
986
987 return IRQ_HANDLED;
988}
989
6e8cf5c0
TP		 990#ifdef CONFIG_NET_POLL_CONTROLLER
991/*
992 * Polling receive - used by netconsole and other diagnostic tools
993 * to allow network i/o with interrupts disabled.
994 */
995static void macb_poll_controller(struct net_device *dev)
996{
997 unsigned long flags;
998
999 local_irq_save(flags);
1000 macb_interrupt(dev->irq, dev);
1001 local_irq_restore(flags);
1002}
1003#endif
1004
89e5785f
HS		 1005static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1006{
1007 struct macb *bp = netdev_priv(dev);
1008 dma_addr_t mapping;
1009 unsigned int len, entry;
55054a16
HS		 1010 struct macb_dma_desc *desc;
1011 struct macb_tx_skb *tx_skb;
89e5785f 1012 u32 ctrl;
4871953c 1013 unsigned long flags;
89e5785f 1014
a268adb1
HS		 1015#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1016 netdev_vdbg(bp->dev,
c220f8cd
JI		 1017 "start_xmit: len %u head %p data %p tail %p end %p\n",
1018 skb->len, skb->head, skb->data,
1019 skb_tail_pointer(skb), skb_end_pointer(skb));
1020 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1021 skb->data, 16, true);
89e5785f
HS		 1022#endif
1023
1024 len = skb->len;
4871953c 1025 spin_lock_irqsave(&bp->lock, flags);
89e5785f
HS		 1026
1027 /* This is a hard error, log it. */
909a8583 1028 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
89e5785f 1029 netif_stop_queue(dev);
4871953c 1030 spin_unlock_irqrestore(&bp->lock, flags);
c220f8cd
JI		 1031 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
1032 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1033 bp->tx_head, bp->tx_tail);
5b548140 1034 return NETDEV_TX_BUSY;
89e5785f
HS		 1035 }
1036
55054a16 1037 entry = macb_tx_ring_wrap(bp->tx_head);
a268adb1 1038 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
89e5785f
HS		 1039 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1040 len, DMA_TO_DEVICE);
92030908 1041 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
c88b5b6a 1042 dev_kfree_skb_any(skb);
92030908
SB		 1043 goto unlock;
1044 }
55054a16 1045
92030908 1046 bp->tx_head++;
55054a16
HS		 1047 tx_skb = &bp->tx_skb[entry];
1048 tx_skb->skb = skb;
1049 tx_skb->mapping = mapping;
a268adb1 1050 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
c220f8cd 1051 skb->data, (unsigned long)mapping);
89e5785f
HS		 1052
1053 ctrl = MACB_BF(TX_FRMLEN, len);
1054 ctrl |= MACB_BIT(TX_LAST);
1055 if (entry == (TX_RING_SIZE - 1))
1056 ctrl |= MACB_BIT(TX_WRAP);
1057
55054a16
HS		 1058 desc = &bp->tx_ring[entry];
1059 desc->addr = mapping;
1060 desc->ctrl = ctrl;
03dbe05f
HS		 1061
1062 /* Make newly initialized descriptor visible to hardware */
89e5785f
HS		 1063 wmb();
1064
e072092f
RC		 1065 skb_tx_timestamp(skb);
1066
89e5785f
HS		 1067 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1068
909a8583 1069 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
89e5785f
HS		 1070 netif_stop_queue(dev);
1071
92030908 1072unlock:
4871953c 1073 spin_unlock_irqrestore(&bp->lock, flags);
89e5785f 1074
6ed10654 1075 return NETDEV_TX_OK;
89e5785f
HS		 1076}
1077
4df95131 1078static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1b44791a
NF		 1079{
1080 if (!macb_is_gem(bp)) {
1081 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1082 } else {
4df95131 1083 bp->rx_buffer_size = size;
1b44791a 1084
1b44791a 1085 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
4df95131
NF		 1086 netdev_dbg(bp->dev,
1087 "RX buffer must be multiple of %d bytes, expanding\n",
1b44791a
NF		 1088 RX_BUFFER_MULTIPLE);
1089 bp->rx_buffer_size =
4df95131 1090 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1b44791a 1091 }
1b44791a 1092 }
4df95131
NF		 1093
1094 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1095 bp->dev->mtu, bp->rx_buffer_size);
1b44791a
NF		 1096}
1097
4df95131
NF		 1098static void gem_free_rx_buffers(struct macb *bp)
1099{
1100 struct sk_buff *skb;
1101 struct macb_dma_desc *desc;
1102 dma_addr_t addr;
1103 int i;
1104
1105 if (!bp->rx_skbuff)
1106 return;
1107
1108 for (i = 0; i < RX_RING_SIZE; i++) {
1109 skb = bp->rx_skbuff[i];
1110
1111 if (skb == NULL)
1112 continue;
1113
1114 desc = &bp->rx_ring[i];
1115 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
ccd6d0a9 1116 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
4df95131
NF		 1117 DMA_FROM_DEVICE);
1118 dev_kfree_skb_any(skb);
1119 skb = NULL;
1120 }
1121
1122 kfree(bp->rx_skbuff);
1123 bp->rx_skbuff = NULL;
1124}
1125
1126static void macb_free_rx_buffers(struct macb *bp)
1127{
1128 if (bp->rx_buffers) {
1129 dma_free_coherent(&bp->pdev->dev,
1130 RX_RING_SIZE * bp->rx_buffer_size,
1131 bp->rx_buffers, bp->rx_buffers_dma);
1132 bp->rx_buffers = NULL;
1133 }
1134}
1b44791a 1135
89e5785f
HS		 1136static void macb_free_consistent(struct macb *bp)
1137{
1138 if (bp->tx_skb) {
1139 kfree(bp->tx_skb);
1140 bp->tx_skb = NULL;
1141 }
4df95131 1142 bp->macbgem_ops.mog_free_rx_buffers(bp);
89e5785f
HS		 1143 if (bp->rx_ring) {
1144 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1145 bp->rx_ring, bp->rx_ring_dma);
1146 bp->rx_ring = NULL;
1147 }
1148 if (bp->tx_ring) {
1149 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1150 bp->tx_ring, bp->tx_ring_dma);
1151 bp->tx_ring = NULL;
1152 }
4df95131
NF		 1153}
1154
1155static int gem_alloc_rx_buffers(struct macb *bp)
1156{
1157 int size;
1158
1159 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1160 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1161 if (!bp->rx_skbuff)
1162 return -ENOMEM;
1163 else
1164 netdev_dbg(bp->dev,
1165 "Allocated %d RX struct sk_buff entries at %p\n",
1166 RX_RING_SIZE, bp->rx_skbuff);
1167 return 0;
1168}
1169
1170static int macb_alloc_rx_buffers(struct macb *bp)
1171{
1172 int size;
1173
1174 size = RX_RING_SIZE * bp->rx_buffer_size;
1175 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1176 &bp->rx_buffers_dma, GFP_KERNEL);
1177 if (!bp->rx_buffers)
1178 return -ENOMEM;
1179 else
1180 netdev_dbg(bp->dev,
1181 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1182 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1183 return 0;
89e5785f
HS		 1184}
1185
1186static int macb_alloc_consistent(struct macb *bp)
1187{
1188 int size;
1189
55054a16 1190 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
89e5785f
HS		 1191 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1192 if (!bp->tx_skb)
1193 goto out_err;
1194
1195 size = RX_RING_BYTES;
1196 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1197 &bp->rx_ring_dma, GFP_KERNEL);
1198 if (!bp->rx_ring)
1199 goto out_err;
c220f8cd
JI		 1200 netdev_dbg(bp->dev,
1201 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1202 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
89e5785f
HS		 1203
1204 size = TX_RING_BYTES;
1205 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1206 &bp->tx_ring_dma, GFP_KERNEL);
1207 if (!bp->tx_ring)
1208 goto out_err;
c220f8cd
JI		 1209 netdev_dbg(bp->dev,
1210 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1211 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
89e5785f 1212
4df95131 1213 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
89e5785f 1214 goto out_err;
89e5785f
HS		 1215
1216 return 0;
1217
1218out_err:
1219 macb_free_consistent(bp);
1220 return -ENOMEM;
1221}
1222
4df95131
NF		 1223static void gem_init_rings(struct macb *bp)
1224{
1225 int i;
1226
1227 for (i = 0; i < TX_RING_SIZE; i++) {
1228 bp->tx_ring[i].addr = 0;
1229 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1230 }
1231 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1232
1233 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1234
1235 gem_rx_refill(bp);
1236}
1237
89e5785f
HS		 1238static void macb_init_rings(struct macb *bp)
1239{
1240 int i;
1241 dma_addr_t addr;
1242
1243 addr = bp->rx_buffers_dma;
1244 for (i = 0; i < RX_RING_SIZE; i++) {
1245 bp->rx_ring[i].addr = addr;
1246 bp->rx_ring[i].ctrl = 0;
1b44791a 1247 addr += bp->rx_buffer_size;
89e5785f
HS		 1248 }
1249 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1250
1251 for (i = 0; i < TX_RING_SIZE; i++) {
1252 bp->tx_ring[i].addr = 0;
1253 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1254 }
1255 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1256
1257 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1258}
1259
1260static void macb_reset_hw(struct macb *bp)
1261{
89e5785f
HS		 1262 /*
1263 * Disable RX and TX (XXX: Should we halt the transmission
1264 * more gracefully?)
1265 */
1266 macb_writel(bp, NCR, 0);
1267
1268 /* Clear the stats registers (XXX: Update stats first?) */
1269 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1270
1271 /* Clear all status flags */
95ebcea6
JE		 1272 macb_writel(bp, TSR, -1);
1273 macb_writel(bp, RSR, -1);
89e5785f
HS		 1274
1275 /* Disable all interrupts */
95ebcea6 1276 macb_writel(bp, IDR, -1);
89e5785f
HS		 1277 macb_readl(bp, ISR);
1278}
1279
70c9f3d4
JI		 1280static u32 gem_mdc_clk_div(struct macb *bp)
1281{
1282 u32 config;
1283 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1284
1285 if (pclk_hz <= 20000000)
1286 config = GEM_BF(CLK, GEM_CLK_DIV8);
1287 else if (pclk_hz <= 40000000)
1288 config = GEM_BF(CLK, GEM_CLK_DIV16);
1289 else if (pclk_hz <= 80000000)
1290 config = GEM_BF(CLK, GEM_CLK_DIV32);
1291 else if (pclk_hz <= 120000000)
1292 config = GEM_BF(CLK, GEM_CLK_DIV48);
1293 else if (pclk_hz <= 160000000)
1294 config = GEM_BF(CLK, GEM_CLK_DIV64);
1295 else
1296 config = GEM_BF(CLK, GEM_CLK_DIV96);
1297
1298 return config;
1299}
1300
1301static u32 macb_mdc_clk_div(struct macb *bp)
1302{
1303 u32 config;
1304 unsigned long pclk_hz;
1305
1306 if (macb_is_gem(bp))
1307 return gem_mdc_clk_div(bp);
1308
1309 pclk_hz = clk_get_rate(bp->pclk);
1310 if (pclk_hz <= 20000000)
1311 config = MACB_BF(CLK, MACB_CLK_DIV8);
1312 else if (pclk_hz <= 40000000)
1313 config = MACB_BF(CLK, MACB_CLK_DIV16);
1314 else if (pclk_hz <= 80000000)
1315 config = MACB_BF(CLK, MACB_CLK_DIV32);
1316 else
1317 config = MACB_BF(CLK, MACB_CLK_DIV64);
1318
1319 return config;
1320}
1321
757a03c6
JI		 1322/*
1323 * Get the DMA bus width field of the network configuration register that we
1324 * should program. We find the width from decoding the design configuration
1325 * register to find the maximum supported data bus width.
1326 */
1327static u32 macb_dbw(struct macb *bp)
1328{
1329 if (!macb_is_gem(bp))
1330 return 0;
1331
1332 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1333 case 4:
1334 return GEM_BF(DBW, GEM_DBW128);
1335 case 2:
1336 return GEM_BF(DBW, GEM_DBW64);
1337 case 1:
1338 default:
1339 return GEM_BF(DBW, GEM_DBW32);
1340 }
1341}
1342
0116da4f 1343/*
b3e3bd71
NF		 1344 * Configure the receive DMA engine
1345 * - use the correct receive buffer size
e175587f 1346 * - set best burst length for DMA operations
b3e3bd71
NF		 1347 * (if not supported by FIFO, it will fallback to default)
1348 * - set both rx/tx packet buffers to full memory size
1349 * These are configurable parameters for GEM.
0116da4f
JI		 1350 */
1351static void macb_configure_dma(struct macb *bp)
1352{
1353 u32 dmacfg;
1354
1355 if (macb_is_gem(bp)) {
1356 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1b44791a 1357 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
e175587f
NF		 1358 if (bp->dma_burst_length)
1359 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
b3e3bd71 1360 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
a1ae385d 1361 dmacfg &= ~GEM_BIT(ENDIA);
e175587f
NF		 1362 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1363 dmacfg);
0116da4f
JI		 1364 gem_writel(bp, DMACFG, dmacfg);
1365 }
1366}
1367
89e5785f
HS		 1368static void macb_init_hw(struct macb *bp)
1369{
1370 u32 config;
1371
1372 macb_reset_hw(bp);
314bccc4 1373 macb_set_hwaddr(bp);
89e5785f 1374
70c9f3d4 1375 config = macb_mdc_clk_div(bp);
29bc2e1e 1376 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
89e5785f
HS		 1377 config |= MACB_BIT(PAE); /* PAuse Enable */
1378 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
8dd4bd00 1379 config |= MACB_BIT(BIG); /* Receive oversized frames */
89e5785f
HS		 1380 if (bp->dev->flags & IFF_PROMISC)
1381 config |= MACB_BIT(CAF); /* Copy All Frames */
1382 if (!(bp->dev->flags & IFF_BROADCAST))
1383 config |= MACB_BIT(NBC); /* No BroadCast */
757a03c6 1384 config |= macb_dbw(bp);
89e5785f 1385 macb_writel(bp, NCFGR, config);
26cdfb49
VD		 1386 bp->speed = SPEED_10;
1387 bp->duplex = DUPLEX_HALF;
89e5785f 1388
0116da4f
JI		 1389 macb_configure_dma(bp);
1390
89e5785f
HS		 1391 /* Initialize TX and RX buffers */
1392 macb_writel(bp, RBQP, bp->rx_ring_dma);
1393 macb_writel(bp, TBQP, bp->tx_ring_dma);
1394
1395 /* Enable TX and RX */
6c36a707 1396 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS		 1397
1398 /* Enable interrupts */
e86cd53a
NF		 1399 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1400 | MACB_TX_INT_FLAGS
89e5785f 1401 | MACB_BIT(HRESP)));
89e5785f 1402
89e5785f
HS		 1403}
1404
446ebd01
PV		 1405/*
1406 * The hash address register is 64 bits long and takes up two
1407 * locations in the memory map. The least significant bits are stored
1408 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1409 *
1410 * The unicast hash enable and the multicast hash enable bits in the
1411 * network configuration register enable the reception of hash matched
1412 * frames. The destination address is reduced to a 6 bit index into
1413 * the 64 bit hash register using the following hash function. The
1414 * hash function is an exclusive or of every sixth bit of the
1415 * destination address.
1416 *
1417 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1418 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1419 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1420 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1421 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1422 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1423 *
1424 * da[0] represents the least significant bit of the first byte
1425 * received, that is, the multicast/unicast indicator, and da[47]
1426 * represents the most significant bit of the last byte received. If
1427 * the hash index, hi[n], points to a bit that is set in the hash
1428 * register then the frame will be matched according to whether the
1429 * frame is multicast or unicast. A multicast match will be signalled
1430 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1431 * index points to a bit set in the hash register. A unicast match
1432 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1433 * and the hash index points to a bit set in the hash register. To
1434 * receive all multicast frames, the hash register should be set with
1435 * all ones and the multicast hash enable bit should be set in the
1436 * network configuration register.
1437 */
1438
1439static inline int hash_bit_value(int bitnr, __u8 *addr)
1440{
1441 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1442 return 1;
1443 return 0;
1444}
1445
1446/*
1447 * Return the hash index value for the specified address.
1448 */
1449static int hash_get_index(__u8 *addr)
1450{
1451 int i, j, bitval;
1452 int hash_index = 0;
1453
1454 for (j = 0; j < 6; j++) {
1455 for (i = 0, bitval = 0; i < 8; i++)
1456 bitval ^= hash_bit_value(i*6 + j, addr);
1457
1458 hash_index |= (bitval << j);
1459 }
1460
1461 return hash_index;
1462}
1463
1464/*
1465 * Add multicast addresses to the internal multicast-hash table.
1466 */
1467static void macb_sethashtable(struct net_device *dev)
1468{
22bedad3 1469 struct netdev_hw_addr *ha;
446ebd01 1470 unsigned long mc_filter[2];
f9dcbcc9 1471 unsigned int bitnr;
446ebd01
PV		 1472 struct macb *bp = netdev_priv(dev);
1473
1474 mc_filter[0] = mc_filter[1] = 0;
1475
22bedad3
JP		 1476 netdev_for_each_mc_addr(ha, dev) {
1477 bitnr = hash_get_index(ha->addr);
446ebd01
PV		 1478 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1479 }
1480
f75ba50b
JI		 1481 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1482 macb_or_gem_writel(bp, HRT, mc_filter[1]);
446ebd01
PV		 1483}
1484
1485/*
1486 * Enable/Disable promiscuous and multicast modes.
1487 */
e0da1f14 1488void macb_set_rx_mode(struct net_device *dev)
446ebd01
PV		 1489{
1490 unsigned long cfg;
1491 struct macb *bp = netdev_priv(dev);
1492
1493 cfg = macb_readl(bp, NCFGR);
1494
1495 if (dev->flags & IFF_PROMISC)
1496 /* Enable promiscuous mode */
1497 cfg |= MACB_BIT(CAF);
1498 else if (dev->flags & (~IFF_PROMISC))
1499 /* Disable promiscuous mode */
1500 cfg &= ~MACB_BIT(CAF);
1501
1502 if (dev->flags & IFF_ALLMULTI) {
1503 /* Enable all multicast mode */
f75ba50b
JI		 1504 macb_or_gem_writel(bp, HRB, -1);
1505 macb_or_gem_writel(bp, HRT, -1);
446ebd01 1506 cfg |= MACB_BIT(NCFGR_MTI);
4cd24eaf 1507 } else if (!netdev_mc_empty(dev)) {
446ebd01
PV		 1508 /* Enable specific multicasts */
1509 macb_sethashtable(dev);
1510 cfg |= MACB_BIT(NCFGR_MTI);
1511 } else if (dev->flags & (~IFF_ALLMULTI)) {
1512 /* Disable all multicast mode */
f75ba50b
JI		 1513 macb_or_gem_writel(bp, HRB, 0);
1514 macb_or_gem_writel(bp, HRT, 0);
446ebd01
PV		 1515 cfg &= ~MACB_BIT(NCFGR_MTI);
1516 }
1517
1518 macb_writel(bp, NCFGR, cfg);
1519}
e0da1f14 1520EXPORT_SYMBOL_GPL(macb_set_rx_mode);
446ebd01 1521
89e5785f
HS		 1522static int macb_open(struct net_device *dev)
1523{
1524 struct macb *bp = netdev_priv(dev);
4df95131 1525 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
89e5785f
HS		 1526 int err;
1527
c220f8cd 1528 netdev_dbg(bp->dev, "open\n");
89e5785f 1529
03fc4721
NF		 1530 /* carrier starts down */
1531 netif_carrier_off(dev);
1532
6c36a707
R		 1533 /* if the phy is not yet register, retry later*/
1534 if (!bp->phy_dev)
1535 return -EAGAIN;
1b44791a
NF		 1536
1537 /* RX buffers initialization */
4df95131 1538 macb_init_rx_buffer_size(bp, bufsz);
6c36a707 1539
89e5785f
HS		 1540 err = macb_alloc_consistent(bp);
1541 if (err) {
c220f8cd
JI		 1542 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1543 err);
89e5785f
HS		 1544 return err;
1545 }
1546
bea3348e
SH		 1547 napi_enable(&bp->napi);
1548
4df95131 1549 bp->macbgem_ops.mog_init_rings(bp);
89e5785f 1550 macb_init_hw(bp);
89e5785f 1551
6c36a707
R		 1552 /* schedule a link state check */
1553 phy_start(bp->phy_dev);
89e5785f 1554
6c36a707 1555 netif_start_queue(dev);
89e5785f
HS		 1556
1557 return 0;
1558}
1559
1560static int macb_close(struct net_device *dev)
1561{
1562 struct macb *bp = netdev_priv(dev);
1563 unsigned long flags;
1564
89e5785f 1565 netif_stop_queue(dev);
bea3348e 1566 napi_disable(&bp->napi);
89e5785f 1567
6c36a707
R		 1568 if (bp->phy_dev)
1569 phy_stop(bp->phy_dev);
1570
89e5785f
HS		 1571 spin_lock_irqsave(&bp->lock, flags);
1572 macb_reset_hw(bp);
1573 netif_carrier_off(dev);
1574 spin_unlock_irqrestore(&bp->lock, flags);
1575
1576 macb_free_consistent(bp);
1577
1578 return 0;
1579}
1580
a494ed8e
JI		 1581static void gem_update_stats(struct macb *bp)
1582{
1583 u32 __iomem *reg = bp->regs + GEM_OTX;
1584 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1585 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1586
1587 for (; p < end; p++, reg++)
1588 *p += __raw_readl(reg);
1589}
1590
1591static struct net_device_stats *gem_get_stats(struct macb *bp)
1592{
1593 struct gem_stats *hwstat = &bp->hw_stats.gem;
1594 struct net_device_stats *nstat = &bp->stats;
1595
1596 gem_update_stats(bp);
1597
1598 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1599 hwstat->rx_alignment_errors +
1600 hwstat->rx_resource_errors +
1601 hwstat->rx_overruns +
1602 hwstat->rx_oversize_frames +
1603 hwstat->rx_jabbers +
1604 hwstat->rx_undersized_frames +
1605 hwstat->rx_length_field_frame_errors);
1606 nstat->tx_errors = (hwstat->tx_late_collisions +
1607 hwstat->tx_excessive_collisions +
1608 hwstat->tx_underrun +
1609 hwstat->tx_carrier_sense_errors);
1610 nstat->multicast = hwstat->rx_multicast_frames;
1611 nstat->collisions = (hwstat->tx_single_collision_frames +
1612 hwstat->tx_multiple_collision_frames +
1613 hwstat->tx_excessive_collisions);
1614 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1615 hwstat->rx_jabbers +
1616 hwstat->rx_undersized_frames +
1617 hwstat->rx_length_field_frame_errors);
1618 nstat->rx_over_errors = hwstat->rx_resource_errors;
1619 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1620 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1621 nstat->rx_fifo_errors = hwstat->rx_overruns;
1622 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1623 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1624 nstat->tx_fifo_errors = hwstat->tx_underrun;
1625
1626 return nstat;
1627}
1628
2ea32eed 1629struct net_device_stats *macb_get_stats(struct net_device *dev)
89e5785f
HS		 1630{
1631 struct macb *bp = netdev_priv(dev);
1632 struct net_device_stats *nstat = &bp->stats;
a494ed8e
JI		 1633 struct macb_stats *hwstat = &bp->hw_stats.macb;
1634
1635 if (macb_is_gem(bp))
1636 return gem_get_stats(bp);
89e5785f 1637
6c36a707
R		 1638 /* read stats from hardware */
1639 macb_update_stats(bp);
1640
89e5785f
HS		 1641 /* Convert HW stats into netdevice stats */
1642 nstat->rx_errors = (hwstat->rx_fcs_errors +
1643 hwstat->rx_align_errors +
1644 hwstat->rx_resource_errors +
1645 hwstat->rx_overruns +
1646 hwstat->rx_oversize_pkts +
1647 hwstat->rx_jabbers +
1648 hwstat->rx_undersize_pkts +
1649 hwstat->sqe_test_errors +
1650 hwstat->rx_length_mismatch);
1651 nstat->tx_errors = (hwstat->tx_late_cols +
1652 hwstat->tx_excessive_cols +
1653 hwstat->tx_underruns +
1654 hwstat->tx_carrier_errors);
1655 nstat->collisions = (hwstat->tx_single_cols +
1656 hwstat->tx_multiple_cols +
1657 hwstat->tx_excessive_cols);
1658 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1659 hwstat->rx_jabbers +
1660 hwstat->rx_undersize_pkts +
1661 hwstat->rx_length_mismatch);
b19f7f71
AS		 1662 nstat->rx_over_errors = hwstat->rx_resource_errors +
1663 hwstat->rx_overruns;
89e5785f
HS		 1664 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1665 nstat->rx_frame_errors = hwstat->rx_align_errors;
1666 nstat->rx_fifo_errors = hwstat->rx_overruns;
1667 /* XXX: What does "missed" mean? */
1668 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1669 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1670 nstat->tx_fifo_errors = hwstat->tx_underruns;
1671 /* Don't know about heartbeat or window errors... */
1672
1673 return nstat;
1674}
2ea32eed 1675EXPORT_SYMBOL_GPL(macb_get_stats);
89e5785f
HS		 1676
1677static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1678{
1679 struct macb *bp = netdev_priv(dev);
6c36a707
R		 1680 struct phy_device *phydev = bp->phy_dev;
1681
1682 if (!phydev)
1683 return -ENODEV;
89e5785f 1684
6c36a707 1685 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS		 1686}
1687
1688static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1689{
1690 struct macb *bp = netdev_priv(dev);
6c36a707 1691 struct phy_device *phydev = bp->phy_dev;
89e5785f 1692
6c36a707
R		 1693 if (!phydev)
1694 return -ENODEV;
1695
1696 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS		 1697}
1698
d1d1b53d
NF		 1699static int macb_get_regs_len(struct net_device *netdev)
1700{
1701 return MACB_GREGS_NBR * sizeof(u32);
1702}
1703
1704static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1705 void *p)
1706{
1707 struct macb *bp = netdev_priv(dev);
1708 unsigned int tail, head;
1709 u32 *regs_buff = p;
1710
1711 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1712 | MACB_GREGS_VERSION;
1713
1714 tail = macb_tx_ring_wrap(bp->tx_tail);
1715 head = macb_tx_ring_wrap(bp->tx_head);
1716
1717 regs_buff[0] = macb_readl(bp, NCR);
1718 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1719 regs_buff[2] = macb_readl(bp, NSR);
1720 regs_buff[3] = macb_readl(bp, TSR);
1721 regs_buff[4] = macb_readl(bp, RBQP);
1722 regs_buff[5] = macb_readl(bp, TBQP);
1723 regs_buff[6] = macb_readl(bp, RSR);
1724 regs_buff[7] = macb_readl(bp, IMR);
1725
1726 regs_buff[8] = tail;
1727 regs_buff[9] = head;
1728 regs_buff[10] = macb_tx_dma(bp, tail);
1729 regs_buff[11] = macb_tx_dma(bp, head);
1730
1731 if (macb_is_gem(bp)) {
1732 regs_buff[12] = gem_readl(bp, USRIO);
1733 regs_buff[13] = gem_readl(bp, DMACFG);
1734 }
1735}
1736
0005f541 1737const struct ethtool_ops macb_ethtool_ops = {
89e5785f
HS		 1738 .get_settings = macb_get_settings,
1739 .set_settings = macb_set_settings,
d1d1b53d
NF		 1740 .get_regs_len = macb_get_regs_len,
1741 .get_regs = macb_get_regs,
89e5785f 1742 .get_link = ethtool_op_get_link,
17f393e8 1743 .get_ts_info = ethtool_op_get_ts_info,
89e5785f 1744};
0005f541 1745EXPORT_SYMBOL_GPL(macb_ethtool_ops);
89e5785f 1746
0005f541 1747int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
89e5785f
HS		 1748{
1749 struct macb *bp = netdev_priv(dev);
6c36a707 1750 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS		 1751
1752 if (!netif_running(dev))
1753 return -EINVAL;
1754
6c36a707
R		 1755 if (!phydev)
1756 return -ENODEV;
89e5785f 1757
28b04113 1758 return phy_mii_ioctl(phydev, rq, cmd);
89e5785f 1759}
0005f541 1760EXPORT_SYMBOL_GPL(macb_ioctl);
89e5785f 1761
5f1fa992
AB		 1762static const struct net_device_ops macb_netdev_ops = {
1763 .ndo_open = macb_open,
1764 .ndo_stop = macb_close,
1765 .ndo_start_xmit = macb_start_xmit,
afc4b13d 1766 .ndo_set_rx_mode = macb_set_rx_mode,
5f1fa992
AB		 1767 .ndo_get_stats = macb_get_stats,
1768 .ndo_do_ioctl = macb_ioctl,
1769 .ndo_validate_addr = eth_validate_addr,
1770 .ndo_change_mtu = eth_change_mtu,
1771 .ndo_set_mac_address = eth_mac_addr,
6e8cf5c0
TP		 1772#ifdef CONFIG_NET_POLL_CONTROLLER
1773 .ndo_poll_controller = macb_poll_controller,
1774#endif
5f1fa992
AB		 1775};
1776
fb97a846 1777#if defined(CONFIG_OF)
e175587f
NF		 1778static struct macb_config pc302gem_config = {
1779 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE,
1780 .dma_burst_length = 16,
1781};
1782
fb97a846
JCPV		 1783static const struct of_device_id macb_dt_ids[] = {
1784 { .compatible = "cdns,at32ap7000-macb" },
1785 { .compatible = "cdns,at91sam9260-macb" },
1786 { .compatible = "cdns,macb" },
e175587f
NF		 1787 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
1788 { .compatible = "cdns,gem", .data = &pc302gem_config },
fb97a846
JCPV		 1789 { /* sentinel */ }
1790};
fb97a846 1791MODULE_DEVICE_TABLE(of, macb_dt_ids);
fb97a846
JCPV		 1792#endif
1793
e175587f
NF		 1794/*
1795 * Configure peripheral capacities according to device tree
1796 * and integration options used
1797 */
1798static void macb_configure_caps(struct macb *bp)
1799{
1800 u32 dcfg;
1801 const struct of_device_id *match;
1802 const struct macb_config *config;
1803
1804 if (bp->pdev->dev.of_node) {
1805 match = of_match_node(macb_dt_ids, bp->pdev->dev.of_node);
1806 if (match && match->data) {
1807 config = (const struct macb_config *)match->data;
1808
1809 bp->caps = config->caps;
1810 /*
1811 * As we have access to the matching node, configure
1812 * DMA burst length as well
1813 */
1814 bp->dma_burst_length = config->dma_burst_length;
1815 }
1816 }
1817
1818 if (MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2)
1819 bp->caps |= MACB_CAPS_MACB_IS_GEM;
1820
1821 if (macb_is_gem(bp)) {
1822 dcfg = gem_readl(bp, DCFG1);
1823 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
1824 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
1825 dcfg = gem_readl(bp, DCFG2);
1826 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
1827 bp->caps |= MACB_CAPS_FIFO_MODE;
1828 }
1829
1830 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
1831}
1832
06c3fd6a 1833static int __init macb_probe(struct platform_device *pdev)
89e5785f 1834{
84e0cdb0 1835 struct macb_platform_data *pdata;
89e5785f
HS		 1836 struct resource *regs;
1837 struct net_device *dev;
1838 struct macb *bp;
6c36a707 1839 struct phy_device *phydev;
89e5785f
HS		 1840 u32 config;
1841 int err = -ENXIO;
8ef29f8a 1842 struct pinctrl *pinctrl;
50907043 1843 const char *mac;
89e5785f
HS		 1844
1845 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1846 if (!regs) {
1847 dev_err(&pdev->dev, "no mmio resource defined\n");
1848 goto err_out;
1849 }
1850
8ef29f8a
JCPV		 1851 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1852 if (IS_ERR(pinctrl)) {
1853 err = PTR_ERR(pinctrl);
1854 if (err == -EPROBE_DEFER)
1855 goto err_out;
1856
1857 dev_warn(&pdev->dev, "No pinctrl provided\n");
1858 }
1859
89e5785f
HS		 1860 err = -ENOMEM;
1861 dev = alloc_etherdev(sizeof(*bp));
41de8d4c 1862 if (!dev)
89e5785f 1863 goto err_out;
89e5785f 1864
89e5785f
HS		 1865 SET_NETDEV_DEV(dev, &pdev->dev);
1866
1867 /* TODO: Actually, we have some interesting features... */
1868 dev->features |= 0;
1869
1870 bp = netdev_priv(dev);
1871 bp->pdev = pdev;
1872 bp->dev = dev;
1873
1874 spin_lock_init(&bp->lock);
e86cd53a 1875 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
89e5785f 1876
b48e0bab 1877 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
0cc8674f 1878 if (IS_ERR(bp->pclk)) {
b48e0bab
SB		 1879 err = PTR_ERR(bp->pclk);
1880 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
0cc8674f
AV		 1881 goto err_out_free_dev;
1882 }
461845db 1883
b48e0bab 1884 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
89e5785f 1885 if (IS_ERR(bp->hclk)) {
b48e0bab
SB		 1886 err = PTR_ERR(bp->hclk);
1887 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
1888 goto err_out_free_dev;
1889 }
1890
e1824dfe
SB		 1891 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
1892
b48e0bab
SB		 1893 err = clk_prepare_enable(bp->pclk);
1894 if (err) {
1895 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
1896 goto err_out_free_dev;
1897 }
1898
1899 err = clk_prepare_enable(bp->hclk);
1900 if (err) {
1901 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
1902 goto err_out_disable_pclk;
89e5785f 1903 }
89e5785f 1904
e1824dfe
SB		 1905 if (!IS_ERR(bp->tx_clk)) {
1906 err = clk_prepare_enable(bp->tx_clk);
1907 if (err) {
1908 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n",
1909 err);
1910 goto err_out_disable_hclk;
1911 }
1912 }
1913
60fe716f 1914 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
89e5785f
HS		 1915 if (!bp->regs) {
1916 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1917 err = -ENOMEM;
1918 goto err_out_disable_clocks;
1919 }
1920
1921 dev->irq = platform_get_irq(pdev, 0);
0a4acf08
SB		 1922 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0,
1923 dev->name, dev);
89e5785f 1924 if (err) {
c220f8cd
JI		 1925 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1926 dev->irq, err);
60fe716f 1927 goto err_out_disable_clocks;
89e5785f
HS		 1928 }
1929
5f1fa992 1930 dev->netdev_ops = &macb_netdev_ops;
bea3348e 1931 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f
HS		 1932 dev->ethtool_ops = &macb_ethtool_ops;
1933
1934 dev->base_addr = regs->start;
1935
e175587f
NF		 1936 /* setup capacities */
1937 macb_configure_caps(bp);
1938
4df95131
NF		 1939 /* setup appropriated routines according to adapter type */
1940 if (macb_is_gem(bp)) {
1941 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
1942 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
1943 bp->macbgem_ops.mog_init_rings = gem_init_rings;
1944 bp->macbgem_ops.mog_rx = gem_rx;
1945 } else {
1946 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
1947 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
1948 bp->macbgem_ops.mog_init_rings = macb_init_rings;
1949 bp->macbgem_ops.mog_rx = macb_rx;
1950 }
1951
89e5785f 1952 /* Set MII management clock divider */
70c9f3d4 1953 config = macb_mdc_clk_div(bp);
757a03c6 1954 config |= macb_dbw(bp);
89e5785f
HS		 1955 macb_writel(bp, NCFGR, config);
1956
50907043
GR		 1957 mac = of_get_mac_address(pdev->dev.of_node);
1958 if (mac)
1959 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1960 else
fb97a846
JCPV		 1961 macb_get_hwaddr(bp);
1962
50907043 1963 err = of_get_phy_mode(pdev->dev.of_node);
fb97a846 1964 if (err < 0) {
c607a0d9 1965 pdata = dev_get_platdata(&pdev->dev);
fb97a846
JCPV		 1966 if (pdata && pdata->is_rmii)
1967 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1968 else
1969 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1970 } else {
1971 bp->phy_interface = err;
1972 }
6c36a707 1973
140b7552
PV		 1974 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1975 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1976 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
0cc8674f 1977#if defined(CONFIG_ARCH_AT91)
f75ba50b
JI		 1978 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1979 MACB_BIT(CLKEN)));
0cc8674f 1980#else
f75ba50b 1981 macb_or_gem_writel(bp, USRIO, 0);
0cc8674f 1982#endif
89e5785f 1983 else
0cc8674f 1984#if defined(CONFIG_ARCH_AT91)
f75ba50b 1985 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
0cc8674f 1986#else
f75ba50b 1987 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
0cc8674f 1988#endif
89e5785f 1989
89e5785f
HS		 1990 err = register_netdev(dev);
1991 if (err) {
1992 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
0a4acf08 1993 goto err_out_disable_clocks;
89e5785f
HS		 1994 }
1995
72ca820b
NF		 1996 err = macb_mii_init(bp);
1997 if (err)
6c36a707 1998 goto err_out_unregister_netdev;
89e5785f 1999
6c36a707 2000 platform_set_drvdata(pdev, dev);
89e5785f 2001
03fc4721
NF		 2002 netif_carrier_off(dev);
2003
f75ba50b
JI		 2004 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
2005 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
2006 dev->irq, dev->dev_addr);
89e5785f 2007
6c36a707 2008 phydev = bp->phy_dev;
c220f8cd
JI		 2009 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2010 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
6c36a707 2011
89e5785f
HS		 2012 return 0;
2013
6c36a707
R		 2014err_out_unregister_netdev:
2015 unregister_netdev(dev);
89e5785f 2016err_out_disable_clocks:
e1824dfe
SB		 2017 if (!IS_ERR(bp->tx_clk))
2018 clk_disable_unprepare(bp->tx_clk);
2019err_out_disable_hclk:
ace58010 2020 clk_disable_unprepare(bp->hclk);
b48e0bab 2021err_out_disable_pclk:
ace58010 2022 clk_disable_unprepare(bp->pclk);
89e5785f
HS		 2023err_out_free_dev:
2024 free_netdev(dev);
2025err_out:
89e5785f
HS		 2026 return err;
2027}
2028
06c3fd6a 2029static int __exit macb_remove(struct platform_device *pdev)
89e5785f
HS		 2030{
2031 struct net_device *dev;
2032 struct macb *bp;
2033
2034 dev = platform_get_drvdata(pdev);
2035
2036 if (dev) {
2037 bp = netdev_priv(dev);
84b7901f
AN		 2038 if (bp->phy_dev)
2039 phy_disconnect(bp->phy_dev);
298cf9be
LB		 2040 mdiobus_unregister(bp->mii_bus);
2041 kfree(bp->mii_bus->irq);
2042 mdiobus_free(bp->mii_bus);
89e5785f 2043 unregister_netdev(dev);
e1824dfe
SB		 2044 if (!IS_ERR(bp->tx_clk))
2045 clk_disable_unprepare(bp->tx_clk);
ace58010 2046 clk_disable_unprepare(bp->hclk);
ace58010 2047 clk_disable_unprepare(bp->pclk);
89e5785f 2048 free_netdev(dev);
89e5785f
HS		 2049 }
2050
2051 return 0;
2052}
2053
c1f598fd 2054#ifdef CONFIG_PM
0dfc3e18 2055static int macb_suspend(struct device *dev)
c1f598fd 2056{
0dfc3e18 2057 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS		 2058 struct net_device *netdev = platform_get_drvdata(pdev);
2059 struct macb *bp = netdev_priv(netdev);
2060
03fc4721 2061 netif_carrier_off(netdev);
c1f598fd
HS		 2062 netif_device_detach(netdev);
2063
e1824dfe
SB		 2064 if (!IS_ERR(bp->tx_clk))
2065 clk_disable_unprepare(bp->tx_clk);
ace58010
ST		 2066 clk_disable_unprepare(bp->hclk);
2067 clk_disable_unprepare(bp->pclk);
c1f598fd
HS		 2068
2069 return 0;
2070}
2071
0dfc3e18 2072static int macb_resume(struct device *dev)
c1f598fd 2073{
0dfc3e18 2074 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS		 2075 struct net_device *netdev = platform_get_drvdata(pdev);
2076 struct macb *bp = netdev_priv(netdev);
2077
ace58010
ST		 2078 clk_prepare_enable(bp->pclk);
2079 clk_prepare_enable(bp->hclk);
e1824dfe
SB		 2080 if (!IS_ERR(bp->tx_clk))
2081 clk_prepare_enable(bp->tx_clk);
c1f598fd
HS		 2082
2083 netif_device_attach(netdev);
2084
2085 return 0;
2086}
c1f598fd
HS		 2087#endif
2088
0dfc3e18
SB		 2089static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2090
89e5785f 2091static struct platform_driver macb_driver = {
06c3fd6a 2092 .remove = __exit_p(macb_remove),
89e5785f
HS		 2093 .driver = {
2094 .name = "macb",
72abb461 2095 .owner = THIS_MODULE,
fb97a846 2096 .of_match_table = of_match_ptr(macb_dt_ids),
0dfc3e18 2097 .pm = &macb_pm_ops,
89e5785f
HS		 2098 },
2099};
2100
b543a8d8 2101module_platform_driver_probe(macb_driver, macb_probe);
89e5785f
HS		 2102
2103MODULE_LICENSE("GPL");
f75ba50b 2104MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
e05503ef 2105MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
72abb461 2106MODULE_ALIAS("platform:macb");
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