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89e5785f HS |
1 | /* |
2 | * Atmel MACB Ethernet Controller driver | |
3 | * | |
4 | * Copyright (C) 2004-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #ifndef _MACB_H | |
11 | #define _MACB_H | |
12 | ||
fc182b85 | 13 | #include <linux/phy.h> |
ab91f0a9 RO |
14 | #include <linux/ptp_clock_kernel.h> |
15 | #include <linux/net_tstamp.h> | |
032dc41b | 16 | #include <linux/interrupt.h> |
fc182b85 | 17 | |
7b429614 RO |
18 | #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP) |
19 | #define MACB_EXT_DESC | |
20 | #endif | |
21 | ||
d1d1b53d | 22 | #define MACB_GREGS_NBR 16 |
7c39994f | 23 | #define MACB_GREGS_VERSION 2 |
02c958dd | 24 | #define MACB_MAX_QUEUES 8 |
d1d1b53d | 25 | |
89e5785f | 26 | /* MACB register offsets */ |
6f79eed8 XH |
27 | #define MACB_NCR 0x0000 /* Network Control */ |
28 | #define MACB_NCFGR 0x0004 /* Network Config */ | |
29 | #define MACB_NSR 0x0008 /* Network Status */ | |
30 | #define MACB_TAR 0x000c /* AT91RM9200 only */ | |
31 | #define MACB_TCR 0x0010 /* AT91RM9200 only */ | |
32 | #define MACB_TSR 0x0014 /* Transmit Status */ | |
33 | #define MACB_RBQP 0x0018 /* RX Q Base Address */ | |
34 | #define MACB_TBQP 0x001c /* TX Q Base Address */ | |
35 | #define MACB_RSR 0x0020 /* Receive Status */ | |
36 | #define MACB_ISR 0x0024 /* Interrupt Status */ | |
37 | #define MACB_IER 0x0028 /* Interrupt Enable */ | |
38 | #define MACB_IDR 0x002c /* Interrupt Disable */ | |
39 | #define MACB_IMR 0x0030 /* Interrupt Mask */ | |
40 | #define MACB_MAN 0x0034 /* PHY Maintenance */ | |
41 | #define MACB_PTR 0x0038 | |
42 | #define MACB_PFR 0x003c | |
43 | #define MACB_FTO 0x0040 | |
44 | #define MACB_SCF 0x0044 | |
45 | #define MACB_MCF 0x0048 | |
46 | #define MACB_FRO 0x004c | |
47 | #define MACB_FCSE 0x0050 | |
48 | #define MACB_ALE 0x0054 | |
49 | #define MACB_DTF 0x0058 | |
50 | #define MACB_LCOL 0x005c | |
51 | #define MACB_EXCOL 0x0060 | |
52 | #define MACB_TUND 0x0064 | |
53 | #define MACB_CSE 0x0068 | |
54 | #define MACB_RRE 0x006c | |
55 | #define MACB_ROVR 0x0070 | |
56 | #define MACB_RSE 0x0074 | |
57 | #define MACB_ELE 0x0078 | |
58 | #define MACB_RJA 0x007c | |
59 | #define MACB_USF 0x0080 | |
60 | #define MACB_STE 0x0084 | |
61 | #define MACB_RLE 0x0088 | |
62 | #define MACB_TPF 0x008c | |
63 | #define MACB_HRB 0x0090 | |
64 | #define MACB_HRT 0x0094 | |
65 | #define MACB_SA1B 0x0098 | |
66 | #define MACB_SA1T 0x009c | |
67 | #define MACB_SA2B 0x00a0 | |
68 | #define MACB_SA2T 0x00a4 | |
69 | #define MACB_SA3B 0x00a8 | |
70 | #define MACB_SA3T 0x00ac | |
71 | #define MACB_SA4B 0x00b0 | |
72 | #define MACB_SA4T 0x00b4 | |
73 | #define MACB_TID 0x00b8 | |
74 | #define MACB_TPQ 0x00bc | |
75 | #define MACB_USRIO 0x00c0 | |
76 | #define MACB_WOL 0x00c4 | |
77 | #define MACB_MID 0x00fc | |
fff8019a HK |
78 | #define MACB_TBQPH 0x04C8 |
79 | #define MACB_RBQPH 0x04D4 | |
f75ba50b JI |
80 | |
81 | /* GEM register offsets. */ | |
6f79eed8 XH |
82 | #define GEM_NCFGR 0x0004 /* Network Config */ |
83 | #define GEM_USRIO 0x000c /* User IO */ | |
84 | #define GEM_DMACFG 0x0010 /* DMA Configuration */ | |
98b5a0f4 | 85 | #define GEM_JML 0x0048 /* Jumbo Max Length */ |
6f79eed8 XH |
86 | #define GEM_HRB 0x0080 /* Hash Bottom */ |
87 | #define GEM_HRT 0x0084 /* Hash Top */ | |
88 | #define GEM_SA1B 0x0088 /* Specific1 Bottom */ | |
89 | #define GEM_SA1T 0x008C /* Specific1 Top */ | |
90 | #define GEM_SA2B 0x0090 /* Specific2 Bottom */ | |
91 | #define GEM_SA2T 0x0094 /* Specific2 Top */ | |
92 | #define GEM_SA3B 0x0098 /* Specific3 Bottom */ | |
93 | #define GEM_SA3T 0x009C /* Specific3 Top */ | |
94 | #define GEM_SA4B 0x00A0 /* Specific4 Bottom */ | |
95 | #define GEM_SA4T 0x00A4 /* Specific4 Top */ | |
ab91f0a9 RO |
96 | #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */ |
97 | #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */ | |
98 | #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */ | |
99 | #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */ | |
6f79eed8 XH |
100 | #define GEM_OTX 0x0100 /* Octets transmitted */ |
101 | #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */ | |
102 | #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */ | |
103 | #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */ | |
104 | #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */ | |
105 | #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */ | |
106 | #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */ | |
107 | #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */ | |
108 | #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */ | |
109 | #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */ | |
110 | #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */ | |
111 | #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */ | |
112 | #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */ | |
113 | #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */ | |
114 | #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */ | |
115 | #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */ | |
116 | #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */ | |
117 | #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */ | |
118 | #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */ | |
119 | #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */ | |
120 | #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */ | |
121 | #define GEM_ORX 0x0150 /* Octets received */ | |
122 | #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */ | |
123 | #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */ | |
124 | #define GEM_RXCNT 0x0158 /* Frames Received Counter */ | |
125 | #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */ | |
126 | #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */ | |
127 | #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */ | |
128 | #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */ | |
129 | #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */ | |
130 | #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */ | |
131 | #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */ | |
132 | #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */ | |
133 | #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */ | |
134 | #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */ | |
135 | #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */ | |
136 | #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */ | |
137 | #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */ | |
138 | #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */ | |
139 | #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */ | |
140 | #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */ | |
141 | #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */ | |
142 | #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */ | |
143 | #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */ | |
144 | #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */ | |
145 | #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */ | |
146 | #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */ | |
c2594d80 AP |
147 | #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */ |
148 | #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */ | |
149 | #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */ | |
150 | #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */ | |
151 | #define GEM_TA 0x01d8 /* 1588 Timer Adjust */ | |
152 | #define GEM_TI 0x01dc /* 1588 Timer Increment */ | |
153 | #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */ | |
154 | #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */ | |
155 | #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */ | |
156 | #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */ | |
157 | #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */ | |
158 | #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */ | |
159 | #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */ | |
160 | #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */ | |
6f79eed8 XH |
161 | #define GEM_DCFG1 0x0280 /* Design Config 1 */ |
162 | #define GEM_DCFG2 0x0284 /* Design Config 2 */ | |
163 | #define GEM_DCFG3 0x0288 /* Design Config 3 */ | |
164 | #define GEM_DCFG4 0x028c /* Design Config 4 */ | |
165 | #define GEM_DCFG5 0x0290 /* Design Config 5 */ | |
166 | #define GEM_DCFG6 0x0294 /* Design Config 6 */ | |
167 | #define GEM_DCFG7 0x0298 /* Design Config 7 */ | |
ae8223de | 168 | #define GEM_DCFG8 0x029C /* Design Config 8 */ |
404cd086 | 169 | #define GEM_DCFG10 0x02A4 /* Design Config 10 */ |
6f79eed8 | 170 | |
ab91f0a9 RO |
171 | #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */ |
172 | #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */ | |
173 | ||
ae8223de RO |
174 | /* Screener Type 2 match registers */ |
175 | #define GEM_SCRT2 0x540 | |
176 | ||
177 | /* EtherType registers */ | |
178 | #define GEM_ETHT 0x06E0 | |
179 | ||
180 | /* Type 2 compare registers */ | |
181 | #define GEM_T2CMPW0 0x0700 | |
182 | #define GEM_T2CMPW1 0x0704 | |
183 | #define T2CMP_OFST(t2idx) (t2idx * 2) | |
184 | ||
185 | /* type 2 compare registers | |
186 | * each location requires 3 compare regs | |
187 | */ | |
188 | #define GEM_IP4SRC_CMP(idx) (idx * 3) | |
189 | #define GEM_IP4DST_CMP(idx) (idx * 3 + 1) | |
190 | #define GEM_PORT_CMP(idx) (idx * 3 + 2) | |
191 | ||
192 | /* Which screening type 2 EtherType register will be used (0 - 7) */ | |
193 | #define SCRT2_ETHT 0 | |
194 | ||
6f79eed8 XH |
195 | #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) |
196 | #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) | |
fff8019a | 197 | #define GEM_TBQPH(hw_q) (0x04C8) |
6f79eed8 | 198 | #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) |
ae1f2a56 RO |
199 | #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2)) |
200 | #define GEM_RBQPH(hw_q) (0x04D4) | |
6f79eed8 XH |
201 | #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) |
202 | #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) | |
203 | #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) | |
02c958dd | 204 | |
89e5785f | 205 | /* Bitfields in NCR */ |
6f79eed8 XH |
206 | #define MACB_LB_OFFSET 0 /* reserved */ |
207 | #define MACB_LB_SIZE 1 | |
208 | #define MACB_LLB_OFFSET 1 /* Loop back local */ | |
209 | #define MACB_LLB_SIZE 1 | |
210 | #define MACB_RE_OFFSET 2 /* Receive enable */ | |
211 | #define MACB_RE_SIZE 1 | |
212 | #define MACB_TE_OFFSET 3 /* Transmit enable */ | |
213 | #define MACB_TE_SIZE 1 | |
214 | #define MACB_MPE_OFFSET 4 /* Management port enable */ | |
215 | #define MACB_MPE_SIZE 1 | |
216 | #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */ | |
217 | #define MACB_CLRSTAT_SIZE 1 | |
218 | #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */ | |
219 | #define MACB_INCSTAT_SIZE 1 | |
220 | #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */ | |
221 | #define MACB_WESTAT_SIZE 1 | |
222 | #define MACB_BP_OFFSET 8 /* Back pressure */ | |
223 | #define MACB_BP_SIZE 1 | |
224 | #define MACB_TSTART_OFFSET 9 /* Start transmission */ | |
225 | #define MACB_TSTART_SIZE 1 | |
226 | #define MACB_THALT_OFFSET 10 /* Transmit halt */ | |
227 | #define MACB_THALT_SIZE 1 | |
228 | #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */ | |
229 | #define MACB_NCR_TPF_SIZE 1 | |
230 | #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */ | |
231 | #define MACB_TZQ_SIZE 1 | |
c2594d80 | 232 | #define MACB_SRTSM_OFFSET 15 |
ab91f0a9 RO |
233 | #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */ |
234 | #define MACB_OSSMODE_SIZE 1 | |
89e5785f HS |
235 | |
236 | /* Bitfields in NCFGR */ | |
6f79eed8 XH |
237 | #define MACB_SPD_OFFSET 0 /* Speed */ |
238 | #define MACB_SPD_SIZE 1 | |
239 | #define MACB_FD_OFFSET 1 /* Full duplex */ | |
240 | #define MACB_FD_SIZE 1 | |
241 | #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */ | |
242 | #define MACB_BIT_RATE_SIZE 1 | |
243 | #define MACB_JFRAME_OFFSET 3 /* reserved */ | |
244 | #define MACB_JFRAME_SIZE 1 | |
245 | #define MACB_CAF_OFFSET 4 /* Copy all frames */ | |
246 | #define MACB_CAF_SIZE 1 | |
247 | #define MACB_NBC_OFFSET 5 /* No broadcast */ | |
248 | #define MACB_NBC_SIZE 1 | |
249 | #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */ | |
250 | #define MACB_NCFGR_MTI_SIZE 1 | |
251 | #define MACB_UNI_OFFSET 7 /* Unicast hash enable */ | |
252 | #define MACB_UNI_SIZE 1 | |
253 | #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */ | |
254 | #define MACB_BIG_SIZE 1 | |
255 | #define MACB_EAE_OFFSET 9 /* External address match enable */ | |
256 | #define MACB_EAE_SIZE 1 | |
257 | #define MACB_CLK_OFFSET 10 | |
258 | #define MACB_CLK_SIZE 2 | |
259 | #define MACB_RTY_OFFSET 12 /* Retry test */ | |
260 | #define MACB_RTY_SIZE 1 | |
261 | #define MACB_PAE_OFFSET 13 /* Pause enable */ | |
262 | #define MACB_PAE_SIZE 1 | |
263 | #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ | |
264 | #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ | |
265 | #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */ | |
266 | #define MACB_RBOF_SIZE 2 | |
267 | #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */ | |
268 | #define MACB_RLCE_SIZE 1 | |
269 | #define MACB_DRFCS_OFFSET 17 /* FCS remove */ | |
270 | #define MACB_DRFCS_SIZE 1 | |
271 | #define MACB_EFRHD_OFFSET 18 | |
272 | #define MACB_EFRHD_SIZE 1 | |
273 | #define MACB_IRXFCS_OFFSET 19 | |
274 | #define MACB_IRXFCS_SIZE 1 | |
89e5785f | 275 | |
70c9f3d4 | 276 | /* GEM specific NCFGR bitfields. */ |
6f79eed8 XH |
277 | #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ |
278 | #define GEM_GBE_SIZE 1 | |
022be25c PCK |
279 | #define GEM_PCSSEL_OFFSET 11 |
280 | #define GEM_PCSSEL_SIZE 1 | |
6f79eed8 XH |
281 | #define GEM_CLK_OFFSET 18 /* MDC clock division */ |
282 | #define GEM_CLK_SIZE 3 | |
283 | #define GEM_DBW_OFFSET 21 /* Data bus width */ | |
284 | #define GEM_DBW_SIZE 2 | |
285 | #define GEM_RXCOEN_OFFSET 24 | |
286 | #define GEM_RXCOEN_SIZE 1 | |
022be25c PCK |
287 | #define GEM_SGMIIEN_OFFSET 27 |
288 | #define GEM_SGMIIEN_SIZE 1 | |
289 | ||
757a03c6 JI |
290 | |
291 | /* Constants for data bus width. */ | |
6f79eed8 XH |
292 | #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ |
293 | #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ | |
294 | #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */ | |
757a03c6 | 295 | |
0116da4f | 296 | /* Bitfields in DMACFG. */ |
6f79eed8 XH |
297 | #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ |
298 | #define GEM_FBLDO_SIZE 5 | |
a50dad35 | 299 | #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ |
ea373041 | 300 | #define GEM_ENDIA_DESC_SIZE 1 |
a50dad35 | 301 | #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ |
ea373041 | 302 | #define GEM_ENDIA_PKT_SIZE 1 |
6f79eed8 XH |
303 | #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ |
304 | #define GEM_RXBMS_SIZE 2 | |
305 | #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ | |
306 | #define GEM_TXPBMS_SIZE 1 | |
307 | #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */ | |
308 | #define GEM_TXCOEN_SIZE 1 | |
309 | #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */ | |
310 | #define GEM_RXBS_SIZE 8 | |
311 | #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */ | |
312 | #define GEM_DDRP_SIZE 1 | |
7b429614 RO |
313 | #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */ |
314 | #define GEM_RXEXT_SIZE 1 | |
315 | #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */ | |
316 | #define GEM_TXEXT_SIZE 1 | |
fff8019a HK |
317 | #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */ |
318 | #define GEM_ADDR64_SIZE 1 | |
b3e3bd71 | 319 | |
0116da4f | 320 | |
89e5785f | 321 | /* Bitfields in NSR */ |
6f79eed8 XH |
322 | #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ |
323 | #define MACB_NSR_LINK_SIZE 1 | |
324 | #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */ | |
325 | #define MACB_MDIO_SIZE 1 | |
326 | #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ | |
327 | #define MACB_IDLE_SIZE 1 | |
89e5785f HS |
328 | |
329 | /* Bitfields in TSR */ | |
6f79eed8 XH |
330 | #define MACB_UBR_OFFSET 0 /* Used bit read */ |
331 | #define MACB_UBR_SIZE 1 | |
332 | #define MACB_COL_OFFSET 1 /* Collision occurred */ | |
333 | #define MACB_COL_SIZE 1 | |
334 | #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */ | |
335 | #define MACB_TSR_RLE_SIZE 1 | |
336 | #define MACB_TGO_OFFSET 3 /* Transmit go */ | |
337 | #define MACB_TGO_SIZE 1 | |
338 | #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */ | |
339 | #define MACB_BEX_SIZE 1 | |
340 | #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ | |
341 | #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ | |
342 | #define MACB_COMP_OFFSET 5 /* Trnasmit complete */ | |
343 | #define MACB_COMP_SIZE 1 | |
344 | #define MACB_UND_OFFSET 6 /* Trnasmit under run */ | |
345 | #define MACB_UND_SIZE 1 | |
89e5785f HS |
346 | |
347 | /* Bitfields in RSR */ | |
6f79eed8 XH |
348 | #define MACB_BNA_OFFSET 0 /* Buffer not available */ |
349 | #define MACB_BNA_SIZE 1 | |
350 | #define MACB_REC_OFFSET 1 /* Frame received */ | |
351 | #define MACB_REC_SIZE 1 | |
352 | #define MACB_OVR_OFFSET 2 /* Receive overrun */ | |
353 | #define MACB_OVR_SIZE 1 | |
89e5785f HS |
354 | |
355 | /* Bitfields in ISR/IER/IDR/IMR */ | |
6f79eed8 XH |
356 | #define MACB_MFD_OFFSET 0 /* Management frame sent */ |
357 | #define MACB_MFD_SIZE 1 | |
358 | #define MACB_RCOMP_OFFSET 1 /* Receive complete */ | |
359 | #define MACB_RCOMP_SIZE 1 | |
360 | #define MACB_RXUBR_OFFSET 2 /* RX used bit read */ | |
361 | #define MACB_RXUBR_SIZE 1 | |
362 | #define MACB_TXUBR_OFFSET 3 /* TX used bit read */ | |
363 | #define MACB_TXUBR_SIZE 1 | |
364 | #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */ | |
365 | #define MACB_ISR_TUND_SIZE 1 | |
366 | #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */ | |
367 | #define MACB_ISR_RLE_SIZE 1 | |
368 | #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */ | |
369 | #define MACB_TXERR_SIZE 1 | |
370 | #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */ | |
371 | #define MACB_TCOMP_SIZE 1 | |
372 | #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */ | |
373 | #define MACB_ISR_LINK_SIZE 1 | |
374 | #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */ | |
375 | #define MACB_ISR_ROVR_SIZE 1 | |
376 | #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */ | |
377 | #define MACB_HRESP_SIZE 1 | |
378 | #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */ | |
379 | #define MACB_PFR_SIZE 1 | |
380 | #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */ | |
381 | #define MACB_PTZ_SIZE 1 | |
3e2a5e15 SP |
382 | #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */ |
383 | #define MACB_WOL_SIZE 1 | |
c2594d80 AP |
384 | #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */ |
385 | #define MACB_DRQFR_SIZE 1 | |
386 | #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */ | |
387 | #define MACB_SFR_SIZE 1 | |
388 | #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */ | |
389 | #define MACB_DRQFT_SIZE 1 | |
390 | #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */ | |
391 | #define MACB_SFT_SIZE 1 | |
392 | #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */ | |
393 | #define MACB_PDRQFR_SIZE 1 | |
394 | #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */ | |
395 | #define MACB_PDRSFR_SIZE 1 | |
396 | #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */ | |
397 | #define MACB_PDRQFT_SIZE 1 | |
398 | #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */ | |
399 | #define MACB_PDRSFT_SIZE 1 | |
400 | #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */ | |
401 | #define MACB_SRI_SIZE 1 | |
402 | ||
403 | /* Timer increment fields */ | |
404 | #define MACB_TI_CNS_OFFSET 0 | |
405 | #define MACB_TI_CNS_SIZE 8 | |
406 | #define MACB_TI_ACNS_OFFSET 8 | |
407 | #define MACB_TI_ACNS_SIZE 8 | |
408 | #define MACB_TI_NIT_OFFSET 16 | |
409 | #define MACB_TI_NIT_SIZE 8 | |
89e5785f HS |
410 | |
411 | /* Bitfields in MAN */ | |
6f79eed8 XH |
412 | #define MACB_DATA_OFFSET 0 /* data */ |
413 | #define MACB_DATA_SIZE 16 | |
414 | #define MACB_CODE_OFFSET 16 /* Must be written to 10 */ | |
415 | #define MACB_CODE_SIZE 2 | |
416 | #define MACB_REGA_OFFSET 18 /* Register address */ | |
417 | #define MACB_REGA_SIZE 5 | |
418 | #define MACB_PHYA_OFFSET 23 /* PHY address */ | |
419 | #define MACB_PHYA_SIZE 5 | |
420 | #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */ | |
421 | #define MACB_RW_SIZE 2 | |
422 | #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */ | |
423 | #define MACB_SOF_SIZE 2 | |
89e5785f | 424 | |
0cc8674f | 425 | /* Bitfields in USRIO (AVR32) */ |
89e5785f HS |
426 | #define MACB_MII_OFFSET 0 |
427 | #define MACB_MII_SIZE 1 | |
428 | #define MACB_EAM_OFFSET 1 | |
429 | #define MACB_EAM_SIZE 1 | |
430 | #define MACB_TX_PAUSE_OFFSET 2 | |
431 | #define MACB_TX_PAUSE_SIZE 1 | |
432 | #define MACB_TX_PAUSE_ZERO_OFFSET 3 | |
433 | #define MACB_TX_PAUSE_ZERO_SIZE 1 | |
434 | ||
0cc8674f AV |
435 | /* Bitfields in USRIO (AT91) */ |
436 | #define MACB_RMII_OFFSET 0 | |
437 | #define MACB_RMII_SIZE 1 | |
5c2fa0f6 | 438 | #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ |
140b7552 | 439 | #define GEM_RGMII_SIZE 1 |
0cc8674f AV |
440 | #define MACB_CLKEN_OFFSET 1 |
441 | #define MACB_CLKEN_SIZE 1 | |
442 | ||
89e5785f HS |
443 | /* Bitfields in WOL */ |
444 | #define MACB_IP_OFFSET 0 | |
445 | #define MACB_IP_SIZE 16 | |
446 | #define MACB_MAG_OFFSET 16 | |
447 | #define MACB_MAG_SIZE 1 | |
448 | #define MACB_ARP_OFFSET 17 | |
449 | #define MACB_ARP_SIZE 1 | |
450 | #define MACB_SA1_OFFSET 18 | |
451 | #define MACB_SA1_SIZE 1 | |
452 | #define MACB_WOL_MTI_OFFSET 19 | |
453 | #define MACB_WOL_MTI_SIZE 1 | |
454 | ||
f75ba50b JI |
455 | /* Bitfields in MID */ |
456 | #define MACB_IDNUM_OFFSET 16 | |
d941bebf | 457 | #define MACB_IDNUM_SIZE 12 |
f75ba50b JI |
458 | #define MACB_REV_OFFSET 0 |
459 | #define MACB_REV_SIZE 16 | |
460 | ||
757a03c6 | 461 | /* Bitfields in DCFG1. */ |
581df9e1 NF |
462 | #define GEM_IRQCOR_OFFSET 23 |
463 | #define GEM_IRQCOR_SIZE 1 | |
757a03c6 JI |
464 | #define GEM_DBWDEF_OFFSET 25 |
465 | #define GEM_DBWDEF_SIZE 3 | |
466 | ||
e175587f NF |
467 | /* Bitfields in DCFG2. */ |
468 | #define GEM_RX_PKT_BUFF_OFFSET 20 | |
469 | #define GEM_RX_PKT_BUFF_SIZE 1 | |
470 | #define GEM_TX_PKT_BUFF_OFFSET 21 | |
471 | #define GEM_TX_PKT_BUFF_SIZE 1 | |
472 | ||
7b429614 RO |
473 | |
474 | /* Bitfields in DCFG5. */ | |
475 | #define GEM_TSU_OFFSET 8 | |
476 | #define GEM_TSU_SIZE 1 | |
477 | ||
1629dd4f RO |
478 | /* Bitfields in DCFG6. */ |
479 | #define GEM_PBUF_LSO_OFFSET 27 | |
480 | #define GEM_PBUF_LSO_SIZE 1 | |
dc97a89e RO |
481 | #define GEM_DAW64_OFFSET 23 |
482 | #define GEM_DAW64_SIZE 1 | |
1629dd4f | 483 | |
ae8223de RO |
484 | /* Bitfields in DCFG8. */ |
485 | #define GEM_T1SCR_OFFSET 24 | |
486 | #define GEM_T1SCR_SIZE 8 | |
487 | #define GEM_T2SCR_OFFSET 16 | |
488 | #define GEM_T2SCR_SIZE 8 | |
489 | #define GEM_SCR2ETH_OFFSET 8 | |
490 | #define GEM_SCR2ETH_SIZE 8 | |
491 | #define GEM_SCR2CMP_OFFSET 0 | |
492 | #define GEM_SCR2CMP_SIZE 8 | |
493 | ||
404cd086 HK |
494 | /* Bitfields in DCFG10 */ |
495 | #define GEM_TXBD_RDBUFF_OFFSET 12 | |
496 | #define GEM_TXBD_RDBUFF_SIZE 4 | |
497 | #define GEM_RXBD_RDBUFF_OFFSET 8 | |
498 | #define GEM_RXBD_RDBUFF_SIZE 4 | |
499 | ||
c2594d80 AP |
500 | /* Bitfields in TISUBN */ |
501 | #define GEM_SUBNSINCR_OFFSET 0 | |
502 | #define GEM_SUBNSINCR_SIZE 16 | |
503 | ||
504 | /* Bitfields in TI */ | |
505 | #define GEM_NSINCR_OFFSET 0 | |
506 | #define GEM_NSINCR_SIZE 8 | |
507 | ||
ab91f0a9 RO |
508 | /* Bitfields in TSH */ |
509 | #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */ | |
510 | #define GEM_TSH_SIZE 16 | |
511 | ||
512 | /* Bitfields in TSL */ | |
513 | #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */ | |
514 | #define GEM_TSL_SIZE 32 | |
515 | ||
516 | /* Bitfields in TN */ | |
517 | #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */ | |
518 | #define GEM_TN_SIZE 30 | |
519 | ||
520 | /* Bitfields in TXBDCTRL */ | |
521 | #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */ | |
522 | #define GEM_TXTSMODE_SIZE 2 | |
523 | ||
524 | /* Bitfields in RXBDCTRL */ | |
525 | #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */ | |
526 | #define GEM_RXTSMODE_SIZE 2 | |
527 | ||
ae8223de RO |
528 | /* Bitfields in SCRT2 */ |
529 | #define GEM_QUEUE_OFFSET 0 /* Queue Number */ | |
530 | #define GEM_QUEUE_SIZE 4 | |
531 | #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */ | |
532 | #define GEM_VLANPR_SIZE 3 | |
533 | #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */ | |
534 | #define GEM_VLANEN_SIZE 1 | |
535 | #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */ | |
536 | #define GEM_ETHT2IDX_SIZE 3 | |
537 | #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */ | |
538 | #define GEM_ETHTEN_SIZE 1 | |
539 | #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */ | |
540 | #define GEM_CMPA_SIZE 5 | |
541 | #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */ | |
542 | #define GEM_CMPAEN_SIZE 1 | |
543 | #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */ | |
544 | #define GEM_CMPB_SIZE 5 | |
545 | #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */ | |
546 | #define GEM_CMPBEN_SIZE 1 | |
547 | #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */ | |
548 | #define GEM_CMPC_SIZE 5 | |
549 | #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */ | |
550 | #define GEM_CMPCEN_SIZE 1 | |
551 | ||
552 | /* Bitfields in ETHT */ | |
553 | #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */ | |
554 | #define GEM_ETHTCMP_SIZE 16 | |
555 | ||
556 | /* Bitfields in T2CMPW0 */ | |
557 | #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */ | |
558 | #define GEM_T2CMP_SIZE 16 | |
559 | #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */ | |
560 | #define GEM_T2MASK_SIZE 16 | |
561 | ||
562 | /* Bitfields in T2CMPW1 */ | |
563 | #define GEM_T2DISMSK_OFFSET 9 /* disable mask */ | |
564 | #define GEM_T2DISMSK_SIZE 1 | |
565 | #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */ | |
566 | #define GEM_T2CMPOFST_SIZE 2 | |
567 | #define GEM_T2OFST_OFFSET 0 /* offset value */ | |
568 | #define GEM_T2OFST_SIZE 7 | |
569 | ||
570 | /* Offset for screener type 2 compare values (T2CMPOFST). | |
571 | * Note the offset is applied after the specified point, | |
572 | * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset | |
573 | * of 12 bytes from this would be the source IP address in an IP header | |
574 | */ | |
575 | #define GEM_T2COMPOFST_SOF 0 | |
576 | #define GEM_T2COMPOFST_ETYPE 1 | |
577 | #define GEM_T2COMPOFST_IPHDR 2 | |
578 | #define GEM_T2COMPOFST_TCPUDP 3 | |
579 | ||
580 | /* offset from EtherType to IP address */ | |
581 | #define ETYPE_SRCIP_OFFSET 12 | |
582 | #define ETYPE_DSTIP_OFFSET 16 | |
583 | ||
584 | /* offset from IP header to port */ | |
585 | #define IPHDR_SRCPORT_OFFSET 0 | |
586 | #define IPHDR_DSTPORT_OFFSET 2 | |
587 | ||
ab91f0a9 RO |
588 | /* Transmit DMA buffer descriptor Word 1 */ |
589 | #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */ | |
590 | #define GEM_DMA_TXVALID_SIZE 1 | |
591 | ||
592 | /* Receive DMA buffer descriptor Word 0 */ | |
593 | #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */ | |
594 | #define GEM_DMA_RXVALID_SIZE 1 | |
595 | ||
596 | /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */ | |
597 | #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */ | |
598 | #define GEM_DMA_SECL_SIZE 2 | |
599 | #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */ | |
600 | #define GEM_DMA_NSEC_SIZE 30 | |
601 | ||
602 | /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */ | |
603 | ||
604 | /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor. | |
605 | * Old hardware supports only 6 bit precision but it is enough for PTP. | |
606 | * Less accuracy is used always instead of checking hardware version. | |
607 | */ | |
608 | #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */ | |
609 | #define GEM_DMA_SECH_SIZE 4 | |
610 | #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE) | |
611 | #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH) | |
612 | #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1) | |
613 | ||
c2594d80 AP |
614 | /* Bitfields in ADJ */ |
615 | #define GEM_ADDSUB_OFFSET 31 | |
616 | #define GEM_ADDSUB_SIZE 1 | |
89e5785f HS |
617 | /* Constants for CLK */ |
618 | #define MACB_CLK_DIV8 0 | |
619 | #define MACB_CLK_DIV16 1 | |
620 | #define MACB_CLK_DIV32 2 | |
621 | #define MACB_CLK_DIV64 3 | |
622 | ||
70c9f3d4 JI |
623 | /* GEM specific constants for CLK. */ |
624 | #define GEM_CLK_DIV8 0 | |
625 | #define GEM_CLK_DIV16 1 | |
626 | #define GEM_CLK_DIV32 2 | |
627 | #define GEM_CLK_DIV48 3 | |
628 | #define GEM_CLK_DIV64 4 | |
629 | #define GEM_CLK_DIV96 5 | |
630 | ||
89e5785f HS |
631 | /* Constants for MAN register */ |
632 | #define MACB_MAN_SOF 1 | |
633 | #define MACB_MAN_WRITE 1 | |
634 | #define MACB_MAN_READ 2 | |
635 | #define MACB_MAN_CODE 2 | |
636 | ||
581df9e1 | 637 | /* Capability mask bits */ |
e175587f | 638 | #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 |
a8487489 | 639 | #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 |
6bdaa5e9 | 640 | #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004 |
222ca8e0 | 641 | #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 |
ce721a70 | 642 | #define MACB_CAPS_USRIO_DISABLED 0x00000010 |
c5181895 | 643 | #define MACB_CAPS_JUMBO 0x00000020 |
c2594d80 | 644 | #define MACB_CAPS_GEM_HAS_PTP 0x00000040 |
404cd086 | 645 | #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 |
e501070e | 646 | #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 |
e175587f NF |
647 | #define MACB_CAPS_FIFO_MODE 0x10000000 |
648 | #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 | |
a4c35ed3 | 649 | #define MACB_CAPS_SG_DISABLED 0x40000000 |
e175587f | 650 | #define MACB_CAPS_MACB_IS_GEM 0x80000000 |
581df9e1 | 651 | |
1629dd4f RO |
652 | /* LSO settings */ |
653 | #define MACB_LSO_UFO_ENABLE 0x01 | |
654 | #define MACB_LSO_TSO_ENABLE 0x02 | |
655 | ||
89e5785f HS |
656 | /* Bit manipulation macros */ |
657 | #define MACB_BIT(name) \ | |
658 | (1 << MACB_##name##_OFFSET) | |
659 | #define MACB_BF(name,value) \ | |
660 | (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ | |
661 | << MACB_##name##_OFFSET) | |
662 | #define MACB_BFEXT(name,value)\ | |
663 | (((value) >> MACB_##name##_OFFSET) \ | |
664 | & ((1 << MACB_##name##_SIZE) - 1)) | |
665 | #define MACB_BFINS(name,value,old) \ | |
666 | (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ | |
667 | << MACB_##name##_OFFSET)) \ | |
668 | | MACB_BF(name,value)) | |
669 | ||
f75ba50b JI |
670 | #define GEM_BIT(name) \ |
671 | (1 << GEM_##name##_OFFSET) | |
672 | #define GEM_BF(name, value) \ | |
673 | (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ | |
674 | << GEM_##name##_OFFSET) | |
675 | #define GEM_BFEXT(name, value)\ | |
676 | (((value) >> GEM_##name##_OFFSET) \ | |
677 | & ((1 << GEM_##name##_SIZE) - 1)) | |
678 | #define GEM_BFINS(name, value, old) \ | |
679 | (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ | |
680 | << GEM_##name##_OFFSET)) \ | |
681 | | GEM_BF(name, value)) | |
682 | ||
89e5785f | 683 | /* Register access macros */ |
7a6e0706 DM |
684 | #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg) |
685 | #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value)) | |
686 | #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg) | |
687 | #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value)) | |
688 | #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg) | |
689 | #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value)) | |
ae8223de RO |
690 | #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4) |
691 | #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value)) | |
f75ba50b | 692 | |
ab91f0a9 RO |
693 | #define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */ |
694 | ||
6f79eed8 | 695 | /* Conditional GEM/MACB macros. These perform the operation to the correct |
f75ba50b JI |
696 | * register dependent on whether the device is a GEM or a MACB. For registers |
697 | * and bitfields that are common across both devices, use macb_{read,write}l | |
698 | * to avoid the cost of the conditional. | |
699 | */ | |
700 | #define macb_or_gem_writel(__bp, __reg, __value) \ | |
701 | ({ \ | |
702 | if (macb_is_gem((__bp))) \ | |
703 | gem_writel((__bp), __reg, __value); \ | |
704 | else \ | |
705 | macb_writel((__bp), __reg, __value); \ | |
706 | }) | |
707 | ||
708 | #define macb_or_gem_readl(__bp, __reg) \ | |
709 | ({ \ | |
710 | u32 __v; \ | |
711 | if (macb_is_gem((__bp))) \ | |
712 | __v = gem_readl((__bp), __reg); \ | |
713 | else \ | |
714 | __v = macb_readl((__bp), __reg); \ | |
715 | __v; \ | |
716 | }) | |
89e5785f | 717 | |
8beb79b7 HK |
718 | #define MACB_READ_NSR(bp) macb_readl(bp, NSR) |
719 | ||
6f79eed8 | 720 | /* struct macb_dma_desc - Hardware DMA descriptor |
55054a16 HS |
721 | * @addr: DMA address of data buffer |
722 | * @ctrl: Control and status bits | |
723 | */ | |
724 | struct macb_dma_desc { | |
89e5785f HS |
725 | u32 addr; |
726 | u32 ctrl; | |
dc97a89e RO |
727 | }; |
728 | ||
7b429614 RO |
729 | #ifdef MACB_EXT_DESC |
730 | #define HW_DMA_CAP_32B 0 | |
731 | #define HW_DMA_CAP_64B (1 << 0) | |
732 | #define HW_DMA_CAP_PTP (1 << 1) | |
733 | #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP) | |
89e5785f | 734 | |
dc97a89e RO |
735 | struct macb_dma_desc_64 { |
736 | u32 addrh; | |
737 | u32 resvd; | |
89e5785f | 738 | }; |
7b429614 RO |
739 | |
740 | struct macb_dma_desc_ptp { | |
741 | u32 ts_1; | |
742 | u32 ts_2; | |
743 | }; | |
ab91f0a9 RO |
744 | |
745 | struct gem_tx_ts { | |
746 | struct sk_buff *skb; | |
747 | struct macb_dma_desc_ptp desc_ptp; | |
748 | }; | |
dc97a89e | 749 | #endif |
89e5785f HS |
750 | |
751 | /* DMA descriptor bitfields */ | |
752 | #define MACB_RX_USED_OFFSET 0 | |
753 | #define MACB_RX_USED_SIZE 1 | |
754 | #define MACB_RX_WRAP_OFFSET 1 | |
755 | #define MACB_RX_WRAP_SIZE 1 | |
756 | #define MACB_RX_WADDR_OFFSET 2 | |
757 | #define MACB_RX_WADDR_SIZE 30 | |
758 | ||
759 | #define MACB_RX_FRMLEN_OFFSET 0 | |
760 | #define MACB_RX_FRMLEN_SIZE 12 | |
761 | #define MACB_RX_OFFSET_OFFSET 12 | |
762 | #define MACB_RX_OFFSET_SIZE 2 | |
763 | #define MACB_RX_SOF_OFFSET 14 | |
764 | #define MACB_RX_SOF_SIZE 1 | |
765 | #define MACB_RX_EOF_OFFSET 15 | |
766 | #define MACB_RX_EOF_SIZE 1 | |
767 | #define MACB_RX_CFI_OFFSET 16 | |
768 | #define MACB_RX_CFI_SIZE 1 | |
769 | #define MACB_RX_VLAN_PRI_OFFSET 17 | |
770 | #define MACB_RX_VLAN_PRI_SIZE 3 | |
771 | #define MACB_RX_PRI_TAG_OFFSET 20 | |
772 | #define MACB_RX_PRI_TAG_SIZE 1 | |
773 | #define MACB_RX_VLAN_TAG_OFFSET 21 | |
774 | #define MACB_RX_VLAN_TAG_SIZE 1 | |
775 | #define MACB_RX_TYPEID_MATCH_OFFSET 22 | |
776 | #define MACB_RX_TYPEID_MATCH_SIZE 1 | |
777 | #define MACB_RX_SA4_MATCH_OFFSET 23 | |
778 | #define MACB_RX_SA4_MATCH_SIZE 1 | |
779 | #define MACB_RX_SA3_MATCH_OFFSET 24 | |
780 | #define MACB_RX_SA3_MATCH_SIZE 1 | |
781 | #define MACB_RX_SA2_MATCH_OFFSET 25 | |
782 | #define MACB_RX_SA2_MATCH_SIZE 1 | |
783 | #define MACB_RX_SA1_MATCH_OFFSET 26 | |
784 | #define MACB_RX_SA1_MATCH_SIZE 1 | |
785 | #define MACB_RX_EXT_MATCH_OFFSET 28 | |
786 | #define MACB_RX_EXT_MATCH_SIZE 1 | |
787 | #define MACB_RX_UHASH_MATCH_OFFSET 29 | |
788 | #define MACB_RX_UHASH_MATCH_SIZE 1 | |
789 | #define MACB_RX_MHASH_MATCH_OFFSET 30 | |
790 | #define MACB_RX_MHASH_MATCH_SIZE 1 | |
791 | #define MACB_RX_BROADCAST_OFFSET 31 | |
792 | #define MACB_RX_BROADCAST_SIZE 1 | |
793 | ||
98b5a0f4 HK |
794 | #define MACB_RX_FRMLEN_MASK 0xFFF |
795 | #define MACB_RX_JFRMLEN_MASK 0x3FFF | |
796 | ||
924ec53c CP |
797 | /* RX checksum offload disabled: bit 24 clear in NCFGR */ |
798 | #define GEM_RX_TYPEID_MATCH_OFFSET 22 | |
799 | #define GEM_RX_TYPEID_MATCH_SIZE 2 | |
800 | ||
801 | /* RX checksum offload enabled: bit 24 set in NCFGR */ | |
802 | #define GEM_RX_CSUM_OFFSET 22 | |
803 | #define GEM_RX_CSUM_SIZE 2 | |
804 | ||
89e5785f HS |
805 | #define MACB_TX_FRMLEN_OFFSET 0 |
806 | #define MACB_TX_FRMLEN_SIZE 11 | |
807 | #define MACB_TX_LAST_OFFSET 15 | |
808 | #define MACB_TX_LAST_SIZE 1 | |
809 | #define MACB_TX_NOCRC_OFFSET 16 | |
810 | #define MACB_TX_NOCRC_SIZE 1 | |
1629dd4f RO |
811 | #define MACB_MSS_MFS_OFFSET 16 |
812 | #define MACB_MSS_MFS_SIZE 14 | |
813 | #define MACB_TX_LSO_OFFSET 17 | |
814 | #define MACB_TX_LSO_SIZE 2 | |
815 | #define MACB_TX_TCP_SEQ_SRC_OFFSET 19 | |
816 | #define MACB_TX_TCP_SEQ_SRC_SIZE 1 | |
89e5785f HS |
817 | #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 |
818 | #define MACB_TX_BUF_EXHAUSTED_SIZE 1 | |
819 | #define MACB_TX_UNDERRUN_OFFSET 28 | |
820 | #define MACB_TX_UNDERRUN_SIZE 1 | |
821 | #define MACB_TX_ERROR_OFFSET 29 | |
822 | #define MACB_TX_ERROR_SIZE 1 | |
823 | #define MACB_TX_WRAP_OFFSET 30 | |
824 | #define MACB_TX_WRAP_SIZE 1 | |
825 | #define MACB_TX_USED_OFFSET 31 | |
826 | #define MACB_TX_USED_SIZE 1 | |
827 | ||
a4c35ed3 CP |
828 | #define GEM_TX_FRMLEN_OFFSET 0 |
829 | #define GEM_TX_FRMLEN_SIZE 14 | |
830 | ||
924ec53c CP |
831 | /* Buffer descriptor constants */ |
832 | #define GEM_RX_CSUM_NONE 0 | |
833 | #define GEM_RX_CSUM_IP_ONLY 1 | |
834 | #define GEM_RX_CSUM_IP_TCP 2 | |
835 | #define GEM_RX_CSUM_IP_UDP 3 | |
836 | ||
837 | /* limit RX checksum offload to TCP and UDP packets */ | |
838 | #define GEM_RX_CSUM_CHECKED_MASK 2 | |
839 | ||
6f79eed8 | 840 | /* struct macb_tx_skb - data about an skb which is being transmitted |
a4c35ed3 CP |
841 | * @skb: skb currently being transmitted, only set for the last buffer |
842 | * of the frame | |
843 | * @mapping: DMA address of the skb's fragment buffer | |
844 | * @size: size of the DMA mapped buffer | |
845 | * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(), | |
846 | * false when buffer was mapped with dma_map_single() | |
55054a16 HS |
847 | */ |
848 | struct macb_tx_skb { | |
89e5785f HS |
849 | struct sk_buff *skb; |
850 | dma_addr_t mapping; | |
a4c35ed3 CP |
851 | size_t size; |
852 | bool mapped_as_page; | |
89e5785f HS |
853 | }; |
854 | ||
6f79eed8 | 855 | /* Hardware-collected statistics. Used when updating the network |
89e5785f HS |
856 | * device stats by a periodic timer. |
857 | */ | |
858 | struct macb_stats { | |
859 | u32 rx_pause_frames; | |
860 | u32 tx_ok; | |
861 | u32 tx_single_cols; | |
862 | u32 tx_multiple_cols; | |
863 | u32 rx_ok; | |
864 | u32 rx_fcs_errors; | |
865 | u32 rx_align_errors; | |
866 | u32 tx_deferred; | |
867 | u32 tx_late_cols; | |
868 | u32 tx_excessive_cols; | |
869 | u32 tx_underruns; | |
870 | u32 tx_carrier_errors; | |
871 | u32 rx_resource_errors; | |
872 | u32 rx_overruns; | |
873 | u32 rx_symbol_errors; | |
874 | u32 rx_oversize_pkts; | |
875 | u32 rx_jabbers; | |
876 | u32 rx_undersize_pkts; | |
877 | u32 sqe_test_errors; | |
878 | u32 rx_length_mismatch; | |
879 | u32 tx_pause_frames; | |
880 | }; | |
881 | ||
a494ed8e JI |
882 | struct gem_stats { |
883 | u32 tx_octets_31_0; | |
884 | u32 tx_octets_47_32; | |
885 | u32 tx_frames; | |
886 | u32 tx_broadcast_frames; | |
887 | u32 tx_multicast_frames; | |
888 | u32 tx_pause_frames; | |
889 | u32 tx_64_byte_frames; | |
890 | u32 tx_65_127_byte_frames; | |
891 | u32 tx_128_255_byte_frames; | |
892 | u32 tx_256_511_byte_frames; | |
893 | u32 tx_512_1023_byte_frames; | |
894 | u32 tx_1024_1518_byte_frames; | |
895 | u32 tx_greater_than_1518_byte_frames; | |
896 | u32 tx_underrun; | |
897 | u32 tx_single_collision_frames; | |
898 | u32 tx_multiple_collision_frames; | |
899 | u32 tx_excessive_collisions; | |
900 | u32 tx_late_collisions; | |
901 | u32 tx_deferred_frames; | |
902 | u32 tx_carrier_sense_errors; | |
903 | u32 rx_octets_31_0; | |
904 | u32 rx_octets_47_32; | |
905 | u32 rx_frames; | |
906 | u32 rx_broadcast_frames; | |
907 | u32 rx_multicast_frames; | |
908 | u32 rx_pause_frames; | |
909 | u32 rx_64_byte_frames; | |
910 | u32 rx_65_127_byte_frames; | |
911 | u32 rx_128_255_byte_frames; | |
912 | u32 rx_256_511_byte_frames; | |
913 | u32 rx_512_1023_byte_frames; | |
914 | u32 rx_1024_1518_byte_frames; | |
915 | u32 rx_greater_than_1518_byte_frames; | |
916 | u32 rx_undersized_frames; | |
917 | u32 rx_oversize_frames; | |
918 | u32 rx_jabbers; | |
919 | u32 rx_frame_check_sequence_errors; | |
920 | u32 rx_length_field_frame_errors; | |
921 | u32 rx_symbol_errors; | |
922 | u32 rx_alignment_errors; | |
923 | u32 rx_resource_errors; | |
924 | u32 rx_overruns; | |
925 | u32 rx_ip_header_checksum_errors; | |
926 | u32 rx_tcp_checksum_errors; | |
927 | u32 rx_udp_checksum_errors; | |
928 | }; | |
929 | ||
3ff13f1c XH |
930 | /* Describes the name and offset of an individual statistic register, as |
931 | * returned by `ethtool -S`. Also describes which net_device_stats statistics | |
932 | * this register should contribute to. | |
933 | */ | |
934 | struct gem_statistic { | |
935 | char stat_string[ETH_GSTRING_LEN]; | |
936 | int offset; | |
937 | u32 stat_bits; | |
938 | }; | |
939 | ||
940 | /* Bitfield defs for net_device_stat statistics */ | |
941 | #define GEM_NDS_RXERR_OFFSET 0 | |
942 | #define GEM_NDS_RXLENERR_OFFSET 1 | |
943 | #define GEM_NDS_RXOVERERR_OFFSET 2 | |
944 | #define GEM_NDS_RXCRCERR_OFFSET 3 | |
945 | #define GEM_NDS_RXFRAMEERR_OFFSET 4 | |
946 | #define GEM_NDS_RXFIFOERR_OFFSET 5 | |
947 | #define GEM_NDS_TXERR_OFFSET 6 | |
948 | #define GEM_NDS_TXABORTEDERR_OFFSET 7 | |
949 | #define GEM_NDS_TXCARRIERERR_OFFSET 8 | |
950 | #define GEM_NDS_TXFIFOERR_OFFSET 9 | |
951 | #define GEM_NDS_COLLISIONS_OFFSET 10 | |
952 | ||
953 | #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0) | |
954 | #define GEM_STAT_TITLE_BITS(name, title, bits) { \ | |
955 | .stat_string = title, \ | |
956 | .offset = GEM_##name, \ | |
957 | .stat_bits = bits \ | |
958 | } | |
959 | ||
960 | /* list of gem statistic registers. The names MUST match the | |
961 | * corresponding GEM_* definitions. | |
962 | */ | |
963 | static const struct gem_statistic gem_statistics[] = { | |
964 | GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */ | |
965 | GEM_STAT_TITLE(TXCNT, "tx_frames"), | |
966 | GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"), | |
967 | GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"), | |
968 | GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"), | |
969 | GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"), | |
970 | GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"), | |
971 | GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"), | |
972 | GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"), | |
973 | GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"), | |
974 | GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"), | |
975 | GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"), | |
976 | GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun", | |
977 | GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)), | |
978 | GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames", | |
979 | GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), | |
980 | GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames", | |
981 | GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), | |
982 | GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions", | |
983 | GEM_BIT(NDS_TXERR)| | |
984 | GEM_BIT(NDS_TXABORTEDERR)| | |
985 | GEM_BIT(NDS_COLLISIONS)), | |
986 | GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions", | |
987 | GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), | |
988 | GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"), | |
989 | GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors", | |
990 | GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), | |
991 | GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */ | |
992 | GEM_STAT_TITLE(RXCNT, "rx_frames"), | |
993 | GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"), | |
994 | GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"), | |
995 | GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"), | |
996 | GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"), | |
997 | GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"), | |
998 | GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"), | |
999 | GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"), | |
1000 | GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"), | |
1001 | GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"), | |
1002 | GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"), | |
1003 | GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames", | |
1004 | GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), | |
1005 | GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames", | |
1006 | GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), | |
1007 | GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers", | |
1008 | GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), | |
1009 | GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors", | |
1010 | GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)), | |
1011 | GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors", | |
1012 | GEM_BIT(NDS_RXERR)), | |
1013 | GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors", | |
1014 | GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)), | |
1015 | GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors", | |
1016 | GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), | |
1017 | GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors", | |
1018 | GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), | |
1019 | GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns", | |
1020 | GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)), | |
1021 | GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors", | |
1022 | GEM_BIT(NDS_RXERR)), | |
1023 | GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors", | |
1024 | GEM_BIT(NDS_RXERR)), | |
1025 | GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors", | |
1026 | GEM_BIT(NDS_RXERR)), | |
1027 | }; | |
1028 | ||
1029 | #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics) | |
1030 | ||
512286bb RO |
1031 | #define QUEUE_STAT_TITLE(title) { \ |
1032 | .stat_string = title, \ | |
1033 | } | |
1034 | ||
1035 | /* per queue statistics, each should be unsigned long type */ | |
1036 | struct queue_stats { | |
1037 | union { | |
1038 | unsigned long first; | |
1039 | unsigned long rx_packets; | |
1040 | }; | |
1041 | unsigned long rx_bytes; | |
1042 | unsigned long rx_dropped; | |
1043 | unsigned long tx_packets; | |
1044 | unsigned long tx_bytes; | |
1045 | unsigned long tx_dropped; | |
1046 | }; | |
1047 | ||
1048 | static const struct gem_statistic queue_statistics[] = { | |
1049 | QUEUE_STAT_TITLE("rx_packets"), | |
1050 | QUEUE_STAT_TITLE("rx_bytes"), | |
1051 | QUEUE_STAT_TITLE("rx_dropped"), | |
1052 | QUEUE_STAT_TITLE("tx_packets"), | |
1053 | QUEUE_STAT_TITLE("tx_bytes"), | |
1054 | QUEUE_STAT_TITLE("tx_dropped"), | |
1055 | }; | |
1056 | ||
1057 | #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics) | |
1058 | ||
4df95131 | 1059 | struct macb; |
ae1f2a56 | 1060 | struct macb_queue; |
4df95131 NF |
1061 | |
1062 | struct macb_or_gem_ops { | |
1063 | int (*mog_alloc_rx_buffers)(struct macb *bp); | |
1064 | void (*mog_free_rx_buffers)(struct macb *bp); | |
1065 | void (*mog_init_rings)(struct macb *bp); | |
ae1f2a56 | 1066 | int (*mog_rx)(struct macb_queue *queue, int budget); |
4df95131 NF |
1067 | }; |
1068 | ||
c2594d80 AP |
1069 | /* MACB-PTP interface: adapt to platform needs. */ |
1070 | struct macb_ptp_info { | |
1071 | void (*ptp_init)(struct net_device *ndev); | |
1072 | void (*ptp_remove)(struct net_device *ndev); | |
1073 | s32 (*get_ptp_max_adj)(void); | |
1074 | unsigned int (*get_tsu_rate)(struct macb *bp); | |
1075 | int (*get_ts_info)(struct net_device *dev, | |
1076 | struct ethtool_ts_info *info); | |
1077 | int (*get_hwtst)(struct net_device *netdev, | |
1078 | struct ifreq *ifr); | |
1079 | int (*set_hwtst)(struct net_device *netdev, | |
1080 | struct ifreq *ifr, int cmd); | |
1081 | }; | |
1082 | ||
c1e85c6c CB |
1083 | struct macb_pm_data { |
1084 | u32 scrt2; | |
1085 | u32 usrio; | |
1086 | }; | |
1087 | ||
e175587f NF |
1088 | struct macb_config { |
1089 | u32 caps; | |
1090 | unsigned int dma_burst_length; | |
c69618b3 | 1091 | int (*clk_init)(struct platform_device *pdev, struct clk **pclk, |
aead88bd | 1092 | struct clk **hclk, struct clk **tx_clk, |
f5473d1d | 1093 | struct clk **rx_clk, struct clk **tsu_clk); |
421d9df0 | 1094 | int (*init)(struct platform_device *pdev); |
98b5a0f4 | 1095 | int jumbo_max_len; |
e175587f NF |
1096 | }; |
1097 | ||
ab91f0a9 RO |
1098 | struct tsu_incr { |
1099 | u32 sub_ns; | |
1100 | u32 ns; | |
1101 | }; | |
1102 | ||
02c958dd CP |
1103 | struct macb_queue { |
1104 | struct macb *bp; | |
1105 | int irq; | |
1106 | ||
1107 | unsigned int ISR; | |
1108 | unsigned int IER; | |
1109 | unsigned int IDR; | |
1110 | unsigned int IMR; | |
1111 | unsigned int TBQP; | |
fff8019a | 1112 | unsigned int TBQPH; |
ae1f2a56 RO |
1113 | unsigned int RBQS; |
1114 | unsigned int RBQP; | |
1115 | unsigned int RBQPH; | |
02c958dd CP |
1116 | |
1117 | unsigned int tx_head, tx_tail; | |
1118 | struct macb_dma_desc *tx_ring; | |
1119 | struct macb_tx_skb *tx_skb; | |
1120 | dma_addr_t tx_ring_dma; | |
1121 | struct work_struct tx_error_task; | |
ab91f0a9 | 1122 | |
ae1f2a56 RO |
1123 | dma_addr_t rx_ring_dma; |
1124 | dma_addr_t rx_buffers_dma; | |
1125 | unsigned int rx_tail; | |
1126 | unsigned int rx_prepared_head; | |
1127 | struct macb_dma_desc *rx_ring; | |
1128 | struct sk_buff **rx_skbuff; | |
1129 | void *rx_buffers; | |
1130 | struct napi_struct napi; | |
512286bb | 1131 | struct queue_stats stats; |
ae1f2a56 | 1132 | |
ab91f0a9 RO |
1133 | #ifdef CONFIG_MACB_USE_HWSTAMP |
1134 | struct work_struct tx_ts_task; | |
1135 | unsigned int tx_ts_head, tx_ts_tail; | |
1136 | struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE]; | |
1137 | #endif | |
02c958dd CP |
1138 | }; |
1139 | ||
ae8223de RO |
1140 | struct ethtool_rx_fs_item { |
1141 | struct ethtool_rx_flow_spec fs; | |
1142 | struct list_head list; | |
1143 | }; | |
1144 | ||
1145 | struct ethtool_rx_fs_list { | |
1146 | struct list_head list; | |
1147 | unsigned int count; | |
1148 | }; | |
1149 | ||
89e5785f HS |
1150 | struct macb { |
1151 | void __iomem *regs; | |
f2ce8a9e AS |
1152 | bool native_io; |
1153 | ||
1154 | /* hardware IO accessors */ | |
7a6e0706 DM |
1155 | u32 (*macb_reg_readl)(struct macb *bp, int offset); |
1156 | void (*macb_reg_writel)(struct macb *bp, int offset, u32 value); | |
89e5785f | 1157 | |
1b44791a | 1158 | size_t rx_buffer_size; |
89e5785f | 1159 | |
b410d13e ZB |
1160 | unsigned int rx_ring_size; |
1161 | unsigned int tx_ring_size; | |
1162 | ||
02c958dd | 1163 | unsigned int num_queues; |
bfa0914a | 1164 | unsigned int queue_mask; |
02c958dd | 1165 | struct macb_queue queues[MACB_MAX_QUEUES]; |
89e5785f HS |
1166 | |
1167 | spinlock_t lock; | |
1168 | struct platform_device *pdev; | |
1169 | struct clk *pclk; | |
1170 | struct clk *hclk; | |
e1824dfe | 1171 | struct clk *tx_clk; |
aead88bd | 1172 | struct clk *rx_clk; |
f5473d1d | 1173 | struct clk *tsu_clk; |
89e5785f | 1174 | struct net_device *dev; |
a494ed8e JI |
1175 | union { |
1176 | struct macb_stats macb; | |
1177 | struct gem_stats gem; | |
1178 | } hw_stats; | |
89e5785f | 1179 | |
4df95131 NF |
1180 | struct macb_or_gem_ops macbgem_ops; |
1181 | ||
298cf9be | 1182 | struct mii_bus *mii_bus; |
dacdbb4d | 1183 | struct device_node *phy_node; |
8bcbf82f AS |
1184 | int link; |
1185 | int speed; | |
1186 | int duplex; | |
fb97a846 | 1187 | |
581df9e1 | 1188 | u32 caps; |
e175587f | 1189 | unsigned int dma_burst_length; |
581df9e1 | 1190 | |
fb97a846 | 1191 | phy_interface_t phy_interface; |
b85008b7 | 1192 | |
4dda6f6d | 1193 | /* AT91RM9200 transmit */ |
b85008b7 JE |
1194 | struct sk_buff *skb; /* holds skb until xmit interrupt completes */ |
1195 | dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ | |
1196 | int skb_length; /* saved skb length for pci_unmap_single */ | |
a4c35ed3 | 1197 | unsigned int max_tx_length; |
3ff13f1c | 1198 | |
512286bb | 1199 | u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES]; |
98b5a0f4 HK |
1200 | |
1201 | unsigned int rx_frm_len_mask; | |
1202 | unsigned int jumbo_max_len; | |
3e2a5e15 SP |
1203 | |
1204 | u32 wol; | |
c2594d80 AP |
1205 | |
1206 | struct macb_ptp_info *ptp_info; /* macb-ptp interface */ | |
7b429614 RO |
1207 | #ifdef MACB_EXT_DESC |
1208 | uint8_t hw_dma_cap; | |
dc97a89e | 1209 | #endif |
ab91f0a9 RO |
1210 | spinlock_t tsu_clk_lock; /* gem tsu clock locking */ |
1211 | unsigned int tsu_rate; | |
1212 | struct ptp_clock *ptp_clock; | |
1213 | struct ptp_clock_info ptp_clock_info; | |
1214 | struct tsu_incr tsu_incr; | |
1215 | struct hwtstamp_config tstamp_config; | |
ae8223de RO |
1216 | |
1217 | /* RX queue filer rule set*/ | |
1218 | struct ethtool_rx_fs_list rx_fs_list; | |
1219 | spinlock_t rx_fs_lock; | |
1220 | unsigned int max_tuples; | |
032dc41b HK |
1221 | |
1222 | struct tasklet_struct hresp_err_tasklet; | |
404cd086 HK |
1223 | |
1224 | int rx_bd_rd_prefetch; | |
1225 | int tx_bd_rd_prefetch; | |
e501070e HK |
1226 | |
1227 | u32 rx_intr_mask; | |
c1e85c6c CB |
1228 | |
1229 | struct macb_pm_data pm_data; | |
89e5785f HS |
1230 | }; |
1231 | ||
ab91f0a9 RO |
1232 | #ifdef CONFIG_MACB_USE_HWSTAMP |
1233 | #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE) | |
1234 | #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1) | |
1235 | #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1) | |
1236 | ||
1237 | enum macb_bd_control { | |
1238 | TSTAMP_DISABLED, | |
1239 | TSTAMP_FRAME_PTP_EVENT_ONLY, | |
1240 | TSTAMP_ALL_PTP_FRAMES, | |
1241 | TSTAMP_ALL_FRAMES, | |
1242 | }; | |
1243 | ||
1244 | void gem_ptp_init(struct net_device *ndev); | |
1245 | void gem_ptp_remove(struct net_device *ndev); | |
1246 | int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des); | |
1247 | void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc); | |
1248 | static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc) | |
1249 | { | |
1250 | if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED) | |
1251 | return -ENOTSUPP; | |
1252 | ||
1253 | return gem_ptp_txstamp(queue, skb, desc); | |
1254 | } | |
1255 | ||
1256 | static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) | |
1257 | { | |
1258 | if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED) | |
1259 | return; | |
1260 | ||
1261 | gem_ptp_rxstamp(bp, skb, desc); | |
1262 | } | |
1263 | int gem_get_hwtst(struct net_device *dev, struct ifreq *rq); | |
1264 | int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd); | |
1265 | #else | |
1266 | static inline void gem_ptp_init(struct net_device *ndev) { } | |
1267 | static inline void gem_ptp_remove(struct net_device *ndev) { } | |
1268 | ||
1269 | static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc) | |
1270 | { | |
1271 | return -1; | |
1272 | } | |
1273 | ||
1274 | static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { } | |
1275 | #endif | |
1276 | ||
f75ba50b JI |
1277 | static inline bool macb_is_gem(struct macb *bp) |
1278 | { | |
e175587f | 1279 | return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); |
f75ba50b JI |
1280 | } |
1281 | ||
c2594d80 AP |
1282 | static inline bool gem_has_ptp(struct macb *bp) |
1283 | { | |
1284 | return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP); | |
1285 | } | |
1286 | ||
89e5785f | 1287 | #endif /* _MACB_H */ |