]>
Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
89e5785f | 2 | /* |
f75ba50b | 3 | * Cadence MACB/GEM Ethernet Controller driver |
89e5785f HS |
4 | * |
5 | * Copyright (C) 2004-2006 Atmel Corporation | |
89e5785f HS |
6 | */ |
7 | ||
c220f8cd | 8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
89e5785f | 9 | #include <linux/clk.h> |
c218ad55 | 10 | #include <linux/clk-provider.h> |
653e92a9 | 11 | #include <linux/crc32.h> |
89e5785f HS |
12 | #include <linux/module.h> |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/types.h> | |
909a8583 | 16 | #include <linux/circ_buf.h> |
89e5785f HS |
17 | #include <linux/slab.h> |
18 | #include <linux/init.h> | |
60fe716f | 19 | #include <linux/io.h> |
2dbfdbb9 | 20 | #include <linux/gpio.h> |
270c499f | 21 | #include <linux/gpio/consumer.h> |
a6b7a407 | 22 | #include <linux/interrupt.h> |
89e5785f HS |
23 | #include <linux/netdevice.h> |
24 | #include <linux/etherdevice.h> | |
89e5785f | 25 | #include <linux/dma-mapping.h> |
84e0cdb0 | 26 | #include <linux/platform_data/macb.h> |
89e5785f | 27 | #include <linux/platform_device.h> |
7897b071 | 28 | #include <linux/phylink.h> |
b17471f5 | 29 | #include <linux/of.h> |
fb97a846 | 30 | #include <linux/of_device.h> |
270c499f | 31 | #include <linux/of_gpio.h> |
148cbb53 | 32 | #include <linux/of_mdio.h> |
fb97a846 | 33 | #include <linux/of_net.h> |
1629dd4f RO |
34 | #include <linux/ip.h> |
35 | #include <linux/udp.h> | |
36 | #include <linux/tcp.h> | |
8beb79b7 | 37 | #include <linux/iopoll.h> |
d54f89af | 38 | #include <linux/pm_runtime.h> |
89e5785f HS |
39 | #include "macb.h" |
40 | ||
c218ad55 YS |
41 | /* This structure is only used for MACB on SiFive FU540 devices */ |
42 | struct sifive_fu540_macb_mgmt { | |
43 | void __iomem *reg; | |
44 | unsigned long rate; | |
45 | struct clk_hw hw; | |
46 | }; | |
47 | ||
1b44791a | 48 | #define MACB_RX_BUFFER_SIZE 128 |
1b44791a | 49 | #define RX_BUFFER_MULTIPLE 64 /* bytes */ |
8441bb33 | 50 | |
b410d13e | 51 | #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */ |
8441bb33 ZB |
52 | #define MIN_RX_RING_SIZE 64 |
53 | #define MAX_RX_RING_SIZE 8192 | |
dc97a89e | 54 | #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \ |
b410d13e | 55 | * (bp)->rx_ring_size) |
89e5785f | 56 | |
b410d13e | 57 | #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */ |
8441bb33 ZB |
58 | #define MIN_TX_RING_SIZE 64 |
59 | #define MAX_TX_RING_SIZE 4096 | |
dc97a89e | 60 | #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \ |
b410d13e | 61 | * (bp)->tx_ring_size) |
89e5785f | 62 | |
909a8583 | 63 | /* level of occupied TX descriptors under which we wake up TX process */ |
b410d13e | 64 | #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4) |
89e5785f | 65 | |
e501070e | 66 | #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR)) |
e86cd53a NF |
67 | #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ |
68 | | MACB_BIT(ISR_RLE) \ | |
69 | | MACB_BIT(TXERR)) | |
42983885 CB |
70 | #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \ |
71 | | MACB_BIT(TXUBR)) | |
e86cd53a | 72 | |
1629dd4f RO |
73 | /* Max length of transmit frame must be a multiple of 8 bytes */ |
74 | #define MACB_TX_LEN_ALIGN 8 | |
75 | #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1))) | |
76 | #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1))) | |
a4c35ed3 | 77 | |
44770e11 | 78 | #define GEM_MTU_MIN_SIZE ETH_MIN_MTU |
f9c45ae0 | 79 | #define MACB_NETIF_LSO NETIF_F_TSO |
a5898ea0 | 80 | |
3e2a5e15 SP |
81 | #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0) |
82 | #define MACB_WOL_ENABLED (0x1 << 1) | |
83 | ||
64ec42fe | 84 | /* Graceful stop timeouts in us. We should allow up to |
e86cd53a NF |
85 | * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) |
86 | */ | |
87 | #define MACB_HALT_TIMEOUT 1230 | |
89e5785f | 88 | |
d54f89af HK |
89 | #define MACB_PM_TIMEOUT 100 /* ms */ |
90 | ||
8beb79b7 HK |
91 | #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */ |
92 | ||
dc97a89e | 93 | /* DMA buffer descriptor might be different size |
7b429614 RO |
94 | * depends on hardware configuration: |
95 | * | |
96 | * 1. dma address width 32 bits: | |
97 | * word 1: 32 bit address of Data Buffer | |
98 | * word 2: control | |
99 | * | |
100 | * 2. dma address width 64 bits: | |
101 | * word 1: 32 bit address of Data Buffer | |
102 | * word 2: control | |
103 | * word 3: upper 32 bit address of Data Buffer | |
104 | * word 4: unused | |
105 | * | |
106 | * 3. dma address width 32 bits with hardware timestamping: | |
107 | * word 1: 32 bit address of Data Buffer | |
108 | * word 2: control | |
109 | * word 3: timestamp word 1 | |
110 | * word 4: timestamp word 2 | |
111 | * | |
112 | * 4. dma address width 64 bits with hardware timestamping: | |
113 | * word 1: 32 bit address of Data Buffer | |
114 | * word 2: control | |
115 | * word 3: upper 32 bit address of Data Buffer | |
116 | * word 4: unused | |
117 | * word 5: timestamp word 1 | |
118 | * word 6: timestamp word 2 | |
dc97a89e RO |
119 | */ |
120 | static unsigned int macb_dma_desc_get_size(struct macb *bp) | |
121 | { | |
7b429614 RO |
122 | #ifdef MACB_EXT_DESC |
123 | unsigned int desc_size; | |
124 | ||
125 | switch (bp->hw_dma_cap) { | |
126 | case HW_DMA_CAP_64B: | |
127 | desc_size = sizeof(struct macb_dma_desc) | |
128 | + sizeof(struct macb_dma_desc_64); | |
129 | break; | |
130 | case HW_DMA_CAP_PTP: | |
131 | desc_size = sizeof(struct macb_dma_desc) | |
132 | + sizeof(struct macb_dma_desc_ptp); | |
133 | break; | |
134 | case HW_DMA_CAP_64B_PTP: | |
135 | desc_size = sizeof(struct macb_dma_desc) | |
136 | + sizeof(struct macb_dma_desc_64) | |
137 | + sizeof(struct macb_dma_desc_ptp); | |
138 | break; | |
139 | default: | |
140 | desc_size = sizeof(struct macb_dma_desc); | |
141 | } | |
142 | return desc_size; | |
dc97a89e RO |
143 | #endif |
144 | return sizeof(struct macb_dma_desc); | |
145 | } | |
146 | ||
7b429614 | 147 | static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx) |
dc97a89e | 148 | { |
7b429614 RO |
149 | #ifdef MACB_EXT_DESC |
150 | switch (bp->hw_dma_cap) { | |
151 | case HW_DMA_CAP_64B: | |
152 | case HW_DMA_CAP_PTP: | |
153 | desc_idx <<= 1; | |
154 | break; | |
155 | case HW_DMA_CAP_64B_PTP: | |
156 | desc_idx *= 3; | |
157 | break; | |
158 | default: | |
159 | break; | |
160 | } | |
dc97a89e | 161 | #endif |
7b429614 | 162 | return desc_idx; |
dc97a89e RO |
163 | } |
164 | ||
165 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
166 | static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc) | |
167 | { | |
99dcb843 SD |
168 | return (struct macb_dma_desc_64 *)((void *)desc |
169 | + sizeof(struct macb_dma_desc)); | |
dc97a89e RO |
170 | } |
171 | #endif | |
172 | ||
55054a16 | 173 | /* Ring buffer accessors */ |
b410d13e | 174 | static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index) |
55054a16 | 175 | { |
b410d13e | 176 | return index & (bp->tx_ring_size - 1); |
55054a16 HS |
177 | } |
178 | ||
02c958dd CP |
179 | static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue, |
180 | unsigned int index) | |
55054a16 | 181 | { |
dc97a89e RO |
182 | index = macb_tx_ring_wrap(queue->bp, index); |
183 | index = macb_adj_dma_desc_idx(queue->bp, index); | |
184 | return &queue->tx_ring[index]; | |
55054a16 HS |
185 | } |
186 | ||
02c958dd CP |
187 | static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue, |
188 | unsigned int index) | |
55054a16 | 189 | { |
b410d13e | 190 | return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)]; |
55054a16 HS |
191 | } |
192 | ||
02c958dd | 193 | static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index) |
55054a16 HS |
194 | { |
195 | dma_addr_t offset; | |
196 | ||
b410d13e | 197 | offset = macb_tx_ring_wrap(queue->bp, index) * |
dc97a89e | 198 | macb_dma_desc_get_size(queue->bp); |
55054a16 | 199 | |
02c958dd | 200 | return queue->tx_ring_dma + offset; |
55054a16 HS |
201 | } |
202 | ||
b410d13e | 203 | static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index) |
55054a16 | 204 | { |
b410d13e | 205 | return index & (bp->rx_ring_size - 1); |
55054a16 HS |
206 | } |
207 | ||
ae1f2a56 | 208 | static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index) |
55054a16 | 209 | { |
ae1f2a56 RO |
210 | index = macb_rx_ring_wrap(queue->bp, index); |
211 | index = macb_adj_dma_desc_idx(queue->bp, index); | |
212 | return &queue->rx_ring[index]; | |
55054a16 HS |
213 | } |
214 | ||
ae1f2a56 | 215 | static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index) |
55054a16 | 216 | { |
ae1f2a56 RO |
217 | return queue->rx_buffers + queue->bp->rx_buffer_size * |
218 | macb_rx_ring_wrap(queue->bp, index); | |
55054a16 HS |
219 | } |
220 | ||
f2ce8a9e AS |
221 | /* I/O accessors */ |
222 | static u32 hw_readl_native(struct macb *bp, int offset) | |
223 | { | |
224 | return __raw_readl(bp->regs + offset); | |
225 | } | |
226 | ||
227 | static void hw_writel_native(struct macb *bp, int offset, u32 value) | |
228 | { | |
229 | __raw_writel(value, bp->regs + offset); | |
230 | } | |
231 | ||
232 | static u32 hw_readl(struct macb *bp, int offset) | |
233 | { | |
234 | return readl_relaxed(bp->regs + offset); | |
235 | } | |
236 | ||
237 | static void hw_writel(struct macb *bp, int offset, u32 value) | |
238 | { | |
239 | writel_relaxed(value, bp->regs + offset); | |
240 | } | |
241 | ||
64ec42fe | 242 | /* Find the CPU endianness by using the loopback bit of NCR register. When the |
88023beb | 243 | * CPU is in big endian we need to program swapped mode for management |
f2ce8a9e AS |
244 | * descriptor access. |
245 | */ | |
246 | static bool hw_is_native_io(void __iomem *addr) | |
247 | { | |
248 | u32 value = MACB_BIT(LLB); | |
249 | ||
250 | __raw_writel(value, addr + MACB_NCR); | |
251 | value = __raw_readl(addr + MACB_NCR); | |
252 | ||
253 | /* Write 0 back to disable everything */ | |
254 | __raw_writel(0, addr + MACB_NCR); | |
255 | ||
256 | return value == MACB_BIT(LLB); | |
257 | } | |
258 | ||
259 | static bool hw_is_gem(void __iomem *addr, bool native_io) | |
260 | { | |
261 | u32 id; | |
262 | ||
263 | if (native_io) | |
264 | id = __raw_readl(addr + MACB_MID); | |
265 | else | |
266 | id = readl_relaxed(addr + MACB_MID); | |
267 | ||
268 | return MACB_BFEXT(IDNUM, id) >= 0x2; | |
269 | } | |
270 | ||
421d9df0 | 271 | static void macb_set_hwaddr(struct macb *bp) |
89e5785f HS |
272 | { |
273 | u32 bottom; | |
274 | u16 top; | |
275 | ||
276 | bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); | |
f75ba50b | 277 | macb_or_gem_writel(bp, SA1B, bottom); |
89e5785f | 278 | top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); |
f75ba50b | 279 | macb_or_gem_writel(bp, SA1T, top); |
3629a6ce JE |
280 | |
281 | /* Clear unused address register sets */ | |
282 | macb_or_gem_writel(bp, SA2B, 0); | |
283 | macb_or_gem_writel(bp, SA2T, 0); | |
284 | macb_or_gem_writel(bp, SA3B, 0); | |
285 | macb_or_gem_writel(bp, SA3T, 0); | |
286 | macb_or_gem_writel(bp, SA4B, 0); | |
287 | macb_or_gem_writel(bp, SA4T, 0); | |
89e5785f HS |
288 | } |
289 | ||
421d9df0 | 290 | static void macb_get_hwaddr(struct macb *bp) |
89e5785f HS |
291 | { |
292 | u32 bottom; | |
293 | u16 top; | |
294 | u8 addr[6]; | |
17b8bb3e JE |
295 | int i; |
296 | ||
aa50b552 | 297 | /* Check all 4 address register for valid address */ |
17b8bb3e JE |
298 | for (i = 0; i < 4; i++) { |
299 | bottom = macb_or_gem_readl(bp, SA1B + i * 8); | |
300 | top = macb_or_gem_readl(bp, SA1T + i * 8); | |
301 | ||
8b952747 NF |
302 | addr[0] = bottom & 0xff; |
303 | addr[1] = (bottom >> 8) & 0xff; | |
304 | addr[2] = (bottom >> 16) & 0xff; | |
305 | addr[3] = (bottom >> 24) & 0xff; | |
306 | addr[4] = top & 0xff; | |
307 | addr[5] = (top >> 8) & 0xff; | |
17b8bb3e JE |
308 | |
309 | if (is_valid_ether_addr(addr)) { | |
310 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); | |
311 | return; | |
312 | } | |
d1d5741d | 313 | } |
17b8bb3e | 314 | |
a35919e1 | 315 | dev_info(&bp->pdev->dev, "invalid hw address, using random\n"); |
17b8bb3e | 316 | eth_hw_addr_random(bp->dev); |
89e5785f HS |
317 | } |
318 | ||
8beb79b7 HK |
319 | static int macb_mdio_wait_for_idle(struct macb *bp) |
320 | { | |
321 | u32 val; | |
322 | ||
323 | return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE), | |
324 | 1, MACB_MDIO_TIMEOUT); | |
325 | } | |
326 | ||
6c36a707 | 327 | static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
89e5785f | 328 | { |
6c36a707 | 329 | struct macb *bp = bus->priv; |
d54f89af | 330 | int status; |
8beb79b7 | 331 | |
d54f89af HK |
332 | status = pm_runtime_get_sync(&bp->pdev->dev); |
333 | if (status < 0) | |
334 | goto mdio_pm_exit; | |
335 | ||
336 | status = macb_mdio_wait_for_idle(bp); | |
337 | if (status < 0) | |
338 | goto mdio_read_exit; | |
89e5785f | 339 | |
89e5785f HS |
340 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) |
341 | | MACB_BF(RW, MACB_MAN_READ) | |
6c36a707 R |
342 | | MACB_BF(PHYA, mii_id) |
343 | | MACB_BF(REGA, regnum) | |
89e5785f HS |
344 | | MACB_BF(CODE, MACB_MAN_CODE))); |
345 | ||
d54f89af HK |
346 | status = macb_mdio_wait_for_idle(bp); |
347 | if (status < 0) | |
348 | goto mdio_read_exit; | |
89e5785f | 349 | |
d54f89af | 350 | status = MACB_BFEXT(DATA, macb_readl(bp, MAN)); |
89e5785f | 351 | |
d54f89af HK |
352 | mdio_read_exit: |
353 | pm_runtime_mark_last_busy(&bp->pdev->dev); | |
354 | pm_runtime_put_autosuspend(&bp->pdev->dev); | |
355 | mdio_pm_exit: | |
356 | return status; | |
89e5785f HS |
357 | } |
358 | ||
6c36a707 R |
359 | static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
360 | u16 value) | |
89e5785f | 361 | { |
6c36a707 | 362 | struct macb *bp = bus->priv; |
d54f89af | 363 | int status; |
8beb79b7 | 364 | |
d54f89af HK |
365 | status = pm_runtime_get_sync(&bp->pdev->dev); |
366 | if (status < 0) | |
367 | goto mdio_pm_exit; | |
368 | ||
369 | status = macb_mdio_wait_for_idle(bp); | |
370 | if (status < 0) | |
371 | goto mdio_write_exit; | |
89e5785f HS |
372 | |
373 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) | |
374 | | MACB_BF(RW, MACB_MAN_WRITE) | |
6c36a707 R |
375 | | MACB_BF(PHYA, mii_id) |
376 | | MACB_BF(REGA, regnum) | |
89e5785f | 377 | | MACB_BF(CODE, MACB_MAN_CODE) |
6c36a707 | 378 | | MACB_BF(DATA, value))); |
89e5785f | 379 | |
d54f89af HK |
380 | status = macb_mdio_wait_for_idle(bp); |
381 | if (status < 0) | |
382 | goto mdio_write_exit; | |
6c36a707 | 383 | |
d54f89af HK |
384 | mdio_write_exit: |
385 | pm_runtime_mark_last_busy(&bp->pdev->dev); | |
386 | pm_runtime_put_autosuspend(&bp->pdev->dev); | |
387 | mdio_pm_exit: | |
388 | return status; | |
6c36a707 | 389 | } |
89e5785f | 390 | |
6e952d95 AT |
391 | static void macb_init_buffers(struct macb *bp) |
392 | { | |
393 | struct macb_queue *queue; | |
394 | unsigned int q; | |
395 | ||
396 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { | |
397 | queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma)); | |
398 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
399 | if (bp->hw_dma_cap & HW_DMA_CAP_64B) | |
400 | queue_writel(queue, RBQPH, | |
401 | upper_32_bits(queue->rx_ring_dma)); | |
402 | #endif | |
403 | queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); | |
404 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
405 | if (bp->hw_dma_cap & HW_DMA_CAP_64B) | |
406 | queue_writel(queue, TBQPH, | |
407 | upper_32_bits(queue->tx_ring_dma)); | |
408 | #endif | |
409 | } | |
410 | } | |
411 | ||
e1824dfe SB |
412 | /** |
413 | * macb_set_tx_clk() - Set a clock to a new frequency | |
414 | * @clk Pointer to the clock to change | |
415 | * @rate New frequency in Hz | |
416 | * @dev Pointer to the struct net_device | |
417 | */ | |
418 | static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) | |
419 | { | |
420 | long ferr, rate, rate_rounded; | |
421 | ||
93b31f48 CP |
422 | if (!clk) |
423 | return; | |
424 | ||
e1824dfe SB |
425 | switch (speed) { |
426 | case SPEED_10: | |
427 | rate = 2500000; | |
428 | break; | |
429 | case SPEED_100: | |
430 | rate = 25000000; | |
431 | break; | |
432 | case SPEED_1000: | |
433 | rate = 125000000; | |
434 | break; | |
435 | default: | |
9319e47c | 436 | return; |
e1824dfe SB |
437 | } |
438 | ||
439 | rate_rounded = clk_round_rate(clk, rate); | |
440 | if (rate_rounded < 0) | |
441 | return; | |
442 | ||
443 | /* RGMII allows 50 ppm frequency error. Test and warn if this limit | |
444 | * is not satisfied. | |
445 | */ | |
446 | ferr = abs(rate_rounded - rate); | |
447 | ferr = DIV_ROUND_UP(ferr, rate / 100000); | |
448 | if (ferr > 5) | |
449 | netdev_warn(dev, "unable to generate target frequency: %ld Hz\n", | |
aa50b552 | 450 | rate); |
e1824dfe SB |
451 | |
452 | if (clk_set_rate(clk, rate_rounded)) | |
453 | netdev_err(dev, "adjusting tx_clk failed.\n"); | |
454 | } | |
455 | ||
7897b071 AT |
456 | static void macb_validate(struct phylink_config *config, |
457 | unsigned long *supported, | |
458 | struct phylink_link_state *state) | |
89e5785f | 459 | { |
7897b071 AT |
460 | struct net_device *ndev = to_net_dev(config->dev); |
461 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; | |
462 | struct macb *bp = netdev_priv(ndev); | |
463 | ||
464 | /* We only support MII, RMII, GMII, RGMII & SGMII. */ | |
465 | if (state->interface != PHY_INTERFACE_MODE_NA && | |
466 | state->interface != PHY_INTERFACE_MODE_MII && | |
467 | state->interface != PHY_INTERFACE_MODE_RMII && | |
468 | state->interface != PHY_INTERFACE_MODE_GMII && | |
469 | state->interface != PHY_INTERFACE_MODE_SGMII && | |
470 | !phy_interface_mode_is_rgmii(state->interface)) { | |
471 | bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
472 | return; | |
473 | } | |
474 | ||
475 | if (!macb_is_gem(bp) && | |
476 | (state->interface == PHY_INTERFACE_MODE_GMII || | |
477 | phy_interface_mode_is_rgmii(state->interface))) { | |
478 | bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
479 | return; | |
480 | } | |
481 | ||
482 | phylink_set_port_modes(mask); | |
483 | phylink_set(mask, Autoneg); | |
484 | phylink_set(mask, Asym_Pause); | |
485 | ||
486 | phylink_set(mask, 10baseT_Half); | |
487 | phylink_set(mask, 10baseT_Full); | |
488 | phylink_set(mask, 100baseT_Half); | |
489 | phylink_set(mask, 100baseT_Full); | |
490 | ||
491 | if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE && | |
492 | (state->interface == PHY_INTERFACE_MODE_NA || | |
493 | state->interface == PHY_INTERFACE_MODE_GMII || | |
494 | state->interface == PHY_INTERFACE_MODE_SGMII || | |
495 | phy_interface_mode_is_rgmii(state->interface))) { | |
496 | phylink_set(mask, 1000baseT_Full); | |
497 | phylink_set(mask, 1000baseX_Full); | |
498 | ||
499 | if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) | |
500 | phylink_set(mask, 1000baseT_Half); | |
501 | } | |
502 | ||
503 | bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
504 | bitmap_and(state->advertising, state->advertising, mask, | |
505 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
506 | } | |
507 | ||
d46b7e4f RK |
508 | static void macb_mac_pcs_get_state(struct phylink_config *config, |
509 | struct phylink_link_state *state) | |
7897b071 | 510 | { |
d46b7e4f | 511 | state->link = 0; |
7897b071 AT |
512 | } |
513 | ||
514 | static void macb_mac_an_restart(struct phylink_config *config) | |
515 | { | |
516 | /* Not supported */ | |
517 | } | |
518 | ||
519 | static void macb_mac_config(struct phylink_config *config, unsigned int mode, | |
520 | const struct phylink_link_state *state) | |
521 | { | |
522 | struct net_device *ndev = to_net_dev(config->dev); | |
523 | struct macb *bp = netdev_priv(ndev); | |
6c36a707 | 524 | unsigned long flags; |
7897b071 | 525 | u32 old_ctrl, ctrl; |
89e5785f | 526 | |
6c36a707 R |
527 | spin_lock_irqsave(&bp->lock, flags); |
528 | ||
7897b071 | 529 | old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR); |
6c36a707 | 530 | |
7897b071 AT |
531 | /* Clear all the bits we might set later */ |
532 | ctrl &= ~(GEM_BIT(GBE) | MACB_BIT(SPD) | MACB_BIT(FD) | MACB_BIT(PAE) | | |
533 | GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL)); | |
6c36a707 | 534 | |
7897b071 AT |
535 | if (state->speed == SPEED_1000) |
536 | ctrl |= GEM_BIT(GBE); | |
537 | else if (state->speed == SPEED_100) | |
538 | ctrl |= MACB_BIT(SPD); | |
6c36a707 | 539 | |
7897b071 AT |
540 | if (state->duplex) |
541 | ctrl |= MACB_BIT(FD); | |
6c36a707 | 542 | |
7897b071 AT |
543 | /* We do not support MLO_PAUSE_RX yet */ |
544 | if (state->pause & MLO_PAUSE_TX) | |
545 | ctrl |= MACB_BIT(PAE); | |
89e5785f | 546 | |
7897b071 AT |
547 | if (state->interface == PHY_INTERFACE_MODE_SGMII) |
548 | ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); | |
89e5785f | 549 | |
7897b071 AT |
550 | /* Apply the new configuration, if any */ |
551 | if (old_ctrl ^ ctrl) | |
552 | macb_or_gem_writel(bp, NCFGR, ctrl); | |
553 | ||
554 | bp->speed = state->speed; | |
89e5785f | 555 | |
6c36a707 | 556 | spin_unlock_irqrestore(&bp->lock, flags); |
7897b071 | 557 | } |
6c36a707 | 558 | |
7897b071 AT |
559 | static void macb_mac_link_down(struct phylink_config *config, unsigned int mode, |
560 | phy_interface_t interface) | |
561 | { | |
562 | struct net_device *ndev = to_net_dev(config->dev); | |
563 | struct macb *bp = netdev_priv(ndev); | |
564 | struct macb_queue *queue; | |
565 | unsigned int q; | |
566 | u32 ctrl; | |
2c29b235 | 567 | |
7897b071 AT |
568 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) |
569 | queue_writel(queue, IDR, | |
570 | bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP)); | |
571 | ||
572 | /* Disable Rx and Tx */ | |
573 | ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE)); | |
574 | macb_writel(bp, NCR, ctrl); | |
575 | ||
576 | netif_tx_stop_all_queues(ndev); | |
89e5785f HS |
577 | } |
578 | ||
7897b071 AT |
579 | static void macb_mac_link_up(struct phylink_config *config, unsigned int mode, |
580 | phy_interface_t interface, struct phy_device *phy) | |
89e5785f | 581 | { |
7897b071 AT |
582 | struct net_device *ndev = to_net_dev(config->dev); |
583 | struct macb *bp = netdev_priv(ndev); | |
584 | struct macb_queue *queue; | |
585 | unsigned int q; | |
739de9a1 | 586 | |
7897b071 | 587 | macb_set_tx_clk(bp->tx_clk, bp->speed, ndev); |
739de9a1 | 588 | |
7897b071 AT |
589 | /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down |
590 | * cleared the pipeline and control registers. | |
591 | */ | |
592 | bp->macbgem_ops.mog_init_rings(bp); | |
593 | macb_init_buffers(bp); | |
739de9a1 | 594 | |
7897b071 AT |
595 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) |
596 | queue_writel(queue, IER, | |
597 | bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP)); | |
6c36a707 | 598 | |
7897b071 AT |
599 | /* Enable Rx and Tx */ |
600 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE)); | |
601 | ||
602 | netif_tx_wake_all_queues(ndev); | |
603 | } | |
604 | ||
605 | static const struct phylink_mac_ops macb_phylink_ops = { | |
606 | .validate = macb_validate, | |
d46b7e4f | 607 | .mac_pcs_get_state = macb_mac_pcs_get_state, |
7897b071 AT |
608 | .mac_an_restart = macb_mac_an_restart, |
609 | .mac_config = macb_mac_config, | |
610 | .mac_link_down = macb_mac_link_down, | |
611 | .mac_link_up = macb_mac_link_up, | |
612 | }; | |
613 | ||
614 | static int macb_phylink_connect(struct macb *bp) | |
615 | { | |
616 | struct net_device *dev = bp->dev; | |
617 | struct phy_device *phydev; | |
618 | int ret; | |
619 | ||
620 | if (bp->pdev->dev.of_node && | |
621 | of_parse_phandle(bp->pdev->dev.of_node, "phy-handle", 0)) { | |
622 | ret = phylink_of_phy_connect(bp->phylink, bp->pdev->dev.of_node, | |
623 | 0); | |
624 | if (ret) { | |
625 | netdev_err(dev, "Could not attach PHY (%d)\n", ret); | |
626 | return ret; | |
627 | } | |
dacdbb4d MG |
628 | } else { |
629 | phydev = phy_find_first(bp->mii_bus); | |
630 | if (!phydev) { | |
631 | netdev_err(dev, "no PHY found\n"); | |
632 | return -ENXIO; | |
633 | } | |
6c36a707 | 634 | |
dacdbb4d | 635 | /* attach the mac to the phy */ |
7897b071 | 636 | ret = phylink_connect_phy(bp->phylink, phydev); |
dacdbb4d | 637 | if (ret) { |
7897b071 | 638 | netdev_err(dev, "Could not attach to PHY (%d)\n", ret); |
dacdbb4d MG |
639 | return ret; |
640 | } | |
6c36a707 R |
641 | } |
642 | ||
7897b071 | 643 | phylink_start(bp->phylink); |
6c36a707 | 644 | |
7897b071 AT |
645 | return 0; |
646 | } | |
6c36a707 | 647 | |
7897b071 AT |
648 | /* based on au1000_eth. c*/ |
649 | static int macb_mii_probe(struct net_device *dev) | |
650 | { | |
651 | struct macb *bp = netdev_priv(dev); | |
652 | ||
653 | bp->phylink_config.dev = &dev->dev; | |
654 | bp->phylink_config.type = PHYLINK_NETDEV; | |
655 | ||
656 | bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode, | |
657 | bp->phy_interface, &macb_phylink_ops); | |
658 | if (IS_ERR(bp->phylink)) { | |
659 | netdev_err(dev, "Could not create a phylink instance (%ld)\n", | |
660 | PTR_ERR(bp->phylink)); | |
661 | return PTR_ERR(bp->phylink); | |
662 | } | |
6c36a707 R |
663 | |
664 | return 0; | |
89e5785f HS |
665 | } |
666 | ||
421d9df0 | 667 | static int macb_mii_init(struct macb *bp) |
89e5785f | 668 | { |
148cbb53 | 669 | struct device_node *np; |
ab5f1105 | 670 | int err = -ENXIO; |
89e5785f | 671 | |
3dbda77e | 672 | /* Enable management port */ |
6c36a707 | 673 | macb_writel(bp, NCR, MACB_BIT(MPE)); |
89e5785f | 674 | |
298cf9be | 675 | bp->mii_bus = mdiobus_alloc(); |
aa50b552 | 676 | if (!bp->mii_bus) { |
298cf9be LB |
677 | err = -ENOMEM; |
678 | goto err_out; | |
679 | } | |
680 | ||
681 | bp->mii_bus->name = "MACB_mii_bus"; | |
682 | bp->mii_bus->read = &macb_mdio_read; | |
683 | bp->mii_bus->write = &macb_mdio_write; | |
98d5e57e | 684 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
aa50b552 | 685 | bp->pdev->name, bp->pdev->id); |
298cf9be | 686 | bp->mii_bus->priv = bp; |
cf669660 | 687 | bp->mii_bus->parent = &bp->pdev->dev; |
89e5785f | 688 | |
91523947 | 689 | dev_set_drvdata(&bp->dev->dev, bp->mii_bus); |
89e5785f | 690 | |
148cbb53 | 691 | np = bp->pdev->dev.of_node; |
dacdbb4d | 692 | |
7897b071 | 693 | err = of_mdiobus_register(bp->mii_bus, np); |
148cbb53 | 694 | if (err) |
7897b071 | 695 | goto err_out_free_mdiobus; |
89e5785f | 696 | |
7daa78e3 BB |
697 | err = macb_mii_probe(bp->dev); |
698 | if (err) | |
6c36a707 | 699 | goto err_out_unregister_bus; |
89e5785f | 700 | |
6c36a707 | 701 | return 0; |
89e5785f | 702 | |
6c36a707 | 703 | err_out_unregister_bus: |
298cf9be | 704 | mdiobus_unregister(bp->mii_bus); |
739de9a1 | 705 | err_out_free_mdiobus: |
298cf9be | 706 | mdiobus_free(bp->mii_bus); |
6c36a707 R |
707 | err_out: |
708 | return err; | |
89e5785f HS |
709 | } |
710 | ||
711 | static void macb_update_stats(struct macb *bp) | |
712 | { | |
a494ed8e JI |
713 | u32 *p = &bp->hw_stats.macb.rx_pause_frames; |
714 | u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; | |
f2ce8a9e | 715 | int offset = MACB_PFR; |
89e5785f HS |
716 | |
717 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | |
718 | ||
96ec6310 | 719 | for (; p < end; p++, offset += 4) |
7a6e0706 | 720 | *p += bp->macb_reg_readl(bp, offset); |
89e5785f HS |
721 | } |
722 | ||
e86cd53a | 723 | static int macb_halt_tx(struct macb *bp) |
89e5785f | 724 | { |
e86cd53a NF |
725 | unsigned long halt_time, timeout; |
726 | u32 status; | |
89e5785f | 727 | |
e86cd53a | 728 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT)); |
89e5785f | 729 | |
e86cd53a NF |
730 | timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT); |
731 | do { | |
732 | halt_time = jiffies; | |
733 | status = macb_readl(bp, TSR); | |
734 | if (!(status & MACB_BIT(TGO))) | |
735 | return 0; | |
89e5785f | 736 | |
16fe10cf | 737 | udelay(250); |
e86cd53a | 738 | } while (time_before(halt_time, timeout)); |
bdcba151 | 739 | |
e86cd53a NF |
740 | return -ETIMEDOUT; |
741 | } | |
39eddb4c | 742 | |
a4c35ed3 CP |
743 | static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb) |
744 | { | |
745 | if (tx_skb->mapping) { | |
746 | if (tx_skb->mapped_as_page) | |
747 | dma_unmap_page(&bp->pdev->dev, tx_skb->mapping, | |
748 | tx_skb->size, DMA_TO_DEVICE); | |
749 | else | |
750 | dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, | |
751 | tx_skb->size, DMA_TO_DEVICE); | |
752 | tx_skb->mapping = 0; | |
753 | } | |
754 | ||
755 | if (tx_skb->skb) { | |
756 | dev_kfree_skb_any(tx_skb->skb); | |
757 | tx_skb->skb = NULL; | |
758 | } | |
759 | } | |
760 | ||
dc97a89e | 761 | static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr) |
fff8019a | 762 | { |
fff8019a | 763 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
dc97a89e RO |
764 | struct macb_dma_desc_64 *desc_64; |
765 | ||
7b429614 | 766 | if (bp->hw_dma_cap & HW_DMA_CAP_64B) { |
dc97a89e RO |
767 | desc_64 = macb_64b_desc(bp, desc); |
768 | desc_64->addrh = upper_32_bits(addr); | |
e100a897 AH |
769 | /* The low bits of RX address contain the RX_USED bit, clearing |
770 | * of which allows packet RX. Make sure the high bits are also | |
771 | * visible to HW at that point. | |
772 | */ | |
773 | dma_wmb(); | |
dc97a89e | 774 | } |
fff8019a | 775 | #endif |
dc97a89e RO |
776 | desc->addr = lower_32_bits(addr); |
777 | } | |
778 | ||
779 | static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc) | |
780 | { | |
781 | dma_addr_t addr = 0; | |
782 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
783 | struct macb_dma_desc_64 *desc_64; | |
784 | ||
7b429614 | 785 | if (bp->hw_dma_cap & HW_DMA_CAP_64B) { |
dc97a89e RO |
786 | desc_64 = macb_64b_desc(bp, desc); |
787 | addr = ((u64)(desc_64->addrh) << 32); | |
788 | } | |
789 | #endif | |
790 | addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); | |
791 | return addr; | |
fff8019a HK |
792 | } |
793 | ||
e86cd53a NF |
794 | static void macb_tx_error_task(struct work_struct *work) |
795 | { | |
02c958dd CP |
796 | struct macb_queue *queue = container_of(work, struct macb_queue, |
797 | tx_error_task); | |
798 | struct macb *bp = queue->bp; | |
e86cd53a | 799 | struct macb_tx_skb *tx_skb; |
02c958dd | 800 | struct macb_dma_desc *desc; |
e86cd53a NF |
801 | struct sk_buff *skb; |
802 | unsigned int tail; | |
02c958dd CP |
803 | unsigned long flags; |
804 | ||
805 | netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n", | |
806 | (unsigned int)(queue - bp->queues), | |
807 | queue->tx_tail, queue->tx_head); | |
bdcba151 | 808 | |
02c958dd CP |
809 | /* Prevent the queue IRQ handlers from running: each of them may call |
810 | * macb_tx_interrupt(), which in turn may call netif_wake_subqueue(). | |
811 | * As explained below, we have to halt the transmission before updating | |
812 | * TBQP registers so we call netif_tx_stop_all_queues() to notify the | |
813 | * network engine about the macb/gem being halted. | |
814 | */ | |
815 | spin_lock_irqsave(&bp->lock, flags); | |
bdcba151 | 816 | |
e86cd53a | 817 | /* Make sure nobody is trying to queue up new packets */ |
02c958dd | 818 | netif_tx_stop_all_queues(bp->dev); |
d3e61457 | 819 | |
64ec42fe | 820 | /* Stop transmission now |
e86cd53a | 821 | * (in case we have just queued new packets) |
02c958dd | 822 | * macb/gem must be halted to write TBQP register |
e86cd53a NF |
823 | */ |
824 | if (macb_halt_tx(bp)) | |
825 | /* Just complain for now, reinitializing TX path can be good */ | |
826 | netdev_err(bp->dev, "BUG: halt tx timed out\n"); | |
bdcba151 | 827 | |
64ec42fe | 828 | /* Treat frames in TX queue including the ones that caused the error. |
e86cd53a NF |
829 | * Free transmit buffers in upper layer. |
830 | */ | |
02c958dd CP |
831 | for (tail = queue->tx_tail; tail != queue->tx_head; tail++) { |
832 | u32 ctrl; | |
55054a16 | 833 | |
02c958dd | 834 | desc = macb_tx_desc(queue, tail); |
e86cd53a | 835 | ctrl = desc->ctrl; |
02c958dd | 836 | tx_skb = macb_tx_skb(queue, tail); |
e86cd53a | 837 | skb = tx_skb->skb; |
bdcba151 | 838 | |
e86cd53a | 839 | if (ctrl & MACB_BIT(TX_USED)) { |
a4c35ed3 CP |
840 | /* skb is set for the last buffer of the frame */ |
841 | while (!skb) { | |
842 | macb_tx_unmap(bp, tx_skb); | |
843 | tail++; | |
02c958dd | 844 | tx_skb = macb_tx_skb(queue, tail); |
a4c35ed3 CP |
845 | skb = tx_skb->skb; |
846 | } | |
847 | ||
848 | /* ctrl still refers to the first buffer descriptor | |
849 | * since it's the only one written back by the hardware | |
850 | */ | |
851 | if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) { | |
852 | netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n", | |
b410d13e ZB |
853 | macb_tx_ring_wrap(bp, tail), |
854 | skb->data); | |
5f1d3a5c | 855 | bp->dev->stats.tx_packets++; |
512286bb | 856 | queue->stats.tx_packets++; |
5f1d3a5c | 857 | bp->dev->stats.tx_bytes += skb->len; |
512286bb | 858 | queue->stats.tx_bytes += skb->len; |
a4c35ed3 | 859 | } |
e86cd53a | 860 | } else { |
64ec42fe MF |
861 | /* "Buffers exhausted mid-frame" errors may only happen |
862 | * if the driver is buggy, so complain loudly about | |
863 | * those. Statistics are updated by hardware. | |
e86cd53a NF |
864 | */ |
865 | if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) | |
866 | netdev_err(bp->dev, | |
867 | "BUG: TX buffers exhausted mid-frame\n"); | |
39eddb4c | 868 | |
e86cd53a NF |
869 | desc->ctrl = ctrl | MACB_BIT(TX_USED); |
870 | } | |
871 | ||
a4c35ed3 | 872 | macb_tx_unmap(bp, tx_skb); |
89e5785f HS |
873 | } |
874 | ||
02c958dd CP |
875 | /* Set end of TX queue */ |
876 | desc = macb_tx_desc(queue, 0); | |
dc97a89e | 877 | macb_set_addr(bp, desc, 0); |
02c958dd CP |
878 | desc->ctrl = MACB_BIT(TX_USED); |
879 | ||
e86cd53a NF |
880 | /* Make descriptor updates visible to hardware */ |
881 | wmb(); | |
882 | ||
883 | /* Reinitialize the TX desc queue */ | |
dc97a89e | 884 | queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); |
fff8019a | 885 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
7b429614 | 886 | if (bp->hw_dma_cap & HW_DMA_CAP_64B) |
dc97a89e | 887 | queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma)); |
fff8019a | 888 | #endif |
e86cd53a | 889 | /* Make TX ring reflect state of hardware */ |
02c958dd CP |
890 | queue->tx_head = 0; |
891 | queue->tx_tail = 0; | |
e86cd53a NF |
892 | |
893 | /* Housework before enabling TX IRQ */ | |
894 | macb_writel(bp, TSR, macb_readl(bp, TSR)); | |
02c958dd CP |
895 | queue_writel(queue, IER, MACB_TX_INT_FLAGS); |
896 | ||
897 | /* Now we are ready to start transmission again */ | |
898 | netif_tx_start_all_queues(bp->dev); | |
899 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); | |
900 | ||
901 | spin_unlock_irqrestore(&bp->lock, flags); | |
e86cd53a NF |
902 | } |
903 | ||
02c958dd | 904 | static void macb_tx_interrupt(struct macb_queue *queue) |
e86cd53a NF |
905 | { |
906 | unsigned int tail; | |
907 | unsigned int head; | |
908 | u32 status; | |
02c958dd CP |
909 | struct macb *bp = queue->bp; |
910 | u16 queue_index = queue - bp->queues; | |
e86cd53a NF |
911 | |
912 | status = macb_readl(bp, TSR); | |
913 | macb_writel(bp, TSR, status); | |
914 | ||
581df9e1 | 915 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
02c958dd | 916 | queue_writel(queue, ISR, MACB_BIT(TCOMP)); |
749a2b66 | 917 | |
e86cd53a | 918 | netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", |
aa50b552 | 919 | (unsigned long)status); |
89e5785f | 920 | |
02c958dd CP |
921 | head = queue->tx_head; |
922 | for (tail = queue->tx_tail; tail != head; tail++) { | |
55054a16 HS |
923 | struct macb_tx_skb *tx_skb; |
924 | struct sk_buff *skb; | |
925 | struct macb_dma_desc *desc; | |
926 | u32 ctrl; | |
89e5785f | 927 | |
02c958dd | 928 | desc = macb_tx_desc(queue, tail); |
89e5785f | 929 | |
03dbe05f | 930 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 931 | rmb(); |
03dbe05f | 932 | |
55054a16 | 933 | ctrl = desc->ctrl; |
89e5785f | 934 | |
a4c35ed3 CP |
935 | /* TX_USED bit is only set by hardware on the very first buffer |
936 | * descriptor of the transmitted frame. | |
937 | */ | |
55054a16 | 938 | if (!(ctrl & MACB_BIT(TX_USED))) |
89e5785f HS |
939 | break; |
940 | ||
a4c35ed3 CP |
941 | /* Process all buffers of the current transmitted frame */ |
942 | for (;; tail++) { | |
02c958dd | 943 | tx_skb = macb_tx_skb(queue, tail); |
a4c35ed3 CP |
944 | skb = tx_skb->skb; |
945 | ||
946 | /* First, update TX stats if needed */ | |
947 | if (skb) { | |
a6252047 PT |
948 | if (unlikely(skb_shinfo(skb)->tx_flags & |
949 | SKBTX_HW_TSTAMP) && | |
950 | gem_ptp_do_txstamp(queue, skb, desc) == 0) { | |
ab91f0a9 RO |
951 | /* skb now belongs to timestamp buffer |
952 | * and will be removed later | |
953 | */ | |
954 | tx_skb->skb = NULL; | |
955 | } | |
a4c35ed3 | 956 | netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", |
b410d13e ZB |
957 | macb_tx_ring_wrap(bp, tail), |
958 | skb->data); | |
5f1d3a5c | 959 | bp->dev->stats.tx_packets++; |
512286bb | 960 | queue->stats.tx_packets++; |
5f1d3a5c | 961 | bp->dev->stats.tx_bytes += skb->len; |
512286bb | 962 | queue->stats.tx_bytes += skb->len; |
a4c35ed3 | 963 | } |
55054a16 | 964 | |
a4c35ed3 CP |
965 | /* Now we can safely release resources */ |
966 | macb_tx_unmap(bp, tx_skb); | |
967 | ||
968 | /* skb is set only for the last buffer of the frame. | |
969 | * WARNING: at this point skb has been freed by | |
970 | * macb_tx_unmap(). | |
971 | */ | |
972 | if (skb) | |
973 | break; | |
974 | } | |
89e5785f HS |
975 | } |
976 | ||
02c958dd CP |
977 | queue->tx_tail = tail; |
978 | if (__netif_subqueue_stopped(bp->dev, queue_index) && | |
979 | CIRC_CNT(queue->tx_head, queue->tx_tail, | |
b410d13e | 980 | bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp)) |
02c958dd | 981 | netif_wake_subqueue(bp->dev, queue_index); |
89e5785f HS |
982 | } |
983 | ||
ae1f2a56 | 984 | static void gem_rx_refill(struct macb_queue *queue) |
4df95131 NF |
985 | { |
986 | unsigned int entry; | |
987 | struct sk_buff *skb; | |
4df95131 | 988 | dma_addr_t paddr; |
ae1f2a56 | 989 | struct macb *bp = queue->bp; |
dc97a89e | 990 | struct macb_dma_desc *desc; |
4df95131 | 991 | |
ae1f2a56 RO |
992 | while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail, |
993 | bp->rx_ring_size) > 0) { | |
994 | entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head); | |
4df95131 NF |
995 | |
996 | /* Make hw descriptor updates visible to CPU */ | |
997 | rmb(); | |
998 | ||
ae1f2a56 RO |
999 | queue->rx_prepared_head++; |
1000 | desc = macb_rx_desc(queue, entry); | |
4df95131 | 1001 | |
ae1f2a56 | 1002 | if (!queue->rx_skbuff[entry]) { |
4df95131 NF |
1003 | /* allocate sk_buff for this free entry in ring */ |
1004 | skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size); | |
aa50b552 | 1005 | if (unlikely(!skb)) { |
4df95131 NF |
1006 | netdev_err(bp->dev, |
1007 | "Unable to allocate sk_buff\n"); | |
1008 | break; | |
1009 | } | |
4df95131 NF |
1010 | |
1011 | /* now fill corresponding descriptor entry */ | |
1012 | paddr = dma_map_single(&bp->pdev->dev, skb->data, | |
64ec42fe MF |
1013 | bp->rx_buffer_size, |
1014 | DMA_FROM_DEVICE); | |
92030908 SB |
1015 | if (dma_mapping_error(&bp->pdev->dev, paddr)) { |
1016 | dev_kfree_skb(skb); | |
1017 | break; | |
1018 | } | |
1019 | ||
ae1f2a56 | 1020 | queue->rx_skbuff[entry] = skb; |
4df95131 | 1021 | |
b410d13e | 1022 | if (entry == bp->rx_ring_size - 1) |
4df95131 | 1023 | paddr |= MACB_BIT(RX_WRAP); |
dc97a89e | 1024 | desc->ctrl = 0; |
8159ecab AH |
1025 | /* Setting addr clears RX_USED and allows reception, |
1026 | * make sure ctrl is cleared first to avoid a race. | |
1027 | */ | |
1028 | dma_wmb(); | |
1029 | macb_set_addr(bp, desc, paddr); | |
4df95131 NF |
1030 | |
1031 | /* properly align Ethernet header */ | |
1032 | skb_reserve(skb, NET_IP_ALIGN); | |
d4c216c5 | 1033 | } else { |
dc97a89e | 1034 | desc->ctrl = 0; |
8159ecab AH |
1035 | dma_wmb(); |
1036 | desc->addr &= ~MACB_BIT(RX_USED); | |
4df95131 NF |
1037 | } |
1038 | } | |
1039 | ||
1040 | /* Make descriptor updates visible to hardware */ | |
1041 | wmb(); | |
1042 | ||
ae1f2a56 RO |
1043 | netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n", |
1044 | queue, queue->rx_prepared_head, queue->rx_tail); | |
4df95131 NF |
1045 | } |
1046 | ||
1047 | /* Mark DMA descriptors from begin up to and not including end as unused */ | |
ae1f2a56 | 1048 | static void discard_partial_frame(struct macb_queue *queue, unsigned int begin, |
4df95131 NF |
1049 | unsigned int end) |
1050 | { | |
1051 | unsigned int frag; | |
1052 | ||
1053 | for (frag = begin; frag != end; frag++) { | |
ae1f2a56 | 1054 | struct macb_dma_desc *desc = macb_rx_desc(queue, frag); |
64ec42fe | 1055 | |
4df95131 NF |
1056 | desc->addr &= ~MACB_BIT(RX_USED); |
1057 | } | |
1058 | ||
1059 | /* Make descriptor updates visible to hardware */ | |
1060 | wmb(); | |
1061 | ||
64ec42fe | 1062 | /* When this happens, the hardware stats registers for |
4df95131 NF |
1063 | * whatever caused this is updated, so we don't have to record |
1064 | * anything. | |
1065 | */ | |
1066 | } | |
1067 | ||
97236cda AT |
1068 | static int gem_rx(struct macb_queue *queue, struct napi_struct *napi, |
1069 | int budget) | |
4df95131 | 1070 | { |
ae1f2a56 | 1071 | struct macb *bp = queue->bp; |
4df95131 NF |
1072 | unsigned int len; |
1073 | unsigned int entry; | |
1074 | struct sk_buff *skb; | |
1075 | struct macb_dma_desc *desc; | |
1076 | int count = 0; | |
1077 | ||
1078 | while (count < budget) { | |
fff8019a HK |
1079 | u32 ctrl; |
1080 | dma_addr_t addr; | |
1081 | bool rxused; | |
4df95131 | 1082 | |
ae1f2a56 RO |
1083 | entry = macb_rx_ring_wrap(bp, queue->rx_tail); |
1084 | desc = macb_rx_desc(queue, entry); | |
4df95131 NF |
1085 | |
1086 | /* Make hw descriptor updates visible to CPU */ | |
1087 | rmb(); | |
1088 | ||
fff8019a | 1089 | rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false; |
dc97a89e | 1090 | addr = macb_get_addr(bp, desc); |
4df95131 | 1091 | |
fff8019a | 1092 | if (!rxused) |
4df95131 NF |
1093 | break; |
1094 | ||
6e0af298 AH |
1095 | /* Ensure ctrl is at least as up-to-date as rxused */ |
1096 | dma_rmb(); | |
1097 | ||
1098 | ctrl = desc->ctrl; | |
1099 | ||
ae1f2a56 | 1100 | queue->rx_tail++; |
4df95131 NF |
1101 | count++; |
1102 | ||
1103 | if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) { | |
1104 | netdev_err(bp->dev, | |
1105 | "not whole frame pointed by descriptor\n"); | |
5f1d3a5c | 1106 | bp->dev->stats.rx_dropped++; |
512286bb | 1107 | queue->stats.rx_dropped++; |
4df95131 NF |
1108 | break; |
1109 | } | |
ae1f2a56 | 1110 | skb = queue->rx_skbuff[entry]; |
4df95131 NF |
1111 | if (unlikely(!skb)) { |
1112 | netdev_err(bp->dev, | |
1113 | "inconsistent Rx descriptor chain\n"); | |
5f1d3a5c | 1114 | bp->dev->stats.rx_dropped++; |
512286bb | 1115 | queue->stats.rx_dropped++; |
4df95131 NF |
1116 | break; |
1117 | } | |
1118 | /* now everything is ready for receiving packet */ | |
ae1f2a56 | 1119 | queue->rx_skbuff[entry] = NULL; |
98b5a0f4 | 1120 | len = ctrl & bp->rx_frm_len_mask; |
4df95131 NF |
1121 | |
1122 | netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len); | |
1123 | ||
1124 | skb_put(skb, len); | |
4df95131 | 1125 | dma_unmap_single(&bp->pdev->dev, addr, |
48330e08 | 1126 | bp->rx_buffer_size, DMA_FROM_DEVICE); |
4df95131 NF |
1127 | |
1128 | skb->protocol = eth_type_trans(skb, bp->dev); | |
1129 | skb_checksum_none_assert(skb); | |
924ec53c CP |
1130 | if (bp->dev->features & NETIF_F_RXCSUM && |
1131 | !(bp->dev->flags & IFF_PROMISC) && | |
1132 | GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK) | |
1133 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4df95131 | 1134 | |
5f1d3a5c | 1135 | bp->dev->stats.rx_packets++; |
512286bb | 1136 | queue->stats.rx_packets++; |
5f1d3a5c | 1137 | bp->dev->stats.rx_bytes += skb->len; |
512286bb | 1138 | queue->stats.rx_bytes += skb->len; |
4df95131 | 1139 | |
ab91f0a9 RO |
1140 | gem_ptp_do_rxstamp(bp, skb, desc); |
1141 | ||
4df95131 NF |
1142 | #if defined(DEBUG) && defined(VERBOSE_DEBUG) |
1143 | netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", | |
1144 | skb->len, skb->csum); | |
1145 | print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1, | |
51f83014 | 1146 | skb_mac_header(skb), 16, true); |
4df95131 NF |
1147 | print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1, |
1148 | skb->data, 32, true); | |
1149 | #endif | |
1150 | ||
97236cda | 1151 | napi_gro_receive(napi, skb); |
4df95131 NF |
1152 | } |
1153 | ||
ae1f2a56 | 1154 | gem_rx_refill(queue); |
4df95131 NF |
1155 | |
1156 | return count; | |
1157 | } | |
1158 | ||
97236cda AT |
1159 | static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi, |
1160 | unsigned int first_frag, unsigned int last_frag) | |
89e5785f HS |
1161 | { |
1162 | unsigned int len; | |
1163 | unsigned int frag; | |
29bc2e1e | 1164 | unsigned int offset; |
89e5785f | 1165 | struct sk_buff *skb; |
55054a16 | 1166 | struct macb_dma_desc *desc; |
ae1f2a56 | 1167 | struct macb *bp = queue->bp; |
89e5785f | 1168 | |
ae1f2a56 | 1169 | desc = macb_rx_desc(queue, last_frag); |
98b5a0f4 | 1170 | len = desc->ctrl & bp->rx_frm_len_mask; |
89e5785f | 1171 | |
a268adb1 | 1172 | netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", |
b410d13e ZB |
1173 | macb_rx_ring_wrap(bp, first_frag), |
1174 | macb_rx_ring_wrap(bp, last_frag), len); | |
89e5785f | 1175 | |
64ec42fe | 1176 | /* The ethernet header starts NET_IP_ALIGN bytes into the |
29bc2e1e HS |
1177 | * first buffer. Since the header is 14 bytes, this makes the |
1178 | * payload word-aligned. | |
1179 | * | |
1180 | * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy | |
1181 | * the two padding bytes into the skb so that we avoid hitting | |
1182 | * the slowpath in memcpy(), and pull them off afterwards. | |
1183 | */ | |
1184 | skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN); | |
89e5785f | 1185 | if (!skb) { |
5f1d3a5c | 1186 | bp->dev->stats.rx_dropped++; |
55054a16 | 1187 | for (frag = first_frag; ; frag++) { |
ae1f2a56 | 1188 | desc = macb_rx_desc(queue, frag); |
55054a16 | 1189 | desc->addr &= ~MACB_BIT(RX_USED); |
89e5785f HS |
1190 | if (frag == last_frag) |
1191 | break; | |
1192 | } | |
03dbe05f HS |
1193 | |
1194 | /* Make descriptor updates visible to hardware */ | |
89e5785f | 1195 | wmb(); |
03dbe05f | 1196 | |
89e5785f HS |
1197 | return 1; |
1198 | } | |
1199 | ||
29bc2e1e HS |
1200 | offset = 0; |
1201 | len += NET_IP_ALIGN; | |
bc8acf2c | 1202 | skb_checksum_none_assert(skb); |
89e5785f HS |
1203 | skb_put(skb, len); |
1204 | ||
55054a16 | 1205 | for (frag = first_frag; ; frag++) { |
1b44791a | 1206 | unsigned int frag_len = bp->rx_buffer_size; |
89e5785f HS |
1207 | |
1208 | if (offset + frag_len > len) { | |
9ba723b0 CP |
1209 | if (unlikely(frag != last_frag)) { |
1210 | dev_kfree_skb_any(skb); | |
1211 | return -1; | |
1212 | } | |
89e5785f HS |
1213 | frag_len = len - offset; |
1214 | } | |
27d7ff46 | 1215 | skb_copy_to_linear_data_offset(skb, offset, |
ae1f2a56 | 1216 | macb_rx_buffer(queue, frag), |
aa50b552 | 1217 | frag_len); |
1b44791a | 1218 | offset += bp->rx_buffer_size; |
ae1f2a56 | 1219 | desc = macb_rx_desc(queue, frag); |
55054a16 | 1220 | desc->addr &= ~MACB_BIT(RX_USED); |
89e5785f HS |
1221 | |
1222 | if (frag == last_frag) | |
1223 | break; | |
1224 | } | |
1225 | ||
03dbe05f HS |
1226 | /* Make descriptor updates visible to hardware */ |
1227 | wmb(); | |
1228 | ||
29bc2e1e | 1229 | __skb_pull(skb, NET_IP_ALIGN); |
89e5785f HS |
1230 | skb->protocol = eth_type_trans(skb, bp->dev); |
1231 | ||
5f1d3a5c TK |
1232 | bp->dev->stats.rx_packets++; |
1233 | bp->dev->stats.rx_bytes += skb->len; | |
a268adb1 | 1234 | netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", |
aa50b552 | 1235 | skb->len, skb->csum); |
97236cda | 1236 | napi_gro_receive(napi, skb); |
89e5785f HS |
1237 | |
1238 | return 0; | |
1239 | } | |
1240 | ||
ae1f2a56 | 1241 | static inline void macb_init_rx_ring(struct macb_queue *queue) |
9ba723b0 | 1242 | { |
ae1f2a56 | 1243 | struct macb *bp = queue->bp; |
9ba723b0 | 1244 | dma_addr_t addr; |
dc97a89e | 1245 | struct macb_dma_desc *desc = NULL; |
9ba723b0 CP |
1246 | int i; |
1247 | ||
ae1f2a56 | 1248 | addr = queue->rx_buffers_dma; |
b410d13e | 1249 | for (i = 0; i < bp->rx_ring_size; i++) { |
ae1f2a56 | 1250 | desc = macb_rx_desc(queue, i); |
dc97a89e RO |
1251 | macb_set_addr(bp, desc, addr); |
1252 | desc->ctrl = 0; | |
9ba723b0 CP |
1253 | addr += bp->rx_buffer_size; |
1254 | } | |
dc97a89e | 1255 | desc->addr |= MACB_BIT(RX_WRAP); |
ae1f2a56 | 1256 | queue->rx_tail = 0; |
9ba723b0 CP |
1257 | } |
1258 | ||
97236cda AT |
1259 | static int macb_rx(struct macb_queue *queue, struct napi_struct *napi, |
1260 | int budget) | |
89e5785f | 1261 | { |
ae1f2a56 | 1262 | struct macb *bp = queue->bp; |
9ba723b0 | 1263 | bool reset_rx_queue = false; |
89e5785f | 1264 | int received = 0; |
55054a16 | 1265 | unsigned int tail; |
89e5785f HS |
1266 | int first_frag = -1; |
1267 | ||
ae1f2a56 RO |
1268 | for (tail = queue->rx_tail; budget > 0; tail++) { |
1269 | struct macb_dma_desc *desc = macb_rx_desc(queue, tail); | |
dc97a89e | 1270 | u32 ctrl; |
89e5785f | 1271 | |
03dbe05f | 1272 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 1273 | rmb(); |
03dbe05f | 1274 | |
dc97a89e | 1275 | if (!(desc->addr & MACB_BIT(RX_USED))) |
89e5785f HS |
1276 | break; |
1277 | ||
6e0af298 AH |
1278 | /* Ensure ctrl is at least as up-to-date as addr */ |
1279 | dma_rmb(); | |
1280 | ||
1281 | ctrl = desc->ctrl; | |
1282 | ||
89e5785f HS |
1283 | if (ctrl & MACB_BIT(RX_SOF)) { |
1284 | if (first_frag != -1) | |
ae1f2a56 | 1285 | discard_partial_frame(queue, first_frag, tail); |
89e5785f HS |
1286 | first_frag = tail; |
1287 | } | |
1288 | ||
1289 | if (ctrl & MACB_BIT(RX_EOF)) { | |
1290 | int dropped; | |
9ba723b0 CP |
1291 | |
1292 | if (unlikely(first_frag == -1)) { | |
1293 | reset_rx_queue = true; | |
1294 | continue; | |
1295 | } | |
89e5785f | 1296 | |
97236cda | 1297 | dropped = macb_rx_frame(queue, napi, first_frag, tail); |
89e5785f | 1298 | first_frag = -1; |
9ba723b0 CP |
1299 | if (unlikely(dropped < 0)) { |
1300 | reset_rx_queue = true; | |
1301 | continue; | |
1302 | } | |
89e5785f HS |
1303 | if (!dropped) { |
1304 | received++; | |
1305 | budget--; | |
1306 | } | |
1307 | } | |
1308 | } | |
1309 | ||
9ba723b0 CP |
1310 | if (unlikely(reset_rx_queue)) { |
1311 | unsigned long flags; | |
1312 | u32 ctrl; | |
1313 | ||
1314 | netdev_err(bp->dev, "RX queue corruption: reset it\n"); | |
1315 | ||
1316 | spin_lock_irqsave(&bp->lock, flags); | |
1317 | ||
1318 | ctrl = macb_readl(bp, NCR); | |
1319 | macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); | |
1320 | ||
ae1f2a56 RO |
1321 | macb_init_rx_ring(queue); |
1322 | queue_writel(queue, RBQP, queue->rx_ring_dma); | |
9ba723b0 CP |
1323 | |
1324 | macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); | |
1325 | ||
1326 | spin_unlock_irqrestore(&bp->lock, flags); | |
1327 | return received; | |
1328 | } | |
1329 | ||
89e5785f | 1330 | if (first_frag != -1) |
ae1f2a56 | 1331 | queue->rx_tail = first_frag; |
89e5785f | 1332 | else |
ae1f2a56 | 1333 | queue->rx_tail = tail; |
89e5785f HS |
1334 | |
1335 | return received; | |
1336 | } | |
1337 | ||
bea3348e | 1338 | static int macb_poll(struct napi_struct *napi, int budget) |
89e5785f | 1339 | { |
ae1f2a56 RO |
1340 | struct macb_queue *queue = container_of(napi, struct macb_queue, napi); |
1341 | struct macb *bp = queue->bp; | |
bea3348e | 1342 | int work_done; |
89e5785f HS |
1343 | u32 status; |
1344 | ||
1345 | status = macb_readl(bp, RSR); | |
1346 | macb_writel(bp, RSR, status); | |
1347 | ||
a268adb1 | 1348 | netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n", |
aa50b552 | 1349 | (unsigned long)status, budget); |
89e5785f | 1350 | |
97236cda | 1351 | work_done = bp->macbgem_ops.mog_rx(queue, napi, budget); |
b336369c | 1352 | if (work_done < budget) { |
6ad20165 | 1353 | napi_complete_done(napi, work_done); |
89e5785f | 1354 | |
8770e91a NF |
1355 | /* Packets received while interrupts were disabled */ |
1356 | status = macb_readl(bp, RSR); | |
504ad98d | 1357 | if (status) { |
02f7a34f | 1358 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
ae1f2a56 | 1359 | queue_writel(queue, ISR, MACB_BIT(RCOMP)); |
8770e91a | 1360 | napi_reschedule(napi); |
02f7a34f | 1361 | } else { |
e501070e | 1362 | queue_writel(queue, IER, bp->rx_intr_mask); |
02f7a34f | 1363 | } |
b336369c | 1364 | } |
89e5785f HS |
1365 | |
1366 | /* TODO: Handle errors */ | |
1367 | ||
bea3348e | 1368 | return work_done; |
89e5785f HS |
1369 | } |
1370 | ||
032dc41b HK |
1371 | static void macb_hresp_error_task(unsigned long data) |
1372 | { | |
1373 | struct macb *bp = (struct macb *)data; | |
1374 | struct net_device *dev = bp->dev; | |
1375 | struct macb_queue *queue = bp->queues; | |
1376 | unsigned int q; | |
1377 | u32 ctrl; | |
1378 | ||
1379 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { | |
e501070e | 1380 | queue_writel(queue, IDR, bp->rx_intr_mask | |
032dc41b HK |
1381 | MACB_TX_INT_FLAGS | |
1382 | MACB_BIT(HRESP)); | |
1383 | } | |
1384 | ctrl = macb_readl(bp, NCR); | |
1385 | ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE)); | |
1386 | macb_writel(bp, NCR, ctrl); | |
1387 | ||
1388 | netif_tx_stop_all_queues(dev); | |
1389 | netif_carrier_off(dev); | |
1390 | ||
1391 | bp->macbgem_ops.mog_init_rings(bp); | |
1392 | ||
1393 | /* Initialize TX and RX buffers */ | |
6e952d95 | 1394 | macb_init_buffers(bp); |
032dc41b | 1395 | |
6e952d95 AT |
1396 | /* Enable interrupts */ |
1397 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) | |
032dc41b | 1398 | queue_writel(queue, IER, |
e501070e | 1399 | bp->rx_intr_mask | |
032dc41b HK |
1400 | MACB_TX_INT_FLAGS | |
1401 | MACB_BIT(HRESP)); | |
032dc41b HK |
1402 | |
1403 | ctrl |= MACB_BIT(RE) | MACB_BIT(TE); | |
1404 | macb_writel(bp, NCR, ctrl); | |
1405 | ||
1406 | netif_carrier_on(dev); | |
1407 | netif_tx_start_all_queues(dev); | |
1408 | } | |
1409 | ||
42983885 CB |
1410 | static void macb_tx_restart(struct macb_queue *queue) |
1411 | { | |
1412 | unsigned int head = queue->tx_head; | |
1413 | unsigned int tail = queue->tx_tail; | |
1414 | struct macb *bp = queue->bp; | |
1415 | ||
1416 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
1417 | queue_writel(queue, ISR, MACB_BIT(TXUBR)); | |
1418 | ||
1419 | if (head == tail) | |
1420 | return; | |
1421 | ||
1422 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); | |
1423 | } | |
1424 | ||
89e5785f HS |
1425 | static irqreturn_t macb_interrupt(int irq, void *dev_id) |
1426 | { | |
02c958dd CP |
1427 | struct macb_queue *queue = dev_id; |
1428 | struct macb *bp = queue->bp; | |
1429 | struct net_device *dev = bp->dev; | |
bfbb92c4 | 1430 | u32 status, ctrl; |
89e5785f | 1431 | |
02c958dd | 1432 | status = queue_readl(queue, ISR); |
89e5785f HS |
1433 | |
1434 | if (unlikely(!status)) | |
1435 | return IRQ_NONE; | |
1436 | ||
1437 | spin_lock(&bp->lock); | |
1438 | ||
1439 | while (status) { | |
89e5785f HS |
1440 | /* close possible race with dev_close */ |
1441 | if (unlikely(!netif_running(dev))) { | |
02c958dd | 1442 | queue_writel(queue, IDR, -1); |
24468374 NS |
1443 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
1444 | queue_writel(queue, ISR, -1); | |
89e5785f HS |
1445 | break; |
1446 | } | |
1447 | ||
02c958dd CP |
1448 | netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n", |
1449 | (unsigned int)(queue - bp->queues), | |
1450 | (unsigned long)status); | |
a268adb1 | 1451 | |
e501070e | 1452 | if (status & bp->rx_intr_mask) { |
64ec42fe | 1453 | /* There's no point taking any more interrupts |
b336369c JH |
1454 | * until we have processed the buffers. The |
1455 | * scheduling call may fail if the poll routine | |
1456 | * is already scheduled, so disable interrupts | |
1457 | * now. | |
1458 | */ | |
e501070e | 1459 | queue_writel(queue, IDR, bp->rx_intr_mask); |
581df9e1 | 1460 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
02c958dd | 1461 | queue_writel(queue, ISR, MACB_BIT(RCOMP)); |
b336369c | 1462 | |
ae1f2a56 | 1463 | if (napi_schedule_prep(&queue->napi)) { |
a268adb1 | 1464 | netdev_vdbg(bp->dev, "scheduling RX softirq\n"); |
ae1f2a56 | 1465 | __napi_schedule(&queue->napi); |
89e5785f HS |
1466 | } |
1467 | } | |
1468 | ||
e86cd53a | 1469 | if (unlikely(status & (MACB_TX_ERR_FLAGS))) { |
02c958dd CP |
1470 | queue_writel(queue, IDR, MACB_TX_INT_FLAGS); |
1471 | schedule_work(&queue->tx_error_task); | |
6a027b70 SB |
1472 | |
1473 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
02c958dd | 1474 | queue_writel(queue, ISR, MACB_TX_ERR_FLAGS); |
6a027b70 | 1475 | |
e86cd53a NF |
1476 | break; |
1477 | } | |
1478 | ||
1479 | if (status & MACB_BIT(TCOMP)) | |
02c958dd | 1480 | macb_tx_interrupt(queue); |
89e5785f | 1481 | |
42983885 CB |
1482 | if (status & MACB_BIT(TXUBR)) |
1483 | macb_tx_restart(queue); | |
1484 | ||
64ec42fe | 1485 | /* Link change detection isn't possible with RMII, so we'll |
89e5785f HS |
1486 | * add that if/when we get our hands on a full-blown MII PHY. |
1487 | */ | |
1488 | ||
86b5e7de NS |
1489 | /* There is a hardware issue under heavy load where DMA can |
1490 | * stop, this causes endless "used buffer descriptor read" | |
1491 | * interrupts but it can be cleared by re-enabling RX. See | |
e501070e HK |
1492 | * the at91rm9200 manual, section 41.3.1 or the Zynq manual |
1493 | * section 16.7.4 for details. RXUBR is only enabled for | |
1494 | * these two versions. | |
86b5e7de | 1495 | */ |
bfbb92c4 NS |
1496 | if (status & MACB_BIT(RXUBR)) { |
1497 | ctrl = macb_readl(bp, NCR); | |
1498 | macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); | |
ffac0e96 | 1499 | wmb(); |
bfbb92c4 NS |
1500 | macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); |
1501 | ||
1502 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
ba504994 | 1503 | queue_writel(queue, ISR, MACB_BIT(RXUBR)); |
bfbb92c4 NS |
1504 | } |
1505 | ||
b19f7f71 AS |
1506 | if (status & MACB_BIT(ISR_ROVR)) { |
1507 | /* We missed at least one packet */ | |
f75ba50b JI |
1508 | if (macb_is_gem(bp)) |
1509 | bp->hw_stats.gem.rx_overruns++; | |
1510 | else | |
1511 | bp->hw_stats.macb.rx_overruns++; | |
6a027b70 SB |
1512 | |
1513 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
02c958dd | 1514 | queue_writel(queue, ISR, MACB_BIT(ISR_ROVR)); |
b19f7f71 AS |
1515 | } |
1516 | ||
89e5785f | 1517 | if (status & MACB_BIT(HRESP)) { |
032dc41b | 1518 | tasklet_schedule(&bp->hresp_err_tasklet); |
c220f8cd | 1519 | netdev_err(dev, "DMA bus error: HRESP not OK\n"); |
6a027b70 SB |
1520 | |
1521 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
02c958dd | 1522 | queue_writel(queue, ISR, MACB_BIT(HRESP)); |
89e5785f | 1523 | } |
02c958dd | 1524 | status = queue_readl(queue, ISR); |
89e5785f HS |
1525 | } |
1526 | ||
1527 | spin_unlock(&bp->lock); | |
1528 | ||
1529 | return IRQ_HANDLED; | |
1530 | } | |
1531 | ||
6e8cf5c0 | 1532 | #ifdef CONFIG_NET_POLL_CONTROLLER |
64ec42fe | 1533 | /* Polling receive - used by netconsole and other diagnostic tools |
6e8cf5c0 TP |
1534 | * to allow network i/o with interrupts disabled. |
1535 | */ | |
1536 | static void macb_poll_controller(struct net_device *dev) | |
1537 | { | |
02c958dd CP |
1538 | struct macb *bp = netdev_priv(dev); |
1539 | struct macb_queue *queue; | |
6e8cf5c0 | 1540 | unsigned long flags; |
02c958dd | 1541 | unsigned int q; |
6e8cf5c0 TP |
1542 | |
1543 | local_irq_save(flags); | |
02c958dd CP |
1544 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) |
1545 | macb_interrupt(dev->irq, queue); | |
6e8cf5c0 TP |
1546 | local_irq_restore(flags); |
1547 | } | |
1548 | #endif | |
1549 | ||
a4c35ed3 | 1550 | static unsigned int macb_tx_map(struct macb *bp, |
02c958dd | 1551 | struct macb_queue *queue, |
1629dd4f RO |
1552 | struct sk_buff *skb, |
1553 | unsigned int hdrlen) | |
89e5785f | 1554 | { |
89e5785f | 1555 | dma_addr_t mapping; |
02c958dd | 1556 | unsigned int len, entry, i, tx_head = queue->tx_head; |
a4c35ed3 | 1557 | struct macb_tx_skb *tx_skb = NULL; |
55054a16 | 1558 | struct macb_dma_desc *desc; |
a4c35ed3 CP |
1559 | unsigned int offset, size, count = 0; |
1560 | unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags; | |
1629dd4f RO |
1561 | unsigned int eof = 1, mss_mfs = 0; |
1562 | u32 ctrl, lso_ctrl = 0, seq_ctrl = 0; | |
1563 | ||
1564 | /* LSO */ | |
1565 | if (skb_shinfo(skb)->gso_size != 0) { | |
1566 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) | |
1567 | /* UDP - UFO */ | |
1568 | lso_ctrl = MACB_LSO_UFO_ENABLE; | |
1569 | else | |
1570 | /* TCP - TSO */ | |
1571 | lso_ctrl = MACB_LSO_TSO_ENABLE; | |
1572 | } | |
a4c35ed3 CP |
1573 | |
1574 | /* First, map non-paged data */ | |
1575 | len = skb_headlen(skb); | |
1629dd4f RO |
1576 | |
1577 | /* first buffer length */ | |
1578 | size = hdrlen; | |
1579 | ||
a4c35ed3 CP |
1580 | offset = 0; |
1581 | while (len) { | |
b410d13e | 1582 | entry = macb_tx_ring_wrap(bp, tx_head); |
02c958dd | 1583 | tx_skb = &queue->tx_skb[entry]; |
a4c35ed3 CP |
1584 | |
1585 | mapping = dma_map_single(&bp->pdev->dev, | |
1586 | skb->data + offset, | |
1587 | size, DMA_TO_DEVICE); | |
1588 | if (dma_mapping_error(&bp->pdev->dev, mapping)) | |
1589 | goto dma_error; | |
1590 | ||
1591 | /* Save info to properly release resources */ | |
1592 | tx_skb->skb = NULL; | |
1593 | tx_skb->mapping = mapping; | |
1594 | tx_skb->size = size; | |
1595 | tx_skb->mapped_as_page = false; | |
1596 | ||
1597 | len -= size; | |
1598 | offset += size; | |
1599 | count++; | |
1600 | tx_head++; | |
1629dd4f RO |
1601 | |
1602 | size = min(len, bp->max_tx_length); | |
a4c35ed3 CP |
1603 | } |
1604 | ||
1605 | /* Then, map paged data from fragments */ | |
1606 | for (f = 0; f < nr_frags; f++) { | |
1607 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; | |
1608 | ||
1609 | len = skb_frag_size(frag); | |
1610 | offset = 0; | |
1611 | while (len) { | |
1612 | size = min(len, bp->max_tx_length); | |
b410d13e | 1613 | entry = macb_tx_ring_wrap(bp, tx_head); |
02c958dd | 1614 | tx_skb = &queue->tx_skb[entry]; |
a4c35ed3 CP |
1615 | |
1616 | mapping = skb_frag_dma_map(&bp->pdev->dev, frag, | |
1617 | offset, size, DMA_TO_DEVICE); | |
1618 | if (dma_mapping_error(&bp->pdev->dev, mapping)) | |
1619 | goto dma_error; | |
1620 | ||
1621 | /* Save info to properly release resources */ | |
1622 | tx_skb->skb = NULL; | |
1623 | tx_skb->mapping = mapping; | |
1624 | tx_skb->size = size; | |
1625 | tx_skb->mapped_as_page = true; | |
1626 | ||
1627 | len -= size; | |
1628 | offset += size; | |
1629 | count++; | |
1630 | tx_head++; | |
1631 | } | |
1632 | } | |
1633 | ||
1634 | /* Should never happen */ | |
aa50b552 | 1635 | if (unlikely(!tx_skb)) { |
a4c35ed3 CP |
1636 | netdev_err(bp->dev, "BUG! empty skb!\n"); |
1637 | return 0; | |
1638 | } | |
1639 | ||
1640 | /* This is the last buffer of the frame: save socket buffer */ | |
1641 | tx_skb->skb = skb; | |
1642 | ||
1643 | /* Update TX ring: update buffer descriptors in reverse order | |
1644 | * to avoid race condition | |
1645 | */ | |
1646 | ||
1647 | /* Set 'TX_USED' bit in buffer descriptor at tx_head position | |
1648 | * to set the end of TX queue | |
1649 | */ | |
1650 | i = tx_head; | |
b410d13e | 1651 | entry = macb_tx_ring_wrap(bp, i); |
a4c35ed3 | 1652 | ctrl = MACB_BIT(TX_USED); |
dc97a89e | 1653 | desc = macb_tx_desc(queue, entry); |
a4c35ed3 CP |
1654 | desc->ctrl = ctrl; |
1655 | ||
1629dd4f RO |
1656 | if (lso_ctrl) { |
1657 | if (lso_ctrl == MACB_LSO_UFO_ENABLE) | |
1658 | /* include header and FCS in value given to h/w */ | |
1659 | mss_mfs = skb_shinfo(skb)->gso_size + | |
1660 | skb_transport_offset(skb) + | |
1661 | ETH_FCS_LEN; | |
1662 | else /* TSO */ { | |
1663 | mss_mfs = skb_shinfo(skb)->gso_size; | |
1664 | /* TCP Sequence Number Source Select | |
1665 | * can be set only for TSO | |
1666 | */ | |
1667 | seq_ctrl = 0; | |
1668 | } | |
1669 | } | |
1670 | ||
a4c35ed3 CP |
1671 | do { |
1672 | i--; | |
b410d13e | 1673 | entry = macb_tx_ring_wrap(bp, i); |
02c958dd | 1674 | tx_skb = &queue->tx_skb[entry]; |
dc97a89e | 1675 | desc = macb_tx_desc(queue, entry); |
a4c35ed3 CP |
1676 | |
1677 | ctrl = (u32)tx_skb->size; | |
1678 | if (eof) { | |
1679 | ctrl |= MACB_BIT(TX_LAST); | |
1680 | eof = 0; | |
1681 | } | |
b410d13e | 1682 | if (unlikely(entry == (bp->tx_ring_size - 1))) |
a4c35ed3 CP |
1683 | ctrl |= MACB_BIT(TX_WRAP); |
1684 | ||
1629dd4f RO |
1685 | /* First descriptor is header descriptor */ |
1686 | if (i == queue->tx_head) { | |
1687 | ctrl |= MACB_BF(TX_LSO, lso_ctrl); | |
1688 | ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl); | |
653e92a9 CB |
1689 | if ((bp->dev->features & NETIF_F_HW_CSUM) && |
1690 | skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl) | |
1691 | ctrl |= MACB_BIT(TX_NOCRC); | |
1629dd4f RO |
1692 | } else |
1693 | /* Only set MSS/MFS on payload descriptors | |
1694 | * (second or later descriptor) | |
1695 | */ | |
1696 | ctrl |= MACB_BF(MSS_MFS, mss_mfs); | |
1697 | ||
a4c35ed3 | 1698 | /* Set TX buffer descriptor */ |
dc97a89e | 1699 | macb_set_addr(bp, desc, tx_skb->mapping); |
a4c35ed3 CP |
1700 | /* desc->addr must be visible to hardware before clearing |
1701 | * 'TX_USED' bit in desc->ctrl. | |
1702 | */ | |
1703 | wmb(); | |
1704 | desc->ctrl = ctrl; | |
02c958dd | 1705 | } while (i != queue->tx_head); |
a4c35ed3 | 1706 | |
02c958dd | 1707 | queue->tx_head = tx_head; |
a4c35ed3 CP |
1708 | |
1709 | return count; | |
1710 | ||
1711 | dma_error: | |
1712 | netdev_err(bp->dev, "TX DMA map failed\n"); | |
1713 | ||
02c958dd CP |
1714 | for (i = queue->tx_head; i != tx_head; i++) { |
1715 | tx_skb = macb_tx_skb(queue, i); | |
a4c35ed3 CP |
1716 | |
1717 | macb_tx_unmap(bp, tx_skb); | |
1718 | } | |
1719 | ||
1720 | return 0; | |
1721 | } | |
1722 | ||
1629dd4f RO |
1723 | static netdev_features_t macb_features_check(struct sk_buff *skb, |
1724 | struct net_device *dev, | |
1725 | netdev_features_t features) | |
1726 | { | |
1727 | unsigned int nr_frags, f; | |
1728 | unsigned int hdrlen; | |
1729 | ||
1730 | /* Validate LSO compatibility */ | |
1731 | ||
1732 | /* there is only one buffer */ | |
1733 | if (!skb_is_nonlinear(skb)) | |
1734 | return features; | |
1735 | ||
1736 | /* length of header */ | |
1737 | hdrlen = skb_transport_offset(skb); | |
1738 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) | |
1739 | hdrlen += tcp_hdrlen(skb); | |
1740 | ||
1741 | /* For LSO: | |
1742 | * When software supplies two or more payload buffers all payload buffers | |
1743 | * apart from the last must be a multiple of 8 bytes in size. | |
1744 | */ | |
1745 | if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN)) | |
1746 | return features & ~MACB_NETIF_LSO; | |
1747 | ||
1748 | nr_frags = skb_shinfo(skb)->nr_frags; | |
1749 | /* No need to check last fragment */ | |
1750 | nr_frags--; | |
1751 | for (f = 0; f < nr_frags; f++) { | |
1752 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; | |
1753 | ||
1754 | if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN)) | |
1755 | return features & ~MACB_NETIF_LSO; | |
1756 | } | |
1757 | return features; | |
1758 | } | |
1759 | ||
007e4ba3 HB |
1760 | static inline int macb_clear_csum(struct sk_buff *skb) |
1761 | { | |
1762 | /* no change for packets without checksum offloading */ | |
1763 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
1764 | return 0; | |
1765 | ||
1766 | /* make sure we can modify the header */ | |
1767 | if (unlikely(skb_cow_head(skb, 0))) | |
1768 | return -1; | |
1769 | ||
1770 | /* initialize checksum field | |
1771 | * This is required - at least for Zynq, which otherwise calculates | |
1772 | * wrong UDP header checksums for UDP packets with UDP data len <=2 | |
1773 | */ | |
1774 | *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0; | |
1775 | return 0; | |
1776 | } | |
1777 | ||
653e92a9 CB |
1778 | static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev) |
1779 | { | |
1780 | bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb); | |
1781 | int padlen = ETH_ZLEN - (*skb)->len; | |
1782 | int headroom = skb_headroom(*skb); | |
1783 | int tailroom = skb_tailroom(*skb); | |
1784 | struct sk_buff *nskb; | |
1785 | u32 fcs; | |
1786 | ||
1787 | if (!(ndev->features & NETIF_F_HW_CSUM) || | |
1788 | !((*skb)->ip_summed != CHECKSUM_PARTIAL) || | |
1789 | skb_shinfo(*skb)->gso_size) /* Not available for GSO */ | |
1790 | return 0; | |
1791 | ||
1792 | if (padlen <= 0) { | |
1793 | /* FCS could be appeded to tailroom. */ | |
1794 | if (tailroom >= ETH_FCS_LEN) | |
1795 | goto add_fcs; | |
1796 | /* FCS could be appeded by moving data to headroom. */ | |
1797 | else if (!cloned && headroom + tailroom >= ETH_FCS_LEN) | |
1798 | padlen = 0; | |
1799 | /* No room for FCS, need to reallocate skb. */ | |
1800 | else | |
899ecaed | 1801 | padlen = ETH_FCS_LEN; |
653e92a9 CB |
1802 | } else { |
1803 | /* Add room for FCS. */ | |
1804 | padlen += ETH_FCS_LEN; | |
1805 | } | |
1806 | ||
1807 | if (!cloned && headroom + tailroom >= padlen) { | |
1808 | (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len); | |
1809 | skb_set_tail_pointer(*skb, (*skb)->len); | |
1810 | } else { | |
1811 | nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC); | |
1812 | if (!nskb) | |
1813 | return -ENOMEM; | |
1814 | ||
f3e5c070 | 1815 | dev_consume_skb_any(*skb); |
653e92a9 CB |
1816 | *skb = nskb; |
1817 | } | |
1818 | ||
ba3e1847 CB |
1819 | if (padlen > ETH_FCS_LEN) |
1820 | skb_put_zero(*skb, padlen - ETH_FCS_LEN); | |
653e92a9 CB |
1821 | |
1822 | add_fcs: | |
1823 | /* set FCS to packet */ | |
1824 | fcs = crc32_le(~0, (*skb)->data, (*skb)->len); | |
1825 | fcs = ~fcs; | |
1826 | ||
1827 | skb_put_u8(*skb, fcs & 0xff); | |
1828 | skb_put_u8(*skb, (fcs >> 8) & 0xff); | |
1829 | skb_put_u8(*skb, (fcs >> 16) & 0xff); | |
1830 | skb_put_u8(*skb, (fcs >> 24) & 0xff); | |
1831 | ||
1832 | return 0; | |
1833 | } | |
1834 | ||
d1c38957 | 1835 | static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev) |
a4c35ed3 | 1836 | { |
02c958dd | 1837 | u16 queue_index = skb_get_queue_mapping(skb); |
a4c35ed3 | 1838 | struct macb *bp = netdev_priv(dev); |
02c958dd | 1839 | struct macb_queue *queue = &bp->queues[queue_index]; |
4871953c | 1840 | unsigned long flags; |
1629dd4f RO |
1841 | unsigned int desc_cnt, nr_frags, frag_size, f; |
1842 | unsigned int hdrlen; | |
1843 | bool is_lso, is_udp = 0; | |
d1c38957 | 1844 | netdev_tx_t ret = NETDEV_TX_OK; |
1629dd4f | 1845 | |
33729f25 CB |
1846 | if (macb_clear_csum(skb)) { |
1847 | dev_kfree_skb_any(skb); | |
1848 | return ret; | |
1849 | } | |
1850 | ||
653e92a9 CB |
1851 | if (macb_pad_and_fcs(&skb, dev)) { |
1852 | dev_kfree_skb_any(skb); | |
1853 | return ret; | |
1854 | } | |
1855 | ||
1629dd4f RO |
1856 | is_lso = (skb_shinfo(skb)->gso_size != 0); |
1857 | ||
1858 | if (is_lso) { | |
1859 | is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP); | |
1860 | ||
1861 | /* length of headers */ | |
1862 | if (is_udp) | |
1863 | /* only queue eth + ip headers separately for UDP */ | |
1864 | hdrlen = skb_transport_offset(skb); | |
1865 | else | |
1866 | hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
1867 | if (skb_headlen(skb) < hdrlen) { | |
1868 | netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n"); | |
1869 | /* if this is required, would need to copy to single buffer */ | |
1870 | return NETDEV_TX_BUSY; | |
1871 | } | |
1872 | } else | |
1873 | hdrlen = min(skb_headlen(skb), bp->max_tx_length); | |
89e5785f | 1874 | |
a268adb1 HS |
1875 | #if defined(DEBUG) && defined(VERBOSE_DEBUG) |
1876 | netdev_vdbg(bp->dev, | |
aa50b552 MF |
1877 | "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n", |
1878 | queue_index, skb->len, skb->head, skb->data, | |
1879 | skb_tail_pointer(skb), skb_end_pointer(skb)); | |
c220f8cd JI |
1880 | print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, |
1881 | skb->data, 16, true); | |
89e5785f HS |
1882 | #endif |
1883 | ||
a4c35ed3 CP |
1884 | /* Count how many TX buffer descriptors are needed to send this |
1885 | * socket buffer: skb fragments of jumbo frames may need to be | |
aa50b552 | 1886 | * split into many buffer descriptors. |
a4c35ed3 | 1887 | */ |
1629dd4f RO |
1888 | if (is_lso && (skb_headlen(skb) > hdrlen)) |
1889 | /* extra header descriptor if also payload in first buffer */ | |
1890 | desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1; | |
1891 | else | |
1892 | desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length); | |
a4c35ed3 CP |
1893 | nr_frags = skb_shinfo(skb)->nr_frags; |
1894 | for (f = 0; f < nr_frags; f++) { | |
1895 | frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); | |
1629dd4f | 1896 | desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length); |
a4c35ed3 CP |
1897 | } |
1898 | ||
4871953c | 1899 | spin_lock_irqsave(&bp->lock, flags); |
89e5785f HS |
1900 | |
1901 | /* This is a hard error, log it. */ | |
b410d13e | 1902 | if (CIRC_SPACE(queue->tx_head, queue->tx_tail, |
1629dd4f | 1903 | bp->tx_ring_size) < desc_cnt) { |
02c958dd | 1904 | netif_stop_subqueue(dev, queue_index); |
4871953c | 1905 | spin_unlock_irqrestore(&bp->lock, flags); |
c220f8cd | 1906 | netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", |
02c958dd | 1907 | queue->tx_head, queue->tx_tail); |
5b548140 | 1908 | return NETDEV_TX_BUSY; |
89e5785f HS |
1909 | } |
1910 | ||
a4c35ed3 | 1911 | /* Map socket buffer for DMA transfer */ |
1629dd4f | 1912 | if (!macb_tx_map(bp, queue, skb, hdrlen)) { |
c88b5b6a | 1913 | dev_kfree_skb_any(skb); |
92030908 SB |
1914 | goto unlock; |
1915 | } | |
55054a16 | 1916 | |
03dbe05f | 1917 | /* Make newly initialized descriptor visible to hardware */ |
89e5785f | 1918 | wmb(); |
e072092f RC |
1919 | skb_tx_timestamp(skb); |
1920 | ||
89e5785f HS |
1921 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); |
1922 | ||
b410d13e | 1923 | if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1) |
02c958dd | 1924 | netif_stop_subqueue(dev, queue_index); |
89e5785f | 1925 | |
92030908 | 1926 | unlock: |
4871953c | 1927 | spin_unlock_irqrestore(&bp->lock, flags); |
89e5785f | 1928 | |
d1c38957 | 1929 | return ret; |
89e5785f HS |
1930 | } |
1931 | ||
4df95131 | 1932 | static void macb_init_rx_buffer_size(struct macb *bp, size_t size) |
1b44791a NF |
1933 | { |
1934 | if (!macb_is_gem(bp)) { | |
1935 | bp->rx_buffer_size = MACB_RX_BUFFER_SIZE; | |
1936 | } else { | |
4df95131 | 1937 | bp->rx_buffer_size = size; |
1b44791a | 1938 | |
1b44791a | 1939 | if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) { |
4df95131 | 1940 | netdev_dbg(bp->dev, |
aa50b552 MF |
1941 | "RX buffer must be multiple of %d bytes, expanding\n", |
1942 | RX_BUFFER_MULTIPLE); | |
1b44791a | 1943 | bp->rx_buffer_size = |
4df95131 | 1944 | roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE); |
1b44791a | 1945 | } |
1b44791a | 1946 | } |
4df95131 | 1947 | |
5b5e0928 | 1948 | netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n", |
4df95131 | 1949 | bp->dev->mtu, bp->rx_buffer_size); |
1b44791a NF |
1950 | } |
1951 | ||
4df95131 NF |
1952 | static void gem_free_rx_buffers(struct macb *bp) |
1953 | { | |
1954 | struct sk_buff *skb; | |
1955 | struct macb_dma_desc *desc; | |
ae1f2a56 | 1956 | struct macb_queue *queue; |
4df95131 | 1957 | dma_addr_t addr; |
ae1f2a56 | 1958 | unsigned int q; |
4df95131 NF |
1959 | int i; |
1960 | ||
ae1f2a56 RO |
1961 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
1962 | if (!queue->rx_skbuff) | |
1963 | continue; | |
4df95131 | 1964 | |
ae1f2a56 RO |
1965 | for (i = 0; i < bp->rx_ring_size; i++) { |
1966 | skb = queue->rx_skbuff[i]; | |
4df95131 | 1967 | |
ae1f2a56 RO |
1968 | if (!skb) |
1969 | continue; | |
4df95131 | 1970 | |
ae1f2a56 RO |
1971 | desc = macb_rx_desc(queue, i); |
1972 | addr = macb_get_addr(bp, desc); | |
dc97a89e | 1973 | |
ae1f2a56 RO |
1974 | dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size, |
1975 | DMA_FROM_DEVICE); | |
1976 | dev_kfree_skb_any(skb); | |
1977 | skb = NULL; | |
1978 | } | |
4df95131 | 1979 | |
ae1f2a56 RO |
1980 | kfree(queue->rx_skbuff); |
1981 | queue->rx_skbuff = NULL; | |
1982 | } | |
4df95131 NF |
1983 | } |
1984 | ||
1985 | static void macb_free_rx_buffers(struct macb *bp) | |
1986 | { | |
ae1f2a56 RO |
1987 | struct macb_queue *queue = &bp->queues[0]; |
1988 | ||
1989 | if (queue->rx_buffers) { | |
4df95131 | 1990 | dma_free_coherent(&bp->pdev->dev, |
b410d13e | 1991 | bp->rx_ring_size * bp->rx_buffer_size, |
ae1f2a56 RO |
1992 | queue->rx_buffers, queue->rx_buffers_dma); |
1993 | queue->rx_buffers = NULL; | |
4df95131 NF |
1994 | } |
1995 | } | |
1b44791a | 1996 | |
89e5785f HS |
1997 | static void macb_free_consistent(struct macb *bp) |
1998 | { | |
02c958dd CP |
1999 | struct macb_queue *queue; |
2000 | unsigned int q; | |
404cd086 | 2001 | int size; |
02c958dd | 2002 | |
4df95131 | 2003 | bp->macbgem_ops.mog_free_rx_buffers(bp); |
02c958dd CP |
2004 | |
2005 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { | |
2006 | kfree(queue->tx_skb); | |
2007 | queue->tx_skb = NULL; | |
2008 | if (queue->tx_ring) { | |
404cd086 HK |
2009 | size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch; |
2010 | dma_free_coherent(&bp->pdev->dev, size, | |
02c958dd CP |
2011 | queue->tx_ring, queue->tx_ring_dma); |
2012 | queue->tx_ring = NULL; | |
2013 | } | |
e50b770e | 2014 | if (queue->rx_ring) { |
404cd086 HK |
2015 | size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch; |
2016 | dma_free_coherent(&bp->pdev->dev, size, | |
e50b770e HK |
2017 | queue->rx_ring, queue->rx_ring_dma); |
2018 | queue->rx_ring = NULL; | |
2019 | } | |
89e5785f | 2020 | } |
4df95131 NF |
2021 | } |
2022 | ||
2023 | static int gem_alloc_rx_buffers(struct macb *bp) | |
2024 | { | |
ae1f2a56 RO |
2025 | struct macb_queue *queue; |
2026 | unsigned int q; | |
4df95131 NF |
2027 | int size; |
2028 | ||
ae1f2a56 RO |
2029 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
2030 | size = bp->rx_ring_size * sizeof(struct sk_buff *); | |
2031 | queue->rx_skbuff = kzalloc(size, GFP_KERNEL); | |
2032 | if (!queue->rx_skbuff) | |
2033 | return -ENOMEM; | |
2034 | else | |
2035 | netdev_dbg(bp->dev, | |
2036 | "Allocated %d RX struct sk_buff entries at %p\n", | |
2037 | bp->rx_ring_size, queue->rx_skbuff); | |
2038 | } | |
4df95131 NF |
2039 | return 0; |
2040 | } | |
2041 | ||
2042 | static int macb_alloc_rx_buffers(struct macb *bp) | |
2043 | { | |
ae1f2a56 | 2044 | struct macb_queue *queue = &bp->queues[0]; |
4df95131 NF |
2045 | int size; |
2046 | ||
b410d13e | 2047 | size = bp->rx_ring_size * bp->rx_buffer_size; |
ae1f2a56 RO |
2048 | queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, |
2049 | &queue->rx_buffers_dma, GFP_KERNEL); | |
2050 | if (!queue->rx_buffers) | |
4df95131 | 2051 | return -ENOMEM; |
64ec42fe MF |
2052 | |
2053 | netdev_dbg(bp->dev, | |
2054 | "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", | |
ae1f2a56 | 2055 | size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers); |
4df95131 | 2056 | return 0; |
89e5785f HS |
2057 | } |
2058 | ||
2059 | static int macb_alloc_consistent(struct macb *bp) | |
2060 | { | |
02c958dd CP |
2061 | struct macb_queue *queue; |
2062 | unsigned int q; | |
89e5785f HS |
2063 | int size; |
2064 | ||
02c958dd | 2065 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
404cd086 | 2066 | size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch; |
02c958dd CP |
2067 | queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, |
2068 | &queue->tx_ring_dma, | |
2069 | GFP_KERNEL); | |
2070 | if (!queue->tx_ring) | |
2071 | goto out_err; | |
2072 | netdev_dbg(bp->dev, | |
2073 | "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n", | |
2074 | q, size, (unsigned long)queue->tx_ring_dma, | |
2075 | queue->tx_ring); | |
2076 | ||
b410d13e | 2077 | size = bp->tx_ring_size * sizeof(struct macb_tx_skb); |
02c958dd CP |
2078 | queue->tx_skb = kmalloc(size, GFP_KERNEL); |
2079 | if (!queue->tx_skb) | |
2080 | goto out_err; | |
89e5785f | 2081 | |
404cd086 | 2082 | size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch; |
ae1f2a56 RO |
2083 | queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, |
2084 | &queue->rx_ring_dma, GFP_KERNEL); | |
2085 | if (!queue->rx_ring) | |
2086 | goto out_err; | |
2087 | netdev_dbg(bp->dev, | |
2088 | "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", | |
2089 | size, (unsigned long)queue->rx_ring_dma, queue->rx_ring); | |
2090 | } | |
4df95131 | 2091 | if (bp->macbgem_ops.mog_alloc_rx_buffers(bp)) |
89e5785f | 2092 | goto out_err; |
89e5785f HS |
2093 | |
2094 | return 0; | |
2095 | ||
2096 | out_err: | |
2097 | macb_free_consistent(bp); | |
2098 | return -ENOMEM; | |
2099 | } | |
2100 | ||
4df95131 NF |
2101 | static void gem_init_rings(struct macb *bp) |
2102 | { | |
02c958dd | 2103 | struct macb_queue *queue; |
dc97a89e | 2104 | struct macb_dma_desc *desc = NULL; |
02c958dd | 2105 | unsigned int q; |
4df95131 NF |
2106 | int i; |
2107 | ||
02c958dd | 2108 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
b410d13e | 2109 | for (i = 0; i < bp->tx_ring_size; i++) { |
dc97a89e RO |
2110 | desc = macb_tx_desc(queue, i); |
2111 | macb_set_addr(bp, desc, 0); | |
2112 | desc->ctrl = MACB_BIT(TX_USED); | |
02c958dd | 2113 | } |
dc97a89e | 2114 | desc->ctrl |= MACB_BIT(TX_WRAP); |
02c958dd CP |
2115 | queue->tx_head = 0; |
2116 | queue->tx_tail = 0; | |
4df95131 | 2117 | |
ae1f2a56 RO |
2118 | queue->rx_tail = 0; |
2119 | queue->rx_prepared_head = 0; | |
2120 | ||
2121 | gem_rx_refill(queue); | |
2122 | } | |
4df95131 | 2123 | |
4df95131 NF |
2124 | } |
2125 | ||
89e5785f HS |
2126 | static void macb_init_rings(struct macb *bp) |
2127 | { | |
2128 | int i; | |
dc97a89e | 2129 | struct macb_dma_desc *desc = NULL; |
89e5785f | 2130 | |
ae1f2a56 | 2131 | macb_init_rx_ring(&bp->queues[0]); |
89e5785f | 2132 | |
b410d13e | 2133 | for (i = 0; i < bp->tx_ring_size; i++) { |
dc97a89e RO |
2134 | desc = macb_tx_desc(&bp->queues[0], i); |
2135 | macb_set_addr(bp, desc, 0); | |
2136 | desc->ctrl = MACB_BIT(TX_USED); | |
89e5785f | 2137 | } |
21d3515c BS |
2138 | bp->queues[0].tx_head = 0; |
2139 | bp->queues[0].tx_tail = 0; | |
dc97a89e | 2140 | desc->ctrl |= MACB_BIT(TX_WRAP); |
89e5785f HS |
2141 | } |
2142 | ||
2143 | static void macb_reset_hw(struct macb *bp) | |
2144 | { | |
02c958dd CP |
2145 | struct macb_queue *queue; |
2146 | unsigned int q; | |
0da70f80 | 2147 | u32 ctrl = macb_readl(bp, NCR); |
02c958dd | 2148 | |
64ec42fe | 2149 | /* Disable RX and TX (XXX: Should we halt the transmission |
89e5785f HS |
2150 | * more gracefully?) |
2151 | */ | |
0da70f80 | 2152 | ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE)); |
89e5785f HS |
2153 | |
2154 | /* Clear the stats registers (XXX: Update stats first?) */ | |
0da70f80 AH |
2155 | ctrl |= MACB_BIT(CLRSTAT); |
2156 | ||
2157 | macb_writel(bp, NCR, ctrl); | |
89e5785f HS |
2158 | |
2159 | /* Clear all status flags */ | |
95ebcea6 JE |
2160 | macb_writel(bp, TSR, -1); |
2161 | macb_writel(bp, RSR, -1); | |
89e5785f HS |
2162 | |
2163 | /* Disable all interrupts */ | |
02c958dd CP |
2164 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
2165 | queue_writel(queue, IDR, -1); | |
2166 | queue_readl(queue, ISR); | |
24468374 NS |
2167 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
2168 | queue_writel(queue, ISR, -1); | |
02c958dd | 2169 | } |
89e5785f HS |
2170 | } |
2171 | ||
70c9f3d4 JI |
2172 | static u32 gem_mdc_clk_div(struct macb *bp) |
2173 | { | |
2174 | u32 config; | |
2175 | unsigned long pclk_hz = clk_get_rate(bp->pclk); | |
2176 | ||
2177 | if (pclk_hz <= 20000000) | |
2178 | config = GEM_BF(CLK, GEM_CLK_DIV8); | |
2179 | else if (pclk_hz <= 40000000) | |
2180 | config = GEM_BF(CLK, GEM_CLK_DIV16); | |
2181 | else if (pclk_hz <= 80000000) | |
2182 | config = GEM_BF(CLK, GEM_CLK_DIV32); | |
2183 | else if (pclk_hz <= 120000000) | |
2184 | config = GEM_BF(CLK, GEM_CLK_DIV48); | |
2185 | else if (pclk_hz <= 160000000) | |
2186 | config = GEM_BF(CLK, GEM_CLK_DIV64); | |
2187 | else | |
2188 | config = GEM_BF(CLK, GEM_CLK_DIV96); | |
2189 | ||
2190 | return config; | |
2191 | } | |
2192 | ||
2193 | static u32 macb_mdc_clk_div(struct macb *bp) | |
2194 | { | |
2195 | u32 config; | |
2196 | unsigned long pclk_hz; | |
2197 | ||
2198 | if (macb_is_gem(bp)) | |
2199 | return gem_mdc_clk_div(bp); | |
2200 | ||
2201 | pclk_hz = clk_get_rate(bp->pclk); | |
2202 | if (pclk_hz <= 20000000) | |
2203 | config = MACB_BF(CLK, MACB_CLK_DIV8); | |
2204 | else if (pclk_hz <= 40000000) | |
2205 | config = MACB_BF(CLK, MACB_CLK_DIV16); | |
2206 | else if (pclk_hz <= 80000000) | |
2207 | config = MACB_BF(CLK, MACB_CLK_DIV32); | |
2208 | else | |
2209 | config = MACB_BF(CLK, MACB_CLK_DIV64); | |
2210 | ||
2211 | return config; | |
2212 | } | |
2213 | ||
64ec42fe | 2214 | /* Get the DMA bus width field of the network configuration register that we |
757a03c6 JI |
2215 | * should program. We find the width from decoding the design configuration |
2216 | * register to find the maximum supported data bus width. | |
2217 | */ | |
2218 | static u32 macb_dbw(struct macb *bp) | |
2219 | { | |
2220 | if (!macb_is_gem(bp)) | |
2221 | return 0; | |
2222 | ||
2223 | switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { | |
2224 | case 4: | |
2225 | return GEM_BF(DBW, GEM_DBW128); | |
2226 | case 2: | |
2227 | return GEM_BF(DBW, GEM_DBW64); | |
2228 | case 1: | |
2229 | default: | |
2230 | return GEM_BF(DBW, GEM_DBW32); | |
2231 | } | |
2232 | } | |
2233 | ||
64ec42fe | 2234 | /* Configure the receive DMA engine |
b3e3bd71 | 2235 | * - use the correct receive buffer size |
e175587f | 2236 | * - set best burst length for DMA operations |
b3e3bd71 NF |
2237 | * (if not supported by FIFO, it will fallback to default) |
2238 | * - set both rx/tx packet buffers to full memory size | |
2239 | * These are configurable parameters for GEM. | |
0116da4f JI |
2240 | */ |
2241 | static void macb_configure_dma(struct macb *bp) | |
2242 | { | |
ae1f2a56 RO |
2243 | struct macb_queue *queue; |
2244 | u32 buffer_size; | |
2245 | unsigned int q; | |
0116da4f JI |
2246 | u32 dmacfg; |
2247 | ||
ae1f2a56 | 2248 | buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE; |
0116da4f JI |
2249 | if (macb_is_gem(bp)) { |
2250 | dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); | |
ae1f2a56 RO |
2251 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
2252 | if (q) | |
2253 | queue_writel(queue, RBQS, buffer_size); | |
2254 | else | |
2255 | dmacfg |= GEM_BF(RXBS, buffer_size); | |
2256 | } | |
e175587f NF |
2257 | if (bp->dma_burst_length) |
2258 | dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); | |
b3e3bd71 | 2259 | dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); |
a50dad35 | 2260 | dmacfg &= ~GEM_BIT(ENDIA_PKT); |
62f6924c | 2261 | |
f2ce8a9e | 2262 | if (bp->native_io) |
62f6924c AC |
2263 | dmacfg &= ~GEM_BIT(ENDIA_DESC); |
2264 | else | |
2265 | dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */ | |
2266 | ||
85ff3d87 CP |
2267 | if (bp->dev->features & NETIF_F_HW_CSUM) |
2268 | dmacfg |= GEM_BIT(TXCOEN); | |
2269 | else | |
2270 | dmacfg &= ~GEM_BIT(TXCOEN); | |
fff8019a | 2271 | |
bd620720 | 2272 | dmacfg &= ~GEM_BIT(ADDR64); |
fff8019a | 2273 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
7b429614 | 2274 | if (bp->hw_dma_cap & HW_DMA_CAP_64B) |
dc97a89e | 2275 | dmacfg |= GEM_BIT(ADDR64); |
7b429614 RO |
2276 | #endif |
2277 | #ifdef CONFIG_MACB_USE_HWSTAMP | |
2278 | if (bp->hw_dma_cap & HW_DMA_CAP_PTP) | |
2279 | dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT); | |
fff8019a | 2280 | #endif |
e175587f NF |
2281 | netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n", |
2282 | dmacfg); | |
0116da4f JI |
2283 | gem_writel(bp, DMACFG, dmacfg); |
2284 | } | |
2285 | } | |
2286 | ||
89e5785f HS |
2287 | static void macb_init_hw(struct macb *bp) |
2288 | { | |
2289 | u32 config; | |
2290 | ||
2291 | macb_reset_hw(bp); | |
314bccc4 | 2292 | macb_set_hwaddr(bp); |
89e5785f | 2293 | |
70c9f3d4 | 2294 | config = macb_mdc_clk_div(bp); |
29bc2e1e | 2295 | config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */ |
89e5785f | 2296 | config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ |
a104a6b3 | 2297 | if (bp->caps & MACB_CAPS_JUMBO) |
98b5a0f4 HK |
2298 | config |= MACB_BIT(JFRAME); /* Enable jumbo frames */ |
2299 | else | |
2300 | config |= MACB_BIT(BIG); /* Receive oversized frames */ | |
89e5785f HS |
2301 | if (bp->dev->flags & IFF_PROMISC) |
2302 | config |= MACB_BIT(CAF); /* Copy All Frames */ | |
924ec53c CP |
2303 | else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM) |
2304 | config |= GEM_BIT(RXCOEN); | |
89e5785f HS |
2305 | if (!(bp->dev->flags & IFF_BROADCAST)) |
2306 | config |= MACB_BIT(NBC); /* No BroadCast */ | |
757a03c6 | 2307 | config |= macb_dbw(bp); |
89e5785f | 2308 | macb_writel(bp, NCFGR, config); |
a104a6b3 | 2309 | if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len) |
98b5a0f4 | 2310 | gem_writel(bp, JML, bp->jumbo_max_len); |
98b5a0f4 | 2311 | bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK; |
a104a6b3 | 2312 | if (bp->caps & MACB_CAPS_JUMBO) |
98b5a0f4 | 2313 | bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; |
89e5785f | 2314 | |
0116da4f | 2315 | macb_configure_dma(bp); |
89e5785f HS |
2316 | } |
2317 | ||
64ec42fe | 2318 | /* The hash address register is 64 bits long and takes up two |
446ebd01 PV |
2319 | * locations in the memory map. The least significant bits are stored |
2320 | * in EMAC_HSL and the most significant bits in EMAC_HSH. | |
2321 | * | |
2322 | * The unicast hash enable and the multicast hash enable bits in the | |
2323 | * network configuration register enable the reception of hash matched | |
2324 | * frames. The destination address is reduced to a 6 bit index into | |
2325 | * the 64 bit hash register using the following hash function. The | |
2326 | * hash function is an exclusive or of every sixth bit of the | |
2327 | * destination address. | |
2328 | * | |
2329 | * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
2330 | * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
2331 | * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
2332 | * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
2333 | * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
2334 | * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
2335 | * | |
2336 | * da[0] represents the least significant bit of the first byte | |
2337 | * received, that is, the multicast/unicast indicator, and da[47] | |
2338 | * represents the most significant bit of the last byte received. If | |
2339 | * the hash index, hi[n], points to a bit that is set in the hash | |
2340 | * register then the frame will be matched according to whether the | |
2341 | * frame is multicast or unicast. A multicast match will be signalled | |
2342 | * if the multicast hash enable bit is set, da[0] is 1 and the hash | |
2343 | * index points to a bit set in the hash register. A unicast match | |
2344 | * will be signalled if the unicast hash enable bit is set, da[0] is 0 | |
2345 | * and the hash index points to a bit set in the hash register. To | |
2346 | * receive all multicast frames, the hash register should be set with | |
2347 | * all ones and the multicast hash enable bit should be set in the | |
2348 | * network configuration register. | |
2349 | */ | |
2350 | ||
2351 | static inline int hash_bit_value(int bitnr, __u8 *addr) | |
2352 | { | |
2353 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
2354 | return 1; | |
2355 | return 0; | |
2356 | } | |
2357 | ||
64ec42fe | 2358 | /* Return the hash index value for the specified address. */ |
446ebd01 PV |
2359 | static int hash_get_index(__u8 *addr) |
2360 | { | |
2361 | int i, j, bitval; | |
2362 | int hash_index = 0; | |
2363 | ||
2364 | for (j = 0; j < 6; j++) { | |
2365 | for (i = 0, bitval = 0; i < 8; i++) | |
2fa45e22 | 2366 | bitval ^= hash_bit_value(i * 6 + j, addr); |
446ebd01 PV |
2367 | |
2368 | hash_index |= (bitval << j); | |
2369 | } | |
2370 | ||
2371 | return hash_index; | |
2372 | } | |
2373 | ||
64ec42fe | 2374 | /* Add multicast addresses to the internal multicast-hash table. */ |
446ebd01 PV |
2375 | static void macb_sethashtable(struct net_device *dev) |
2376 | { | |
22bedad3 | 2377 | struct netdev_hw_addr *ha; |
446ebd01 | 2378 | unsigned long mc_filter[2]; |
f9dcbcc9 | 2379 | unsigned int bitnr; |
446ebd01 PV |
2380 | struct macb *bp = netdev_priv(dev); |
2381 | ||
aa50b552 MF |
2382 | mc_filter[0] = 0; |
2383 | mc_filter[1] = 0; | |
446ebd01 | 2384 | |
22bedad3 JP |
2385 | netdev_for_each_mc_addr(ha, dev) { |
2386 | bitnr = hash_get_index(ha->addr); | |
446ebd01 PV |
2387 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); |
2388 | } | |
2389 | ||
f75ba50b JI |
2390 | macb_or_gem_writel(bp, HRB, mc_filter[0]); |
2391 | macb_or_gem_writel(bp, HRT, mc_filter[1]); | |
446ebd01 PV |
2392 | } |
2393 | ||
64ec42fe | 2394 | /* Enable/Disable promiscuous and multicast modes. */ |
421d9df0 | 2395 | static void macb_set_rx_mode(struct net_device *dev) |
446ebd01 PV |
2396 | { |
2397 | unsigned long cfg; | |
2398 | struct macb *bp = netdev_priv(dev); | |
2399 | ||
2400 | cfg = macb_readl(bp, NCFGR); | |
2401 | ||
924ec53c | 2402 | if (dev->flags & IFF_PROMISC) { |
446ebd01 PV |
2403 | /* Enable promiscuous mode */ |
2404 | cfg |= MACB_BIT(CAF); | |
924ec53c CP |
2405 | |
2406 | /* Disable RX checksum offload */ | |
2407 | if (macb_is_gem(bp)) | |
2408 | cfg &= ~GEM_BIT(RXCOEN); | |
2409 | } else { | |
2410 | /* Disable promiscuous mode */ | |
446ebd01 PV |
2411 | cfg &= ~MACB_BIT(CAF); |
2412 | ||
924ec53c CP |
2413 | /* Enable RX checksum offload only if requested */ |
2414 | if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM) | |
2415 | cfg |= GEM_BIT(RXCOEN); | |
2416 | } | |
2417 | ||
446ebd01 PV |
2418 | if (dev->flags & IFF_ALLMULTI) { |
2419 | /* Enable all multicast mode */ | |
f75ba50b JI |
2420 | macb_or_gem_writel(bp, HRB, -1); |
2421 | macb_or_gem_writel(bp, HRT, -1); | |
446ebd01 | 2422 | cfg |= MACB_BIT(NCFGR_MTI); |
4cd24eaf | 2423 | } else if (!netdev_mc_empty(dev)) { |
446ebd01 PV |
2424 | /* Enable specific multicasts */ |
2425 | macb_sethashtable(dev); | |
2426 | cfg |= MACB_BIT(NCFGR_MTI); | |
2427 | } else if (dev->flags & (~IFF_ALLMULTI)) { | |
2428 | /* Disable all multicast mode */ | |
f75ba50b JI |
2429 | macb_or_gem_writel(bp, HRB, 0); |
2430 | macb_or_gem_writel(bp, HRT, 0); | |
446ebd01 PV |
2431 | cfg &= ~MACB_BIT(NCFGR_MTI); |
2432 | } | |
2433 | ||
2434 | macb_writel(bp, NCFGR, cfg); | |
2435 | } | |
2436 | ||
89e5785f HS |
2437 | static int macb_open(struct net_device *dev) |
2438 | { | |
4df95131 | 2439 | size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN; |
7897b071 | 2440 | struct macb *bp = netdev_priv(dev); |
ae1f2a56 RO |
2441 | struct macb_queue *queue; |
2442 | unsigned int q; | |
89e5785f HS |
2443 | int err; |
2444 | ||
c220f8cd | 2445 | netdev_dbg(bp->dev, "open\n"); |
89e5785f | 2446 | |
d54f89af HK |
2447 | err = pm_runtime_get_sync(&bp->pdev->dev); |
2448 | if (err < 0) | |
2449 | goto pm_exit; | |
2450 | ||
1b44791a | 2451 | /* RX buffers initialization */ |
4df95131 | 2452 | macb_init_rx_buffer_size(bp, bufsz); |
6c36a707 | 2453 | |
89e5785f HS |
2454 | err = macb_alloc_consistent(bp); |
2455 | if (err) { | |
c220f8cd JI |
2456 | netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", |
2457 | err); | |
d54f89af | 2458 | goto pm_exit; |
89e5785f HS |
2459 | } |
2460 | ||
ae1f2a56 RO |
2461 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) |
2462 | napi_enable(&queue->napi); | |
2463 | ||
05044531 | 2464 | macb_init_hw(bp); |
ae1f2a56 | 2465 | |
7897b071 AT |
2466 | err = macb_phylink_connect(bp); |
2467 | if (err) | |
2468 | goto pm_exit; | |
89e5785f | 2469 | |
02c958dd | 2470 | netif_tx_start_all_queues(dev); |
89e5785f | 2471 | |
c2594d80 AP |
2472 | if (bp->ptp_info) |
2473 | bp->ptp_info->ptp_init(dev); | |
2474 | ||
d54f89af HK |
2475 | pm_exit: |
2476 | if (err) { | |
2477 | pm_runtime_put_sync(&bp->pdev->dev); | |
2478 | return err; | |
2479 | } | |
89e5785f HS |
2480 | return 0; |
2481 | } | |
2482 | ||
2483 | static int macb_close(struct net_device *dev) | |
2484 | { | |
2485 | struct macb *bp = netdev_priv(dev); | |
ae1f2a56 | 2486 | struct macb_queue *queue; |
89e5785f | 2487 | unsigned long flags; |
ae1f2a56 | 2488 | unsigned int q; |
89e5785f | 2489 | |
02c958dd | 2490 | netif_tx_stop_all_queues(dev); |
ae1f2a56 RO |
2491 | |
2492 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) | |
2493 | napi_disable(&queue->napi); | |
89e5785f | 2494 | |
7897b071 AT |
2495 | phylink_stop(bp->phylink); |
2496 | phylink_disconnect_phy(bp->phylink); | |
6c36a707 | 2497 | |
89e5785f HS |
2498 | spin_lock_irqsave(&bp->lock, flags); |
2499 | macb_reset_hw(bp); | |
2500 | netif_carrier_off(dev); | |
2501 | spin_unlock_irqrestore(&bp->lock, flags); | |
2502 | ||
2503 | macb_free_consistent(bp); | |
2504 | ||
c2594d80 AP |
2505 | if (bp->ptp_info) |
2506 | bp->ptp_info->ptp_remove(dev); | |
2507 | ||
d54f89af HK |
2508 | pm_runtime_put(&bp->pdev->dev); |
2509 | ||
89e5785f HS |
2510 | return 0; |
2511 | } | |
2512 | ||
a5898ea0 HK |
2513 | static int macb_change_mtu(struct net_device *dev, int new_mtu) |
2514 | { | |
a5898ea0 HK |
2515 | if (netif_running(dev)) |
2516 | return -EBUSY; | |
2517 | ||
a5898ea0 HK |
2518 | dev->mtu = new_mtu; |
2519 | ||
2520 | return 0; | |
2521 | } | |
2522 | ||
a494ed8e JI |
2523 | static void gem_update_stats(struct macb *bp) |
2524 | { | |
512286bb RO |
2525 | struct macb_queue *queue; |
2526 | unsigned int i, q, idx; | |
2527 | unsigned long *stat; | |
2528 | ||
a494ed8e | 2529 | u32 *p = &bp->hw_stats.gem.tx_octets_31_0; |
a494ed8e | 2530 | |
3ff13f1c XH |
2531 | for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { |
2532 | u32 offset = gem_statistics[i].offset; | |
7a6e0706 | 2533 | u64 val = bp->macb_reg_readl(bp, offset); |
3ff13f1c XH |
2534 | |
2535 | bp->ethtool_stats[i] += val; | |
2536 | *p += val; | |
2537 | ||
2538 | if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { | |
2539 | /* Add GEM_OCTTXH, GEM_OCTRXH */ | |
7a6e0706 | 2540 | val = bp->macb_reg_readl(bp, offset + 4); |
2fa45e22 | 2541 | bp->ethtool_stats[i] += ((u64)val) << 32; |
3ff13f1c XH |
2542 | *(++p) += val; |
2543 | } | |
2544 | } | |
512286bb RO |
2545 | |
2546 | idx = GEM_STATS_LEN; | |
2547 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) | |
2548 | for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat) | |
2549 | bp->ethtool_stats[idx++] = *stat; | |
a494ed8e JI |
2550 | } |
2551 | ||
2552 | static struct net_device_stats *gem_get_stats(struct macb *bp) | |
2553 | { | |
2554 | struct gem_stats *hwstat = &bp->hw_stats.gem; | |
5f1d3a5c | 2555 | struct net_device_stats *nstat = &bp->dev->stats; |
a494ed8e JI |
2556 | |
2557 | gem_update_stats(bp); | |
2558 | ||
2559 | nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + | |
2560 | hwstat->rx_alignment_errors + | |
2561 | hwstat->rx_resource_errors + | |
2562 | hwstat->rx_overruns + | |
2563 | hwstat->rx_oversize_frames + | |
2564 | hwstat->rx_jabbers + | |
2565 | hwstat->rx_undersized_frames + | |
2566 | hwstat->rx_length_field_frame_errors); | |
2567 | nstat->tx_errors = (hwstat->tx_late_collisions + | |
2568 | hwstat->tx_excessive_collisions + | |
2569 | hwstat->tx_underrun + | |
2570 | hwstat->tx_carrier_sense_errors); | |
2571 | nstat->multicast = hwstat->rx_multicast_frames; | |
2572 | nstat->collisions = (hwstat->tx_single_collision_frames + | |
2573 | hwstat->tx_multiple_collision_frames + | |
2574 | hwstat->tx_excessive_collisions); | |
2575 | nstat->rx_length_errors = (hwstat->rx_oversize_frames + | |
2576 | hwstat->rx_jabbers + | |
2577 | hwstat->rx_undersized_frames + | |
2578 | hwstat->rx_length_field_frame_errors); | |
2579 | nstat->rx_over_errors = hwstat->rx_resource_errors; | |
2580 | nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; | |
2581 | nstat->rx_frame_errors = hwstat->rx_alignment_errors; | |
2582 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
2583 | nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; | |
2584 | nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; | |
2585 | nstat->tx_fifo_errors = hwstat->tx_underrun; | |
2586 | ||
2587 | return nstat; | |
2588 | } | |
2589 | ||
3ff13f1c XH |
2590 | static void gem_get_ethtool_stats(struct net_device *dev, |
2591 | struct ethtool_stats *stats, u64 *data) | |
2592 | { | |
2593 | struct macb *bp; | |
2594 | ||
2595 | bp = netdev_priv(dev); | |
2596 | gem_update_stats(bp); | |
512286bb RO |
2597 | memcpy(data, &bp->ethtool_stats, sizeof(u64) |
2598 | * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES)); | |
3ff13f1c XH |
2599 | } |
2600 | ||
2601 | static int gem_get_sset_count(struct net_device *dev, int sset) | |
2602 | { | |
512286bb RO |
2603 | struct macb *bp = netdev_priv(dev); |
2604 | ||
3ff13f1c XH |
2605 | switch (sset) { |
2606 | case ETH_SS_STATS: | |
512286bb | 2607 | return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN; |
3ff13f1c XH |
2608 | default: |
2609 | return -EOPNOTSUPP; | |
2610 | } | |
2611 | } | |
2612 | ||
2613 | static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p) | |
2614 | { | |
512286bb RO |
2615 | char stat_string[ETH_GSTRING_LEN]; |
2616 | struct macb *bp = netdev_priv(dev); | |
2617 | struct macb_queue *queue; | |
8bcbf82f | 2618 | unsigned int i; |
512286bb | 2619 | unsigned int q; |
3ff13f1c XH |
2620 | |
2621 | switch (sset) { | |
2622 | case ETH_SS_STATS: | |
2623 | for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN) | |
2624 | memcpy(p, gem_statistics[i].stat_string, | |
2625 | ETH_GSTRING_LEN); | |
512286bb RO |
2626 | |
2627 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { | |
2628 | for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) { | |
2629 | snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s", | |
2630 | q, queue_statistics[i].stat_string); | |
2631 | memcpy(p, stat_string, ETH_GSTRING_LEN); | |
2632 | } | |
2633 | } | |
3ff13f1c XH |
2634 | break; |
2635 | } | |
2636 | } | |
2637 | ||
421d9df0 | 2638 | static struct net_device_stats *macb_get_stats(struct net_device *dev) |
89e5785f HS |
2639 | { |
2640 | struct macb *bp = netdev_priv(dev); | |
5f1d3a5c | 2641 | struct net_device_stats *nstat = &bp->dev->stats; |
a494ed8e JI |
2642 | struct macb_stats *hwstat = &bp->hw_stats.macb; |
2643 | ||
2644 | if (macb_is_gem(bp)) | |
2645 | return gem_get_stats(bp); | |
89e5785f | 2646 | |
6c36a707 R |
2647 | /* read stats from hardware */ |
2648 | macb_update_stats(bp); | |
2649 | ||
89e5785f HS |
2650 | /* Convert HW stats into netdevice stats */ |
2651 | nstat->rx_errors = (hwstat->rx_fcs_errors + | |
2652 | hwstat->rx_align_errors + | |
2653 | hwstat->rx_resource_errors + | |
2654 | hwstat->rx_overruns + | |
2655 | hwstat->rx_oversize_pkts + | |
2656 | hwstat->rx_jabbers + | |
2657 | hwstat->rx_undersize_pkts + | |
89e5785f HS |
2658 | hwstat->rx_length_mismatch); |
2659 | nstat->tx_errors = (hwstat->tx_late_cols + | |
2660 | hwstat->tx_excessive_cols + | |
2661 | hwstat->tx_underruns + | |
716723c2 WS |
2662 | hwstat->tx_carrier_errors + |
2663 | hwstat->sqe_test_errors); | |
89e5785f HS |
2664 | nstat->collisions = (hwstat->tx_single_cols + |
2665 | hwstat->tx_multiple_cols + | |
2666 | hwstat->tx_excessive_cols); | |
2667 | nstat->rx_length_errors = (hwstat->rx_oversize_pkts + | |
2668 | hwstat->rx_jabbers + | |
2669 | hwstat->rx_undersize_pkts + | |
2670 | hwstat->rx_length_mismatch); | |
b19f7f71 AS |
2671 | nstat->rx_over_errors = hwstat->rx_resource_errors + |
2672 | hwstat->rx_overruns; | |
89e5785f HS |
2673 | nstat->rx_crc_errors = hwstat->rx_fcs_errors; |
2674 | nstat->rx_frame_errors = hwstat->rx_align_errors; | |
2675 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
2676 | /* XXX: What does "missed" mean? */ | |
2677 | nstat->tx_aborted_errors = hwstat->tx_excessive_cols; | |
2678 | nstat->tx_carrier_errors = hwstat->tx_carrier_errors; | |
2679 | nstat->tx_fifo_errors = hwstat->tx_underruns; | |
2680 | /* Don't know about heartbeat or window errors... */ | |
2681 | ||
2682 | return nstat; | |
2683 | } | |
2684 | ||
d1d1b53d NF |
2685 | static int macb_get_regs_len(struct net_device *netdev) |
2686 | { | |
2687 | return MACB_GREGS_NBR * sizeof(u32); | |
2688 | } | |
2689 | ||
2690 | static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2691 | void *p) | |
2692 | { | |
2693 | struct macb *bp = netdev_priv(dev); | |
2694 | unsigned int tail, head; | |
2695 | u32 *regs_buff = p; | |
2696 | ||
2697 | regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) | |
2698 | | MACB_GREGS_VERSION; | |
2699 | ||
b410d13e ZB |
2700 | tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail); |
2701 | head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head); | |
d1d1b53d NF |
2702 | |
2703 | regs_buff[0] = macb_readl(bp, NCR); | |
2704 | regs_buff[1] = macb_or_gem_readl(bp, NCFGR); | |
2705 | regs_buff[2] = macb_readl(bp, NSR); | |
2706 | regs_buff[3] = macb_readl(bp, TSR); | |
2707 | regs_buff[4] = macb_readl(bp, RBQP); | |
2708 | regs_buff[5] = macb_readl(bp, TBQP); | |
2709 | regs_buff[6] = macb_readl(bp, RSR); | |
2710 | regs_buff[7] = macb_readl(bp, IMR); | |
2711 | ||
2712 | regs_buff[8] = tail; | |
2713 | regs_buff[9] = head; | |
02c958dd CP |
2714 | regs_buff[10] = macb_tx_dma(&bp->queues[0], tail); |
2715 | regs_buff[11] = macb_tx_dma(&bp->queues[0], head); | |
d1d1b53d | 2716 | |
ce721a70 NA |
2717 | if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) |
2718 | regs_buff[12] = macb_or_gem_readl(bp, USRIO); | |
64ec42fe | 2719 | if (macb_is_gem(bp)) |
d1d1b53d | 2720 | regs_buff[13] = gem_readl(bp, DMACFG); |
d1d1b53d NF |
2721 | } |
2722 | ||
3e2a5e15 SP |
2723 | static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) |
2724 | { | |
2725 | struct macb *bp = netdev_priv(netdev); | |
2726 | ||
2727 | wol->supported = 0; | |
2728 | wol->wolopts = 0; | |
2729 | ||
7897b071 AT |
2730 | if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) |
2731 | phylink_ethtool_get_wol(bp->phylink, wol); | |
3e2a5e15 SP |
2732 | } |
2733 | ||
2734 | static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
2735 | { | |
2736 | struct macb *bp = netdev_priv(netdev); | |
7897b071 AT |
2737 | int ret; |
2738 | ||
2739 | ret = phylink_ethtool_set_wol(bp->phylink, wol); | |
2740 | if (!ret) | |
2741 | return 0; | |
3e2a5e15 SP |
2742 | |
2743 | if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) || | |
2744 | (wol->wolopts & ~WAKE_MAGIC)) | |
2745 | return -EOPNOTSUPP; | |
2746 | ||
2747 | if (wol->wolopts & WAKE_MAGIC) | |
2748 | bp->wol |= MACB_WOL_ENABLED; | |
2749 | else | |
2750 | bp->wol &= ~MACB_WOL_ENABLED; | |
2751 | ||
2752 | device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED); | |
2753 | ||
2754 | return 0; | |
2755 | } | |
2756 | ||
7897b071 AT |
2757 | static int macb_get_link_ksettings(struct net_device *netdev, |
2758 | struct ethtool_link_ksettings *kset) | |
2759 | { | |
2760 | struct macb *bp = netdev_priv(netdev); | |
2761 | ||
2762 | return phylink_ethtool_ksettings_get(bp->phylink, kset); | |
2763 | } | |
2764 | ||
2765 | static int macb_set_link_ksettings(struct net_device *netdev, | |
2766 | const struct ethtool_link_ksettings *kset) | |
2767 | { | |
2768 | struct macb *bp = netdev_priv(netdev); | |
2769 | ||
2770 | return phylink_ethtool_ksettings_set(bp->phylink, kset); | |
2771 | } | |
2772 | ||
8441bb33 ZB |
2773 | static void macb_get_ringparam(struct net_device *netdev, |
2774 | struct ethtool_ringparam *ring) | |
2775 | { | |
2776 | struct macb *bp = netdev_priv(netdev); | |
2777 | ||
2778 | ring->rx_max_pending = MAX_RX_RING_SIZE; | |
2779 | ring->tx_max_pending = MAX_TX_RING_SIZE; | |
2780 | ||
2781 | ring->rx_pending = bp->rx_ring_size; | |
2782 | ring->tx_pending = bp->tx_ring_size; | |
2783 | } | |
2784 | ||
2785 | static int macb_set_ringparam(struct net_device *netdev, | |
2786 | struct ethtool_ringparam *ring) | |
2787 | { | |
2788 | struct macb *bp = netdev_priv(netdev); | |
2789 | u32 new_rx_size, new_tx_size; | |
2790 | unsigned int reset = 0; | |
2791 | ||
2792 | if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) | |
2793 | return -EINVAL; | |
2794 | ||
2795 | new_rx_size = clamp_t(u32, ring->rx_pending, | |
2796 | MIN_RX_RING_SIZE, MAX_RX_RING_SIZE); | |
2797 | new_rx_size = roundup_pow_of_two(new_rx_size); | |
2798 | ||
2799 | new_tx_size = clamp_t(u32, ring->tx_pending, | |
2800 | MIN_TX_RING_SIZE, MAX_TX_RING_SIZE); | |
2801 | new_tx_size = roundup_pow_of_two(new_tx_size); | |
2802 | ||
2803 | if ((new_tx_size == bp->tx_ring_size) && | |
2804 | (new_rx_size == bp->rx_ring_size)) { | |
2805 | /* nothing to do */ | |
2806 | return 0; | |
2807 | } | |
2808 | ||
2809 | if (netif_running(bp->dev)) { | |
2810 | reset = 1; | |
2811 | macb_close(bp->dev); | |
2812 | } | |
2813 | ||
2814 | bp->rx_ring_size = new_rx_size; | |
2815 | bp->tx_ring_size = new_tx_size; | |
2816 | ||
2817 | if (reset) | |
2818 | macb_open(bp->dev); | |
2819 | ||
2820 | return 0; | |
2821 | } | |
2822 | ||
ab91f0a9 RO |
2823 | #ifdef CONFIG_MACB_USE_HWSTAMP |
2824 | static unsigned int gem_get_tsu_rate(struct macb *bp) | |
2825 | { | |
2826 | struct clk *tsu_clk; | |
2827 | unsigned int tsu_rate; | |
2828 | ||
2829 | tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk"); | |
2830 | if (!IS_ERR(tsu_clk)) | |
2831 | tsu_rate = clk_get_rate(tsu_clk); | |
2832 | /* try pclk instead */ | |
2833 | else if (!IS_ERR(bp->pclk)) { | |
2834 | tsu_clk = bp->pclk; | |
2835 | tsu_rate = clk_get_rate(tsu_clk); | |
2836 | } else | |
2837 | return -ENOTSUPP; | |
2838 | return tsu_rate; | |
2839 | } | |
2840 | ||
2841 | static s32 gem_get_ptp_max_adj(void) | |
2842 | { | |
2843 | return 64000000; | |
2844 | } | |
2845 | ||
2846 | static int gem_get_ts_info(struct net_device *dev, | |
2847 | struct ethtool_ts_info *info) | |
2848 | { | |
2849 | struct macb *bp = netdev_priv(dev); | |
2850 | ||
2851 | if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) { | |
2852 | ethtool_op_get_ts_info(dev, info); | |
2853 | return 0; | |
2854 | } | |
2855 | ||
2856 | info->so_timestamping = | |
2857 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
2858 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
2859 | SOF_TIMESTAMPING_SOFTWARE | | |
2860 | SOF_TIMESTAMPING_TX_HARDWARE | | |
2861 | SOF_TIMESTAMPING_RX_HARDWARE | | |
2862 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
2863 | info->tx_types = | |
2864 | (1 << HWTSTAMP_TX_ONESTEP_SYNC) | | |
2865 | (1 << HWTSTAMP_TX_OFF) | | |
2866 | (1 << HWTSTAMP_TX_ON); | |
2867 | info->rx_filters = | |
2868 | (1 << HWTSTAMP_FILTER_NONE) | | |
2869 | (1 << HWTSTAMP_FILTER_ALL); | |
2870 | ||
2871 | info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1; | |
2872 | ||
2873 | return 0; | |
2874 | } | |
2875 | ||
2876 | static struct macb_ptp_info gem_ptp_info = { | |
2877 | .ptp_init = gem_ptp_init, | |
2878 | .ptp_remove = gem_ptp_remove, | |
2879 | .get_ptp_max_adj = gem_get_ptp_max_adj, | |
2880 | .get_tsu_rate = gem_get_tsu_rate, | |
2881 | .get_ts_info = gem_get_ts_info, | |
2882 | .get_hwtst = gem_get_hwtst, | |
2883 | .set_hwtst = gem_set_hwtst, | |
2884 | }; | |
2885 | #endif | |
2886 | ||
c2594d80 AP |
2887 | static int macb_get_ts_info(struct net_device *netdev, |
2888 | struct ethtool_ts_info *info) | |
2889 | { | |
2890 | struct macb *bp = netdev_priv(netdev); | |
2891 | ||
2892 | if (bp->ptp_info) | |
2893 | return bp->ptp_info->get_ts_info(netdev, info); | |
2894 | ||
2895 | return ethtool_op_get_ts_info(netdev, info); | |
2896 | } | |
2897 | ||
ae8223de RO |
2898 | static void gem_enable_flow_filters(struct macb *bp, bool enable) |
2899 | { | |
c1e85c6c | 2900 | struct net_device *netdev = bp->dev; |
ae8223de RO |
2901 | struct ethtool_rx_fs_item *item; |
2902 | u32 t2_scr; | |
2903 | int num_t2_scr; | |
2904 | ||
c1e85c6c CB |
2905 | if (!(netdev->features & NETIF_F_NTUPLE)) |
2906 | return; | |
2907 | ||
ae8223de RO |
2908 | num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8)); |
2909 | ||
2910 | list_for_each_entry(item, &bp->rx_fs_list.list, list) { | |
2911 | struct ethtool_rx_flow_spec *fs = &item->fs; | |
2912 | struct ethtool_tcpip4_spec *tp4sp_m; | |
2913 | ||
2914 | if (fs->location >= num_t2_scr) | |
2915 | continue; | |
2916 | ||
2917 | t2_scr = gem_readl_n(bp, SCRT2, fs->location); | |
2918 | ||
2919 | /* enable/disable screener regs for the flow entry */ | |
2920 | t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr); | |
2921 | ||
2922 | /* only enable fields with no masking */ | |
2923 | tp4sp_m = &(fs->m_u.tcp_ip4_spec); | |
2924 | ||
2925 | if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF)) | |
2926 | t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr); | |
2927 | else | |
2928 | t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr); | |
2929 | ||
2930 | if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF)) | |
2931 | t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr); | |
2932 | else | |
2933 | t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr); | |
2934 | ||
2935 | if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF))) | |
2936 | t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr); | |
2937 | else | |
2938 | t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr); | |
2939 | ||
2940 | gem_writel_n(bp, SCRT2, fs->location, t2_scr); | |
2941 | } | |
2942 | } | |
2943 | ||
2944 | static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs) | |
2945 | { | |
2946 | struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m; | |
2947 | uint16_t index = fs->location; | |
2948 | u32 w0, w1, t2_scr; | |
2949 | bool cmp_a = false; | |
2950 | bool cmp_b = false; | |
2951 | bool cmp_c = false; | |
2952 | ||
2953 | tp4sp_v = &(fs->h_u.tcp_ip4_spec); | |
2954 | tp4sp_m = &(fs->m_u.tcp_ip4_spec); | |
2955 | ||
2956 | /* ignore field if any masking set */ | |
2957 | if (tp4sp_m->ip4src == 0xFFFFFFFF) { | |
2958 | /* 1st compare reg - IP source address */ | |
2959 | w0 = 0; | |
2960 | w1 = 0; | |
2961 | w0 = tp4sp_v->ip4src; | |
2962 | w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ | |
2963 | w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1); | |
2964 | w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1); | |
2965 | gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0); | |
2966 | gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1); | |
2967 | cmp_a = true; | |
2968 | } | |
2969 | ||
2970 | /* ignore field if any masking set */ | |
2971 | if (tp4sp_m->ip4dst == 0xFFFFFFFF) { | |
2972 | /* 2nd compare reg - IP destination address */ | |
2973 | w0 = 0; | |
2974 | w1 = 0; | |
2975 | w0 = tp4sp_v->ip4dst; | |
2976 | w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ | |
2977 | w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1); | |
2978 | w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1); | |
2979 | gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0); | |
2980 | gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1); | |
2981 | cmp_b = true; | |
2982 | } | |
2983 | ||
2984 | /* ignore both port fields if masking set in both */ | |
2985 | if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) { | |
2986 | /* 3rd compare reg - source port, destination port */ | |
2987 | w0 = 0; | |
2988 | w1 = 0; | |
2989 | w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1); | |
2990 | if (tp4sp_m->psrc == tp4sp_m->pdst) { | |
2991 | w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0); | |
2992 | w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0); | |
2993 | w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ | |
2994 | w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1); | |
2995 | } else { | |
2996 | /* only one port definition */ | |
2997 | w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */ | |
2998 | w0 = GEM_BFINS(T2MASK, 0xFFFF, w0); | |
2999 | if (tp4sp_m->psrc == 0xFFFF) { /* src port */ | |
3000 | w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0); | |
3001 | w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1); | |
3002 | } else { /* dst port */ | |
3003 | w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0); | |
3004 | w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1); | |
3005 | } | |
3006 | } | |
3007 | gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0); | |
3008 | gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1); | |
3009 | cmp_c = true; | |
3010 | } | |
3011 | ||
3012 | t2_scr = 0; | |
3013 | t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr); | |
3014 | t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr); | |
3015 | if (cmp_a) | |
3016 | t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr); | |
3017 | if (cmp_b) | |
3018 | t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr); | |
3019 | if (cmp_c) | |
3020 | t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr); | |
3021 | gem_writel_n(bp, SCRT2, index, t2_scr); | |
3022 | } | |
3023 | ||
3024 | static int gem_add_flow_filter(struct net_device *netdev, | |
3025 | struct ethtool_rxnfc *cmd) | |
3026 | { | |
3027 | struct macb *bp = netdev_priv(netdev); | |
3028 | struct ethtool_rx_flow_spec *fs = &cmd->fs; | |
3029 | struct ethtool_rx_fs_item *item, *newfs; | |
7038cdb7 | 3030 | unsigned long flags; |
ae8223de RO |
3031 | int ret = -EINVAL; |
3032 | bool added = false; | |
3033 | ||
cc1674ee | 3034 | newfs = kmalloc(sizeof(*newfs), GFP_KERNEL); |
ae8223de RO |
3035 | if (newfs == NULL) |
3036 | return -ENOMEM; | |
3037 | memcpy(&newfs->fs, fs, sizeof(newfs->fs)); | |
3038 | ||
3039 | netdev_dbg(netdev, | |
3040 | "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n", | |
3041 | fs->flow_type, (int)fs->ring_cookie, fs->location, | |
3042 | htonl(fs->h_u.tcp_ip4_spec.ip4src), | |
3043 | htonl(fs->h_u.tcp_ip4_spec.ip4dst), | |
3044 | htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst)); | |
3045 | ||
7038cdb7 JC |
3046 | spin_lock_irqsave(&bp->rx_fs_lock, flags); |
3047 | ||
ae8223de | 3048 | /* find correct place to add in list */ |
a3da8adc JC |
3049 | list_for_each_entry(item, &bp->rx_fs_list.list, list) { |
3050 | if (item->fs.location > newfs->fs.location) { | |
3051 | list_add_tail(&newfs->list, &item->list); | |
3052 | added = true; | |
3053 | break; | |
3054 | } else if (item->fs.location == fs->location) { | |
3055 | netdev_err(netdev, "Rule not added: location %d not free!\n", | |
3056 | fs->location); | |
3057 | ret = -EBUSY; | |
3058 | goto err; | |
ae8223de | 3059 | } |
ae8223de | 3060 | } |
a3da8adc JC |
3061 | if (!added) |
3062 | list_add_tail(&newfs->list, &bp->rx_fs_list.list); | |
ae8223de RO |
3063 | |
3064 | gem_prog_cmp_regs(bp, fs); | |
3065 | bp->rx_fs_list.count++; | |
3066 | /* enable filtering if NTUPLE on */ | |
c1e85c6c | 3067 | gem_enable_flow_filters(bp, 1); |
ae8223de | 3068 | |
7038cdb7 | 3069 | spin_unlock_irqrestore(&bp->rx_fs_lock, flags); |
ae8223de RO |
3070 | return 0; |
3071 | ||
3072 | err: | |
7038cdb7 | 3073 | spin_unlock_irqrestore(&bp->rx_fs_lock, flags); |
ae8223de RO |
3074 | kfree(newfs); |
3075 | return ret; | |
3076 | } | |
3077 | ||
3078 | static int gem_del_flow_filter(struct net_device *netdev, | |
3079 | struct ethtool_rxnfc *cmd) | |
3080 | { | |
3081 | struct macb *bp = netdev_priv(netdev); | |
3082 | struct ethtool_rx_fs_item *item; | |
3083 | struct ethtool_rx_flow_spec *fs; | |
7038cdb7 JC |
3084 | unsigned long flags; |
3085 | ||
3086 | spin_lock_irqsave(&bp->rx_fs_lock, flags); | |
ae8223de | 3087 | |
ae8223de RO |
3088 | list_for_each_entry(item, &bp->rx_fs_list.list, list) { |
3089 | if (item->fs.location == cmd->fs.location) { | |
3090 | /* disable screener regs for the flow entry */ | |
3091 | fs = &(item->fs); | |
3092 | netdev_dbg(netdev, | |
3093 | "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n", | |
3094 | fs->flow_type, (int)fs->ring_cookie, fs->location, | |
3095 | htonl(fs->h_u.tcp_ip4_spec.ip4src), | |
3096 | htonl(fs->h_u.tcp_ip4_spec.ip4dst), | |
3097 | htons(fs->h_u.tcp_ip4_spec.psrc), | |
3098 | htons(fs->h_u.tcp_ip4_spec.pdst)); | |
3099 | ||
3100 | gem_writel_n(bp, SCRT2, fs->location, 0); | |
3101 | ||
3102 | list_del(&item->list); | |
ae8223de | 3103 | bp->rx_fs_list.count--; |
7038cdb7 JC |
3104 | spin_unlock_irqrestore(&bp->rx_fs_lock, flags); |
3105 | kfree(item); | |
ae8223de RO |
3106 | return 0; |
3107 | } | |
3108 | } | |
3109 | ||
7038cdb7 | 3110 | spin_unlock_irqrestore(&bp->rx_fs_lock, flags); |
ae8223de RO |
3111 | return -EINVAL; |
3112 | } | |
3113 | ||
3114 | static int gem_get_flow_entry(struct net_device *netdev, | |
3115 | struct ethtool_rxnfc *cmd) | |
3116 | { | |
3117 | struct macb *bp = netdev_priv(netdev); | |
3118 | struct ethtool_rx_fs_item *item; | |
3119 | ||
3120 | list_for_each_entry(item, &bp->rx_fs_list.list, list) { | |
3121 | if (item->fs.location == cmd->fs.location) { | |
3122 | memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs)); | |
3123 | return 0; | |
3124 | } | |
3125 | } | |
3126 | return -EINVAL; | |
3127 | } | |
3128 | ||
3129 | static int gem_get_all_flow_entries(struct net_device *netdev, | |
3130 | struct ethtool_rxnfc *cmd, u32 *rule_locs) | |
3131 | { | |
3132 | struct macb *bp = netdev_priv(netdev); | |
3133 | struct ethtool_rx_fs_item *item; | |
3134 | uint32_t cnt = 0; | |
3135 | ||
3136 | list_for_each_entry(item, &bp->rx_fs_list.list, list) { | |
3137 | if (cnt == cmd->rule_cnt) | |
3138 | return -EMSGSIZE; | |
3139 | rule_locs[cnt] = item->fs.location; | |
3140 | cnt++; | |
3141 | } | |
3142 | cmd->data = bp->max_tuples; | |
3143 | cmd->rule_cnt = cnt; | |
3144 | ||
3145 | return 0; | |
3146 | } | |
3147 | ||
3148 | static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd, | |
3149 | u32 *rule_locs) | |
3150 | { | |
3151 | struct macb *bp = netdev_priv(netdev); | |
3152 | int ret = 0; | |
3153 | ||
3154 | switch (cmd->cmd) { | |
3155 | case ETHTOOL_GRXRINGS: | |
3156 | cmd->data = bp->num_queues; | |
3157 | break; | |
3158 | case ETHTOOL_GRXCLSRLCNT: | |
3159 | cmd->rule_cnt = bp->rx_fs_list.count; | |
3160 | break; | |
3161 | case ETHTOOL_GRXCLSRULE: | |
3162 | ret = gem_get_flow_entry(netdev, cmd); | |
3163 | break; | |
3164 | case ETHTOOL_GRXCLSRLALL: | |
3165 | ret = gem_get_all_flow_entries(netdev, cmd, rule_locs); | |
3166 | break; | |
3167 | default: | |
3168 | netdev_err(netdev, | |
3169 | "Command parameter %d is not supported\n", cmd->cmd); | |
3170 | ret = -EOPNOTSUPP; | |
3171 | } | |
3172 | ||
3173 | return ret; | |
3174 | } | |
3175 | ||
3176 | static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd) | |
3177 | { | |
3178 | struct macb *bp = netdev_priv(netdev); | |
ae8223de RO |
3179 | int ret; |
3180 | ||
ae8223de RO |
3181 | switch (cmd->cmd) { |
3182 | case ETHTOOL_SRXCLSRLINS: | |
3183 | if ((cmd->fs.location >= bp->max_tuples) | |
3184 | || (cmd->fs.ring_cookie >= bp->num_queues)) { | |
3185 | ret = -EINVAL; | |
3186 | break; | |
3187 | } | |
3188 | ret = gem_add_flow_filter(netdev, cmd); | |
3189 | break; | |
3190 | case ETHTOOL_SRXCLSRLDEL: | |
3191 | ret = gem_del_flow_filter(netdev, cmd); | |
3192 | break; | |
3193 | default: | |
3194 | netdev_err(netdev, | |
3195 | "Command parameter %d is not supported\n", cmd->cmd); | |
3196 | ret = -EOPNOTSUPP; | |
3197 | } | |
3198 | ||
ae8223de RO |
3199 | return ret; |
3200 | } | |
3201 | ||
421d9df0 | 3202 | static const struct ethtool_ops macb_ethtool_ops = { |
d1d1b53d NF |
3203 | .get_regs_len = macb_get_regs_len, |
3204 | .get_regs = macb_get_regs, | |
89e5785f | 3205 | .get_link = ethtool_op_get_link, |
17f393e8 | 3206 | .get_ts_info = ethtool_op_get_ts_info, |
3e2a5e15 SP |
3207 | .get_wol = macb_get_wol, |
3208 | .set_wol = macb_set_wol, | |
7897b071 AT |
3209 | .get_link_ksettings = macb_get_link_ksettings, |
3210 | .set_link_ksettings = macb_set_link_ksettings, | |
8441bb33 ZB |
3211 | .get_ringparam = macb_get_ringparam, |
3212 | .set_ringparam = macb_set_ringparam, | |
8cd5a56c | 3213 | }; |
8cd5a56c | 3214 | |
8093b1c3 | 3215 | static const struct ethtool_ops gem_ethtool_ops = { |
8cd5a56c XH |
3216 | .get_regs_len = macb_get_regs_len, |
3217 | .get_regs = macb_get_regs, | |
3218 | .get_link = ethtool_op_get_link, | |
c2594d80 | 3219 | .get_ts_info = macb_get_ts_info, |
3ff13f1c XH |
3220 | .get_ethtool_stats = gem_get_ethtool_stats, |
3221 | .get_strings = gem_get_ethtool_strings, | |
3222 | .get_sset_count = gem_get_sset_count, | |
7897b071 AT |
3223 | .get_link_ksettings = macb_get_link_ksettings, |
3224 | .set_link_ksettings = macb_set_link_ksettings, | |
8441bb33 ZB |
3225 | .get_ringparam = macb_get_ringparam, |
3226 | .set_ringparam = macb_set_ringparam, | |
ae8223de RO |
3227 | .get_rxnfc = gem_get_rxnfc, |
3228 | .set_rxnfc = gem_set_rxnfc, | |
89e5785f HS |
3229 | }; |
3230 | ||
421d9df0 | 3231 | static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
89e5785f | 3232 | { |
c2594d80 | 3233 | struct macb *bp = netdev_priv(dev); |
89e5785f HS |
3234 | |
3235 | if (!netif_running(dev)) | |
3236 | return -EINVAL; | |
3237 | ||
7897b071 AT |
3238 | if (bp->ptp_info) { |
3239 | switch (cmd) { | |
3240 | case SIOCSHWTSTAMP: | |
3241 | return bp->ptp_info->set_hwtst(dev, rq, cmd); | |
3242 | case SIOCGHWTSTAMP: | |
3243 | return bp->ptp_info->get_hwtst(dev, rq); | |
3244 | } | |
c2594d80 | 3245 | } |
7897b071 AT |
3246 | |
3247 | return phylink_mii_ioctl(bp->phylink, rq, cmd); | |
89e5785f HS |
3248 | } |
3249 | ||
c1e85c6c CB |
3250 | static inline void macb_set_txcsum_feature(struct macb *bp, |
3251 | netdev_features_t features) | |
3252 | { | |
3253 | u32 val; | |
3254 | ||
3255 | if (!macb_is_gem(bp)) | |
3256 | return; | |
3257 | ||
3258 | val = gem_readl(bp, DMACFG); | |
3259 | if (features & NETIF_F_HW_CSUM) | |
3260 | val |= GEM_BIT(TXCOEN); | |
3261 | else | |
3262 | val &= ~GEM_BIT(TXCOEN); | |
3263 | ||
3264 | gem_writel(bp, DMACFG, val); | |
3265 | } | |
3266 | ||
3267 | static inline void macb_set_rxcsum_feature(struct macb *bp, | |
3268 | netdev_features_t features) | |
3269 | { | |
3270 | struct net_device *netdev = bp->dev; | |
3271 | u32 val; | |
3272 | ||
3273 | if (!macb_is_gem(bp)) | |
3274 | return; | |
3275 | ||
3276 | val = gem_readl(bp, NCFGR); | |
3277 | if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC)) | |
3278 | val |= GEM_BIT(RXCOEN); | |
3279 | else | |
3280 | val &= ~GEM_BIT(RXCOEN); | |
3281 | ||
3282 | gem_writel(bp, NCFGR, val); | |
3283 | } | |
3284 | ||
3285 | static inline void macb_set_rxflow_feature(struct macb *bp, | |
3286 | netdev_features_t features) | |
3287 | { | |
3288 | if (!macb_is_gem(bp)) | |
3289 | return; | |
3290 | ||
3291 | gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE)); | |
3292 | } | |
3293 | ||
85ff3d87 CP |
3294 | static int macb_set_features(struct net_device *netdev, |
3295 | netdev_features_t features) | |
3296 | { | |
3297 | struct macb *bp = netdev_priv(netdev); | |
3298 | netdev_features_t changed = features ^ netdev->features; | |
3299 | ||
3300 | /* TX checksum offload */ | |
c1e85c6c CB |
3301 | if (changed & NETIF_F_HW_CSUM) |
3302 | macb_set_txcsum_feature(bp, features); | |
85ff3d87 | 3303 | |
924ec53c | 3304 | /* RX checksum offload */ |
c1e85c6c CB |
3305 | if (changed & NETIF_F_RXCSUM) |
3306 | macb_set_rxcsum_feature(bp, features); | |
924ec53c | 3307 | |
ae8223de | 3308 | /* RX Flow Filters */ |
c1e85c6c CB |
3309 | if (changed & NETIF_F_NTUPLE) |
3310 | macb_set_rxflow_feature(bp, features); | |
ae8223de | 3311 | |
85ff3d87 CP |
3312 | return 0; |
3313 | } | |
3314 | ||
c1e85c6c CB |
3315 | static void macb_restore_features(struct macb *bp) |
3316 | { | |
3317 | struct net_device *netdev = bp->dev; | |
3318 | netdev_features_t features = netdev->features; | |
3319 | ||
3320 | /* TX checksum offload */ | |
3321 | macb_set_txcsum_feature(bp, features); | |
3322 | ||
3323 | /* RX checksum offload */ | |
3324 | macb_set_rxcsum_feature(bp, features); | |
3325 | ||
3326 | /* RX Flow Filters */ | |
3327 | macb_set_rxflow_feature(bp, features); | |
3328 | } | |
3329 | ||
5f1fa992 AB |
3330 | static const struct net_device_ops macb_netdev_ops = { |
3331 | .ndo_open = macb_open, | |
3332 | .ndo_stop = macb_close, | |
3333 | .ndo_start_xmit = macb_start_xmit, | |
afc4b13d | 3334 | .ndo_set_rx_mode = macb_set_rx_mode, |
5f1fa992 AB |
3335 | .ndo_get_stats = macb_get_stats, |
3336 | .ndo_do_ioctl = macb_ioctl, | |
3337 | .ndo_validate_addr = eth_validate_addr, | |
a5898ea0 | 3338 | .ndo_change_mtu = macb_change_mtu, |
5f1fa992 | 3339 | .ndo_set_mac_address = eth_mac_addr, |
6e8cf5c0 TP |
3340 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3341 | .ndo_poll_controller = macb_poll_controller, | |
3342 | #endif | |
85ff3d87 | 3343 | .ndo_set_features = macb_set_features, |
1629dd4f | 3344 | .ndo_features_check = macb_features_check, |
5f1fa992 AB |
3345 | }; |
3346 | ||
64ec42fe | 3347 | /* Configure peripheral capabilities according to device tree |
e175587f NF |
3348 | * and integration options used |
3349 | */ | |
64ec42fe MF |
3350 | static void macb_configure_caps(struct macb *bp, |
3351 | const struct macb_config *dt_conf) | |
e175587f NF |
3352 | { |
3353 | u32 dcfg; | |
e175587f | 3354 | |
f6970505 NF |
3355 | if (dt_conf) |
3356 | bp->caps = dt_conf->caps; | |
3357 | ||
f2ce8a9e | 3358 | if (hw_is_gem(bp->regs, bp->native_io)) { |
e175587f NF |
3359 | bp->caps |= MACB_CAPS_MACB_IS_GEM; |
3360 | ||
e175587f NF |
3361 | dcfg = gem_readl(bp, DCFG1); |
3362 | if (GEM_BFEXT(IRQCOR, dcfg) == 0) | |
3363 | bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; | |
3364 | dcfg = gem_readl(bp, DCFG2); | |
3365 | if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) | |
3366 | bp->caps |= MACB_CAPS_FIFO_MODE; | |
ab91f0a9 RO |
3367 | #ifdef CONFIG_MACB_USE_HWSTAMP |
3368 | if (gem_has_ptp(bp)) { | |
7b429614 | 3369 | if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5))) |
7897b071 AT |
3370 | dev_err(&bp->pdev->dev, |
3371 | "GEM doesn't support hardware ptp.\n"); | |
ab91f0a9 | 3372 | else { |
7b429614 | 3373 | bp->hw_dma_cap |= HW_DMA_CAP_PTP; |
ab91f0a9 RO |
3374 | bp->ptp_info = &gem_ptp_info; |
3375 | } | |
7b429614 | 3376 | } |
ab91f0a9 | 3377 | #endif |
e175587f NF |
3378 | } |
3379 | ||
a35919e1 | 3380 | dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps); |
e175587f NF |
3381 | } |
3382 | ||
02c958dd | 3383 | static void macb_probe_queues(void __iomem *mem, |
f2ce8a9e | 3384 | bool native_io, |
02c958dd CP |
3385 | unsigned int *queue_mask, |
3386 | unsigned int *num_queues) | |
3387 | { | |
3388 | unsigned int hw_q; | |
02c958dd CP |
3389 | |
3390 | *queue_mask = 0x1; | |
3391 | *num_queues = 1; | |
3392 | ||
da120112 NF |
3393 | /* is it macb or gem ? |
3394 | * | |
3395 | * We need to read directly from the hardware here because | |
3396 | * we are early in the probe process and don't have the | |
3397 | * MACB_CAPS_MACB_IS_GEM flag positioned | |
3398 | */ | |
f2ce8a9e | 3399 | if (!hw_is_gem(mem, native_io)) |
02c958dd CP |
3400 | return; |
3401 | ||
3402 | /* bit 0 is never set but queue 0 always exists */ | |
a50dad35 AC |
3403 | *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff; |
3404 | ||
02c958dd CP |
3405 | *queue_mask |= 0x1; |
3406 | ||
3407 | for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q) | |
3408 | if (*queue_mask & (1 << hw_q)) | |
3409 | (*num_queues)++; | |
3410 | } | |
3411 | ||
c69618b3 | 3412 | static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, |
aead88bd | 3413 | struct clk **hclk, struct clk **tx_clk, |
f5473d1d | 3414 | struct clk **rx_clk, struct clk **tsu_clk) |
89e5785f | 3415 | { |
83a77e9e | 3416 | struct macb_platform_data *pdata; |
421d9df0 | 3417 | int err; |
89e5785f | 3418 | |
83a77e9e BF |
3419 | pdata = dev_get_platdata(&pdev->dev); |
3420 | if (pdata) { | |
3421 | *pclk = pdata->pclk; | |
3422 | *hclk = pdata->hclk; | |
3423 | } else { | |
3424 | *pclk = devm_clk_get(&pdev->dev, "pclk"); | |
3425 | *hclk = devm_clk_get(&pdev->dev, "hclk"); | |
3426 | } | |
3427 | ||
cd5afa91 | 3428 | if (IS_ERR_OR_NULL(*pclk)) { |
c69618b3 | 3429 | err = PTR_ERR(*pclk); |
cd5afa91 HK |
3430 | if (!err) |
3431 | err = -ENODEV; | |
3432 | ||
f413cbb3 | 3433 | dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err); |
421d9df0 | 3434 | return err; |
0cc8674f | 3435 | } |
461845db | 3436 | |
cd5afa91 | 3437 | if (IS_ERR_OR_NULL(*hclk)) { |
c69618b3 | 3438 | err = PTR_ERR(*hclk); |
cd5afa91 HK |
3439 | if (!err) |
3440 | err = -ENODEV; | |
3441 | ||
f413cbb3 | 3442 | dev_err(&pdev->dev, "failed to get hclk (%d)\n", err); |
421d9df0 | 3443 | return err; |
b48e0bab SB |
3444 | } |
3445 | ||
bd310aca | 3446 | *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk"); |
c69618b3 | 3447 | if (IS_ERR(*tx_clk)) |
bd310aca | 3448 | return PTR_ERR(*tx_clk); |
e1824dfe | 3449 | |
bd310aca | 3450 | *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk"); |
aead88bd | 3451 | if (IS_ERR(*rx_clk)) |
bd310aca | 3452 | return PTR_ERR(*rx_clk); |
aead88bd | 3453 | |
bd310aca | 3454 | *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk"); |
f5473d1d | 3455 | if (IS_ERR(*tsu_clk)) |
bd310aca | 3456 | return PTR_ERR(*tsu_clk); |
f5473d1d | 3457 | |
c69618b3 | 3458 | err = clk_prepare_enable(*pclk); |
b48e0bab | 3459 | if (err) { |
f413cbb3 | 3460 | dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err); |
421d9df0 | 3461 | return err; |
b48e0bab SB |
3462 | } |
3463 | ||
c69618b3 | 3464 | err = clk_prepare_enable(*hclk); |
b48e0bab | 3465 | if (err) { |
f413cbb3 | 3466 | dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err); |
421d9df0 | 3467 | goto err_disable_pclk; |
89e5785f | 3468 | } |
89e5785f | 3469 | |
c69618b3 | 3470 | err = clk_prepare_enable(*tx_clk); |
93b31f48 | 3471 | if (err) { |
f413cbb3 | 3472 | dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); |
421d9df0 | 3473 | goto err_disable_hclk; |
e1824dfe SB |
3474 | } |
3475 | ||
aead88bd | 3476 | err = clk_prepare_enable(*rx_clk); |
3477 | if (err) { | |
f413cbb3 | 3478 | dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); |
aead88bd | 3479 | goto err_disable_txclk; |
3480 | } | |
3481 | ||
f5473d1d HK |
3482 | err = clk_prepare_enable(*tsu_clk); |
3483 | if (err) { | |
f413cbb3 | 3484 | dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err); |
f5473d1d HK |
3485 | goto err_disable_rxclk; |
3486 | } | |
3487 | ||
c69618b3 NF |
3488 | return 0; |
3489 | ||
f5473d1d HK |
3490 | err_disable_rxclk: |
3491 | clk_disable_unprepare(*rx_clk); | |
3492 | ||
aead88bd | 3493 | err_disable_txclk: |
3494 | clk_disable_unprepare(*tx_clk); | |
3495 | ||
c69618b3 NF |
3496 | err_disable_hclk: |
3497 | clk_disable_unprepare(*hclk); | |
3498 | ||
3499 | err_disable_pclk: | |
3500 | clk_disable_unprepare(*pclk); | |
3501 | ||
3502 | return err; | |
3503 | } | |
3504 | ||
3505 | static int macb_init(struct platform_device *pdev) | |
3506 | { | |
3507 | struct net_device *dev = platform_get_drvdata(pdev); | |
3508 | unsigned int hw_q, q; | |
3509 | struct macb *bp = netdev_priv(dev); | |
3510 | struct macb_queue *queue; | |
3511 | int err; | |
ae8223de | 3512 | u32 val, reg; |
c69618b3 | 3513 | |
b410d13e ZB |
3514 | bp->tx_ring_size = DEFAULT_TX_RING_SIZE; |
3515 | bp->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
3516 | ||
02c958dd CP |
3517 | /* set the queue register mapping once for all: queue0 has a special |
3518 | * register mapping but we don't want to test the queue index then | |
3519 | * compute the corresponding register offset at run time. | |
3520 | */ | |
cf250de0 | 3521 | for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) { |
bfa0914a | 3522 | if (!(bp->queue_mask & (1 << hw_q))) |
02c958dd CP |
3523 | continue; |
3524 | ||
cf250de0 | 3525 | queue = &bp->queues[q]; |
02c958dd | 3526 | queue->bp = bp; |
760a3c1a | 3527 | netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT); |
02c958dd CP |
3528 | if (hw_q) { |
3529 | queue->ISR = GEM_ISR(hw_q - 1); | |
3530 | queue->IER = GEM_IER(hw_q - 1); | |
3531 | queue->IDR = GEM_IDR(hw_q - 1); | |
3532 | queue->IMR = GEM_IMR(hw_q - 1); | |
3533 | queue->TBQP = GEM_TBQP(hw_q - 1); | |
ae1f2a56 RO |
3534 | queue->RBQP = GEM_RBQP(hw_q - 1); |
3535 | queue->RBQS = GEM_RBQS(hw_q - 1); | |
fff8019a | 3536 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
ae1f2a56 | 3537 | if (bp->hw_dma_cap & HW_DMA_CAP_64B) { |
dc97a89e | 3538 | queue->TBQPH = GEM_TBQPH(hw_q - 1); |
ae1f2a56 RO |
3539 | queue->RBQPH = GEM_RBQPH(hw_q - 1); |
3540 | } | |
fff8019a | 3541 | #endif |
02c958dd CP |
3542 | } else { |
3543 | /* queue0 uses legacy registers */ | |
3544 | queue->ISR = MACB_ISR; | |
3545 | queue->IER = MACB_IER; | |
3546 | queue->IDR = MACB_IDR; | |
3547 | queue->IMR = MACB_IMR; | |
3548 | queue->TBQP = MACB_TBQP; | |
ae1f2a56 | 3549 | queue->RBQP = MACB_RBQP; |
fff8019a | 3550 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
ae1f2a56 | 3551 | if (bp->hw_dma_cap & HW_DMA_CAP_64B) { |
dc97a89e | 3552 | queue->TBQPH = MACB_TBQPH; |
ae1f2a56 RO |
3553 | queue->RBQPH = MACB_RBQPH; |
3554 | } | |
fff8019a | 3555 | #endif |
02c958dd CP |
3556 | } |
3557 | ||
3558 | /* get irq: here we use the linux queue index, not the hardware | |
3559 | * queue index. the queue irq definitions in the device tree | |
3560 | * must remove the optional gaps that could exist in the | |
3561 | * hardware queue mask. | |
3562 | */ | |
cf250de0 | 3563 | queue->irq = platform_get_irq(pdev, q); |
02c958dd | 3564 | err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt, |
20488239 | 3565 | IRQF_SHARED, dev->name, queue); |
02c958dd CP |
3566 | if (err) { |
3567 | dev_err(&pdev->dev, | |
3568 | "Unable to request IRQ %d (error %d)\n", | |
3569 | queue->irq, err); | |
c69618b3 | 3570 | return err; |
02c958dd CP |
3571 | } |
3572 | ||
3573 | INIT_WORK(&queue->tx_error_task, macb_tx_error_task); | |
cf250de0 | 3574 | q++; |
89e5785f HS |
3575 | } |
3576 | ||
5f1fa992 | 3577 | dev->netdev_ops = &macb_netdev_ops; |
89e5785f | 3578 | |
4df95131 NF |
3579 | /* setup appropriated routines according to adapter type */ |
3580 | if (macb_is_gem(bp)) { | |
a4c35ed3 | 3581 | bp->max_tx_length = GEM_MAX_TX_LEN; |
4df95131 NF |
3582 | bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers; |
3583 | bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers; | |
3584 | bp->macbgem_ops.mog_init_rings = gem_init_rings; | |
3585 | bp->macbgem_ops.mog_rx = gem_rx; | |
8cd5a56c | 3586 | dev->ethtool_ops = &gem_ethtool_ops; |
4df95131 | 3587 | } else { |
a4c35ed3 | 3588 | bp->max_tx_length = MACB_MAX_TX_LEN; |
4df95131 NF |
3589 | bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers; |
3590 | bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers; | |
3591 | bp->macbgem_ops.mog_init_rings = macb_init_rings; | |
3592 | bp->macbgem_ops.mog_rx = macb_rx; | |
8cd5a56c | 3593 | dev->ethtool_ops = &macb_ethtool_ops; |
4df95131 NF |
3594 | } |
3595 | ||
a4c35ed3 CP |
3596 | /* Set features */ |
3597 | dev->hw_features = NETIF_F_SG; | |
1629dd4f RO |
3598 | |
3599 | /* Check LSO capability */ | |
3600 | if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6))) | |
3601 | dev->hw_features |= MACB_NETIF_LSO; | |
3602 | ||
85ff3d87 CP |
3603 | /* Checksum offload is only available on gem with packet buffer */ |
3604 | if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE)) | |
924ec53c | 3605 | dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM; |
a4c35ed3 CP |
3606 | if (bp->caps & MACB_CAPS_SG_DISABLED) |
3607 | dev->hw_features &= ~NETIF_F_SG; | |
3608 | dev->features = dev->hw_features; | |
3609 | ||
ae8223de RO |
3610 | /* Check RX Flow Filters support. |
3611 | * Max Rx flows set by availability of screeners & compare regs: | |
3612 | * each 4-tuple define requires 1 T2 screener reg + 3 compare regs | |
3613 | */ | |
3614 | reg = gem_readl(bp, DCFG8); | |
3615 | bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3), | |
3616 | GEM_BFEXT(T2SCR, reg)); | |
3617 | if (bp->max_tuples > 0) { | |
3618 | /* also needs one ethtype match to check IPv4 */ | |
3619 | if (GEM_BFEXT(SCR2ETH, reg) > 0) { | |
3620 | /* program this reg now */ | |
3621 | reg = 0; | |
3622 | reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg); | |
3623 | gem_writel_n(bp, ETHT, SCRT2_ETHT, reg); | |
3624 | /* Filtering is supported in hw but don't enable it in kernel now */ | |
3625 | dev->hw_features |= NETIF_F_NTUPLE; | |
3626 | /* init Rx flow definitions */ | |
3627 | INIT_LIST_HEAD(&bp->rx_fs_list.list); | |
3628 | bp->rx_fs_list.count = 0; | |
3629 | spin_lock_init(&bp->rx_fs_lock); | |
3630 | } else | |
3631 | bp->max_tuples = 0; | |
3632 | } | |
3633 | ||
ce721a70 NA |
3634 | if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { |
3635 | val = 0; | |
3636 | if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
3637 | val = GEM_BIT(RGMII); | |
3638 | else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && | |
6bdaa5e9 | 3639 | (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) |
ce721a70 | 3640 | val = MACB_BIT(RMII); |
6bdaa5e9 | 3641 | else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) |
ce721a70 | 3642 | val = MACB_BIT(MII); |
421d9df0 | 3643 | |
ce721a70 NA |
3644 | if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) |
3645 | val |= MACB_BIT(CLKEN); | |
421d9df0 | 3646 | |
ce721a70 NA |
3647 | macb_or_gem_writel(bp, USRIO, val); |
3648 | } | |
421d9df0 | 3649 | |
89e5785f | 3650 | /* Set MII management clock divider */ |
421d9df0 CP |
3651 | val = macb_mdc_clk_div(bp); |
3652 | val |= macb_dbw(bp); | |
022be25c PCK |
3653 | if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) |
3654 | val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); | |
421d9df0 CP |
3655 | macb_writel(bp, NCFGR, val); |
3656 | ||
3657 | return 0; | |
421d9df0 CP |
3658 | } |
3659 | ||
3660 | #if defined(CONFIG_OF) | |
3661 | /* 1518 rounded up */ | |
3662 | #define AT91ETHER_MAX_RBUFF_SZ 0x600 | |
3663 | /* max number of receive buffers */ | |
3664 | #define AT91ETHER_MAX_RX_DESCR 9 | |
3665 | ||
49db9228 AB |
3666 | static struct sifive_fu540_macb_mgmt *mgmt; |
3667 | ||
421d9df0 CP |
3668 | /* Initialize and start the Receiver and Transmit subsystems */ |
3669 | static int at91ether_start(struct net_device *dev) | |
3670 | { | |
3671 | struct macb *lp = netdev_priv(dev); | |
ae1f2a56 | 3672 | struct macb_queue *q = &lp->queues[0]; |
dc97a89e | 3673 | struct macb_dma_desc *desc; |
421d9df0 CP |
3674 | dma_addr_t addr; |
3675 | u32 ctl; | |
3676 | int i; | |
3677 | ||
ae1f2a56 | 3678 | q->rx_ring = dma_alloc_coherent(&lp->pdev->dev, |
421d9df0 | 3679 | (AT91ETHER_MAX_RX_DESCR * |
dc97a89e | 3680 | macb_dma_desc_get_size(lp)), |
ae1f2a56 RO |
3681 | &q->rx_ring_dma, GFP_KERNEL); |
3682 | if (!q->rx_ring) | |
421d9df0 CP |
3683 | return -ENOMEM; |
3684 | ||
ae1f2a56 | 3685 | q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev, |
421d9df0 CP |
3686 | AT91ETHER_MAX_RX_DESCR * |
3687 | AT91ETHER_MAX_RBUFF_SZ, | |
ae1f2a56 RO |
3688 | &q->rx_buffers_dma, GFP_KERNEL); |
3689 | if (!q->rx_buffers) { | |
421d9df0 CP |
3690 | dma_free_coherent(&lp->pdev->dev, |
3691 | AT91ETHER_MAX_RX_DESCR * | |
dc97a89e | 3692 | macb_dma_desc_get_size(lp), |
ae1f2a56 RO |
3693 | q->rx_ring, q->rx_ring_dma); |
3694 | q->rx_ring = NULL; | |
421d9df0 CP |
3695 | return -ENOMEM; |
3696 | } | |
3697 | ||
ae1f2a56 | 3698 | addr = q->rx_buffers_dma; |
421d9df0 | 3699 | for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) { |
ae1f2a56 | 3700 | desc = macb_rx_desc(q, i); |
dc97a89e RO |
3701 | macb_set_addr(lp, desc, addr); |
3702 | desc->ctrl = 0; | |
421d9df0 CP |
3703 | addr += AT91ETHER_MAX_RBUFF_SZ; |
3704 | } | |
3705 | ||
3706 | /* Set the Wrap bit on the last descriptor */ | |
dc97a89e | 3707 | desc->addr |= MACB_BIT(RX_WRAP); |
421d9df0 CP |
3708 | |
3709 | /* Reset buffer index */ | |
ae1f2a56 | 3710 | q->rx_tail = 0; |
421d9df0 CP |
3711 | |
3712 | /* Program address of descriptor list in Rx Buffer Queue register */ | |
ae1f2a56 | 3713 | macb_writel(lp, RBQP, q->rx_ring_dma); |
421d9df0 CP |
3714 | |
3715 | /* Enable Receive and Transmit */ | |
3716 | ctl = macb_readl(lp, NCR); | |
3717 | macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE)); | |
3718 | ||
3719 | return 0; | |
3720 | } | |
3721 | ||
3722 | /* Open the ethernet interface */ | |
3723 | static int at91ether_open(struct net_device *dev) | |
3724 | { | |
3725 | struct macb *lp = netdev_priv(dev); | |
3726 | u32 ctl; | |
3727 | int ret; | |
3728 | ||
3729 | /* Clear internal statistics */ | |
3730 | ctl = macb_readl(lp, NCR); | |
3731 | macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT)); | |
3732 | ||
3733 | macb_set_hwaddr(lp); | |
3734 | ||
3735 | ret = at91ether_start(dev); | |
3736 | if (ret) | |
3737 | return ret; | |
3738 | ||
3739 | /* Enable MAC interrupts */ | |
3740 | macb_writel(lp, IER, MACB_BIT(RCOMP) | | |
3741 | MACB_BIT(RXUBR) | | |
3742 | MACB_BIT(ISR_TUND) | | |
3743 | MACB_BIT(ISR_RLE) | | |
3744 | MACB_BIT(TCOMP) | | |
3745 | MACB_BIT(ISR_ROVR) | | |
3746 | MACB_BIT(HRESP)); | |
3747 | ||
7897b071 AT |
3748 | ret = macb_phylink_connect(lp); |
3749 | if (ret) | |
3750 | return ret; | |
421d9df0 CP |
3751 | |
3752 | netif_start_queue(dev); | |
3753 | ||
3754 | return 0; | |
3755 | } | |
3756 | ||
3757 | /* Close the interface */ | |
3758 | static int at91ether_close(struct net_device *dev) | |
3759 | { | |
3760 | struct macb *lp = netdev_priv(dev); | |
ae1f2a56 | 3761 | struct macb_queue *q = &lp->queues[0]; |
421d9df0 CP |
3762 | u32 ctl; |
3763 | ||
3764 | /* Disable Receiver and Transmitter */ | |
3765 | ctl = macb_readl(lp, NCR); | |
3766 | macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE))); | |
3767 | ||
3768 | /* Disable MAC interrupts */ | |
3769 | macb_writel(lp, IDR, MACB_BIT(RCOMP) | | |
3770 | MACB_BIT(RXUBR) | | |
3771 | MACB_BIT(ISR_TUND) | | |
3772 | MACB_BIT(ISR_RLE) | | |
3773 | MACB_BIT(TCOMP) | | |
3774 | MACB_BIT(ISR_ROVR) | | |
3775 | MACB_BIT(HRESP)); | |
3776 | ||
3777 | netif_stop_queue(dev); | |
3778 | ||
7897b071 AT |
3779 | phylink_stop(lp->phylink); |
3780 | phylink_disconnect_phy(lp->phylink); | |
3781 | ||
421d9df0 CP |
3782 | dma_free_coherent(&lp->pdev->dev, |
3783 | AT91ETHER_MAX_RX_DESCR * | |
dc97a89e | 3784 | macb_dma_desc_get_size(lp), |
ae1f2a56 RO |
3785 | q->rx_ring, q->rx_ring_dma); |
3786 | q->rx_ring = NULL; | |
421d9df0 CP |
3787 | |
3788 | dma_free_coherent(&lp->pdev->dev, | |
3789 | AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ, | |
ae1f2a56 RO |
3790 | q->rx_buffers, q->rx_buffers_dma); |
3791 | q->rx_buffers = NULL; | |
421d9df0 CP |
3792 | |
3793 | return 0; | |
3794 | } | |
3795 | ||
3796 | /* Transmit packet */ | |
d1c38957 CB |
3797 | static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb, |
3798 | struct net_device *dev) | |
421d9df0 CP |
3799 | { |
3800 | struct macb *lp = netdev_priv(dev); | |
3801 | ||
3802 | if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) { | |
3803 | netif_stop_queue(dev); | |
3804 | ||
3805 | /* Store packet information (to free when Tx completed) */ | |
3806 | lp->skb = skb; | |
3807 | lp->skb_length = skb->len; | |
564923e4 CH |
3808 | lp->skb_physaddr = dma_map_single(&lp->pdev->dev, skb->data, |
3809 | skb->len, DMA_TO_DEVICE); | |
3810 | if (dma_mapping_error(&lp->pdev->dev, lp->skb_physaddr)) { | |
178c7ae9 AK |
3811 | dev_kfree_skb_any(skb); |
3812 | dev->stats.tx_dropped++; | |
3813 | netdev_err(dev, "%s: DMA mapping error\n", __func__); | |
3814 | return NETDEV_TX_OK; | |
3815 | } | |
421d9df0 CP |
3816 | |
3817 | /* Set address of the data in the Transmit Address register */ | |
3818 | macb_writel(lp, TAR, lp->skb_physaddr); | |
3819 | /* Set length of the packet in the Transmit Control register */ | |
3820 | macb_writel(lp, TCR, skb->len); | |
89e5785f | 3821 | |
421d9df0 CP |
3822 | } else { |
3823 | netdev_err(dev, "%s called, but device is busy!\n", __func__); | |
3824 | return NETDEV_TX_BUSY; | |
3825 | } | |
3826 | ||
3827 | return NETDEV_TX_OK; | |
3828 | } | |
3829 | ||
3830 | /* Extract received frame from buffer descriptors and sent to upper layers. | |
3831 | * (Called from interrupt context) | |
3832 | */ | |
3833 | static void at91ether_rx(struct net_device *dev) | |
3834 | { | |
3835 | struct macb *lp = netdev_priv(dev); | |
ae1f2a56 | 3836 | struct macb_queue *q = &lp->queues[0]; |
dc97a89e | 3837 | struct macb_dma_desc *desc; |
421d9df0 CP |
3838 | unsigned char *p_recv; |
3839 | struct sk_buff *skb; | |
3840 | unsigned int pktlen; | |
3841 | ||
ae1f2a56 | 3842 | desc = macb_rx_desc(q, q->rx_tail); |
dc97a89e | 3843 | while (desc->addr & MACB_BIT(RX_USED)) { |
ae1f2a56 | 3844 | p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ; |
dc97a89e | 3845 | pktlen = MACB_BF(RX_FRMLEN, desc->ctrl); |
421d9df0 CP |
3846 | skb = netdev_alloc_skb(dev, pktlen + 2); |
3847 | if (skb) { | |
3848 | skb_reserve(skb, 2); | |
59ae1d12 | 3849 | skb_put_data(skb, p_recv, pktlen); |
421d9df0 CP |
3850 | |
3851 | skb->protocol = eth_type_trans(skb, dev); | |
5f1d3a5c TK |
3852 | dev->stats.rx_packets++; |
3853 | dev->stats.rx_bytes += pktlen; | |
421d9df0 CP |
3854 | netif_rx(skb); |
3855 | } else { | |
5f1d3a5c | 3856 | dev->stats.rx_dropped++; |
421d9df0 CP |
3857 | } |
3858 | ||
dc97a89e | 3859 | if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH)) |
5f1d3a5c | 3860 | dev->stats.multicast++; |
421d9df0 CP |
3861 | |
3862 | /* reset ownership bit */ | |
dc97a89e | 3863 | desc->addr &= ~MACB_BIT(RX_USED); |
421d9df0 CP |
3864 | |
3865 | /* wrap after last buffer */ | |
ae1f2a56 RO |
3866 | if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1) |
3867 | q->rx_tail = 0; | |
421d9df0 | 3868 | else |
ae1f2a56 | 3869 | q->rx_tail++; |
dc97a89e | 3870 | |
ae1f2a56 | 3871 | desc = macb_rx_desc(q, q->rx_tail); |
421d9df0 CP |
3872 | } |
3873 | } | |
3874 | ||
3875 | /* MAC interrupt handler */ | |
3876 | static irqreturn_t at91ether_interrupt(int irq, void *dev_id) | |
3877 | { | |
3878 | struct net_device *dev = dev_id; | |
3879 | struct macb *lp = netdev_priv(dev); | |
3880 | u32 intstatus, ctl; | |
3881 | ||
3882 | /* MAC Interrupt Status register indicates what interrupts are pending. | |
3883 | * It is automatically cleared once read. | |
3884 | */ | |
3885 | intstatus = macb_readl(lp, ISR); | |
3886 | ||
3887 | /* Receive complete */ | |
3888 | if (intstatus & MACB_BIT(RCOMP)) | |
3889 | at91ether_rx(dev); | |
3890 | ||
3891 | /* Transmit complete */ | |
3892 | if (intstatus & MACB_BIT(TCOMP)) { | |
3893 | /* The TCOM bit is set even if the transmission failed */ | |
3894 | if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE))) | |
5f1d3a5c | 3895 | dev->stats.tx_errors++; |
421d9df0 CP |
3896 | |
3897 | if (lp->skb) { | |
b9560a22 | 3898 | dev_consume_skb_irq(lp->skb); |
421d9df0 | 3899 | lp->skb = NULL; |
564923e4 | 3900 | dma_unmap_single(&lp->pdev->dev, lp->skb_physaddr, |
421d9df0 | 3901 | lp->skb_length, DMA_TO_DEVICE); |
5f1d3a5c TK |
3902 | dev->stats.tx_packets++; |
3903 | dev->stats.tx_bytes += lp->skb_length; | |
421d9df0 CP |
3904 | } |
3905 | netif_wake_queue(dev); | |
3906 | } | |
3907 | ||
3908 | /* Work-around for EMAC Errata section 41.3.1 */ | |
3909 | if (intstatus & MACB_BIT(RXUBR)) { | |
3910 | ctl = macb_readl(lp, NCR); | |
3911 | macb_writel(lp, NCR, ctl & ~MACB_BIT(RE)); | |
ffac0e96 | 3912 | wmb(); |
421d9df0 CP |
3913 | macb_writel(lp, NCR, ctl | MACB_BIT(RE)); |
3914 | } | |
3915 | ||
3916 | if (intstatus & MACB_BIT(ISR_ROVR)) | |
3917 | netdev_err(dev, "ROVR error\n"); | |
3918 | ||
3919 | return IRQ_HANDLED; | |
3920 | } | |
3921 | ||
3922 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3923 | static void at91ether_poll_controller(struct net_device *dev) | |
3924 | { | |
3925 | unsigned long flags; | |
3926 | ||
3927 | local_irq_save(flags); | |
3928 | at91ether_interrupt(dev->irq, dev); | |
3929 | local_irq_restore(flags); | |
3930 | } | |
3931 | #endif | |
3932 | ||
3933 | static const struct net_device_ops at91ether_netdev_ops = { | |
3934 | .ndo_open = at91ether_open, | |
3935 | .ndo_stop = at91ether_close, | |
3936 | .ndo_start_xmit = at91ether_start_xmit, | |
3937 | .ndo_get_stats = macb_get_stats, | |
3938 | .ndo_set_rx_mode = macb_set_rx_mode, | |
3939 | .ndo_set_mac_address = eth_mac_addr, | |
3940 | .ndo_do_ioctl = macb_ioctl, | |
3941 | .ndo_validate_addr = eth_validate_addr, | |
421d9df0 CP |
3942 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3943 | .ndo_poll_controller = at91ether_poll_controller, | |
3944 | #endif | |
3945 | }; | |
3946 | ||
c69618b3 | 3947 | static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk, |
aead88bd | 3948 | struct clk **hclk, struct clk **tx_clk, |
f5473d1d | 3949 | struct clk **rx_clk, struct clk **tsu_clk) |
421d9df0 | 3950 | { |
421d9df0 | 3951 | int err; |
421d9df0 | 3952 | |
c69618b3 NF |
3953 | *hclk = NULL; |
3954 | *tx_clk = NULL; | |
aead88bd | 3955 | *rx_clk = NULL; |
f5473d1d | 3956 | *tsu_clk = NULL; |
c69618b3 NF |
3957 | |
3958 | *pclk = devm_clk_get(&pdev->dev, "ether_clk"); | |
3959 | if (IS_ERR(*pclk)) | |
3960 | return PTR_ERR(*pclk); | |
421d9df0 | 3961 | |
c69618b3 | 3962 | err = clk_prepare_enable(*pclk); |
421d9df0 | 3963 | if (err) { |
f413cbb3 | 3964 | dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err); |
421d9df0 CP |
3965 | return err; |
3966 | } | |
3967 | ||
c69618b3 NF |
3968 | return 0; |
3969 | } | |
3970 | ||
3971 | static int at91ether_init(struct platform_device *pdev) | |
3972 | { | |
3973 | struct net_device *dev = platform_get_drvdata(pdev); | |
3974 | struct macb *bp = netdev_priv(dev); | |
3975 | int err; | |
3976 | u32 reg; | |
3977 | ||
fec9d3b1 AB |
3978 | bp->queues[0].bp = bp; |
3979 | ||
421d9df0 CP |
3980 | dev->netdev_ops = &at91ether_netdev_ops; |
3981 | dev->ethtool_ops = &macb_ethtool_ops; | |
3982 | ||
3983 | err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt, | |
3984 | 0, dev->name, dev); | |
3985 | if (err) | |
c69618b3 | 3986 | return err; |
421d9df0 CP |
3987 | |
3988 | macb_writel(bp, NCR, 0); | |
3989 | ||
3990 | reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG); | |
3991 | if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) | |
3992 | reg |= MACB_BIT(RM9200_RMII); | |
3993 | ||
3994 | macb_writel(bp, NCFGR, reg); | |
3995 | ||
3996 | return 0; | |
421d9df0 CP |
3997 | } |
3998 | ||
c218ad55 YS |
3999 | static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw, |
4000 | unsigned long parent_rate) | |
4001 | { | |
4002 | return mgmt->rate; | |
4003 | } | |
4004 | ||
4005 | static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate, | |
4006 | unsigned long *parent_rate) | |
4007 | { | |
4008 | if (WARN_ON(rate < 2500000)) | |
4009 | return 2500000; | |
4010 | else if (rate == 2500000) | |
4011 | return 2500000; | |
4012 | else if (WARN_ON(rate < 13750000)) | |
4013 | return 2500000; | |
4014 | else if (WARN_ON(rate < 25000000)) | |
4015 | return 25000000; | |
4016 | else if (rate == 25000000) | |
4017 | return 25000000; | |
4018 | else if (WARN_ON(rate < 75000000)) | |
4019 | return 25000000; | |
4020 | else if (WARN_ON(rate < 125000000)) | |
4021 | return 125000000; | |
4022 | else if (rate == 125000000) | |
4023 | return 125000000; | |
4024 | ||
4025 | WARN_ON(rate > 125000000); | |
4026 | ||
4027 | return 125000000; | |
4028 | } | |
4029 | ||
4030 | static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate, | |
4031 | unsigned long parent_rate) | |
4032 | { | |
4033 | rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate); | |
4034 | if (rate != 125000000) | |
4035 | iowrite32(1, mgmt->reg); | |
4036 | else | |
4037 | iowrite32(0, mgmt->reg); | |
4038 | mgmt->rate = rate; | |
4039 | ||
4040 | return 0; | |
4041 | } | |
4042 | ||
4043 | static const struct clk_ops fu540_c000_ops = { | |
4044 | .recalc_rate = fu540_macb_tx_recalc_rate, | |
4045 | .round_rate = fu540_macb_tx_round_rate, | |
4046 | .set_rate = fu540_macb_tx_set_rate, | |
4047 | }; | |
4048 | ||
4049 | static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk, | |
4050 | struct clk **hclk, struct clk **tx_clk, | |
4051 | struct clk **rx_clk, struct clk **tsu_clk) | |
4052 | { | |
4053 | struct clk_init_data init; | |
4054 | int err = 0; | |
4055 | ||
4056 | err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk); | |
4057 | if (err) | |
4058 | return err; | |
4059 | ||
4060 | mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL); | |
4061 | if (!mgmt) | |
4062 | return -ENOMEM; | |
4063 | ||
4064 | init.name = "sifive-gemgxl-mgmt"; | |
4065 | init.ops = &fu540_c000_ops; | |
4066 | init.flags = 0; | |
4067 | init.num_parents = 0; | |
4068 | ||
4069 | mgmt->rate = 0; | |
4070 | mgmt->hw.init = &init; | |
4071 | ||
4072 | *tx_clk = clk_register(NULL, &mgmt->hw); | |
4073 | if (IS_ERR(*tx_clk)) | |
4074 | return PTR_ERR(*tx_clk); | |
4075 | ||
4076 | err = clk_prepare_enable(*tx_clk); | |
4077 | if (err) | |
4078 | dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); | |
4079 | else | |
4080 | dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name); | |
4081 | ||
4082 | return 0; | |
4083 | } | |
4084 | ||
4085 | static int fu540_c000_init(struct platform_device *pdev) | |
4086 | { | |
4087 | struct resource *res; | |
4088 | ||
4089 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
4090 | if (!res) | |
4091 | return -ENODEV; | |
4092 | ||
4093 | mgmt->reg = ioremap(res->start, resource_size(res)); | |
4094 | if (!mgmt->reg) | |
4095 | return -ENOMEM; | |
4096 | ||
4097 | return macb_init(pdev); | |
4098 | } | |
4099 | ||
4100 | static const struct macb_config fu540_c000_config = { | |
4101 | .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | | |
4102 | MACB_CAPS_GEM_HAS_PTP, | |
4103 | .dma_burst_length = 16, | |
4104 | .clk_init = fu540_c000_clk_init, | |
4105 | .init = fu540_c000_init, | |
4106 | .jumbo_max_len = 10240, | |
4107 | }; | |
4108 | ||
3cef5c5b | 4109 | static const struct macb_config at91sam9260_config = { |
6bdaa5e9 | 4110 | .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, |
c69618b3 | 4111 | .clk_init = macb_clk_init, |
421d9df0 CP |
4112 | .init = macb_init, |
4113 | }; | |
4114 | ||
eb4ed8e2 NF |
4115 | static const struct macb_config sama5d3macb_config = { |
4116 | .caps = MACB_CAPS_SG_DISABLED | |
4117 | | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, | |
4118 | .clk_init = macb_clk_init, | |
4119 | .init = macb_init, | |
4120 | }; | |
4121 | ||
3cef5c5b | 4122 | static const struct macb_config pc302gem_config = { |
421d9df0 CP |
4123 | .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE, |
4124 | .dma_burst_length = 16, | |
c69618b3 | 4125 | .clk_init = macb_clk_init, |
421d9df0 CP |
4126 | .init = macb_init, |
4127 | }; | |
4128 | ||
5c8fe711 | 4129 | static const struct macb_config sama5d2_config = { |
6bdaa5e9 | 4130 | .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, |
5c8fe711 CP |
4131 | .dma_burst_length = 16, |
4132 | .clk_init = macb_clk_init, | |
4133 | .init = macb_init, | |
4134 | }; | |
4135 | ||
3cef5c5b | 4136 | static const struct macb_config sama5d3_config = { |
6bdaa5e9 | 4137 | .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
233a1587 | 4138 | | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO, |
421d9df0 | 4139 | .dma_burst_length = 16, |
c69618b3 | 4140 | .clk_init = macb_clk_init, |
421d9df0 | 4141 | .init = macb_init, |
233a1587 | 4142 | .jumbo_max_len = 10240, |
421d9df0 CP |
4143 | }; |
4144 | ||
3cef5c5b | 4145 | static const struct macb_config sama5d4_config = { |
6bdaa5e9 | 4146 | .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, |
421d9df0 | 4147 | .dma_burst_length = 4, |
c69618b3 | 4148 | .clk_init = macb_clk_init, |
421d9df0 CP |
4149 | .init = macb_init, |
4150 | }; | |
4151 | ||
3cef5c5b | 4152 | static const struct macb_config emac_config = { |
e501070e | 4153 | .caps = MACB_CAPS_NEEDS_RSTONUBR, |
c69618b3 | 4154 | .clk_init = at91ether_clk_init, |
421d9df0 CP |
4155 | .init = at91ether_init, |
4156 | }; | |
4157 | ||
e611b5b8 NA |
4158 | static const struct macb_config np4_config = { |
4159 | .caps = MACB_CAPS_USRIO_DISABLED, | |
4160 | .clk_init = macb_clk_init, | |
4161 | .init = macb_init, | |
4162 | }; | |
36583eb5 | 4163 | |
7b61f9c1 | 4164 | static const struct macb_config zynqmp_config = { |
ab91f0a9 RO |
4165 | .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | |
4166 | MACB_CAPS_JUMBO | | |
404cd086 | 4167 | MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH, |
7b61f9c1 HK |
4168 | .dma_burst_length = 16, |
4169 | .clk_init = macb_clk_init, | |
4170 | .init = macb_init, | |
98b5a0f4 | 4171 | .jumbo_max_len = 10240, |
7b61f9c1 HK |
4172 | }; |
4173 | ||
222ca8e0 | 4174 | static const struct macb_config zynq_config = { |
e501070e HK |
4175 | .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF | |
4176 | MACB_CAPS_NEEDS_RSTONUBR, | |
222ca8e0 NS |
4177 | .dma_burst_length = 16, |
4178 | .clk_init = macb_clk_init, | |
4179 | .init = macb_init, | |
4180 | }; | |
4181 | ||
421d9df0 CP |
4182 | static const struct of_device_id macb_dt_ids[] = { |
4183 | { .compatible = "cdns,at32ap7000-macb" }, | |
4184 | { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, | |
4185 | { .compatible = "cdns,macb" }, | |
e611b5b8 | 4186 | { .compatible = "cdns,np4-macb", .data = &np4_config }, |
421d9df0 CP |
4187 | { .compatible = "cdns,pc302-gem", .data = &pc302gem_config }, |
4188 | { .compatible = "cdns,gem", .data = &pc302gem_config }, | |
3e3e0cdf | 4189 | { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config }, |
5c8fe711 | 4190 | { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config }, |
421d9df0 | 4191 | { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config }, |
eb4ed8e2 | 4192 | { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config }, |
421d9df0 CP |
4193 | { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config }, |
4194 | { .compatible = "cdns,at91rm9200-emac", .data = &emac_config }, | |
4195 | { .compatible = "cdns,emac", .data = &emac_config }, | |
7b61f9c1 | 4196 | { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, |
222ca8e0 | 4197 | { .compatible = "cdns,zynq-gem", .data = &zynq_config }, |
6342ea88 | 4198 | { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, |
421d9df0 CP |
4199 | { /* sentinel */ } |
4200 | }; | |
4201 | MODULE_DEVICE_TABLE(of, macb_dt_ids); | |
4202 | #endif /* CONFIG_OF */ | |
4203 | ||
83a77e9e | 4204 | static const struct macb_config default_gem_config = { |
ab91f0a9 RO |
4205 | .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | |
4206 | MACB_CAPS_JUMBO | | |
4207 | MACB_CAPS_GEM_HAS_PTP, | |
83a77e9e BF |
4208 | .dma_burst_length = 16, |
4209 | .clk_init = macb_clk_init, | |
4210 | .init = macb_init, | |
4211 | .jumbo_max_len = 10240, | |
4212 | }; | |
4213 | ||
421d9df0 CP |
4214 | static int macb_probe(struct platform_device *pdev) |
4215 | { | |
83a77e9e | 4216 | const struct macb_config *macb_config = &default_gem_config; |
c69618b3 | 4217 | int (*clk_init)(struct platform_device *, struct clk **, |
f5473d1d HK |
4218 | struct clk **, struct clk **, struct clk **, |
4219 | struct clk **) = macb_config->clk_init; | |
83a77e9e | 4220 | int (*init)(struct platform_device *) = macb_config->init; |
421d9df0 | 4221 | struct device_node *np = pdev->dev.of_node; |
aead88bd | 4222 | struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL; |
f5473d1d | 4223 | struct clk *tsu_clk = NULL; |
421d9df0 | 4224 | unsigned int queue_mask, num_queues; |
f2ce8a9e | 4225 | bool native_io; |
0c65b2b9 | 4226 | phy_interface_t interface; |
421d9df0 CP |
4227 | struct net_device *dev; |
4228 | struct resource *regs; | |
4229 | void __iomem *mem; | |
4230 | const char *mac; | |
4231 | struct macb *bp; | |
404cd086 | 4232 | int err, val; |
421d9df0 | 4233 | |
f2ce8a9e AS |
4234 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
4235 | mem = devm_ioremap_resource(&pdev->dev, regs); | |
4236 | if (IS_ERR(mem)) | |
4237 | return PTR_ERR(mem); | |
4238 | ||
c69618b3 NF |
4239 | if (np) { |
4240 | const struct of_device_id *match; | |
4241 | ||
4242 | match = of_match_node(macb_dt_ids, np); | |
4243 | if (match && match->data) { | |
4244 | macb_config = match->data; | |
4245 | clk_init = macb_config->clk_init; | |
4246 | init = macb_config->init; | |
4247 | } | |
4248 | } | |
4249 | ||
f5473d1d | 4250 | err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk); |
c69618b3 NF |
4251 | if (err) |
4252 | return err; | |
4253 | ||
d54f89af HK |
4254 | pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT); |
4255 | pm_runtime_use_autosuspend(&pdev->dev); | |
4256 | pm_runtime_get_noresume(&pdev->dev); | |
4257 | pm_runtime_set_active(&pdev->dev); | |
4258 | pm_runtime_enable(&pdev->dev); | |
f2ce8a9e | 4259 | native_io = hw_is_native_io(mem); |
421d9df0 | 4260 | |
f2ce8a9e | 4261 | macb_probe_queues(mem, native_io, &queue_mask, &num_queues); |
421d9df0 | 4262 | dev = alloc_etherdev_mq(sizeof(*bp), num_queues); |
c69618b3 NF |
4263 | if (!dev) { |
4264 | err = -ENOMEM; | |
4265 | goto err_disable_clocks; | |
4266 | } | |
421d9df0 CP |
4267 | |
4268 | dev->base_addr = regs->start; | |
4269 | ||
4270 | SET_NETDEV_DEV(dev, &pdev->dev); | |
4271 | ||
4272 | bp = netdev_priv(dev); | |
4273 | bp->pdev = pdev; | |
4274 | bp->dev = dev; | |
4275 | bp->regs = mem; | |
f2ce8a9e AS |
4276 | bp->native_io = native_io; |
4277 | if (native_io) { | |
7a6e0706 DM |
4278 | bp->macb_reg_readl = hw_readl_native; |
4279 | bp->macb_reg_writel = hw_writel_native; | |
f2ce8a9e | 4280 | } else { |
7a6e0706 DM |
4281 | bp->macb_reg_readl = hw_readl; |
4282 | bp->macb_reg_writel = hw_writel; | |
f2ce8a9e | 4283 | } |
421d9df0 | 4284 | bp->num_queues = num_queues; |
bfa0914a | 4285 | bp->queue_mask = queue_mask; |
c69618b3 NF |
4286 | if (macb_config) |
4287 | bp->dma_burst_length = macb_config->dma_burst_length; | |
4288 | bp->pclk = pclk; | |
4289 | bp->hclk = hclk; | |
4290 | bp->tx_clk = tx_clk; | |
aead88bd | 4291 | bp->rx_clk = rx_clk; |
f5473d1d | 4292 | bp->tsu_clk = tsu_clk; |
f36dbe6a | 4293 | if (macb_config) |
98b5a0f4 | 4294 | bp->jumbo_max_len = macb_config->jumbo_max_len; |
98b5a0f4 | 4295 | |
3e2a5e15 | 4296 | bp->wol = 0; |
7c4a1d0c | 4297 | if (of_get_property(np, "magic-packet", NULL)) |
3e2a5e15 SP |
4298 | bp->wol |= MACB_WOL_HAS_MAGIC_PACKET; |
4299 | device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET); | |
4300 | ||
421d9df0 CP |
4301 | spin_lock_init(&bp->lock); |
4302 | ||
ad78347f | 4303 | /* setup capabilities */ |
f6970505 NF |
4304 | macb_configure_caps(bp, macb_config); |
4305 | ||
7b429614 RO |
4306 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
4307 | if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) { | |
4308 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(44)); | |
4309 | bp->hw_dma_cap |= HW_DMA_CAP_64B; | |
4310 | } | |
4311 | #endif | |
421d9df0 CP |
4312 | platform_set_drvdata(pdev, dev); |
4313 | ||
4314 | dev->irq = platform_get_irq(pdev, 0); | |
c69618b3 NF |
4315 | if (dev->irq < 0) { |
4316 | err = dev->irq; | |
b22ae0b4 | 4317 | goto err_out_free_netdev; |
c69618b3 | 4318 | } |
421d9df0 | 4319 | |
44770e11 JW |
4320 | /* MTU range: 68 - 1500 or 10240 */ |
4321 | dev->min_mtu = GEM_MTU_MIN_SIZE; | |
4322 | if (bp->caps & MACB_CAPS_JUMBO) | |
4323 | dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN; | |
4324 | else | |
4325 | dev->max_mtu = ETH_DATA_LEN; | |
4326 | ||
404cd086 HK |
4327 | if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) { |
4328 | val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10)); | |
4329 | if (val) | |
4330 | bp->rx_bd_rd_prefetch = (2 << (val - 1)) * | |
4331 | macb_dma_desc_get_size(bp); | |
4332 | ||
4333 | val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10)); | |
4334 | if (val) | |
4335 | bp->tx_bd_rd_prefetch = (2 << (val - 1)) * | |
4336 | macb_dma_desc_get_size(bp); | |
4337 | } | |
4338 | ||
e501070e HK |
4339 | bp->rx_intr_mask = MACB_RX_INT_FLAGS; |
4340 | if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR) | |
4341 | bp->rx_intr_mask |= MACB_BIT(RXUBR); | |
4342 | ||
421d9df0 | 4343 | mac = of_get_mac_address(np); |
541ddc66 PÅ |
4344 | if (PTR_ERR(mac) == -EPROBE_DEFER) { |
4345 | err = -EPROBE_DEFER; | |
4346 | goto err_out_free_netdev; | |
2bf4ecbc | 4347 | } else if (!IS_ERR_OR_NULL(mac)) { |
eefb52d1 | 4348 | ether_addr_copy(bp->dev->dev_addr, mac); |
aa076e3d | 4349 | } else { |
541ddc66 | 4350 | macb_get_hwaddr(bp); |
aa076e3d | 4351 | } |
fb97a846 | 4352 | |
0c65b2b9 AL |
4353 | err = of_get_phy_mode(np, &interface); |
4354 | if (err) | |
8b952747 NF |
4355 | /* not found in DT, MII by default */ |
4356 | bp->phy_interface = PHY_INTERFACE_MODE_MII; | |
4357 | else | |
0c65b2b9 | 4358 | bp->phy_interface = interface; |
6c36a707 | 4359 | |
7897b071 AT |
4360 | bp->speed = SPEED_UNKNOWN; |
4361 | ||
421d9df0 CP |
4362 | /* IP specific init */ |
4363 | err = init(pdev); | |
4364 | if (err) | |
4365 | goto err_out_free_netdev; | |
89e5785f | 4366 | |
cf669660 FF |
4367 | err = macb_mii_init(bp); |
4368 | if (err) | |
4369 | goto err_out_free_netdev; | |
4370 | ||
cf669660 FF |
4371 | netif_carrier_off(dev); |
4372 | ||
89e5785f HS |
4373 | err = register_netdev(dev); |
4374 | if (err) { | |
4375 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | |
cf669660 | 4376 | goto err_out_unregister_mdio; |
89e5785f HS |
4377 | } |
4378 | ||
032dc41b HK |
4379 | tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task, |
4380 | (unsigned long)bp); | |
4381 | ||
5879823f BS |
4382 | netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n", |
4383 | macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID), | |
4384 | dev->base_addr, dev->irq, dev->dev_addr); | |
89e5785f | 4385 | |
d54f89af HK |
4386 | pm_runtime_mark_last_busy(&bp->pdev->dev); |
4387 | pm_runtime_put_autosuspend(&bp->pdev->dev); | |
4388 | ||
89e5785f HS |
4389 | return 0; |
4390 | ||
cf669660 | 4391 | err_out_unregister_mdio: |
cf669660 FF |
4392 | mdiobus_unregister(bp->mii_bus); |
4393 | mdiobus_free(bp->mii_bus); | |
4394 | ||
cf250de0 | 4395 | err_out_free_netdev: |
02c958dd | 4396 | free_netdev(dev); |
421d9df0 | 4397 | |
c69618b3 NF |
4398 | err_disable_clocks: |
4399 | clk_disable_unprepare(tx_clk); | |
c218ad55 | 4400 | clk_unregister(tx_clk); |
c69618b3 NF |
4401 | clk_disable_unprepare(hclk); |
4402 | clk_disable_unprepare(pclk); | |
aead88bd | 4403 | clk_disable_unprepare(rx_clk); |
f5473d1d | 4404 | clk_disable_unprepare(tsu_clk); |
d54f89af HK |
4405 | pm_runtime_disable(&pdev->dev); |
4406 | pm_runtime_set_suspended(&pdev->dev); | |
4407 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
c69618b3 | 4408 | |
89e5785f HS |
4409 | return err; |
4410 | } | |
4411 | ||
9e86d766 | 4412 | static int macb_remove(struct platform_device *pdev) |
89e5785f HS |
4413 | { |
4414 | struct net_device *dev; | |
4415 | struct macb *bp; | |
4416 | ||
4417 | dev = platform_get_drvdata(pdev); | |
4418 | ||
4419 | if (dev) { | |
4420 | bp = netdev_priv(dev); | |
298cf9be | 4421 | mdiobus_unregister(bp->mii_bus); |
298cf9be | 4422 | mdiobus_free(bp->mii_bus); |
5833e052 | 4423 | |
89e5785f | 4424 | unregister_netdev(dev); |
d54f89af HK |
4425 | pm_runtime_disable(&pdev->dev); |
4426 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
4427 | if (!pm_runtime_suspended(&pdev->dev)) { | |
4428 | clk_disable_unprepare(bp->tx_clk); | |
c218ad55 | 4429 | clk_unregister(bp->tx_clk); |
d54f89af HK |
4430 | clk_disable_unprepare(bp->hclk); |
4431 | clk_disable_unprepare(bp->pclk); | |
4432 | clk_disable_unprepare(bp->rx_clk); | |
4433 | clk_disable_unprepare(bp->tsu_clk); | |
4434 | pm_runtime_set_suspended(&pdev->dev); | |
4435 | } | |
7897b071 | 4436 | phylink_destroy(bp->phylink); |
e965be7d | 4437 | free_netdev(dev); |
89e5785f HS |
4438 | } |
4439 | ||
4440 | return 0; | |
4441 | } | |
4442 | ||
d23823dd | 4443 | static int __maybe_unused macb_suspend(struct device *dev) |
c1f598fd | 4444 | { |
ce886a47 | 4445 | struct net_device *netdev = dev_get_drvdata(dev); |
c1f598fd | 4446 | struct macb *bp = netdev_priv(netdev); |
de991c58 HK |
4447 | struct macb_queue *queue = bp->queues; |
4448 | unsigned long flags; | |
4449 | unsigned int q; | |
4450 | ||
4451 | if (!netif_running(netdev)) | |
4452 | return 0; | |
c1f598fd | 4453 | |
3e2a5e15 SP |
4454 | if (bp->wol & MACB_WOL_ENABLED) { |
4455 | macb_writel(bp, IER, MACB_BIT(WOL)); | |
4456 | macb_writel(bp, WOL, MACB_BIT(MAG)); | |
4457 | enable_irq_wake(bp->queues[0].irq); | |
de991c58 HK |
4458 | netif_device_detach(netdev); |
4459 | } else { | |
4460 | netif_device_detach(netdev); | |
4461 | for (q = 0, queue = bp->queues; q < bp->num_queues; | |
4462 | ++q, ++queue) | |
4463 | napi_disable(&queue->napi); | |
7897b071 AT |
4464 | rtnl_lock(); |
4465 | phylink_stop(bp->phylink); | |
4466 | rtnl_unlock(); | |
de991c58 HK |
4467 | spin_lock_irqsave(&bp->lock, flags); |
4468 | macb_reset_hw(bp); | |
4469 | spin_unlock_irqrestore(&bp->lock, flags); | |
c1e85c6c CB |
4470 | |
4471 | if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) | |
4472 | bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO); | |
4473 | ||
4474 | if (netdev->hw_features & NETIF_F_NTUPLE) | |
4475 | bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT); | |
3e2a5e15 | 4476 | } |
d54f89af | 4477 | |
de991c58 HK |
4478 | netif_carrier_off(netdev); |
4479 | if (bp->ptp_info) | |
4480 | bp->ptp_info->ptp_remove(netdev); | |
d54f89af | 4481 | pm_runtime_force_suspend(dev); |
c1f598fd HS |
4482 | |
4483 | return 0; | |
4484 | } | |
4485 | ||
d23823dd | 4486 | static int __maybe_unused macb_resume(struct device *dev) |
c1f598fd | 4487 | { |
ce886a47 | 4488 | struct net_device *netdev = dev_get_drvdata(dev); |
c1f598fd | 4489 | struct macb *bp = netdev_priv(netdev); |
de991c58 HK |
4490 | struct macb_queue *queue = bp->queues; |
4491 | unsigned int q; | |
4492 | ||
4493 | if (!netif_running(netdev)) | |
4494 | return 0; | |
c1f598fd | 4495 | |
d54f89af HK |
4496 | pm_runtime_force_resume(dev); |
4497 | ||
3e2a5e15 SP |
4498 | if (bp->wol & MACB_WOL_ENABLED) { |
4499 | macb_writel(bp, IDR, MACB_BIT(WOL)); | |
4500 | macb_writel(bp, WOL, 0); | |
4501 | disable_irq_wake(bp->queues[0].irq); | |
de991c58 HK |
4502 | } else { |
4503 | macb_writel(bp, NCR, MACB_BIT(MPE)); | |
c1e85c6c CB |
4504 | |
4505 | if (netdev->hw_features & NETIF_F_NTUPLE) | |
4506 | gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2); | |
4507 | ||
4508 | if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) | |
4509 | macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio); | |
4510 | ||
de991c58 HK |
4511 | for (q = 0, queue = bp->queues; q < bp->num_queues; |
4512 | ++q, ++queue) | |
4513 | napi_enable(&queue->napi); | |
7897b071 AT |
4514 | rtnl_lock(); |
4515 | phylink_start(bp->phylink); | |
4516 | rtnl_unlock(); | |
d54f89af HK |
4517 | } |
4518 | ||
de991c58 HK |
4519 | macb_init_hw(bp); |
4520 | macb_set_rx_mode(netdev); | |
c1e85c6c | 4521 | macb_restore_features(bp); |
d54f89af | 4522 | netif_device_attach(netdev); |
de991c58 HK |
4523 | if (bp->ptp_info) |
4524 | bp->ptp_info->ptp_init(netdev); | |
d54f89af HK |
4525 | |
4526 | return 0; | |
4527 | } | |
4528 | ||
4529 | static int __maybe_unused macb_runtime_suspend(struct device *dev) | |
4530 | { | |
f9cb7597 | 4531 | struct net_device *netdev = dev_get_drvdata(dev); |
d54f89af HK |
4532 | struct macb *bp = netdev_priv(netdev); |
4533 | ||
4534 | if (!(device_may_wakeup(&bp->dev->dev))) { | |
4535 | clk_disable_unprepare(bp->tx_clk); | |
4536 | clk_disable_unprepare(bp->hclk); | |
4537 | clk_disable_unprepare(bp->pclk); | |
4538 | clk_disable_unprepare(bp->rx_clk); | |
4539 | } | |
4540 | clk_disable_unprepare(bp->tsu_clk); | |
4541 | ||
4542 | return 0; | |
4543 | } | |
4544 | ||
4545 | static int __maybe_unused macb_runtime_resume(struct device *dev) | |
4546 | { | |
f9cb7597 | 4547 | struct net_device *netdev = dev_get_drvdata(dev); |
d54f89af HK |
4548 | struct macb *bp = netdev_priv(netdev); |
4549 | ||
4550 | if (!(device_may_wakeup(&bp->dev->dev))) { | |
3e2a5e15 SP |
4551 | clk_prepare_enable(bp->pclk); |
4552 | clk_prepare_enable(bp->hclk); | |
4553 | clk_prepare_enable(bp->tx_clk); | |
aead88bd | 4554 | clk_prepare_enable(bp->rx_clk); |
3e2a5e15 | 4555 | } |
f5473d1d | 4556 | clk_prepare_enable(bp->tsu_clk); |
c1f598fd | 4557 | |
c1f598fd HS |
4558 | return 0; |
4559 | } | |
c1f598fd | 4560 | |
d54f89af HK |
4561 | static const struct dev_pm_ops macb_pm_ops = { |
4562 | SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume) | |
4563 | SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL) | |
4564 | }; | |
0dfc3e18 | 4565 | |
89e5785f | 4566 | static struct platform_driver macb_driver = { |
9e86d766 NR |
4567 | .probe = macb_probe, |
4568 | .remove = macb_remove, | |
89e5785f HS |
4569 | .driver = { |
4570 | .name = "macb", | |
fb97a846 | 4571 | .of_match_table = of_match_ptr(macb_dt_ids), |
0dfc3e18 | 4572 | .pm = &macb_pm_ops, |
89e5785f HS |
4573 | }, |
4574 | }; | |
4575 | ||
9e86d766 | 4576 | module_platform_driver(macb_driver); |
89e5785f HS |
4577 | |
4578 | MODULE_LICENSE("GPL"); | |
f75ba50b | 4579 | MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); |
e05503ef | 4580 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
72abb461 | 4581 | MODULE_ALIAS("platform:macb"); |