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liquidio: soft command buffer limits
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / cavium / liquidio / lio_ethtool.c
CommitLineData
f21fb3ed
RV		 1/**********************************************************************
2* Author: Cavium, Inc.
3*
4* Contact: support@cavium.com
5* Please include "LiquidIO" in the subject.
6*
7* Copyright (c) 2003-2015 Cavium, Inc.
8*
9* This file is free software; you can redistribute it and/or modify
10* it under the terms of the GNU General Public License, Version 2, as
11* published by the Free Software Foundation.
12*
13* This file is distributed in the hope that it will be useful, but
14* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16* NONINFRINGEMENT. See the GNU General Public License for more
17* details.
18*
19* This file may also be available under a different license from Cavium.
20* Contact Cavium, Inc. for more information
21**********************************************************************/
22#include <linux/version.h>
23#include <linux/netdevice.h>
24#include <linux/net_tstamp.h>
25#include <linux/ethtool.h>
26#include <linux/dma-mapping.h>
27#include <linux/pci.h>
28#include "octeon_config.h"
29#include "liquidio_common.h"
30#include "octeon_droq.h"
31#include "octeon_iq.h"
32#include "response_manager.h"
33#include "octeon_device.h"
34#include "octeon_nic.h"
35#include "octeon_main.h"
36#include "octeon_network.h"
37#include "cn66xx_regs.h"
38#include "cn66xx_device.h"
39#include "cn68xx_regs.h"
40#include "cn68xx_device.h"
41#include "liquidio_image.h"
42
43struct oct_mdio_cmd_context {
44 int octeon_id;
45 wait_queue_head_t wc;
46 int cond;
47};
48
49struct oct_mdio_cmd_resp {
50 u64 rh;
51 struct oct_mdio_cmd resp;
52 u64 status;
53};
54
55#define OCT_MDIO45_RESP_SIZE (sizeof(struct oct_mdio_cmd_resp))
56
57/* Octeon's interface mode of operation */
58enum {
59 INTERFACE_MODE_DISABLED,
60 INTERFACE_MODE_RGMII,
61 INTERFACE_MODE_GMII,
62 INTERFACE_MODE_SPI,
63 INTERFACE_MODE_PCIE,
64 INTERFACE_MODE_XAUI,
65 INTERFACE_MODE_SGMII,
66 INTERFACE_MODE_PICMG,
67 INTERFACE_MODE_NPI,
68 INTERFACE_MODE_LOOP,
69 INTERFACE_MODE_SRIO,
70 INTERFACE_MODE_ILK,
71 INTERFACE_MODE_RXAUI,
72 INTERFACE_MODE_QSGMII,
73 INTERFACE_MODE_AGL,
74};
75
76#define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0]))
77#define OCT_ETHTOOL_REGDUMP_LEN 4096
78#define OCT_ETHTOOL_REGSVER 1
79
80static const char oct_iq_stats_strings[][ETH_GSTRING_LEN] = {
81 "Instr posted",
82 "Instr processed",
83 "Instr dropped",
84 "Bytes Sent",
85 "Sgentry_sent",
86 "Inst cntreg",
87 "Tx done",
88 "Tx Iq busy",
89 "Tx dropped",
90 "Tx bytes",
91};
92
93static const char oct_droq_stats_strings[][ETH_GSTRING_LEN] = {
94 "OQ Pkts Received",
95 "OQ Bytes Received",
96 "Dropped no dispatch",
97 "Dropped nomem",
98 "Dropped toomany",
99 "Stack RX cnt",
100 "Stack RX Bytes",
101 "RX dropped",
102};
103
104#define OCTNIC_NCMD_AUTONEG_ON 0x1
105#define OCTNIC_NCMD_PHY_ON 0x2
106
107static int lio_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
108{
109 struct lio *lio = GET_LIO(netdev);
110 struct octeon_device *oct = lio->oct_dev;
111 struct oct_link_info *linfo;
112
113 linfo = &lio->linfo;
114
115 if (linfo->link.s.interface == INTERFACE_MODE_XAUI ||
116 linfo->link.s.interface == INTERFACE_MODE_RXAUI) {
117 ecmd->port = PORT_FIBRE;
118 ecmd->supported =
119 (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE |
120 SUPPORTED_Pause);
121 ecmd->advertising =
122 (ADVERTISED_10000baseT_Full | ADVERTISED_Pause);
123 ecmd->transceiver = XCVR_EXTERNAL;
124 ecmd->autoneg = AUTONEG_DISABLE;
125
126 } else {
127 dev_err(&oct->pci_dev->dev, "Unknown link interface reported\n");
128 }
129
0cece6c5 130 if (linfo->link.s.link_up) {
f21fb3ed
RV		 131 ethtool_cmd_speed_set(ecmd, linfo->link.s.speed);
132 ecmd->duplex = linfo->link.s.duplex;
133 } else {
134 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
135 ecmd->duplex = DUPLEX_UNKNOWN;
136 }
137
138 return 0;
139}
140
141static void
142lio_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
143{
144 struct lio *lio;
145 struct octeon_device *oct;
146
147 lio = GET_LIO(netdev);
148 oct = lio->oct_dev;
149
150 memset(drvinfo, 0, sizeof(struct ethtool_drvinfo));
151 strcpy(drvinfo->driver, "liquidio");
152 strcpy(drvinfo->version, LIQUIDIO_VERSION);
153 strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version,
154 ETHTOOL_FWVERS_LEN);
155 strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32);
f21fb3ed
RV		 156}
157
158static void
159lio_ethtool_get_channels(struct net_device *dev,
160 struct ethtool_channels *channel)
161{
162 struct lio *lio = GET_LIO(dev);
163 struct octeon_device *oct = lio->oct_dev;
164 u32 max_rx = 0, max_tx = 0, tx_count = 0, rx_count = 0;
165
166 if (OCTEON_CN6XXX(oct)) {
167 struct octeon_config *conf6x = CHIP_FIELD(oct, cn6xxx, conf);
168
169 max_rx = CFG_GET_OQ_MAX_Q(conf6x);
170 max_tx = CFG_GET_IQ_MAX_Q(conf6x);
171 rx_count = CFG_GET_NUM_RXQS_NIC_IF(conf6x, lio->ifidx);
172 tx_count = CFG_GET_NUM_TXQS_NIC_IF(conf6x, lio->ifidx);
173 }
174
175 channel->max_rx = max_rx;
176 channel->max_tx = max_tx;
177 channel->rx_count = rx_count;
178 channel->tx_count = tx_count;
179}
180
181static int lio_get_eeprom_len(struct net_device *netdev)
182{
183 u8 buf[128];
184 struct lio *lio = GET_LIO(netdev);
185 struct octeon_device *oct_dev = lio->oct_dev;
186 struct octeon_board_info *board_info;
187 int len;
188
189 board_info = (struct octeon_board_info *)(&oct_dev->boardinfo);
190 len = sprintf(buf, "boardname:%s serialnum:%s maj:%lld min:%lld\n",
191 board_info->name, board_info->serial_number,
192 board_info->major, board_info->minor);
193
194 return len;
195}
196
197static int
198lio_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom,
199 u8 *bytes)
200{
201 struct lio *lio = GET_LIO(netdev);
202 struct octeon_device *oct_dev = lio->oct_dev;
203 struct octeon_board_info *board_info;
204 int len;
205
206 if (eeprom->offset != 0)
207 return -EINVAL;
208
209 eeprom->magic = oct_dev->pci_dev->vendor;
210 board_info = (struct octeon_board_info *)(&oct_dev->boardinfo);
211 len =
212 sprintf((char *)bytes,
213 "boardname:%s serialnum:%s maj:%lld min:%lld\n",
214 board_info->name, board_info->serial_number,
215 board_info->major, board_info->minor);
216
217 return 0;
218}
219
220static int octnet_gpio_access(struct net_device *netdev, int addr, int val)
221{
222 struct lio *lio = GET_LIO(netdev);
223 struct octeon_device *oct = lio->oct_dev;
224 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 225 int ret = 0;
226
227 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
228
229 nctrl.ncmd.u64 = 0;
230 nctrl.ncmd.s.cmd = OCTNET_CMD_GPIO_ACCESS;
0cece6c5
RV		 231 nctrl.ncmd.s.param1 = addr;
232 nctrl.ncmd.s.param2 = val;
233 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 234 nctrl.wait_time = 100;
235 nctrl.netpndev = (u64)netdev;
236 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
237
0cece6c5 238 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 239 if (ret < 0) {
240 dev_err(&oct->pci_dev->dev, "Failed to configure gpio value\n");
241 return -EINVAL;
242 }
243
244 return 0;
245}
246
247/* Callback for when mdio command response arrives
248 */
249static void octnet_mdio_resp_callback(struct octeon_device *oct,
250 u32 status,
251 void *buf)
252{
253 struct oct_mdio_cmd_resp *mdio_cmd_rsp;
254 struct oct_mdio_cmd_context *mdio_cmd_ctx;
255 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
256
257 mdio_cmd_rsp = (struct oct_mdio_cmd_resp *)sc->virtrptr;
258 mdio_cmd_ctx = (struct oct_mdio_cmd_context *)sc->ctxptr;
259
260 oct = lio_get_device(mdio_cmd_ctx->octeon_id);
261 if (status) {
262 dev_err(&oct->pci_dev->dev, "MIDO instruction failed. Status: %llx\n",
263 CVM_CAST64(status));
264 ACCESS_ONCE(mdio_cmd_ctx->cond) = -1;
265 } else {
266 ACCESS_ONCE(mdio_cmd_ctx->cond) = 1;
267 }
268 wake_up_interruptible(&mdio_cmd_ctx->wc);
269}
270
271/* This routine provides PHY access routines for
272 * mdio clause45 .
273 */
274static int
275octnet_mdio45_access(struct lio *lio, int op, int loc, int *value)
276{
277 struct octeon_device *oct_dev = lio->oct_dev;
278 struct octeon_soft_command *sc;
279 struct oct_mdio_cmd_resp *mdio_cmd_rsp;
280 struct oct_mdio_cmd_context *mdio_cmd_ctx;
281 struct oct_mdio_cmd *mdio_cmd;
282 int retval = 0;
283
284 sc = (struct octeon_soft_command *)
285 octeon_alloc_soft_command(oct_dev,
286 sizeof(struct oct_mdio_cmd),
287 sizeof(struct oct_mdio_cmd_resp),
288 sizeof(struct oct_mdio_cmd_context));
289
290 if (!sc)
291 return -ENOMEM;
292
293 mdio_cmd_ctx = (struct oct_mdio_cmd_context *)sc->ctxptr;
294 mdio_cmd_rsp = (struct oct_mdio_cmd_resp *)sc->virtrptr;
295 mdio_cmd = (struct oct_mdio_cmd *)sc->virtdptr;
296
297 ACCESS_ONCE(mdio_cmd_ctx->cond) = 0;
298 mdio_cmd_ctx->octeon_id = lio_get_device_id(oct_dev);
299 mdio_cmd->op = op;
300 mdio_cmd->mdio_addr = loc;
301 if (op)
302 mdio_cmd->value1 = *value;
f21fb3ed
RV		 303 octeon_swap_8B_data((u64 *)mdio_cmd, sizeof(struct oct_mdio_cmd) / 8);
304
0cece6c5
RV		 305 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
306
f21fb3ed
RV		 307 octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC, OPCODE_NIC_MDIO45,
308 0, 0, 0);
309
310 sc->wait_time = 1000;
311 sc->callback = octnet_mdio_resp_callback;
312 sc->callback_arg = sc;
313
314 init_waitqueue_head(&mdio_cmd_ctx->wc);
315
316 retval = octeon_send_soft_command(oct_dev, sc);
317
ddc173a6 318 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 319 dev_err(&oct_dev->pci_dev->dev,
320 "octnet_mdio45_access instruction failed status: %x\n",
321 retval);
322 retval = -EBUSY;
323 } else {
324 /* Sleep on a wait queue till the cond flag indicates that the
325 * response arrived
326 */
327 sleep_cond(&mdio_cmd_ctx->wc, &mdio_cmd_ctx->cond);
328 retval = mdio_cmd_rsp->status;
329 if (retval) {
330 dev_err(&oct_dev->pci_dev->dev, "octnet mdio45 access failed\n");
331 retval = -EBUSY;
332 } else {
333 octeon_swap_8B_data((u64 *)(&mdio_cmd_rsp->resp),
334 sizeof(struct oct_mdio_cmd) / 8);
335
336 if (ACCESS_ONCE(mdio_cmd_ctx->cond) == 1) {
337 if (!op)
338 *value = mdio_cmd_rsp->resp.value1;
339 } else {
340 retval = -EINVAL;
341 }
342 }
343 }
344
345 octeon_free_soft_command(oct_dev, sc);
346
347 return retval;
348}
349
350static int lio_set_phys_id(struct net_device *netdev,
351 enum ethtool_phys_id_state state)
352{
353 struct lio *lio = GET_LIO(netdev);
354 struct octeon_device *oct = lio->oct_dev;
355 int value, ret;
356
357 switch (state) {
358 case ETHTOOL_ID_ACTIVE:
359 if (oct->chip_id == OCTEON_CN66XX) {
360 octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
361 VITESSE_PHY_GPIO_DRIVEON);
362 return 2;
363
364 } else if (oct->chip_id == OCTEON_CN68XX) {
365 /* Save the current LED settings */
366 ret = octnet_mdio45_access(lio, 0,
367 LIO68XX_LED_BEACON_ADDR,
368 &lio->phy_beacon_val);
369 if (ret)
370 return ret;
371
372 ret = octnet_mdio45_access(lio, 0,
373 LIO68XX_LED_CTRL_ADDR,
374 &lio->led_ctrl_val);
375 if (ret)
376 return ret;
377
378 /* Configure Beacon values */
379 value = LIO68XX_LED_BEACON_CFGON;
380 ret =
381 octnet_mdio45_access(lio, 1,
382 LIO68XX_LED_BEACON_ADDR,
383 &value);
384 if (ret)
385 return ret;
386
387 value = LIO68XX_LED_CTRL_CFGON;
388 ret =
389 octnet_mdio45_access(lio, 1,
390 LIO68XX_LED_CTRL_ADDR,
391 &value);
392 if (ret)
393 return ret;
394 } else {
395 return -EINVAL;
396 }
397 break;
398
399 case ETHTOOL_ID_ON:
400 if (oct->chip_id == OCTEON_CN66XX) {
401 octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
402 VITESSE_PHY_GPIO_HIGH);
403
404 } else if (oct->chip_id == OCTEON_CN68XX) {
405 return -EINVAL;
406 } else {
407 return -EINVAL;
408 }
409 break;
410
411 case ETHTOOL_ID_OFF:
412 if (oct->chip_id == OCTEON_CN66XX)
413 octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
414 VITESSE_PHY_GPIO_LOW);
415 else if (oct->chip_id == OCTEON_CN68XX)
416 return -EINVAL;
417 else
418 return -EINVAL;
419
420 break;
421
422 case ETHTOOL_ID_INACTIVE:
423 if (oct->chip_id == OCTEON_CN66XX) {
424 octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
425 VITESSE_PHY_GPIO_DRIVEOFF);
426 } else if (oct->chip_id == OCTEON_CN68XX) {
427 /* Restore LED settings */
428 ret = octnet_mdio45_access(lio, 1,
429 LIO68XX_LED_CTRL_ADDR,
430 &lio->led_ctrl_val);
431 if (ret)
432 return ret;
433
cbdb9777
DC		 434 ret = octnet_mdio45_access(lio, 1,
435 LIO68XX_LED_BEACON_ADDR,
436 &lio->phy_beacon_val);
f21fb3ed
RV		 437 if (ret)
438 return ret;
439
440 } else {
441 return -EINVAL;
442 }
443 break;
444
445 default:
446 return -EINVAL;
447 }
448
449 return 0;
450}
451
452static void
453lio_ethtool_get_ringparam(struct net_device *netdev,
454 struct ethtool_ringparam *ering)
455{
456 struct lio *lio = GET_LIO(netdev);
457 struct octeon_device *oct = lio->oct_dev;
458 u32 tx_max_pending = 0, rx_max_pending = 0, tx_pending = 0,
459 rx_pending = 0;
460
461 if (OCTEON_CN6XXX(oct)) {
462 struct octeon_config *conf6x = CHIP_FIELD(oct, cn6xxx, conf);
463
464 tx_max_pending = CN6XXX_MAX_IQ_DESCRIPTORS;
465 rx_max_pending = CN6XXX_MAX_OQ_DESCRIPTORS;
466 rx_pending = CFG_GET_NUM_RX_DESCS_NIC_IF(conf6x, lio->ifidx);
467 tx_pending = CFG_GET_NUM_TX_DESCS_NIC_IF(conf6x, lio->ifidx);
468 }
469
470 if (lio->mtu > OCTNET_DEFAULT_FRM_SIZE) {
471 ering->rx_pending = 0;
472 ering->rx_max_pending = 0;
473 ering->rx_mini_pending = 0;
474 ering->rx_jumbo_pending = rx_pending;
475 ering->rx_mini_max_pending = 0;
476 ering->rx_jumbo_max_pending = rx_max_pending;
477 } else {
478 ering->rx_pending = rx_pending;
479 ering->rx_max_pending = rx_max_pending;
480 ering->rx_mini_pending = 0;
481 ering->rx_jumbo_pending = 0;
482 ering->rx_mini_max_pending = 0;
483 ering->rx_jumbo_max_pending = 0;
484 }
485
486 ering->tx_pending = tx_pending;
487 ering->tx_max_pending = tx_max_pending;
488}
489
490static u32 lio_get_msglevel(struct net_device *netdev)
491{
492 struct lio *lio = GET_LIO(netdev);
493
494 return lio->msg_enable;
495}
496
497static void lio_set_msglevel(struct net_device *netdev, u32 msglvl)
498{
499 struct lio *lio = GET_LIO(netdev);
500
501 if ((msglvl ^ lio->msg_enable) & NETIF_MSG_HW) {
502 if (msglvl & NETIF_MSG_HW)
503 liquidio_set_feature(netdev,
0cece6c5 504 OCTNET_CMD_VERBOSE_ENABLE, 0);
f21fb3ed
RV		 505 else
506 liquidio_set_feature(netdev,
0cece6c5 507 OCTNET_CMD_VERBOSE_DISABLE, 0);
f21fb3ed
RV		 508 }
509
510 lio->msg_enable = msglvl;
511}
512
513static void
514lio_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
515{
516 /* Notes: Not supporting any auto negotiation in these
517 * drivers. Just report pause frame support.
518 */
519 pause->tx_pause = 1;
520 pause->rx_pause = 1; /* TODO: Need to support RX pause frame!!. */
521}
522
523static void
524lio_get_ethtool_stats(struct net_device *netdev,
525 struct ethtool_stats *stats, u64 *data)
526{
527 struct lio *lio = GET_LIO(netdev);
528 struct octeon_device *oct_dev = lio->oct_dev;
529 int i = 0, j;
530
63da8404
RV		 531 for (j = 0; j < MAX_OCTEON_INSTR_QUEUES(oct); j++) {
532 if (!(oct_dev->io_qmask.iq & (1ULL << j)))
f21fb3ed
RV		 533 continue;
534 data[i++] =
535 CVM_CAST64(oct_dev->instr_queue[j]->stats.instr_posted);
536 data[i++] =
537 CVM_CAST64(
538 oct_dev->instr_queue[j]->stats.instr_processed);
539 data[i++] =
540 CVM_CAST64(
541 oct_dev->instr_queue[j]->stats.instr_dropped);
542 data[i++] =
543 CVM_CAST64(oct_dev->instr_queue[j]->stats.bytes_sent);
544 data[i++] =
545 CVM_CAST64(oct_dev->instr_queue[j]->stats.sgentry_sent);
546 data[i++] =
547 readl(oct_dev->instr_queue[j]->inst_cnt_reg);
548 data[i++] =
549 CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_done);
550 data[i++] =
551 CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_iq_busy);
552 data[i++] =
553 CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_dropped);
554 data[i++] =
555 CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_tot_bytes);
556 }
557
558 /* for (j = 0; j < oct_dev->num_oqs; j++){ */
63da8404
RV		 559 for (j = 0; j < MAX_OCTEON_OUTPUT_QUEUES(oct); j++) {
560 if (!(oct_dev->io_qmask.oq & (1ULL << j)))
f21fb3ed
RV		 561 continue;
562 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.pkts_received);
563 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.bytes_received);
564 data[i++] =
565 CVM_CAST64(oct_dev->droq[j]->stats.dropped_nodispatch);
566 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem);
567 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_toomany);
568 data[i++] =
569 CVM_CAST64(oct_dev->droq[j]->stats.rx_pkts_received);
570 data[i++] =
571 CVM_CAST64(oct_dev->droq[j]->stats.rx_bytes_received);
572 data[i++] =
573 CVM_CAST64(oct_dev->droq[j]->stats.rx_dropped);
574 }
575}
576
577static void lio_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
578{
579 struct lio *lio = GET_LIO(netdev);
580 struct octeon_device *oct_dev = lio->oct_dev;
581 int num_iq_stats, num_oq_stats, i, j;
582
583 num_iq_stats = ARRAY_SIZE(oct_iq_stats_strings);
63da8404
RV		 584 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
585 if (!(oct_dev->io_qmask.iq & (1ULL << i)))
f21fb3ed
RV		 586 continue;
587 for (j = 0; j < num_iq_stats; j++) {
588 sprintf(data, "IQ%d %s", i, oct_iq_stats_strings[j]);
589 data += ETH_GSTRING_LEN;
590 }
591 }
592
593 num_oq_stats = ARRAY_SIZE(oct_droq_stats_strings);
594 /* for (i = 0; i < oct_dev->num_oqs; i++) { */
63da8404
RV		 595 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
596 if (!(oct_dev->io_qmask.oq & (1ULL << i)))
f21fb3ed
RV		 597 continue;
598 for (j = 0; j < num_oq_stats; j++) {
599 sprintf(data, "OQ%d %s", i, oct_droq_stats_strings[j]);
600 data += ETH_GSTRING_LEN;
601 }
602 }
603}
604
605static int lio_get_sset_count(struct net_device *netdev, int sset)
606{
607 struct lio *lio = GET_LIO(netdev);
608 struct octeon_device *oct_dev = lio->oct_dev;
609
610 return (ARRAY_SIZE(oct_iq_stats_strings) * oct_dev->num_iqs) +
611 (ARRAY_SIZE(oct_droq_stats_strings) * oct_dev->num_oqs);
612}
613
614static int lio_get_intr_coalesce(struct net_device *netdev,
615 struct ethtool_coalesce *intr_coal)
616{
617 struct lio *lio = GET_LIO(netdev);
618 struct octeon_device *oct = lio->oct_dev;
619 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip;
620 struct octeon_instr_queue *iq;
621 struct oct_intrmod_cfg *intrmod_cfg;
622
623 intrmod_cfg = &oct->intrmod;
624
625 switch (oct->chip_id) {
626 /* case OCTEON_CN73XX: Todo */
627 /* break; */
628 case OCTEON_CN68XX:
629 case OCTEON_CN66XX:
630 if (!intrmod_cfg->intrmod_enable) {
631 intr_coal->rx_coalesce_usecs =
632 CFG_GET_OQ_INTR_TIME(cn6xxx->conf);
633 intr_coal->rx_max_coalesced_frames =
634 CFG_GET_OQ_INTR_PKT(cn6xxx->conf);
635 } else {
636 intr_coal->use_adaptive_rx_coalesce =
637 intrmod_cfg->intrmod_enable;
638 intr_coal->rate_sample_interval =
639 intrmod_cfg->intrmod_check_intrvl;
640 intr_coal->pkt_rate_high =
641 intrmod_cfg->intrmod_maxpkt_ratethr;
642 intr_coal->pkt_rate_low =
643 intrmod_cfg->intrmod_minpkt_ratethr;
644 intr_coal->rx_max_coalesced_frames_high =
645 intrmod_cfg->intrmod_maxcnt_trigger;
646 intr_coal->rx_coalesce_usecs_high =
647 intrmod_cfg->intrmod_maxtmr_trigger;
648 intr_coal->rx_coalesce_usecs_low =
649 intrmod_cfg->intrmod_mintmr_trigger;
650 intr_coal->rx_max_coalesced_frames_low =
651 intrmod_cfg->intrmod_mincnt_trigger;
652 }
653
26236fa9 654 iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no];
f21fb3ed
RV		 655 intr_coal->tx_max_coalesced_frames = iq->fill_threshold;
656 break;
657
658 default:
659 netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n");
660 return -EINVAL;
661 }
662
663 return 0;
664}
665
666/* Callback function for intrmod */
667static void octnet_intrmod_callback(struct octeon_device *oct_dev,
668 u32 status,
669 void *ptr)
670{
671 struct oct_intrmod_cmd *cmd = ptr;
672 struct octeon_soft_command *sc = cmd->sc;
673
674 oct_dev = cmd->oct_dev;
675
676 if (status)
677 dev_err(&oct_dev->pci_dev->dev, "intrmod config failed. Status: %llx\n",
678 CVM_CAST64(status));
679 else
680 dev_info(&oct_dev->pci_dev->dev,
681 "Rx-Adaptive Interrupt moderation enabled:%llx\n",
682 oct_dev->intrmod.intrmod_enable);
683
684 octeon_free_soft_command(oct_dev, sc);
685}
686
687/* Configure interrupt moderation parameters */
688static int octnet_set_intrmod_cfg(void *oct, struct oct_intrmod_cfg *intr_cfg)
689{
690 struct octeon_soft_command *sc;
691 struct oct_intrmod_cmd *cmd;
692 struct oct_intrmod_cfg *cfg;
693 int retval;
694 struct octeon_device *oct_dev = (struct octeon_device *)oct;
695
696 /* Alloc soft command */
697 sc = (struct octeon_soft_command *)
698 octeon_alloc_soft_command(oct_dev,
699 sizeof(struct oct_intrmod_cfg),
700 0,
701 sizeof(struct oct_intrmod_cmd));
702
703 if (!sc)
704 return -ENOMEM;
705
706 cmd = (struct oct_intrmod_cmd *)sc->ctxptr;
707 cfg = (struct oct_intrmod_cfg *)sc->virtdptr;
708
709 memcpy(cfg, intr_cfg, sizeof(struct oct_intrmod_cfg));
710 octeon_swap_8B_data((u64 *)cfg, (sizeof(struct oct_intrmod_cfg)) / 8);
711 cmd->sc = sc;
712 cmd->cfg = cfg;
713 cmd->oct_dev = oct_dev;
714
715 octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
716 OPCODE_NIC_INTRMOD_CFG, 0, 0, 0);
717
718 sc->callback = octnet_intrmod_callback;
719 sc->callback_arg = cmd;
720 sc->wait_time = 1000;
721
722 retval = octeon_send_soft_command(oct_dev, sc);
ddc173a6 723 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 724 octeon_free_soft_command(oct_dev, sc);
725 return -EINVAL;
726 }
727
728 return 0;
729}
730
731/* Enable/Disable auto interrupt Moderation */
732static int oct_cfg_adaptive_intr(struct lio *lio, struct ethtool_coalesce
733 *intr_coal, int adaptive)
734{
735 int ret = 0;
736 struct octeon_device *oct = lio->oct_dev;
737 struct oct_intrmod_cfg *intrmod_cfg;
738
739 intrmod_cfg = &oct->intrmod;
740
741 if (adaptive) {
742 if (intr_coal->rate_sample_interval)
743 intrmod_cfg->intrmod_check_intrvl =
744 intr_coal->rate_sample_interval;
745 else
746 intrmod_cfg->intrmod_check_intrvl =
747 LIO_INTRMOD_CHECK_INTERVAL;
748
749 if (intr_coal->pkt_rate_high)
750 intrmod_cfg->intrmod_maxpkt_ratethr =
751 intr_coal->pkt_rate_high;
752 else
753 intrmod_cfg->intrmod_maxpkt_ratethr =
754 LIO_INTRMOD_MAXPKT_RATETHR;
755
756 if (intr_coal->pkt_rate_low)
757 intrmod_cfg->intrmod_minpkt_ratethr =
758 intr_coal->pkt_rate_low;
759 else
760 intrmod_cfg->intrmod_minpkt_ratethr =
761 LIO_INTRMOD_MINPKT_RATETHR;
762
763 if (intr_coal->rx_max_coalesced_frames_high)
764 intrmod_cfg->intrmod_maxcnt_trigger =
765 intr_coal->rx_max_coalesced_frames_high;
766 else
767 intrmod_cfg->intrmod_maxcnt_trigger =
768 LIO_INTRMOD_MAXCNT_TRIGGER;
769
770 if (intr_coal->rx_coalesce_usecs_high)
771 intrmod_cfg->intrmod_maxtmr_trigger =
772 intr_coal->rx_coalesce_usecs_high;
773 else
774 intrmod_cfg->intrmod_maxtmr_trigger =
775 LIO_INTRMOD_MAXTMR_TRIGGER;
776
777 if (intr_coal->rx_coalesce_usecs_low)
778 intrmod_cfg->intrmod_mintmr_trigger =
779 intr_coal->rx_coalesce_usecs_low;
780 else
781 intrmod_cfg->intrmod_mintmr_trigger =
782 LIO_INTRMOD_MINTMR_TRIGGER;
783
784 if (intr_coal->rx_max_coalesced_frames_low)
785 intrmod_cfg->intrmod_mincnt_trigger =
786 intr_coal->rx_max_coalesced_frames_low;
787 else
788 intrmod_cfg->intrmod_mincnt_trigger =
789 LIO_INTRMOD_MINCNT_TRIGGER;
790 }
791
792 intrmod_cfg->intrmod_enable = adaptive;
793 ret = octnet_set_intrmod_cfg(oct, intrmod_cfg);
794
795 return ret;
796}
797
798static int
799oct_cfg_rx_intrcnt(struct lio *lio, struct ethtool_coalesce *intr_coal)
800{
801 int ret;
802 struct octeon_device *oct = lio->oct_dev;
803 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip;
804 u32 rx_max_coalesced_frames;
805
806 if (!intr_coal->rx_max_coalesced_frames)
807 rx_max_coalesced_frames = CN6XXX_OQ_INTR_PKT;
808 else
809 rx_max_coalesced_frames = intr_coal->rx_max_coalesced_frames;
810
811 /* Disable adaptive interrupt modulation */
812 ret = oct_cfg_adaptive_intr(lio, intr_coal, 0);
813 if (ret)
814 return ret;
815
816 /* Config Cnt based interrupt values */
817 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_PKTS,
818 rx_max_coalesced_frames);
819 CFG_SET_OQ_INTR_PKT(cn6xxx->conf, rx_max_coalesced_frames);
820 return 0;
821}
822
823static int oct_cfg_rx_intrtime(struct lio *lio, struct ethtool_coalesce
824 *intr_coal)
825{
826 int ret;
827 struct octeon_device *oct = lio->oct_dev;
828 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip;
829 u32 time_threshold, rx_coalesce_usecs;
830
831 if (!intr_coal->rx_coalesce_usecs)
832 rx_coalesce_usecs = CN6XXX_OQ_INTR_TIME;
833 else
834 rx_coalesce_usecs = intr_coal->rx_coalesce_usecs;
835
836 /* Disable adaptive interrupt modulation */
837 ret = oct_cfg_adaptive_intr(lio, intr_coal, 0);
838 if (ret)
839 return ret;
840
841 /* Config Time based interrupt values */
842 time_threshold = lio_cn6xxx_get_oq_ticks(oct, rx_coalesce_usecs);
843 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_TIME, time_threshold);
844 CFG_SET_OQ_INTR_TIME(cn6xxx->conf, rx_coalesce_usecs);
845
846 return 0;
847}
848
849static int lio_set_intr_coalesce(struct net_device *netdev,
850 struct ethtool_coalesce *intr_coal)
851{
852 struct lio *lio = GET_LIO(netdev);
853 int ret;
854 struct octeon_device *oct = lio->oct_dev;
855 u32 j, q_no;
856
857 if ((intr_coal->tx_max_coalesced_frames >= CN6XXX_DB_MIN) &&
858 (intr_coal->tx_max_coalesced_frames <= CN6XXX_DB_MAX)) {
859 for (j = 0; j < lio->linfo.num_txpciq; j++) {
26236fa9 860 q_no = lio->linfo.txpciq[j].s.q_no;
f21fb3ed
RV		 861 oct->instr_queue[q_no]->fill_threshold =
862 intr_coal->tx_max_coalesced_frames;
863 }
864 } else {
865 dev_err(&oct->pci_dev->dev,
866 "LIQUIDIO: Invalid tx-frames:%d. Range is min:%d max:%d\n",
867 intr_coal->tx_max_coalesced_frames, CN6XXX_DB_MIN,
868 CN6XXX_DB_MAX);
869 return -EINVAL;
870 }
871
872 /* User requested adaptive-rx on */
873 if (intr_coal->use_adaptive_rx_coalesce) {
874 ret = oct_cfg_adaptive_intr(lio, intr_coal, 1);
875 if (ret)
876 goto ret_intrmod;
877 }
878
879 /* User requested adaptive-rx off and rx coalesce */
880 if ((intr_coal->rx_coalesce_usecs) &&
881 (!intr_coal->use_adaptive_rx_coalesce)) {
882 ret = oct_cfg_rx_intrtime(lio, intr_coal);
883 if (ret)
884 goto ret_intrmod;
885 }
886
887 /* User requested adaptive-rx off and rx coalesce */
888 if ((intr_coal->rx_max_coalesced_frames) &&
889 (!intr_coal->use_adaptive_rx_coalesce)) {
890 ret = oct_cfg_rx_intrcnt(lio, intr_coal);
891 if (ret)
892 goto ret_intrmod;
893 }
894
895 /* User requested adaptive-rx off, so use default coalesce params */
896 if ((!intr_coal->rx_max_coalesced_frames) &&
897 (!intr_coal->use_adaptive_rx_coalesce) &&
898 (!intr_coal->rx_coalesce_usecs)) {
899 dev_info(&oct->pci_dev->dev,
900 "Turning off adaptive-rx interrupt moderation\n");
901 dev_info(&oct->pci_dev->dev,
902 "Using RX Coalesce Default values rx_coalesce_usecs:%d rx_max_coalesced_frames:%d\n",
903 CN6XXX_OQ_INTR_TIME, CN6XXX_OQ_INTR_PKT);
904 ret = oct_cfg_rx_intrtime(lio, intr_coal);
905 if (ret)
906 goto ret_intrmod;
907
908 ret = oct_cfg_rx_intrcnt(lio, intr_coal);
909 if (ret)
910 goto ret_intrmod;
911 }
912
913 return 0;
914ret_intrmod:
915 return ret;
916}
917
918static int lio_get_ts_info(struct net_device *netdev,
919 struct ethtool_ts_info *info)
920{
921 struct lio *lio = GET_LIO(netdev);
922
923 info->so_timestamping =
924 SOF_TIMESTAMPING_TX_HARDWARE |
925 SOF_TIMESTAMPING_TX_SOFTWARE |
926 SOF_TIMESTAMPING_RX_HARDWARE |
927 SOF_TIMESTAMPING_RX_SOFTWARE |
928 SOF_TIMESTAMPING_SOFTWARE | SOF_TIMESTAMPING_RAW_HARDWARE;
929
930 if (lio->ptp_clock)
931 info->phc_index = ptp_clock_index(lio->ptp_clock);
932 else
933 info->phc_index = -1;
934
935 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
936
937 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
938 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
939 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
940 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
941
942 return 0;
943}
944
945static int lio_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
946{
947 struct lio *lio = GET_LIO(netdev);
948 struct octeon_device *oct = lio->oct_dev;
949 struct oct_link_info *linfo;
950 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 951 int ret = 0;
952
953 /* get the link info */
954 linfo = &lio->linfo;
955
956 if (ecmd->autoneg != AUTONEG_ENABLE && ecmd->autoneg != AUTONEG_DISABLE)
957 return -EINVAL;
958
959 if (ecmd->autoneg == AUTONEG_DISABLE && ((ecmd->speed != SPEED_100 &&
960 ecmd->speed != SPEED_10) ||
961 (ecmd->duplex != DUPLEX_HALF &&
962 ecmd->duplex != DUPLEX_FULL)))
963 return -EINVAL;
964
965 /* Ethtool Support is not provided for XAUI and RXAUI Interfaces
966 * as they operate at fixed Speed and Duplex settings
967 */
968 if (linfo->link.s.interface == INTERFACE_MODE_XAUI ||
969 linfo->link.s.interface == INTERFACE_MODE_RXAUI) {
970 dev_info(&oct->pci_dev->dev, "XAUI IFs settings cannot be modified.\n");
971 return -EINVAL;
972 }
973
974 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
975
976 nctrl.ncmd.u64 = 0;
977 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_SETTINGS;
0cece6c5 978 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 979 nctrl.wait_time = 1000;
980 nctrl.netpndev = (u64)netdev;
f21fb3ed
RV		 981 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
982
983 /* Passing the parameters sent by ethtool like Speed, Autoneg & Duplex
984 * to SE core application using ncmd.s.more & ncmd.s.param
985 */
986 if (ecmd->autoneg == AUTONEG_ENABLE) {
987 /* Autoneg ON */
988 nctrl.ncmd.s.more = OCTNIC_NCMD_PHY_ON |
989 OCTNIC_NCMD_AUTONEG_ON;
0cece6c5 990 nctrl.ncmd.s.param1 = ecmd->advertising;
f21fb3ed
RV		 991 } else {
992 /* Autoneg OFF */
993 nctrl.ncmd.s.more = OCTNIC_NCMD_PHY_ON;
994
0cece6c5 995 nctrl.ncmd.s.param2 = ecmd->duplex;
f21fb3ed 996
0cece6c5 997 nctrl.ncmd.s.param1 = ecmd->speed;
f21fb3ed
RV		 998 }
999
0cece6c5 1000 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 1001 if (ret < 0) {
1002 dev_err(&oct->pci_dev->dev, "Failed to set settings\n");
1003 return -1;
1004 }
1005
1006 return 0;
1007}
1008
1009static int lio_nway_reset(struct net_device *netdev)
1010{
1011 if (netif_running(netdev)) {
1012 struct ethtool_cmd ecmd;
1013
1014 memset(&ecmd, 0, sizeof(struct ethtool_cmd));
1015 ecmd.autoneg = 0;
1016 ecmd.speed = 0;
1017 ecmd.duplex = 0;
1018 lio_set_settings(netdev, &ecmd);
1019 }
1020 return 0;
1021}
1022
1023/* Return register dump len. */
1024static int lio_get_regs_len(struct net_device *dev)
1025{
1026 return OCT_ETHTOOL_REGDUMP_LEN;
1027}
1028
1029static int cn6xxx_read_csr_reg(char *s, struct octeon_device *oct)
1030{
1031 u32 reg;
1032 int i, len = 0;
1033
1034 /* PCI Window Registers */
1035
1036 len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n");
1037 reg = CN6XXX_WIN_WR_ADDR_LO;
1038 len += sprintf(s + len, "\n[%02x] (WIN_WR_ADDR_LO): %08x\n",
1039 CN6XXX_WIN_WR_ADDR_LO, octeon_read_csr(oct, reg));
1040 reg = CN6XXX_WIN_WR_ADDR_HI;
1041 len += sprintf(s + len, "[%02x] (WIN_WR_ADDR_HI): %08x\n",
1042 CN6XXX_WIN_WR_ADDR_HI, octeon_read_csr(oct, reg));
1043 reg = CN6XXX_WIN_RD_ADDR_LO;
1044 len += sprintf(s + len, "[%02x] (WIN_RD_ADDR_LO): %08x\n",
1045 CN6XXX_WIN_RD_ADDR_LO, octeon_read_csr(oct, reg));
1046 reg = CN6XXX_WIN_RD_ADDR_HI;
1047 len += sprintf(s + len, "[%02x] (WIN_RD_ADDR_HI): %08x\n",
1048 CN6XXX_WIN_RD_ADDR_HI, octeon_read_csr(oct, reg));
1049 reg = CN6XXX_WIN_WR_DATA_LO;
1050 len += sprintf(s + len, "[%02x] (WIN_WR_DATA_LO): %08x\n",
1051 CN6XXX_WIN_WR_DATA_LO, octeon_read_csr(oct, reg));
1052 reg = CN6XXX_WIN_WR_DATA_HI;
1053 len += sprintf(s + len, "[%02x] (WIN_WR_DATA_HI): %08x\n",
1054 CN6XXX_WIN_WR_DATA_HI, octeon_read_csr(oct, reg));
1055 len += sprintf(s + len, "[%02x] (WIN_WR_MASK_REG): %08x\n",
1056 CN6XXX_WIN_WR_MASK_REG,
1057 octeon_read_csr(oct, CN6XXX_WIN_WR_MASK_REG));
1058
1059 /* PCI Interrupt Register */
1060 len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 0): %08x\n",
1061 CN6XXX_SLI_INT_ENB64_PORT0, octeon_read_csr(oct,
1062 CN6XXX_SLI_INT_ENB64_PORT0));
1063 len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 1): %08x\n",
1064 CN6XXX_SLI_INT_ENB64_PORT1,
1065 octeon_read_csr(oct, CN6XXX_SLI_INT_ENB64_PORT1));
1066 len += sprintf(s + len, "[%x] (INT_SUM): %08x\n", CN6XXX_SLI_INT_SUM64,
1067 octeon_read_csr(oct, CN6XXX_SLI_INT_SUM64));
1068
1069 /* PCI Output queue registers */
1070 for (i = 0; i < oct->num_oqs; i++) {
1071 reg = CN6XXX_SLI_OQ_PKTS_SENT(i);
1072 len += sprintf(s + len, "\n[%x] (PKTS_SENT_%d): %08x\n",
1073 reg, i, octeon_read_csr(oct, reg));
1074 reg = CN6XXX_SLI_OQ_PKTS_CREDIT(i);
1075 len += sprintf(s + len, "[%x] (PKT_CREDITS_%d): %08x\n",
1076 reg, i, octeon_read_csr(oct, reg));
1077 }
1078 reg = CN6XXX_SLI_OQ_INT_LEVEL_PKTS;
1079 len += sprintf(s + len, "\n[%x] (PKTS_SENT_INT_LEVEL): %08x\n",
1080 reg, octeon_read_csr(oct, reg));
1081 reg = CN6XXX_SLI_OQ_INT_LEVEL_TIME;
1082 len += sprintf(s + len, "[%x] (PKTS_SENT_TIME): %08x\n",
1083 reg, octeon_read_csr(oct, reg));
1084
1085 /* PCI Input queue registers */
1086 for (i = 0; i <= 3; i++) {
1087 u32 reg;
1088
1089 reg = CN6XXX_SLI_IQ_DOORBELL(i);
1090 len += sprintf(s + len, "\n[%x] (INSTR_DOORBELL_%d): %08x\n",
1091 reg, i, octeon_read_csr(oct, reg));
1092 reg = CN6XXX_SLI_IQ_INSTR_COUNT(i);
1093 len += sprintf(s + len, "[%x] (INSTR_COUNT_%d): %08x\n",
1094 reg, i, octeon_read_csr(oct, reg));
1095 }
1096
1097 /* PCI DMA registers */
1098
1099 len += sprintf(s + len, "\n[%x] (DMA_CNT_0): %08x\n",
1100 CN6XXX_DMA_CNT(0),
1101 octeon_read_csr(oct, CN6XXX_DMA_CNT(0)));
1102 reg = CN6XXX_DMA_PKT_INT_LEVEL(0);
1103 len += sprintf(s + len, "[%x] (DMA_INT_LEV_0): %08x\n",
1104 CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg));
1105 reg = CN6XXX_DMA_TIME_INT_LEVEL(0);
1106 len += sprintf(s + len, "[%x] (DMA_TIME_0): %08x\n",
1107 CN6XXX_DMA_TIME_INT_LEVEL(0),
1108 octeon_read_csr(oct, reg));
1109
1110 len += sprintf(s + len, "\n[%x] (DMA_CNT_1): %08x\n",
1111 CN6XXX_DMA_CNT(1),
1112 octeon_read_csr(oct, CN6XXX_DMA_CNT(1)));
1113 reg = CN6XXX_DMA_PKT_INT_LEVEL(1);
1114 len += sprintf(s + len, "[%x] (DMA_INT_LEV_1): %08x\n",
1115 CN6XXX_DMA_PKT_INT_LEVEL(1),
1116 octeon_read_csr(oct, reg));
1117 reg = CN6XXX_DMA_PKT_INT_LEVEL(1);
1118 len += sprintf(s + len, "[%x] (DMA_TIME_1): %08x\n",
1119 CN6XXX_DMA_TIME_INT_LEVEL(1),
1120 octeon_read_csr(oct, reg));
1121
1122 /* PCI Index registers */
1123
1124 len += sprintf(s + len, "\n");
1125
1126 for (i = 0; i < 16; i++) {
1127 reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port));
1128 len += sprintf(s + len, "[%llx] (BAR1_INDEX_%02d): %08x\n",
1129 CN6XXX_BAR1_REG(i, oct->pcie_port), i, reg);
1130 }
1131
1132 return len;
1133}
1134
1135static int cn6xxx_read_config_reg(char *s, struct octeon_device *oct)
1136{
1137 u32 val;
1138 int i, len = 0;
1139
1140 /* PCI CONFIG Registers */
1141
1142 len += sprintf(s + len,
1143 "\n\t Octeon Config space Registers\n\n");
1144
1145 for (i = 0; i <= 13; i++) {
1146 pci_read_config_dword(oct->pci_dev, (i * 4), &val);
1147 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n",
1148 (i * 4), i, val);
1149 }
1150
1151 for (i = 30; i <= 34; i++) {
1152 pci_read_config_dword(oct->pci_dev, (i * 4), &val);
1153 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n",
1154 (i * 4), i, val);
1155 }
1156
1157 return len;
1158}
1159
1160/* Return register dump user app. */
1161static void lio_get_regs(struct net_device *dev,
1162 struct ethtool_regs *regs, void *regbuf)
1163{
1164 struct lio *lio = GET_LIO(dev);
1165 int len = 0;
1166 struct octeon_device *oct = lio->oct_dev;
1167
1168 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN);
1169 regs->version = OCT_ETHTOOL_REGSVER;
1170
1171 switch (oct->chip_id) {
1172 /* case OCTEON_CN73XX: Todo */
1173 case OCTEON_CN68XX:
1174 case OCTEON_CN66XX:
1175 len += cn6xxx_read_csr_reg(regbuf + len, oct);
1176 len += cn6xxx_read_config_reg(regbuf + len, oct);
1177 break;
1178 default:
1179 dev_err(&oct->pci_dev->dev, "%s Unknown chipid: %d\n",
1180 __func__, oct->chip_id);
1181 }
1182}
1183
1184static const struct ethtool_ops lio_ethtool_ops = {
1185 .get_settings = lio_get_settings,
1186 .get_link = ethtool_op_get_link,
1187 .get_drvinfo = lio_get_drvinfo,
1188 .get_ringparam = lio_ethtool_get_ringparam,
1189 .get_channels = lio_ethtool_get_channels,
1190 .set_phys_id = lio_set_phys_id,
1191 .get_eeprom_len = lio_get_eeprom_len,
1192 .get_eeprom = lio_get_eeprom,
1193 .get_strings = lio_get_strings,
1194 .get_ethtool_stats = lio_get_ethtool_stats,
1195 .get_pauseparam = lio_get_pauseparam,
1196 .get_regs_len = lio_get_regs_len,
1197 .get_regs = lio_get_regs,
1198 .get_msglevel = lio_get_msglevel,
1199 .set_msglevel = lio_set_msglevel,
1200 .get_sset_count = lio_get_sset_count,
1201 .nway_reset = lio_nway_reset,
1202 .set_settings = lio_set_settings,
1203 .get_coalesce = lio_get_intr_coalesce,
1204 .set_coalesce = lio_set_intr_coalesce,
1205 .get_ts_info = lio_get_ts_info,
1206};
1207
1208void liquidio_set_ethtool_ops(struct net_device *netdev)
1209{
1210 netdev->ethtool_ops = &lio_ethtool_ops;
1211}
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