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liquidio: moved console_bitmask module param to lio_main.c
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / cavium / liquidio / lio_main.c
CommitLineData
f21fb3ed 1/**********************************************************************
50579d3d
RV		 2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
e3bfc6e7 18#include <linux/module.h>
282ccf6e 19#include <linux/interrupt.h>
f21fb3ed 20#include <linux/pci.h>
f21fb3ed 21#include <linux/firmware.h>
01fb237a 22#include <net/vxlan.h>
9ff1a9ba 23#include <linux/kthread.h>
f21fb3ed
RV		 24#include "liquidio_common.h"
25#include "octeon_droq.h"
26#include "octeon_iq.h"
27#include "response_manager.h"
28#include "octeon_device.h"
29#include "octeon_nic.h"
30#include "octeon_main.h"
31#include "octeon_network.h"
32#include "cn66xx_regs.h"
33#include "cn66xx_device.h"
f21fb3ed 34#include "cn68xx_device.h"
72c00912 35#include "cn23xx_pf_device.h"
f21fb3ed
RV		 36#include "liquidio_image.h"
37
38MODULE_AUTHOR("Cavium Networks, <support@cavium.com>");
39MODULE_DESCRIPTION("Cavium LiquidIO Intelligent Server Adapter Driver");
40MODULE_LICENSE("GPL");
41MODULE_VERSION(LIQUIDIO_VERSION);
42MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210SV_NAME LIO_FW_NAME_SUFFIX);
43MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210NV_NAME LIO_FW_NAME_SUFFIX);
44MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_410NV_NAME LIO_FW_NAME_SUFFIX);
c865cdf1 45MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_23XX_NAME LIO_FW_NAME_SUFFIX);
f21fb3ed
RV		 46
47static int ddr_timeout = 10000;
48module_param(ddr_timeout, int, 0644);
49MODULE_PARM_DESC(ddr_timeout,
50 "Number of milliseconds to wait for DDR initialization. 0 waits for ddr_timeout to be set to non-zero value before starting to check");
51
f21fb3ed
RV		 52#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
53
54static int debug = -1;
55module_param(debug, int, 0644);
56MODULE_PARM_DESC(debug, "NETIF_MSG debug bits");
57
58static char fw_type[LIO_MAX_FW_TYPE_LEN];
59module_param_string(fw_type, fw_type, sizeof(fw_type), 0000);
60MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded. Default \"nic\"");
61
2470f3a2
IB		 62static u32 console_bitmask;
63module_param(console_bitmask, int, 0644);
64MODULE_PARM_DESC(console_bitmask,
65 "Bitmask indicating which consoles have debug output redirected to syslog.");
66
67/**
68 * \brief determines if a given console has debug enabled.
69 * @param console console to check
70 * @returns 1 = enabled. 0 otherwise
71 */
72int octeon_console_debug_enabled(u32 console)
73{
74 return (console_bitmask >> (console)) & 0x1;
75}
76
a5b37888
RV		 77static int ptp_enable = 1;
78
f21fb3ed
RV		 79/* Polling interval for determining when NIC application is alive */
80#define LIQUIDIO_STARTER_POLL_INTERVAL_MS 100
81
82/* runtime link query interval */
83#define LIQUIDIO_LINK_QUERY_INTERVAL_MS 1000
84
85struct liquidio_if_cfg_context {
86 int octeon_id;
87
88 wait_queue_head_t wc;
89
90 int cond;
91};
92
93struct liquidio_if_cfg_resp {
94 u64 rh;
95 struct liquidio_if_cfg_info cfg_info;
96 u64 status;
97};
98
afdf841f
RV		 99struct liquidio_rx_ctl_context {
100 int octeon_id;
101
102 wait_queue_head_t wc;
103
104 int cond;
105};
106
f21fb3ed
RV		 107struct oct_link_status_resp {
108 u64 rh;
109 struct oct_link_info link_info;
110 u64 status;
111};
112
113struct oct_timestamp_resp {
114 u64 rh;
115 u64 timestamp;
116 u64 status;
117};
118
119#define OCT_TIMESTAMP_RESP_SIZE (sizeof(struct oct_timestamp_resp))
120
121union tx_info {
122 u64 u64;
123 struct {
124#ifdef __BIG_ENDIAN_BITFIELD
125 u16 gso_size;
126 u16 gso_segs;
127 u32 reserved;
128#else
129 u32 reserved;
130 u16 gso_segs;
131 u16 gso_size;
132#endif
133 } s;
134};
135
136/** Octeon device properties to be used by the NIC module.
137 * Each octeon device in the system will be represented
138 * by this structure in the NIC module.
139 */
140
141#define OCTNIC_MAX_SG (MAX_SKB_FRAGS)
142
143#define OCTNIC_GSO_MAX_HEADER_SIZE 128
72c00912
RV		 144#define OCTNIC_GSO_MAX_SIZE \
145 (CN23XX_DEFAULT_INPUT_JABBER - OCTNIC_GSO_MAX_HEADER_SIZE)
f21fb3ed
RV		 146
147/** Structure of a node in list of gather components maintained by
148 * NIC driver for each network device.
149 */
150struct octnic_gather {
151 /** List manipulation. Next and prev pointers. */
152 struct list_head list;
153
154 /** Size of the gather component at sg in bytes. */
155 int sg_size;
156
157 /** Number of bytes that sg was adjusted to make it 8B-aligned. */
158 int adjust;
159
160 /** Gather component that can accommodate max sized fragment list
161 * received from the IP layer.
162 */
163 struct octeon_sg_entry *sg;
fcd2b5e3 164
67e303e0 165 dma_addr_t sg_dma_ptr;
f21fb3ed
RV		 166};
167
f21fb3ed
RV		 168struct handshake {
169 struct completion init;
170 struct completion started;
171 struct pci_dev *pci_dev;
172 int init_ok;
173 int started_ok;
174};
175
176struct octeon_device_priv {
177 /** Tasklet structures for this device. */
178 struct tasklet_struct droq_tasklet;
179 unsigned long napi_mask;
180};
181
ca6139ff
RV		 182#ifdef CONFIG_PCI_IOV
183static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs);
184#endif
185
f21fb3ed 186static int octeon_device_init(struct octeon_device *);
32581245 187static int liquidio_stop(struct net_device *netdev);
f21fb3ed
RV		 188static void liquidio_remove(struct pci_dev *pdev);
189static int liquidio_probe(struct pci_dev *pdev,
190 const struct pci_device_id *ent);
bb54be58
FM		 191static int liquidio_set_vf_link_state(struct net_device *netdev, int vfidx,
192 int linkstate);
f21fb3ed
RV		 193
194static struct handshake handshake[MAX_OCTEON_DEVICES];
195static struct completion first_stage;
196
5b173cf9 197static void octeon_droq_bh(unsigned long pdev)
f21fb3ed
RV		 198{
199 int q_no;
200 int reschedule = 0;
201 struct octeon_device *oct = (struct octeon_device *)pdev;
202 struct octeon_device_priv *oct_priv =
203 (struct octeon_device_priv *)oct->priv;
204
63da8404 205 for (q_no = 0; q_no < MAX_OCTEON_OUTPUT_QUEUES(oct); q_no++) {
763185a3 206 if (!(oct->io_qmask.oq & BIT_ULL(q_no)))
f21fb3ed
RV		 207 continue;
208 reschedule |= octeon_droq_process_packets(oct, oct->droq[q_no],
209 MAX_PACKET_BUDGET);
cd8b1eb4 210 lio_enable_irq(oct->droq[q_no], NULL);
5b07aee1
RV		 211
212 if (OCTEON_CN23XX_PF(oct) && oct->msix_on) {
213 /* set time and cnt interrupt thresholds for this DROQ
214 * for NAPI
215 */
216 int adjusted_q_no = q_no + oct->sriov_info.pf_srn;
217
218 octeon_write_csr64(
219 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(adjusted_q_no),
220 0x5700000040ULL);
221 octeon_write_csr64(
222 oct, CN23XX_SLI_OQ_PKTS_SENT(adjusted_q_no), 0);
223 }
f21fb3ed
RV		 224 }
225
226 if (reschedule)
227 tasklet_schedule(&oct_priv->droq_tasklet);
228}
229
5b173cf9 230static int lio_wait_for_oq_pkts(struct octeon_device *oct)
f21fb3ed
RV		 231{
232 struct octeon_device_priv *oct_priv =
233 (struct octeon_device_priv *)oct->priv;
234 int retry = 100, pkt_cnt = 0, pending_pkts = 0;
235 int i;
236
237 do {
238 pending_pkts = 0;
239
63da8404 240 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
763185a3 241 if (!(oct->io_qmask.oq & BIT_ULL(i)))
f21fb3ed 242 continue;
a7d5a3dc 243 pkt_cnt += octeon_droq_check_hw_for_pkts(oct->droq[i]);
f21fb3ed
RV		 244 }
245 if (pkt_cnt > 0) {
246 pending_pkts += pkt_cnt;
247 tasklet_schedule(&oct_priv->droq_tasklet);
248 }
249 pkt_cnt = 0;
250 schedule_timeout_uninterruptible(1);
251
252 } while (retry-- && pending_pkts);
253
254 return pkt_cnt;
255}
256
f21fb3ed
RV		 257/**
258 * \brief Forces all IO queues off on a given device
259 * @param oct Pointer to Octeon device
260 */
261static void force_io_queues_off(struct octeon_device *oct)
262{
263 if ((oct->chip_id == OCTEON_CN66XX) ||
264 (oct->chip_id == OCTEON_CN68XX)) {
265 /* Reset the Enable bits for Input Queues. */
266 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
267
268 /* Reset the Enable bits for Output Queues. */
269 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
270 }
271}
272
273/**
274 * \brief wait for all pending requests to complete
275 * @param oct Pointer to Octeon device
276 *
277 * Called during shutdown sequence
278 */
279static int wait_for_pending_requests(struct octeon_device *oct)
280{
281 int i, pcount = 0;
282
283 for (i = 0; i < 100; i++) {
284 pcount =
285 atomic_read(&oct->response_list
286 [OCTEON_ORDERED_SC_LIST].pending_req_count);
287 if (pcount)
288 schedule_timeout_uninterruptible(HZ / 10);
9a96bde4 289 else
f21fb3ed
RV		 290 break;
291 }
292
293 if (pcount)
294 return 1;
295
296 return 0;
297}
298
299/**
300 * \brief Cause device to go quiet so it can be safely removed/reset/etc
301 * @param oct Pointer to Octeon device
302 */
303static inline void pcierror_quiesce_device(struct octeon_device *oct)
304{
305 int i;
306
307 /* Disable the input and output queues now. No more packets will
308 * arrive from Octeon, but we should wait for all packet processing
309 * to finish.
310 */
311 force_io_queues_off(oct);
312
313 /* To allow for in-flight requests */
314 schedule_timeout_uninterruptible(100);
315
316 if (wait_for_pending_requests(oct))
317 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
318
319 /* Force all requests waiting to be fetched by OCTEON to complete. */
63da8404 320 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
f21fb3ed
RV		 321 struct octeon_instr_queue *iq;
322
763185a3 323 if (!(oct->io_qmask.iq & BIT_ULL(i)))
f21fb3ed
RV		 324 continue;
325 iq = oct->instr_queue[i];
326
327 if (atomic_read(&iq->instr_pending)) {
328 spin_lock_bh(&iq->lock);
329 iq->fill_cnt = 0;
330 iq->octeon_read_index = iq->host_write_index;
331 iq->stats.instr_processed +=
332 atomic_read(&iq->instr_pending);
9a96bde4 333 lio_process_iq_request_list(oct, iq, 0);
f21fb3ed
RV		 334 spin_unlock_bh(&iq->lock);
335 }
336 }
337
338 /* Force all pending ordered list requests to time out. */
339 lio_process_ordered_list(oct, 1);
340
341 /* We do not need to wait for output queue packets to be processed. */
342}
343
344/**
345 * \brief Cleanup PCI AER uncorrectable error status
346 * @param dev Pointer to PCI device
347 */
348static void cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
349{
350 int pos = 0x100;
351 u32 status, mask;
352
353 pr_info("%s :\n", __func__);
354
355 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
356 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
357 if (dev->error_state == pci_channel_io_normal)
358 status &= ~mask; /* Clear corresponding nonfatal bits */
359 else
360 status &= mask; /* Clear corresponding fatal bits */
361 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
362}
363
364/**
365 * \brief Stop all PCI IO to a given device
366 * @param dev Pointer to Octeon device
367 */
368static void stop_pci_io(struct octeon_device *oct)
369{
370 /* No more instructions will be forwarded. */
371 atomic_set(&oct->status, OCT_DEV_IN_RESET);
372
373 pci_disable_device(oct->pci_dev);
374
375 /* Disable interrupts */
5b07aee1 376 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
f21fb3ed
RV		 377
378 pcierror_quiesce_device(oct);
379
380 /* Release the interrupt line */
381 free_irq(oct->pci_dev->irq, oct);
382
383 if (oct->flags & LIO_FLAG_MSI_ENABLED)
384 pci_disable_msi(oct->pci_dev);
385
386 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
387 lio_get_state_string(&oct->status));
388
f21fb3ed
RV		 389 /* making it a common function for all OCTEON models */
390 cleanup_aer_uncorrect_error_status(oct->pci_dev);
391}
392
393/**
394 * \brief called when PCI error is detected
395 * @param pdev Pointer to PCI device
396 * @param state The current pci connection state
397 *
398 * This function is called after a PCI bus error affecting
399 * this device has been detected.
400 */
401static pci_ers_result_t liquidio_pcie_error_detected(struct pci_dev *pdev,
402 pci_channel_state_t state)
403{
404 struct octeon_device *oct = pci_get_drvdata(pdev);
405
406 /* Non-correctable Non-fatal errors */
407 if (state == pci_channel_io_normal) {
408 dev_err(&oct->pci_dev->dev, "Non-correctable non-fatal error reported:\n");
409 cleanup_aer_uncorrect_error_status(oct->pci_dev);
410 return PCI_ERS_RESULT_CAN_RECOVER;
411 }
412
413 /* Non-correctable Fatal errors */
414 dev_err(&oct->pci_dev->dev, "Non-correctable FATAL reported by PCI AER driver\n");
415 stop_pci_io(oct);
416
417 /* Always return a DISCONNECT. There is no support for recovery but only
418 * for a clean shutdown.
419 */
420 return PCI_ERS_RESULT_DISCONNECT;
421}
422
423/**
424 * \brief mmio handler
425 * @param pdev Pointer to PCI device
426 */
a7d5a3dc
RV		 427static pci_ers_result_t liquidio_pcie_mmio_enabled(
428 struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 429{
430 /* We should never hit this since we never ask for a reset for a Fatal
431 * Error. We always return DISCONNECT in io_error above.
432 * But play safe and return RECOVERED for now.
433 */
434 return PCI_ERS_RESULT_RECOVERED;
435}
436
437/**
438 * \brief called after the pci bus has been reset.
439 * @param pdev Pointer to PCI device
440 *
441 * Restart the card from scratch, as if from a cold-boot. Implementation
442 * resembles the first-half of the octeon_resume routine.
443 */
a7d5a3dc
RV		 444static pci_ers_result_t liquidio_pcie_slot_reset(
445 struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 446{
447 /* We should never hit this since we never ask for a reset for a Fatal
448 * Error. We always return DISCONNECT in io_error above.
449 * But play safe and return RECOVERED for now.
450 */
451 return PCI_ERS_RESULT_RECOVERED;
452}
453
454/**
455 * \brief called when traffic can start flowing again.
456 * @param pdev Pointer to PCI device
457 *
458 * This callback is called when the error recovery driver tells us that
459 * its OK to resume normal operation. Implementation resembles the
460 * second-half of the octeon_resume routine.
461 */
a7d5a3dc 462static void liquidio_pcie_resume(struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 463{
464 /* Nothing to be done here. */
465}
466
467#ifdef CONFIG_PM
468/**
469 * \brief called when suspending
470 * @param pdev Pointer to PCI device
471 * @param state state to suspend to
472 */
a7d5a3dc
RV		 473static int liquidio_suspend(struct pci_dev *pdev __attribute__((unused)),
474 pm_message_t state __attribute__((unused)))
f21fb3ed
RV		 475{
476 return 0;
477}
478
479/**
480 * \brief called when resuming
481 * @param pdev Pointer to PCI device
482 */
a7d5a3dc 483static int liquidio_resume(struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 484{
485 return 0;
486}
487#endif
488
489/* For PCI-E Advanced Error Recovery (AER) Interface */
166e2362 490static const struct pci_error_handlers liquidio_err_handler = {
f21fb3ed
RV		 491 .error_detected = liquidio_pcie_error_detected,
492 .mmio_enabled = liquidio_pcie_mmio_enabled,
493 .slot_reset = liquidio_pcie_slot_reset,
494 .resume = liquidio_pcie_resume,
495};
496
497static const struct pci_device_id liquidio_pci_tbl[] = {
498 { /* 68xx */
499 PCI_VENDOR_ID_CAVIUM, 0x91, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
500 },
501 { /* 66xx */
502 PCI_VENDOR_ID_CAVIUM, 0x92, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
503 },
e86b1ab6
RV		 504 { /* 23xx pf */
505 PCI_VENDOR_ID_CAVIUM, 0x9702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
506 },
f21fb3ed
RV		 507 {
508 0, 0, 0, 0, 0, 0, 0
509 }
510};
511MODULE_DEVICE_TABLE(pci, liquidio_pci_tbl);
512
513static struct pci_driver liquidio_pci_driver = {
514 .name = "LiquidIO",
515 .id_table = liquidio_pci_tbl,
516 .probe = liquidio_probe,
517 .remove = liquidio_remove,
518 .err_handler = &liquidio_err_handler, /* For AER */
519
520#ifdef CONFIG_PM
521 .suspend = liquidio_suspend,
522 .resume = liquidio_resume,
523#endif
ca6139ff
RV		 524#ifdef CONFIG_PCI_IOV
525 .sriov_configure = liquidio_enable_sriov,
526#endif
f21fb3ed
RV		 527};
528
529/**
530 * \brief register PCI driver
531 */
532static int liquidio_init_pci(void)
533{
534 return pci_register_driver(&liquidio_pci_driver);
535}
536
537/**
538 * \brief unregister PCI driver
539 */
540static void liquidio_deinit_pci(void)
541{
542 pci_unregister_driver(&liquidio_pci_driver);
543}
544
f21fb3ed
RV		 545/**
546 * \brief Stop Tx queues
547 * @param netdev network device
548 */
549static inline void txqs_stop(struct net_device *netdev)
550{
551 if (netif_is_multiqueue(netdev)) {
552 int i;
553
554 for (i = 0; i < netdev->num_tx_queues; i++)
555 netif_stop_subqueue(netdev, i);
556 } else {
557 netif_stop_queue(netdev);
558 }
559}
560
561/**
562 * \brief Start Tx queues
563 * @param netdev network device
564 */
565static inline void txqs_start(struct net_device *netdev)
566{
567 if (netif_is_multiqueue(netdev)) {
568 int i;
569
570 for (i = 0; i < netdev->num_tx_queues; i++)
571 netif_start_subqueue(netdev, i);
572 } else {
573 netif_start_queue(netdev);
574 }
575}
576
577/**
578 * \brief Wake Tx queues
579 * @param netdev network device
580 */
581static inline void txqs_wake(struct net_device *netdev)
582{
1f164717
RV		 583 struct lio *lio = GET_LIO(netdev);
584
f21fb3ed
RV		 585 if (netif_is_multiqueue(netdev)) {
586 int i;
587
1f164717
RV		 588 for (i = 0; i < netdev->num_tx_queues; i++) {
589 int qno = lio->linfo.txpciq[i %
590 (lio->linfo.num_txpciq)].s.q_no;
591
592 if (__netif_subqueue_stopped(netdev, i)) {
593 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, qno,
594 tx_restart, 1);
26236fa9 595 netif_wake_subqueue(netdev, i);
1f164717
RV		 596 }
597 }
f21fb3ed 598 } else {
1f164717
RV		 599 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, lio->txq,
600 tx_restart, 1);
f21fb3ed
RV		 601 netif_wake_queue(netdev);
602 }
603}
604
605/**
606 * \brief Stop Tx queue
607 * @param netdev network device
608 */
609static void stop_txq(struct net_device *netdev)
610{
611 txqs_stop(netdev);
612}
613
614/**
615 * \brief Start Tx queue
616 * @param netdev network device
617 */
618static void start_txq(struct net_device *netdev)
619{
620 struct lio *lio = GET_LIO(netdev);
621
0cece6c5 622 if (lio->linfo.link.s.link_up) {
f21fb3ed
RV		 623 txqs_start(netdev);
624 return;
625 }
626}
627
628/**
629 * \brief Wake a queue
630 * @param netdev network device
631 * @param q which queue to wake
632 */
633static inline void wake_q(struct net_device *netdev, int q)
634{
635 if (netif_is_multiqueue(netdev))
636 netif_wake_subqueue(netdev, q);
637 else
638 netif_wake_queue(netdev);
639}
640
641/**
642 * \brief Stop a queue
643 * @param netdev network device
644 * @param q which queue to stop
645 */
646static inline void stop_q(struct net_device *netdev, int q)
647{
648 if (netif_is_multiqueue(netdev))
649 netif_stop_subqueue(netdev, q);
650 else
651 netif_stop_queue(netdev);
652}
653
654/**
655 * \brief Check Tx queue status, and take appropriate action
656 * @param lio per-network private data
657 * @returns 0 if full, number of queues woken up otherwise
658 */
659static inline int check_txq_status(struct lio *lio)
660{
661 int ret_val = 0;
662
663 if (netif_is_multiqueue(lio->netdev)) {
664 int numqs = lio->netdev->num_tx_queues;
665 int q, iq = 0;
666
667 /* check each sub-queue state */
668 for (q = 0; q < numqs; q++) {
26236fa9
RV		 669 iq = lio->linfo.txpciq[q %
670 (lio->linfo.num_txpciq)].s.q_no;
f21fb3ed
RV		 671 if (octnet_iq_is_full(lio->oct_dev, iq))
672 continue;
26236fa9
RV		 673 if (__netif_subqueue_stopped(lio->netdev, q)) {
674 wake_q(lio->netdev, q);
1f164717
RV		 675 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq,
676 tx_restart, 1);
26236fa9
RV		 677 ret_val++;
678 }
f21fb3ed
RV		 679 }
680 } else {
681 if (octnet_iq_is_full(lio->oct_dev, lio->txq))
682 return 0;
683 wake_q(lio->netdev, lio->txq);
1f164717
RV		 684 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, lio->txq,
685 tx_restart, 1);
f21fb3ed
RV		 686 ret_val = 1;
687 }
688 return ret_val;
689}
690
691/**
692 * Remove the node at the head of the list. The list would be empty at
693 * the end of this call if there are no more nodes in the list.
694 */
695static inline struct list_head *list_delete_head(struct list_head *root)
696{
697 struct list_head *node;
698
699 if ((root->prev == root) && (root->next == root))
700 node = NULL;
701 else
702 node = root->next;
703
704 if (node)
705 list_del(node);
706
707 return node;
708}
709
710/**
fcd2b5e3 711 * \brief Delete gather lists
f21fb3ed
RV		 712 * @param lio per-network private data
713 */
fcd2b5e3 714static void delete_glists(struct lio *lio)
f21fb3ed
RV		 715{
716 struct octnic_gather *g;
fcd2b5e3 717 int i;
f21fb3ed 718
67e303e0
VB		 719 kfree(lio->glist_lock);
720 lio->glist_lock = NULL;
721
fcd2b5e3
RV		 722 if (!lio->glist)
723 return;
724
725 for (i = 0; i < lio->linfo.num_txpciq; i++) {
726 do {
727 g = (struct octnic_gather *)
728 list_delete_head(&lio->glist[i]);
67e303e0 729 if (g)
fcd2b5e3 730 kfree(g);
fcd2b5e3 731 } while (g);
67e303e0 732
58ad3198
FM		 733 if (lio->glists_virt_base && lio->glists_virt_base[i] &&
734 lio->glists_dma_base && lio->glists_dma_base[i]) {
67e303e0
VB		 735 lio_dma_free(lio->oct_dev,
736 lio->glist_entry_size * lio->tx_qsize,
737 lio->glists_virt_base[i],
738 lio->glists_dma_base[i]);
739 }
fcd2b5e3
RV		 740 }
741
67e303e0
VB		 742 kfree(lio->glists_virt_base);
743 lio->glists_virt_base = NULL;
744
745 kfree(lio->glists_dma_base);
746 lio->glists_dma_base = NULL;
747
748 kfree(lio->glist);
749 lio->glist = NULL;
f21fb3ed
RV		 750}
751
752/**
fcd2b5e3 753 * \brief Setup gather lists
f21fb3ed
RV		 754 * @param lio per-network private data
755 */
fcd2b5e3 756static int setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs)
f21fb3ed 757{
fcd2b5e3 758 int i, j;
f21fb3ed
RV		 759 struct octnic_gather *g;
760
fcd2b5e3
RV		 761 lio->glist_lock = kcalloc(num_iqs, sizeof(*lio->glist_lock),
762 GFP_KERNEL);
763 if (!lio->glist_lock)
67e303e0 764 return -ENOMEM;
f21fb3ed 765
fcd2b5e3
RV		 766 lio->glist = kcalloc(num_iqs, sizeof(*lio->glist),
767 GFP_KERNEL);
768 if (!lio->glist) {
67e303e0
VB		 769 kfree(lio->glist_lock);
770 lio->glist_lock = NULL;
771 return -ENOMEM;
772 }
773
774 lio->glist_entry_size =
775 ROUNDUP8((ROUNDUP4(OCTNIC_MAX_SG) >> 2) * OCT_SG_ENTRY_SIZE);
776
777 /* allocate memory to store virtual and dma base address of
778 * per glist consistent memory
779 */
780 lio->glists_virt_base = kcalloc(num_iqs, sizeof(*lio->glists_virt_base),
781 GFP_KERNEL);
782 lio->glists_dma_base = kcalloc(num_iqs, sizeof(*lio->glists_dma_base),
783 GFP_KERNEL);
784
785 if (!lio->glists_virt_base || !lio->glists_dma_base) {
786 delete_glists(lio);
787 return -ENOMEM;
fcd2b5e3 788 }
f21fb3ed 789
fcd2b5e3 790 for (i = 0; i < num_iqs; i++) {
b3ca9af0 791 int numa_node = dev_to_node(&oct->pci_dev->dev);
f21fb3ed 792
fcd2b5e3
RV		 793 spin_lock_init(&lio->glist_lock[i]);
794
795 INIT_LIST_HEAD(&lio->glist[i]);
796
67e303e0
VB		 797 lio->glists_virt_base[i] =
798 lio_dma_alloc(oct,
799 lio->glist_entry_size * lio->tx_qsize,
800 &lio->glists_dma_base[i]);
801
802 if (!lio->glists_virt_base[i]) {
803 delete_glists(lio);
804 return -ENOMEM;
805 }
806
fcd2b5e3
RV		 807 for (j = 0; j < lio->tx_qsize; j++) {
808 g = kzalloc_node(sizeof(*g), GFP_KERNEL,
809 numa_node);
810 if (!g)
811 g = kzalloc(sizeof(*g), GFP_KERNEL);
812 if (!g)
813 break;
814
67e303e0
VB		 815 g->sg = lio->glists_virt_base[i] +
816 (j * lio->glist_entry_size);
fcd2b5e3 817
67e303e0
VB		 818 g->sg_dma_ptr = lio->glists_dma_base[i] +
819 (j * lio->glist_entry_size);
fcd2b5e3
RV		 820
821 list_add_tail(&g->list, &lio->glist[i]);
f21fb3ed
RV		 822 }
823
fcd2b5e3
RV		 824 if (j != lio->tx_qsize) {
825 delete_glists(lio);
67e303e0 826 return -ENOMEM;
f21fb3ed 827 }
f21fb3ed
RV		 828 }
829
fcd2b5e3 830 return 0;
f21fb3ed
RV		 831}
832
833/**
834 * \brief Print link information
835 * @param netdev network device
836 */
837static void print_link_info(struct net_device *netdev)
838{
839 struct lio *lio = GET_LIO(netdev);
840
841 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED) {
842 struct oct_link_info *linfo = &lio->linfo;
843
0cece6c5 844 if (linfo->link.s.link_up) {
f21fb3ed
RV		 845 netif_info(lio, link, lio->netdev, "%d Mbps %s Duplex UP\n",
846 linfo->link.s.speed,
847 (linfo->link.s.duplex) ? "Full" : "Half");
848 } else {
849 netif_info(lio, link, lio->netdev, "Link Down\n");
850 }
851 }
852}
853
7b6b6c95
RV		 854/**
855 * \brief Routine to notify MTU change
856 * @param work work_struct data structure
857 */
858static void octnet_link_status_change(struct work_struct *work)
859{
860 struct cavium_wk *wk = (struct cavium_wk *)work;
861 struct lio *lio = (struct lio *)wk->ctxptr;
862
863 rtnl_lock();
864 call_netdevice_notifiers(NETDEV_CHANGEMTU, lio->netdev);
865 rtnl_unlock();
866}
867
868/**
869 * \brief Sets up the mtu status change work
870 * @param netdev network device
871 */
872static inline int setup_link_status_change_wq(struct net_device *netdev)
873{
874 struct lio *lio = GET_LIO(netdev);
875 struct octeon_device *oct = lio->oct_dev;
876
877 lio->link_status_wq.wq = alloc_workqueue("link-status",
878 WQ_MEM_RECLAIM, 0);
879 if (!lio->link_status_wq.wq) {
880 dev_err(&oct->pci_dev->dev, "unable to create cavium link status wq\n");
881 return -1;
882 }
883 INIT_DELAYED_WORK(&lio->link_status_wq.wk.work,
884 octnet_link_status_change);
885 lio->link_status_wq.wk.ctxptr = lio;
886
887 return 0;
888}
889
890static inline void cleanup_link_status_change_wq(struct net_device *netdev)
891{
892 struct lio *lio = GET_LIO(netdev);
893
894 if (lio->link_status_wq.wq) {
895 cancel_delayed_work_sync(&lio->link_status_wq.wk.work);
896 destroy_workqueue(lio->link_status_wq.wq);
897 }
898}
899
f21fb3ed
RV		 900/**
901 * \brief Update link status
902 * @param netdev network device
903 * @param ls link status structure
904 *
905 * Called on receipt of a link status response from the core application to
906 * update each interface's link status.
907 */
908static inline void update_link_status(struct net_device *netdev,
909 union oct_link_status *ls)
910{
911 struct lio *lio = GET_LIO(netdev);
0cece6c5 912 int changed = (lio->linfo.link.u64 != ls->u64);
f21fb3ed 913
0cece6c5 914 lio->linfo.link.u64 = ls->u64;
f21fb3ed 915
0cece6c5 916 if ((lio->intf_open) && (changed)) {
f21fb3ed 917 print_link_info(netdev);
0cece6c5 918 lio->link_changes++;
f21fb3ed 919
0cece6c5 920 if (lio->linfo.link.s.link_up) {
f21fb3ed 921 netif_carrier_on(netdev);
f21fb3ed
RV		 922 txqs_wake(netdev);
923 } else {
924 netif_carrier_off(netdev);
925 stop_txq(netdev);
926 }
927 }
928}
929
9a96bde4
RV		 930/* Runs in interrupt context. */
931static void update_txq_status(struct octeon_device *oct, int iq_num)
932{
933 struct net_device *netdev;
934 struct lio *lio;
935 struct octeon_instr_queue *iq = oct->instr_queue[iq_num];
936
9a96bde4
RV		 937 netdev = oct->props[iq->ifidx].netdev;
938
939 /* This is needed because the first IQ does not have
940 * a netdev associated with it.
941 */
942 if (!netdev)
943 return;
944
945 lio = GET_LIO(netdev);
946 if (netif_is_multiqueue(netdev)) {
947 if (__netif_subqueue_stopped(netdev, iq->q_index) &&
948 lio->linfo.link.s.link_up &&
949 (!octnet_iq_is_full(oct, iq_num))) {
1f164717
RV		 950 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq_num,
951 tx_restart, 1);
9a96bde4 952 netif_wake_subqueue(netdev, iq->q_index);
9a96bde4 953 }
6069f3fb
VB		 954 } else if (netif_queue_stopped(netdev) &&
955 lio->linfo.link.s.link_up &&
956 (!octnet_iq_is_full(oct, lio->txq))) {
957 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev,
958 lio->txq, tx_restart, 1);
959 netif_wake_queue(netdev);
9a96bde4
RV		 960 }
961}
962
5b07aee1
RV		 963static
964int liquidio_schedule_msix_droq_pkt_handler(struct octeon_droq *droq, u64 ret)
965{
966 struct octeon_device *oct = droq->oct_dev;
967 struct octeon_device_priv *oct_priv =
968 (struct octeon_device_priv *)oct->priv;
969
970 if (droq->ops.poll_mode) {
971 droq->ops.napi_fn(droq);
972 } else {
973 if (ret & MSIX_PO_INT) {
974 tasklet_schedule(&oct_priv->droq_tasklet);
975 return 1;
976 }
977 /* this will be flushed periodically by check iq db */
978 if (ret & MSIX_PI_INT)
979 return 0;
980 }
981 return 0;
982}
983
f21fb3ed
RV		 984/**
985 * \brief Droq packet processor sceduler
986 * @param oct octeon device
987 */
9ded1a51 988static void liquidio_schedule_droq_pkt_handlers(struct octeon_device *oct)
f21fb3ed
RV		 989{
990 struct octeon_device_priv *oct_priv =
991 (struct octeon_device_priv *)oct->priv;
992 u64 oq_no;
993 struct octeon_droq *droq;
994
995 if (oct->int_status & OCT_DEV_INTR_PKT_DATA) {
63da8404
RV		 996 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct);
997 oq_no++) {
763185a3 998 if (!(oct->droq_intr & BIT_ULL(oq_no)))
f21fb3ed
RV		 999 continue;
1000
1001 droq = oct->droq[oq_no];
1002
1003 if (droq->ops.poll_mode) {
1004 droq->ops.napi_fn(droq);
1005 oct_priv->napi_mask |= (1 << oq_no);
1006 } else {
1007 tasklet_schedule(&oct_priv->droq_tasklet);
1008 }
1009 }
1010 }
1011}
1012
5b07aee1
RV		 1013static irqreturn_t
1014liquidio_msix_intr_handler(int irq __attribute__((unused)), void *dev)
1015{
1016 u64 ret;
1017 struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev;
1018 struct octeon_device *oct = ioq_vector->oct_dev;
1019 struct octeon_droq *droq = oct->droq[ioq_vector->droq_index];
1020
1021 ret = oct->fn_list.msix_interrupt_handler(ioq_vector);
1022
1023 if ((ret & MSIX_PO_INT) || (ret & MSIX_PI_INT))
1024 liquidio_schedule_msix_droq_pkt_handler(droq, ret);
1025
1026 return IRQ_HANDLED;
1027}
1028
f21fb3ed
RV		 1029/**
1030 * \brief Interrupt handler for octeon
1031 * @param irq unused
1032 * @param dev octeon device
1033 */
1034static
5b07aee1
RV		 1035irqreturn_t liquidio_legacy_intr_handler(int irq __attribute__((unused)),
1036 void *dev)
f21fb3ed
RV		 1037{
1038 struct octeon_device *oct = (struct octeon_device *)dev;
1039 irqreturn_t ret;
1040
1041 /* Disable our interrupts for the duration of ISR */
5b07aee1 1042 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
f21fb3ed
RV		 1043
1044 ret = oct->fn_list.process_interrupt_regs(oct);
1045
1046 if (ret == IRQ_HANDLED)
1047 liquidio_schedule_droq_pkt_handlers(oct);
1048
1049 /* Re-enable our interrupts */
1050 if (!(atomic_read(&oct->status) == OCT_DEV_IN_RESET))
5b07aee1 1051 oct->fn_list.enable_interrupt(oct, OCTEON_ALL_INTR);
f21fb3ed
RV		 1052
1053 return ret;
1054}
1055
1056/**
1057 * \brief Setup interrupt for octeon device
1058 * @param oct octeon device
1059 *
1060 * Enable interrupt in Octeon device as given in the PCI interrupt mask.
1061 */
1062static int octeon_setup_interrupt(struct octeon_device *oct)
1063{
1064 int irqret, err;
5b07aee1
RV		 1065 struct msix_entry *msix_entries;
1066 int i;
1067 int num_ioq_vectors;
1068 int num_alloc_ioq_vectors;
0c88a761
RF		 1069 char *queue_irq_names = NULL;
1070 char *aux_irq_name = NULL;
f21fb3ed 1071
5b07aee1
RV		 1072 if (OCTEON_CN23XX_PF(oct) && oct->msix_on) {
1073 oct->num_msix_irqs = oct->sriov_info.num_pf_rings;
1074 /* one non ioq interrupt for handling sli_mac_pf_int_sum */
1075 oct->num_msix_irqs += 1;
f21fb3ed 1076
0c88a761
RF		 1077 /* allocate storage for the names assigned to each irq */
1078 oct->irq_name_storage =
1079 kcalloc((MAX_IOQ_INTERRUPTS_PER_PF + 1), INTRNAMSIZ,
1080 GFP_KERNEL);
1081 if (!oct->irq_name_storage) {
1082 dev_err(&oct->pci_dev->dev, "Irq name storage alloc failed...\n");
1083 return -ENOMEM;
1084 }
1085
1086 queue_irq_names = oct->irq_name_storage;
1087 aux_irq_name = &queue_irq_names
1088 [IRQ_NAME_OFF(MAX_IOQ_INTERRUPTS_PER_PF)];
1089
5b07aee1
RV		 1090 oct->msix_entries = kcalloc(
1091 oct->num_msix_irqs, sizeof(struct msix_entry), GFP_KERNEL);
0c88a761
RF		 1092 if (!oct->msix_entries) {
1093 dev_err(&oct->pci_dev->dev, "Memory Alloc failed...\n");
1094 kfree(oct->irq_name_storage);
1095 oct->irq_name_storage = NULL;
1096 return -ENOMEM;
1097 }
5b07aee1
RV		 1098
1099 msix_entries = (struct msix_entry *)oct->msix_entries;
1100 /*Assumption is that pf msix vectors start from pf srn to pf to
1101 * trs and not from 0. if not change this code
1102 */
1103 for (i = 0; i < oct->num_msix_irqs - 1; i++)
1104 msix_entries[i].entry = oct->sriov_info.pf_srn + i;
1105 msix_entries[oct->num_msix_irqs - 1].entry =
1106 oct->sriov_info.trs;
1107 num_alloc_ioq_vectors = pci_enable_msix_range(
1108 oct->pci_dev, msix_entries,
1109 oct->num_msix_irqs,
1110 oct->num_msix_irqs);
1111 if (num_alloc_ioq_vectors < 0) {
1112 dev_err(&oct->pci_dev->dev, "unable to Allocate MSI-X interrupts\n");
1113 kfree(oct->msix_entries);
1114 oct->msix_entries = NULL;
0c88a761
RF		 1115 kfree(oct->irq_name_storage);
1116 oct->irq_name_storage = NULL;
1117 return num_alloc_ioq_vectors;
5b07aee1
RV		 1118 }
1119 dev_dbg(&oct->pci_dev->dev, "OCTEON: Enough MSI-X interrupts are allocated...\n");
1120
1121 num_ioq_vectors = oct->num_msix_irqs;
1122
1123 /** For PF, there is one non-ioq interrupt handler */
1124 num_ioq_vectors -= 1;
0c88a761
RF		 1125
1126 snprintf(aux_irq_name, INTRNAMSIZ,
1127 "LiquidIO%u-pf%u-aux", oct->octeon_id, oct->pf_num);
5b07aee1 1128 irqret = request_irq(msix_entries[num_ioq_vectors].vector,
0c88a761
RF		 1129 liquidio_legacy_intr_handler, 0,
1130 aux_irq_name, oct);
5b07aee1
RV		 1131 if (irqret) {
1132 dev_err(&oct->pci_dev->dev,
1133 "OCTEON: Request_irq failed for MSIX interrupt Error: %d\n",
1134 irqret);
1135 pci_disable_msix(oct->pci_dev);
1136 kfree(oct->msix_entries);
1137 oct->msix_entries = NULL;
0c88a761
RF		 1138 kfree(oct->irq_name_storage);
1139 oct->irq_name_storage = NULL;
1140 return irqret;
5b07aee1
RV		 1141 }
1142
1143 for (i = 0; i < num_ioq_vectors; i++) {
0c88a761
RF		 1144 snprintf(&queue_irq_names[IRQ_NAME_OFF(i)], INTRNAMSIZ,
1145 "LiquidIO%u-pf%u-rxtx-%u",
1146 oct->octeon_id, oct->pf_num, i);
1147
5b07aee1
RV		 1148 irqret = request_irq(msix_entries[i].vector,
1149 liquidio_msix_intr_handler, 0,
0c88a761
RF		 1150 &queue_irq_names[IRQ_NAME_OFF(i)],
1151 &oct->ioq_vector[i]);
5b07aee1
RV		 1152 if (irqret) {
1153 dev_err(&oct->pci_dev->dev,
1154 "OCTEON: Request_irq failed for MSIX interrupt Error: %d\n",
1155 irqret);
1156 /** Freeing the non-ioq irq vector here . */
1157 free_irq(msix_entries[num_ioq_vectors].vector,
1158 oct);
1159
1160 while (i) {
1161 i--;
1162 /** clearing affinity mask. */
1163 irq_set_affinity_hint(
1164 msix_entries[i].vector, NULL);
1165 free_irq(msix_entries[i].vector,
1166 &oct->ioq_vector[i]);
1167 }
1168 pci_disable_msix(oct->pci_dev);
1169 kfree(oct->msix_entries);
1170 oct->msix_entries = NULL;
0c88a761
RF		 1171 kfree(oct->irq_name_storage);
1172 oct->irq_name_storage = NULL;
1173 return irqret;
5b07aee1
RV		 1174 }
1175 oct->ioq_vector[i].vector = msix_entries[i].vector;
1176 /* assign the cpu mask for this msix interrupt vector */
1177 irq_set_affinity_hint(
1178 msix_entries[i].vector,
1179 (&oct->ioq_vector[i].affinity_mask));
1180 }
1181 dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: MSI-X enabled\n",
1182 oct->octeon_id);
1183 } else {
1184 err = pci_enable_msi(oct->pci_dev);
1185 if (err)
1186 dev_warn(&oct->pci_dev->dev, "Reverting to legacy interrupts. Error: %d\n",
1187 err);
1188 else
1189 oct->flags |= LIO_FLAG_MSI_ENABLED;
1190
0c88a761
RF		 1191 /* allocate storage for the names assigned to the irq */
1192 oct->irq_name_storage = kcalloc(1, INTRNAMSIZ, GFP_KERNEL);
1193 if (!oct->irq_name_storage)
1194 return -ENOMEM;
1195
1196 queue_irq_names = oct->irq_name_storage;
1197
1198 snprintf(&queue_irq_names[IRQ_NAME_OFF(0)], INTRNAMSIZ,
1199 "LiquidIO%u-pf%u-rxtx-%u",
1200 oct->octeon_id, oct->pf_num, 0);
1201
5b07aee1 1202 irqret = request_irq(oct->pci_dev->irq,
0c88a761
RF		 1203 liquidio_legacy_intr_handler,
1204 IRQF_SHARED,
1205 &queue_irq_names[IRQ_NAME_OFF(0)], oct);
5b07aee1
RV		 1206 if (irqret) {
1207 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1208 pci_disable_msi(oct->pci_dev);
1209 dev_err(&oct->pci_dev->dev, "Request IRQ failed with code: %d\n",
1210 irqret);
0c88a761
RF		 1211 kfree(oct->irq_name_storage);
1212 oct->irq_name_storage = NULL;
1213 return irqret;
5b07aee1
RV		 1214 }
1215 }
f21fb3ed
RV		 1216 return 0;
1217}
1218
bb54be58
FM		 1219static struct octeon_device *get_other_octeon_device(struct octeon_device *oct)
1220{
1221 struct octeon_device *other_oct;
1222
1223 other_oct = lio_get_device(oct->octeon_id + 1);
1224
1225 if (other_oct && other_oct->pci_dev) {
1226 int oct_busnum, other_oct_busnum;
1227
1228 oct_busnum = oct->pci_dev->bus->number;
1229 other_oct_busnum = other_oct->pci_dev->bus->number;
1230
1231 if (oct_busnum == other_oct_busnum) {
1232 int oct_slot, other_oct_slot;
1233
1234 oct_slot = PCI_SLOT(oct->pci_dev->devfn);
1235 other_oct_slot = PCI_SLOT(other_oct->pci_dev->devfn);
1236
1237 if (oct_slot == other_oct_slot)
1238 return other_oct;
1239 }
1240 }
1241
1242 return NULL;
1243}
1244
1245static void disable_all_vf_links(struct octeon_device *oct)
1246{
1247 struct net_device *netdev;
1248 int max_vfs, vf, i;
1249
1250 if (!oct)
1251 return;
1252
1253 max_vfs = oct->sriov_info.max_vfs;
1254
1255 for (i = 0; i < oct->ifcount; i++) {
1256 netdev = oct->props[i].netdev;
1257 if (!netdev)
1258 continue;
1259
1260 for (vf = 0; vf < max_vfs; vf++)
1261 liquidio_set_vf_link_state(netdev, vf,
1262 IFLA_VF_LINK_STATE_DISABLE);
1263 }
1264}
1265
9ff1a9ba
RV		 1266static int liquidio_watchdog(void *param)
1267{
bb54be58
FM		 1268 bool err_msg_was_printed[LIO_MAX_CORES];
1269 u16 mask_of_crashed_or_stuck_cores = 0;
1270 bool all_vf_links_are_disabled = false;
9ff1a9ba 1271 struct octeon_device *oct = param;
bb54be58
FM		 1272 struct octeon_device *other_oct;
1273#ifdef CONFIG_MODULE_UNLOAD
1274 long refcount, vfs_referencing_pf;
1275 u64 vfs_mask1, vfs_mask2;
1276#endif
1277 int core;
9ff1a9ba 1278
bb54be58 1279 memset(err_msg_was_printed, 0, sizeof(err_msg_was_printed));
9ff1a9ba
RV		 1280
1281 while (!kthread_should_stop()) {
bb54be58
FM		 1282 /* sleep for a couple of seconds so that we don't hog the CPU */
1283 set_current_state(TASK_INTERRUPTIBLE);
1284 schedule_timeout(msecs_to_jiffies(2000));
1285
1286 mask_of_crashed_or_stuck_cores =
9ff1a9ba
RV		 1287 (u16)octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2);
1288
bb54be58
FM		 1289 if (!mask_of_crashed_or_stuck_cores)
1290 continue;
9ff1a9ba 1291
bb54be58
FM		 1292 WRITE_ONCE(oct->cores_crashed, true);
1293 other_oct = get_other_octeon_device(oct);
1294 if (other_oct)
1295 WRITE_ONCE(other_oct->cores_crashed, true);
9ff1a9ba 1296
bb54be58
FM		 1297 for (core = 0; core < LIO_MAX_CORES; core++) {
1298 bool core_crashed_or_got_stuck;
9ff1a9ba 1299
bb54be58
FM		 1300 core_crashed_or_got_stuck =
1301 (mask_of_crashed_or_stuck_cores
1302 >> core) & 1;
1303
1304 if (core_crashed_or_got_stuck &&
1305 !err_msg_was_printed[core]) {
1306 dev_err(&oct->pci_dev->dev,
1307 "ERROR: Octeon core %d crashed or got stuck! See oct-fwdump for details.\n",
1308 core);
1309 err_msg_was_printed[core] = true;
9ff1a9ba
RV		 1310 }
1311 }
bb54be58
FM		 1312
1313 if (all_vf_links_are_disabled)
1314 continue;
1315
1316 disable_all_vf_links(oct);
1317 disable_all_vf_links(other_oct);
1318 all_vf_links_are_disabled = true;
1319
9ff1a9ba 1320#ifdef CONFIG_MODULE_UNLOAD
bb54be58
FM		 1321 vfs_mask1 = READ_ONCE(oct->sriov_info.vf_drv_loaded_mask);
1322 vfs_mask2 = READ_ONCE(other_oct->sriov_info.vf_drv_loaded_mask);
9ff1a9ba 1323
bb54be58
FM		 1324 vfs_referencing_pf = hweight64(vfs_mask1);
1325 vfs_referencing_pf += hweight64(vfs_mask2);
9ff1a9ba 1326
bb54be58
FM		 1327 refcount = module_refcount(THIS_MODULE);
1328 if (refcount >= vfs_referencing_pf) {
1329 while (vfs_referencing_pf) {
9ff1a9ba 1330 module_put(THIS_MODULE);
bb54be58 1331 vfs_referencing_pf--;
9ff1a9ba
RV		 1332 }
1333 }
1334#endif
9ff1a9ba
RV		 1335 }
1336
1337 return 0;
1338}
1339
f21fb3ed
RV		 1340/**
1341 * \brief PCI probe handler
1342 * @param pdev PCI device structure
1343 * @param ent unused
1344 */
a7d5a3dc
RV		 1345static int
1346liquidio_probe(struct pci_dev *pdev,
1347 const struct pci_device_id *ent __attribute__((unused)))
f21fb3ed
RV		 1348{
1349 struct octeon_device *oct_dev = NULL;
1350 struct handshake *hs;
1351
1352 oct_dev = octeon_allocate_device(pdev->device,
1353 sizeof(struct octeon_device_priv));
1354 if (!oct_dev) {
1355 dev_err(&pdev->dev, "Unable to allocate device\n");
1356 return -ENOMEM;
1357 }
1358
5b07aee1
RV		 1359 if (pdev->device == OCTEON_CN23XX_PF_VID)
1360 oct_dev->msix_on = LIO_FLAG_MSIX_ENABLED;
1361
f21fb3ed
RV		 1362 dev_info(&pdev->dev, "Initializing device %x:%x.\n",
1363 (u32)pdev->vendor, (u32)pdev->device);
1364
1365 /* Assign octeon_device for this device to the private data area. */
1366 pci_set_drvdata(pdev, oct_dev);
1367
1368 /* set linux specific device pointer */
1369 oct_dev->pci_dev = (void *)pdev;
1370
1371 hs = &handshake[oct_dev->octeon_id];
1372 init_completion(&hs->init);
1373 init_completion(&hs->started);
1374 hs->pci_dev = pdev;
1375
1376 if (oct_dev->octeon_id == 0)
1377 /* first LiquidIO NIC is detected */
1378 complete(&first_stage);
1379
1380 if (octeon_device_init(oct_dev)) {
515e752d 1381 complete(&hs->init);
f21fb3ed
RV		 1382 liquidio_remove(pdev);
1383 return -ENOMEM;
1384 }
1385
9ff1a9ba
RV		 1386 if (OCTEON_CN23XX_PF(oct_dev)) {
1387 u64 scratch1;
1388 u8 bus, device, function;
1389
1390 scratch1 = octeon_read_csr64(oct_dev, CN23XX_SLI_SCRATCH1);
1391 if (!(scratch1 & 4ULL)) {
1392 /* Bit 2 of SLI_SCRATCH_1 is a flag that indicates that
1393 * the lio watchdog kernel thread is running for this
1394 * NIC. Each NIC gets one watchdog kernel thread.
1395 */
1396 scratch1 |= 4ULL;
1397 octeon_write_csr64(oct_dev, CN23XX_SLI_SCRATCH1,
1398 scratch1);
1399
1400 bus = pdev->bus->number;
1401 device = PCI_SLOT(pdev->devfn);
1402 function = PCI_FUNC(pdev->devfn);
1403 oct_dev->watchdog_task = kthread_create(
1404 liquidio_watchdog, oct_dev,
1405 "liowd/%02hhx:%02hhx.%hhx", bus, device, function);
515e752d
RV		 1406 if (!IS_ERR(oct_dev->watchdog_task)) {
1407 wake_up_process(oct_dev->watchdog_task);
1408 } else {
1409 oct_dev->watchdog_task = NULL;
1410 dev_err(&oct_dev->pci_dev->dev,
1411 "failed to create kernel_thread\n");
1412 liquidio_remove(pdev);
1413 return -1;
1414 }
9ff1a9ba
RV		 1415 }
1416 }
1417
1f164717
RV		 1418 oct_dev->rx_pause = 1;
1419 oct_dev->tx_pause = 1;
1420
f21fb3ed
RV		 1421 dev_dbg(&oct_dev->pci_dev->dev, "Device is ready\n");
1422
1423 return 0;
1424}
1425
7cc61db9
FM		 1426static bool fw_type_is_none(void)
1427{
1428 return strncmp(fw_type, LIO_FW_NAME_TYPE_NONE,
1429 sizeof(LIO_FW_NAME_TYPE_NONE)) == 0;
1430}
1431
f21fb3ed
RV		 1432/**
1433 *\brief Destroy resources associated with octeon device
1434 * @param pdev PCI device structure
1435 * @param ent unused
1436 */
1437static void octeon_destroy_resources(struct octeon_device *oct)
1438{
e1e3ce62 1439 int i, refcount;
5b07aee1 1440 struct msix_entry *msix_entries;
f21fb3ed
RV		 1441 struct octeon_device_priv *oct_priv =
1442 (struct octeon_device_priv *)oct->priv;
1443
1444 struct handshake *hs;
1445
1446 switch (atomic_read(&oct->status)) {
1447 case OCT_DEV_RUNNING:
1448 case OCT_DEV_CORE_OK:
1449
1450 /* No more instructions will be forwarded. */
1451 atomic_set(&oct->status, OCT_DEV_IN_RESET);
1452
1453 oct->app_mode = CVM_DRV_INVALID_APP;
1454 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
1455 lio_get_state_string(&oct->status));
1456
1457 schedule_timeout_uninterruptible(HZ / 10);
1458
1459 /* fallthrough */
1460 case OCT_DEV_HOST_OK:
1461
1462 /* fallthrough */
1463 case OCT_DEV_CONSOLE_INIT_DONE:
1464 /* Remove any consoles */
1465 octeon_remove_consoles(oct);
1466
1467 /* fallthrough */
1468 case OCT_DEV_IO_QUEUES_DONE:
1469 if (wait_for_pending_requests(oct))
1470 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
1471
1472 if (lio_wait_for_instr_fetch(oct))
1473 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n");
1474
1475 /* Disable the input and output queues now. No more packets will
1476 * arrive from Octeon, but we should wait for all packet
1477 * processing to finish.
1478 */
1479 oct->fn_list.disable_io_queues(oct);
1480
1481 if (lio_wait_for_oq_pkts(oct))
1482 dev_err(&oct->pci_dev->dev, "OQ had pending packets\n");
1483
515e752d
RV		 1484 /* fallthrough */
1485 case OCT_DEV_INTR_SET_DONE:
f21fb3ed 1486 /* Disable interrupts */
5b07aee1
RV		 1487 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
1488
1489 if (oct->msix_on) {
1490 msix_entries = (struct msix_entry *)oct->msix_entries;
1491 for (i = 0; i < oct->num_msix_irqs - 1; i++) {
1492 /* clear the affinity_cpumask */
1493 irq_set_affinity_hint(msix_entries[i].vector,
1494 NULL);
1495 free_irq(msix_entries[i].vector,
1496 &oct->ioq_vector[i]);
1497 }
1498 /* non-iov vector's argument is oct struct */
1499 free_irq(msix_entries[i].vector, oct);
f21fb3ed 1500
5b07aee1
RV		 1501 pci_disable_msix(oct->pci_dev);
1502 kfree(oct->msix_entries);
1503 oct->msix_entries = NULL;
1504 } else {
1505 /* Release the interrupt line */
1506 free_irq(oct->pci_dev->irq, oct);
f21fb3ed 1507
5b07aee1
RV		 1508 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1509 pci_disable_msi(oct->pci_dev);
1510 }
f21fb3ed 1511
0c88a761
RF		 1512 kfree(oct->irq_name_storage);
1513 oct->irq_name_storage = NULL;
1514
515e752d
RV		 1515 /* fallthrough */
1516 case OCT_DEV_MSIX_ALLOC_VECTOR_DONE:
5b07aee1
RV		 1517 if (OCTEON_CN23XX_PF(oct))
1518 octeon_free_ioq_vector(oct);
5d65556b
RV		 1519
1520 /* fallthrough */
1521 case OCT_DEV_MBOX_SETUP_DONE:
1522 if (OCTEON_CN23XX_PF(oct))
1523 oct->fn_list.free_mbox(oct);
1524
5b07aee1 1525 /* fallthrough */
f21fb3ed
RV		 1526 case OCT_DEV_IN_RESET:
1527 case OCT_DEV_DROQ_INIT_DONE:
763185a3 1528 /* Wait for any pending operations */
f21fb3ed 1529 mdelay(100);
63da8404 1530 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
5b07aee1 1531 if (!(oct->io_qmask.oq & BIT_ULL(i)))
f21fb3ed
RV		 1532 continue;
1533 octeon_delete_droq(oct, i);
1534 }
1535
1536 /* Force any pending handshakes to complete */
1537 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
1538 hs = &handshake[i];
1539
1540 if (hs->pci_dev) {
1541 handshake[oct->octeon_id].init_ok = 0;
1542 complete(&handshake[oct->octeon_id].init);
1543 handshake[oct->octeon_id].started_ok = 0;
1544 complete(&handshake[oct->octeon_id].started);
1545 }
1546 }
1547
1548 /* fallthrough */
1549 case OCT_DEV_RESP_LIST_INIT_DONE:
1550 octeon_delete_response_list(oct);
1551
f21fb3ed
RV		 1552 /* fallthrough */
1553 case OCT_DEV_INSTR_QUEUE_INIT_DONE:
63da8404 1554 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
5b823514 1555 if (!(oct->io_qmask.iq & BIT_ULL(i)))
f21fb3ed
RV		 1556 continue;
1557 octeon_delete_instr_queue(oct, i);
1558 }
ca6139ff
RV		 1559#ifdef CONFIG_PCI_IOV
1560 if (oct->sriov_info.sriov_enabled)
1561 pci_disable_sriov(oct->pci_dev);
1562#endif
5b823514
RV		 1563 /* fallthrough */
1564 case OCT_DEV_SC_BUFF_POOL_INIT_DONE:
1565 octeon_free_sc_buffer_pool(oct);
f21fb3ed
RV		 1566
1567 /* fallthrough */
1568 case OCT_DEV_DISPATCH_INIT_DONE:
1569 octeon_delete_dispatch_list(oct);
1570 cancel_delayed_work_sync(&oct->nic_poll_work.work);
1571
1572 /* fallthrough */
1573 case OCT_DEV_PCI_MAP_DONE:
e1e3ce62
RF		 1574 refcount = octeon_deregister_device(oct);
1575
7cc61db9 1576 if (!fw_type_is_none()) {
e1e3ce62
RF		 1577 /* Soft reset the octeon device before exiting.
1578 * Implementation note: here, we reset the device
1579 * if it is a CN6XXX OR the last CN23XX device.
1580 */
1581 if (OCTEON_CN6XXX(oct) || !refcount)
7cc61db9
FM		 1582 oct->fn_list.soft_reset(oct);
1583 }
60b48c5a 1584
f21fb3ed
RV		 1585 octeon_unmap_pci_barx(oct, 0);
1586 octeon_unmap_pci_barx(oct, 1);
1587
1588 /* fallthrough */
515e752d
RV		 1589 case OCT_DEV_PCI_ENABLE_DONE:
1590 pci_clear_master(oct->pci_dev);
60b48c5a
RV		 1591 /* Disable the device, releasing the PCI INT */
1592 pci_disable_device(oct->pci_dev);
1593
515e752d
RV		 1594 /* fallthrough */
1595 case OCT_DEV_BEGIN_STATE:
f21fb3ed
RV		 1596 /* Nothing to be done here either */
1597 break;
a2c64b67 1598 } /* end switch (oct->status) */
f21fb3ed
RV		 1599
1600 tasklet_kill(&oct_priv->droq_tasklet);
1601}
1602
afdf841f
RV		 1603/**
1604 * \brief Callback for rx ctrl
1605 * @param status status of request
1606 * @param buf pointer to resp structure
1607 */
1608static void rx_ctl_callback(struct octeon_device *oct,
1609 u32 status,
1610 void *buf)
1611{
1612 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
1613 struct liquidio_rx_ctl_context *ctx;
1614
1615 ctx = (struct liquidio_rx_ctl_context *)sc->ctxptr;
1616
1617 oct = lio_get_device(ctx->octeon_id);
1618 if (status)
1619 dev_err(&oct->pci_dev->dev, "rx ctl instruction failed. Status: %llx\n",
1620 CVM_CAST64(status));
1621 WRITE_ONCE(ctx->cond, 1);
1622
1623 /* This barrier is required to be sure that the response has been
1624 * written fully before waking up the handler
1625 */
1626 wmb();
1627
1628 wake_up_interruptible(&ctx->wc);
1629}
1630
f21fb3ed
RV		 1631/**
1632 * \brief Send Rx control command
1633 * @param lio per-network private data
1634 * @param start_stop whether to start or stop
1635 */
1636static void send_rx_ctrl_cmd(struct lio *lio, int start_stop)
1637{
afdf841f
RV		 1638 struct octeon_soft_command *sc;
1639 struct liquidio_rx_ctl_context *ctx;
1640 union octnet_cmd *ncmd;
1641 int ctx_size = sizeof(struct liquidio_rx_ctl_context);
1642 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1643 int retval;
f21fb3ed 1644
afdf841f
RV		 1645 if (oct->props[lio->ifidx].rx_on == start_stop)
1646 return;
f21fb3ed 1647
afdf841f
RV		 1648 sc = (struct octeon_soft_command *)
1649 octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
1650 16, ctx_size);
1651
1652 ncmd = (union octnet_cmd *)sc->virtdptr;
1653 ctx = (struct liquidio_rx_ctl_context *)sc->ctxptr;
1654
1655 WRITE_ONCE(ctx->cond, 0);
1656 ctx->octeon_id = lio_get_device_id(oct);
1657 init_waitqueue_head(&ctx->wc);
1658
1659 ncmd->u64 = 0;
1660 ncmd->s.cmd = OCTNET_CMD_RX_CTL;
1661 ncmd->s.param1 = start_stop;
1662
1663 octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1664
1665 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1666
1667 octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1668 OPCODE_NIC_CMD, 0, 0, 0);
1669
1670 sc->callback = rx_ctl_callback;
1671 sc->callback_arg = sc;
1672 sc->wait_time = 5000;
f21fb3ed 1673
afdf841f
RV		 1674 retval = octeon_send_soft_command(oct, sc);
1675 if (retval == IQ_SEND_FAILED) {
f21fb3ed 1676 netif_info(lio, rx_err, lio->netdev, "Failed to send RX Control message\n");
afdf841f
RV		 1677 } else {
1678 /* Sleep on a wait queue till the cond flag indicates that the
1679 * response arrived or timed-out.
1680 */
1681 if (sleep_cond(&ctx->wc, &ctx->cond) == -EINTR)
1682 return;
1683 oct->props[lio->ifidx].rx_on = start_stop;
1684 }
1685
1686 octeon_free_soft_command(oct, sc);
f21fb3ed
RV		 1687}
1688
1689/**
1690 * \brief Destroy NIC device interface
1691 * @param oct octeon device
1692 * @param ifidx which interface to destroy
1693 *
1694 * Cleanup associated with each interface for an Octeon device when NIC
1695 * module is being unloaded or if initialization fails during load.
1696 */
1697static void liquidio_destroy_nic_device(struct octeon_device *oct, int ifidx)
1698{
1699 struct net_device *netdev = oct->props[ifidx].netdev;
1700 struct lio *lio;
9a96bde4 1701 struct napi_struct *napi, *n;
f21fb3ed
RV		 1702
1703 if (!netdev) {
1704 dev_err(&oct->pci_dev->dev, "%s No netdevice ptr for index %d\n",
1705 __func__, ifidx);
1706 return;
1707 }
1708
1709 lio = GET_LIO(netdev);
1710
1711 dev_dbg(&oct->pci_dev->dev, "NIC device cleanup\n");
1712
f21fb3ed 1713 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING)
afdf841f 1714 liquidio_stop(netdev);
f21fb3ed 1715
7cc61db9
FM		 1716 if (fw_type_is_none()) {
1717 struct octnic_ctrl_pkt nctrl;
1718
1719 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
1720 nctrl.ncmd.s.cmd = OCTNET_CMD_RESET_PF;
1721 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
1722 octnet_send_nic_ctrl_pkt(oct, &nctrl);
1723 }
1724
9a96bde4
RV		 1725 if (oct->props[lio->ifidx].napi_enabled == 1) {
1726 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
1727 napi_disable(napi);
1728
1729 oct->props[lio->ifidx].napi_enabled = 0;
7b6b6c95
RV		 1730
1731 if (OCTEON_CN23XX_PF(oct))
1732 oct->droq[0]->ops.poll_mode = 0;
9a96bde4
RV		 1733 }
1734
f21fb3ed
RV		 1735 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED)
1736 unregister_netdev(netdev);
1737
7b6b6c95
RV		 1738 cleanup_link_status_change_wq(netdev);
1739
031d4f12
SB		 1740 cleanup_rx_oom_poll_fn(netdev);
1741
fcd2b5e3 1742 delete_glists(lio);
f21fb3ed
RV		 1743
1744 free_netdev(netdev);
1745
0cece6c5
RV		 1746 oct->props[ifidx].gmxport = -1;
1747
f21fb3ed
RV		 1748 oct->props[ifidx].netdev = NULL;
1749}
1750
1751/**
1752 * \brief Stop complete NIC functionality
1753 * @param oct octeon device
1754 */
1755static int liquidio_stop_nic_module(struct octeon_device *oct)
1756{
1757 int i, j;
1758 struct lio *lio;
1759
1760 dev_dbg(&oct->pci_dev->dev, "Stopping network interfaces\n");
1761 if (!oct->ifcount) {
1762 dev_err(&oct->pci_dev->dev, "Init for Octeon was not completed\n");
1763 return 1;
1764 }
1765
60441888
RV		 1766 spin_lock_bh(&oct->cmd_resp_wqlock);
1767 oct->cmd_resp_state = OCT_DRV_OFFLINE;
1768 spin_unlock_bh(&oct->cmd_resp_wqlock);
1769
f21fb3ed
RV		 1770 for (i = 0; i < oct->ifcount; i++) {
1771 lio = GET_LIO(oct->props[i].netdev);
1772 for (j = 0; j < lio->linfo.num_rxpciq; j++)
26236fa9
RV		 1773 octeon_unregister_droq_ops(oct,
1774 lio->linfo.rxpciq[j].s.q_no);
f21fb3ed
RV		 1775 }
1776
1777 for (i = 0; i < oct->ifcount; i++)
1778 liquidio_destroy_nic_device(oct, i);
1779
1780 dev_dbg(&oct->pci_dev->dev, "Network interfaces stopped\n");
1781 return 0;
1782}
1783
1784/**
1785 * \brief Cleans up resources at unload time
1786 * @param pdev PCI device structure
1787 */
1788static void liquidio_remove(struct pci_dev *pdev)
1789{
1790 struct octeon_device *oct_dev = pci_get_drvdata(pdev);
1791
1792 dev_dbg(&oct_dev->pci_dev->dev, "Stopping device\n");
1793
9ff1a9ba
RV		 1794 if (oct_dev->watchdog_task)
1795 kthread_stop(oct_dev->watchdog_task);
1796
f21fb3ed
RV		 1797 if (oct_dev->app_mode && (oct_dev->app_mode == CVM_DRV_NIC_APP))
1798 liquidio_stop_nic_module(oct_dev);
1799
1800 /* Reset the octeon device and cleanup all memory allocated for
1801 * the octeon device by driver.
1802 */
1803 octeon_destroy_resources(oct_dev);
1804
1805 dev_info(&oct_dev->pci_dev->dev, "Device removed\n");
1806
1807 /* This octeon device has been removed. Update the global
1808 * data structure to reflect this. Free the device structure.
1809 */
1810 octeon_free_device_mem(oct_dev);
1811}
1812
1813/**
1814 * \brief Identify the Octeon device and to map the BAR address space
1815 * @param oct octeon device
1816 */
1817static int octeon_chip_specific_setup(struct octeon_device *oct)
1818{
1819 u32 dev_id, rev_id;
1820 int ret = 1;
d3d7e6c6 1821 char *s;
f21fb3ed
RV		 1822
1823 pci_read_config_dword(oct->pci_dev, 0, &dev_id);
1824 pci_read_config_dword(oct->pci_dev, 8, &rev_id);
1825 oct->rev_id = rev_id & 0xff;
1826
1827 switch (dev_id) {
1828 case OCTEON_CN68XX_PCIID:
1829 oct->chip_id = OCTEON_CN68XX;
1830 ret = lio_setup_cn68xx_octeon_device(oct);
d3d7e6c6 1831 s = "CN68XX";
f21fb3ed
RV		 1832 break;
1833
1834 case OCTEON_CN66XX_PCIID:
1835 oct->chip_id = OCTEON_CN66XX;
1836 ret = lio_setup_cn66xx_octeon_device(oct);
d3d7e6c6 1837 s = "CN66XX";
f21fb3ed 1838 break;
d3d7e6c6 1839
72c00912
RV		 1840 case OCTEON_CN23XX_PCIID_PF:
1841 oct->chip_id = OCTEON_CN23XX_PF_VID;
1842 ret = setup_cn23xx_octeon_pf_device(oct);
cf19a8c3
DC		 1843#ifdef CONFIG_PCI_IOV
1844 if (!ret)
1845 pci_sriov_set_totalvfs(oct->pci_dev,
1846 oct->sriov_info.max_vfs);
1847#endif
72c00912
RV		 1848 s = "CN23XX";
1849 break;
1850
f21fb3ed 1851 default:
d3d7e6c6 1852 s = "?";
f21fb3ed
RV		 1853 dev_err(&oct->pci_dev->dev, "Unknown device found (dev_id: %x)\n",
1854 dev_id);
1855 }
1856
1857 if (!ret)
d3d7e6c6 1858 dev_info(&oct->pci_dev->dev, "%s PASS%d.%d %s Version: %s\n", s,
f21fb3ed
RV		 1859 OCTEON_MAJOR_REV(oct),
1860 OCTEON_MINOR_REV(oct),
d3d7e6c6
RV		 1861 octeon_get_conf(oct)->card_name,
1862 LIQUIDIO_VERSION);
f21fb3ed
RV		 1863
1864 return ret;
1865}
1866
1867/**
1868 * \brief PCI initialization for each Octeon device.
1869 * @param oct octeon device
1870 */
1871static int octeon_pci_os_setup(struct octeon_device *oct)
1872{
1873 /* setup PCI stuff first */
1874 if (pci_enable_device(oct->pci_dev)) {
1875 dev_err(&oct->pci_dev->dev, "pci_enable_device failed\n");
1876 return 1;
1877 }
1878
1879 if (dma_set_mask_and_coherent(&oct->pci_dev->dev, DMA_BIT_MASK(64))) {
1880 dev_err(&oct->pci_dev->dev, "Unexpected DMA device capability\n");
515e752d 1881 pci_disable_device(oct->pci_dev);
f21fb3ed
RV		 1882 return 1;
1883 }
1884
1885 /* Enable PCI DMA Master. */
1886 pci_set_master(oct->pci_dev);
1887
1888 return 0;
1889}
1890
fcd2b5e3
RV		 1891static inline int skb_iq(struct lio *lio, struct sk_buff *skb)
1892{
1893 int q = 0;
1894
1895 if (netif_is_multiqueue(lio->netdev))
1896 q = skb->queue_mapping % lio->linfo.num_txpciq;
1897
1898 return q;
1899}
1900
f21fb3ed
RV		 1901/**
1902 * \brief Check Tx queue state for a given network buffer
1903 * @param lio per-network private data
1904 * @param skb network buffer
1905 */
1906static inline int check_txq_state(struct lio *lio, struct sk_buff *skb)
1907{
1908 int q = 0, iq = 0;
1909
1910 if (netif_is_multiqueue(lio->netdev)) {
1911 q = skb->queue_mapping;
26236fa9 1912 iq = lio->linfo.txpciq[(q % (lio->linfo.num_txpciq))].s.q_no;
f21fb3ed
RV		 1913 } else {
1914 iq = lio->txq;
26236fa9 1915 q = iq;
f21fb3ed
RV		 1916 }
1917
1918 if (octnet_iq_is_full(lio->oct_dev, iq))
1919 return 0;
26236fa9 1920
1f164717
RV		 1921 if (__netif_subqueue_stopped(lio->netdev, q)) {
1922 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq, tx_restart, 1);
26236fa9 1923 wake_q(lio->netdev, q);
1f164717 1924 }
f21fb3ed
RV		 1925 return 1;
1926}
1927
1928/**
1929 * \brief Unmap and free network buffer
1930 * @param buf buffer
1931 */
1932static void free_netbuf(void *buf)
1933{
1934 struct sk_buff *skb;
1935 struct octnet_buf_free_info *finfo;
1936 struct lio *lio;
1937
1938 finfo = (struct octnet_buf_free_info *)buf;
1939 skb = finfo->skb;
1940 lio = finfo->lio;
1941
1942 dma_unmap_single(&lio->oct_dev->pci_dev->dev, finfo->dptr, skb->len,
1943 DMA_TO_DEVICE);
1944
1945 check_txq_state(lio, skb);
1946
cabeb13b 1947 tx_buffer_free(skb);
f21fb3ed
RV		 1948}
1949
1950/**
1951 * \brief Unmap and free gather buffer
1952 * @param buf buffer
1953 */
1954static void free_netsgbuf(void *buf)
1955{
1956 struct octnet_buf_free_info *finfo;
1957 struct sk_buff *skb;
1958 struct lio *lio;
1959 struct octnic_gather *g;
fcd2b5e3 1960 int i, frags, iq;
f21fb3ed
RV		 1961
1962 finfo = (struct octnet_buf_free_info *)buf;
1963 skb = finfo->skb;
1964 lio = finfo->lio;
1965 g = finfo->g;
1966 frags = skb_shinfo(skb)->nr_frags;
1967
1968 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1969 g->sg[0].ptr[0], (skb->len - skb->data_len),
1970 DMA_TO_DEVICE);
1971
1972 i = 1;
1973 while (frags--) {
1974 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1975
1976 pci_unmap_page((lio->oct_dev)->pci_dev,
1977 g->sg[(i >> 2)].ptr[(i & 3)],
1978 frag->size, DMA_TO_DEVICE);
1979 i++;
1980 }
1981
fcd2b5e3
RV		 1982 iq = skb_iq(lio, skb);
1983 spin_lock(&lio->glist_lock[iq]);
1984 list_add_tail(&g->list, &lio->glist[iq]);
1985 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1986
1987 check_txq_state(lio, skb); /* mq support: sub-queue state check */
1988
cabeb13b 1989 tx_buffer_free(skb);
f21fb3ed
RV		 1990}
1991
1992/**
1993 * \brief Unmap and free gather buffer with response
1994 * @param buf buffer
1995 */
1996static void free_netsgbuf_with_resp(void *buf)
1997{
1998 struct octeon_soft_command *sc;
1999 struct octnet_buf_free_info *finfo;
2000 struct sk_buff *skb;
2001 struct lio *lio;
2002 struct octnic_gather *g;
fcd2b5e3 2003 int i, frags, iq;
f21fb3ed
RV		 2004
2005 sc = (struct octeon_soft_command *)buf;
2006 skb = (struct sk_buff *)sc->callback_arg;
2007 finfo = (struct octnet_buf_free_info *)&skb->cb;
2008
2009 lio = finfo->lio;
2010 g = finfo->g;
2011 frags = skb_shinfo(skb)->nr_frags;
2012
2013 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
2014 g->sg[0].ptr[0], (skb->len - skb->data_len),
2015 DMA_TO_DEVICE);
2016
2017 i = 1;
2018 while (frags--) {
2019 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
2020
2021 pci_unmap_page((lio->oct_dev)->pci_dev,
2022 g->sg[(i >> 2)].ptr[(i & 3)],
2023 frag->size, DMA_TO_DEVICE);
2024 i++;
2025 }
2026
fcd2b5e3
RV		 2027 iq = skb_iq(lio, skb);
2028
2029 spin_lock(&lio->glist_lock[iq]);
2030 list_add_tail(&g->list, &lio->glist[iq]);
2031 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 2032
2033 /* Don't free the skb yet */
2034
2035 check_txq_state(lio, skb);
2036}
2037
2038/**
2039 * \brief Adjust ptp frequency
2040 * @param ptp PTP clock info
2041 * @param ppb how much to adjust by, in parts-per-billion
2042 */
2043static int liquidio_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
2044{
2045 struct lio *lio = container_of(ptp, struct lio, ptp_info);
2046 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
2047 u64 comp, delta;
2048 unsigned long flags;
2049 bool neg_adj = false;
2050
2051 if (ppb < 0) {
2052 neg_adj = true;
2053 ppb = -ppb;
2054 }
2055
2056 /* The hardware adds the clock compensation value to the
2057 * PTP clock on every coprocessor clock cycle, so we
2058 * compute the delta in terms of coprocessor clocks.
2059 */
2060 delta = (u64)ppb << 32;
2061 do_div(delta, oct->coproc_clock_rate);
2062
2063 spin_lock_irqsave(&lio->ptp_lock, flags);
2064 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP);
2065 if (neg_adj)
2066 comp -= delta;
2067 else
2068 comp += delta;
2069 lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP);
2070 spin_unlock_irqrestore(&lio->ptp_lock, flags);
2071
2072 return 0;
2073}
2074
2075/**
2076 * \brief Adjust ptp time
2077 * @param ptp PTP clock info
2078 * @param delta how much to adjust by, in nanosecs
2079 */
2080static int liquidio_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
2081{
2082 unsigned long flags;
2083 struct lio *lio = container_of(ptp, struct lio, ptp_info);
2084
2085 spin_lock_irqsave(&lio->ptp_lock, flags);
2086 lio->ptp_adjust += delta;
2087 spin_unlock_irqrestore(&lio->ptp_lock, flags);
2088
2089 return 0;
2090}
2091
2092/**
2093 * \brief Get hardware clock time, including any adjustment
2094 * @param ptp PTP clock info
2095 * @param ts timespec
2096 */
2097static int liquidio_ptp_gettime(struct ptp_clock_info *ptp,
2098 struct timespec64 *ts)
2099{
2100 u64 ns;
f21fb3ed
RV		 2101 unsigned long flags;
2102 struct lio *lio = container_of(ptp, struct lio, ptp_info);
2103 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
2104
2105 spin_lock_irqsave(&lio->ptp_lock, flags);
2106 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI);
2107 ns += lio->ptp_adjust;
2108 spin_unlock_irqrestore(&lio->ptp_lock, flags);
2109
286af315 2110 *ts = ns_to_timespec64(ns);
f21fb3ed
RV		 2111
2112 return 0;
2113}
2114
2115/**
2116 * \brief Set hardware clock time. Reset adjustment
2117 * @param ptp PTP clock info
2118 * @param ts timespec
2119 */
2120static int liquidio_ptp_settime(struct ptp_clock_info *ptp,
2121 const struct timespec64 *ts)
2122{
2123 u64 ns;
2124 unsigned long flags;
2125 struct lio *lio = container_of(ptp, struct lio, ptp_info);
2126 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
2127
2128 ns = timespec_to_ns(ts);
2129
2130 spin_lock_irqsave(&lio->ptp_lock, flags);
2131 lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI);
2132 lio->ptp_adjust = 0;
2133 spin_unlock_irqrestore(&lio->ptp_lock, flags);
2134
2135 return 0;
2136}
2137
2138/**
2139 * \brief Check if PTP is enabled
2140 * @param ptp PTP clock info
2141 * @param rq request
2142 * @param on is it on
2143 */
a7d5a3dc
RV		 2144static int
2145liquidio_ptp_enable(struct ptp_clock_info *ptp __attribute__((unused)),
2146 struct ptp_clock_request *rq __attribute__((unused)),
2147 int on __attribute__((unused)))
f21fb3ed
RV		 2148{
2149 return -EOPNOTSUPP;
2150}
2151
2152/**
2153 * \brief Open PTP clock source
2154 * @param netdev network device
2155 */
2156static void oct_ptp_open(struct net_device *netdev)
2157{
2158 struct lio *lio = GET_LIO(netdev);
2159 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
2160
2161 spin_lock_init(&lio->ptp_lock);
2162
2163 snprintf(lio->ptp_info.name, 16, "%s", netdev->name);
2164 lio->ptp_info.owner = THIS_MODULE;
2165 lio->ptp_info.max_adj = 250000000;
2166 lio->ptp_info.n_alarm = 0;
2167 lio->ptp_info.n_ext_ts = 0;
2168 lio->ptp_info.n_per_out = 0;
2169 lio->ptp_info.pps = 0;
2170 lio->ptp_info.adjfreq = liquidio_ptp_adjfreq;
2171 lio->ptp_info.adjtime = liquidio_ptp_adjtime;
2172 lio->ptp_info.gettime64 = liquidio_ptp_gettime;
2173 lio->ptp_info.settime64 = liquidio_ptp_settime;
2174 lio->ptp_info.enable = liquidio_ptp_enable;
2175
2176 lio->ptp_adjust = 0;
2177
2178 lio->ptp_clock = ptp_clock_register(&lio->ptp_info,
2179 &oct->pci_dev->dev);
2180
2181 if (IS_ERR(lio->ptp_clock))
2182 lio->ptp_clock = NULL;
2183}
2184
2185/**
2186 * \brief Init PTP clock
2187 * @param oct octeon device
2188 */
2189static void liquidio_ptp_init(struct octeon_device *oct)
2190{
2191 u64 clock_comp, cfg;
2192
2193 clock_comp = (u64)NSEC_PER_SEC << 32;
2194 do_div(clock_comp, oct->coproc_clock_rate);
2195 lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP);
2196
2197 /* Enable */
2198 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG);
2199 lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG);
2200}
2201
2202/**
2203 * \brief Load firmware to device
2204 * @param oct octeon device
2205 *
2206 * Maps device to firmware filename, requests firmware, and downloads it
2207 */
2208static int load_firmware(struct octeon_device *oct)
2209{
2210 int ret = 0;
2211 const struct firmware *fw;
2212 char fw_name[LIO_MAX_FW_FILENAME_LEN];
2213 char *tmp_fw_type;
2214
7cc61db9 2215 if (fw_type_is_none()) {
f21fb3ed
RV		 2216 dev_info(&oct->pci_dev->dev, "Skipping firmware load\n");
2217 return ret;
2218 }
2219
2220 if (fw_type[0] == '\0')
2221 tmp_fw_type = LIO_FW_NAME_TYPE_NIC;
2222 else
2223 tmp_fw_type = fw_type;
2224
2225 sprintf(fw_name, "%s%s%s_%s%s", LIO_FW_DIR, LIO_FW_BASE_NAME,
2226 octeon_get_conf(oct)->card_name, tmp_fw_type,
2227 LIO_FW_NAME_SUFFIX);
2228
2229 ret = request_firmware(&fw, fw_name, &oct->pci_dev->dev);
2230 if (ret) {
2231 dev_err(&oct->pci_dev->dev, "Request firmware failed. Could not find file %s.\n.",
2232 fw_name);
d3d7e6c6 2233 release_firmware(fw);
f21fb3ed
RV		 2234 return ret;
2235 }
2236
2237 ret = octeon_download_firmware(oct, fw->data, fw->size);
2238
2239 release_firmware(fw);
2240
2241 return ret;
2242}
2243
2244/**
2245 * \brief Setup output queue
2246 * @param oct octeon device
2247 * @param q_no which queue
2248 * @param num_descs how many descriptors
2249 * @param desc_size size of each descriptor
2250 * @param app_ctx application context
2251 */
2252static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs,
2253 int desc_size, void *app_ctx)
2254{
2255 int ret_val = 0;
2256
2257 dev_dbg(&oct->pci_dev->dev, "Creating Droq: %d\n", q_no);
2258 /* droq creation and local register settings. */
2259 ret_val = octeon_create_droq(oct, q_no, num_descs, desc_size, app_ctx);
08a965ec 2260 if (ret_val < 0)
f21fb3ed
RV		 2261 return ret_val;
2262
2263 if (ret_val == 1) {
2264 dev_dbg(&oct->pci_dev->dev, "Using default droq %d\n", q_no);
2265 return 0;
2266 }
2267 /* tasklet creation for the droq */
2268
2269 /* Enable the droq queues */
2270 octeon_set_droq_pkt_op(oct, q_no, 1);
2271
2272 /* Send Credit for Octeon Output queues. Credits are always
2273 * sent after the output queue is enabled.
2274 */
2275 writel(oct->droq[q_no]->max_count,
2276 oct->droq[q_no]->pkts_credit_reg);
2277
2278 return ret_val;
2279}
2280
2281/**
2282 * \brief Callback for getting interface configuration
2283 * @param status status of request
2284 * @param buf pointer to resp structure
2285 */
2286static void if_cfg_callback(struct octeon_device *oct,
a7d5a3dc 2287 u32 status __attribute__((unused)),
f21fb3ed
RV		 2288 void *buf)
2289{
2290 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
2291 struct liquidio_if_cfg_resp *resp;
2292 struct liquidio_if_cfg_context *ctx;
2293
2294 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
30136395 2295 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
f21fb3ed
RV		 2296
2297 oct = lio_get_device(ctx->octeon_id);
2298 if (resp->status)
c5b71e63
RF		 2299 dev_err(&oct->pci_dev->dev, "nic if cfg instruction failed. Status: 0x%llx (0x%08x)\n",
2300 CVM_CAST64(resp->status), status);
a7d5a3dc 2301 WRITE_ONCE(ctx->cond, 1);
f21fb3ed 2302
d3d7e6c6
RV		 2303 snprintf(oct->fw_info.liquidio_firmware_version, 32, "%s",
2304 resp->cfg_info.liquidio_firmware_version);
2305
f21fb3ed
RV		 2306 /* This barrier is required to be sure that the response has been
2307 * written fully before waking up the handler
2308 */
2309 wmb();
2310
2311 wake_up_interruptible(&ctx->wc);
2312}
2313
f21fb3ed
RV		 2314/** Routine to push packets arriving on Octeon interface upto network layer.
2315 * @param oct_id - octeon device id.
2316 * @param skbuff - skbuff struct to be passed to network layer.
2317 * @param len - size of total data received.
2318 * @param rh - Control header associated with the packet
2319 * @param param - additional control data with the packet
0cece6c5 2320 * @param arg - farg registered in droq_ops
f21fb3ed
RV		 2321 */
2322static void
a7d5a3dc 2323liquidio_push_packet(u32 octeon_id __attribute__((unused)),
f21fb3ed
RV		 2324 void *skbuff,
2325 u32 len,
2326 union octeon_rh *rh,
0cece6c5
RV		 2327 void *param,
2328 void *arg)
f21fb3ed
RV		 2329{
2330 struct napi_struct *napi = param;
f21fb3ed
RV		 2331 struct sk_buff *skb = (struct sk_buff *)skbuff;
2332 struct skb_shared_hwtstamps *shhwtstamps;
2333 u64 ns;
0da0b77c 2334 u16 vtag = 0;
de28c99d 2335 u32 r_dh_off;
0cece6c5 2336 struct net_device *netdev = (struct net_device *)arg;
f21fb3ed
RV		 2337 struct octeon_droq *droq = container_of(param, struct octeon_droq,
2338 napi);
2339 if (netdev) {
2340 int packet_was_received;
2341 struct lio *lio = GET_LIO(netdev);
a5b37888 2342 struct octeon_device *oct = lio->oct_dev;
f21fb3ed
RV		 2343
2344 /* Do not proceed if the interface is not in RUNNING state. */
2345 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) {
2346 recv_buffer_free(skb);
2347 droq->stats.rx_dropped++;
2348 return;
2349 }
2350
2351 skb->dev = netdev;
2352
26236fa9 2353 skb_record_rx_queue(skb, droq->q_no);
cabeb13b
RV		 2354 if (likely(len > MIN_SKB_SIZE)) {
2355 struct octeon_skb_page_info *pg_info;
2356 unsigned char *va;
2357
2358 pg_info = ((struct octeon_skb_page_info *)(skb->cb));
2359 if (pg_info->page) {
2360 /* For Paged allocation use the frags */
2361 va = page_address(pg_info->page) +
2362 pg_info->page_offset;
2363 memcpy(skb->data, va, MIN_SKB_SIZE);
2364 skb_put(skb, MIN_SKB_SIZE);
2365 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2366 pg_info->page,
2367 pg_info->page_offset +
2368 MIN_SKB_SIZE,
2369 len - MIN_SKB_SIZE,
2370 LIO_RXBUFFER_SZ);
2371 }
2372 } else {
2373 struct octeon_skb_page_info *pg_info =
2374 ((struct octeon_skb_page_info *)(skb->cb));
2375 skb_copy_to_linear_data(skb, page_address(pg_info->page)
2376 + pg_info->page_offset, len);
2377 skb_put(skb, len);
2378 put_page(pg_info->page);
2379 }
26236fa9 2380
de28c99d
PK		 2381 r_dh_off = (rh->r_dh.len - 1) * BYTES_PER_DHLEN_UNIT;
2382
a5b37888
RV		 2383 if (((oct->chip_id == OCTEON_CN66XX) ||
2384 (oct->chip_id == OCTEON_CN68XX)) &&
2385 ptp_enable) {
2386 if (rh->r_dh.has_hwtstamp) {
2387 /* timestamp is included from the hardware at
2388 * the beginning of the packet.
f21fb3ed 2389 */
a5b37888
RV		 2390 if (ifstate_check
2391 (lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED)) {
2392 /* Nanoseconds are in the first 64-bits
2393 * of the packet.
2394 */
de28c99d
PK		 2395 memcpy(&ns, (skb->data + r_dh_off),
2396 sizeof(ns));
2397 r_dh_off -= BYTES_PER_DHLEN_UNIT;
a5b37888
RV		 2398 shhwtstamps = skb_hwtstamps(skb);
2399 shhwtstamps->hwtstamp =
2400 ns_to_ktime(ns +
2401 lio->ptp_adjust);
2402 }
f21fb3ed 2403 }
f21fb3ed
RV		 2404 }
2405
de28c99d
PK		 2406 if (rh->r_dh.has_hash) {
2407 __be32 *hash_be = (__be32 *)(skb->data + r_dh_off);
2408 u32 hash = be32_to_cpu(*hash_be);
2409
2410 skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
2411 r_dh_off -= BYTES_PER_DHLEN_UNIT;
2412 }
2413
2414 skb_pull(skb, rh->r_dh.len * BYTES_PER_DHLEN_UNIT);
2415
f21fb3ed 2416 skb->protocol = eth_type_trans(skb, skb->dev);
f21fb3ed 2417 if ((netdev->features & NETIF_F_RXCSUM) &&
01fb237a
RV		 2418 (((rh->r_dh.encap_on) &&
2419 (rh->r_dh.csum_verified & CNNIC_TUN_CSUM_VERIFIED)) ||
2420 (!(rh->r_dh.encap_on) &&
2421 (rh->r_dh.csum_verified & CNNIC_CSUM_VERIFIED))))
f21fb3ed
RV		 2422 /* checksum has already been verified */
2423 skb->ip_summed = CHECKSUM_UNNECESSARY;
2424 else
2425 skb->ip_summed = CHECKSUM_NONE;
2426
01fb237a
RV		 2427 /* Setting Encapsulation field on basis of status received
2428 * from the firmware
2429 */
2430 if (rh->r_dh.encap_on) {
2431 skb->encapsulation = 1;
2432 skb->csum_level = 1;
2433 droq->stats.rx_vxlan++;
2434 }
2435
0da0b77c
RV		 2436 /* inbound VLAN tag */
2437 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2438 (rh->r_dh.vlan != 0)) {
2439 u16 vid = rh->r_dh.vlan;
2440 u16 priority = rh->r_dh.priority;
2441
2442 vtag = priority << 13 | vid;
2443 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
2444 }
2445
f21fb3ed
RV		 2446 packet_was_received = napi_gro_receive(napi, skb) != GRO_DROP;
2447
2448 if (packet_was_received) {
2449 droq->stats.rx_bytes_received += len;
2450 droq->stats.rx_pkts_received++;
f21fb3ed
RV		 2451 } else {
2452 droq->stats.rx_dropped++;
2453 netif_info(lio, rx_err, lio->netdev,
2454 "droq:%d error rx_dropped:%llu\n",
2455 droq->q_no, droq->stats.rx_dropped);
2456 }
2457
2458 } else {
2459 recv_buffer_free(skb);
2460 }
2461}
2462
2463/**
2464 * \brief wrapper for calling napi_schedule
2465 * @param param parameters to pass to napi_schedule
2466 *
2467 * Used when scheduling on different CPUs
2468 */
2469static void napi_schedule_wrapper(void *param)
2470{
2471 struct napi_struct *napi = param;
2472
2473 napi_schedule(napi);
2474}
2475
2476/**
2477 * \brief callback when receive interrupt occurs and we are in NAPI mode
2478 * @param arg pointer to octeon output queue
2479 */
2480static void liquidio_napi_drv_callback(void *arg)
2481{
9ded1a51 2482 struct octeon_device *oct;
f21fb3ed
RV		 2483 struct octeon_droq *droq = arg;
2484 int this_cpu = smp_processor_id();
2485
9ded1a51
RV		 2486 oct = droq->oct_dev;
2487
2488 if (OCTEON_CN23XX_PF(oct) || droq->cpu_id == this_cpu) {
2489 napi_schedule_irqoff(&droq->napi);
f21fb3ed
RV		 2490 } else {
2491 struct call_single_data *csd = &droq->csd;
2492
2493 csd->func = napi_schedule_wrapper;
2494 csd->info = &droq->napi;
2495 csd->flags = 0;
2496
2497 smp_call_function_single_async(droq->cpu_id, csd);
2498 }
2499}
2500
f21fb3ed
RV		 2501/**
2502 * \brief Entry point for NAPI polling
2503 * @param napi NAPI structure
2504 * @param budget maximum number of items to process
2505 */
2506static int liquidio_napi_poll(struct napi_struct *napi, int budget)
2507{
2508 struct octeon_droq *droq;
2509 int work_done;
9a96bde4
RV		 2510 int tx_done = 0, iq_no;
2511 struct octeon_instr_queue *iq;
2512 struct octeon_device *oct;
f21fb3ed
RV		 2513
2514 droq = container_of(napi, struct octeon_droq, napi);
9a96bde4
RV		 2515 oct = droq->oct_dev;
2516 iq_no = droq->q_no;
2517 /* Handle Droq descriptors */
2518 work_done = octeon_process_droq_poll_cmd(oct, droq->q_no,
2519 POLL_EVENT_PROCESS_PKTS,
2520 budget);
f21fb3ed 2521
9a96bde4
RV		 2522 /* Flush the instruction queue */
2523 iq = oct->instr_queue[iq_no];
2524 if (iq) {
6069f3fb
VB		 2525 if (atomic_read(&iq->instr_pending))
2526 /* Process iq buffers with in the budget limits */
2527 tx_done = octeon_flush_iq(oct, iq, budget);
2528 else
2529 tx_done = 1;
9a96bde4
RV		 2530 /* Update iq read-index rather than waiting for next interrupt.
2531 * Return back if tx_done is false.
2532 */
2533 update_txq_status(oct, iq_no);
9a96bde4
RV		 2534 } else {
2535 dev_err(&oct->pci_dev->dev, "%s: iq (%d) num invalid\n",
2536 __func__, iq_no);
2537 }
f21fb3ed 2538
cdb478e5
SB		 2539 /* force enable interrupt if reg cnts are high to avoid wraparound */
2540 if ((work_done < budget && tx_done) ||
76e0e70e 2541 (iq && iq->pkt_in_done >= MAX_REG_CNT) ||
cdb478e5
SB		 2542 (droq->pkt_count >= MAX_REG_CNT)) {
2543 tx_done = 1;
6ad20165 2544 napi_complete_done(napi, work_done);
f21fb3ed
RV		 2545 octeon_process_droq_poll_cmd(droq->oct_dev, droq->q_no,
2546 POLL_EVENT_ENABLE_INTR, 0);
2547 return 0;
2548 }
2549
9a96bde4 2550 return (!tx_done) ? (budget) : (work_done);
f21fb3ed
RV		 2551}
2552
2553/**
2554 * \brief Setup input and output queues
2555 * @param octeon_dev octeon device
a2c64b67 2556 * @param ifidx Interface Index
f21fb3ed
RV		 2557 *
2558 * Note: Queues are with respect to the octeon device. Thus
2559 * an input queue is for egress packets, and output queues
2560 * are for ingress packets.
2561 */
2562static inline int setup_io_queues(struct octeon_device *octeon_dev,
0cece6c5 2563 int ifidx)
f21fb3ed 2564{
0cece6c5
RV		 2565 struct octeon_droq_ops droq_ops;
2566 struct net_device *netdev;
eb2b9874
GS		 2567 int cpu_id;
2568 int cpu_id_modulus;
f21fb3ed
RV		 2569 struct octeon_droq *droq;
2570 struct napi_struct *napi;
2571 int q, q_no, retval = 0;
2572 struct lio *lio;
2573 int num_tx_descs;
2574
0cece6c5
RV		 2575 netdev = octeon_dev->props[ifidx].netdev;
2576
2577 lio = GET_LIO(netdev);
f21fb3ed 2578
0cece6c5 2579 memset(&droq_ops, 0, sizeof(struct octeon_droq_ops));
f21fb3ed 2580
0cece6c5
RV		 2581 droq_ops.fptr = liquidio_push_packet;
2582 droq_ops.farg = (void *)netdev;
2583
2584 droq_ops.poll_mode = 1;
2585 droq_ops.napi_fn = liquidio_napi_drv_callback;
2586 cpu_id = 0;
2587 cpu_id_modulus = num_present_cpus();
f21fb3ed
RV		 2588
2589 /* set up DROQs. */
2590 for (q = 0; q < lio->linfo.num_rxpciq; q++) {
26236fa9
RV		 2591 q_no = lio->linfo.rxpciq[q].s.q_no;
2592 dev_dbg(&octeon_dev->pci_dev->dev,
2593 "setup_io_queues index:%d linfo.rxpciq.s.q_no:%d\n",
2594 q, q_no);
f21fb3ed
RV		 2595 retval = octeon_setup_droq(octeon_dev, q_no,
2596 CFG_GET_NUM_RX_DESCS_NIC_IF
2597 (octeon_get_conf(octeon_dev),
2598 lio->ifidx),
2599 CFG_GET_NUM_RX_BUF_SIZE_NIC_IF
2600 (octeon_get_conf(octeon_dev),
2601 lio->ifidx), NULL);
2602 if (retval) {
2603 dev_err(&octeon_dev->pci_dev->dev,
32581245 2604 "%s : Runtime DROQ(RxQ) creation failed.\n",
f21fb3ed
RV		 2605 __func__);
2606 return 1;
2607 }
2608
2609 droq = octeon_dev->droq[q_no];
2610 napi = &droq->napi;
1b7c55c4
RV		 2611 dev_dbg(&octeon_dev->pci_dev->dev, "netif_napi_add netdev:%llx oct:%llx pf_num:%d\n",
2612 (u64)netdev, (u64)octeon_dev, octeon_dev->pf_num);
0cece6c5 2613 netif_napi_add(netdev, napi, liquidio_napi_poll, 64);
f21fb3ed
RV		 2614
2615 /* designate a CPU for this droq */
2616 droq->cpu_id = cpu_id;
2617 cpu_id++;
2618 if (cpu_id >= cpu_id_modulus)
2619 cpu_id = 0;
2620
2621 octeon_register_droq_ops(octeon_dev, q_no, &droq_ops);
2622 }
2623
7b6b6c95
RV		 2624 if (OCTEON_CN23XX_PF(octeon_dev)) {
2625 /* 23XX PF can receive control messages (via the first PF-owned
2626 * droq) from the firmware even if the ethX interface is down,
2627 * so that's why poll_mode must be off for the first droq.
2628 */
2629 octeon_dev->droq[0]->ops.poll_mode = 0;
2630 }
2631
f21fb3ed
RV		 2632 /* set up IQs. */
2633 for (q = 0; q < lio->linfo.num_txpciq; q++) {
2634 num_tx_descs = CFG_GET_NUM_TX_DESCS_NIC_IF(octeon_get_conf
2635 (octeon_dev),
2636 lio->ifidx);
0cece6c5
RV		 2637 retval = octeon_setup_iq(octeon_dev, ifidx, q,
2638 lio->linfo.txpciq[q], num_tx_descs,
2639 netdev_get_tx_queue(netdev, q));
f21fb3ed
RV		 2640 if (retval) {
2641 dev_err(&octeon_dev->pci_dev->dev,
2642 " %s : Runtime IQ(TxQ) creation failed.\n",
2643 __func__);
2644 return 1;
2645 }
35ae57ea
RF		 2646
2647 if (octeon_dev->ioq_vector) {
2648 struct octeon_ioq_vector *ioq_vector;
2649
2650 ioq_vector = &octeon_dev->ioq_vector[q];
2651 netif_set_xps_queue(netdev,
2652 &ioq_vector->affinity_mask,
2653 ioq_vector->iq_index);
2654 }
f21fb3ed
RV		 2655 }
2656
2657 return 0;
2658}
2659
2660/**
2661 * \brief Poll routine for checking transmit queue status
2662 * @param work work_struct data structure
2663 */
2664static void octnet_poll_check_txq_status(struct work_struct *work)
2665{
2666 struct cavium_wk *wk = (struct cavium_wk *)work;
2667 struct lio *lio = (struct lio *)wk->ctxptr;
2668
2669 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING))
2670 return;
2671
2672 check_txq_status(lio);
2673 queue_delayed_work(lio->txq_status_wq.wq,
2674 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2675}
2676
2677/**
2678 * \brief Sets up the txq poll check
2679 * @param netdev network device
2680 */
5b07aee1 2681static inline int setup_tx_poll_fn(struct net_device *netdev)
f21fb3ed
RV		 2682{
2683 struct lio *lio = GET_LIO(netdev);
2684 struct octeon_device *oct = lio->oct_dev;
2685
292b9dab
BS		 2686 lio->txq_status_wq.wq = alloc_workqueue("txq-status",
2687 WQ_MEM_RECLAIM, 0);
f21fb3ed
RV		 2688 if (!lio->txq_status_wq.wq) {
2689 dev_err(&oct->pci_dev->dev, "unable to create cavium txq status wq\n");
5b07aee1 2690 return -1;
f21fb3ed
RV		 2691 }
2692 INIT_DELAYED_WORK(&lio->txq_status_wq.wk.work,
2693 octnet_poll_check_txq_status);
2694 lio->txq_status_wq.wk.ctxptr = lio;
2695 queue_delayed_work(lio->txq_status_wq.wq,
2696 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
5b07aee1 2697 return 0;
f21fb3ed
RV		 2698}
2699
9a96bde4
RV		 2700static inline void cleanup_tx_poll_fn(struct net_device *netdev)
2701{
2702 struct lio *lio = GET_LIO(netdev);
2703
5b07aee1
RV		 2704 if (lio->txq_status_wq.wq) {
2705 cancel_delayed_work_sync(&lio->txq_status_wq.wk.work);
2706 destroy_workqueue(lio->txq_status_wq.wq);
2707 }
9a96bde4
RV		 2708}
2709
f21fb3ed
RV		 2710/**
2711 * \brief Net device open for LiquidIO
2712 * @param netdev network device
2713 */
2714static int liquidio_open(struct net_device *netdev)
2715{
2716 struct lio *lio = GET_LIO(netdev);
2717 struct octeon_device *oct = lio->oct_dev;
2718 struct napi_struct *napi, *n;
2719
9a96bde4
RV		 2720 if (oct->props[lio->ifidx].napi_enabled == 0) {
2721 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
2722 napi_enable(napi);
2723
2724 oct->props[lio->ifidx].napi_enabled = 1;
7b6b6c95
RV		 2725
2726 if (OCTEON_CN23XX_PF(oct))
2727 oct->droq[0]->ops.poll_mode = 1;
9a96bde4 2728 }
f21fb3ed 2729
9feb16ae
PK		 2730 if ((oct->chip_id == OCTEON_CN66XX || oct->chip_id == OCTEON_CN68XX) &&
2731 ptp_enable)
2732 oct_ptp_open(netdev);
f21fb3ed
RV		 2733
2734 ifstate_set(lio, LIO_IFSTATE_RUNNING);
9a96bde4 2735
7b6b6c95
RV		 2736 /* Ready for link status updates */
2737 lio->intf_open = 1;
2738
2739 netif_info(lio, ifup, lio->netdev, "Interface Open, ready for traffic\n");
2740
5b07aee1
RV		 2741 if (OCTEON_CN23XX_PF(oct)) {
2742 if (!oct->msix_on)
2743 if (setup_tx_poll_fn(netdev))
2744 return -1;
2745 } else {
2746 if (setup_tx_poll_fn(netdev))
2747 return -1;
2748 }
9a96bde4 2749
f21fb3ed
RV		 2750 start_txq(netdev);
2751
f21fb3ed
RV		 2752 /* tell Octeon to start forwarding packets to host */
2753 send_rx_ctrl_cmd(lio, 1);
2754
f21fb3ed
RV		 2755 dev_info(&oct->pci_dev->dev, "%s interface is opened\n",
2756 netdev->name);
2757
2758 return 0;
2759}
2760
2761/**
2762 * \brief Net device stop for LiquidIO
2763 * @param netdev network device
2764 */
2765static int liquidio_stop(struct net_device *netdev)
2766{
f21fb3ed
RV		 2767 struct lio *lio = GET_LIO(netdev);
2768 struct octeon_device *oct = lio->oct_dev;
2769
9a96bde4
RV		 2770 ifstate_reset(lio, LIO_IFSTATE_RUNNING);
2771
2772 netif_tx_disable(netdev);
2773
f21fb3ed 2774 /* Inform that netif carrier is down */
9a96bde4 2775 netif_carrier_off(netdev);
f21fb3ed 2776 lio->intf_open = 0;
0cece6c5
RV		 2777 lio->linfo.link.s.link_up = 0;
2778 lio->link_changes++;
f21fb3ed 2779
cb2336b5 2780 /* Tell Octeon that nic interface is down. */
f21fb3ed
RV		 2781 send_rx_ctrl_cmd(lio, 0);
2782
5b07aee1
RV		 2783 if (OCTEON_CN23XX_PF(oct)) {
2784 if (!oct->msix_on)
2785 cleanup_tx_poll_fn(netdev);
2786 } else {
2787 cleanup_tx_poll_fn(netdev);
2788 }
f21fb3ed
RV		 2789
2790 if (lio->ptp_clock) {
2791 ptp_clock_unregister(lio->ptp_clock);
2792 lio->ptp_clock = NULL;
2793 }
2794
f21fb3ed 2795 dev_info(&oct->pci_dev->dev, "%s interface is stopped\n", netdev->name);
f21fb3ed
RV		 2796
2797 return 0;
2798}
2799
f21fb3ed
RV		 2800/**
2801 * \brief Converts a mask based on net device flags
2802 * @param netdev network device
2803 *
2804 * This routine generates a octnet_ifflags mask from the net device flags
2805 * received from the OS.
2806 */
2807static inline enum octnet_ifflags get_new_flags(struct net_device *netdev)
2808{
2809 enum octnet_ifflags f = OCTNET_IFFLAG_UNICAST;
2810
2811 if (netdev->flags & IFF_PROMISC)
2812 f |= OCTNET_IFFLAG_PROMISC;
2813
2814 if (netdev->flags & IFF_ALLMULTI)
2815 f |= OCTNET_IFFLAG_ALLMULTI;
2816
2817 if (netdev->flags & IFF_MULTICAST) {
2818 f |= OCTNET_IFFLAG_MULTICAST;
2819
2820 /* Accept all multicast addresses if there are more than we
2821 * can handle
2822 */
2823 if (netdev_mc_count(netdev) > MAX_OCTEON_MULTICAST_ADDR)
2824 f |= OCTNET_IFFLAG_ALLMULTI;
2825 }
2826
2827 if (netdev->flags & IFF_BROADCAST)
2828 f |= OCTNET_IFFLAG_BROADCAST;
2829
2830 return f;
2831}
2832
2833/**
2834 * \brief Net device set_multicast_list
2835 * @param netdev network device
2836 */
2837static void liquidio_set_mcast_list(struct net_device *netdev)
2838{
2839 struct lio *lio = GET_LIO(netdev);
2840 struct octeon_device *oct = lio->oct_dev;
2841 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2842 struct netdev_hw_addr *ha;
2843 u64 *mc;
a7d5a3dc 2844 int ret;
f21fb3ed
RV		 2845 int mc_count = min(netdev_mc_count(netdev), MAX_OCTEON_MULTICAST_ADDR);
2846
2847 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2848
2849 /* Create a ctrl pkt command to be sent to core app. */
2850 nctrl.ncmd.u64 = 0;
2851 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_MULTI_LIST;
0cece6c5
RV		 2852 nctrl.ncmd.s.param1 = get_new_flags(netdev);
2853 nctrl.ncmd.s.param2 = mc_count;
f21fb3ed 2854 nctrl.ncmd.s.more = mc_count;
0cece6c5 2855 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2856 nctrl.netpndev = (u64)netdev;
2857 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2858
2859 /* copy all the addresses into the udd */
f21fb3ed
RV		 2860 mc = &nctrl.udd[0];
2861 netdev_for_each_mc_addr(ha, netdev) {
2862 *mc = 0;
2863 memcpy(((u8 *)mc) + 2, ha->addr, ETH_ALEN);
2864 /* no need to swap bytes */
2865
2866 if (++mc > &nctrl.udd[mc_count])
2867 break;
2868 }
2869
2870 /* Apparently, any activity in this call from the kernel has to
2871 * be atomic. So we won't wait for response.
2872 */
2873 nctrl.wait_time = 0;
2874
0cece6c5 2875 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2876 if (ret < 0) {
2877 dev_err(&oct->pci_dev->dev, "DEVFLAGS change failed in core (ret: 0x%x)\n",
2878 ret);
2879 }
2880}
2881
2882/**
2883 * \brief Net device set_mac_address
2884 * @param netdev network device
2885 */
2886static int liquidio_set_mac(struct net_device *netdev, void *p)
2887{
2888 int ret = 0;
2889 struct lio *lio = GET_LIO(netdev);
2890 struct octeon_device *oct = lio->oct_dev;
2891 struct sockaddr *addr = (struct sockaddr *)p;
2892 struct octnic_ctrl_pkt nctrl;
f21fb3ed 2893
0cece6c5 2894 if (!is_valid_ether_addr(addr->sa_data))
f21fb3ed
RV		 2895 return -EADDRNOTAVAIL;
2896
2897 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2898
2899 nctrl.ncmd.u64 = 0;
2900 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
0cece6c5 2901 nctrl.ncmd.s.param1 = 0;
f21fb3ed 2902 nctrl.ncmd.s.more = 1;
0cece6c5 2903 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2904 nctrl.netpndev = (u64)netdev;
2905 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2906 nctrl.wait_time = 100;
2907
2908 nctrl.udd[0] = 0;
2909 /* The MAC Address is presented in network byte order. */
2910 memcpy((u8 *)&nctrl.udd[0] + 2, addr->sa_data, ETH_ALEN);
2911
0cece6c5 2912 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2913 if (ret < 0) {
2914 dev_err(&oct->pci_dev->dev, "MAC Address change failed\n");
2915 return -ENOMEM;
2916 }
2917 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2918 memcpy(((u8 *)&lio->linfo.hw_addr) + 2, addr->sa_data, ETH_ALEN);
2919
2920 return 0;
2921}
2922
2923/**
2924 * \brief Net device get_stats
2925 * @param netdev network device
2926 */
2927static struct net_device_stats *liquidio_get_stats(struct net_device *netdev)
2928{
2929 struct lio *lio = GET_LIO(netdev);
2930 struct net_device_stats *stats = &netdev->stats;
2931 struct octeon_device *oct;
2932 u64 pkts = 0, drop = 0, bytes = 0;
2933 struct oct_droq_stats *oq_stats;
2934 struct oct_iq_stats *iq_stats;
2935 int i, iq_no, oq_no;
2936
2937 oct = lio->oct_dev;
2938
2939 for (i = 0; i < lio->linfo.num_txpciq; i++) {
26236fa9 2940 iq_no = lio->linfo.txpciq[i].s.q_no;
f21fb3ed
RV		 2941 iq_stats = &oct->instr_queue[iq_no]->stats;
2942 pkts += iq_stats->tx_done;
2943 drop += iq_stats->tx_dropped;
2944 bytes += iq_stats->tx_tot_bytes;
2945 }
2946
2947 stats->tx_packets = pkts;
2948 stats->tx_bytes = bytes;
2949 stats->tx_dropped = drop;
2950
2951 pkts = 0;
2952 drop = 0;
2953 bytes = 0;
2954
2955 for (i = 0; i < lio->linfo.num_rxpciq; i++) {
26236fa9 2956 oq_no = lio->linfo.rxpciq[i].s.q_no;
f21fb3ed
RV		 2957 oq_stats = &oct->droq[oq_no]->stats;
2958 pkts += oq_stats->rx_pkts_received;
2959 drop += (oq_stats->rx_dropped +
2960 oq_stats->dropped_nodispatch +
2961 oq_stats->dropped_toomany +
2962 oq_stats->dropped_nomem);
2963 bytes += oq_stats->rx_bytes_received;
2964 }
2965
2966 stats->rx_bytes = bytes;
2967 stats->rx_packets = pkts;
2968 stats->rx_dropped = drop;
2969
2970 return stats;
2971}
2972
2973/**
2974 * \brief Net device change_mtu
2975 * @param netdev network device
2976 */
2977static int liquidio_change_mtu(struct net_device *netdev, int new_mtu)
2978{
2979 struct lio *lio = GET_LIO(netdev);
2980 struct octeon_device *oct = lio->oct_dev;
2981 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2982 int ret = 0;
2983
f21fb3ed
RV		 2984 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2985
2986 nctrl.ncmd.u64 = 0;
2987 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MTU;
0cece6c5
RV		 2988 nctrl.ncmd.s.param1 = new_mtu;
2989 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2990 nctrl.wait_time = 100;
2991 nctrl.netpndev = (u64)netdev;
2992 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2993
0cece6c5 2994 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2995 if (ret < 0) {
2996 dev_err(&oct->pci_dev->dev, "Failed to set MTU\n");
2997 return -1;
2998 }
2999
3000 lio->mtu = new_mtu;
3001
3002 return 0;
3003}
3004
3005/**
3006 * \brief Handler for SIOCSHWTSTAMP ioctl
3007 * @param netdev network device
3008 * @param ifr interface request
3009 * @param cmd command
3010 */
a7d5a3dc 3011static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
f21fb3ed
RV		 3012{
3013 struct hwtstamp_config conf;
3014 struct lio *lio = GET_LIO(netdev);
3015
3016 if (copy_from_user(&conf, ifr->ifr_data, sizeof(conf)))
3017 return -EFAULT;
3018
3019 if (conf.flags)
3020 return -EINVAL;
3021
3022 switch (conf.tx_type) {
3023 case HWTSTAMP_TX_ON:
3024 case HWTSTAMP_TX_OFF:
3025 break;
3026 default:
3027 return -ERANGE;
3028 }
3029
3030 switch (conf.rx_filter) {
3031 case HWTSTAMP_FILTER_NONE:
3032 break;
3033 case HWTSTAMP_FILTER_ALL:
3034 case HWTSTAMP_FILTER_SOME:
3035 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3036 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3037 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3038 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3039 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3040 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3041 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3042 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3043 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3044 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3045 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3046 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
e3412575 3047 case HWTSTAMP_FILTER_NTP_ALL:
f21fb3ed
RV		 3048 conf.rx_filter = HWTSTAMP_FILTER_ALL;
3049 break;
3050 default:
3051 return -ERANGE;
3052 }
3053
3054 if (conf.rx_filter == HWTSTAMP_FILTER_ALL)
3055 ifstate_set(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
3056
3057 else
3058 ifstate_reset(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
3059
3060 return copy_to_user(ifr->ifr_data, &conf, sizeof(conf)) ? -EFAULT : 0;
3061}
3062
3063/**
3064 * \brief ioctl handler
3065 * @param netdev network device
3066 * @param ifr interface request
3067 * @param cmd command
3068 */
3069static int liquidio_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3070{
9feb16ae
PK		 3071 struct lio *lio = GET_LIO(netdev);
3072
f21fb3ed
RV		 3073 switch (cmd) {
3074 case SIOCSHWTSTAMP:
9feb16ae
PK		 3075 if ((lio->oct_dev->chip_id == OCTEON_CN66XX ||
3076 lio->oct_dev->chip_id == OCTEON_CN68XX) && ptp_enable)
3077 return hwtstamp_ioctl(netdev, ifr);
f21fb3ed
RV		 3078 default:
3079 return -EOPNOTSUPP;
3080 }
3081}
3082
3083/**
3084 * \brief handle a Tx timestamp response
3085 * @param status response status
3086 * @param buf pointer to skb
3087 */
3088static void handle_timestamp(struct octeon_device *oct,
3089 u32 status,
3090 void *buf)
3091{
3092 struct octnet_buf_free_info *finfo;
3093 struct octeon_soft_command *sc;
3094 struct oct_timestamp_resp *resp;
3095 struct lio *lio;
3096 struct sk_buff *skb = (struct sk_buff *)buf;
3097
3098 finfo = (struct octnet_buf_free_info *)skb->cb;
3099 lio = finfo->lio;
3100 sc = finfo->sc;
3101 oct = lio->oct_dev;
3102 resp = (struct oct_timestamp_resp *)sc->virtrptr;
3103
3104 if (status != OCTEON_REQUEST_DONE) {
3105 dev_err(&oct->pci_dev->dev, "Tx timestamp instruction failed. Status: %llx\n",
3106 CVM_CAST64(status));
3107 resp->timestamp = 0;
3108 }
3109
3110 octeon_swap_8B_data(&resp->timestamp, 1);
3111
19a6d156 3112 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) != 0)) {
f21fb3ed
RV		 3113 struct skb_shared_hwtstamps ts;
3114 u64 ns = resp->timestamp;
3115
3116 netif_info(lio, tx_done, lio->netdev,
3117 "Got resulting SKBTX_HW_TSTAMP skb=%p ns=%016llu\n",
3118 skb, (unsigned long long)ns);
3119 ts.hwtstamp = ns_to_ktime(ns + lio->ptp_adjust);
3120 skb_tstamp_tx(skb, &ts);
3121 }
3122
3123 octeon_free_soft_command(oct, sc);
cabeb13b 3124 tx_buffer_free(skb);
f21fb3ed
RV		 3125}
3126
3127/* \brief Send a data packet that will be timestamped
3128 * @param oct octeon device
3129 * @param ndata pointer to network data
3130 * @param finfo pointer to private network data
3131 */
3132static inline int send_nic_timestamp_pkt(struct octeon_device *oct,
3133 struct octnic_data_pkt *ndata,
32581245 3134 struct octnet_buf_free_info *finfo)
f21fb3ed
RV		 3135{
3136 int retval;
3137 struct octeon_soft_command *sc;
f21fb3ed
RV		 3138 struct lio *lio;
3139 int ring_doorbell;
6a885b60 3140 u32 len;
f21fb3ed
RV		 3141
3142 lio = finfo->lio;
3143
3144 sc = octeon_alloc_soft_command_resp(oct, &ndata->cmd,
3145 sizeof(struct oct_timestamp_resp));
3146 finfo->sc = sc;
3147
3148 if (!sc) {
3149 dev_err(&oct->pci_dev->dev, "No memory for timestamped data packet\n");
3150 return IQ_SEND_FAILED;
3151 }
3152
3153 if (ndata->reqtype == REQTYPE_NORESP_NET)
3154 ndata->reqtype = REQTYPE_RESP_NET;
3155 else if (ndata->reqtype == REQTYPE_NORESP_NET_SG)
3156 ndata->reqtype = REQTYPE_RESP_NET_SG;
3157
3158 sc->callback = handle_timestamp;
3159 sc->callback_arg = finfo->skb;
3160 sc->iq_no = ndata->q_no;
3161
5b823514
RV		 3162 if (OCTEON_CN23XX_PF(oct))
3163 len = (u32)((struct octeon_instr_ih3 *)
3164 (&sc->cmd.cmd3.ih3))->dlengsz;
3165 else
3166 len = (u32)((struct octeon_instr_ih2 *)
3167 (&sc->cmd.cmd2.ih2))->dlengsz;
f21fb3ed 3168
32581245 3169 ring_doorbell = 1;
5b823514 3170
f21fb3ed 3171 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd,
6a885b60 3172 sc, len, ndata->reqtype);
f21fb3ed 3173
ddc173a6 3174 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 3175 dev_err(&oct->pci_dev->dev, "timestamp data packet failed status: %x\n",
3176 retval);
3177 octeon_free_soft_command(oct, sc);
3178 } else {
3179 netif_info(lio, tx_queued, lio->netdev, "Queued timestamp packet\n");
3180 }
3181
3182 return retval;
3183}
3184
f21fb3ed
RV		 3185/** \brief Transmit networks packets to the Octeon interface
3186 * @param skbuff skbuff struct to be passed to network layer.
3187 * @param netdev pointer to network device
3188 * @returns whether the packet was transmitted to the device okay or not
3189 * (NETDEV_TX_OK or NETDEV_TX_BUSY)
3190 */
3191static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev)
3192{
3193 struct lio *lio;
3194 struct octnet_buf_free_info *finfo;
3195 union octnic_cmd_setup cmdsetup;
3196 struct octnic_data_pkt ndata;
3197 struct octeon_device *oct;
3198 struct oct_iq_stats *stats;
6a885b60
RV		 3199 struct octeon_instr_irh *irh;
3200 union tx_info *tx_info;
26236fa9 3201 int status = 0;
f21fb3ed 3202 int q_idx = 0, iq_no = 0;
32581245 3203 int j;
fcd2b5e3 3204 u64 dptr = 0;
f21fb3ed
RV		 3205 u32 tag = 0;
3206
3207 lio = GET_LIO(netdev);
3208 oct = lio->oct_dev;
3209
3210 if (netif_is_multiqueue(netdev)) {
26236fa9
RV		 3211 q_idx = skb->queue_mapping;
3212 q_idx = (q_idx % (lio->linfo.num_txpciq));
3213 tag = q_idx;
3214 iq_no = lio->linfo.txpciq[q_idx].s.q_no;
f21fb3ed
RV		 3215 } else {
3216 iq_no = lio->txq;
3217 }
3218
3219 stats = &oct->instr_queue[iq_no]->stats;
3220
3221 /* Check for all conditions in which the current packet cannot be
3222 * transmitted.
3223 */
3224 if (!(atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) ||
0cece6c5 3225 (!lio->linfo.link.s.link_up) ||
f21fb3ed
RV		 3226 (skb->len <= 0)) {
3227 netif_info(lio, tx_err, lio->netdev,
3228 "Transmit failed link_status : %d\n",
0cece6c5 3229 lio->linfo.link.s.link_up);
f21fb3ed
RV		 3230 goto lio_xmit_failed;
3231 }
3232
3233 /* Use space in skb->cb to store info used to unmap and
3234 * free the buffers.
3235 */
3236 finfo = (struct octnet_buf_free_info *)skb->cb;
3237 finfo->lio = lio;
3238 finfo->skb = skb;
3239 finfo->sc = NULL;
3240
3241 /* Prepare the attributes for the data to be passed to OSI. */
3242 memset(&ndata, 0, sizeof(struct octnic_data_pkt));
3243
3244 ndata.buf = (void *)finfo;
3245
3246 ndata.q_no = iq_no;
3247
3248 if (netif_is_multiqueue(netdev)) {
3249 if (octnet_iq_is_full(oct, ndata.q_no)) {
3250 /* defer sending if queue is full */
3251 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
3252 ndata.q_no);
3253 stats->tx_iq_busy++;
3254 return NETDEV_TX_BUSY;
3255 }
3256 } else {
3257 if (octnet_iq_is_full(oct, lio->txq)) {
3258 /* defer sending if queue is full */
3259 stats->tx_iq_busy++;
3260 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
a2c64b67 3261 lio->txq);
f21fb3ed
RV		 3262 return NETDEV_TX_BUSY;
3263 }
3264 }
3265 /* pr_info(" XMIT - valid Qs: %d, 1st Q no: %d, cpu: %d, q_no:%d\n",
a2c64b67 3266 * lio->linfo.num_txpciq, lio->txq, cpu, ndata.q_no);
f21fb3ed
RV		 3267 */
3268
3269 ndata.datasize = skb->len;
3270
3271 cmdsetup.u64 = 0;
7275ebfc 3272 cmdsetup.s.iq_no = iq_no;
f21fb3ed 3273
01fb237a
RV		 3274 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3275 if (skb->encapsulation) {
3276 cmdsetup.s.tnl_csum = 1;
3277 stats->tx_vxlan++;
3278 } else {
3279 cmdsetup.s.transport_csum = 1;
3280 }
3281 }
f21fb3ed
RV		 3282 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
3283 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3284 cmdsetup.s.timestamp = 1;
3285 }
3286
3287 if (skb_shinfo(skb)->nr_frags == 0) {
3288 cmdsetup.s.u.datasize = skb->len;
0cece6c5 3289 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
a2c64b67 3290
f21fb3ed 3291 /* Offload checksum calculation for TCP/UDP packets */
6a885b60
RV		 3292 dptr = dma_map_single(&oct->pci_dev->dev,
3293 skb->data,
3294 skb->len,
3295 DMA_TO_DEVICE);
3296 if (dma_mapping_error(&oct->pci_dev->dev, dptr)) {
f21fb3ed
RV		 3297 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 1\n",
3298 __func__);
3299 return NETDEV_TX_BUSY;
3300 }
3301
5b823514
RV		 3302 if (OCTEON_CN23XX_PF(oct))
3303 ndata.cmd.cmd3.dptr = dptr;
3304 else
3305 ndata.cmd.cmd2.dptr = dptr;
6a885b60 3306 finfo->dptr = dptr;
f21fb3ed
RV		 3307 ndata.reqtype = REQTYPE_NORESP_NET;
3308
3309 } else {
3310 int i, frags;
3311 struct skb_frag_struct *frag;
3312 struct octnic_gather *g;
3313
fcd2b5e3
RV		 3314 spin_lock(&lio->glist_lock[q_idx]);
3315 g = (struct octnic_gather *)
3316 list_delete_head(&lio->glist[q_idx]);
3317 spin_unlock(&lio->glist_lock[q_idx]);
f21fb3ed
RV		 3318
3319 if (!g) {
3320 netif_info(lio, tx_err, lio->netdev,
3321 "Transmit scatter gather: glist null!\n");
3322 goto lio_xmit_failed;
3323 }
3324
3325 cmdsetup.s.gather = 1;
3326 cmdsetup.s.u.gatherptrs = (skb_shinfo(skb)->nr_frags + 1);
0cece6c5 3327 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
f21fb3ed
RV		 3328
3329 memset(g->sg, 0, g->sg_size);
3330
3331 g->sg[0].ptr[0] = dma_map_single(&oct->pci_dev->dev,
3332 skb->data,
3333 (skb->len - skb->data_len),
3334 DMA_TO_DEVICE);
3335 if (dma_mapping_error(&oct->pci_dev->dev, g->sg[0].ptr[0])) {
3336 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 2\n",
3337 __func__);
3338 return NETDEV_TX_BUSY;
3339 }
3340 add_sg_size(&g->sg[0], (skb->len - skb->data_len), 0);
3341
3342 frags = skb_shinfo(skb)->nr_frags;
3343 i = 1;
3344 while (frags--) {
3345 frag = &skb_shinfo(skb)->frags[i - 1];
3346
3347 g->sg[(i >> 2)].ptr[(i & 3)] =
3348 dma_map_page(&oct->pci_dev->dev,
3349 frag->page.p,
3350 frag->page_offset,
3351 frag->size,
3352 DMA_TO_DEVICE);
3353
fcd2b5e3
RV		 3354 if (dma_mapping_error(&oct->pci_dev->dev,
3355 g->sg[i >> 2].ptr[i & 3])) {
3356 dma_unmap_single(&oct->pci_dev->dev,
3357 g->sg[0].ptr[0],
3358 skb->len - skb->data_len,
3359 DMA_TO_DEVICE);
3360 for (j = 1; j < i; j++) {
3361 frag = &skb_shinfo(skb)->frags[j - 1];
3362 dma_unmap_page(&oct->pci_dev->dev,
3363 g->sg[j >> 2].ptr[j & 3],
3364 frag->size,
3365 DMA_TO_DEVICE);
3366 }
3367 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 3\n",
3368 __func__);
3369 return NETDEV_TX_BUSY;
3370 }
3371
f21fb3ed
RV		 3372 add_sg_size(&g->sg[(i >> 2)], frag->size, (i & 3));
3373 i++;
3374 }
3375
fcd2b5e3 3376 dptr = g->sg_dma_ptr;
f21fb3ed 3377
5b823514
RV		 3378 if (OCTEON_CN23XX_PF(oct))
3379 ndata.cmd.cmd3.dptr = dptr;
3380 else
3381 ndata.cmd.cmd2.dptr = dptr;
6a885b60 3382 finfo->dptr = dptr;
f21fb3ed
RV		 3383 finfo->g = g;
3384
3385 ndata.reqtype = REQTYPE_NORESP_NET_SG;
3386 }
3387
5b823514
RV		 3388 if (OCTEON_CN23XX_PF(oct)) {
3389 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd3.irh;
3390 tx_info = (union tx_info *)&ndata.cmd.cmd3.ossp[0];
3391 } else {
3392 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd2.irh;
3393 tx_info = (union tx_info *)&ndata.cmd.cmd2.ossp[0];
3394 }
f21fb3ed 3395
6a885b60 3396 if (skb_shinfo(skb)->gso_size) {
f21fb3ed
RV		 3397 tx_info->s.gso_size = skb_shinfo(skb)->gso_size;
3398 tx_info->s.gso_segs = skb_shinfo(skb)->gso_segs;
1f164717 3399 stats->tx_gso++;
f21fb3ed 3400 }
1f164717 3401
0da0b77c
RV		 3402 /* HW insert VLAN tag */
3403 if (skb_vlan_tag_present(skb)) {
3404 irh->priority = skb_vlan_tag_get(skb) >> 13;
3405 irh->vlan = skb_vlan_tag_get(skb) & 0xfff;
3406 }
f21fb3ed 3407
f21fb3ed 3408 if (unlikely(cmdsetup.s.timestamp))
32581245 3409 status = send_nic_timestamp_pkt(oct, &ndata, finfo);
f21fb3ed 3410 else
32581245 3411 status = octnet_send_nic_data_pkt(oct, &ndata);
f21fb3ed
RV		 3412 if (status == IQ_SEND_FAILED)
3413 goto lio_xmit_failed;
3414
3415 netif_info(lio, tx_queued, lio->netdev, "Transmit queued successfully\n");
3416
3417 if (status == IQ_SEND_STOP)
3418 stop_q(lio->netdev, q_idx);
3419
860e9538 3420 netif_trans_update(netdev);
f21fb3ed 3421
80c8eae6
SB		 3422 if (tx_info->s.gso_segs)
3423 stats->tx_done += tx_info->s.gso_segs;
1f164717
RV		 3424 else
3425 stats->tx_done++;
80c8eae6 3426 stats->tx_tot_bytes += ndata.datasize;
f21fb3ed
RV		 3427
3428 return NETDEV_TX_OK;
3429
3430lio_xmit_failed:
3431 stats->tx_dropped++;
3432 netif_info(lio, tx_err, lio->netdev, "IQ%d Transmit dropped:%llu\n",
3433 iq_no, stats->tx_dropped);
6a885b60
RV		 3434 if (dptr)
3435 dma_unmap_single(&oct->pci_dev->dev, dptr,
3436 ndata.datasize, DMA_TO_DEVICE);
cabeb13b 3437 tx_buffer_free(skb);
f21fb3ed
RV		 3438 return NETDEV_TX_OK;
3439}
3440
3441/** \brief Network device Tx timeout
3442 * @param netdev pointer to network device
3443 */
3444static void liquidio_tx_timeout(struct net_device *netdev)
3445{
3446 struct lio *lio;
3447
3448 lio = GET_LIO(netdev);
3449
3450 netif_info(lio, tx_err, lio->netdev,
3451 "Transmit timeout tx_dropped:%ld, waking up queues now!!\n",
3452 netdev->stats.tx_dropped);
860e9538 3453 netif_trans_update(netdev);
f21fb3ed
RV		 3454 txqs_wake(netdev);
3455}
3456
63245f25
RV		 3457static int liquidio_vlan_rx_add_vid(struct net_device *netdev,
3458 __be16 proto __attribute__((unused)),
3459 u16 vid)
3460{
3461 struct lio *lio = GET_LIO(netdev);
3462 struct octeon_device *oct = lio->oct_dev;
3463 struct octnic_ctrl_pkt nctrl;
3464 int ret = 0;
3465
3466 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3467
3468 nctrl.ncmd.u64 = 0;
3469 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER;
3470 nctrl.ncmd.s.param1 = vid;
3471 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3472 nctrl.wait_time = 100;
3473 nctrl.netpndev = (u64)netdev;
3474 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3475
3476 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3477 if (ret < 0) {
3478 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
3479 ret);
3480 }
3481
3482 return ret;
3483}
3484
3485static int liquidio_vlan_rx_kill_vid(struct net_device *netdev,
3486 __be16 proto __attribute__((unused)),
3487 u16 vid)
3488{
3489 struct lio *lio = GET_LIO(netdev);
3490 struct octeon_device *oct = lio->oct_dev;
3491 struct octnic_ctrl_pkt nctrl;
3492 int ret = 0;
3493
3494 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3495
3496 nctrl.ncmd.u64 = 0;
3497 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER;
3498 nctrl.ncmd.s.param1 = vid;
3499 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3500 nctrl.wait_time = 100;
3501 nctrl.netpndev = (u64)netdev;
3502 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3503
3504 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3505 if (ret < 0) {
3506 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
3507 ret);
3508 }
3509 return ret;
3510}
3511
01fb237a
RV		 3512/** Sending command to enable/disable RX checksum offload
3513 * @param netdev pointer to network device
3514 * @param command OCTNET_CMD_TNL_RX_CSUM_CTL
3515 * @param rx_cmd_bit OCTNET_CMD_RXCSUM_ENABLE/
3516 * OCTNET_CMD_RXCSUM_DISABLE
3517 * @returns SUCCESS or FAILURE
3518 */
c41419b0
NMG		 3519static int liquidio_set_rxcsum_command(struct net_device *netdev, int command,
3520 u8 rx_cmd)
01fb237a
RV		 3521{
3522 struct lio *lio = GET_LIO(netdev);
3523 struct octeon_device *oct = lio->oct_dev;
3524 struct octnic_ctrl_pkt nctrl;
3525 int ret = 0;
3526
0c264588
FM		 3527 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3528
01fb237a
RV		 3529 nctrl.ncmd.u64 = 0;
3530 nctrl.ncmd.s.cmd = command;
3531 nctrl.ncmd.s.param1 = rx_cmd;
3532 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3533 nctrl.wait_time = 100;
3534 nctrl.netpndev = (u64)netdev;
3535 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3536
3537 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3538 if (ret < 0) {
3539 dev_err(&oct->pci_dev->dev,
3540 "DEVFLAGS RXCSUM change failed in core(ret:0x%x)\n",
3541 ret);
3542 }
3543 return ret;
3544}
3545
3546/** Sending command to add/delete VxLAN UDP port to firmware
3547 * @param netdev pointer to network device
3548 * @param command OCTNET_CMD_VXLAN_PORT_CONFIG
3549 * @param vxlan_port VxLAN port to be added or deleted
3550 * @param vxlan_cmd_bit OCTNET_CMD_VXLAN_PORT_ADD,
3551 * OCTNET_CMD_VXLAN_PORT_DEL
3552 * @returns SUCCESS or FAILURE
3553 */
3554static int liquidio_vxlan_port_command(struct net_device *netdev, int command,
3555 u16 vxlan_port, u8 vxlan_cmd_bit)
3556{
3557 struct lio *lio = GET_LIO(netdev);
3558 struct octeon_device *oct = lio->oct_dev;
3559 struct octnic_ctrl_pkt nctrl;
3560 int ret = 0;
3561
0c264588
FM		 3562 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3563
01fb237a
RV		 3564 nctrl.ncmd.u64 = 0;
3565 nctrl.ncmd.s.cmd = command;
3566 nctrl.ncmd.s.more = vxlan_cmd_bit;
3567 nctrl.ncmd.s.param1 = vxlan_port;
3568 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3569 nctrl.wait_time = 100;
3570 nctrl.netpndev = (u64)netdev;
3571 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3572
3573 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3574 if (ret < 0) {
3575 dev_err(&oct->pci_dev->dev,
3576 "VxLAN port add/delete failed in core (ret:0x%x)\n",
3577 ret);
3578 }
3579 return ret;
3580}
3581
f21fb3ed
RV		 3582/** \brief Net device fix features
3583 * @param netdev pointer to network device
3584 * @param request features requested
3585 * @returns updated features list
3586 */
3587static netdev_features_t liquidio_fix_features(struct net_device *netdev,
3588 netdev_features_t request)
3589{
3590 struct lio *lio = netdev_priv(netdev);
3591
3592 if ((request & NETIF_F_RXCSUM) &&
3593 !(lio->dev_capability & NETIF_F_RXCSUM))
3594 request &= ~NETIF_F_RXCSUM;
3595
3596 if ((request & NETIF_F_HW_CSUM) &&
3597 !(lio->dev_capability & NETIF_F_HW_CSUM))
3598 request &= ~NETIF_F_HW_CSUM;
3599
3600 if ((request & NETIF_F_TSO) && !(lio->dev_capability & NETIF_F_TSO))
3601 request &= ~NETIF_F_TSO;
3602
3603 if ((request & NETIF_F_TSO6) && !(lio->dev_capability & NETIF_F_TSO6))
3604 request &= ~NETIF_F_TSO6;
3605
3606 if ((request & NETIF_F_LRO) && !(lio->dev_capability & NETIF_F_LRO))
3607 request &= ~NETIF_F_LRO;
3608
3609 /*Disable LRO if RXCSUM is off */
3610 if (!(request & NETIF_F_RXCSUM) && (netdev->features & NETIF_F_LRO) &&
3611 (lio->dev_capability & NETIF_F_LRO))
3612 request &= ~NETIF_F_LRO;
3613
836d57e5
PK		 3614 if ((request & NETIF_F_HW_VLAN_CTAG_FILTER) &&
3615 !(lio->dev_capability & NETIF_F_HW_VLAN_CTAG_FILTER))
3616 request &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3617
f21fb3ed
RV		 3618 return request;
3619}
3620
3621/** \brief Net device set features
3622 * @param netdev pointer to network device
3623 * @param features features to enable/disable
3624 */
3625static int liquidio_set_features(struct net_device *netdev,
3626 netdev_features_t features)
3627{
3628 struct lio *lio = netdev_priv(netdev);
3629
836d57e5
PK		 3630 if ((features & NETIF_F_LRO) &&
3631 (lio->dev_capability & NETIF_F_LRO) &&
3632 !(netdev->features & NETIF_F_LRO))
0cece6c5
RV		 3633 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
3634 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed 3635 else if (!(features & NETIF_F_LRO) &&
836d57e5
PK		 3636 (lio->dev_capability & NETIF_F_LRO) &&
3637 (netdev->features & NETIF_F_LRO))
0cece6c5
RV		 3638 liquidio_set_feature(netdev, OCTNET_CMD_LRO_DISABLE,
3639 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed 3640
01fb237a
RV		 3641 /* Sending command to firmware to enable/disable RX checksum
3642 * offload settings using ethtool
3643 */
3644 if (!(netdev->features & NETIF_F_RXCSUM) &&
3645 (lio->enc_dev_capability & NETIF_F_RXCSUM) &&
3646 (features & NETIF_F_RXCSUM))
3647 liquidio_set_rxcsum_command(netdev,
3648 OCTNET_CMD_TNL_RX_CSUM_CTL,
3649 OCTNET_CMD_RXCSUM_ENABLE);
3650 else if ((netdev->features & NETIF_F_RXCSUM) &&
3651 (lio->enc_dev_capability & NETIF_F_RXCSUM) &&
3652 !(features & NETIF_F_RXCSUM))
3653 liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL,
3654 OCTNET_CMD_RXCSUM_DISABLE);
3655
836d57e5
PK		 3656 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) &&
3657 (lio->dev_capability & NETIF_F_HW_VLAN_CTAG_FILTER) &&
3658 !(netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
3659 liquidio_set_feature(netdev, OCTNET_CMD_VLAN_FILTER_CTL,
3660 OCTNET_CMD_VLAN_FILTER_ENABLE);
3661 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) &&
3662 (lio->dev_capability & NETIF_F_HW_VLAN_CTAG_FILTER) &&
3663 (netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
3664 liquidio_set_feature(netdev, OCTNET_CMD_VLAN_FILTER_CTL,
3665 OCTNET_CMD_VLAN_FILTER_DISABLE);
3666
f21fb3ed
RV		 3667 return 0;
3668}
3669
01fb237a
RV		 3670static void liquidio_add_vxlan_port(struct net_device *netdev,
3671 struct udp_tunnel_info *ti)
3672{
3673 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3674 return;
3675
3676 liquidio_vxlan_port_command(netdev,
3677 OCTNET_CMD_VXLAN_PORT_CONFIG,
3678 htons(ti->port),
3679 OCTNET_CMD_VXLAN_PORT_ADD);
3680}
3681
3682static void liquidio_del_vxlan_port(struct net_device *netdev,
3683 struct udp_tunnel_info *ti)
3684{
3685 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3686 return;
3687
3688 liquidio_vxlan_port_command(netdev,
3689 OCTNET_CMD_VXLAN_PORT_CONFIG,
3690 htons(ti->port),
3691 OCTNET_CMD_VXLAN_PORT_DEL);
3692}
3693
86dea55b
RV		 3694static int __liquidio_set_vf_mac(struct net_device *netdev, int vfidx,
3695 u8 *mac, bool is_admin_assigned)
3696{
3697 struct lio *lio = GET_LIO(netdev);
3698 struct octeon_device *oct = lio->oct_dev;
3699 struct octnic_ctrl_pkt nctrl;
3700
3701 if (!is_valid_ether_addr(mac))
3702 return -EINVAL;
3703
3704 if (vfidx < 0 || vfidx >= oct->sriov_info.max_vfs)
3705 return -EINVAL;
3706
3707 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3708
3709 nctrl.ncmd.u64 = 0;
3710 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
3711 /* vfidx is 0 based, but vf_num (param1) is 1 based */
3712 nctrl.ncmd.s.param1 = vfidx + 1;
3713 nctrl.ncmd.s.param2 = (is_admin_assigned ? 1 : 0);
3714 nctrl.ncmd.s.more = 1;
3715 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
9549c6c8
RF		 3716 nctrl.netpndev = (u64)netdev;
3717 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
86dea55b
RV		 3718 nctrl.wait_time = LIO_CMD_WAIT_TM;
3719
3720 nctrl.udd[0] = 0;
3721 /* The MAC Address is presented in network byte order. */
3722 ether_addr_copy((u8 *)&nctrl.udd[0] + 2, mac);
3723
3724 oct->sriov_info.vf_macaddr[vfidx] = nctrl.udd[0];
3725
3726 octnet_send_nic_ctrl_pkt(oct, &nctrl);
3727
3728 return 0;
3729}
3730
3731static int liquidio_set_vf_mac(struct net_device *netdev, int vfidx, u8 *mac)
3732{
3733 struct lio *lio = GET_LIO(netdev);
3734 struct octeon_device *oct = lio->oct_dev;
3735 int retval;
3736
0d9a5997
FM		 3737 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
3738 return -EINVAL;
3739
86dea55b
RV		 3740 retval = __liquidio_set_vf_mac(netdev, vfidx, mac, true);
3741 if (!retval)
3742 cn23xx_tell_vf_its_macaddr_changed(oct, vfidx, mac);
3743
3744 return retval;
3745}
3746
3747static int liquidio_set_vf_vlan(struct net_device *netdev, int vfidx,
3748 u16 vlan, u8 qos, __be16 vlan_proto)
3749{
3750 struct lio *lio = GET_LIO(netdev);
3751 struct octeon_device *oct = lio->oct_dev;
3752 struct octnic_ctrl_pkt nctrl;
3753 u16 vlantci;
3754
3755 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
3756 return -EINVAL;
3757
3758 if (vlan_proto != htons(ETH_P_8021Q))
3759 return -EPROTONOSUPPORT;
3760
3761 if (vlan >= VLAN_N_VID || qos > 7)
3762 return -EINVAL;
3763
3764 if (vlan)
3765 vlantci = vlan | (u16)qos << VLAN_PRIO_SHIFT;
3766 else
3767 vlantci = 0;
3768
3769 if (oct->sriov_info.vf_vlantci[vfidx] == vlantci)
3770 return 0;
3771
3772 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3773
3774 if (vlan)
3775 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER;
3776 else
3777 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER;
3778
3779 nctrl.ncmd.s.param1 = vlantci;
3780 nctrl.ncmd.s.param2 =
3781 vfidx + 1; /* vfidx is 0 based, but vf_num (param2) is 1 based */
3782 nctrl.ncmd.s.more = 0;
3783 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3784 nctrl.cb_fn = 0;
3785 nctrl.wait_time = LIO_CMD_WAIT_TM;
3786
3787 octnet_send_nic_ctrl_pkt(oct, &nctrl);
3788
3789 oct->sriov_info.vf_vlantci[vfidx] = vlantci;
3790
3791 return 0;
3792}
3793
3794static int liquidio_get_vf_config(struct net_device *netdev, int vfidx,
3795 struct ifla_vf_info *ivi)
3796{
3797 struct lio *lio = GET_LIO(netdev);
3798 struct octeon_device *oct = lio->oct_dev;
3799 u8 *macaddr;
3800
3801 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
3802 return -EINVAL;
3803
3804 ivi->vf = vfidx;
3805 macaddr = 2 + (u8 *)&oct->sriov_info.vf_macaddr[vfidx];
3806 ether_addr_copy(&ivi->mac[0], macaddr);
3807 ivi->vlan = oct->sriov_info.vf_vlantci[vfidx] & VLAN_VID_MASK;
3808 ivi->qos = oct->sriov_info.vf_vlantci[vfidx] >> VLAN_PRIO_SHIFT;
3809 ivi->linkstate = oct->sriov_info.vf_linkstate[vfidx];
3810 return 0;
3811}
3812
3813static int liquidio_set_vf_link_state(struct net_device *netdev, int vfidx,
3814 int linkstate)
3815{
3816 struct lio *lio = GET_LIO(netdev);
3817 struct octeon_device *oct = lio->oct_dev;
3818 struct octnic_ctrl_pkt nctrl;
3819
3820 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
3821 return -EINVAL;
3822
3823 if (oct->sriov_info.vf_linkstate[vfidx] == linkstate)
3824 return 0;
3825
3826 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3827 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_VF_LINKSTATE;
3828 nctrl.ncmd.s.param1 =
3829 vfidx + 1; /* vfidx is 0 based, but vf_num (param1) is 1 based */
3830 nctrl.ncmd.s.param2 = linkstate;
3831 nctrl.ncmd.s.more = 0;
3832 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3833 nctrl.cb_fn = 0;
3834 nctrl.wait_time = LIO_CMD_WAIT_TM;
3835
3836 octnet_send_nic_ctrl_pkt(oct, &nctrl);
3837
3838 oct->sriov_info.vf_linkstate[vfidx] = linkstate;
3839
3840 return 0;
3841}
3842
97a25326 3843static const struct net_device_ops lionetdevops = {
f21fb3ed
RV		 3844 .ndo_open = liquidio_open,
3845 .ndo_stop = liquidio_stop,
3846 .ndo_start_xmit = liquidio_xmit,
3847 .ndo_get_stats = liquidio_get_stats,
3848 .ndo_set_mac_address = liquidio_set_mac,
3849 .ndo_set_rx_mode = liquidio_set_mcast_list,
3850 .ndo_tx_timeout = liquidio_tx_timeout,
63245f25
RV		 3851
3852 .ndo_vlan_rx_add_vid = liquidio_vlan_rx_add_vid,
3853 .ndo_vlan_rx_kill_vid = liquidio_vlan_rx_kill_vid,
f21fb3ed
RV		 3854 .ndo_change_mtu = liquidio_change_mtu,
3855 .ndo_do_ioctl = liquidio_ioctl,
3856 .ndo_fix_features = liquidio_fix_features,
3857 .ndo_set_features = liquidio_set_features,
01fb237a
RV		 3858 .ndo_udp_tunnel_add = liquidio_add_vxlan_port,
3859 .ndo_udp_tunnel_del = liquidio_del_vxlan_port,
86dea55b
RV		 3860 .ndo_set_vf_mac = liquidio_set_vf_mac,
3861 .ndo_set_vf_vlan = liquidio_set_vf_vlan,
3862 .ndo_get_vf_config = liquidio_get_vf_config,
3863 .ndo_set_vf_link_state = liquidio_set_vf_link_state,
f21fb3ed
RV		 3864};
3865
3866/** \brief Entry point for the liquidio module
3867 */
3868static int __init liquidio_init(void)
3869{
3870 int i;
3871 struct handshake *hs;
3872
3873 init_completion(&first_stage);
3874
97a25326 3875 octeon_init_device_list(OCTEON_CONFIG_TYPE_DEFAULT);
f21fb3ed
RV		 3876
3877 if (liquidio_init_pci())
3878 return -EINVAL;
3879
3880 wait_for_completion_timeout(&first_stage, msecs_to_jiffies(1000));
3881
3882 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3883 hs = &handshake[i];
3884 if (hs->pci_dev) {
3885 wait_for_completion(&hs->init);
3886 if (!hs->init_ok) {
3887 /* init handshake failed */
3888 dev_err(&hs->pci_dev->dev,
3889 "Failed to init device\n");
3890 liquidio_deinit_pci();
3891 return -EIO;
3892 }
3893 }
3894 }
3895
3896 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3897 hs = &handshake[i];
3898 if (hs->pci_dev) {
3899 wait_for_completion_timeout(&hs->started,
3900 msecs_to_jiffies(30000));
3901 if (!hs->started_ok) {
3902 /* starter handshake failed */
3903 dev_err(&hs->pci_dev->dev,
3904 "Firmware failed to start\n");
3905 liquidio_deinit_pci();
3906 return -EIO;
3907 }
3908 }
3909 }
3910
3911 return 0;
3912}
3913
5b173cf9 3914static int lio_nic_info(struct octeon_recv_info *recv_info, void *buf)
f21fb3ed
RV		 3915{
3916 struct octeon_device *oct = (struct octeon_device *)buf;
3917 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
0cece6c5 3918 int gmxport = 0;
f21fb3ed
RV		 3919 union oct_link_status *ls;
3920 int i;
3921
c4ee5d81 3922 if (recv_pkt->buffer_size[0] != (sizeof(*ls) + OCT_DROQ_INFO_SIZE)) {
f21fb3ed
RV		 3923 dev_err(&oct->pci_dev->dev, "Malformed NIC_INFO, len=%d, ifidx=%d\n",
3924 recv_pkt->buffer_size[0],
0cece6c5 3925 recv_pkt->rh.r_nic_info.gmxport);
f21fb3ed
RV		 3926 goto nic_info_err;
3927 }
3928
0cece6c5 3929 gmxport = recv_pkt->rh.r_nic_info.gmxport;
c4ee5d81
PK		 3930 ls = (union oct_link_status *)(get_rbd(recv_pkt->buffer_ptr[0]) +
3931 OCT_DROQ_INFO_SIZE);
f21fb3ed
RV		 3932
3933 octeon_swap_8B_data((u64 *)ls, (sizeof(union oct_link_status)) >> 3);
0cece6c5
RV		 3934 for (i = 0; i < oct->ifcount; i++) {
3935 if (oct->props[i].gmxport == gmxport) {
3936 update_link_status(oct->props[i].netdev, ls);
3937 break;
3938 }
3939 }
f21fb3ed
RV		 3940
3941nic_info_err:
3942 for (i = 0; i < recv_pkt->buffer_count; i++)
3943 recv_buffer_free(recv_pkt->buffer_ptr[i]);
3944 octeon_free_recv_info(recv_info);
3945 return 0;
3946}
3947
3948/**
3949 * \brief Setup network interfaces
3950 * @param octeon_dev octeon device
3951 *
3952 * Called during init time for each device. It assumes the NIC
3953 * is already up and running. The link information for each
3954 * interface is passed in link_info.
3955 */
3956static int setup_nic_devices(struct octeon_device *octeon_dev)
3957{
3958 struct lio *lio = NULL;
3959 struct net_device *netdev;
3960 u8 mac[6], i, j;
3961 struct octeon_soft_command *sc;
3962 struct liquidio_if_cfg_context *ctx;
3963 struct liquidio_if_cfg_resp *resp;
3964 struct octdev_props *props;
26236fa9 3965 int retval, num_iqueues, num_oqueues;
f21fb3ed
RV		 3966 union oct_nic_if_cfg if_cfg;
3967 unsigned int base_queue;
3968 unsigned int gmx_port_id;
83101ce3 3969 u32 resp_size, ctx_size, data_size;
0cece6c5 3970 u32 ifidx_or_pfnum;
83101ce3 3971 struct lio_version *vdata;
f21fb3ed
RV		 3972
3973 /* This is to handle link status changes */
3974 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3975 OPCODE_NIC_INFO,
3976 lio_nic_info, octeon_dev);
3977
3978 /* REQTYPE_RESP_NET and REQTYPE_SOFT_COMMAND do not have free functions.
3979 * They are handled directly.
3980 */
3981 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET,
3982 free_netbuf);
3983
3984 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET_SG,
3985 free_netsgbuf);
3986
3987 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_RESP_NET_SG,
3988 free_netsgbuf_with_resp);
3989
3990 for (i = 0; i < octeon_dev->ifcount; i++) {
3991 resp_size = sizeof(struct liquidio_if_cfg_resp);
3992 ctx_size = sizeof(struct liquidio_if_cfg_context);
83101ce3 3993 data_size = sizeof(struct lio_version);
f21fb3ed 3994 sc = (struct octeon_soft_command *)
83101ce3 3995 octeon_alloc_soft_command(octeon_dev, data_size,
f21fb3ed
RV		 3996 resp_size, ctx_size);
3997 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
3998 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
83101ce3
RV		 3999 vdata = (struct lio_version *)sc->virtdptr;
4000
4001 *((u64 *)vdata) = 0;
4002 vdata->major = cpu_to_be16(LIQUIDIO_BASE_MAJOR_VERSION);
4003 vdata->minor = cpu_to_be16(LIQUIDIO_BASE_MINOR_VERSION);
4004 vdata->micro = cpu_to_be16(LIQUIDIO_BASE_MICRO_VERSION);
f21fb3ed 4005
e86b1ab6
RV		 4006 if (OCTEON_CN23XX_PF(octeon_dev)) {
4007 num_iqueues = octeon_dev->sriov_info.num_pf_rings;
4008 num_oqueues = octeon_dev->sriov_info.num_pf_rings;
4009 base_queue = octeon_dev->sriov_info.pf_srn;
4010
4011 gmx_port_id = octeon_dev->pf_num;
4012 ifidx_or_pfnum = octeon_dev->pf_num;
4013 } else {
4014 num_iqueues = CFG_GET_NUM_TXQS_NIC_IF(
4015 octeon_get_conf(octeon_dev), i);
4016 num_oqueues = CFG_GET_NUM_RXQS_NIC_IF(
4017 octeon_get_conf(octeon_dev), i);
4018 base_queue = CFG_GET_BASE_QUE_NIC_IF(
4019 octeon_get_conf(octeon_dev), i);
4020 gmx_port_id = CFG_GET_GMXID_NIC_IF(
4021 octeon_get_conf(octeon_dev), i);
4022 ifidx_or_pfnum = i;
4023 }
3dcef2ca 4024
f21fb3ed
RV		 4025 dev_dbg(&octeon_dev->pci_dev->dev,
4026 "requesting config for interface %d, iqs %d, oqs %d\n",
0cece6c5 4027 ifidx_or_pfnum, num_iqueues, num_oqueues);
a7d5a3dc 4028 WRITE_ONCE(ctx->cond, 0);
f21fb3ed
RV		 4029 ctx->octeon_id = lio_get_device_id(octeon_dev);
4030 init_waitqueue_head(&ctx->wc);
4031
4032 if_cfg.u64 = 0;
4033 if_cfg.s.num_iqueues = num_iqueues;
4034 if_cfg.s.num_oqueues = num_oqueues;
4035 if_cfg.s.base_queue = base_queue;
4036 if_cfg.s.gmx_port_id = gmx_port_id;
0cece6c5
RV		 4037
4038 sc->iq_no = 0;
4039
f21fb3ed 4040 octeon_prepare_soft_command(octeon_dev, sc, OPCODE_NIC,
0cece6c5 4041 OPCODE_NIC_IF_CFG, 0,
f21fb3ed
RV		 4042 if_cfg.u64, 0);
4043
4044 sc->callback = if_cfg_callback;
4045 sc->callback_arg = sc;
55893a63 4046 sc->wait_time = 3000;
f21fb3ed
RV		 4047
4048 retval = octeon_send_soft_command(octeon_dev, sc);
ddc173a6 4049 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 4050 dev_err(&octeon_dev->pci_dev->dev,
4051 "iq/oq config failed status: %x\n",
4052 retval);
4053 /* Soft instr is freed by driver in case of failure. */
4054 goto setup_nic_dev_fail;
4055 }
4056
4057 /* Sleep on a wait queue till the cond flag indicates that the
4058 * response arrived or timed-out.
4059 */
afdf841f
RV		 4060 if (sleep_cond(&ctx->wc, &ctx->cond) == -EINTR) {
4061 dev_err(&octeon_dev->pci_dev->dev, "Wait interrupted\n");
4062 goto setup_nic_wait_intr;
4063 }
4064
f21fb3ed
RV		 4065 retval = resp->status;
4066 if (retval) {
4067 dev_err(&octeon_dev->pci_dev->dev, "iq/oq config failed\n");
4068 goto setup_nic_dev_fail;
4069 }
4070
4071 octeon_swap_8B_data((u64 *)(&resp->cfg_info),
4072 (sizeof(struct liquidio_if_cfg_info)) >> 3);
4073
4074 num_iqueues = hweight64(resp->cfg_info.iqmask);
4075 num_oqueues = hweight64(resp->cfg_info.oqmask);
4076
4077 if (!(num_iqueues) || !(num_oqueues)) {
4078 dev_err(&octeon_dev->pci_dev->dev,
4079 "Got bad iqueues (%016llx) or oqueues (%016llx) from firmware.\n",
4080 resp->cfg_info.iqmask,
4081 resp->cfg_info.oqmask);
4082 goto setup_nic_dev_fail;
4083 }
4084 dev_dbg(&octeon_dev->pci_dev->dev,
4085 "interface %d, iqmask %016llx, oqmask %016llx, numiqueues %d, numoqueues %d\n",
4086 i, resp->cfg_info.iqmask, resp->cfg_info.oqmask,
4087 num_iqueues, num_oqueues);
4088 netdev = alloc_etherdev_mq(LIO_SIZE, num_iqueues);
4089
4090 if (!netdev) {
4091 dev_err(&octeon_dev->pci_dev->dev, "Device allocation failed\n");
4092 goto setup_nic_dev_fail;
4093 }
4094
0cece6c5 4095 SET_NETDEV_DEV(netdev, &octeon_dev->pci_dev->dev);
f21fb3ed 4096
f21fb3ed
RV		 4097 /* Associate the routines that will handle different
4098 * netdev tasks.
4099 */
4100 netdev->netdev_ops = &lionetdevops;
4101
4102 lio = GET_LIO(netdev);
4103
4104 memset(lio, 0, sizeof(struct lio));
4105
0cece6c5
RV		 4106 lio->ifidx = ifidx_or_pfnum;
4107
4108 props = &octeon_dev->props[i];
4109 props->gmxport = resp->cfg_info.linfo.gmxport;
4110 props->netdev = netdev;
f21fb3ed
RV		 4111
4112 lio->linfo.num_rxpciq = num_oqueues;
4113 lio->linfo.num_txpciq = num_iqueues;
f21fb3ed 4114 for (j = 0; j < num_oqueues; j++) {
26236fa9
RV		 4115 lio->linfo.rxpciq[j].u64 =
4116 resp->cfg_info.linfo.rxpciq[j].u64;
f21fb3ed 4117 }
f21fb3ed 4118 for (j = 0; j < num_iqueues; j++) {
26236fa9
RV		 4119 lio->linfo.txpciq[j].u64 =
4120 resp->cfg_info.linfo.txpciq[j].u64;
f21fb3ed
RV		 4121 }
4122 lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr;
4123 lio->linfo.gmxport = resp->cfg_info.linfo.gmxport;
4124 lio->linfo.link.u64 = resp->cfg_info.linfo.link.u64;
4125
4126 lio->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
4127
e86b1ab6
RV		 4128 if (OCTEON_CN23XX_PF(octeon_dev) ||
4129 OCTEON_CN6XXX(octeon_dev)) {
4130 lio->dev_capability = NETIF_F_HIGHDMA
4131 | NETIF_F_IP_CSUM
4132 | NETIF_F_IPV6_CSUM
4133 | NETIF_F_SG | NETIF_F_RXCSUM
4134 | NETIF_F_GRO
4135 | NETIF_F_TSO | NETIF_F_TSO6
4136 | NETIF_F_LRO;
4137 }
f21fb3ed
RV		 4138 netif_set_gso_max_size(netdev, OCTNIC_GSO_MAX_SIZE);
4139
01fb237a
RV		 4140 /* Copy of transmit encapsulation capabilities:
4141 * TSO, TSO6, Checksums for this device
4142 */
4143 lio->enc_dev_capability = NETIF_F_IP_CSUM
4144 | NETIF_F_IPV6_CSUM
4145 | NETIF_F_GSO_UDP_TUNNEL
4146 | NETIF_F_HW_CSUM | NETIF_F_SG
4147 | NETIF_F_RXCSUM
4148 | NETIF_F_TSO | NETIF_F_TSO6
4149 | NETIF_F_LRO;
4150
4151 netdev->hw_enc_features = (lio->enc_dev_capability &
4152 ~NETIF_F_LRO);
4153
4154 lio->dev_capability |= NETIF_F_GSO_UDP_TUNNEL;
4155
f21fb3ed 4156 netdev->vlan_features = lio->dev_capability;
0da0b77c 4157 /* Add any unchangeable hw features */
63245f25
RV		 4158 lio->dev_capability |= NETIF_F_HW_VLAN_CTAG_FILTER |
4159 NETIF_F_HW_VLAN_CTAG_RX |
0da0b77c
RV		 4160 NETIF_F_HW_VLAN_CTAG_TX;
4161
4162 netdev->features = (lio->dev_capability & ~NETIF_F_LRO);
f21fb3ed
RV		 4163
4164 netdev->hw_features = lio->dev_capability;
0da0b77c
RV		 4165 /*HW_VLAN_RX and HW_VLAN_FILTER is always on*/
4166 netdev->hw_features = netdev->hw_features &
4167 ~NETIF_F_HW_VLAN_CTAG_RX;
f21fb3ed 4168
109cc165
JW		 4169 /* MTU range: 68 - 16000 */
4170 netdev->min_mtu = LIO_MIN_MTU_SIZE;
4171 netdev->max_mtu = LIO_MAX_MTU_SIZE;
4172
f21fb3ed
RV		 4173 /* Point to the properties for octeon device to which this
4174 * interface belongs.
4175 */
4176 lio->oct_dev = octeon_dev;
4177 lio->octprops = props;
4178 lio->netdev = netdev;
f21fb3ed
RV		 4179
4180 dev_dbg(&octeon_dev->pci_dev->dev,
4181 "if%d gmx: %d hw_addr: 0x%llx\n", i,
4182 lio->linfo.gmxport, CVM_CAST64(lio->linfo.hw_addr));
4183
86dea55b
RV		 4184 for (j = 0; j < octeon_dev->sriov_info.max_vfs; j++) {
4185 u8 vfmac[ETH_ALEN];
4186
4187 random_ether_addr(&vfmac[0]);
4188 if (__liquidio_set_vf_mac(netdev, j,
4189 &vfmac[0], false)) {
4190 dev_err(&octeon_dev->pci_dev->dev,
4191 "Error setting VF%d MAC address\n",
4192 j);
4193 goto setup_nic_dev_fail;
4194 }
4195 }
4196
f21fb3ed
RV		 4197 /* 64-bit swap required on LE machines */
4198 octeon_swap_8B_data(&lio->linfo.hw_addr, 1);
4199 for (j = 0; j < 6; j++)
4200 mac[j] = *((u8 *)(((u8 *)&lio->linfo.hw_addr) + 2 + j));
4201
4202 /* Copy MAC Address to OS network device structure */
4203
4204 ether_addr_copy(netdev->dev_addr, mac);
4205
26236fa9
RV		 4206 /* By default all interfaces on a single Octeon uses the same
4207 * tx and rx queues
4208 */
4209 lio->txq = lio->linfo.txpciq[0].s.q_no;
4210 lio->rxq = lio->linfo.rxpciq[0].s.q_no;
0cece6c5 4211 if (setup_io_queues(octeon_dev, i)) {
f21fb3ed
RV		 4212 dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n");
4213 goto setup_nic_dev_fail;
4214 }
4215
4216 ifstate_set(lio, LIO_IFSTATE_DROQ_OPS);
4217
f21fb3ed
RV		 4218 lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq);
4219 lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq);
4220
fcd2b5e3 4221 if (setup_glists(octeon_dev, lio, num_iqueues)) {
f21fb3ed
RV		 4222 dev_err(&octeon_dev->pci_dev->dev,
4223 "Gather list allocation failed\n");
4224 goto setup_nic_dev_fail;
4225 }
4226
4227 /* Register ethtool support */
4228 liquidio_set_ethtool_ops(netdev);
30136395
RV		 4229 if (lio->oct_dev->chip_id == OCTEON_CN23XX_PF_VID)
4230 octeon_dev->priv_flags = OCT_PRIV_FLAG_DEFAULT;
4231 else
4232 octeon_dev->priv_flags = 0x0;
f21fb3ed 4233
0cece6c5 4234 if (netdev->features & NETIF_F_LRO)
a2c64b67
RV		 4235 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
4236 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed 4237
836d57e5
PK		 4238 liquidio_set_feature(netdev, OCTNET_CMD_VLAN_FILTER_CTL,
4239 OCTNET_CMD_VLAN_FILTER_ENABLE);
63245f25 4240
f21fb3ed 4241 if ((debug != -1) && (debug & NETIF_MSG_HW))
63245f25
RV		 4242 liquidio_set_feature(netdev,
4243 OCTNET_CMD_VERBOSE_ENABLE, 0);
f21fb3ed 4244
7b6b6c95
RV		 4245 if (setup_link_status_change_wq(netdev))
4246 goto setup_nic_dev_fail;
4247
031d4f12
SB		 4248 if (setup_rx_oom_poll_fn(netdev))
4249 goto setup_nic_dev_fail;
4250
f21fb3ed
RV		 4251 /* Register the network device with the OS */
4252 if (register_netdev(netdev)) {
4253 dev_err(&octeon_dev->pci_dev->dev, "Device registration failed\n");
4254 goto setup_nic_dev_fail;
4255 }
4256
4257 dev_dbg(&octeon_dev->pci_dev->dev,
4258 "Setup NIC ifidx:%d mac:%02x%02x%02x%02x%02x%02x\n",
4259 i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
4260 netif_carrier_off(netdev);
0cece6c5 4261 lio->link_changes++;
f21fb3ed
RV		 4262
4263 ifstate_set(lio, LIO_IFSTATE_REGISTERED);
4264
01fb237a
RV		 4265 /* Sending command to firmware to enable Rx checksum offload
4266 * by default at the time of setup of Liquidio driver for
4267 * this device
4268 */
4269 liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL,
4270 OCTNET_CMD_RXCSUM_ENABLE);
4271 liquidio_set_feature(netdev, OCTNET_CMD_TNL_TX_CSUM_CTL,
4272 OCTNET_CMD_TXCSUM_ENABLE);
4273
f21fb3ed
RV		 4274 dev_dbg(&octeon_dev->pci_dev->dev,
4275 "NIC ifidx:%d Setup successful\n", i);
4276
4277 octeon_free_soft_command(octeon_dev, sc);
4278 }
4279
4280 return 0;
4281
4282setup_nic_dev_fail:
4283
4284 octeon_free_soft_command(octeon_dev, sc);
4285
afdf841f
RV		 4286setup_nic_wait_intr:
4287
f21fb3ed
RV		 4288 while (i--) {
4289 dev_err(&octeon_dev->pci_dev->dev,
4290 "NIC ifidx:%d Setup failed\n", i);
4291 liquidio_destroy_nic_device(octeon_dev, i);
4292 }
4293 return -ENODEV;
4294}
4295
ca6139ff
RV		 4296#ifdef CONFIG_PCI_IOV
4297static int octeon_enable_sriov(struct octeon_device *oct)
4298{
4299 unsigned int num_vfs_alloced = oct->sriov_info.num_vfs_alloced;
4300 struct pci_dev *vfdev;
4301 int err;
4302 u32 u;
4303
4304 if (OCTEON_CN23XX_PF(oct) && num_vfs_alloced) {
4305 err = pci_enable_sriov(oct->pci_dev,
4306 oct->sriov_info.num_vfs_alloced);
4307 if (err) {
4308 dev_err(&oct->pci_dev->dev,
4309 "OCTEON: Failed to enable PCI sriov: %d\n",
4310 err);
4311 oct->sriov_info.num_vfs_alloced = 0;
4312 return err;
4313 }
4314 oct->sriov_info.sriov_enabled = 1;
4315
4316 /* init lookup table that maps DPI ring number to VF pci_dev
4317 * struct pointer
4318 */
4319 u = 0;
4320 vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
4321 OCTEON_CN23XX_VF_VID, NULL);
4322 while (vfdev) {
4323 if (vfdev->is_virtfn &&
4324 (vfdev->physfn == oct->pci_dev)) {
4325 oct->sriov_info.dpiring_to_vfpcidev_lut[u] =
4326 vfdev;
4327 u += oct->sriov_info.rings_per_vf;
4328 }
4329 vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
4330 OCTEON_CN23XX_VF_VID, vfdev);
4331 }
4332 }
4333
4334 return num_vfs_alloced;
4335}
4336
4337static int lio_pci_sriov_disable(struct octeon_device *oct)
4338{
4339 int u;
4340
4341 if (pci_vfs_assigned(oct->pci_dev)) {
4342 dev_err(&oct->pci_dev->dev, "VFs are still assigned to VMs.\n");
4343 return -EPERM;
4344 }
4345
4346 pci_disable_sriov(oct->pci_dev);
4347
4348 u = 0;
4349 while (u < MAX_POSSIBLE_VFS) {
4350 oct->sriov_info.dpiring_to_vfpcidev_lut[u] = NULL;
4351 u += oct->sriov_info.rings_per_vf;
4352 }
4353
4354 oct->sriov_info.num_vfs_alloced = 0;
4355 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d disabled VFs\n",
4356 oct->pf_num);
4357
4358 return 0;
4359}
4360
4361static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs)
4362{
4363 struct octeon_device *oct = pci_get_drvdata(dev);
4364 int ret = 0;
4365
4366 if ((num_vfs == oct->sriov_info.num_vfs_alloced) &&
4367 (oct->sriov_info.sriov_enabled)) {
4368 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d already enabled num_vfs:%d\n",
4369 oct->pf_num, num_vfs);
4370 return 0;
4371 }
4372
4373 if (!num_vfs) {
4374 ret = lio_pci_sriov_disable(oct);
4375 } else if (num_vfs > oct->sriov_info.max_vfs) {
4376 dev_err(&oct->pci_dev->dev,
4377 "OCTEON: Max allowed VFs:%d user requested:%d",
4378 oct->sriov_info.max_vfs, num_vfs);
4379 ret = -EPERM;
4380 } else {
4381 oct->sriov_info.num_vfs_alloced = num_vfs;
4382 ret = octeon_enable_sriov(oct);
4383 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d num_vfs:%d\n",
4384 oct->pf_num, num_vfs);
4385 }
4386
4387 return ret;
4388}
4389#endif
4390
f21fb3ed
RV		 4391/**
4392 * \brief initialize the NIC
4393 * @param oct octeon device
4394 *
4395 * This initialization routine is called once the Octeon device application is
4396 * up and running
4397 */
4398static int liquidio_init_nic_module(struct octeon_device *oct)
4399{
0cece6c5 4400 int i, retval = 0;
f21fb3ed
RV		 4401 int num_nic_ports = CFG_GET_NUM_NIC_PORTS(octeon_get_conf(oct));
4402
4403 dev_dbg(&oct->pci_dev->dev, "Initializing network interfaces\n");
4404
4405 /* only default iq and oq were initialized
4406 * initialize the rest as well
4407 */
4408 /* run port_config command for each port */
4409 oct->ifcount = num_nic_ports;
4410
30136395 4411 memset(oct->props, 0, sizeof(struct octdev_props) * num_nic_ports);
f21fb3ed 4412
0cece6c5
RV		 4413 for (i = 0; i < MAX_OCTEON_LINKS; i++)
4414 oct->props[i].gmxport = -1;
4415
f21fb3ed
RV		 4416 retval = setup_nic_devices(oct);
4417 if (retval) {
4418 dev_err(&oct->pci_dev->dev, "Setup NIC devices failed\n");
4419 goto octnet_init_failure;
4420 }
4421
4422 liquidio_ptp_init(oct);
4423
f21fb3ed
RV		 4424 dev_dbg(&oct->pci_dev->dev, "Network interfaces ready\n");
4425
4426 return retval;
4427
4428octnet_init_failure:
4429
4430 oct->ifcount = 0;
4431
4432 return retval;
4433}
4434
4435/**
4436 * \brief starter callback that invokes the remaining initialization work after
4437 * the NIC is up and running.
4438 * @param octptr work struct work_struct
4439 */
4440static void nic_starter(struct work_struct *work)
4441{
4442 struct octeon_device *oct;
4443 struct cavium_wk *wk = (struct cavium_wk *)work;
4444
4445 oct = (struct octeon_device *)wk->ctxptr;
4446
4447 if (atomic_read(&oct->status) == OCT_DEV_RUNNING)
4448 return;
4449
4450 /* If the status of the device is CORE_OK, the core
4451 * application has reported its application type. Call
4452 * any registered handlers now and move to the RUNNING
4453 * state.
4454 */
4455 if (atomic_read(&oct->status) != OCT_DEV_CORE_OK) {
4456 schedule_delayed_work(&oct->nic_poll_work.work,
4457 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
4458 return;
4459 }
4460
4461 atomic_set(&oct->status, OCT_DEV_RUNNING);
4462
4463 if (oct->app_mode && oct->app_mode == CVM_DRV_NIC_APP) {
4464 dev_dbg(&oct->pci_dev->dev, "Starting NIC module\n");
4465
4466 if (liquidio_init_nic_module(oct))
4467 dev_err(&oct->pci_dev->dev, "NIC initialization failed\n");
4468 else
4469 handshake[oct->octeon_id].started_ok = 1;
4470 } else {
4471 dev_err(&oct->pci_dev->dev,
4472 "Unexpected application running on NIC (%d). Check firmware.\n",
4473 oct->app_mode);
4474 }
4475
4476 complete(&handshake[oct->octeon_id].started);
4477}
4478
86dea55b
RV		 4479static int
4480octeon_recv_vf_drv_notice(struct octeon_recv_info *recv_info, void *buf)
4481{
4482 struct octeon_device *oct = (struct octeon_device *)buf;
4483 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
4484 int i, notice, vf_idx;
bb54be58 4485 bool cores_crashed;
86dea55b
RV		 4486 u64 *data, vf_num;
4487
4488 notice = recv_pkt->rh.r.ossp;
c4ee5d81 4489 data = (u64 *)(get_rbd(recv_pkt->buffer_ptr[0]) + OCT_DROQ_INFO_SIZE);
86dea55b
RV		 4490
4491 /* the first 64-bit word of data is the vf_num */
4492 vf_num = data[0];
4493 octeon_swap_8B_data(&vf_num, 1);
4494 vf_idx = (int)vf_num - 1;
4495
bb54be58
FM		 4496 cores_crashed = READ_ONCE(oct->cores_crashed);
4497
86dea55b
RV		 4498 if (notice == VF_DRV_LOADED) {
4499 if (!(oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx))) {
4500 oct->sriov_info.vf_drv_loaded_mask |= BIT_ULL(vf_idx);
4501 dev_info(&oct->pci_dev->dev,
4502 "driver for VF%d was loaded\n", vf_idx);
bb54be58
FM		 4503 if (!cores_crashed)
4504 try_module_get(THIS_MODULE);
86dea55b
RV		 4505 }
4506 } else if (notice == VF_DRV_REMOVED) {
4507 if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx)) {
4508 oct->sriov_info.vf_drv_loaded_mask &= ~BIT_ULL(vf_idx);
4509 dev_info(&oct->pci_dev->dev,
4510 "driver for VF%d was removed\n", vf_idx);
bb54be58
FM		 4511 if (!cores_crashed)
4512 module_put(THIS_MODULE);
86dea55b
RV		 4513 }
4514 } else if (notice == VF_DRV_MACADDR_CHANGED) {
4515 u8 *b = (u8 *)&data[1];
4516
4517 oct->sriov_info.vf_macaddr[vf_idx] = data[1];
4518 dev_info(&oct->pci_dev->dev,
4519 "VF driver changed VF%d's MAC address to %pM\n",
4520 vf_idx, b + 2);
4521 }
4522
4523 for (i = 0; i < recv_pkt->buffer_count; i++)
4524 recv_buffer_free(recv_pkt->buffer_ptr[i]);
4525 octeon_free_recv_info(recv_info);
4526
4527 return 0;
4528}
4529
f21fb3ed
RV		 4530/**
4531 * \brief Device initialization for each Octeon device that is probed
4532 * @param octeon_dev octeon device
4533 */
4534static int octeon_device_init(struct octeon_device *octeon_dev)
4535{
4536 int j, ret;
c0eab5b3 4537 int fw_loaded = 0;
d3d7e6c6 4538 char bootcmd[] = "\n";
f21fb3ed
RV		 4539 struct octeon_device_priv *oct_priv =
4540 (struct octeon_device_priv *)octeon_dev->priv;
4541 atomic_set(&octeon_dev->status, OCT_DEV_BEGIN_STATE);
4542
4543 /* Enable access to the octeon device and make its DMA capability
4544 * known to the OS.
4545 */
4546 if (octeon_pci_os_setup(octeon_dev))
4547 return 1;
4548
515e752d
RV		 4549 atomic_set(&octeon_dev->status, OCT_DEV_PCI_ENABLE_DONE);
4550
f21fb3ed
RV		 4551 /* Identify the Octeon type and map the BAR address space. */
4552 if (octeon_chip_specific_setup(octeon_dev)) {
4553 dev_err(&octeon_dev->pci_dev->dev, "Chip specific setup failed\n");
4554 return 1;
4555 }
4556
4557 atomic_set(&octeon_dev->status, OCT_DEV_PCI_MAP_DONE);
4558
e1e3ce62
RF		 4559 /* Only add a reference after setting status 'OCT_DEV_PCI_MAP_DONE',
4560 * since that is what is required for the reference to be removed
4561 * during de-initialization (see 'octeon_destroy_resources').
4562 */
4563 octeon_register_device(octeon_dev, octeon_dev->pci_dev->bus->number,
4564 PCI_SLOT(octeon_dev->pci_dev->devfn),
4565 PCI_FUNC(octeon_dev->pci_dev->devfn),
4566 true);
4567
f21fb3ed
RV		 4568 octeon_dev->app_mode = CVM_DRV_INVALID_APP;
4569
c0eab5b3
RV		 4570 if (OCTEON_CN23XX_PF(octeon_dev)) {
4571 if (!cn23xx_fw_loaded(octeon_dev)) {
4572 fw_loaded = 0;
7cc61db9
FM		 4573 if (!fw_type_is_none()) {
4574 /* Do a soft reset of the Octeon device. */
4575 if (octeon_dev->fn_list.soft_reset(octeon_dev))
4576 return 1;
4577 /* things might have changed */
4578 if (!cn23xx_fw_loaded(octeon_dev))
4579 fw_loaded = 0;
4580 else
4581 fw_loaded = 1;
4582 }
c0eab5b3
RV		 4583 } else {
4584 fw_loaded = 1;
4585 }
4586 } else if (octeon_dev->fn_list.soft_reset(octeon_dev)) {
f21fb3ed 4587 return 1;
c0eab5b3 4588 }
f21fb3ed
RV		 4589
4590 /* Initialize the dispatch mechanism used to push packets arriving on
4591 * Octeon Output queues.
4592 */
4593 if (octeon_init_dispatch_list(octeon_dev))
4594 return 1;
4595
4596 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
4597 OPCODE_NIC_CORE_DRV_ACTIVE,
4598 octeon_core_drv_init,
4599 octeon_dev);
4600
86dea55b
RV		 4601 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
4602 OPCODE_NIC_VF_DRV_NOTICE,
4603 octeon_recv_vf_drv_notice, octeon_dev);
f21fb3ed
RV		 4604 INIT_DELAYED_WORK(&octeon_dev->nic_poll_work.work, nic_starter);
4605 octeon_dev->nic_poll_work.ctxptr = (void *)octeon_dev;
4606 schedule_delayed_work(&octeon_dev->nic_poll_work.work,
4607 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
4608
4609 atomic_set(&octeon_dev->status, OCT_DEV_DISPATCH_INIT_DONE);
4610
c865cdf1
RV		 4611 if (octeon_set_io_queues_off(octeon_dev)) {
4612 dev_err(&octeon_dev->pci_dev->dev, "setting io queues off failed\n");
4613 return 1;
4614 }
f21fb3ed 4615
3451b97c
RV		 4616 if (OCTEON_CN23XX_PF(octeon_dev)) {
4617 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
4618 if (ret) {
4619 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Failed to configure device registers\n");
4620 return ret;
4621 }
4622 }
4623
4624 /* Initialize soft command buffer pool
4625 */
4626 if (octeon_setup_sc_buffer_pool(octeon_dev)) {
4627 dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n");
4628 return 1;
4629 }
4630 atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
4631
f21fb3ed
RV		 4632 /* Setup the data structures that manage this Octeon's Input queues. */
4633 if (octeon_setup_instr_queues(octeon_dev)) {
4634 dev_err(&octeon_dev->pci_dev->dev,
4635 "instruction queue initialization failed\n");
f21fb3ed
RV		 4636 return 1;
4637 }
4638 atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE);
4639
f21fb3ed
RV		 4640 /* Initialize lists to manage the requests of different types that
4641 * arrive from user & kernel applications for this octeon device.
4642 */
4643 if (octeon_setup_response_list(octeon_dev)) {
4644 dev_err(&octeon_dev->pci_dev->dev, "Response list allocation failed\n");
4645 return 1;
4646 }
4647 atomic_set(&octeon_dev->status, OCT_DEV_RESP_LIST_INIT_DONE);
4648
4649 if (octeon_setup_output_queues(octeon_dev)) {
4650 dev_err(&octeon_dev->pci_dev->dev, "Output queue initialization failed\n");
1e0d30fe 4651 return 1;
f21fb3ed
RV		 4652 }
4653
4654 atomic_set(&octeon_dev->status, OCT_DEV_DROQ_INIT_DONE);
4655
5b07aee1 4656 if (OCTEON_CN23XX_PF(octeon_dev)) {
5d65556b
RV		 4657 if (octeon_dev->fn_list.setup_mbox(octeon_dev)) {
4658 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Mailbox setup failed\n");
4659 return 1;
4660 }
4661 atomic_set(&octeon_dev->status, OCT_DEV_MBOX_SETUP_DONE);
4662
5b07aee1
RV		 4663 if (octeon_allocate_ioq_vector(octeon_dev)) {
4664 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: ioq vector allocation failed\n");
4665 return 1;
4666 }
515e752d 4667 atomic_set(&octeon_dev->status, OCT_DEV_MSIX_ALLOC_VECTOR_DONE);
5b07aee1
RV		 4668
4669 } else {
4670 /* The input and output queue registers were setup earlier (the
4671 * queues were not enabled). Any additional registers
4672 * that need to be programmed should be done now.
4673 */
4674 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
4675 if (ret) {
4676 dev_err(&octeon_dev->pci_dev->dev,
4677 "Failed to configure device registers\n");
4678 return ret;
4679 }
f21fb3ed
RV		 4680 }
4681
4682 /* Initialize the tasklet that handles output queue packet processing.*/
4683 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing droq tasklet\n");
4684 tasklet_init(&oct_priv->droq_tasklet, octeon_droq_bh,
4685 (unsigned long)octeon_dev);
4686
4687 /* Setup the interrupt handler and record the INT SUM register address
4688 */
1e0d30fe
RV		 4689 if (octeon_setup_interrupt(octeon_dev))
4690 return 1;
f21fb3ed
RV		 4691
4692 /* Enable Octeon device interrupts */
5b07aee1 4693 octeon_dev->fn_list.enable_interrupt(octeon_dev, OCTEON_ALL_INTR);
f21fb3ed 4694
515e752d
RV		 4695 atomic_set(&octeon_dev->status, OCT_DEV_INTR_SET_DONE);
4696
f21fb3ed 4697 /* Enable the input and output queues for this Octeon device */
1b7c55c4
RV		 4698 ret = octeon_dev->fn_list.enable_io_queues(octeon_dev);
4699 if (ret) {
4700 dev_err(&octeon_dev->pci_dev->dev, "Failed to enable input/output queues");
4701 return ret;
4702 }
f21fb3ed
RV		 4703
4704 atomic_set(&octeon_dev->status, OCT_DEV_IO_QUEUES_DONE);
4705
c0eab5b3
RV		 4706 if ((!OCTEON_CN23XX_PF(octeon_dev)) || !fw_loaded) {
4707 dev_dbg(&octeon_dev->pci_dev->dev, "Waiting for DDR initialization...\n");
4708 if (!ddr_timeout) {
4709 dev_info(&octeon_dev->pci_dev->dev,
4710 "WAITING. Set ddr_timeout to non-zero value to proceed with initialization.\n");
4711 }
f21fb3ed 4712
c0eab5b3 4713 schedule_timeout_uninterruptible(HZ * LIO_RESET_SECS);
f21fb3ed 4714
c0eab5b3
RV		 4715 /* Wait for the octeon to initialize DDR after the soft-reset.*/
4716 while (!ddr_timeout) {
4717 set_current_state(TASK_INTERRUPTIBLE);
4718 if (schedule_timeout(HZ / 10)) {
4719 /* user probably pressed Control-C */
4720 return 1;
4721 }
4722 }
4723 ret = octeon_wait_for_ddr_init(octeon_dev, &ddr_timeout);
4724 if (ret) {
4725 dev_err(&octeon_dev->pci_dev->dev,
4726 "DDR not initialized. Please confirm that board is configured to boot from Flash, ret: %d\n",
4727 ret);
4b129ae3
RV		 4728 return 1;
4729 }
f21fb3ed 4730
c0eab5b3
RV		 4731 if (octeon_wait_for_bootloader(octeon_dev, 1000)) {
4732 dev_err(&octeon_dev->pci_dev->dev, "Board not responding\n");
4733 return 1;
4734 }
f21fb3ed 4735
c0eab5b3
RV		 4736 /* Divert uboot to take commands from host instead. */
4737 ret = octeon_console_send_cmd(octeon_dev, bootcmd, 50);
d3d7e6c6 4738
c0eab5b3
RV		 4739 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing consoles\n");
4740 ret = octeon_init_consoles(octeon_dev);
4741 if (ret) {
4742 dev_err(&octeon_dev->pci_dev->dev, "Could not access board consoles\n");
4743 return 1;
4744 }
4745 ret = octeon_add_console(octeon_dev, 0);
4746 if (ret) {
4747 dev_err(&octeon_dev->pci_dev->dev, "Could not access board console\n");
4748 return 1;
4749 }
f21fb3ed 4750
c0eab5b3 4751 atomic_set(&octeon_dev->status, OCT_DEV_CONSOLE_INIT_DONE);
f21fb3ed 4752
c0eab5b3
RV		 4753 dev_dbg(&octeon_dev->pci_dev->dev, "Loading firmware\n");
4754 ret = load_firmware(octeon_dev);
4755 if (ret) {
4756 dev_err(&octeon_dev->pci_dev->dev, "Could not load firmware to board\n");
4757 return 1;
4758 }
4759 /* set bit 1 of SLI_SCRATCH_1 to indicate that firmware is
4760 * loaded
4761 */
4762 if (OCTEON_CN23XX_PF(octeon_dev))
4763 octeon_write_csr64(octeon_dev, CN23XX_SLI_SCRATCH1,
4764 2ULL);
f21fb3ed
RV		 4765 }
4766
4767 handshake[octeon_dev->octeon_id].init_ok = 1;
4768 complete(&handshake[octeon_dev->octeon_id].init);
4769
4770 atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK);
4771
4772 /* Send Credit for Octeon Output queues. Credits are always sent after
4773 * the output queue is enabled.
4774 */
4775 for (j = 0; j < octeon_dev->num_oqs; j++)
4776 writel(octeon_dev->droq[j]->max_count,
4777 octeon_dev->droq[j]->pkts_credit_reg);
4778
4779 /* Packets can start arriving on the output queues from this point. */
f21fb3ed
RV		 4780 return 0;
4781}
4782
4783/**
4784 * \brief Exits the module
4785 */
4786static void __exit liquidio_exit(void)
4787{
4788 liquidio_deinit_pci();
4789
4790 pr_info("LiquidIO network module is now unloaded\n");
4791}
4792
4793module_init(liquidio_init);
4794module_exit(liquidio_exit);
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