]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/ethernet/cavium/liquidio/lio_main.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
liquidio: tx rx interrupt moderation
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / cavium / liquidio / lio_main.c
CommitLineData
f21fb3ed
RV		 1/**********************************************************************
2* Author: Cavium, Inc.
3*
4* Contact: support@cavium.com
5* Please include "LiquidIO" in the subject.
6*
7* Copyright (c) 2003-2015 Cavium, Inc.
8*
9* This file is free software; you can redistribute it and/or modify
10* it under the terms of the GNU General Public License, Version 2, as
11* published by the Free Software Foundation.
12*
13* This file is distributed in the hope that it will be useful, but
14* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16* NONINFRINGEMENT. See the GNU General Public License for more
17* details.
18*
19* This file may also be available under a different license from Cavium.
20* Contact Cavium, Inc. for more information
21**********************************************************************/
22#include <linux/version.h>
23#include <linux/module.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/pci.h>
27#include <linux/pci_ids.h>
28#include <linux/ip.h>
5b173cf9 29#include <net/ip.h>
f21fb3ed
RV		 30#include <linux/ipv6.h>
31#include <linux/net_tstamp.h>
32#include <linux/if_vlan.h>
33#include <linux/firmware.h>
34#include <linux/ethtool.h>
35#include <linux/ptp_clock_kernel.h>
36#include <linux/types.h>
37#include <linux/list.h>
38#include <linux/workqueue.h>
39#include <linux/interrupt.h>
40#include "octeon_config.h"
41#include "liquidio_common.h"
42#include "octeon_droq.h"
43#include "octeon_iq.h"
44#include "response_manager.h"
45#include "octeon_device.h"
46#include "octeon_nic.h"
47#include "octeon_main.h"
48#include "octeon_network.h"
49#include "cn66xx_regs.h"
50#include "cn66xx_device.h"
51#include "cn68xx_regs.h"
52#include "cn68xx_device.h"
53#include "liquidio_image.h"
54
55MODULE_AUTHOR("Cavium Networks, <support@cavium.com>");
56MODULE_DESCRIPTION("Cavium LiquidIO Intelligent Server Adapter Driver");
57MODULE_LICENSE("GPL");
58MODULE_VERSION(LIQUIDIO_VERSION);
59MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210SV_NAME LIO_FW_NAME_SUFFIX);
60MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210NV_NAME LIO_FW_NAME_SUFFIX);
61MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_410NV_NAME LIO_FW_NAME_SUFFIX);
62
63static int ddr_timeout = 10000;
64module_param(ddr_timeout, int, 0644);
65MODULE_PARM_DESC(ddr_timeout,
66 "Number of milliseconds to wait for DDR initialization. 0 waits for ddr_timeout to be set to non-zero value before starting to check");
67
68static u32 console_bitmask;
69module_param(console_bitmask, int, 0644);
70MODULE_PARM_DESC(console_bitmask,
71 "Bitmask indicating which consoles have debug output redirected to syslog.");
72
73#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
74
75static int debug = -1;
76module_param(debug, int, 0644);
77MODULE_PARM_DESC(debug, "NETIF_MSG debug bits");
78
79static char fw_type[LIO_MAX_FW_TYPE_LEN];
80module_param_string(fw_type, fw_type, sizeof(fw_type), 0000);
81MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded. Default \"nic\"");
82
83static int conf_type;
84module_param(conf_type, int, 0);
85MODULE_PARM_DESC(conf_type, "select octeon configuration 0 default 1 ovs");
86
a5b37888
RV		 87static int ptp_enable = 1;
88
f21fb3ed
RV		 89/* Bit mask values for lio->ifstate */
90#define LIO_IFSTATE_DROQ_OPS 0x01
91#define LIO_IFSTATE_REGISTERED 0x02
92#define LIO_IFSTATE_RUNNING 0x04
93#define LIO_IFSTATE_RX_TIMESTAMP_ENABLED 0x08
94
95/* Polling interval for determining when NIC application is alive */
96#define LIQUIDIO_STARTER_POLL_INTERVAL_MS 100
97
98/* runtime link query interval */
99#define LIQUIDIO_LINK_QUERY_INTERVAL_MS 1000
100
101struct liquidio_if_cfg_context {
102 int octeon_id;
103
104 wait_queue_head_t wc;
105
106 int cond;
107};
108
109struct liquidio_if_cfg_resp {
110 u64 rh;
111 struct liquidio_if_cfg_info cfg_info;
112 u64 status;
113};
114
115struct oct_link_status_resp {
116 u64 rh;
117 struct oct_link_info link_info;
118 u64 status;
119};
120
121struct oct_timestamp_resp {
122 u64 rh;
123 u64 timestamp;
124 u64 status;
125};
126
127#define OCT_TIMESTAMP_RESP_SIZE (sizeof(struct oct_timestamp_resp))
128
129union tx_info {
130 u64 u64;
131 struct {
132#ifdef __BIG_ENDIAN_BITFIELD
133 u16 gso_size;
134 u16 gso_segs;
135 u32 reserved;
136#else
137 u32 reserved;
138 u16 gso_segs;
139 u16 gso_size;
140#endif
141 } s;
142};
143
144/** Octeon device properties to be used by the NIC module.
145 * Each octeon device in the system will be represented
146 * by this structure in the NIC module.
147 */
148
149#define OCTNIC_MAX_SG (MAX_SKB_FRAGS)
150
151#define OCTNIC_GSO_MAX_HEADER_SIZE 128
152#define OCTNIC_GSO_MAX_SIZE (GSO_MAX_SIZE - OCTNIC_GSO_MAX_HEADER_SIZE)
153
154/** Structure of a node in list of gather components maintained by
155 * NIC driver for each network device.
156 */
157struct octnic_gather {
158 /** List manipulation. Next and prev pointers. */
159 struct list_head list;
160
161 /** Size of the gather component at sg in bytes. */
162 int sg_size;
163
164 /** Number of bytes that sg was adjusted to make it 8B-aligned. */
165 int adjust;
166
167 /** Gather component that can accommodate max sized fragment list
168 * received from the IP layer.
169 */
170 struct octeon_sg_entry *sg;
fcd2b5e3
RV		 171
172 u64 sg_dma_ptr;
f21fb3ed
RV		 173};
174
175/** This structure is used by NIC driver to store information required
176 * to free the sk_buff when the packet has been fetched by Octeon.
177 * Bytes offset below assume worst-case of a 64-bit system.
178 */
179struct octnet_buf_free_info {
180 /** Bytes 1-8. Pointer to network device private structure. */
181 struct lio *lio;
182
183 /** Bytes 9-16. Pointer to sk_buff. */
184 struct sk_buff *skb;
185
186 /** Bytes 17-24. Pointer to gather list. */
187 struct octnic_gather *g;
188
189 /** Bytes 25-32. Physical address of skb->data or gather list. */
190 u64 dptr;
191
192 /** Bytes 33-47. Piggybacked soft command, if any */
193 struct octeon_soft_command *sc;
194};
195
196struct handshake {
197 struct completion init;
198 struct completion started;
199 struct pci_dev *pci_dev;
200 int init_ok;
201 int started_ok;
202};
203
204struct octeon_device_priv {
205 /** Tasklet structures for this device. */
206 struct tasklet_struct droq_tasklet;
207 unsigned long napi_mask;
208};
209
210static int octeon_device_init(struct octeon_device *);
211static void liquidio_remove(struct pci_dev *pdev);
212static int liquidio_probe(struct pci_dev *pdev,
213 const struct pci_device_id *ent);
214
215static struct handshake handshake[MAX_OCTEON_DEVICES];
216static struct completion first_stage;
217
5b173cf9 218static void octeon_droq_bh(unsigned long pdev)
f21fb3ed
RV		 219{
220 int q_no;
221 int reschedule = 0;
222 struct octeon_device *oct = (struct octeon_device *)pdev;
223 struct octeon_device_priv *oct_priv =
224 (struct octeon_device_priv *)oct->priv;
225
226 /* for (q_no = 0; q_no < oct->num_oqs; q_no++) { */
63da8404
RV		 227 for (q_no = 0; q_no < MAX_OCTEON_OUTPUT_QUEUES(oct); q_no++) {
228 if (!(oct->io_qmask.oq & (1ULL << q_no)))
f21fb3ed
RV		 229 continue;
230 reschedule |= octeon_droq_process_packets(oct, oct->droq[q_no],
231 MAX_PACKET_BUDGET);
232 }
233
234 if (reschedule)
235 tasklet_schedule(&oct_priv->droq_tasklet);
236}
237
5b173cf9 238static int lio_wait_for_oq_pkts(struct octeon_device *oct)
f21fb3ed
RV		 239{
240 struct octeon_device_priv *oct_priv =
241 (struct octeon_device_priv *)oct->priv;
242 int retry = 100, pkt_cnt = 0, pending_pkts = 0;
243 int i;
244
245 do {
246 pending_pkts = 0;
247
63da8404
RV		 248 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
249 if (!(oct->io_qmask.oq & (1ULL << i)))
f21fb3ed
RV		 250 continue;
251 pkt_cnt += octeon_droq_check_hw_for_pkts(oct,
252 oct->droq[i]);
253 }
254 if (pkt_cnt > 0) {
255 pending_pkts += pkt_cnt;
256 tasklet_schedule(&oct_priv->droq_tasklet);
257 }
258 pkt_cnt = 0;
259 schedule_timeout_uninterruptible(1);
260
261 } while (retry-- && pending_pkts);
262
263 return pkt_cnt;
264}
265
266void octeon_report_tx_completion_to_bql(void *txq, unsigned int pkts_compl,
267 unsigned int bytes_compl)
268{
269 struct netdev_queue *netdev_queue = txq;
270
271 netdev_tx_completed_queue(netdev_queue, pkts_compl, bytes_compl);
272}
273
274void octeon_update_tx_completion_counters(void *buf, int reqtype,
275 unsigned int *pkts_compl,
276 unsigned int *bytes_compl)
277{
278 struct octnet_buf_free_info *finfo;
279 struct sk_buff *skb = NULL;
280 struct octeon_soft_command *sc;
281
282 switch (reqtype) {
283 case REQTYPE_NORESP_NET:
284 case REQTYPE_NORESP_NET_SG:
285 finfo = buf;
286 skb = finfo->skb;
287 break;
288
289 case REQTYPE_RESP_NET_SG:
290 case REQTYPE_RESP_NET:
291 sc = buf;
292 skb = sc->callback_arg;
293 break;
294
295 default:
296 return;
297 }
298
299 (*pkts_compl)++;
300 *bytes_compl += skb->len;
301}
302
303void octeon_report_sent_bytes_to_bql(void *buf, int reqtype)
304{
305 struct octnet_buf_free_info *finfo;
306 struct sk_buff *skb;
307 struct octeon_soft_command *sc;
308 struct netdev_queue *txq;
309
310 switch (reqtype) {
311 case REQTYPE_NORESP_NET:
312 case REQTYPE_NORESP_NET_SG:
313 finfo = buf;
314 skb = finfo->skb;
315 break;
316
317 case REQTYPE_RESP_NET_SG:
318 case REQTYPE_RESP_NET:
319 sc = buf;
320 skb = sc->callback_arg;
321 break;
322
323 default:
324 return;
325 }
326
327 txq = netdev_get_tx_queue(skb->dev, skb_get_queue_mapping(skb));
328 netdev_tx_sent_queue(txq, skb->len);
329}
330
331int octeon_console_debug_enabled(u32 console)
332{
333 return (console_bitmask >> (console)) & 0x1;
334}
335
336/**
337 * \brief Forces all IO queues off on a given device
338 * @param oct Pointer to Octeon device
339 */
340static void force_io_queues_off(struct octeon_device *oct)
341{
342 if ((oct->chip_id == OCTEON_CN66XX) ||
343 (oct->chip_id == OCTEON_CN68XX)) {
344 /* Reset the Enable bits for Input Queues. */
345 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
346
347 /* Reset the Enable bits for Output Queues. */
348 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
349 }
350}
351
352/**
353 * \brief wait for all pending requests to complete
354 * @param oct Pointer to Octeon device
355 *
356 * Called during shutdown sequence
357 */
358static int wait_for_pending_requests(struct octeon_device *oct)
359{
360 int i, pcount = 0;
361
362 for (i = 0; i < 100; i++) {
363 pcount =
364 atomic_read(&oct->response_list
365 [OCTEON_ORDERED_SC_LIST].pending_req_count);
366 if (pcount)
367 schedule_timeout_uninterruptible(HZ / 10);
9a96bde4 368 else
f21fb3ed
RV		 369 break;
370 }
371
372 if (pcount)
373 return 1;
374
375 return 0;
376}
377
378/**
379 * \brief Cause device to go quiet so it can be safely removed/reset/etc
380 * @param oct Pointer to Octeon device
381 */
382static inline void pcierror_quiesce_device(struct octeon_device *oct)
383{
384 int i;
385
386 /* Disable the input and output queues now. No more packets will
387 * arrive from Octeon, but we should wait for all packet processing
388 * to finish.
389 */
390 force_io_queues_off(oct);
391
392 /* To allow for in-flight requests */
393 schedule_timeout_uninterruptible(100);
394
395 if (wait_for_pending_requests(oct))
396 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
397
398 /* Force all requests waiting to be fetched by OCTEON to complete. */
63da8404 399 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
f21fb3ed
RV		 400 struct octeon_instr_queue *iq;
401
63da8404 402 if (!(oct->io_qmask.iq & (1ULL << i)))
f21fb3ed
RV		 403 continue;
404 iq = oct->instr_queue[i];
405
406 if (atomic_read(&iq->instr_pending)) {
407 spin_lock_bh(&iq->lock);
408 iq->fill_cnt = 0;
409 iq->octeon_read_index = iq->host_write_index;
410 iq->stats.instr_processed +=
411 atomic_read(&iq->instr_pending);
9a96bde4 412 lio_process_iq_request_list(oct, iq, 0);
f21fb3ed
RV		 413 spin_unlock_bh(&iq->lock);
414 }
415 }
416
417 /* Force all pending ordered list requests to time out. */
418 lio_process_ordered_list(oct, 1);
419
420 /* We do not need to wait for output queue packets to be processed. */
421}
422
423/**
424 * \brief Cleanup PCI AER uncorrectable error status
425 * @param dev Pointer to PCI device
426 */
427static void cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
428{
429 int pos = 0x100;
430 u32 status, mask;
431
432 pr_info("%s :\n", __func__);
433
434 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
435 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
436 if (dev->error_state == pci_channel_io_normal)
437 status &= ~mask; /* Clear corresponding nonfatal bits */
438 else
439 status &= mask; /* Clear corresponding fatal bits */
440 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
441}
442
443/**
444 * \brief Stop all PCI IO to a given device
445 * @param dev Pointer to Octeon device
446 */
447static void stop_pci_io(struct octeon_device *oct)
448{
449 /* No more instructions will be forwarded. */
450 atomic_set(&oct->status, OCT_DEV_IN_RESET);
451
452 pci_disable_device(oct->pci_dev);
453
454 /* Disable interrupts */
455 oct->fn_list.disable_interrupt(oct->chip);
456
457 pcierror_quiesce_device(oct);
458
459 /* Release the interrupt line */
460 free_irq(oct->pci_dev->irq, oct);
461
462 if (oct->flags & LIO_FLAG_MSI_ENABLED)
463 pci_disable_msi(oct->pci_dev);
464
465 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
466 lio_get_state_string(&oct->status));
467
468 /* cn63xx_cleanup_aer_uncorrect_error_status(oct->pci_dev); */
469 /* making it a common function for all OCTEON models */
470 cleanup_aer_uncorrect_error_status(oct->pci_dev);
471}
472
473/**
474 * \brief called when PCI error is detected
475 * @param pdev Pointer to PCI device
476 * @param state The current pci connection state
477 *
478 * This function is called after a PCI bus error affecting
479 * this device has been detected.
480 */
481static pci_ers_result_t liquidio_pcie_error_detected(struct pci_dev *pdev,
482 pci_channel_state_t state)
483{
484 struct octeon_device *oct = pci_get_drvdata(pdev);
485
486 /* Non-correctable Non-fatal errors */
487 if (state == pci_channel_io_normal) {
488 dev_err(&oct->pci_dev->dev, "Non-correctable non-fatal error reported:\n");
489 cleanup_aer_uncorrect_error_status(oct->pci_dev);
490 return PCI_ERS_RESULT_CAN_RECOVER;
491 }
492
493 /* Non-correctable Fatal errors */
494 dev_err(&oct->pci_dev->dev, "Non-correctable FATAL reported by PCI AER driver\n");
495 stop_pci_io(oct);
496
497 /* Always return a DISCONNECT. There is no support for recovery but only
498 * for a clean shutdown.
499 */
500 return PCI_ERS_RESULT_DISCONNECT;
501}
502
503/**
504 * \brief mmio handler
505 * @param pdev Pointer to PCI device
506 */
507static pci_ers_result_t liquidio_pcie_mmio_enabled(struct pci_dev *pdev)
508{
509 /* We should never hit this since we never ask for a reset for a Fatal
510 * Error. We always return DISCONNECT in io_error above.
511 * But play safe and return RECOVERED for now.
512 */
513 return PCI_ERS_RESULT_RECOVERED;
514}
515
516/**
517 * \brief called after the pci bus has been reset.
518 * @param pdev Pointer to PCI device
519 *
520 * Restart the card from scratch, as if from a cold-boot. Implementation
521 * resembles the first-half of the octeon_resume routine.
522 */
523static pci_ers_result_t liquidio_pcie_slot_reset(struct pci_dev *pdev)
524{
525 /* We should never hit this since we never ask for a reset for a Fatal
526 * Error. We always return DISCONNECT in io_error above.
527 * But play safe and return RECOVERED for now.
528 */
529 return PCI_ERS_RESULT_RECOVERED;
530}
531
532/**
533 * \brief called when traffic can start flowing again.
534 * @param pdev Pointer to PCI device
535 *
536 * This callback is called when the error recovery driver tells us that
537 * its OK to resume normal operation. Implementation resembles the
538 * second-half of the octeon_resume routine.
539 */
540static void liquidio_pcie_resume(struct pci_dev *pdev)
541{
542 /* Nothing to be done here. */
543}
544
545#ifdef CONFIG_PM
546/**
547 * \brief called when suspending
548 * @param pdev Pointer to PCI device
549 * @param state state to suspend to
550 */
551static int liquidio_suspend(struct pci_dev *pdev, pm_message_t state)
552{
553 return 0;
554}
555
556/**
557 * \brief called when resuming
558 * @param pdev Pointer to PCI device
559 */
560static int liquidio_resume(struct pci_dev *pdev)
561{
562 return 0;
563}
564#endif
565
566/* For PCI-E Advanced Error Recovery (AER) Interface */
166e2362 567static const struct pci_error_handlers liquidio_err_handler = {
f21fb3ed
RV		 568 .error_detected = liquidio_pcie_error_detected,
569 .mmio_enabled = liquidio_pcie_mmio_enabled,
570 .slot_reset = liquidio_pcie_slot_reset,
571 .resume = liquidio_pcie_resume,
572};
573
574static const struct pci_device_id liquidio_pci_tbl[] = {
575 { /* 68xx */
576 PCI_VENDOR_ID_CAVIUM, 0x91, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
577 },
578 { /* 66xx */
579 PCI_VENDOR_ID_CAVIUM, 0x92, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
580 },
581 {
582 0, 0, 0, 0, 0, 0, 0
583 }
584};
585MODULE_DEVICE_TABLE(pci, liquidio_pci_tbl);
586
587static struct pci_driver liquidio_pci_driver = {
588 .name = "LiquidIO",
589 .id_table = liquidio_pci_tbl,
590 .probe = liquidio_probe,
591 .remove = liquidio_remove,
592 .err_handler = &liquidio_err_handler, /* For AER */
593
594#ifdef CONFIG_PM
595 .suspend = liquidio_suspend,
596 .resume = liquidio_resume,
597#endif
598
599};
600
601/**
602 * \brief register PCI driver
603 */
604static int liquidio_init_pci(void)
605{
606 return pci_register_driver(&liquidio_pci_driver);
607}
608
609/**
610 * \brief unregister PCI driver
611 */
612static void liquidio_deinit_pci(void)
613{
614 pci_unregister_driver(&liquidio_pci_driver);
615}
616
617/**
618 * \brief check interface state
619 * @param lio per-network private data
620 * @param state_flag flag state to check
621 */
622static inline int ifstate_check(struct lio *lio, int state_flag)
623{
624 return atomic_read(&lio->ifstate) & state_flag;
625}
626
627/**
628 * \brief set interface state
629 * @param lio per-network private data
630 * @param state_flag flag state to set
631 */
632static inline void ifstate_set(struct lio *lio, int state_flag)
633{
634 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) | state_flag));
635}
636
637/**
638 * \brief clear interface state
639 * @param lio per-network private data
640 * @param state_flag flag state to clear
641 */
642static inline void ifstate_reset(struct lio *lio, int state_flag)
643{
644 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) & ~(state_flag)));
645}
646
647/**
648 * \brief Stop Tx queues
649 * @param netdev network device
650 */
651static inline void txqs_stop(struct net_device *netdev)
652{
653 if (netif_is_multiqueue(netdev)) {
654 int i;
655
656 for (i = 0; i < netdev->num_tx_queues; i++)
657 netif_stop_subqueue(netdev, i);
658 } else {
659 netif_stop_queue(netdev);
660 }
661}
662
663/**
664 * \brief Start Tx queues
665 * @param netdev network device
666 */
667static inline void txqs_start(struct net_device *netdev)
668{
669 if (netif_is_multiqueue(netdev)) {
670 int i;
671
672 for (i = 0; i < netdev->num_tx_queues; i++)
673 netif_start_subqueue(netdev, i);
674 } else {
675 netif_start_queue(netdev);
676 }
677}
678
679/**
680 * \brief Wake Tx queues
681 * @param netdev network device
682 */
683static inline void txqs_wake(struct net_device *netdev)
684{
685 if (netif_is_multiqueue(netdev)) {
686 int i;
687
688 for (i = 0; i < netdev->num_tx_queues; i++)
26236fa9
RV		 689 if (__netif_subqueue_stopped(netdev, i))
690 netif_wake_subqueue(netdev, i);
f21fb3ed
RV		 691 } else {
692 netif_wake_queue(netdev);
693 }
694}
695
696/**
697 * \brief Stop Tx queue
698 * @param netdev network device
699 */
700static void stop_txq(struct net_device *netdev)
701{
702 txqs_stop(netdev);
703}
704
705/**
706 * \brief Start Tx queue
707 * @param netdev network device
708 */
709static void start_txq(struct net_device *netdev)
710{
711 struct lio *lio = GET_LIO(netdev);
712
0cece6c5 713 if (lio->linfo.link.s.link_up) {
f21fb3ed
RV		 714 txqs_start(netdev);
715 return;
716 }
717}
718
719/**
720 * \brief Wake a queue
721 * @param netdev network device
722 * @param q which queue to wake
723 */
724static inline void wake_q(struct net_device *netdev, int q)
725{
726 if (netif_is_multiqueue(netdev))
727 netif_wake_subqueue(netdev, q);
728 else
729 netif_wake_queue(netdev);
730}
731
732/**
733 * \brief Stop a queue
734 * @param netdev network device
735 * @param q which queue to stop
736 */
737static inline void stop_q(struct net_device *netdev, int q)
738{
739 if (netif_is_multiqueue(netdev))
740 netif_stop_subqueue(netdev, q);
741 else
742 netif_stop_queue(netdev);
743}
744
745/**
746 * \brief Check Tx queue status, and take appropriate action
747 * @param lio per-network private data
748 * @returns 0 if full, number of queues woken up otherwise
749 */
750static inline int check_txq_status(struct lio *lio)
751{
752 int ret_val = 0;
753
754 if (netif_is_multiqueue(lio->netdev)) {
755 int numqs = lio->netdev->num_tx_queues;
756 int q, iq = 0;
757
758 /* check each sub-queue state */
759 for (q = 0; q < numqs; q++) {
26236fa9
RV		 760 iq = lio->linfo.txpciq[q %
761 (lio->linfo.num_txpciq)].s.q_no;
f21fb3ed
RV		 762 if (octnet_iq_is_full(lio->oct_dev, iq))
763 continue;
26236fa9
RV		 764 if (__netif_subqueue_stopped(lio->netdev, q)) {
765 wake_q(lio->netdev, q);
766 ret_val++;
767 }
f21fb3ed
RV		 768 }
769 } else {
770 if (octnet_iq_is_full(lio->oct_dev, lio->txq))
771 return 0;
772 wake_q(lio->netdev, lio->txq);
773 ret_val = 1;
774 }
775 return ret_val;
776}
777
778/**
779 * Remove the node at the head of the list. The list would be empty at
780 * the end of this call if there are no more nodes in the list.
781 */
782static inline struct list_head *list_delete_head(struct list_head *root)
783{
784 struct list_head *node;
785
786 if ((root->prev == root) && (root->next == root))
787 node = NULL;
788 else
789 node = root->next;
790
791 if (node)
792 list_del(node);
793
794 return node;
795}
796
797/**
fcd2b5e3 798 * \brief Delete gather lists
f21fb3ed
RV		 799 * @param lio per-network private data
800 */
fcd2b5e3 801static void delete_glists(struct lio *lio)
f21fb3ed
RV		 802{
803 struct octnic_gather *g;
fcd2b5e3 804 int i;
f21fb3ed 805
fcd2b5e3
RV		 806 if (!lio->glist)
807 return;
808
809 for (i = 0; i < lio->linfo.num_txpciq; i++) {
810 do {
811 g = (struct octnic_gather *)
812 list_delete_head(&lio->glist[i]);
813 if (g) {
814 if (g->sg) {
815 dma_unmap_single(&lio->oct_dev->
816 pci_dev->dev,
817 g->sg_dma_ptr,
818 g->sg_size,
819 DMA_TO_DEVICE);
820 kfree((void *)((unsigned long)g->sg -
821 g->adjust));
822 }
823 kfree(g);
824 }
825 } while (g);
826 }
827
828 kfree((void *)lio->glist);
f21fb3ed
RV		 829}
830
831/**
fcd2b5e3 832 * \brief Setup gather lists
f21fb3ed
RV		 833 * @param lio per-network private data
834 */
fcd2b5e3 835static int setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs)
f21fb3ed 836{
fcd2b5e3 837 int i, j;
f21fb3ed
RV		 838 struct octnic_gather *g;
839
fcd2b5e3
RV		 840 lio->glist_lock = kcalloc(num_iqs, sizeof(*lio->glist_lock),
841 GFP_KERNEL);
842 if (!lio->glist_lock)
843 return 1;
f21fb3ed 844
fcd2b5e3
RV		 845 lio->glist = kcalloc(num_iqs, sizeof(*lio->glist),
846 GFP_KERNEL);
847 if (!lio->glist) {
848 kfree((void *)lio->glist_lock);
849 return 1;
850 }
f21fb3ed 851
fcd2b5e3
RV		 852 for (i = 0; i < num_iqs; i++) {
853 int numa_node = cpu_to_node(i % num_online_cpus());
f21fb3ed 854
fcd2b5e3
RV		 855 spin_lock_init(&lio->glist_lock[i]);
856
857 INIT_LIST_HEAD(&lio->glist[i]);
858
859 for (j = 0; j < lio->tx_qsize; j++) {
860 g = kzalloc_node(sizeof(*g), GFP_KERNEL,
861 numa_node);
862 if (!g)
863 g = kzalloc(sizeof(*g), GFP_KERNEL);
864 if (!g)
865 break;
866
867 g->sg_size = ((ROUNDUP4(OCTNIC_MAX_SG) >> 2) *
868 OCT_SG_ENTRY_SIZE);
869
870 g->sg = kmalloc_node(g->sg_size + 8,
871 GFP_KERNEL, numa_node);
872 if (!g->sg)
873 g->sg = kmalloc(g->sg_size + 8, GFP_KERNEL);
874 if (!g->sg) {
875 kfree(g);
876 break;
877 }
878
879 /* The gather component should be aligned on 64-bit
880 * boundary
881 */
882 if (((unsigned long)g->sg) & 7) {
883 g->adjust = 8 - (((unsigned long)g->sg) & 7);
884 g->sg = (struct octeon_sg_entry *)
885 ((unsigned long)g->sg + g->adjust);
886 }
887 g->sg_dma_ptr = dma_map_single(&oct->pci_dev->dev,
888 g->sg, g->sg_size,
889 DMA_TO_DEVICE);
890 if (dma_mapping_error(&oct->pci_dev->dev,
891 g->sg_dma_ptr)) {
892 kfree((void *)((unsigned long)g->sg -
893 g->adjust));
894 kfree(g);
895 break;
896 }
897
898 list_add_tail(&g->list, &lio->glist[i]);
f21fb3ed
RV		 899 }
900
fcd2b5e3
RV		 901 if (j != lio->tx_qsize) {
902 delete_glists(lio);
903 return 1;
f21fb3ed 904 }
f21fb3ed
RV		 905 }
906
fcd2b5e3 907 return 0;
f21fb3ed
RV		 908}
909
910/**
911 * \brief Print link information
912 * @param netdev network device
913 */
914static void print_link_info(struct net_device *netdev)
915{
916 struct lio *lio = GET_LIO(netdev);
917
918 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED) {
919 struct oct_link_info *linfo = &lio->linfo;
920
0cece6c5 921 if (linfo->link.s.link_up) {
f21fb3ed
RV		 922 netif_info(lio, link, lio->netdev, "%d Mbps %s Duplex UP\n",
923 linfo->link.s.speed,
924 (linfo->link.s.duplex) ? "Full" : "Half");
925 } else {
926 netif_info(lio, link, lio->netdev, "Link Down\n");
927 }
928 }
929}
930
931/**
932 * \brief Update link status
933 * @param netdev network device
934 * @param ls link status structure
935 *
936 * Called on receipt of a link status response from the core application to
937 * update each interface's link status.
938 */
939static inline void update_link_status(struct net_device *netdev,
940 union oct_link_status *ls)
941{
942 struct lio *lio = GET_LIO(netdev);
0cece6c5 943 int changed = (lio->linfo.link.u64 != ls->u64);
f21fb3ed 944
0cece6c5 945 lio->linfo.link.u64 = ls->u64;
f21fb3ed 946
0cece6c5 947 if ((lio->intf_open) && (changed)) {
f21fb3ed 948 print_link_info(netdev);
0cece6c5 949 lio->link_changes++;
f21fb3ed 950
0cece6c5 951 if (lio->linfo.link.s.link_up) {
f21fb3ed
RV		 952 netif_carrier_on(netdev);
953 /* start_txq(netdev); */
954 txqs_wake(netdev);
955 } else {
956 netif_carrier_off(netdev);
957 stop_txq(netdev);
958 }
959 }
960}
961
9a96bde4
RV		 962/* Runs in interrupt context. */
963static void update_txq_status(struct octeon_device *oct, int iq_num)
964{
965 struct net_device *netdev;
966 struct lio *lio;
967 struct octeon_instr_queue *iq = oct->instr_queue[iq_num];
968
969 /*octeon_update_iq_read_idx(oct, iq);*/
970
971 netdev = oct->props[iq->ifidx].netdev;
972
973 /* This is needed because the first IQ does not have
974 * a netdev associated with it.
975 */
976 if (!netdev)
977 return;
978
979 lio = GET_LIO(netdev);
980 if (netif_is_multiqueue(netdev)) {
981 if (__netif_subqueue_stopped(netdev, iq->q_index) &&
982 lio->linfo.link.s.link_up &&
983 (!octnet_iq_is_full(oct, iq_num))) {
984 netif_wake_subqueue(netdev, iq->q_index);
985 } else {
986 if (!octnet_iq_is_full(oct, lio->txq))
987 wake_q(netdev, lio->txq);
988 }
989 }
990}
991
f21fb3ed
RV		 992/**
993 * \brief Droq packet processor sceduler
994 * @param oct octeon device
995 */
996static
997void liquidio_schedule_droq_pkt_handlers(struct octeon_device *oct)
998{
999 struct octeon_device_priv *oct_priv =
1000 (struct octeon_device_priv *)oct->priv;
1001 u64 oq_no;
1002 struct octeon_droq *droq;
1003
1004 if (oct->int_status & OCT_DEV_INTR_PKT_DATA) {
63da8404
RV		 1005 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct);
1006 oq_no++) {
1007 if (!(oct->droq_intr & (1ULL << oq_no)))
f21fb3ed
RV		 1008 continue;
1009
1010 droq = oct->droq[oq_no];
1011
1012 if (droq->ops.poll_mode) {
1013 droq->ops.napi_fn(droq);
1014 oct_priv->napi_mask |= (1 << oq_no);
1015 } else {
1016 tasklet_schedule(&oct_priv->droq_tasklet);
1017 }
1018 }
1019 }
1020}
1021
1022/**
1023 * \brief Interrupt handler for octeon
1024 * @param irq unused
1025 * @param dev octeon device
1026 */
1027static
1028irqreturn_t liquidio_intr_handler(int irq __attribute__((unused)), void *dev)
1029{
1030 struct octeon_device *oct = (struct octeon_device *)dev;
1031 irqreturn_t ret;
1032
1033 /* Disable our interrupts for the duration of ISR */
1034 oct->fn_list.disable_interrupt(oct->chip);
1035
1036 ret = oct->fn_list.process_interrupt_regs(oct);
1037
1038 if (ret == IRQ_HANDLED)
1039 liquidio_schedule_droq_pkt_handlers(oct);
1040
1041 /* Re-enable our interrupts */
1042 if (!(atomic_read(&oct->status) == OCT_DEV_IN_RESET))
1043 oct->fn_list.enable_interrupt(oct->chip);
1044
1045 return ret;
1046}
1047
1048/**
1049 * \brief Setup interrupt for octeon device
1050 * @param oct octeon device
1051 *
1052 * Enable interrupt in Octeon device as given in the PCI interrupt mask.
1053 */
1054static int octeon_setup_interrupt(struct octeon_device *oct)
1055{
1056 int irqret, err;
1057
1058 err = pci_enable_msi(oct->pci_dev);
1059 if (err)
1060 dev_warn(&oct->pci_dev->dev, "Reverting to legacy interrupts. Error: %d\n",
1061 err);
1062 else
1063 oct->flags |= LIO_FLAG_MSI_ENABLED;
1064
1065 irqret = request_irq(oct->pci_dev->irq, liquidio_intr_handler,
1066 IRQF_SHARED, "octeon", oct);
1067 if (irqret) {
1068 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1069 pci_disable_msi(oct->pci_dev);
1070 dev_err(&oct->pci_dev->dev, "Request IRQ failed with code: %d\n",
1071 irqret);
1072 return 1;
1073 }
1074
1075 return 0;
1076}
1077
1078/**
1079 * \brief PCI probe handler
1080 * @param pdev PCI device structure
1081 * @param ent unused
1082 */
1083static int liquidio_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1084{
1085 struct octeon_device *oct_dev = NULL;
1086 struct handshake *hs;
1087
1088 oct_dev = octeon_allocate_device(pdev->device,
1089 sizeof(struct octeon_device_priv));
1090 if (!oct_dev) {
1091 dev_err(&pdev->dev, "Unable to allocate device\n");
1092 return -ENOMEM;
1093 }
1094
1095 dev_info(&pdev->dev, "Initializing device %x:%x.\n",
1096 (u32)pdev->vendor, (u32)pdev->device);
1097
1098 /* Assign octeon_device for this device to the private data area. */
1099 pci_set_drvdata(pdev, oct_dev);
1100
1101 /* set linux specific device pointer */
1102 oct_dev->pci_dev = (void *)pdev;
1103
1104 hs = &handshake[oct_dev->octeon_id];
1105 init_completion(&hs->init);
1106 init_completion(&hs->started);
1107 hs->pci_dev = pdev;
1108
1109 if (oct_dev->octeon_id == 0)
1110 /* first LiquidIO NIC is detected */
1111 complete(&first_stage);
1112
1113 if (octeon_device_init(oct_dev)) {
1114 liquidio_remove(pdev);
1115 return -ENOMEM;
1116 }
1117
1118 dev_dbg(&oct_dev->pci_dev->dev, "Device is ready\n");
1119
1120 return 0;
1121}
1122
1123/**
1124 *\brief Destroy resources associated with octeon device
1125 * @param pdev PCI device structure
1126 * @param ent unused
1127 */
1128static void octeon_destroy_resources(struct octeon_device *oct)
1129{
1130 int i;
1131 struct octeon_device_priv *oct_priv =
1132 (struct octeon_device_priv *)oct->priv;
1133
1134 struct handshake *hs;
1135
1136 switch (atomic_read(&oct->status)) {
1137 case OCT_DEV_RUNNING:
1138 case OCT_DEV_CORE_OK:
1139
1140 /* No more instructions will be forwarded. */
1141 atomic_set(&oct->status, OCT_DEV_IN_RESET);
1142
1143 oct->app_mode = CVM_DRV_INVALID_APP;
1144 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
1145 lio_get_state_string(&oct->status));
1146
1147 schedule_timeout_uninterruptible(HZ / 10);
1148
1149 /* fallthrough */
1150 case OCT_DEV_HOST_OK:
1151
1152 /* fallthrough */
1153 case OCT_DEV_CONSOLE_INIT_DONE:
1154 /* Remove any consoles */
1155 octeon_remove_consoles(oct);
1156
1157 /* fallthrough */
1158 case OCT_DEV_IO_QUEUES_DONE:
1159 if (wait_for_pending_requests(oct))
1160 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
1161
1162 if (lio_wait_for_instr_fetch(oct))
1163 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n");
1164
1165 /* Disable the input and output queues now. No more packets will
1166 * arrive from Octeon, but we should wait for all packet
1167 * processing to finish.
1168 */
1169 oct->fn_list.disable_io_queues(oct);
1170
1171 if (lio_wait_for_oq_pkts(oct))
1172 dev_err(&oct->pci_dev->dev, "OQ had pending packets\n");
1173
1174 /* Disable interrupts */
1175 oct->fn_list.disable_interrupt(oct->chip);
1176
1177 /* Release the interrupt line */
1178 free_irq(oct->pci_dev->irq, oct);
1179
1180 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1181 pci_disable_msi(oct->pci_dev);
1182
f21fb3ed
RV		 1183 /* fallthrough */
1184 case OCT_DEV_IN_RESET:
1185 case OCT_DEV_DROQ_INIT_DONE:
1186 /*atomic_set(&oct->status, OCT_DEV_DROQ_INIT_DONE);*/
1187 mdelay(100);
63da8404
RV		 1188 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
1189 if (!(oct->io_qmask.oq & (1ULL << i)))
f21fb3ed
RV		 1190 continue;
1191 octeon_delete_droq(oct, i);
1192 }
1193
1194 /* Force any pending handshakes to complete */
1195 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
1196 hs = &handshake[i];
1197
1198 if (hs->pci_dev) {
1199 handshake[oct->octeon_id].init_ok = 0;
1200 complete(&handshake[oct->octeon_id].init);
1201 handshake[oct->octeon_id].started_ok = 0;
1202 complete(&handshake[oct->octeon_id].started);
1203 }
1204 }
1205
1206 /* fallthrough */
1207 case OCT_DEV_RESP_LIST_INIT_DONE:
1208 octeon_delete_response_list(oct);
1209
1210 /* fallthrough */
1211 case OCT_DEV_SC_BUFF_POOL_INIT_DONE:
1212 octeon_free_sc_buffer_pool(oct);
1213
1214 /* fallthrough */
1215 case OCT_DEV_INSTR_QUEUE_INIT_DONE:
63da8404
RV		 1216 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
1217 if (!(oct->io_qmask.iq & (1ULL << i)))
f21fb3ed
RV		 1218 continue;
1219 octeon_delete_instr_queue(oct, i);
1220 }
1221
1222 /* fallthrough */
1223 case OCT_DEV_DISPATCH_INIT_DONE:
1224 octeon_delete_dispatch_list(oct);
1225 cancel_delayed_work_sync(&oct->nic_poll_work.work);
1226
1227 /* fallthrough */
1228 case OCT_DEV_PCI_MAP_DONE:
60b48c5a
RV		 1229
1230 /* Soft reset the octeon device before exiting */
1231 oct->fn_list.soft_reset(oct);
1232
f21fb3ed
RV		 1233 octeon_unmap_pci_barx(oct, 0);
1234 octeon_unmap_pci_barx(oct, 1);
1235
1236 /* fallthrough */
1237 case OCT_DEV_BEGIN_STATE:
60b48c5a
RV		 1238 /* Disable the device, releasing the PCI INT */
1239 pci_disable_device(oct->pci_dev);
1240
f21fb3ed
RV		 1241 /* Nothing to be done here either */
1242 break;
1243 } /* end switch(oct->status) */
1244
1245 tasklet_kill(&oct_priv->droq_tasklet);
1246}
1247
1248/**
1249 * \brief Send Rx control command
1250 * @param lio per-network private data
1251 * @param start_stop whether to start or stop
1252 */
1253static void send_rx_ctrl_cmd(struct lio *lio, int start_stop)
1254{
1255 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 1256
1257 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
1258
1259 nctrl.ncmd.s.cmd = OCTNET_CMD_RX_CTL;
0cece6c5
RV		 1260 nctrl.ncmd.s.param1 = start_stop;
1261 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 1262 nctrl.netpndev = (u64)lio->netdev;
1263
0cece6c5 1264 if (octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl) < 0)
f21fb3ed
RV		 1265 netif_info(lio, rx_err, lio->netdev, "Failed to send RX Control message\n");
1266}
1267
1268/**
1269 * \brief Destroy NIC device interface
1270 * @param oct octeon device
1271 * @param ifidx which interface to destroy
1272 *
1273 * Cleanup associated with each interface for an Octeon device when NIC
1274 * module is being unloaded or if initialization fails during load.
1275 */
1276static void liquidio_destroy_nic_device(struct octeon_device *oct, int ifidx)
1277{
1278 struct net_device *netdev = oct->props[ifidx].netdev;
1279 struct lio *lio;
9a96bde4 1280 struct napi_struct *napi, *n;
f21fb3ed
RV		 1281
1282 if (!netdev) {
1283 dev_err(&oct->pci_dev->dev, "%s No netdevice ptr for index %d\n",
1284 __func__, ifidx);
1285 return;
1286 }
1287
1288 lio = GET_LIO(netdev);
1289
1290 dev_dbg(&oct->pci_dev->dev, "NIC device cleanup\n");
1291
1292 send_rx_ctrl_cmd(lio, 0);
1293
1294 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING)
1295 txqs_stop(netdev);
1296
9a96bde4
RV		 1297 if (oct->props[lio->ifidx].napi_enabled == 1) {
1298 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
1299 napi_disable(napi);
1300
1301 oct->props[lio->ifidx].napi_enabled = 0;
1302 }
1303
f21fb3ed
RV		 1304 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED)
1305 unregister_netdev(netdev);
1306
fcd2b5e3 1307 delete_glists(lio);
f21fb3ed
RV		 1308
1309 free_netdev(netdev);
1310
0cece6c5
RV		 1311 oct->props[ifidx].gmxport = -1;
1312
f21fb3ed
RV		 1313 oct->props[ifidx].netdev = NULL;
1314}
1315
1316/**
1317 * \brief Stop complete NIC functionality
1318 * @param oct octeon device
1319 */
1320static int liquidio_stop_nic_module(struct octeon_device *oct)
1321{
1322 int i, j;
1323 struct lio *lio;
1324
1325 dev_dbg(&oct->pci_dev->dev, "Stopping network interfaces\n");
1326 if (!oct->ifcount) {
1327 dev_err(&oct->pci_dev->dev, "Init for Octeon was not completed\n");
1328 return 1;
1329 }
1330
60441888
RV		 1331 spin_lock_bh(&oct->cmd_resp_wqlock);
1332 oct->cmd_resp_state = OCT_DRV_OFFLINE;
1333 spin_unlock_bh(&oct->cmd_resp_wqlock);
1334
f21fb3ed
RV		 1335 for (i = 0; i < oct->ifcount; i++) {
1336 lio = GET_LIO(oct->props[i].netdev);
1337 for (j = 0; j < lio->linfo.num_rxpciq; j++)
26236fa9
RV		 1338 octeon_unregister_droq_ops(oct,
1339 lio->linfo.rxpciq[j].s.q_no);
f21fb3ed
RV		 1340 }
1341
1342 for (i = 0; i < oct->ifcount; i++)
1343 liquidio_destroy_nic_device(oct, i);
1344
1345 dev_dbg(&oct->pci_dev->dev, "Network interfaces stopped\n");
1346 return 0;
1347}
1348
1349/**
1350 * \brief Cleans up resources at unload time
1351 * @param pdev PCI device structure
1352 */
1353static void liquidio_remove(struct pci_dev *pdev)
1354{
1355 struct octeon_device *oct_dev = pci_get_drvdata(pdev);
1356
1357 dev_dbg(&oct_dev->pci_dev->dev, "Stopping device\n");
1358
1359 if (oct_dev->app_mode && (oct_dev->app_mode == CVM_DRV_NIC_APP))
1360 liquidio_stop_nic_module(oct_dev);
1361
1362 /* Reset the octeon device and cleanup all memory allocated for
1363 * the octeon device by driver.
1364 */
1365 octeon_destroy_resources(oct_dev);
1366
1367 dev_info(&oct_dev->pci_dev->dev, "Device removed\n");
1368
1369 /* This octeon device has been removed. Update the global
1370 * data structure to reflect this. Free the device structure.
1371 */
1372 octeon_free_device_mem(oct_dev);
1373}
1374
1375/**
1376 * \brief Identify the Octeon device and to map the BAR address space
1377 * @param oct octeon device
1378 */
1379static int octeon_chip_specific_setup(struct octeon_device *oct)
1380{
1381 u32 dev_id, rev_id;
1382 int ret = 1;
d3d7e6c6 1383 char *s;
f21fb3ed
RV		 1384
1385 pci_read_config_dword(oct->pci_dev, 0, &dev_id);
1386 pci_read_config_dword(oct->pci_dev, 8, &rev_id);
1387 oct->rev_id = rev_id & 0xff;
1388
1389 switch (dev_id) {
1390 case OCTEON_CN68XX_PCIID:
1391 oct->chip_id = OCTEON_CN68XX;
1392 ret = lio_setup_cn68xx_octeon_device(oct);
d3d7e6c6 1393 s = "CN68XX";
f21fb3ed
RV		 1394 break;
1395
1396 case OCTEON_CN66XX_PCIID:
1397 oct->chip_id = OCTEON_CN66XX;
1398 ret = lio_setup_cn66xx_octeon_device(oct);
d3d7e6c6 1399 s = "CN66XX";
f21fb3ed 1400 break;
d3d7e6c6 1401
f21fb3ed 1402 default:
d3d7e6c6 1403 s = "?";
f21fb3ed
RV		 1404 dev_err(&oct->pci_dev->dev, "Unknown device found (dev_id: %x)\n",
1405 dev_id);
1406 }
1407
1408 if (!ret)
d3d7e6c6 1409 dev_info(&oct->pci_dev->dev, "%s PASS%d.%d %s Version: %s\n", s,
f21fb3ed
RV		 1410 OCTEON_MAJOR_REV(oct),
1411 OCTEON_MINOR_REV(oct),
d3d7e6c6
RV		 1412 octeon_get_conf(oct)->card_name,
1413 LIQUIDIO_VERSION);
f21fb3ed
RV		 1414
1415 return ret;
1416}
1417
1418/**
1419 * \brief PCI initialization for each Octeon device.
1420 * @param oct octeon device
1421 */
1422static int octeon_pci_os_setup(struct octeon_device *oct)
1423{
1424 /* setup PCI stuff first */
1425 if (pci_enable_device(oct->pci_dev)) {
1426 dev_err(&oct->pci_dev->dev, "pci_enable_device failed\n");
1427 return 1;
1428 }
1429
1430 if (dma_set_mask_and_coherent(&oct->pci_dev->dev, DMA_BIT_MASK(64))) {
1431 dev_err(&oct->pci_dev->dev, "Unexpected DMA device capability\n");
1432 return 1;
1433 }
1434
1435 /* Enable PCI DMA Master. */
1436 pci_set_master(oct->pci_dev);
1437
1438 return 0;
1439}
1440
fcd2b5e3
RV		 1441static inline int skb_iq(struct lio *lio, struct sk_buff *skb)
1442{
1443 int q = 0;
1444
1445 if (netif_is_multiqueue(lio->netdev))
1446 q = skb->queue_mapping % lio->linfo.num_txpciq;
1447
1448 return q;
1449}
1450
f21fb3ed
RV		 1451/**
1452 * \brief Check Tx queue state for a given network buffer
1453 * @param lio per-network private data
1454 * @param skb network buffer
1455 */
1456static inline int check_txq_state(struct lio *lio, struct sk_buff *skb)
1457{
1458 int q = 0, iq = 0;
1459
1460 if (netif_is_multiqueue(lio->netdev)) {
1461 q = skb->queue_mapping;
26236fa9 1462 iq = lio->linfo.txpciq[(q % (lio->linfo.num_txpciq))].s.q_no;
f21fb3ed
RV		 1463 } else {
1464 iq = lio->txq;
26236fa9 1465 q = iq;
f21fb3ed
RV		 1466 }
1467
1468 if (octnet_iq_is_full(lio->oct_dev, iq))
1469 return 0;
26236fa9
RV		 1470
1471 if (__netif_subqueue_stopped(lio->netdev, q))
1472 wake_q(lio->netdev, q);
f21fb3ed
RV		 1473 return 1;
1474}
1475
1476/**
1477 * \brief Unmap and free network buffer
1478 * @param buf buffer
1479 */
1480static void free_netbuf(void *buf)
1481{
1482 struct sk_buff *skb;
1483 struct octnet_buf_free_info *finfo;
1484 struct lio *lio;
1485
1486 finfo = (struct octnet_buf_free_info *)buf;
1487 skb = finfo->skb;
1488 lio = finfo->lio;
1489
1490 dma_unmap_single(&lio->oct_dev->pci_dev->dev, finfo->dptr, skb->len,
1491 DMA_TO_DEVICE);
1492
1493 check_txq_state(lio, skb);
1494
cabeb13b 1495 tx_buffer_free(skb);
f21fb3ed
RV		 1496}
1497
1498/**
1499 * \brief Unmap and free gather buffer
1500 * @param buf buffer
1501 */
1502static void free_netsgbuf(void *buf)
1503{
1504 struct octnet_buf_free_info *finfo;
1505 struct sk_buff *skb;
1506 struct lio *lio;
1507 struct octnic_gather *g;
fcd2b5e3 1508 int i, frags, iq;
f21fb3ed
RV		 1509
1510 finfo = (struct octnet_buf_free_info *)buf;
1511 skb = finfo->skb;
1512 lio = finfo->lio;
1513 g = finfo->g;
1514 frags = skb_shinfo(skb)->nr_frags;
1515
1516 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1517 g->sg[0].ptr[0], (skb->len - skb->data_len),
1518 DMA_TO_DEVICE);
1519
1520 i = 1;
1521 while (frags--) {
1522 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1523
1524 pci_unmap_page((lio->oct_dev)->pci_dev,
1525 g->sg[(i >> 2)].ptr[(i & 3)],
1526 frag->size, DMA_TO_DEVICE);
1527 i++;
1528 }
1529
fcd2b5e3
RV		 1530 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
1531 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
f21fb3ed 1532
fcd2b5e3
RV		 1533 iq = skb_iq(lio, skb);
1534 spin_lock(&lio->glist_lock[iq]);
1535 list_add_tail(&g->list, &lio->glist[iq]);
1536 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1537
1538 check_txq_state(lio, skb); /* mq support: sub-queue state check */
1539
cabeb13b 1540 tx_buffer_free(skb);
f21fb3ed
RV		 1541}
1542
1543/**
1544 * \brief Unmap and free gather buffer with response
1545 * @param buf buffer
1546 */
1547static void free_netsgbuf_with_resp(void *buf)
1548{
1549 struct octeon_soft_command *sc;
1550 struct octnet_buf_free_info *finfo;
1551 struct sk_buff *skb;
1552 struct lio *lio;
1553 struct octnic_gather *g;
fcd2b5e3 1554 int i, frags, iq;
f21fb3ed
RV		 1555
1556 sc = (struct octeon_soft_command *)buf;
1557 skb = (struct sk_buff *)sc->callback_arg;
1558 finfo = (struct octnet_buf_free_info *)&skb->cb;
1559
1560 lio = finfo->lio;
1561 g = finfo->g;
1562 frags = skb_shinfo(skb)->nr_frags;
1563
1564 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1565 g->sg[0].ptr[0], (skb->len - skb->data_len),
1566 DMA_TO_DEVICE);
1567
1568 i = 1;
1569 while (frags--) {
1570 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1571
1572 pci_unmap_page((lio->oct_dev)->pci_dev,
1573 g->sg[(i >> 2)].ptr[(i & 3)],
1574 frag->size, DMA_TO_DEVICE);
1575 i++;
1576 }
1577
fcd2b5e3
RV		 1578 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
1579 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
f21fb3ed 1580
fcd2b5e3
RV		 1581 iq = skb_iq(lio, skb);
1582
1583 spin_lock(&lio->glist_lock[iq]);
1584 list_add_tail(&g->list, &lio->glist[iq]);
1585 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1586
1587 /* Don't free the skb yet */
1588
1589 check_txq_state(lio, skb);
1590}
1591
1592/**
1593 * \brief Adjust ptp frequency
1594 * @param ptp PTP clock info
1595 * @param ppb how much to adjust by, in parts-per-billion
1596 */
1597static int liquidio_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
1598{
1599 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1600 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1601 u64 comp, delta;
1602 unsigned long flags;
1603 bool neg_adj = false;
1604
1605 if (ppb < 0) {
1606 neg_adj = true;
1607 ppb = -ppb;
1608 }
1609
1610 /* The hardware adds the clock compensation value to the
1611 * PTP clock on every coprocessor clock cycle, so we
1612 * compute the delta in terms of coprocessor clocks.
1613 */
1614 delta = (u64)ppb << 32;
1615 do_div(delta, oct->coproc_clock_rate);
1616
1617 spin_lock_irqsave(&lio->ptp_lock, flags);
1618 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP);
1619 if (neg_adj)
1620 comp -= delta;
1621 else
1622 comp += delta;
1623 lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP);
1624 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1625
1626 return 0;
1627}
1628
1629/**
1630 * \brief Adjust ptp time
1631 * @param ptp PTP clock info
1632 * @param delta how much to adjust by, in nanosecs
1633 */
1634static int liquidio_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
1635{
1636 unsigned long flags;
1637 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1638
1639 spin_lock_irqsave(&lio->ptp_lock, flags);
1640 lio->ptp_adjust += delta;
1641 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1642
1643 return 0;
1644}
1645
1646/**
1647 * \brief Get hardware clock time, including any adjustment
1648 * @param ptp PTP clock info
1649 * @param ts timespec
1650 */
1651static int liquidio_ptp_gettime(struct ptp_clock_info *ptp,
1652 struct timespec64 *ts)
1653{
1654 u64 ns;
f21fb3ed
RV		 1655 unsigned long flags;
1656 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1657 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1658
1659 spin_lock_irqsave(&lio->ptp_lock, flags);
1660 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI);
1661 ns += lio->ptp_adjust;
1662 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1663
286af315 1664 *ts = ns_to_timespec64(ns);
f21fb3ed
RV		 1665
1666 return 0;
1667}
1668
1669/**
1670 * \brief Set hardware clock time. Reset adjustment
1671 * @param ptp PTP clock info
1672 * @param ts timespec
1673 */
1674static int liquidio_ptp_settime(struct ptp_clock_info *ptp,
1675 const struct timespec64 *ts)
1676{
1677 u64 ns;
1678 unsigned long flags;
1679 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1680 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1681
1682 ns = timespec_to_ns(ts);
1683
1684 spin_lock_irqsave(&lio->ptp_lock, flags);
1685 lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI);
1686 lio->ptp_adjust = 0;
1687 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1688
1689 return 0;
1690}
1691
1692/**
1693 * \brief Check if PTP is enabled
1694 * @param ptp PTP clock info
1695 * @param rq request
1696 * @param on is it on
1697 */
1698static int liquidio_ptp_enable(struct ptp_clock_info *ptp,
1699 struct ptp_clock_request *rq, int on)
1700{
1701 return -EOPNOTSUPP;
1702}
1703
1704/**
1705 * \brief Open PTP clock source
1706 * @param netdev network device
1707 */
1708static void oct_ptp_open(struct net_device *netdev)
1709{
1710 struct lio *lio = GET_LIO(netdev);
1711 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1712
1713 spin_lock_init(&lio->ptp_lock);
1714
1715 snprintf(lio->ptp_info.name, 16, "%s", netdev->name);
1716 lio->ptp_info.owner = THIS_MODULE;
1717 lio->ptp_info.max_adj = 250000000;
1718 lio->ptp_info.n_alarm = 0;
1719 lio->ptp_info.n_ext_ts = 0;
1720 lio->ptp_info.n_per_out = 0;
1721 lio->ptp_info.pps = 0;
1722 lio->ptp_info.adjfreq = liquidio_ptp_adjfreq;
1723 lio->ptp_info.adjtime = liquidio_ptp_adjtime;
1724 lio->ptp_info.gettime64 = liquidio_ptp_gettime;
1725 lio->ptp_info.settime64 = liquidio_ptp_settime;
1726 lio->ptp_info.enable = liquidio_ptp_enable;
1727
1728 lio->ptp_adjust = 0;
1729
1730 lio->ptp_clock = ptp_clock_register(&lio->ptp_info,
1731 &oct->pci_dev->dev);
1732
1733 if (IS_ERR(lio->ptp_clock))
1734 lio->ptp_clock = NULL;
1735}
1736
1737/**
1738 * \brief Init PTP clock
1739 * @param oct octeon device
1740 */
1741static void liquidio_ptp_init(struct octeon_device *oct)
1742{
1743 u64 clock_comp, cfg;
1744
1745 clock_comp = (u64)NSEC_PER_SEC << 32;
1746 do_div(clock_comp, oct->coproc_clock_rate);
1747 lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP);
1748
1749 /* Enable */
1750 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG);
1751 lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG);
1752}
1753
1754/**
1755 * \brief Load firmware to device
1756 * @param oct octeon device
1757 *
1758 * Maps device to firmware filename, requests firmware, and downloads it
1759 */
1760static int load_firmware(struct octeon_device *oct)
1761{
1762 int ret = 0;
1763 const struct firmware *fw;
1764 char fw_name[LIO_MAX_FW_FILENAME_LEN];
1765 char *tmp_fw_type;
1766
1767 if (strncmp(fw_type, LIO_FW_NAME_TYPE_NONE,
1768 sizeof(LIO_FW_NAME_TYPE_NONE)) == 0) {
1769 dev_info(&oct->pci_dev->dev, "Skipping firmware load\n");
1770 return ret;
1771 }
1772
1773 if (fw_type[0] == '\0')
1774 tmp_fw_type = LIO_FW_NAME_TYPE_NIC;
1775 else
1776 tmp_fw_type = fw_type;
1777
1778 sprintf(fw_name, "%s%s%s_%s%s", LIO_FW_DIR, LIO_FW_BASE_NAME,
1779 octeon_get_conf(oct)->card_name, tmp_fw_type,
1780 LIO_FW_NAME_SUFFIX);
1781
1782 ret = request_firmware(&fw, fw_name, &oct->pci_dev->dev);
1783 if (ret) {
1784 dev_err(&oct->pci_dev->dev, "Request firmware failed. Could not find file %s.\n.",
1785 fw_name);
d3d7e6c6 1786 release_firmware(fw);
f21fb3ed
RV		 1787 return ret;
1788 }
1789
1790 ret = octeon_download_firmware(oct, fw->data, fw->size);
1791
1792 release_firmware(fw);
1793
1794 return ret;
1795}
1796
1797/**
1798 * \brief Setup output queue
1799 * @param oct octeon device
1800 * @param q_no which queue
1801 * @param num_descs how many descriptors
1802 * @param desc_size size of each descriptor
1803 * @param app_ctx application context
1804 */
1805static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs,
1806 int desc_size, void *app_ctx)
1807{
1808 int ret_val = 0;
1809
1810 dev_dbg(&oct->pci_dev->dev, "Creating Droq: %d\n", q_no);
1811 /* droq creation and local register settings. */
1812 ret_val = octeon_create_droq(oct, q_no, num_descs, desc_size, app_ctx);
08a965ec 1813 if (ret_val < 0)
f21fb3ed
RV		 1814 return ret_val;
1815
1816 if (ret_val == 1) {
1817 dev_dbg(&oct->pci_dev->dev, "Using default droq %d\n", q_no);
1818 return 0;
1819 }
1820 /* tasklet creation for the droq */
1821
1822 /* Enable the droq queues */
1823 octeon_set_droq_pkt_op(oct, q_no, 1);
1824
1825 /* Send Credit for Octeon Output queues. Credits are always
1826 * sent after the output queue is enabled.
1827 */
1828 writel(oct->droq[q_no]->max_count,
1829 oct->droq[q_no]->pkts_credit_reg);
1830
1831 return ret_val;
1832}
1833
1834/**
1835 * \brief Callback for getting interface configuration
1836 * @param status status of request
1837 * @param buf pointer to resp structure
1838 */
1839static void if_cfg_callback(struct octeon_device *oct,
1840 u32 status,
1841 void *buf)
1842{
1843 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
1844 struct liquidio_if_cfg_resp *resp;
1845 struct liquidio_if_cfg_context *ctx;
1846
1847 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
1848 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
1849
1850 oct = lio_get_device(ctx->octeon_id);
1851 if (resp->status)
1852 dev_err(&oct->pci_dev->dev, "nic if cfg instruction failed. Status: %llx\n",
1853 CVM_CAST64(resp->status));
1854 ACCESS_ONCE(ctx->cond) = 1;
1855
d3d7e6c6
RV		 1856 snprintf(oct->fw_info.liquidio_firmware_version, 32, "%s",
1857 resp->cfg_info.liquidio_firmware_version);
1858
f21fb3ed
RV		 1859 /* This barrier is required to be sure that the response has been
1860 * written fully before waking up the handler
1861 */
1862 wmb();
1863
1864 wake_up_interruptible(&ctx->wc);
1865}
1866
1867/**
1868 * \brief Select queue based on hash
1869 * @param dev Net device
1870 * @param skb sk_buff structure
1871 * @returns selected queue number
1872 */
1873static u16 select_q(struct net_device *dev, struct sk_buff *skb,
1874 void *accel_priv, select_queue_fallback_t fallback)
1875{
26236fa9 1876 u32 qindex = 0;
f21fb3ed
RV		 1877 struct lio *lio;
1878
1879 lio = GET_LIO(dev);
26236fa9
RV		 1880 qindex = skb_tx_hash(dev, skb);
1881
1882 return (u16)(qindex % (lio->linfo.num_txpciq));
f21fb3ed
RV		 1883}
1884
1885/** Routine to push packets arriving on Octeon interface upto network layer.
1886 * @param oct_id - octeon device id.
1887 * @param skbuff - skbuff struct to be passed to network layer.
1888 * @param len - size of total data received.
1889 * @param rh - Control header associated with the packet
1890 * @param param - additional control data with the packet
0cece6c5 1891 * @param arg - farg registered in droq_ops
f21fb3ed
RV		 1892 */
1893static void
1894liquidio_push_packet(u32 octeon_id,
1895 void *skbuff,
1896 u32 len,
1897 union octeon_rh *rh,
0cece6c5
RV		 1898 void *param,
1899 void *arg)
f21fb3ed
RV		 1900{
1901 struct napi_struct *napi = param;
f21fb3ed
RV		 1902 struct sk_buff *skb = (struct sk_buff *)skbuff;
1903 struct skb_shared_hwtstamps *shhwtstamps;
1904 u64 ns;
0da0b77c 1905 u16 vtag = 0;
0cece6c5 1906 struct net_device *netdev = (struct net_device *)arg;
f21fb3ed
RV		 1907 struct octeon_droq *droq = container_of(param, struct octeon_droq,
1908 napi);
1909 if (netdev) {
1910 int packet_was_received;
1911 struct lio *lio = GET_LIO(netdev);
a5b37888 1912 struct octeon_device *oct = lio->oct_dev;
f21fb3ed
RV		 1913
1914 /* Do not proceed if the interface is not in RUNNING state. */
1915 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) {
1916 recv_buffer_free(skb);
1917 droq->stats.rx_dropped++;
1918 return;
1919 }
1920
1921 skb->dev = netdev;
1922
26236fa9 1923 skb_record_rx_queue(skb, droq->q_no);
cabeb13b
RV		 1924 if (likely(len > MIN_SKB_SIZE)) {
1925 struct octeon_skb_page_info *pg_info;
1926 unsigned char *va;
1927
1928 pg_info = ((struct octeon_skb_page_info *)(skb->cb));
1929 if (pg_info->page) {
1930 /* For Paged allocation use the frags */
1931 va = page_address(pg_info->page) +
1932 pg_info->page_offset;
1933 memcpy(skb->data, va, MIN_SKB_SIZE);
1934 skb_put(skb, MIN_SKB_SIZE);
1935 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1936 pg_info->page,
1937 pg_info->page_offset +
1938 MIN_SKB_SIZE,
1939 len - MIN_SKB_SIZE,
1940 LIO_RXBUFFER_SZ);
1941 }
1942 } else {
1943 struct octeon_skb_page_info *pg_info =
1944 ((struct octeon_skb_page_info *)(skb->cb));
1945 skb_copy_to_linear_data(skb, page_address(pg_info->page)
1946 + pg_info->page_offset, len);
1947 skb_put(skb, len);
1948 put_page(pg_info->page);
1949 }
26236fa9 1950
a5b37888
RV		 1951 if (((oct->chip_id == OCTEON_CN66XX) ||
1952 (oct->chip_id == OCTEON_CN68XX)) &&
1953 ptp_enable) {
1954 if (rh->r_dh.has_hwtstamp) {
1955 /* timestamp is included from the hardware at
1956 * the beginning of the packet.
f21fb3ed 1957 */
a5b37888
RV		 1958 if (ifstate_check
1959 (lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED)) {
1960 /* Nanoseconds are in the first 64-bits
1961 * of the packet.
1962 */
1963 memcpy(&ns, (skb->data), sizeof(ns));
1964 shhwtstamps = skb_hwtstamps(skb);
1965 shhwtstamps->hwtstamp =
1966 ns_to_ktime(ns +
1967 lio->ptp_adjust);
1968 }
1969 skb_pull(skb, sizeof(ns));
f21fb3ed 1970 }
f21fb3ed
RV		 1971 }
1972
1973 skb->protocol = eth_type_trans(skb, skb->dev);
1974
1975 if ((netdev->features & NETIF_F_RXCSUM) &&
1976 (rh->r_dh.csum_verified == CNNIC_CSUM_VERIFIED))
1977 /* checksum has already been verified */
1978 skb->ip_summed = CHECKSUM_UNNECESSARY;
1979 else
1980 skb->ip_summed = CHECKSUM_NONE;
1981
0da0b77c
RV		 1982 /* inbound VLAN tag */
1983 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1984 (rh->r_dh.vlan != 0)) {
1985 u16 vid = rh->r_dh.vlan;
1986 u16 priority = rh->r_dh.priority;
1987
1988 vtag = priority << 13 | vid;
1989 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
1990 }
1991
f21fb3ed
RV		 1992 packet_was_received = napi_gro_receive(napi, skb) != GRO_DROP;
1993
1994 if (packet_was_received) {
1995 droq->stats.rx_bytes_received += len;
1996 droq->stats.rx_pkts_received++;
1997 netdev->last_rx = jiffies;
1998 } else {
1999 droq->stats.rx_dropped++;
2000 netif_info(lio, rx_err, lio->netdev,
2001 "droq:%d error rx_dropped:%llu\n",
2002 droq->q_no, droq->stats.rx_dropped);
2003 }
2004
2005 } else {
2006 recv_buffer_free(skb);
2007 }
2008}
2009
2010/**
2011 * \brief wrapper for calling napi_schedule
2012 * @param param parameters to pass to napi_schedule
2013 *
2014 * Used when scheduling on different CPUs
2015 */
2016static void napi_schedule_wrapper(void *param)
2017{
2018 struct napi_struct *napi = param;
2019
2020 napi_schedule(napi);
2021}
2022
2023/**
2024 * \brief callback when receive interrupt occurs and we are in NAPI mode
2025 * @param arg pointer to octeon output queue
2026 */
2027static void liquidio_napi_drv_callback(void *arg)
2028{
2029 struct octeon_droq *droq = arg;
2030 int this_cpu = smp_processor_id();
2031
2032 if (droq->cpu_id == this_cpu) {
2033 napi_schedule(&droq->napi);
2034 } else {
2035 struct call_single_data *csd = &droq->csd;
2036
2037 csd->func = napi_schedule_wrapper;
2038 csd->info = &droq->napi;
2039 csd->flags = 0;
2040
2041 smp_call_function_single_async(droq->cpu_id, csd);
2042 }
2043}
2044
f21fb3ed
RV		 2045/**
2046 * \brief Entry point for NAPI polling
2047 * @param napi NAPI structure
2048 * @param budget maximum number of items to process
2049 */
2050static int liquidio_napi_poll(struct napi_struct *napi, int budget)
2051{
2052 struct octeon_droq *droq;
2053 int work_done;
9a96bde4
RV		 2054 int tx_done = 0, iq_no;
2055 struct octeon_instr_queue *iq;
2056 struct octeon_device *oct;
f21fb3ed
RV		 2057
2058 droq = container_of(napi, struct octeon_droq, napi);
9a96bde4
RV		 2059 oct = droq->oct_dev;
2060 iq_no = droq->q_no;
2061 /* Handle Droq descriptors */
2062 work_done = octeon_process_droq_poll_cmd(oct, droq->q_no,
2063 POLL_EVENT_PROCESS_PKTS,
2064 budget);
f21fb3ed 2065
9a96bde4
RV		 2066 /* Flush the instruction queue */
2067 iq = oct->instr_queue[iq_no];
2068 if (iq) {
2069 /* Process iq buffers with in the budget limits */
2070 tx_done = octeon_flush_iq(oct, iq, 1, budget);
2071 /* Update iq read-index rather than waiting for next interrupt.
2072 * Return back if tx_done is false.
2073 */
2074 update_txq_status(oct, iq_no);
2075 /*tx_done = (iq->flush_index == iq->octeon_read_index);*/
2076 } else {
2077 dev_err(&oct->pci_dev->dev, "%s: iq (%d) num invalid\n",
2078 __func__, iq_no);
2079 }
f21fb3ed 2080
9a96bde4 2081 if ((work_done < budget) && (tx_done)) {
f21fb3ed
RV		 2082 napi_complete(napi);
2083 octeon_process_droq_poll_cmd(droq->oct_dev, droq->q_no,
2084 POLL_EVENT_ENABLE_INTR, 0);
2085 return 0;
2086 }
2087
9a96bde4 2088 return (!tx_done) ? (budget) : (work_done);
f21fb3ed
RV		 2089}
2090
2091/**
2092 * \brief Setup input and output queues
2093 * @param octeon_dev octeon device
2094 * @param net_device Net device
2095 *
2096 * Note: Queues are with respect to the octeon device. Thus
2097 * an input queue is for egress packets, and output queues
2098 * are for ingress packets.
2099 */
2100static inline int setup_io_queues(struct octeon_device *octeon_dev,
0cece6c5 2101 int ifidx)
f21fb3ed 2102{
0cece6c5
RV		 2103 struct octeon_droq_ops droq_ops;
2104 struct net_device *netdev;
f21fb3ed
RV		 2105 static int cpu_id;
2106 static int cpu_id_modulus;
2107 struct octeon_droq *droq;
2108 struct napi_struct *napi;
2109 int q, q_no, retval = 0;
2110 struct lio *lio;
2111 int num_tx_descs;
2112
0cece6c5
RV		 2113 netdev = octeon_dev->props[ifidx].netdev;
2114
2115 lio = GET_LIO(netdev);
f21fb3ed 2116
0cece6c5 2117 memset(&droq_ops, 0, sizeof(struct octeon_droq_ops));
f21fb3ed 2118
0cece6c5
RV		 2119 droq_ops.fptr = liquidio_push_packet;
2120 droq_ops.farg = (void *)netdev;
2121
2122 droq_ops.poll_mode = 1;
2123 droq_ops.napi_fn = liquidio_napi_drv_callback;
2124 cpu_id = 0;
2125 cpu_id_modulus = num_present_cpus();
f21fb3ed
RV		 2126
2127 /* set up DROQs. */
2128 for (q = 0; q < lio->linfo.num_rxpciq; q++) {
26236fa9
RV		 2129 q_no = lio->linfo.rxpciq[q].s.q_no;
2130 dev_dbg(&octeon_dev->pci_dev->dev,
2131 "setup_io_queues index:%d linfo.rxpciq.s.q_no:%d\n",
2132 q, q_no);
f21fb3ed
RV		 2133 retval = octeon_setup_droq(octeon_dev, q_no,
2134 CFG_GET_NUM_RX_DESCS_NIC_IF
2135 (octeon_get_conf(octeon_dev),
2136 lio->ifidx),
2137 CFG_GET_NUM_RX_BUF_SIZE_NIC_IF
2138 (octeon_get_conf(octeon_dev),
2139 lio->ifidx), NULL);
2140 if (retval) {
2141 dev_err(&octeon_dev->pci_dev->dev,
2142 " %s : Runtime DROQ(RxQ) creation failed.\n",
2143 __func__);
2144 return 1;
2145 }
2146
2147 droq = octeon_dev->droq[q_no];
2148 napi = &droq->napi;
0cece6c5
RV		 2149 dev_dbg(&octeon_dev->pci_dev->dev,
2150 "netif_napi_add netdev:%llx oct:%llx\n",
2151 (u64)netdev,
2152 (u64)octeon_dev);
2153 netif_napi_add(netdev, napi, liquidio_napi_poll, 64);
f21fb3ed
RV		 2154
2155 /* designate a CPU for this droq */
2156 droq->cpu_id = cpu_id;
2157 cpu_id++;
2158 if (cpu_id >= cpu_id_modulus)
2159 cpu_id = 0;
2160
2161 octeon_register_droq_ops(octeon_dev, q_no, &droq_ops);
2162 }
2163
2164 /* set up IQs. */
2165 for (q = 0; q < lio->linfo.num_txpciq; q++) {
2166 num_tx_descs = CFG_GET_NUM_TX_DESCS_NIC_IF(octeon_get_conf
2167 (octeon_dev),
2168 lio->ifidx);
0cece6c5
RV		 2169 retval = octeon_setup_iq(octeon_dev, ifidx, q,
2170 lio->linfo.txpciq[q], num_tx_descs,
2171 netdev_get_tx_queue(netdev, q));
f21fb3ed
RV		 2172 if (retval) {
2173 dev_err(&octeon_dev->pci_dev->dev,
2174 " %s : Runtime IQ(TxQ) creation failed.\n",
2175 __func__);
2176 return 1;
2177 }
2178 }
2179
2180 return 0;
2181}
2182
2183/**
2184 * \brief Poll routine for checking transmit queue status
2185 * @param work work_struct data structure
2186 */
2187static void octnet_poll_check_txq_status(struct work_struct *work)
2188{
2189 struct cavium_wk *wk = (struct cavium_wk *)work;
2190 struct lio *lio = (struct lio *)wk->ctxptr;
2191
2192 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING))
2193 return;
2194
2195 check_txq_status(lio);
2196 queue_delayed_work(lio->txq_status_wq.wq,
2197 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2198}
2199
2200/**
2201 * \brief Sets up the txq poll check
2202 * @param netdev network device
2203 */
2204static inline void setup_tx_poll_fn(struct net_device *netdev)
2205{
2206 struct lio *lio = GET_LIO(netdev);
2207 struct octeon_device *oct = lio->oct_dev;
2208
292b9dab
BS		 2209 lio->txq_status_wq.wq = alloc_workqueue("txq-status",
2210 WQ_MEM_RECLAIM, 0);
f21fb3ed
RV		 2211 if (!lio->txq_status_wq.wq) {
2212 dev_err(&oct->pci_dev->dev, "unable to create cavium txq status wq\n");
2213 return;
2214 }
2215 INIT_DELAYED_WORK(&lio->txq_status_wq.wk.work,
2216 octnet_poll_check_txq_status);
2217 lio->txq_status_wq.wk.ctxptr = lio;
2218 queue_delayed_work(lio->txq_status_wq.wq,
2219 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2220}
2221
9a96bde4
RV		 2222static inline void cleanup_tx_poll_fn(struct net_device *netdev)
2223{
2224 struct lio *lio = GET_LIO(netdev);
2225
2226 cancel_delayed_work_sync(&lio->txq_status_wq.wk.work);
2227 destroy_workqueue(lio->txq_status_wq.wq);
2228}
2229
f21fb3ed
RV		 2230/**
2231 * \brief Net device open for LiquidIO
2232 * @param netdev network device
2233 */
2234static int liquidio_open(struct net_device *netdev)
2235{
2236 struct lio *lio = GET_LIO(netdev);
2237 struct octeon_device *oct = lio->oct_dev;
2238 struct napi_struct *napi, *n;
2239
9a96bde4
RV		 2240 if (oct->props[lio->ifidx].napi_enabled == 0) {
2241 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
2242 napi_enable(napi);
2243
2244 oct->props[lio->ifidx].napi_enabled = 1;
2245 }
f21fb3ed
RV		 2246
2247 oct_ptp_open(netdev);
2248
2249 ifstate_set(lio, LIO_IFSTATE_RUNNING);
9a96bde4 2250
f21fb3ed 2251 setup_tx_poll_fn(netdev);
9a96bde4 2252
f21fb3ed
RV		 2253 start_txq(netdev);
2254
2255 netif_info(lio, ifup, lio->netdev, "Interface Open, ready for traffic\n");
f21fb3ed
RV		 2256
2257 /* tell Octeon to start forwarding packets to host */
2258 send_rx_ctrl_cmd(lio, 1);
2259
2260 /* Ready for link status updates */
2261 lio->intf_open = 1;
2262
2263 dev_info(&oct->pci_dev->dev, "%s interface is opened\n",
2264 netdev->name);
2265
2266 return 0;
2267}
2268
2269/**
2270 * \brief Net device stop for LiquidIO
2271 * @param netdev network device
2272 */
2273static int liquidio_stop(struct net_device *netdev)
2274{
f21fb3ed
RV		 2275 struct lio *lio = GET_LIO(netdev);
2276 struct octeon_device *oct = lio->oct_dev;
2277
9a96bde4
RV		 2278 ifstate_reset(lio, LIO_IFSTATE_RUNNING);
2279
2280 netif_tx_disable(netdev);
2281
f21fb3ed 2282 /* Inform that netif carrier is down */
9a96bde4 2283 netif_carrier_off(netdev);
f21fb3ed 2284 lio->intf_open = 0;
0cece6c5
RV		 2285 lio->linfo.link.s.link_up = 0;
2286 lio->link_changes++;
f21fb3ed 2287
9a96bde4
RV		 2288 /* Pause for a moment and wait for Octeon to flush out (to the wire) any
2289 * egress packets that are in-flight.
2290 */
2291 set_current_state(TASK_INTERRUPTIBLE);
2292 schedule_timeout(msecs_to_jiffies(100));
f21fb3ed 2293
9a96bde4 2294 /* Now it should be safe to tell Octeon that nic interface is down. */
f21fb3ed
RV		 2295 send_rx_ctrl_cmd(lio, 0);
2296
9a96bde4 2297 cleanup_tx_poll_fn(netdev);
f21fb3ed
RV		 2298
2299 if (lio->ptp_clock) {
2300 ptp_clock_unregister(lio->ptp_clock);
2301 lio->ptp_clock = NULL;
2302 }
2303
f21fb3ed
RV		 2304 dev_info(&oct->pci_dev->dev, "%s interface is stopped\n", netdev->name);
2305 module_put(THIS_MODULE);
2306
2307 return 0;
2308}
2309
2310void liquidio_link_ctrl_cmd_completion(void *nctrl_ptr)
2311{
2312 struct octnic_ctrl_pkt *nctrl = (struct octnic_ctrl_pkt *)nctrl_ptr;
2313 struct net_device *netdev = (struct net_device *)nctrl->netpndev;
2314 struct lio *lio = GET_LIO(netdev);
2315 struct octeon_device *oct = lio->oct_dev;
2316
2317 switch (nctrl->ncmd.s.cmd) {
2318 case OCTNET_CMD_CHANGE_DEVFLAGS:
2319 case OCTNET_CMD_SET_MULTI_LIST:
2320 break;
2321
2322 case OCTNET_CMD_CHANGE_MACADDR:
2323 /* If command is successful, change the MACADDR. */
2324 netif_info(lio, probe, lio->netdev, " MACAddr changed to 0x%llx\n",
2325 CVM_CAST64(nctrl->udd[0]));
2326 dev_info(&oct->pci_dev->dev, "%s MACAddr changed to 0x%llx\n",
2327 netdev->name, CVM_CAST64(nctrl->udd[0]));
2328 memcpy(netdev->dev_addr, ((u8 *)&nctrl->udd[0]) + 2, ETH_ALEN);
2329 break;
2330
2331 case OCTNET_CMD_CHANGE_MTU:
2332 /* If command is successful, change the MTU. */
2333 netif_info(lio, probe, lio->netdev, " MTU Changed from %d to %d\n",
2334 netdev->mtu, nctrl->ncmd.s.param2);
2335 dev_info(&oct->pci_dev->dev, "%s MTU Changed from %d to %d\n",
2336 netdev->name, netdev->mtu,
2337 nctrl->ncmd.s.param2);
2338 netdev->mtu = nctrl->ncmd.s.param2;
2339 break;
2340
2341 case OCTNET_CMD_GPIO_ACCESS:
2342 netif_info(lio, probe, lio->netdev, "LED Flashing visual identification\n");
2343
2344 break;
2345
2346 case OCTNET_CMD_LRO_ENABLE:
2347 dev_info(&oct->pci_dev->dev, "%s LRO Enabled\n", netdev->name);
2348 break;
2349
2350 case OCTNET_CMD_LRO_DISABLE:
2351 dev_info(&oct->pci_dev->dev, "%s LRO Disabled\n",
2352 netdev->name);
2353 break;
2354
2355 case OCTNET_CMD_VERBOSE_ENABLE:
2356 dev_info(&oct->pci_dev->dev, "%s LRO Enabled\n", netdev->name);
2357 break;
2358
2359 case OCTNET_CMD_VERBOSE_DISABLE:
2360 dev_info(&oct->pci_dev->dev, "%s LRO Disabled\n",
2361 netdev->name);
2362 break;
2363
63245f25
RV		 2364 case OCTNET_CMD_ENABLE_VLAN_FILTER:
2365 dev_info(&oct->pci_dev->dev, "%s VLAN filter enabled\n",
2366 netdev->name);
2367 break;
2368
2369 case OCTNET_CMD_ADD_VLAN_FILTER:
2370 dev_info(&oct->pci_dev->dev, "%s VLAN filter %d added\n",
2371 netdev->name, nctrl->ncmd.s.param1);
2372 break;
2373
2374 case OCTNET_CMD_DEL_VLAN_FILTER:
2375 dev_info(&oct->pci_dev->dev, "%s VLAN filter %d removed\n",
2376 netdev->name, nctrl->ncmd.s.param1);
2377 break;
2378
f21fb3ed
RV		 2379 case OCTNET_CMD_SET_SETTINGS:
2380 dev_info(&oct->pci_dev->dev, "%s settings changed\n",
2381 netdev->name);
2382
2383 break;
2384
2385 default:
2386 dev_err(&oct->pci_dev->dev, "%s Unknown cmd %d\n", __func__,
2387 nctrl->ncmd.s.cmd);
2388 }
2389}
2390
2391/**
2392 * \brief Converts a mask based on net device flags
2393 * @param netdev network device
2394 *
2395 * This routine generates a octnet_ifflags mask from the net device flags
2396 * received from the OS.
2397 */
2398static inline enum octnet_ifflags get_new_flags(struct net_device *netdev)
2399{
2400 enum octnet_ifflags f = OCTNET_IFFLAG_UNICAST;
2401
2402 if (netdev->flags & IFF_PROMISC)
2403 f |= OCTNET_IFFLAG_PROMISC;
2404
2405 if (netdev->flags & IFF_ALLMULTI)
2406 f |= OCTNET_IFFLAG_ALLMULTI;
2407
2408 if (netdev->flags & IFF_MULTICAST) {
2409 f |= OCTNET_IFFLAG_MULTICAST;
2410
2411 /* Accept all multicast addresses if there are more than we
2412 * can handle
2413 */
2414 if (netdev_mc_count(netdev) > MAX_OCTEON_MULTICAST_ADDR)
2415 f |= OCTNET_IFFLAG_ALLMULTI;
2416 }
2417
2418 if (netdev->flags & IFF_BROADCAST)
2419 f |= OCTNET_IFFLAG_BROADCAST;
2420
2421 return f;
2422}
2423
2424/**
2425 * \brief Net device set_multicast_list
2426 * @param netdev network device
2427 */
2428static void liquidio_set_mcast_list(struct net_device *netdev)
2429{
2430 struct lio *lio = GET_LIO(netdev);
2431 struct octeon_device *oct = lio->oct_dev;
2432 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2433 struct netdev_hw_addr *ha;
2434 u64 *mc;
2435 int ret, i;
2436 int mc_count = min(netdev_mc_count(netdev), MAX_OCTEON_MULTICAST_ADDR);
2437
2438 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2439
2440 /* Create a ctrl pkt command to be sent to core app. */
2441 nctrl.ncmd.u64 = 0;
2442 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_MULTI_LIST;
0cece6c5
RV		 2443 nctrl.ncmd.s.param1 = get_new_flags(netdev);
2444 nctrl.ncmd.s.param2 = mc_count;
f21fb3ed 2445 nctrl.ncmd.s.more = mc_count;
0cece6c5 2446 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2447 nctrl.netpndev = (u64)netdev;
2448 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2449
2450 /* copy all the addresses into the udd */
2451 i = 0;
2452 mc = &nctrl.udd[0];
2453 netdev_for_each_mc_addr(ha, netdev) {
2454 *mc = 0;
2455 memcpy(((u8 *)mc) + 2, ha->addr, ETH_ALEN);
2456 /* no need to swap bytes */
2457
2458 if (++mc > &nctrl.udd[mc_count])
2459 break;
2460 }
2461
2462 /* Apparently, any activity in this call from the kernel has to
2463 * be atomic. So we won't wait for response.
2464 */
2465 nctrl.wait_time = 0;
2466
0cece6c5 2467 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2468 if (ret < 0) {
2469 dev_err(&oct->pci_dev->dev, "DEVFLAGS change failed in core (ret: 0x%x)\n",
2470 ret);
2471 }
2472}
2473
2474/**
2475 * \brief Net device set_mac_address
2476 * @param netdev network device
2477 */
2478static int liquidio_set_mac(struct net_device *netdev, void *p)
2479{
2480 int ret = 0;
2481 struct lio *lio = GET_LIO(netdev);
2482 struct octeon_device *oct = lio->oct_dev;
2483 struct sockaddr *addr = (struct sockaddr *)p;
2484 struct octnic_ctrl_pkt nctrl;
f21fb3ed 2485
0cece6c5 2486 if (!is_valid_ether_addr(addr->sa_data))
f21fb3ed
RV		 2487 return -EADDRNOTAVAIL;
2488
2489 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2490
2491 nctrl.ncmd.u64 = 0;
2492 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
0cece6c5 2493 nctrl.ncmd.s.param1 = 0;
f21fb3ed 2494 nctrl.ncmd.s.more = 1;
0cece6c5 2495 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2496 nctrl.netpndev = (u64)netdev;
2497 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2498 nctrl.wait_time = 100;
2499
2500 nctrl.udd[0] = 0;
2501 /* The MAC Address is presented in network byte order. */
2502 memcpy((u8 *)&nctrl.udd[0] + 2, addr->sa_data, ETH_ALEN);
2503
0cece6c5 2504 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2505 if (ret < 0) {
2506 dev_err(&oct->pci_dev->dev, "MAC Address change failed\n");
2507 return -ENOMEM;
2508 }
2509 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2510 memcpy(((u8 *)&lio->linfo.hw_addr) + 2, addr->sa_data, ETH_ALEN);
2511
2512 return 0;
2513}
2514
2515/**
2516 * \brief Net device get_stats
2517 * @param netdev network device
2518 */
2519static struct net_device_stats *liquidio_get_stats(struct net_device *netdev)
2520{
2521 struct lio *lio = GET_LIO(netdev);
2522 struct net_device_stats *stats = &netdev->stats;
2523 struct octeon_device *oct;
2524 u64 pkts = 0, drop = 0, bytes = 0;
2525 struct oct_droq_stats *oq_stats;
2526 struct oct_iq_stats *iq_stats;
2527 int i, iq_no, oq_no;
2528
2529 oct = lio->oct_dev;
2530
2531 for (i = 0; i < lio->linfo.num_txpciq; i++) {
26236fa9 2532 iq_no = lio->linfo.txpciq[i].s.q_no;
f21fb3ed
RV		 2533 iq_stats = &oct->instr_queue[iq_no]->stats;
2534 pkts += iq_stats->tx_done;
2535 drop += iq_stats->tx_dropped;
2536 bytes += iq_stats->tx_tot_bytes;
2537 }
2538
2539 stats->tx_packets = pkts;
2540 stats->tx_bytes = bytes;
2541 stats->tx_dropped = drop;
2542
2543 pkts = 0;
2544 drop = 0;
2545 bytes = 0;
2546
2547 for (i = 0; i < lio->linfo.num_rxpciq; i++) {
26236fa9 2548 oq_no = lio->linfo.rxpciq[i].s.q_no;
f21fb3ed
RV		 2549 oq_stats = &oct->droq[oq_no]->stats;
2550 pkts += oq_stats->rx_pkts_received;
2551 drop += (oq_stats->rx_dropped +
2552 oq_stats->dropped_nodispatch +
2553 oq_stats->dropped_toomany +
2554 oq_stats->dropped_nomem);
2555 bytes += oq_stats->rx_bytes_received;
2556 }
2557
2558 stats->rx_bytes = bytes;
2559 stats->rx_packets = pkts;
2560 stats->rx_dropped = drop;
2561
2562 return stats;
2563}
2564
2565/**
2566 * \brief Net device change_mtu
2567 * @param netdev network device
2568 */
2569static int liquidio_change_mtu(struct net_device *netdev, int new_mtu)
2570{
2571 struct lio *lio = GET_LIO(netdev);
2572 struct octeon_device *oct = lio->oct_dev;
2573 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2574 int max_frm_size = new_mtu + OCTNET_FRM_HEADER_SIZE;
2575 int ret = 0;
2576
2577 /* Limit the MTU to make sure the ethernet packets are between 64 bytes
2578 * and 65535 bytes
2579 */
2580 if ((max_frm_size < OCTNET_MIN_FRM_SIZE) ||
2581 (max_frm_size > OCTNET_MAX_FRM_SIZE)) {
2582 dev_err(&oct->pci_dev->dev, "Invalid MTU: %d\n", new_mtu);
2583 dev_err(&oct->pci_dev->dev, "Valid range %d and %d\n",
2584 (OCTNET_MIN_FRM_SIZE - OCTNET_FRM_HEADER_SIZE),
2585 (OCTNET_MAX_FRM_SIZE - OCTNET_FRM_HEADER_SIZE));
2586 return -EINVAL;
2587 }
2588
2589 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2590
2591 nctrl.ncmd.u64 = 0;
2592 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MTU;
0cece6c5
RV		 2593 nctrl.ncmd.s.param1 = new_mtu;
2594 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2595 nctrl.wait_time = 100;
2596 nctrl.netpndev = (u64)netdev;
2597 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2598
0cece6c5 2599 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2600 if (ret < 0) {
2601 dev_err(&oct->pci_dev->dev, "Failed to set MTU\n");
2602 return -1;
2603 }
2604
2605 lio->mtu = new_mtu;
2606
2607 return 0;
2608}
2609
2610/**
2611 * \brief Handler for SIOCSHWTSTAMP ioctl
2612 * @param netdev network device
2613 * @param ifr interface request
2614 * @param cmd command
2615 */
2616static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2617{
2618 struct hwtstamp_config conf;
2619 struct lio *lio = GET_LIO(netdev);
2620
2621 if (copy_from_user(&conf, ifr->ifr_data, sizeof(conf)))
2622 return -EFAULT;
2623
2624 if (conf.flags)
2625 return -EINVAL;
2626
2627 switch (conf.tx_type) {
2628 case HWTSTAMP_TX_ON:
2629 case HWTSTAMP_TX_OFF:
2630 break;
2631 default:
2632 return -ERANGE;
2633 }
2634
2635 switch (conf.rx_filter) {
2636 case HWTSTAMP_FILTER_NONE:
2637 break;
2638 case HWTSTAMP_FILTER_ALL:
2639 case HWTSTAMP_FILTER_SOME:
2640 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2641 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2642 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2643 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2644 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2645 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2646 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2647 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2648 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2649 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2650 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2651 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2652 conf.rx_filter = HWTSTAMP_FILTER_ALL;
2653 break;
2654 default:
2655 return -ERANGE;
2656 }
2657
2658 if (conf.rx_filter == HWTSTAMP_FILTER_ALL)
2659 ifstate_set(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
2660
2661 else
2662 ifstate_reset(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
2663
2664 return copy_to_user(ifr->ifr_data, &conf, sizeof(conf)) ? -EFAULT : 0;
2665}
2666
2667/**
2668 * \brief ioctl handler
2669 * @param netdev network device
2670 * @param ifr interface request
2671 * @param cmd command
2672 */
2673static int liquidio_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2674{
2675 switch (cmd) {
2676 case SIOCSHWTSTAMP:
2677 return hwtstamp_ioctl(netdev, ifr, cmd);
2678 default:
2679 return -EOPNOTSUPP;
2680 }
2681}
2682
2683/**
2684 * \brief handle a Tx timestamp response
2685 * @param status response status
2686 * @param buf pointer to skb
2687 */
2688static void handle_timestamp(struct octeon_device *oct,
2689 u32 status,
2690 void *buf)
2691{
2692 struct octnet_buf_free_info *finfo;
2693 struct octeon_soft_command *sc;
2694 struct oct_timestamp_resp *resp;
2695 struct lio *lio;
2696 struct sk_buff *skb = (struct sk_buff *)buf;
2697
2698 finfo = (struct octnet_buf_free_info *)skb->cb;
2699 lio = finfo->lio;
2700 sc = finfo->sc;
2701 oct = lio->oct_dev;
2702 resp = (struct oct_timestamp_resp *)sc->virtrptr;
2703
2704 if (status != OCTEON_REQUEST_DONE) {
2705 dev_err(&oct->pci_dev->dev, "Tx timestamp instruction failed. Status: %llx\n",
2706 CVM_CAST64(status));
2707 resp->timestamp = 0;
2708 }
2709
2710 octeon_swap_8B_data(&resp->timestamp, 1);
2711
19a6d156 2712 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) != 0)) {
f21fb3ed
RV		 2713 struct skb_shared_hwtstamps ts;
2714 u64 ns = resp->timestamp;
2715
2716 netif_info(lio, tx_done, lio->netdev,
2717 "Got resulting SKBTX_HW_TSTAMP skb=%p ns=%016llu\n",
2718 skb, (unsigned long long)ns);
2719 ts.hwtstamp = ns_to_ktime(ns + lio->ptp_adjust);
2720 skb_tstamp_tx(skb, &ts);
2721 }
2722
2723 octeon_free_soft_command(oct, sc);
cabeb13b 2724 tx_buffer_free(skb);
f21fb3ed
RV		 2725}
2726
2727/* \brief Send a data packet that will be timestamped
2728 * @param oct octeon device
2729 * @param ndata pointer to network data
2730 * @param finfo pointer to private network data
2731 */
2732static inline int send_nic_timestamp_pkt(struct octeon_device *oct,
2733 struct octnic_data_pkt *ndata,
2734 struct octnet_buf_free_info *finfo,
2735 int xmit_more)
2736{
2737 int retval;
2738 struct octeon_soft_command *sc;
f21fb3ed
RV		 2739 struct lio *lio;
2740 int ring_doorbell;
6a885b60 2741 u32 len;
f21fb3ed
RV		 2742
2743 lio = finfo->lio;
2744
2745 sc = octeon_alloc_soft_command_resp(oct, &ndata->cmd,
2746 sizeof(struct oct_timestamp_resp));
2747 finfo->sc = sc;
2748
2749 if (!sc) {
2750 dev_err(&oct->pci_dev->dev, "No memory for timestamped data packet\n");
2751 return IQ_SEND_FAILED;
2752 }
2753
2754 if (ndata->reqtype == REQTYPE_NORESP_NET)
2755 ndata->reqtype = REQTYPE_RESP_NET;
2756 else if (ndata->reqtype == REQTYPE_NORESP_NET_SG)
2757 ndata->reqtype = REQTYPE_RESP_NET_SG;
2758
2759 sc->callback = handle_timestamp;
2760 sc->callback_arg = finfo->skb;
2761 sc->iq_no = ndata->q_no;
2762
6a885b60 2763 len = (u32)((struct octeon_instr_ih2 *)(&sc->cmd.cmd2.ih2))->dlengsz;
f21fb3ed
RV		 2764
2765 ring_doorbell = !xmit_more;
2766 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd,
6a885b60 2767 sc, len, ndata->reqtype);
f21fb3ed 2768
ddc173a6 2769 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 2770 dev_err(&oct->pci_dev->dev, "timestamp data packet failed status: %x\n",
2771 retval);
2772 octeon_free_soft_command(oct, sc);
2773 } else {
2774 netif_info(lio, tx_queued, lio->netdev, "Queued timestamp packet\n");
2775 }
2776
2777 return retval;
2778}
2779
f21fb3ed
RV		 2780/** \brief Transmit networks packets to the Octeon interface
2781 * @param skbuff skbuff struct to be passed to network layer.
2782 * @param netdev pointer to network device
2783 * @returns whether the packet was transmitted to the device okay or not
2784 * (NETDEV_TX_OK or NETDEV_TX_BUSY)
2785 */
2786static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev)
2787{
2788 struct lio *lio;
2789 struct octnet_buf_free_info *finfo;
2790 union octnic_cmd_setup cmdsetup;
2791 struct octnic_data_pkt ndata;
2792 struct octeon_device *oct;
2793 struct oct_iq_stats *stats;
6a885b60
RV		 2794 struct octeon_instr_irh *irh;
2795 union tx_info *tx_info;
26236fa9 2796 int status = 0;
f21fb3ed 2797 int q_idx = 0, iq_no = 0;
fcd2b5e3
RV		 2798 int xmit_more, j;
2799 u64 dptr = 0;
f21fb3ed
RV		 2800 u32 tag = 0;
2801
2802 lio = GET_LIO(netdev);
2803 oct = lio->oct_dev;
2804
2805 if (netif_is_multiqueue(netdev)) {
26236fa9
RV		 2806 q_idx = skb->queue_mapping;
2807 q_idx = (q_idx % (lio->linfo.num_txpciq));
2808 tag = q_idx;
2809 iq_no = lio->linfo.txpciq[q_idx].s.q_no;
f21fb3ed
RV		 2810 } else {
2811 iq_no = lio->txq;
2812 }
2813
2814 stats = &oct->instr_queue[iq_no]->stats;
2815
2816 /* Check for all conditions in which the current packet cannot be
2817 * transmitted.
2818 */
2819 if (!(atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) ||
0cece6c5 2820 (!lio->linfo.link.s.link_up) ||
f21fb3ed
RV		 2821 (skb->len <= 0)) {
2822 netif_info(lio, tx_err, lio->netdev,
2823 "Transmit failed link_status : %d\n",
0cece6c5 2824 lio->linfo.link.s.link_up);
f21fb3ed
RV		 2825 goto lio_xmit_failed;
2826 }
2827
2828 /* Use space in skb->cb to store info used to unmap and
2829 * free the buffers.
2830 */
2831 finfo = (struct octnet_buf_free_info *)skb->cb;
2832 finfo->lio = lio;
2833 finfo->skb = skb;
2834 finfo->sc = NULL;
2835
2836 /* Prepare the attributes for the data to be passed to OSI. */
2837 memset(&ndata, 0, sizeof(struct octnic_data_pkt));
2838
2839 ndata.buf = (void *)finfo;
2840
2841 ndata.q_no = iq_no;
2842
2843 if (netif_is_multiqueue(netdev)) {
2844 if (octnet_iq_is_full(oct, ndata.q_no)) {
2845 /* defer sending if queue is full */
2846 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
2847 ndata.q_no);
2848 stats->tx_iq_busy++;
2849 return NETDEV_TX_BUSY;
2850 }
2851 } else {
2852 if (octnet_iq_is_full(oct, lio->txq)) {
2853 /* defer sending if queue is full */
2854 stats->tx_iq_busy++;
2855 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
2856 ndata.q_no);
2857 return NETDEV_TX_BUSY;
2858 }
2859 }
2860 /* pr_info(" XMIT - valid Qs: %d, 1st Q no: %d, cpu: %d, q_no:%d\n",
2861 * lio->linfo.num_txpciq, lio->txq, cpu, ndata.q_no );
2862 */
2863
2864 ndata.datasize = skb->len;
2865
2866 cmdsetup.u64 = 0;
7275ebfc 2867 cmdsetup.s.iq_no = iq_no;
f21fb3ed 2868
7275ebfc
RV		 2869 if (skb->ip_summed == CHECKSUM_PARTIAL)
2870 cmdsetup.s.transport_csum = 1;
f21fb3ed 2871
f21fb3ed
RV		 2872 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
2873 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2874 cmdsetup.s.timestamp = 1;
2875 }
2876
2877 if (skb_shinfo(skb)->nr_frags == 0) {
2878 cmdsetup.s.u.datasize = skb->len;
0cece6c5 2879 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
f21fb3ed 2880 /* Offload checksum calculation for TCP/UDP packets */
6a885b60
RV		 2881 dptr = dma_map_single(&oct->pci_dev->dev,
2882 skb->data,
2883 skb->len,
2884 DMA_TO_DEVICE);
2885 if (dma_mapping_error(&oct->pci_dev->dev, dptr)) {
f21fb3ed
RV		 2886 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 1\n",
2887 __func__);
2888 return NETDEV_TX_BUSY;
2889 }
2890
6a885b60
RV		 2891 ndata.cmd.cmd2.dptr = dptr;
2892 finfo->dptr = dptr;
f21fb3ed
RV		 2893 ndata.reqtype = REQTYPE_NORESP_NET;
2894
2895 } else {
2896 int i, frags;
2897 struct skb_frag_struct *frag;
2898 struct octnic_gather *g;
2899
fcd2b5e3
RV		 2900 spin_lock(&lio->glist_lock[q_idx]);
2901 g = (struct octnic_gather *)
2902 list_delete_head(&lio->glist[q_idx]);
2903 spin_unlock(&lio->glist_lock[q_idx]);
f21fb3ed
RV		 2904
2905 if (!g) {
2906 netif_info(lio, tx_err, lio->netdev,
2907 "Transmit scatter gather: glist null!\n");
2908 goto lio_xmit_failed;
2909 }
2910
2911 cmdsetup.s.gather = 1;
2912 cmdsetup.s.u.gatherptrs = (skb_shinfo(skb)->nr_frags + 1);
0cece6c5 2913 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
f21fb3ed
RV		 2914
2915 memset(g->sg, 0, g->sg_size);
2916
2917 g->sg[0].ptr[0] = dma_map_single(&oct->pci_dev->dev,
2918 skb->data,
2919 (skb->len - skb->data_len),
2920 DMA_TO_DEVICE);
2921 if (dma_mapping_error(&oct->pci_dev->dev, g->sg[0].ptr[0])) {
2922 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 2\n",
2923 __func__);
2924 return NETDEV_TX_BUSY;
2925 }
2926 add_sg_size(&g->sg[0], (skb->len - skb->data_len), 0);
2927
2928 frags = skb_shinfo(skb)->nr_frags;
2929 i = 1;
2930 while (frags--) {
2931 frag = &skb_shinfo(skb)->frags[i - 1];
2932
2933 g->sg[(i >> 2)].ptr[(i & 3)] =
2934 dma_map_page(&oct->pci_dev->dev,
2935 frag->page.p,
2936 frag->page_offset,
2937 frag->size,
2938 DMA_TO_DEVICE);
2939
fcd2b5e3
RV		 2940 if (dma_mapping_error(&oct->pci_dev->dev,
2941 g->sg[i >> 2].ptr[i & 3])) {
2942 dma_unmap_single(&oct->pci_dev->dev,
2943 g->sg[0].ptr[0],
2944 skb->len - skb->data_len,
2945 DMA_TO_DEVICE);
2946 for (j = 1; j < i; j++) {
2947 frag = &skb_shinfo(skb)->frags[j - 1];
2948 dma_unmap_page(&oct->pci_dev->dev,
2949 g->sg[j >> 2].ptr[j & 3],
2950 frag->size,
2951 DMA_TO_DEVICE);
2952 }
2953 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 3\n",
2954 __func__);
2955 return NETDEV_TX_BUSY;
2956 }
2957
f21fb3ed
RV		 2958 add_sg_size(&g->sg[(i >> 2)], frag->size, (i & 3));
2959 i++;
2960 }
2961
fcd2b5e3
RV		 2962 dma_sync_single_for_device(&oct->pci_dev->dev, g->sg_dma_ptr,
2963 g->sg_size, DMA_TO_DEVICE);
2964 dptr = g->sg_dma_ptr;
f21fb3ed 2965
6a885b60
RV		 2966 ndata.cmd.cmd2.dptr = dptr;
2967 finfo->dptr = dptr;
f21fb3ed
RV		 2968 finfo->g = g;
2969
2970 ndata.reqtype = REQTYPE_NORESP_NET_SG;
2971 }
2972
6a885b60
RV		 2973 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd2.irh;
2974 tx_info = (union tx_info *)&ndata.cmd.cmd2.ossp[0];
f21fb3ed 2975
6a885b60 2976 if (skb_shinfo(skb)->gso_size) {
f21fb3ed
RV		 2977 tx_info->s.gso_size = skb_shinfo(skb)->gso_size;
2978 tx_info->s.gso_segs = skb_shinfo(skb)->gso_segs;
2979 }
0da0b77c
RV		 2980 /* HW insert VLAN tag */
2981 if (skb_vlan_tag_present(skb)) {
2982 irh->priority = skb_vlan_tag_get(skb) >> 13;
2983 irh->vlan = skb_vlan_tag_get(skb) & 0xfff;
2984 }
f21fb3ed
RV		 2985
2986 xmit_more = skb->xmit_more;
2987
2988 if (unlikely(cmdsetup.s.timestamp))
2989 status = send_nic_timestamp_pkt(oct, &ndata, finfo, xmit_more);
2990 else
2991 status = octnet_send_nic_data_pkt(oct, &ndata, xmit_more);
2992 if (status == IQ_SEND_FAILED)
2993 goto lio_xmit_failed;
2994
2995 netif_info(lio, tx_queued, lio->netdev, "Transmit queued successfully\n");
2996
2997 if (status == IQ_SEND_STOP)
2998 stop_q(lio->netdev, q_idx);
2999
860e9538 3000 netif_trans_update(netdev);
f21fb3ed
RV		 3001
3002 stats->tx_done++;
3003 stats->tx_tot_bytes += skb->len;
3004
3005 return NETDEV_TX_OK;
3006
3007lio_xmit_failed:
3008 stats->tx_dropped++;
3009 netif_info(lio, tx_err, lio->netdev, "IQ%d Transmit dropped:%llu\n",
3010 iq_no, stats->tx_dropped);
6a885b60
RV		 3011 if (dptr)
3012 dma_unmap_single(&oct->pci_dev->dev, dptr,
3013 ndata.datasize, DMA_TO_DEVICE);
cabeb13b 3014 tx_buffer_free(skb);
f21fb3ed
RV		 3015 return NETDEV_TX_OK;
3016}
3017
3018/** \brief Network device Tx timeout
3019 * @param netdev pointer to network device
3020 */
3021static void liquidio_tx_timeout(struct net_device *netdev)
3022{
3023 struct lio *lio;
3024
3025 lio = GET_LIO(netdev);
3026
3027 netif_info(lio, tx_err, lio->netdev,
3028 "Transmit timeout tx_dropped:%ld, waking up queues now!!\n",
3029 netdev->stats.tx_dropped);
860e9538 3030 netif_trans_update(netdev);
f21fb3ed
RV		 3031 txqs_wake(netdev);
3032}
3033
63245f25
RV		 3034static int liquidio_vlan_rx_add_vid(struct net_device *netdev,
3035 __be16 proto __attribute__((unused)),
3036 u16 vid)
3037{
3038 struct lio *lio = GET_LIO(netdev);
3039 struct octeon_device *oct = lio->oct_dev;
3040 struct octnic_ctrl_pkt nctrl;
3041 int ret = 0;
3042
3043 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3044
3045 nctrl.ncmd.u64 = 0;
3046 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER;
3047 nctrl.ncmd.s.param1 = vid;
3048 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3049 nctrl.wait_time = 100;
3050 nctrl.netpndev = (u64)netdev;
3051 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3052
3053 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3054 if (ret < 0) {
3055 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
3056 ret);
3057 }
3058
3059 return ret;
3060}
3061
3062static int liquidio_vlan_rx_kill_vid(struct net_device *netdev,
3063 __be16 proto __attribute__((unused)),
3064 u16 vid)
3065{
3066 struct lio *lio = GET_LIO(netdev);
3067 struct octeon_device *oct = lio->oct_dev;
3068 struct octnic_ctrl_pkt nctrl;
3069 int ret = 0;
3070
3071 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3072
3073 nctrl.ncmd.u64 = 0;
3074 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER;
3075 nctrl.ncmd.s.param1 = vid;
3076 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3077 nctrl.wait_time = 100;
3078 nctrl.netpndev = (u64)netdev;
3079 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3080
3081 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3082 if (ret < 0) {
3083 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
3084 ret);
3085 }
3086 return ret;
3087}
3088
0cece6c5 3089int liquidio_set_feature(struct net_device *netdev, int cmd, u16 param1)
f21fb3ed
RV		 3090{
3091 struct lio *lio = GET_LIO(netdev);
3092 struct octeon_device *oct = lio->oct_dev;
3093 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 3094 int ret = 0;
3095
3096 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3097
3098 nctrl.ncmd.u64 = 0;
3099 nctrl.ncmd.s.cmd = cmd;
0cece6c5
RV		 3100 nctrl.ncmd.s.param1 = param1;
3101 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 3102 nctrl.wait_time = 100;
3103 nctrl.netpndev = (u64)netdev;
3104 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3105
0cece6c5 3106 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 3107 if (ret < 0) {
3108 dev_err(&oct->pci_dev->dev, "Feature change failed in core (ret: 0x%x)\n",
3109 ret);
3110 }
3111 return ret;
3112}
3113
3114/** \brief Net device fix features
3115 * @param netdev pointer to network device
3116 * @param request features requested
3117 * @returns updated features list
3118 */
3119static netdev_features_t liquidio_fix_features(struct net_device *netdev,
3120 netdev_features_t request)
3121{
3122 struct lio *lio = netdev_priv(netdev);
3123
3124 if ((request & NETIF_F_RXCSUM) &&
3125 !(lio->dev_capability & NETIF_F_RXCSUM))
3126 request &= ~NETIF_F_RXCSUM;
3127
3128 if ((request & NETIF_F_HW_CSUM) &&
3129 !(lio->dev_capability & NETIF_F_HW_CSUM))
3130 request &= ~NETIF_F_HW_CSUM;
3131
3132 if ((request & NETIF_F_TSO) && !(lio->dev_capability & NETIF_F_TSO))
3133 request &= ~NETIF_F_TSO;
3134
3135 if ((request & NETIF_F_TSO6) && !(lio->dev_capability & NETIF_F_TSO6))
3136 request &= ~NETIF_F_TSO6;
3137
3138 if ((request & NETIF_F_LRO) && !(lio->dev_capability & NETIF_F_LRO))
3139 request &= ~NETIF_F_LRO;
3140
3141 /*Disable LRO if RXCSUM is off */
3142 if (!(request & NETIF_F_RXCSUM) && (netdev->features & NETIF_F_LRO) &&
3143 (lio->dev_capability & NETIF_F_LRO))
3144 request &= ~NETIF_F_LRO;
3145
3146 return request;
3147}
3148
3149/** \brief Net device set features
3150 * @param netdev pointer to network device
3151 * @param features features to enable/disable
3152 */
3153static int liquidio_set_features(struct net_device *netdev,
3154 netdev_features_t features)
3155{
3156 struct lio *lio = netdev_priv(netdev);
3157
3158 if (!((netdev->features ^ features) & NETIF_F_LRO))
3159 return 0;
3160
3161 if ((features & NETIF_F_LRO) && (lio->dev_capability & NETIF_F_LRO))
0cece6c5
RV		 3162 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
3163 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed
RV		 3164 else if (!(features & NETIF_F_LRO) &&
3165 (lio->dev_capability & NETIF_F_LRO))
0cece6c5
RV		 3166 liquidio_set_feature(netdev, OCTNET_CMD_LRO_DISABLE,
3167 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed
RV		 3168
3169 return 0;
3170}
3171
3172static struct net_device_ops lionetdevops = {
3173 .ndo_open = liquidio_open,
3174 .ndo_stop = liquidio_stop,
3175 .ndo_start_xmit = liquidio_xmit,
3176 .ndo_get_stats = liquidio_get_stats,
3177 .ndo_set_mac_address = liquidio_set_mac,
3178 .ndo_set_rx_mode = liquidio_set_mcast_list,
3179 .ndo_tx_timeout = liquidio_tx_timeout,
63245f25
RV		 3180
3181 .ndo_vlan_rx_add_vid = liquidio_vlan_rx_add_vid,
3182 .ndo_vlan_rx_kill_vid = liquidio_vlan_rx_kill_vid,
f21fb3ed
RV		 3183 .ndo_change_mtu = liquidio_change_mtu,
3184 .ndo_do_ioctl = liquidio_ioctl,
3185 .ndo_fix_features = liquidio_fix_features,
3186 .ndo_set_features = liquidio_set_features,
3187};
3188
3189/** \brief Entry point for the liquidio module
3190 */
3191static int __init liquidio_init(void)
3192{
3193 int i;
3194 struct handshake *hs;
3195
3196 init_completion(&first_stage);
3197
3198 octeon_init_device_list(conf_type);
3199
3200 if (liquidio_init_pci())
3201 return -EINVAL;
3202
3203 wait_for_completion_timeout(&first_stage, msecs_to_jiffies(1000));
3204
3205 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3206 hs = &handshake[i];
3207 if (hs->pci_dev) {
3208 wait_for_completion(&hs->init);
3209 if (!hs->init_ok) {
3210 /* init handshake failed */
3211 dev_err(&hs->pci_dev->dev,
3212 "Failed to init device\n");
3213 liquidio_deinit_pci();
3214 return -EIO;
3215 }
3216 }
3217 }
3218
3219 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3220 hs = &handshake[i];
3221 if (hs->pci_dev) {
3222 wait_for_completion_timeout(&hs->started,
3223 msecs_to_jiffies(30000));
3224 if (!hs->started_ok) {
3225 /* starter handshake failed */
3226 dev_err(&hs->pci_dev->dev,
3227 "Firmware failed to start\n");
3228 liquidio_deinit_pci();
3229 return -EIO;
3230 }
3231 }
3232 }
3233
3234 return 0;
3235}
3236
5b173cf9 3237static int lio_nic_info(struct octeon_recv_info *recv_info, void *buf)
f21fb3ed
RV		 3238{
3239 struct octeon_device *oct = (struct octeon_device *)buf;
3240 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
0cece6c5 3241 int gmxport = 0;
f21fb3ed
RV		 3242 union oct_link_status *ls;
3243 int i;
3244
0cece6c5 3245 if (recv_pkt->buffer_size[0] != sizeof(*ls)) {
f21fb3ed
RV		 3246 dev_err(&oct->pci_dev->dev, "Malformed NIC_INFO, len=%d, ifidx=%d\n",
3247 recv_pkt->buffer_size[0],
0cece6c5 3248 recv_pkt->rh.r_nic_info.gmxport);
f21fb3ed
RV		 3249 goto nic_info_err;
3250 }
3251
0cece6c5 3252 gmxport = recv_pkt->rh.r_nic_info.gmxport;
f21fb3ed
RV		 3253 ls = (union oct_link_status *)get_rbd(recv_pkt->buffer_ptr[0]);
3254
3255 octeon_swap_8B_data((u64 *)ls, (sizeof(union oct_link_status)) >> 3);
0cece6c5
RV		 3256 for (i = 0; i < oct->ifcount; i++) {
3257 if (oct->props[i].gmxport == gmxport) {
3258 update_link_status(oct->props[i].netdev, ls);
3259 break;
3260 }
3261 }
f21fb3ed
RV		 3262
3263nic_info_err:
3264 for (i = 0; i < recv_pkt->buffer_count; i++)
3265 recv_buffer_free(recv_pkt->buffer_ptr[i]);
3266 octeon_free_recv_info(recv_info);
3267 return 0;
3268}
3269
3270/**
3271 * \brief Setup network interfaces
3272 * @param octeon_dev octeon device
3273 *
3274 * Called during init time for each device. It assumes the NIC
3275 * is already up and running. The link information for each
3276 * interface is passed in link_info.
3277 */
3278static int setup_nic_devices(struct octeon_device *octeon_dev)
3279{
3280 struct lio *lio = NULL;
3281 struct net_device *netdev;
3282 u8 mac[6], i, j;
3283 struct octeon_soft_command *sc;
3284 struct liquidio_if_cfg_context *ctx;
3285 struct liquidio_if_cfg_resp *resp;
3286 struct octdev_props *props;
26236fa9 3287 int retval, num_iqueues, num_oqueues;
f21fb3ed
RV		 3288 int num_cpus = num_online_cpus();
3289 union oct_nic_if_cfg if_cfg;
3290 unsigned int base_queue;
3291 unsigned int gmx_port_id;
3292 u32 resp_size, ctx_size;
0cece6c5 3293 u32 ifidx_or_pfnum;
f21fb3ed
RV		 3294
3295 /* This is to handle link status changes */
3296 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3297 OPCODE_NIC_INFO,
3298 lio_nic_info, octeon_dev);
3299
3300 /* REQTYPE_RESP_NET and REQTYPE_SOFT_COMMAND do not have free functions.
3301 * They are handled directly.
3302 */
3303 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET,
3304 free_netbuf);
3305
3306 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET_SG,
3307 free_netsgbuf);
3308
3309 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_RESP_NET_SG,
3310 free_netsgbuf_with_resp);
3311
3312 for (i = 0; i < octeon_dev->ifcount; i++) {
3313 resp_size = sizeof(struct liquidio_if_cfg_resp);
3314 ctx_size = sizeof(struct liquidio_if_cfg_context);
3315 sc = (struct octeon_soft_command *)
3316 octeon_alloc_soft_command(octeon_dev, 0,
3317 resp_size, ctx_size);
3318 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
3319 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
3320
3321 num_iqueues =
3322 CFG_GET_NUM_TXQS_NIC_IF(octeon_get_conf(octeon_dev), i);
3323 num_oqueues =
3324 CFG_GET_NUM_RXQS_NIC_IF(octeon_get_conf(octeon_dev), i);
3325 base_queue =
3326 CFG_GET_BASE_QUE_NIC_IF(octeon_get_conf(octeon_dev), i);
3327 gmx_port_id =
3328 CFG_GET_GMXID_NIC_IF(octeon_get_conf(octeon_dev), i);
0cece6c5 3329 ifidx_or_pfnum = i;
f21fb3ed
RV		 3330 if (num_iqueues > num_cpus)
3331 num_iqueues = num_cpus;
3332 if (num_oqueues > num_cpus)
3333 num_oqueues = num_cpus;
3334 dev_dbg(&octeon_dev->pci_dev->dev,
3335 "requesting config for interface %d, iqs %d, oqs %d\n",
0cece6c5 3336 ifidx_or_pfnum, num_iqueues, num_oqueues);
f21fb3ed
RV		 3337 ACCESS_ONCE(ctx->cond) = 0;
3338 ctx->octeon_id = lio_get_device_id(octeon_dev);
3339 init_waitqueue_head(&ctx->wc);
3340
3341 if_cfg.u64 = 0;
3342 if_cfg.s.num_iqueues = num_iqueues;
3343 if_cfg.s.num_oqueues = num_oqueues;
3344 if_cfg.s.base_queue = base_queue;
3345 if_cfg.s.gmx_port_id = gmx_port_id;
0cece6c5
RV		 3346
3347 sc->iq_no = 0;
3348
f21fb3ed 3349 octeon_prepare_soft_command(octeon_dev, sc, OPCODE_NIC,
0cece6c5 3350 OPCODE_NIC_IF_CFG, 0,
f21fb3ed
RV		 3351 if_cfg.u64, 0);
3352
3353 sc->callback = if_cfg_callback;
3354 sc->callback_arg = sc;
3355 sc->wait_time = 1000;
3356
3357 retval = octeon_send_soft_command(octeon_dev, sc);
ddc173a6 3358 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 3359 dev_err(&octeon_dev->pci_dev->dev,
3360 "iq/oq config failed status: %x\n",
3361 retval);
3362 /* Soft instr is freed by driver in case of failure. */
3363 goto setup_nic_dev_fail;
3364 }
3365
3366 /* Sleep on a wait queue till the cond flag indicates that the
3367 * response arrived or timed-out.
3368 */
3369 sleep_cond(&ctx->wc, &ctx->cond);
3370 retval = resp->status;
3371 if (retval) {
3372 dev_err(&octeon_dev->pci_dev->dev, "iq/oq config failed\n");
3373 goto setup_nic_dev_fail;
3374 }
3375
3376 octeon_swap_8B_data((u64 *)(&resp->cfg_info),
3377 (sizeof(struct liquidio_if_cfg_info)) >> 3);
3378
3379 num_iqueues = hweight64(resp->cfg_info.iqmask);
3380 num_oqueues = hweight64(resp->cfg_info.oqmask);
3381
3382 if (!(num_iqueues) || !(num_oqueues)) {
3383 dev_err(&octeon_dev->pci_dev->dev,
3384 "Got bad iqueues (%016llx) or oqueues (%016llx) from firmware.\n",
3385 resp->cfg_info.iqmask,
3386 resp->cfg_info.oqmask);
3387 goto setup_nic_dev_fail;
3388 }
3389 dev_dbg(&octeon_dev->pci_dev->dev,
3390 "interface %d, iqmask %016llx, oqmask %016llx, numiqueues %d, numoqueues %d\n",
3391 i, resp->cfg_info.iqmask, resp->cfg_info.oqmask,
3392 num_iqueues, num_oqueues);
3393 netdev = alloc_etherdev_mq(LIO_SIZE, num_iqueues);
3394
3395 if (!netdev) {
3396 dev_err(&octeon_dev->pci_dev->dev, "Device allocation failed\n");
3397 goto setup_nic_dev_fail;
3398 }
3399
0cece6c5 3400 SET_NETDEV_DEV(netdev, &octeon_dev->pci_dev->dev);
f21fb3ed
RV		 3401
3402 if (num_iqueues > 1)
3403 lionetdevops.ndo_select_queue = select_q;
3404
3405 /* Associate the routines that will handle different
3406 * netdev tasks.
3407 */
3408 netdev->netdev_ops = &lionetdevops;
3409
3410 lio = GET_LIO(netdev);
3411
3412 memset(lio, 0, sizeof(struct lio));
3413
0cece6c5
RV		 3414 lio->ifidx = ifidx_or_pfnum;
3415
3416 props = &octeon_dev->props[i];
3417 props->gmxport = resp->cfg_info.linfo.gmxport;
3418 props->netdev = netdev;
f21fb3ed
RV		 3419
3420 lio->linfo.num_rxpciq = num_oqueues;
3421 lio->linfo.num_txpciq = num_iqueues;
f21fb3ed 3422 for (j = 0; j < num_oqueues; j++) {
26236fa9
RV		 3423 lio->linfo.rxpciq[j].u64 =
3424 resp->cfg_info.linfo.rxpciq[j].u64;
f21fb3ed 3425 }
f21fb3ed 3426 for (j = 0; j < num_iqueues; j++) {
26236fa9
RV		 3427 lio->linfo.txpciq[j].u64 =
3428 resp->cfg_info.linfo.txpciq[j].u64;
f21fb3ed
RV		 3429 }
3430 lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr;
3431 lio->linfo.gmxport = resp->cfg_info.linfo.gmxport;
3432 lio->linfo.link.u64 = resp->cfg_info.linfo.link.u64;
3433
3434 lio->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3435
3436 lio->dev_capability = NETIF_F_HIGHDMA
0cece6c5
RV		 3437 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3438 | NETIF_F_SG | NETIF_F_RXCSUM
3439 | NETIF_F_GRO
3440 | NETIF_F_TSO | NETIF_F_TSO6
3441 | NETIF_F_LRO;
f21fb3ed
RV		 3442 netif_set_gso_max_size(netdev, OCTNIC_GSO_MAX_SIZE);
3443
f21fb3ed 3444 netdev->vlan_features = lio->dev_capability;
0da0b77c 3445 /* Add any unchangeable hw features */
63245f25
RV		 3446 lio->dev_capability |= NETIF_F_HW_VLAN_CTAG_FILTER |
3447 NETIF_F_HW_VLAN_CTAG_RX |
0da0b77c
RV		 3448 NETIF_F_HW_VLAN_CTAG_TX;
3449
3450 netdev->features = (lio->dev_capability & ~NETIF_F_LRO);
f21fb3ed
RV		 3451
3452 netdev->hw_features = lio->dev_capability;
0da0b77c
RV		 3453 /*HW_VLAN_RX and HW_VLAN_FILTER is always on*/
3454 netdev->hw_features = netdev->hw_features &
3455 ~NETIF_F_HW_VLAN_CTAG_RX;
f21fb3ed
RV		 3456
3457 /* Point to the properties for octeon device to which this
3458 * interface belongs.
3459 */
3460 lio->oct_dev = octeon_dev;
3461 lio->octprops = props;
3462 lio->netdev = netdev;
f21fb3ed
RV		 3463
3464 dev_dbg(&octeon_dev->pci_dev->dev,
3465 "if%d gmx: %d hw_addr: 0x%llx\n", i,
3466 lio->linfo.gmxport, CVM_CAST64(lio->linfo.hw_addr));
3467
3468 /* 64-bit swap required on LE machines */
3469 octeon_swap_8B_data(&lio->linfo.hw_addr, 1);
3470 for (j = 0; j < 6; j++)
3471 mac[j] = *((u8 *)(((u8 *)&lio->linfo.hw_addr) + 2 + j));
3472
3473 /* Copy MAC Address to OS network device structure */
3474
3475 ether_addr_copy(netdev->dev_addr, mac);
3476
26236fa9
RV		 3477 /* By default all interfaces on a single Octeon uses the same
3478 * tx and rx queues
3479 */
3480 lio->txq = lio->linfo.txpciq[0].s.q_no;
3481 lio->rxq = lio->linfo.rxpciq[0].s.q_no;
0cece6c5 3482 if (setup_io_queues(octeon_dev, i)) {
f21fb3ed
RV		 3483 dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n");
3484 goto setup_nic_dev_fail;
3485 }
3486
3487 ifstate_set(lio, LIO_IFSTATE_DROQ_OPS);
3488
f21fb3ed
RV		 3489 lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq);
3490 lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq);
3491
fcd2b5e3 3492 if (setup_glists(octeon_dev, lio, num_iqueues)) {
f21fb3ed
RV		 3493 dev_err(&octeon_dev->pci_dev->dev,
3494 "Gather list allocation failed\n");
3495 goto setup_nic_dev_fail;
3496 }
3497
3498 /* Register ethtool support */
3499 liquidio_set_ethtool_ops(netdev);
3500
0cece6c5
RV		 3501 if (netdev->features & NETIF_F_LRO)
3502 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
3503 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed 3504
63245f25
RV		 3505 liquidio_set_feature(netdev, OCTNET_CMD_ENABLE_VLAN_FILTER, 0);
3506
f21fb3ed 3507 if ((debug != -1) && (debug & NETIF_MSG_HW))
63245f25
RV		 3508 liquidio_set_feature(netdev,
3509 OCTNET_CMD_VERBOSE_ENABLE, 0);
f21fb3ed
RV		 3510
3511 /* Register the network device with the OS */
3512 if (register_netdev(netdev)) {
3513 dev_err(&octeon_dev->pci_dev->dev, "Device registration failed\n");
3514 goto setup_nic_dev_fail;
3515 }
3516
3517 dev_dbg(&octeon_dev->pci_dev->dev,
3518 "Setup NIC ifidx:%d mac:%02x%02x%02x%02x%02x%02x\n",
3519 i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
3520 netif_carrier_off(netdev);
0cece6c5 3521 lio->link_changes++;
f21fb3ed
RV		 3522
3523 ifstate_set(lio, LIO_IFSTATE_REGISTERED);
3524
3525 dev_dbg(&octeon_dev->pci_dev->dev,
3526 "NIC ifidx:%d Setup successful\n", i);
3527
3528 octeon_free_soft_command(octeon_dev, sc);
3529 }
3530
3531 return 0;
3532
3533setup_nic_dev_fail:
3534
3535 octeon_free_soft_command(octeon_dev, sc);
3536
3537 while (i--) {
3538 dev_err(&octeon_dev->pci_dev->dev,
3539 "NIC ifidx:%d Setup failed\n", i);
3540 liquidio_destroy_nic_device(octeon_dev, i);
3541 }
3542 return -ENODEV;
3543}
3544
3545/**
3546 * \brief initialize the NIC
3547 * @param oct octeon device
3548 *
3549 * This initialization routine is called once the Octeon device application is
3550 * up and running
3551 */
3552static int liquidio_init_nic_module(struct octeon_device *oct)
3553{
3554 struct oct_intrmod_cfg *intrmod_cfg;
0cece6c5 3555 int i, retval = 0;
f21fb3ed
RV		 3556 int num_nic_ports = CFG_GET_NUM_NIC_PORTS(octeon_get_conf(oct));
3557
3558 dev_dbg(&oct->pci_dev->dev, "Initializing network interfaces\n");
3559
3560 /* only default iq and oq were initialized
3561 * initialize the rest as well
3562 */
3563 /* run port_config command for each port */
3564 oct->ifcount = num_nic_ports;
3565
3566 memset(oct->props, 0,
3567 sizeof(struct octdev_props) * num_nic_ports);
3568
0cece6c5
RV		 3569 for (i = 0; i < MAX_OCTEON_LINKS; i++)
3570 oct->props[i].gmxport = -1;
3571
f21fb3ed
RV		 3572 retval = setup_nic_devices(oct);
3573 if (retval) {
3574 dev_err(&oct->pci_dev->dev, "Setup NIC devices failed\n");
3575 goto octnet_init_failure;
3576 }
3577
3578 liquidio_ptp_init(oct);
3579
3580 /* Initialize interrupt moderation params */
3581 intrmod_cfg = &((struct octeon_device *)oct)->intrmod;
78e6a9b4
RV		 3582 intrmod_cfg->rx_enable = 1;
3583 intrmod_cfg->check_intrvl = LIO_INTRMOD_CHECK_INTERVAL;
3584 intrmod_cfg->maxpkt_ratethr = LIO_INTRMOD_MAXPKT_RATETHR;
3585 intrmod_cfg->minpkt_ratethr = LIO_INTRMOD_MINPKT_RATETHR;
3586 intrmod_cfg->rx_maxcnt_trigger = LIO_INTRMOD_RXMAXCNT_TRIGGER;
3587 intrmod_cfg->rx_maxtmr_trigger = LIO_INTRMOD_RXMAXTMR_TRIGGER;
3588 intrmod_cfg->rx_mintmr_trigger = LIO_INTRMOD_RXMINTMR_TRIGGER;
3589 intrmod_cfg->rx_mincnt_trigger = LIO_INTRMOD_RXMINCNT_TRIGGER;
3590 intrmod_cfg->tx_enable = 1;
3591 intrmod_cfg->tx_maxcnt_trigger = LIO_INTRMOD_TXMAXCNT_TRIGGER;
3592 intrmod_cfg->tx_mincnt_trigger = LIO_INTRMOD_TXMINCNT_TRIGGER;
3593 intrmod_cfg->rx_frames = CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct));
3594 intrmod_cfg->rx_usecs = CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct));
f21fb3ed
RV		 3595 dev_dbg(&oct->pci_dev->dev, "Network interfaces ready\n");
3596
3597 return retval;
3598
3599octnet_init_failure:
3600
3601 oct->ifcount = 0;
3602
3603 return retval;
3604}
3605
3606/**
3607 * \brief starter callback that invokes the remaining initialization work after
3608 * the NIC is up and running.
3609 * @param octptr work struct work_struct
3610 */
3611static void nic_starter(struct work_struct *work)
3612{
3613 struct octeon_device *oct;
3614 struct cavium_wk *wk = (struct cavium_wk *)work;
3615
3616 oct = (struct octeon_device *)wk->ctxptr;
3617
3618 if (atomic_read(&oct->status) == OCT_DEV_RUNNING)
3619 return;
3620
3621 /* If the status of the device is CORE_OK, the core
3622 * application has reported its application type. Call
3623 * any registered handlers now and move to the RUNNING
3624 * state.
3625 */
3626 if (atomic_read(&oct->status) != OCT_DEV_CORE_OK) {
3627 schedule_delayed_work(&oct->nic_poll_work.work,
3628 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
3629 return;
3630 }
3631
3632 atomic_set(&oct->status, OCT_DEV_RUNNING);
3633
3634 if (oct->app_mode && oct->app_mode == CVM_DRV_NIC_APP) {
3635 dev_dbg(&oct->pci_dev->dev, "Starting NIC module\n");
3636
3637 if (liquidio_init_nic_module(oct))
3638 dev_err(&oct->pci_dev->dev, "NIC initialization failed\n");
3639 else
3640 handshake[oct->octeon_id].started_ok = 1;
3641 } else {
3642 dev_err(&oct->pci_dev->dev,
3643 "Unexpected application running on NIC (%d). Check firmware.\n",
3644 oct->app_mode);
3645 }
3646
3647 complete(&handshake[oct->octeon_id].started);
3648}
3649
3650/**
3651 * \brief Device initialization for each Octeon device that is probed
3652 * @param octeon_dev octeon device
3653 */
3654static int octeon_device_init(struct octeon_device *octeon_dev)
3655{
3656 int j, ret;
d3d7e6c6 3657 char bootcmd[] = "\n";
f21fb3ed
RV		 3658 struct octeon_device_priv *oct_priv =
3659 (struct octeon_device_priv *)octeon_dev->priv;
3660 atomic_set(&octeon_dev->status, OCT_DEV_BEGIN_STATE);
3661
3662 /* Enable access to the octeon device and make its DMA capability
3663 * known to the OS.
3664 */
3665 if (octeon_pci_os_setup(octeon_dev))
3666 return 1;
3667
3668 /* Identify the Octeon type and map the BAR address space. */
3669 if (octeon_chip_specific_setup(octeon_dev)) {
3670 dev_err(&octeon_dev->pci_dev->dev, "Chip specific setup failed\n");
3671 return 1;
3672 }
3673
3674 atomic_set(&octeon_dev->status, OCT_DEV_PCI_MAP_DONE);
3675
3676 octeon_dev->app_mode = CVM_DRV_INVALID_APP;
3677
3678 /* Do a soft reset of the Octeon device. */
3679 if (octeon_dev->fn_list.soft_reset(octeon_dev))
3680 return 1;
3681
3682 /* Initialize the dispatch mechanism used to push packets arriving on
3683 * Octeon Output queues.
3684 */
3685 if (octeon_init_dispatch_list(octeon_dev))
3686 return 1;
3687
3688 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3689 OPCODE_NIC_CORE_DRV_ACTIVE,
3690 octeon_core_drv_init,
3691 octeon_dev);
3692
3693 INIT_DELAYED_WORK(&octeon_dev->nic_poll_work.work, nic_starter);
3694 octeon_dev->nic_poll_work.ctxptr = (void *)octeon_dev;
3695 schedule_delayed_work(&octeon_dev->nic_poll_work.work,
3696 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
3697
3698 atomic_set(&octeon_dev->status, OCT_DEV_DISPATCH_INIT_DONE);
3699
3700 octeon_set_io_queues_off(octeon_dev);
3701
3702 /* Setup the data structures that manage this Octeon's Input queues. */
3703 if (octeon_setup_instr_queues(octeon_dev)) {
3704 dev_err(&octeon_dev->pci_dev->dev,
3705 "instruction queue initialization failed\n");
3706 /* On error, release any previously allocated queues */
3707 for (j = 0; j < octeon_dev->num_iqs; j++)
3708 octeon_delete_instr_queue(octeon_dev, j);
3709 return 1;
3710 }
3711 atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE);
3712
3713 /* Initialize soft command buffer pool
3714 */
3715 if (octeon_setup_sc_buffer_pool(octeon_dev)) {
3716 dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n");
3717 return 1;
3718 }
3719 atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
3720
3721 /* Initialize lists to manage the requests of different types that
3722 * arrive from user & kernel applications for this octeon device.
3723 */
3724 if (octeon_setup_response_list(octeon_dev)) {
3725 dev_err(&octeon_dev->pci_dev->dev, "Response list allocation failed\n");
3726 return 1;
3727 }
3728 atomic_set(&octeon_dev->status, OCT_DEV_RESP_LIST_INIT_DONE);
3729
3730 if (octeon_setup_output_queues(octeon_dev)) {
3731 dev_err(&octeon_dev->pci_dev->dev, "Output queue initialization failed\n");
3732 /* Release any previously allocated queues */
3733 for (j = 0; j < octeon_dev->num_oqs; j++)
3734 octeon_delete_droq(octeon_dev, j);
3735 }
3736
3737 atomic_set(&octeon_dev->status, OCT_DEV_DROQ_INIT_DONE);
3738
3739 /* The input and output queue registers were setup earlier (the queues
3740 * were not enabled). Any additional registers that need to be
3741 * programmed should be done now.
3742 */
3743 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
3744 if (ret) {
3745 dev_err(&octeon_dev->pci_dev->dev,
3746 "Failed to configure device registers\n");
3747 return ret;
3748 }
3749
3750 /* Initialize the tasklet that handles output queue packet processing.*/
3751 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing droq tasklet\n");
3752 tasklet_init(&oct_priv->droq_tasklet, octeon_droq_bh,
3753 (unsigned long)octeon_dev);
3754
3755 /* Setup the interrupt handler and record the INT SUM register address
3756 */
3757 octeon_setup_interrupt(octeon_dev);
3758
3759 /* Enable Octeon device interrupts */
3760 octeon_dev->fn_list.enable_interrupt(octeon_dev->chip);
3761
3762 /* Enable the input and output queues for this Octeon device */
3763 octeon_dev->fn_list.enable_io_queues(octeon_dev);
3764
3765 atomic_set(&octeon_dev->status, OCT_DEV_IO_QUEUES_DONE);
3766
3767 dev_dbg(&octeon_dev->pci_dev->dev, "Waiting for DDR initialization...\n");
3768
3769 if (ddr_timeout == 0) {
3770 dev_info(&octeon_dev->pci_dev->dev,
3771 "WAITING. Set ddr_timeout to non-zero value to proceed with initialization.\n");
3772 }
3773
3774 schedule_timeout_uninterruptible(HZ * LIO_RESET_SECS);
3775
3776 /* Wait for the octeon to initialize DDR after the soft-reset. */
3777 ret = octeon_wait_for_ddr_init(octeon_dev, &ddr_timeout);
3778 if (ret) {
3779 dev_err(&octeon_dev->pci_dev->dev,
3780 "DDR not initialized. Please confirm that board is configured to boot from Flash, ret: %d\n",
3781 ret);
3782 return 1;
3783 }
3784
3785 if (octeon_wait_for_bootloader(octeon_dev, 1000) != 0) {
3786 dev_err(&octeon_dev->pci_dev->dev, "Board not responding\n");
3787 return 1;
3788 }
3789
d3d7e6c6
RV		 3790 /* Divert uboot to take commands from host instead. */
3791 ret = octeon_console_send_cmd(octeon_dev, bootcmd, 50);
3792
f21fb3ed
RV		 3793 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing consoles\n");
3794 ret = octeon_init_consoles(octeon_dev);
3795 if (ret) {
3796 dev_err(&octeon_dev->pci_dev->dev, "Could not access board consoles\n");
3797 return 1;
3798 }
3799 ret = octeon_add_console(octeon_dev, 0);
3800 if (ret) {
3801 dev_err(&octeon_dev->pci_dev->dev, "Could not access board console\n");
3802 return 1;
3803 }
3804
3805 atomic_set(&octeon_dev->status, OCT_DEV_CONSOLE_INIT_DONE);
3806
3807 dev_dbg(&octeon_dev->pci_dev->dev, "Loading firmware\n");
3808 ret = load_firmware(octeon_dev);
3809 if (ret) {
3810 dev_err(&octeon_dev->pci_dev->dev, "Could not load firmware to board\n");
3811 return 1;
3812 }
3813
3814 handshake[octeon_dev->octeon_id].init_ok = 1;
3815 complete(&handshake[octeon_dev->octeon_id].init);
3816
3817 atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK);
3818
3819 /* Send Credit for Octeon Output queues. Credits are always sent after
3820 * the output queue is enabled.
3821 */
3822 for (j = 0; j < octeon_dev->num_oqs; j++)
3823 writel(octeon_dev->droq[j]->max_count,
3824 octeon_dev->droq[j]->pkts_credit_reg);
3825
3826 /* Packets can start arriving on the output queues from this point. */
3827
3828 return 0;
3829}
3830
3831/**
3832 * \brief Exits the module
3833 */
3834static void __exit liquidio_exit(void)
3835{
3836 liquidio_deinit_pci();
3837
3838 pr_info("LiquidIO network module is now unloaded\n");
3839}
3840
3841module_init(liquidio_init);
3842module_exit(liquidio_exit);
ubuntu-bionic-kernel mirror