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liquidio:RX queue alloc changes
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f21fb3ed
RV		 1/**********************************************************************
2* Author: Cavium, Inc.
3*
4* Contact: support@cavium.com
5* Please include "LiquidIO" in the subject.
6*
7* Copyright (c) 2003-2015 Cavium, Inc.
8*
9* This file is free software; you can redistribute it and/or modify
10* it under the terms of the GNU General Public License, Version 2, as
11* published by the Free Software Foundation.
12*
13* This file is distributed in the hope that it will be useful, but
14* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16* NONINFRINGEMENT. See the GNU General Public License for more
17* details.
18*
19* This file may also be available under a different license from Cavium.
20* Contact Cavium, Inc. for more information
21**********************************************************************/
22#include <linux/version.h>
23#include <linux/module.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/pci.h>
27#include <linux/pci_ids.h>
28#include <linux/ip.h>
5b173cf9 29#include <net/ip.h>
f21fb3ed
RV		 30#include <linux/ipv6.h>
31#include <linux/net_tstamp.h>
32#include <linux/if_vlan.h>
33#include <linux/firmware.h>
34#include <linux/ethtool.h>
35#include <linux/ptp_clock_kernel.h>
36#include <linux/types.h>
37#include <linux/list.h>
38#include <linux/workqueue.h>
39#include <linux/interrupt.h>
40#include "octeon_config.h"
41#include "liquidio_common.h"
42#include "octeon_droq.h"
43#include "octeon_iq.h"
44#include "response_manager.h"
45#include "octeon_device.h"
46#include "octeon_nic.h"
47#include "octeon_main.h"
48#include "octeon_network.h"
49#include "cn66xx_regs.h"
50#include "cn66xx_device.h"
51#include "cn68xx_regs.h"
52#include "cn68xx_device.h"
53#include "liquidio_image.h"
54
55MODULE_AUTHOR("Cavium Networks, <support@cavium.com>");
56MODULE_DESCRIPTION("Cavium LiquidIO Intelligent Server Adapter Driver");
57MODULE_LICENSE("GPL");
58MODULE_VERSION(LIQUIDIO_VERSION);
59MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210SV_NAME LIO_FW_NAME_SUFFIX);
60MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210NV_NAME LIO_FW_NAME_SUFFIX);
61MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_410NV_NAME LIO_FW_NAME_SUFFIX);
62
63static int ddr_timeout = 10000;
64module_param(ddr_timeout, int, 0644);
65MODULE_PARM_DESC(ddr_timeout,
66 "Number of milliseconds to wait for DDR initialization. 0 waits for ddr_timeout to be set to non-zero value before starting to check");
67
68static u32 console_bitmask;
69module_param(console_bitmask, int, 0644);
70MODULE_PARM_DESC(console_bitmask,
71 "Bitmask indicating which consoles have debug output redirected to syslog.");
72
73#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
74
75static int debug = -1;
76module_param(debug, int, 0644);
77MODULE_PARM_DESC(debug, "NETIF_MSG debug bits");
78
79static char fw_type[LIO_MAX_FW_TYPE_LEN];
80module_param_string(fw_type, fw_type, sizeof(fw_type), 0000);
81MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded. Default \"nic\"");
82
83static int conf_type;
84module_param(conf_type, int, 0);
85MODULE_PARM_DESC(conf_type, "select octeon configuration 0 default 1 ovs");
86
87/* Bit mask values for lio->ifstate */
88#define LIO_IFSTATE_DROQ_OPS 0x01
89#define LIO_IFSTATE_REGISTERED 0x02
90#define LIO_IFSTATE_RUNNING 0x04
91#define LIO_IFSTATE_RX_TIMESTAMP_ENABLED 0x08
92
93/* Polling interval for determining when NIC application is alive */
94#define LIQUIDIO_STARTER_POLL_INTERVAL_MS 100
95
96/* runtime link query interval */
97#define LIQUIDIO_LINK_QUERY_INTERVAL_MS 1000
98
99struct liquidio_if_cfg_context {
100 int octeon_id;
101
102 wait_queue_head_t wc;
103
104 int cond;
105};
106
107struct liquidio_if_cfg_resp {
108 u64 rh;
109 struct liquidio_if_cfg_info cfg_info;
110 u64 status;
111};
112
113struct oct_link_status_resp {
114 u64 rh;
115 struct oct_link_info link_info;
116 u64 status;
117};
118
119struct oct_timestamp_resp {
120 u64 rh;
121 u64 timestamp;
122 u64 status;
123};
124
125#define OCT_TIMESTAMP_RESP_SIZE (sizeof(struct oct_timestamp_resp))
126
127union tx_info {
128 u64 u64;
129 struct {
130#ifdef __BIG_ENDIAN_BITFIELD
131 u16 gso_size;
132 u16 gso_segs;
133 u32 reserved;
134#else
135 u32 reserved;
136 u16 gso_segs;
137 u16 gso_size;
138#endif
139 } s;
140};
141
142/** Octeon device properties to be used by the NIC module.
143 * Each octeon device in the system will be represented
144 * by this structure in the NIC module.
145 */
146
147#define OCTNIC_MAX_SG (MAX_SKB_FRAGS)
148
149#define OCTNIC_GSO_MAX_HEADER_SIZE 128
150#define OCTNIC_GSO_MAX_SIZE (GSO_MAX_SIZE - OCTNIC_GSO_MAX_HEADER_SIZE)
151
152/** Structure of a node in list of gather components maintained by
153 * NIC driver for each network device.
154 */
155struct octnic_gather {
156 /** List manipulation. Next and prev pointers. */
157 struct list_head list;
158
159 /** Size of the gather component at sg in bytes. */
160 int sg_size;
161
162 /** Number of bytes that sg was adjusted to make it 8B-aligned. */
163 int adjust;
164
165 /** Gather component that can accommodate max sized fragment list
166 * received from the IP layer.
167 */
168 struct octeon_sg_entry *sg;
fcd2b5e3
RV		 169
170 u64 sg_dma_ptr;
f21fb3ed
RV		 171};
172
173/** This structure is used by NIC driver to store information required
174 * to free the sk_buff when the packet has been fetched by Octeon.
175 * Bytes offset below assume worst-case of a 64-bit system.
176 */
177struct octnet_buf_free_info {
178 /** Bytes 1-8. Pointer to network device private structure. */
179 struct lio *lio;
180
181 /** Bytes 9-16. Pointer to sk_buff. */
182 struct sk_buff *skb;
183
184 /** Bytes 17-24. Pointer to gather list. */
185 struct octnic_gather *g;
186
187 /** Bytes 25-32. Physical address of skb->data or gather list. */
188 u64 dptr;
189
190 /** Bytes 33-47. Piggybacked soft command, if any */
191 struct octeon_soft_command *sc;
192};
193
194struct handshake {
195 struct completion init;
196 struct completion started;
197 struct pci_dev *pci_dev;
198 int init_ok;
199 int started_ok;
200};
201
202struct octeon_device_priv {
203 /** Tasklet structures for this device. */
204 struct tasklet_struct droq_tasklet;
205 unsigned long napi_mask;
206};
207
208static int octeon_device_init(struct octeon_device *);
209static void liquidio_remove(struct pci_dev *pdev);
210static int liquidio_probe(struct pci_dev *pdev,
211 const struct pci_device_id *ent);
212
213static struct handshake handshake[MAX_OCTEON_DEVICES];
214static struct completion first_stage;
215
5b173cf9 216static void octeon_droq_bh(unsigned long pdev)
f21fb3ed
RV		 217{
218 int q_no;
219 int reschedule = 0;
220 struct octeon_device *oct = (struct octeon_device *)pdev;
221 struct octeon_device_priv *oct_priv =
222 (struct octeon_device_priv *)oct->priv;
223
224 /* for (q_no = 0; q_no < oct->num_oqs; q_no++) { */
225 for (q_no = 0; q_no < MAX_OCTEON_OUTPUT_QUEUES; q_no++) {
226 if (!(oct->io_qmask.oq & (1UL << q_no)))
227 continue;
228 reschedule |= octeon_droq_process_packets(oct, oct->droq[q_no],
229 MAX_PACKET_BUDGET);
230 }
231
232 if (reschedule)
233 tasklet_schedule(&oct_priv->droq_tasklet);
234}
235
5b173cf9 236static int lio_wait_for_oq_pkts(struct octeon_device *oct)
f21fb3ed
RV		 237{
238 struct octeon_device_priv *oct_priv =
239 (struct octeon_device_priv *)oct->priv;
240 int retry = 100, pkt_cnt = 0, pending_pkts = 0;
241 int i;
242
243 do {
244 pending_pkts = 0;
245
246 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES; i++) {
247 if (!(oct->io_qmask.oq & (1UL << i)))
248 continue;
249 pkt_cnt += octeon_droq_check_hw_for_pkts(oct,
250 oct->droq[i]);
251 }
252 if (pkt_cnt > 0) {
253 pending_pkts += pkt_cnt;
254 tasklet_schedule(&oct_priv->droq_tasklet);
255 }
256 pkt_cnt = 0;
257 schedule_timeout_uninterruptible(1);
258
259 } while (retry-- && pending_pkts);
260
261 return pkt_cnt;
262}
263
264void octeon_report_tx_completion_to_bql(void *txq, unsigned int pkts_compl,
265 unsigned int bytes_compl)
266{
267 struct netdev_queue *netdev_queue = txq;
268
269 netdev_tx_completed_queue(netdev_queue, pkts_compl, bytes_compl);
270}
271
272void octeon_update_tx_completion_counters(void *buf, int reqtype,
273 unsigned int *pkts_compl,
274 unsigned int *bytes_compl)
275{
276 struct octnet_buf_free_info *finfo;
277 struct sk_buff *skb = NULL;
278 struct octeon_soft_command *sc;
279
280 switch (reqtype) {
281 case REQTYPE_NORESP_NET:
282 case REQTYPE_NORESP_NET_SG:
283 finfo = buf;
284 skb = finfo->skb;
285 break;
286
287 case REQTYPE_RESP_NET_SG:
288 case REQTYPE_RESP_NET:
289 sc = buf;
290 skb = sc->callback_arg;
291 break;
292
293 default:
294 return;
295 }
296
297 (*pkts_compl)++;
298 *bytes_compl += skb->len;
299}
300
301void octeon_report_sent_bytes_to_bql(void *buf, int reqtype)
302{
303 struct octnet_buf_free_info *finfo;
304 struct sk_buff *skb;
305 struct octeon_soft_command *sc;
306 struct netdev_queue *txq;
307
308 switch (reqtype) {
309 case REQTYPE_NORESP_NET:
310 case REQTYPE_NORESP_NET_SG:
311 finfo = buf;
312 skb = finfo->skb;
313 break;
314
315 case REQTYPE_RESP_NET_SG:
316 case REQTYPE_RESP_NET:
317 sc = buf;
318 skb = sc->callback_arg;
319 break;
320
321 default:
322 return;
323 }
324
325 txq = netdev_get_tx_queue(skb->dev, skb_get_queue_mapping(skb));
326 netdev_tx_sent_queue(txq, skb->len);
327}
328
329int octeon_console_debug_enabled(u32 console)
330{
331 return (console_bitmask >> (console)) & 0x1;
332}
333
334/**
335 * \brief Forces all IO queues off on a given device
336 * @param oct Pointer to Octeon device
337 */
338static void force_io_queues_off(struct octeon_device *oct)
339{
340 if ((oct->chip_id == OCTEON_CN66XX) ||
341 (oct->chip_id == OCTEON_CN68XX)) {
342 /* Reset the Enable bits for Input Queues. */
343 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
344
345 /* Reset the Enable bits for Output Queues. */
346 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
347 }
348}
349
350/**
351 * \brief wait for all pending requests to complete
352 * @param oct Pointer to Octeon device
353 *
354 * Called during shutdown sequence
355 */
356static int wait_for_pending_requests(struct octeon_device *oct)
357{
358 int i, pcount = 0;
359
360 for (i = 0; i < 100; i++) {
361 pcount =
362 atomic_read(&oct->response_list
363 [OCTEON_ORDERED_SC_LIST].pending_req_count);
364 if (pcount)
365 schedule_timeout_uninterruptible(HZ / 10);
366 else
367 break;
368 }
369
370 if (pcount)
371 return 1;
372
373 return 0;
374}
375
376/**
377 * \brief Cause device to go quiet so it can be safely removed/reset/etc
378 * @param oct Pointer to Octeon device
379 */
380static inline void pcierror_quiesce_device(struct octeon_device *oct)
381{
382 int i;
383
384 /* Disable the input and output queues now. No more packets will
385 * arrive from Octeon, but we should wait for all packet processing
386 * to finish.
387 */
388 force_io_queues_off(oct);
389
390 /* To allow for in-flight requests */
391 schedule_timeout_uninterruptible(100);
392
393 if (wait_for_pending_requests(oct))
394 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
395
396 /* Force all requests waiting to be fetched by OCTEON to complete. */
397 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES; i++) {
398 struct octeon_instr_queue *iq;
399
400 if (!(oct->io_qmask.iq & (1UL << i)))
401 continue;
402 iq = oct->instr_queue[i];
403
404 if (atomic_read(&iq->instr_pending)) {
405 spin_lock_bh(&iq->lock);
406 iq->fill_cnt = 0;
407 iq->octeon_read_index = iq->host_write_index;
408 iq->stats.instr_processed +=
409 atomic_read(&iq->instr_pending);
410 lio_process_iq_request_list(oct, iq);
411 spin_unlock_bh(&iq->lock);
412 }
413 }
414
415 /* Force all pending ordered list requests to time out. */
416 lio_process_ordered_list(oct, 1);
417
418 /* We do not need to wait for output queue packets to be processed. */
419}
420
421/**
422 * \brief Cleanup PCI AER uncorrectable error status
423 * @param dev Pointer to PCI device
424 */
425static void cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
426{
427 int pos = 0x100;
428 u32 status, mask;
429
430 pr_info("%s :\n", __func__);
431
432 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
433 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
434 if (dev->error_state == pci_channel_io_normal)
435 status &= ~mask; /* Clear corresponding nonfatal bits */
436 else
437 status &= mask; /* Clear corresponding fatal bits */
438 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
439}
440
441/**
442 * \brief Stop all PCI IO to a given device
443 * @param dev Pointer to Octeon device
444 */
445static void stop_pci_io(struct octeon_device *oct)
446{
447 /* No more instructions will be forwarded. */
448 atomic_set(&oct->status, OCT_DEV_IN_RESET);
449
450 pci_disable_device(oct->pci_dev);
451
452 /* Disable interrupts */
453 oct->fn_list.disable_interrupt(oct->chip);
454
455 pcierror_quiesce_device(oct);
456
457 /* Release the interrupt line */
458 free_irq(oct->pci_dev->irq, oct);
459
460 if (oct->flags & LIO_FLAG_MSI_ENABLED)
461 pci_disable_msi(oct->pci_dev);
462
463 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
464 lio_get_state_string(&oct->status));
465
466 /* cn63xx_cleanup_aer_uncorrect_error_status(oct->pci_dev); */
467 /* making it a common function for all OCTEON models */
468 cleanup_aer_uncorrect_error_status(oct->pci_dev);
469}
470
471/**
472 * \brief called when PCI error is detected
473 * @param pdev Pointer to PCI device
474 * @param state The current pci connection state
475 *
476 * This function is called after a PCI bus error affecting
477 * this device has been detected.
478 */
479static pci_ers_result_t liquidio_pcie_error_detected(struct pci_dev *pdev,
480 pci_channel_state_t state)
481{
482 struct octeon_device *oct = pci_get_drvdata(pdev);
483
484 /* Non-correctable Non-fatal errors */
485 if (state == pci_channel_io_normal) {
486 dev_err(&oct->pci_dev->dev, "Non-correctable non-fatal error reported:\n");
487 cleanup_aer_uncorrect_error_status(oct->pci_dev);
488 return PCI_ERS_RESULT_CAN_RECOVER;
489 }
490
491 /* Non-correctable Fatal errors */
492 dev_err(&oct->pci_dev->dev, "Non-correctable FATAL reported by PCI AER driver\n");
493 stop_pci_io(oct);
494
495 /* Always return a DISCONNECT. There is no support for recovery but only
496 * for a clean shutdown.
497 */
498 return PCI_ERS_RESULT_DISCONNECT;
499}
500
501/**
502 * \brief mmio handler
503 * @param pdev Pointer to PCI device
504 */
505static pci_ers_result_t liquidio_pcie_mmio_enabled(struct pci_dev *pdev)
506{
507 /* We should never hit this since we never ask for a reset for a Fatal
508 * Error. We always return DISCONNECT in io_error above.
509 * But play safe and return RECOVERED for now.
510 */
511 return PCI_ERS_RESULT_RECOVERED;
512}
513
514/**
515 * \brief called after the pci bus has been reset.
516 * @param pdev Pointer to PCI device
517 *
518 * Restart the card from scratch, as if from a cold-boot. Implementation
519 * resembles the first-half of the octeon_resume routine.
520 */
521static pci_ers_result_t liquidio_pcie_slot_reset(struct pci_dev *pdev)
522{
523 /* We should never hit this since we never ask for a reset for a Fatal
524 * Error. We always return DISCONNECT in io_error above.
525 * But play safe and return RECOVERED for now.
526 */
527 return PCI_ERS_RESULT_RECOVERED;
528}
529
530/**
531 * \brief called when traffic can start flowing again.
532 * @param pdev Pointer to PCI device
533 *
534 * This callback is called when the error recovery driver tells us that
535 * its OK to resume normal operation. Implementation resembles the
536 * second-half of the octeon_resume routine.
537 */
538static void liquidio_pcie_resume(struct pci_dev *pdev)
539{
540 /* Nothing to be done here. */
541}
542
543#ifdef CONFIG_PM
544/**
545 * \brief called when suspending
546 * @param pdev Pointer to PCI device
547 * @param state state to suspend to
548 */
549static int liquidio_suspend(struct pci_dev *pdev, pm_message_t state)
550{
551 return 0;
552}
553
554/**
555 * \brief called when resuming
556 * @param pdev Pointer to PCI device
557 */
558static int liquidio_resume(struct pci_dev *pdev)
559{
560 return 0;
561}
562#endif
563
564/* For PCI-E Advanced Error Recovery (AER) Interface */
166e2362 565static const struct pci_error_handlers liquidio_err_handler = {
f21fb3ed
RV		 566 .error_detected = liquidio_pcie_error_detected,
567 .mmio_enabled = liquidio_pcie_mmio_enabled,
568 .slot_reset = liquidio_pcie_slot_reset,
569 .resume = liquidio_pcie_resume,
570};
571
572static const struct pci_device_id liquidio_pci_tbl[] = {
573 { /* 68xx */
574 PCI_VENDOR_ID_CAVIUM, 0x91, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
575 },
576 { /* 66xx */
577 PCI_VENDOR_ID_CAVIUM, 0x92, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
578 },
579 {
580 0, 0, 0, 0, 0, 0, 0
581 }
582};
583MODULE_DEVICE_TABLE(pci, liquidio_pci_tbl);
584
585static struct pci_driver liquidio_pci_driver = {
586 .name = "LiquidIO",
587 .id_table = liquidio_pci_tbl,
588 .probe = liquidio_probe,
589 .remove = liquidio_remove,
590 .err_handler = &liquidio_err_handler, /* For AER */
591
592#ifdef CONFIG_PM
593 .suspend = liquidio_suspend,
594 .resume = liquidio_resume,
595#endif
596
597};
598
599/**
600 * \brief register PCI driver
601 */
602static int liquidio_init_pci(void)
603{
604 return pci_register_driver(&liquidio_pci_driver);
605}
606
607/**
608 * \brief unregister PCI driver
609 */
610static void liquidio_deinit_pci(void)
611{
612 pci_unregister_driver(&liquidio_pci_driver);
613}
614
615/**
616 * \brief check interface state
617 * @param lio per-network private data
618 * @param state_flag flag state to check
619 */
620static inline int ifstate_check(struct lio *lio, int state_flag)
621{
622 return atomic_read(&lio->ifstate) & state_flag;
623}
624
625/**
626 * \brief set interface state
627 * @param lio per-network private data
628 * @param state_flag flag state to set
629 */
630static inline void ifstate_set(struct lio *lio, int state_flag)
631{
632 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) | state_flag));
633}
634
635/**
636 * \brief clear interface state
637 * @param lio per-network private data
638 * @param state_flag flag state to clear
639 */
640static inline void ifstate_reset(struct lio *lio, int state_flag)
641{
642 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) & ~(state_flag)));
643}
644
645/**
646 * \brief Stop Tx queues
647 * @param netdev network device
648 */
649static inline void txqs_stop(struct net_device *netdev)
650{
651 if (netif_is_multiqueue(netdev)) {
652 int i;
653
654 for (i = 0; i < netdev->num_tx_queues; i++)
655 netif_stop_subqueue(netdev, i);
656 } else {
657 netif_stop_queue(netdev);
658 }
659}
660
661/**
662 * \brief Start Tx queues
663 * @param netdev network device
664 */
665static inline void txqs_start(struct net_device *netdev)
666{
667 if (netif_is_multiqueue(netdev)) {
668 int i;
669
670 for (i = 0; i < netdev->num_tx_queues; i++)
671 netif_start_subqueue(netdev, i);
672 } else {
673 netif_start_queue(netdev);
674 }
675}
676
677/**
678 * \brief Wake Tx queues
679 * @param netdev network device
680 */
681static inline void txqs_wake(struct net_device *netdev)
682{
683 if (netif_is_multiqueue(netdev)) {
684 int i;
685
686 for (i = 0; i < netdev->num_tx_queues; i++)
26236fa9
RV		 687 if (__netif_subqueue_stopped(netdev, i))
688 netif_wake_subqueue(netdev, i);
f21fb3ed
RV		 689 } else {
690 netif_wake_queue(netdev);
691 }
692}
693
694/**
695 * \brief Stop Tx queue
696 * @param netdev network device
697 */
698static void stop_txq(struct net_device *netdev)
699{
700 txqs_stop(netdev);
701}
702
703/**
704 * \brief Start Tx queue
705 * @param netdev network device
706 */
707static void start_txq(struct net_device *netdev)
708{
709 struct lio *lio = GET_LIO(netdev);
710
711 if (lio->linfo.link.s.status) {
712 txqs_start(netdev);
713 return;
714 }
715}
716
717/**
718 * \brief Wake a queue
719 * @param netdev network device
720 * @param q which queue to wake
721 */
722static inline void wake_q(struct net_device *netdev, int q)
723{
724 if (netif_is_multiqueue(netdev))
725 netif_wake_subqueue(netdev, q);
726 else
727 netif_wake_queue(netdev);
728}
729
730/**
731 * \brief Stop a queue
732 * @param netdev network device
733 * @param q which queue to stop
734 */
735static inline void stop_q(struct net_device *netdev, int q)
736{
737 if (netif_is_multiqueue(netdev))
738 netif_stop_subqueue(netdev, q);
739 else
740 netif_stop_queue(netdev);
741}
742
743/**
744 * \brief Check Tx queue status, and take appropriate action
745 * @param lio per-network private data
746 * @returns 0 if full, number of queues woken up otherwise
747 */
748static inline int check_txq_status(struct lio *lio)
749{
750 int ret_val = 0;
751
752 if (netif_is_multiqueue(lio->netdev)) {
753 int numqs = lio->netdev->num_tx_queues;
754 int q, iq = 0;
755
756 /* check each sub-queue state */
757 for (q = 0; q < numqs; q++) {
26236fa9
RV		 758 iq = lio->linfo.txpciq[q %
759 (lio->linfo.num_txpciq)].s.q_no;
f21fb3ed
RV		 760 if (octnet_iq_is_full(lio->oct_dev, iq))
761 continue;
26236fa9
RV		 762 if (__netif_subqueue_stopped(lio->netdev, q)) {
763 wake_q(lio->netdev, q);
764 ret_val++;
765 }
f21fb3ed
RV		 766 }
767 } else {
768 if (octnet_iq_is_full(lio->oct_dev, lio->txq))
769 return 0;
770 wake_q(lio->netdev, lio->txq);
771 ret_val = 1;
772 }
773 return ret_val;
774}
775
776/**
777 * Remove the node at the head of the list. The list would be empty at
778 * the end of this call if there are no more nodes in the list.
779 */
780static inline struct list_head *list_delete_head(struct list_head *root)
781{
782 struct list_head *node;
783
784 if ((root->prev == root) && (root->next == root))
785 node = NULL;
786 else
787 node = root->next;
788
789 if (node)
790 list_del(node);
791
792 return node;
793}
794
795/**
fcd2b5e3 796 * \brief Delete gather lists
f21fb3ed
RV		 797 * @param lio per-network private data
798 */
fcd2b5e3 799static void delete_glists(struct lio *lio)
f21fb3ed
RV		 800{
801 struct octnic_gather *g;
fcd2b5e3 802 int i;
f21fb3ed 803
fcd2b5e3
RV		 804 if (!lio->glist)
805 return;
806
807 for (i = 0; i < lio->linfo.num_txpciq; i++) {
808 do {
809 g = (struct octnic_gather *)
810 list_delete_head(&lio->glist[i]);
811 if (g) {
812 if (g->sg) {
813 dma_unmap_single(&lio->oct_dev->
814 pci_dev->dev,
815 g->sg_dma_ptr,
816 g->sg_size,
817 DMA_TO_DEVICE);
818 kfree((void *)((unsigned long)g->sg -
819 g->adjust));
820 }
821 kfree(g);
822 }
823 } while (g);
824 }
825
826 kfree((void *)lio->glist);
f21fb3ed
RV		 827}
828
829/**
fcd2b5e3 830 * \brief Setup gather lists
f21fb3ed
RV		 831 * @param lio per-network private data
832 */
fcd2b5e3 833static int setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs)
f21fb3ed 834{
fcd2b5e3 835 int i, j;
f21fb3ed
RV		 836 struct octnic_gather *g;
837
fcd2b5e3
RV		 838 lio->glist_lock = kcalloc(num_iqs, sizeof(*lio->glist_lock),
839 GFP_KERNEL);
840 if (!lio->glist_lock)
841 return 1;
f21fb3ed 842
fcd2b5e3
RV		 843 lio->glist = kcalloc(num_iqs, sizeof(*lio->glist),
844 GFP_KERNEL);
845 if (!lio->glist) {
846 kfree((void *)lio->glist_lock);
847 return 1;
848 }
f21fb3ed 849
fcd2b5e3
RV		 850 for (i = 0; i < num_iqs; i++) {
851 int numa_node = cpu_to_node(i % num_online_cpus());
f21fb3ed 852
fcd2b5e3
RV		 853 spin_lock_init(&lio->glist_lock[i]);
854
855 INIT_LIST_HEAD(&lio->glist[i]);
856
857 for (j = 0; j < lio->tx_qsize; j++) {
858 g = kzalloc_node(sizeof(*g), GFP_KERNEL,
859 numa_node);
860 if (!g)
861 g = kzalloc(sizeof(*g), GFP_KERNEL);
862 if (!g)
863 break;
864
865 g->sg_size = ((ROUNDUP4(OCTNIC_MAX_SG) >> 2) *
866 OCT_SG_ENTRY_SIZE);
867
868 g->sg = kmalloc_node(g->sg_size + 8,
869 GFP_KERNEL, numa_node);
870 if (!g->sg)
871 g->sg = kmalloc(g->sg_size + 8, GFP_KERNEL);
872 if (!g->sg) {
873 kfree(g);
874 break;
875 }
876
877 /* The gather component should be aligned on 64-bit
878 * boundary
879 */
880 if (((unsigned long)g->sg) & 7) {
881 g->adjust = 8 - (((unsigned long)g->sg) & 7);
882 g->sg = (struct octeon_sg_entry *)
883 ((unsigned long)g->sg + g->adjust);
884 }
885 g->sg_dma_ptr = dma_map_single(&oct->pci_dev->dev,
886 g->sg, g->sg_size,
887 DMA_TO_DEVICE);
888 if (dma_mapping_error(&oct->pci_dev->dev,
889 g->sg_dma_ptr)) {
890 kfree((void *)((unsigned long)g->sg -
891 g->adjust));
892 kfree(g);
893 break;
894 }
895
896 list_add_tail(&g->list, &lio->glist[i]);
f21fb3ed
RV		 897 }
898
fcd2b5e3
RV		 899 if (j != lio->tx_qsize) {
900 delete_glists(lio);
901 return 1;
f21fb3ed 902 }
f21fb3ed
RV		 903 }
904
fcd2b5e3 905 return 0;
f21fb3ed
RV		 906}
907
908/**
909 * \brief Print link information
910 * @param netdev network device
911 */
912static void print_link_info(struct net_device *netdev)
913{
914 struct lio *lio = GET_LIO(netdev);
915
916 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED) {
917 struct oct_link_info *linfo = &lio->linfo;
918
919 if (linfo->link.s.status) {
920 netif_info(lio, link, lio->netdev, "%d Mbps %s Duplex UP\n",
921 linfo->link.s.speed,
922 (linfo->link.s.duplex) ? "Full" : "Half");
923 } else {
924 netif_info(lio, link, lio->netdev, "Link Down\n");
925 }
926 }
927}
928
929/**
930 * \brief Update link status
931 * @param netdev network device
932 * @param ls link status structure
933 *
934 * Called on receipt of a link status response from the core application to
935 * update each interface's link status.
936 */
937static inline void update_link_status(struct net_device *netdev,
938 union oct_link_status *ls)
939{
940 struct lio *lio = GET_LIO(netdev);
941
942 if ((lio->intf_open) && (lio->linfo.link.u64 != ls->u64)) {
943 lio->linfo.link.u64 = ls->u64;
944
945 print_link_info(netdev);
946
947 if (lio->linfo.link.s.status) {
948 netif_carrier_on(netdev);
949 /* start_txq(netdev); */
950 txqs_wake(netdev);
951 } else {
952 netif_carrier_off(netdev);
953 stop_txq(netdev);
954 }
955 }
956}
957
958/**
959 * \brief Droq packet processor sceduler
960 * @param oct octeon device
961 */
962static
963void liquidio_schedule_droq_pkt_handlers(struct octeon_device *oct)
964{
965 struct octeon_device_priv *oct_priv =
966 (struct octeon_device_priv *)oct->priv;
967 u64 oq_no;
968 struct octeon_droq *droq;
969
970 if (oct->int_status & OCT_DEV_INTR_PKT_DATA) {
971 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES; oq_no++) {
972 if (!(oct->droq_intr & (1 << oq_no)))
973 continue;
974
975 droq = oct->droq[oq_no];
976
977 if (droq->ops.poll_mode) {
978 droq->ops.napi_fn(droq);
979 oct_priv->napi_mask |= (1 << oq_no);
980 } else {
981 tasklet_schedule(&oct_priv->droq_tasklet);
982 }
983 }
984 }
985}
986
987/**
988 * \brief Interrupt handler for octeon
989 * @param irq unused
990 * @param dev octeon device
991 */
992static
993irqreturn_t liquidio_intr_handler(int irq __attribute__((unused)), void *dev)
994{
995 struct octeon_device *oct = (struct octeon_device *)dev;
996 irqreturn_t ret;
997
998 /* Disable our interrupts for the duration of ISR */
999 oct->fn_list.disable_interrupt(oct->chip);
1000
1001 ret = oct->fn_list.process_interrupt_regs(oct);
1002
1003 if (ret == IRQ_HANDLED)
1004 liquidio_schedule_droq_pkt_handlers(oct);
1005
1006 /* Re-enable our interrupts */
1007 if (!(atomic_read(&oct->status) == OCT_DEV_IN_RESET))
1008 oct->fn_list.enable_interrupt(oct->chip);
1009
1010 return ret;
1011}
1012
1013/**
1014 * \brief Setup interrupt for octeon device
1015 * @param oct octeon device
1016 *
1017 * Enable interrupt in Octeon device as given in the PCI interrupt mask.
1018 */
1019static int octeon_setup_interrupt(struct octeon_device *oct)
1020{
1021 int irqret, err;
1022
1023 err = pci_enable_msi(oct->pci_dev);
1024 if (err)
1025 dev_warn(&oct->pci_dev->dev, "Reverting to legacy interrupts. Error: %d\n",
1026 err);
1027 else
1028 oct->flags |= LIO_FLAG_MSI_ENABLED;
1029
1030 irqret = request_irq(oct->pci_dev->irq, liquidio_intr_handler,
1031 IRQF_SHARED, "octeon", oct);
1032 if (irqret) {
1033 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1034 pci_disable_msi(oct->pci_dev);
1035 dev_err(&oct->pci_dev->dev, "Request IRQ failed with code: %d\n",
1036 irqret);
1037 return 1;
1038 }
1039
1040 return 0;
1041}
1042
1043/**
1044 * \brief PCI probe handler
1045 * @param pdev PCI device structure
1046 * @param ent unused
1047 */
1048static int liquidio_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1049{
1050 struct octeon_device *oct_dev = NULL;
1051 struct handshake *hs;
1052
1053 oct_dev = octeon_allocate_device(pdev->device,
1054 sizeof(struct octeon_device_priv));
1055 if (!oct_dev) {
1056 dev_err(&pdev->dev, "Unable to allocate device\n");
1057 return -ENOMEM;
1058 }
1059
1060 dev_info(&pdev->dev, "Initializing device %x:%x.\n",
1061 (u32)pdev->vendor, (u32)pdev->device);
1062
1063 /* Assign octeon_device for this device to the private data area. */
1064 pci_set_drvdata(pdev, oct_dev);
1065
1066 /* set linux specific device pointer */
1067 oct_dev->pci_dev = (void *)pdev;
1068
1069 hs = &handshake[oct_dev->octeon_id];
1070 init_completion(&hs->init);
1071 init_completion(&hs->started);
1072 hs->pci_dev = pdev;
1073
1074 if (oct_dev->octeon_id == 0)
1075 /* first LiquidIO NIC is detected */
1076 complete(&first_stage);
1077
1078 if (octeon_device_init(oct_dev)) {
1079 liquidio_remove(pdev);
1080 return -ENOMEM;
1081 }
1082
1083 dev_dbg(&oct_dev->pci_dev->dev, "Device is ready\n");
1084
1085 return 0;
1086}
1087
1088/**
1089 *\brief Destroy resources associated with octeon device
1090 * @param pdev PCI device structure
1091 * @param ent unused
1092 */
1093static void octeon_destroy_resources(struct octeon_device *oct)
1094{
1095 int i;
1096 struct octeon_device_priv *oct_priv =
1097 (struct octeon_device_priv *)oct->priv;
1098
1099 struct handshake *hs;
1100
1101 switch (atomic_read(&oct->status)) {
1102 case OCT_DEV_RUNNING:
1103 case OCT_DEV_CORE_OK:
1104
1105 /* No more instructions will be forwarded. */
1106 atomic_set(&oct->status, OCT_DEV_IN_RESET);
1107
1108 oct->app_mode = CVM_DRV_INVALID_APP;
1109 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
1110 lio_get_state_string(&oct->status));
1111
1112 schedule_timeout_uninterruptible(HZ / 10);
1113
1114 /* fallthrough */
1115 case OCT_DEV_HOST_OK:
1116
1117 /* fallthrough */
1118 case OCT_DEV_CONSOLE_INIT_DONE:
1119 /* Remove any consoles */
1120 octeon_remove_consoles(oct);
1121
1122 /* fallthrough */
1123 case OCT_DEV_IO_QUEUES_DONE:
1124 if (wait_for_pending_requests(oct))
1125 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
1126
1127 if (lio_wait_for_instr_fetch(oct))
1128 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n");
1129
1130 /* Disable the input and output queues now. No more packets will
1131 * arrive from Octeon, but we should wait for all packet
1132 * processing to finish.
1133 */
1134 oct->fn_list.disable_io_queues(oct);
1135
1136 if (lio_wait_for_oq_pkts(oct))
1137 dev_err(&oct->pci_dev->dev, "OQ had pending packets\n");
1138
1139 /* Disable interrupts */
1140 oct->fn_list.disable_interrupt(oct->chip);
1141
1142 /* Release the interrupt line */
1143 free_irq(oct->pci_dev->irq, oct);
1144
1145 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1146 pci_disable_msi(oct->pci_dev);
1147
1148 /* Soft reset the octeon device before exiting */
1149 oct->fn_list.soft_reset(oct);
1150
1151 /* Disable the device, releasing the PCI INT */
1152 pci_disable_device(oct->pci_dev);
1153
1154 /* fallthrough */
1155 case OCT_DEV_IN_RESET:
1156 case OCT_DEV_DROQ_INIT_DONE:
1157 /*atomic_set(&oct->status, OCT_DEV_DROQ_INIT_DONE);*/
1158 mdelay(100);
1159 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES; i++) {
1160 if (!(oct->io_qmask.oq & (1UL << i)))
1161 continue;
1162 octeon_delete_droq(oct, i);
1163 }
1164
1165 /* Force any pending handshakes to complete */
1166 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
1167 hs = &handshake[i];
1168
1169 if (hs->pci_dev) {
1170 handshake[oct->octeon_id].init_ok = 0;
1171 complete(&handshake[oct->octeon_id].init);
1172 handshake[oct->octeon_id].started_ok = 0;
1173 complete(&handshake[oct->octeon_id].started);
1174 }
1175 }
1176
1177 /* fallthrough */
1178 case OCT_DEV_RESP_LIST_INIT_DONE:
1179 octeon_delete_response_list(oct);
1180
1181 /* fallthrough */
1182 case OCT_DEV_SC_BUFF_POOL_INIT_DONE:
1183 octeon_free_sc_buffer_pool(oct);
1184
1185 /* fallthrough */
1186 case OCT_DEV_INSTR_QUEUE_INIT_DONE:
1187 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES; i++) {
1188 if (!(oct->io_qmask.iq & (1UL << i)))
1189 continue;
1190 octeon_delete_instr_queue(oct, i);
1191 }
1192
1193 /* fallthrough */
1194 case OCT_DEV_DISPATCH_INIT_DONE:
1195 octeon_delete_dispatch_list(oct);
1196 cancel_delayed_work_sync(&oct->nic_poll_work.work);
1197
1198 /* fallthrough */
1199 case OCT_DEV_PCI_MAP_DONE:
1200 octeon_unmap_pci_barx(oct, 0);
1201 octeon_unmap_pci_barx(oct, 1);
1202
1203 /* fallthrough */
1204 case OCT_DEV_BEGIN_STATE:
1205 /* Nothing to be done here either */
1206 break;
1207 } /* end switch(oct->status) */
1208
1209 tasklet_kill(&oct_priv->droq_tasklet);
1210}
1211
1212/**
1213 * \brief Send Rx control command
1214 * @param lio per-network private data
1215 * @param start_stop whether to start or stop
1216 */
1217static void send_rx_ctrl_cmd(struct lio *lio, int start_stop)
1218{
1219 struct octnic_ctrl_pkt nctrl;
1220 struct octnic_ctrl_params nparams;
1221
1222 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
1223
1224 nctrl.ncmd.s.cmd = OCTNET_CMD_RX_CTL;
1225 nctrl.ncmd.s.param1 = lio->linfo.ifidx;
1226 nctrl.ncmd.s.param2 = start_stop;
1227 nctrl.netpndev = (u64)lio->netdev;
1228
1229 nparams.resp_order = OCTEON_RESP_NORESPONSE;
1230
1231 if (octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl, nparams) < 0)
1232 netif_info(lio, rx_err, lio->netdev, "Failed to send RX Control message\n");
1233}
1234
1235/**
1236 * \brief Destroy NIC device interface
1237 * @param oct octeon device
1238 * @param ifidx which interface to destroy
1239 *
1240 * Cleanup associated with each interface for an Octeon device when NIC
1241 * module is being unloaded or if initialization fails during load.
1242 */
1243static void liquidio_destroy_nic_device(struct octeon_device *oct, int ifidx)
1244{
1245 struct net_device *netdev = oct->props[ifidx].netdev;
1246 struct lio *lio;
1247
1248 if (!netdev) {
1249 dev_err(&oct->pci_dev->dev, "%s No netdevice ptr for index %d\n",
1250 __func__, ifidx);
1251 return;
1252 }
1253
1254 lio = GET_LIO(netdev);
1255
1256 dev_dbg(&oct->pci_dev->dev, "NIC device cleanup\n");
1257
1258 send_rx_ctrl_cmd(lio, 0);
1259
1260 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING)
1261 txqs_stop(netdev);
1262
1263 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED)
1264 unregister_netdev(netdev);
1265
fcd2b5e3 1266 delete_glists(lio);
f21fb3ed
RV		 1267
1268 free_netdev(netdev);
1269
1270 oct->props[ifidx].netdev = NULL;
1271}
1272
1273/**
1274 * \brief Stop complete NIC functionality
1275 * @param oct octeon device
1276 */
1277static int liquidio_stop_nic_module(struct octeon_device *oct)
1278{
1279 int i, j;
1280 struct lio *lio;
1281
1282 dev_dbg(&oct->pci_dev->dev, "Stopping network interfaces\n");
1283 if (!oct->ifcount) {
1284 dev_err(&oct->pci_dev->dev, "Init for Octeon was not completed\n");
1285 return 1;
1286 }
1287
1288 for (i = 0; i < oct->ifcount; i++) {
1289 lio = GET_LIO(oct->props[i].netdev);
1290 for (j = 0; j < lio->linfo.num_rxpciq; j++)
26236fa9
RV		 1291 octeon_unregister_droq_ops(oct,
1292 lio->linfo.rxpciq[j].s.q_no);
f21fb3ed
RV		 1293 }
1294
1295 for (i = 0; i < oct->ifcount; i++)
1296 liquidio_destroy_nic_device(oct, i);
1297
1298 dev_dbg(&oct->pci_dev->dev, "Network interfaces stopped\n");
1299 return 0;
1300}
1301
1302/**
1303 * \brief Cleans up resources at unload time
1304 * @param pdev PCI device structure
1305 */
1306static void liquidio_remove(struct pci_dev *pdev)
1307{
1308 struct octeon_device *oct_dev = pci_get_drvdata(pdev);
1309
1310 dev_dbg(&oct_dev->pci_dev->dev, "Stopping device\n");
1311
1312 if (oct_dev->app_mode && (oct_dev->app_mode == CVM_DRV_NIC_APP))
1313 liquidio_stop_nic_module(oct_dev);
1314
1315 /* Reset the octeon device and cleanup all memory allocated for
1316 * the octeon device by driver.
1317 */
1318 octeon_destroy_resources(oct_dev);
1319
1320 dev_info(&oct_dev->pci_dev->dev, "Device removed\n");
1321
1322 /* This octeon device has been removed. Update the global
1323 * data structure to reflect this. Free the device structure.
1324 */
1325 octeon_free_device_mem(oct_dev);
1326}
1327
1328/**
1329 * \brief Identify the Octeon device and to map the BAR address space
1330 * @param oct octeon device
1331 */
1332static int octeon_chip_specific_setup(struct octeon_device *oct)
1333{
1334 u32 dev_id, rev_id;
1335 int ret = 1;
1336
1337 pci_read_config_dword(oct->pci_dev, 0, &dev_id);
1338 pci_read_config_dword(oct->pci_dev, 8, &rev_id);
1339 oct->rev_id = rev_id & 0xff;
1340
1341 switch (dev_id) {
1342 case OCTEON_CN68XX_PCIID:
1343 oct->chip_id = OCTEON_CN68XX;
1344 ret = lio_setup_cn68xx_octeon_device(oct);
1345 break;
1346
1347 case OCTEON_CN66XX_PCIID:
1348 oct->chip_id = OCTEON_CN66XX;
1349 ret = lio_setup_cn66xx_octeon_device(oct);
1350 break;
1351 default:
1352 dev_err(&oct->pci_dev->dev, "Unknown device found (dev_id: %x)\n",
1353 dev_id);
1354 }
1355
1356 if (!ret)
1357 dev_info(&oct->pci_dev->dev, "CN68XX PASS%d.%d %s\n",
1358 OCTEON_MAJOR_REV(oct),
1359 OCTEON_MINOR_REV(oct),
1360 octeon_get_conf(oct)->card_name);
1361
1362 return ret;
1363}
1364
1365/**
1366 * \brief PCI initialization for each Octeon device.
1367 * @param oct octeon device
1368 */
1369static int octeon_pci_os_setup(struct octeon_device *oct)
1370{
1371 /* setup PCI stuff first */
1372 if (pci_enable_device(oct->pci_dev)) {
1373 dev_err(&oct->pci_dev->dev, "pci_enable_device failed\n");
1374 return 1;
1375 }
1376
1377 if (dma_set_mask_and_coherent(&oct->pci_dev->dev, DMA_BIT_MASK(64))) {
1378 dev_err(&oct->pci_dev->dev, "Unexpected DMA device capability\n");
1379 return 1;
1380 }
1381
1382 /* Enable PCI DMA Master. */
1383 pci_set_master(oct->pci_dev);
1384
1385 return 0;
1386}
1387
fcd2b5e3
RV		 1388static inline int skb_iq(struct lio *lio, struct sk_buff *skb)
1389{
1390 int q = 0;
1391
1392 if (netif_is_multiqueue(lio->netdev))
1393 q = skb->queue_mapping % lio->linfo.num_txpciq;
1394
1395 return q;
1396}
1397
f21fb3ed
RV		 1398/**
1399 * \brief Check Tx queue state for a given network buffer
1400 * @param lio per-network private data
1401 * @param skb network buffer
1402 */
1403static inline int check_txq_state(struct lio *lio, struct sk_buff *skb)
1404{
1405 int q = 0, iq = 0;
1406
1407 if (netif_is_multiqueue(lio->netdev)) {
1408 q = skb->queue_mapping;
26236fa9 1409 iq = lio->linfo.txpciq[(q % (lio->linfo.num_txpciq))].s.q_no;
f21fb3ed
RV		 1410 } else {
1411 iq = lio->txq;
26236fa9 1412 q = iq;
f21fb3ed
RV		 1413 }
1414
1415 if (octnet_iq_is_full(lio->oct_dev, iq))
1416 return 0;
26236fa9
RV		 1417
1418 if (__netif_subqueue_stopped(lio->netdev, q))
1419 wake_q(lio->netdev, q);
f21fb3ed
RV		 1420 return 1;
1421}
1422
1423/**
1424 * \brief Unmap and free network buffer
1425 * @param buf buffer
1426 */
1427static void free_netbuf(void *buf)
1428{
1429 struct sk_buff *skb;
1430 struct octnet_buf_free_info *finfo;
1431 struct lio *lio;
1432
1433 finfo = (struct octnet_buf_free_info *)buf;
1434 skb = finfo->skb;
1435 lio = finfo->lio;
1436
1437 dma_unmap_single(&lio->oct_dev->pci_dev->dev, finfo->dptr, skb->len,
1438 DMA_TO_DEVICE);
1439
1440 check_txq_state(lio, skb);
1441
1442 recv_buffer_free((struct sk_buff *)skb);
1443}
1444
1445/**
1446 * \brief Unmap and free gather buffer
1447 * @param buf buffer
1448 */
1449static void free_netsgbuf(void *buf)
1450{
1451 struct octnet_buf_free_info *finfo;
1452 struct sk_buff *skb;
1453 struct lio *lio;
1454 struct octnic_gather *g;
fcd2b5e3 1455 int i, frags, iq;
f21fb3ed
RV		 1456
1457 finfo = (struct octnet_buf_free_info *)buf;
1458 skb = finfo->skb;
1459 lio = finfo->lio;
1460 g = finfo->g;
1461 frags = skb_shinfo(skb)->nr_frags;
1462
1463 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1464 g->sg[0].ptr[0], (skb->len - skb->data_len),
1465 DMA_TO_DEVICE);
1466
1467 i = 1;
1468 while (frags--) {
1469 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1470
1471 pci_unmap_page((lio->oct_dev)->pci_dev,
1472 g->sg[(i >> 2)].ptr[(i & 3)],
1473 frag->size, DMA_TO_DEVICE);
1474 i++;
1475 }
1476
fcd2b5e3
RV		 1477 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
1478 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
f21fb3ed 1479
fcd2b5e3
RV		 1480 iq = skb_iq(lio, skb);
1481 spin_lock(&lio->glist_lock[iq]);
1482 list_add_tail(&g->list, &lio->glist[iq]);
1483 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1484
1485 check_txq_state(lio, skb); /* mq support: sub-queue state check */
1486
1487 recv_buffer_free((struct sk_buff *)skb);
1488}
1489
1490/**
1491 * \brief Unmap and free gather buffer with response
1492 * @param buf buffer
1493 */
1494static void free_netsgbuf_with_resp(void *buf)
1495{
1496 struct octeon_soft_command *sc;
1497 struct octnet_buf_free_info *finfo;
1498 struct sk_buff *skb;
1499 struct lio *lio;
1500 struct octnic_gather *g;
fcd2b5e3 1501 int i, frags, iq;
f21fb3ed
RV		 1502
1503 sc = (struct octeon_soft_command *)buf;
1504 skb = (struct sk_buff *)sc->callback_arg;
1505 finfo = (struct octnet_buf_free_info *)&skb->cb;
1506
1507 lio = finfo->lio;
1508 g = finfo->g;
1509 frags = skb_shinfo(skb)->nr_frags;
1510
1511 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1512 g->sg[0].ptr[0], (skb->len - skb->data_len),
1513 DMA_TO_DEVICE);
1514
1515 i = 1;
1516 while (frags--) {
1517 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1518
1519 pci_unmap_page((lio->oct_dev)->pci_dev,
1520 g->sg[(i >> 2)].ptr[(i & 3)],
1521 frag->size, DMA_TO_DEVICE);
1522 i++;
1523 }
1524
fcd2b5e3
RV		 1525 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
1526 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
f21fb3ed 1527
fcd2b5e3
RV		 1528 iq = skb_iq(lio, skb);
1529
1530 spin_lock(&lio->glist_lock[iq]);
1531 list_add_tail(&g->list, &lio->glist[iq]);
1532 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1533
1534 /* Don't free the skb yet */
1535
1536 check_txq_state(lio, skb);
1537}
1538
1539/**
1540 * \brief Adjust ptp frequency
1541 * @param ptp PTP clock info
1542 * @param ppb how much to adjust by, in parts-per-billion
1543 */
1544static int liquidio_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
1545{
1546 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1547 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1548 u64 comp, delta;
1549 unsigned long flags;
1550 bool neg_adj = false;
1551
1552 if (ppb < 0) {
1553 neg_adj = true;
1554 ppb = -ppb;
1555 }
1556
1557 /* The hardware adds the clock compensation value to the
1558 * PTP clock on every coprocessor clock cycle, so we
1559 * compute the delta in terms of coprocessor clocks.
1560 */
1561 delta = (u64)ppb << 32;
1562 do_div(delta, oct->coproc_clock_rate);
1563
1564 spin_lock_irqsave(&lio->ptp_lock, flags);
1565 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP);
1566 if (neg_adj)
1567 comp -= delta;
1568 else
1569 comp += delta;
1570 lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP);
1571 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1572
1573 return 0;
1574}
1575
1576/**
1577 * \brief Adjust ptp time
1578 * @param ptp PTP clock info
1579 * @param delta how much to adjust by, in nanosecs
1580 */
1581static int liquidio_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
1582{
1583 unsigned long flags;
1584 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1585
1586 spin_lock_irqsave(&lio->ptp_lock, flags);
1587 lio->ptp_adjust += delta;
1588 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1589
1590 return 0;
1591}
1592
1593/**
1594 * \brief Get hardware clock time, including any adjustment
1595 * @param ptp PTP clock info
1596 * @param ts timespec
1597 */
1598static int liquidio_ptp_gettime(struct ptp_clock_info *ptp,
1599 struct timespec64 *ts)
1600{
1601 u64 ns;
f21fb3ed
RV		 1602 unsigned long flags;
1603 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1604 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1605
1606 spin_lock_irqsave(&lio->ptp_lock, flags);
1607 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI);
1608 ns += lio->ptp_adjust;
1609 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1610
286af315 1611 *ts = ns_to_timespec64(ns);
f21fb3ed
RV		 1612
1613 return 0;
1614}
1615
1616/**
1617 * \brief Set hardware clock time. Reset adjustment
1618 * @param ptp PTP clock info
1619 * @param ts timespec
1620 */
1621static int liquidio_ptp_settime(struct ptp_clock_info *ptp,
1622 const struct timespec64 *ts)
1623{
1624 u64 ns;
1625 unsigned long flags;
1626 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1627 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1628
1629 ns = timespec_to_ns(ts);
1630
1631 spin_lock_irqsave(&lio->ptp_lock, flags);
1632 lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI);
1633 lio->ptp_adjust = 0;
1634 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1635
1636 return 0;
1637}
1638
1639/**
1640 * \brief Check if PTP is enabled
1641 * @param ptp PTP clock info
1642 * @param rq request
1643 * @param on is it on
1644 */
1645static int liquidio_ptp_enable(struct ptp_clock_info *ptp,
1646 struct ptp_clock_request *rq, int on)
1647{
1648 return -EOPNOTSUPP;
1649}
1650
1651/**
1652 * \brief Open PTP clock source
1653 * @param netdev network device
1654 */
1655static void oct_ptp_open(struct net_device *netdev)
1656{
1657 struct lio *lio = GET_LIO(netdev);
1658 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1659
1660 spin_lock_init(&lio->ptp_lock);
1661
1662 snprintf(lio->ptp_info.name, 16, "%s", netdev->name);
1663 lio->ptp_info.owner = THIS_MODULE;
1664 lio->ptp_info.max_adj = 250000000;
1665 lio->ptp_info.n_alarm = 0;
1666 lio->ptp_info.n_ext_ts = 0;
1667 lio->ptp_info.n_per_out = 0;
1668 lio->ptp_info.pps = 0;
1669 lio->ptp_info.adjfreq = liquidio_ptp_adjfreq;
1670 lio->ptp_info.adjtime = liquidio_ptp_adjtime;
1671 lio->ptp_info.gettime64 = liquidio_ptp_gettime;
1672 lio->ptp_info.settime64 = liquidio_ptp_settime;
1673 lio->ptp_info.enable = liquidio_ptp_enable;
1674
1675 lio->ptp_adjust = 0;
1676
1677 lio->ptp_clock = ptp_clock_register(&lio->ptp_info,
1678 &oct->pci_dev->dev);
1679
1680 if (IS_ERR(lio->ptp_clock))
1681 lio->ptp_clock = NULL;
1682}
1683
1684/**
1685 * \brief Init PTP clock
1686 * @param oct octeon device
1687 */
1688static void liquidio_ptp_init(struct octeon_device *oct)
1689{
1690 u64 clock_comp, cfg;
1691
1692 clock_comp = (u64)NSEC_PER_SEC << 32;
1693 do_div(clock_comp, oct->coproc_clock_rate);
1694 lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP);
1695
1696 /* Enable */
1697 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG);
1698 lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG);
1699}
1700
1701/**
1702 * \brief Load firmware to device
1703 * @param oct octeon device
1704 *
1705 * Maps device to firmware filename, requests firmware, and downloads it
1706 */
1707static int load_firmware(struct octeon_device *oct)
1708{
1709 int ret = 0;
1710 const struct firmware *fw;
1711 char fw_name[LIO_MAX_FW_FILENAME_LEN];
1712 char *tmp_fw_type;
1713
1714 if (strncmp(fw_type, LIO_FW_NAME_TYPE_NONE,
1715 sizeof(LIO_FW_NAME_TYPE_NONE)) == 0) {
1716 dev_info(&oct->pci_dev->dev, "Skipping firmware load\n");
1717 return ret;
1718 }
1719
1720 if (fw_type[0] == '\0')
1721 tmp_fw_type = LIO_FW_NAME_TYPE_NIC;
1722 else
1723 tmp_fw_type = fw_type;
1724
1725 sprintf(fw_name, "%s%s%s_%s%s", LIO_FW_DIR, LIO_FW_BASE_NAME,
1726 octeon_get_conf(oct)->card_name, tmp_fw_type,
1727 LIO_FW_NAME_SUFFIX);
1728
1729 ret = request_firmware(&fw, fw_name, &oct->pci_dev->dev);
1730 if (ret) {
1731 dev_err(&oct->pci_dev->dev, "Request firmware failed. Could not find file %s.\n.",
1732 fw_name);
1733 return ret;
1734 }
1735
1736 ret = octeon_download_firmware(oct, fw->data, fw->size);
1737
1738 release_firmware(fw);
1739
1740 return ret;
1741}
1742
1743/**
1744 * \brief Setup output queue
1745 * @param oct octeon device
1746 * @param q_no which queue
1747 * @param num_descs how many descriptors
1748 * @param desc_size size of each descriptor
1749 * @param app_ctx application context
1750 */
1751static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs,
1752 int desc_size, void *app_ctx)
1753{
1754 int ret_val = 0;
1755
1756 dev_dbg(&oct->pci_dev->dev, "Creating Droq: %d\n", q_no);
1757 /* droq creation and local register settings. */
1758 ret_val = octeon_create_droq(oct, q_no, num_descs, desc_size, app_ctx);
08a965ec 1759 if (ret_val < 0)
f21fb3ed
RV		 1760 return ret_val;
1761
1762 if (ret_val == 1) {
1763 dev_dbg(&oct->pci_dev->dev, "Using default droq %d\n", q_no);
1764 return 0;
1765 }
1766 /* tasklet creation for the droq */
1767
1768 /* Enable the droq queues */
1769 octeon_set_droq_pkt_op(oct, q_no, 1);
1770
1771 /* Send Credit for Octeon Output queues. Credits are always
1772 * sent after the output queue is enabled.
1773 */
1774 writel(oct->droq[q_no]->max_count,
1775 oct->droq[q_no]->pkts_credit_reg);
1776
1777 return ret_val;
1778}
1779
1780/**
1781 * \brief Callback for getting interface configuration
1782 * @param status status of request
1783 * @param buf pointer to resp structure
1784 */
1785static void if_cfg_callback(struct octeon_device *oct,
1786 u32 status,
1787 void *buf)
1788{
1789 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
1790 struct liquidio_if_cfg_resp *resp;
1791 struct liquidio_if_cfg_context *ctx;
1792
1793 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
1794 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
1795
1796 oct = lio_get_device(ctx->octeon_id);
1797 if (resp->status)
1798 dev_err(&oct->pci_dev->dev, "nic if cfg instruction failed. Status: %llx\n",
1799 CVM_CAST64(resp->status));
1800 ACCESS_ONCE(ctx->cond) = 1;
1801
1802 /* This barrier is required to be sure that the response has been
1803 * written fully before waking up the handler
1804 */
1805 wmb();
1806
1807 wake_up_interruptible(&ctx->wc);
1808}
1809
1810/**
1811 * \brief Select queue based on hash
1812 * @param dev Net device
1813 * @param skb sk_buff structure
1814 * @returns selected queue number
1815 */
1816static u16 select_q(struct net_device *dev, struct sk_buff *skb,
1817 void *accel_priv, select_queue_fallback_t fallback)
1818{
26236fa9 1819 u32 qindex = 0;
f21fb3ed
RV		 1820 struct lio *lio;
1821
1822 lio = GET_LIO(dev);
26236fa9
RV		 1823 qindex = skb_tx_hash(dev, skb);
1824
1825 return (u16)(qindex % (lio->linfo.num_txpciq));
f21fb3ed
RV		 1826}
1827
1828/** Routine to push packets arriving on Octeon interface upto network layer.
1829 * @param oct_id - octeon device id.
1830 * @param skbuff - skbuff struct to be passed to network layer.
1831 * @param len - size of total data received.
1832 * @param rh - Control header associated with the packet
1833 * @param param - additional control data with the packet
1834 */
1835static void
1836liquidio_push_packet(u32 octeon_id,
1837 void *skbuff,
1838 u32 len,
1839 union octeon_rh *rh,
1840 void *param)
1841{
1842 struct napi_struct *napi = param;
1843 struct octeon_device *oct = lio_get_device(octeon_id);
1844 struct sk_buff *skb = (struct sk_buff *)skbuff;
1845 struct skb_shared_hwtstamps *shhwtstamps;
1846 u64 ns;
1847 struct net_device *netdev =
1848 (struct net_device *)oct->props[rh->r_dh.link].netdev;
1849 struct octeon_droq *droq = container_of(param, struct octeon_droq,
1850 napi);
1851 if (netdev) {
1852 int packet_was_received;
1853 struct lio *lio = GET_LIO(netdev);
1854
1855 /* Do not proceed if the interface is not in RUNNING state. */
1856 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) {
1857 recv_buffer_free(skb);
1858 droq->stats.rx_dropped++;
1859 return;
1860 }
1861
1862 skb->dev = netdev;
1863
26236fa9
RV		 1864 skb_record_rx_queue(skb, droq->q_no);
1865
f21fb3ed
RV		 1866 if (rh->r_dh.has_hwtstamp) {
1867 /* timestamp is included from the hardware at the
1868 * beginning of the packet.
1869 */
1870 if (ifstate_check(lio,
1871 LIO_IFSTATE_RX_TIMESTAMP_ENABLED)) {
1872 /* Nanoseconds are in the first 64-bits
1873 * of the packet.
1874 */
1875 memcpy(&ns, (skb->data), sizeof(ns));
1876 shhwtstamps = skb_hwtstamps(skb);
1877 shhwtstamps->hwtstamp =
1878 ns_to_ktime(ns + lio->ptp_adjust);
1879 }
1880 skb_pull(skb, sizeof(ns));
1881 }
1882
1883 skb->protocol = eth_type_trans(skb, skb->dev);
1884
1885 if ((netdev->features & NETIF_F_RXCSUM) &&
1886 (rh->r_dh.csum_verified == CNNIC_CSUM_VERIFIED))
1887 /* checksum has already been verified */
1888 skb->ip_summed = CHECKSUM_UNNECESSARY;
1889 else
1890 skb->ip_summed = CHECKSUM_NONE;
1891
1892 packet_was_received = napi_gro_receive(napi, skb) != GRO_DROP;
1893
1894 if (packet_was_received) {
1895 droq->stats.rx_bytes_received += len;
1896 droq->stats.rx_pkts_received++;
1897 netdev->last_rx = jiffies;
1898 } else {
1899 droq->stats.rx_dropped++;
1900 netif_info(lio, rx_err, lio->netdev,
1901 "droq:%d error rx_dropped:%llu\n",
1902 droq->q_no, droq->stats.rx_dropped);
1903 }
1904
1905 } else {
1906 recv_buffer_free(skb);
1907 }
1908}
1909
1910/**
1911 * \brief wrapper for calling napi_schedule
1912 * @param param parameters to pass to napi_schedule
1913 *
1914 * Used when scheduling on different CPUs
1915 */
1916static void napi_schedule_wrapper(void *param)
1917{
1918 struct napi_struct *napi = param;
1919
1920 napi_schedule(napi);
1921}
1922
1923/**
1924 * \brief callback when receive interrupt occurs and we are in NAPI mode
1925 * @param arg pointer to octeon output queue
1926 */
1927static void liquidio_napi_drv_callback(void *arg)
1928{
1929 struct octeon_droq *droq = arg;
1930 int this_cpu = smp_processor_id();
1931
1932 if (droq->cpu_id == this_cpu) {
1933 napi_schedule(&droq->napi);
1934 } else {
1935 struct call_single_data *csd = &droq->csd;
1936
1937 csd->func = napi_schedule_wrapper;
1938 csd->info = &droq->napi;
1939 csd->flags = 0;
1940
1941 smp_call_function_single_async(droq->cpu_id, csd);
1942 }
1943}
1944
1945/**
1946 * \brief Main NAPI poll function
1947 * @param droq octeon output queue
1948 * @param budget maximum number of items to process
1949 */
1950static int liquidio_napi_do_rx(struct octeon_droq *droq, int budget)
1951{
1952 int work_done;
1953 struct lio *lio = GET_LIO(droq->napi.dev);
1954 struct octeon_device *oct = lio->oct_dev;
1955
1956 work_done = octeon_process_droq_poll_cmd(oct, droq->q_no,
1957 POLL_EVENT_PROCESS_PKTS,
1958 budget);
1959 if (work_done < 0) {
1960 netif_info(lio, rx_err, lio->netdev,
1961 "Receive work_done < 0, rxq:%d\n", droq->q_no);
1962 goto octnet_napi_finish;
1963 }
1964
1965 if (work_done > budget)
1966 dev_err(&oct->pci_dev->dev, ">>>> %s work_done: %d budget: %d\n",
1967 __func__, work_done, budget);
1968
1969 return work_done;
1970
1971octnet_napi_finish:
1972 napi_complete(&droq->napi);
1973 octeon_process_droq_poll_cmd(oct, droq->q_no, POLL_EVENT_ENABLE_INTR,
1974 0);
1975 return 0;
1976}
1977
1978/**
1979 * \brief Entry point for NAPI polling
1980 * @param napi NAPI structure
1981 * @param budget maximum number of items to process
1982 */
1983static int liquidio_napi_poll(struct napi_struct *napi, int budget)
1984{
1985 struct octeon_droq *droq;
1986 int work_done;
1987
1988 droq = container_of(napi, struct octeon_droq, napi);
1989
1990 work_done = liquidio_napi_do_rx(droq, budget);
1991
1992 if (work_done < budget) {
1993 napi_complete(napi);
1994 octeon_process_droq_poll_cmd(droq->oct_dev, droq->q_no,
1995 POLL_EVENT_ENABLE_INTR, 0);
1996 return 0;
1997 }
1998
1999 return work_done;
2000}
2001
2002/**
2003 * \brief Setup input and output queues
2004 * @param octeon_dev octeon device
2005 * @param net_device Net device
2006 *
2007 * Note: Queues are with respect to the octeon device. Thus
2008 * an input queue is for egress packets, and output queues
2009 * are for ingress packets.
2010 */
2011static inline int setup_io_queues(struct octeon_device *octeon_dev,
2012 struct net_device *net_device)
2013{
2014 static int first_time = 1;
2015 static struct octeon_droq_ops droq_ops;
2016 static int cpu_id;
2017 static int cpu_id_modulus;
2018 struct octeon_droq *droq;
2019 struct napi_struct *napi;
2020 int q, q_no, retval = 0;
2021 struct lio *lio;
2022 int num_tx_descs;
2023
2024 lio = GET_LIO(net_device);
2025 if (first_time) {
2026 first_time = 0;
2027 memset(&droq_ops, 0, sizeof(struct octeon_droq_ops));
2028
2029 droq_ops.fptr = liquidio_push_packet;
2030
2031 droq_ops.poll_mode = 1;
2032 droq_ops.napi_fn = liquidio_napi_drv_callback;
2033 cpu_id = 0;
2034 cpu_id_modulus = num_present_cpus();
2035 }
2036
2037 /* set up DROQs. */
2038 for (q = 0; q < lio->linfo.num_rxpciq; q++) {
26236fa9
RV		 2039 q_no = lio->linfo.rxpciq[q].s.q_no;
2040 dev_dbg(&octeon_dev->pci_dev->dev,
2041 "setup_io_queues index:%d linfo.rxpciq.s.q_no:%d\n",
2042 q, q_no);
f21fb3ed
RV		 2043 retval = octeon_setup_droq(octeon_dev, q_no,
2044 CFG_GET_NUM_RX_DESCS_NIC_IF
2045 (octeon_get_conf(octeon_dev),
2046 lio->ifidx),
2047 CFG_GET_NUM_RX_BUF_SIZE_NIC_IF
2048 (octeon_get_conf(octeon_dev),
2049 lio->ifidx), NULL);
2050 if (retval) {
2051 dev_err(&octeon_dev->pci_dev->dev,
2052 " %s : Runtime DROQ(RxQ) creation failed.\n",
2053 __func__);
2054 return 1;
2055 }
2056
2057 droq = octeon_dev->droq[q_no];
2058 napi = &droq->napi;
2059 netif_napi_add(net_device, napi, liquidio_napi_poll, 64);
2060
2061 /* designate a CPU for this droq */
2062 droq->cpu_id = cpu_id;
2063 cpu_id++;
2064 if (cpu_id >= cpu_id_modulus)
2065 cpu_id = 0;
2066
2067 octeon_register_droq_ops(octeon_dev, q_no, &droq_ops);
2068 }
2069
2070 /* set up IQs. */
2071 for (q = 0; q < lio->linfo.num_txpciq; q++) {
2072 num_tx_descs = CFG_GET_NUM_TX_DESCS_NIC_IF(octeon_get_conf
2073 (octeon_dev),
2074 lio->ifidx);
2075 retval = octeon_setup_iq(octeon_dev, lio->linfo.txpciq[q],
2076 num_tx_descs,
2077 netdev_get_tx_queue(net_device, q));
2078 if (retval) {
2079 dev_err(&octeon_dev->pci_dev->dev,
2080 " %s : Runtime IQ(TxQ) creation failed.\n",
2081 __func__);
2082 return 1;
2083 }
2084 }
2085
2086 return 0;
2087}
2088
2089/**
2090 * \brief Poll routine for checking transmit queue status
2091 * @param work work_struct data structure
2092 */
2093static void octnet_poll_check_txq_status(struct work_struct *work)
2094{
2095 struct cavium_wk *wk = (struct cavium_wk *)work;
2096 struct lio *lio = (struct lio *)wk->ctxptr;
2097
2098 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING))
2099 return;
2100
2101 check_txq_status(lio);
2102 queue_delayed_work(lio->txq_status_wq.wq,
2103 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2104}
2105
2106/**
2107 * \brief Sets up the txq poll check
2108 * @param netdev network device
2109 */
2110static inline void setup_tx_poll_fn(struct net_device *netdev)
2111{
2112 struct lio *lio = GET_LIO(netdev);
2113 struct octeon_device *oct = lio->oct_dev;
2114
292b9dab
BS		 2115 lio->txq_status_wq.wq = alloc_workqueue("txq-status",
2116 WQ_MEM_RECLAIM, 0);
f21fb3ed
RV		 2117 if (!lio->txq_status_wq.wq) {
2118 dev_err(&oct->pci_dev->dev, "unable to create cavium txq status wq\n");
2119 return;
2120 }
2121 INIT_DELAYED_WORK(&lio->txq_status_wq.wk.work,
2122 octnet_poll_check_txq_status);
2123 lio->txq_status_wq.wk.ctxptr = lio;
2124 queue_delayed_work(lio->txq_status_wq.wq,
2125 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2126}
2127
2128/**
2129 * \brief Net device open for LiquidIO
2130 * @param netdev network device
2131 */
2132static int liquidio_open(struct net_device *netdev)
2133{
2134 struct lio *lio = GET_LIO(netdev);
2135 struct octeon_device *oct = lio->oct_dev;
2136 struct napi_struct *napi, *n;
2137
2138 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
2139 napi_enable(napi);
2140
2141 oct_ptp_open(netdev);
2142
2143 ifstate_set(lio, LIO_IFSTATE_RUNNING);
2144 setup_tx_poll_fn(netdev);
2145 start_txq(netdev);
2146
2147 netif_info(lio, ifup, lio->netdev, "Interface Open, ready for traffic\n");
2148 try_module_get(THIS_MODULE);
2149
2150 /* tell Octeon to start forwarding packets to host */
2151 send_rx_ctrl_cmd(lio, 1);
2152
2153 /* Ready for link status updates */
2154 lio->intf_open = 1;
2155
2156 dev_info(&oct->pci_dev->dev, "%s interface is opened\n",
2157 netdev->name);
2158
2159 return 0;
2160}
2161
2162/**
2163 * \brief Net device stop for LiquidIO
2164 * @param netdev network device
2165 */
2166static int liquidio_stop(struct net_device *netdev)
2167{
2168 struct napi_struct *napi, *n;
2169 struct lio *lio = GET_LIO(netdev);
2170 struct octeon_device *oct = lio->oct_dev;
2171
2172 netif_info(lio, ifdown, lio->netdev, "Stopping interface!\n");
2173 /* Inform that netif carrier is down */
2174 lio->intf_open = 0;
2175 lio->linfo.link.s.status = 0;
2176
2177 netif_carrier_off(netdev);
2178
2179 /* tell Octeon to stop forwarding packets to host */
2180 send_rx_ctrl_cmd(lio, 0);
2181
2182 cancel_delayed_work_sync(&lio->txq_status_wq.wk.work);
f21fb3ed
RV		 2183 destroy_workqueue(lio->txq_status_wq.wq);
2184
2185 if (lio->ptp_clock) {
2186 ptp_clock_unregister(lio->ptp_clock);
2187 lio->ptp_clock = NULL;
2188 }
2189
2190 ifstate_reset(lio, LIO_IFSTATE_RUNNING);
2191
2192 /* This is a hack that allows DHCP to continue working. */
2193 set_bit(__LINK_STATE_START, &lio->netdev->state);
2194
2195 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
2196 napi_disable(napi);
2197
2198 txqs_stop(netdev);
2199
2200 dev_info(&oct->pci_dev->dev, "%s interface is stopped\n", netdev->name);
2201 module_put(THIS_MODULE);
2202
2203 return 0;
2204}
2205
2206void liquidio_link_ctrl_cmd_completion(void *nctrl_ptr)
2207{
2208 struct octnic_ctrl_pkt *nctrl = (struct octnic_ctrl_pkt *)nctrl_ptr;
2209 struct net_device *netdev = (struct net_device *)nctrl->netpndev;
2210 struct lio *lio = GET_LIO(netdev);
2211 struct octeon_device *oct = lio->oct_dev;
2212
2213 switch (nctrl->ncmd.s.cmd) {
2214 case OCTNET_CMD_CHANGE_DEVFLAGS:
2215 case OCTNET_CMD_SET_MULTI_LIST:
2216 break;
2217
2218 case OCTNET_CMD_CHANGE_MACADDR:
2219 /* If command is successful, change the MACADDR. */
2220 netif_info(lio, probe, lio->netdev, " MACAddr changed to 0x%llx\n",
2221 CVM_CAST64(nctrl->udd[0]));
2222 dev_info(&oct->pci_dev->dev, "%s MACAddr changed to 0x%llx\n",
2223 netdev->name, CVM_CAST64(nctrl->udd[0]));
2224 memcpy(netdev->dev_addr, ((u8 *)&nctrl->udd[0]) + 2, ETH_ALEN);
2225 break;
2226
2227 case OCTNET_CMD_CHANGE_MTU:
2228 /* If command is successful, change the MTU. */
2229 netif_info(lio, probe, lio->netdev, " MTU Changed from %d to %d\n",
2230 netdev->mtu, nctrl->ncmd.s.param2);
2231 dev_info(&oct->pci_dev->dev, "%s MTU Changed from %d to %d\n",
2232 netdev->name, netdev->mtu,
2233 nctrl->ncmd.s.param2);
2234 netdev->mtu = nctrl->ncmd.s.param2;
2235 break;
2236
2237 case OCTNET_CMD_GPIO_ACCESS:
2238 netif_info(lio, probe, lio->netdev, "LED Flashing visual identification\n");
2239
2240 break;
2241
2242 case OCTNET_CMD_LRO_ENABLE:
2243 dev_info(&oct->pci_dev->dev, "%s LRO Enabled\n", netdev->name);
2244 break;
2245
2246 case OCTNET_CMD_LRO_DISABLE:
2247 dev_info(&oct->pci_dev->dev, "%s LRO Disabled\n",
2248 netdev->name);
2249 break;
2250
2251 case OCTNET_CMD_VERBOSE_ENABLE:
2252 dev_info(&oct->pci_dev->dev, "%s LRO Enabled\n", netdev->name);
2253 break;
2254
2255 case OCTNET_CMD_VERBOSE_DISABLE:
2256 dev_info(&oct->pci_dev->dev, "%s LRO Disabled\n",
2257 netdev->name);
2258 break;
2259
2260 case OCTNET_CMD_SET_SETTINGS:
2261 dev_info(&oct->pci_dev->dev, "%s settings changed\n",
2262 netdev->name);
2263
2264 break;
2265
2266 default:
2267 dev_err(&oct->pci_dev->dev, "%s Unknown cmd %d\n", __func__,
2268 nctrl->ncmd.s.cmd);
2269 }
2270}
2271
2272/**
2273 * \brief Converts a mask based on net device flags
2274 * @param netdev network device
2275 *
2276 * This routine generates a octnet_ifflags mask from the net device flags
2277 * received from the OS.
2278 */
2279static inline enum octnet_ifflags get_new_flags(struct net_device *netdev)
2280{
2281 enum octnet_ifflags f = OCTNET_IFFLAG_UNICAST;
2282
2283 if (netdev->flags & IFF_PROMISC)
2284 f |= OCTNET_IFFLAG_PROMISC;
2285
2286 if (netdev->flags & IFF_ALLMULTI)
2287 f |= OCTNET_IFFLAG_ALLMULTI;
2288
2289 if (netdev->flags & IFF_MULTICAST) {
2290 f |= OCTNET_IFFLAG_MULTICAST;
2291
2292 /* Accept all multicast addresses if there are more than we
2293 * can handle
2294 */
2295 if (netdev_mc_count(netdev) > MAX_OCTEON_MULTICAST_ADDR)
2296 f |= OCTNET_IFFLAG_ALLMULTI;
2297 }
2298
2299 if (netdev->flags & IFF_BROADCAST)
2300 f |= OCTNET_IFFLAG_BROADCAST;
2301
2302 return f;
2303}
2304
2305/**
2306 * \brief Net device set_multicast_list
2307 * @param netdev network device
2308 */
2309static void liquidio_set_mcast_list(struct net_device *netdev)
2310{
2311 struct lio *lio = GET_LIO(netdev);
2312 struct octeon_device *oct = lio->oct_dev;
2313 struct octnic_ctrl_pkt nctrl;
2314 struct octnic_ctrl_params nparams;
2315 struct netdev_hw_addr *ha;
2316 u64 *mc;
2317 int ret, i;
2318 int mc_count = min(netdev_mc_count(netdev), MAX_OCTEON_MULTICAST_ADDR);
2319
2320 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2321
2322 /* Create a ctrl pkt command to be sent to core app. */
2323 nctrl.ncmd.u64 = 0;
2324 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_MULTI_LIST;
2325 nctrl.ncmd.s.param1 = lio->linfo.ifidx;
2326 nctrl.ncmd.s.param2 = get_new_flags(netdev);
2327 nctrl.ncmd.s.param3 = mc_count;
2328 nctrl.ncmd.s.more = mc_count;
2329 nctrl.netpndev = (u64)netdev;
2330 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2331
2332 /* copy all the addresses into the udd */
2333 i = 0;
2334 mc = &nctrl.udd[0];
2335 netdev_for_each_mc_addr(ha, netdev) {
2336 *mc = 0;
2337 memcpy(((u8 *)mc) + 2, ha->addr, ETH_ALEN);
2338 /* no need to swap bytes */
2339
2340 if (++mc > &nctrl.udd[mc_count])
2341 break;
2342 }
2343
2344 /* Apparently, any activity in this call from the kernel has to
2345 * be atomic. So we won't wait for response.
2346 */
2347 nctrl.wait_time = 0;
2348
2349 nparams.resp_order = OCTEON_RESP_NORESPONSE;
2350
2351 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl, nparams);
2352 if (ret < 0) {
2353 dev_err(&oct->pci_dev->dev, "DEVFLAGS change failed in core (ret: 0x%x)\n",
2354 ret);
2355 }
2356}
2357
2358/**
2359 * \brief Net device set_mac_address
2360 * @param netdev network device
2361 */
2362static int liquidio_set_mac(struct net_device *netdev, void *p)
2363{
2364 int ret = 0;
2365 struct lio *lio = GET_LIO(netdev);
2366 struct octeon_device *oct = lio->oct_dev;
2367 struct sockaddr *addr = (struct sockaddr *)p;
2368 struct octnic_ctrl_pkt nctrl;
2369 struct octnic_ctrl_params nparams;
2370
2371 if ((!is_valid_ether_addr(addr->sa_data)) ||
2372 (ifstate_check(lio, LIO_IFSTATE_RUNNING)))
2373 return -EADDRNOTAVAIL;
2374
2375 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2376
2377 nctrl.ncmd.u64 = 0;
2378 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
2379 nctrl.ncmd.s.param1 = lio->linfo.ifidx;
2380 nctrl.ncmd.s.param2 = 0;
2381 nctrl.ncmd.s.more = 1;
2382 nctrl.netpndev = (u64)netdev;
2383 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2384 nctrl.wait_time = 100;
2385
2386 nctrl.udd[0] = 0;
2387 /* The MAC Address is presented in network byte order. */
2388 memcpy((u8 *)&nctrl.udd[0] + 2, addr->sa_data, ETH_ALEN);
2389
2390 nparams.resp_order = OCTEON_RESP_ORDERED;
2391
2392 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl, nparams);
2393 if (ret < 0) {
2394 dev_err(&oct->pci_dev->dev, "MAC Address change failed\n");
2395 return -ENOMEM;
2396 }
2397 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2398 memcpy(((u8 *)&lio->linfo.hw_addr) + 2, addr->sa_data, ETH_ALEN);
2399
2400 return 0;
2401}
2402
2403/**
2404 * \brief Net device get_stats
2405 * @param netdev network device
2406 */
2407static struct net_device_stats *liquidio_get_stats(struct net_device *netdev)
2408{
2409 struct lio *lio = GET_LIO(netdev);
2410 struct net_device_stats *stats = &netdev->stats;
2411 struct octeon_device *oct;
2412 u64 pkts = 0, drop = 0, bytes = 0;
2413 struct oct_droq_stats *oq_stats;
2414 struct oct_iq_stats *iq_stats;
2415 int i, iq_no, oq_no;
2416
2417 oct = lio->oct_dev;
2418
2419 for (i = 0; i < lio->linfo.num_txpciq; i++) {
26236fa9 2420 iq_no = lio->linfo.txpciq[i].s.q_no;
f21fb3ed
RV		 2421 iq_stats = &oct->instr_queue[iq_no]->stats;
2422 pkts += iq_stats->tx_done;
2423 drop += iq_stats->tx_dropped;
2424 bytes += iq_stats->tx_tot_bytes;
2425 }
2426
2427 stats->tx_packets = pkts;
2428 stats->tx_bytes = bytes;
2429 stats->tx_dropped = drop;
2430
2431 pkts = 0;
2432 drop = 0;
2433 bytes = 0;
2434
2435 for (i = 0; i < lio->linfo.num_rxpciq; i++) {
26236fa9 2436 oq_no = lio->linfo.rxpciq[i].s.q_no;
f21fb3ed
RV		 2437 oq_stats = &oct->droq[oq_no]->stats;
2438 pkts += oq_stats->rx_pkts_received;
2439 drop += (oq_stats->rx_dropped +
2440 oq_stats->dropped_nodispatch +
2441 oq_stats->dropped_toomany +
2442 oq_stats->dropped_nomem);
2443 bytes += oq_stats->rx_bytes_received;
2444 }
2445
2446 stats->rx_bytes = bytes;
2447 stats->rx_packets = pkts;
2448 stats->rx_dropped = drop;
2449
2450 return stats;
2451}
2452
2453/**
2454 * \brief Net device change_mtu
2455 * @param netdev network device
2456 */
2457static int liquidio_change_mtu(struct net_device *netdev, int new_mtu)
2458{
2459 struct lio *lio = GET_LIO(netdev);
2460 struct octeon_device *oct = lio->oct_dev;
2461 struct octnic_ctrl_pkt nctrl;
2462 struct octnic_ctrl_params nparams;
2463 int max_frm_size = new_mtu + OCTNET_FRM_HEADER_SIZE;
2464 int ret = 0;
2465
2466 /* Limit the MTU to make sure the ethernet packets are between 64 bytes
2467 * and 65535 bytes
2468 */
2469 if ((max_frm_size < OCTNET_MIN_FRM_SIZE) ||
2470 (max_frm_size > OCTNET_MAX_FRM_SIZE)) {
2471 dev_err(&oct->pci_dev->dev, "Invalid MTU: %d\n", new_mtu);
2472 dev_err(&oct->pci_dev->dev, "Valid range %d and %d\n",
2473 (OCTNET_MIN_FRM_SIZE - OCTNET_FRM_HEADER_SIZE),
2474 (OCTNET_MAX_FRM_SIZE - OCTNET_FRM_HEADER_SIZE));
2475 return -EINVAL;
2476 }
2477
2478 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2479
2480 nctrl.ncmd.u64 = 0;
2481 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MTU;
2482 nctrl.ncmd.s.param1 = lio->linfo.ifidx;
2483 nctrl.ncmd.s.param2 = new_mtu;
2484 nctrl.wait_time = 100;
2485 nctrl.netpndev = (u64)netdev;
2486 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2487
2488 nparams.resp_order = OCTEON_RESP_ORDERED;
2489
2490 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl, nparams);
2491 if (ret < 0) {
2492 dev_err(&oct->pci_dev->dev, "Failed to set MTU\n");
2493 return -1;
2494 }
2495
2496 lio->mtu = new_mtu;
2497
2498 return 0;
2499}
2500
2501/**
2502 * \brief Handler for SIOCSHWTSTAMP ioctl
2503 * @param netdev network device
2504 * @param ifr interface request
2505 * @param cmd command
2506 */
2507static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2508{
2509 struct hwtstamp_config conf;
2510 struct lio *lio = GET_LIO(netdev);
2511
2512 if (copy_from_user(&conf, ifr->ifr_data, sizeof(conf)))
2513 return -EFAULT;
2514
2515 if (conf.flags)
2516 return -EINVAL;
2517
2518 switch (conf.tx_type) {
2519 case HWTSTAMP_TX_ON:
2520 case HWTSTAMP_TX_OFF:
2521 break;
2522 default:
2523 return -ERANGE;
2524 }
2525
2526 switch (conf.rx_filter) {
2527 case HWTSTAMP_FILTER_NONE:
2528 break;
2529 case HWTSTAMP_FILTER_ALL:
2530 case HWTSTAMP_FILTER_SOME:
2531 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2532 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2533 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2534 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2535 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2536 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2537 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2538 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2539 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2540 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2541 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2542 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2543 conf.rx_filter = HWTSTAMP_FILTER_ALL;
2544 break;
2545 default:
2546 return -ERANGE;
2547 }
2548
2549 if (conf.rx_filter == HWTSTAMP_FILTER_ALL)
2550 ifstate_set(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
2551
2552 else
2553 ifstate_reset(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
2554
2555 return copy_to_user(ifr->ifr_data, &conf, sizeof(conf)) ? -EFAULT : 0;
2556}
2557
2558/**
2559 * \brief ioctl handler
2560 * @param netdev network device
2561 * @param ifr interface request
2562 * @param cmd command
2563 */
2564static int liquidio_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2565{
2566 switch (cmd) {
2567 case SIOCSHWTSTAMP:
2568 return hwtstamp_ioctl(netdev, ifr, cmd);
2569 default:
2570 return -EOPNOTSUPP;
2571 }
2572}
2573
2574/**
2575 * \brief handle a Tx timestamp response
2576 * @param status response status
2577 * @param buf pointer to skb
2578 */
2579static void handle_timestamp(struct octeon_device *oct,
2580 u32 status,
2581 void *buf)
2582{
2583 struct octnet_buf_free_info *finfo;
2584 struct octeon_soft_command *sc;
2585 struct oct_timestamp_resp *resp;
2586 struct lio *lio;
2587 struct sk_buff *skb = (struct sk_buff *)buf;
2588
2589 finfo = (struct octnet_buf_free_info *)skb->cb;
2590 lio = finfo->lio;
2591 sc = finfo->sc;
2592 oct = lio->oct_dev;
2593 resp = (struct oct_timestamp_resp *)sc->virtrptr;
2594
2595 if (status != OCTEON_REQUEST_DONE) {
2596 dev_err(&oct->pci_dev->dev, "Tx timestamp instruction failed. Status: %llx\n",
2597 CVM_CAST64(status));
2598 resp->timestamp = 0;
2599 }
2600
2601 octeon_swap_8B_data(&resp->timestamp, 1);
2602
19a6d156 2603 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) != 0)) {
f21fb3ed
RV		 2604 struct skb_shared_hwtstamps ts;
2605 u64 ns = resp->timestamp;
2606
2607 netif_info(lio, tx_done, lio->netdev,
2608 "Got resulting SKBTX_HW_TSTAMP skb=%p ns=%016llu\n",
2609 skb, (unsigned long long)ns);
2610 ts.hwtstamp = ns_to_ktime(ns + lio->ptp_adjust);
2611 skb_tstamp_tx(skb, &ts);
2612 }
2613
2614 octeon_free_soft_command(oct, sc);
2615 recv_buffer_free(skb);
2616}
2617
2618/* \brief Send a data packet that will be timestamped
2619 * @param oct octeon device
2620 * @param ndata pointer to network data
2621 * @param finfo pointer to private network data
2622 */
2623static inline int send_nic_timestamp_pkt(struct octeon_device *oct,
2624 struct octnic_data_pkt *ndata,
2625 struct octnet_buf_free_info *finfo,
2626 int xmit_more)
2627{
2628 int retval;
2629 struct octeon_soft_command *sc;
2630 struct octeon_instr_ih *ih;
2631 struct octeon_instr_rdp *rdp;
2632 struct lio *lio;
2633 int ring_doorbell;
2634
2635 lio = finfo->lio;
2636
2637 sc = octeon_alloc_soft_command_resp(oct, &ndata->cmd,
2638 sizeof(struct oct_timestamp_resp));
2639 finfo->sc = sc;
2640
2641 if (!sc) {
2642 dev_err(&oct->pci_dev->dev, "No memory for timestamped data packet\n");
2643 return IQ_SEND_FAILED;
2644 }
2645
2646 if (ndata->reqtype == REQTYPE_NORESP_NET)
2647 ndata->reqtype = REQTYPE_RESP_NET;
2648 else if (ndata->reqtype == REQTYPE_NORESP_NET_SG)
2649 ndata->reqtype = REQTYPE_RESP_NET_SG;
2650
2651 sc->callback = handle_timestamp;
2652 sc->callback_arg = finfo->skb;
2653 sc->iq_no = ndata->q_no;
2654
2655 ih = (struct octeon_instr_ih *)&sc->cmd.ih;
2656 rdp = (struct octeon_instr_rdp *)&sc->cmd.rdp;
2657
2658 ring_doorbell = !xmit_more;
2659 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd,
2660 sc, ih->dlengsz, ndata->reqtype);
2661
ddc173a6 2662 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 2663 dev_err(&oct->pci_dev->dev, "timestamp data packet failed status: %x\n",
2664 retval);
2665 octeon_free_soft_command(oct, sc);
2666 } else {
2667 netif_info(lio, tx_queued, lio->netdev, "Queued timestamp packet\n");
2668 }
2669
2670 return retval;
2671}
2672
2673static inline int is_ipv4(struct sk_buff *skb)
2674{
2675 return (skb->protocol == htons(ETH_P_IP)) &&
2676 (ip_hdr(skb)->version == 4);
2677}
2678
2679static inline int is_vlan(struct sk_buff *skb)
2680{
2681 return skb->protocol == htons(ETH_P_8021Q);
2682}
2683
2684static inline int is_ip_fragmented(struct sk_buff *skb)
2685{
2686 /* The Don't fragment and Reserved flag fields are ignored.
2687 * IP is fragmented if
2688 * - the More fragments bit is set (indicating this IP is a fragment
2689 * with more to follow; the current offset could be 0 ).
2690 * - ths offset field is non-zero.
2691 */
5b173cf9 2692 return (ip_hdr(skb)->frag_off & htons(IP_MF | IP_OFFSET)) ? 1 : 0;
f21fb3ed
RV		 2693}
2694
2695static inline int is_ipv6(struct sk_buff *skb)
2696{
2697 return (skb->protocol == htons(ETH_P_IPV6)) &&
2698 (ipv6_hdr(skb)->version == 6);
2699}
2700
2701static inline int is_with_extn_hdr(struct sk_buff *skb)
2702{
2703 return (ipv6_hdr(skb)->nexthdr != IPPROTO_TCP) &&
2704 (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP);
2705}
2706
2707static inline int is_tcpudp(struct sk_buff *skb)
2708{
2709 return (ip_hdr(skb)->protocol == IPPROTO_TCP) ||
2710 (ip_hdr(skb)->protocol == IPPROTO_UDP);
2711}
2712
2713static inline u32 get_ipv4_5tuple_tag(struct sk_buff *skb)
2714{
2715 u32 tag;
2716 struct iphdr *iphdr = ip_hdr(skb);
2717
2718 tag = crc32(0, &iphdr->protocol, 1);
2719 tag = crc32(tag, (u8 *)&iphdr->saddr, 8);
2720 tag = crc32(tag, skb_transport_header(skb), 4);
2721 return tag;
2722}
2723
2724static inline u32 get_ipv6_5tuple_tag(struct sk_buff *skb)
2725{
2726 u32 tag;
2727 struct ipv6hdr *ipv6hdr = ipv6_hdr(skb);
2728
2729 tag = crc32(0, &ipv6hdr->nexthdr, 1);
2730 tag = crc32(tag, (u8 *)&ipv6hdr->saddr, 32);
2731 tag = crc32(tag, skb_transport_header(skb), 4);
2732 return tag;
2733}
2734
2735/** \brief Transmit networks packets to the Octeon interface
2736 * @param skbuff skbuff struct to be passed to network layer.
2737 * @param netdev pointer to network device
2738 * @returns whether the packet was transmitted to the device okay or not
2739 * (NETDEV_TX_OK or NETDEV_TX_BUSY)
2740 */
2741static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev)
2742{
2743 struct lio *lio;
2744 struct octnet_buf_free_info *finfo;
2745 union octnic_cmd_setup cmdsetup;
2746 struct octnic_data_pkt ndata;
2747 struct octeon_device *oct;
2748 struct oct_iq_stats *stats;
26236fa9 2749 int status = 0;
f21fb3ed 2750 int q_idx = 0, iq_no = 0;
fcd2b5e3
RV		 2751 int xmit_more, j;
2752 u64 dptr = 0;
f21fb3ed
RV		 2753 u32 tag = 0;
2754
2755 lio = GET_LIO(netdev);
2756 oct = lio->oct_dev;
2757
2758 if (netif_is_multiqueue(netdev)) {
26236fa9
RV		 2759 q_idx = skb->queue_mapping;
2760 q_idx = (q_idx % (lio->linfo.num_txpciq));
2761 tag = q_idx;
2762 iq_no = lio->linfo.txpciq[q_idx].s.q_no;
f21fb3ed
RV		 2763 } else {
2764 iq_no = lio->txq;
2765 }
2766
2767 stats = &oct->instr_queue[iq_no]->stats;
2768
2769 /* Check for all conditions in which the current packet cannot be
2770 * transmitted.
2771 */
2772 if (!(atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) ||
2773 (!lio->linfo.link.s.status) ||
2774 (skb->len <= 0)) {
2775 netif_info(lio, tx_err, lio->netdev,
2776 "Transmit failed link_status : %d\n",
2777 lio->linfo.link.s.status);
2778 goto lio_xmit_failed;
2779 }
2780
2781 /* Use space in skb->cb to store info used to unmap and
2782 * free the buffers.
2783 */
2784 finfo = (struct octnet_buf_free_info *)skb->cb;
2785 finfo->lio = lio;
2786 finfo->skb = skb;
2787 finfo->sc = NULL;
2788
2789 /* Prepare the attributes for the data to be passed to OSI. */
2790 memset(&ndata, 0, sizeof(struct octnic_data_pkt));
2791
2792 ndata.buf = (void *)finfo;
2793
2794 ndata.q_no = iq_no;
2795
2796 if (netif_is_multiqueue(netdev)) {
2797 if (octnet_iq_is_full(oct, ndata.q_no)) {
2798 /* defer sending if queue is full */
2799 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
2800 ndata.q_no);
2801 stats->tx_iq_busy++;
2802 return NETDEV_TX_BUSY;
2803 }
2804 } else {
2805 if (octnet_iq_is_full(oct, lio->txq)) {
2806 /* defer sending if queue is full */
2807 stats->tx_iq_busy++;
2808 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
2809 ndata.q_no);
2810 return NETDEV_TX_BUSY;
2811 }
2812 }
2813 /* pr_info(" XMIT - valid Qs: %d, 1st Q no: %d, cpu: %d, q_no:%d\n",
2814 * lio->linfo.num_txpciq, lio->txq, cpu, ndata.q_no );
2815 */
2816
2817 ndata.datasize = skb->len;
2818
2819 cmdsetup.u64 = 0;
2820 cmdsetup.s.ifidx = lio->linfo.ifidx;
2821
2822 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2823 if (is_ipv4(skb) && !is_ip_fragmented(skb) && is_tcpudp(skb)) {
2824 tag = get_ipv4_5tuple_tag(skb);
2825
2826 cmdsetup.s.cksum_offset = sizeof(struct ethhdr) + 1;
2827
2828 if (ip_hdr(skb)->ihl > 5)
2829 cmdsetup.s.ipv4opts_ipv6exthdr =
2830 OCT_PKT_PARAM_IPV4OPTS;
2831
2832 } else if (is_ipv6(skb)) {
2833 tag = get_ipv6_5tuple_tag(skb);
2834
2835 cmdsetup.s.cksum_offset = sizeof(struct ethhdr) + 1;
2836
2837 if (is_with_extn_hdr(skb))
2838 cmdsetup.s.ipv4opts_ipv6exthdr =
2839 OCT_PKT_PARAM_IPV6EXTHDR;
2840
2841 } else if (is_vlan(skb)) {
2842 if (vlan_eth_hdr(skb)->h_vlan_encapsulated_proto
2843 == htons(ETH_P_IP) &&
2844 !is_ip_fragmented(skb) && is_tcpudp(skb)) {
2845 tag = get_ipv4_5tuple_tag(skb);
2846
2847 cmdsetup.s.cksum_offset =
2848 sizeof(struct vlan_ethhdr) + 1;
2849
2850 if (ip_hdr(skb)->ihl > 5)
2851 cmdsetup.s.ipv4opts_ipv6exthdr =
2852 OCT_PKT_PARAM_IPV4OPTS;
2853
2854 } else if (vlan_eth_hdr(skb)->h_vlan_encapsulated_proto
2855 == htons(ETH_P_IPV6)) {
2856 tag = get_ipv6_5tuple_tag(skb);
2857
2858 cmdsetup.s.cksum_offset =
2859 sizeof(struct vlan_ethhdr) + 1;
2860
2861 if (is_with_extn_hdr(skb))
2862 cmdsetup.s.ipv4opts_ipv6exthdr =
2863 OCT_PKT_PARAM_IPV6EXTHDR;
2864 }
2865 }
2866 }
2867 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
2868 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2869 cmdsetup.s.timestamp = 1;
2870 }
2871
2872 if (skb_shinfo(skb)->nr_frags == 0) {
2873 cmdsetup.s.u.datasize = skb->len;
2874 octnet_prepare_pci_cmd(&ndata.cmd, &cmdsetup, tag);
2875 /* Offload checksum calculation for TCP/UDP packets */
2876 ndata.cmd.dptr = dma_map_single(&oct->pci_dev->dev,
2877 skb->data,
2878 skb->len,
2879 DMA_TO_DEVICE);
2880 if (dma_mapping_error(&oct->pci_dev->dev, ndata.cmd.dptr)) {
2881 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 1\n",
2882 __func__);
2883 return NETDEV_TX_BUSY;
2884 }
2885
2886 finfo->dptr = ndata.cmd.dptr;
2887
2888 ndata.reqtype = REQTYPE_NORESP_NET;
2889
2890 } else {
2891 int i, frags;
2892 struct skb_frag_struct *frag;
2893 struct octnic_gather *g;
2894
fcd2b5e3
RV		 2895 spin_lock(&lio->glist_lock[q_idx]);
2896 g = (struct octnic_gather *)
2897 list_delete_head(&lio->glist[q_idx]);
2898 spin_unlock(&lio->glist_lock[q_idx]);
f21fb3ed
RV		 2899
2900 if (!g) {
2901 netif_info(lio, tx_err, lio->netdev,
2902 "Transmit scatter gather: glist null!\n");
2903 goto lio_xmit_failed;
2904 }
2905
2906 cmdsetup.s.gather = 1;
2907 cmdsetup.s.u.gatherptrs = (skb_shinfo(skb)->nr_frags + 1);
2908 octnet_prepare_pci_cmd(&ndata.cmd, &cmdsetup, tag);
2909
2910 memset(g->sg, 0, g->sg_size);
2911
2912 g->sg[0].ptr[0] = dma_map_single(&oct->pci_dev->dev,
2913 skb->data,
2914 (skb->len - skb->data_len),
2915 DMA_TO_DEVICE);
2916 if (dma_mapping_error(&oct->pci_dev->dev, g->sg[0].ptr[0])) {
2917 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 2\n",
2918 __func__);
2919 return NETDEV_TX_BUSY;
2920 }
2921 add_sg_size(&g->sg[0], (skb->len - skb->data_len), 0);
2922
2923 frags = skb_shinfo(skb)->nr_frags;
2924 i = 1;
2925 while (frags--) {
2926 frag = &skb_shinfo(skb)->frags[i - 1];
2927
2928 g->sg[(i >> 2)].ptr[(i & 3)] =
2929 dma_map_page(&oct->pci_dev->dev,
2930 frag->page.p,
2931 frag->page_offset,
2932 frag->size,
2933 DMA_TO_DEVICE);
2934
fcd2b5e3
RV		 2935 if (dma_mapping_error(&oct->pci_dev->dev,
2936 g->sg[i >> 2].ptr[i & 3])) {
2937 dma_unmap_single(&oct->pci_dev->dev,
2938 g->sg[0].ptr[0],
2939 skb->len - skb->data_len,
2940 DMA_TO_DEVICE);
2941 for (j = 1; j < i; j++) {
2942 frag = &skb_shinfo(skb)->frags[j - 1];
2943 dma_unmap_page(&oct->pci_dev->dev,
2944 g->sg[j >> 2].ptr[j & 3],
2945 frag->size,
2946 DMA_TO_DEVICE);
2947 }
2948 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 3\n",
2949 __func__);
2950 return NETDEV_TX_BUSY;
2951 }
2952
f21fb3ed
RV		 2953 add_sg_size(&g->sg[(i >> 2)], frag->size, (i & 3));
2954 i++;
2955 }
2956
fcd2b5e3
RV		 2957 dma_sync_single_for_device(&oct->pci_dev->dev, g->sg_dma_ptr,
2958 g->sg_size, DMA_TO_DEVICE);
2959 dptr = g->sg_dma_ptr;
f21fb3ed
RV		 2960
2961 finfo->dptr = ndata.cmd.dptr;
2962 finfo->g = g;
2963
2964 ndata.reqtype = REQTYPE_NORESP_NET_SG;
2965 }
2966
2967 if (skb_shinfo(skb)->gso_size) {
2968 struct octeon_instr_irh *irh =
2969 (struct octeon_instr_irh *)&ndata.cmd.irh;
2970 union tx_info *tx_info = (union tx_info *)&ndata.cmd.ossp[0];
2971
2972 irh->len = 1; /* to indicate that ossp[0] contains tx_info */
2973 tx_info->s.gso_size = skb_shinfo(skb)->gso_size;
2974 tx_info->s.gso_segs = skb_shinfo(skb)->gso_segs;
2975 }
2976
2977 xmit_more = skb->xmit_more;
2978
2979 if (unlikely(cmdsetup.s.timestamp))
2980 status = send_nic_timestamp_pkt(oct, &ndata, finfo, xmit_more);
2981 else
2982 status = octnet_send_nic_data_pkt(oct, &ndata, xmit_more);
2983 if (status == IQ_SEND_FAILED)
2984 goto lio_xmit_failed;
2985
2986 netif_info(lio, tx_queued, lio->netdev, "Transmit queued successfully\n");
2987
2988 if (status == IQ_SEND_STOP)
2989 stop_q(lio->netdev, q_idx);
2990
860e9538 2991 netif_trans_update(netdev);
f21fb3ed
RV		 2992
2993 stats->tx_done++;
2994 stats->tx_tot_bytes += skb->len;
2995
2996 return NETDEV_TX_OK;
2997
2998lio_xmit_failed:
2999 stats->tx_dropped++;
3000 netif_info(lio, tx_err, lio->netdev, "IQ%d Transmit dropped:%llu\n",
3001 iq_no, stats->tx_dropped);
3002 dma_unmap_single(&oct->pci_dev->dev, ndata.cmd.dptr,
3003 ndata.datasize, DMA_TO_DEVICE);
3004 recv_buffer_free(skb);
3005 return NETDEV_TX_OK;
3006}
3007
3008/** \brief Network device Tx timeout
3009 * @param netdev pointer to network device
3010 */
3011static void liquidio_tx_timeout(struct net_device *netdev)
3012{
3013 struct lio *lio;
3014
3015 lio = GET_LIO(netdev);
3016
3017 netif_info(lio, tx_err, lio->netdev,
3018 "Transmit timeout tx_dropped:%ld, waking up queues now!!\n",
3019 netdev->stats.tx_dropped);
860e9538 3020 netif_trans_update(netdev);
f21fb3ed
RV		 3021 txqs_wake(netdev);
3022}
3023
3024int liquidio_set_feature(struct net_device *netdev, int cmd)
3025{
3026 struct lio *lio = GET_LIO(netdev);
3027 struct octeon_device *oct = lio->oct_dev;
3028 struct octnic_ctrl_pkt nctrl;
3029 struct octnic_ctrl_params nparams;
3030 int ret = 0;
3031
3032 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3033
3034 nctrl.ncmd.u64 = 0;
3035 nctrl.ncmd.s.cmd = cmd;
3036 nctrl.ncmd.s.param1 = lio->linfo.ifidx;
3037 nctrl.ncmd.s.param2 = OCTNIC_LROIPV4 | OCTNIC_LROIPV6;
3038 nctrl.wait_time = 100;
3039 nctrl.netpndev = (u64)netdev;
3040 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3041
3042 nparams.resp_order = OCTEON_RESP_NORESPONSE;
3043
3044 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl, nparams);
3045 if (ret < 0) {
3046 dev_err(&oct->pci_dev->dev, "Feature change failed in core (ret: 0x%x)\n",
3047 ret);
3048 }
3049 return ret;
3050}
3051
3052/** \brief Net device fix features
3053 * @param netdev pointer to network device
3054 * @param request features requested
3055 * @returns updated features list
3056 */
3057static netdev_features_t liquidio_fix_features(struct net_device *netdev,
3058 netdev_features_t request)
3059{
3060 struct lio *lio = netdev_priv(netdev);
3061
3062 if ((request & NETIF_F_RXCSUM) &&
3063 !(lio->dev_capability & NETIF_F_RXCSUM))
3064 request &= ~NETIF_F_RXCSUM;
3065
3066 if ((request & NETIF_F_HW_CSUM) &&
3067 !(lio->dev_capability & NETIF_F_HW_CSUM))
3068 request &= ~NETIF_F_HW_CSUM;
3069
3070 if ((request & NETIF_F_TSO) && !(lio->dev_capability & NETIF_F_TSO))
3071 request &= ~NETIF_F_TSO;
3072
3073 if ((request & NETIF_F_TSO6) && !(lio->dev_capability & NETIF_F_TSO6))
3074 request &= ~NETIF_F_TSO6;
3075
3076 if ((request & NETIF_F_LRO) && !(lio->dev_capability & NETIF_F_LRO))
3077 request &= ~NETIF_F_LRO;
3078
3079 /*Disable LRO if RXCSUM is off */
3080 if (!(request & NETIF_F_RXCSUM) && (netdev->features & NETIF_F_LRO) &&
3081 (lio->dev_capability & NETIF_F_LRO))
3082 request &= ~NETIF_F_LRO;
3083
3084 return request;
3085}
3086
3087/** \brief Net device set features
3088 * @param netdev pointer to network device
3089 * @param features features to enable/disable
3090 */
3091static int liquidio_set_features(struct net_device *netdev,
3092 netdev_features_t features)
3093{
3094 struct lio *lio = netdev_priv(netdev);
3095
3096 if (!((netdev->features ^ features) & NETIF_F_LRO))
3097 return 0;
3098
3099 if ((features & NETIF_F_LRO) && (lio->dev_capability & NETIF_F_LRO))
3100 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE);
3101 else if (!(features & NETIF_F_LRO) &&
3102 (lio->dev_capability & NETIF_F_LRO))
3103 liquidio_set_feature(netdev, OCTNET_CMD_LRO_DISABLE);
3104
3105 return 0;
3106}
3107
3108static struct net_device_ops lionetdevops = {
3109 .ndo_open = liquidio_open,
3110 .ndo_stop = liquidio_stop,
3111 .ndo_start_xmit = liquidio_xmit,
3112 .ndo_get_stats = liquidio_get_stats,
3113 .ndo_set_mac_address = liquidio_set_mac,
3114 .ndo_set_rx_mode = liquidio_set_mcast_list,
3115 .ndo_tx_timeout = liquidio_tx_timeout,
3116 .ndo_change_mtu = liquidio_change_mtu,
3117 .ndo_do_ioctl = liquidio_ioctl,
3118 .ndo_fix_features = liquidio_fix_features,
3119 .ndo_set_features = liquidio_set_features,
3120};
3121
3122/** \brief Entry point for the liquidio module
3123 */
3124static int __init liquidio_init(void)
3125{
3126 int i;
3127 struct handshake *hs;
3128
3129 init_completion(&first_stage);
3130
3131 octeon_init_device_list(conf_type);
3132
3133 if (liquidio_init_pci())
3134 return -EINVAL;
3135
3136 wait_for_completion_timeout(&first_stage, msecs_to_jiffies(1000));
3137
3138 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3139 hs = &handshake[i];
3140 if (hs->pci_dev) {
3141 wait_for_completion(&hs->init);
3142 if (!hs->init_ok) {
3143 /* init handshake failed */
3144 dev_err(&hs->pci_dev->dev,
3145 "Failed to init device\n");
3146 liquidio_deinit_pci();
3147 return -EIO;
3148 }
3149 }
3150 }
3151
3152 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3153 hs = &handshake[i];
3154 if (hs->pci_dev) {
3155 wait_for_completion_timeout(&hs->started,
3156 msecs_to_jiffies(30000));
3157 if (!hs->started_ok) {
3158 /* starter handshake failed */
3159 dev_err(&hs->pci_dev->dev,
3160 "Firmware failed to start\n");
3161 liquidio_deinit_pci();
3162 return -EIO;
3163 }
3164 }
3165 }
3166
3167 return 0;
3168}
3169
5b173cf9 3170static int lio_nic_info(struct octeon_recv_info *recv_info, void *buf)
f21fb3ed
RV		 3171{
3172 struct octeon_device *oct = (struct octeon_device *)buf;
3173 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
3174 int ifidx = 0;
3175 union oct_link_status *ls;
3176 int i;
3177
3178 if ((recv_pkt->buffer_size[0] != sizeof(*ls)) ||
3179 (recv_pkt->rh.r_nic_info.ifidx > oct->ifcount)) {
3180 dev_err(&oct->pci_dev->dev, "Malformed NIC_INFO, len=%d, ifidx=%d\n",
3181 recv_pkt->buffer_size[0],
3182 recv_pkt->rh.r_nic_info.ifidx);
3183 goto nic_info_err;
3184 }
3185
3186 ifidx = recv_pkt->rh.r_nic_info.ifidx;
3187 ls = (union oct_link_status *)get_rbd(recv_pkt->buffer_ptr[0]);
3188
3189 octeon_swap_8B_data((u64 *)ls, (sizeof(union oct_link_status)) >> 3);
3190
3191 update_link_status(oct->props[ifidx].netdev, ls);
3192
3193nic_info_err:
3194 for (i = 0; i < recv_pkt->buffer_count; i++)
3195 recv_buffer_free(recv_pkt->buffer_ptr[i]);
3196 octeon_free_recv_info(recv_info);
3197 return 0;
3198}
3199
3200/**
3201 * \brief Setup network interfaces
3202 * @param octeon_dev octeon device
3203 *
3204 * Called during init time for each device. It assumes the NIC
3205 * is already up and running. The link information for each
3206 * interface is passed in link_info.
3207 */
3208static int setup_nic_devices(struct octeon_device *octeon_dev)
3209{
3210 struct lio *lio = NULL;
3211 struct net_device *netdev;
3212 u8 mac[6], i, j;
3213 struct octeon_soft_command *sc;
3214 struct liquidio_if_cfg_context *ctx;
3215 struct liquidio_if_cfg_resp *resp;
3216 struct octdev_props *props;
26236fa9 3217 int retval, num_iqueues, num_oqueues;
f21fb3ed
RV		 3218 u64 q_mask;
3219 int num_cpus = num_online_cpus();
3220 union oct_nic_if_cfg if_cfg;
3221 unsigned int base_queue;
3222 unsigned int gmx_port_id;
3223 u32 resp_size, ctx_size;
3224
3225 /* This is to handle link status changes */
3226 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3227 OPCODE_NIC_INFO,
3228 lio_nic_info, octeon_dev);
3229
3230 /* REQTYPE_RESP_NET and REQTYPE_SOFT_COMMAND do not have free functions.
3231 * They are handled directly.
3232 */
3233 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET,
3234 free_netbuf);
3235
3236 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET_SG,
3237 free_netsgbuf);
3238
3239 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_RESP_NET_SG,
3240 free_netsgbuf_with_resp);
3241
3242 for (i = 0; i < octeon_dev->ifcount; i++) {
3243 resp_size = sizeof(struct liquidio_if_cfg_resp);
3244 ctx_size = sizeof(struct liquidio_if_cfg_context);
3245 sc = (struct octeon_soft_command *)
3246 octeon_alloc_soft_command(octeon_dev, 0,
3247 resp_size, ctx_size);
3248 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
3249 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
3250
3251 num_iqueues =
3252 CFG_GET_NUM_TXQS_NIC_IF(octeon_get_conf(octeon_dev), i);
3253 num_oqueues =
3254 CFG_GET_NUM_RXQS_NIC_IF(octeon_get_conf(octeon_dev), i);
3255 base_queue =
3256 CFG_GET_BASE_QUE_NIC_IF(octeon_get_conf(octeon_dev), i);
3257 gmx_port_id =
3258 CFG_GET_GMXID_NIC_IF(octeon_get_conf(octeon_dev), i);
3259 if (num_iqueues > num_cpus)
3260 num_iqueues = num_cpus;
3261 if (num_oqueues > num_cpus)
3262 num_oqueues = num_cpus;
3263 dev_dbg(&octeon_dev->pci_dev->dev,
3264 "requesting config for interface %d, iqs %d, oqs %d\n",
3265 i, num_iqueues, num_oqueues);
3266 ACCESS_ONCE(ctx->cond) = 0;
3267 ctx->octeon_id = lio_get_device_id(octeon_dev);
3268 init_waitqueue_head(&ctx->wc);
3269
3270 if_cfg.u64 = 0;
3271 if_cfg.s.num_iqueues = num_iqueues;
3272 if_cfg.s.num_oqueues = num_oqueues;
3273 if_cfg.s.base_queue = base_queue;
3274 if_cfg.s.gmx_port_id = gmx_port_id;
3275 octeon_prepare_soft_command(octeon_dev, sc, OPCODE_NIC,
3276 OPCODE_NIC_IF_CFG, i,
3277 if_cfg.u64, 0);
3278
3279 sc->callback = if_cfg_callback;
3280 sc->callback_arg = sc;
3281 sc->wait_time = 1000;
3282
3283 retval = octeon_send_soft_command(octeon_dev, sc);
ddc173a6 3284 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 3285 dev_err(&octeon_dev->pci_dev->dev,
3286 "iq/oq config failed status: %x\n",
3287 retval);
3288 /* Soft instr is freed by driver in case of failure. */
3289 goto setup_nic_dev_fail;
3290 }
3291
3292 /* Sleep on a wait queue till the cond flag indicates that the
3293 * response arrived or timed-out.
3294 */
3295 sleep_cond(&ctx->wc, &ctx->cond);
3296 retval = resp->status;
3297 if (retval) {
3298 dev_err(&octeon_dev->pci_dev->dev, "iq/oq config failed\n");
3299 goto setup_nic_dev_fail;
3300 }
3301
3302 octeon_swap_8B_data((u64 *)(&resp->cfg_info),
3303 (sizeof(struct liquidio_if_cfg_info)) >> 3);
3304
3305 num_iqueues = hweight64(resp->cfg_info.iqmask);
3306 num_oqueues = hweight64(resp->cfg_info.oqmask);
3307
3308 if (!(num_iqueues) || !(num_oqueues)) {
3309 dev_err(&octeon_dev->pci_dev->dev,
3310 "Got bad iqueues (%016llx) or oqueues (%016llx) from firmware.\n",
3311 resp->cfg_info.iqmask,
3312 resp->cfg_info.oqmask);
3313 goto setup_nic_dev_fail;
3314 }
3315 dev_dbg(&octeon_dev->pci_dev->dev,
3316 "interface %d, iqmask %016llx, oqmask %016llx, numiqueues %d, numoqueues %d\n",
3317 i, resp->cfg_info.iqmask, resp->cfg_info.oqmask,
3318 num_iqueues, num_oqueues);
3319 netdev = alloc_etherdev_mq(LIO_SIZE, num_iqueues);
3320
3321 if (!netdev) {
3322 dev_err(&octeon_dev->pci_dev->dev, "Device allocation failed\n");
3323 goto setup_nic_dev_fail;
3324 }
3325
3326 props = &octeon_dev->props[i];
3327 props->netdev = netdev;
3328
3329 if (num_iqueues > 1)
3330 lionetdevops.ndo_select_queue = select_q;
3331
3332 /* Associate the routines that will handle different
3333 * netdev tasks.
3334 */
3335 netdev->netdev_ops = &lionetdevops;
3336
3337 lio = GET_LIO(netdev);
3338
3339 memset(lio, 0, sizeof(struct lio));
3340
3341 lio->linfo.ifidx = resp->cfg_info.ifidx;
3342 lio->ifidx = resp->cfg_info.ifidx;
3343
3344 lio->linfo.num_rxpciq = num_oqueues;
3345 lio->linfo.num_txpciq = num_iqueues;
3346 q_mask = resp->cfg_info.oqmask;
3347 /* q_mask is 0-based and already verified mask is nonzero */
3348 for (j = 0; j < num_oqueues; j++) {
26236fa9
RV		 3349 lio->linfo.rxpciq[j].u64 =
3350 resp->cfg_info.linfo.rxpciq[j].u64;
f21fb3ed
RV		 3351 }
3352 q_mask = resp->cfg_info.iqmask;
3353 for (j = 0; j < num_iqueues; j++) {
26236fa9
RV		 3354 lio->linfo.txpciq[j].u64 =
3355 resp->cfg_info.linfo.txpciq[j].u64;
f21fb3ed
RV		 3356 }
3357 lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr;
3358 lio->linfo.gmxport = resp->cfg_info.linfo.gmxport;
3359 lio->linfo.link.u64 = resp->cfg_info.linfo.link.u64;
3360
3361 lio->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3362
3363 lio->dev_capability = NETIF_F_HIGHDMA
3364 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3365 | NETIF_F_SG | NETIF_F_RXCSUM
3366 | NETIF_F_TSO | NETIF_F_TSO6
3367 | NETIF_F_LRO;
3368 netif_set_gso_max_size(netdev, OCTNIC_GSO_MAX_SIZE);
3369
3370 netdev->features = lio->dev_capability;
3371 netdev->vlan_features = lio->dev_capability;
3372
3373 netdev->hw_features = lio->dev_capability;
3374
3375 /* Point to the properties for octeon device to which this
3376 * interface belongs.
3377 */
3378 lio->oct_dev = octeon_dev;
3379 lio->octprops = props;
3380 lio->netdev = netdev;
f21fb3ed
RV		 3381
3382 dev_dbg(&octeon_dev->pci_dev->dev,
3383 "if%d gmx: %d hw_addr: 0x%llx\n", i,
3384 lio->linfo.gmxport, CVM_CAST64(lio->linfo.hw_addr));
3385
3386 /* 64-bit swap required on LE machines */
3387 octeon_swap_8B_data(&lio->linfo.hw_addr, 1);
3388 for (j = 0; j < 6; j++)
3389 mac[j] = *((u8 *)(((u8 *)&lio->linfo.hw_addr) + 2 + j));
3390
3391 /* Copy MAC Address to OS network device structure */
3392
3393 ether_addr_copy(netdev->dev_addr, mac);
3394
26236fa9
RV		 3395 /* By default all interfaces on a single Octeon uses the same
3396 * tx and rx queues
3397 */
3398 lio->txq = lio->linfo.txpciq[0].s.q_no;
3399 lio->rxq = lio->linfo.rxpciq[0].s.q_no;
f21fb3ed
RV		 3400 if (setup_io_queues(octeon_dev, netdev)) {
3401 dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n");
3402 goto setup_nic_dev_fail;
3403 }
3404
3405 ifstate_set(lio, LIO_IFSTATE_DROQ_OPS);
3406
f21fb3ed
RV		 3407 lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq);
3408 lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq);
3409
fcd2b5e3 3410 if (setup_glists(octeon_dev, lio, num_iqueues)) {
f21fb3ed
RV		 3411 dev_err(&octeon_dev->pci_dev->dev,
3412 "Gather list allocation failed\n");
3413 goto setup_nic_dev_fail;
3414 }
3415
3416 /* Register ethtool support */
3417 liquidio_set_ethtool_ops(netdev);
3418
3419 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE);
3420
3421 if ((debug != -1) && (debug & NETIF_MSG_HW))
3422 liquidio_set_feature(netdev, OCTNET_CMD_VERBOSE_ENABLE);
3423
3424 /* Register the network device with the OS */
3425 if (register_netdev(netdev)) {
3426 dev_err(&octeon_dev->pci_dev->dev, "Device registration failed\n");
3427 goto setup_nic_dev_fail;
3428 }
3429
3430 dev_dbg(&octeon_dev->pci_dev->dev,
3431 "Setup NIC ifidx:%d mac:%02x%02x%02x%02x%02x%02x\n",
3432 i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
3433 netif_carrier_off(netdev);
3434
3435 if (lio->linfo.link.s.status) {
3436 netif_carrier_on(netdev);
3437 start_txq(netdev);
3438 } else {
3439 netif_carrier_off(netdev);
3440 }
3441
3442 ifstate_set(lio, LIO_IFSTATE_REGISTERED);
3443
3444 dev_dbg(&octeon_dev->pci_dev->dev,
3445 "NIC ifidx:%d Setup successful\n", i);
3446
3447 octeon_free_soft_command(octeon_dev, sc);
3448 }
3449
3450 return 0;
3451
3452setup_nic_dev_fail:
3453
3454 octeon_free_soft_command(octeon_dev, sc);
3455
3456 while (i--) {
3457 dev_err(&octeon_dev->pci_dev->dev,
3458 "NIC ifidx:%d Setup failed\n", i);
3459 liquidio_destroy_nic_device(octeon_dev, i);
3460 }
3461 return -ENODEV;
3462}
3463
3464/**
3465 * \brief initialize the NIC
3466 * @param oct octeon device
3467 *
3468 * This initialization routine is called once the Octeon device application is
3469 * up and running
3470 */
3471static int liquidio_init_nic_module(struct octeon_device *oct)
3472{
3473 struct oct_intrmod_cfg *intrmod_cfg;
3474 int retval = 0;
3475 int num_nic_ports = CFG_GET_NUM_NIC_PORTS(octeon_get_conf(oct));
3476
3477 dev_dbg(&oct->pci_dev->dev, "Initializing network interfaces\n");
3478
3479 /* only default iq and oq were initialized
3480 * initialize the rest as well
3481 */
3482 /* run port_config command for each port */
3483 oct->ifcount = num_nic_ports;
3484
3485 memset(oct->props, 0,
3486 sizeof(struct octdev_props) * num_nic_ports);
3487
3488 retval = setup_nic_devices(oct);
3489 if (retval) {
3490 dev_err(&oct->pci_dev->dev, "Setup NIC devices failed\n");
3491 goto octnet_init_failure;
3492 }
3493
3494 liquidio_ptp_init(oct);
3495
3496 /* Initialize interrupt moderation params */
3497 intrmod_cfg = &((struct octeon_device *)oct)->intrmod;
3498 intrmod_cfg->intrmod_enable = 1;
3499 intrmod_cfg->intrmod_check_intrvl = LIO_INTRMOD_CHECK_INTERVAL;
3500 intrmod_cfg->intrmod_maxpkt_ratethr = LIO_INTRMOD_MAXPKT_RATETHR;
3501 intrmod_cfg->intrmod_minpkt_ratethr = LIO_INTRMOD_MINPKT_RATETHR;
3502 intrmod_cfg->intrmod_maxcnt_trigger = LIO_INTRMOD_MAXCNT_TRIGGER;
3503 intrmod_cfg->intrmod_maxtmr_trigger = LIO_INTRMOD_MAXTMR_TRIGGER;
3504 intrmod_cfg->intrmod_mintmr_trigger = LIO_INTRMOD_MINTMR_TRIGGER;
3505 intrmod_cfg->intrmod_mincnt_trigger = LIO_INTRMOD_MINCNT_TRIGGER;
3506
3507 dev_dbg(&oct->pci_dev->dev, "Network interfaces ready\n");
3508
3509 return retval;
3510
3511octnet_init_failure:
3512
3513 oct->ifcount = 0;
3514
3515 return retval;
3516}
3517
3518/**
3519 * \brief starter callback that invokes the remaining initialization work after
3520 * the NIC is up and running.
3521 * @param octptr work struct work_struct
3522 */
3523static void nic_starter(struct work_struct *work)
3524{
3525 struct octeon_device *oct;
3526 struct cavium_wk *wk = (struct cavium_wk *)work;
3527
3528 oct = (struct octeon_device *)wk->ctxptr;
3529
3530 if (atomic_read(&oct->status) == OCT_DEV_RUNNING)
3531 return;
3532
3533 /* If the status of the device is CORE_OK, the core
3534 * application has reported its application type. Call
3535 * any registered handlers now and move to the RUNNING
3536 * state.
3537 */
3538 if (atomic_read(&oct->status) != OCT_DEV_CORE_OK) {
3539 schedule_delayed_work(&oct->nic_poll_work.work,
3540 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
3541 return;
3542 }
3543
3544 atomic_set(&oct->status, OCT_DEV_RUNNING);
3545
3546 if (oct->app_mode && oct->app_mode == CVM_DRV_NIC_APP) {
3547 dev_dbg(&oct->pci_dev->dev, "Starting NIC module\n");
3548
3549 if (liquidio_init_nic_module(oct))
3550 dev_err(&oct->pci_dev->dev, "NIC initialization failed\n");
3551 else
3552 handshake[oct->octeon_id].started_ok = 1;
3553 } else {
3554 dev_err(&oct->pci_dev->dev,
3555 "Unexpected application running on NIC (%d). Check firmware.\n",
3556 oct->app_mode);
3557 }
3558
3559 complete(&handshake[oct->octeon_id].started);
3560}
3561
3562/**
3563 * \brief Device initialization for each Octeon device that is probed
3564 * @param octeon_dev octeon device
3565 */
3566static int octeon_device_init(struct octeon_device *octeon_dev)
3567{
3568 int j, ret;
3569 struct octeon_device_priv *oct_priv =
3570 (struct octeon_device_priv *)octeon_dev->priv;
3571 atomic_set(&octeon_dev->status, OCT_DEV_BEGIN_STATE);
3572
3573 /* Enable access to the octeon device and make its DMA capability
3574 * known to the OS.
3575 */
3576 if (octeon_pci_os_setup(octeon_dev))
3577 return 1;
3578
3579 /* Identify the Octeon type and map the BAR address space. */
3580 if (octeon_chip_specific_setup(octeon_dev)) {
3581 dev_err(&octeon_dev->pci_dev->dev, "Chip specific setup failed\n");
3582 return 1;
3583 }
3584
3585 atomic_set(&octeon_dev->status, OCT_DEV_PCI_MAP_DONE);
3586
3587 octeon_dev->app_mode = CVM_DRV_INVALID_APP;
3588
3589 /* Do a soft reset of the Octeon device. */
3590 if (octeon_dev->fn_list.soft_reset(octeon_dev))
3591 return 1;
3592
3593 /* Initialize the dispatch mechanism used to push packets arriving on
3594 * Octeon Output queues.
3595 */
3596 if (octeon_init_dispatch_list(octeon_dev))
3597 return 1;
3598
3599 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3600 OPCODE_NIC_CORE_DRV_ACTIVE,
3601 octeon_core_drv_init,
3602 octeon_dev);
3603
3604 INIT_DELAYED_WORK(&octeon_dev->nic_poll_work.work, nic_starter);
3605 octeon_dev->nic_poll_work.ctxptr = (void *)octeon_dev;
3606 schedule_delayed_work(&octeon_dev->nic_poll_work.work,
3607 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
3608
3609 atomic_set(&octeon_dev->status, OCT_DEV_DISPATCH_INIT_DONE);
3610
3611 octeon_set_io_queues_off(octeon_dev);
3612
3613 /* Setup the data structures that manage this Octeon's Input queues. */
3614 if (octeon_setup_instr_queues(octeon_dev)) {
3615 dev_err(&octeon_dev->pci_dev->dev,
3616 "instruction queue initialization failed\n");
3617 /* On error, release any previously allocated queues */
3618 for (j = 0; j < octeon_dev->num_iqs; j++)
3619 octeon_delete_instr_queue(octeon_dev, j);
3620 return 1;
3621 }
3622 atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE);
3623
3624 /* Initialize soft command buffer pool
3625 */
3626 if (octeon_setup_sc_buffer_pool(octeon_dev)) {
3627 dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n");
3628 return 1;
3629 }
3630 atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
3631
3632 /* Initialize lists to manage the requests of different types that
3633 * arrive from user & kernel applications for this octeon device.
3634 */
3635 if (octeon_setup_response_list(octeon_dev)) {
3636 dev_err(&octeon_dev->pci_dev->dev, "Response list allocation failed\n");
3637 return 1;
3638 }
3639 atomic_set(&octeon_dev->status, OCT_DEV_RESP_LIST_INIT_DONE);
3640
3641 if (octeon_setup_output_queues(octeon_dev)) {
3642 dev_err(&octeon_dev->pci_dev->dev, "Output queue initialization failed\n");
3643 /* Release any previously allocated queues */
3644 for (j = 0; j < octeon_dev->num_oqs; j++)
3645 octeon_delete_droq(octeon_dev, j);
3646 }
3647
3648 atomic_set(&octeon_dev->status, OCT_DEV_DROQ_INIT_DONE);
3649
3650 /* The input and output queue registers were setup earlier (the queues
3651 * were not enabled). Any additional registers that need to be
3652 * programmed should be done now.
3653 */
3654 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
3655 if (ret) {
3656 dev_err(&octeon_dev->pci_dev->dev,
3657 "Failed to configure device registers\n");
3658 return ret;
3659 }
3660
3661 /* Initialize the tasklet that handles output queue packet processing.*/
3662 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing droq tasklet\n");
3663 tasklet_init(&oct_priv->droq_tasklet, octeon_droq_bh,
3664 (unsigned long)octeon_dev);
3665
3666 /* Setup the interrupt handler and record the INT SUM register address
3667 */
3668 octeon_setup_interrupt(octeon_dev);
3669
3670 /* Enable Octeon device interrupts */
3671 octeon_dev->fn_list.enable_interrupt(octeon_dev->chip);
3672
3673 /* Enable the input and output queues for this Octeon device */
3674 octeon_dev->fn_list.enable_io_queues(octeon_dev);
3675
3676 atomic_set(&octeon_dev->status, OCT_DEV_IO_QUEUES_DONE);
3677
3678 dev_dbg(&octeon_dev->pci_dev->dev, "Waiting for DDR initialization...\n");
3679
3680 if (ddr_timeout == 0) {
3681 dev_info(&octeon_dev->pci_dev->dev,
3682 "WAITING. Set ddr_timeout to non-zero value to proceed with initialization.\n");
3683 }
3684
3685 schedule_timeout_uninterruptible(HZ * LIO_RESET_SECS);
3686
3687 /* Wait for the octeon to initialize DDR after the soft-reset. */
3688 ret = octeon_wait_for_ddr_init(octeon_dev, &ddr_timeout);
3689 if (ret) {
3690 dev_err(&octeon_dev->pci_dev->dev,
3691 "DDR not initialized. Please confirm that board is configured to boot from Flash, ret: %d\n",
3692 ret);
3693 return 1;
3694 }
3695
3696 if (octeon_wait_for_bootloader(octeon_dev, 1000) != 0) {
3697 dev_err(&octeon_dev->pci_dev->dev, "Board not responding\n");
3698 return 1;
3699 }
3700
3701 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing consoles\n");
3702 ret = octeon_init_consoles(octeon_dev);
3703 if (ret) {
3704 dev_err(&octeon_dev->pci_dev->dev, "Could not access board consoles\n");
3705 return 1;
3706 }
3707 ret = octeon_add_console(octeon_dev, 0);
3708 if (ret) {
3709 dev_err(&octeon_dev->pci_dev->dev, "Could not access board console\n");
3710 return 1;
3711 }
3712
3713 atomic_set(&octeon_dev->status, OCT_DEV_CONSOLE_INIT_DONE);
3714
3715 dev_dbg(&octeon_dev->pci_dev->dev, "Loading firmware\n");
3716 ret = load_firmware(octeon_dev);
3717 if (ret) {
3718 dev_err(&octeon_dev->pci_dev->dev, "Could not load firmware to board\n");
3719 return 1;
3720 }
3721
3722 handshake[octeon_dev->octeon_id].init_ok = 1;
3723 complete(&handshake[octeon_dev->octeon_id].init);
3724
3725 atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK);
3726
3727 /* Send Credit for Octeon Output queues. Credits are always sent after
3728 * the output queue is enabled.
3729 */
3730 for (j = 0; j < octeon_dev->num_oqs; j++)
3731 writel(octeon_dev->droq[j]->max_count,
3732 octeon_dev->droq[j]->pkts_credit_reg);
3733
3734 /* Packets can start arriving on the output queues from this point. */
3735
3736 return 0;
3737}
3738
3739/**
3740 * \brief Exits the module
3741 */
3742static void __exit liquidio_exit(void)
3743{
3744 liquidio_deinit_pci();
3745
3746 pr_info("LiquidIO network module is now unloaded\n");
3747}
3748
3749module_init(liquidio_init);
3750module_exit(liquidio_exit);
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