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liquidio: Napi rx/tx traffic
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / cavium / liquidio / lio_main.c
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f21fb3ed
RV		 1/**********************************************************************
2* Author: Cavium, Inc.
3*
4* Contact: support@cavium.com
5* Please include "LiquidIO" in the subject.
6*
7* Copyright (c) 2003-2015 Cavium, Inc.
8*
9* This file is free software; you can redistribute it and/or modify
10* it under the terms of the GNU General Public License, Version 2, as
11* published by the Free Software Foundation.
12*
13* This file is distributed in the hope that it will be useful, but
14* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16* NONINFRINGEMENT. See the GNU General Public License for more
17* details.
18*
19* This file may also be available under a different license from Cavium.
20* Contact Cavium, Inc. for more information
21**********************************************************************/
22#include <linux/version.h>
23#include <linux/module.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/pci.h>
27#include <linux/pci_ids.h>
28#include <linux/ip.h>
5b173cf9 29#include <net/ip.h>
f21fb3ed
RV		 30#include <linux/ipv6.h>
31#include <linux/net_tstamp.h>
32#include <linux/if_vlan.h>
33#include <linux/firmware.h>
34#include <linux/ethtool.h>
35#include <linux/ptp_clock_kernel.h>
36#include <linux/types.h>
37#include <linux/list.h>
38#include <linux/workqueue.h>
39#include <linux/interrupt.h>
40#include "octeon_config.h"
41#include "liquidio_common.h"
42#include "octeon_droq.h"
43#include "octeon_iq.h"
44#include "response_manager.h"
45#include "octeon_device.h"
46#include "octeon_nic.h"
47#include "octeon_main.h"
48#include "octeon_network.h"
49#include "cn66xx_regs.h"
50#include "cn66xx_device.h"
51#include "cn68xx_regs.h"
52#include "cn68xx_device.h"
53#include "liquidio_image.h"
54
55MODULE_AUTHOR("Cavium Networks, <support@cavium.com>");
56MODULE_DESCRIPTION("Cavium LiquidIO Intelligent Server Adapter Driver");
57MODULE_LICENSE("GPL");
58MODULE_VERSION(LIQUIDIO_VERSION);
59MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210SV_NAME LIO_FW_NAME_SUFFIX);
60MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210NV_NAME LIO_FW_NAME_SUFFIX);
61MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_410NV_NAME LIO_FW_NAME_SUFFIX);
62
63static int ddr_timeout = 10000;
64module_param(ddr_timeout, int, 0644);
65MODULE_PARM_DESC(ddr_timeout,
66 "Number of milliseconds to wait for DDR initialization. 0 waits for ddr_timeout to be set to non-zero value before starting to check");
67
68static u32 console_bitmask;
69module_param(console_bitmask, int, 0644);
70MODULE_PARM_DESC(console_bitmask,
71 "Bitmask indicating which consoles have debug output redirected to syslog.");
72
73#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
74
75static int debug = -1;
76module_param(debug, int, 0644);
77MODULE_PARM_DESC(debug, "NETIF_MSG debug bits");
78
79static char fw_type[LIO_MAX_FW_TYPE_LEN];
80module_param_string(fw_type, fw_type, sizeof(fw_type), 0000);
81MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded. Default \"nic\"");
82
83static int conf_type;
84module_param(conf_type, int, 0);
85MODULE_PARM_DESC(conf_type, "select octeon configuration 0 default 1 ovs");
86
a5b37888
RV		 87static int ptp_enable = 1;
88
f21fb3ed
RV		 89/* Bit mask values for lio->ifstate */
90#define LIO_IFSTATE_DROQ_OPS 0x01
91#define LIO_IFSTATE_REGISTERED 0x02
92#define LIO_IFSTATE_RUNNING 0x04
93#define LIO_IFSTATE_RX_TIMESTAMP_ENABLED 0x08
94
95/* Polling interval for determining when NIC application is alive */
96#define LIQUIDIO_STARTER_POLL_INTERVAL_MS 100
97
98/* runtime link query interval */
99#define LIQUIDIO_LINK_QUERY_INTERVAL_MS 1000
100
101struct liquidio_if_cfg_context {
102 int octeon_id;
103
104 wait_queue_head_t wc;
105
106 int cond;
107};
108
109struct liquidio_if_cfg_resp {
110 u64 rh;
111 struct liquidio_if_cfg_info cfg_info;
112 u64 status;
113};
114
115struct oct_link_status_resp {
116 u64 rh;
117 struct oct_link_info link_info;
118 u64 status;
119};
120
121struct oct_timestamp_resp {
122 u64 rh;
123 u64 timestamp;
124 u64 status;
125};
126
127#define OCT_TIMESTAMP_RESP_SIZE (sizeof(struct oct_timestamp_resp))
128
129union tx_info {
130 u64 u64;
131 struct {
132#ifdef __BIG_ENDIAN_BITFIELD
133 u16 gso_size;
134 u16 gso_segs;
135 u32 reserved;
136#else
137 u32 reserved;
138 u16 gso_segs;
139 u16 gso_size;
140#endif
141 } s;
142};
143
144/** Octeon device properties to be used by the NIC module.
145 * Each octeon device in the system will be represented
146 * by this structure in the NIC module.
147 */
148
149#define OCTNIC_MAX_SG (MAX_SKB_FRAGS)
150
151#define OCTNIC_GSO_MAX_HEADER_SIZE 128
152#define OCTNIC_GSO_MAX_SIZE (GSO_MAX_SIZE - OCTNIC_GSO_MAX_HEADER_SIZE)
153
154/** Structure of a node in list of gather components maintained by
155 * NIC driver for each network device.
156 */
157struct octnic_gather {
158 /** List manipulation. Next and prev pointers. */
159 struct list_head list;
160
161 /** Size of the gather component at sg in bytes. */
162 int sg_size;
163
164 /** Number of bytes that sg was adjusted to make it 8B-aligned. */
165 int adjust;
166
167 /** Gather component that can accommodate max sized fragment list
168 * received from the IP layer.
169 */
170 struct octeon_sg_entry *sg;
fcd2b5e3
RV		 171
172 u64 sg_dma_ptr;
f21fb3ed
RV		 173};
174
175/** This structure is used by NIC driver to store information required
176 * to free the sk_buff when the packet has been fetched by Octeon.
177 * Bytes offset below assume worst-case of a 64-bit system.
178 */
179struct octnet_buf_free_info {
180 /** Bytes 1-8. Pointer to network device private structure. */
181 struct lio *lio;
182
183 /** Bytes 9-16. Pointer to sk_buff. */
184 struct sk_buff *skb;
185
186 /** Bytes 17-24. Pointer to gather list. */
187 struct octnic_gather *g;
188
189 /** Bytes 25-32. Physical address of skb->data or gather list. */
190 u64 dptr;
191
192 /** Bytes 33-47. Piggybacked soft command, if any */
193 struct octeon_soft_command *sc;
194};
195
196struct handshake {
197 struct completion init;
198 struct completion started;
199 struct pci_dev *pci_dev;
200 int init_ok;
201 int started_ok;
202};
203
204struct octeon_device_priv {
205 /** Tasklet structures for this device. */
206 struct tasklet_struct droq_tasklet;
207 unsigned long napi_mask;
208};
209
210static int octeon_device_init(struct octeon_device *);
211static void liquidio_remove(struct pci_dev *pdev);
212static int liquidio_probe(struct pci_dev *pdev,
213 const struct pci_device_id *ent);
214
215static struct handshake handshake[MAX_OCTEON_DEVICES];
216static struct completion first_stage;
217
5b173cf9 218static void octeon_droq_bh(unsigned long pdev)
f21fb3ed
RV		 219{
220 int q_no;
221 int reschedule = 0;
222 struct octeon_device *oct = (struct octeon_device *)pdev;
223 struct octeon_device_priv *oct_priv =
224 (struct octeon_device_priv *)oct->priv;
225
226 /* for (q_no = 0; q_no < oct->num_oqs; q_no++) { */
63da8404
RV		 227 for (q_no = 0; q_no < MAX_OCTEON_OUTPUT_QUEUES(oct); q_no++) {
228 if (!(oct->io_qmask.oq & (1ULL << q_no)))
f21fb3ed
RV		 229 continue;
230 reschedule |= octeon_droq_process_packets(oct, oct->droq[q_no],
231 MAX_PACKET_BUDGET);
232 }
233
234 if (reschedule)
235 tasklet_schedule(&oct_priv->droq_tasklet);
236}
237
5b173cf9 238static int lio_wait_for_oq_pkts(struct octeon_device *oct)
f21fb3ed
RV		 239{
240 struct octeon_device_priv *oct_priv =
241 (struct octeon_device_priv *)oct->priv;
242 int retry = 100, pkt_cnt = 0, pending_pkts = 0;
243 int i;
244
245 do {
246 pending_pkts = 0;
247
63da8404
RV		 248 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
249 if (!(oct->io_qmask.oq & (1ULL << i)))
f21fb3ed
RV		 250 continue;
251 pkt_cnt += octeon_droq_check_hw_for_pkts(oct,
252 oct->droq[i]);
253 }
254 if (pkt_cnt > 0) {
255 pending_pkts += pkt_cnt;
256 tasklet_schedule(&oct_priv->droq_tasklet);
257 }
258 pkt_cnt = 0;
259 schedule_timeout_uninterruptible(1);
260
261 } while (retry-- && pending_pkts);
262
263 return pkt_cnt;
264}
265
266void octeon_report_tx_completion_to_bql(void *txq, unsigned int pkts_compl,
267 unsigned int bytes_compl)
268{
269 struct netdev_queue *netdev_queue = txq;
270
271 netdev_tx_completed_queue(netdev_queue, pkts_compl, bytes_compl);
272}
273
274void octeon_update_tx_completion_counters(void *buf, int reqtype,
275 unsigned int *pkts_compl,
276 unsigned int *bytes_compl)
277{
278 struct octnet_buf_free_info *finfo;
279 struct sk_buff *skb = NULL;
280 struct octeon_soft_command *sc;
281
282 switch (reqtype) {
283 case REQTYPE_NORESP_NET:
284 case REQTYPE_NORESP_NET_SG:
285 finfo = buf;
286 skb = finfo->skb;
287 break;
288
289 case REQTYPE_RESP_NET_SG:
290 case REQTYPE_RESP_NET:
291 sc = buf;
292 skb = sc->callback_arg;
293 break;
294
295 default:
296 return;
297 }
298
299 (*pkts_compl)++;
300 *bytes_compl += skb->len;
301}
302
303void octeon_report_sent_bytes_to_bql(void *buf, int reqtype)
304{
305 struct octnet_buf_free_info *finfo;
306 struct sk_buff *skb;
307 struct octeon_soft_command *sc;
308 struct netdev_queue *txq;
309
310 switch (reqtype) {
311 case REQTYPE_NORESP_NET:
312 case REQTYPE_NORESP_NET_SG:
313 finfo = buf;
314 skb = finfo->skb;
315 break;
316
317 case REQTYPE_RESP_NET_SG:
318 case REQTYPE_RESP_NET:
319 sc = buf;
320 skb = sc->callback_arg;
321 break;
322
323 default:
324 return;
325 }
326
327 txq = netdev_get_tx_queue(skb->dev, skb_get_queue_mapping(skb));
328 netdev_tx_sent_queue(txq, skb->len);
329}
330
331int octeon_console_debug_enabled(u32 console)
332{
333 return (console_bitmask >> (console)) & 0x1;
334}
335
336/**
337 * \brief Forces all IO queues off on a given device
338 * @param oct Pointer to Octeon device
339 */
340static void force_io_queues_off(struct octeon_device *oct)
341{
342 if ((oct->chip_id == OCTEON_CN66XX) ||
343 (oct->chip_id == OCTEON_CN68XX)) {
344 /* Reset the Enable bits for Input Queues. */
345 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
346
347 /* Reset the Enable bits for Output Queues. */
348 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
349 }
350}
351
352/**
353 * \brief wait for all pending requests to complete
354 * @param oct Pointer to Octeon device
355 *
356 * Called during shutdown sequence
357 */
358static int wait_for_pending_requests(struct octeon_device *oct)
359{
360 int i, pcount = 0;
361
362 for (i = 0; i < 100; i++) {
363 pcount =
364 atomic_read(&oct->response_list
365 [OCTEON_ORDERED_SC_LIST].pending_req_count);
366 if (pcount)
367 schedule_timeout_uninterruptible(HZ / 10);
9a96bde4 368 else
f21fb3ed
RV		 369 break;
370 }
371
372 if (pcount)
373 return 1;
374
375 return 0;
376}
377
378/**
379 * \brief Cause device to go quiet so it can be safely removed/reset/etc
380 * @param oct Pointer to Octeon device
381 */
382static inline void pcierror_quiesce_device(struct octeon_device *oct)
383{
384 int i;
385
386 /* Disable the input and output queues now. No more packets will
387 * arrive from Octeon, but we should wait for all packet processing
388 * to finish.
389 */
390 force_io_queues_off(oct);
391
392 /* To allow for in-flight requests */
393 schedule_timeout_uninterruptible(100);
394
395 if (wait_for_pending_requests(oct))
396 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
397
398 /* Force all requests waiting to be fetched by OCTEON to complete. */
63da8404 399 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
f21fb3ed
RV		 400 struct octeon_instr_queue *iq;
401
63da8404 402 if (!(oct->io_qmask.iq & (1ULL << i)))
f21fb3ed
RV		 403 continue;
404 iq = oct->instr_queue[i];
405
406 if (atomic_read(&iq->instr_pending)) {
407 spin_lock_bh(&iq->lock);
408 iq->fill_cnt = 0;
409 iq->octeon_read_index = iq->host_write_index;
410 iq->stats.instr_processed +=
411 atomic_read(&iq->instr_pending);
9a96bde4 412 lio_process_iq_request_list(oct, iq, 0);
f21fb3ed
RV		 413 spin_unlock_bh(&iq->lock);
414 }
415 }
416
417 /* Force all pending ordered list requests to time out. */
418 lio_process_ordered_list(oct, 1);
419
420 /* We do not need to wait for output queue packets to be processed. */
421}
422
423/**
424 * \brief Cleanup PCI AER uncorrectable error status
425 * @param dev Pointer to PCI device
426 */
427static void cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
428{
429 int pos = 0x100;
430 u32 status, mask;
431
432 pr_info("%s :\n", __func__);
433
434 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
435 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
436 if (dev->error_state == pci_channel_io_normal)
437 status &= ~mask; /* Clear corresponding nonfatal bits */
438 else
439 status &= mask; /* Clear corresponding fatal bits */
440 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
441}
442
443/**
444 * \brief Stop all PCI IO to a given device
445 * @param dev Pointer to Octeon device
446 */
447static void stop_pci_io(struct octeon_device *oct)
448{
449 /* No more instructions will be forwarded. */
450 atomic_set(&oct->status, OCT_DEV_IN_RESET);
451
452 pci_disable_device(oct->pci_dev);
453
454 /* Disable interrupts */
455 oct->fn_list.disable_interrupt(oct->chip);
456
457 pcierror_quiesce_device(oct);
458
459 /* Release the interrupt line */
460 free_irq(oct->pci_dev->irq, oct);
461
462 if (oct->flags & LIO_FLAG_MSI_ENABLED)
463 pci_disable_msi(oct->pci_dev);
464
465 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
466 lio_get_state_string(&oct->status));
467
468 /* cn63xx_cleanup_aer_uncorrect_error_status(oct->pci_dev); */
469 /* making it a common function for all OCTEON models */
470 cleanup_aer_uncorrect_error_status(oct->pci_dev);
471}
472
473/**
474 * \brief called when PCI error is detected
475 * @param pdev Pointer to PCI device
476 * @param state The current pci connection state
477 *
478 * This function is called after a PCI bus error affecting
479 * this device has been detected.
480 */
481static pci_ers_result_t liquidio_pcie_error_detected(struct pci_dev *pdev,
482 pci_channel_state_t state)
483{
484 struct octeon_device *oct = pci_get_drvdata(pdev);
485
486 /* Non-correctable Non-fatal errors */
487 if (state == pci_channel_io_normal) {
488 dev_err(&oct->pci_dev->dev, "Non-correctable non-fatal error reported:\n");
489 cleanup_aer_uncorrect_error_status(oct->pci_dev);
490 return PCI_ERS_RESULT_CAN_RECOVER;
491 }
492
493 /* Non-correctable Fatal errors */
494 dev_err(&oct->pci_dev->dev, "Non-correctable FATAL reported by PCI AER driver\n");
495 stop_pci_io(oct);
496
497 /* Always return a DISCONNECT. There is no support for recovery but only
498 * for a clean shutdown.
499 */
500 return PCI_ERS_RESULT_DISCONNECT;
501}
502
503/**
504 * \brief mmio handler
505 * @param pdev Pointer to PCI device
506 */
507static pci_ers_result_t liquidio_pcie_mmio_enabled(struct pci_dev *pdev)
508{
509 /* We should never hit this since we never ask for a reset for a Fatal
510 * Error. We always return DISCONNECT in io_error above.
511 * But play safe and return RECOVERED for now.
512 */
513 return PCI_ERS_RESULT_RECOVERED;
514}
515
516/**
517 * \brief called after the pci bus has been reset.
518 * @param pdev Pointer to PCI device
519 *
520 * Restart the card from scratch, as if from a cold-boot. Implementation
521 * resembles the first-half of the octeon_resume routine.
522 */
523static pci_ers_result_t liquidio_pcie_slot_reset(struct pci_dev *pdev)
524{
525 /* We should never hit this since we never ask for a reset for a Fatal
526 * Error. We always return DISCONNECT in io_error above.
527 * But play safe and return RECOVERED for now.
528 */
529 return PCI_ERS_RESULT_RECOVERED;
530}
531
532/**
533 * \brief called when traffic can start flowing again.
534 * @param pdev Pointer to PCI device
535 *
536 * This callback is called when the error recovery driver tells us that
537 * its OK to resume normal operation. Implementation resembles the
538 * second-half of the octeon_resume routine.
539 */
540static void liquidio_pcie_resume(struct pci_dev *pdev)
541{
542 /* Nothing to be done here. */
543}
544
545#ifdef CONFIG_PM
546/**
547 * \brief called when suspending
548 * @param pdev Pointer to PCI device
549 * @param state state to suspend to
550 */
551static int liquidio_suspend(struct pci_dev *pdev, pm_message_t state)
552{
553 return 0;
554}
555
556/**
557 * \brief called when resuming
558 * @param pdev Pointer to PCI device
559 */
560static int liquidio_resume(struct pci_dev *pdev)
561{
562 return 0;
563}
564#endif
565
566/* For PCI-E Advanced Error Recovery (AER) Interface */
166e2362 567static const struct pci_error_handlers liquidio_err_handler = {
f21fb3ed
RV		 568 .error_detected = liquidio_pcie_error_detected,
569 .mmio_enabled = liquidio_pcie_mmio_enabled,
570 .slot_reset = liquidio_pcie_slot_reset,
571 .resume = liquidio_pcie_resume,
572};
573
574static const struct pci_device_id liquidio_pci_tbl[] = {
575 { /* 68xx */
576 PCI_VENDOR_ID_CAVIUM, 0x91, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
577 },
578 { /* 66xx */
579 PCI_VENDOR_ID_CAVIUM, 0x92, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
580 },
581 {
582 0, 0, 0, 0, 0, 0, 0
583 }
584};
585MODULE_DEVICE_TABLE(pci, liquidio_pci_tbl);
586
587static struct pci_driver liquidio_pci_driver = {
588 .name = "LiquidIO",
589 .id_table = liquidio_pci_tbl,
590 .probe = liquidio_probe,
591 .remove = liquidio_remove,
592 .err_handler = &liquidio_err_handler, /* For AER */
593
594#ifdef CONFIG_PM
595 .suspend = liquidio_suspend,
596 .resume = liquidio_resume,
597#endif
598
599};
600
601/**
602 * \brief register PCI driver
603 */
604static int liquidio_init_pci(void)
605{
606 return pci_register_driver(&liquidio_pci_driver);
607}
608
609/**
610 * \brief unregister PCI driver
611 */
612static void liquidio_deinit_pci(void)
613{
614 pci_unregister_driver(&liquidio_pci_driver);
615}
616
617/**
618 * \brief check interface state
619 * @param lio per-network private data
620 * @param state_flag flag state to check
621 */
622static inline int ifstate_check(struct lio *lio, int state_flag)
623{
624 return atomic_read(&lio->ifstate) & state_flag;
625}
626
627/**
628 * \brief set interface state
629 * @param lio per-network private data
630 * @param state_flag flag state to set
631 */
632static inline void ifstate_set(struct lio *lio, int state_flag)
633{
634 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) | state_flag));
635}
636
637/**
638 * \brief clear interface state
639 * @param lio per-network private data
640 * @param state_flag flag state to clear
641 */
642static inline void ifstate_reset(struct lio *lio, int state_flag)
643{
644 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) & ~(state_flag)));
645}
646
647/**
648 * \brief Stop Tx queues
649 * @param netdev network device
650 */
651static inline void txqs_stop(struct net_device *netdev)
652{
653 if (netif_is_multiqueue(netdev)) {
654 int i;
655
656 for (i = 0; i < netdev->num_tx_queues; i++)
657 netif_stop_subqueue(netdev, i);
658 } else {
659 netif_stop_queue(netdev);
660 }
661}
662
663/**
664 * \brief Start Tx queues
665 * @param netdev network device
666 */
667static inline void txqs_start(struct net_device *netdev)
668{
669 if (netif_is_multiqueue(netdev)) {
670 int i;
671
672 for (i = 0; i < netdev->num_tx_queues; i++)
673 netif_start_subqueue(netdev, i);
674 } else {
675 netif_start_queue(netdev);
676 }
677}
678
679/**
680 * \brief Wake Tx queues
681 * @param netdev network device
682 */
683static inline void txqs_wake(struct net_device *netdev)
684{
685 if (netif_is_multiqueue(netdev)) {
686 int i;
687
688 for (i = 0; i < netdev->num_tx_queues; i++)
26236fa9
RV		 689 if (__netif_subqueue_stopped(netdev, i))
690 netif_wake_subqueue(netdev, i);
f21fb3ed
RV		 691 } else {
692 netif_wake_queue(netdev);
693 }
694}
695
696/**
697 * \brief Stop Tx queue
698 * @param netdev network device
699 */
700static void stop_txq(struct net_device *netdev)
701{
702 txqs_stop(netdev);
703}
704
705/**
706 * \brief Start Tx queue
707 * @param netdev network device
708 */
709static void start_txq(struct net_device *netdev)
710{
711 struct lio *lio = GET_LIO(netdev);
712
0cece6c5 713 if (lio->linfo.link.s.link_up) {
f21fb3ed
RV		 714 txqs_start(netdev);
715 return;
716 }
717}
718
719/**
720 * \brief Wake a queue
721 * @param netdev network device
722 * @param q which queue to wake
723 */
724static inline void wake_q(struct net_device *netdev, int q)
725{
726 if (netif_is_multiqueue(netdev))
727 netif_wake_subqueue(netdev, q);
728 else
729 netif_wake_queue(netdev);
730}
731
732/**
733 * \brief Stop a queue
734 * @param netdev network device
735 * @param q which queue to stop
736 */
737static inline void stop_q(struct net_device *netdev, int q)
738{
739 if (netif_is_multiqueue(netdev))
740 netif_stop_subqueue(netdev, q);
741 else
742 netif_stop_queue(netdev);
743}
744
745/**
746 * \brief Check Tx queue status, and take appropriate action
747 * @param lio per-network private data
748 * @returns 0 if full, number of queues woken up otherwise
749 */
750static inline int check_txq_status(struct lio *lio)
751{
752 int ret_val = 0;
753
754 if (netif_is_multiqueue(lio->netdev)) {
755 int numqs = lio->netdev->num_tx_queues;
756 int q, iq = 0;
757
758 /* check each sub-queue state */
759 for (q = 0; q < numqs; q++) {
26236fa9
RV		 760 iq = lio->linfo.txpciq[q %
761 (lio->linfo.num_txpciq)].s.q_no;
f21fb3ed
RV		 762 if (octnet_iq_is_full(lio->oct_dev, iq))
763 continue;
26236fa9
RV		 764 if (__netif_subqueue_stopped(lio->netdev, q)) {
765 wake_q(lio->netdev, q);
766 ret_val++;
767 }
f21fb3ed
RV		 768 }
769 } else {
770 if (octnet_iq_is_full(lio->oct_dev, lio->txq))
771 return 0;
772 wake_q(lio->netdev, lio->txq);
773 ret_val = 1;
774 }
775 return ret_val;
776}
777
778/**
779 * Remove the node at the head of the list. The list would be empty at
780 * the end of this call if there are no more nodes in the list.
781 */
782static inline struct list_head *list_delete_head(struct list_head *root)
783{
784 struct list_head *node;
785
786 if ((root->prev == root) && (root->next == root))
787 node = NULL;
788 else
789 node = root->next;
790
791 if (node)
792 list_del(node);
793
794 return node;
795}
796
797/**
fcd2b5e3 798 * \brief Delete gather lists
f21fb3ed
RV		 799 * @param lio per-network private data
800 */
fcd2b5e3 801static void delete_glists(struct lio *lio)
f21fb3ed
RV		 802{
803 struct octnic_gather *g;
fcd2b5e3 804 int i;
f21fb3ed 805
fcd2b5e3
RV		 806 if (!lio->glist)
807 return;
808
809 for (i = 0; i < lio->linfo.num_txpciq; i++) {
810 do {
811 g = (struct octnic_gather *)
812 list_delete_head(&lio->glist[i]);
813 if (g) {
814 if (g->sg) {
815 dma_unmap_single(&lio->oct_dev->
816 pci_dev->dev,
817 g->sg_dma_ptr,
818 g->sg_size,
819 DMA_TO_DEVICE);
820 kfree((void *)((unsigned long)g->sg -
821 g->adjust));
822 }
823 kfree(g);
824 }
825 } while (g);
826 }
827
828 kfree((void *)lio->glist);
f21fb3ed
RV		 829}
830
831/**
fcd2b5e3 832 * \brief Setup gather lists
f21fb3ed
RV		 833 * @param lio per-network private data
834 */
fcd2b5e3 835static int setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs)
f21fb3ed 836{
fcd2b5e3 837 int i, j;
f21fb3ed
RV		 838 struct octnic_gather *g;
839
fcd2b5e3
RV		 840 lio->glist_lock = kcalloc(num_iqs, sizeof(*lio->glist_lock),
841 GFP_KERNEL);
842 if (!lio->glist_lock)
843 return 1;
f21fb3ed 844
fcd2b5e3
RV		 845 lio->glist = kcalloc(num_iqs, sizeof(*lio->glist),
846 GFP_KERNEL);
847 if (!lio->glist) {
848 kfree((void *)lio->glist_lock);
849 return 1;
850 }
f21fb3ed 851
fcd2b5e3
RV		 852 for (i = 0; i < num_iqs; i++) {
853 int numa_node = cpu_to_node(i % num_online_cpus());
f21fb3ed 854
fcd2b5e3
RV		 855 spin_lock_init(&lio->glist_lock[i]);
856
857 INIT_LIST_HEAD(&lio->glist[i]);
858
859 for (j = 0; j < lio->tx_qsize; j++) {
860 g = kzalloc_node(sizeof(*g), GFP_KERNEL,
861 numa_node);
862 if (!g)
863 g = kzalloc(sizeof(*g), GFP_KERNEL);
864 if (!g)
865 break;
866
867 g->sg_size = ((ROUNDUP4(OCTNIC_MAX_SG) >> 2) *
868 OCT_SG_ENTRY_SIZE);
869
870 g->sg = kmalloc_node(g->sg_size + 8,
871 GFP_KERNEL, numa_node);
872 if (!g->sg)
873 g->sg = kmalloc(g->sg_size + 8, GFP_KERNEL);
874 if (!g->sg) {
875 kfree(g);
876 break;
877 }
878
879 /* The gather component should be aligned on 64-bit
880 * boundary
881 */
882 if (((unsigned long)g->sg) & 7) {
883 g->adjust = 8 - (((unsigned long)g->sg) & 7);
884 g->sg = (struct octeon_sg_entry *)
885 ((unsigned long)g->sg + g->adjust);
886 }
887 g->sg_dma_ptr = dma_map_single(&oct->pci_dev->dev,
888 g->sg, g->sg_size,
889 DMA_TO_DEVICE);
890 if (dma_mapping_error(&oct->pci_dev->dev,
891 g->sg_dma_ptr)) {
892 kfree((void *)((unsigned long)g->sg -
893 g->adjust));
894 kfree(g);
895 break;
896 }
897
898 list_add_tail(&g->list, &lio->glist[i]);
f21fb3ed
RV		 899 }
900
fcd2b5e3
RV		 901 if (j != lio->tx_qsize) {
902 delete_glists(lio);
903 return 1;
f21fb3ed 904 }
f21fb3ed
RV		 905 }
906
fcd2b5e3 907 return 0;
f21fb3ed
RV		 908}
909
910/**
911 * \brief Print link information
912 * @param netdev network device
913 */
914static void print_link_info(struct net_device *netdev)
915{
916 struct lio *lio = GET_LIO(netdev);
917
918 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED) {
919 struct oct_link_info *linfo = &lio->linfo;
920
0cece6c5 921 if (linfo->link.s.link_up) {
f21fb3ed
RV		 922 netif_info(lio, link, lio->netdev, "%d Mbps %s Duplex UP\n",
923 linfo->link.s.speed,
924 (linfo->link.s.duplex) ? "Full" : "Half");
925 } else {
926 netif_info(lio, link, lio->netdev, "Link Down\n");
927 }
928 }
929}
930
931/**
932 * \brief Update link status
933 * @param netdev network device
934 * @param ls link status structure
935 *
936 * Called on receipt of a link status response from the core application to
937 * update each interface's link status.
938 */
939static inline void update_link_status(struct net_device *netdev,
940 union oct_link_status *ls)
941{
942 struct lio *lio = GET_LIO(netdev);
0cece6c5 943 int changed = (lio->linfo.link.u64 != ls->u64);
f21fb3ed 944
0cece6c5 945 lio->linfo.link.u64 = ls->u64;
f21fb3ed 946
0cece6c5 947 if ((lio->intf_open) && (changed)) {
f21fb3ed 948 print_link_info(netdev);
0cece6c5 949 lio->link_changes++;
f21fb3ed 950
0cece6c5 951 if (lio->linfo.link.s.link_up) {
f21fb3ed
RV		 952 netif_carrier_on(netdev);
953 /* start_txq(netdev); */
954 txqs_wake(netdev);
955 } else {
956 netif_carrier_off(netdev);
957 stop_txq(netdev);
958 }
959 }
960}
961
9a96bde4
RV		 962/* Runs in interrupt context. */
963static void update_txq_status(struct octeon_device *oct, int iq_num)
964{
965 struct net_device *netdev;
966 struct lio *lio;
967 struct octeon_instr_queue *iq = oct->instr_queue[iq_num];
968
969 /*octeon_update_iq_read_idx(oct, iq);*/
970
971 netdev = oct->props[iq->ifidx].netdev;
972
973 /* This is needed because the first IQ does not have
974 * a netdev associated with it.
975 */
976 if (!netdev)
977 return;
978
979 lio = GET_LIO(netdev);
980 if (netif_is_multiqueue(netdev)) {
981 if (__netif_subqueue_stopped(netdev, iq->q_index) &&
982 lio->linfo.link.s.link_up &&
983 (!octnet_iq_is_full(oct, iq_num))) {
984 netif_wake_subqueue(netdev, iq->q_index);
985 } else {
986 if (!octnet_iq_is_full(oct, lio->txq))
987 wake_q(netdev, lio->txq);
988 }
989 }
990}
991
f21fb3ed
RV		 992/**
993 * \brief Droq packet processor sceduler
994 * @param oct octeon device
995 */
996static
997void liquidio_schedule_droq_pkt_handlers(struct octeon_device *oct)
998{
999 struct octeon_device_priv *oct_priv =
1000 (struct octeon_device_priv *)oct->priv;
1001 u64 oq_no;
1002 struct octeon_droq *droq;
1003
1004 if (oct->int_status & OCT_DEV_INTR_PKT_DATA) {
63da8404
RV		 1005 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct);
1006 oq_no++) {
1007 if (!(oct->droq_intr & (1ULL << oq_no)))
f21fb3ed
RV		 1008 continue;
1009
1010 droq = oct->droq[oq_no];
1011
1012 if (droq->ops.poll_mode) {
1013 droq->ops.napi_fn(droq);
1014 oct_priv->napi_mask |= (1 << oq_no);
1015 } else {
1016 tasklet_schedule(&oct_priv->droq_tasklet);
1017 }
1018 }
1019 }
1020}
1021
1022/**
1023 * \brief Interrupt handler for octeon
1024 * @param irq unused
1025 * @param dev octeon device
1026 */
1027static
1028irqreturn_t liquidio_intr_handler(int irq __attribute__((unused)), void *dev)
1029{
1030 struct octeon_device *oct = (struct octeon_device *)dev;
1031 irqreturn_t ret;
1032
1033 /* Disable our interrupts for the duration of ISR */
1034 oct->fn_list.disable_interrupt(oct->chip);
1035
1036 ret = oct->fn_list.process_interrupt_regs(oct);
1037
1038 if (ret == IRQ_HANDLED)
1039 liquidio_schedule_droq_pkt_handlers(oct);
1040
1041 /* Re-enable our interrupts */
1042 if (!(atomic_read(&oct->status) == OCT_DEV_IN_RESET))
1043 oct->fn_list.enable_interrupt(oct->chip);
1044
1045 return ret;
1046}
1047
1048/**
1049 * \brief Setup interrupt for octeon device
1050 * @param oct octeon device
1051 *
1052 * Enable interrupt in Octeon device as given in the PCI interrupt mask.
1053 */
1054static int octeon_setup_interrupt(struct octeon_device *oct)
1055{
1056 int irqret, err;
1057
1058 err = pci_enable_msi(oct->pci_dev);
1059 if (err)
1060 dev_warn(&oct->pci_dev->dev, "Reverting to legacy interrupts. Error: %d\n",
1061 err);
1062 else
1063 oct->flags |= LIO_FLAG_MSI_ENABLED;
1064
1065 irqret = request_irq(oct->pci_dev->irq, liquidio_intr_handler,
1066 IRQF_SHARED, "octeon", oct);
1067 if (irqret) {
1068 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1069 pci_disable_msi(oct->pci_dev);
1070 dev_err(&oct->pci_dev->dev, "Request IRQ failed with code: %d\n",
1071 irqret);
1072 return 1;
1073 }
1074
1075 return 0;
1076}
1077
1078/**
1079 * \brief PCI probe handler
1080 * @param pdev PCI device structure
1081 * @param ent unused
1082 */
1083static int liquidio_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1084{
1085 struct octeon_device *oct_dev = NULL;
1086 struct handshake *hs;
1087
1088 oct_dev = octeon_allocate_device(pdev->device,
1089 sizeof(struct octeon_device_priv));
1090 if (!oct_dev) {
1091 dev_err(&pdev->dev, "Unable to allocate device\n");
1092 return -ENOMEM;
1093 }
1094
1095 dev_info(&pdev->dev, "Initializing device %x:%x.\n",
1096 (u32)pdev->vendor, (u32)pdev->device);
1097
1098 /* Assign octeon_device for this device to the private data area. */
1099 pci_set_drvdata(pdev, oct_dev);
1100
1101 /* set linux specific device pointer */
1102 oct_dev->pci_dev = (void *)pdev;
1103
1104 hs = &handshake[oct_dev->octeon_id];
1105 init_completion(&hs->init);
1106 init_completion(&hs->started);
1107 hs->pci_dev = pdev;
1108
1109 if (oct_dev->octeon_id == 0)
1110 /* first LiquidIO NIC is detected */
1111 complete(&first_stage);
1112
1113 if (octeon_device_init(oct_dev)) {
1114 liquidio_remove(pdev);
1115 return -ENOMEM;
1116 }
1117
1118 dev_dbg(&oct_dev->pci_dev->dev, "Device is ready\n");
1119
1120 return 0;
1121}
1122
1123/**
1124 *\brief Destroy resources associated with octeon device
1125 * @param pdev PCI device structure
1126 * @param ent unused
1127 */
1128static void octeon_destroy_resources(struct octeon_device *oct)
1129{
1130 int i;
1131 struct octeon_device_priv *oct_priv =
1132 (struct octeon_device_priv *)oct->priv;
1133
1134 struct handshake *hs;
1135
1136 switch (atomic_read(&oct->status)) {
1137 case OCT_DEV_RUNNING:
1138 case OCT_DEV_CORE_OK:
1139
1140 /* No more instructions will be forwarded. */
1141 atomic_set(&oct->status, OCT_DEV_IN_RESET);
1142
1143 oct->app_mode = CVM_DRV_INVALID_APP;
1144 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
1145 lio_get_state_string(&oct->status));
1146
1147 schedule_timeout_uninterruptible(HZ / 10);
1148
1149 /* fallthrough */
1150 case OCT_DEV_HOST_OK:
1151
1152 /* fallthrough */
1153 case OCT_DEV_CONSOLE_INIT_DONE:
1154 /* Remove any consoles */
1155 octeon_remove_consoles(oct);
1156
1157 /* fallthrough */
1158 case OCT_DEV_IO_QUEUES_DONE:
1159 if (wait_for_pending_requests(oct))
1160 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
1161
1162 if (lio_wait_for_instr_fetch(oct))
1163 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n");
1164
1165 /* Disable the input and output queues now. No more packets will
1166 * arrive from Octeon, but we should wait for all packet
1167 * processing to finish.
1168 */
1169 oct->fn_list.disable_io_queues(oct);
1170
1171 if (lio_wait_for_oq_pkts(oct))
1172 dev_err(&oct->pci_dev->dev, "OQ had pending packets\n");
1173
1174 /* Disable interrupts */
1175 oct->fn_list.disable_interrupt(oct->chip);
1176
1177 /* Release the interrupt line */
1178 free_irq(oct->pci_dev->irq, oct);
1179
1180 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1181 pci_disable_msi(oct->pci_dev);
1182
1183 /* Soft reset the octeon device before exiting */
1184 oct->fn_list.soft_reset(oct);
1185
1186 /* Disable the device, releasing the PCI INT */
1187 pci_disable_device(oct->pci_dev);
1188
1189 /* fallthrough */
1190 case OCT_DEV_IN_RESET:
1191 case OCT_DEV_DROQ_INIT_DONE:
1192 /*atomic_set(&oct->status, OCT_DEV_DROQ_INIT_DONE);*/
1193 mdelay(100);
63da8404
RV		 1194 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
1195 if (!(oct->io_qmask.oq & (1ULL << i)))
f21fb3ed
RV		 1196 continue;
1197 octeon_delete_droq(oct, i);
1198 }
1199
1200 /* Force any pending handshakes to complete */
1201 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
1202 hs = &handshake[i];
1203
1204 if (hs->pci_dev) {
1205 handshake[oct->octeon_id].init_ok = 0;
1206 complete(&handshake[oct->octeon_id].init);
1207 handshake[oct->octeon_id].started_ok = 0;
1208 complete(&handshake[oct->octeon_id].started);
1209 }
1210 }
1211
1212 /* fallthrough */
1213 case OCT_DEV_RESP_LIST_INIT_DONE:
1214 octeon_delete_response_list(oct);
1215
1216 /* fallthrough */
1217 case OCT_DEV_SC_BUFF_POOL_INIT_DONE:
1218 octeon_free_sc_buffer_pool(oct);
1219
1220 /* fallthrough */
1221 case OCT_DEV_INSTR_QUEUE_INIT_DONE:
63da8404
RV		 1222 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
1223 if (!(oct->io_qmask.iq & (1ULL << i)))
f21fb3ed
RV		 1224 continue;
1225 octeon_delete_instr_queue(oct, i);
1226 }
1227
1228 /* fallthrough */
1229 case OCT_DEV_DISPATCH_INIT_DONE:
1230 octeon_delete_dispatch_list(oct);
1231 cancel_delayed_work_sync(&oct->nic_poll_work.work);
1232
1233 /* fallthrough */
1234 case OCT_DEV_PCI_MAP_DONE:
1235 octeon_unmap_pci_barx(oct, 0);
1236 octeon_unmap_pci_barx(oct, 1);
1237
1238 /* fallthrough */
1239 case OCT_DEV_BEGIN_STATE:
1240 /* Nothing to be done here either */
1241 break;
1242 } /* end switch(oct->status) */
1243
1244 tasklet_kill(&oct_priv->droq_tasklet);
1245}
1246
1247/**
1248 * \brief Send Rx control command
1249 * @param lio per-network private data
1250 * @param start_stop whether to start or stop
1251 */
1252static void send_rx_ctrl_cmd(struct lio *lio, int start_stop)
1253{
1254 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 1255
1256 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
1257
1258 nctrl.ncmd.s.cmd = OCTNET_CMD_RX_CTL;
0cece6c5
RV		 1259 nctrl.ncmd.s.param1 = start_stop;
1260 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 1261 nctrl.netpndev = (u64)lio->netdev;
1262
0cece6c5 1263 if (octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl) < 0)
f21fb3ed
RV		 1264 netif_info(lio, rx_err, lio->netdev, "Failed to send RX Control message\n");
1265}
1266
1267/**
1268 * \brief Destroy NIC device interface
1269 * @param oct octeon device
1270 * @param ifidx which interface to destroy
1271 *
1272 * Cleanup associated with each interface for an Octeon device when NIC
1273 * module is being unloaded or if initialization fails during load.
1274 */
1275static void liquidio_destroy_nic_device(struct octeon_device *oct, int ifidx)
1276{
1277 struct net_device *netdev = oct->props[ifidx].netdev;
1278 struct lio *lio;
9a96bde4 1279 struct napi_struct *napi, *n;
f21fb3ed
RV		 1280
1281 if (!netdev) {
1282 dev_err(&oct->pci_dev->dev, "%s No netdevice ptr for index %d\n",
1283 __func__, ifidx);
1284 return;
1285 }
1286
1287 lio = GET_LIO(netdev);
1288
1289 dev_dbg(&oct->pci_dev->dev, "NIC device cleanup\n");
1290
1291 send_rx_ctrl_cmd(lio, 0);
1292
1293 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING)
1294 txqs_stop(netdev);
1295
9a96bde4
RV		 1296 if (oct->props[lio->ifidx].napi_enabled == 1) {
1297 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
1298 napi_disable(napi);
1299
1300 oct->props[lio->ifidx].napi_enabled = 0;
1301 }
1302
f21fb3ed
RV		 1303 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED)
1304 unregister_netdev(netdev);
1305
fcd2b5e3 1306 delete_glists(lio);
f21fb3ed
RV		 1307
1308 free_netdev(netdev);
1309
0cece6c5
RV		 1310 oct->props[ifidx].gmxport = -1;
1311
f21fb3ed
RV		 1312 oct->props[ifidx].netdev = NULL;
1313}
1314
1315/**
1316 * \brief Stop complete NIC functionality
1317 * @param oct octeon device
1318 */
1319static int liquidio_stop_nic_module(struct octeon_device *oct)
1320{
1321 int i, j;
1322 struct lio *lio;
1323
1324 dev_dbg(&oct->pci_dev->dev, "Stopping network interfaces\n");
1325 if (!oct->ifcount) {
1326 dev_err(&oct->pci_dev->dev, "Init for Octeon was not completed\n");
1327 return 1;
1328 }
1329
1330 for (i = 0; i < oct->ifcount; i++) {
1331 lio = GET_LIO(oct->props[i].netdev);
1332 for (j = 0; j < lio->linfo.num_rxpciq; j++)
26236fa9
RV		 1333 octeon_unregister_droq_ops(oct,
1334 lio->linfo.rxpciq[j].s.q_no);
f21fb3ed
RV		 1335 }
1336
1337 for (i = 0; i < oct->ifcount; i++)
1338 liquidio_destroy_nic_device(oct, i);
1339
1340 dev_dbg(&oct->pci_dev->dev, "Network interfaces stopped\n");
1341 return 0;
1342}
1343
1344/**
1345 * \brief Cleans up resources at unload time
1346 * @param pdev PCI device structure
1347 */
1348static void liquidio_remove(struct pci_dev *pdev)
1349{
1350 struct octeon_device *oct_dev = pci_get_drvdata(pdev);
1351
1352 dev_dbg(&oct_dev->pci_dev->dev, "Stopping device\n");
1353
1354 if (oct_dev->app_mode && (oct_dev->app_mode == CVM_DRV_NIC_APP))
1355 liquidio_stop_nic_module(oct_dev);
1356
1357 /* Reset the octeon device and cleanup all memory allocated for
1358 * the octeon device by driver.
1359 */
1360 octeon_destroy_resources(oct_dev);
1361
1362 dev_info(&oct_dev->pci_dev->dev, "Device removed\n");
1363
1364 /* This octeon device has been removed. Update the global
1365 * data structure to reflect this. Free the device structure.
1366 */
1367 octeon_free_device_mem(oct_dev);
1368}
1369
1370/**
1371 * \brief Identify the Octeon device and to map the BAR address space
1372 * @param oct octeon device
1373 */
1374static int octeon_chip_specific_setup(struct octeon_device *oct)
1375{
1376 u32 dev_id, rev_id;
1377 int ret = 1;
1378
1379 pci_read_config_dword(oct->pci_dev, 0, &dev_id);
1380 pci_read_config_dword(oct->pci_dev, 8, &rev_id);
1381 oct->rev_id = rev_id & 0xff;
1382
1383 switch (dev_id) {
1384 case OCTEON_CN68XX_PCIID:
1385 oct->chip_id = OCTEON_CN68XX;
1386 ret = lio_setup_cn68xx_octeon_device(oct);
1387 break;
1388
1389 case OCTEON_CN66XX_PCIID:
1390 oct->chip_id = OCTEON_CN66XX;
1391 ret = lio_setup_cn66xx_octeon_device(oct);
1392 break;
1393 default:
1394 dev_err(&oct->pci_dev->dev, "Unknown device found (dev_id: %x)\n",
1395 dev_id);
1396 }
1397
1398 if (!ret)
1399 dev_info(&oct->pci_dev->dev, "CN68XX PASS%d.%d %s\n",
1400 OCTEON_MAJOR_REV(oct),
1401 OCTEON_MINOR_REV(oct),
1402 octeon_get_conf(oct)->card_name);
1403
1404 return ret;
1405}
1406
1407/**
1408 * \brief PCI initialization for each Octeon device.
1409 * @param oct octeon device
1410 */
1411static int octeon_pci_os_setup(struct octeon_device *oct)
1412{
1413 /* setup PCI stuff first */
1414 if (pci_enable_device(oct->pci_dev)) {
1415 dev_err(&oct->pci_dev->dev, "pci_enable_device failed\n");
1416 return 1;
1417 }
1418
1419 if (dma_set_mask_and_coherent(&oct->pci_dev->dev, DMA_BIT_MASK(64))) {
1420 dev_err(&oct->pci_dev->dev, "Unexpected DMA device capability\n");
1421 return 1;
1422 }
1423
1424 /* Enable PCI DMA Master. */
1425 pci_set_master(oct->pci_dev);
1426
1427 return 0;
1428}
1429
fcd2b5e3
RV		 1430static inline int skb_iq(struct lio *lio, struct sk_buff *skb)
1431{
1432 int q = 0;
1433
1434 if (netif_is_multiqueue(lio->netdev))
1435 q = skb->queue_mapping % lio->linfo.num_txpciq;
1436
1437 return q;
1438}
1439
f21fb3ed
RV		 1440/**
1441 * \brief Check Tx queue state for a given network buffer
1442 * @param lio per-network private data
1443 * @param skb network buffer
1444 */
1445static inline int check_txq_state(struct lio *lio, struct sk_buff *skb)
1446{
1447 int q = 0, iq = 0;
1448
1449 if (netif_is_multiqueue(lio->netdev)) {
1450 q = skb->queue_mapping;
26236fa9 1451 iq = lio->linfo.txpciq[(q % (lio->linfo.num_txpciq))].s.q_no;
f21fb3ed
RV		 1452 } else {
1453 iq = lio->txq;
26236fa9 1454 q = iq;
f21fb3ed
RV		 1455 }
1456
1457 if (octnet_iq_is_full(lio->oct_dev, iq))
1458 return 0;
26236fa9
RV		 1459
1460 if (__netif_subqueue_stopped(lio->netdev, q))
1461 wake_q(lio->netdev, q);
f21fb3ed
RV		 1462 return 1;
1463}
1464
1465/**
1466 * \brief Unmap and free network buffer
1467 * @param buf buffer
1468 */
1469static void free_netbuf(void *buf)
1470{
1471 struct sk_buff *skb;
1472 struct octnet_buf_free_info *finfo;
1473 struct lio *lio;
1474
1475 finfo = (struct octnet_buf_free_info *)buf;
1476 skb = finfo->skb;
1477 lio = finfo->lio;
1478
1479 dma_unmap_single(&lio->oct_dev->pci_dev->dev, finfo->dptr, skb->len,
1480 DMA_TO_DEVICE);
1481
1482 check_txq_state(lio, skb);
1483
cabeb13b 1484 tx_buffer_free(skb);
f21fb3ed
RV		 1485}
1486
1487/**
1488 * \brief Unmap and free gather buffer
1489 * @param buf buffer
1490 */
1491static void free_netsgbuf(void *buf)
1492{
1493 struct octnet_buf_free_info *finfo;
1494 struct sk_buff *skb;
1495 struct lio *lio;
1496 struct octnic_gather *g;
fcd2b5e3 1497 int i, frags, iq;
f21fb3ed
RV		 1498
1499 finfo = (struct octnet_buf_free_info *)buf;
1500 skb = finfo->skb;
1501 lio = finfo->lio;
1502 g = finfo->g;
1503 frags = skb_shinfo(skb)->nr_frags;
1504
1505 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1506 g->sg[0].ptr[0], (skb->len - skb->data_len),
1507 DMA_TO_DEVICE);
1508
1509 i = 1;
1510 while (frags--) {
1511 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1512
1513 pci_unmap_page((lio->oct_dev)->pci_dev,
1514 g->sg[(i >> 2)].ptr[(i & 3)],
1515 frag->size, DMA_TO_DEVICE);
1516 i++;
1517 }
1518
fcd2b5e3
RV		 1519 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
1520 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
f21fb3ed 1521
fcd2b5e3
RV		 1522 iq = skb_iq(lio, skb);
1523 spin_lock(&lio->glist_lock[iq]);
1524 list_add_tail(&g->list, &lio->glist[iq]);
1525 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1526
1527 check_txq_state(lio, skb); /* mq support: sub-queue state check */
1528
cabeb13b 1529 tx_buffer_free(skb);
f21fb3ed
RV		 1530}
1531
1532/**
1533 * \brief Unmap and free gather buffer with response
1534 * @param buf buffer
1535 */
1536static void free_netsgbuf_with_resp(void *buf)
1537{
1538 struct octeon_soft_command *sc;
1539 struct octnet_buf_free_info *finfo;
1540 struct sk_buff *skb;
1541 struct lio *lio;
1542 struct octnic_gather *g;
fcd2b5e3 1543 int i, frags, iq;
f21fb3ed
RV		 1544
1545 sc = (struct octeon_soft_command *)buf;
1546 skb = (struct sk_buff *)sc->callback_arg;
1547 finfo = (struct octnet_buf_free_info *)&skb->cb;
1548
1549 lio = finfo->lio;
1550 g = finfo->g;
1551 frags = skb_shinfo(skb)->nr_frags;
1552
1553 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1554 g->sg[0].ptr[0], (skb->len - skb->data_len),
1555 DMA_TO_DEVICE);
1556
1557 i = 1;
1558 while (frags--) {
1559 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1560
1561 pci_unmap_page((lio->oct_dev)->pci_dev,
1562 g->sg[(i >> 2)].ptr[(i & 3)],
1563 frag->size, DMA_TO_DEVICE);
1564 i++;
1565 }
1566
fcd2b5e3
RV		 1567 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
1568 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
f21fb3ed 1569
fcd2b5e3
RV		 1570 iq = skb_iq(lio, skb);
1571
1572 spin_lock(&lio->glist_lock[iq]);
1573 list_add_tail(&g->list, &lio->glist[iq]);
1574 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1575
1576 /* Don't free the skb yet */
1577
1578 check_txq_state(lio, skb);
1579}
1580
1581/**
1582 * \brief Adjust ptp frequency
1583 * @param ptp PTP clock info
1584 * @param ppb how much to adjust by, in parts-per-billion
1585 */
1586static int liquidio_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
1587{
1588 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1589 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1590 u64 comp, delta;
1591 unsigned long flags;
1592 bool neg_adj = false;
1593
1594 if (ppb < 0) {
1595 neg_adj = true;
1596 ppb = -ppb;
1597 }
1598
1599 /* The hardware adds the clock compensation value to the
1600 * PTP clock on every coprocessor clock cycle, so we
1601 * compute the delta in terms of coprocessor clocks.
1602 */
1603 delta = (u64)ppb << 32;
1604 do_div(delta, oct->coproc_clock_rate);
1605
1606 spin_lock_irqsave(&lio->ptp_lock, flags);
1607 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP);
1608 if (neg_adj)
1609 comp -= delta;
1610 else
1611 comp += delta;
1612 lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP);
1613 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1614
1615 return 0;
1616}
1617
1618/**
1619 * \brief Adjust ptp time
1620 * @param ptp PTP clock info
1621 * @param delta how much to adjust by, in nanosecs
1622 */
1623static int liquidio_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
1624{
1625 unsigned long flags;
1626 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1627
1628 spin_lock_irqsave(&lio->ptp_lock, flags);
1629 lio->ptp_adjust += delta;
1630 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1631
1632 return 0;
1633}
1634
1635/**
1636 * \brief Get hardware clock time, including any adjustment
1637 * @param ptp PTP clock info
1638 * @param ts timespec
1639 */
1640static int liquidio_ptp_gettime(struct ptp_clock_info *ptp,
1641 struct timespec64 *ts)
1642{
1643 u64 ns;
f21fb3ed
RV		 1644 unsigned long flags;
1645 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1646 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1647
1648 spin_lock_irqsave(&lio->ptp_lock, flags);
1649 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI);
1650 ns += lio->ptp_adjust;
1651 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1652
286af315 1653 *ts = ns_to_timespec64(ns);
f21fb3ed
RV		 1654
1655 return 0;
1656}
1657
1658/**
1659 * \brief Set hardware clock time. Reset adjustment
1660 * @param ptp PTP clock info
1661 * @param ts timespec
1662 */
1663static int liquidio_ptp_settime(struct ptp_clock_info *ptp,
1664 const struct timespec64 *ts)
1665{
1666 u64 ns;
1667 unsigned long flags;
1668 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1669 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1670
1671 ns = timespec_to_ns(ts);
1672
1673 spin_lock_irqsave(&lio->ptp_lock, flags);
1674 lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI);
1675 lio->ptp_adjust = 0;
1676 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1677
1678 return 0;
1679}
1680
1681/**
1682 * \brief Check if PTP is enabled
1683 * @param ptp PTP clock info
1684 * @param rq request
1685 * @param on is it on
1686 */
1687static int liquidio_ptp_enable(struct ptp_clock_info *ptp,
1688 struct ptp_clock_request *rq, int on)
1689{
1690 return -EOPNOTSUPP;
1691}
1692
1693/**
1694 * \brief Open PTP clock source
1695 * @param netdev network device
1696 */
1697static void oct_ptp_open(struct net_device *netdev)
1698{
1699 struct lio *lio = GET_LIO(netdev);
1700 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1701
1702 spin_lock_init(&lio->ptp_lock);
1703
1704 snprintf(lio->ptp_info.name, 16, "%s", netdev->name);
1705 lio->ptp_info.owner = THIS_MODULE;
1706 lio->ptp_info.max_adj = 250000000;
1707 lio->ptp_info.n_alarm = 0;
1708 lio->ptp_info.n_ext_ts = 0;
1709 lio->ptp_info.n_per_out = 0;
1710 lio->ptp_info.pps = 0;
1711 lio->ptp_info.adjfreq = liquidio_ptp_adjfreq;
1712 lio->ptp_info.adjtime = liquidio_ptp_adjtime;
1713 lio->ptp_info.gettime64 = liquidio_ptp_gettime;
1714 lio->ptp_info.settime64 = liquidio_ptp_settime;
1715 lio->ptp_info.enable = liquidio_ptp_enable;
1716
1717 lio->ptp_adjust = 0;
1718
1719 lio->ptp_clock = ptp_clock_register(&lio->ptp_info,
1720 &oct->pci_dev->dev);
1721
1722 if (IS_ERR(lio->ptp_clock))
1723 lio->ptp_clock = NULL;
1724}
1725
1726/**
1727 * \brief Init PTP clock
1728 * @param oct octeon device
1729 */
1730static void liquidio_ptp_init(struct octeon_device *oct)
1731{
1732 u64 clock_comp, cfg;
1733
1734 clock_comp = (u64)NSEC_PER_SEC << 32;
1735 do_div(clock_comp, oct->coproc_clock_rate);
1736 lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP);
1737
1738 /* Enable */
1739 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG);
1740 lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG);
1741}
1742
1743/**
1744 * \brief Load firmware to device
1745 * @param oct octeon device
1746 *
1747 * Maps device to firmware filename, requests firmware, and downloads it
1748 */
1749static int load_firmware(struct octeon_device *oct)
1750{
1751 int ret = 0;
1752 const struct firmware *fw;
1753 char fw_name[LIO_MAX_FW_FILENAME_LEN];
1754 char *tmp_fw_type;
1755
1756 if (strncmp(fw_type, LIO_FW_NAME_TYPE_NONE,
1757 sizeof(LIO_FW_NAME_TYPE_NONE)) == 0) {
1758 dev_info(&oct->pci_dev->dev, "Skipping firmware load\n");
1759 return ret;
1760 }
1761
1762 if (fw_type[0] == '\0')
1763 tmp_fw_type = LIO_FW_NAME_TYPE_NIC;
1764 else
1765 tmp_fw_type = fw_type;
1766
1767 sprintf(fw_name, "%s%s%s_%s%s", LIO_FW_DIR, LIO_FW_BASE_NAME,
1768 octeon_get_conf(oct)->card_name, tmp_fw_type,
1769 LIO_FW_NAME_SUFFIX);
1770
1771 ret = request_firmware(&fw, fw_name, &oct->pci_dev->dev);
1772 if (ret) {
1773 dev_err(&oct->pci_dev->dev, "Request firmware failed. Could not find file %s.\n.",
1774 fw_name);
1775 return ret;
1776 }
1777
1778 ret = octeon_download_firmware(oct, fw->data, fw->size);
1779
1780 release_firmware(fw);
1781
1782 return ret;
1783}
1784
1785/**
1786 * \brief Setup output queue
1787 * @param oct octeon device
1788 * @param q_no which queue
1789 * @param num_descs how many descriptors
1790 * @param desc_size size of each descriptor
1791 * @param app_ctx application context
1792 */
1793static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs,
1794 int desc_size, void *app_ctx)
1795{
1796 int ret_val = 0;
1797
1798 dev_dbg(&oct->pci_dev->dev, "Creating Droq: %d\n", q_no);
1799 /* droq creation and local register settings. */
1800 ret_val = octeon_create_droq(oct, q_no, num_descs, desc_size, app_ctx);
08a965ec 1801 if (ret_val < 0)
f21fb3ed
RV		 1802 return ret_val;
1803
1804 if (ret_val == 1) {
1805 dev_dbg(&oct->pci_dev->dev, "Using default droq %d\n", q_no);
1806 return 0;
1807 }
1808 /* tasklet creation for the droq */
1809
1810 /* Enable the droq queues */
1811 octeon_set_droq_pkt_op(oct, q_no, 1);
1812
1813 /* Send Credit for Octeon Output queues. Credits are always
1814 * sent after the output queue is enabled.
1815 */
1816 writel(oct->droq[q_no]->max_count,
1817 oct->droq[q_no]->pkts_credit_reg);
1818
1819 return ret_val;
1820}
1821
1822/**
1823 * \brief Callback for getting interface configuration
1824 * @param status status of request
1825 * @param buf pointer to resp structure
1826 */
1827static void if_cfg_callback(struct octeon_device *oct,
1828 u32 status,
1829 void *buf)
1830{
1831 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
1832 struct liquidio_if_cfg_resp *resp;
1833 struct liquidio_if_cfg_context *ctx;
1834
1835 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
1836 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
1837
1838 oct = lio_get_device(ctx->octeon_id);
1839 if (resp->status)
1840 dev_err(&oct->pci_dev->dev, "nic if cfg instruction failed. Status: %llx\n",
1841 CVM_CAST64(resp->status));
1842 ACCESS_ONCE(ctx->cond) = 1;
1843
1844 /* This barrier is required to be sure that the response has been
1845 * written fully before waking up the handler
1846 */
1847 wmb();
1848
1849 wake_up_interruptible(&ctx->wc);
1850}
1851
1852/**
1853 * \brief Select queue based on hash
1854 * @param dev Net device
1855 * @param skb sk_buff structure
1856 * @returns selected queue number
1857 */
1858static u16 select_q(struct net_device *dev, struct sk_buff *skb,
1859 void *accel_priv, select_queue_fallback_t fallback)
1860{
26236fa9 1861 u32 qindex = 0;
f21fb3ed
RV		 1862 struct lio *lio;
1863
1864 lio = GET_LIO(dev);
26236fa9
RV		 1865 qindex = skb_tx_hash(dev, skb);
1866
1867 return (u16)(qindex % (lio->linfo.num_txpciq));
f21fb3ed
RV		 1868}
1869
1870/** Routine to push packets arriving on Octeon interface upto network layer.
1871 * @param oct_id - octeon device id.
1872 * @param skbuff - skbuff struct to be passed to network layer.
1873 * @param len - size of total data received.
1874 * @param rh - Control header associated with the packet
1875 * @param param - additional control data with the packet
0cece6c5 1876 * @param arg - farg registered in droq_ops
f21fb3ed
RV		 1877 */
1878static void
1879liquidio_push_packet(u32 octeon_id,
1880 void *skbuff,
1881 u32 len,
1882 union octeon_rh *rh,
0cece6c5
RV		 1883 void *param,
1884 void *arg)
f21fb3ed
RV		 1885{
1886 struct napi_struct *napi = param;
f21fb3ed
RV		 1887 struct sk_buff *skb = (struct sk_buff *)skbuff;
1888 struct skb_shared_hwtstamps *shhwtstamps;
1889 u64 ns;
0da0b77c 1890 u16 vtag = 0;
0cece6c5 1891 struct net_device *netdev = (struct net_device *)arg;
f21fb3ed
RV		 1892 struct octeon_droq *droq = container_of(param, struct octeon_droq,
1893 napi);
1894 if (netdev) {
1895 int packet_was_received;
1896 struct lio *lio = GET_LIO(netdev);
a5b37888 1897 struct octeon_device *oct = lio->oct_dev;
f21fb3ed
RV		 1898
1899 /* Do not proceed if the interface is not in RUNNING state. */
1900 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) {
1901 recv_buffer_free(skb);
1902 droq->stats.rx_dropped++;
1903 return;
1904 }
1905
1906 skb->dev = netdev;
1907
26236fa9 1908 skb_record_rx_queue(skb, droq->q_no);
cabeb13b
RV		 1909 if (likely(len > MIN_SKB_SIZE)) {
1910 struct octeon_skb_page_info *pg_info;
1911 unsigned char *va;
1912
1913 pg_info = ((struct octeon_skb_page_info *)(skb->cb));
1914 if (pg_info->page) {
1915 /* For Paged allocation use the frags */
1916 va = page_address(pg_info->page) +
1917 pg_info->page_offset;
1918 memcpy(skb->data, va, MIN_SKB_SIZE);
1919 skb_put(skb, MIN_SKB_SIZE);
1920 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1921 pg_info->page,
1922 pg_info->page_offset +
1923 MIN_SKB_SIZE,
1924 len - MIN_SKB_SIZE,
1925 LIO_RXBUFFER_SZ);
1926 }
1927 } else {
1928 struct octeon_skb_page_info *pg_info =
1929 ((struct octeon_skb_page_info *)(skb->cb));
1930 skb_copy_to_linear_data(skb, page_address(pg_info->page)
1931 + pg_info->page_offset, len);
1932 skb_put(skb, len);
1933 put_page(pg_info->page);
1934 }
26236fa9 1935
a5b37888
RV		 1936 if (((oct->chip_id == OCTEON_CN66XX) ||
1937 (oct->chip_id == OCTEON_CN68XX)) &&
1938 ptp_enable) {
1939 if (rh->r_dh.has_hwtstamp) {
1940 /* timestamp is included from the hardware at
1941 * the beginning of the packet.
f21fb3ed 1942 */
a5b37888
RV		 1943 if (ifstate_check
1944 (lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED)) {
1945 /* Nanoseconds are in the first 64-bits
1946 * of the packet.
1947 */
1948 memcpy(&ns, (skb->data), sizeof(ns));
1949 shhwtstamps = skb_hwtstamps(skb);
1950 shhwtstamps->hwtstamp =
1951 ns_to_ktime(ns +
1952 lio->ptp_adjust);
1953 }
1954 skb_pull(skb, sizeof(ns));
f21fb3ed 1955 }
f21fb3ed
RV		 1956 }
1957
1958 skb->protocol = eth_type_trans(skb, skb->dev);
1959
1960 if ((netdev->features & NETIF_F_RXCSUM) &&
1961 (rh->r_dh.csum_verified == CNNIC_CSUM_VERIFIED))
1962 /* checksum has already been verified */
1963 skb->ip_summed = CHECKSUM_UNNECESSARY;
1964 else
1965 skb->ip_summed = CHECKSUM_NONE;
1966
0da0b77c
RV		 1967 /* inbound VLAN tag */
1968 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1969 (rh->r_dh.vlan != 0)) {
1970 u16 vid = rh->r_dh.vlan;
1971 u16 priority = rh->r_dh.priority;
1972
1973 vtag = priority << 13 | vid;
1974 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
1975 }
1976
f21fb3ed
RV		 1977 packet_was_received = napi_gro_receive(napi, skb) != GRO_DROP;
1978
1979 if (packet_was_received) {
1980 droq->stats.rx_bytes_received += len;
1981 droq->stats.rx_pkts_received++;
1982 netdev->last_rx = jiffies;
1983 } else {
1984 droq->stats.rx_dropped++;
1985 netif_info(lio, rx_err, lio->netdev,
1986 "droq:%d error rx_dropped:%llu\n",
1987 droq->q_no, droq->stats.rx_dropped);
1988 }
1989
1990 } else {
1991 recv_buffer_free(skb);
1992 }
1993}
1994
1995/**
1996 * \brief wrapper for calling napi_schedule
1997 * @param param parameters to pass to napi_schedule
1998 *
1999 * Used when scheduling on different CPUs
2000 */
2001static void napi_schedule_wrapper(void *param)
2002{
2003 struct napi_struct *napi = param;
2004
2005 napi_schedule(napi);
2006}
2007
2008/**
2009 * \brief callback when receive interrupt occurs and we are in NAPI mode
2010 * @param arg pointer to octeon output queue
2011 */
2012static void liquidio_napi_drv_callback(void *arg)
2013{
2014 struct octeon_droq *droq = arg;
2015 int this_cpu = smp_processor_id();
2016
2017 if (droq->cpu_id == this_cpu) {
2018 napi_schedule(&droq->napi);
2019 } else {
2020 struct call_single_data *csd = &droq->csd;
2021
2022 csd->func = napi_schedule_wrapper;
2023 csd->info = &droq->napi;
2024 csd->flags = 0;
2025
2026 smp_call_function_single_async(droq->cpu_id, csd);
2027 }
2028}
2029
f21fb3ed
RV		 2030/**
2031 * \brief Entry point for NAPI polling
2032 * @param napi NAPI structure
2033 * @param budget maximum number of items to process
2034 */
2035static int liquidio_napi_poll(struct napi_struct *napi, int budget)
2036{
2037 struct octeon_droq *droq;
2038 int work_done;
9a96bde4
RV		 2039 int tx_done = 0, iq_no;
2040 struct octeon_instr_queue *iq;
2041 struct octeon_device *oct;
f21fb3ed
RV		 2042
2043 droq = container_of(napi, struct octeon_droq, napi);
9a96bde4
RV		 2044 oct = droq->oct_dev;
2045 iq_no = droq->q_no;
2046 /* Handle Droq descriptors */
2047 work_done = octeon_process_droq_poll_cmd(oct, droq->q_no,
2048 POLL_EVENT_PROCESS_PKTS,
2049 budget);
f21fb3ed 2050
9a96bde4
RV		 2051 /* Flush the instruction queue */
2052 iq = oct->instr_queue[iq_no];
2053 if (iq) {
2054 /* Process iq buffers with in the budget limits */
2055 tx_done = octeon_flush_iq(oct, iq, 1, budget);
2056 /* Update iq read-index rather than waiting for next interrupt.
2057 * Return back if tx_done is false.
2058 */
2059 update_txq_status(oct, iq_no);
2060 /*tx_done = (iq->flush_index == iq->octeon_read_index);*/
2061 } else {
2062 dev_err(&oct->pci_dev->dev, "%s: iq (%d) num invalid\n",
2063 __func__, iq_no);
2064 }
f21fb3ed 2065
9a96bde4 2066 if ((work_done < budget) && (tx_done)) {
f21fb3ed
RV		 2067 napi_complete(napi);
2068 octeon_process_droq_poll_cmd(droq->oct_dev, droq->q_no,
2069 POLL_EVENT_ENABLE_INTR, 0);
2070 return 0;
2071 }
2072
9a96bde4 2073 return (!tx_done) ? (budget) : (work_done);
f21fb3ed
RV		 2074}
2075
2076/**
2077 * \brief Setup input and output queues
2078 * @param octeon_dev octeon device
2079 * @param net_device Net device
2080 *
2081 * Note: Queues are with respect to the octeon device. Thus
2082 * an input queue is for egress packets, and output queues
2083 * are for ingress packets.
2084 */
2085static inline int setup_io_queues(struct octeon_device *octeon_dev,
0cece6c5 2086 int ifidx)
f21fb3ed 2087{
0cece6c5
RV		 2088 struct octeon_droq_ops droq_ops;
2089 struct net_device *netdev;
f21fb3ed
RV		 2090 static int cpu_id;
2091 static int cpu_id_modulus;
2092 struct octeon_droq *droq;
2093 struct napi_struct *napi;
2094 int q, q_no, retval = 0;
2095 struct lio *lio;
2096 int num_tx_descs;
2097
0cece6c5
RV		 2098 netdev = octeon_dev->props[ifidx].netdev;
2099
2100 lio = GET_LIO(netdev);
f21fb3ed 2101
0cece6c5 2102 memset(&droq_ops, 0, sizeof(struct octeon_droq_ops));
f21fb3ed 2103
0cece6c5
RV		 2104 droq_ops.fptr = liquidio_push_packet;
2105 droq_ops.farg = (void *)netdev;
2106
2107 droq_ops.poll_mode = 1;
2108 droq_ops.napi_fn = liquidio_napi_drv_callback;
2109 cpu_id = 0;
2110 cpu_id_modulus = num_present_cpus();
f21fb3ed
RV		 2111
2112 /* set up DROQs. */
2113 for (q = 0; q < lio->linfo.num_rxpciq; q++) {
26236fa9
RV		 2114 q_no = lio->linfo.rxpciq[q].s.q_no;
2115 dev_dbg(&octeon_dev->pci_dev->dev,
2116 "setup_io_queues index:%d linfo.rxpciq.s.q_no:%d\n",
2117 q, q_no);
f21fb3ed
RV		 2118 retval = octeon_setup_droq(octeon_dev, q_no,
2119 CFG_GET_NUM_RX_DESCS_NIC_IF
2120 (octeon_get_conf(octeon_dev),
2121 lio->ifidx),
2122 CFG_GET_NUM_RX_BUF_SIZE_NIC_IF
2123 (octeon_get_conf(octeon_dev),
2124 lio->ifidx), NULL);
2125 if (retval) {
2126 dev_err(&octeon_dev->pci_dev->dev,
2127 " %s : Runtime DROQ(RxQ) creation failed.\n",
2128 __func__);
2129 return 1;
2130 }
2131
2132 droq = octeon_dev->droq[q_no];
2133 napi = &droq->napi;
0cece6c5
RV		 2134 dev_dbg(&octeon_dev->pci_dev->dev,
2135 "netif_napi_add netdev:%llx oct:%llx\n",
2136 (u64)netdev,
2137 (u64)octeon_dev);
2138 netif_napi_add(netdev, napi, liquidio_napi_poll, 64);
f21fb3ed
RV		 2139
2140 /* designate a CPU for this droq */
2141 droq->cpu_id = cpu_id;
2142 cpu_id++;
2143 if (cpu_id >= cpu_id_modulus)
2144 cpu_id = 0;
2145
2146 octeon_register_droq_ops(octeon_dev, q_no, &droq_ops);
2147 }
2148
2149 /* set up IQs. */
2150 for (q = 0; q < lio->linfo.num_txpciq; q++) {
2151 num_tx_descs = CFG_GET_NUM_TX_DESCS_NIC_IF(octeon_get_conf
2152 (octeon_dev),
2153 lio->ifidx);
0cece6c5
RV		 2154 retval = octeon_setup_iq(octeon_dev, ifidx, q,
2155 lio->linfo.txpciq[q], num_tx_descs,
2156 netdev_get_tx_queue(netdev, q));
f21fb3ed
RV		 2157 if (retval) {
2158 dev_err(&octeon_dev->pci_dev->dev,
2159 " %s : Runtime IQ(TxQ) creation failed.\n",
2160 __func__);
2161 return 1;
2162 }
2163 }
2164
2165 return 0;
2166}
2167
2168/**
2169 * \brief Poll routine for checking transmit queue status
2170 * @param work work_struct data structure
2171 */
2172static void octnet_poll_check_txq_status(struct work_struct *work)
2173{
2174 struct cavium_wk *wk = (struct cavium_wk *)work;
2175 struct lio *lio = (struct lio *)wk->ctxptr;
2176
2177 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING))
2178 return;
2179
2180 check_txq_status(lio);
2181 queue_delayed_work(lio->txq_status_wq.wq,
2182 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2183}
2184
2185/**
2186 * \brief Sets up the txq poll check
2187 * @param netdev network device
2188 */
2189static inline void setup_tx_poll_fn(struct net_device *netdev)
2190{
2191 struct lio *lio = GET_LIO(netdev);
2192 struct octeon_device *oct = lio->oct_dev;
2193
292b9dab
BS		 2194 lio->txq_status_wq.wq = alloc_workqueue("txq-status",
2195 WQ_MEM_RECLAIM, 0);
f21fb3ed
RV		 2196 if (!lio->txq_status_wq.wq) {
2197 dev_err(&oct->pci_dev->dev, "unable to create cavium txq status wq\n");
2198 return;
2199 }
2200 INIT_DELAYED_WORK(&lio->txq_status_wq.wk.work,
2201 octnet_poll_check_txq_status);
2202 lio->txq_status_wq.wk.ctxptr = lio;
2203 queue_delayed_work(lio->txq_status_wq.wq,
2204 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2205}
2206
9a96bde4
RV		 2207static inline void cleanup_tx_poll_fn(struct net_device *netdev)
2208{
2209 struct lio *lio = GET_LIO(netdev);
2210
2211 cancel_delayed_work_sync(&lio->txq_status_wq.wk.work);
2212 destroy_workqueue(lio->txq_status_wq.wq);
2213}
2214
f21fb3ed
RV		 2215/**
2216 * \brief Net device open for LiquidIO
2217 * @param netdev network device
2218 */
2219static int liquidio_open(struct net_device *netdev)
2220{
2221 struct lio *lio = GET_LIO(netdev);
2222 struct octeon_device *oct = lio->oct_dev;
2223 struct napi_struct *napi, *n;
2224
9a96bde4
RV		 2225 if (oct->props[lio->ifidx].napi_enabled == 0) {
2226 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
2227 napi_enable(napi);
2228
2229 oct->props[lio->ifidx].napi_enabled = 1;
2230 }
f21fb3ed
RV		 2231
2232 oct_ptp_open(netdev);
2233
2234 ifstate_set(lio, LIO_IFSTATE_RUNNING);
9a96bde4 2235
f21fb3ed 2236 setup_tx_poll_fn(netdev);
9a96bde4 2237
f21fb3ed
RV		 2238 start_txq(netdev);
2239
2240 netif_info(lio, ifup, lio->netdev, "Interface Open, ready for traffic\n");
f21fb3ed
RV		 2241
2242 /* tell Octeon to start forwarding packets to host */
2243 send_rx_ctrl_cmd(lio, 1);
2244
2245 /* Ready for link status updates */
2246 lio->intf_open = 1;
2247
2248 dev_info(&oct->pci_dev->dev, "%s interface is opened\n",
2249 netdev->name);
2250
2251 return 0;
2252}
2253
2254/**
2255 * \brief Net device stop for LiquidIO
2256 * @param netdev network device
2257 */
2258static int liquidio_stop(struct net_device *netdev)
2259{
f21fb3ed
RV		 2260 struct lio *lio = GET_LIO(netdev);
2261 struct octeon_device *oct = lio->oct_dev;
2262
9a96bde4
RV		 2263 ifstate_reset(lio, LIO_IFSTATE_RUNNING);
2264
2265 netif_tx_disable(netdev);
2266
f21fb3ed 2267 /* Inform that netif carrier is down */
9a96bde4 2268 netif_carrier_off(netdev);
f21fb3ed 2269 lio->intf_open = 0;
0cece6c5
RV		 2270 lio->linfo.link.s.link_up = 0;
2271 lio->link_changes++;
f21fb3ed 2272
9a96bde4
RV		 2273 /* Pause for a moment and wait for Octeon to flush out (to the wire) any
2274 * egress packets that are in-flight.
2275 */
2276 set_current_state(TASK_INTERRUPTIBLE);
2277 schedule_timeout(msecs_to_jiffies(100));
f21fb3ed 2278
9a96bde4 2279 /* Now it should be safe to tell Octeon that nic interface is down. */
f21fb3ed
RV		 2280 send_rx_ctrl_cmd(lio, 0);
2281
9a96bde4 2282 cleanup_tx_poll_fn(netdev);
f21fb3ed
RV		 2283
2284 if (lio->ptp_clock) {
2285 ptp_clock_unregister(lio->ptp_clock);
2286 lio->ptp_clock = NULL;
2287 }
2288
f21fb3ed
RV		 2289 dev_info(&oct->pci_dev->dev, "%s interface is stopped\n", netdev->name);
2290 module_put(THIS_MODULE);
2291
2292 return 0;
2293}
2294
2295void liquidio_link_ctrl_cmd_completion(void *nctrl_ptr)
2296{
2297 struct octnic_ctrl_pkt *nctrl = (struct octnic_ctrl_pkt *)nctrl_ptr;
2298 struct net_device *netdev = (struct net_device *)nctrl->netpndev;
2299 struct lio *lio = GET_LIO(netdev);
2300 struct octeon_device *oct = lio->oct_dev;
2301
2302 switch (nctrl->ncmd.s.cmd) {
2303 case OCTNET_CMD_CHANGE_DEVFLAGS:
2304 case OCTNET_CMD_SET_MULTI_LIST:
2305 break;
2306
2307 case OCTNET_CMD_CHANGE_MACADDR:
2308 /* If command is successful, change the MACADDR. */
2309 netif_info(lio, probe, lio->netdev, " MACAddr changed to 0x%llx\n",
2310 CVM_CAST64(nctrl->udd[0]));
2311 dev_info(&oct->pci_dev->dev, "%s MACAddr changed to 0x%llx\n",
2312 netdev->name, CVM_CAST64(nctrl->udd[0]));
2313 memcpy(netdev->dev_addr, ((u8 *)&nctrl->udd[0]) + 2, ETH_ALEN);
2314 break;
2315
2316 case OCTNET_CMD_CHANGE_MTU:
2317 /* If command is successful, change the MTU. */
2318 netif_info(lio, probe, lio->netdev, " MTU Changed from %d to %d\n",
2319 netdev->mtu, nctrl->ncmd.s.param2);
2320 dev_info(&oct->pci_dev->dev, "%s MTU Changed from %d to %d\n",
2321 netdev->name, netdev->mtu,
2322 nctrl->ncmd.s.param2);
2323 netdev->mtu = nctrl->ncmd.s.param2;
2324 break;
2325
2326 case OCTNET_CMD_GPIO_ACCESS:
2327 netif_info(lio, probe, lio->netdev, "LED Flashing visual identification\n");
2328
2329 break;
2330
2331 case OCTNET_CMD_LRO_ENABLE:
2332 dev_info(&oct->pci_dev->dev, "%s LRO Enabled\n", netdev->name);
2333 break;
2334
2335 case OCTNET_CMD_LRO_DISABLE:
2336 dev_info(&oct->pci_dev->dev, "%s LRO Disabled\n",
2337 netdev->name);
2338 break;
2339
2340 case OCTNET_CMD_VERBOSE_ENABLE:
2341 dev_info(&oct->pci_dev->dev, "%s LRO Enabled\n", netdev->name);
2342 break;
2343
2344 case OCTNET_CMD_VERBOSE_DISABLE:
2345 dev_info(&oct->pci_dev->dev, "%s LRO Disabled\n",
2346 netdev->name);
2347 break;
2348
63245f25
RV		 2349 case OCTNET_CMD_ENABLE_VLAN_FILTER:
2350 dev_info(&oct->pci_dev->dev, "%s VLAN filter enabled\n",
2351 netdev->name);
2352 break;
2353
2354 case OCTNET_CMD_ADD_VLAN_FILTER:
2355 dev_info(&oct->pci_dev->dev, "%s VLAN filter %d added\n",
2356 netdev->name, nctrl->ncmd.s.param1);
2357 break;
2358
2359 case OCTNET_CMD_DEL_VLAN_FILTER:
2360 dev_info(&oct->pci_dev->dev, "%s VLAN filter %d removed\n",
2361 netdev->name, nctrl->ncmd.s.param1);
2362 break;
2363
f21fb3ed
RV		 2364 case OCTNET_CMD_SET_SETTINGS:
2365 dev_info(&oct->pci_dev->dev, "%s settings changed\n",
2366 netdev->name);
2367
2368 break;
2369
2370 default:
2371 dev_err(&oct->pci_dev->dev, "%s Unknown cmd %d\n", __func__,
2372 nctrl->ncmd.s.cmd);
2373 }
2374}
2375
2376/**
2377 * \brief Converts a mask based on net device flags
2378 * @param netdev network device
2379 *
2380 * This routine generates a octnet_ifflags mask from the net device flags
2381 * received from the OS.
2382 */
2383static inline enum octnet_ifflags get_new_flags(struct net_device *netdev)
2384{
2385 enum octnet_ifflags f = OCTNET_IFFLAG_UNICAST;
2386
2387 if (netdev->flags & IFF_PROMISC)
2388 f |= OCTNET_IFFLAG_PROMISC;
2389
2390 if (netdev->flags & IFF_ALLMULTI)
2391 f |= OCTNET_IFFLAG_ALLMULTI;
2392
2393 if (netdev->flags & IFF_MULTICAST) {
2394 f |= OCTNET_IFFLAG_MULTICAST;
2395
2396 /* Accept all multicast addresses if there are more than we
2397 * can handle
2398 */
2399 if (netdev_mc_count(netdev) > MAX_OCTEON_MULTICAST_ADDR)
2400 f |= OCTNET_IFFLAG_ALLMULTI;
2401 }
2402
2403 if (netdev->flags & IFF_BROADCAST)
2404 f |= OCTNET_IFFLAG_BROADCAST;
2405
2406 return f;
2407}
2408
2409/**
2410 * \brief Net device set_multicast_list
2411 * @param netdev network device
2412 */
2413static void liquidio_set_mcast_list(struct net_device *netdev)
2414{
2415 struct lio *lio = GET_LIO(netdev);
2416 struct octeon_device *oct = lio->oct_dev;
2417 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2418 struct netdev_hw_addr *ha;
2419 u64 *mc;
2420 int ret, i;
2421 int mc_count = min(netdev_mc_count(netdev), MAX_OCTEON_MULTICAST_ADDR);
2422
2423 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2424
2425 /* Create a ctrl pkt command to be sent to core app. */
2426 nctrl.ncmd.u64 = 0;
2427 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_MULTI_LIST;
0cece6c5
RV		 2428 nctrl.ncmd.s.param1 = get_new_flags(netdev);
2429 nctrl.ncmd.s.param2 = mc_count;
f21fb3ed 2430 nctrl.ncmd.s.more = mc_count;
0cece6c5 2431 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2432 nctrl.netpndev = (u64)netdev;
2433 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2434
2435 /* copy all the addresses into the udd */
2436 i = 0;
2437 mc = &nctrl.udd[0];
2438 netdev_for_each_mc_addr(ha, netdev) {
2439 *mc = 0;
2440 memcpy(((u8 *)mc) + 2, ha->addr, ETH_ALEN);
2441 /* no need to swap bytes */
2442
2443 if (++mc > &nctrl.udd[mc_count])
2444 break;
2445 }
2446
2447 /* Apparently, any activity in this call from the kernel has to
2448 * be atomic. So we won't wait for response.
2449 */
2450 nctrl.wait_time = 0;
2451
0cece6c5 2452 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2453 if (ret < 0) {
2454 dev_err(&oct->pci_dev->dev, "DEVFLAGS change failed in core (ret: 0x%x)\n",
2455 ret);
2456 }
2457}
2458
2459/**
2460 * \brief Net device set_mac_address
2461 * @param netdev network device
2462 */
2463static int liquidio_set_mac(struct net_device *netdev, void *p)
2464{
2465 int ret = 0;
2466 struct lio *lio = GET_LIO(netdev);
2467 struct octeon_device *oct = lio->oct_dev;
2468 struct sockaddr *addr = (struct sockaddr *)p;
2469 struct octnic_ctrl_pkt nctrl;
f21fb3ed 2470
0cece6c5 2471 if (!is_valid_ether_addr(addr->sa_data))
f21fb3ed
RV		 2472 return -EADDRNOTAVAIL;
2473
2474 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2475
2476 nctrl.ncmd.u64 = 0;
2477 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
0cece6c5 2478 nctrl.ncmd.s.param1 = 0;
f21fb3ed 2479 nctrl.ncmd.s.more = 1;
0cece6c5 2480 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2481 nctrl.netpndev = (u64)netdev;
2482 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2483 nctrl.wait_time = 100;
2484
2485 nctrl.udd[0] = 0;
2486 /* The MAC Address is presented in network byte order. */
2487 memcpy((u8 *)&nctrl.udd[0] + 2, addr->sa_data, ETH_ALEN);
2488
0cece6c5 2489 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2490 if (ret < 0) {
2491 dev_err(&oct->pci_dev->dev, "MAC Address change failed\n");
2492 return -ENOMEM;
2493 }
2494 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2495 memcpy(((u8 *)&lio->linfo.hw_addr) + 2, addr->sa_data, ETH_ALEN);
2496
2497 return 0;
2498}
2499
2500/**
2501 * \brief Net device get_stats
2502 * @param netdev network device
2503 */
2504static struct net_device_stats *liquidio_get_stats(struct net_device *netdev)
2505{
2506 struct lio *lio = GET_LIO(netdev);
2507 struct net_device_stats *stats = &netdev->stats;
2508 struct octeon_device *oct;
2509 u64 pkts = 0, drop = 0, bytes = 0;
2510 struct oct_droq_stats *oq_stats;
2511 struct oct_iq_stats *iq_stats;
2512 int i, iq_no, oq_no;
2513
2514 oct = lio->oct_dev;
2515
2516 for (i = 0; i < lio->linfo.num_txpciq; i++) {
26236fa9 2517 iq_no = lio->linfo.txpciq[i].s.q_no;
f21fb3ed
RV		 2518 iq_stats = &oct->instr_queue[iq_no]->stats;
2519 pkts += iq_stats->tx_done;
2520 drop += iq_stats->tx_dropped;
2521 bytes += iq_stats->tx_tot_bytes;
2522 }
2523
2524 stats->tx_packets = pkts;
2525 stats->tx_bytes = bytes;
2526 stats->tx_dropped = drop;
2527
2528 pkts = 0;
2529 drop = 0;
2530 bytes = 0;
2531
2532 for (i = 0; i < lio->linfo.num_rxpciq; i++) {
26236fa9 2533 oq_no = lio->linfo.rxpciq[i].s.q_no;
f21fb3ed
RV		 2534 oq_stats = &oct->droq[oq_no]->stats;
2535 pkts += oq_stats->rx_pkts_received;
2536 drop += (oq_stats->rx_dropped +
2537 oq_stats->dropped_nodispatch +
2538 oq_stats->dropped_toomany +
2539 oq_stats->dropped_nomem);
2540 bytes += oq_stats->rx_bytes_received;
2541 }
2542
2543 stats->rx_bytes = bytes;
2544 stats->rx_packets = pkts;
2545 stats->rx_dropped = drop;
2546
2547 return stats;
2548}
2549
2550/**
2551 * \brief Net device change_mtu
2552 * @param netdev network device
2553 */
2554static int liquidio_change_mtu(struct net_device *netdev, int new_mtu)
2555{
2556 struct lio *lio = GET_LIO(netdev);
2557 struct octeon_device *oct = lio->oct_dev;
2558 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2559 int max_frm_size = new_mtu + OCTNET_FRM_HEADER_SIZE;
2560 int ret = 0;
2561
2562 /* Limit the MTU to make sure the ethernet packets are between 64 bytes
2563 * and 65535 bytes
2564 */
2565 if ((max_frm_size < OCTNET_MIN_FRM_SIZE) ||
2566 (max_frm_size > OCTNET_MAX_FRM_SIZE)) {
2567 dev_err(&oct->pci_dev->dev, "Invalid MTU: %d\n", new_mtu);
2568 dev_err(&oct->pci_dev->dev, "Valid range %d and %d\n",
2569 (OCTNET_MIN_FRM_SIZE - OCTNET_FRM_HEADER_SIZE),
2570 (OCTNET_MAX_FRM_SIZE - OCTNET_FRM_HEADER_SIZE));
2571 return -EINVAL;
2572 }
2573
2574 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2575
2576 nctrl.ncmd.u64 = 0;
2577 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MTU;
0cece6c5
RV		 2578 nctrl.ncmd.s.param1 = new_mtu;
2579 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2580 nctrl.wait_time = 100;
2581 nctrl.netpndev = (u64)netdev;
2582 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2583
0cece6c5 2584 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2585 if (ret < 0) {
2586 dev_err(&oct->pci_dev->dev, "Failed to set MTU\n");
2587 return -1;
2588 }
2589
2590 lio->mtu = new_mtu;
2591
2592 return 0;
2593}
2594
2595/**
2596 * \brief Handler for SIOCSHWTSTAMP ioctl
2597 * @param netdev network device
2598 * @param ifr interface request
2599 * @param cmd command
2600 */
2601static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2602{
2603 struct hwtstamp_config conf;
2604 struct lio *lio = GET_LIO(netdev);
2605
2606 if (copy_from_user(&conf, ifr->ifr_data, sizeof(conf)))
2607 return -EFAULT;
2608
2609 if (conf.flags)
2610 return -EINVAL;
2611
2612 switch (conf.tx_type) {
2613 case HWTSTAMP_TX_ON:
2614 case HWTSTAMP_TX_OFF:
2615 break;
2616 default:
2617 return -ERANGE;
2618 }
2619
2620 switch (conf.rx_filter) {
2621 case HWTSTAMP_FILTER_NONE:
2622 break;
2623 case HWTSTAMP_FILTER_ALL:
2624 case HWTSTAMP_FILTER_SOME:
2625 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2626 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2627 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2628 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2629 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2630 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2631 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2632 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2633 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2634 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2635 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2636 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2637 conf.rx_filter = HWTSTAMP_FILTER_ALL;
2638 break;
2639 default:
2640 return -ERANGE;
2641 }
2642
2643 if (conf.rx_filter == HWTSTAMP_FILTER_ALL)
2644 ifstate_set(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
2645
2646 else
2647 ifstate_reset(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
2648
2649 return copy_to_user(ifr->ifr_data, &conf, sizeof(conf)) ? -EFAULT : 0;
2650}
2651
2652/**
2653 * \brief ioctl handler
2654 * @param netdev network device
2655 * @param ifr interface request
2656 * @param cmd command
2657 */
2658static int liquidio_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2659{
2660 switch (cmd) {
2661 case SIOCSHWTSTAMP:
2662 return hwtstamp_ioctl(netdev, ifr, cmd);
2663 default:
2664 return -EOPNOTSUPP;
2665 }
2666}
2667
2668/**
2669 * \brief handle a Tx timestamp response
2670 * @param status response status
2671 * @param buf pointer to skb
2672 */
2673static void handle_timestamp(struct octeon_device *oct,
2674 u32 status,
2675 void *buf)
2676{
2677 struct octnet_buf_free_info *finfo;
2678 struct octeon_soft_command *sc;
2679 struct oct_timestamp_resp *resp;
2680 struct lio *lio;
2681 struct sk_buff *skb = (struct sk_buff *)buf;
2682
2683 finfo = (struct octnet_buf_free_info *)skb->cb;
2684 lio = finfo->lio;
2685 sc = finfo->sc;
2686 oct = lio->oct_dev;
2687 resp = (struct oct_timestamp_resp *)sc->virtrptr;
2688
2689 if (status != OCTEON_REQUEST_DONE) {
2690 dev_err(&oct->pci_dev->dev, "Tx timestamp instruction failed. Status: %llx\n",
2691 CVM_CAST64(status));
2692 resp->timestamp = 0;
2693 }
2694
2695 octeon_swap_8B_data(&resp->timestamp, 1);
2696
19a6d156 2697 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) != 0)) {
f21fb3ed
RV		 2698 struct skb_shared_hwtstamps ts;
2699 u64 ns = resp->timestamp;
2700
2701 netif_info(lio, tx_done, lio->netdev,
2702 "Got resulting SKBTX_HW_TSTAMP skb=%p ns=%016llu\n",
2703 skb, (unsigned long long)ns);
2704 ts.hwtstamp = ns_to_ktime(ns + lio->ptp_adjust);
2705 skb_tstamp_tx(skb, &ts);
2706 }
2707
2708 octeon_free_soft_command(oct, sc);
cabeb13b 2709 tx_buffer_free(skb);
f21fb3ed
RV		 2710}
2711
2712/* \brief Send a data packet that will be timestamped
2713 * @param oct octeon device
2714 * @param ndata pointer to network data
2715 * @param finfo pointer to private network data
2716 */
2717static inline int send_nic_timestamp_pkt(struct octeon_device *oct,
2718 struct octnic_data_pkt *ndata,
2719 struct octnet_buf_free_info *finfo,
2720 int xmit_more)
2721{
2722 int retval;
2723 struct octeon_soft_command *sc;
f21fb3ed
RV		 2724 struct lio *lio;
2725 int ring_doorbell;
6a885b60 2726 u32 len;
f21fb3ed
RV		 2727
2728 lio = finfo->lio;
2729
2730 sc = octeon_alloc_soft_command_resp(oct, &ndata->cmd,
2731 sizeof(struct oct_timestamp_resp));
2732 finfo->sc = sc;
2733
2734 if (!sc) {
2735 dev_err(&oct->pci_dev->dev, "No memory for timestamped data packet\n");
2736 return IQ_SEND_FAILED;
2737 }
2738
2739 if (ndata->reqtype == REQTYPE_NORESP_NET)
2740 ndata->reqtype = REQTYPE_RESP_NET;
2741 else if (ndata->reqtype == REQTYPE_NORESP_NET_SG)
2742 ndata->reqtype = REQTYPE_RESP_NET_SG;
2743
2744 sc->callback = handle_timestamp;
2745 sc->callback_arg = finfo->skb;
2746 sc->iq_no = ndata->q_no;
2747
6a885b60 2748 len = (u32)((struct octeon_instr_ih2 *)(&sc->cmd.cmd2.ih2))->dlengsz;
f21fb3ed
RV		 2749
2750 ring_doorbell = !xmit_more;
2751 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd,
6a885b60 2752 sc, len, ndata->reqtype);
f21fb3ed 2753
ddc173a6 2754 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 2755 dev_err(&oct->pci_dev->dev, "timestamp data packet failed status: %x\n",
2756 retval);
2757 octeon_free_soft_command(oct, sc);
2758 } else {
2759 netif_info(lio, tx_queued, lio->netdev, "Queued timestamp packet\n");
2760 }
2761
2762 return retval;
2763}
2764
f21fb3ed
RV		 2765/** \brief Transmit networks packets to the Octeon interface
2766 * @param skbuff skbuff struct to be passed to network layer.
2767 * @param netdev pointer to network device
2768 * @returns whether the packet was transmitted to the device okay or not
2769 * (NETDEV_TX_OK or NETDEV_TX_BUSY)
2770 */
2771static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev)
2772{
2773 struct lio *lio;
2774 struct octnet_buf_free_info *finfo;
2775 union octnic_cmd_setup cmdsetup;
2776 struct octnic_data_pkt ndata;
2777 struct octeon_device *oct;
2778 struct oct_iq_stats *stats;
6a885b60
RV		 2779 struct octeon_instr_irh *irh;
2780 union tx_info *tx_info;
26236fa9 2781 int status = 0;
f21fb3ed 2782 int q_idx = 0, iq_no = 0;
fcd2b5e3
RV		 2783 int xmit_more, j;
2784 u64 dptr = 0;
f21fb3ed
RV		 2785 u32 tag = 0;
2786
2787 lio = GET_LIO(netdev);
2788 oct = lio->oct_dev;
2789
2790 if (netif_is_multiqueue(netdev)) {
26236fa9
RV		 2791 q_idx = skb->queue_mapping;
2792 q_idx = (q_idx % (lio->linfo.num_txpciq));
2793 tag = q_idx;
2794 iq_no = lio->linfo.txpciq[q_idx].s.q_no;
f21fb3ed
RV		 2795 } else {
2796 iq_no = lio->txq;
2797 }
2798
2799 stats = &oct->instr_queue[iq_no]->stats;
2800
2801 /* Check for all conditions in which the current packet cannot be
2802 * transmitted.
2803 */
2804 if (!(atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) ||
0cece6c5 2805 (!lio->linfo.link.s.link_up) ||
f21fb3ed
RV		 2806 (skb->len <= 0)) {
2807 netif_info(lio, tx_err, lio->netdev,
2808 "Transmit failed link_status : %d\n",
0cece6c5 2809 lio->linfo.link.s.link_up);
f21fb3ed
RV		 2810 goto lio_xmit_failed;
2811 }
2812
2813 /* Use space in skb->cb to store info used to unmap and
2814 * free the buffers.
2815 */
2816 finfo = (struct octnet_buf_free_info *)skb->cb;
2817 finfo->lio = lio;
2818 finfo->skb = skb;
2819 finfo->sc = NULL;
2820
2821 /* Prepare the attributes for the data to be passed to OSI. */
2822 memset(&ndata, 0, sizeof(struct octnic_data_pkt));
2823
2824 ndata.buf = (void *)finfo;
2825
2826 ndata.q_no = iq_no;
2827
2828 if (netif_is_multiqueue(netdev)) {
2829 if (octnet_iq_is_full(oct, ndata.q_no)) {
2830 /* defer sending if queue is full */
2831 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
2832 ndata.q_no);
2833 stats->tx_iq_busy++;
2834 return NETDEV_TX_BUSY;
2835 }
2836 } else {
2837 if (octnet_iq_is_full(oct, lio->txq)) {
2838 /* defer sending if queue is full */
2839 stats->tx_iq_busy++;
2840 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
2841 ndata.q_no);
2842 return NETDEV_TX_BUSY;
2843 }
2844 }
2845 /* pr_info(" XMIT - valid Qs: %d, 1st Q no: %d, cpu: %d, q_no:%d\n",
2846 * lio->linfo.num_txpciq, lio->txq, cpu, ndata.q_no );
2847 */
2848
2849 ndata.datasize = skb->len;
2850
2851 cmdsetup.u64 = 0;
7275ebfc 2852 cmdsetup.s.iq_no = iq_no;
f21fb3ed 2853
7275ebfc
RV		 2854 if (skb->ip_summed == CHECKSUM_PARTIAL)
2855 cmdsetup.s.transport_csum = 1;
f21fb3ed 2856
f21fb3ed
RV		 2857 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
2858 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2859 cmdsetup.s.timestamp = 1;
2860 }
2861
2862 if (skb_shinfo(skb)->nr_frags == 0) {
2863 cmdsetup.s.u.datasize = skb->len;
0cece6c5 2864 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
f21fb3ed 2865 /* Offload checksum calculation for TCP/UDP packets */
6a885b60
RV		 2866 dptr = dma_map_single(&oct->pci_dev->dev,
2867 skb->data,
2868 skb->len,
2869 DMA_TO_DEVICE);
2870 if (dma_mapping_error(&oct->pci_dev->dev, dptr)) {
f21fb3ed
RV		 2871 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 1\n",
2872 __func__);
2873 return NETDEV_TX_BUSY;
2874 }
2875
6a885b60
RV		 2876 ndata.cmd.cmd2.dptr = dptr;
2877 finfo->dptr = dptr;
f21fb3ed
RV		 2878 ndata.reqtype = REQTYPE_NORESP_NET;
2879
2880 } else {
2881 int i, frags;
2882 struct skb_frag_struct *frag;
2883 struct octnic_gather *g;
2884
fcd2b5e3
RV		 2885 spin_lock(&lio->glist_lock[q_idx]);
2886 g = (struct octnic_gather *)
2887 list_delete_head(&lio->glist[q_idx]);
2888 spin_unlock(&lio->glist_lock[q_idx]);
f21fb3ed
RV		 2889
2890 if (!g) {
2891 netif_info(lio, tx_err, lio->netdev,
2892 "Transmit scatter gather: glist null!\n");
2893 goto lio_xmit_failed;
2894 }
2895
2896 cmdsetup.s.gather = 1;
2897 cmdsetup.s.u.gatherptrs = (skb_shinfo(skb)->nr_frags + 1);
0cece6c5 2898 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
f21fb3ed
RV		 2899
2900 memset(g->sg, 0, g->sg_size);
2901
2902 g->sg[0].ptr[0] = dma_map_single(&oct->pci_dev->dev,
2903 skb->data,
2904 (skb->len - skb->data_len),
2905 DMA_TO_DEVICE);
2906 if (dma_mapping_error(&oct->pci_dev->dev, g->sg[0].ptr[0])) {
2907 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 2\n",
2908 __func__);
2909 return NETDEV_TX_BUSY;
2910 }
2911 add_sg_size(&g->sg[0], (skb->len - skb->data_len), 0);
2912
2913 frags = skb_shinfo(skb)->nr_frags;
2914 i = 1;
2915 while (frags--) {
2916 frag = &skb_shinfo(skb)->frags[i - 1];
2917
2918 g->sg[(i >> 2)].ptr[(i & 3)] =
2919 dma_map_page(&oct->pci_dev->dev,
2920 frag->page.p,
2921 frag->page_offset,
2922 frag->size,
2923 DMA_TO_DEVICE);
2924
fcd2b5e3
RV		 2925 if (dma_mapping_error(&oct->pci_dev->dev,
2926 g->sg[i >> 2].ptr[i & 3])) {
2927 dma_unmap_single(&oct->pci_dev->dev,
2928 g->sg[0].ptr[0],
2929 skb->len - skb->data_len,
2930 DMA_TO_DEVICE);
2931 for (j = 1; j < i; j++) {
2932 frag = &skb_shinfo(skb)->frags[j - 1];
2933 dma_unmap_page(&oct->pci_dev->dev,
2934 g->sg[j >> 2].ptr[j & 3],
2935 frag->size,
2936 DMA_TO_DEVICE);
2937 }
2938 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 3\n",
2939 __func__);
2940 return NETDEV_TX_BUSY;
2941 }
2942
f21fb3ed
RV		 2943 add_sg_size(&g->sg[(i >> 2)], frag->size, (i & 3));
2944 i++;
2945 }
2946
fcd2b5e3
RV		 2947 dma_sync_single_for_device(&oct->pci_dev->dev, g->sg_dma_ptr,
2948 g->sg_size, DMA_TO_DEVICE);
2949 dptr = g->sg_dma_ptr;
f21fb3ed 2950
6a885b60
RV		 2951 ndata.cmd.cmd2.dptr = dptr;
2952 finfo->dptr = dptr;
f21fb3ed
RV		 2953 finfo->g = g;
2954
2955 ndata.reqtype = REQTYPE_NORESP_NET_SG;
2956 }
2957
6a885b60
RV		 2958 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd2.irh;
2959 tx_info = (union tx_info *)&ndata.cmd.cmd2.ossp[0];
f21fb3ed 2960
6a885b60 2961 if (skb_shinfo(skb)->gso_size) {
f21fb3ed
RV		 2962 tx_info->s.gso_size = skb_shinfo(skb)->gso_size;
2963 tx_info->s.gso_segs = skb_shinfo(skb)->gso_segs;
2964 }
0da0b77c
RV		 2965 /* HW insert VLAN tag */
2966 if (skb_vlan_tag_present(skb)) {
2967 irh->priority = skb_vlan_tag_get(skb) >> 13;
2968 irh->vlan = skb_vlan_tag_get(skb) & 0xfff;
2969 }
f21fb3ed
RV		 2970
2971 xmit_more = skb->xmit_more;
2972
2973 if (unlikely(cmdsetup.s.timestamp))
2974 status = send_nic_timestamp_pkt(oct, &ndata, finfo, xmit_more);
2975 else
2976 status = octnet_send_nic_data_pkt(oct, &ndata, xmit_more);
2977 if (status == IQ_SEND_FAILED)
2978 goto lio_xmit_failed;
2979
2980 netif_info(lio, tx_queued, lio->netdev, "Transmit queued successfully\n");
2981
2982 if (status == IQ_SEND_STOP)
2983 stop_q(lio->netdev, q_idx);
2984
860e9538 2985 netif_trans_update(netdev);
f21fb3ed
RV		 2986
2987 stats->tx_done++;
2988 stats->tx_tot_bytes += skb->len;
2989
2990 return NETDEV_TX_OK;
2991
2992lio_xmit_failed:
2993 stats->tx_dropped++;
2994 netif_info(lio, tx_err, lio->netdev, "IQ%d Transmit dropped:%llu\n",
2995 iq_no, stats->tx_dropped);
6a885b60
RV		 2996 if (dptr)
2997 dma_unmap_single(&oct->pci_dev->dev, dptr,
2998 ndata.datasize, DMA_TO_DEVICE);
cabeb13b 2999 tx_buffer_free(skb);
f21fb3ed
RV		 3000 return NETDEV_TX_OK;
3001}
3002
3003/** \brief Network device Tx timeout
3004 * @param netdev pointer to network device
3005 */
3006static void liquidio_tx_timeout(struct net_device *netdev)
3007{
3008 struct lio *lio;
3009
3010 lio = GET_LIO(netdev);
3011
3012 netif_info(lio, tx_err, lio->netdev,
3013 "Transmit timeout tx_dropped:%ld, waking up queues now!!\n",
3014 netdev->stats.tx_dropped);
860e9538 3015 netif_trans_update(netdev);
f21fb3ed
RV		 3016 txqs_wake(netdev);
3017}
3018
63245f25
RV		 3019static int liquidio_vlan_rx_add_vid(struct net_device *netdev,
3020 __be16 proto __attribute__((unused)),
3021 u16 vid)
3022{
3023 struct lio *lio = GET_LIO(netdev);
3024 struct octeon_device *oct = lio->oct_dev;
3025 struct octnic_ctrl_pkt nctrl;
3026 int ret = 0;
3027
3028 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3029
3030 nctrl.ncmd.u64 = 0;
3031 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER;
3032 nctrl.ncmd.s.param1 = vid;
3033 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3034 nctrl.wait_time = 100;
3035 nctrl.netpndev = (u64)netdev;
3036 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3037
3038 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3039 if (ret < 0) {
3040 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
3041 ret);
3042 }
3043
3044 return ret;
3045}
3046
3047static int liquidio_vlan_rx_kill_vid(struct net_device *netdev,
3048 __be16 proto __attribute__((unused)),
3049 u16 vid)
3050{
3051 struct lio *lio = GET_LIO(netdev);
3052 struct octeon_device *oct = lio->oct_dev;
3053 struct octnic_ctrl_pkt nctrl;
3054 int ret = 0;
3055
3056 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3057
3058 nctrl.ncmd.u64 = 0;
3059 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER;
3060 nctrl.ncmd.s.param1 = vid;
3061 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3062 nctrl.wait_time = 100;
3063 nctrl.netpndev = (u64)netdev;
3064 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3065
3066 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3067 if (ret < 0) {
3068 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
3069 ret);
3070 }
3071 return ret;
3072}
3073
0cece6c5 3074int liquidio_set_feature(struct net_device *netdev, int cmd, u16 param1)
f21fb3ed
RV		 3075{
3076 struct lio *lio = GET_LIO(netdev);
3077 struct octeon_device *oct = lio->oct_dev;
3078 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 3079 int ret = 0;
3080
3081 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3082
3083 nctrl.ncmd.u64 = 0;
3084 nctrl.ncmd.s.cmd = cmd;
0cece6c5
RV		 3085 nctrl.ncmd.s.param1 = param1;
3086 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 3087 nctrl.wait_time = 100;
3088 nctrl.netpndev = (u64)netdev;
3089 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3090
0cece6c5 3091 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 3092 if (ret < 0) {
3093 dev_err(&oct->pci_dev->dev, "Feature change failed in core (ret: 0x%x)\n",
3094 ret);
3095 }
3096 return ret;
3097}
3098
3099/** \brief Net device fix features
3100 * @param netdev pointer to network device
3101 * @param request features requested
3102 * @returns updated features list
3103 */
3104static netdev_features_t liquidio_fix_features(struct net_device *netdev,
3105 netdev_features_t request)
3106{
3107 struct lio *lio = netdev_priv(netdev);
3108
3109 if ((request & NETIF_F_RXCSUM) &&
3110 !(lio->dev_capability & NETIF_F_RXCSUM))
3111 request &= ~NETIF_F_RXCSUM;
3112
3113 if ((request & NETIF_F_HW_CSUM) &&
3114 !(lio->dev_capability & NETIF_F_HW_CSUM))
3115 request &= ~NETIF_F_HW_CSUM;
3116
3117 if ((request & NETIF_F_TSO) && !(lio->dev_capability & NETIF_F_TSO))
3118 request &= ~NETIF_F_TSO;
3119
3120 if ((request & NETIF_F_TSO6) && !(lio->dev_capability & NETIF_F_TSO6))
3121 request &= ~NETIF_F_TSO6;
3122
3123 if ((request & NETIF_F_LRO) && !(lio->dev_capability & NETIF_F_LRO))
3124 request &= ~NETIF_F_LRO;
3125
3126 /*Disable LRO if RXCSUM is off */
3127 if (!(request & NETIF_F_RXCSUM) && (netdev->features & NETIF_F_LRO) &&
3128 (lio->dev_capability & NETIF_F_LRO))
3129 request &= ~NETIF_F_LRO;
3130
3131 return request;
3132}
3133
3134/** \brief Net device set features
3135 * @param netdev pointer to network device
3136 * @param features features to enable/disable
3137 */
3138static int liquidio_set_features(struct net_device *netdev,
3139 netdev_features_t features)
3140{
3141 struct lio *lio = netdev_priv(netdev);
3142
3143 if (!((netdev->features ^ features) & NETIF_F_LRO))
3144 return 0;
3145
3146 if ((features & NETIF_F_LRO) && (lio->dev_capability & NETIF_F_LRO))
0cece6c5
RV		 3147 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
3148 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed
RV		 3149 else if (!(features & NETIF_F_LRO) &&
3150 (lio->dev_capability & NETIF_F_LRO))
0cece6c5
RV		 3151 liquidio_set_feature(netdev, OCTNET_CMD_LRO_DISABLE,
3152 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed
RV		 3153
3154 return 0;
3155}
3156
3157static struct net_device_ops lionetdevops = {
3158 .ndo_open = liquidio_open,
3159 .ndo_stop = liquidio_stop,
3160 .ndo_start_xmit = liquidio_xmit,
3161 .ndo_get_stats = liquidio_get_stats,
3162 .ndo_set_mac_address = liquidio_set_mac,
3163 .ndo_set_rx_mode = liquidio_set_mcast_list,
3164 .ndo_tx_timeout = liquidio_tx_timeout,
63245f25
RV		 3165
3166 .ndo_vlan_rx_add_vid = liquidio_vlan_rx_add_vid,
3167 .ndo_vlan_rx_kill_vid = liquidio_vlan_rx_kill_vid,
f21fb3ed
RV		 3168 .ndo_change_mtu = liquidio_change_mtu,
3169 .ndo_do_ioctl = liquidio_ioctl,
3170 .ndo_fix_features = liquidio_fix_features,
3171 .ndo_set_features = liquidio_set_features,
3172};
3173
3174/** \brief Entry point for the liquidio module
3175 */
3176static int __init liquidio_init(void)
3177{
3178 int i;
3179 struct handshake *hs;
3180
3181 init_completion(&first_stage);
3182
3183 octeon_init_device_list(conf_type);
3184
3185 if (liquidio_init_pci())
3186 return -EINVAL;
3187
3188 wait_for_completion_timeout(&first_stage, msecs_to_jiffies(1000));
3189
3190 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3191 hs = &handshake[i];
3192 if (hs->pci_dev) {
3193 wait_for_completion(&hs->init);
3194 if (!hs->init_ok) {
3195 /* init handshake failed */
3196 dev_err(&hs->pci_dev->dev,
3197 "Failed to init device\n");
3198 liquidio_deinit_pci();
3199 return -EIO;
3200 }
3201 }
3202 }
3203
3204 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3205 hs = &handshake[i];
3206 if (hs->pci_dev) {
3207 wait_for_completion_timeout(&hs->started,
3208 msecs_to_jiffies(30000));
3209 if (!hs->started_ok) {
3210 /* starter handshake failed */
3211 dev_err(&hs->pci_dev->dev,
3212 "Firmware failed to start\n");
3213 liquidio_deinit_pci();
3214 return -EIO;
3215 }
3216 }
3217 }
3218
3219 return 0;
3220}
3221
5b173cf9 3222static int lio_nic_info(struct octeon_recv_info *recv_info, void *buf)
f21fb3ed
RV		 3223{
3224 struct octeon_device *oct = (struct octeon_device *)buf;
3225 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
0cece6c5 3226 int gmxport = 0;
f21fb3ed
RV		 3227 union oct_link_status *ls;
3228 int i;
3229
0cece6c5 3230 if (recv_pkt->buffer_size[0] != sizeof(*ls)) {
f21fb3ed
RV		 3231 dev_err(&oct->pci_dev->dev, "Malformed NIC_INFO, len=%d, ifidx=%d\n",
3232 recv_pkt->buffer_size[0],
0cece6c5 3233 recv_pkt->rh.r_nic_info.gmxport);
f21fb3ed
RV		 3234 goto nic_info_err;
3235 }
3236
0cece6c5 3237 gmxport = recv_pkt->rh.r_nic_info.gmxport;
f21fb3ed
RV		 3238 ls = (union oct_link_status *)get_rbd(recv_pkt->buffer_ptr[0]);
3239
3240 octeon_swap_8B_data((u64 *)ls, (sizeof(union oct_link_status)) >> 3);
0cece6c5
RV		 3241 for (i = 0; i < oct->ifcount; i++) {
3242 if (oct->props[i].gmxport == gmxport) {
3243 update_link_status(oct->props[i].netdev, ls);
3244 break;
3245 }
3246 }
f21fb3ed
RV		 3247
3248nic_info_err:
3249 for (i = 0; i < recv_pkt->buffer_count; i++)
3250 recv_buffer_free(recv_pkt->buffer_ptr[i]);
3251 octeon_free_recv_info(recv_info);
3252 return 0;
3253}
3254
3255/**
3256 * \brief Setup network interfaces
3257 * @param octeon_dev octeon device
3258 *
3259 * Called during init time for each device. It assumes the NIC
3260 * is already up and running. The link information for each
3261 * interface is passed in link_info.
3262 */
3263static int setup_nic_devices(struct octeon_device *octeon_dev)
3264{
3265 struct lio *lio = NULL;
3266 struct net_device *netdev;
3267 u8 mac[6], i, j;
3268 struct octeon_soft_command *sc;
3269 struct liquidio_if_cfg_context *ctx;
3270 struct liquidio_if_cfg_resp *resp;
3271 struct octdev_props *props;
26236fa9 3272 int retval, num_iqueues, num_oqueues;
f21fb3ed
RV		 3273 int num_cpus = num_online_cpus();
3274 union oct_nic_if_cfg if_cfg;
3275 unsigned int base_queue;
3276 unsigned int gmx_port_id;
3277 u32 resp_size, ctx_size;
0cece6c5 3278 u32 ifidx_or_pfnum;
f21fb3ed
RV		 3279
3280 /* This is to handle link status changes */
3281 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3282 OPCODE_NIC_INFO,
3283 lio_nic_info, octeon_dev);
3284
3285 /* REQTYPE_RESP_NET and REQTYPE_SOFT_COMMAND do not have free functions.
3286 * They are handled directly.
3287 */
3288 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET,
3289 free_netbuf);
3290
3291 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET_SG,
3292 free_netsgbuf);
3293
3294 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_RESP_NET_SG,
3295 free_netsgbuf_with_resp);
3296
3297 for (i = 0; i < octeon_dev->ifcount; i++) {
3298 resp_size = sizeof(struct liquidio_if_cfg_resp);
3299 ctx_size = sizeof(struct liquidio_if_cfg_context);
3300 sc = (struct octeon_soft_command *)
3301 octeon_alloc_soft_command(octeon_dev, 0,
3302 resp_size, ctx_size);
3303 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
3304 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
3305
3306 num_iqueues =
3307 CFG_GET_NUM_TXQS_NIC_IF(octeon_get_conf(octeon_dev), i);
3308 num_oqueues =
3309 CFG_GET_NUM_RXQS_NIC_IF(octeon_get_conf(octeon_dev), i);
3310 base_queue =
3311 CFG_GET_BASE_QUE_NIC_IF(octeon_get_conf(octeon_dev), i);
3312 gmx_port_id =
3313 CFG_GET_GMXID_NIC_IF(octeon_get_conf(octeon_dev), i);
0cece6c5 3314 ifidx_or_pfnum = i;
f21fb3ed
RV		 3315 if (num_iqueues > num_cpus)
3316 num_iqueues = num_cpus;
3317 if (num_oqueues > num_cpus)
3318 num_oqueues = num_cpus;
3319 dev_dbg(&octeon_dev->pci_dev->dev,
3320 "requesting config for interface %d, iqs %d, oqs %d\n",
0cece6c5 3321 ifidx_or_pfnum, num_iqueues, num_oqueues);
f21fb3ed
RV		 3322 ACCESS_ONCE(ctx->cond) = 0;
3323 ctx->octeon_id = lio_get_device_id(octeon_dev);
3324 init_waitqueue_head(&ctx->wc);
3325
3326 if_cfg.u64 = 0;
3327 if_cfg.s.num_iqueues = num_iqueues;
3328 if_cfg.s.num_oqueues = num_oqueues;
3329 if_cfg.s.base_queue = base_queue;
3330 if_cfg.s.gmx_port_id = gmx_port_id;
0cece6c5
RV		 3331
3332 sc->iq_no = 0;
3333
f21fb3ed 3334 octeon_prepare_soft_command(octeon_dev, sc, OPCODE_NIC,
0cece6c5 3335 OPCODE_NIC_IF_CFG, 0,
f21fb3ed
RV		 3336 if_cfg.u64, 0);
3337
3338 sc->callback = if_cfg_callback;
3339 sc->callback_arg = sc;
3340 sc->wait_time = 1000;
3341
3342 retval = octeon_send_soft_command(octeon_dev, sc);
ddc173a6 3343 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 3344 dev_err(&octeon_dev->pci_dev->dev,
3345 "iq/oq config failed status: %x\n",
3346 retval);
3347 /* Soft instr is freed by driver in case of failure. */
3348 goto setup_nic_dev_fail;
3349 }
3350
3351 /* Sleep on a wait queue till the cond flag indicates that the
3352 * response arrived or timed-out.
3353 */
3354 sleep_cond(&ctx->wc, &ctx->cond);
3355 retval = resp->status;
3356 if (retval) {
3357 dev_err(&octeon_dev->pci_dev->dev, "iq/oq config failed\n");
3358 goto setup_nic_dev_fail;
3359 }
3360
3361 octeon_swap_8B_data((u64 *)(&resp->cfg_info),
3362 (sizeof(struct liquidio_if_cfg_info)) >> 3);
3363
3364 num_iqueues = hweight64(resp->cfg_info.iqmask);
3365 num_oqueues = hweight64(resp->cfg_info.oqmask);
3366
3367 if (!(num_iqueues) || !(num_oqueues)) {
3368 dev_err(&octeon_dev->pci_dev->dev,
3369 "Got bad iqueues (%016llx) or oqueues (%016llx) from firmware.\n",
3370 resp->cfg_info.iqmask,
3371 resp->cfg_info.oqmask);
3372 goto setup_nic_dev_fail;
3373 }
3374 dev_dbg(&octeon_dev->pci_dev->dev,
3375 "interface %d, iqmask %016llx, oqmask %016llx, numiqueues %d, numoqueues %d\n",
3376 i, resp->cfg_info.iqmask, resp->cfg_info.oqmask,
3377 num_iqueues, num_oqueues);
3378 netdev = alloc_etherdev_mq(LIO_SIZE, num_iqueues);
3379
3380 if (!netdev) {
3381 dev_err(&octeon_dev->pci_dev->dev, "Device allocation failed\n");
3382 goto setup_nic_dev_fail;
3383 }
3384
0cece6c5 3385 SET_NETDEV_DEV(netdev, &octeon_dev->pci_dev->dev);
f21fb3ed
RV		 3386
3387 if (num_iqueues > 1)
3388 lionetdevops.ndo_select_queue = select_q;
3389
3390 /* Associate the routines that will handle different
3391 * netdev tasks.
3392 */
3393 netdev->netdev_ops = &lionetdevops;
3394
3395 lio = GET_LIO(netdev);
3396
3397 memset(lio, 0, sizeof(struct lio));
3398
0cece6c5
RV		 3399 lio->ifidx = ifidx_or_pfnum;
3400
3401 props = &octeon_dev->props[i];
3402 props->gmxport = resp->cfg_info.linfo.gmxport;
3403 props->netdev = netdev;
f21fb3ed
RV		 3404
3405 lio->linfo.num_rxpciq = num_oqueues;
3406 lio->linfo.num_txpciq = num_iqueues;
f21fb3ed 3407 for (j = 0; j < num_oqueues; j++) {
26236fa9
RV		 3408 lio->linfo.rxpciq[j].u64 =
3409 resp->cfg_info.linfo.rxpciq[j].u64;
f21fb3ed 3410 }
f21fb3ed 3411 for (j = 0; j < num_iqueues; j++) {
26236fa9
RV		 3412 lio->linfo.txpciq[j].u64 =
3413 resp->cfg_info.linfo.txpciq[j].u64;
f21fb3ed
RV		 3414 }
3415 lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr;
3416 lio->linfo.gmxport = resp->cfg_info.linfo.gmxport;
3417 lio->linfo.link.u64 = resp->cfg_info.linfo.link.u64;
3418
3419 lio->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3420
3421 lio->dev_capability = NETIF_F_HIGHDMA
0cece6c5
RV		 3422 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3423 | NETIF_F_SG | NETIF_F_RXCSUM
3424 | NETIF_F_GRO
3425 | NETIF_F_TSO | NETIF_F_TSO6
3426 | NETIF_F_LRO;
f21fb3ed
RV		 3427 netif_set_gso_max_size(netdev, OCTNIC_GSO_MAX_SIZE);
3428
f21fb3ed 3429 netdev->vlan_features = lio->dev_capability;
0da0b77c 3430 /* Add any unchangeable hw features */
63245f25
RV		 3431 lio->dev_capability |= NETIF_F_HW_VLAN_CTAG_FILTER |
3432 NETIF_F_HW_VLAN_CTAG_RX |
0da0b77c
RV		 3433 NETIF_F_HW_VLAN_CTAG_TX;
3434
3435 netdev->features = (lio->dev_capability & ~NETIF_F_LRO);
f21fb3ed
RV		 3436
3437 netdev->hw_features = lio->dev_capability;
0da0b77c
RV		 3438 /*HW_VLAN_RX and HW_VLAN_FILTER is always on*/
3439 netdev->hw_features = netdev->hw_features &
3440 ~NETIF_F_HW_VLAN_CTAG_RX;
f21fb3ed
RV		 3441
3442 /* Point to the properties for octeon device to which this
3443 * interface belongs.
3444 */
3445 lio->oct_dev = octeon_dev;
3446 lio->octprops = props;
3447 lio->netdev = netdev;
f21fb3ed
RV		 3448
3449 dev_dbg(&octeon_dev->pci_dev->dev,
3450 "if%d gmx: %d hw_addr: 0x%llx\n", i,
3451 lio->linfo.gmxport, CVM_CAST64(lio->linfo.hw_addr));
3452
3453 /* 64-bit swap required on LE machines */
3454 octeon_swap_8B_data(&lio->linfo.hw_addr, 1);
3455 for (j = 0; j < 6; j++)
3456 mac[j] = *((u8 *)(((u8 *)&lio->linfo.hw_addr) + 2 + j));
3457
3458 /* Copy MAC Address to OS network device structure */
3459
3460 ether_addr_copy(netdev->dev_addr, mac);
3461
26236fa9
RV		 3462 /* By default all interfaces on a single Octeon uses the same
3463 * tx and rx queues
3464 */
3465 lio->txq = lio->linfo.txpciq[0].s.q_no;
3466 lio->rxq = lio->linfo.rxpciq[0].s.q_no;
0cece6c5 3467 if (setup_io_queues(octeon_dev, i)) {
f21fb3ed
RV		 3468 dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n");
3469 goto setup_nic_dev_fail;
3470 }
3471
3472 ifstate_set(lio, LIO_IFSTATE_DROQ_OPS);
3473
f21fb3ed
RV		 3474 lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq);
3475 lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq);
3476
fcd2b5e3 3477 if (setup_glists(octeon_dev, lio, num_iqueues)) {
f21fb3ed
RV		 3478 dev_err(&octeon_dev->pci_dev->dev,
3479 "Gather list allocation failed\n");
3480 goto setup_nic_dev_fail;
3481 }
3482
3483 /* Register ethtool support */
3484 liquidio_set_ethtool_ops(netdev);
3485
0cece6c5
RV		 3486 if (netdev->features & NETIF_F_LRO)
3487 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
3488 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed 3489
63245f25
RV		 3490 liquidio_set_feature(netdev, OCTNET_CMD_ENABLE_VLAN_FILTER, 0);
3491
f21fb3ed 3492 if ((debug != -1) && (debug & NETIF_MSG_HW))
63245f25
RV		 3493 liquidio_set_feature(netdev,
3494 OCTNET_CMD_VERBOSE_ENABLE, 0);
f21fb3ed
RV		 3495
3496 /* Register the network device with the OS */
3497 if (register_netdev(netdev)) {
3498 dev_err(&octeon_dev->pci_dev->dev, "Device registration failed\n");
3499 goto setup_nic_dev_fail;
3500 }
3501
3502 dev_dbg(&octeon_dev->pci_dev->dev,
3503 "Setup NIC ifidx:%d mac:%02x%02x%02x%02x%02x%02x\n",
3504 i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
3505 netif_carrier_off(netdev);
0cece6c5 3506 lio->link_changes++;
f21fb3ed
RV		 3507
3508 ifstate_set(lio, LIO_IFSTATE_REGISTERED);
3509
3510 dev_dbg(&octeon_dev->pci_dev->dev,
3511 "NIC ifidx:%d Setup successful\n", i);
3512
3513 octeon_free_soft_command(octeon_dev, sc);
3514 }
3515
3516 return 0;
3517
3518setup_nic_dev_fail:
3519
3520 octeon_free_soft_command(octeon_dev, sc);
3521
3522 while (i--) {
3523 dev_err(&octeon_dev->pci_dev->dev,
3524 "NIC ifidx:%d Setup failed\n", i);
3525 liquidio_destroy_nic_device(octeon_dev, i);
3526 }
3527 return -ENODEV;
3528}
3529
3530/**
3531 * \brief initialize the NIC
3532 * @param oct octeon device
3533 *
3534 * This initialization routine is called once the Octeon device application is
3535 * up and running
3536 */
3537static int liquidio_init_nic_module(struct octeon_device *oct)
3538{
3539 struct oct_intrmod_cfg *intrmod_cfg;
0cece6c5 3540 int i, retval = 0;
f21fb3ed
RV		 3541 int num_nic_ports = CFG_GET_NUM_NIC_PORTS(octeon_get_conf(oct));
3542
3543 dev_dbg(&oct->pci_dev->dev, "Initializing network interfaces\n");
3544
3545 /* only default iq and oq were initialized
3546 * initialize the rest as well
3547 */
3548 /* run port_config command for each port */
3549 oct->ifcount = num_nic_ports;
3550
3551 memset(oct->props, 0,
3552 sizeof(struct octdev_props) * num_nic_ports);
3553
0cece6c5
RV		 3554 for (i = 0; i < MAX_OCTEON_LINKS; i++)
3555 oct->props[i].gmxport = -1;
3556
f21fb3ed
RV		 3557 retval = setup_nic_devices(oct);
3558 if (retval) {
3559 dev_err(&oct->pci_dev->dev, "Setup NIC devices failed\n");
3560 goto octnet_init_failure;
3561 }
3562
3563 liquidio_ptp_init(oct);
3564
3565 /* Initialize interrupt moderation params */
3566 intrmod_cfg = &((struct octeon_device *)oct)->intrmod;
3567 intrmod_cfg->intrmod_enable = 1;
3568 intrmod_cfg->intrmod_check_intrvl = LIO_INTRMOD_CHECK_INTERVAL;
3569 intrmod_cfg->intrmod_maxpkt_ratethr = LIO_INTRMOD_MAXPKT_RATETHR;
3570 intrmod_cfg->intrmod_minpkt_ratethr = LIO_INTRMOD_MINPKT_RATETHR;
3571 intrmod_cfg->intrmod_maxcnt_trigger = LIO_INTRMOD_MAXCNT_TRIGGER;
3572 intrmod_cfg->intrmod_maxtmr_trigger = LIO_INTRMOD_MAXTMR_TRIGGER;
3573 intrmod_cfg->intrmod_mintmr_trigger = LIO_INTRMOD_MINTMR_TRIGGER;
3574 intrmod_cfg->intrmod_mincnt_trigger = LIO_INTRMOD_MINCNT_TRIGGER;
3575
3576 dev_dbg(&oct->pci_dev->dev, "Network interfaces ready\n");
3577
3578 return retval;
3579
3580octnet_init_failure:
3581
3582 oct->ifcount = 0;
3583
3584 return retval;
3585}
3586
3587/**
3588 * \brief starter callback that invokes the remaining initialization work after
3589 * the NIC is up and running.
3590 * @param octptr work struct work_struct
3591 */
3592static void nic_starter(struct work_struct *work)
3593{
3594 struct octeon_device *oct;
3595 struct cavium_wk *wk = (struct cavium_wk *)work;
3596
3597 oct = (struct octeon_device *)wk->ctxptr;
3598
3599 if (atomic_read(&oct->status) == OCT_DEV_RUNNING)
3600 return;
3601
3602 /* If the status of the device is CORE_OK, the core
3603 * application has reported its application type. Call
3604 * any registered handlers now and move to the RUNNING
3605 * state.
3606 */
3607 if (atomic_read(&oct->status) != OCT_DEV_CORE_OK) {
3608 schedule_delayed_work(&oct->nic_poll_work.work,
3609 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
3610 return;
3611 }
3612
3613 atomic_set(&oct->status, OCT_DEV_RUNNING);
3614
3615 if (oct->app_mode && oct->app_mode == CVM_DRV_NIC_APP) {
3616 dev_dbg(&oct->pci_dev->dev, "Starting NIC module\n");
3617
3618 if (liquidio_init_nic_module(oct))
3619 dev_err(&oct->pci_dev->dev, "NIC initialization failed\n");
3620 else
3621 handshake[oct->octeon_id].started_ok = 1;
3622 } else {
3623 dev_err(&oct->pci_dev->dev,
3624 "Unexpected application running on NIC (%d). Check firmware.\n",
3625 oct->app_mode);
3626 }
3627
3628 complete(&handshake[oct->octeon_id].started);
3629}
3630
3631/**
3632 * \brief Device initialization for each Octeon device that is probed
3633 * @param octeon_dev octeon device
3634 */
3635static int octeon_device_init(struct octeon_device *octeon_dev)
3636{
3637 int j, ret;
3638 struct octeon_device_priv *oct_priv =
3639 (struct octeon_device_priv *)octeon_dev->priv;
3640 atomic_set(&octeon_dev->status, OCT_DEV_BEGIN_STATE);
3641
3642 /* Enable access to the octeon device and make its DMA capability
3643 * known to the OS.
3644 */
3645 if (octeon_pci_os_setup(octeon_dev))
3646 return 1;
3647
3648 /* Identify the Octeon type and map the BAR address space. */
3649 if (octeon_chip_specific_setup(octeon_dev)) {
3650 dev_err(&octeon_dev->pci_dev->dev, "Chip specific setup failed\n");
3651 return 1;
3652 }
3653
3654 atomic_set(&octeon_dev->status, OCT_DEV_PCI_MAP_DONE);
3655
3656 octeon_dev->app_mode = CVM_DRV_INVALID_APP;
3657
3658 /* Do a soft reset of the Octeon device. */
3659 if (octeon_dev->fn_list.soft_reset(octeon_dev))
3660 return 1;
3661
3662 /* Initialize the dispatch mechanism used to push packets arriving on
3663 * Octeon Output queues.
3664 */
3665 if (octeon_init_dispatch_list(octeon_dev))
3666 return 1;
3667
3668 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3669 OPCODE_NIC_CORE_DRV_ACTIVE,
3670 octeon_core_drv_init,
3671 octeon_dev);
3672
3673 INIT_DELAYED_WORK(&octeon_dev->nic_poll_work.work, nic_starter);
3674 octeon_dev->nic_poll_work.ctxptr = (void *)octeon_dev;
3675 schedule_delayed_work(&octeon_dev->nic_poll_work.work,
3676 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
3677
3678 atomic_set(&octeon_dev->status, OCT_DEV_DISPATCH_INIT_DONE);
3679
3680 octeon_set_io_queues_off(octeon_dev);
3681
3682 /* Setup the data structures that manage this Octeon's Input queues. */
3683 if (octeon_setup_instr_queues(octeon_dev)) {
3684 dev_err(&octeon_dev->pci_dev->dev,
3685 "instruction queue initialization failed\n");
3686 /* On error, release any previously allocated queues */
3687 for (j = 0; j < octeon_dev->num_iqs; j++)
3688 octeon_delete_instr_queue(octeon_dev, j);
3689 return 1;
3690 }
3691 atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE);
3692
3693 /* Initialize soft command buffer pool
3694 */
3695 if (octeon_setup_sc_buffer_pool(octeon_dev)) {
3696 dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n");
3697 return 1;
3698 }
3699 atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
3700
3701 /* Initialize lists to manage the requests of different types that
3702 * arrive from user & kernel applications for this octeon device.
3703 */
3704 if (octeon_setup_response_list(octeon_dev)) {
3705 dev_err(&octeon_dev->pci_dev->dev, "Response list allocation failed\n");
3706 return 1;
3707 }
3708 atomic_set(&octeon_dev->status, OCT_DEV_RESP_LIST_INIT_DONE);
3709
3710 if (octeon_setup_output_queues(octeon_dev)) {
3711 dev_err(&octeon_dev->pci_dev->dev, "Output queue initialization failed\n");
3712 /* Release any previously allocated queues */
3713 for (j = 0; j < octeon_dev->num_oqs; j++)
3714 octeon_delete_droq(octeon_dev, j);
3715 }
3716
3717 atomic_set(&octeon_dev->status, OCT_DEV_DROQ_INIT_DONE);
3718
3719 /* The input and output queue registers were setup earlier (the queues
3720 * were not enabled). Any additional registers that need to be
3721 * programmed should be done now.
3722 */
3723 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
3724 if (ret) {
3725 dev_err(&octeon_dev->pci_dev->dev,
3726 "Failed to configure device registers\n");
3727 return ret;
3728 }
3729
3730 /* Initialize the tasklet that handles output queue packet processing.*/
3731 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing droq tasklet\n");
3732 tasklet_init(&oct_priv->droq_tasklet, octeon_droq_bh,
3733 (unsigned long)octeon_dev);
3734
3735 /* Setup the interrupt handler and record the INT SUM register address
3736 */
3737 octeon_setup_interrupt(octeon_dev);
3738
3739 /* Enable Octeon device interrupts */
3740 octeon_dev->fn_list.enable_interrupt(octeon_dev->chip);
3741
3742 /* Enable the input and output queues for this Octeon device */
3743 octeon_dev->fn_list.enable_io_queues(octeon_dev);
3744
3745 atomic_set(&octeon_dev->status, OCT_DEV_IO_QUEUES_DONE);
3746
3747 dev_dbg(&octeon_dev->pci_dev->dev, "Waiting for DDR initialization...\n");
3748
3749 if (ddr_timeout == 0) {
3750 dev_info(&octeon_dev->pci_dev->dev,
3751 "WAITING. Set ddr_timeout to non-zero value to proceed with initialization.\n");
3752 }
3753
3754 schedule_timeout_uninterruptible(HZ * LIO_RESET_SECS);
3755
3756 /* Wait for the octeon to initialize DDR after the soft-reset. */
3757 ret = octeon_wait_for_ddr_init(octeon_dev, &ddr_timeout);
3758 if (ret) {
3759 dev_err(&octeon_dev->pci_dev->dev,
3760 "DDR not initialized. Please confirm that board is configured to boot from Flash, ret: %d\n",
3761 ret);
3762 return 1;
3763 }
3764
3765 if (octeon_wait_for_bootloader(octeon_dev, 1000) != 0) {
3766 dev_err(&octeon_dev->pci_dev->dev, "Board not responding\n");
3767 return 1;
3768 }
3769
3770 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing consoles\n");
3771 ret = octeon_init_consoles(octeon_dev);
3772 if (ret) {
3773 dev_err(&octeon_dev->pci_dev->dev, "Could not access board consoles\n");
3774 return 1;
3775 }
3776 ret = octeon_add_console(octeon_dev, 0);
3777 if (ret) {
3778 dev_err(&octeon_dev->pci_dev->dev, "Could not access board console\n");
3779 return 1;
3780 }
3781
3782 atomic_set(&octeon_dev->status, OCT_DEV_CONSOLE_INIT_DONE);
3783
3784 dev_dbg(&octeon_dev->pci_dev->dev, "Loading firmware\n");
3785 ret = load_firmware(octeon_dev);
3786 if (ret) {
3787 dev_err(&octeon_dev->pci_dev->dev, "Could not load firmware to board\n");
3788 return 1;
3789 }
3790
3791 handshake[octeon_dev->octeon_id].init_ok = 1;
3792 complete(&handshake[octeon_dev->octeon_id].init);
3793
3794 atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK);
3795
3796 /* Send Credit for Octeon Output queues. Credits are always sent after
3797 * the output queue is enabled.
3798 */
3799 for (j = 0; j < octeon_dev->num_oqs; j++)
3800 writel(octeon_dev->droq[j]->max_count,
3801 octeon_dev->droq[j]->pkts_credit_reg);
3802
3803 /* Packets can start arriving on the output queues from this point. */
3804
3805 return 0;
3806}
3807
3808/**
3809 * \brief Exits the module
3810 */
3811static void __exit liquidio_exit(void)
3812{
3813 liquidio_deinit_pci();
3814
3815 pr_info("LiquidIO network module is now unloaded\n");
3816}
3817
3818module_init(liquidio_init);
3819module_exit(liquidio_exit);
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