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netvsc: Initialize all channel related state prior to opening the channel
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / cavium / liquidio / lio_main.c
CommitLineData
f21fb3ed 1/**********************************************************************
50579d3d
RV		 2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
e3bfc6e7 18#include <linux/module.h>
282ccf6e 19#include <linux/interrupt.h>
f21fb3ed 20#include <linux/pci.h>
f21fb3ed 21#include <linux/firmware.h>
01fb237a 22#include <net/vxlan.h>
9ff1a9ba 23#include <linux/kthread.h>
f21fb3ed
RV		 24#include "liquidio_common.h"
25#include "octeon_droq.h"
26#include "octeon_iq.h"
27#include "response_manager.h"
28#include "octeon_device.h"
29#include "octeon_nic.h"
30#include "octeon_main.h"
31#include "octeon_network.h"
32#include "cn66xx_regs.h"
33#include "cn66xx_device.h"
f21fb3ed 34#include "cn68xx_device.h"
72c00912 35#include "cn23xx_pf_device.h"
f21fb3ed
RV		 36#include "liquidio_image.h"
37
38MODULE_AUTHOR("Cavium Networks, <support@cavium.com>");
39MODULE_DESCRIPTION("Cavium LiquidIO Intelligent Server Adapter Driver");
40MODULE_LICENSE("GPL");
41MODULE_VERSION(LIQUIDIO_VERSION);
42MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210SV_NAME LIO_FW_NAME_SUFFIX);
43MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210NV_NAME LIO_FW_NAME_SUFFIX);
44MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_410NV_NAME LIO_FW_NAME_SUFFIX);
c865cdf1 45MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_23XX_NAME LIO_FW_NAME_SUFFIX);
f21fb3ed
RV		 46
47static int ddr_timeout = 10000;
48module_param(ddr_timeout, int, 0644);
49MODULE_PARM_DESC(ddr_timeout,
50 "Number of milliseconds to wait for DDR initialization. 0 waits for ddr_timeout to be set to non-zero value before starting to check");
51
f21fb3ed
RV		 52#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
53
54static int debug = -1;
55module_param(debug, int, 0644);
56MODULE_PARM_DESC(debug, "NETIF_MSG debug bits");
57
58static char fw_type[LIO_MAX_FW_TYPE_LEN];
59module_param_string(fw_type, fw_type, sizeof(fw_type), 0000);
60MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded. Default \"nic\"");
61
a5b37888
RV		 62static int ptp_enable = 1;
63
f21fb3ed
RV		 64/* Polling interval for determining when NIC application is alive */
65#define LIQUIDIO_STARTER_POLL_INTERVAL_MS 100
66
67/* runtime link query interval */
68#define LIQUIDIO_LINK_QUERY_INTERVAL_MS 1000
69
70struct liquidio_if_cfg_context {
71 int octeon_id;
72
73 wait_queue_head_t wc;
74
75 int cond;
76};
77
78struct liquidio_if_cfg_resp {
79 u64 rh;
80 struct liquidio_if_cfg_info cfg_info;
81 u64 status;
82};
83
afdf841f
RV		 84struct liquidio_rx_ctl_context {
85 int octeon_id;
86
87 wait_queue_head_t wc;
88
89 int cond;
90};
91
f21fb3ed
RV		 92struct oct_link_status_resp {
93 u64 rh;
94 struct oct_link_info link_info;
95 u64 status;
96};
97
98struct oct_timestamp_resp {
99 u64 rh;
100 u64 timestamp;
101 u64 status;
102};
103
104#define OCT_TIMESTAMP_RESP_SIZE (sizeof(struct oct_timestamp_resp))
105
106union tx_info {
107 u64 u64;
108 struct {
109#ifdef __BIG_ENDIAN_BITFIELD
110 u16 gso_size;
111 u16 gso_segs;
112 u32 reserved;
113#else
114 u32 reserved;
115 u16 gso_segs;
116 u16 gso_size;
117#endif
118 } s;
119};
120
121/** Octeon device properties to be used by the NIC module.
122 * Each octeon device in the system will be represented
123 * by this structure in the NIC module.
124 */
125
126#define OCTNIC_MAX_SG (MAX_SKB_FRAGS)
127
128#define OCTNIC_GSO_MAX_HEADER_SIZE 128
72c00912
RV		 129#define OCTNIC_GSO_MAX_SIZE \
130 (CN23XX_DEFAULT_INPUT_JABBER - OCTNIC_GSO_MAX_HEADER_SIZE)
f21fb3ed
RV		 131
132/** Structure of a node in list of gather components maintained by
133 * NIC driver for each network device.
134 */
135struct octnic_gather {
136 /** List manipulation. Next and prev pointers. */
137 struct list_head list;
138
139 /** Size of the gather component at sg in bytes. */
140 int sg_size;
141
142 /** Number of bytes that sg was adjusted to make it 8B-aligned. */
143 int adjust;
144
145 /** Gather component that can accommodate max sized fragment list
146 * received from the IP layer.
147 */
148 struct octeon_sg_entry *sg;
fcd2b5e3 149
67e303e0 150 dma_addr_t sg_dma_ptr;
f21fb3ed
RV		 151};
152
f21fb3ed
RV		 153struct handshake {
154 struct completion init;
155 struct completion started;
156 struct pci_dev *pci_dev;
157 int init_ok;
158 int started_ok;
159};
160
161struct octeon_device_priv {
162 /** Tasklet structures for this device. */
163 struct tasklet_struct droq_tasklet;
164 unsigned long napi_mask;
165};
166
ca6139ff
RV		 167#ifdef CONFIG_PCI_IOV
168static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs);
169#endif
170
f21fb3ed 171static int octeon_device_init(struct octeon_device *);
32581245 172static int liquidio_stop(struct net_device *netdev);
f21fb3ed
RV		 173static void liquidio_remove(struct pci_dev *pdev);
174static int liquidio_probe(struct pci_dev *pdev,
175 const struct pci_device_id *ent);
bb54be58
FM		 176static int liquidio_set_vf_link_state(struct net_device *netdev, int vfidx,
177 int linkstate);
f21fb3ed
RV		 178
179static struct handshake handshake[MAX_OCTEON_DEVICES];
180static struct completion first_stage;
181
5b173cf9 182static void octeon_droq_bh(unsigned long pdev)
f21fb3ed
RV		 183{
184 int q_no;
185 int reschedule = 0;
186 struct octeon_device *oct = (struct octeon_device *)pdev;
187 struct octeon_device_priv *oct_priv =
188 (struct octeon_device_priv *)oct->priv;
189
63da8404 190 for (q_no = 0; q_no < MAX_OCTEON_OUTPUT_QUEUES(oct); q_no++) {
763185a3 191 if (!(oct->io_qmask.oq & BIT_ULL(q_no)))
f21fb3ed
RV		 192 continue;
193 reschedule |= octeon_droq_process_packets(oct, oct->droq[q_no],
194 MAX_PACKET_BUDGET);
cd8b1eb4 195 lio_enable_irq(oct->droq[q_no], NULL);
5b07aee1
RV		 196
197 if (OCTEON_CN23XX_PF(oct) && oct->msix_on) {
198 /* set time and cnt interrupt thresholds for this DROQ
199 * for NAPI
200 */
201 int adjusted_q_no = q_no + oct->sriov_info.pf_srn;
202
203 octeon_write_csr64(
204 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(adjusted_q_no),
205 0x5700000040ULL);
206 octeon_write_csr64(
207 oct, CN23XX_SLI_OQ_PKTS_SENT(adjusted_q_no), 0);
208 }
f21fb3ed
RV		 209 }
210
211 if (reschedule)
212 tasklet_schedule(&oct_priv->droq_tasklet);
213}
214
5b173cf9 215static int lio_wait_for_oq_pkts(struct octeon_device *oct)
f21fb3ed
RV		 216{
217 struct octeon_device_priv *oct_priv =
218 (struct octeon_device_priv *)oct->priv;
219 int retry = 100, pkt_cnt = 0, pending_pkts = 0;
220 int i;
221
222 do {
223 pending_pkts = 0;
224
63da8404 225 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
763185a3 226 if (!(oct->io_qmask.oq & BIT_ULL(i)))
f21fb3ed 227 continue;
a7d5a3dc 228 pkt_cnt += octeon_droq_check_hw_for_pkts(oct->droq[i]);
f21fb3ed
RV		 229 }
230 if (pkt_cnt > 0) {
231 pending_pkts += pkt_cnt;
232 tasklet_schedule(&oct_priv->droq_tasklet);
233 }
234 pkt_cnt = 0;
235 schedule_timeout_uninterruptible(1);
236
237 } while (retry-- && pending_pkts);
238
239 return pkt_cnt;
240}
241
f21fb3ed
RV		 242/**
243 * \brief Forces all IO queues off on a given device
244 * @param oct Pointer to Octeon device
245 */
246static void force_io_queues_off(struct octeon_device *oct)
247{
248 if ((oct->chip_id == OCTEON_CN66XX) ||
249 (oct->chip_id == OCTEON_CN68XX)) {
250 /* Reset the Enable bits for Input Queues. */
251 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
252
253 /* Reset the Enable bits for Output Queues. */
254 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
255 }
256}
257
258/**
259 * \brief wait for all pending requests to complete
260 * @param oct Pointer to Octeon device
261 *
262 * Called during shutdown sequence
263 */
264static int wait_for_pending_requests(struct octeon_device *oct)
265{
266 int i, pcount = 0;
267
268 for (i = 0; i < 100; i++) {
269 pcount =
270 atomic_read(&oct->response_list
271 [OCTEON_ORDERED_SC_LIST].pending_req_count);
272 if (pcount)
273 schedule_timeout_uninterruptible(HZ / 10);
9a96bde4 274 else
f21fb3ed
RV		 275 break;
276 }
277
278 if (pcount)
279 return 1;
280
281 return 0;
282}
283
284/**
285 * \brief Cause device to go quiet so it can be safely removed/reset/etc
286 * @param oct Pointer to Octeon device
287 */
288static inline void pcierror_quiesce_device(struct octeon_device *oct)
289{
290 int i;
291
292 /* Disable the input and output queues now. No more packets will
293 * arrive from Octeon, but we should wait for all packet processing
294 * to finish.
295 */
296 force_io_queues_off(oct);
297
298 /* To allow for in-flight requests */
299 schedule_timeout_uninterruptible(100);
300
301 if (wait_for_pending_requests(oct))
302 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
303
304 /* Force all requests waiting to be fetched by OCTEON to complete. */
63da8404 305 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
f21fb3ed
RV		 306 struct octeon_instr_queue *iq;
307
763185a3 308 if (!(oct->io_qmask.iq & BIT_ULL(i)))
f21fb3ed
RV		 309 continue;
310 iq = oct->instr_queue[i];
311
312 if (atomic_read(&iq->instr_pending)) {
313 spin_lock_bh(&iq->lock);
314 iq->fill_cnt = 0;
315 iq->octeon_read_index = iq->host_write_index;
316 iq->stats.instr_processed +=
317 atomic_read(&iq->instr_pending);
9a96bde4 318 lio_process_iq_request_list(oct, iq, 0);
f21fb3ed
RV		 319 spin_unlock_bh(&iq->lock);
320 }
321 }
322
323 /* Force all pending ordered list requests to time out. */
324 lio_process_ordered_list(oct, 1);
325
326 /* We do not need to wait for output queue packets to be processed. */
327}
328
329/**
330 * \brief Cleanup PCI AER uncorrectable error status
331 * @param dev Pointer to PCI device
332 */
333static void cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
334{
335 int pos = 0x100;
336 u32 status, mask;
337
338 pr_info("%s :\n", __func__);
339
340 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
341 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
342 if (dev->error_state == pci_channel_io_normal)
343 status &= ~mask; /* Clear corresponding nonfatal bits */
344 else
345 status &= mask; /* Clear corresponding fatal bits */
346 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
347}
348
349/**
350 * \brief Stop all PCI IO to a given device
351 * @param dev Pointer to Octeon device
352 */
353static void stop_pci_io(struct octeon_device *oct)
354{
355 /* No more instructions will be forwarded. */
356 atomic_set(&oct->status, OCT_DEV_IN_RESET);
357
358 pci_disable_device(oct->pci_dev);
359
360 /* Disable interrupts */
5b07aee1 361 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
f21fb3ed
RV		 362
363 pcierror_quiesce_device(oct);
364
365 /* Release the interrupt line */
366 free_irq(oct->pci_dev->irq, oct);
367
368 if (oct->flags & LIO_FLAG_MSI_ENABLED)
369 pci_disable_msi(oct->pci_dev);
370
371 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
372 lio_get_state_string(&oct->status));
373
f21fb3ed
RV		 374 /* making it a common function for all OCTEON models */
375 cleanup_aer_uncorrect_error_status(oct->pci_dev);
376}
377
378/**
379 * \brief called when PCI error is detected
380 * @param pdev Pointer to PCI device
381 * @param state The current pci connection state
382 *
383 * This function is called after a PCI bus error affecting
384 * this device has been detected.
385 */
386static pci_ers_result_t liquidio_pcie_error_detected(struct pci_dev *pdev,
387 pci_channel_state_t state)
388{
389 struct octeon_device *oct = pci_get_drvdata(pdev);
390
391 /* Non-correctable Non-fatal errors */
392 if (state == pci_channel_io_normal) {
393 dev_err(&oct->pci_dev->dev, "Non-correctable non-fatal error reported:\n");
394 cleanup_aer_uncorrect_error_status(oct->pci_dev);
395 return PCI_ERS_RESULT_CAN_RECOVER;
396 }
397
398 /* Non-correctable Fatal errors */
399 dev_err(&oct->pci_dev->dev, "Non-correctable FATAL reported by PCI AER driver\n");
400 stop_pci_io(oct);
401
402 /* Always return a DISCONNECT. There is no support for recovery but only
403 * for a clean shutdown.
404 */
405 return PCI_ERS_RESULT_DISCONNECT;
406}
407
408/**
409 * \brief mmio handler
410 * @param pdev Pointer to PCI device
411 */
a7d5a3dc
RV		 412static pci_ers_result_t liquidio_pcie_mmio_enabled(
413 struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 414{
415 /* We should never hit this since we never ask for a reset for a Fatal
416 * Error. We always return DISCONNECT in io_error above.
417 * But play safe and return RECOVERED for now.
418 */
419 return PCI_ERS_RESULT_RECOVERED;
420}
421
422/**
423 * \brief called after the pci bus has been reset.
424 * @param pdev Pointer to PCI device
425 *
426 * Restart the card from scratch, as if from a cold-boot. Implementation
427 * resembles the first-half of the octeon_resume routine.
428 */
a7d5a3dc
RV		 429static pci_ers_result_t liquidio_pcie_slot_reset(
430 struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 431{
432 /* We should never hit this since we never ask for a reset for a Fatal
433 * Error. We always return DISCONNECT in io_error above.
434 * But play safe and return RECOVERED for now.
435 */
436 return PCI_ERS_RESULT_RECOVERED;
437}
438
439/**
440 * \brief called when traffic can start flowing again.
441 * @param pdev Pointer to PCI device
442 *
443 * This callback is called when the error recovery driver tells us that
444 * its OK to resume normal operation. Implementation resembles the
445 * second-half of the octeon_resume routine.
446 */
a7d5a3dc 447static void liquidio_pcie_resume(struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 448{
449 /* Nothing to be done here. */
450}
451
452#ifdef CONFIG_PM
453/**
454 * \brief called when suspending
455 * @param pdev Pointer to PCI device
456 * @param state state to suspend to
457 */
a7d5a3dc
RV		 458static int liquidio_suspend(struct pci_dev *pdev __attribute__((unused)),
459 pm_message_t state __attribute__((unused)))
f21fb3ed
RV		 460{
461 return 0;
462}
463
464/**
465 * \brief called when resuming
466 * @param pdev Pointer to PCI device
467 */
a7d5a3dc 468static int liquidio_resume(struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 469{
470 return 0;
471}
472#endif
473
474/* For PCI-E Advanced Error Recovery (AER) Interface */
166e2362 475static const struct pci_error_handlers liquidio_err_handler = {
f21fb3ed
RV		 476 .error_detected = liquidio_pcie_error_detected,
477 .mmio_enabled = liquidio_pcie_mmio_enabled,
478 .slot_reset = liquidio_pcie_slot_reset,
479 .resume = liquidio_pcie_resume,
480};
481
482static const struct pci_device_id liquidio_pci_tbl[] = {
483 { /* 68xx */
484 PCI_VENDOR_ID_CAVIUM, 0x91, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
485 },
486 { /* 66xx */
487 PCI_VENDOR_ID_CAVIUM, 0x92, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
488 },
e86b1ab6
RV		 489 { /* 23xx pf */
490 PCI_VENDOR_ID_CAVIUM, 0x9702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
491 },
f21fb3ed
RV		 492 {
493 0, 0, 0, 0, 0, 0, 0
494 }
495};
496MODULE_DEVICE_TABLE(pci, liquidio_pci_tbl);
497
498static struct pci_driver liquidio_pci_driver = {
499 .name = "LiquidIO",
500 .id_table = liquidio_pci_tbl,
501 .probe = liquidio_probe,
502 .remove = liquidio_remove,
503 .err_handler = &liquidio_err_handler, /* For AER */
504
505#ifdef CONFIG_PM
506 .suspend = liquidio_suspend,
507 .resume = liquidio_resume,
508#endif
ca6139ff
RV		 509#ifdef CONFIG_PCI_IOV
510 .sriov_configure = liquidio_enable_sriov,
511#endif
f21fb3ed
RV		 512};
513
514/**
515 * \brief register PCI driver
516 */
517static int liquidio_init_pci(void)
518{
519 return pci_register_driver(&liquidio_pci_driver);
520}
521
522/**
523 * \brief unregister PCI driver
524 */
525static void liquidio_deinit_pci(void)
526{
527 pci_unregister_driver(&liquidio_pci_driver);
528}
529
f21fb3ed
RV		 530/**
531 * \brief Stop Tx queues
532 * @param netdev network device
533 */
534static inline void txqs_stop(struct net_device *netdev)
535{
536 if (netif_is_multiqueue(netdev)) {
537 int i;
538
539 for (i = 0; i < netdev->num_tx_queues; i++)
540 netif_stop_subqueue(netdev, i);
541 } else {
542 netif_stop_queue(netdev);
543 }
544}
545
546/**
547 * \brief Start Tx queues
548 * @param netdev network device
549 */
550static inline void txqs_start(struct net_device *netdev)
551{
552 if (netif_is_multiqueue(netdev)) {
553 int i;
554
555 for (i = 0; i < netdev->num_tx_queues; i++)
556 netif_start_subqueue(netdev, i);
557 } else {
558 netif_start_queue(netdev);
559 }
560}
561
562/**
563 * \brief Wake Tx queues
564 * @param netdev network device
565 */
566static inline void txqs_wake(struct net_device *netdev)
567{
1f164717
RV		 568 struct lio *lio = GET_LIO(netdev);
569
f21fb3ed
RV		 570 if (netif_is_multiqueue(netdev)) {
571 int i;
572
1f164717
RV		 573 for (i = 0; i < netdev->num_tx_queues; i++) {
574 int qno = lio->linfo.txpciq[i %
575 (lio->linfo.num_txpciq)].s.q_no;
576
577 if (__netif_subqueue_stopped(netdev, i)) {
578 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, qno,
579 tx_restart, 1);
26236fa9 580 netif_wake_subqueue(netdev, i);
1f164717
RV		 581 }
582 }
f21fb3ed 583 } else {
1f164717
RV		 584 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, lio->txq,
585 tx_restart, 1);
f21fb3ed
RV		 586 netif_wake_queue(netdev);
587 }
588}
589
590/**
591 * \brief Stop Tx queue
592 * @param netdev network device
593 */
594static void stop_txq(struct net_device *netdev)
595{
596 txqs_stop(netdev);
597}
598
599/**
600 * \brief Start Tx queue
601 * @param netdev network device
602 */
603static void start_txq(struct net_device *netdev)
604{
605 struct lio *lio = GET_LIO(netdev);
606
0cece6c5 607 if (lio->linfo.link.s.link_up) {
f21fb3ed
RV		 608 txqs_start(netdev);
609 return;
610 }
611}
612
613/**
614 * \brief Wake a queue
615 * @param netdev network device
616 * @param q which queue to wake
617 */
618static inline void wake_q(struct net_device *netdev, int q)
619{
620 if (netif_is_multiqueue(netdev))
621 netif_wake_subqueue(netdev, q);
622 else
623 netif_wake_queue(netdev);
624}
625
626/**
627 * \brief Stop a queue
628 * @param netdev network device
629 * @param q which queue to stop
630 */
631static inline void stop_q(struct net_device *netdev, int q)
632{
633 if (netif_is_multiqueue(netdev))
634 netif_stop_subqueue(netdev, q);
635 else
636 netif_stop_queue(netdev);
637}
638
639/**
640 * \brief Check Tx queue status, and take appropriate action
641 * @param lio per-network private data
642 * @returns 0 if full, number of queues woken up otherwise
643 */
644static inline int check_txq_status(struct lio *lio)
645{
646 int ret_val = 0;
647
648 if (netif_is_multiqueue(lio->netdev)) {
649 int numqs = lio->netdev->num_tx_queues;
650 int q, iq = 0;
651
652 /* check each sub-queue state */
653 for (q = 0; q < numqs; q++) {
26236fa9
RV		 654 iq = lio->linfo.txpciq[q %
655 (lio->linfo.num_txpciq)].s.q_no;
f21fb3ed
RV		 656 if (octnet_iq_is_full(lio->oct_dev, iq))
657 continue;
26236fa9
RV		 658 if (__netif_subqueue_stopped(lio->netdev, q)) {
659 wake_q(lio->netdev, q);
1f164717
RV		 660 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq,
661 tx_restart, 1);
26236fa9
RV		 662 ret_val++;
663 }
f21fb3ed
RV		 664 }
665 } else {
666 if (octnet_iq_is_full(lio->oct_dev, lio->txq))
667 return 0;
668 wake_q(lio->netdev, lio->txq);
1f164717
RV		 669 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, lio->txq,
670 tx_restart, 1);
f21fb3ed
RV		 671 ret_val = 1;
672 }
673 return ret_val;
674}
675
676/**
677 * Remove the node at the head of the list. The list would be empty at
678 * the end of this call if there are no more nodes in the list.
679 */
680static inline struct list_head *list_delete_head(struct list_head *root)
681{
682 struct list_head *node;
683
684 if ((root->prev == root) && (root->next == root))
685 node = NULL;
686 else
687 node = root->next;
688
689 if (node)
690 list_del(node);
691
692 return node;
693}
694
695/**
fcd2b5e3 696 * \brief Delete gather lists
f21fb3ed
RV		 697 * @param lio per-network private data
698 */
fcd2b5e3 699static void delete_glists(struct lio *lio)
f21fb3ed
RV		 700{
701 struct octnic_gather *g;
fcd2b5e3 702 int i;
f21fb3ed 703
67e303e0
VB		 704 kfree(lio->glist_lock);
705 lio->glist_lock = NULL;
706
fcd2b5e3
RV		 707 if (!lio->glist)
708 return;
709
710 for (i = 0; i < lio->linfo.num_txpciq; i++) {
711 do {
712 g = (struct octnic_gather *)
713 list_delete_head(&lio->glist[i]);
67e303e0 714 if (g)
fcd2b5e3 715 kfree(g);
fcd2b5e3 716 } while (g);
67e303e0 717
58ad3198
FM		 718 if (lio->glists_virt_base && lio->glists_virt_base[i] &&
719 lio->glists_dma_base && lio->glists_dma_base[i]) {
67e303e0
VB		 720 lio_dma_free(lio->oct_dev,
721 lio->glist_entry_size * lio->tx_qsize,
722 lio->glists_virt_base[i],
723 lio->glists_dma_base[i]);
724 }
fcd2b5e3
RV		 725 }
726
67e303e0
VB		 727 kfree(lio->glists_virt_base);
728 lio->glists_virt_base = NULL;
729
730 kfree(lio->glists_dma_base);
731 lio->glists_dma_base = NULL;
732
733 kfree(lio->glist);
734 lio->glist = NULL;
f21fb3ed
RV		 735}
736
737/**
fcd2b5e3 738 * \brief Setup gather lists
f21fb3ed
RV		 739 * @param lio per-network private data
740 */
fcd2b5e3 741static int setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs)
f21fb3ed 742{
fcd2b5e3 743 int i, j;
f21fb3ed
RV		 744 struct octnic_gather *g;
745
fcd2b5e3
RV		 746 lio->glist_lock = kcalloc(num_iqs, sizeof(*lio->glist_lock),
747 GFP_KERNEL);
748 if (!lio->glist_lock)
67e303e0 749 return -ENOMEM;
f21fb3ed 750
fcd2b5e3
RV		 751 lio->glist = kcalloc(num_iqs, sizeof(*lio->glist),
752 GFP_KERNEL);
753 if (!lio->glist) {
67e303e0
VB		 754 kfree(lio->glist_lock);
755 lio->glist_lock = NULL;
756 return -ENOMEM;
757 }
758
759 lio->glist_entry_size =
760 ROUNDUP8((ROUNDUP4(OCTNIC_MAX_SG) >> 2) * OCT_SG_ENTRY_SIZE);
761
762 /* allocate memory to store virtual and dma base address of
763 * per glist consistent memory
764 */
765 lio->glists_virt_base = kcalloc(num_iqs, sizeof(*lio->glists_virt_base),
766 GFP_KERNEL);
767 lio->glists_dma_base = kcalloc(num_iqs, sizeof(*lio->glists_dma_base),
768 GFP_KERNEL);
769
770 if (!lio->glists_virt_base || !lio->glists_dma_base) {
771 delete_glists(lio);
772 return -ENOMEM;
fcd2b5e3 773 }
f21fb3ed 774
fcd2b5e3 775 for (i = 0; i < num_iqs; i++) {
b3ca9af0 776 int numa_node = dev_to_node(&oct->pci_dev->dev);
f21fb3ed 777
fcd2b5e3
RV		 778 spin_lock_init(&lio->glist_lock[i]);
779
780 INIT_LIST_HEAD(&lio->glist[i]);
781
67e303e0
VB		 782 lio->glists_virt_base[i] =
783 lio_dma_alloc(oct,
784 lio->glist_entry_size * lio->tx_qsize,
785 &lio->glists_dma_base[i]);
786
787 if (!lio->glists_virt_base[i]) {
788 delete_glists(lio);
789 return -ENOMEM;
790 }
791
fcd2b5e3
RV		 792 for (j = 0; j < lio->tx_qsize; j++) {
793 g = kzalloc_node(sizeof(*g), GFP_KERNEL,
794 numa_node);
795 if (!g)
796 g = kzalloc(sizeof(*g), GFP_KERNEL);
797 if (!g)
798 break;
799
67e303e0
VB		 800 g->sg = lio->glists_virt_base[i] +
801 (j * lio->glist_entry_size);
fcd2b5e3 802
67e303e0
VB		 803 g->sg_dma_ptr = lio->glists_dma_base[i] +
804 (j * lio->glist_entry_size);
fcd2b5e3
RV		 805
806 list_add_tail(&g->list, &lio->glist[i]);
f21fb3ed
RV		 807 }
808
fcd2b5e3
RV		 809 if (j != lio->tx_qsize) {
810 delete_glists(lio);
67e303e0 811 return -ENOMEM;
f21fb3ed 812 }
f21fb3ed
RV		 813 }
814
fcd2b5e3 815 return 0;
f21fb3ed
RV		 816}
817
818/**
819 * \brief Print link information
820 * @param netdev network device
821 */
822static void print_link_info(struct net_device *netdev)
823{
824 struct lio *lio = GET_LIO(netdev);
825
826 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED) {
827 struct oct_link_info *linfo = &lio->linfo;
828
0cece6c5 829 if (linfo->link.s.link_up) {
f21fb3ed
RV		 830 netif_info(lio, link, lio->netdev, "%d Mbps %s Duplex UP\n",
831 linfo->link.s.speed,
832 (linfo->link.s.duplex) ? "Full" : "Half");
833 } else {
834 netif_info(lio, link, lio->netdev, "Link Down\n");
835 }
836 }
837}
838
7b6b6c95
RV		 839/**
840 * \brief Routine to notify MTU change
841 * @param work work_struct data structure
842 */
843static void octnet_link_status_change(struct work_struct *work)
844{
845 struct cavium_wk *wk = (struct cavium_wk *)work;
846 struct lio *lio = (struct lio *)wk->ctxptr;
847
848 rtnl_lock();
849 call_netdevice_notifiers(NETDEV_CHANGEMTU, lio->netdev);
850 rtnl_unlock();
851}
852
853/**
854 * \brief Sets up the mtu status change work
855 * @param netdev network device
856 */
857static inline int setup_link_status_change_wq(struct net_device *netdev)
858{
859 struct lio *lio = GET_LIO(netdev);
860 struct octeon_device *oct = lio->oct_dev;
861
862 lio->link_status_wq.wq = alloc_workqueue("link-status",
863 WQ_MEM_RECLAIM, 0);
864 if (!lio->link_status_wq.wq) {
865 dev_err(&oct->pci_dev->dev, "unable to create cavium link status wq\n");
866 return -1;
867 }
868 INIT_DELAYED_WORK(&lio->link_status_wq.wk.work,
869 octnet_link_status_change);
870 lio->link_status_wq.wk.ctxptr = lio;
871
872 return 0;
873}
874
875static inline void cleanup_link_status_change_wq(struct net_device *netdev)
876{
877 struct lio *lio = GET_LIO(netdev);
878
879 if (lio->link_status_wq.wq) {
880 cancel_delayed_work_sync(&lio->link_status_wq.wk.work);
881 destroy_workqueue(lio->link_status_wq.wq);
882 }
883}
884
f21fb3ed
RV		 885/**
886 * \brief Update link status
887 * @param netdev network device
888 * @param ls link status structure
889 *
890 * Called on receipt of a link status response from the core application to
891 * update each interface's link status.
892 */
893static inline void update_link_status(struct net_device *netdev,
894 union oct_link_status *ls)
895{
896 struct lio *lio = GET_LIO(netdev);
0cece6c5 897 int changed = (lio->linfo.link.u64 != ls->u64);
f21fb3ed 898
0cece6c5 899 lio->linfo.link.u64 = ls->u64;
f21fb3ed 900
0cece6c5 901 if ((lio->intf_open) && (changed)) {
f21fb3ed 902 print_link_info(netdev);
0cece6c5 903 lio->link_changes++;
f21fb3ed 904
0cece6c5 905 if (lio->linfo.link.s.link_up) {
f21fb3ed 906 netif_carrier_on(netdev);
f21fb3ed
RV		 907 txqs_wake(netdev);
908 } else {
909 netif_carrier_off(netdev);
910 stop_txq(netdev);
911 }
912 }
913}
914
9a96bde4
RV		 915/* Runs in interrupt context. */
916static void update_txq_status(struct octeon_device *oct, int iq_num)
917{
918 struct net_device *netdev;
919 struct lio *lio;
920 struct octeon_instr_queue *iq = oct->instr_queue[iq_num];
921
9a96bde4
RV		 922 netdev = oct->props[iq->ifidx].netdev;
923
924 /* This is needed because the first IQ does not have
925 * a netdev associated with it.
926 */
927 if (!netdev)
928 return;
929
930 lio = GET_LIO(netdev);
931 if (netif_is_multiqueue(netdev)) {
932 if (__netif_subqueue_stopped(netdev, iq->q_index) &&
933 lio->linfo.link.s.link_up &&
934 (!octnet_iq_is_full(oct, iq_num))) {
1f164717
RV		 935 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq_num,
936 tx_restart, 1);
9a96bde4 937 netif_wake_subqueue(netdev, iq->q_index);
9a96bde4 938 }
6069f3fb
VB		 939 } else if (netif_queue_stopped(netdev) &&
940 lio->linfo.link.s.link_up &&
941 (!octnet_iq_is_full(oct, lio->txq))) {
942 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev,
943 lio->txq, tx_restart, 1);
944 netif_wake_queue(netdev);
9a96bde4
RV		 945 }
946}
947
5b07aee1
RV		 948static
949int liquidio_schedule_msix_droq_pkt_handler(struct octeon_droq *droq, u64 ret)
950{
951 struct octeon_device *oct = droq->oct_dev;
952 struct octeon_device_priv *oct_priv =
953 (struct octeon_device_priv *)oct->priv;
954
955 if (droq->ops.poll_mode) {
956 droq->ops.napi_fn(droq);
957 } else {
958 if (ret & MSIX_PO_INT) {
959 tasklet_schedule(&oct_priv->droq_tasklet);
960 return 1;
961 }
962 /* this will be flushed periodically by check iq db */
963 if (ret & MSIX_PI_INT)
964 return 0;
965 }
966 return 0;
967}
968
f21fb3ed
RV		 969/**
970 * \brief Droq packet processor sceduler
971 * @param oct octeon device
972 */
9ded1a51 973static void liquidio_schedule_droq_pkt_handlers(struct octeon_device *oct)
f21fb3ed
RV		 974{
975 struct octeon_device_priv *oct_priv =
976 (struct octeon_device_priv *)oct->priv;
977 u64 oq_no;
978 struct octeon_droq *droq;
979
980 if (oct->int_status & OCT_DEV_INTR_PKT_DATA) {
63da8404
RV		 981 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct);
982 oq_no++) {
763185a3 983 if (!(oct->droq_intr & BIT_ULL(oq_no)))
f21fb3ed
RV		 984 continue;
985
986 droq = oct->droq[oq_no];
987
988 if (droq->ops.poll_mode) {
989 droq->ops.napi_fn(droq);
990 oct_priv->napi_mask |= (1 << oq_no);
991 } else {
992 tasklet_schedule(&oct_priv->droq_tasklet);
993 }
994 }
995 }
996}
997
5b07aee1
RV		 998static irqreturn_t
999liquidio_msix_intr_handler(int irq __attribute__((unused)), void *dev)
1000{
1001 u64 ret;
1002 struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev;
1003 struct octeon_device *oct = ioq_vector->oct_dev;
1004 struct octeon_droq *droq = oct->droq[ioq_vector->droq_index];
1005
1006 ret = oct->fn_list.msix_interrupt_handler(ioq_vector);
1007
1008 if ((ret & MSIX_PO_INT) || (ret & MSIX_PI_INT))
1009 liquidio_schedule_msix_droq_pkt_handler(droq, ret);
1010
1011 return IRQ_HANDLED;
1012}
1013
f21fb3ed
RV		 1014/**
1015 * \brief Interrupt handler for octeon
1016 * @param irq unused
1017 * @param dev octeon device
1018 */
1019static
5b07aee1
RV		 1020irqreturn_t liquidio_legacy_intr_handler(int irq __attribute__((unused)),
1021 void *dev)
f21fb3ed
RV		 1022{
1023 struct octeon_device *oct = (struct octeon_device *)dev;
1024 irqreturn_t ret;
1025
1026 /* Disable our interrupts for the duration of ISR */
5b07aee1 1027 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
f21fb3ed
RV		 1028
1029 ret = oct->fn_list.process_interrupt_regs(oct);
1030
1031 if (ret == IRQ_HANDLED)
1032 liquidio_schedule_droq_pkt_handlers(oct);
1033
1034 /* Re-enable our interrupts */
1035 if (!(atomic_read(&oct->status) == OCT_DEV_IN_RESET))
5b07aee1 1036 oct->fn_list.enable_interrupt(oct, OCTEON_ALL_INTR);
f21fb3ed
RV		 1037
1038 return ret;
1039}
1040
1041/**
1042 * \brief Setup interrupt for octeon device
1043 * @param oct octeon device
1044 *
1045 * Enable interrupt in Octeon device as given in the PCI interrupt mask.
1046 */
1047static int octeon_setup_interrupt(struct octeon_device *oct)
1048{
1049 int irqret, err;
5b07aee1
RV		 1050 struct msix_entry *msix_entries;
1051 int i;
1052 int num_ioq_vectors;
1053 int num_alloc_ioq_vectors;
0c88a761
RF		 1054 char *queue_irq_names = NULL;
1055 char *aux_irq_name = NULL;
f21fb3ed 1056
5b07aee1
RV		 1057 if (OCTEON_CN23XX_PF(oct) && oct->msix_on) {
1058 oct->num_msix_irqs = oct->sriov_info.num_pf_rings;
1059 /* one non ioq interrupt for handling sli_mac_pf_int_sum */
1060 oct->num_msix_irqs += 1;
f21fb3ed 1061
0c88a761
RF		 1062 /* allocate storage for the names assigned to each irq */
1063 oct->irq_name_storage =
1064 kcalloc((MAX_IOQ_INTERRUPTS_PER_PF + 1), INTRNAMSIZ,
1065 GFP_KERNEL);
1066 if (!oct->irq_name_storage) {
1067 dev_err(&oct->pci_dev->dev, "Irq name storage alloc failed...\n");
1068 return -ENOMEM;
1069 }
1070
1071 queue_irq_names = oct->irq_name_storage;
1072 aux_irq_name = &queue_irq_names
1073 [IRQ_NAME_OFF(MAX_IOQ_INTERRUPTS_PER_PF)];
1074
5b07aee1
RV		 1075 oct->msix_entries = kcalloc(
1076 oct->num_msix_irqs, sizeof(struct msix_entry), GFP_KERNEL);
0c88a761
RF		 1077 if (!oct->msix_entries) {
1078 dev_err(&oct->pci_dev->dev, "Memory Alloc failed...\n");
1079 kfree(oct->irq_name_storage);
1080 oct->irq_name_storage = NULL;
1081 return -ENOMEM;
1082 }
5b07aee1
RV		 1083
1084 msix_entries = (struct msix_entry *)oct->msix_entries;
1085 /*Assumption is that pf msix vectors start from pf srn to pf to
1086 * trs and not from 0. if not change this code
1087 */
1088 for (i = 0; i < oct->num_msix_irqs - 1; i++)
1089 msix_entries[i].entry = oct->sriov_info.pf_srn + i;
1090 msix_entries[oct->num_msix_irqs - 1].entry =
1091 oct->sriov_info.trs;
1092 num_alloc_ioq_vectors = pci_enable_msix_range(
1093 oct->pci_dev, msix_entries,
1094 oct->num_msix_irqs,
1095 oct->num_msix_irqs);
1096 if (num_alloc_ioq_vectors < 0) {
1097 dev_err(&oct->pci_dev->dev, "unable to Allocate MSI-X interrupts\n");
1098 kfree(oct->msix_entries);
1099 oct->msix_entries = NULL;
0c88a761
RF		 1100 kfree(oct->irq_name_storage);
1101 oct->irq_name_storage = NULL;
1102 return num_alloc_ioq_vectors;
5b07aee1
RV		 1103 }
1104 dev_dbg(&oct->pci_dev->dev, "OCTEON: Enough MSI-X interrupts are allocated...\n");
1105
1106 num_ioq_vectors = oct->num_msix_irqs;
1107
1108 /** For PF, there is one non-ioq interrupt handler */
1109 num_ioq_vectors -= 1;
0c88a761
RF		 1110
1111 snprintf(aux_irq_name, INTRNAMSIZ,
1112 "LiquidIO%u-pf%u-aux", oct->octeon_id, oct->pf_num);
5b07aee1 1113 irqret = request_irq(msix_entries[num_ioq_vectors].vector,
0c88a761
RF		 1114 liquidio_legacy_intr_handler, 0,
1115 aux_irq_name, oct);
5b07aee1
RV		 1116 if (irqret) {
1117 dev_err(&oct->pci_dev->dev,
1118 "OCTEON: Request_irq failed for MSIX interrupt Error: %d\n",
1119 irqret);
1120 pci_disable_msix(oct->pci_dev);
1121 kfree(oct->msix_entries);
1122 oct->msix_entries = NULL;
0c88a761
RF		 1123 kfree(oct->irq_name_storage);
1124 oct->irq_name_storage = NULL;
1125 return irqret;
5b07aee1
RV		 1126 }
1127
1128 for (i = 0; i < num_ioq_vectors; i++) {
0c88a761
RF		 1129 snprintf(&queue_irq_names[IRQ_NAME_OFF(i)], INTRNAMSIZ,
1130 "LiquidIO%u-pf%u-rxtx-%u",
1131 oct->octeon_id, oct->pf_num, i);
1132
5b07aee1
RV		 1133 irqret = request_irq(msix_entries[i].vector,
1134 liquidio_msix_intr_handler, 0,
0c88a761
RF		 1135 &queue_irq_names[IRQ_NAME_OFF(i)],
1136 &oct->ioq_vector[i]);
5b07aee1
RV		 1137 if (irqret) {
1138 dev_err(&oct->pci_dev->dev,
1139 "OCTEON: Request_irq failed for MSIX interrupt Error: %d\n",
1140 irqret);
1141 /** Freeing the non-ioq irq vector here . */
1142 free_irq(msix_entries[num_ioq_vectors].vector,
1143 oct);
1144
1145 while (i) {
1146 i--;
1147 /** clearing affinity mask. */
1148 irq_set_affinity_hint(
1149 msix_entries[i].vector, NULL);
1150 free_irq(msix_entries[i].vector,
1151 &oct->ioq_vector[i]);
1152 }
1153 pci_disable_msix(oct->pci_dev);
1154 kfree(oct->msix_entries);
1155 oct->msix_entries = NULL;
0c88a761
RF		 1156 kfree(oct->irq_name_storage);
1157 oct->irq_name_storage = NULL;
1158 return irqret;
5b07aee1
RV		 1159 }
1160 oct->ioq_vector[i].vector = msix_entries[i].vector;
1161 /* assign the cpu mask for this msix interrupt vector */
1162 irq_set_affinity_hint(
1163 msix_entries[i].vector,
1164 (&oct->ioq_vector[i].affinity_mask));
1165 }
1166 dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: MSI-X enabled\n",
1167 oct->octeon_id);
1168 } else {
1169 err = pci_enable_msi(oct->pci_dev);
1170 if (err)
1171 dev_warn(&oct->pci_dev->dev, "Reverting to legacy interrupts. Error: %d\n",
1172 err);
1173 else
1174 oct->flags |= LIO_FLAG_MSI_ENABLED;
1175
0c88a761
RF		 1176 /* allocate storage for the names assigned to the irq */
1177 oct->irq_name_storage = kcalloc(1, INTRNAMSIZ, GFP_KERNEL);
1178 if (!oct->irq_name_storage)
1179 return -ENOMEM;
1180
1181 queue_irq_names = oct->irq_name_storage;
1182
1183 snprintf(&queue_irq_names[IRQ_NAME_OFF(0)], INTRNAMSIZ,
1184 "LiquidIO%u-pf%u-rxtx-%u",
1185 oct->octeon_id, oct->pf_num, 0);
1186
5b07aee1 1187 irqret = request_irq(oct->pci_dev->irq,
0c88a761
RF		 1188 liquidio_legacy_intr_handler,
1189 IRQF_SHARED,
1190 &queue_irq_names[IRQ_NAME_OFF(0)], oct);
5b07aee1
RV		 1191 if (irqret) {
1192 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1193 pci_disable_msi(oct->pci_dev);
1194 dev_err(&oct->pci_dev->dev, "Request IRQ failed with code: %d\n",
1195 irqret);
0c88a761
RF		 1196 kfree(oct->irq_name_storage);
1197 oct->irq_name_storage = NULL;
1198 return irqret;
5b07aee1
RV		 1199 }
1200 }
f21fb3ed
RV		 1201 return 0;
1202}
1203
bb54be58
FM		 1204static struct octeon_device *get_other_octeon_device(struct octeon_device *oct)
1205{
1206 struct octeon_device *other_oct;
1207
1208 other_oct = lio_get_device(oct->octeon_id + 1);
1209
1210 if (other_oct && other_oct->pci_dev) {
1211 int oct_busnum, other_oct_busnum;
1212
1213 oct_busnum = oct->pci_dev->bus->number;
1214 other_oct_busnum = other_oct->pci_dev->bus->number;
1215
1216 if (oct_busnum == other_oct_busnum) {
1217 int oct_slot, other_oct_slot;
1218
1219 oct_slot = PCI_SLOT(oct->pci_dev->devfn);
1220 other_oct_slot = PCI_SLOT(other_oct->pci_dev->devfn);
1221
1222 if (oct_slot == other_oct_slot)
1223 return other_oct;
1224 }
1225 }
1226
1227 return NULL;
1228}
1229
1230static void disable_all_vf_links(struct octeon_device *oct)
1231{
1232 struct net_device *netdev;
1233 int max_vfs, vf, i;
1234
1235 if (!oct)
1236 return;
1237
1238 max_vfs = oct->sriov_info.max_vfs;
1239
1240 for (i = 0; i < oct->ifcount; i++) {
1241 netdev = oct->props[i].netdev;
1242 if (!netdev)
1243 continue;
1244
1245 for (vf = 0; vf < max_vfs; vf++)
1246 liquidio_set_vf_link_state(netdev, vf,
1247 IFLA_VF_LINK_STATE_DISABLE);
1248 }
1249}
1250
9ff1a9ba
RV		 1251static int liquidio_watchdog(void *param)
1252{
bb54be58
FM		 1253 bool err_msg_was_printed[LIO_MAX_CORES];
1254 u16 mask_of_crashed_or_stuck_cores = 0;
1255 bool all_vf_links_are_disabled = false;
9ff1a9ba 1256 struct octeon_device *oct = param;
bb54be58
FM		 1257 struct octeon_device *other_oct;
1258#ifdef CONFIG_MODULE_UNLOAD
1259 long refcount, vfs_referencing_pf;
1260 u64 vfs_mask1, vfs_mask2;
1261#endif
1262 int core;
9ff1a9ba 1263
bb54be58 1264 memset(err_msg_was_printed, 0, sizeof(err_msg_was_printed));
9ff1a9ba
RV		 1265
1266 while (!kthread_should_stop()) {
bb54be58
FM		 1267 /* sleep for a couple of seconds so that we don't hog the CPU */
1268 set_current_state(TASK_INTERRUPTIBLE);
1269 schedule_timeout(msecs_to_jiffies(2000));
1270
1271 mask_of_crashed_or_stuck_cores =
9ff1a9ba
RV		 1272 (u16)octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2);
1273
bb54be58
FM		 1274 if (!mask_of_crashed_or_stuck_cores)
1275 continue;
9ff1a9ba 1276
bb54be58
FM		 1277 WRITE_ONCE(oct->cores_crashed, true);
1278 other_oct = get_other_octeon_device(oct);
1279 if (other_oct)
1280 WRITE_ONCE(other_oct->cores_crashed, true);
9ff1a9ba 1281
bb54be58
FM		 1282 for (core = 0; core < LIO_MAX_CORES; core++) {
1283 bool core_crashed_or_got_stuck;
9ff1a9ba 1284
bb54be58
FM		 1285 core_crashed_or_got_stuck =
1286 (mask_of_crashed_or_stuck_cores
1287 >> core) & 1;
1288
1289 if (core_crashed_or_got_stuck &&
1290 !err_msg_was_printed[core]) {
1291 dev_err(&oct->pci_dev->dev,
1292 "ERROR: Octeon core %d crashed or got stuck! See oct-fwdump for details.\n",
1293 core);
1294 err_msg_was_printed[core] = true;
9ff1a9ba
RV		 1295 }
1296 }
bb54be58
FM		 1297
1298 if (all_vf_links_are_disabled)
1299 continue;
1300
1301 disable_all_vf_links(oct);
1302 disable_all_vf_links(other_oct);
1303 all_vf_links_are_disabled = true;
1304
9ff1a9ba 1305#ifdef CONFIG_MODULE_UNLOAD
bb54be58
FM		 1306 vfs_mask1 = READ_ONCE(oct->sriov_info.vf_drv_loaded_mask);
1307 vfs_mask2 = READ_ONCE(other_oct->sriov_info.vf_drv_loaded_mask);
9ff1a9ba 1308
bb54be58
FM		 1309 vfs_referencing_pf = hweight64(vfs_mask1);
1310 vfs_referencing_pf += hweight64(vfs_mask2);
9ff1a9ba 1311
bb54be58
FM		 1312 refcount = module_refcount(THIS_MODULE);
1313 if (refcount >= vfs_referencing_pf) {
1314 while (vfs_referencing_pf) {
9ff1a9ba 1315 module_put(THIS_MODULE);
bb54be58 1316 vfs_referencing_pf--;
9ff1a9ba
RV		 1317 }
1318 }
1319#endif
9ff1a9ba
RV		 1320 }
1321
1322 return 0;
1323}
1324
f21fb3ed
RV		 1325/**
1326 * \brief PCI probe handler
1327 * @param pdev PCI device structure
1328 * @param ent unused
1329 */
a7d5a3dc
RV		 1330static int
1331liquidio_probe(struct pci_dev *pdev,
1332 const struct pci_device_id *ent __attribute__((unused)))
f21fb3ed
RV		 1333{
1334 struct octeon_device *oct_dev = NULL;
1335 struct handshake *hs;
1336
1337 oct_dev = octeon_allocate_device(pdev->device,
1338 sizeof(struct octeon_device_priv));
1339 if (!oct_dev) {
1340 dev_err(&pdev->dev, "Unable to allocate device\n");
1341 return -ENOMEM;
1342 }
1343
5b07aee1
RV		 1344 if (pdev->device == OCTEON_CN23XX_PF_VID)
1345 oct_dev->msix_on = LIO_FLAG_MSIX_ENABLED;
1346
f21fb3ed
RV		 1347 dev_info(&pdev->dev, "Initializing device %x:%x.\n",
1348 (u32)pdev->vendor, (u32)pdev->device);
1349
1350 /* Assign octeon_device for this device to the private data area. */
1351 pci_set_drvdata(pdev, oct_dev);
1352
1353 /* set linux specific device pointer */
1354 oct_dev->pci_dev = (void *)pdev;
1355
1356 hs = &handshake[oct_dev->octeon_id];
1357 init_completion(&hs->init);
1358 init_completion(&hs->started);
1359 hs->pci_dev = pdev;
1360
1361 if (oct_dev->octeon_id == 0)
1362 /* first LiquidIO NIC is detected */
1363 complete(&first_stage);
1364
1365 if (octeon_device_init(oct_dev)) {
515e752d 1366 complete(&hs->init);
f21fb3ed
RV		 1367 liquidio_remove(pdev);
1368 return -ENOMEM;
1369 }
1370
9ff1a9ba
RV		 1371 if (OCTEON_CN23XX_PF(oct_dev)) {
1372 u64 scratch1;
1373 u8 bus, device, function;
1374
1375 scratch1 = octeon_read_csr64(oct_dev, CN23XX_SLI_SCRATCH1);
1376 if (!(scratch1 & 4ULL)) {
1377 /* Bit 2 of SLI_SCRATCH_1 is a flag that indicates that
1378 * the lio watchdog kernel thread is running for this
1379 * NIC. Each NIC gets one watchdog kernel thread.
1380 */
1381 scratch1 |= 4ULL;
1382 octeon_write_csr64(oct_dev, CN23XX_SLI_SCRATCH1,
1383 scratch1);
1384
1385 bus = pdev->bus->number;
1386 device = PCI_SLOT(pdev->devfn);
1387 function = PCI_FUNC(pdev->devfn);
1388 oct_dev->watchdog_task = kthread_create(
1389 liquidio_watchdog, oct_dev,
1390 "liowd/%02hhx:%02hhx.%hhx", bus, device, function);
515e752d
RV		 1391 if (!IS_ERR(oct_dev->watchdog_task)) {
1392 wake_up_process(oct_dev->watchdog_task);
1393 } else {
1394 oct_dev->watchdog_task = NULL;
1395 dev_err(&oct_dev->pci_dev->dev,
1396 "failed to create kernel_thread\n");
1397 liquidio_remove(pdev);
1398 return -1;
1399 }
9ff1a9ba
RV		 1400 }
1401 }
1402
1f164717
RV		 1403 oct_dev->rx_pause = 1;
1404 oct_dev->tx_pause = 1;
1405
f21fb3ed
RV		 1406 dev_dbg(&oct_dev->pci_dev->dev, "Device is ready\n");
1407
1408 return 0;
1409}
1410
7cc61db9
FM		 1411static bool fw_type_is_none(void)
1412{
1413 return strncmp(fw_type, LIO_FW_NAME_TYPE_NONE,
1414 sizeof(LIO_FW_NAME_TYPE_NONE)) == 0;
1415}
1416
f21fb3ed
RV		 1417/**
1418 *\brief Destroy resources associated with octeon device
1419 * @param pdev PCI device structure
1420 * @param ent unused
1421 */
1422static void octeon_destroy_resources(struct octeon_device *oct)
1423{
1424 int i;
5b07aee1 1425 struct msix_entry *msix_entries;
f21fb3ed
RV		 1426 struct octeon_device_priv *oct_priv =
1427 (struct octeon_device_priv *)oct->priv;
1428
1429 struct handshake *hs;
1430
1431 switch (atomic_read(&oct->status)) {
1432 case OCT_DEV_RUNNING:
1433 case OCT_DEV_CORE_OK:
1434
1435 /* No more instructions will be forwarded. */
1436 atomic_set(&oct->status, OCT_DEV_IN_RESET);
1437
1438 oct->app_mode = CVM_DRV_INVALID_APP;
1439 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
1440 lio_get_state_string(&oct->status));
1441
1442 schedule_timeout_uninterruptible(HZ / 10);
1443
1444 /* fallthrough */
1445 case OCT_DEV_HOST_OK:
1446
1447 /* fallthrough */
1448 case OCT_DEV_CONSOLE_INIT_DONE:
1449 /* Remove any consoles */
1450 octeon_remove_consoles(oct);
1451
1452 /* fallthrough */
1453 case OCT_DEV_IO_QUEUES_DONE:
1454 if (wait_for_pending_requests(oct))
1455 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
1456
1457 if (lio_wait_for_instr_fetch(oct))
1458 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n");
1459
1460 /* Disable the input and output queues now. No more packets will
1461 * arrive from Octeon, but we should wait for all packet
1462 * processing to finish.
1463 */
1464 oct->fn_list.disable_io_queues(oct);
1465
1466 if (lio_wait_for_oq_pkts(oct))
1467 dev_err(&oct->pci_dev->dev, "OQ had pending packets\n");
1468
515e752d
RV		 1469 /* fallthrough */
1470 case OCT_DEV_INTR_SET_DONE:
f21fb3ed 1471 /* Disable interrupts */
5b07aee1
RV		 1472 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
1473
1474 if (oct->msix_on) {
1475 msix_entries = (struct msix_entry *)oct->msix_entries;
1476 for (i = 0; i < oct->num_msix_irqs - 1; i++) {
1477 /* clear the affinity_cpumask */
1478 irq_set_affinity_hint(msix_entries[i].vector,
1479 NULL);
1480 free_irq(msix_entries[i].vector,
1481 &oct->ioq_vector[i]);
1482 }
1483 /* non-iov vector's argument is oct struct */
1484 free_irq(msix_entries[i].vector, oct);
f21fb3ed 1485
5b07aee1
RV		 1486 pci_disable_msix(oct->pci_dev);
1487 kfree(oct->msix_entries);
1488 oct->msix_entries = NULL;
1489 } else {
1490 /* Release the interrupt line */
1491 free_irq(oct->pci_dev->irq, oct);
f21fb3ed 1492
5b07aee1
RV		 1493 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1494 pci_disable_msi(oct->pci_dev);
1495 }
f21fb3ed 1496
0c88a761
RF		 1497 kfree(oct->irq_name_storage);
1498 oct->irq_name_storage = NULL;
1499
515e752d
RV		 1500 /* fallthrough */
1501 case OCT_DEV_MSIX_ALLOC_VECTOR_DONE:
5b07aee1
RV		 1502 if (OCTEON_CN23XX_PF(oct))
1503 octeon_free_ioq_vector(oct);
5d65556b
RV		 1504
1505 /* fallthrough */
1506 case OCT_DEV_MBOX_SETUP_DONE:
1507 if (OCTEON_CN23XX_PF(oct))
1508 oct->fn_list.free_mbox(oct);
1509
5b07aee1 1510 /* fallthrough */
f21fb3ed
RV		 1511 case OCT_DEV_IN_RESET:
1512 case OCT_DEV_DROQ_INIT_DONE:
763185a3 1513 /* Wait for any pending operations */
f21fb3ed 1514 mdelay(100);
63da8404 1515 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
5b07aee1 1516 if (!(oct->io_qmask.oq & BIT_ULL(i)))
f21fb3ed
RV		 1517 continue;
1518 octeon_delete_droq(oct, i);
1519 }
1520
1521 /* Force any pending handshakes to complete */
1522 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
1523 hs = &handshake[i];
1524
1525 if (hs->pci_dev) {
1526 handshake[oct->octeon_id].init_ok = 0;
1527 complete(&handshake[oct->octeon_id].init);
1528 handshake[oct->octeon_id].started_ok = 0;
1529 complete(&handshake[oct->octeon_id].started);
1530 }
1531 }
1532
1533 /* fallthrough */
1534 case OCT_DEV_RESP_LIST_INIT_DONE:
1535 octeon_delete_response_list(oct);
1536
f21fb3ed
RV		 1537 /* fallthrough */
1538 case OCT_DEV_INSTR_QUEUE_INIT_DONE:
63da8404 1539 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
5b823514 1540 if (!(oct->io_qmask.iq & BIT_ULL(i)))
f21fb3ed
RV		 1541 continue;
1542 octeon_delete_instr_queue(oct, i);
1543 }
ca6139ff
RV		 1544#ifdef CONFIG_PCI_IOV
1545 if (oct->sriov_info.sriov_enabled)
1546 pci_disable_sriov(oct->pci_dev);
1547#endif
5b823514
RV		 1548 /* fallthrough */
1549 case OCT_DEV_SC_BUFF_POOL_INIT_DONE:
1550 octeon_free_sc_buffer_pool(oct);
f21fb3ed
RV		 1551
1552 /* fallthrough */
1553 case OCT_DEV_DISPATCH_INIT_DONE:
1554 octeon_delete_dispatch_list(oct);
1555 cancel_delayed_work_sync(&oct->nic_poll_work.work);
1556
1557 /* fallthrough */
1558 case OCT_DEV_PCI_MAP_DONE:
7cc61db9
FM		 1559 if (!fw_type_is_none()) {
1560 /* Soft reset the octeon device before exiting */
1561 if (!OCTEON_CN23XX_PF(oct) ||
1562 (OCTEON_CN23XX_PF(oct) && !oct->octeon_id))
1563 oct->fn_list.soft_reset(oct);
1564 }
60b48c5a 1565
f21fb3ed
RV		 1566 octeon_unmap_pci_barx(oct, 0);
1567 octeon_unmap_pci_barx(oct, 1);
1568
1569 /* fallthrough */
515e752d
RV		 1570 case OCT_DEV_PCI_ENABLE_DONE:
1571 pci_clear_master(oct->pci_dev);
60b48c5a
RV		 1572 /* Disable the device, releasing the PCI INT */
1573 pci_disable_device(oct->pci_dev);
1574
515e752d
RV		 1575 /* fallthrough */
1576 case OCT_DEV_BEGIN_STATE:
f21fb3ed
RV		 1577 /* Nothing to be done here either */
1578 break;
a2c64b67 1579 } /* end switch (oct->status) */
f21fb3ed
RV		 1580
1581 tasklet_kill(&oct_priv->droq_tasklet);
1582}
1583
afdf841f
RV		 1584/**
1585 * \brief Callback for rx ctrl
1586 * @param status status of request
1587 * @param buf pointer to resp structure
1588 */
1589static void rx_ctl_callback(struct octeon_device *oct,
1590 u32 status,
1591 void *buf)
1592{
1593 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
1594 struct liquidio_rx_ctl_context *ctx;
1595
1596 ctx = (struct liquidio_rx_ctl_context *)sc->ctxptr;
1597
1598 oct = lio_get_device(ctx->octeon_id);
1599 if (status)
1600 dev_err(&oct->pci_dev->dev, "rx ctl instruction failed. Status: %llx\n",
1601 CVM_CAST64(status));
1602 WRITE_ONCE(ctx->cond, 1);
1603
1604 /* This barrier is required to be sure that the response has been
1605 * written fully before waking up the handler
1606 */
1607 wmb();
1608
1609 wake_up_interruptible(&ctx->wc);
1610}
1611
f21fb3ed
RV		 1612/**
1613 * \brief Send Rx control command
1614 * @param lio per-network private data
1615 * @param start_stop whether to start or stop
1616 */
1617static void send_rx_ctrl_cmd(struct lio *lio, int start_stop)
1618{
afdf841f
RV		 1619 struct octeon_soft_command *sc;
1620 struct liquidio_rx_ctl_context *ctx;
1621 union octnet_cmd *ncmd;
1622 int ctx_size = sizeof(struct liquidio_rx_ctl_context);
1623 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1624 int retval;
f21fb3ed 1625
afdf841f
RV		 1626 if (oct->props[lio->ifidx].rx_on == start_stop)
1627 return;
f21fb3ed 1628
afdf841f
RV		 1629 sc = (struct octeon_soft_command *)
1630 octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
1631 16, ctx_size);
1632
1633 ncmd = (union octnet_cmd *)sc->virtdptr;
1634 ctx = (struct liquidio_rx_ctl_context *)sc->ctxptr;
1635
1636 WRITE_ONCE(ctx->cond, 0);
1637 ctx->octeon_id = lio_get_device_id(oct);
1638 init_waitqueue_head(&ctx->wc);
1639
1640 ncmd->u64 = 0;
1641 ncmd->s.cmd = OCTNET_CMD_RX_CTL;
1642 ncmd->s.param1 = start_stop;
1643
1644 octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1645
1646 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1647
1648 octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1649 OPCODE_NIC_CMD, 0, 0, 0);
1650
1651 sc->callback = rx_ctl_callback;
1652 sc->callback_arg = sc;
1653 sc->wait_time = 5000;
f21fb3ed 1654
afdf841f
RV		 1655 retval = octeon_send_soft_command(oct, sc);
1656 if (retval == IQ_SEND_FAILED) {
f21fb3ed 1657 netif_info(lio, rx_err, lio->netdev, "Failed to send RX Control message\n");
afdf841f
RV		 1658 } else {
1659 /* Sleep on a wait queue till the cond flag indicates that the
1660 * response arrived or timed-out.
1661 */
1662 if (sleep_cond(&ctx->wc, &ctx->cond) == -EINTR)
1663 return;
1664 oct->props[lio->ifidx].rx_on = start_stop;
1665 }
1666
1667 octeon_free_soft_command(oct, sc);
f21fb3ed
RV		 1668}
1669
1670/**
1671 * \brief Destroy NIC device interface
1672 * @param oct octeon device
1673 * @param ifidx which interface to destroy
1674 *
1675 * Cleanup associated with each interface for an Octeon device when NIC
1676 * module is being unloaded or if initialization fails during load.
1677 */
1678static void liquidio_destroy_nic_device(struct octeon_device *oct, int ifidx)
1679{
1680 struct net_device *netdev = oct->props[ifidx].netdev;
1681 struct lio *lio;
9a96bde4 1682 struct napi_struct *napi, *n;
f21fb3ed
RV		 1683
1684 if (!netdev) {
1685 dev_err(&oct->pci_dev->dev, "%s No netdevice ptr for index %d\n",
1686 __func__, ifidx);
1687 return;
1688 }
1689
1690 lio = GET_LIO(netdev);
1691
1692 dev_dbg(&oct->pci_dev->dev, "NIC device cleanup\n");
1693
f21fb3ed 1694 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING)
afdf841f 1695 liquidio_stop(netdev);
f21fb3ed 1696
7cc61db9
FM		 1697 if (fw_type_is_none()) {
1698 struct octnic_ctrl_pkt nctrl;
1699
1700 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
1701 nctrl.ncmd.s.cmd = OCTNET_CMD_RESET_PF;
1702 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
1703 octnet_send_nic_ctrl_pkt(oct, &nctrl);
1704 }
1705
9a96bde4
RV		 1706 if (oct->props[lio->ifidx].napi_enabled == 1) {
1707 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
1708 napi_disable(napi);
1709
1710 oct->props[lio->ifidx].napi_enabled = 0;
7b6b6c95
RV		 1711
1712 if (OCTEON_CN23XX_PF(oct))
1713 oct->droq[0]->ops.poll_mode = 0;
9a96bde4
RV		 1714 }
1715
f21fb3ed
RV		 1716 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED)
1717 unregister_netdev(netdev);
1718
7b6b6c95
RV		 1719 cleanup_link_status_change_wq(netdev);
1720
031d4f12
SB		 1721 cleanup_rx_oom_poll_fn(netdev);
1722
fcd2b5e3 1723 delete_glists(lio);
f21fb3ed
RV		 1724
1725 free_netdev(netdev);
1726
0cece6c5
RV		 1727 oct->props[ifidx].gmxport = -1;
1728
f21fb3ed
RV		 1729 oct->props[ifidx].netdev = NULL;
1730}
1731
1732/**
1733 * \brief Stop complete NIC functionality
1734 * @param oct octeon device
1735 */
1736static int liquidio_stop_nic_module(struct octeon_device *oct)
1737{
1738 int i, j;
1739 struct lio *lio;
1740
1741 dev_dbg(&oct->pci_dev->dev, "Stopping network interfaces\n");
1742 if (!oct->ifcount) {
1743 dev_err(&oct->pci_dev->dev, "Init for Octeon was not completed\n");
1744 return 1;
1745 }
1746
60441888
RV		 1747 spin_lock_bh(&oct->cmd_resp_wqlock);
1748 oct->cmd_resp_state = OCT_DRV_OFFLINE;
1749 spin_unlock_bh(&oct->cmd_resp_wqlock);
1750
f21fb3ed
RV		 1751 for (i = 0; i < oct->ifcount; i++) {
1752 lio = GET_LIO(oct->props[i].netdev);
1753 for (j = 0; j < lio->linfo.num_rxpciq; j++)
26236fa9
RV		 1754 octeon_unregister_droq_ops(oct,
1755 lio->linfo.rxpciq[j].s.q_no);
f21fb3ed
RV		 1756 }
1757
1758 for (i = 0; i < oct->ifcount; i++)
1759 liquidio_destroy_nic_device(oct, i);
1760
1761 dev_dbg(&oct->pci_dev->dev, "Network interfaces stopped\n");
1762 return 0;
1763}
1764
1765/**
1766 * \brief Cleans up resources at unload time
1767 * @param pdev PCI device structure
1768 */
1769static void liquidio_remove(struct pci_dev *pdev)
1770{
1771 struct octeon_device *oct_dev = pci_get_drvdata(pdev);
1772
1773 dev_dbg(&oct_dev->pci_dev->dev, "Stopping device\n");
1774
9ff1a9ba
RV		 1775 if (oct_dev->watchdog_task)
1776 kthread_stop(oct_dev->watchdog_task);
1777
f21fb3ed
RV		 1778 if (oct_dev->app_mode && (oct_dev->app_mode == CVM_DRV_NIC_APP))
1779 liquidio_stop_nic_module(oct_dev);
1780
1781 /* Reset the octeon device and cleanup all memory allocated for
1782 * the octeon device by driver.
1783 */
1784 octeon_destroy_resources(oct_dev);
1785
1786 dev_info(&oct_dev->pci_dev->dev, "Device removed\n");
1787
1788 /* This octeon device has been removed. Update the global
1789 * data structure to reflect this. Free the device structure.
1790 */
1791 octeon_free_device_mem(oct_dev);
1792}
1793
1794/**
1795 * \brief Identify the Octeon device and to map the BAR address space
1796 * @param oct octeon device
1797 */
1798static int octeon_chip_specific_setup(struct octeon_device *oct)
1799{
1800 u32 dev_id, rev_id;
1801 int ret = 1;
d3d7e6c6 1802 char *s;
f21fb3ed
RV		 1803
1804 pci_read_config_dword(oct->pci_dev, 0, &dev_id);
1805 pci_read_config_dword(oct->pci_dev, 8, &rev_id);
1806 oct->rev_id = rev_id & 0xff;
1807
1808 switch (dev_id) {
1809 case OCTEON_CN68XX_PCIID:
1810 oct->chip_id = OCTEON_CN68XX;
1811 ret = lio_setup_cn68xx_octeon_device(oct);
d3d7e6c6 1812 s = "CN68XX";
f21fb3ed
RV		 1813 break;
1814
1815 case OCTEON_CN66XX_PCIID:
1816 oct->chip_id = OCTEON_CN66XX;
1817 ret = lio_setup_cn66xx_octeon_device(oct);
d3d7e6c6 1818 s = "CN66XX";
f21fb3ed 1819 break;
d3d7e6c6 1820
72c00912
RV		 1821 case OCTEON_CN23XX_PCIID_PF:
1822 oct->chip_id = OCTEON_CN23XX_PF_VID;
1823 ret = setup_cn23xx_octeon_pf_device(oct);
1824 s = "CN23XX";
1825 break;
1826
f21fb3ed 1827 default:
d3d7e6c6 1828 s = "?";
f21fb3ed
RV		 1829 dev_err(&oct->pci_dev->dev, "Unknown device found (dev_id: %x)\n",
1830 dev_id);
1831 }
1832
1833 if (!ret)
d3d7e6c6 1834 dev_info(&oct->pci_dev->dev, "%s PASS%d.%d %s Version: %s\n", s,
f21fb3ed
RV		 1835 OCTEON_MAJOR_REV(oct),
1836 OCTEON_MINOR_REV(oct),
d3d7e6c6
RV		 1837 octeon_get_conf(oct)->card_name,
1838 LIQUIDIO_VERSION);
f21fb3ed
RV		 1839
1840 return ret;
1841}
1842
1843/**
1844 * \brief PCI initialization for each Octeon device.
1845 * @param oct octeon device
1846 */
1847static int octeon_pci_os_setup(struct octeon_device *oct)
1848{
1849 /* setup PCI stuff first */
1850 if (pci_enable_device(oct->pci_dev)) {
1851 dev_err(&oct->pci_dev->dev, "pci_enable_device failed\n");
1852 return 1;
1853 }
1854
1855 if (dma_set_mask_and_coherent(&oct->pci_dev->dev, DMA_BIT_MASK(64))) {
1856 dev_err(&oct->pci_dev->dev, "Unexpected DMA device capability\n");
515e752d 1857 pci_disable_device(oct->pci_dev);
f21fb3ed
RV		 1858 return 1;
1859 }
1860
1861 /* Enable PCI DMA Master. */
1862 pci_set_master(oct->pci_dev);
1863
1864 return 0;
1865}
1866
fcd2b5e3
RV		 1867static inline int skb_iq(struct lio *lio, struct sk_buff *skb)
1868{
1869 int q = 0;
1870
1871 if (netif_is_multiqueue(lio->netdev))
1872 q = skb->queue_mapping % lio->linfo.num_txpciq;
1873
1874 return q;
1875}
1876
f21fb3ed
RV		 1877/**
1878 * \brief Check Tx queue state for a given network buffer
1879 * @param lio per-network private data
1880 * @param skb network buffer
1881 */
1882static inline int check_txq_state(struct lio *lio, struct sk_buff *skb)
1883{
1884 int q = 0, iq = 0;
1885
1886 if (netif_is_multiqueue(lio->netdev)) {
1887 q = skb->queue_mapping;
26236fa9 1888 iq = lio->linfo.txpciq[(q % (lio->linfo.num_txpciq))].s.q_no;
f21fb3ed
RV		 1889 } else {
1890 iq = lio->txq;
26236fa9 1891 q = iq;
f21fb3ed
RV		 1892 }
1893
1894 if (octnet_iq_is_full(lio->oct_dev, iq))
1895 return 0;
26236fa9 1896
1f164717
RV		 1897 if (__netif_subqueue_stopped(lio->netdev, q)) {
1898 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq, tx_restart, 1);
26236fa9 1899 wake_q(lio->netdev, q);
1f164717 1900 }
f21fb3ed
RV		 1901 return 1;
1902}
1903
1904/**
1905 * \brief Unmap and free network buffer
1906 * @param buf buffer
1907 */
1908static void free_netbuf(void *buf)
1909{
1910 struct sk_buff *skb;
1911 struct octnet_buf_free_info *finfo;
1912 struct lio *lio;
1913
1914 finfo = (struct octnet_buf_free_info *)buf;
1915 skb = finfo->skb;
1916 lio = finfo->lio;
1917
1918 dma_unmap_single(&lio->oct_dev->pci_dev->dev, finfo->dptr, skb->len,
1919 DMA_TO_DEVICE);
1920
1921 check_txq_state(lio, skb);
1922
cabeb13b 1923 tx_buffer_free(skb);
f21fb3ed
RV		 1924}
1925
1926/**
1927 * \brief Unmap and free gather buffer
1928 * @param buf buffer
1929 */
1930static void free_netsgbuf(void *buf)
1931{
1932 struct octnet_buf_free_info *finfo;
1933 struct sk_buff *skb;
1934 struct lio *lio;
1935 struct octnic_gather *g;
fcd2b5e3 1936 int i, frags, iq;
f21fb3ed
RV		 1937
1938 finfo = (struct octnet_buf_free_info *)buf;
1939 skb = finfo->skb;
1940 lio = finfo->lio;
1941 g = finfo->g;
1942 frags = skb_shinfo(skb)->nr_frags;
1943
1944 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1945 g->sg[0].ptr[0], (skb->len - skb->data_len),
1946 DMA_TO_DEVICE);
1947
1948 i = 1;
1949 while (frags--) {
1950 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1951
1952 pci_unmap_page((lio->oct_dev)->pci_dev,
1953 g->sg[(i >> 2)].ptr[(i & 3)],
1954 frag->size, DMA_TO_DEVICE);
1955 i++;
1956 }
1957
fcd2b5e3
RV		 1958 iq = skb_iq(lio, skb);
1959 spin_lock(&lio->glist_lock[iq]);
1960 list_add_tail(&g->list, &lio->glist[iq]);
1961 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1962
1963 check_txq_state(lio, skb); /* mq support: sub-queue state check */
1964
cabeb13b 1965 tx_buffer_free(skb);
f21fb3ed
RV		 1966}
1967
1968/**
1969 * \brief Unmap and free gather buffer with response
1970 * @param buf buffer
1971 */
1972static void free_netsgbuf_with_resp(void *buf)
1973{
1974 struct octeon_soft_command *sc;
1975 struct octnet_buf_free_info *finfo;
1976 struct sk_buff *skb;
1977 struct lio *lio;
1978 struct octnic_gather *g;
fcd2b5e3 1979 int i, frags, iq;
f21fb3ed
RV		 1980
1981 sc = (struct octeon_soft_command *)buf;
1982 skb = (struct sk_buff *)sc->callback_arg;
1983 finfo = (struct octnet_buf_free_info *)&skb->cb;
1984
1985 lio = finfo->lio;
1986 g = finfo->g;
1987 frags = skb_shinfo(skb)->nr_frags;
1988
1989 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1990 g->sg[0].ptr[0], (skb->len - skb->data_len),
1991 DMA_TO_DEVICE);
1992
1993 i = 1;
1994 while (frags--) {
1995 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1996
1997 pci_unmap_page((lio->oct_dev)->pci_dev,
1998 g->sg[(i >> 2)].ptr[(i & 3)],
1999 frag->size, DMA_TO_DEVICE);
2000 i++;
2001 }
2002
fcd2b5e3
RV		 2003 iq = skb_iq(lio, skb);
2004
2005 spin_lock(&lio->glist_lock[iq]);
2006 list_add_tail(&g->list, &lio->glist[iq]);
2007 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 2008
2009 /* Don't free the skb yet */
2010
2011 check_txq_state(lio, skb);
2012}
2013
2014/**
2015 * \brief Adjust ptp frequency
2016 * @param ptp PTP clock info
2017 * @param ppb how much to adjust by, in parts-per-billion
2018 */
2019static int liquidio_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
2020{
2021 struct lio *lio = container_of(ptp, struct lio, ptp_info);
2022 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
2023 u64 comp, delta;
2024 unsigned long flags;
2025 bool neg_adj = false;
2026
2027 if (ppb < 0) {
2028 neg_adj = true;
2029 ppb = -ppb;
2030 }
2031
2032 /* The hardware adds the clock compensation value to the
2033 * PTP clock on every coprocessor clock cycle, so we
2034 * compute the delta in terms of coprocessor clocks.
2035 */
2036 delta = (u64)ppb << 32;
2037 do_div(delta, oct->coproc_clock_rate);
2038
2039 spin_lock_irqsave(&lio->ptp_lock, flags);
2040 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP);
2041 if (neg_adj)
2042 comp -= delta;
2043 else
2044 comp += delta;
2045 lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP);
2046 spin_unlock_irqrestore(&lio->ptp_lock, flags);
2047
2048 return 0;
2049}
2050
2051/**
2052 * \brief Adjust ptp time
2053 * @param ptp PTP clock info
2054 * @param delta how much to adjust by, in nanosecs
2055 */
2056static int liquidio_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
2057{
2058 unsigned long flags;
2059 struct lio *lio = container_of(ptp, struct lio, ptp_info);
2060
2061 spin_lock_irqsave(&lio->ptp_lock, flags);
2062 lio->ptp_adjust += delta;
2063 spin_unlock_irqrestore(&lio->ptp_lock, flags);
2064
2065 return 0;
2066}
2067
2068/**
2069 * \brief Get hardware clock time, including any adjustment
2070 * @param ptp PTP clock info
2071 * @param ts timespec
2072 */
2073static int liquidio_ptp_gettime(struct ptp_clock_info *ptp,
2074 struct timespec64 *ts)
2075{
2076 u64 ns;
f21fb3ed
RV		 2077 unsigned long flags;
2078 struct lio *lio = container_of(ptp, struct lio, ptp_info);
2079 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
2080
2081 spin_lock_irqsave(&lio->ptp_lock, flags);
2082 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI);
2083 ns += lio->ptp_adjust;
2084 spin_unlock_irqrestore(&lio->ptp_lock, flags);
2085
286af315 2086 *ts = ns_to_timespec64(ns);
f21fb3ed
RV		 2087
2088 return 0;
2089}
2090
2091/**
2092 * \brief Set hardware clock time. Reset adjustment
2093 * @param ptp PTP clock info
2094 * @param ts timespec
2095 */
2096static int liquidio_ptp_settime(struct ptp_clock_info *ptp,
2097 const struct timespec64 *ts)
2098{
2099 u64 ns;
2100 unsigned long flags;
2101 struct lio *lio = container_of(ptp, struct lio, ptp_info);
2102 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
2103
2104 ns = timespec_to_ns(ts);
2105
2106 spin_lock_irqsave(&lio->ptp_lock, flags);
2107 lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI);
2108 lio->ptp_adjust = 0;
2109 spin_unlock_irqrestore(&lio->ptp_lock, flags);
2110
2111 return 0;
2112}
2113
2114/**
2115 * \brief Check if PTP is enabled
2116 * @param ptp PTP clock info
2117 * @param rq request
2118 * @param on is it on
2119 */
a7d5a3dc
RV		 2120static int
2121liquidio_ptp_enable(struct ptp_clock_info *ptp __attribute__((unused)),
2122 struct ptp_clock_request *rq __attribute__((unused)),
2123 int on __attribute__((unused)))
f21fb3ed
RV		 2124{
2125 return -EOPNOTSUPP;
2126}
2127
2128/**
2129 * \brief Open PTP clock source
2130 * @param netdev network device
2131 */
2132static void oct_ptp_open(struct net_device *netdev)
2133{
2134 struct lio *lio = GET_LIO(netdev);
2135 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
2136
2137 spin_lock_init(&lio->ptp_lock);
2138
2139 snprintf(lio->ptp_info.name, 16, "%s", netdev->name);
2140 lio->ptp_info.owner = THIS_MODULE;
2141 lio->ptp_info.max_adj = 250000000;
2142 lio->ptp_info.n_alarm = 0;
2143 lio->ptp_info.n_ext_ts = 0;
2144 lio->ptp_info.n_per_out = 0;
2145 lio->ptp_info.pps = 0;
2146 lio->ptp_info.adjfreq = liquidio_ptp_adjfreq;
2147 lio->ptp_info.adjtime = liquidio_ptp_adjtime;
2148 lio->ptp_info.gettime64 = liquidio_ptp_gettime;
2149 lio->ptp_info.settime64 = liquidio_ptp_settime;
2150 lio->ptp_info.enable = liquidio_ptp_enable;
2151
2152 lio->ptp_adjust = 0;
2153
2154 lio->ptp_clock = ptp_clock_register(&lio->ptp_info,
2155 &oct->pci_dev->dev);
2156
2157 if (IS_ERR(lio->ptp_clock))
2158 lio->ptp_clock = NULL;
2159}
2160
2161/**
2162 * \brief Init PTP clock
2163 * @param oct octeon device
2164 */
2165static void liquidio_ptp_init(struct octeon_device *oct)
2166{
2167 u64 clock_comp, cfg;
2168
2169 clock_comp = (u64)NSEC_PER_SEC << 32;
2170 do_div(clock_comp, oct->coproc_clock_rate);
2171 lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP);
2172
2173 /* Enable */
2174 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG);
2175 lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG);
2176}
2177
2178/**
2179 * \brief Load firmware to device
2180 * @param oct octeon device
2181 *
2182 * Maps device to firmware filename, requests firmware, and downloads it
2183 */
2184static int load_firmware(struct octeon_device *oct)
2185{
2186 int ret = 0;
2187 const struct firmware *fw;
2188 char fw_name[LIO_MAX_FW_FILENAME_LEN];
2189 char *tmp_fw_type;
2190
7cc61db9 2191 if (fw_type_is_none()) {
f21fb3ed
RV		 2192 dev_info(&oct->pci_dev->dev, "Skipping firmware load\n");
2193 return ret;
2194 }
2195
2196 if (fw_type[0] == '\0')
2197 tmp_fw_type = LIO_FW_NAME_TYPE_NIC;
2198 else
2199 tmp_fw_type = fw_type;
2200
2201 sprintf(fw_name, "%s%s%s_%s%s", LIO_FW_DIR, LIO_FW_BASE_NAME,
2202 octeon_get_conf(oct)->card_name, tmp_fw_type,
2203 LIO_FW_NAME_SUFFIX);
2204
2205 ret = request_firmware(&fw, fw_name, &oct->pci_dev->dev);
2206 if (ret) {
2207 dev_err(&oct->pci_dev->dev, "Request firmware failed. Could not find file %s.\n.",
2208 fw_name);
d3d7e6c6 2209 release_firmware(fw);
f21fb3ed
RV		 2210 return ret;
2211 }
2212
2213 ret = octeon_download_firmware(oct, fw->data, fw->size);
2214
2215 release_firmware(fw);
2216
2217 return ret;
2218}
2219
2220/**
2221 * \brief Setup output queue
2222 * @param oct octeon device
2223 * @param q_no which queue
2224 * @param num_descs how many descriptors
2225 * @param desc_size size of each descriptor
2226 * @param app_ctx application context
2227 */
2228static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs,
2229 int desc_size, void *app_ctx)
2230{
2231 int ret_val = 0;
2232
2233 dev_dbg(&oct->pci_dev->dev, "Creating Droq: %d\n", q_no);
2234 /* droq creation and local register settings. */
2235 ret_val = octeon_create_droq(oct, q_no, num_descs, desc_size, app_ctx);
08a965ec 2236 if (ret_val < 0)
f21fb3ed
RV		 2237 return ret_val;
2238
2239 if (ret_val == 1) {
2240 dev_dbg(&oct->pci_dev->dev, "Using default droq %d\n", q_no);
2241 return 0;
2242 }
2243 /* tasklet creation for the droq */
2244
2245 /* Enable the droq queues */
2246 octeon_set_droq_pkt_op(oct, q_no, 1);
2247
2248 /* Send Credit for Octeon Output queues. Credits are always
2249 * sent after the output queue is enabled.
2250 */
2251 writel(oct->droq[q_no]->max_count,
2252 oct->droq[q_no]->pkts_credit_reg);
2253
2254 return ret_val;
2255}
2256
2257/**
2258 * \brief Callback for getting interface configuration
2259 * @param status status of request
2260 * @param buf pointer to resp structure
2261 */
2262static void if_cfg_callback(struct octeon_device *oct,
a7d5a3dc 2263 u32 status __attribute__((unused)),
f21fb3ed
RV		 2264 void *buf)
2265{
2266 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
2267 struct liquidio_if_cfg_resp *resp;
2268 struct liquidio_if_cfg_context *ctx;
2269
2270 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
30136395 2271 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
f21fb3ed
RV		 2272
2273 oct = lio_get_device(ctx->octeon_id);
2274 if (resp->status)
c5b71e63
RF		 2275 dev_err(&oct->pci_dev->dev, "nic if cfg instruction failed. Status: 0x%llx (0x%08x)\n",
2276 CVM_CAST64(resp->status), status);
a7d5a3dc 2277 WRITE_ONCE(ctx->cond, 1);
f21fb3ed 2278
d3d7e6c6
RV		 2279 snprintf(oct->fw_info.liquidio_firmware_version, 32, "%s",
2280 resp->cfg_info.liquidio_firmware_version);
2281
f21fb3ed
RV		 2282 /* This barrier is required to be sure that the response has been
2283 * written fully before waking up the handler
2284 */
2285 wmb();
2286
2287 wake_up_interruptible(&ctx->wc);
2288}
2289
f21fb3ed
RV		 2290/** Routine to push packets arriving on Octeon interface upto network layer.
2291 * @param oct_id - octeon device id.
2292 * @param skbuff - skbuff struct to be passed to network layer.
2293 * @param len - size of total data received.
2294 * @param rh - Control header associated with the packet
2295 * @param param - additional control data with the packet
0cece6c5 2296 * @param arg - farg registered in droq_ops
f21fb3ed
RV		 2297 */
2298static void
a7d5a3dc 2299liquidio_push_packet(u32 octeon_id __attribute__((unused)),
f21fb3ed
RV		 2300 void *skbuff,
2301 u32 len,
2302 union octeon_rh *rh,
0cece6c5
RV		 2303 void *param,
2304 void *arg)
f21fb3ed
RV		 2305{
2306 struct napi_struct *napi = param;
f21fb3ed
RV		 2307 struct sk_buff *skb = (struct sk_buff *)skbuff;
2308 struct skb_shared_hwtstamps *shhwtstamps;
2309 u64 ns;
0da0b77c 2310 u16 vtag = 0;
de28c99d 2311 u32 r_dh_off;
0cece6c5 2312 struct net_device *netdev = (struct net_device *)arg;
f21fb3ed
RV		 2313 struct octeon_droq *droq = container_of(param, struct octeon_droq,
2314 napi);
2315 if (netdev) {
2316 int packet_was_received;
2317 struct lio *lio = GET_LIO(netdev);
a5b37888 2318 struct octeon_device *oct = lio->oct_dev;
f21fb3ed
RV		 2319
2320 /* Do not proceed if the interface is not in RUNNING state. */
2321 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) {
2322 recv_buffer_free(skb);
2323 droq->stats.rx_dropped++;
2324 return;
2325 }
2326
2327 skb->dev = netdev;
2328
26236fa9 2329 skb_record_rx_queue(skb, droq->q_no);
cabeb13b
RV		 2330 if (likely(len > MIN_SKB_SIZE)) {
2331 struct octeon_skb_page_info *pg_info;
2332 unsigned char *va;
2333
2334 pg_info = ((struct octeon_skb_page_info *)(skb->cb));
2335 if (pg_info->page) {
2336 /* For Paged allocation use the frags */
2337 va = page_address(pg_info->page) +
2338 pg_info->page_offset;
2339 memcpy(skb->data, va, MIN_SKB_SIZE);
2340 skb_put(skb, MIN_SKB_SIZE);
2341 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2342 pg_info->page,
2343 pg_info->page_offset +
2344 MIN_SKB_SIZE,
2345 len - MIN_SKB_SIZE,
2346 LIO_RXBUFFER_SZ);
2347 }
2348 } else {
2349 struct octeon_skb_page_info *pg_info =
2350 ((struct octeon_skb_page_info *)(skb->cb));
2351 skb_copy_to_linear_data(skb, page_address(pg_info->page)
2352 + pg_info->page_offset, len);
2353 skb_put(skb, len);
2354 put_page(pg_info->page);
2355 }
26236fa9 2356
de28c99d
PK		 2357 r_dh_off = (rh->r_dh.len - 1) * BYTES_PER_DHLEN_UNIT;
2358
a5b37888
RV		 2359 if (((oct->chip_id == OCTEON_CN66XX) ||
2360 (oct->chip_id == OCTEON_CN68XX)) &&
2361 ptp_enable) {
2362 if (rh->r_dh.has_hwtstamp) {
2363 /* timestamp is included from the hardware at
2364 * the beginning of the packet.
f21fb3ed 2365 */
a5b37888
RV		 2366 if (ifstate_check
2367 (lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED)) {
2368 /* Nanoseconds are in the first 64-bits
2369 * of the packet.
2370 */
de28c99d
PK		 2371 memcpy(&ns, (skb->data + r_dh_off),
2372 sizeof(ns));
2373 r_dh_off -= BYTES_PER_DHLEN_UNIT;
a5b37888
RV		 2374 shhwtstamps = skb_hwtstamps(skb);
2375 shhwtstamps->hwtstamp =
2376 ns_to_ktime(ns +
2377 lio->ptp_adjust);
2378 }
f21fb3ed 2379 }
f21fb3ed
RV		 2380 }
2381
de28c99d
PK		 2382 if (rh->r_dh.has_hash) {
2383 __be32 *hash_be = (__be32 *)(skb->data + r_dh_off);
2384 u32 hash = be32_to_cpu(*hash_be);
2385
2386 skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
2387 r_dh_off -= BYTES_PER_DHLEN_UNIT;
2388 }
2389
2390 skb_pull(skb, rh->r_dh.len * BYTES_PER_DHLEN_UNIT);
2391
f21fb3ed 2392 skb->protocol = eth_type_trans(skb, skb->dev);
f21fb3ed 2393 if ((netdev->features & NETIF_F_RXCSUM) &&
01fb237a
RV		 2394 (((rh->r_dh.encap_on) &&
2395 (rh->r_dh.csum_verified & CNNIC_TUN_CSUM_VERIFIED)) ||
2396 (!(rh->r_dh.encap_on) &&
2397 (rh->r_dh.csum_verified & CNNIC_CSUM_VERIFIED))))
f21fb3ed
RV		 2398 /* checksum has already been verified */
2399 skb->ip_summed = CHECKSUM_UNNECESSARY;
2400 else
2401 skb->ip_summed = CHECKSUM_NONE;
2402
01fb237a
RV		 2403 /* Setting Encapsulation field on basis of status received
2404 * from the firmware
2405 */
2406 if (rh->r_dh.encap_on) {
2407 skb->encapsulation = 1;
2408 skb->csum_level = 1;
2409 droq->stats.rx_vxlan++;
2410 }
2411
0da0b77c
RV		 2412 /* inbound VLAN tag */
2413 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2414 (rh->r_dh.vlan != 0)) {
2415 u16 vid = rh->r_dh.vlan;
2416 u16 priority = rh->r_dh.priority;
2417
2418 vtag = priority << 13 | vid;
2419 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
2420 }
2421
f21fb3ed
RV		 2422 packet_was_received = napi_gro_receive(napi, skb) != GRO_DROP;
2423
2424 if (packet_was_received) {
2425 droq->stats.rx_bytes_received += len;
2426 droq->stats.rx_pkts_received++;
f21fb3ed
RV		 2427 } else {
2428 droq->stats.rx_dropped++;
2429 netif_info(lio, rx_err, lio->netdev,
2430 "droq:%d error rx_dropped:%llu\n",
2431 droq->q_no, droq->stats.rx_dropped);
2432 }
2433
2434 } else {
2435 recv_buffer_free(skb);
2436 }
2437}
2438
2439/**
2440 * \brief wrapper for calling napi_schedule
2441 * @param param parameters to pass to napi_schedule
2442 *
2443 * Used when scheduling on different CPUs
2444 */
2445static void napi_schedule_wrapper(void *param)
2446{
2447 struct napi_struct *napi = param;
2448
2449 napi_schedule(napi);
2450}
2451
2452/**
2453 * \brief callback when receive interrupt occurs and we are in NAPI mode
2454 * @param arg pointer to octeon output queue
2455 */
2456static void liquidio_napi_drv_callback(void *arg)
2457{
9ded1a51 2458 struct octeon_device *oct;
f21fb3ed
RV		 2459 struct octeon_droq *droq = arg;
2460 int this_cpu = smp_processor_id();
2461
9ded1a51
RV		 2462 oct = droq->oct_dev;
2463
2464 if (OCTEON_CN23XX_PF(oct) || droq->cpu_id == this_cpu) {
2465 napi_schedule_irqoff(&droq->napi);
f21fb3ed
RV		 2466 } else {
2467 struct call_single_data *csd = &droq->csd;
2468
2469 csd->func = napi_schedule_wrapper;
2470 csd->info = &droq->napi;
2471 csd->flags = 0;
2472
2473 smp_call_function_single_async(droq->cpu_id, csd);
2474 }
2475}
2476
f21fb3ed
RV		 2477/**
2478 * \brief Entry point for NAPI polling
2479 * @param napi NAPI structure
2480 * @param budget maximum number of items to process
2481 */
2482static int liquidio_napi_poll(struct napi_struct *napi, int budget)
2483{
2484 struct octeon_droq *droq;
2485 int work_done;
9a96bde4
RV		 2486 int tx_done = 0, iq_no;
2487 struct octeon_instr_queue *iq;
2488 struct octeon_device *oct;
f21fb3ed
RV		 2489
2490 droq = container_of(napi, struct octeon_droq, napi);
9a96bde4
RV		 2491 oct = droq->oct_dev;
2492 iq_no = droq->q_no;
2493 /* Handle Droq descriptors */
2494 work_done = octeon_process_droq_poll_cmd(oct, droq->q_no,
2495 POLL_EVENT_PROCESS_PKTS,
2496 budget);
f21fb3ed 2497
9a96bde4
RV		 2498 /* Flush the instruction queue */
2499 iq = oct->instr_queue[iq_no];
2500 if (iq) {
6069f3fb
VB		 2501 if (atomic_read(&iq->instr_pending))
2502 /* Process iq buffers with in the budget limits */
2503 tx_done = octeon_flush_iq(oct, iq, budget);
2504 else
2505 tx_done = 1;
9a96bde4
RV		 2506 /* Update iq read-index rather than waiting for next interrupt.
2507 * Return back if tx_done is false.
2508 */
2509 update_txq_status(oct, iq_no);
9a96bde4
RV		 2510 } else {
2511 dev_err(&oct->pci_dev->dev, "%s: iq (%d) num invalid\n",
2512 __func__, iq_no);
2513 }
f21fb3ed 2514
cdb478e5
SB		 2515 /* force enable interrupt if reg cnts are high to avoid wraparound */
2516 if ((work_done < budget && tx_done) ||
76e0e70e 2517 (iq && iq->pkt_in_done >= MAX_REG_CNT) ||
cdb478e5
SB		 2518 (droq->pkt_count >= MAX_REG_CNT)) {
2519 tx_done = 1;
6ad20165 2520 napi_complete_done(napi, work_done);
f21fb3ed
RV		 2521 octeon_process_droq_poll_cmd(droq->oct_dev, droq->q_no,
2522 POLL_EVENT_ENABLE_INTR, 0);
2523 return 0;
2524 }
2525
9a96bde4 2526 return (!tx_done) ? (budget) : (work_done);
f21fb3ed
RV		 2527}
2528
2529/**
2530 * \brief Setup input and output queues
2531 * @param octeon_dev octeon device
a2c64b67 2532 * @param ifidx Interface Index
f21fb3ed
RV		 2533 *
2534 * Note: Queues are with respect to the octeon device. Thus
2535 * an input queue is for egress packets, and output queues
2536 * are for ingress packets.
2537 */
2538static inline int setup_io_queues(struct octeon_device *octeon_dev,
0cece6c5 2539 int ifidx)
f21fb3ed 2540{
0cece6c5
RV		 2541 struct octeon_droq_ops droq_ops;
2542 struct net_device *netdev;
f21fb3ed
RV		 2543 static int cpu_id;
2544 static int cpu_id_modulus;
2545 struct octeon_droq *droq;
2546 struct napi_struct *napi;
2547 int q, q_no, retval = 0;
2548 struct lio *lio;
2549 int num_tx_descs;
2550
0cece6c5
RV		 2551 netdev = octeon_dev->props[ifidx].netdev;
2552
2553 lio = GET_LIO(netdev);
f21fb3ed 2554
0cece6c5 2555 memset(&droq_ops, 0, sizeof(struct octeon_droq_ops));
f21fb3ed 2556
0cece6c5
RV		 2557 droq_ops.fptr = liquidio_push_packet;
2558 droq_ops.farg = (void *)netdev;
2559
2560 droq_ops.poll_mode = 1;
2561 droq_ops.napi_fn = liquidio_napi_drv_callback;
2562 cpu_id = 0;
2563 cpu_id_modulus = num_present_cpus();
f21fb3ed
RV		 2564
2565 /* set up DROQs. */
2566 for (q = 0; q < lio->linfo.num_rxpciq; q++) {
26236fa9
RV		 2567 q_no = lio->linfo.rxpciq[q].s.q_no;
2568 dev_dbg(&octeon_dev->pci_dev->dev,
2569 "setup_io_queues index:%d linfo.rxpciq.s.q_no:%d\n",
2570 q, q_no);
f21fb3ed
RV		 2571 retval = octeon_setup_droq(octeon_dev, q_no,
2572 CFG_GET_NUM_RX_DESCS_NIC_IF
2573 (octeon_get_conf(octeon_dev),
2574 lio->ifidx),
2575 CFG_GET_NUM_RX_BUF_SIZE_NIC_IF
2576 (octeon_get_conf(octeon_dev),
2577 lio->ifidx), NULL);
2578 if (retval) {
2579 dev_err(&octeon_dev->pci_dev->dev,
32581245 2580 "%s : Runtime DROQ(RxQ) creation failed.\n",
f21fb3ed
RV		 2581 __func__);
2582 return 1;
2583 }
2584
2585 droq = octeon_dev->droq[q_no];
2586 napi = &droq->napi;
1b7c55c4
RV		 2587 dev_dbg(&octeon_dev->pci_dev->dev, "netif_napi_add netdev:%llx oct:%llx pf_num:%d\n",
2588 (u64)netdev, (u64)octeon_dev, octeon_dev->pf_num);
0cece6c5 2589 netif_napi_add(netdev, napi, liquidio_napi_poll, 64);
f21fb3ed
RV		 2590
2591 /* designate a CPU for this droq */
2592 droq->cpu_id = cpu_id;
2593 cpu_id++;
2594 if (cpu_id >= cpu_id_modulus)
2595 cpu_id = 0;
2596
2597 octeon_register_droq_ops(octeon_dev, q_no, &droq_ops);
2598 }
2599
7b6b6c95
RV		 2600 if (OCTEON_CN23XX_PF(octeon_dev)) {
2601 /* 23XX PF can receive control messages (via the first PF-owned
2602 * droq) from the firmware even if the ethX interface is down,
2603 * so that's why poll_mode must be off for the first droq.
2604 */
2605 octeon_dev->droq[0]->ops.poll_mode = 0;
2606 }
2607
f21fb3ed
RV		 2608 /* set up IQs. */
2609 for (q = 0; q < lio->linfo.num_txpciq; q++) {
2610 num_tx_descs = CFG_GET_NUM_TX_DESCS_NIC_IF(octeon_get_conf
2611 (octeon_dev),
2612 lio->ifidx);
0cece6c5
RV		 2613 retval = octeon_setup_iq(octeon_dev, ifidx, q,
2614 lio->linfo.txpciq[q], num_tx_descs,
2615 netdev_get_tx_queue(netdev, q));
f21fb3ed
RV		 2616 if (retval) {
2617 dev_err(&octeon_dev->pci_dev->dev,
2618 " %s : Runtime IQ(TxQ) creation failed.\n",
2619 __func__);
2620 return 1;
2621 }
35ae57ea
RF		 2622
2623 if (octeon_dev->ioq_vector) {
2624 struct octeon_ioq_vector *ioq_vector;
2625
2626 ioq_vector = &octeon_dev->ioq_vector[q];
2627 netif_set_xps_queue(netdev,
2628 &ioq_vector->affinity_mask,
2629 ioq_vector->iq_index);
2630 }
f21fb3ed
RV		 2631 }
2632
2633 return 0;
2634}
2635
2636/**
2637 * \brief Poll routine for checking transmit queue status
2638 * @param work work_struct data structure
2639 */
2640static void octnet_poll_check_txq_status(struct work_struct *work)
2641{
2642 struct cavium_wk *wk = (struct cavium_wk *)work;
2643 struct lio *lio = (struct lio *)wk->ctxptr;
2644
2645 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING))
2646 return;
2647
2648 check_txq_status(lio);
2649 queue_delayed_work(lio->txq_status_wq.wq,
2650 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2651}
2652
2653/**
2654 * \brief Sets up the txq poll check
2655 * @param netdev network device
2656 */
5b07aee1 2657static inline int setup_tx_poll_fn(struct net_device *netdev)
f21fb3ed
RV		 2658{
2659 struct lio *lio = GET_LIO(netdev);
2660 struct octeon_device *oct = lio->oct_dev;
2661
292b9dab
BS		 2662 lio->txq_status_wq.wq = alloc_workqueue("txq-status",
2663 WQ_MEM_RECLAIM, 0);
f21fb3ed
RV		 2664 if (!lio->txq_status_wq.wq) {
2665 dev_err(&oct->pci_dev->dev, "unable to create cavium txq status wq\n");
5b07aee1 2666 return -1;
f21fb3ed
RV		 2667 }
2668 INIT_DELAYED_WORK(&lio->txq_status_wq.wk.work,
2669 octnet_poll_check_txq_status);
2670 lio->txq_status_wq.wk.ctxptr = lio;
2671 queue_delayed_work(lio->txq_status_wq.wq,
2672 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
5b07aee1 2673 return 0;
f21fb3ed
RV		 2674}
2675
9a96bde4
RV		 2676static inline void cleanup_tx_poll_fn(struct net_device *netdev)
2677{
2678 struct lio *lio = GET_LIO(netdev);
2679
5b07aee1
RV		 2680 if (lio->txq_status_wq.wq) {
2681 cancel_delayed_work_sync(&lio->txq_status_wq.wk.work);
2682 destroy_workqueue(lio->txq_status_wq.wq);
2683 }
9a96bde4
RV		 2684}
2685
f21fb3ed
RV		 2686/**
2687 * \brief Net device open for LiquidIO
2688 * @param netdev network device
2689 */
2690static int liquidio_open(struct net_device *netdev)
2691{
2692 struct lio *lio = GET_LIO(netdev);
2693 struct octeon_device *oct = lio->oct_dev;
2694 struct napi_struct *napi, *n;
2695
9a96bde4
RV		 2696 if (oct->props[lio->ifidx].napi_enabled == 0) {
2697 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
2698 napi_enable(napi);
2699
2700 oct->props[lio->ifidx].napi_enabled = 1;
7b6b6c95
RV		 2701
2702 if (OCTEON_CN23XX_PF(oct))
2703 oct->droq[0]->ops.poll_mode = 1;
9a96bde4 2704 }
f21fb3ed 2705
9feb16ae
PK		 2706 if ((oct->chip_id == OCTEON_CN66XX || oct->chip_id == OCTEON_CN68XX) &&
2707 ptp_enable)
2708 oct_ptp_open(netdev);
f21fb3ed
RV		 2709
2710 ifstate_set(lio, LIO_IFSTATE_RUNNING);
9a96bde4 2711
7b6b6c95
RV		 2712 /* Ready for link status updates */
2713 lio->intf_open = 1;
2714
2715 netif_info(lio, ifup, lio->netdev, "Interface Open, ready for traffic\n");
2716
5b07aee1
RV		 2717 if (OCTEON_CN23XX_PF(oct)) {
2718 if (!oct->msix_on)
2719 if (setup_tx_poll_fn(netdev))
2720 return -1;
2721 } else {
2722 if (setup_tx_poll_fn(netdev))
2723 return -1;
2724 }
9a96bde4 2725
f21fb3ed
RV		 2726 start_txq(netdev);
2727
f21fb3ed
RV		 2728 /* tell Octeon to start forwarding packets to host */
2729 send_rx_ctrl_cmd(lio, 1);
2730
f21fb3ed
RV		 2731 dev_info(&oct->pci_dev->dev, "%s interface is opened\n",
2732 netdev->name);
2733
2734 return 0;
2735}
2736
2737/**
2738 * \brief Net device stop for LiquidIO
2739 * @param netdev network device
2740 */
2741static int liquidio_stop(struct net_device *netdev)
2742{
f21fb3ed
RV		 2743 struct lio *lio = GET_LIO(netdev);
2744 struct octeon_device *oct = lio->oct_dev;
2745
9a96bde4
RV		 2746 ifstate_reset(lio, LIO_IFSTATE_RUNNING);
2747
2748 netif_tx_disable(netdev);
2749
f21fb3ed 2750 /* Inform that netif carrier is down */
9a96bde4 2751 netif_carrier_off(netdev);
f21fb3ed 2752 lio->intf_open = 0;
0cece6c5
RV		 2753 lio->linfo.link.s.link_up = 0;
2754 lio->link_changes++;
f21fb3ed 2755
cb2336b5 2756 /* Tell Octeon that nic interface is down. */
f21fb3ed
RV		 2757 send_rx_ctrl_cmd(lio, 0);
2758
5b07aee1
RV		 2759 if (OCTEON_CN23XX_PF(oct)) {
2760 if (!oct->msix_on)
2761 cleanup_tx_poll_fn(netdev);
2762 } else {
2763 cleanup_tx_poll_fn(netdev);
2764 }
f21fb3ed
RV		 2765
2766 if (lio->ptp_clock) {
2767 ptp_clock_unregister(lio->ptp_clock);
2768 lio->ptp_clock = NULL;
2769 }
2770
f21fb3ed 2771 dev_info(&oct->pci_dev->dev, "%s interface is stopped\n", netdev->name);
f21fb3ed
RV		 2772
2773 return 0;
2774}
2775
f21fb3ed
RV		 2776/**
2777 * \brief Converts a mask based on net device flags
2778 * @param netdev network device
2779 *
2780 * This routine generates a octnet_ifflags mask from the net device flags
2781 * received from the OS.
2782 */
2783static inline enum octnet_ifflags get_new_flags(struct net_device *netdev)
2784{
2785 enum octnet_ifflags f = OCTNET_IFFLAG_UNICAST;
2786
2787 if (netdev->flags & IFF_PROMISC)
2788 f |= OCTNET_IFFLAG_PROMISC;
2789
2790 if (netdev->flags & IFF_ALLMULTI)
2791 f |= OCTNET_IFFLAG_ALLMULTI;
2792
2793 if (netdev->flags & IFF_MULTICAST) {
2794 f |= OCTNET_IFFLAG_MULTICAST;
2795
2796 /* Accept all multicast addresses if there are more than we
2797 * can handle
2798 */
2799 if (netdev_mc_count(netdev) > MAX_OCTEON_MULTICAST_ADDR)
2800 f |= OCTNET_IFFLAG_ALLMULTI;
2801 }
2802
2803 if (netdev->flags & IFF_BROADCAST)
2804 f |= OCTNET_IFFLAG_BROADCAST;
2805
2806 return f;
2807}
2808
2809/**
2810 * \brief Net device set_multicast_list
2811 * @param netdev network device
2812 */
2813static void liquidio_set_mcast_list(struct net_device *netdev)
2814{
2815 struct lio *lio = GET_LIO(netdev);
2816 struct octeon_device *oct = lio->oct_dev;
2817 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2818 struct netdev_hw_addr *ha;
2819 u64 *mc;
a7d5a3dc 2820 int ret;
f21fb3ed
RV		 2821 int mc_count = min(netdev_mc_count(netdev), MAX_OCTEON_MULTICAST_ADDR);
2822
2823 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2824
2825 /* Create a ctrl pkt command to be sent to core app. */
2826 nctrl.ncmd.u64 = 0;
2827 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_MULTI_LIST;
0cece6c5
RV		 2828 nctrl.ncmd.s.param1 = get_new_flags(netdev);
2829 nctrl.ncmd.s.param2 = mc_count;
f21fb3ed 2830 nctrl.ncmd.s.more = mc_count;
0cece6c5 2831 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2832 nctrl.netpndev = (u64)netdev;
2833 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2834
2835 /* copy all the addresses into the udd */
f21fb3ed
RV		 2836 mc = &nctrl.udd[0];
2837 netdev_for_each_mc_addr(ha, netdev) {
2838 *mc = 0;
2839 memcpy(((u8 *)mc) + 2, ha->addr, ETH_ALEN);
2840 /* no need to swap bytes */
2841
2842 if (++mc > &nctrl.udd[mc_count])
2843 break;
2844 }
2845
2846 /* Apparently, any activity in this call from the kernel has to
2847 * be atomic. So we won't wait for response.
2848 */
2849 nctrl.wait_time = 0;
2850
0cece6c5 2851 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2852 if (ret < 0) {
2853 dev_err(&oct->pci_dev->dev, "DEVFLAGS change failed in core (ret: 0x%x)\n",
2854 ret);
2855 }
2856}
2857
2858/**
2859 * \brief Net device set_mac_address
2860 * @param netdev network device
2861 */
2862static int liquidio_set_mac(struct net_device *netdev, void *p)
2863{
2864 int ret = 0;
2865 struct lio *lio = GET_LIO(netdev);
2866 struct octeon_device *oct = lio->oct_dev;
2867 struct sockaddr *addr = (struct sockaddr *)p;
2868 struct octnic_ctrl_pkt nctrl;
f21fb3ed 2869
0cece6c5 2870 if (!is_valid_ether_addr(addr->sa_data))
f21fb3ed
RV		 2871 return -EADDRNOTAVAIL;
2872
2873 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2874
2875 nctrl.ncmd.u64 = 0;
2876 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
0cece6c5 2877 nctrl.ncmd.s.param1 = 0;
f21fb3ed 2878 nctrl.ncmd.s.more = 1;
0cece6c5 2879 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2880 nctrl.netpndev = (u64)netdev;
2881 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2882 nctrl.wait_time = 100;
2883
2884 nctrl.udd[0] = 0;
2885 /* The MAC Address is presented in network byte order. */
2886 memcpy((u8 *)&nctrl.udd[0] + 2, addr->sa_data, ETH_ALEN);
2887
0cece6c5 2888 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2889 if (ret < 0) {
2890 dev_err(&oct->pci_dev->dev, "MAC Address change failed\n");
2891 return -ENOMEM;
2892 }
2893 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2894 memcpy(((u8 *)&lio->linfo.hw_addr) + 2, addr->sa_data, ETH_ALEN);
2895
2896 return 0;
2897}
2898
2899/**
2900 * \brief Net device get_stats
2901 * @param netdev network device
2902 */
2903static struct net_device_stats *liquidio_get_stats(struct net_device *netdev)
2904{
2905 struct lio *lio = GET_LIO(netdev);
2906 struct net_device_stats *stats = &netdev->stats;
2907 struct octeon_device *oct;
2908 u64 pkts = 0, drop = 0, bytes = 0;
2909 struct oct_droq_stats *oq_stats;
2910 struct oct_iq_stats *iq_stats;
2911 int i, iq_no, oq_no;
2912
2913 oct = lio->oct_dev;
2914
2915 for (i = 0; i < lio->linfo.num_txpciq; i++) {
26236fa9 2916 iq_no = lio->linfo.txpciq[i].s.q_no;
f21fb3ed
RV		 2917 iq_stats = &oct->instr_queue[iq_no]->stats;
2918 pkts += iq_stats->tx_done;
2919 drop += iq_stats->tx_dropped;
2920 bytes += iq_stats->tx_tot_bytes;
2921 }
2922
2923 stats->tx_packets = pkts;
2924 stats->tx_bytes = bytes;
2925 stats->tx_dropped = drop;
2926
2927 pkts = 0;
2928 drop = 0;
2929 bytes = 0;
2930
2931 for (i = 0; i < lio->linfo.num_rxpciq; i++) {
26236fa9 2932 oq_no = lio->linfo.rxpciq[i].s.q_no;
f21fb3ed
RV		 2933 oq_stats = &oct->droq[oq_no]->stats;
2934 pkts += oq_stats->rx_pkts_received;
2935 drop += (oq_stats->rx_dropped +
2936 oq_stats->dropped_nodispatch +
2937 oq_stats->dropped_toomany +
2938 oq_stats->dropped_nomem);
2939 bytes += oq_stats->rx_bytes_received;
2940 }
2941
2942 stats->rx_bytes = bytes;
2943 stats->rx_packets = pkts;
2944 stats->rx_dropped = drop;
2945
2946 return stats;
2947}
2948
2949/**
2950 * \brief Net device change_mtu
2951 * @param netdev network device
2952 */
2953static int liquidio_change_mtu(struct net_device *netdev, int new_mtu)
2954{
2955 struct lio *lio = GET_LIO(netdev);
2956 struct octeon_device *oct = lio->oct_dev;
2957 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2958 int ret = 0;
2959
f21fb3ed
RV		 2960 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2961
2962 nctrl.ncmd.u64 = 0;
2963 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MTU;
0cece6c5
RV		 2964 nctrl.ncmd.s.param1 = new_mtu;
2965 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2966 nctrl.wait_time = 100;
2967 nctrl.netpndev = (u64)netdev;
2968 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2969
0cece6c5 2970 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2971 if (ret < 0) {
2972 dev_err(&oct->pci_dev->dev, "Failed to set MTU\n");
2973 return -1;
2974 }
2975
2976 lio->mtu = new_mtu;
2977
2978 return 0;
2979}
2980
2981/**
2982 * \brief Handler for SIOCSHWTSTAMP ioctl
2983 * @param netdev network device
2984 * @param ifr interface request
2985 * @param cmd command
2986 */
a7d5a3dc 2987static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
f21fb3ed
RV		 2988{
2989 struct hwtstamp_config conf;
2990 struct lio *lio = GET_LIO(netdev);
2991
2992 if (copy_from_user(&conf, ifr->ifr_data, sizeof(conf)))
2993 return -EFAULT;
2994
2995 if (conf.flags)
2996 return -EINVAL;
2997
2998 switch (conf.tx_type) {
2999 case HWTSTAMP_TX_ON:
3000 case HWTSTAMP_TX_OFF:
3001 break;
3002 default:
3003 return -ERANGE;
3004 }
3005
3006 switch (conf.rx_filter) {
3007 case HWTSTAMP_FILTER_NONE:
3008 break;
3009 case HWTSTAMP_FILTER_ALL:
3010 case HWTSTAMP_FILTER_SOME:
3011 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3012 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3013 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3014 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3015 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3016 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3017 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3018 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3019 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3020 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3021 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3022 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3023 conf.rx_filter = HWTSTAMP_FILTER_ALL;
3024 break;
3025 default:
3026 return -ERANGE;
3027 }
3028
3029 if (conf.rx_filter == HWTSTAMP_FILTER_ALL)
3030 ifstate_set(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
3031
3032 else
3033 ifstate_reset(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
3034
3035 return copy_to_user(ifr->ifr_data, &conf, sizeof(conf)) ? -EFAULT : 0;
3036}
3037
3038/**
3039 * \brief ioctl handler
3040 * @param netdev network device
3041 * @param ifr interface request
3042 * @param cmd command
3043 */
3044static int liquidio_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3045{
9feb16ae
PK		 3046 struct lio *lio = GET_LIO(netdev);
3047
f21fb3ed
RV		 3048 switch (cmd) {
3049 case SIOCSHWTSTAMP:
9feb16ae
PK		 3050 if ((lio->oct_dev->chip_id == OCTEON_CN66XX ||
3051 lio->oct_dev->chip_id == OCTEON_CN68XX) && ptp_enable)
3052 return hwtstamp_ioctl(netdev, ifr);
f21fb3ed
RV		 3053 default:
3054 return -EOPNOTSUPP;
3055 }
3056}
3057
3058/**
3059 * \brief handle a Tx timestamp response
3060 * @param status response status
3061 * @param buf pointer to skb
3062 */
3063static void handle_timestamp(struct octeon_device *oct,
3064 u32 status,
3065 void *buf)
3066{
3067 struct octnet_buf_free_info *finfo;
3068 struct octeon_soft_command *sc;
3069 struct oct_timestamp_resp *resp;
3070 struct lio *lio;
3071 struct sk_buff *skb = (struct sk_buff *)buf;
3072
3073 finfo = (struct octnet_buf_free_info *)skb->cb;
3074 lio = finfo->lio;
3075 sc = finfo->sc;
3076 oct = lio->oct_dev;
3077 resp = (struct oct_timestamp_resp *)sc->virtrptr;
3078
3079 if (status != OCTEON_REQUEST_DONE) {
3080 dev_err(&oct->pci_dev->dev, "Tx timestamp instruction failed. Status: %llx\n",
3081 CVM_CAST64(status));
3082 resp->timestamp = 0;
3083 }
3084
3085 octeon_swap_8B_data(&resp->timestamp, 1);
3086
19a6d156 3087 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) != 0)) {
f21fb3ed
RV		 3088 struct skb_shared_hwtstamps ts;
3089 u64 ns = resp->timestamp;
3090
3091 netif_info(lio, tx_done, lio->netdev,
3092 "Got resulting SKBTX_HW_TSTAMP skb=%p ns=%016llu\n",
3093 skb, (unsigned long long)ns);
3094 ts.hwtstamp = ns_to_ktime(ns + lio->ptp_adjust);
3095 skb_tstamp_tx(skb, &ts);
3096 }
3097
3098 octeon_free_soft_command(oct, sc);
cabeb13b 3099 tx_buffer_free(skb);
f21fb3ed
RV		 3100}
3101
3102/* \brief Send a data packet that will be timestamped
3103 * @param oct octeon device
3104 * @param ndata pointer to network data
3105 * @param finfo pointer to private network data
3106 */
3107static inline int send_nic_timestamp_pkt(struct octeon_device *oct,
3108 struct octnic_data_pkt *ndata,
32581245 3109 struct octnet_buf_free_info *finfo)
f21fb3ed
RV		 3110{
3111 int retval;
3112 struct octeon_soft_command *sc;
f21fb3ed
RV		 3113 struct lio *lio;
3114 int ring_doorbell;
6a885b60 3115 u32 len;
f21fb3ed
RV		 3116
3117 lio = finfo->lio;
3118
3119 sc = octeon_alloc_soft_command_resp(oct, &ndata->cmd,
3120 sizeof(struct oct_timestamp_resp));
3121 finfo->sc = sc;
3122
3123 if (!sc) {
3124 dev_err(&oct->pci_dev->dev, "No memory for timestamped data packet\n");
3125 return IQ_SEND_FAILED;
3126 }
3127
3128 if (ndata->reqtype == REQTYPE_NORESP_NET)
3129 ndata->reqtype = REQTYPE_RESP_NET;
3130 else if (ndata->reqtype == REQTYPE_NORESP_NET_SG)
3131 ndata->reqtype = REQTYPE_RESP_NET_SG;
3132
3133 sc->callback = handle_timestamp;
3134 sc->callback_arg = finfo->skb;
3135 sc->iq_no = ndata->q_no;
3136
5b823514
RV		 3137 if (OCTEON_CN23XX_PF(oct))
3138 len = (u32)((struct octeon_instr_ih3 *)
3139 (&sc->cmd.cmd3.ih3))->dlengsz;
3140 else
3141 len = (u32)((struct octeon_instr_ih2 *)
3142 (&sc->cmd.cmd2.ih2))->dlengsz;
f21fb3ed 3143
32581245 3144 ring_doorbell = 1;
5b823514 3145
f21fb3ed 3146 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd,
6a885b60 3147 sc, len, ndata->reqtype);
f21fb3ed 3148
ddc173a6 3149 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 3150 dev_err(&oct->pci_dev->dev, "timestamp data packet failed status: %x\n",
3151 retval);
3152 octeon_free_soft_command(oct, sc);
3153 } else {
3154 netif_info(lio, tx_queued, lio->netdev, "Queued timestamp packet\n");
3155 }
3156
3157 return retval;
3158}
3159
f21fb3ed
RV		 3160/** \brief Transmit networks packets to the Octeon interface
3161 * @param skbuff skbuff struct to be passed to network layer.
3162 * @param netdev pointer to network device
3163 * @returns whether the packet was transmitted to the device okay or not
3164 * (NETDEV_TX_OK or NETDEV_TX_BUSY)
3165 */
3166static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev)
3167{
3168 struct lio *lio;
3169 struct octnet_buf_free_info *finfo;
3170 union octnic_cmd_setup cmdsetup;
3171 struct octnic_data_pkt ndata;
3172 struct octeon_device *oct;
3173 struct oct_iq_stats *stats;
6a885b60
RV		 3174 struct octeon_instr_irh *irh;
3175 union tx_info *tx_info;
26236fa9 3176 int status = 0;
f21fb3ed 3177 int q_idx = 0, iq_no = 0;
32581245 3178 int j;
fcd2b5e3 3179 u64 dptr = 0;
f21fb3ed
RV		 3180 u32 tag = 0;
3181
3182 lio = GET_LIO(netdev);
3183 oct = lio->oct_dev;
3184
3185 if (netif_is_multiqueue(netdev)) {
26236fa9
RV		 3186 q_idx = skb->queue_mapping;
3187 q_idx = (q_idx % (lio->linfo.num_txpciq));
3188 tag = q_idx;
3189 iq_no = lio->linfo.txpciq[q_idx].s.q_no;
f21fb3ed
RV		 3190 } else {
3191 iq_no = lio->txq;
3192 }
3193
3194 stats = &oct->instr_queue[iq_no]->stats;
3195
3196 /* Check for all conditions in which the current packet cannot be
3197 * transmitted.
3198 */
3199 if (!(atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) ||
0cece6c5 3200 (!lio->linfo.link.s.link_up) ||
f21fb3ed
RV		 3201 (skb->len <= 0)) {
3202 netif_info(lio, tx_err, lio->netdev,
3203 "Transmit failed link_status : %d\n",
0cece6c5 3204 lio->linfo.link.s.link_up);
f21fb3ed
RV		 3205 goto lio_xmit_failed;
3206 }
3207
3208 /* Use space in skb->cb to store info used to unmap and
3209 * free the buffers.
3210 */
3211 finfo = (struct octnet_buf_free_info *)skb->cb;
3212 finfo->lio = lio;
3213 finfo->skb = skb;
3214 finfo->sc = NULL;
3215
3216 /* Prepare the attributes for the data to be passed to OSI. */
3217 memset(&ndata, 0, sizeof(struct octnic_data_pkt));
3218
3219 ndata.buf = (void *)finfo;
3220
3221 ndata.q_no = iq_no;
3222
3223 if (netif_is_multiqueue(netdev)) {
3224 if (octnet_iq_is_full(oct, ndata.q_no)) {
3225 /* defer sending if queue is full */
3226 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
3227 ndata.q_no);
3228 stats->tx_iq_busy++;
3229 return NETDEV_TX_BUSY;
3230 }
3231 } else {
3232 if (octnet_iq_is_full(oct, lio->txq)) {
3233 /* defer sending if queue is full */
3234 stats->tx_iq_busy++;
3235 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
a2c64b67 3236 lio->txq);
f21fb3ed
RV		 3237 return NETDEV_TX_BUSY;
3238 }
3239 }
3240 /* pr_info(" XMIT - valid Qs: %d, 1st Q no: %d, cpu: %d, q_no:%d\n",
a2c64b67 3241 * lio->linfo.num_txpciq, lio->txq, cpu, ndata.q_no);
f21fb3ed
RV		 3242 */
3243
3244 ndata.datasize = skb->len;
3245
3246 cmdsetup.u64 = 0;
7275ebfc 3247 cmdsetup.s.iq_no = iq_no;
f21fb3ed 3248
01fb237a
RV		 3249 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3250 if (skb->encapsulation) {
3251 cmdsetup.s.tnl_csum = 1;
3252 stats->tx_vxlan++;
3253 } else {
3254 cmdsetup.s.transport_csum = 1;
3255 }
3256 }
f21fb3ed
RV		 3257 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
3258 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3259 cmdsetup.s.timestamp = 1;
3260 }
3261
3262 if (skb_shinfo(skb)->nr_frags == 0) {
3263 cmdsetup.s.u.datasize = skb->len;
0cece6c5 3264 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
a2c64b67 3265
f21fb3ed 3266 /* Offload checksum calculation for TCP/UDP packets */
6a885b60
RV		 3267 dptr = dma_map_single(&oct->pci_dev->dev,
3268 skb->data,
3269 skb->len,
3270 DMA_TO_DEVICE);
3271 if (dma_mapping_error(&oct->pci_dev->dev, dptr)) {
f21fb3ed
RV		 3272 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 1\n",
3273 __func__);
3274 return NETDEV_TX_BUSY;
3275 }
3276
5b823514
RV		 3277 if (OCTEON_CN23XX_PF(oct))
3278 ndata.cmd.cmd3.dptr = dptr;
3279 else
3280 ndata.cmd.cmd2.dptr = dptr;
6a885b60 3281 finfo->dptr = dptr;
f21fb3ed
RV		 3282 ndata.reqtype = REQTYPE_NORESP_NET;
3283
3284 } else {
3285 int i, frags;
3286 struct skb_frag_struct *frag;
3287 struct octnic_gather *g;
3288
fcd2b5e3
RV		 3289 spin_lock(&lio->glist_lock[q_idx]);
3290 g = (struct octnic_gather *)
3291 list_delete_head(&lio->glist[q_idx]);
3292 spin_unlock(&lio->glist_lock[q_idx]);
f21fb3ed
RV		 3293
3294 if (!g) {
3295 netif_info(lio, tx_err, lio->netdev,
3296 "Transmit scatter gather: glist null!\n");
3297 goto lio_xmit_failed;
3298 }
3299
3300 cmdsetup.s.gather = 1;
3301 cmdsetup.s.u.gatherptrs = (skb_shinfo(skb)->nr_frags + 1);
0cece6c5 3302 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
f21fb3ed
RV		 3303
3304 memset(g->sg, 0, g->sg_size);
3305
3306 g->sg[0].ptr[0] = dma_map_single(&oct->pci_dev->dev,
3307 skb->data,
3308 (skb->len - skb->data_len),
3309 DMA_TO_DEVICE);
3310 if (dma_mapping_error(&oct->pci_dev->dev, g->sg[0].ptr[0])) {
3311 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 2\n",
3312 __func__);
3313 return NETDEV_TX_BUSY;
3314 }
3315 add_sg_size(&g->sg[0], (skb->len - skb->data_len), 0);
3316
3317 frags = skb_shinfo(skb)->nr_frags;
3318 i = 1;
3319 while (frags--) {
3320 frag = &skb_shinfo(skb)->frags[i - 1];
3321
3322 g->sg[(i >> 2)].ptr[(i & 3)] =
3323 dma_map_page(&oct->pci_dev->dev,
3324 frag->page.p,
3325 frag->page_offset,
3326 frag->size,
3327 DMA_TO_DEVICE);
3328
fcd2b5e3
RV		 3329 if (dma_mapping_error(&oct->pci_dev->dev,
3330 g->sg[i >> 2].ptr[i & 3])) {
3331 dma_unmap_single(&oct->pci_dev->dev,
3332 g->sg[0].ptr[0],
3333 skb->len - skb->data_len,
3334 DMA_TO_DEVICE);
3335 for (j = 1; j < i; j++) {
3336 frag = &skb_shinfo(skb)->frags[j - 1];
3337 dma_unmap_page(&oct->pci_dev->dev,
3338 g->sg[j >> 2].ptr[j & 3],
3339 frag->size,
3340 DMA_TO_DEVICE);
3341 }
3342 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 3\n",
3343 __func__);
3344 return NETDEV_TX_BUSY;
3345 }
3346
f21fb3ed
RV		 3347 add_sg_size(&g->sg[(i >> 2)], frag->size, (i & 3));
3348 i++;
3349 }
3350
fcd2b5e3 3351 dptr = g->sg_dma_ptr;
f21fb3ed 3352
5b823514
RV		 3353 if (OCTEON_CN23XX_PF(oct))
3354 ndata.cmd.cmd3.dptr = dptr;
3355 else
3356 ndata.cmd.cmd2.dptr = dptr;
6a885b60 3357 finfo->dptr = dptr;
f21fb3ed
RV		 3358 finfo->g = g;
3359
3360 ndata.reqtype = REQTYPE_NORESP_NET_SG;
3361 }
3362
5b823514
RV		 3363 if (OCTEON_CN23XX_PF(oct)) {
3364 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd3.irh;
3365 tx_info = (union tx_info *)&ndata.cmd.cmd3.ossp[0];
3366 } else {
3367 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd2.irh;
3368 tx_info = (union tx_info *)&ndata.cmd.cmd2.ossp[0];
3369 }
f21fb3ed 3370
6a885b60 3371 if (skb_shinfo(skb)->gso_size) {
f21fb3ed
RV		 3372 tx_info->s.gso_size = skb_shinfo(skb)->gso_size;
3373 tx_info->s.gso_segs = skb_shinfo(skb)->gso_segs;
1f164717 3374 stats->tx_gso++;
f21fb3ed 3375 }
1f164717 3376
0da0b77c
RV		 3377 /* HW insert VLAN tag */
3378 if (skb_vlan_tag_present(skb)) {
3379 irh->priority = skb_vlan_tag_get(skb) >> 13;
3380 irh->vlan = skb_vlan_tag_get(skb) & 0xfff;
3381 }
f21fb3ed 3382
f21fb3ed 3383 if (unlikely(cmdsetup.s.timestamp))
32581245 3384 status = send_nic_timestamp_pkt(oct, &ndata, finfo);
f21fb3ed 3385 else
32581245 3386 status = octnet_send_nic_data_pkt(oct, &ndata);
f21fb3ed
RV		 3387 if (status == IQ_SEND_FAILED)
3388 goto lio_xmit_failed;
3389
3390 netif_info(lio, tx_queued, lio->netdev, "Transmit queued successfully\n");
3391
3392 if (status == IQ_SEND_STOP)
3393 stop_q(lio->netdev, q_idx);
3394
860e9538 3395 netif_trans_update(netdev);
f21fb3ed 3396
80c8eae6
SB		 3397 if (tx_info->s.gso_segs)
3398 stats->tx_done += tx_info->s.gso_segs;
1f164717
RV		 3399 else
3400 stats->tx_done++;
80c8eae6 3401 stats->tx_tot_bytes += ndata.datasize;
f21fb3ed
RV		 3402
3403 return NETDEV_TX_OK;
3404
3405lio_xmit_failed:
3406 stats->tx_dropped++;
3407 netif_info(lio, tx_err, lio->netdev, "IQ%d Transmit dropped:%llu\n",
3408 iq_no, stats->tx_dropped);
6a885b60
RV		 3409 if (dptr)
3410 dma_unmap_single(&oct->pci_dev->dev, dptr,
3411 ndata.datasize, DMA_TO_DEVICE);
cabeb13b 3412 tx_buffer_free(skb);
f21fb3ed
RV		 3413 return NETDEV_TX_OK;
3414}
3415
3416/** \brief Network device Tx timeout
3417 * @param netdev pointer to network device
3418 */
3419static void liquidio_tx_timeout(struct net_device *netdev)
3420{
3421 struct lio *lio;
3422
3423 lio = GET_LIO(netdev);
3424
3425 netif_info(lio, tx_err, lio->netdev,
3426 "Transmit timeout tx_dropped:%ld, waking up queues now!!\n",
3427 netdev->stats.tx_dropped);
860e9538 3428 netif_trans_update(netdev);
f21fb3ed
RV		 3429 txqs_wake(netdev);
3430}
3431
63245f25
RV		 3432static int liquidio_vlan_rx_add_vid(struct net_device *netdev,
3433 __be16 proto __attribute__((unused)),
3434 u16 vid)
3435{
3436 struct lio *lio = GET_LIO(netdev);
3437 struct octeon_device *oct = lio->oct_dev;
3438 struct octnic_ctrl_pkt nctrl;
3439 int ret = 0;
3440
3441 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3442
3443 nctrl.ncmd.u64 = 0;
3444 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER;
3445 nctrl.ncmd.s.param1 = vid;
3446 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3447 nctrl.wait_time = 100;
3448 nctrl.netpndev = (u64)netdev;
3449 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3450
3451 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3452 if (ret < 0) {
3453 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
3454 ret);
3455 }
3456
3457 return ret;
3458}
3459
3460static int liquidio_vlan_rx_kill_vid(struct net_device *netdev,
3461 __be16 proto __attribute__((unused)),
3462 u16 vid)
3463{
3464 struct lio *lio = GET_LIO(netdev);
3465 struct octeon_device *oct = lio->oct_dev;
3466 struct octnic_ctrl_pkt nctrl;
3467 int ret = 0;
3468
3469 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3470
3471 nctrl.ncmd.u64 = 0;
3472 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER;
3473 nctrl.ncmd.s.param1 = vid;
3474 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3475 nctrl.wait_time = 100;
3476 nctrl.netpndev = (u64)netdev;
3477 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3478
3479 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3480 if (ret < 0) {
3481 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
3482 ret);
3483 }
3484 return ret;
3485}
3486
01fb237a
RV		 3487/** Sending command to enable/disable RX checksum offload
3488 * @param netdev pointer to network device
3489 * @param command OCTNET_CMD_TNL_RX_CSUM_CTL
3490 * @param rx_cmd_bit OCTNET_CMD_RXCSUM_ENABLE/
3491 * OCTNET_CMD_RXCSUM_DISABLE
3492 * @returns SUCCESS or FAILURE
3493 */
c41419b0
NMG		 3494static int liquidio_set_rxcsum_command(struct net_device *netdev, int command,
3495 u8 rx_cmd)
01fb237a
RV		 3496{
3497 struct lio *lio = GET_LIO(netdev);
3498 struct octeon_device *oct = lio->oct_dev;
3499 struct octnic_ctrl_pkt nctrl;
3500 int ret = 0;
3501
3502 nctrl.ncmd.u64 = 0;
3503 nctrl.ncmd.s.cmd = command;
3504 nctrl.ncmd.s.param1 = rx_cmd;
3505 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3506 nctrl.wait_time = 100;
3507 nctrl.netpndev = (u64)netdev;
3508 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3509
3510 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3511 if (ret < 0) {
3512 dev_err(&oct->pci_dev->dev,
3513 "DEVFLAGS RXCSUM change failed in core(ret:0x%x)\n",
3514 ret);
3515 }
3516 return ret;
3517}
3518
3519/** Sending command to add/delete VxLAN UDP port to firmware
3520 * @param netdev pointer to network device
3521 * @param command OCTNET_CMD_VXLAN_PORT_CONFIG
3522 * @param vxlan_port VxLAN port to be added or deleted
3523 * @param vxlan_cmd_bit OCTNET_CMD_VXLAN_PORT_ADD,
3524 * OCTNET_CMD_VXLAN_PORT_DEL
3525 * @returns SUCCESS or FAILURE
3526 */
3527static int liquidio_vxlan_port_command(struct net_device *netdev, int command,
3528 u16 vxlan_port, u8 vxlan_cmd_bit)
3529{
3530 struct lio *lio = GET_LIO(netdev);
3531 struct octeon_device *oct = lio->oct_dev;
3532 struct octnic_ctrl_pkt nctrl;
3533 int ret = 0;
3534
3535 nctrl.ncmd.u64 = 0;
3536 nctrl.ncmd.s.cmd = command;
3537 nctrl.ncmd.s.more = vxlan_cmd_bit;
3538 nctrl.ncmd.s.param1 = vxlan_port;
3539 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3540 nctrl.wait_time = 100;
3541 nctrl.netpndev = (u64)netdev;
3542 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3543
3544 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3545 if (ret < 0) {
3546 dev_err(&oct->pci_dev->dev,
3547 "VxLAN port add/delete failed in core (ret:0x%x)\n",
3548 ret);
3549 }
3550 return ret;
3551}
3552
f21fb3ed
RV		 3553/** \brief Net device fix features
3554 * @param netdev pointer to network device
3555 * @param request features requested
3556 * @returns updated features list
3557 */
3558static netdev_features_t liquidio_fix_features(struct net_device *netdev,
3559 netdev_features_t request)
3560{
3561 struct lio *lio = netdev_priv(netdev);
3562
3563 if ((request & NETIF_F_RXCSUM) &&
3564 !(lio->dev_capability & NETIF_F_RXCSUM))
3565 request &= ~NETIF_F_RXCSUM;
3566
3567 if ((request & NETIF_F_HW_CSUM) &&
3568 !(lio->dev_capability & NETIF_F_HW_CSUM))
3569 request &= ~NETIF_F_HW_CSUM;
3570
3571 if ((request & NETIF_F_TSO) && !(lio->dev_capability & NETIF_F_TSO))
3572 request &= ~NETIF_F_TSO;
3573
3574 if ((request & NETIF_F_TSO6) && !(lio->dev_capability & NETIF_F_TSO6))
3575 request &= ~NETIF_F_TSO6;
3576
3577 if ((request & NETIF_F_LRO) && !(lio->dev_capability & NETIF_F_LRO))
3578 request &= ~NETIF_F_LRO;
3579
3580 /*Disable LRO if RXCSUM is off */
3581 if (!(request & NETIF_F_RXCSUM) && (netdev->features & NETIF_F_LRO) &&
3582 (lio->dev_capability & NETIF_F_LRO))
3583 request &= ~NETIF_F_LRO;
3584
3585 return request;
3586}
3587
3588/** \brief Net device set features
3589 * @param netdev pointer to network device
3590 * @param features features to enable/disable
3591 */
3592static int liquidio_set_features(struct net_device *netdev,
3593 netdev_features_t features)
3594{
3595 struct lio *lio = netdev_priv(netdev);
3596
3597 if (!((netdev->features ^ features) & NETIF_F_LRO))
3598 return 0;
3599
3600 if ((features & NETIF_F_LRO) && (lio->dev_capability & NETIF_F_LRO))
0cece6c5
RV		 3601 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
3602 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed
RV		 3603 else if (!(features & NETIF_F_LRO) &&
3604 (lio->dev_capability & NETIF_F_LRO))
0cece6c5
RV		 3605 liquidio_set_feature(netdev, OCTNET_CMD_LRO_DISABLE,
3606 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed 3607
01fb237a
RV		 3608 /* Sending command to firmware to enable/disable RX checksum
3609 * offload settings using ethtool
3610 */
3611 if (!(netdev->features & NETIF_F_RXCSUM) &&
3612 (lio->enc_dev_capability & NETIF_F_RXCSUM) &&
3613 (features & NETIF_F_RXCSUM))
3614 liquidio_set_rxcsum_command(netdev,
3615 OCTNET_CMD_TNL_RX_CSUM_CTL,
3616 OCTNET_CMD_RXCSUM_ENABLE);
3617 else if ((netdev->features & NETIF_F_RXCSUM) &&
3618 (lio->enc_dev_capability & NETIF_F_RXCSUM) &&
3619 !(features & NETIF_F_RXCSUM))
3620 liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL,
3621 OCTNET_CMD_RXCSUM_DISABLE);
3622
f21fb3ed
RV		 3623 return 0;
3624}
3625
01fb237a
RV		 3626static void liquidio_add_vxlan_port(struct net_device *netdev,
3627 struct udp_tunnel_info *ti)
3628{
3629 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3630 return;
3631
3632 liquidio_vxlan_port_command(netdev,
3633 OCTNET_CMD_VXLAN_PORT_CONFIG,
3634 htons(ti->port),
3635 OCTNET_CMD_VXLAN_PORT_ADD);
3636}
3637
3638static void liquidio_del_vxlan_port(struct net_device *netdev,
3639 struct udp_tunnel_info *ti)
3640{
3641 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3642 return;
3643
3644 liquidio_vxlan_port_command(netdev,
3645 OCTNET_CMD_VXLAN_PORT_CONFIG,
3646 htons(ti->port),
3647 OCTNET_CMD_VXLAN_PORT_DEL);
3648}
3649
86dea55b
RV		 3650static int __liquidio_set_vf_mac(struct net_device *netdev, int vfidx,
3651 u8 *mac, bool is_admin_assigned)
3652{
3653 struct lio *lio = GET_LIO(netdev);
3654 struct octeon_device *oct = lio->oct_dev;
3655 struct octnic_ctrl_pkt nctrl;
3656
3657 if (!is_valid_ether_addr(mac))
3658 return -EINVAL;
3659
3660 if (vfidx < 0 || vfidx >= oct->sriov_info.max_vfs)
3661 return -EINVAL;
3662
3663 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3664
3665 nctrl.ncmd.u64 = 0;
3666 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
3667 /* vfidx is 0 based, but vf_num (param1) is 1 based */
3668 nctrl.ncmd.s.param1 = vfidx + 1;
3669 nctrl.ncmd.s.param2 = (is_admin_assigned ? 1 : 0);
3670 nctrl.ncmd.s.more = 1;
3671 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
9549c6c8
RF		 3672 nctrl.netpndev = (u64)netdev;
3673 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
86dea55b
RV		 3674 nctrl.wait_time = LIO_CMD_WAIT_TM;
3675
3676 nctrl.udd[0] = 0;
3677 /* The MAC Address is presented in network byte order. */
3678 ether_addr_copy((u8 *)&nctrl.udd[0] + 2, mac);
3679
3680 oct->sriov_info.vf_macaddr[vfidx] = nctrl.udd[0];
3681
3682 octnet_send_nic_ctrl_pkt(oct, &nctrl);
3683
3684 return 0;
3685}
3686
3687static int liquidio_set_vf_mac(struct net_device *netdev, int vfidx, u8 *mac)
3688{
3689 struct lio *lio = GET_LIO(netdev);
3690 struct octeon_device *oct = lio->oct_dev;
3691 int retval;
3692
3693 retval = __liquidio_set_vf_mac(netdev, vfidx, mac, true);
3694 if (!retval)
3695 cn23xx_tell_vf_its_macaddr_changed(oct, vfidx, mac);
3696
3697 return retval;
3698}
3699
3700static int liquidio_set_vf_vlan(struct net_device *netdev, int vfidx,
3701 u16 vlan, u8 qos, __be16 vlan_proto)
3702{
3703 struct lio *lio = GET_LIO(netdev);
3704 struct octeon_device *oct = lio->oct_dev;
3705 struct octnic_ctrl_pkt nctrl;
3706 u16 vlantci;
3707
3708 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
3709 return -EINVAL;
3710
3711 if (vlan_proto != htons(ETH_P_8021Q))
3712 return -EPROTONOSUPPORT;
3713
3714 if (vlan >= VLAN_N_VID || qos > 7)
3715 return -EINVAL;
3716
3717 if (vlan)
3718 vlantci = vlan | (u16)qos << VLAN_PRIO_SHIFT;
3719 else
3720 vlantci = 0;
3721
3722 if (oct->sriov_info.vf_vlantci[vfidx] == vlantci)
3723 return 0;
3724
3725 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3726
3727 if (vlan)
3728 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER;
3729 else
3730 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER;
3731
3732 nctrl.ncmd.s.param1 = vlantci;
3733 nctrl.ncmd.s.param2 =
3734 vfidx + 1; /* vfidx is 0 based, but vf_num (param2) is 1 based */
3735 nctrl.ncmd.s.more = 0;
3736 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3737 nctrl.cb_fn = 0;
3738 nctrl.wait_time = LIO_CMD_WAIT_TM;
3739
3740 octnet_send_nic_ctrl_pkt(oct, &nctrl);
3741
3742 oct->sriov_info.vf_vlantci[vfidx] = vlantci;
3743
3744 return 0;
3745}
3746
3747static int liquidio_get_vf_config(struct net_device *netdev, int vfidx,
3748 struct ifla_vf_info *ivi)
3749{
3750 struct lio *lio = GET_LIO(netdev);
3751 struct octeon_device *oct = lio->oct_dev;
3752 u8 *macaddr;
3753
3754 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
3755 return -EINVAL;
3756
3757 ivi->vf = vfidx;
3758 macaddr = 2 + (u8 *)&oct->sriov_info.vf_macaddr[vfidx];
3759 ether_addr_copy(&ivi->mac[0], macaddr);
3760 ivi->vlan = oct->sriov_info.vf_vlantci[vfidx] & VLAN_VID_MASK;
3761 ivi->qos = oct->sriov_info.vf_vlantci[vfidx] >> VLAN_PRIO_SHIFT;
3762 ivi->linkstate = oct->sriov_info.vf_linkstate[vfidx];
3763 return 0;
3764}
3765
3766static int liquidio_set_vf_link_state(struct net_device *netdev, int vfidx,
3767 int linkstate)
3768{
3769 struct lio *lio = GET_LIO(netdev);
3770 struct octeon_device *oct = lio->oct_dev;
3771 struct octnic_ctrl_pkt nctrl;
3772
3773 if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
3774 return -EINVAL;
3775
3776 if (oct->sriov_info.vf_linkstate[vfidx] == linkstate)
3777 return 0;
3778
3779 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3780 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_VF_LINKSTATE;
3781 nctrl.ncmd.s.param1 =
3782 vfidx + 1; /* vfidx is 0 based, but vf_num (param1) is 1 based */
3783 nctrl.ncmd.s.param2 = linkstate;
3784 nctrl.ncmd.s.more = 0;
3785 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3786 nctrl.cb_fn = 0;
3787 nctrl.wait_time = LIO_CMD_WAIT_TM;
3788
3789 octnet_send_nic_ctrl_pkt(oct, &nctrl);
3790
3791 oct->sriov_info.vf_linkstate[vfidx] = linkstate;
3792
3793 return 0;
3794}
3795
97a25326 3796static const struct net_device_ops lionetdevops = {
f21fb3ed
RV		 3797 .ndo_open = liquidio_open,
3798 .ndo_stop = liquidio_stop,
3799 .ndo_start_xmit = liquidio_xmit,
3800 .ndo_get_stats = liquidio_get_stats,
3801 .ndo_set_mac_address = liquidio_set_mac,
3802 .ndo_set_rx_mode = liquidio_set_mcast_list,
3803 .ndo_tx_timeout = liquidio_tx_timeout,
63245f25
RV		 3804
3805 .ndo_vlan_rx_add_vid = liquidio_vlan_rx_add_vid,
3806 .ndo_vlan_rx_kill_vid = liquidio_vlan_rx_kill_vid,
f21fb3ed
RV		 3807 .ndo_change_mtu = liquidio_change_mtu,
3808 .ndo_do_ioctl = liquidio_ioctl,
3809 .ndo_fix_features = liquidio_fix_features,
3810 .ndo_set_features = liquidio_set_features,
01fb237a
RV		 3811 .ndo_udp_tunnel_add = liquidio_add_vxlan_port,
3812 .ndo_udp_tunnel_del = liquidio_del_vxlan_port,
86dea55b
RV		 3813 .ndo_set_vf_mac = liquidio_set_vf_mac,
3814 .ndo_set_vf_vlan = liquidio_set_vf_vlan,
3815 .ndo_get_vf_config = liquidio_get_vf_config,
3816 .ndo_set_vf_link_state = liquidio_set_vf_link_state,
f21fb3ed
RV		 3817};
3818
3819/** \brief Entry point for the liquidio module
3820 */
3821static int __init liquidio_init(void)
3822{
3823 int i;
3824 struct handshake *hs;
3825
3826 init_completion(&first_stage);
3827
97a25326 3828 octeon_init_device_list(OCTEON_CONFIG_TYPE_DEFAULT);
f21fb3ed
RV		 3829
3830 if (liquidio_init_pci())
3831 return -EINVAL;
3832
3833 wait_for_completion_timeout(&first_stage, msecs_to_jiffies(1000));
3834
3835 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3836 hs = &handshake[i];
3837 if (hs->pci_dev) {
3838 wait_for_completion(&hs->init);
3839 if (!hs->init_ok) {
3840 /* init handshake failed */
3841 dev_err(&hs->pci_dev->dev,
3842 "Failed to init device\n");
3843 liquidio_deinit_pci();
3844 return -EIO;
3845 }
3846 }
3847 }
3848
3849 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3850 hs = &handshake[i];
3851 if (hs->pci_dev) {
3852 wait_for_completion_timeout(&hs->started,
3853 msecs_to_jiffies(30000));
3854 if (!hs->started_ok) {
3855 /* starter handshake failed */
3856 dev_err(&hs->pci_dev->dev,
3857 "Firmware failed to start\n");
3858 liquidio_deinit_pci();
3859 return -EIO;
3860 }
3861 }
3862 }
3863
3864 return 0;
3865}
3866
5b173cf9 3867static int lio_nic_info(struct octeon_recv_info *recv_info, void *buf)
f21fb3ed
RV		 3868{
3869 struct octeon_device *oct = (struct octeon_device *)buf;
3870 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
0cece6c5 3871 int gmxport = 0;
f21fb3ed
RV		 3872 union oct_link_status *ls;
3873 int i;
3874
0cece6c5 3875 if (recv_pkt->buffer_size[0] != sizeof(*ls)) {
f21fb3ed
RV		 3876 dev_err(&oct->pci_dev->dev, "Malformed NIC_INFO, len=%d, ifidx=%d\n",
3877 recv_pkt->buffer_size[0],
0cece6c5 3878 recv_pkt->rh.r_nic_info.gmxport);
f21fb3ed
RV		 3879 goto nic_info_err;
3880 }
3881
0cece6c5 3882 gmxport = recv_pkt->rh.r_nic_info.gmxport;
f21fb3ed
RV		 3883 ls = (union oct_link_status *)get_rbd(recv_pkt->buffer_ptr[0]);
3884
3885 octeon_swap_8B_data((u64 *)ls, (sizeof(union oct_link_status)) >> 3);
0cece6c5
RV		 3886 for (i = 0; i < oct->ifcount; i++) {
3887 if (oct->props[i].gmxport == gmxport) {
3888 update_link_status(oct->props[i].netdev, ls);
3889 break;
3890 }
3891 }
f21fb3ed
RV		 3892
3893nic_info_err:
3894 for (i = 0; i < recv_pkt->buffer_count; i++)
3895 recv_buffer_free(recv_pkt->buffer_ptr[i]);
3896 octeon_free_recv_info(recv_info);
3897 return 0;
3898}
3899
3900/**
3901 * \brief Setup network interfaces
3902 * @param octeon_dev octeon device
3903 *
3904 * Called during init time for each device. It assumes the NIC
3905 * is already up and running. The link information for each
3906 * interface is passed in link_info.
3907 */
3908static int setup_nic_devices(struct octeon_device *octeon_dev)
3909{
3910 struct lio *lio = NULL;
3911 struct net_device *netdev;
3912 u8 mac[6], i, j;
3913 struct octeon_soft_command *sc;
3914 struct liquidio_if_cfg_context *ctx;
3915 struct liquidio_if_cfg_resp *resp;
3916 struct octdev_props *props;
26236fa9 3917 int retval, num_iqueues, num_oqueues;
f21fb3ed
RV		 3918 union oct_nic_if_cfg if_cfg;
3919 unsigned int base_queue;
3920 unsigned int gmx_port_id;
83101ce3 3921 u32 resp_size, ctx_size, data_size;
0cece6c5 3922 u32 ifidx_or_pfnum;
83101ce3 3923 struct lio_version *vdata;
f21fb3ed
RV		 3924
3925 /* This is to handle link status changes */
3926 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3927 OPCODE_NIC_INFO,
3928 lio_nic_info, octeon_dev);
3929
3930 /* REQTYPE_RESP_NET and REQTYPE_SOFT_COMMAND do not have free functions.
3931 * They are handled directly.
3932 */
3933 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET,
3934 free_netbuf);
3935
3936 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET_SG,
3937 free_netsgbuf);
3938
3939 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_RESP_NET_SG,
3940 free_netsgbuf_with_resp);
3941
3942 for (i = 0; i < octeon_dev->ifcount; i++) {
3943 resp_size = sizeof(struct liquidio_if_cfg_resp);
3944 ctx_size = sizeof(struct liquidio_if_cfg_context);
83101ce3 3945 data_size = sizeof(struct lio_version);
f21fb3ed 3946 sc = (struct octeon_soft_command *)
83101ce3 3947 octeon_alloc_soft_command(octeon_dev, data_size,
f21fb3ed
RV		 3948 resp_size, ctx_size);
3949 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
3950 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
83101ce3
RV		 3951 vdata = (struct lio_version *)sc->virtdptr;
3952
3953 *((u64 *)vdata) = 0;
3954 vdata->major = cpu_to_be16(LIQUIDIO_BASE_MAJOR_VERSION);
3955 vdata->minor = cpu_to_be16(LIQUIDIO_BASE_MINOR_VERSION);
3956 vdata->micro = cpu_to_be16(LIQUIDIO_BASE_MICRO_VERSION);
f21fb3ed 3957
e86b1ab6
RV		 3958 if (OCTEON_CN23XX_PF(octeon_dev)) {
3959 num_iqueues = octeon_dev->sriov_info.num_pf_rings;
3960 num_oqueues = octeon_dev->sriov_info.num_pf_rings;
3961 base_queue = octeon_dev->sriov_info.pf_srn;
3962
3963 gmx_port_id = octeon_dev->pf_num;
3964 ifidx_or_pfnum = octeon_dev->pf_num;
3965 } else {
3966 num_iqueues = CFG_GET_NUM_TXQS_NIC_IF(
3967 octeon_get_conf(octeon_dev), i);
3968 num_oqueues = CFG_GET_NUM_RXQS_NIC_IF(
3969 octeon_get_conf(octeon_dev), i);
3970 base_queue = CFG_GET_BASE_QUE_NIC_IF(
3971 octeon_get_conf(octeon_dev), i);
3972 gmx_port_id = CFG_GET_GMXID_NIC_IF(
3973 octeon_get_conf(octeon_dev), i);
3974 ifidx_or_pfnum = i;
3975 }
3dcef2ca 3976
f21fb3ed
RV		 3977 dev_dbg(&octeon_dev->pci_dev->dev,
3978 "requesting config for interface %d, iqs %d, oqs %d\n",
0cece6c5 3979 ifidx_or_pfnum, num_iqueues, num_oqueues);
a7d5a3dc 3980 WRITE_ONCE(ctx->cond, 0);
f21fb3ed
RV		 3981 ctx->octeon_id = lio_get_device_id(octeon_dev);
3982 init_waitqueue_head(&ctx->wc);
3983
3984 if_cfg.u64 = 0;
3985 if_cfg.s.num_iqueues = num_iqueues;
3986 if_cfg.s.num_oqueues = num_oqueues;
3987 if_cfg.s.base_queue = base_queue;
3988 if_cfg.s.gmx_port_id = gmx_port_id;
0cece6c5
RV		 3989
3990 sc->iq_no = 0;
3991
f21fb3ed 3992 octeon_prepare_soft_command(octeon_dev, sc, OPCODE_NIC,
0cece6c5 3993 OPCODE_NIC_IF_CFG, 0,
f21fb3ed
RV		 3994 if_cfg.u64, 0);
3995
3996 sc->callback = if_cfg_callback;
3997 sc->callback_arg = sc;
55893a63 3998 sc->wait_time = 3000;
f21fb3ed
RV		 3999
4000 retval = octeon_send_soft_command(octeon_dev, sc);
ddc173a6 4001 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 4002 dev_err(&octeon_dev->pci_dev->dev,
4003 "iq/oq config failed status: %x\n",
4004 retval);
4005 /* Soft instr is freed by driver in case of failure. */
4006 goto setup_nic_dev_fail;
4007 }
4008
4009 /* Sleep on a wait queue till the cond flag indicates that the
4010 * response arrived or timed-out.
4011 */
afdf841f
RV		 4012 if (sleep_cond(&ctx->wc, &ctx->cond) == -EINTR) {
4013 dev_err(&octeon_dev->pci_dev->dev, "Wait interrupted\n");
4014 goto setup_nic_wait_intr;
4015 }
4016
f21fb3ed
RV		 4017 retval = resp->status;
4018 if (retval) {
4019 dev_err(&octeon_dev->pci_dev->dev, "iq/oq config failed\n");
4020 goto setup_nic_dev_fail;
4021 }
4022
4023 octeon_swap_8B_data((u64 *)(&resp->cfg_info),
4024 (sizeof(struct liquidio_if_cfg_info)) >> 3);
4025
4026 num_iqueues = hweight64(resp->cfg_info.iqmask);
4027 num_oqueues = hweight64(resp->cfg_info.oqmask);
4028
4029 if (!(num_iqueues) || !(num_oqueues)) {
4030 dev_err(&octeon_dev->pci_dev->dev,
4031 "Got bad iqueues (%016llx) or oqueues (%016llx) from firmware.\n",
4032 resp->cfg_info.iqmask,
4033 resp->cfg_info.oqmask);
4034 goto setup_nic_dev_fail;
4035 }
4036 dev_dbg(&octeon_dev->pci_dev->dev,
4037 "interface %d, iqmask %016llx, oqmask %016llx, numiqueues %d, numoqueues %d\n",
4038 i, resp->cfg_info.iqmask, resp->cfg_info.oqmask,
4039 num_iqueues, num_oqueues);
4040 netdev = alloc_etherdev_mq(LIO_SIZE, num_iqueues);
4041
4042 if (!netdev) {
4043 dev_err(&octeon_dev->pci_dev->dev, "Device allocation failed\n");
4044 goto setup_nic_dev_fail;
4045 }
4046
0cece6c5 4047 SET_NETDEV_DEV(netdev, &octeon_dev->pci_dev->dev);
f21fb3ed 4048
f21fb3ed
RV		 4049 /* Associate the routines that will handle different
4050 * netdev tasks.
4051 */
4052 netdev->netdev_ops = &lionetdevops;
4053
4054 lio = GET_LIO(netdev);
4055
4056 memset(lio, 0, sizeof(struct lio));
4057
0cece6c5
RV		 4058 lio->ifidx = ifidx_or_pfnum;
4059
4060 props = &octeon_dev->props[i];
4061 props->gmxport = resp->cfg_info.linfo.gmxport;
4062 props->netdev = netdev;
f21fb3ed
RV		 4063
4064 lio->linfo.num_rxpciq = num_oqueues;
4065 lio->linfo.num_txpciq = num_iqueues;
f21fb3ed 4066 for (j = 0; j < num_oqueues; j++) {
26236fa9
RV		 4067 lio->linfo.rxpciq[j].u64 =
4068 resp->cfg_info.linfo.rxpciq[j].u64;
f21fb3ed 4069 }
f21fb3ed 4070 for (j = 0; j < num_iqueues; j++) {
26236fa9
RV		 4071 lio->linfo.txpciq[j].u64 =
4072 resp->cfg_info.linfo.txpciq[j].u64;
f21fb3ed
RV		 4073 }
4074 lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr;
4075 lio->linfo.gmxport = resp->cfg_info.linfo.gmxport;
4076 lio->linfo.link.u64 = resp->cfg_info.linfo.link.u64;
4077
4078 lio->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
4079
e86b1ab6
RV		 4080 if (OCTEON_CN23XX_PF(octeon_dev) ||
4081 OCTEON_CN6XXX(octeon_dev)) {
4082 lio->dev_capability = NETIF_F_HIGHDMA
4083 | NETIF_F_IP_CSUM
4084 | NETIF_F_IPV6_CSUM
4085 | NETIF_F_SG | NETIF_F_RXCSUM
4086 | NETIF_F_GRO
4087 | NETIF_F_TSO | NETIF_F_TSO6
4088 | NETIF_F_LRO;
4089 }
f21fb3ed
RV		 4090 netif_set_gso_max_size(netdev, OCTNIC_GSO_MAX_SIZE);
4091
01fb237a
RV		 4092 /* Copy of transmit encapsulation capabilities:
4093 * TSO, TSO6, Checksums for this device
4094 */
4095 lio->enc_dev_capability = NETIF_F_IP_CSUM
4096 | NETIF_F_IPV6_CSUM
4097 | NETIF_F_GSO_UDP_TUNNEL
4098 | NETIF_F_HW_CSUM | NETIF_F_SG
4099 | NETIF_F_RXCSUM
4100 | NETIF_F_TSO | NETIF_F_TSO6
4101 | NETIF_F_LRO;
4102
4103 netdev->hw_enc_features = (lio->enc_dev_capability &
4104 ~NETIF_F_LRO);
4105
4106 lio->dev_capability |= NETIF_F_GSO_UDP_TUNNEL;
4107
f21fb3ed 4108 netdev->vlan_features = lio->dev_capability;
0da0b77c 4109 /* Add any unchangeable hw features */
63245f25
RV		 4110 lio->dev_capability |= NETIF_F_HW_VLAN_CTAG_FILTER |
4111 NETIF_F_HW_VLAN_CTAG_RX |
0da0b77c
RV		 4112 NETIF_F_HW_VLAN_CTAG_TX;
4113
4114 netdev->features = (lio->dev_capability & ~NETIF_F_LRO);
f21fb3ed
RV		 4115
4116 netdev->hw_features = lio->dev_capability;
0da0b77c
RV		 4117 /*HW_VLAN_RX and HW_VLAN_FILTER is always on*/
4118 netdev->hw_features = netdev->hw_features &
4119 ~NETIF_F_HW_VLAN_CTAG_RX;
f21fb3ed 4120
109cc165
JW		 4121 /* MTU range: 68 - 16000 */
4122 netdev->min_mtu = LIO_MIN_MTU_SIZE;
4123 netdev->max_mtu = LIO_MAX_MTU_SIZE;
4124
f21fb3ed
RV		 4125 /* Point to the properties for octeon device to which this
4126 * interface belongs.
4127 */
4128 lio->oct_dev = octeon_dev;
4129 lio->octprops = props;
4130 lio->netdev = netdev;
f21fb3ed
RV		 4131
4132 dev_dbg(&octeon_dev->pci_dev->dev,
4133 "if%d gmx: %d hw_addr: 0x%llx\n", i,
4134 lio->linfo.gmxport, CVM_CAST64(lio->linfo.hw_addr));
4135
86dea55b
RV		 4136 for (j = 0; j < octeon_dev->sriov_info.max_vfs; j++) {
4137 u8 vfmac[ETH_ALEN];
4138
4139 random_ether_addr(&vfmac[0]);
4140 if (__liquidio_set_vf_mac(netdev, j,
4141 &vfmac[0], false)) {
4142 dev_err(&octeon_dev->pci_dev->dev,
4143 "Error setting VF%d MAC address\n",
4144 j);
4145 goto setup_nic_dev_fail;
4146 }
4147 }
4148
f21fb3ed
RV		 4149 /* 64-bit swap required on LE machines */
4150 octeon_swap_8B_data(&lio->linfo.hw_addr, 1);
4151 for (j = 0; j < 6; j++)
4152 mac[j] = *((u8 *)(((u8 *)&lio->linfo.hw_addr) + 2 + j));
4153
4154 /* Copy MAC Address to OS network device structure */
4155
4156 ether_addr_copy(netdev->dev_addr, mac);
4157
26236fa9
RV		 4158 /* By default all interfaces on a single Octeon uses the same
4159 * tx and rx queues
4160 */
4161 lio->txq = lio->linfo.txpciq[0].s.q_no;
4162 lio->rxq = lio->linfo.rxpciq[0].s.q_no;
0cece6c5 4163 if (setup_io_queues(octeon_dev, i)) {
f21fb3ed
RV		 4164 dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n");
4165 goto setup_nic_dev_fail;
4166 }
4167
4168 ifstate_set(lio, LIO_IFSTATE_DROQ_OPS);
4169
f21fb3ed
RV		 4170 lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq);
4171 lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq);
4172
fcd2b5e3 4173 if (setup_glists(octeon_dev, lio, num_iqueues)) {
f21fb3ed
RV		 4174 dev_err(&octeon_dev->pci_dev->dev,
4175 "Gather list allocation failed\n");
4176 goto setup_nic_dev_fail;
4177 }
4178
4179 /* Register ethtool support */
4180 liquidio_set_ethtool_ops(netdev);
30136395
RV		 4181 if (lio->oct_dev->chip_id == OCTEON_CN23XX_PF_VID)
4182 octeon_dev->priv_flags = OCT_PRIV_FLAG_DEFAULT;
4183 else
4184 octeon_dev->priv_flags = 0x0;
f21fb3ed 4185
0cece6c5 4186 if (netdev->features & NETIF_F_LRO)
a2c64b67
RV		 4187 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
4188 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed 4189
63245f25
RV		 4190 liquidio_set_feature(netdev, OCTNET_CMD_ENABLE_VLAN_FILTER, 0);
4191
f21fb3ed 4192 if ((debug != -1) && (debug & NETIF_MSG_HW))
63245f25
RV		 4193 liquidio_set_feature(netdev,
4194 OCTNET_CMD_VERBOSE_ENABLE, 0);
f21fb3ed 4195
7b6b6c95
RV		 4196 if (setup_link_status_change_wq(netdev))
4197 goto setup_nic_dev_fail;
4198
031d4f12
SB		 4199 if (setup_rx_oom_poll_fn(netdev))
4200 goto setup_nic_dev_fail;
4201
f21fb3ed
RV		 4202 /* Register the network device with the OS */
4203 if (register_netdev(netdev)) {
4204 dev_err(&octeon_dev->pci_dev->dev, "Device registration failed\n");
4205 goto setup_nic_dev_fail;
4206 }
4207
4208 dev_dbg(&octeon_dev->pci_dev->dev,
4209 "Setup NIC ifidx:%d mac:%02x%02x%02x%02x%02x%02x\n",
4210 i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
4211 netif_carrier_off(netdev);
0cece6c5 4212 lio->link_changes++;
f21fb3ed
RV		 4213
4214 ifstate_set(lio, LIO_IFSTATE_REGISTERED);
4215
01fb237a
RV		 4216 /* Sending command to firmware to enable Rx checksum offload
4217 * by default at the time of setup of Liquidio driver for
4218 * this device
4219 */
4220 liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL,
4221 OCTNET_CMD_RXCSUM_ENABLE);
4222 liquidio_set_feature(netdev, OCTNET_CMD_TNL_TX_CSUM_CTL,
4223 OCTNET_CMD_TXCSUM_ENABLE);
4224
f21fb3ed
RV		 4225 dev_dbg(&octeon_dev->pci_dev->dev,
4226 "NIC ifidx:%d Setup successful\n", i);
4227
4228 octeon_free_soft_command(octeon_dev, sc);
4229 }
4230
4231 return 0;
4232
4233setup_nic_dev_fail:
4234
4235 octeon_free_soft_command(octeon_dev, sc);
4236
afdf841f
RV		 4237setup_nic_wait_intr:
4238
f21fb3ed
RV		 4239 while (i--) {
4240 dev_err(&octeon_dev->pci_dev->dev,
4241 "NIC ifidx:%d Setup failed\n", i);
4242 liquidio_destroy_nic_device(octeon_dev, i);
4243 }
4244 return -ENODEV;
4245}
4246
ca6139ff
RV		 4247#ifdef CONFIG_PCI_IOV
4248static int octeon_enable_sriov(struct octeon_device *oct)
4249{
4250 unsigned int num_vfs_alloced = oct->sriov_info.num_vfs_alloced;
4251 struct pci_dev *vfdev;
4252 int err;
4253 u32 u;
4254
4255 if (OCTEON_CN23XX_PF(oct) && num_vfs_alloced) {
4256 err = pci_enable_sriov(oct->pci_dev,
4257 oct->sriov_info.num_vfs_alloced);
4258 if (err) {
4259 dev_err(&oct->pci_dev->dev,
4260 "OCTEON: Failed to enable PCI sriov: %d\n",
4261 err);
4262 oct->sriov_info.num_vfs_alloced = 0;
4263 return err;
4264 }
4265 oct->sriov_info.sriov_enabled = 1;
4266
4267 /* init lookup table that maps DPI ring number to VF pci_dev
4268 * struct pointer
4269 */
4270 u = 0;
4271 vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
4272 OCTEON_CN23XX_VF_VID, NULL);
4273 while (vfdev) {
4274 if (vfdev->is_virtfn &&
4275 (vfdev->physfn == oct->pci_dev)) {
4276 oct->sriov_info.dpiring_to_vfpcidev_lut[u] =
4277 vfdev;
4278 u += oct->sriov_info.rings_per_vf;
4279 }
4280 vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
4281 OCTEON_CN23XX_VF_VID, vfdev);
4282 }
4283 }
4284
4285 return num_vfs_alloced;
4286}
4287
4288static int lio_pci_sriov_disable(struct octeon_device *oct)
4289{
4290 int u;
4291
4292 if (pci_vfs_assigned(oct->pci_dev)) {
4293 dev_err(&oct->pci_dev->dev, "VFs are still assigned to VMs.\n");
4294 return -EPERM;
4295 }
4296
4297 pci_disable_sriov(oct->pci_dev);
4298
4299 u = 0;
4300 while (u < MAX_POSSIBLE_VFS) {
4301 oct->sriov_info.dpiring_to_vfpcidev_lut[u] = NULL;
4302 u += oct->sriov_info.rings_per_vf;
4303 }
4304
4305 oct->sriov_info.num_vfs_alloced = 0;
4306 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d disabled VFs\n",
4307 oct->pf_num);
4308
4309 return 0;
4310}
4311
4312static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs)
4313{
4314 struct octeon_device *oct = pci_get_drvdata(dev);
4315 int ret = 0;
4316
4317 if ((num_vfs == oct->sriov_info.num_vfs_alloced) &&
4318 (oct->sriov_info.sriov_enabled)) {
4319 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d already enabled num_vfs:%d\n",
4320 oct->pf_num, num_vfs);
4321 return 0;
4322 }
4323
4324 if (!num_vfs) {
4325 ret = lio_pci_sriov_disable(oct);
4326 } else if (num_vfs > oct->sriov_info.max_vfs) {
4327 dev_err(&oct->pci_dev->dev,
4328 "OCTEON: Max allowed VFs:%d user requested:%d",
4329 oct->sriov_info.max_vfs, num_vfs);
4330 ret = -EPERM;
4331 } else {
4332 oct->sriov_info.num_vfs_alloced = num_vfs;
4333 ret = octeon_enable_sriov(oct);
4334 dev_info(&oct->pci_dev->dev, "oct->pf_num:%d num_vfs:%d\n",
4335 oct->pf_num, num_vfs);
4336 }
4337
4338 return ret;
4339}
4340#endif
4341
f21fb3ed
RV		 4342/**
4343 * \brief initialize the NIC
4344 * @param oct octeon device
4345 *
4346 * This initialization routine is called once the Octeon device application is
4347 * up and running
4348 */
4349static int liquidio_init_nic_module(struct octeon_device *oct)
4350{
0cece6c5 4351 int i, retval = 0;
f21fb3ed
RV		 4352 int num_nic_ports = CFG_GET_NUM_NIC_PORTS(octeon_get_conf(oct));
4353
4354 dev_dbg(&oct->pci_dev->dev, "Initializing network interfaces\n");
4355
4356 /* only default iq and oq were initialized
4357 * initialize the rest as well
4358 */
4359 /* run port_config command for each port */
4360 oct->ifcount = num_nic_ports;
4361
30136395 4362 memset(oct->props, 0, sizeof(struct octdev_props) * num_nic_ports);
f21fb3ed 4363
0cece6c5
RV		 4364 for (i = 0; i < MAX_OCTEON_LINKS; i++)
4365 oct->props[i].gmxport = -1;
4366
f21fb3ed
RV		 4367 retval = setup_nic_devices(oct);
4368 if (retval) {
4369 dev_err(&oct->pci_dev->dev, "Setup NIC devices failed\n");
4370 goto octnet_init_failure;
4371 }
4372
4373 liquidio_ptp_init(oct);
4374
f21fb3ed
RV		 4375 dev_dbg(&oct->pci_dev->dev, "Network interfaces ready\n");
4376
4377 return retval;
4378
4379octnet_init_failure:
4380
4381 oct->ifcount = 0;
4382
4383 return retval;
4384}
4385
4386/**
4387 * \brief starter callback that invokes the remaining initialization work after
4388 * the NIC is up and running.
4389 * @param octptr work struct work_struct
4390 */
4391static void nic_starter(struct work_struct *work)
4392{
4393 struct octeon_device *oct;
4394 struct cavium_wk *wk = (struct cavium_wk *)work;
4395
4396 oct = (struct octeon_device *)wk->ctxptr;
4397
4398 if (atomic_read(&oct->status) == OCT_DEV_RUNNING)
4399 return;
4400
4401 /* If the status of the device is CORE_OK, the core
4402 * application has reported its application type. Call
4403 * any registered handlers now and move to the RUNNING
4404 * state.
4405 */
4406 if (atomic_read(&oct->status) != OCT_DEV_CORE_OK) {
4407 schedule_delayed_work(&oct->nic_poll_work.work,
4408 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
4409 return;
4410 }
4411
4412 atomic_set(&oct->status, OCT_DEV_RUNNING);
4413
4414 if (oct->app_mode && oct->app_mode == CVM_DRV_NIC_APP) {
4415 dev_dbg(&oct->pci_dev->dev, "Starting NIC module\n");
4416
4417 if (liquidio_init_nic_module(oct))
4418 dev_err(&oct->pci_dev->dev, "NIC initialization failed\n");
4419 else
4420 handshake[oct->octeon_id].started_ok = 1;
4421 } else {
4422 dev_err(&oct->pci_dev->dev,
4423 "Unexpected application running on NIC (%d). Check firmware.\n",
4424 oct->app_mode);
4425 }
4426
4427 complete(&handshake[oct->octeon_id].started);
4428}
4429
86dea55b
RV		 4430static int
4431octeon_recv_vf_drv_notice(struct octeon_recv_info *recv_info, void *buf)
4432{
4433 struct octeon_device *oct = (struct octeon_device *)buf;
4434 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
4435 int i, notice, vf_idx;
bb54be58 4436 bool cores_crashed;
86dea55b
RV		 4437 u64 *data, vf_num;
4438
4439 notice = recv_pkt->rh.r.ossp;
4440 data = (u64 *)get_rbd(recv_pkt->buffer_ptr[0]);
4441
4442 /* the first 64-bit word of data is the vf_num */
4443 vf_num = data[0];
4444 octeon_swap_8B_data(&vf_num, 1);
4445 vf_idx = (int)vf_num - 1;
4446
bb54be58
FM		 4447 cores_crashed = READ_ONCE(oct->cores_crashed);
4448
86dea55b
RV		 4449 if (notice == VF_DRV_LOADED) {
4450 if (!(oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx))) {
4451 oct->sriov_info.vf_drv_loaded_mask |= BIT_ULL(vf_idx);
4452 dev_info(&oct->pci_dev->dev,
4453 "driver for VF%d was loaded\n", vf_idx);
bb54be58
FM		 4454 if (!cores_crashed)
4455 try_module_get(THIS_MODULE);
86dea55b
RV		 4456 }
4457 } else if (notice == VF_DRV_REMOVED) {
4458 if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx)) {
4459 oct->sriov_info.vf_drv_loaded_mask &= ~BIT_ULL(vf_idx);
4460 dev_info(&oct->pci_dev->dev,
4461 "driver for VF%d was removed\n", vf_idx);
bb54be58
FM		 4462 if (!cores_crashed)
4463 module_put(THIS_MODULE);
86dea55b
RV		 4464 }
4465 } else if (notice == VF_DRV_MACADDR_CHANGED) {
4466 u8 *b = (u8 *)&data[1];
4467
4468 oct->sriov_info.vf_macaddr[vf_idx] = data[1];
4469 dev_info(&oct->pci_dev->dev,
4470 "VF driver changed VF%d's MAC address to %pM\n",
4471 vf_idx, b + 2);
4472 }
4473
4474 for (i = 0; i < recv_pkt->buffer_count; i++)
4475 recv_buffer_free(recv_pkt->buffer_ptr[i]);
4476 octeon_free_recv_info(recv_info);
4477
4478 return 0;
4479}
4480
f21fb3ed
RV		 4481/**
4482 * \brief Device initialization for each Octeon device that is probed
4483 * @param octeon_dev octeon device
4484 */
4485static int octeon_device_init(struct octeon_device *octeon_dev)
4486{
4487 int j, ret;
c0eab5b3 4488 int fw_loaded = 0;
d3d7e6c6 4489 char bootcmd[] = "\n";
f21fb3ed
RV		 4490 struct octeon_device_priv *oct_priv =
4491 (struct octeon_device_priv *)octeon_dev->priv;
4492 atomic_set(&octeon_dev->status, OCT_DEV_BEGIN_STATE);
4493
4494 /* Enable access to the octeon device and make its DMA capability
4495 * known to the OS.
4496 */
4497 if (octeon_pci_os_setup(octeon_dev))
4498 return 1;
4499
515e752d
RV		 4500 atomic_set(&octeon_dev->status, OCT_DEV_PCI_ENABLE_DONE);
4501
f21fb3ed
RV		 4502 /* Identify the Octeon type and map the BAR address space. */
4503 if (octeon_chip_specific_setup(octeon_dev)) {
4504 dev_err(&octeon_dev->pci_dev->dev, "Chip specific setup failed\n");
4505 return 1;
4506 }
4507
4508 atomic_set(&octeon_dev->status, OCT_DEV_PCI_MAP_DONE);
4509
4510 octeon_dev->app_mode = CVM_DRV_INVALID_APP;
4511
c0eab5b3
RV		 4512 if (OCTEON_CN23XX_PF(octeon_dev)) {
4513 if (!cn23xx_fw_loaded(octeon_dev)) {
4514 fw_loaded = 0;
7cc61db9
FM		 4515 if (!fw_type_is_none()) {
4516 /* Do a soft reset of the Octeon device. */
4517 if (octeon_dev->fn_list.soft_reset(octeon_dev))
4518 return 1;
4519 /* things might have changed */
4520 if (!cn23xx_fw_loaded(octeon_dev))
4521 fw_loaded = 0;
4522 else
4523 fw_loaded = 1;
4524 }
c0eab5b3
RV		 4525 } else {
4526 fw_loaded = 1;
4527 }
4528 } else if (octeon_dev->fn_list.soft_reset(octeon_dev)) {
f21fb3ed 4529 return 1;
c0eab5b3 4530 }
f21fb3ed
RV		 4531
4532 /* Initialize the dispatch mechanism used to push packets arriving on
4533 * Octeon Output queues.
4534 */
4535 if (octeon_init_dispatch_list(octeon_dev))
4536 return 1;
4537
4538 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
4539 OPCODE_NIC_CORE_DRV_ACTIVE,
4540 octeon_core_drv_init,
4541 octeon_dev);
4542
86dea55b
RV		 4543 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
4544 OPCODE_NIC_VF_DRV_NOTICE,
4545 octeon_recv_vf_drv_notice, octeon_dev);
f21fb3ed
RV		 4546 INIT_DELAYED_WORK(&octeon_dev->nic_poll_work.work, nic_starter);
4547 octeon_dev->nic_poll_work.ctxptr = (void *)octeon_dev;
4548 schedule_delayed_work(&octeon_dev->nic_poll_work.work,
4549 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
4550
4551 atomic_set(&octeon_dev->status, OCT_DEV_DISPATCH_INIT_DONE);
4552
c865cdf1
RV		 4553 if (octeon_set_io_queues_off(octeon_dev)) {
4554 dev_err(&octeon_dev->pci_dev->dev, "setting io queues off failed\n");
4555 return 1;
4556 }
f21fb3ed 4557
3451b97c
RV		 4558 if (OCTEON_CN23XX_PF(octeon_dev)) {
4559 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
4560 if (ret) {
4561 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Failed to configure device registers\n");
4562 return ret;
4563 }
4564 }
4565
4566 /* Initialize soft command buffer pool
4567 */
4568 if (octeon_setup_sc_buffer_pool(octeon_dev)) {
4569 dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n");
4570 return 1;
4571 }
4572 atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
4573
f21fb3ed
RV		 4574 /* Setup the data structures that manage this Octeon's Input queues. */
4575 if (octeon_setup_instr_queues(octeon_dev)) {
4576 dev_err(&octeon_dev->pci_dev->dev,
4577 "instruction queue initialization failed\n");
f21fb3ed
RV		 4578 return 1;
4579 }
4580 atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE);
4581
f21fb3ed
RV		 4582 /* Initialize lists to manage the requests of different types that
4583 * arrive from user & kernel applications for this octeon device.
4584 */
4585 if (octeon_setup_response_list(octeon_dev)) {
4586 dev_err(&octeon_dev->pci_dev->dev, "Response list allocation failed\n");
4587 return 1;
4588 }
4589 atomic_set(&octeon_dev->status, OCT_DEV_RESP_LIST_INIT_DONE);
4590
4591 if (octeon_setup_output_queues(octeon_dev)) {
4592 dev_err(&octeon_dev->pci_dev->dev, "Output queue initialization failed\n");
1e0d30fe 4593 return 1;
f21fb3ed
RV		 4594 }
4595
4596 atomic_set(&octeon_dev->status, OCT_DEV_DROQ_INIT_DONE);
4597
5b07aee1 4598 if (OCTEON_CN23XX_PF(octeon_dev)) {
5d65556b
RV		 4599 if (octeon_dev->fn_list.setup_mbox(octeon_dev)) {
4600 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Mailbox setup failed\n");
4601 return 1;
4602 }
4603 atomic_set(&octeon_dev->status, OCT_DEV_MBOX_SETUP_DONE);
4604
5b07aee1
RV		 4605 if (octeon_allocate_ioq_vector(octeon_dev)) {
4606 dev_err(&octeon_dev->pci_dev->dev, "OCTEON: ioq vector allocation failed\n");
4607 return 1;
4608 }
515e752d 4609 atomic_set(&octeon_dev->status, OCT_DEV_MSIX_ALLOC_VECTOR_DONE);
5b07aee1
RV		 4610
4611 } else {
4612 /* The input and output queue registers were setup earlier (the
4613 * queues were not enabled). Any additional registers
4614 * that need to be programmed should be done now.
4615 */
4616 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
4617 if (ret) {
4618 dev_err(&octeon_dev->pci_dev->dev,
4619 "Failed to configure device registers\n");
4620 return ret;
4621 }
f21fb3ed
RV		 4622 }
4623
4624 /* Initialize the tasklet that handles output queue packet processing.*/
4625 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing droq tasklet\n");
4626 tasklet_init(&oct_priv->droq_tasklet, octeon_droq_bh,
4627 (unsigned long)octeon_dev);
4628
4629 /* Setup the interrupt handler and record the INT SUM register address
4630 */
1e0d30fe
RV		 4631 if (octeon_setup_interrupt(octeon_dev))
4632 return 1;
f21fb3ed
RV		 4633
4634 /* Enable Octeon device interrupts */
5b07aee1 4635 octeon_dev->fn_list.enable_interrupt(octeon_dev, OCTEON_ALL_INTR);
f21fb3ed 4636
515e752d
RV		 4637 atomic_set(&octeon_dev->status, OCT_DEV_INTR_SET_DONE);
4638
f21fb3ed 4639 /* Enable the input and output queues for this Octeon device */
1b7c55c4
RV		 4640 ret = octeon_dev->fn_list.enable_io_queues(octeon_dev);
4641 if (ret) {
4642 dev_err(&octeon_dev->pci_dev->dev, "Failed to enable input/output queues");
4643 return ret;
4644 }
f21fb3ed
RV		 4645
4646 atomic_set(&octeon_dev->status, OCT_DEV_IO_QUEUES_DONE);
4647
c0eab5b3
RV		 4648 if ((!OCTEON_CN23XX_PF(octeon_dev)) || !fw_loaded) {
4649 dev_dbg(&octeon_dev->pci_dev->dev, "Waiting for DDR initialization...\n");
4650 if (!ddr_timeout) {
4651 dev_info(&octeon_dev->pci_dev->dev,
4652 "WAITING. Set ddr_timeout to non-zero value to proceed with initialization.\n");
4653 }
f21fb3ed 4654
c0eab5b3 4655 schedule_timeout_uninterruptible(HZ * LIO_RESET_SECS);
f21fb3ed 4656
c0eab5b3
RV		 4657 /* Wait for the octeon to initialize DDR after the soft-reset.*/
4658 while (!ddr_timeout) {
4659 set_current_state(TASK_INTERRUPTIBLE);
4660 if (schedule_timeout(HZ / 10)) {
4661 /* user probably pressed Control-C */
4662 return 1;
4663 }
4664 }
4665 ret = octeon_wait_for_ddr_init(octeon_dev, &ddr_timeout);
4666 if (ret) {
4667 dev_err(&octeon_dev->pci_dev->dev,
4668 "DDR not initialized. Please confirm that board is configured to boot from Flash, ret: %d\n",
4669 ret);
4b129ae3
RV		 4670 return 1;
4671 }
f21fb3ed 4672
c0eab5b3
RV		 4673 if (octeon_wait_for_bootloader(octeon_dev, 1000)) {
4674 dev_err(&octeon_dev->pci_dev->dev, "Board not responding\n");
4675 return 1;
4676 }
f21fb3ed 4677
c0eab5b3
RV		 4678 /* Divert uboot to take commands from host instead. */
4679 ret = octeon_console_send_cmd(octeon_dev, bootcmd, 50);
d3d7e6c6 4680
c0eab5b3
RV		 4681 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing consoles\n");
4682 ret = octeon_init_consoles(octeon_dev);
4683 if (ret) {
4684 dev_err(&octeon_dev->pci_dev->dev, "Could not access board consoles\n");
4685 return 1;
4686 }
4687 ret = octeon_add_console(octeon_dev, 0);
4688 if (ret) {
4689 dev_err(&octeon_dev->pci_dev->dev, "Could not access board console\n");
4690 return 1;
4691 }
f21fb3ed 4692
c0eab5b3 4693 atomic_set(&octeon_dev->status, OCT_DEV_CONSOLE_INIT_DONE);
f21fb3ed 4694
c0eab5b3
RV		 4695 dev_dbg(&octeon_dev->pci_dev->dev, "Loading firmware\n");
4696 ret = load_firmware(octeon_dev);
4697 if (ret) {
4698 dev_err(&octeon_dev->pci_dev->dev, "Could not load firmware to board\n");
4699 return 1;
4700 }
4701 /* set bit 1 of SLI_SCRATCH_1 to indicate that firmware is
4702 * loaded
4703 */
4704 if (OCTEON_CN23XX_PF(octeon_dev))
4705 octeon_write_csr64(octeon_dev, CN23XX_SLI_SCRATCH1,
4706 2ULL);
f21fb3ed
RV		 4707 }
4708
4709 handshake[octeon_dev->octeon_id].init_ok = 1;
4710 complete(&handshake[octeon_dev->octeon_id].init);
4711
4712 atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK);
4713
4714 /* Send Credit for Octeon Output queues. Credits are always sent after
4715 * the output queue is enabled.
4716 */
4717 for (j = 0; j < octeon_dev->num_oqs; j++)
4718 writel(octeon_dev->droq[j]->max_count,
4719 octeon_dev->droq[j]->pkts_credit_reg);
4720
4721 /* Packets can start arriving on the output queues from this point. */
f21fb3ed
RV		 4722 return 0;
4723}
4724
4725/**
4726 * \brief Exits the module
4727 */
4728static void __exit liquidio_exit(void)
4729{
4730 liquidio_deinit_pci();
4731
4732 pr_info("LiquidIO network module is now unloaded\n");
4733}
4734
4735module_init(liquidio_init);
4736module_exit(liquidio_exit);
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