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f21fb3ed
RV		 1/**********************************************************************
2* Author: Cavium, Inc.
3*
4* Contact: support@cavium.com
5* Please include "LiquidIO" in the subject.
6*
7* Copyright (c) 2003-2015 Cavium, Inc.
8*
9* This file is free software; you can redistribute it and/or modify
10* it under the terms of the GNU General Public License, Version 2, as
11* published by the Free Software Foundation.
12*
13* This file is distributed in the hope that it will be useful, but
14* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16* NONINFRINGEMENT. See the GNU General Public License for more
17* details.
18*
19* This file may also be available under a different license from Cavium.
20* Contact Cavium, Inc. for more information
21**********************************************************************/
22#include <linux/version.h>
23#include <linux/module.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/pci.h>
27#include <linux/pci_ids.h>
28#include <linux/ip.h>
5b173cf9 29#include <net/ip.h>
f21fb3ed
RV		 30#include <linux/ipv6.h>
31#include <linux/net_tstamp.h>
32#include <linux/if_vlan.h>
33#include <linux/firmware.h>
34#include <linux/ethtool.h>
35#include <linux/ptp_clock_kernel.h>
36#include <linux/types.h>
37#include <linux/list.h>
38#include <linux/workqueue.h>
39#include <linux/interrupt.h>
40#include "octeon_config.h"
41#include "liquidio_common.h"
42#include "octeon_droq.h"
43#include "octeon_iq.h"
44#include "response_manager.h"
45#include "octeon_device.h"
46#include "octeon_nic.h"
47#include "octeon_main.h"
48#include "octeon_network.h"
49#include "cn66xx_regs.h"
50#include "cn66xx_device.h"
51#include "cn68xx_regs.h"
52#include "cn68xx_device.h"
53#include "liquidio_image.h"
54
55MODULE_AUTHOR("Cavium Networks, <support@cavium.com>");
56MODULE_DESCRIPTION("Cavium LiquidIO Intelligent Server Adapter Driver");
57MODULE_LICENSE("GPL");
58MODULE_VERSION(LIQUIDIO_VERSION);
59MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210SV_NAME LIO_FW_NAME_SUFFIX);
60MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210NV_NAME LIO_FW_NAME_SUFFIX);
61MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_410NV_NAME LIO_FW_NAME_SUFFIX);
62
63static int ddr_timeout = 10000;
64module_param(ddr_timeout, int, 0644);
65MODULE_PARM_DESC(ddr_timeout,
66 "Number of milliseconds to wait for DDR initialization. 0 waits for ddr_timeout to be set to non-zero value before starting to check");
67
68static u32 console_bitmask;
69module_param(console_bitmask, int, 0644);
70MODULE_PARM_DESC(console_bitmask,
71 "Bitmask indicating which consoles have debug output redirected to syslog.");
72
73#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
74
75static int debug = -1;
76module_param(debug, int, 0644);
77MODULE_PARM_DESC(debug, "NETIF_MSG debug bits");
78
79static char fw_type[LIO_MAX_FW_TYPE_LEN];
80module_param_string(fw_type, fw_type, sizeof(fw_type), 0000);
81MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded. Default \"nic\"");
82
83static int conf_type;
84module_param(conf_type, int, 0);
85MODULE_PARM_DESC(conf_type, "select octeon configuration 0 default 1 ovs");
86
a5b37888
RV		 87static int ptp_enable = 1;
88
f21fb3ed
RV		 89/* Bit mask values for lio->ifstate */
90#define LIO_IFSTATE_DROQ_OPS 0x01
91#define LIO_IFSTATE_REGISTERED 0x02
92#define LIO_IFSTATE_RUNNING 0x04
93#define LIO_IFSTATE_RX_TIMESTAMP_ENABLED 0x08
94
95/* Polling interval for determining when NIC application is alive */
96#define LIQUIDIO_STARTER_POLL_INTERVAL_MS 100
97
98/* runtime link query interval */
99#define LIQUIDIO_LINK_QUERY_INTERVAL_MS 1000
100
101struct liquidio_if_cfg_context {
102 int octeon_id;
103
104 wait_queue_head_t wc;
105
106 int cond;
107};
108
109struct liquidio_if_cfg_resp {
110 u64 rh;
111 struct liquidio_if_cfg_info cfg_info;
112 u64 status;
113};
114
115struct oct_link_status_resp {
116 u64 rh;
117 struct oct_link_info link_info;
118 u64 status;
119};
120
121struct oct_timestamp_resp {
122 u64 rh;
123 u64 timestamp;
124 u64 status;
125};
126
127#define OCT_TIMESTAMP_RESP_SIZE (sizeof(struct oct_timestamp_resp))
128
129union tx_info {
130 u64 u64;
131 struct {
132#ifdef __BIG_ENDIAN_BITFIELD
133 u16 gso_size;
134 u16 gso_segs;
135 u32 reserved;
136#else
137 u32 reserved;
138 u16 gso_segs;
139 u16 gso_size;
140#endif
141 } s;
142};
143
144/** Octeon device properties to be used by the NIC module.
145 * Each octeon device in the system will be represented
146 * by this structure in the NIC module.
147 */
148
149#define OCTNIC_MAX_SG (MAX_SKB_FRAGS)
150
151#define OCTNIC_GSO_MAX_HEADER_SIZE 128
152#define OCTNIC_GSO_MAX_SIZE (GSO_MAX_SIZE - OCTNIC_GSO_MAX_HEADER_SIZE)
153
154/** Structure of a node in list of gather components maintained by
155 * NIC driver for each network device.
156 */
157struct octnic_gather {
158 /** List manipulation. Next and prev pointers. */
159 struct list_head list;
160
161 /** Size of the gather component at sg in bytes. */
162 int sg_size;
163
164 /** Number of bytes that sg was adjusted to make it 8B-aligned. */
165 int adjust;
166
167 /** Gather component that can accommodate max sized fragment list
168 * received from the IP layer.
169 */
170 struct octeon_sg_entry *sg;
fcd2b5e3
RV		 171
172 u64 sg_dma_ptr;
f21fb3ed
RV		 173};
174
175/** This structure is used by NIC driver to store information required
176 * to free the sk_buff when the packet has been fetched by Octeon.
177 * Bytes offset below assume worst-case of a 64-bit system.
178 */
179struct octnet_buf_free_info {
180 /** Bytes 1-8. Pointer to network device private structure. */
181 struct lio *lio;
182
183 /** Bytes 9-16. Pointer to sk_buff. */
184 struct sk_buff *skb;
185
186 /** Bytes 17-24. Pointer to gather list. */
187 struct octnic_gather *g;
188
189 /** Bytes 25-32. Physical address of skb->data or gather list. */
190 u64 dptr;
191
192 /** Bytes 33-47. Piggybacked soft command, if any */
193 struct octeon_soft_command *sc;
194};
195
196struct handshake {
197 struct completion init;
198 struct completion started;
199 struct pci_dev *pci_dev;
200 int init_ok;
201 int started_ok;
202};
203
204struct octeon_device_priv {
205 /** Tasklet structures for this device. */
206 struct tasklet_struct droq_tasklet;
207 unsigned long napi_mask;
208};
209
210static int octeon_device_init(struct octeon_device *);
211static void liquidio_remove(struct pci_dev *pdev);
212static int liquidio_probe(struct pci_dev *pdev,
213 const struct pci_device_id *ent);
214
215static struct handshake handshake[MAX_OCTEON_DEVICES];
216static struct completion first_stage;
217
5b173cf9 218static void octeon_droq_bh(unsigned long pdev)
f21fb3ed
RV		 219{
220 int q_no;
221 int reschedule = 0;
222 struct octeon_device *oct = (struct octeon_device *)pdev;
223 struct octeon_device_priv *oct_priv =
224 (struct octeon_device_priv *)oct->priv;
225
226 /* for (q_no = 0; q_no < oct->num_oqs; q_no++) { */
63da8404
RV		 227 for (q_no = 0; q_no < MAX_OCTEON_OUTPUT_QUEUES(oct); q_no++) {
228 if (!(oct->io_qmask.oq & (1ULL << q_no)))
f21fb3ed
RV		 229 continue;
230 reschedule |= octeon_droq_process_packets(oct, oct->droq[q_no],
231 MAX_PACKET_BUDGET);
232 }
233
234 if (reschedule)
235 tasklet_schedule(&oct_priv->droq_tasklet);
236}
237
5b173cf9 238static int lio_wait_for_oq_pkts(struct octeon_device *oct)
f21fb3ed
RV		 239{
240 struct octeon_device_priv *oct_priv =
241 (struct octeon_device_priv *)oct->priv;
242 int retry = 100, pkt_cnt = 0, pending_pkts = 0;
243 int i;
244
245 do {
246 pending_pkts = 0;
247
63da8404
RV		 248 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
249 if (!(oct->io_qmask.oq & (1ULL << i)))
f21fb3ed
RV		 250 continue;
251 pkt_cnt += octeon_droq_check_hw_for_pkts(oct,
252 oct->droq[i]);
253 }
254 if (pkt_cnt > 0) {
255 pending_pkts += pkt_cnt;
256 tasklet_schedule(&oct_priv->droq_tasklet);
257 }
258 pkt_cnt = 0;
259 schedule_timeout_uninterruptible(1);
260
261 } while (retry-- && pending_pkts);
262
263 return pkt_cnt;
264}
265
266void octeon_report_tx_completion_to_bql(void *txq, unsigned int pkts_compl,
267 unsigned int bytes_compl)
268{
269 struct netdev_queue *netdev_queue = txq;
270
271 netdev_tx_completed_queue(netdev_queue, pkts_compl, bytes_compl);
272}
273
274void octeon_update_tx_completion_counters(void *buf, int reqtype,
275 unsigned int *pkts_compl,
276 unsigned int *bytes_compl)
277{
278 struct octnet_buf_free_info *finfo;
279 struct sk_buff *skb = NULL;
280 struct octeon_soft_command *sc;
281
282 switch (reqtype) {
283 case REQTYPE_NORESP_NET:
284 case REQTYPE_NORESP_NET_SG:
285 finfo = buf;
286 skb = finfo->skb;
287 break;
288
289 case REQTYPE_RESP_NET_SG:
290 case REQTYPE_RESP_NET:
291 sc = buf;
292 skb = sc->callback_arg;
293 break;
294
295 default:
296 return;
297 }
298
299 (*pkts_compl)++;
300 *bytes_compl += skb->len;
301}
302
303void octeon_report_sent_bytes_to_bql(void *buf, int reqtype)
304{
305 struct octnet_buf_free_info *finfo;
306 struct sk_buff *skb;
307 struct octeon_soft_command *sc;
308 struct netdev_queue *txq;
309
310 switch (reqtype) {
311 case REQTYPE_NORESP_NET:
312 case REQTYPE_NORESP_NET_SG:
313 finfo = buf;
314 skb = finfo->skb;
315 break;
316
317 case REQTYPE_RESP_NET_SG:
318 case REQTYPE_RESP_NET:
319 sc = buf;
320 skb = sc->callback_arg;
321 break;
322
323 default:
324 return;
325 }
326
327 txq = netdev_get_tx_queue(skb->dev, skb_get_queue_mapping(skb));
328 netdev_tx_sent_queue(txq, skb->len);
329}
330
331int octeon_console_debug_enabled(u32 console)
332{
333 return (console_bitmask >> (console)) & 0x1;
334}
335
336/**
337 * \brief Forces all IO queues off on a given device
338 * @param oct Pointer to Octeon device
339 */
340static void force_io_queues_off(struct octeon_device *oct)
341{
342 if ((oct->chip_id == OCTEON_CN66XX) ||
343 (oct->chip_id == OCTEON_CN68XX)) {
344 /* Reset the Enable bits for Input Queues. */
345 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
346
347 /* Reset the Enable bits for Output Queues. */
348 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
349 }
350}
351
352/**
353 * \brief wait for all pending requests to complete
354 * @param oct Pointer to Octeon device
355 *
356 * Called during shutdown sequence
357 */
358static int wait_for_pending_requests(struct octeon_device *oct)
359{
360 int i, pcount = 0;
361
362 for (i = 0; i < 100; i++) {
363 pcount =
364 atomic_read(&oct->response_list
365 [OCTEON_ORDERED_SC_LIST].pending_req_count);
366 if (pcount)
367 schedule_timeout_uninterruptible(HZ / 10);
9a96bde4 368 else
f21fb3ed
RV		 369 break;
370 }
371
372 if (pcount)
373 return 1;
374
375 return 0;
376}
377
378/**
379 * \brief Cause device to go quiet so it can be safely removed/reset/etc
380 * @param oct Pointer to Octeon device
381 */
382static inline void pcierror_quiesce_device(struct octeon_device *oct)
383{
384 int i;
385
386 /* Disable the input and output queues now. No more packets will
387 * arrive from Octeon, but we should wait for all packet processing
388 * to finish.
389 */
390 force_io_queues_off(oct);
391
392 /* To allow for in-flight requests */
393 schedule_timeout_uninterruptible(100);
394
395 if (wait_for_pending_requests(oct))
396 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
397
398 /* Force all requests waiting to be fetched by OCTEON to complete. */
63da8404 399 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
f21fb3ed
RV		 400 struct octeon_instr_queue *iq;
401
63da8404 402 if (!(oct->io_qmask.iq & (1ULL << i)))
f21fb3ed
RV		 403 continue;
404 iq = oct->instr_queue[i];
405
406 if (atomic_read(&iq->instr_pending)) {
407 spin_lock_bh(&iq->lock);
408 iq->fill_cnt = 0;
409 iq->octeon_read_index = iq->host_write_index;
410 iq->stats.instr_processed +=
411 atomic_read(&iq->instr_pending);
9a96bde4 412 lio_process_iq_request_list(oct, iq, 0);
f21fb3ed
RV		 413 spin_unlock_bh(&iq->lock);
414 }
415 }
416
417 /* Force all pending ordered list requests to time out. */
418 lio_process_ordered_list(oct, 1);
419
420 /* We do not need to wait for output queue packets to be processed. */
421}
422
423/**
424 * \brief Cleanup PCI AER uncorrectable error status
425 * @param dev Pointer to PCI device
426 */
427static void cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
428{
429 int pos = 0x100;
430 u32 status, mask;
431
432 pr_info("%s :\n", __func__);
433
434 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
435 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
436 if (dev->error_state == pci_channel_io_normal)
437 status &= ~mask; /* Clear corresponding nonfatal bits */
438 else
439 status &= mask; /* Clear corresponding fatal bits */
440 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
441}
442
443/**
444 * \brief Stop all PCI IO to a given device
445 * @param dev Pointer to Octeon device
446 */
447static void stop_pci_io(struct octeon_device *oct)
448{
449 /* No more instructions will be forwarded. */
450 atomic_set(&oct->status, OCT_DEV_IN_RESET);
451
452 pci_disable_device(oct->pci_dev);
453
454 /* Disable interrupts */
455 oct->fn_list.disable_interrupt(oct->chip);
456
457 pcierror_quiesce_device(oct);
458
459 /* Release the interrupt line */
460 free_irq(oct->pci_dev->irq, oct);
461
462 if (oct->flags & LIO_FLAG_MSI_ENABLED)
463 pci_disable_msi(oct->pci_dev);
464
465 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
466 lio_get_state_string(&oct->status));
467
468 /* cn63xx_cleanup_aer_uncorrect_error_status(oct->pci_dev); */
469 /* making it a common function for all OCTEON models */
470 cleanup_aer_uncorrect_error_status(oct->pci_dev);
471}
472
473/**
474 * \brief called when PCI error is detected
475 * @param pdev Pointer to PCI device
476 * @param state The current pci connection state
477 *
478 * This function is called after a PCI bus error affecting
479 * this device has been detected.
480 */
481static pci_ers_result_t liquidio_pcie_error_detected(struct pci_dev *pdev,
482 pci_channel_state_t state)
483{
484 struct octeon_device *oct = pci_get_drvdata(pdev);
485
486 /* Non-correctable Non-fatal errors */
487 if (state == pci_channel_io_normal) {
488 dev_err(&oct->pci_dev->dev, "Non-correctable non-fatal error reported:\n");
489 cleanup_aer_uncorrect_error_status(oct->pci_dev);
490 return PCI_ERS_RESULT_CAN_RECOVER;
491 }
492
493 /* Non-correctable Fatal errors */
494 dev_err(&oct->pci_dev->dev, "Non-correctable FATAL reported by PCI AER driver\n");
495 stop_pci_io(oct);
496
497 /* Always return a DISCONNECT. There is no support for recovery but only
498 * for a clean shutdown.
499 */
500 return PCI_ERS_RESULT_DISCONNECT;
501}
502
503/**
504 * \brief mmio handler
505 * @param pdev Pointer to PCI device
506 */
507static pci_ers_result_t liquidio_pcie_mmio_enabled(struct pci_dev *pdev)
508{
509 /* We should never hit this since we never ask for a reset for a Fatal
510 * Error. We always return DISCONNECT in io_error above.
511 * But play safe and return RECOVERED for now.
512 */
513 return PCI_ERS_RESULT_RECOVERED;
514}
515
516/**
517 * \brief called after the pci bus has been reset.
518 * @param pdev Pointer to PCI device
519 *
520 * Restart the card from scratch, as if from a cold-boot. Implementation
521 * resembles the first-half of the octeon_resume routine.
522 */
523static pci_ers_result_t liquidio_pcie_slot_reset(struct pci_dev *pdev)
524{
525 /* We should never hit this since we never ask for a reset for a Fatal
526 * Error. We always return DISCONNECT in io_error above.
527 * But play safe and return RECOVERED for now.
528 */
529 return PCI_ERS_RESULT_RECOVERED;
530}
531
532/**
533 * \brief called when traffic can start flowing again.
534 * @param pdev Pointer to PCI device
535 *
536 * This callback is called when the error recovery driver tells us that
537 * its OK to resume normal operation. Implementation resembles the
538 * second-half of the octeon_resume routine.
539 */
540static void liquidio_pcie_resume(struct pci_dev *pdev)
541{
542 /* Nothing to be done here. */
543}
544
545#ifdef CONFIG_PM
546/**
547 * \brief called when suspending
548 * @param pdev Pointer to PCI device
549 * @param state state to suspend to
550 */
551static int liquidio_suspend(struct pci_dev *pdev, pm_message_t state)
552{
553 return 0;
554}
555
556/**
557 * \brief called when resuming
558 * @param pdev Pointer to PCI device
559 */
560static int liquidio_resume(struct pci_dev *pdev)
561{
562 return 0;
563}
564#endif
565
566/* For PCI-E Advanced Error Recovery (AER) Interface */
166e2362 567static const struct pci_error_handlers liquidio_err_handler = {
f21fb3ed
RV		 568 .error_detected = liquidio_pcie_error_detected,
569 .mmio_enabled = liquidio_pcie_mmio_enabled,
570 .slot_reset = liquidio_pcie_slot_reset,
571 .resume = liquidio_pcie_resume,
572};
573
574static const struct pci_device_id liquidio_pci_tbl[] = {
575 { /* 68xx */
576 PCI_VENDOR_ID_CAVIUM, 0x91, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
577 },
578 { /* 66xx */
579 PCI_VENDOR_ID_CAVIUM, 0x92, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
580 },
581 {
582 0, 0, 0, 0, 0, 0, 0
583 }
584};
585MODULE_DEVICE_TABLE(pci, liquidio_pci_tbl);
586
587static struct pci_driver liquidio_pci_driver = {
588 .name = "LiquidIO",
589 .id_table = liquidio_pci_tbl,
590 .probe = liquidio_probe,
591 .remove = liquidio_remove,
592 .err_handler = &liquidio_err_handler, /* For AER */
593
594#ifdef CONFIG_PM
595 .suspend = liquidio_suspend,
596 .resume = liquidio_resume,
597#endif
598
599};
600
601/**
602 * \brief register PCI driver
603 */
604static int liquidio_init_pci(void)
605{
606 return pci_register_driver(&liquidio_pci_driver);
607}
608
609/**
610 * \brief unregister PCI driver
611 */
612static void liquidio_deinit_pci(void)
613{
614 pci_unregister_driver(&liquidio_pci_driver);
615}
616
617/**
618 * \brief check interface state
619 * @param lio per-network private data
620 * @param state_flag flag state to check
621 */
622static inline int ifstate_check(struct lio *lio, int state_flag)
623{
624 return atomic_read(&lio->ifstate) & state_flag;
625}
626
627/**
628 * \brief set interface state
629 * @param lio per-network private data
630 * @param state_flag flag state to set
631 */
632static inline void ifstate_set(struct lio *lio, int state_flag)
633{
634 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) | state_flag));
635}
636
637/**
638 * \brief clear interface state
639 * @param lio per-network private data
640 * @param state_flag flag state to clear
641 */
642static inline void ifstate_reset(struct lio *lio, int state_flag)
643{
644 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) & ~(state_flag)));
645}
646
647/**
648 * \brief Stop Tx queues
649 * @param netdev network device
650 */
651static inline void txqs_stop(struct net_device *netdev)
652{
653 if (netif_is_multiqueue(netdev)) {
654 int i;
655
656 for (i = 0; i < netdev->num_tx_queues; i++)
657 netif_stop_subqueue(netdev, i);
658 } else {
659 netif_stop_queue(netdev);
660 }
661}
662
663/**
664 * \brief Start Tx queues
665 * @param netdev network device
666 */
667static inline void txqs_start(struct net_device *netdev)
668{
669 if (netif_is_multiqueue(netdev)) {
670 int i;
671
672 for (i = 0; i < netdev->num_tx_queues; i++)
673 netif_start_subqueue(netdev, i);
674 } else {
675 netif_start_queue(netdev);
676 }
677}
678
679/**
680 * \brief Wake Tx queues
681 * @param netdev network device
682 */
683static inline void txqs_wake(struct net_device *netdev)
684{
685 if (netif_is_multiqueue(netdev)) {
686 int i;
687
688 for (i = 0; i < netdev->num_tx_queues; i++)
26236fa9
RV		 689 if (__netif_subqueue_stopped(netdev, i))
690 netif_wake_subqueue(netdev, i);
f21fb3ed
RV		 691 } else {
692 netif_wake_queue(netdev);
693 }
694}
695
696/**
697 * \brief Stop Tx queue
698 * @param netdev network device
699 */
700static void stop_txq(struct net_device *netdev)
701{
702 txqs_stop(netdev);
703}
704
705/**
706 * \brief Start Tx queue
707 * @param netdev network device
708 */
709static void start_txq(struct net_device *netdev)
710{
711 struct lio *lio = GET_LIO(netdev);
712
0cece6c5 713 if (lio->linfo.link.s.link_up) {
f21fb3ed
RV		 714 txqs_start(netdev);
715 return;
716 }
717}
718
719/**
720 * \brief Wake a queue
721 * @param netdev network device
722 * @param q which queue to wake
723 */
724static inline void wake_q(struct net_device *netdev, int q)
725{
726 if (netif_is_multiqueue(netdev))
727 netif_wake_subqueue(netdev, q);
728 else
729 netif_wake_queue(netdev);
730}
731
732/**
733 * \brief Stop a queue
734 * @param netdev network device
735 * @param q which queue to stop
736 */
737static inline void stop_q(struct net_device *netdev, int q)
738{
739 if (netif_is_multiqueue(netdev))
740 netif_stop_subqueue(netdev, q);
741 else
742 netif_stop_queue(netdev);
743}
744
745/**
746 * \brief Check Tx queue status, and take appropriate action
747 * @param lio per-network private data
748 * @returns 0 if full, number of queues woken up otherwise
749 */
750static inline int check_txq_status(struct lio *lio)
751{
752 int ret_val = 0;
753
754 if (netif_is_multiqueue(lio->netdev)) {
755 int numqs = lio->netdev->num_tx_queues;
756 int q, iq = 0;
757
758 /* check each sub-queue state */
759 for (q = 0; q < numqs; q++) {
26236fa9
RV		 760 iq = lio->linfo.txpciq[q %
761 (lio->linfo.num_txpciq)].s.q_no;
f21fb3ed
RV		 762 if (octnet_iq_is_full(lio->oct_dev, iq))
763 continue;
26236fa9
RV		 764 if (__netif_subqueue_stopped(lio->netdev, q)) {
765 wake_q(lio->netdev, q);
766 ret_val++;
767 }
f21fb3ed
RV		 768 }
769 } else {
770 if (octnet_iq_is_full(lio->oct_dev, lio->txq))
771 return 0;
772 wake_q(lio->netdev, lio->txq);
773 ret_val = 1;
774 }
775 return ret_val;
776}
777
778/**
779 * Remove the node at the head of the list. The list would be empty at
780 * the end of this call if there are no more nodes in the list.
781 */
782static inline struct list_head *list_delete_head(struct list_head *root)
783{
784 struct list_head *node;
785
786 if ((root->prev == root) && (root->next == root))
787 node = NULL;
788 else
789 node = root->next;
790
791 if (node)
792 list_del(node);
793
794 return node;
795}
796
797/**
fcd2b5e3 798 * \brief Delete gather lists
f21fb3ed
RV		 799 * @param lio per-network private data
800 */
fcd2b5e3 801static void delete_glists(struct lio *lio)
f21fb3ed
RV		 802{
803 struct octnic_gather *g;
fcd2b5e3 804 int i;
f21fb3ed 805
fcd2b5e3
RV		 806 if (!lio->glist)
807 return;
808
809 for (i = 0; i < lio->linfo.num_txpciq; i++) {
810 do {
811 g = (struct octnic_gather *)
812 list_delete_head(&lio->glist[i]);
813 if (g) {
814 if (g->sg) {
815 dma_unmap_single(&lio->oct_dev->
816 pci_dev->dev,
817 g->sg_dma_ptr,
818 g->sg_size,
819 DMA_TO_DEVICE);
820 kfree((void *)((unsigned long)g->sg -
821 g->adjust));
822 }
823 kfree(g);
824 }
825 } while (g);
826 }
827
828 kfree((void *)lio->glist);
f21fb3ed
RV		 829}
830
831/**
fcd2b5e3 832 * \brief Setup gather lists
f21fb3ed
RV		 833 * @param lio per-network private data
834 */
fcd2b5e3 835static int setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs)
f21fb3ed 836{
fcd2b5e3 837 int i, j;
f21fb3ed
RV		 838 struct octnic_gather *g;
839
fcd2b5e3
RV		 840 lio->glist_lock = kcalloc(num_iqs, sizeof(*lio->glist_lock),
841 GFP_KERNEL);
842 if (!lio->glist_lock)
843 return 1;
f21fb3ed 844
fcd2b5e3
RV		 845 lio->glist = kcalloc(num_iqs, sizeof(*lio->glist),
846 GFP_KERNEL);
847 if (!lio->glist) {
848 kfree((void *)lio->glist_lock);
849 return 1;
850 }
f21fb3ed 851
fcd2b5e3
RV		 852 for (i = 0; i < num_iqs; i++) {
853 int numa_node = cpu_to_node(i % num_online_cpus());
f21fb3ed 854
fcd2b5e3
RV		 855 spin_lock_init(&lio->glist_lock[i]);
856
857 INIT_LIST_HEAD(&lio->glist[i]);
858
859 for (j = 0; j < lio->tx_qsize; j++) {
860 g = kzalloc_node(sizeof(*g), GFP_KERNEL,
861 numa_node);
862 if (!g)
863 g = kzalloc(sizeof(*g), GFP_KERNEL);
864 if (!g)
865 break;
866
867 g->sg_size = ((ROUNDUP4(OCTNIC_MAX_SG) >> 2) *
868 OCT_SG_ENTRY_SIZE);
869
870 g->sg = kmalloc_node(g->sg_size + 8,
871 GFP_KERNEL, numa_node);
872 if (!g->sg)
873 g->sg = kmalloc(g->sg_size + 8, GFP_KERNEL);
874 if (!g->sg) {
875 kfree(g);
876 break;
877 }
878
879 /* The gather component should be aligned on 64-bit
880 * boundary
881 */
882 if (((unsigned long)g->sg) & 7) {
883 g->adjust = 8 - (((unsigned long)g->sg) & 7);
884 g->sg = (struct octeon_sg_entry *)
885 ((unsigned long)g->sg + g->adjust);
886 }
887 g->sg_dma_ptr = dma_map_single(&oct->pci_dev->dev,
888 g->sg, g->sg_size,
889 DMA_TO_DEVICE);
890 if (dma_mapping_error(&oct->pci_dev->dev,
891 g->sg_dma_ptr)) {
892 kfree((void *)((unsigned long)g->sg -
893 g->adjust));
894 kfree(g);
895 break;
896 }
897
898 list_add_tail(&g->list, &lio->glist[i]);
f21fb3ed
RV		 899 }
900
fcd2b5e3
RV		 901 if (j != lio->tx_qsize) {
902 delete_glists(lio);
903 return 1;
f21fb3ed 904 }
f21fb3ed
RV		 905 }
906
fcd2b5e3 907 return 0;
f21fb3ed
RV		 908}
909
910/**
911 * \brief Print link information
912 * @param netdev network device
913 */
914static void print_link_info(struct net_device *netdev)
915{
916 struct lio *lio = GET_LIO(netdev);
917
918 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED) {
919 struct oct_link_info *linfo = &lio->linfo;
920
0cece6c5 921 if (linfo->link.s.link_up) {
f21fb3ed
RV		 922 netif_info(lio, link, lio->netdev, "%d Mbps %s Duplex UP\n",
923 linfo->link.s.speed,
924 (linfo->link.s.duplex) ? "Full" : "Half");
925 } else {
926 netif_info(lio, link, lio->netdev, "Link Down\n");
927 }
928 }
929}
930
931/**
932 * \brief Update link status
933 * @param netdev network device
934 * @param ls link status structure
935 *
936 * Called on receipt of a link status response from the core application to
937 * update each interface's link status.
938 */
939static inline void update_link_status(struct net_device *netdev,
940 union oct_link_status *ls)
941{
942 struct lio *lio = GET_LIO(netdev);
0cece6c5 943 int changed = (lio->linfo.link.u64 != ls->u64);
f21fb3ed 944
0cece6c5 945 lio->linfo.link.u64 = ls->u64;
f21fb3ed 946
0cece6c5 947 if ((lio->intf_open) && (changed)) {
f21fb3ed 948 print_link_info(netdev);
0cece6c5 949 lio->link_changes++;
f21fb3ed 950
0cece6c5 951 if (lio->linfo.link.s.link_up) {
f21fb3ed
RV		 952 netif_carrier_on(netdev);
953 /* start_txq(netdev); */
954 txqs_wake(netdev);
955 } else {
956 netif_carrier_off(netdev);
957 stop_txq(netdev);
958 }
959 }
960}
961
9a96bde4
RV		 962/* Runs in interrupt context. */
963static void update_txq_status(struct octeon_device *oct, int iq_num)
964{
965 struct net_device *netdev;
966 struct lio *lio;
967 struct octeon_instr_queue *iq = oct->instr_queue[iq_num];
968
969 /*octeon_update_iq_read_idx(oct, iq);*/
970
971 netdev = oct->props[iq->ifidx].netdev;
972
973 /* This is needed because the first IQ does not have
974 * a netdev associated with it.
975 */
976 if (!netdev)
977 return;
978
979 lio = GET_LIO(netdev);
980 if (netif_is_multiqueue(netdev)) {
981 if (__netif_subqueue_stopped(netdev, iq->q_index) &&
982 lio->linfo.link.s.link_up &&
983 (!octnet_iq_is_full(oct, iq_num))) {
984 netif_wake_subqueue(netdev, iq->q_index);
985 } else {
986 if (!octnet_iq_is_full(oct, lio->txq))
987 wake_q(netdev, lio->txq);
988 }
989 }
990}
991
f21fb3ed
RV		 992/**
993 * \brief Droq packet processor sceduler
994 * @param oct octeon device
995 */
996static
997void liquidio_schedule_droq_pkt_handlers(struct octeon_device *oct)
998{
999 struct octeon_device_priv *oct_priv =
1000 (struct octeon_device_priv *)oct->priv;
1001 u64 oq_no;
1002 struct octeon_droq *droq;
1003
1004 if (oct->int_status & OCT_DEV_INTR_PKT_DATA) {
63da8404
RV		 1005 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct);
1006 oq_no++) {
1007 if (!(oct->droq_intr & (1ULL << oq_no)))
f21fb3ed
RV		 1008 continue;
1009
1010 droq = oct->droq[oq_no];
1011
1012 if (droq->ops.poll_mode) {
1013 droq->ops.napi_fn(droq);
1014 oct_priv->napi_mask |= (1 << oq_no);
1015 } else {
1016 tasklet_schedule(&oct_priv->droq_tasklet);
1017 }
1018 }
1019 }
1020}
1021
1022/**
1023 * \brief Interrupt handler for octeon
1024 * @param irq unused
1025 * @param dev octeon device
1026 */
1027static
1028irqreturn_t liquidio_intr_handler(int irq __attribute__((unused)), void *dev)
1029{
1030 struct octeon_device *oct = (struct octeon_device *)dev;
1031 irqreturn_t ret;
1032
1033 /* Disable our interrupts for the duration of ISR */
1034 oct->fn_list.disable_interrupt(oct->chip);
1035
1036 ret = oct->fn_list.process_interrupt_regs(oct);
1037
1038 if (ret == IRQ_HANDLED)
1039 liquidio_schedule_droq_pkt_handlers(oct);
1040
1041 /* Re-enable our interrupts */
1042 if (!(atomic_read(&oct->status) == OCT_DEV_IN_RESET))
1043 oct->fn_list.enable_interrupt(oct->chip);
1044
1045 return ret;
1046}
1047
1048/**
1049 * \brief Setup interrupt for octeon device
1050 * @param oct octeon device
1051 *
1052 * Enable interrupt in Octeon device as given in the PCI interrupt mask.
1053 */
1054static int octeon_setup_interrupt(struct octeon_device *oct)
1055{
1056 int irqret, err;
1057
1058 err = pci_enable_msi(oct->pci_dev);
1059 if (err)
1060 dev_warn(&oct->pci_dev->dev, "Reverting to legacy interrupts. Error: %d\n",
1061 err);
1062 else
1063 oct->flags |= LIO_FLAG_MSI_ENABLED;
1064
1065 irqret = request_irq(oct->pci_dev->irq, liquidio_intr_handler,
1066 IRQF_SHARED, "octeon", oct);
1067 if (irqret) {
1068 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1069 pci_disable_msi(oct->pci_dev);
1070 dev_err(&oct->pci_dev->dev, "Request IRQ failed with code: %d\n",
1071 irqret);
1072 return 1;
1073 }
1074
1075 return 0;
1076}
1077
1078/**
1079 * \brief PCI probe handler
1080 * @param pdev PCI device structure
1081 * @param ent unused
1082 */
1083static int liquidio_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1084{
1085 struct octeon_device *oct_dev = NULL;
1086 struct handshake *hs;
1087
1088 oct_dev = octeon_allocate_device(pdev->device,
1089 sizeof(struct octeon_device_priv));
1090 if (!oct_dev) {
1091 dev_err(&pdev->dev, "Unable to allocate device\n");
1092 return -ENOMEM;
1093 }
1094
1095 dev_info(&pdev->dev, "Initializing device %x:%x.\n",
1096 (u32)pdev->vendor, (u32)pdev->device);
1097
1098 /* Assign octeon_device for this device to the private data area. */
1099 pci_set_drvdata(pdev, oct_dev);
1100
1101 /* set linux specific device pointer */
1102 oct_dev->pci_dev = (void *)pdev;
1103
1104 hs = &handshake[oct_dev->octeon_id];
1105 init_completion(&hs->init);
1106 init_completion(&hs->started);
1107 hs->pci_dev = pdev;
1108
1109 if (oct_dev->octeon_id == 0)
1110 /* first LiquidIO NIC is detected */
1111 complete(&first_stage);
1112
1113 if (octeon_device_init(oct_dev)) {
1114 liquidio_remove(pdev);
1115 return -ENOMEM;
1116 }
1117
1118 dev_dbg(&oct_dev->pci_dev->dev, "Device is ready\n");
1119
1120 return 0;
1121}
1122
1123/**
1124 *\brief Destroy resources associated with octeon device
1125 * @param pdev PCI device structure
1126 * @param ent unused
1127 */
1128static void octeon_destroy_resources(struct octeon_device *oct)
1129{
1130 int i;
1131 struct octeon_device_priv *oct_priv =
1132 (struct octeon_device_priv *)oct->priv;
1133
1134 struct handshake *hs;
1135
1136 switch (atomic_read(&oct->status)) {
1137 case OCT_DEV_RUNNING:
1138 case OCT_DEV_CORE_OK:
1139
1140 /* No more instructions will be forwarded. */
1141 atomic_set(&oct->status, OCT_DEV_IN_RESET);
1142
1143 oct->app_mode = CVM_DRV_INVALID_APP;
1144 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
1145 lio_get_state_string(&oct->status));
1146
1147 schedule_timeout_uninterruptible(HZ / 10);
1148
1149 /* fallthrough */
1150 case OCT_DEV_HOST_OK:
1151
1152 /* fallthrough */
1153 case OCT_DEV_CONSOLE_INIT_DONE:
1154 /* Remove any consoles */
1155 octeon_remove_consoles(oct);
1156
1157 /* fallthrough */
1158 case OCT_DEV_IO_QUEUES_DONE:
1159 if (wait_for_pending_requests(oct))
1160 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
1161
1162 if (lio_wait_for_instr_fetch(oct))
1163 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n");
1164
1165 /* Disable the input and output queues now. No more packets will
1166 * arrive from Octeon, but we should wait for all packet
1167 * processing to finish.
1168 */
1169 oct->fn_list.disable_io_queues(oct);
1170
1171 if (lio_wait_for_oq_pkts(oct))
1172 dev_err(&oct->pci_dev->dev, "OQ had pending packets\n");
1173
1174 /* Disable interrupts */
1175 oct->fn_list.disable_interrupt(oct->chip);
1176
1177 /* Release the interrupt line */
1178 free_irq(oct->pci_dev->irq, oct);
1179
1180 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1181 pci_disable_msi(oct->pci_dev);
1182
1183 /* Soft reset the octeon device before exiting */
1184 oct->fn_list.soft_reset(oct);
1185
1186 /* Disable the device, releasing the PCI INT */
1187 pci_disable_device(oct->pci_dev);
1188
1189 /* fallthrough */
1190 case OCT_DEV_IN_RESET:
1191 case OCT_DEV_DROQ_INIT_DONE:
1192 /*atomic_set(&oct->status, OCT_DEV_DROQ_INIT_DONE);*/
1193 mdelay(100);
63da8404
RV		 1194 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
1195 if (!(oct->io_qmask.oq & (1ULL << i)))
f21fb3ed
RV		 1196 continue;
1197 octeon_delete_droq(oct, i);
1198 }
1199
1200 /* Force any pending handshakes to complete */
1201 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
1202 hs = &handshake[i];
1203
1204 if (hs->pci_dev) {
1205 handshake[oct->octeon_id].init_ok = 0;
1206 complete(&handshake[oct->octeon_id].init);
1207 handshake[oct->octeon_id].started_ok = 0;
1208 complete(&handshake[oct->octeon_id].started);
1209 }
1210 }
1211
1212 /* fallthrough */
1213 case OCT_DEV_RESP_LIST_INIT_DONE:
1214 octeon_delete_response_list(oct);
1215
1216 /* fallthrough */
1217 case OCT_DEV_SC_BUFF_POOL_INIT_DONE:
1218 octeon_free_sc_buffer_pool(oct);
1219
1220 /* fallthrough */
1221 case OCT_DEV_INSTR_QUEUE_INIT_DONE:
63da8404
RV		 1222 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
1223 if (!(oct->io_qmask.iq & (1ULL << i)))
f21fb3ed
RV		 1224 continue;
1225 octeon_delete_instr_queue(oct, i);
1226 }
1227
1228 /* fallthrough */
1229 case OCT_DEV_DISPATCH_INIT_DONE:
1230 octeon_delete_dispatch_list(oct);
1231 cancel_delayed_work_sync(&oct->nic_poll_work.work);
1232
1233 /* fallthrough */
1234 case OCT_DEV_PCI_MAP_DONE:
1235 octeon_unmap_pci_barx(oct, 0);
1236 octeon_unmap_pci_barx(oct, 1);
1237
1238 /* fallthrough */
1239 case OCT_DEV_BEGIN_STATE:
1240 /* Nothing to be done here either */
1241 break;
1242 } /* end switch(oct->status) */
1243
1244 tasklet_kill(&oct_priv->droq_tasklet);
1245}
1246
1247/**
1248 * \brief Send Rx control command
1249 * @param lio per-network private data
1250 * @param start_stop whether to start or stop
1251 */
1252static void send_rx_ctrl_cmd(struct lio *lio, int start_stop)
1253{
1254 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 1255
1256 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
1257
1258 nctrl.ncmd.s.cmd = OCTNET_CMD_RX_CTL;
0cece6c5
RV		 1259 nctrl.ncmd.s.param1 = start_stop;
1260 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 1261 nctrl.netpndev = (u64)lio->netdev;
1262
0cece6c5 1263 if (octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl) < 0)
f21fb3ed
RV		 1264 netif_info(lio, rx_err, lio->netdev, "Failed to send RX Control message\n");
1265}
1266
1267/**
1268 * \brief Destroy NIC device interface
1269 * @param oct octeon device
1270 * @param ifidx which interface to destroy
1271 *
1272 * Cleanup associated with each interface for an Octeon device when NIC
1273 * module is being unloaded or if initialization fails during load.
1274 */
1275static void liquidio_destroy_nic_device(struct octeon_device *oct, int ifidx)
1276{
1277 struct net_device *netdev = oct->props[ifidx].netdev;
1278 struct lio *lio;
9a96bde4 1279 struct napi_struct *napi, *n;
f21fb3ed
RV		 1280
1281 if (!netdev) {
1282 dev_err(&oct->pci_dev->dev, "%s No netdevice ptr for index %d\n",
1283 __func__, ifidx);
1284 return;
1285 }
1286
1287 lio = GET_LIO(netdev);
1288
1289 dev_dbg(&oct->pci_dev->dev, "NIC device cleanup\n");
1290
1291 send_rx_ctrl_cmd(lio, 0);
1292
1293 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING)
1294 txqs_stop(netdev);
1295
9a96bde4
RV		 1296 if (oct->props[lio->ifidx].napi_enabled == 1) {
1297 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
1298 napi_disable(napi);
1299
1300 oct->props[lio->ifidx].napi_enabled = 0;
1301 }
1302
f21fb3ed
RV		 1303 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED)
1304 unregister_netdev(netdev);
1305
fcd2b5e3 1306 delete_glists(lio);
f21fb3ed
RV		 1307
1308 free_netdev(netdev);
1309
0cece6c5
RV		 1310 oct->props[ifidx].gmxport = -1;
1311
f21fb3ed
RV		 1312 oct->props[ifidx].netdev = NULL;
1313}
1314
1315/**
1316 * \brief Stop complete NIC functionality
1317 * @param oct octeon device
1318 */
1319static int liquidio_stop_nic_module(struct octeon_device *oct)
1320{
1321 int i, j;
1322 struct lio *lio;
1323
1324 dev_dbg(&oct->pci_dev->dev, "Stopping network interfaces\n");
1325 if (!oct->ifcount) {
1326 dev_err(&oct->pci_dev->dev, "Init for Octeon was not completed\n");
1327 return 1;
1328 }
1329
1330 for (i = 0; i < oct->ifcount; i++) {
1331 lio = GET_LIO(oct->props[i].netdev);
1332 for (j = 0; j < lio->linfo.num_rxpciq; j++)
26236fa9
RV		 1333 octeon_unregister_droq_ops(oct,
1334 lio->linfo.rxpciq[j].s.q_no);
f21fb3ed
RV		 1335 }
1336
1337 for (i = 0; i < oct->ifcount; i++)
1338 liquidio_destroy_nic_device(oct, i);
1339
1340 dev_dbg(&oct->pci_dev->dev, "Network interfaces stopped\n");
1341 return 0;
1342}
1343
1344/**
1345 * \brief Cleans up resources at unload time
1346 * @param pdev PCI device structure
1347 */
1348static void liquidio_remove(struct pci_dev *pdev)
1349{
1350 struct octeon_device *oct_dev = pci_get_drvdata(pdev);
1351
1352 dev_dbg(&oct_dev->pci_dev->dev, "Stopping device\n");
1353
1354 if (oct_dev->app_mode && (oct_dev->app_mode == CVM_DRV_NIC_APP))
1355 liquidio_stop_nic_module(oct_dev);
1356
1357 /* Reset the octeon device and cleanup all memory allocated for
1358 * the octeon device by driver.
1359 */
1360 octeon_destroy_resources(oct_dev);
1361
1362 dev_info(&oct_dev->pci_dev->dev, "Device removed\n");
1363
1364 /* This octeon device has been removed. Update the global
1365 * data structure to reflect this. Free the device structure.
1366 */
1367 octeon_free_device_mem(oct_dev);
1368}
1369
1370/**
1371 * \brief Identify the Octeon device and to map the BAR address space
1372 * @param oct octeon device
1373 */
1374static int octeon_chip_specific_setup(struct octeon_device *oct)
1375{
1376 u32 dev_id, rev_id;
1377 int ret = 1;
d3d7e6c6 1378 char *s;
f21fb3ed
RV		 1379
1380 pci_read_config_dword(oct->pci_dev, 0, &dev_id);
1381 pci_read_config_dword(oct->pci_dev, 8, &rev_id);
1382 oct->rev_id = rev_id & 0xff;
1383
1384 switch (dev_id) {
1385 case OCTEON_CN68XX_PCIID:
1386 oct->chip_id = OCTEON_CN68XX;
1387 ret = lio_setup_cn68xx_octeon_device(oct);
d3d7e6c6 1388 s = "CN68XX";
f21fb3ed
RV		 1389 break;
1390
1391 case OCTEON_CN66XX_PCIID:
1392 oct->chip_id = OCTEON_CN66XX;
1393 ret = lio_setup_cn66xx_octeon_device(oct);
d3d7e6c6 1394 s = "CN66XX";
f21fb3ed 1395 break;
d3d7e6c6 1396
f21fb3ed 1397 default:
d3d7e6c6 1398 s = "?";
f21fb3ed
RV		 1399 dev_err(&oct->pci_dev->dev, "Unknown device found (dev_id: %x)\n",
1400 dev_id);
1401 }
1402
1403 if (!ret)
d3d7e6c6 1404 dev_info(&oct->pci_dev->dev, "%s PASS%d.%d %s Version: %s\n", s,
f21fb3ed
RV		 1405 OCTEON_MAJOR_REV(oct),
1406 OCTEON_MINOR_REV(oct),
d3d7e6c6
RV		 1407 octeon_get_conf(oct)->card_name,
1408 LIQUIDIO_VERSION);
f21fb3ed
RV		 1409
1410 return ret;
1411}
1412
1413/**
1414 * \brief PCI initialization for each Octeon device.
1415 * @param oct octeon device
1416 */
1417static int octeon_pci_os_setup(struct octeon_device *oct)
1418{
1419 /* setup PCI stuff first */
1420 if (pci_enable_device(oct->pci_dev)) {
1421 dev_err(&oct->pci_dev->dev, "pci_enable_device failed\n");
1422 return 1;
1423 }
1424
1425 if (dma_set_mask_and_coherent(&oct->pci_dev->dev, DMA_BIT_MASK(64))) {
1426 dev_err(&oct->pci_dev->dev, "Unexpected DMA device capability\n");
1427 return 1;
1428 }
1429
1430 /* Enable PCI DMA Master. */
1431 pci_set_master(oct->pci_dev);
1432
1433 return 0;
1434}
1435
fcd2b5e3
RV		 1436static inline int skb_iq(struct lio *lio, struct sk_buff *skb)
1437{
1438 int q = 0;
1439
1440 if (netif_is_multiqueue(lio->netdev))
1441 q = skb->queue_mapping % lio->linfo.num_txpciq;
1442
1443 return q;
1444}
1445
f21fb3ed
RV		 1446/**
1447 * \brief Check Tx queue state for a given network buffer
1448 * @param lio per-network private data
1449 * @param skb network buffer
1450 */
1451static inline int check_txq_state(struct lio *lio, struct sk_buff *skb)
1452{
1453 int q = 0, iq = 0;
1454
1455 if (netif_is_multiqueue(lio->netdev)) {
1456 q = skb->queue_mapping;
26236fa9 1457 iq = lio->linfo.txpciq[(q % (lio->linfo.num_txpciq))].s.q_no;
f21fb3ed
RV		 1458 } else {
1459 iq = lio->txq;
26236fa9 1460 q = iq;
f21fb3ed
RV		 1461 }
1462
1463 if (octnet_iq_is_full(lio->oct_dev, iq))
1464 return 0;
26236fa9
RV		 1465
1466 if (__netif_subqueue_stopped(lio->netdev, q))
1467 wake_q(lio->netdev, q);
f21fb3ed
RV		 1468 return 1;
1469}
1470
1471/**
1472 * \brief Unmap and free network buffer
1473 * @param buf buffer
1474 */
1475static void free_netbuf(void *buf)
1476{
1477 struct sk_buff *skb;
1478 struct octnet_buf_free_info *finfo;
1479 struct lio *lio;
1480
1481 finfo = (struct octnet_buf_free_info *)buf;
1482 skb = finfo->skb;
1483 lio = finfo->lio;
1484
1485 dma_unmap_single(&lio->oct_dev->pci_dev->dev, finfo->dptr, skb->len,
1486 DMA_TO_DEVICE);
1487
1488 check_txq_state(lio, skb);
1489
cabeb13b 1490 tx_buffer_free(skb);
f21fb3ed
RV		 1491}
1492
1493/**
1494 * \brief Unmap and free gather buffer
1495 * @param buf buffer
1496 */
1497static void free_netsgbuf(void *buf)
1498{
1499 struct octnet_buf_free_info *finfo;
1500 struct sk_buff *skb;
1501 struct lio *lio;
1502 struct octnic_gather *g;
fcd2b5e3 1503 int i, frags, iq;
f21fb3ed
RV		 1504
1505 finfo = (struct octnet_buf_free_info *)buf;
1506 skb = finfo->skb;
1507 lio = finfo->lio;
1508 g = finfo->g;
1509 frags = skb_shinfo(skb)->nr_frags;
1510
1511 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1512 g->sg[0].ptr[0], (skb->len - skb->data_len),
1513 DMA_TO_DEVICE);
1514
1515 i = 1;
1516 while (frags--) {
1517 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1518
1519 pci_unmap_page((lio->oct_dev)->pci_dev,
1520 g->sg[(i >> 2)].ptr[(i & 3)],
1521 frag->size, DMA_TO_DEVICE);
1522 i++;
1523 }
1524
fcd2b5e3
RV		 1525 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
1526 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
f21fb3ed 1527
fcd2b5e3
RV		 1528 iq = skb_iq(lio, skb);
1529 spin_lock(&lio->glist_lock[iq]);
1530 list_add_tail(&g->list, &lio->glist[iq]);
1531 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1532
1533 check_txq_state(lio, skb); /* mq support: sub-queue state check */
1534
cabeb13b 1535 tx_buffer_free(skb);
f21fb3ed
RV		 1536}
1537
1538/**
1539 * \brief Unmap and free gather buffer with response
1540 * @param buf buffer
1541 */
1542static void free_netsgbuf_with_resp(void *buf)
1543{
1544 struct octeon_soft_command *sc;
1545 struct octnet_buf_free_info *finfo;
1546 struct sk_buff *skb;
1547 struct lio *lio;
1548 struct octnic_gather *g;
fcd2b5e3 1549 int i, frags, iq;
f21fb3ed
RV		 1550
1551 sc = (struct octeon_soft_command *)buf;
1552 skb = (struct sk_buff *)sc->callback_arg;
1553 finfo = (struct octnet_buf_free_info *)&skb->cb;
1554
1555 lio = finfo->lio;
1556 g = finfo->g;
1557 frags = skb_shinfo(skb)->nr_frags;
1558
1559 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1560 g->sg[0].ptr[0], (skb->len - skb->data_len),
1561 DMA_TO_DEVICE);
1562
1563 i = 1;
1564 while (frags--) {
1565 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1566
1567 pci_unmap_page((lio->oct_dev)->pci_dev,
1568 g->sg[(i >> 2)].ptr[(i & 3)],
1569 frag->size, DMA_TO_DEVICE);
1570 i++;
1571 }
1572
fcd2b5e3
RV		 1573 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
1574 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
f21fb3ed 1575
fcd2b5e3
RV		 1576 iq = skb_iq(lio, skb);
1577
1578 spin_lock(&lio->glist_lock[iq]);
1579 list_add_tail(&g->list, &lio->glist[iq]);
1580 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1581
1582 /* Don't free the skb yet */
1583
1584 check_txq_state(lio, skb);
1585}
1586
1587/**
1588 * \brief Adjust ptp frequency
1589 * @param ptp PTP clock info
1590 * @param ppb how much to adjust by, in parts-per-billion
1591 */
1592static int liquidio_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
1593{
1594 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1595 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1596 u64 comp, delta;
1597 unsigned long flags;
1598 bool neg_adj = false;
1599
1600 if (ppb < 0) {
1601 neg_adj = true;
1602 ppb = -ppb;
1603 }
1604
1605 /* The hardware adds the clock compensation value to the
1606 * PTP clock on every coprocessor clock cycle, so we
1607 * compute the delta in terms of coprocessor clocks.
1608 */
1609 delta = (u64)ppb << 32;
1610 do_div(delta, oct->coproc_clock_rate);
1611
1612 spin_lock_irqsave(&lio->ptp_lock, flags);
1613 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP);
1614 if (neg_adj)
1615 comp -= delta;
1616 else
1617 comp += delta;
1618 lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP);
1619 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1620
1621 return 0;
1622}
1623
1624/**
1625 * \brief Adjust ptp time
1626 * @param ptp PTP clock info
1627 * @param delta how much to adjust by, in nanosecs
1628 */
1629static int liquidio_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
1630{
1631 unsigned long flags;
1632 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1633
1634 spin_lock_irqsave(&lio->ptp_lock, flags);
1635 lio->ptp_adjust += delta;
1636 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1637
1638 return 0;
1639}
1640
1641/**
1642 * \brief Get hardware clock time, including any adjustment
1643 * @param ptp PTP clock info
1644 * @param ts timespec
1645 */
1646static int liquidio_ptp_gettime(struct ptp_clock_info *ptp,
1647 struct timespec64 *ts)
1648{
1649 u64 ns;
f21fb3ed
RV		 1650 unsigned long flags;
1651 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1652 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1653
1654 spin_lock_irqsave(&lio->ptp_lock, flags);
1655 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI);
1656 ns += lio->ptp_adjust;
1657 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1658
286af315 1659 *ts = ns_to_timespec64(ns);
f21fb3ed
RV		 1660
1661 return 0;
1662}
1663
1664/**
1665 * \brief Set hardware clock time. Reset adjustment
1666 * @param ptp PTP clock info
1667 * @param ts timespec
1668 */
1669static int liquidio_ptp_settime(struct ptp_clock_info *ptp,
1670 const struct timespec64 *ts)
1671{
1672 u64 ns;
1673 unsigned long flags;
1674 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1675 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1676
1677 ns = timespec_to_ns(ts);
1678
1679 spin_lock_irqsave(&lio->ptp_lock, flags);
1680 lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI);
1681 lio->ptp_adjust = 0;
1682 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1683
1684 return 0;
1685}
1686
1687/**
1688 * \brief Check if PTP is enabled
1689 * @param ptp PTP clock info
1690 * @param rq request
1691 * @param on is it on
1692 */
1693static int liquidio_ptp_enable(struct ptp_clock_info *ptp,
1694 struct ptp_clock_request *rq, int on)
1695{
1696 return -EOPNOTSUPP;
1697}
1698
1699/**
1700 * \brief Open PTP clock source
1701 * @param netdev network device
1702 */
1703static void oct_ptp_open(struct net_device *netdev)
1704{
1705 struct lio *lio = GET_LIO(netdev);
1706 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1707
1708 spin_lock_init(&lio->ptp_lock);
1709
1710 snprintf(lio->ptp_info.name, 16, "%s", netdev->name);
1711 lio->ptp_info.owner = THIS_MODULE;
1712 lio->ptp_info.max_adj = 250000000;
1713 lio->ptp_info.n_alarm = 0;
1714 lio->ptp_info.n_ext_ts = 0;
1715 lio->ptp_info.n_per_out = 0;
1716 lio->ptp_info.pps = 0;
1717 lio->ptp_info.adjfreq = liquidio_ptp_adjfreq;
1718 lio->ptp_info.adjtime = liquidio_ptp_adjtime;
1719 lio->ptp_info.gettime64 = liquidio_ptp_gettime;
1720 lio->ptp_info.settime64 = liquidio_ptp_settime;
1721 lio->ptp_info.enable = liquidio_ptp_enable;
1722
1723 lio->ptp_adjust = 0;
1724
1725 lio->ptp_clock = ptp_clock_register(&lio->ptp_info,
1726 &oct->pci_dev->dev);
1727
1728 if (IS_ERR(lio->ptp_clock))
1729 lio->ptp_clock = NULL;
1730}
1731
1732/**
1733 * \brief Init PTP clock
1734 * @param oct octeon device
1735 */
1736static void liquidio_ptp_init(struct octeon_device *oct)
1737{
1738 u64 clock_comp, cfg;
1739
1740 clock_comp = (u64)NSEC_PER_SEC << 32;
1741 do_div(clock_comp, oct->coproc_clock_rate);
1742 lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP);
1743
1744 /* Enable */
1745 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG);
1746 lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG);
1747}
1748
1749/**
1750 * \brief Load firmware to device
1751 * @param oct octeon device
1752 *
1753 * Maps device to firmware filename, requests firmware, and downloads it
1754 */
1755static int load_firmware(struct octeon_device *oct)
1756{
1757 int ret = 0;
1758 const struct firmware *fw;
1759 char fw_name[LIO_MAX_FW_FILENAME_LEN];
1760 char *tmp_fw_type;
1761
1762 if (strncmp(fw_type, LIO_FW_NAME_TYPE_NONE,
1763 sizeof(LIO_FW_NAME_TYPE_NONE)) == 0) {
1764 dev_info(&oct->pci_dev->dev, "Skipping firmware load\n");
1765 return ret;
1766 }
1767
1768 if (fw_type[0] == '\0')
1769 tmp_fw_type = LIO_FW_NAME_TYPE_NIC;
1770 else
1771 tmp_fw_type = fw_type;
1772
1773 sprintf(fw_name, "%s%s%s_%s%s", LIO_FW_DIR, LIO_FW_BASE_NAME,
1774 octeon_get_conf(oct)->card_name, tmp_fw_type,
1775 LIO_FW_NAME_SUFFIX);
1776
1777 ret = request_firmware(&fw, fw_name, &oct->pci_dev->dev);
1778 if (ret) {
1779 dev_err(&oct->pci_dev->dev, "Request firmware failed. Could not find file %s.\n.",
1780 fw_name);
d3d7e6c6 1781 release_firmware(fw);
f21fb3ed
RV		 1782 return ret;
1783 }
1784
1785 ret = octeon_download_firmware(oct, fw->data, fw->size);
1786
1787 release_firmware(fw);
1788
1789 return ret;
1790}
1791
1792/**
1793 * \brief Setup output queue
1794 * @param oct octeon device
1795 * @param q_no which queue
1796 * @param num_descs how many descriptors
1797 * @param desc_size size of each descriptor
1798 * @param app_ctx application context
1799 */
1800static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs,
1801 int desc_size, void *app_ctx)
1802{
1803 int ret_val = 0;
1804
1805 dev_dbg(&oct->pci_dev->dev, "Creating Droq: %d\n", q_no);
1806 /* droq creation and local register settings. */
1807 ret_val = octeon_create_droq(oct, q_no, num_descs, desc_size, app_ctx);
08a965ec 1808 if (ret_val < 0)
f21fb3ed
RV		 1809 return ret_val;
1810
1811 if (ret_val == 1) {
1812 dev_dbg(&oct->pci_dev->dev, "Using default droq %d\n", q_no);
1813 return 0;
1814 }
1815 /* tasklet creation for the droq */
1816
1817 /* Enable the droq queues */
1818 octeon_set_droq_pkt_op(oct, q_no, 1);
1819
1820 /* Send Credit for Octeon Output queues. Credits are always
1821 * sent after the output queue is enabled.
1822 */
1823 writel(oct->droq[q_no]->max_count,
1824 oct->droq[q_no]->pkts_credit_reg);
1825
1826 return ret_val;
1827}
1828
1829/**
1830 * \brief Callback for getting interface configuration
1831 * @param status status of request
1832 * @param buf pointer to resp structure
1833 */
1834static void if_cfg_callback(struct octeon_device *oct,
1835 u32 status,
1836 void *buf)
1837{
1838 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
1839 struct liquidio_if_cfg_resp *resp;
1840 struct liquidio_if_cfg_context *ctx;
1841
1842 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
1843 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
1844
1845 oct = lio_get_device(ctx->octeon_id);
1846 if (resp->status)
1847 dev_err(&oct->pci_dev->dev, "nic if cfg instruction failed. Status: %llx\n",
1848 CVM_CAST64(resp->status));
1849 ACCESS_ONCE(ctx->cond) = 1;
1850
d3d7e6c6
RV		 1851 snprintf(oct->fw_info.liquidio_firmware_version, 32, "%s",
1852 resp->cfg_info.liquidio_firmware_version);
1853
f21fb3ed
RV		 1854 /* This barrier is required to be sure that the response has been
1855 * written fully before waking up the handler
1856 */
1857 wmb();
1858
1859 wake_up_interruptible(&ctx->wc);
1860}
1861
1862/**
1863 * \brief Select queue based on hash
1864 * @param dev Net device
1865 * @param skb sk_buff structure
1866 * @returns selected queue number
1867 */
1868static u16 select_q(struct net_device *dev, struct sk_buff *skb,
1869 void *accel_priv, select_queue_fallback_t fallback)
1870{
26236fa9 1871 u32 qindex = 0;
f21fb3ed
RV		 1872 struct lio *lio;
1873
1874 lio = GET_LIO(dev);
26236fa9
RV		 1875 qindex = skb_tx_hash(dev, skb);
1876
1877 return (u16)(qindex % (lio->linfo.num_txpciq));
f21fb3ed
RV		 1878}
1879
1880/** Routine to push packets arriving on Octeon interface upto network layer.
1881 * @param oct_id - octeon device id.
1882 * @param skbuff - skbuff struct to be passed to network layer.
1883 * @param len - size of total data received.
1884 * @param rh - Control header associated with the packet
1885 * @param param - additional control data with the packet
0cece6c5 1886 * @param arg - farg registered in droq_ops
f21fb3ed
RV		 1887 */
1888static void
1889liquidio_push_packet(u32 octeon_id,
1890 void *skbuff,
1891 u32 len,
1892 union octeon_rh *rh,
0cece6c5
RV		 1893 void *param,
1894 void *arg)
f21fb3ed
RV		 1895{
1896 struct napi_struct *napi = param;
f21fb3ed
RV		 1897 struct sk_buff *skb = (struct sk_buff *)skbuff;
1898 struct skb_shared_hwtstamps *shhwtstamps;
1899 u64 ns;
0da0b77c 1900 u16 vtag = 0;
0cece6c5 1901 struct net_device *netdev = (struct net_device *)arg;
f21fb3ed
RV		 1902 struct octeon_droq *droq = container_of(param, struct octeon_droq,
1903 napi);
1904 if (netdev) {
1905 int packet_was_received;
1906 struct lio *lio = GET_LIO(netdev);
a5b37888 1907 struct octeon_device *oct = lio->oct_dev;
f21fb3ed
RV		 1908
1909 /* Do not proceed if the interface is not in RUNNING state. */
1910 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) {
1911 recv_buffer_free(skb);
1912 droq->stats.rx_dropped++;
1913 return;
1914 }
1915
1916 skb->dev = netdev;
1917
26236fa9 1918 skb_record_rx_queue(skb, droq->q_no);
cabeb13b
RV		 1919 if (likely(len > MIN_SKB_SIZE)) {
1920 struct octeon_skb_page_info *pg_info;
1921 unsigned char *va;
1922
1923 pg_info = ((struct octeon_skb_page_info *)(skb->cb));
1924 if (pg_info->page) {
1925 /* For Paged allocation use the frags */
1926 va = page_address(pg_info->page) +
1927 pg_info->page_offset;
1928 memcpy(skb->data, va, MIN_SKB_SIZE);
1929 skb_put(skb, MIN_SKB_SIZE);
1930 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1931 pg_info->page,
1932 pg_info->page_offset +
1933 MIN_SKB_SIZE,
1934 len - MIN_SKB_SIZE,
1935 LIO_RXBUFFER_SZ);
1936 }
1937 } else {
1938 struct octeon_skb_page_info *pg_info =
1939 ((struct octeon_skb_page_info *)(skb->cb));
1940 skb_copy_to_linear_data(skb, page_address(pg_info->page)
1941 + pg_info->page_offset, len);
1942 skb_put(skb, len);
1943 put_page(pg_info->page);
1944 }
26236fa9 1945
a5b37888
RV		 1946 if (((oct->chip_id == OCTEON_CN66XX) ||
1947 (oct->chip_id == OCTEON_CN68XX)) &&
1948 ptp_enable) {
1949 if (rh->r_dh.has_hwtstamp) {
1950 /* timestamp is included from the hardware at
1951 * the beginning of the packet.
f21fb3ed 1952 */
a5b37888
RV		 1953 if (ifstate_check
1954 (lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED)) {
1955 /* Nanoseconds are in the first 64-bits
1956 * of the packet.
1957 */
1958 memcpy(&ns, (skb->data), sizeof(ns));
1959 shhwtstamps = skb_hwtstamps(skb);
1960 shhwtstamps->hwtstamp =
1961 ns_to_ktime(ns +
1962 lio->ptp_adjust);
1963 }
1964 skb_pull(skb, sizeof(ns));
f21fb3ed 1965 }
f21fb3ed
RV		 1966 }
1967
1968 skb->protocol = eth_type_trans(skb, skb->dev);
1969
1970 if ((netdev->features & NETIF_F_RXCSUM) &&
1971 (rh->r_dh.csum_verified == CNNIC_CSUM_VERIFIED))
1972 /* checksum has already been verified */
1973 skb->ip_summed = CHECKSUM_UNNECESSARY;
1974 else
1975 skb->ip_summed = CHECKSUM_NONE;
1976
0da0b77c
RV		 1977 /* inbound VLAN tag */
1978 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1979 (rh->r_dh.vlan != 0)) {
1980 u16 vid = rh->r_dh.vlan;
1981 u16 priority = rh->r_dh.priority;
1982
1983 vtag = priority << 13 | vid;
1984 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
1985 }
1986
f21fb3ed
RV		 1987 packet_was_received = napi_gro_receive(napi, skb) != GRO_DROP;
1988
1989 if (packet_was_received) {
1990 droq->stats.rx_bytes_received += len;
1991 droq->stats.rx_pkts_received++;
1992 netdev->last_rx = jiffies;
1993 } else {
1994 droq->stats.rx_dropped++;
1995 netif_info(lio, rx_err, lio->netdev,
1996 "droq:%d error rx_dropped:%llu\n",
1997 droq->q_no, droq->stats.rx_dropped);
1998 }
1999
2000 } else {
2001 recv_buffer_free(skb);
2002 }
2003}
2004
2005/**
2006 * \brief wrapper for calling napi_schedule
2007 * @param param parameters to pass to napi_schedule
2008 *
2009 * Used when scheduling on different CPUs
2010 */
2011static void napi_schedule_wrapper(void *param)
2012{
2013 struct napi_struct *napi = param;
2014
2015 napi_schedule(napi);
2016}
2017
2018/**
2019 * \brief callback when receive interrupt occurs and we are in NAPI mode
2020 * @param arg pointer to octeon output queue
2021 */
2022static void liquidio_napi_drv_callback(void *arg)
2023{
2024 struct octeon_droq *droq = arg;
2025 int this_cpu = smp_processor_id();
2026
2027 if (droq->cpu_id == this_cpu) {
2028 napi_schedule(&droq->napi);
2029 } else {
2030 struct call_single_data *csd = &droq->csd;
2031
2032 csd->func = napi_schedule_wrapper;
2033 csd->info = &droq->napi;
2034 csd->flags = 0;
2035
2036 smp_call_function_single_async(droq->cpu_id, csd);
2037 }
2038}
2039
f21fb3ed
RV		 2040/**
2041 * \brief Entry point for NAPI polling
2042 * @param napi NAPI structure
2043 * @param budget maximum number of items to process
2044 */
2045static int liquidio_napi_poll(struct napi_struct *napi, int budget)
2046{
2047 struct octeon_droq *droq;
2048 int work_done;
9a96bde4
RV		 2049 int tx_done = 0, iq_no;
2050 struct octeon_instr_queue *iq;
2051 struct octeon_device *oct;
f21fb3ed
RV		 2052
2053 droq = container_of(napi, struct octeon_droq, napi);
9a96bde4
RV		 2054 oct = droq->oct_dev;
2055 iq_no = droq->q_no;
2056 /* Handle Droq descriptors */
2057 work_done = octeon_process_droq_poll_cmd(oct, droq->q_no,
2058 POLL_EVENT_PROCESS_PKTS,
2059 budget);
f21fb3ed 2060
9a96bde4
RV		 2061 /* Flush the instruction queue */
2062 iq = oct->instr_queue[iq_no];
2063 if (iq) {
2064 /* Process iq buffers with in the budget limits */
2065 tx_done = octeon_flush_iq(oct, iq, 1, budget);
2066 /* Update iq read-index rather than waiting for next interrupt.
2067 * Return back if tx_done is false.
2068 */
2069 update_txq_status(oct, iq_no);
2070 /*tx_done = (iq->flush_index == iq->octeon_read_index);*/
2071 } else {
2072 dev_err(&oct->pci_dev->dev, "%s: iq (%d) num invalid\n",
2073 __func__, iq_no);
2074 }
f21fb3ed 2075
9a96bde4 2076 if ((work_done < budget) && (tx_done)) {
f21fb3ed
RV		 2077 napi_complete(napi);
2078 octeon_process_droq_poll_cmd(droq->oct_dev, droq->q_no,
2079 POLL_EVENT_ENABLE_INTR, 0);
2080 return 0;
2081 }
2082
9a96bde4 2083 return (!tx_done) ? (budget) : (work_done);
f21fb3ed
RV		 2084}
2085
2086/**
2087 * \brief Setup input and output queues
2088 * @param octeon_dev octeon device
2089 * @param net_device Net device
2090 *
2091 * Note: Queues are with respect to the octeon device. Thus
2092 * an input queue is for egress packets, and output queues
2093 * are for ingress packets.
2094 */
2095static inline int setup_io_queues(struct octeon_device *octeon_dev,
0cece6c5 2096 int ifidx)
f21fb3ed 2097{
0cece6c5
RV		 2098 struct octeon_droq_ops droq_ops;
2099 struct net_device *netdev;
f21fb3ed
RV		 2100 static int cpu_id;
2101 static int cpu_id_modulus;
2102 struct octeon_droq *droq;
2103 struct napi_struct *napi;
2104 int q, q_no, retval = 0;
2105 struct lio *lio;
2106 int num_tx_descs;
2107
0cece6c5
RV		 2108 netdev = octeon_dev->props[ifidx].netdev;
2109
2110 lio = GET_LIO(netdev);
f21fb3ed 2111
0cece6c5 2112 memset(&droq_ops, 0, sizeof(struct octeon_droq_ops));
f21fb3ed 2113
0cece6c5
RV		 2114 droq_ops.fptr = liquidio_push_packet;
2115 droq_ops.farg = (void *)netdev;
2116
2117 droq_ops.poll_mode = 1;
2118 droq_ops.napi_fn = liquidio_napi_drv_callback;
2119 cpu_id = 0;
2120 cpu_id_modulus = num_present_cpus();
f21fb3ed
RV		 2121
2122 /* set up DROQs. */
2123 for (q = 0; q < lio->linfo.num_rxpciq; q++) {
26236fa9
RV		 2124 q_no = lio->linfo.rxpciq[q].s.q_no;
2125 dev_dbg(&octeon_dev->pci_dev->dev,
2126 "setup_io_queues index:%d linfo.rxpciq.s.q_no:%d\n",
2127 q, q_no);
f21fb3ed
RV		 2128 retval = octeon_setup_droq(octeon_dev, q_no,
2129 CFG_GET_NUM_RX_DESCS_NIC_IF
2130 (octeon_get_conf(octeon_dev),
2131 lio->ifidx),
2132 CFG_GET_NUM_RX_BUF_SIZE_NIC_IF
2133 (octeon_get_conf(octeon_dev),
2134 lio->ifidx), NULL);
2135 if (retval) {
2136 dev_err(&octeon_dev->pci_dev->dev,
2137 " %s : Runtime DROQ(RxQ) creation failed.\n",
2138 __func__);
2139 return 1;
2140 }
2141
2142 droq = octeon_dev->droq[q_no];
2143 napi = &droq->napi;
0cece6c5
RV		 2144 dev_dbg(&octeon_dev->pci_dev->dev,
2145 "netif_napi_add netdev:%llx oct:%llx\n",
2146 (u64)netdev,
2147 (u64)octeon_dev);
2148 netif_napi_add(netdev, napi, liquidio_napi_poll, 64);
f21fb3ed
RV		 2149
2150 /* designate a CPU for this droq */
2151 droq->cpu_id = cpu_id;
2152 cpu_id++;
2153 if (cpu_id >= cpu_id_modulus)
2154 cpu_id = 0;
2155
2156 octeon_register_droq_ops(octeon_dev, q_no, &droq_ops);
2157 }
2158
2159 /* set up IQs. */
2160 for (q = 0; q < lio->linfo.num_txpciq; q++) {
2161 num_tx_descs = CFG_GET_NUM_TX_DESCS_NIC_IF(octeon_get_conf
2162 (octeon_dev),
2163 lio->ifidx);
0cece6c5
RV		 2164 retval = octeon_setup_iq(octeon_dev, ifidx, q,
2165 lio->linfo.txpciq[q], num_tx_descs,
2166 netdev_get_tx_queue(netdev, q));
f21fb3ed
RV		 2167 if (retval) {
2168 dev_err(&octeon_dev->pci_dev->dev,
2169 " %s : Runtime IQ(TxQ) creation failed.\n",
2170 __func__);
2171 return 1;
2172 }
2173 }
2174
2175 return 0;
2176}
2177
2178/**
2179 * \brief Poll routine for checking transmit queue status
2180 * @param work work_struct data structure
2181 */
2182static void octnet_poll_check_txq_status(struct work_struct *work)
2183{
2184 struct cavium_wk *wk = (struct cavium_wk *)work;
2185 struct lio *lio = (struct lio *)wk->ctxptr;
2186
2187 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING))
2188 return;
2189
2190 check_txq_status(lio);
2191 queue_delayed_work(lio->txq_status_wq.wq,
2192 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2193}
2194
2195/**
2196 * \brief Sets up the txq poll check
2197 * @param netdev network device
2198 */
2199static inline void setup_tx_poll_fn(struct net_device *netdev)
2200{
2201 struct lio *lio = GET_LIO(netdev);
2202 struct octeon_device *oct = lio->oct_dev;
2203
292b9dab
BS		 2204 lio->txq_status_wq.wq = alloc_workqueue("txq-status",
2205 WQ_MEM_RECLAIM, 0);
f21fb3ed
RV		 2206 if (!lio->txq_status_wq.wq) {
2207 dev_err(&oct->pci_dev->dev, "unable to create cavium txq status wq\n");
2208 return;
2209 }
2210 INIT_DELAYED_WORK(&lio->txq_status_wq.wk.work,
2211 octnet_poll_check_txq_status);
2212 lio->txq_status_wq.wk.ctxptr = lio;
2213 queue_delayed_work(lio->txq_status_wq.wq,
2214 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2215}
2216
9a96bde4
RV		 2217static inline void cleanup_tx_poll_fn(struct net_device *netdev)
2218{
2219 struct lio *lio = GET_LIO(netdev);
2220
2221 cancel_delayed_work_sync(&lio->txq_status_wq.wk.work);
2222 destroy_workqueue(lio->txq_status_wq.wq);
2223}
2224
f21fb3ed
RV		 2225/**
2226 * \brief Net device open for LiquidIO
2227 * @param netdev network device
2228 */
2229static int liquidio_open(struct net_device *netdev)
2230{
2231 struct lio *lio = GET_LIO(netdev);
2232 struct octeon_device *oct = lio->oct_dev;
2233 struct napi_struct *napi, *n;
2234
9a96bde4
RV		 2235 if (oct->props[lio->ifidx].napi_enabled == 0) {
2236 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
2237 napi_enable(napi);
2238
2239 oct->props[lio->ifidx].napi_enabled = 1;
2240 }
f21fb3ed
RV		 2241
2242 oct_ptp_open(netdev);
2243
2244 ifstate_set(lio, LIO_IFSTATE_RUNNING);
9a96bde4 2245
f21fb3ed 2246 setup_tx_poll_fn(netdev);
9a96bde4 2247
f21fb3ed
RV		 2248 start_txq(netdev);
2249
2250 netif_info(lio, ifup, lio->netdev, "Interface Open, ready for traffic\n");
f21fb3ed
RV		 2251
2252 /* tell Octeon to start forwarding packets to host */
2253 send_rx_ctrl_cmd(lio, 1);
2254
2255 /* Ready for link status updates */
2256 lio->intf_open = 1;
2257
2258 dev_info(&oct->pci_dev->dev, "%s interface is opened\n",
2259 netdev->name);
2260
2261 return 0;
2262}
2263
2264/**
2265 * \brief Net device stop for LiquidIO
2266 * @param netdev network device
2267 */
2268static int liquidio_stop(struct net_device *netdev)
2269{
f21fb3ed
RV		 2270 struct lio *lio = GET_LIO(netdev);
2271 struct octeon_device *oct = lio->oct_dev;
2272
9a96bde4
RV		 2273 ifstate_reset(lio, LIO_IFSTATE_RUNNING);
2274
2275 netif_tx_disable(netdev);
2276
f21fb3ed 2277 /* Inform that netif carrier is down */
9a96bde4 2278 netif_carrier_off(netdev);
f21fb3ed 2279 lio->intf_open = 0;
0cece6c5
RV		 2280 lio->linfo.link.s.link_up = 0;
2281 lio->link_changes++;
f21fb3ed 2282
9a96bde4
RV		 2283 /* Pause for a moment and wait for Octeon to flush out (to the wire) any
2284 * egress packets that are in-flight.
2285 */
2286 set_current_state(TASK_INTERRUPTIBLE);
2287 schedule_timeout(msecs_to_jiffies(100));
f21fb3ed 2288
9a96bde4 2289 /* Now it should be safe to tell Octeon that nic interface is down. */
f21fb3ed
RV		 2290 send_rx_ctrl_cmd(lio, 0);
2291
9a96bde4 2292 cleanup_tx_poll_fn(netdev);
f21fb3ed
RV		 2293
2294 if (lio->ptp_clock) {
2295 ptp_clock_unregister(lio->ptp_clock);
2296 lio->ptp_clock = NULL;
2297 }
2298
f21fb3ed
RV		 2299 dev_info(&oct->pci_dev->dev, "%s interface is stopped\n", netdev->name);
2300 module_put(THIS_MODULE);
2301
2302 return 0;
2303}
2304
2305void liquidio_link_ctrl_cmd_completion(void *nctrl_ptr)
2306{
2307 struct octnic_ctrl_pkt *nctrl = (struct octnic_ctrl_pkt *)nctrl_ptr;
2308 struct net_device *netdev = (struct net_device *)nctrl->netpndev;
2309 struct lio *lio = GET_LIO(netdev);
2310 struct octeon_device *oct = lio->oct_dev;
2311
2312 switch (nctrl->ncmd.s.cmd) {
2313 case OCTNET_CMD_CHANGE_DEVFLAGS:
2314 case OCTNET_CMD_SET_MULTI_LIST:
2315 break;
2316
2317 case OCTNET_CMD_CHANGE_MACADDR:
2318 /* If command is successful, change the MACADDR. */
2319 netif_info(lio, probe, lio->netdev, " MACAddr changed to 0x%llx\n",
2320 CVM_CAST64(nctrl->udd[0]));
2321 dev_info(&oct->pci_dev->dev, "%s MACAddr changed to 0x%llx\n",
2322 netdev->name, CVM_CAST64(nctrl->udd[0]));
2323 memcpy(netdev->dev_addr, ((u8 *)&nctrl->udd[0]) + 2, ETH_ALEN);
2324 break;
2325
2326 case OCTNET_CMD_CHANGE_MTU:
2327 /* If command is successful, change the MTU. */
2328 netif_info(lio, probe, lio->netdev, " MTU Changed from %d to %d\n",
2329 netdev->mtu, nctrl->ncmd.s.param2);
2330 dev_info(&oct->pci_dev->dev, "%s MTU Changed from %d to %d\n",
2331 netdev->name, netdev->mtu,
2332 nctrl->ncmd.s.param2);
2333 netdev->mtu = nctrl->ncmd.s.param2;
2334 break;
2335
2336 case OCTNET_CMD_GPIO_ACCESS:
2337 netif_info(lio, probe, lio->netdev, "LED Flashing visual identification\n");
2338
2339 break;
2340
2341 case OCTNET_CMD_LRO_ENABLE:
2342 dev_info(&oct->pci_dev->dev, "%s LRO Enabled\n", netdev->name);
2343 break;
2344
2345 case OCTNET_CMD_LRO_DISABLE:
2346 dev_info(&oct->pci_dev->dev, "%s LRO Disabled\n",
2347 netdev->name);
2348 break;
2349
2350 case OCTNET_CMD_VERBOSE_ENABLE:
2351 dev_info(&oct->pci_dev->dev, "%s LRO Enabled\n", netdev->name);
2352 break;
2353
2354 case OCTNET_CMD_VERBOSE_DISABLE:
2355 dev_info(&oct->pci_dev->dev, "%s LRO Disabled\n",
2356 netdev->name);
2357 break;
2358
63245f25
RV		 2359 case OCTNET_CMD_ENABLE_VLAN_FILTER:
2360 dev_info(&oct->pci_dev->dev, "%s VLAN filter enabled\n",
2361 netdev->name);
2362 break;
2363
2364 case OCTNET_CMD_ADD_VLAN_FILTER:
2365 dev_info(&oct->pci_dev->dev, "%s VLAN filter %d added\n",
2366 netdev->name, nctrl->ncmd.s.param1);
2367 break;
2368
2369 case OCTNET_CMD_DEL_VLAN_FILTER:
2370 dev_info(&oct->pci_dev->dev, "%s VLAN filter %d removed\n",
2371 netdev->name, nctrl->ncmd.s.param1);
2372 break;
2373
f21fb3ed
RV		 2374 case OCTNET_CMD_SET_SETTINGS:
2375 dev_info(&oct->pci_dev->dev, "%s settings changed\n",
2376 netdev->name);
2377
2378 break;
2379
2380 default:
2381 dev_err(&oct->pci_dev->dev, "%s Unknown cmd %d\n", __func__,
2382 nctrl->ncmd.s.cmd);
2383 }
2384}
2385
2386/**
2387 * \brief Converts a mask based on net device flags
2388 * @param netdev network device
2389 *
2390 * This routine generates a octnet_ifflags mask from the net device flags
2391 * received from the OS.
2392 */
2393static inline enum octnet_ifflags get_new_flags(struct net_device *netdev)
2394{
2395 enum octnet_ifflags f = OCTNET_IFFLAG_UNICAST;
2396
2397 if (netdev->flags & IFF_PROMISC)
2398 f |= OCTNET_IFFLAG_PROMISC;
2399
2400 if (netdev->flags & IFF_ALLMULTI)
2401 f |= OCTNET_IFFLAG_ALLMULTI;
2402
2403 if (netdev->flags & IFF_MULTICAST) {
2404 f |= OCTNET_IFFLAG_MULTICAST;
2405
2406 /* Accept all multicast addresses if there are more than we
2407 * can handle
2408 */
2409 if (netdev_mc_count(netdev) > MAX_OCTEON_MULTICAST_ADDR)
2410 f |= OCTNET_IFFLAG_ALLMULTI;
2411 }
2412
2413 if (netdev->flags & IFF_BROADCAST)
2414 f |= OCTNET_IFFLAG_BROADCAST;
2415
2416 return f;
2417}
2418
2419/**
2420 * \brief Net device set_multicast_list
2421 * @param netdev network device
2422 */
2423static void liquidio_set_mcast_list(struct net_device *netdev)
2424{
2425 struct lio *lio = GET_LIO(netdev);
2426 struct octeon_device *oct = lio->oct_dev;
2427 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2428 struct netdev_hw_addr *ha;
2429 u64 *mc;
2430 int ret, i;
2431 int mc_count = min(netdev_mc_count(netdev), MAX_OCTEON_MULTICAST_ADDR);
2432
2433 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2434
2435 /* Create a ctrl pkt command to be sent to core app. */
2436 nctrl.ncmd.u64 = 0;
2437 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_MULTI_LIST;
0cece6c5
RV		 2438 nctrl.ncmd.s.param1 = get_new_flags(netdev);
2439 nctrl.ncmd.s.param2 = mc_count;
f21fb3ed 2440 nctrl.ncmd.s.more = mc_count;
0cece6c5 2441 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2442 nctrl.netpndev = (u64)netdev;
2443 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2444
2445 /* copy all the addresses into the udd */
2446 i = 0;
2447 mc = &nctrl.udd[0];
2448 netdev_for_each_mc_addr(ha, netdev) {
2449 *mc = 0;
2450 memcpy(((u8 *)mc) + 2, ha->addr, ETH_ALEN);
2451 /* no need to swap bytes */
2452
2453 if (++mc > &nctrl.udd[mc_count])
2454 break;
2455 }
2456
2457 /* Apparently, any activity in this call from the kernel has to
2458 * be atomic. So we won't wait for response.
2459 */
2460 nctrl.wait_time = 0;
2461
0cece6c5 2462 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2463 if (ret < 0) {
2464 dev_err(&oct->pci_dev->dev, "DEVFLAGS change failed in core (ret: 0x%x)\n",
2465 ret);
2466 }
2467}
2468
2469/**
2470 * \brief Net device set_mac_address
2471 * @param netdev network device
2472 */
2473static int liquidio_set_mac(struct net_device *netdev, void *p)
2474{
2475 int ret = 0;
2476 struct lio *lio = GET_LIO(netdev);
2477 struct octeon_device *oct = lio->oct_dev;
2478 struct sockaddr *addr = (struct sockaddr *)p;
2479 struct octnic_ctrl_pkt nctrl;
f21fb3ed 2480
0cece6c5 2481 if (!is_valid_ether_addr(addr->sa_data))
f21fb3ed
RV		 2482 return -EADDRNOTAVAIL;
2483
2484 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2485
2486 nctrl.ncmd.u64 = 0;
2487 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
0cece6c5 2488 nctrl.ncmd.s.param1 = 0;
f21fb3ed 2489 nctrl.ncmd.s.more = 1;
0cece6c5 2490 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2491 nctrl.netpndev = (u64)netdev;
2492 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2493 nctrl.wait_time = 100;
2494
2495 nctrl.udd[0] = 0;
2496 /* The MAC Address is presented in network byte order. */
2497 memcpy((u8 *)&nctrl.udd[0] + 2, addr->sa_data, ETH_ALEN);
2498
0cece6c5 2499 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2500 if (ret < 0) {
2501 dev_err(&oct->pci_dev->dev, "MAC Address change failed\n");
2502 return -ENOMEM;
2503 }
2504 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2505 memcpy(((u8 *)&lio->linfo.hw_addr) + 2, addr->sa_data, ETH_ALEN);
2506
2507 return 0;
2508}
2509
2510/**
2511 * \brief Net device get_stats
2512 * @param netdev network device
2513 */
2514static struct net_device_stats *liquidio_get_stats(struct net_device *netdev)
2515{
2516 struct lio *lio = GET_LIO(netdev);
2517 struct net_device_stats *stats = &netdev->stats;
2518 struct octeon_device *oct;
2519 u64 pkts = 0, drop = 0, bytes = 0;
2520 struct oct_droq_stats *oq_stats;
2521 struct oct_iq_stats *iq_stats;
2522 int i, iq_no, oq_no;
2523
2524 oct = lio->oct_dev;
2525
2526 for (i = 0; i < lio->linfo.num_txpciq; i++) {
26236fa9 2527 iq_no = lio->linfo.txpciq[i].s.q_no;
f21fb3ed
RV		 2528 iq_stats = &oct->instr_queue[iq_no]->stats;
2529 pkts += iq_stats->tx_done;
2530 drop += iq_stats->tx_dropped;
2531 bytes += iq_stats->tx_tot_bytes;
2532 }
2533
2534 stats->tx_packets = pkts;
2535 stats->tx_bytes = bytes;
2536 stats->tx_dropped = drop;
2537
2538 pkts = 0;
2539 drop = 0;
2540 bytes = 0;
2541
2542 for (i = 0; i < lio->linfo.num_rxpciq; i++) {
26236fa9 2543 oq_no = lio->linfo.rxpciq[i].s.q_no;
f21fb3ed
RV		 2544 oq_stats = &oct->droq[oq_no]->stats;
2545 pkts += oq_stats->rx_pkts_received;
2546 drop += (oq_stats->rx_dropped +
2547 oq_stats->dropped_nodispatch +
2548 oq_stats->dropped_toomany +
2549 oq_stats->dropped_nomem);
2550 bytes += oq_stats->rx_bytes_received;
2551 }
2552
2553 stats->rx_bytes = bytes;
2554 stats->rx_packets = pkts;
2555 stats->rx_dropped = drop;
2556
2557 return stats;
2558}
2559
2560/**
2561 * \brief Net device change_mtu
2562 * @param netdev network device
2563 */
2564static int liquidio_change_mtu(struct net_device *netdev, int new_mtu)
2565{
2566 struct lio *lio = GET_LIO(netdev);
2567 struct octeon_device *oct = lio->oct_dev;
2568 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2569 int max_frm_size = new_mtu + OCTNET_FRM_HEADER_SIZE;
2570 int ret = 0;
2571
2572 /* Limit the MTU to make sure the ethernet packets are between 64 bytes
2573 * and 65535 bytes
2574 */
2575 if ((max_frm_size < OCTNET_MIN_FRM_SIZE) ||
2576 (max_frm_size > OCTNET_MAX_FRM_SIZE)) {
2577 dev_err(&oct->pci_dev->dev, "Invalid MTU: %d\n", new_mtu);
2578 dev_err(&oct->pci_dev->dev, "Valid range %d and %d\n",
2579 (OCTNET_MIN_FRM_SIZE - OCTNET_FRM_HEADER_SIZE),
2580 (OCTNET_MAX_FRM_SIZE - OCTNET_FRM_HEADER_SIZE));
2581 return -EINVAL;
2582 }
2583
2584 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2585
2586 nctrl.ncmd.u64 = 0;
2587 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MTU;
0cece6c5
RV		 2588 nctrl.ncmd.s.param1 = new_mtu;
2589 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2590 nctrl.wait_time = 100;
2591 nctrl.netpndev = (u64)netdev;
2592 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2593
0cece6c5 2594 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2595 if (ret < 0) {
2596 dev_err(&oct->pci_dev->dev, "Failed to set MTU\n");
2597 return -1;
2598 }
2599
2600 lio->mtu = new_mtu;
2601
2602 return 0;
2603}
2604
2605/**
2606 * \brief Handler for SIOCSHWTSTAMP ioctl
2607 * @param netdev network device
2608 * @param ifr interface request
2609 * @param cmd command
2610 */
2611static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2612{
2613 struct hwtstamp_config conf;
2614 struct lio *lio = GET_LIO(netdev);
2615
2616 if (copy_from_user(&conf, ifr->ifr_data, sizeof(conf)))
2617 return -EFAULT;
2618
2619 if (conf.flags)
2620 return -EINVAL;
2621
2622 switch (conf.tx_type) {
2623 case HWTSTAMP_TX_ON:
2624 case HWTSTAMP_TX_OFF:
2625 break;
2626 default:
2627 return -ERANGE;
2628 }
2629
2630 switch (conf.rx_filter) {
2631 case HWTSTAMP_FILTER_NONE:
2632 break;
2633 case HWTSTAMP_FILTER_ALL:
2634 case HWTSTAMP_FILTER_SOME:
2635 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2636 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2637 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2638 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2639 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2640 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2641 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2642 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2643 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2644 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2645 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2646 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2647 conf.rx_filter = HWTSTAMP_FILTER_ALL;
2648 break;
2649 default:
2650 return -ERANGE;
2651 }
2652
2653 if (conf.rx_filter == HWTSTAMP_FILTER_ALL)
2654 ifstate_set(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
2655
2656 else
2657 ifstate_reset(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
2658
2659 return copy_to_user(ifr->ifr_data, &conf, sizeof(conf)) ? -EFAULT : 0;
2660}
2661
2662/**
2663 * \brief ioctl handler
2664 * @param netdev network device
2665 * @param ifr interface request
2666 * @param cmd command
2667 */
2668static int liquidio_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2669{
2670 switch (cmd) {
2671 case SIOCSHWTSTAMP:
2672 return hwtstamp_ioctl(netdev, ifr, cmd);
2673 default:
2674 return -EOPNOTSUPP;
2675 }
2676}
2677
2678/**
2679 * \brief handle a Tx timestamp response
2680 * @param status response status
2681 * @param buf pointer to skb
2682 */
2683static void handle_timestamp(struct octeon_device *oct,
2684 u32 status,
2685 void *buf)
2686{
2687 struct octnet_buf_free_info *finfo;
2688 struct octeon_soft_command *sc;
2689 struct oct_timestamp_resp *resp;
2690 struct lio *lio;
2691 struct sk_buff *skb = (struct sk_buff *)buf;
2692
2693 finfo = (struct octnet_buf_free_info *)skb->cb;
2694 lio = finfo->lio;
2695 sc = finfo->sc;
2696 oct = lio->oct_dev;
2697 resp = (struct oct_timestamp_resp *)sc->virtrptr;
2698
2699 if (status != OCTEON_REQUEST_DONE) {
2700 dev_err(&oct->pci_dev->dev, "Tx timestamp instruction failed. Status: %llx\n",
2701 CVM_CAST64(status));
2702 resp->timestamp = 0;
2703 }
2704
2705 octeon_swap_8B_data(&resp->timestamp, 1);
2706
19a6d156 2707 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) != 0)) {
f21fb3ed
RV		 2708 struct skb_shared_hwtstamps ts;
2709 u64 ns = resp->timestamp;
2710
2711 netif_info(lio, tx_done, lio->netdev,
2712 "Got resulting SKBTX_HW_TSTAMP skb=%p ns=%016llu\n",
2713 skb, (unsigned long long)ns);
2714 ts.hwtstamp = ns_to_ktime(ns + lio->ptp_adjust);
2715 skb_tstamp_tx(skb, &ts);
2716 }
2717
2718 octeon_free_soft_command(oct, sc);
cabeb13b 2719 tx_buffer_free(skb);
f21fb3ed
RV		 2720}
2721
2722/* \brief Send a data packet that will be timestamped
2723 * @param oct octeon device
2724 * @param ndata pointer to network data
2725 * @param finfo pointer to private network data
2726 */
2727static inline int send_nic_timestamp_pkt(struct octeon_device *oct,
2728 struct octnic_data_pkt *ndata,
2729 struct octnet_buf_free_info *finfo,
2730 int xmit_more)
2731{
2732 int retval;
2733 struct octeon_soft_command *sc;
f21fb3ed
RV		 2734 struct lio *lio;
2735 int ring_doorbell;
6a885b60 2736 u32 len;
f21fb3ed
RV		 2737
2738 lio = finfo->lio;
2739
2740 sc = octeon_alloc_soft_command_resp(oct, &ndata->cmd,
2741 sizeof(struct oct_timestamp_resp));
2742 finfo->sc = sc;
2743
2744 if (!sc) {
2745 dev_err(&oct->pci_dev->dev, "No memory for timestamped data packet\n");
2746 return IQ_SEND_FAILED;
2747 }
2748
2749 if (ndata->reqtype == REQTYPE_NORESP_NET)
2750 ndata->reqtype = REQTYPE_RESP_NET;
2751 else if (ndata->reqtype == REQTYPE_NORESP_NET_SG)
2752 ndata->reqtype = REQTYPE_RESP_NET_SG;
2753
2754 sc->callback = handle_timestamp;
2755 sc->callback_arg = finfo->skb;
2756 sc->iq_no = ndata->q_no;
2757
6a885b60 2758 len = (u32)((struct octeon_instr_ih2 *)(&sc->cmd.cmd2.ih2))->dlengsz;
f21fb3ed
RV		 2759
2760 ring_doorbell = !xmit_more;
2761 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd,
6a885b60 2762 sc, len, ndata->reqtype);
f21fb3ed 2763
ddc173a6 2764 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 2765 dev_err(&oct->pci_dev->dev, "timestamp data packet failed status: %x\n",
2766 retval);
2767 octeon_free_soft_command(oct, sc);
2768 } else {
2769 netif_info(lio, tx_queued, lio->netdev, "Queued timestamp packet\n");
2770 }
2771
2772 return retval;
2773}
2774
f21fb3ed
RV		 2775/** \brief Transmit networks packets to the Octeon interface
2776 * @param skbuff skbuff struct to be passed to network layer.
2777 * @param netdev pointer to network device
2778 * @returns whether the packet was transmitted to the device okay or not
2779 * (NETDEV_TX_OK or NETDEV_TX_BUSY)
2780 */
2781static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev)
2782{
2783 struct lio *lio;
2784 struct octnet_buf_free_info *finfo;
2785 union octnic_cmd_setup cmdsetup;
2786 struct octnic_data_pkt ndata;
2787 struct octeon_device *oct;
2788 struct oct_iq_stats *stats;
6a885b60
RV		 2789 struct octeon_instr_irh *irh;
2790 union tx_info *tx_info;
26236fa9 2791 int status = 0;
f21fb3ed 2792 int q_idx = 0, iq_no = 0;
fcd2b5e3
RV		 2793 int xmit_more, j;
2794 u64 dptr = 0;
f21fb3ed
RV		 2795 u32 tag = 0;
2796
2797 lio = GET_LIO(netdev);
2798 oct = lio->oct_dev;
2799
2800 if (netif_is_multiqueue(netdev)) {
26236fa9
RV		 2801 q_idx = skb->queue_mapping;
2802 q_idx = (q_idx % (lio->linfo.num_txpciq));
2803 tag = q_idx;
2804 iq_no = lio->linfo.txpciq[q_idx].s.q_no;
f21fb3ed
RV		 2805 } else {
2806 iq_no = lio->txq;
2807 }
2808
2809 stats = &oct->instr_queue[iq_no]->stats;
2810
2811 /* Check for all conditions in which the current packet cannot be
2812 * transmitted.
2813 */
2814 if (!(atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) ||
0cece6c5 2815 (!lio->linfo.link.s.link_up) ||
f21fb3ed
RV		 2816 (skb->len <= 0)) {
2817 netif_info(lio, tx_err, lio->netdev,
2818 "Transmit failed link_status : %d\n",
0cece6c5 2819 lio->linfo.link.s.link_up);
f21fb3ed
RV		 2820 goto lio_xmit_failed;
2821 }
2822
2823 /* Use space in skb->cb to store info used to unmap and
2824 * free the buffers.
2825 */
2826 finfo = (struct octnet_buf_free_info *)skb->cb;
2827 finfo->lio = lio;
2828 finfo->skb = skb;
2829 finfo->sc = NULL;
2830
2831 /* Prepare the attributes for the data to be passed to OSI. */
2832 memset(&ndata, 0, sizeof(struct octnic_data_pkt));
2833
2834 ndata.buf = (void *)finfo;
2835
2836 ndata.q_no = iq_no;
2837
2838 if (netif_is_multiqueue(netdev)) {
2839 if (octnet_iq_is_full(oct, ndata.q_no)) {
2840 /* defer sending if queue is full */
2841 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
2842 ndata.q_no);
2843 stats->tx_iq_busy++;
2844 return NETDEV_TX_BUSY;
2845 }
2846 } else {
2847 if (octnet_iq_is_full(oct, lio->txq)) {
2848 /* defer sending if queue is full */
2849 stats->tx_iq_busy++;
2850 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
2851 ndata.q_no);
2852 return NETDEV_TX_BUSY;
2853 }
2854 }
2855 /* pr_info(" XMIT - valid Qs: %d, 1st Q no: %d, cpu: %d, q_no:%d\n",
2856 * lio->linfo.num_txpciq, lio->txq, cpu, ndata.q_no );
2857 */
2858
2859 ndata.datasize = skb->len;
2860
2861 cmdsetup.u64 = 0;
7275ebfc 2862 cmdsetup.s.iq_no = iq_no;
f21fb3ed 2863
7275ebfc
RV		 2864 if (skb->ip_summed == CHECKSUM_PARTIAL)
2865 cmdsetup.s.transport_csum = 1;
f21fb3ed 2866
f21fb3ed
RV		 2867 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
2868 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2869 cmdsetup.s.timestamp = 1;
2870 }
2871
2872 if (skb_shinfo(skb)->nr_frags == 0) {
2873 cmdsetup.s.u.datasize = skb->len;
0cece6c5 2874 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
f21fb3ed 2875 /* Offload checksum calculation for TCP/UDP packets */
6a885b60
RV		 2876 dptr = dma_map_single(&oct->pci_dev->dev,
2877 skb->data,
2878 skb->len,
2879 DMA_TO_DEVICE);
2880 if (dma_mapping_error(&oct->pci_dev->dev, dptr)) {
f21fb3ed
RV		 2881 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 1\n",
2882 __func__);
2883 return NETDEV_TX_BUSY;
2884 }
2885
6a885b60
RV		 2886 ndata.cmd.cmd2.dptr = dptr;
2887 finfo->dptr = dptr;
f21fb3ed
RV		 2888 ndata.reqtype = REQTYPE_NORESP_NET;
2889
2890 } else {
2891 int i, frags;
2892 struct skb_frag_struct *frag;
2893 struct octnic_gather *g;
2894
fcd2b5e3
RV		 2895 spin_lock(&lio->glist_lock[q_idx]);
2896 g = (struct octnic_gather *)
2897 list_delete_head(&lio->glist[q_idx]);
2898 spin_unlock(&lio->glist_lock[q_idx]);
f21fb3ed
RV		 2899
2900 if (!g) {
2901 netif_info(lio, tx_err, lio->netdev,
2902 "Transmit scatter gather: glist null!\n");
2903 goto lio_xmit_failed;
2904 }
2905
2906 cmdsetup.s.gather = 1;
2907 cmdsetup.s.u.gatherptrs = (skb_shinfo(skb)->nr_frags + 1);
0cece6c5 2908 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
f21fb3ed
RV		 2909
2910 memset(g->sg, 0, g->sg_size);
2911
2912 g->sg[0].ptr[0] = dma_map_single(&oct->pci_dev->dev,
2913 skb->data,
2914 (skb->len - skb->data_len),
2915 DMA_TO_DEVICE);
2916 if (dma_mapping_error(&oct->pci_dev->dev, g->sg[0].ptr[0])) {
2917 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 2\n",
2918 __func__);
2919 return NETDEV_TX_BUSY;
2920 }
2921 add_sg_size(&g->sg[0], (skb->len - skb->data_len), 0);
2922
2923 frags = skb_shinfo(skb)->nr_frags;
2924 i = 1;
2925 while (frags--) {
2926 frag = &skb_shinfo(skb)->frags[i - 1];
2927
2928 g->sg[(i >> 2)].ptr[(i & 3)] =
2929 dma_map_page(&oct->pci_dev->dev,
2930 frag->page.p,
2931 frag->page_offset,
2932 frag->size,
2933 DMA_TO_DEVICE);
2934
fcd2b5e3
RV		 2935 if (dma_mapping_error(&oct->pci_dev->dev,
2936 g->sg[i >> 2].ptr[i & 3])) {
2937 dma_unmap_single(&oct->pci_dev->dev,
2938 g->sg[0].ptr[0],
2939 skb->len - skb->data_len,
2940 DMA_TO_DEVICE);
2941 for (j = 1; j < i; j++) {
2942 frag = &skb_shinfo(skb)->frags[j - 1];
2943 dma_unmap_page(&oct->pci_dev->dev,
2944 g->sg[j >> 2].ptr[j & 3],
2945 frag->size,
2946 DMA_TO_DEVICE);
2947 }
2948 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 3\n",
2949 __func__);
2950 return NETDEV_TX_BUSY;
2951 }
2952
f21fb3ed
RV		 2953 add_sg_size(&g->sg[(i >> 2)], frag->size, (i & 3));
2954 i++;
2955 }
2956
fcd2b5e3
RV		 2957 dma_sync_single_for_device(&oct->pci_dev->dev, g->sg_dma_ptr,
2958 g->sg_size, DMA_TO_DEVICE);
2959 dptr = g->sg_dma_ptr;
f21fb3ed 2960
6a885b60
RV		 2961 ndata.cmd.cmd2.dptr = dptr;
2962 finfo->dptr = dptr;
f21fb3ed
RV		 2963 finfo->g = g;
2964
2965 ndata.reqtype = REQTYPE_NORESP_NET_SG;
2966 }
2967
6a885b60
RV		 2968 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd2.irh;
2969 tx_info = (union tx_info *)&ndata.cmd.cmd2.ossp[0];
f21fb3ed 2970
6a885b60 2971 if (skb_shinfo(skb)->gso_size) {
f21fb3ed
RV		 2972 tx_info->s.gso_size = skb_shinfo(skb)->gso_size;
2973 tx_info->s.gso_segs = skb_shinfo(skb)->gso_segs;
2974 }
0da0b77c
RV		 2975 /* HW insert VLAN tag */
2976 if (skb_vlan_tag_present(skb)) {
2977 irh->priority = skb_vlan_tag_get(skb) >> 13;
2978 irh->vlan = skb_vlan_tag_get(skb) & 0xfff;
2979 }
f21fb3ed
RV		 2980
2981 xmit_more = skb->xmit_more;
2982
2983 if (unlikely(cmdsetup.s.timestamp))
2984 status = send_nic_timestamp_pkt(oct, &ndata, finfo, xmit_more);
2985 else
2986 status = octnet_send_nic_data_pkt(oct, &ndata, xmit_more);
2987 if (status == IQ_SEND_FAILED)
2988 goto lio_xmit_failed;
2989
2990 netif_info(lio, tx_queued, lio->netdev, "Transmit queued successfully\n");
2991
2992 if (status == IQ_SEND_STOP)
2993 stop_q(lio->netdev, q_idx);
2994
860e9538 2995 netif_trans_update(netdev);
f21fb3ed
RV		 2996
2997 stats->tx_done++;
2998 stats->tx_tot_bytes += skb->len;
2999
3000 return NETDEV_TX_OK;
3001
3002lio_xmit_failed:
3003 stats->tx_dropped++;
3004 netif_info(lio, tx_err, lio->netdev, "IQ%d Transmit dropped:%llu\n",
3005 iq_no, stats->tx_dropped);
6a885b60
RV		 3006 if (dptr)
3007 dma_unmap_single(&oct->pci_dev->dev, dptr,
3008 ndata.datasize, DMA_TO_DEVICE);
cabeb13b 3009 tx_buffer_free(skb);
f21fb3ed
RV		 3010 return NETDEV_TX_OK;
3011}
3012
3013/** \brief Network device Tx timeout
3014 * @param netdev pointer to network device
3015 */
3016static void liquidio_tx_timeout(struct net_device *netdev)
3017{
3018 struct lio *lio;
3019
3020 lio = GET_LIO(netdev);
3021
3022 netif_info(lio, tx_err, lio->netdev,
3023 "Transmit timeout tx_dropped:%ld, waking up queues now!!\n",
3024 netdev->stats.tx_dropped);
860e9538 3025 netif_trans_update(netdev);
f21fb3ed
RV		 3026 txqs_wake(netdev);
3027}
3028
63245f25
RV		 3029static int liquidio_vlan_rx_add_vid(struct net_device *netdev,
3030 __be16 proto __attribute__((unused)),
3031 u16 vid)
3032{
3033 struct lio *lio = GET_LIO(netdev);
3034 struct octeon_device *oct = lio->oct_dev;
3035 struct octnic_ctrl_pkt nctrl;
3036 int ret = 0;
3037
3038 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3039
3040 nctrl.ncmd.u64 = 0;
3041 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER;
3042 nctrl.ncmd.s.param1 = vid;
3043 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3044 nctrl.wait_time = 100;
3045 nctrl.netpndev = (u64)netdev;
3046 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3047
3048 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3049 if (ret < 0) {
3050 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
3051 ret);
3052 }
3053
3054 return ret;
3055}
3056
3057static int liquidio_vlan_rx_kill_vid(struct net_device *netdev,
3058 __be16 proto __attribute__((unused)),
3059 u16 vid)
3060{
3061 struct lio *lio = GET_LIO(netdev);
3062 struct octeon_device *oct = lio->oct_dev;
3063 struct octnic_ctrl_pkt nctrl;
3064 int ret = 0;
3065
3066 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3067
3068 nctrl.ncmd.u64 = 0;
3069 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER;
3070 nctrl.ncmd.s.param1 = vid;
3071 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3072 nctrl.wait_time = 100;
3073 nctrl.netpndev = (u64)netdev;
3074 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3075
3076 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3077 if (ret < 0) {
3078 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
3079 ret);
3080 }
3081 return ret;
3082}
3083
0cece6c5 3084int liquidio_set_feature(struct net_device *netdev, int cmd, u16 param1)
f21fb3ed
RV		 3085{
3086 struct lio *lio = GET_LIO(netdev);
3087 struct octeon_device *oct = lio->oct_dev;
3088 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 3089 int ret = 0;
3090
3091 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
3092
3093 nctrl.ncmd.u64 = 0;
3094 nctrl.ncmd.s.cmd = cmd;
0cece6c5
RV		 3095 nctrl.ncmd.s.param1 = param1;
3096 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 3097 nctrl.wait_time = 100;
3098 nctrl.netpndev = (u64)netdev;
3099 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3100
0cece6c5 3101 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 3102 if (ret < 0) {
3103 dev_err(&oct->pci_dev->dev, "Feature change failed in core (ret: 0x%x)\n",
3104 ret);
3105 }
3106 return ret;
3107}
3108
3109/** \brief Net device fix features
3110 * @param netdev pointer to network device
3111 * @param request features requested
3112 * @returns updated features list
3113 */
3114static netdev_features_t liquidio_fix_features(struct net_device *netdev,
3115 netdev_features_t request)
3116{
3117 struct lio *lio = netdev_priv(netdev);
3118
3119 if ((request & NETIF_F_RXCSUM) &&
3120 !(lio->dev_capability & NETIF_F_RXCSUM))
3121 request &= ~NETIF_F_RXCSUM;
3122
3123 if ((request & NETIF_F_HW_CSUM) &&
3124 !(lio->dev_capability & NETIF_F_HW_CSUM))
3125 request &= ~NETIF_F_HW_CSUM;
3126
3127 if ((request & NETIF_F_TSO) && !(lio->dev_capability & NETIF_F_TSO))
3128 request &= ~NETIF_F_TSO;
3129
3130 if ((request & NETIF_F_TSO6) && !(lio->dev_capability & NETIF_F_TSO6))
3131 request &= ~NETIF_F_TSO6;
3132
3133 if ((request & NETIF_F_LRO) && !(lio->dev_capability & NETIF_F_LRO))
3134 request &= ~NETIF_F_LRO;
3135
3136 /*Disable LRO if RXCSUM is off */
3137 if (!(request & NETIF_F_RXCSUM) && (netdev->features & NETIF_F_LRO) &&
3138 (lio->dev_capability & NETIF_F_LRO))
3139 request &= ~NETIF_F_LRO;
3140
3141 return request;
3142}
3143
3144/** \brief Net device set features
3145 * @param netdev pointer to network device
3146 * @param features features to enable/disable
3147 */
3148static int liquidio_set_features(struct net_device *netdev,
3149 netdev_features_t features)
3150{
3151 struct lio *lio = netdev_priv(netdev);
3152
3153 if (!((netdev->features ^ features) & NETIF_F_LRO))
3154 return 0;
3155
3156 if ((features & NETIF_F_LRO) && (lio->dev_capability & NETIF_F_LRO))
0cece6c5
RV		 3157 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
3158 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed
RV		 3159 else if (!(features & NETIF_F_LRO) &&
3160 (lio->dev_capability & NETIF_F_LRO))
0cece6c5
RV		 3161 liquidio_set_feature(netdev, OCTNET_CMD_LRO_DISABLE,
3162 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed
RV		 3163
3164 return 0;
3165}
3166
3167static struct net_device_ops lionetdevops = {
3168 .ndo_open = liquidio_open,
3169 .ndo_stop = liquidio_stop,
3170 .ndo_start_xmit = liquidio_xmit,
3171 .ndo_get_stats = liquidio_get_stats,
3172 .ndo_set_mac_address = liquidio_set_mac,
3173 .ndo_set_rx_mode = liquidio_set_mcast_list,
3174 .ndo_tx_timeout = liquidio_tx_timeout,
63245f25
RV		 3175
3176 .ndo_vlan_rx_add_vid = liquidio_vlan_rx_add_vid,
3177 .ndo_vlan_rx_kill_vid = liquidio_vlan_rx_kill_vid,
f21fb3ed
RV		 3178 .ndo_change_mtu = liquidio_change_mtu,
3179 .ndo_do_ioctl = liquidio_ioctl,
3180 .ndo_fix_features = liquidio_fix_features,
3181 .ndo_set_features = liquidio_set_features,
3182};
3183
3184/** \brief Entry point for the liquidio module
3185 */
3186static int __init liquidio_init(void)
3187{
3188 int i;
3189 struct handshake *hs;
3190
3191 init_completion(&first_stage);
3192
3193 octeon_init_device_list(conf_type);
3194
3195 if (liquidio_init_pci())
3196 return -EINVAL;
3197
3198 wait_for_completion_timeout(&first_stage, msecs_to_jiffies(1000));
3199
3200 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3201 hs = &handshake[i];
3202 if (hs->pci_dev) {
3203 wait_for_completion(&hs->init);
3204 if (!hs->init_ok) {
3205 /* init handshake failed */
3206 dev_err(&hs->pci_dev->dev,
3207 "Failed to init device\n");
3208 liquidio_deinit_pci();
3209 return -EIO;
3210 }
3211 }
3212 }
3213
3214 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3215 hs = &handshake[i];
3216 if (hs->pci_dev) {
3217 wait_for_completion_timeout(&hs->started,
3218 msecs_to_jiffies(30000));
3219 if (!hs->started_ok) {
3220 /* starter handshake failed */
3221 dev_err(&hs->pci_dev->dev,
3222 "Firmware failed to start\n");
3223 liquidio_deinit_pci();
3224 return -EIO;
3225 }
3226 }
3227 }
3228
3229 return 0;
3230}
3231
5b173cf9 3232static int lio_nic_info(struct octeon_recv_info *recv_info, void *buf)
f21fb3ed
RV		 3233{
3234 struct octeon_device *oct = (struct octeon_device *)buf;
3235 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
0cece6c5 3236 int gmxport = 0;
f21fb3ed
RV		 3237 union oct_link_status *ls;
3238 int i;
3239
0cece6c5 3240 if (recv_pkt->buffer_size[0] != sizeof(*ls)) {
f21fb3ed
RV		 3241 dev_err(&oct->pci_dev->dev, "Malformed NIC_INFO, len=%d, ifidx=%d\n",
3242 recv_pkt->buffer_size[0],
0cece6c5 3243 recv_pkt->rh.r_nic_info.gmxport);
f21fb3ed
RV		 3244 goto nic_info_err;
3245 }
3246
0cece6c5 3247 gmxport = recv_pkt->rh.r_nic_info.gmxport;
f21fb3ed
RV		 3248 ls = (union oct_link_status *)get_rbd(recv_pkt->buffer_ptr[0]);
3249
3250 octeon_swap_8B_data((u64 *)ls, (sizeof(union oct_link_status)) >> 3);
0cece6c5
RV		 3251 for (i = 0; i < oct->ifcount; i++) {
3252 if (oct->props[i].gmxport == gmxport) {
3253 update_link_status(oct->props[i].netdev, ls);
3254 break;
3255 }
3256 }
f21fb3ed
RV		 3257
3258nic_info_err:
3259 for (i = 0; i < recv_pkt->buffer_count; i++)
3260 recv_buffer_free(recv_pkt->buffer_ptr[i]);
3261 octeon_free_recv_info(recv_info);
3262 return 0;
3263}
3264
3265/**
3266 * \brief Setup network interfaces
3267 * @param octeon_dev octeon device
3268 *
3269 * Called during init time for each device. It assumes the NIC
3270 * is already up and running. The link information for each
3271 * interface is passed in link_info.
3272 */
3273static int setup_nic_devices(struct octeon_device *octeon_dev)
3274{
3275 struct lio *lio = NULL;
3276 struct net_device *netdev;
3277 u8 mac[6], i, j;
3278 struct octeon_soft_command *sc;
3279 struct liquidio_if_cfg_context *ctx;
3280 struct liquidio_if_cfg_resp *resp;
3281 struct octdev_props *props;
26236fa9 3282 int retval, num_iqueues, num_oqueues;
f21fb3ed
RV		 3283 int num_cpus = num_online_cpus();
3284 union oct_nic_if_cfg if_cfg;
3285 unsigned int base_queue;
3286 unsigned int gmx_port_id;
3287 u32 resp_size, ctx_size;
0cece6c5 3288 u32 ifidx_or_pfnum;
f21fb3ed
RV		 3289
3290 /* This is to handle link status changes */
3291 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3292 OPCODE_NIC_INFO,
3293 lio_nic_info, octeon_dev);
3294
3295 /* REQTYPE_RESP_NET and REQTYPE_SOFT_COMMAND do not have free functions.
3296 * They are handled directly.
3297 */
3298 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET,
3299 free_netbuf);
3300
3301 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET_SG,
3302 free_netsgbuf);
3303
3304 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_RESP_NET_SG,
3305 free_netsgbuf_with_resp);
3306
3307 for (i = 0; i < octeon_dev->ifcount; i++) {
3308 resp_size = sizeof(struct liquidio_if_cfg_resp);
3309 ctx_size = sizeof(struct liquidio_if_cfg_context);
3310 sc = (struct octeon_soft_command *)
3311 octeon_alloc_soft_command(octeon_dev, 0,
3312 resp_size, ctx_size);
3313 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
3314 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
3315
3316 num_iqueues =
3317 CFG_GET_NUM_TXQS_NIC_IF(octeon_get_conf(octeon_dev), i);
3318 num_oqueues =
3319 CFG_GET_NUM_RXQS_NIC_IF(octeon_get_conf(octeon_dev), i);
3320 base_queue =
3321 CFG_GET_BASE_QUE_NIC_IF(octeon_get_conf(octeon_dev), i);
3322 gmx_port_id =
3323 CFG_GET_GMXID_NIC_IF(octeon_get_conf(octeon_dev), i);
0cece6c5 3324 ifidx_or_pfnum = i;
f21fb3ed
RV		 3325 if (num_iqueues > num_cpus)
3326 num_iqueues = num_cpus;
3327 if (num_oqueues > num_cpus)
3328 num_oqueues = num_cpus;
3329 dev_dbg(&octeon_dev->pci_dev->dev,
3330 "requesting config for interface %d, iqs %d, oqs %d\n",
0cece6c5 3331 ifidx_or_pfnum, num_iqueues, num_oqueues);
f21fb3ed
RV		 3332 ACCESS_ONCE(ctx->cond) = 0;
3333 ctx->octeon_id = lio_get_device_id(octeon_dev);
3334 init_waitqueue_head(&ctx->wc);
3335
3336 if_cfg.u64 = 0;
3337 if_cfg.s.num_iqueues = num_iqueues;
3338 if_cfg.s.num_oqueues = num_oqueues;
3339 if_cfg.s.base_queue = base_queue;
3340 if_cfg.s.gmx_port_id = gmx_port_id;
0cece6c5
RV		 3341
3342 sc->iq_no = 0;
3343
f21fb3ed 3344 octeon_prepare_soft_command(octeon_dev, sc, OPCODE_NIC,
0cece6c5 3345 OPCODE_NIC_IF_CFG, 0,
f21fb3ed
RV		 3346 if_cfg.u64, 0);
3347
3348 sc->callback = if_cfg_callback;
3349 sc->callback_arg = sc;
3350 sc->wait_time = 1000;
3351
3352 retval = octeon_send_soft_command(octeon_dev, sc);
ddc173a6 3353 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 3354 dev_err(&octeon_dev->pci_dev->dev,
3355 "iq/oq config failed status: %x\n",
3356 retval);
3357 /* Soft instr is freed by driver in case of failure. */
3358 goto setup_nic_dev_fail;
3359 }
3360
3361 /* Sleep on a wait queue till the cond flag indicates that the
3362 * response arrived or timed-out.
3363 */
3364 sleep_cond(&ctx->wc, &ctx->cond);
3365 retval = resp->status;
3366 if (retval) {
3367 dev_err(&octeon_dev->pci_dev->dev, "iq/oq config failed\n");
3368 goto setup_nic_dev_fail;
3369 }
3370
3371 octeon_swap_8B_data((u64 *)(&resp->cfg_info),
3372 (sizeof(struct liquidio_if_cfg_info)) >> 3);
3373
3374 num_iqueues = hweight64(resp->cfg_info.iqmask);
3375 num_oqueues = hweight64(resp->cfg_info.oqmask);
3376
3377 if (!(num_iqueues) || !(num_oqueues)) {
3378 dev_err(&octeon_dev->pci_dev->dev,
3379 "Got bad iqueues (%016llx) or oqueues (%016llx) from firmware.\n",
3380 resp->cfg_info.iqmask,
3381 resp->cfg_info.oqmask);
3382 goto setup_nic_dev_fail;
3383 }
3384 dev_dbg(&octeon_dev->pci_dev->dev,
3385 "interface %d, iqmask %016llx, oqmask %016llx, numiqueues %d, numoqueues %d\n",
3386 i, resp->cfg_info.iqmask, resp->cfg_info.oqmask,
3387 num_iqueues, num_oqueues);
3388 netdev = alloc_etherdev_mq(LIO_SIZE, num_iqueues);
3389
3390 if (!netdev) {
3391 dev_err(&octeon_dev->pci_dev->dev, "Device allocation failed\n");
3392 goto setup_nic_dev_fail;
3393 }
3394
0cece6c5 3395 SET_NETDEV_DEV(netdev, &octeon_dev->pci_dev->dev);
f21fb3ed
RV		 3396
3397 if (num_iqueues > 1)
3398 lionetdevops.ndo_select_queue = select_q;
3399
3400 /* Associate the routines that will handle different
3401 * netdev tasks.
3402 */
3403 netdev->netdev_ops = &lionetdevops;
3404
3405 lio = GET_LIO(netdev);
3406
3407 memset(lio, 0, sizeof(struct lio));
3408
0cece6c5
RV		 3409 lio->ifidx = ifidx_or_pfnum;
3410
3411 props = &octeon_dev->props[i];
3412 props->gmxport = resp->cfg_info.linfo.gmxport;
3413 props->netdev = netdev;
f21fb3ed
RV		 3414
3415 lio->linfo.num_rxpciq = num_oqueues;
3416 lio->linfo.num_txpciq = num_iqueues;
f21fb3ed 3417 for (j = 0; j < num_oqueues; j++) {
26236fa9
RV		 3418 lio->linfo.rxpciq[j].u64 =
3419 resp->cfg_info.linfo.rxpciq[j].u64;
f21fb3ed 3420 }
f21fb3ed 3421 for (j = 0; j < num_iqueues; j++) {
26236fa9
RV		 3422 lio->linfo.txpciq[j].u64 =
3423 resp->cfg_info.linfo.txpciq[j].u64;
f21fb3ed
RV		 3424 }
3425 lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr;
3426 lio->linfo.gmxport = resp->cfg_info.linfo.gmxport;
3427 lio->linfo.link.u64 = resp->cfg_info.linfo.link.u64;
3428
3429 lio->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3430
3431 lio->dev_capability = NETIF_F_HIGHDMA
0cece6c5
RV		 3432 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3433 | NETIF_F_SG | NETIF_F_RXCSUM
3434 | NETIF_F_GRO
3435 | NETIF_F_TSO | NETIF_F_TSO6
3436 | NETIF_F_LRO;
f21fb3ed
RV		 3437 netif_set_gso_max_size(netdev, OCTNIC_GSO_MAX_SIZE);
3438
f21fb3ed 3439 netdev->vlan_features = lio->dev_capability;
0da0b77c 3440 /* Add any unchangeable hw features */
63245f25
RV		 3441 lio->dev_capability |= NETIF_F_HW_VLAN_CTAG_FILTER |
3442 NETIF_F_HW_VLAN_CTAG_RX |
0da0b77c
RV		 3443 NETIF_F_HW_VLAN_CTAG_TX;
3444
3445 netdev->features = (lio->dev_capability & ~NETIF_F_LRO);
f21fb3ed
RV		 3446
3447 netdev->hw_features = lio->dev_capability;
0da0b77c
RV		 3448 /*HW_VLAN_RX and HW_VLAN_FILTER is always on*/
3449 netdev->hw_features = netdev->hw_features &
3450 ~NETIF_F_HW_VLAN_CTAG_RX;
f21fb3ed
RV		 3451
3452 /* Point to the properties for octeon device to which this
3453 * interface belongs.
3454 */
3455 lio->oct_dev = octeon_dev;
3456 lio->octprops = props;
3457 lio->netdev = netdev;
f21fb3ed
RV		 3458
3459 dev_dbg(&octeon_dev->pci_dev->dev,
3460 "if%d gmx: %d hw_addr: 0x%llx\n", i,
3461 lio->linfo.gmxport, CVM_CAST64(lio->linfo.hw_addr));
3462
3463 /* 64-bit swap required on LE machines */
3464 octeon_swap_8B_data(&lio->linfo.hw_addr, 1);
3465 for (j = 0; j < 6; j++)
3466 mac[j] = *((u8 *)(((u8 *)&lio->linfo.hw_addr) + 2 + j));
3467
3468 /* Copy MAC Address to OS network device structure */
3469
3470 ether_addr_copy(netdev->dev_addr, mac);
3471
26236fa9
RV		 3472 /* By default all interfaces on a single Octeon uses the same
3473 * tx and rx queues
3474 */
3475 lio->txq = lio->linfo.txpciq[0].s.q_no;
3476 lio->rxq = lio->linfo.rxpciq[0].s.q_no;
0cece6c5 3477 if (setup_io_queues(octeon_dev, i)) {
f21fb3ed
RV		 3478 dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n");
3479 goto setup_nic_dev_fail;
3480 }
3481
3482 ifstate_set(lio, LIO_IFSTATE_DROQ_OPS);
3483
f21fb3ed
RV		 3484 lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq);
3485 lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq);
3486
fcd2b5e3 3487 if (setup_glists(octeon_dev, lio, num_iqueues)) {
f21fb3ed
RV		 3488 dev_err(&octeon_dev->pci_dev->dev,
3489 "Gather list allocation failed\n");
3490 goto setup_nic_dev_fail;
3491 }
3492
3493 /* Register ethtool support */
3494 liquidio_set_ethtool_ops(netdev);
3495
0cece6c5
RV		 3496 if (netdev->features & NETIF_F_LRO)
3497 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
3498 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed 3499
63245f25
RV		 3500 liquidio_set_feature(netdev, OCTNET_CMD_ENABLE_VLAN_FILTER, 0);
3501
f21fb3ed 3502 if ((debug != -1) && (debug & NETIF_MSG_HW))
63245f25
RV		 3503 liquidio_set_feature(netdev,
3504 OCTNET_CMD_VERBOSE_ENABLE, 0);
f21fb3ed
RV		 3505
3506 /* Register the network device with the OS */
3507 if (register_netdev(netdev)) {
3508 dev_err(&octeon_dev->pci_dev->dev, "Device registration failed\n");
3509 goto setup_nic_dev_fail;
3510 }
3511
3512 dev_dbg(&octeon_dev->pci_dev->dev,
3513 "Setup NIC ifidx:%d mac:%02x%02x%02x%02x%02x%02x\n",
3514 i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
3515 netif_carrier_off(netdev);
0cece6c5 3516 lio->link_changes++;
f21fb3ed
RV		 3517
3518 ifstate_set(lio, LIO_IFSTATE_REGISTERED);
3519
3520 dev_dbg(&octeon_dev->pci_dev->dev,
3521 "NIC ifidx:%d Setup successful\n", i);
3522
3523 octeon_free_soft_command(octeon_dev, sc);
3524 }
3525
3526 return 0;
3527
3528setup_nic_dev_fail:
3529
3530 octeon_free_soft_command(octeon_dev, sc);
3531
3532 while (i--) {
3533 dev_err(&octeon_dev->pci_dev->dev,
3534 "NIC ifidx:%d Setup failed\n", i);
3535 liquidio_destroy_nic_device(octeon_dev, i);
3536 }
3537 return -ENODEV;
3538}
3539
3540/**
3541 * \brief initialize the NIC
3542 * @param oct octeon device
3543 *
3544 * This initialization routine is called once the Octeon device application is
3545 * up and running
3546 */
3547static int liquidio_init_nic_module(struct octeon_device *oct)
3548{
3549 struct oct_intrmod_cfg *intrmod_cfg;
0cece6c5 3550 int i, retval = 0;
f21fb3ed
RV		 3551 int num_nic_ports = CFG_GET_NUM_NIC_PORTS(octeon_get_conf(oct));
3552
3553 dev_dbg(&oct->pci_dev->dev, "Initializing network interfaces\n");
3554
3555 /* only default iq and oq were initialized
3556 * initialize the rest as well
3557 */
3558 /* run port_config command for each port */
3559 oct->ifcount = num_nic_ports;
3560
3561 memset(oct->props, 0,
3562 sizeof(struct octdev_props) * num_nic_ports);
3563
0cece6c5
RV		 3564 for (i = 0; i < MAX_OCTEON_LINKS; i++)
3565 oct->props[i].gmxport = -1;
3566
f21fb3ed
RV		 3567 retval = setup_nic_devices(oct);
3568 if (retval) {
3569 dev_err(&oct->pci_dev->dev, "Setup NIC devices failed\n");
3570 goto octnet_init_failure;
3571 }
3572
3573 liquidio_ptp_init(oct);
3574
3575 /* Initialize interrupt moderation params */
3576 intrmod_cfg = &((struct octeon_device *)oct)->intrmod;
3577 intrmod_cfg->intrmod_enable = 1;
3578 intrmod_cfg->intrmod_check_intrvl = LIO_INTRMOD_CHECK_INTERVAL;
3579 intrmod_cfg->intrmod_maxpkt_ratethr = LIO_INTRMOD_MAXPKT_RATETHR;
3580 intrmod_cfg->intrmod_minpkt_ratethr = LIO_INTRMOD_MINPKT_RATETHR;
3581 intrmod_cfg->intrmod_maxcnt_trigger = LIO_INTRMOD_MAXCNT_TRIGGER;
3582 intrmod_cfg->intrmod_maxtmr_trigger = LIO_INTRMOD_MAXTMR_TRIGGER;
3583 intrmod_cfg->intrmod_mintmr_trigger = LIO_INTRMOD_MINTMR_TRIGGER;
3584 intrmod_cfg->intrmod_mincnt_trigger = LIO_INTRMOD_MINCNT_TRIGGER;
3585
3586 dev_dbg(&oct->pci_dev->dev, "Network interfaces ready\n");
3587
3588 return retval;
3589
3590octnet_init_failure:
3591
3592 oct->ifcount = 0;
3593
3594 return retval;
3595}
3596
3597/**
3598 * \brief starter callback that invokes the remaining initialization work after
3599 * the NIC is up and running.
3600 * @param octptr work struct work_struct
3601 */
3602static void nic_starter(struct work_struct *work)
3603{
3604 struct octeon_device *oct;
3605 struct cavium_wk *wk = (struct cavium_wk *)work;
3606
3607 oct = (struct octeon_device *)wk->ctxptr;
3608
3609 if (atomic_read(&oct->status) == OCT_DEV_RUNNING)
3610 return;
3611
3612 /* If the status of the device is CORE_OK, the core
3613 * application has reported its application type. Call
3614 * any registered handlers now and move to the RUNNING
3615 * state.
3616 */
3617 if (atomic_read(&oct->status) != OCT_DEV_CORE_OK) {
3618 schedule_delayed_work(&oct->nic_poll_work.work,
3619 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
3620 return;
3621 }
3622
3623 atomic_set(&oct->status, OCT_DEV_RUNNING);
3624
3625 if (oct->app_mode && oct->app_mode == CVM_DRV_NIC_APP) {
3626 dev_dbg(&oct->pci_dev->dev, "Starting NIC module\n");
3627
3628 if (liquidio_init_nic_module(oct))
3629 dev_err(&oct->pci_dev->dev, "NIC initialization failed\n");
3630 else
3631 handshake[oct->octeon_id].started_ok = 1;
3632 } else {
3633 dev_err(&oct->pci_dev->dev,
3634 "Unexpected application running on NIC (%d). Check firmware.\n",
3635 oct->app_mode);
3636 }
3637
3638 complete(&handshake[oct->octeon_id].started);
3639}
3640
3641/**
3642 * \brief Device initialization for each Octeon device that is probed
3643 * @param octeon_dev octeon device
3644 */
3645static int octeon_device_init(struct octeon_device *octeon_dev)
3646{
3647 int j, ret;
d3d7e6c6 3648 char bootcmd[] = "\n";
f21fb3ed
RV		 3649 struct octeon_device_priv *oct_priv =
3650 (struct octeon_device_priv *)octeon_dev->priv;
3651 atomic_set(&octeon_dev->status, OCT_DEV_BEGIN_STATE);
3652
3653 /* Enable access to the octeon device and make its DMA capability
3654 * known to the OS.
3655 */
3656 if (octeon_pci_os_setup(octeon_dev))
3657 return 1;
3658
3659 /* Identify the Octeon type and map the BAR address space. */
3660 if (octeon_chip_specific_setup(octeon_dev)) {
3661 dev_err(&octeon_dev->pci_dev->dev, "Chip specific setup failed\n");
3662 return 1;
3663 }
3664
3665 atomic_set(&octeon_dev->status, OCT_DEV_PCI_MAP_DONE);
3666
3667 octeon_dev->app_mode = CVM_DRV_INVALID_APP;
3668
3669 /* Do a soft reset of the Octeon device. */
3670 if (octeon_dev->fn_list.soft_reset(octeon_dev))
3671 return 1;
3672
3673 /* Initialize the dispatch mechanism used to push packets arriving on
3674 * Octeon Output queues.
3675 */
3676 if (octeon_init_dispatch_list(octeon_dev))
3677 return 1;
3678
3679 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3680 OPCODE_NIC_CORE_DRV_ACTIVE,
3681 octeon_core_drv_init,
3682 octeon_dev);
3683
3684 INIT_DELAYED_WORK(&octeon_dev->nic_poll_work.work, nic_starter);
3685 octeon_dev->nic_poll_work.ctxptr = (void *)octeon_dev;
3686 schedule_delayed_work(&octeon_dev->nic_poll_work.work,
3687 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
3688
3689 atomic_set(&octeon_dev->status, OCT_DEV_DISPATCH_INIT_DONE);
3690
3691 octeon_set_io_queues_off(octeon_dev);
3692
3693 /* Setup the data structures that manage this Octeon's Input queues. */
3694 if (octeon_setup_instr_queues(octeon_dev)) {
3695 dev_err(&octeon_dev->pci_dev->dev,
3696 "instruction queue initialization failed\n");
3697 /* On error, release any previously allocated queues */
3698 for (j = 0; j < octeon_dev->num_iqs; j++)
3699 octeon_delete_instr_queue(octeon_dev, j);
3700 return 1;
3701 }
3702 atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE);
3703
3704 /* Initialize soft command buffer pool
3705 */
3706 if (octeon_setup_sc_buffer_pool(octeon_dev)) {
3707 dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n");
3708 return 1;
3709 }
3710 atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
3711
3712 /* Initialize lists to manage the requests of different types that
3713 * arrive from user & kernel applications for this octeon device.
3714 */
3715 if (octeon_setup_response_list(octeon_dev)) {
3716 dev_err(&octeon_dev->pci_dev->dev, "Response list allocation failed\n");
3717 return 1;
3718 }
3719 atomic_set(&octeon_dev->status, OCT_DEV_RESP_LIST_INIT_DONE);
3720
3721 if (octeon_setup_output_queues(octeon_dev)) {
3722 dev_err(&octeon_dev->pci_dev->dev, "Output queue initialization failed\n");
3723 /* Release any previously allocated queues */
3724 for (j = 0; j < octeon_dev->num_oqs; j++)
3725 octeon_delete_droq(octeon_dev, j);
3726 }
3727
3728 atomic_set(&octeon_dev->status, OCT_DEV_DROQ_INIT_DONE);
3729
3730 /* The input and output queue registers were setup earlier (the queues
3731 * were not enabled). Any additional registers that need to be
3732 * programmed should be done now.
3733 */
3734 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
3735 if (ret) {
3736 dev_err(&octeon_dev->pci_dev->dev,
3737 "Failed to configure device registers\n");
3738 return ret;
3739 }
3740
3741 /* Initialize the tasklet that handles output queue packet processing.*/
3742 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing droq tasklet\n");
3743 tasklet_init(&oct_priv->droq_tasklet, octeon_droq_bh,
3744 (unsigned long)octeon_dev);
3745
3746 /* Setup the interrupt handler and record the INT SUM register address
3747 */
3748 octeon_setup_interrupt(octeon_dev);
3749
3750 /* Enable Octeon device interrupts */
3751 octeon_dev->fn_list.enable_interrupt(octeon_dev->chip);
3752
3753 /* Enable the input and output queues for this Octeon device */
3754 octeon_dev->fn_list.enable_io_queues(octeon_dev);
3755
3756 atomic_set(&octeon_dev->status, OCT_DEV_IO_QUEUES_DONE);
3757
3758 dev_dbg(&octeon_dev->pci_dev->dev, "Waiting for DDR initialization...\n");
3759
3760 if (ddr_timeout == 0) {
3761 dev_info(&octeon_dev->pci_dev->dev,
3762 "WAITING. Set ddr_timeout to non-zero value to proceed with initialization.\n");
3763 }
3764
3765 schedule_timeout_uninterruptible(HZ * LIO_RESET_SECS);
3766
3767 /* Wait for the octeon to initialize DDR after the soft-reset. */
3768 ret = octeon_wait_for_ddr_init(octeon_dev, &ddr_timeout);
3769 if (ret) {
3770 dev_err(&octeon_dev->pci_dev->dev,
3771 "DDR not initialized. Please confirm that board is configured to boot from Flash, ret: %d\n",
3772 ret);
3773 return 1;
3774 }
3775
3776 if (octeon_wait_for_bootloader(octeon_dev, 1000) != 0) {
3777 dev_err(&octeon_dev->pci_dev->dev, "Board not responding\n");
3778 return 1;
3779 }
3780
d3d7e6c6
RV		 3781 /* Divert uboot to take commands from host instead. */
3782 ret = octeon_console_send_cmd(octeon_dev, bootcmd, 50);
3783
f21fb3ed
RV		 3784 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing consoles\n");
3785 ret = octeon_init_consoles(octeon_dev);
3786 if (ret) {
3787 dev_err(&octeon_dev->pci_dev->dev, "Could not access board consoles\n");
3788 return 1;
3789 }
3790 ret = octeon_add_console(octeon_dev, 0);
3791 if (ret) {
3792 dev_err(&octeon_dev->pci_dev->dev, "Could not access board console\n");
3793 return 1;
3794 }
3795
3796 atomic_set(&octeon_dev->status, OCT_DEV_CONSOLE_INIT_DONE);
3797
3798 dev_dbg(&octeon_dev->pci_dev->dev, "Loading firmware\n");
3799 ret = load_firmware(octeon_dev);
3800 if (ret) {
3801 dev_err(&octeon_dev->pci_dev->dev, "Could not load firmware to board\n");
3802 return 1;
3803 }
3804
3805 handshake[octeon_dev->octeon_id].init_ok = 1;
3806 complete(&handshake[octeon_dev->octeon_id].init);
3807
3808 atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK);
3809
3810 /* Send Credit for Octeon Output queues. Credits are always sent after
3811 * the output queue is enabled.
3812 */
3813 for (j = 0; j < octeon_dev->num_oqs; j++)
3814 writel(octeon_dev->droq[j]->max_count,
3815 octeon_dev->droq[j]->pkts_credit_reg);
3816
3817 /* Packets can start arriving on the output queues from this point. */
3818
3819 return 0;
3820}
3821
3822/**
3823 * \brief Exits the module
3824 */
3825static void __exit liquidio_exit(void)
3826{
3827 liquidio_deinit_pci();
3828
3829 pr_info("LiquidIO network module is now unloaded\n");
3830}
3831
3832module_init(liquidio_init);
3833module_exit(liquidio_exit);
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