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liquidio: CN23XX queue definitions
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / cavium / liquidio / lio_main.c
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f21fb3ed
RV		 1/**********************************************************************
2* Author: Cavium, Inc.
3*
4* Contact: support@cavium.com
5* Please include "LiquidIO" in the subject.
6*
7* Copyright (c) 2003-2015 Cavium, Inc.
8*
9* This file is free software; you can redistribute it and/or modify
10* it under the terms of the GNU General Public License, Version 2, as
11* published by the Free Software Foundation.
12*
13* This file is distributed in the hope that it will be useful, but
14* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16* NONINFRINGEMENT. See the GNU General Public License for more
17* details.
18*
19* This file may also be available under a different license from Cavium.
20* Contact Cavium, Inc. for more information
21**********************************************************************/
22#include <linux/version.h>
f21fb3ed 23#include <linux/pci.h>
f21fb3ed 24#include <linux/firmware.h>
f21fb3ed 25#include <linux/ptp_clock_kernel.h>
01fb237a 26#include <net/vxlan.h>
f21fb3ed
RV		 27#include "liquidio_common.h"
28#include "octeon_droq.h"
29#include "octeon_iq.h"
30#include "response_manager.h"
31#include "octeon_device.h"
32#include "octeon_nic.h"
33#include "octeon_main.h"
34#include "octeon_network.h"
35#include "cn66xx_regs.h"
36#include "cn66xx_device.h"
f21fb3ed
RV		 37#include "cn68xx_device.h"
38#include "liquidio_image.h"
39
40MODULE_AUTHOR("Cavium Networks, <support@cavium.com>");
41MODULE_DESCRIPTION("Cavium LiquidIO Intelligent Server Adapter Driver");
42MODULE_LICENSE("GPL");
43MODULE_VERSION(LIQUIDIO_VERSION);
44MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210SV_NAME LIO_FW_NAME_SUFFIX);
45MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210NV_NAME LIO_FW_NAME_SUFFIX);
46MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_410NV_NAME LIO_FW_NAME_SUFFIX);
47
48static int ddr_timeout = 10000;
49module_param(ddr_timeout, int, 0644);
50MODULE_PARM_DESC(ddr_timeout,
51 "Number of milliseconds to wait for DDR initialization. 0 waits for ddr_timeout to be set to non-zero value before starting to check");
52
f21fb3ed
RV		 53#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
54
1f164717
RV		 55#define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count) \
56 (octeon_dev_ptr->instr_queue[iq_no]->stats.field += count)
57
f21fb3ed
RV		 58static int debug = -1;
59module_param(debug, int, 0644);
60MODULE_PARM_DESC(debug, "NETIF_MSG debug bits");
61
62static char fw_type[LIO_MAX_FW_TYPE_LEN];
63module_param_string(fw_type, fw_type, sizeof(fw_type), 0000);
64MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded. Default \"nic\"");
65
66static int conf_type;
67module_param(conf_type, int, 0);
68MODULE_PARM_DESC(conf_type, "select octeon configuration 0 default 1 ovs");
69
a5b37888
RV		 70static int ptp_enable = 1;
71
f21fb3ed
RV		 72/* Bit mask values for lio->ifstate */
73#define LIO_IFSTATE_DROQ_OPS 0x01
74#define LIO_IFSTATE_REGISTERED 0x02
75#define LIO_IFSTATE_RUNNING 0x04
76#define LIO_IFSTATE_RX_TIMESTAMP_ENABLED 0x08
77
78/* Polling interval for determining when NIC application is alive */
79#define LIQUIDIO_STARTER_POLL_INTERVAL_MS 100
80
81/* runtime link query interval */
82#define LIQUIDIO_LINK_QUERY_INTERVAL_MS 1000
83
84struct liquidio_if_cfg_context {
85 int octeon_id;
86
87 wait_queue_head_t wc;
88
89 int cond;
90};
91
92struct liquidio_if_cfg_resp {
93 u64 rh;
94 struct liquidio_if_cfg_info cfg_info;
95 u64 status;
96};
97
98struct oct_link_status_resp {
99 u64 rh;
100 struct oct_link_info link_info;
101 u64 status;
102};
103
104struct oct_timestamp_resp {
105 u64 rh;
106 u64 timestamp;
107 u64 status;
108};
109
110#define OCT_TIMESTAMP_RESP_SIZE (sizeof(struct oct_timestamp_resp))
111
112union tx_info {
113 u64 u64;
114 struct {
115#ifdef __BIG_ENDIAN_BITFIELD
116 u16 gso_size;
117 u16 gso_segs;
118 u32 reserved;
119#else
120 u32 reserved;
121 u16 gso_segs;
122 u16 gso_size;
123#endif
124 } s;
125};
126
127/** Octeon device properties to be used by the NIC module.
128 * Each octeon device in the system will be represented
129 * by this structure in the NIC module.
130 */
131
132#define OCTNIC_MAX_SG (MAX_SKB_FRAGS)
133
134#define OCTNIC_GSO_MAX_HEADER_SIZE 128
135#define OCTNIC_GSO_MAX_SIZE (GSO_MAX_SIZE - OCTNIC_GSO_MAX_HEADER_SIZE)
136
137/** Structure of a node in list of gather components maintained by
138 * NIC driver for each network device.
139 */
140struct octnic_gather {
141 /** List manipulation. Next and prev pointers. */
142 struct list_head list;
143
144 /** Size of the gather component at sg in bytes. */
145 int sg_size;
146
147 /** Number of bytes that sg was adjusted to make it 8B-aligned. */
148 int adjust;
149
150 /** Gather component that can accommodate max sized fragment list
151 * received from the IP layer.
152 */
153 struct octeon_sg_entry *sg;
fcd2b5e3
RV		 154
155 u64 sg_dma_ptr;
f21fb3ed
RV		 156};
157
f21fb3ed
RV		 158struct handshake {
159 struct completion init;
160 struct completion started;
161 struct pci_dev *pci_dev;
162 int init_ok;
163 int started_ok;
164};
165
166struct octeon_device_priv {
167 /** Tasklet structures for this device. */
168 struct tasklet_struct droq_tasklet;
169 unsigned long napi_mask;
170};
171
172static int octeon_device_init(struct octeon_device *);
32581245 173static int liquidio_stop(struct net_device *netdev);
f21fb3ed
RV		 174static void liquidio_remove(struct pci_dev *pdev);
175static int liquidio_probe(struct pci_dev *pdev,
176 const struct pci_device_id *ent);
177
178static struct handshake handshake[MAX_OCTEON_DEVICES];
179static struct completion first_stage;
180
5b173cf9 181static void octeon_droq_bh(unsigned long pdev)
f21fb3ed
RV		 182{
183 int q_no;
184 int reschedule = 0;
185 struct octeon_device *oct = (struct octeon_device *)pdev;
186 struct octeon_device_priv *oct_priv =
187 (struct octeon_device_priv *)oct->priv;
188
189 /* for (q_no = 0; q_no < oct->num_oqs; q_no++) { */
63da8404
RV		 190 for (q_no = 0; q_no < MAX_OCTEON_OUTPUT_QUEUES(oct); q_no++) {
191 if (!(oct->io_qmask.oq & (1ULL << q_no)))
f21fb3ed
RV		 192 continue;
193 reschedule |= octeon_droq_process_packets(oct, oct->droq[q_no],
194 MAX_PACKET_BUDGET);
cd8b1eb4 195 lio_enable_irq(oct->droq[q_no], NULL);
f21fb3ed
RV		 196 }
197
198 if (reschedule)
199 tasklet_schedule(&oct_priv->droq_tasklet);
200}
201
5b173cf9 202static int lio_wait_for_oq_pkts(struct octeon_device *oct)
f21fb3ed
RV		 203{
204 struct octeon_device_priv *oct_priv =
205 (struct octeon_device_priv *)oct->priv;
206 int retry = 100, pkt_cnt = 0, pending_pkts = 0;
207 int i;
208
209 do {
210 pending_pkts = 0;
211
63da8404
RV		 212 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
213 if (!(oct->io_qmask.oq & (1ULL << i)))
f21fb3ed 214 continue;
a7d5a3dc 215 pkt_cnt += octeon_droq_check_hw_for_pkts(oct->droq[i]);
f21fb3ed
RV		 216 }
217 if (pkt_cnt > 0) {
218 pending_pkts += pkt_cnt;
219 tasklet_schedule(&oct_priv->droq_tasklet);
220 }
221 pkt_cnt = 0;
222 schedule_timeout_uninterruptible(1);
223
224 } while (retry-- && pending_pkts);
225
226 return pkt_cnt;
227}
228
f21fb3ed
RV		 229/**
230 * \brief Forces all IO queues off on a given device
231 * @param oct Pointer to Octeon device
232 */
233static void force_io_queues_off(struct octeon_device *oct)
234{
235 if ((oct->chip_id == OCTEON_CN66XX) ||
236 (oct->chip_id == OCTEON_CN68XX)) {
237 /* Reset the Enable bits for Input Queues. */
238 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
239
240 /* Reset the Enable bits for Output Queues. */
241 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
242 }
243}
244
245/**
246 * \brief wait for all pending requests to complete
247 * @param oct Pointer to Octeon device
248 *
249 * Called during shutdown sequence
250 */
251static int wait_for_pending_requests(struct octeon_device *oct)
252{
253 int i, pcount = 0;
254
255 for (i = 0; i < 100; i++) {
256 pcount =
257 atomic_read(&oct->response_list
258 [OCTEON_ORDERED_SC_LIST].pending_req_count);
259 if (pcount)
260 schedule_timeout_uninterruptible(HZ / 10);
9a96bde4 261 else
f21fb3ed
RV		 262 break;
263 }
264
265 if (pcount)
266 return 1;
267
268 return 0;
269}
270
271/**
272 * \brief Cause device to go quiet so it can be safely removed/reset/etc
273 * @param oct Pointer to Octeon device
274 */
275static inline void pcierror_quiesce_device(struct octeon_device *oct)
276{
277 int i;
278
279 /* Disable the input and output queues now. No more packets will
280 * arrive from Octeon, but we should wait for all packet processing
281 * to finish.
282 */
283 force_io_queues_off(oct);
284
285 /* To allow for in-flight requests */
286 schedule_timeout_uninterruptible(100);
287
288 if (wait_for_pending_requests(oct))
289 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
290
291 /* Force all requests waiting to be fetched by OCTEON to complete. */
63da8404 292 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
f21fb3ed
RV		 293 struct octeon_instr_queue *iq;
294
63da8404 295 if (!(oct->io_qmask.iq & (1ULL << i)))
f21fb3ed
RV		 296 continue;
297 iq = oct->instr_queue[i];
298
299 if (atomic_read(&iq->instr_pending)) {
300 spin_lock_bh(&iq->lock);
301 iq->fill_cnt = 0;
302 iq->octeon_read_index = iq->host_write_index;
303 iq->stats.instr_processed +=
304 atomic_read(&iq->instr_pending);
9a96bde4 305 lio_process_iq_request_list(oct, iq, 0);
f21fb3ed
RV		 306 spin_unlock_bh(&iq->lock);
307 }
308 }
309
310 /* Force all pending ordered list requests to time out. */
311 lio_process_ordered_list(oct, 1);
312
313 /* We do not need to wait for output queue packets to be processed. */
314}
315
316/**
317 * \brief Cleanup PCI AER uncorrectable error status
318 * @param dev Pointer to PCI device
319 */
320static void cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
321{
322 int pos = 0x100;
323 u32 status, mask;
324
325 pr_info("%s :\n", __func__);
326
327 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
328 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
329 if (dev->error_state == pci_channel_io_normal)
330 status &= ~mask; /* Clear corresponding nonfatal bits */
331 else
332 status &= mask; /* Clear corresponding fatal bits */
333 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
334}
335
336/**
337 * \brief Stop all PCI IO to a given device
338 * @param dev Pointer to Octeon device
339 */
340static void stop_pci_io(struct octeon_device *oct)
341{
342 /* No more instructions will be forwarded. */
343 atomic_set(&oct->status, OCT_DEV_IN_RESET);
344
345 pci_disable_device(oct->pci_dev);
346
347 /* Disable interrupts */
348 oct->fn_list.disable_interrupt(oct->chip);
349
350 pcierror_quiesce_device(oct);
351
352 /* Release the interrupt line */
353 free_irq(oct->pci_dev->irq, oct);
354
355 if (oct->flags & LIO_FLAG_MSI_ENABLED)
356 pci_disable_msi(oct->pci_dev);
357
358 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
359 lio_get_state_string(&oct->status));
360
361 /* cn63xx_cleanup_aer_uncorrect_error_status(oct->pci_dev); */
362 /* making it a common function for all OCTEON models */
363 cleanup_aer_uncorrect_error_status(oct->pci_dev);
364}
365
366/**
367 * \brief called when PCI error is detected
368 * @param pdev Pointer to PCI device
369 * @param state The current pci connection state
370 *
371 * This function is called after a PCI bus error affecting
372 * this device has been detected.
373 */
374static pci_ers_result_t liquidio_pcie_error_detected(struct pci_dev *pdev,
375 pci_channel_state_t state)
376{
377 struct octeon_device *oct = pci_get_drvdata(pdev);
378
379 /* Non-correctable Non-fatal errors */
380 if (state == pci_channel_io_normal) {
381 dev_err(&oct->pci_dev->dev, "Non-correctable non-fatal error reported:\n");
382 cleanup_aer_uncorrect_error_status(oct->pci_dev);
383 return PCI_ERS_RESULT_CAN_RECOVER;
384 }
385
386 /* Non-correctable Fatal errors */
387 dev_err(&oct->pci_dev->dev, "Non-correctable FATAL reported by PCI AER driver\n");
388 stop_pci_io(oct);
389
390 /* Always return a DISCONNECT. There is no support for recovery but only
391 * for a clean shutdown.
392 */
393 return PCI_ERS_RESULT_DISCONNECT;
394}
395
396/**
397 * \brief mmio handler
398 * @param pdev Pointer to PCI device
399 */
a7d5a3dc
RV		 400static pci_ers_result_t liquidio_pcie_mmio_enabled(
401 struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 402{
403 /* We should never hit this since we never ask for a reset for a Fatal
404 * Error. We always return DISCONNECT in io_error above.
405 * But play safe and return RECOVERED for now.
406 */
407 return PCI_ERS_RESULT_RECOVERED;
408}
409
410/**
411 * \brief called after the pci bus has been reset.
412 * @param pdev Pointer to PCI device
413 *
414 * Restart the card from scratch, as if from a cold-boot. Implementation
415 * resembles the first-half of the octeon_resume routine.
416 */
a7d5a3dc
RV		 417static pci_ers_result_t liquidio_pcie_slot_reset(
418 struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 419{
420 /* We should never hit this since we never ask for a reset for a Fatal
421 * Error. We always return DISCONNECT in io_error above.
422 * But play safe and return RECOVERED for now.
423 */
424 return PCI_ERS_RESULT_RECOVERED;
425}
426
427/**
428 * \brief called when traffic can start flowing again.
429 * @param pdev Pointer to PCI device
430 *
431 * This callback is called when the error recovery driver tells us that
432 * its OK to resume normal operation. Implementation resembles the
433 * second-half of the octeon_resume routine.
434 */
a7d5a3dc 435static void liquidio_pcie_resume(struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 436{
437 /* Nothing to be done here. */
438}
439
440#ifdef CONFIG_PM
441/**
442 * \brief called when suspending
443 * @param pdev Pointer to PCI device
444 * @param state state to suspend to
445 */
a7d5a3dc
RV		 446static int liquidio_suspend(struct pci_dev *pdev __attribute__((unused)),
447 pm_message_t state __attribute__((unused)))
f21fb3ed
RV		 448{
449 return 0;
450}
451
452/**
453 * \brief called when resuming
454 * @param pdev Pointer to PCI device
455 */
a7d5a3dc 456static int liquidio_resume(struct pci_dev *pdev __attribute__((unused)))
f21fb3ed
RV		 457{
458 return 0;
459}
460#endif
461
462/* For PCI-E Advanced Error Recovery (AER) Interface */
166e2362 463static const struct pci_error_handlers liquidio_err_handler = {
f21fb3ed
RV		 464 .error_detected = liquidio_pcie_error_detected,
465 .mmio_enabled = liquidio_pcie_mmio_enabled,
466 .slot_reset = liquidio_pcie_slot_reset,
467 .resume = liquidio_pcie_resume,
468};
469
470static const struct pci_device_id liquidio_pci_tbl[] = {
471 { /* 68xx */
472 PCI_VENDOR_ID_CAVIUM, 0x91, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
473 },
474 { /* 66xx */
475 PCI_VENDOR_ID_CAVIUM, 0x92, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
476 },
e86b1ab6
RV		 477 { /* 23xx pf */
478 PCI_VENDOR_ID_CAVIUM, 0x9702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
479 },
f21fb3ed
RV		 480 {
481 0, 0, 0, 0, 0, 0, 0
482 }
483};
484MODULE_DEVICE_TABLE(pci, liquidio_pci_tbl);
485
486static struct pci_driver liquidio_pci_driver = {
487 .name = "LiquidIO",
488 .id_table = liquidio_pci_tbl,
489 .probe = liquidio_probe,
490 .remove = liquidio_remove,
491 .err_handler = &liquidio_err_handler, /* For AER */
492
493#ifdef CONFIG_PM
494 .suspend = liquidio_suspend,
495 .resume = liquidio_resume,
496#endif
f21fb3ed
RV		 497};
498
499/**
500 * \brief register PCI driver
501 */
502static int liquidio_init_pci(void)
503{
504 return pci_register_driver(&liquidio_pci_driver);
505}
506
507/**
508 * \brief unregister PCI driver
509 */
510static void liquidio_deinit_pci(void)
511{
512 pci_unregister_driver(&liquidio_pci_driver);
513}
514
515/**
516 * \brief check interface state
517 * @param lio per-network private data
518 * @param state_flag flag state to check
519 */
520static inline int ifstate_check(struct lio *lio, int state_flag)
521{
522 return atomic_read(&lio->ifstate) & state_flag;
523}
524
525/**
526 * \brief set interface state
527 * @param lio per-network private data
528 * @param state_flag flag state to set
529 */
530static inline void ifstate_set(struct lio *lio, int state_flag)
531{
532 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) | state_flag));
533}
534
535/**
536 * \brief clear interface state
537 * @param lio per-network private data
538 * @param state_flag flag state to clear
539 */
540static inline void ifstate_reset(struct lio *lio, int state_flag)
541{
542 atomic_set(&lio->ifstate, (atomic_read(&lio->ifstate) & ~(state_flag)));
543}
544
545/**
546 * \brief Stop Tx queues
547 * @param netdev network device
548 */
549static inline void txqs_stop(struct net_device *netdev)
550{
551 if (netif_is_multiqueue(netdev)) {
552 int i;
553
554 for (i = 0; i < netdev->num_tx_queues; i++)
555 netif_stop_subqueue(netdev, i);
556 } else {
557 netif_stop_queue(netdev);
558 }
559}
560
561/**
562 * \brief Start Tx queues
563 * @param netdev network device
564 */
565static inline void txqs_start(struct net_device *netdev)
566{
567 if (netif_is_multiqueue(netdev)) {
568 int i;
569
570 for (i = 0; i < netdev->num_tx_queues; i++)
571 netif_start_subqueue(netdev, i);
572 } else {
573 netif_start_queue(netdev);
574 }
575}
576
577/**
578 * \brief Wake Tx queues
579 * @param netdev network device
580 */
581static inline void txqs_wake(struct net_device *netdev)
582{
1f164717
RV		 583 struct lio *lio = GET_LIO(netdev);
584
f21fb3ed
RV		 585 if (netif_is_multiqueue(netdev)) {
586 int i;
587
1f164717
RV		 588 for (i = 0; i < netdev->num_tx_queues; i++) {
589 int qno = lio->linfo.txpciq[i %
590 (lio->linfo.num_txpciq)].s.q_no;
591
592 if (__netif_subqueue_stopped(netdev, i)) {
593 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, qno,
594 tx_restart, 1);
26236fa9 595 netif_wake_subqueue(netdev, i);
1f164717
RV		 596 }
597 }
f21fb3ed 598 } else {
1f164717
RV		 599 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, lio->txq,
600 tx_restart, 1);
f21fb3ed
RV		 601 netif_wake_queue(netdev);
602 }
603}
604
605/**
606 * \brief Stop Tx queue
607 * @param netdev network device
608 */
609static void stop_txq(struct net_device *netdev)
610{
611 txqs_stop(netdev);
612}
613
614/**
615 * \brief Start Tx queue
616 * @param netdev network device
617 */
618static void start_txq(struct net_device *netdev)
619{
620 struct lio *lio = GET_LIO(netdev);
621
0cece6c5 622 if (lio->linfo.link.s.link_up) {
f21fb3ed
RV		 623 txqs_start(netdev);
624 return;
625 }
626}
627
628/**
629 * \brief Wake a queue
630 * @param netdev network device
631 * @param q which queue to wake
632 */
633static inline void wake_q(struct net_device *netdev, int q)
634{
635 if (netif_is_multiqueue(netdev))
636 netif_wake_subqueue(netdev, q);
637 else
638 netif_wake_queue(netdev);
639}
640
641/**
642 * \brief Stop a queue
643 * @param netdev network device
644 * @param q which queue to stop
645 */
646static inline void stop_q(struct net_device *netdev, int q)
647{
648 if (netif_is_multiqueue(netdev))
649 netif_stop_subqueue(netdev, q);
650 else
651 netif_stop_queue(netdev);
652}
653
654/**
655 * \brief Check Tx queue status, and take appropriate action
656 * @param lio per-network private data
657 * @returns 0 if full, number of queues woken up otherwise
658 */
659static inline int check_txq_status(struct lio *lio)
660{
661 int ret_val = 0;
662
663 if (netif_is_multiqueue(lio->netdev)) {
664 int numqs = lio->netdev->num_tx_queues;
665 int q, iq = 0;
666
667 /* check each sub-queue state */
668 for (q = 0; q < numqs; q++) {
26236fa9
RV		 669 iq = lio->linfo.txpciq[q %
670 (lio->linfo.num_txpciq)].s.q_no;
f21fb3ed
RV		 671 if (octnet_iq_is_full(lio->oct_dev, iq))
672 continue;
26236fa9
RV		 673 if (__netif_subqueue_stopped(lio->netdev, q)) {
674 wake_q(lio->netdev, q);
1f164717
RV		 675 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq,
676 tx_restart, 1);
26236fa9
RV		 677 ret_val++;
678 }
f21fb3ed
RV		 679 }
680 } else {
681 if (octnet_iq_is_full(lio->oct_dev, lio->txq))
682 return 0;
683 wake_q(lio->netdev, lio->txq);
1f164717
RV		 684 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, lio->txq,
685 tx_restart, 1);
f21fb3ed
RV		 686 ret_val = 1;
687 }
688 return ret_val;
689}
690
691/**
692 * Remove the node at the head of the list. The list would be empty at
693 * the end of this call if there are no more nodes in the list.
694 */
695static inline struct list_head *list_delete_head(struct list_head *root)
696{
697 struct list_head *node;
698
699 if ((root->prev == root) && (root->next == root))
700 node = NULL;
701 else
702 node = root->next;
703
704 if (node)
705 list_del(node);
706
707 return node;
708}
709
710/**
fcd2b5e3 711 * \brief Delete gather lists
f21fb3ed
RV		 712 * @param lio per-network private data
713 */
fcd2b5e3 714static void delete_glists(struct lio *lio)
f21fb3ed
RV		 715{
716 struct octnic_gather *g;
fcd2b5e3 717 int i;
f21fb3ed 718
fcd2b5e3
RV		 719 if (!lio->glist)
720 return;
721
722 for (i = 0; i < lio->linfo.num_txpciq; i++) {
723 do {
724 g = (struct octnic_gather *)
725 list_delete_head(&lio->glist[i]);
726 if (g) {
727 if (g->sg) {
728 dma_unmap_single(&lio->oct_dev->
729 pci_dev->dev,
730 g->sg_dma_ptr,
731 g->sg_size,
732 DMA_TO_DEVICE);
733 kfree((void *)((unsigned long)g->sg -
734 g->adjust));
735 }
736 kfree(g);
737 }
738 } while (g);
739 }
740
741 kfree((void *)lio->glist);
f21fb3ed
RV		 742}
743
744/**
fcd2b5e3 745 * \brief Setup gather lists
f21fb3ed
RV		 746 * @param lio per-network private data
747 */
fcd2b5e3 748static int setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs)
f21fb3ed 749{
fcd2b5e3 750 int i, j;
f21fb3ed
RV		 751 struct octnic_gather *g;
752
fcd2b5e3
RV		 753 lio->glist_lock = kcalloc(num_iqs, sizeof(*lio->glist_lock),
754 GFP_KERNEL);
755 if (!lio->glist_lock)
756 return 1;
f21fb3ed 757
fcd2b5e3
RV		 758 lio->glist = kcalloc(num_iqs, sizeof(*lio->glist),
759 GFP_KERNEL);
760 if (!lio->glist) {
761 kfree((void *)lio->glist_lock);
762 return 1;
763 }
f21fb3ed 764
fcd2b5e3
RV		 765 for (i = 0; i < num_iqs; i++) {
766 int numa_node = cpu_to_node(i % num_online_cpus());
f21fb3ed 767
fcd2b5e3
RV		 768 spin_lock_init(&lio->glist_lock[i]);
769
770 INIT_LIST_HEAD(&lio->glist[i]);
771
772 for (j = 0; j < lio->tx_qsize; j++) {
773 g = kzalloc_node(sizeof(*g), GFP_KERNEL,
774 numa_node);
775 if (!g)
776 g = kzalloc(sizeof(*g), GFP_KERNEL);
777 if (!g)
778 break;
779
780 g->sg_size = ((ROUNDUP4(OCTNIC_MAX_SG) >> 2) *
781 OCT_SG_ENTRY_SIZE);
782
783 g->sg = kmalloc_node(g->sg_size + 8,
784 GFP_KERNEL, numa_node);
785 if (!g->sg)
786 g->sg = kmalloc(g->sg_size + 8, GFP_KERNEL);
787 if (!g->sg) {
788 kfree(g);
789 break;
790 }
791
792 /* The gather component should be aligned on 64-bit
793 * boundary
794 */
795 if (((unsigned long)g->sg) & 7) {
796 g->adjust = 8 - (((unsigned long)g->sg) & 7);
797 g->sg = (struct octeon_sg_entry *)
798 ((unsigned long)g->sg + g->adjust);
799 }
800 g->sg_dma_ptr = dma_map_single(&oct->pci_dev->dev,
801 g->sg, g->sg_size,
802 DMA_TO_DEVICE);
803 if (dma_mapping_error(&oct->pci_dev->dev,
804 g->sg_dma_ptr)) {
805 kfree((void *)((unsigned long)g->sg -
806 g->adjust));
807 kfree(g);
808 break;
809 }
810
811 list_add_tail(&g->list, &lio->glist[i]);
f21fb3ed
RV		 812 }
813
fcd2b5e3
RV		 814 if (j != lio->tx_qsize) {
815 delete_glists(lio);
816 return 1;
f21fb3ed 817 }
f21fb3ed
RV		 818 }
819
fcd2b5e3 820 return 0;
f21fb3ed
RV		 821}
822
823/**
824 * \brief Print link information
825 * @param netdev network device
826 */
827static void print_link_info(struct net_device *netdev)
828{
829 struct lio *lio = GET_LIO(netdev);
830
831 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED) {
832 struct oct_link_info *linfo = &lio->linfo;
833
0cece6c5 834 if (linfo->link.s.link_up) {
f21fb3ed
RV		 835 netif_info(lio, link, lio->netdev, "%d Mbps %s Duplex UP\n",
836 linfo->link.s.speed,
837 (linfo->link.s.duplex) ? "Full" : "Half");
838 } else {
839 netif_info(lio, link, lio->netdev, "Link Down\n");
840 }
841 }
842}
843
844/**
845 * \brief Update link status
846 * @param netdev network device
847 * @param ls link status structure
848 *
849 * Called on receipt of a link status response from the core application to
850 * update each interface's link status.
851 */
852static inline void update_link_status(struct net_device *netdev,
853 union oct_link_status *ls)
854{
855 struct lio *lio = GET_LIO(netdev);
0cece6c5 856 int changed = (lio->linfo.link.u64 != ls->u64);
f21fb3ed 857
0cece6c5 858 lio->linfo.link.u64 = ls->u64;
f21fb3ed 859
0cece6c5 860 if ((lio->intf_open) && (changed)) {
f21fb3ed 861 print_link_info(netdev);
0cece6c5 862 lio->link_changes++;
f21fb3ed 863
0cece6c5 864 if (lio->linfo.link.s.link_up) {
f21fb3ed
RV		 865 netif_carrier_on(netdev);
866 /* start_txq(netdev); */
867 txqs_wake(netdev);
868 } else {
869 netif_carrier_off(netdev);
870 stop_txq(netdev);
871 }
872 }
873}
874
9a96bde4
RV		 875/* Runs in interrupt context. */
876static void update_txq_status(struct octeon_device *oct, int iq_num)
877{
878 struct net_device *netdev;
879 struct lio *lio;
880 struct octeon_instr_queue *iq = oct->instr_queue[iq_num];
881
882 /*octeon_update_iq_read_idx(oct, iq);*/
883
884 netdev = oct->props[iq->ifidx].netdev;
885
886 /* This is needed because the first IQ does not have
887 * a netdev associated with it.
888 */
889 if (!netdev)
890 return;
891
892 lio = GET_LIO(netdev);
893 if (netif_is_multiqueue(netdev)) {
894 if (__netif_subqueue_stopped(netdev, iq->q_index) &&
895 lio->linfo.link.s.link_up &&
896 (!octnet_iq_is_full(oct, iq_num))) {
1f164717
RV		 897 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq_num,
898 tx_restart, 1);
9a96bde4
RV		 899 netif_wake_subqueue(netdev, iq->q_index);
900 } else {
1f164717
RV		 901 if (!octnet_iq_is_full(oct, lio->txq)) {
902 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev,
903 lio->txq,
904 tx_restart, 1);
9a96bde4 905 wake_q(netdev, lio->txq);
1f164717 906 }
9a96bde4
RV		 907 }
908 }
909}
910
f21fb3ed
RV		 911/**
912 * \brief Droq packet processor sceduler
913 * @param oct octeon device
914 */
915static
916void liquidio_schedule_droq_pkt_handlers(struct octeon_device *oct)
917{
918 struct octeon_device_priv *oct_priv =
919 (struct octeon_device_priv *)oct->priv;
920 u64 oq_no;
921 struct octeon_droq *droq;
922
923 if (oct->int_status & OCT_DEV_INTR_PKT_DATA) {
63da8404
RV		 924 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct);
925 oq_no++) {
926 if (!(oct->droq_intr & (1ULL << oq_no)))
f21fb3ed
RV		 927 continue;
928
929 droq = oct->droq[oq_no];
930
931 if (droq->ops.poll_mode) {
932 droq->ops.napi_fn(droq);
933 oct_priv->napi_mask |= (1 << oq_no);
934 } else {
935 tasklet_schedule(&oct_priv->droq_tasklet);
936 }
937 }
938 }
939}
940
941/**
942 * \brief Interrupt handler for octeon
943 * @param irq unused
944 * @param dev octeon device
945 */
946static
947irqreturn_t liquidio_intr_handler(int irq __attribute__((unused)), void *dev)
948{
949 struct octeon_device *oct = (struct octeon_device *)dev;
950 irqreturn_t ret;
951
952 /* Disable our interrupts for the duration of ISR */
953 oct->fn_list.disable_interrupt(oct->chip);
954
955 ret = oct->fn_list.process_interrupt_regs(oct);
956
957 if (ret == IRQ_HANDLED)
958 liquidio_schedule_droq_pkt_handlers(oct);
959
960 /* Re-enable our interrupts */
961 if (!(atomic_read(&oct->status) == OCT_DEV_IN_RESET))
962 oct->fn_list.enable_interrupt(oct->chip);
963
964 return ret;
965}
966
967/**
968 * \brief Setup interrupt for octeon device
969 * @param oct octeon device
970 *
971 * Enable interrupt in Octeon device as given in the PCI interrupt mask.
972 */
973static int octeon_setup_interrupt(struct octeon_device *oct)
974{
975 int irqret, err;
976
977 err = pci_enable_msi(oct->pci_dev);
978 if (err)
979 dev_warn(&oct->pci_dev->dev, "Reverting to legacy interrupts. Error: %d\n",
980 err);
981 else
982 oct->flags |= LIO_FLAG_MSI_ENABLED;
983
984 irqret = request_irq(oct->pci_dev->irq, liquidio_intr_handler,
985 IRQF_SHARED, "octeon", oct);
986 if (irqret) {
987 if (oct->flags & LIO_FLAG_MSI_ENABLED)
988 pci_disable_msi(oct->pci_dev);
989 dev_err(&oct->pci_dev->dev, "Request IRQ failed with code: %d\n",
990 irqret);
991 return 1;
992 }
993
994 return 0;
995}
996
997/**
998 * \brief PCI probe handler
999 * @param pdev PCI device structure
1000 * @param ent unused
1001 */
a7d5a3dc
RV		 1002static int
1003liquidio_probe(struct pci_dev *pdev,
1004 const struct pci_device_id *ent __attribute__((unused)))
f21fb3ed
RV		 1005{
1006 struct octeon_device *oct_dev = NULL;
1007 struct handshake *hs;
1008
1009 oct_dev = octeon_allocate_device(pdev->device,
1010 sizeof(struct octeon_device_priv));
1011 if (!oct_dev) {
1012 dev_err(&pdev->dev, "Unable to allocate device\n");
1013 return -ENOMEM;
1014 }
1015
1016 dev_info(&pdev->dev, "Initializing device %x:%x.\n",
1017 (u32)pdev->vendor, (u32)pdev->device);
1018
1019 /* Assign octeon_device for this device to the private data area. */
1020 pci_set_drvdata(pdev, oct_dev);
1021
1022 /* set linux specific device pointer */
1023 oct_dev->pci_dev = (void *)pdev;
1024
1025 hs = &handshake[oct_dev->octeon_id];
1026 init_completion(&hs->init);
1027 init_completion(&hs->started);
1028 hs->pci_dev = pdev;
1029
1030 if (oct_dev->octeon_id == 0)
1031 /* first LiquidIO NIC is detected */
1032 complete(&first_stage);
1033
1034 if (octeon_device_init(oct_dev)) {
1035 liquidio_remove(pdev);
1036 return -ENOMEM;
1037 }
1038
1f164717
RV		 1039 oct_dev->rx_pause = 1;
1040 oct_dev->tx_pause = 1;
1041
f21fb3ed
RV		 1042 dev_dbg(&oct_dev->pci_dev->dev, "Device is ready\n");
1043
1044 return 0;
1045}
1046
1047/**
1048 *\brief Destroy resources associated with octeon device
1049 * @param pdev PCI device structure
1050 * @param ent unused
1051 */
1052static void octeon_destroy_resources(struct octeon_device *oct)
1053{
1054 int i;
1055 struct octeon_device_priv *oct_priv =
1056 (struct octeon_device_priv *)oct->priv;
1057
1058 struct handshake *hs;
1059
1060 switch (atomic_read(&oct->status)) {
1061 case OCT_DEV_RUNNING:
1062 case OCT_DEV_CORE_OK:
1063
1064 /* No more instructions will be forwarded. */
1065 atomic_set(&oct->status, OCT_DEV_IN_RESET);
1066
1067 oct->app_mode = CVM_DRV_INVALID_APP;
1068 dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
1069 lio_get_state_string(&oct->status));
1070
1071 schedule_timeout_uninterruptible(HZ / 10);
1072
1073 /* fallthrough */
1074 case OCT_DEV_HOST_OK:
1075
1076 /* fallthrough */
1077 case OCT_DEV_CONSOLE_INIT_DONE:
1078 /* Remove any consoles */
1079 octeon_remove_consoles(oct);
1080
1081 /* fallthrough */
1082 case OCT_DEV_IO_QUEUES_DONE:
1083 if (wait_for_pending_requests(oct))
1084 dev_err(&oct->pci_dev->dev, "There were pending requests\n");
1085
1086 if (lio_wait_for_instr_fetch(oct))
1087 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n");
1088
1089 /* Disable the input and output queues now. No more packets will
1090 * arrive from Octeon, but we should wait for all packet
1091 * processing to finish.
1092 */
1093 oct->fn_list.disable_io_queues(oct);
1094
1095 if (lio_wait_for_oq_pkts(oct))
1096 dev_err(&oct->pci_dev->dev, "OQ had pending packets\n");
1097
1098 /* Disable interrupts */
1099 oct->fn_list.disable_interrupt(oct->chip);
1100
1101 /* Release the interrupt line */
1102 free_irq(oct->pci_dev->irq, oct);
1103
1104 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1105 pci_disable_msi(oct->pci_dev);
1106
f21fb3ed
RV		 1107 /* fallthrough */
1108 case OCT_DEV_IN_RESET:
1109 case OCT_DEV_DROQ_INIT_DONE:
1110 /*atomic_set(&oct->status, OCT_DEV_DROQ_INIT_DONE);*/
1111 mdelay(100);
63da8404
RV		 1112 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
1113 if (!(oct->io_qmask.oq & (1ULL << i)))
f21fb3ed
RV		 1114 continue;
1115 octeon_delete_droq(oct, i);
1116 }
1117
1118 /* Force any pending handshakes to complete */
1119 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
1120 hs = &handshake[i];
1121
1122 if (hs->pci_dev) {
1123 handshake[oct->octeon_id].init_ok = 0;
1124 complete(&handshake[oct->octeon_id].init);
1125 handshake[oct->octeon_id].started_ok = 0;
1126 complete(&handshake[oct->octeon_id].started);
1127 }
1128 }
1129
1130 /* fallthrough */
1131 case OCT_DEV_RESP_LIST_INIT_DONE:
1132 octeon_delete_response_list(oct);
1133
1134 /* fallthrough */
1135 case OCT_DEV_SC_BUFF_POOL_INIT_DONE:
1136 octeon_free_sc_buffer_pool(oct);
1137
1138 /* fallthrough */
1139 case OCT_DEV_INSTR_QUEUE_INIT_DONE:
63da8404
RV		 1140 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
1141 if (!(oct->io_qmask.iq & (1ULL << i)))
f21fb3ed
RV		 1142 continue;
1143 octeon_delete_instr_queue(oct, i);
1144 }
1145
1146 /* fallthrough */
1147 case OCT_DEV_DISPATCH_INIT_DONE:
1148 octeon_delete_dispatch_list(oct);
1149 cancel_delayed_work_sync(&oct->nic_poll_work.work);
1150
1151 /* fallthrough */
1152 case OCT_DEV_PCI_MAP_DONE:
60b48c5a
RV		 1153
1154 /* Soft reset the octeon device before exiting */
1155 oct->fn_list.soft_reset(oct);
1156
f21fb3ed
RV		 1157 octeon_unmap_pci_barx(oct, 0);
1158 octeon_unmap_pci_barx(oct, 1);
1159
1160 /* fallthrough */
1161 case OCT_DEV_BEGIN_STATE:
60b48c5a
RV		 1162 /* Disable the device, releasing the PCI INT */
1163 pci_disable_device(oct->pci_dev);
1164
f21fb3ed
RV		 1165 /* Nothing to be done here either */
1166 break;
a2c64b67 1167 } /* end switch (oct->status) */
f21fb3ed
RV		 1168
1169 tasklet_kill(&oct_priv->droq_tasklet);
1170}
1171
1172/**
1173 * \brief Send Rx control command
1174 * @param lio per-network private data
1175 * @param start_stop whether to start or stop
1176 */
1177static void send_rx_ctrl_cmd(struct lio *lio, int start_stop)
1178{
1179 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 1180
1181 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
1182
1183 nctrl.ncmd.s.cmd = OCTNET_CMD_RX_CTL;
0cece6c5
RV		 1184 nctrl.ncmd.s.param1 = start_stop;
1185 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 1186 nctrl.netpndev = (u64)lio->netdev;
1187
0cece6c5 1188 if (octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl) < 0)
f21fb3ed
RV		 1189 netif_info(lio, rx_err, lio->netdev, "Failed to send RX Control message\n");
1190}
1191
1192/**
1193 * \brief Destroy NIC device interface
1194 * @param oct octeon device
1195 * @param ifidx which interface to destroy
1196 *
1197 * Cleanup associated with each interface for an Octeon device when NIC
1198 * module is being unloaded or if initialization fails during load.
1199 */
1200static void liquidio_destroy_nic_device(struct octeon_device *oct, int ifidx)
1201{
1202 struct net_device *netdev = oct->props[ifidx].netdev;
1203 struct lio *lio;
9a96bde4 1204 struct napi_struct *napi, *n;
f21fb3ed
RV		 1205
1206 if (!netdev) {
1207 dev_err(&oct->pci_dev->dev, "%s No netdevice ptr for index %d\n",
1208 __func__, ifidx);
1209 return;
1210 }
1211
1212 lio = GET_LIO(netdev);
1213
1214 dev_dbg(&oct->pci_dev->dev, "NIC device cleanup\n");
1215
1216 send_rx_ctrl_cmd(lio, 0);
1217
1218 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING)
1219 txqs_stop(netdev);
1220
9a96bde4
RV		 1221 if (oct->props[lio->ifidx].napi_enabled == 1) {
1222 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
1223 napi_disable(napi);
1224
1225 oct->props[lio->ifidx].napi_enabled = 0;
1226 }
1227
f21fb3ed
RV		 1228 if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED)
1229 unregister_netdev(netdev);
1230
fcd2b5e3 1231 delete_glists(lio);
f21fb3ed
RV		 1232
1233 free_netdev(netdev);
1234
0cece6c5
RV		 1235 oct->props[ifidx].gmxport = -1;
1236
f21fb3ed
RV		 1237 oct->props[ifidx].netdev = NULL;
1238}
1239
1240/**
1241 * \brief Stop complete NIC functionality
1242 * @param oct octeon device
1243 */
1244static int liquidio_stop_nic_module(struct octeon_device *oct)
1245{
1246 int i, j;
1247 struct lio *lio;
1248
1249 dev_dbg(&oct->pci_dev->dev, "Stopping network interfaces\n");
1250 if (!oct->ifcount) {
1251 dev_err(&oct->pci_dev->dev, "Init for Octeon was not completed\n");
1252 return 1;
1253 }
1254
60441888
RV		 1255 spin_lock_bh(&oct->cmd_resp_wqlock);
1256 oct->cmd_resp_state = OCT_DRV_OFFLINE;
1257 spin_unlock_bh(&oct->cmd_resp_wqlock);
1258
f21fb3ed
RV		 1259 for (i = 0; i < oct->ifcount; i++) {
1260 lio = GET_LIO(oct->props[i].netdev);
1261 for (j = 0; j < lio->linfo.num_rxpciq; j++)
26236fa9
RV		 1262 octeon_unregister_droq_ops(oct,
1263 lio->linfo.rxpciq[j].s.q_no);
f21fb3ed
RV		 1264 }
1265
1266 for (i = 0; i < oct->ifcount; i++)
1267 liquidio_destroy_nic_device(oct, i);
1268
1269 dev_dbg(&oct->pci_dev->dev, "Network interfaces stopped\n");
1270 return 0;
1271}
1272
1273/**
1274 * \brief Cleans up resources at unload time
1275 * @param pdev PCI device structure
1276 */
1277static void liquidio_remove(struct pci_dev *pdev)
1278{
1279 struct octeon_device *oct_dev = pci_get_drvdata(pdev);
1280
1281 dev_dbg(&oct_dev->pci_dev->dev, "Stopping device\n");
1282
1283 if (oct_dev->app_mode && (oct_dev->app_mode == CVM_DRV_NIC_APP))
1284 liquidio_stop_nic_module(oct_dev);
1285
1286 /* Reset the octeon device and cleanup all memory allocated for
1287 * the octeon device by driver.
1288 */
1289 octeon_destroy_resources(oct_dev);
1290
1291 dev_info(&oct_dev->pci_dev->dev, "Device removed\n");
1292
1293 /* This octeon device has been removed. Update the global
1294 * data structure to reflect this. Free the device structure.
1295 */
1296 octeon_free_device_mem(oct_dev);
1297}
1298
1299/**
1300 * \brief Identify the Octeon device and to map the BAR address space
1301 * @param oct octeon device
1302 */
1303static int octeon_chip_specific_setup(struct octeon_device *oct)
1304{
1305 u32 dev_id, rev_id;
1306 int ret = 1;
d3d7e6c6 1307 char *s;
f21fb3ed
RV		 1308
1309 pci_read_config_dword(oct->pci_dev, 0, &dev_id);
1310 pci_read_config_dword(oct->pci_dev, 8, &rev_id);
1311 oct->rev_id = rev_id & 0xff;
1312
1313 switch (dev_id) {
1314 case OCTEON_CN68XX_PCIID:
1315 oct->chip_id = OCTEON_CN68XX;
1316 ret = lio_setup_cn68xx_octeon_device(oct);
d3d7e6c6 1317 s = "CN68XX";
f21fb3ed
RV		 1318 break;
1319
1320 case OCTEON_CN66XX_PCIID:
1321 oct->chip_id = OCTEON_CN66XX;
1322 ret = lio_setup_cn66xx_octeon_device(oct);
d3d7e6c6 1323 s = "CN66XX";
f21fb3ed 1324 break;
d3d7e6c6 1325
f21fb3ed 1326 default:
d3d7e6c6 1327 s = "?";
f21fb3ed
RV		 1328 dev_err(&oct->pci_dev->dev, "Unknown device found (dev_id: %x)\n",
1329 dev_id);
1330 }
1331
1332 if (!ret)
d3d7e6c6 1333 dev_info(&oct->pci_dev->dev, "%s PASS%d.%d %s Version: %s\n", s,
f21fb3ed
RV		 1334 OCTEON_MAJOR_REV(oct),
1335 OCTEON_MINOR_REV(oct),
d3d7e6c6
RV		 1336 octeon_get_conf(oct)->card_name,
1337 LIQUIDIO_VERSION);
f21fb3ed
RV		 1338
1339 return ret;
1340}
1341
1342/**
1343 * \brief PCI initialization for each Octeon device.
1344 * @param oct octeon device
1345 */
1346static int octeon_pci_os_setup(struct octeon_device *oct)
1347{
1348 /* setup PCI stuff first */
1349 if (pci_enable_device(oct->pci_dev)) {
1350 dev_err(&oct->pci_dev->dev, "pci_enable_device failed\n");
1351 return 1;
1352 }
1353
1354 if (dma_set_mask_and_coherent(&oct->pci_dev->dev, DMA_BIT_MASK(64))) {
1355 dev_err(&oct->pci_dev->dev, "Unexpected DMA device capability\n");
1356 return 1;
1357 }
1358
1359 /* Enable PCI DMA Master. */
1360 pci_set_master(oct->pci_dev);
1361
1362 return 0;
1363}
1364
fcd2b5e3
RV		 1365static inline int skb_iq(struct lio *lio, struct sk_buff *skb)
1366{
1367 int q = 0;
1368
1369 if (netif_is_multiqueue(lio->netdev))
1370 q = skb->queue_mapping % lio->linfo.num_txpciq;
1371
1372 return q;
1373}
1374
f21fb3ed
RV		 1375/**
1376 * \brief Check Tx queue state for a given network buffer
1377 * @param lio per-network private data
1378 * @param skb network buffer
1379 */
1380static inline int check_txq_state(struct lio *lio, struct sk_buff *skb)
1381{
1382 int q = 0, iq = 0;
1383
1384 if (netif_is_multiqueue(lio->netdev)) {
1385 q = skb->queue_mapping;
26236fa9 1386 iq = lio->linfo.txpciq[(q % (lio->linfo.num_txpciq))].s.q_no;
f21fb3ed
RV		 1387 } else {
1388 iq = lio->txq;
26236fa9 1389 q = iq;
f21fb3ed
RV		 1390 }
1391
1392 if (octnet_iq_is_full(lio->oct_dev, iq))
1393 return 0;
26236fa9 1394
1f164717
RV		 1395 if (__netif_subqueue_stopped(lio->netdev, q)) {
1396 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq, tx_restart, 1);
26236fa9 1397 wake_q(lio->netdev, q);
1f164717 1398 }
f21fb3ed
RV		 1399 return 1;
1400}
1401
1402/**
1403 * \brief Unmap and free network buffer
1404 * @param buf buffer
1405 */
1406static void free_netbuf(void *buf)
1407{
1408 struct sk_buff *skb;
1409 struct octnet_buf_free_info *finfo;
1410 struct lio *lio;
1411
1412 finfo = (struct octnet_buf_free_info *)buf;
1413 skb = finfo->skb;
1414 lio = finfo->lio;
1415
1416 dma_unmap_single(&lio->oct_dev->pci_dev->dev, finfo->dptr, skb->len,
1417 DMA_TO_DEVICE);
1418
1419 check_txq_state(lio, skb);
1420
cabeb13b 1421 tx_buffer_free(skb);
f21fb3ed
RV		 1422}
1423
1424/**
1425 * \brief Unmap and free gather buffer
1426 * @param buf buffer
1427 */
1428static void free_netsgbuf(void *buf)
1429{
1430 struct octnet_buf_free_info *finfo;
1431 struct sk_buff *skb;
1432 struct lio *lio;
1433 struct octnic_gather *g;
fcd2b5e3 1434 int i, frags, iq;
f21fb3ed
RV		 1435
1436 finfo = (struct octnet_buf_free_info *)buf;
1437 skb = finfo->skb;
1438 lio = finfo->lio;
1439 g = finfo->g;
1440 frags = skb_shinfo(skb)->nr_frags;
1441
1442 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1443 g->sg[0].ptr[0], (skb->len - skb->data_len),
1444 DMA_TO_DEVICE);
1445
1446 i = 1;
1447 while (frags--) {
1448 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1449
1450 pci_unmap_page((lio->oct_dev)->pci_dev,
1451 g->sg[(i >> 2)].ptr[(i & 3)],
1452 frag->size, DMA_TO_DEVICE);
1453 i++;
1454 }
1455
fcd2b5e3
RV		 1456 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
1457 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
f21fb3ed 1458
fcd2b5e3
RV		 1459 iq = skb_iq(lio, skb);
1460 spin_lock(&lio->glist_lock[iq]);
1461 list_add_tail(&g->list, &lio->glist[iq]);
1462 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1463
1464 check_txq_state(lio, skb); /* mq support: sub-queue state check */
1465
cabeb13b 1466 tx_buffer_free(skb);
f21fb3ed
RV		 1467}
1468
1469/**
1470 * \brief Unmap and free gather buffer with response
1471 * @param buf buffer
1472 */
1473static void free_netsgbuf_with_resp(void *buf)
1474{
1475 struct octeon_soft_command *sc;
1476 struct octnet_buf_free_info *finfo;
1477 struct sk_buff *skb;
1478 struct lio *lio;
1479 struct octnic_gather *g;
fcd2b5e3 1480 int i, frags, iq;
f21fb3ed
RV		 1481
1482 sc = (struct octeon_soft_command *)buf;
1483 skb = (struct sk_buff *)sc->callback_arg;
1484 finfo = (struct octnet_buf_free_info *)&skb->cb;
1485
1486 lio = finfo->lio;
1487 g = finfo->g;
1488 frags = skb_shinfo(skb)->nr_frags;
1489
1490 dma_unmap_single(&lio->oct_dev->pci_dev->dev,
1491 g->sg[0].ptr[0], (skb->len - skb->data_len),
1492 DMA_TO_DEVICE);
1493
1494 i = 1;
1495 while (frags--) {
1496 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i - 1];
1497
1498 pci_unmap_page((lio->oct_dev)->pci_dev,
1499 g->sg[(i >> 2)].ptr[(i & 3)],
1500 frag->size, DMA_TO_DEVICE);
1501 i++;
1502 }
1503
fcd2b5e3
RV		 1504 dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
1505 g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
f21fb3ed 1506
fcd2b5e3
RV		 1507 iq = skb_iq(lio, skb);
1508
1509 spin_lock(&lio->glist_lock[iq]);
1510 list_add_tail(&g->list, &lio->glist[iq]);
1511 spin_unlock(&lio->glist_lock[iq]);
f21fb3ed
RV		 1512
1513 /* Don't free the skb yet */
1514
1515 check_txq_state(lio, skb);
1516}
1517
1518/**
1519 * \brief Adjust ptp frequency
1520 * @param ptp PTP clock info
1521 * @param ppb how much to adjust by, in parts-per-billion
1522 */
1523static int liquidio_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
1524{
1525 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1526 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1527 u64 comp, delta;
1528 unsigned long flags;
1529 bool neg_adj = false;
1530
1531 if (ppb < 0) {
1532 neg_adj = true;
1533 ppb = -ppb;
1534 }
1535
1536 /* The hardware adds the clock compensation value to the
1537 * PTP clock on every coprocessor clock cycle, so we
1538 * compute the delta in terms of coprocessor clocks.
1539 */
1540 delta = (u64)ppb << 32;
1541 do_div(delta, oct->coproc_clock_rate);
1542
1543 spin_lock_irqsave(&lio->ptp_lock, flags);
1544 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP);
1545 if (neg_adj)
1546 comp -= delta;
1547 else
1548 comp += delta;
1549 lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP);
1550 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1551
1552 return 0;
1553}
1554
1555/**
1556 * \brief Adjust ptp time
1557 * @param ptp PTP clock info
1558 * @param delta how much to adjust by, in nanosecs
1559 */
1560static int liquidio_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
1561{
1562 unsigned long flags;
1563 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1564
1565 spin_lock_irqsave(&lio->ptp_lock, flags);
1566 lio->ptp_adjust += delta;
1567 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1568
1569 return 0;
1570}
1571
1572/**
1573 * \brief Get hardware clock time, including any adjustment
1574 * @param ptp PTP clock info
1575 * @param ts timespec
1576 */
1577static int liquidio_ptp_gettime(struct ptp_clock_info *ptp,
1578 struct timespec64 *ts)
1579{
1580 u64 ns;
f21fb3ed
RV		 1581 unsigned long flags;
1582 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1583 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1584
1585 spin_lock_irqsave(&lio->ptp_lock, flags);
1586 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI);
1587 ns += lio->ptp_adjust;
1588 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1589
286af315 1590 *ts = ns_to_timespec64(ns);
f21fb3ed
RV		 1591
1592 return 0;
1593}
1594
1595/**
1596 * \brief Set hardware clock time. Reset adjustment
1597 * @param ptp PTP clock info
1598 * @param ts timespec
1599 */
1600static int liquidio_ptp_settime(struct ptp_clock_info *ptp,
1601 const struct timespec64 *ts)
1602{
1603 u64 ns;
1604 unsigned long flags;
1605 struct lio *lio = container_of(ptp, struct lio, ptp_info);
1606 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1607
1608 ns = timespec_to_ns(ts);
1609
1610 spin_lock_irqsave(&lio->ptp_lock, flags);
1611 lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI);
1612 lio->ptp_adjust = 0;
1613 spin_unlock_irqrestore(&lio->ptp_lock, flags);
1614
1615 return 0;
1616}
1617
1618/**
1619 * \brief Check if PTP is enabled
1620 * @param ptp PTP clock info
1621 * @param rq request
1622 * @param on is it on
1623 */
a7d5a3dc
RV		 1624static int
1625liquidio_ptp_enable(struct ptp_clock_info *ptp __attribute__((unused)),
1626 struct ptp_clock_request *rq __attribute__((unused)),
1627 int on __attribute__((unused)))
f21fb3ed
RV		 1628{
1629 return -EOPNOTSUPP;
1630}
1631
1632/**
1633 * \brief Open PTP clock source
1634 * @param netdev network device
1635 */
1636static void oct_ptp_open(struct net_device *netdev)
1637{
1638 struct lio *lio = GET_LIO(netdev);
1639 struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
1640
1641 spin_lock_init(&lio->ptp_lock);
1642
1643 snprintf(lio->ptp_info.name, 16, "%s", netdev->name);
1644 lio->ptp_info.owner = THIS_MODULE;
1645 lio->ptp_info.max_adj = 250000000;
1646 lio->ptp_info.n_alarm = 0;
1647 lio->ptp_info.n_ext_ts = 0;
1648 lio->ptp_info.n_per_out = 0;
1649 lio->ptp_info.pps = 0;
1650 lio->ptp_info.adjfreq = liquidio_ptp_adjfreq;
1651 lio->ptp_info.adjtime = liquidio_ptp_adjtime;
1652 lio->ptp_info.gettime64 = liquidio_ptp_gettime;
1653 lio->ptp_info.settime64 = liquidio_ptp_settime;
1654 lio->ptp_info.enable = liquidio_ptp_enable;
1655
1656 lio->ptp_adjust = 0;
1657
1658 lio->ptp_clock = ptp_clock_register(&lio->ptp_info,
1659 &oct->pci_dev->dev);
1660
1661 if (IS_ERR(lio->ptp_clock))
1662 lio->ptp_clock = NULL;
1663}
1664
1665/**
1666 * \brief Init PTP clock
1667 * @param oct octeon device
1668 */
1669static void liquidio_ptp_init(struct octeon_device *oct)
1670{
1671 u64 clock_comp, cfg;
1672
1673 clock_comp = (u64)NSEC_PER_SEC << 32;
1674 do_div(clock_comp, oct->coproc_clock_rate);
1675 lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP);
1676
1677 /* Enable */
1678 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG);
1679 lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG);
1680}
1681
1682/**
1683 * \brief Load firmware to device
1684 * @param oct octeon device
1685 *
1686 * Maps device to firmware filename, requests firmware, and downloads it
1687 */
1688static int load_firmware(struct octeon_device *oct)
1689{
1690 int ret = 0;
1691 const struct firmware *fw;
1692 char fw_name[LIO_MAX_FW_FILENAME_LEN];
1693 char *tmp_fw_type;
1694
1695 if (strncmp(fw_type, LIO_FW_NAME_TYPE_NONE,
1696 sizeof(LIO_FW_NAME_TYPE_NONE)) == 0) {
1697 dev_info(&oct->pci_dev->dev, "Skipping firmware load\n");
1698 return ret;
1699 }
1700
1701 if (fw_type[0] == '\0')
1702 tmp_fw_type = LIO_FW_NAME_TYPE_NIC;
1703 else
1704 tmp_fw_type = fw_type;
1705
1706 sprintf(fw_name, "%s%s%s_%s%s", LIO_FW_DIR, LIO_FW_BASE_NAME,
1707 octeon_get_conf(oct)->card_name, tmp_fw_type,
1708 LIO_FW_NAME_SUFFIX);
1709
1710 ret = request_firmware(&fw, fw_name, &oct->pci_dev->dev);
1711 if (ret) {
1712 dev_err(&oct->pci_dev->dev, "Request firmware failed. Could not find file %s.\n.",
1713 fw_name);
d3d7e6c6 1714 release_firmware(fw);
f21fb3ed
RV		 1715 return ret;
1716 }
1717
1718 ret = octeon_download_firmware(oct, fw->data, fw->size);
1719
1720 release_firmware(fw);
1721
1722 return ret;
1723}
1724
1725/**
1726 * \brief Setup output queue
1727 * @param oct octeon device
1728 * @param q_no which queue
1729 * @param num_descs how many descriptors
1730 * @param desc_size size of each descriptor
1731 * @param app_ctx application context
1732 */
1733static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs,
1734 int desc_size, void *app_ctx)
1735{
1736 int ret_val = 0;
1737
1738 dev_dbg(&oct->pci_dev->dev, "Creating Droq: %d\n", q_no);
1739 /* droq creation and local register settings. */
1740 ret_val = octeon_create_droq(oct, q_no, num_descs, desc_size, app_ctx);
08a965ec 1741 if (ret_val < 0)
f21fb3ed
RV		 1742 return ret_val;
1743
1744 if (ret_val == 1) {
1745 dev_dbg(&oct->pci_dev->dev, "Using default droq %d\n", q_no);
1746 return 0;
1747 }
1748 /* tasklet creation for the droq */
1749
1750 /* Enable the droq queues */
1751 octeon_set_droq_pkt_op(oct, q_no, 1);
1752
1753 /* Send Credit for Octeon Output queues. Credits are always
1754 * sent after the output queue is enabled.
1755 */
1756 writel(oct->droq[q_no]->max_count,
1757 oct->droq[q_no]->pkts_credit_reg);
1758
1759 return ret_val;
1760}
1761
1762/**
1763 * \brief Callback for getting interface configuration
1764 * @param status status of request
1765 * @param buf pointer to resp structure
1766 */
1767static void if_cfg_callback(struct octeon_device *oct,
a7d5a3dc 1768 u32 status __attribute__((unused)),
f21fb3ed
RV		 1769 void *buf)
1770{
1771 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
1772 struct liquidio_if_cfg_resp *resp;
1773 struct liquidio_if_cfg_context *ctx;
1774
1775 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
1776 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
1777
1778 oct = lio_get_device(ctx->octeon_id);
1779 if (resp->status)
1780 dev_err(&oct->pci_dev->dev, "nic if cfg instruction failed. Status: %llx\n",
1781 CVM_CAST64(resp->status));
a7d5a3dc 1782 WRITE_ONCE(ctx->cond, 1);
f21fb3ed 1783
d3d7e6c6
RV		 1784 snprintf(oct->fw_info.liquidio_firmware_version, 32, "%s",
1785 resp->cfg_info.liquidio_firmware_version);
1786
f21fb3ed
RV		 1787 /* This barrier is required to be sure that the response has been
1788 * written fully before waking up the handler
1789 */
1790 wmb();
1791
1792 wake_up_interruptible(&ctx->wc);
1793}
1794
1795/**
1796 * \brief Select queue based on hash
1797 * @param dev Net device
1798 * @param skb sk_buff structure
1799 * @returns selected queue number
1800 */
1801static u16 select_q(struct net_device *dev, struct sk_buff *skb,
a7d5a3dc
RV		 1802 void *accel_priv __attribute__((unused)),
1803 select_queue_fallback_t fallback __attribute__((unused)))
f21fb3ed 1804{
26236fa9 1805 u32 qindex = 0;
f21fb3ed
RV		 1806 struct lio *lio;
1807
1808 lio = GET_LIO(dev);
26236fa9
RV		 1809 qindex = skb_tx_hash(dev, skb);
1810
1811 return (u16)(qindex % (lio->linfo.num_txpciq));
f21fb3ed
RV		 1812}
1813
1814/** Routine to push packets arriving on Octeon interface upto network layer.
1815 * @param oct_id - octeon device id.
1816 * @param skbuff - skbuff struct to be passed to network layer.
1817 * @param len - size of total data received.
1818 * @param rh - Control header associated with the packet
1819 * @param param - additional control data with the packet
0cece6c5 1820 * @param arg - farg registered in droq_ops
f21fb3ed
RV		 1821 */
1822static void
a7d5a3dc 1823liquidio_push_packet(u32 octeon_id __attribute__((unused)),
f21fb3ed
RV		 1824 void *skbuff,
1825 u32 len,
1826 union octeon_rh *rh,
0cece6c5
RV		 1827 void *param,
1828 void *arg)
f21fb3ed
RV		 1829{
1830 struct napi_struct *napi = param;
f21fb3ed
RV		 1831 struct sk_buff *skb = (struct sk_buff *)skbuff;
1832 struct skb_shared_hwtstamps *shhwtstamps;
1833 u64 ns;
0da0b77c 1834 u16 vtag = 0;
0cece6c5 1835 struct net_device *netdev = (struct net_device *)arg;
f21fb3ed
RV		 1836 struct octeon_droq *droq = container_of(param, struct octeon_droq,
1837 napi);
1838 if (netdev) {
1839 int packet_was_received;
1840 struct lio *lio = GET_LIO(netdev);
a5b37888 1841 struct octeon_device *oct = lio->oct_dev;
f21fb3ed
RV		 1842
1843 /* Do not proceed if the interface is not in RUNNING state. */
1844 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) {
1845 recv_buffer_free(skb);
1846 droq->stats.rx_dropped++;
1847 return;
1848 }
1849
1850 skb->dev = netdev;
1851
26236fa9 1852 skb_record_rx_queue(skb, droq->q_no);
cabeb13b
RV		 1853 if (likely(len > MIN_SKB_SIZE)) {
1854 struct octeon_skb_page_info *pg_info;
1855 unsigned char *va;
1856
1857 pg_info = ((struct octeon_skb_page_info *)(skb->cb));
1858 if (pg_info->page) {
1859 /* For Paged allocation use the frags */
1860 va = page_address(pg_info->page) +
1861 pg_info->page_offset;
1862 memcpy(skb->data, va, MIN_SKB_SIZE);
1863 skb_put(skb, MIN_SKB_SIZE);
1864 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1865 pg_info->page,
1866 pg_info->page_offset +
1867 MIN_SKB_SIZE,
1868 len - MIN_SKB_SIZE,
1869 LIO_RXBUFFER_SZ);
1870 }
1871 } else {
1872 struct octeon_skb_page_info *pg_info =
1873 ((struct octeon_skb_page_info *)(skb->cb));
1874 skb_copy_to_linear_data(skb, page_address(pg_info->page)
1875 + pg_info->page_offset, len);
1876 skb_put(skb, len);
1877 put_page(pg_info->page);
1878 }
26236fa9 1879
a5b37888
RV		 1880 if (((oct->chip_id == OCTEON_CN66XX) ||
1881 (oct->chip_id == OCTEON_CN68XX)) &&
1882 ptp_enable) {
1883 if (rh->r_dh.has_hwtstamp) {
1884 /* timestamp is included from the hardware at
1885 * the beginning of the packet.
f21fb3ed 1886 */
a5b37888
RV		 1887 if (ifstate_check
1888 (lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED)) {
1889 /* Nanoseconds are in the first 64-bits
1890 * of the packet.
1891 */
1892 memcpy(&ns, (skb->data), sizeof(ns));
1893 shhwtstamps = skb_hwtstamps(skb);
1894 shhwtstamps->hwtstamp =
1895 ns_to_ktime(ns +
1896 lio->ptp_adjust);
1897 }
1898 skb_pull(skb, sizeof(ns));
f21fb3ed 1899 }
f21fb3ed
RV		 1900 }
1901
1902 skb->protocol = eth_type_trans(skb, skb->dev);
f21fb3ed 1903 if ((netdev->features & NETIF_F_RXCSUM) &&
01fb237a
RV		 1904 (((rh->r_dh.encap_on) &&
1905 (rh->r_dh.csum_verified & CNNIC_TUN_CSUM_VERIFIED)) ||
1906 (!(rh->r_dh.encap_on) &&
1907 (rh->r_dh.csum_verified & CNNIC_CSUM_VERIFIED))))
f21fb3ed
RV		 1908 /* checksum has already been verified */
1909 skb->ip_summed = CHECKSUM_UNNECESSARY;
1910 else
1911 skb->ip_summed = CHECKSUM_NONE;
1912
01fb237a
RV		 1913 /* Setting Encapsulation field on basis of status received
1914 * from the firmware
1915 */
1916 if (rh->r_dh.encap_on) {
1917 skb->encapsulation = 1;
1918 skb->csum_level = 1;
1919 droq->stats.rx_vxlan++;
1920 }
1921
0da0b77c
RV		 1922 /* inbound VLAN tag */
1923 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1924 (rh->r_dh.vlan != 0)) {
1925 u16 vid = rh->r_dh.vlan;
1926 u16 priority = rh->r_dh.priority;
1927
1928 vtag = priority << 13 | vid;
1929 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
1930 }
1931
f21fb3ed
RV		 1932 packet_was_received = napi_gro_receive(napi, skb) != GRO_DROP;
1933
1934 if (packet_was_received) {
1935 droq->stats.rx_bytes_received += len;
1936 droq->stats.rx_pkts_received++;
1937 netdev->last_rx = jiffies;
1938 } else {
1939 droq->stats.rx_dropped++;
1940 netif_info(lio, rx_err, lio->netdev,
1941 "droq:%d error rx_dropped:%llu\n",
1942 droq->q_no, droq->stats.rx_dropped);
1943 }
1944
1945 } else {
1946 recv_buffer_free(skb);
1947 }
1948}
1949
1950/**
1951 * \brief wrapper for calling napi_schedule
1952 * @param param parameters to pass to napi_schedule
1953 *
1954 * Used when scheduling on different CPUs
1955 */
1956static void napi_schedule_wrapper(void *param)
1957{
1958 struct napi_struct *napi = param;
1959
1960 napi_schedule(napi);
1961}
1962
1963/**
1964 * \brief callback when receive interrupt occurs and we are in NAPI mode
1965 * @param arg pointer to octeon output queue
1966 */
1967static void liquidio_napi_drv_callback(void *arg)
1968{
1969 struct octeon_droq *droq = arg;
1970 int this_cpu = smp_processor_id();
1971
1972 if (droq->cpu_id == this_cpu) {
1973 napi_schedule(&droq->napi);
1974 } else {
1975 struct call_single_data *csd = &droq->csd;
1976
1977 csd->func = napi_schedule_wrapper;
1978 csd->info = &droq->napi;
1979 csd->flags = 0;
1980
1981 smp_call_function_single_async(droq->cpu_id, csd);
1982 }
1983}
1984
f21fb3ed
RV		 1985/**
1986 * \brief Entry point for NAPI polling
1987 * @param napi NAPI structure
1988 * @param budget maximum number of items to process
1989 */
1990static int liquidio_napi_poll(struct napi_struct *napi, int budget)
1991{
1992 struct octeon_droq *droq;
1993 int work_done;
9a96bde4
RV		 1994 int tx_done = 0, iq_no;
1995 struct octeon_instr_queue *iq;
1996 struct octeon_device *oct;
f21fb3ed
RV		 1997
1998 droq = container_of(napi, struct octeon_droq, napi);
9a96bde4
RV		 1999 oct = droq->oct_dev;
2000 iq_no = droq->q_no;
2001 /* Handle Droq descriptors */
2002 work_done = octeon_process_droq_poll_cmd(oct, droq->q_no,
2003 POLL_EVENT_PROCESS_PKTS,
2004 budget);
f21fb3ed 2005
9a96bde4
RV		 2006 /* Flush the instruction queue */
2007 iq = oct->instr_queue[iq_no];
2008 if (iq) {
2009 /* Process iq buffers with in the budget limits */
2010 tx_done = octeon_flush_iq(oct, iq, 1, budget);
2011 /* Update iq read-index rather than waiting for next interrupt.
2012 * Return back if tx_done is false.
2013 */
2014 update_txq_status(oct, iq_no);
2015 /*tx_done = (iq->flush_index == iq->octeon_read_index);*/
2016 } else {
2017 dev_err(&oct->pci_dev->dev, "%s: iq (%d) num invalid\n",
2018 __func__, iq_no);
2019 }
f21fb3ed 2020
9a96bde4 2021 if ((work_done < budget) && (tx_done)) {
f21fb3ed
RV		 2022 napi_complete(napi);
2023 octeon_process_droq_poll_cmd(droq->oct_dev, droq->q_no,
2024 POLL_EVENT_ENABLE_INTR, 0);
2025 return 0;
2026 }
2027
9a96bde4 2028 return (!tx_done) ? (budget) : (work_done);
f21fb3ed
RV		 2029}
2030
2031/**
2032 * \brief Setup input and output queues
2033 * @param octeon_dev octeon device
a2c64b67 2034 * @param ifidx Interface Index
f21fb3ed
RV		 2035 *
2036 * Note: Queues are with respect to the octeon device. Thus
2037 * an input queue is for egress packets, and output queues
2038 * are for ingress packets.
2039 */
2040static inline int setup_io_queues(struct octeon_device *octeon_dev,
0cece6c5 2041 int ifidx)
f21fb3ed 2042{
0cece6c5
RV		 2043 struct octeon_droq_ops droq_ops;
2044 struct net_device *netdev;
f21fb3ed
RV		 2045 static int cpu_id;
2046 static int cpu_id_modulus;
2047 struct octeon_droq *droq;
2048 struct napi_struct *napi;
2049 int q, q_no, retval = 0;
2050 struct lio *lio;
2051 int num_tx_descs;
2052
0cece6c5
RV		 2053 netdev = octeon_dev->props[ifidx].netdev;
2054
2055 lio = GET_LIO(netdev);
f21fb3ed 2056
0cece6c5 2057 memset(&droq_ops, 0, sizeof(struct octeon_droq_ops));
f21fb3ed 2058
0cece6c5
RV		 2059 droq_ops.fptr = liquidio_push_packet;
2060 droq_ops.farg = (void *)netdev;
2061
2062 droq_ops.poll_mode = 1;
2063 droq_ops.napi_fn = liquidio_napi_drv_callback;
2064 cpu_id = 0;
2065 cpu_id_modulus = num_present_cpus();
f21fb3ed
RV		 2066
2067 /* set up DROQs. */
2068 for (q = 0; q < lio->linfo.num_rxpciq; q++) {
26236fa9
RV		 2069 q_no = lio->linfo.rxpciq[q].s.q_no;
2070 dev_dbg(&octeon_dev->pci_dev->dev,
2071 "setup_io_queues index:%d linfo.rxpciq.s.q_no:%d\n",
2072 q, q_no);
f21fb3ed
RV		 2073 retval = octeon_setup_droq(octeon_dev, q_no,
2074 CFG_GET_NUM_RX_DESCS_NIC_IF
2075 (octeon_get_conf(octeon_dev),
2076 lio->ifidx),
2077 CFG_GET_NUM_RX_BUF_SIZE_NIC_IF
2078 (octeon_get_conf(octeon_dev),
2079 lio->ifidx), NULL);
2080 if (retval) {
2081 dev_err(&octeon_dev->pci_dev->dev,
32581245 2082 "%s : Runtime DROQ(RxQ) creation failed.\n",
f21fb3ed
RV		 2083 __func__);
2084 return 1;
2085 }
2086
2087 droq = octeon_dev->droq[q_no];
2088 napi = &droq->napi;
0cece6c5
RV		 2089 dev_dbg(&octeon_dev->pci_dev->dev,
2090 "netif_napi_add netdev:%llx oct:%llx\n",
2091 (u64)netdev,
2092 (u64)octeon_dev);
2093 netif_napi_add(netdev, napi, liquidio_napi_poll, 64);
f21fb3ed
RV		 2094
2095 /* designate a CPU for this droq */
2096 droq->cpu_id = cpu_id;
2097 cpu_id++;
2098 if (cpu_id >= cpu_id_modulus)
2099 cpu_id = 0;
2100
2101 octeon_register_droq_ops(octeon_dev, q_no, &droq_ops);
2102 }
2103
2104 /* set up IQs. */
2105 for (q = 0; q < lio->linfo.num_txpciq; q++) {
2106 num_tx_descs = CFG_GET_NUM_TX_DESCS_NIC_IF(octeon_get_conf
2107 (octeon_dev),
2108 lio->ifidx);
0cece6c5
RV		 2109 retval = octeon_setup_iq(octeon_dev, ifidx, q,
2110 lio->linfo.txpciq[q], num_tx_descs,
2111 netdev_get_tx_queue(netdev, q));
f21fb3ed
RV		 2112 if (retval) {
2113 dev_err(&octeon_dev->pci_dev->dev,
2114 " %s : Runtime IQ(TxQ) creation failed.\n",
2115 __func__);
2116 return 1;
2117 }
2118 }
2119
2120 return 0;
2121}
2122
2123/**
2124 * \brief Poll routine for checking transmit queue status
2125 * @param work work_struct data structure
2126 */
2127static void octnet_poll_check_txq_status(struct work_struct *work)
2128{
2129 struct cavium_wk *wk = (struct cavium_wk *)work;
2130 struct lio *lio = (struct lio *)wk->ctxptr;
2131
2132 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING))
2133 return;
2134
2135 check_txq_status(lio);
2136 queue_delayed_work(lio->txq_status_wq.wq,
2137 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2138}
2139
2140/**
2141 * \brief Sets up the txq poll check
2142 * @param netdev network device
2143 */
2144static inline void setup_tx_poll_fn(struct net_device *netdev)
2145{
2146 struct lio *lio = GET_LIO(netdev);
2147 struct octeon_device *oct = lio->oct_dev;
2148
292b9dab
BS		 2149 lio->txq_status_wq.wq = alloc_workqueue("txq-status",
2150 WQ_MEM_RECLAIM, 0);
f21fb3ed
RV		 2151 if (!lio->txq_status_wq.wq) {
2152 dev_err(&oct->pci_dev->dev, "unable to create cavium txq status wq\n");
2153 return;
2154 }
2155 INIT_DELAYED_WORK(&lio->txq_status_wq.wk.work,
2156 octnet_poll_check_txq_status);
2157 lio->txq_status_wq.wk.ctxptr = lio;
2158 queue_delayed_work(lio->txq_status_wq.wq,
2159 &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
2160}
2161
9a96bde4
RV		 2162static inline void cleanup_tx_poll_fn(struct net_device *netdev)
2163{
2164 struct lio *lio = GET_LIO(netdev);
2165
2166 cancel_delayed_work_sync(&lio->txq_status_wq.wk.work);
2167 destroy_workqueue(lio->txq_status_wq.wq);
2168}
2169
f21fb3ed
RV		 2170/**
2171 * \brief Net device open for LiquidIO
2172 * @param netdev network device
2173 */
2174static int liquidio_open(struct net_device *netdev)
2175{
2176 struct lio *lio = GET_LIO(netdev);
2177 struct octeon_device *oct = lio->oct_dev;
2178 struct napi_struct *napi, *n;
2179
9a96bde4
RV		 2180 if (oct->props[lio->ifidx].napi_enabled == 0) {
2181 list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
2182 napi_enable(napi);
2183
2184 oct->props[lio->ifidx].napi_enabled = 1;
2185 }
f21fb3ed
RV		 2186
2187 oct_ptp_open(netdev);
2188
2189 ifstate_set(lio, LIO_IFSTATE_RUNNING);
9a96bde4 2190
f21fb3ed 2191 setup_tx_poll_fn(netdev);
9a96bde4 2192
f21fb3ed
RV		 2193 start_txq(netdev);
2194
2195 netif_info(lio, ifup, lio->netdev, "Interface Open, ready for traffic\n");
f21fb3ed
RV		 2196
2197 /* tell Octeon to start forwarding packets to host */
2198 send_rx_ctrl_cmd(lio, 1);
2199
2200 /* Ready for link status updates */
2201 lio->intf_open = 1;
2202
2203 dev_info(&oct->pci_dev->dev, "%s interface is opened\n",
2204 netdev->name);
2205
2206 return 0;
2207}
2208
2209/**
2210 * \brief Net device stop for LiquidIO
2211 * @param netdev network device
2212 */
2213static int liquidio_stop(struct net_device *netdev)
2214{
f21fb3ed
RV		 2215 struct lio *lio = GET_LIO(netdev);
2216 struct octeon_device *oct = lio->oct_dev;
2217
9a96bde4
RV		 2218 ifstate_reset(lio, LIO_IFSTATE_RUNNING);
2219
2220 netif_tx_disable(netdev);
2221
f21fb3ed 2222 /* Inform that netif carrier is down */
9a96bde4 2223 netif_carrier_off(netdev);
f21fb3ed 2224 lio->intf_open = 0;
0cece6c5
RV		 2225 lio->linfo.link.s.link_up = 0;
2226 lio->link_changes++;
f21fb3ed 2227
9a96bde4
RV		 2228 /* Pause for a moment and wait for Octeon to flush out (to the wire) any
2229 * egress packets that are in-flight.
2230 */
2231 set_current_state(TASK_INTERRUPTIBLE);
2232 schedule_timeout(msecs_to_jiffies(100));
f21fb3ed 2233
9a96bde4 2234 /* Now it should be safe to tell Octeon that nic interface is down. */
f21fb3ed
RV		 2235 send_rx_ctrl_cmd(lio, 0);
2236
9a96bde4 2237 cleanup_tx_poll_fn(netdev);
f21fb3ed
RV		 2238
2239 if (lio->ptp_clock) {
2240 ptp_clock_unregister(lio->ptp_clock);
2241 lio->ptp_clock = NULL;
2242 }
2243
f21fb3ed 2244 dev_info(&oct->pci_dev->dev, "%s interface is stopped\n", netdev->name);
f21fb3ed
RV		 2245
2246 return 0;
2247}
2248
f21fb3ed
RV		 2249/**
2250 * \brief Converts a mask based on net device flags
2251 * @param netdev network device
2252 *
2253 * This routine generates a octnet_ifflags mask from the net device flags
2254 * received from the OS.
2255 */
2256static inline enum octnet_ifflags get_new_flags(struct net_device *netdev)
2257{
2258 enum octnet_ifflags f = OCTNET_IFFLAG_UNICAST;
2259
2260 if (netdev->flags & IFF_PROMISC)
2261 f |= OCTNET_IFFLAG_PROMISC;
2262
2263 if (netdev->flags & IFF_ALLMULTI)
2264 f |= OCTNET_IFFLAG_ALLMULTI;
2265
2266 if (netdev->flags & IFF_MULTICAST) {
2267 f |= OCTNET_IFFLAG_MULTICAST;
2268
2269 /* Accept all multicast addresses if there are more than we
2270 * can handle
2271 */
2272 if (netdev_mc_count(netdev) > MAX_OCTEON_MULTICAST_ADDR)
2273 f |= OCTNET_IFFLAG_ALLMULTI;
2274 }
2275
2276 if (netdev->flags & IFF_BROADCAST)
2277 f |= OCTNET_IFFLAG_BROADCAST;
2278
2279 return f;
2280}
2281
2282/**
2283 * \brief Net device set_multicast_list
2284 * @param netdev network device
2285 */
2286static void liquidio_set_mcast_list(struct net_device *netdev)
2287{
2288 struct lio *lio = GET_LIO(netdev);
2289 struct octeon_device *oct = lio->oct_dev;
2290 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2291 struct netdev_hw_addr *ha;
2292 u64 *mc;
a7d5a3dc 2293 int ret;
f21fb3ed
RV		 2294 int mc_count = min(netdev_mc_count(netdev), MAX_OCTEON_MULTICAST_ADDR);
2295
2296 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2297
2298 /* Create a ctrl pkt command to be sent to core app. */
2299 nctrl.ncmd.u64 = 0;
2300 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_MULTI_LIST;
0cece6c5
RV		 2301 nctrl.ncmd.s.param1 = get_new_flags(netdev);
2302 nctrl.ncmd.s.param2 = mc_count;
f21fb3ed 2303 nctrl.ncmd.s.more = mc_count;
0cece6c5 2304 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2305 nctrl.netpndev = (u64)netdev;
2306 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2307
2308 /* copy all the addresses into the udd */
f21fb3ed
RV		 2309 mc = &nctrl.udd[0];
2310 netdev_for_each_mc_addr(ha, netdev) {
2311 *mc = 0;
2312 memcpy(((u8 *)mc) + 2, ha->addr, ETH_ALEN);
2313 /* no need to swap bytes */
2314
2315 if (++mc > &nctrl.udd[mc_count])
2316 break;
2317 }
2318
2319 /* Apparently, any activity in this call from the kernel has to
2320 * be atomic. So we won't wait for response.
2321 */
2322 nctrl.wait_time = 0;
2323
0cece6c5 2324 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2325 if (ret < 0) {
2326 dev_err(&oct->pci_dev->dev, "DEVFLAGS change failed in core (ret: 0x%x)\n",
2327 ret);
2328 }
2329}
2330
2331/**
2332 * \brief Net device set_mac_address
2333 * @param netdev network device
2334 */
2335static int liquidio_set_mac(struct net_device *netdev, void *p)
2336{
2337 int ret = 0;
2338 struct lio *lio = GET_LIO(netdev);
2339 struct octeon_device *oct = lio->oct_dev;
2340 struct sockaddr *addr = (struct sockaddr *)p;
2341 struct octnic_ctrl_pkt nctrl;
f21fb3ed 2342
0cece6c5 2343 if (!is_valid_ether_addr(addr->sa_data))
f21fb3ed
RV		 2344 return -EADDRNOTAVAIL;
2345
2346 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2347
2348 nctrl.ncmd.u64 = 0;
2349 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
0cece6c5 2350 nctrl.ncmd.s.param1 = 0;
f21fb3ed 2351 nctrl.ncmd.s.more = 1;
0cece6c5 2352 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2353 nctrl.netpndev = (u64)netdev;
2354 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2355 nctrl.wait_time = 100;
2356
2357 nctrl.udd[0] = 0;
2358 /* The MAC Address is presented in network byte order. */
2359 memcpy((u8 *)&nctrl.udd[0] + 2, addr->sa_data, ETH_ALEN);
2360
0cece6c5 2361 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2362 if (ret < 0) {
2363 dev_err(&oct->pci_dev->dev, "MAC Address change failed\n");
2364 return -ENOMEM;
2365 }
2366 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2367 memcpy(((u8 *)&lio->linfo.hw_addr) + 2, addr->sa_data, ETH_ALEN);
2368
2369 return 0;
2370}
2371
2372/**
2373 * \brief Net device get_stats
2374 * @param netdev network device
2375 */
2376static struct net_device_stats *liquidio_get_stats(struct net_device *netdev)
2377{
2378 struct lio *lio = GET_LIO(netdev);
2379 struct net_device_stats *stats = &netdev->stats;
2380 struct octeon_device *oct;
2381 u64 pkts = 0, drop = 0, bytes = 0;
2382 struct oct_droq_stats *oq_stats;
2383 struct oct_iq_stats *iq_stats;
2384 int i, iq_no, oq_no;
2385
2386 oct = lio->oct_dev;
2387
2388 for (i = 0; i < lio->linfo.num_txpciq; i++) {
26236fa9 2389 iq_no = lio->linfo.txpciq[i].s.q_no;
f21fb3ed
RV		 2390 iq_stats = &oct->instr_queue[iq_no]->stats;
2391 pkts += iq_stats->tx_done;
2392 drop += iq_stats->tx_dropped;
2393 bytes += iq_stats->tx_tot_bytes;
2394 }
2395
2396 stats->tx_packets = pkts;
2397 stats->tx_bytes = bytes;
2398 stats->tx_dropped = drop;
2399
2400 pkts = 0;
2401 drop = 0;
2402 bytes = 0;
2403
2404 for (i = 0; i < lio->linfo.num_rxpciq; i++) {
26236fa9 2405 oq_no = lio->linfo.rxpciq[i].s.q_no;
f21fb3ed
RV		 2406 oq_stats = &oct->droq[oq_no]->stats;
2407 pkts += oq_stats->rx_pkts_received;
2408 drop += (oq_stats->rx_dropped +
2409 oq_stats->dropped_nodispatch +
2410 oq_stats->dropped_toomany +
2411 oq_stats->dropped_nomem);
2412 bytes += oq_stats->rx_bytes_received;
2413 }
2414
2415 stats->rx_bytes = bytes;
2416 stats->rx_packets = pkts;
2417 stats->rx_dropped = drop;
2418
2419 return stats;
2420}
2421
2422/**
2423 * \brief Net device change_mtu
2424 * @param netdev network device
2425 */
2426static int liquidio_change_mtu(struct net_device *netdev, int new_mtu)
2427{
2428 struct lio *lio = GET_LIO(netdev);
2429 struct octeon_device *oct = lio->oct_dev;
2430 struct octnic_ctrl_pkt nctrl;
f21fb3ed
RV		 2431 int ret = 0;
2432
4c2743f9
RV		 2433 /* Limit the MTU to make sure the ethernet packets are between 68 bytes
2434 * and 16000 bytes
f21fb3ed 2435 */
4c2743f9
RV		 2436 if ((new_mtu < LIO_MIN_MTU_SIZE) ||
2437 (new_mtu > LIO_MAX_MTU_SIZE)) {
f21fb3ed
RV		 2438 dev_err(&oct->pci_dev->dev, "Invalid MTU: %d\n", new_mtu);
2439 dev_err(&oct->pci_dev->dev, "Valid range %d and %d\n",
4c2743f9 2440 LIO_MIN_MTU_SIZE, LIO_MAX_MTU_SIZE);
f21fb3ed
RV		 2441 return -EINVAL;
2442 }
2443
2444 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2445
2446 nctrl.ncmd.u64 = 0;
2447 nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MTU;
0cece6c5
RV		 2448 nctrl.ncmd.s.param1 = new_mtu;
2449 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
f21fb3ed
RV		 2450 nctrl.wait_time = 100;
2451 nctrl.netpndev = (u64)netdev;
2452 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2453
0cece6c5 2454 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
f21fb3ed
RV		 2455 if (ret < 0) {
2456 dev_err(&oct->pci_dev->dev, "Failed to set MTU\n");
2457 return -1;
2458 }
2459
2460 lio->mtu = new_mtu;
2461
2462 return 0;
2463}
2464
2465/**
2466 * \brief Handler for SIOCSHWTSTAMP ioctl
2467 * @param netdev network device
2468 * @param ifr interface request
2469 * @param cmd command
2470 */
a7d5a3dc 2471static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
f21fb3ed
RV		 2472{
2473 struct hwtstamp_config conf;
2474 struct lio *lio = GET_LIO(netdev);
2475
2476 if (copy_from_user(&conf, ifr->ifr_data, sizeof(conf)))
2477 return -EFAULT;
2478
2479 if (conf.flags)
2480 return -EINVAL;
2481
2482 switch (conf.tx_type) {
2483 case HWTSTAMP_TX_ON:
2484 case HWTSTAMP_TX_OFF:
2485 break;
2486 default:
2487 return -ERANGE;
2488 }
2489
2490 switch (conf.rx_filter) {
2491 case HWTSTAMP_FILTER_NONE:
2492 break;
2493 case HWTSTAMP_FILTER_ALL:
2494 case HWTSTAMP_FILTER_SOME:
2495 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2496 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2497 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2498 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2499 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2500 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2501 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2502 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2503 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2504 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2505 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2506 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2507 conf.rx_filter = HWTSTAMP_FILTER_ALL;
2508 break;
2509 default:
2510 return -ERANGE;
2511 }
2512
2513 if (conf.rx_filter == HWTSTAMP_FILTER_ALL)
2514 ifstate_set(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
2515
2516 else
2517 ifstate_reset(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
2518
2519 return copy_to_user(ifr->ifr_data, &conf, sizeof(conf)) ? -EFAULT : 0;
2520}
2521
2522/**
2523 * \brief ioctl handler
2524 * @param netdev network device
2525 * @param ifr interface request
2526 * @param cmd command
2527 */
2528static int liquidio_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2529{
2530 switch (cmd) {
2531 case SIOCSHWTSTAMP:
a7d5a3dc 2532 return hwtstamp_ioctl(netdev, ifr);
f21fb3ed
RV		 2533 default:
2534 return -EOPNOTSUPP;
2535 }
2536}
2537
2538/**
2539 * \brief handle a Tx timestamp response
2540 * @param status response status
2541 * @param buf pointer to skb
2542 */
2543static void handle_timestamp(struct octeon_device *oct,
2544 u32 status,
2545 void *buf)
2546{
2547 struct octnet_buf_free_info *finfo;
2548 struct octeon_soft_command *sc;
2549 struct oct_timestamp_resp *resp;
2550 struct lio *lio;
2551 struct sk_buff *skb = (struct sk_buff *)buf;
2552
2553 finfo = (struct octnet_buf_free_info *)skb->cb;
2554 lio = finfo->lio;
2555 sc = finfo->sc;
2556 oct = lio->oct_dev;
2557 resp = (struct oct_timestamp_resp *)sc->virtrptr;
2558
2559 if (status != OCTEON_REQUEST_DONE) {
2560 dev_err(&oct->pci_dev->dev, "Tx timestamp instruction failed. Status: %llx\n",
2561 CVM_CAST64(status));
2562 resp->timestamp = 0;
2563 }
2564
2565 octeon_swap_8B_data(&resp->timestamp, 1);
2566
19a6d156 2567 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) != 0)) {
f21fb3ed
RV		 2568 struct skb_shared_hwtstamps ts;
2569 u64 ns = resp->timestamp;
2570
2571 netif_info(lio, tx_done, lio->netdev,
2572 "Got resulting SKBTX_HW_TSTAMP skb=%p ns=%016llu\n",
2573 skb, (unsigned long long)ns);
2574 ts.hwtstamp = ns_to_ktime(ns + lio->ptp_adjust);
2575 skb_tstamp_tx(skb, &ts);
2576 }
2577
2578 octeon_free_soft_command(oct, sc);
cabeb13b 2579 tx_buffer_free(skb);
f21fb3ed
RV		 2580}
2581
2582/* \brief Send a data packet that will be timestamped
2583 * @param oct octeon device
2584 * @param ndata pointer to network data
2585 * @param finfo pointer to private network data
2586 */
2587static inline int send_nic_timestamp_pkt(struct octeon_device *oct,
2588 struct octnic_data_pkt *ndata,
32581245 2589 struct octnet_buf_free_info *finfo)
f21fb3ed
RV		 2590{
2591 int retval;
2592 struct octeon_soft_command *sc;
f21fb3ed
RV		 2593 struct lio *lio;
2594 int ring_doorbell;
6a885b60 2595 u32 len;
f21fb3ed
RV		 2596
2597 lio = finfo->lio;
2598
2599 sc = octeon_alloc_soft_command_resp(oct, &ndata->cmd,
2600 sizeof(struct oct_timestamp_resp));
2601 finfo->sc = sc;
2602
2603 if (!sc) {
2604 dev_err(&oct->pci_dev->dev, "No memory for timestamped data packet\n");
2605 return IQ_SEND_FAILED;
2606 }
2607
2608 if (ndata->reqtype == REQTYPE_NORESP_NET)
2609 ndata->reqtype = REQTYPE_RESP_NET;
2610 else if (ndata->reqtype == REQTYPE_NORESP_NET_SG)
2611 ndata->reqtype = REQTYPE_RESP_NET_SG;
2612
2613 sc->callback = handle_timestamp;
2614 sc->callback_arg = finfo->skb;
2615 sc->iq_no = ndata->q_no;
2616
6a885b60 2617 len = (u32)((struct octeon_instr_ih2 *)(&sc->cmd.cmd2.ih2))->dlengsz;
f21fb3ed 2618
32581245 2619 ring_doorbell = 1;
f21fb3ed 2620 retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd,
6a885b60 2621 sc, len, ndata->reqtype);
f21fb3ed 2622
ddc173a6 2623 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 2624 dev_err(&oct->pci_dev->dev, "timestamp data packet failed status: %x\n",
2625 retval);
2626 octeon_free_soft_command(oct, sc);
2627 } else {
2628 netif_info(lio, tx_queued, lio->netdev, "Queued timestamp packet\n");
2629 }
2630
2631 return retval;
2632}
2633
f21fb3ed
RV		 2634/** \brief Transmit networks packets to the Octeon interface
2635 * @param skbuff skbuff struct to be passed to network layer.
2636 * @param netdev pointer to network device
2637 * @returns whether the packet was transmitted to the device okay or not
2638 * (NETDEV_TX_OK or NETDEV_TX_BUSY)
2639 */
2640static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev)
2641{
2642 struct lio *lio;
2643 struct octnet_buf_free_info *finfo;
2644 union octnic_cmd_setup cmdsetup;
2645 struct octnic_data_pkt ndata;
2646 struct octeon_device *oct;
2647 struct oct_iq_stats *stats;
6a885b60
RV		 2648 struct octeon_instr_irh *irh;
2649 union tx_info *tx_info;
26236fa9 2650 int status = 0;
f21fb3ed 2651 int q_idx = 0, iq_no = 0;
32581245 2652 int j;
fcd2b5e3 2653 u64 dptr = 0;
f21fb3ed
RV		 2654 u32 tag = 0;
2655
2656 lio = GET_LIO(netdev);
2657 oct = lio->oct_dev;
2658
2659 if (netif_is_multiqueue(netdev)) {
26236fa9
RV		 2660 q_idx = skb->queue_mapping;
2661 q_idx = (q_idx % (lio->linfo.num_txpciq));
2662 tag = q_idx;
2663 iq_no = lio->linfo.txpciq[q_idx].s.q_no;
f21fb3ed
RV		 2664 } else {
2665 iq_no = lio->txq;
2666 }
2667
2668 stats = &oct->instr_queue[iq_no]->stats;
2669
2670 /* Check for all conditions in which the current packet cannot be
2671 * transmitted.
2672 */
2673 if (!(atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) ||
0cece6c5 2674 (!lio->linfo.link.s.link_up) ||
f21fb3ed
RV		 2675 (skb->len <= 0)) {
2676 netif_info(lio, tx_err, lio->netdev,
2677 "Transmit failed link_status : %d\n",
0cece6c5 2678 lio->linfo.link.s.link_up);
f21fb3ed
RV		 2679 goto lio_xmit_failed;
2680 }
2681
2682 /* Use space in skb->cb to store info used to unmap and
2683 * free the buffers.
2684 */
2685 finfo = (struct octnet_buf_free_info *)skb->cb;
2686 finfo->lio = lio;
2687 finfo->skb = skb;
2688 finfo->sc = NULL;
2689
2690 /* Prepare the attributes for the data to be passed to OSI. */
2691 memset(&ndata, 0, sizeof(struct octnic_data_pkt));
2692
2693 ndata.buf = (void *)finfo;
2694
2695 ndata.q_no = iq_no;
2696
2697 if (netif_is_multiqueue(netdev)) {
2698 if (octnet_iq_is_full(oct, ndata.q_no)) {
2699 /* defer sending if queue is full */
2700 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
2701 ndata.q_no);
2702 stats->tx_iq_busy++;
2703 return NETDEV_TX_BUSY;
2704 }
2705 } else {
2706 if (octnet_iq_is_full(oct, lio->txq)) {
2707 /* defer sending if queue is full */
2708 stats->tx_iq_busy++;
2709 netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
a2c64b67 2710 lio->txq);
f21fb3ed
RV		 2711 return NETDEV_TX_BUSY;
2712 }
2713 }
2714 /* pr_info(" XMIT - valid Qs: %d, 1st Q no: %d, cpu: %d, q_no:%d\n",
a2c64b67 2715 * lio->linfo.num_txpciq, lio->txq, cpu, ndata.q_no);
f21fb3ed
RV		 2716 */
2717
2718 ndata.datasize = skb->len;
2719
2720 cmdsetup.u64 = 0;
7275ebfc 2721 cmdsetup.s.iq_no = iq_no;
f21fb3ed 2722
01fb237a
RV		 2723 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2724 if (skb->encapsulation) {
2725 cmdsetup.s.tnl_csum = 1;
2726 stats->tx_vxlan++;
2727 } else {
2728 cmdsetup.s.transport_csum = 1;
2729 }
2730 }
f21fb3ed
RV		 2731 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
2732 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2733 cmdsetup.s.timestamp = 1;
2734 }
2735
2736 if (skb_shinfo(skb)->nr_frags == 0) {
2737 cmdsetup.s.u.datasize = skb->len;
0cece6c5 2738 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
a2c64b67 2739
f21fb3ed 2740 /* Offload checksum calculation for TCP/UDP packets */
6a885b60
RV		 2741 dptr = dma_map_single(&oct->pci_dev->dev,
2742 skb->data,
2743 skb->len,
2744 DMA_TO_DEVICE);
2745 if (dma_mapping_error(&oct->pci_dev->dev, dptr)) {
f21fb3ed
RV		 2746 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 1\n",
2747 __func__);
2748 return NETDEV_TX_BUSY;
2749 }
2750
6a885b60
RV		 2751 ndata.cmd.cmd2.dptr = dptr;
2752 finfo->dptr = dptr;
f21fb3ed
RV		 2753 ndata.reqtype = REQTYPE_NORESP_NET;
2754
2755 } else {
2756 int i, frags;
2757 struct skb_frag_struct *frag;
2758 struct octnic_gather *g;
2759
fcd2b5e3
RV		 2760 spin_lock(&lio->glist_lock[q_idx]);
2761 g = (struct octnic_gather *)
2762 list_delete_head(&lio->glist[q_idx]);
2763 spin_unlock(&lio->glist_lock[q_idx]);
f21fb3ed
RV		 2764
2765 if (!g) {
2766 netif_info(lio, tx_err, lio->netdev,
2767 "Transmit scatter gather: glist null!\n");
2768 goto lio_xmit_failed;
2769 }
2770
2771 cmdsetup.s.gather = 1;
2772 cmdsetup.s.u.gatherptrs = (skb_shinfo(skb)->nr_frags + 1);
0cece6c5 2773 octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
f21fb3ed
RV		 2774
2775 memset(g->sg, 0, g->sg_size);
2776
2777 g->sg[0].ptr[0] = dma_map_single(&oct->pci_dev->dev,
2778 skb->data,
2779 (skb->len - skb->data_len),
2780 DMA_TO_DEVICE);
2781 if (dma_mapping_error(&oct->pci_dev->dev, g->sg[0].ptr[0])) {
2782 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 2\n",
2783 __func__);
2784 return NETDEV_TX_BUSY;
2785 }
2786 add_sg_size(&g->sg[0], (skb->len - skb->data_len), 0);
2787
2788 frags = skb_shinfo(skb)->nr_frags;
2789 i = 1;
2790 while (frags--) {
2791 frag = &skb_shinfo(skb)->frags[i - 1];
2792
2793 g->sg[(i >> 2)].ptr[(i & 3)] =
2794 dma_map_page(&oct->pci_dev->dev,
2795 frag->page.p,
2796 frag->page_offset,
2797 frag->size,
2798 DMA_TO_DEVICE);
2799
fcd2b5e3
RV		 2800 if (dma_mapping_error(&oct->pci_dev->dev,
2801 g->sg[i >> 2].ptr[i & 3])) {
2802 dma_unmap_single(&oct->pci_dev->dev,
2803 g->sg[0].ptr[0],
2804 skb->len - skb->data_len,
2805 DMA_TO_DEVICE);
2806 for (j = 1; j < i; j++) {
2807 frag = &skb_shinfo(skb)->frags[j - 1];
2808 dma_unmap_page(&oct->pci_dev->dev,
2809 g->sg[j >> 2].ptr[j & 3],
2810 frag->size,
2811 DMA_TO_DEVICE);
2812 }
2813 dev_err(&oct->pci_dev->dev, "%s DMA mapping error 3\n",
2814 __func__);
2815 return NETDEV_TX_BUSY;
2816 }
2817
f21fb3ed
RV		 2818 add_sg_size(&g->sg[(i >> 2)], frag->size, (i & 3));
2819 i++;
2820 }
2821
fcd2b5e3
RV		 2822 dma_sync_single_for_device(&oct->pci_dev->dev, g->sg_dma_ptr,
2823 g->sg_size, DMA_TO_DEVICE);
2824 dptr = g->sg_dma_ptr;
f21fb3ed 2825
6a885b60
RV		 2826 ndata.cmd.cmd2.dptr = dptr;
2827 finfo->dptr = dptr;
f21fb3ed
RV		 2828 finfo->g = g;
2829
2830 ndata.reqtype = REQTYPE_NORESP_NET_SG;
2831 }
2832
6a885b60
RV		 2833 irh = (struct octeon_instr_irh *)&ndata.cmd.cmd2.irh;
2834 tx_info = (union tx_info *)&ndata.cmd.cmd2.ossp[0];
f21fb3ed 2835
6a885b60 2836 if (skb_shinfo(skb)->gso_size) {
f21fb3ed
RV		 2837 tx_info->s.gso_size = skb_shinfo(skb)->gso_size;
2838 tx_info->s.gso_segs = skb_shinfo(skb)->gso_segs;
1f164717 2839 stats->tx_gso++;
f21fb3ed 2840 }
1f164717 2841
0da0b77c
RV		 2842 /* HW insert VLAN tag */
2843 if (skb_vlan_tag_present(skb)) {
2844 irh->priority = skb_vlan_tag_get(skb) >> 13;
2845 irh->vlan = skb_vlan_tag_get(skb) & 0xfff;
2846 }
f21fb3ed 2847
f21fb3ed 2848 if (unlikely(cmdsetup.s.timestamp))
32581245 2849 status = send_nic_timestamp_pkt(oct, &ndata, finfo);
f21fb3ed 2850 else
32581245 2851 status = octnet_send_nic_data_pkt(oct, &ndata);
f21fb3ed
RV		 2852 if (status == IQ_SEND_FAILED)
2853 goto lio_xmit_failed;
2854
2855 netif_info(lio, tx_queued, lio->netdev, "Transmit queued successfully\n");
2856
2857 if (status == IQ_SEND_STOP)
2858 stop_q(lio->netdev, q_idx);
2859
860e9538 2860 netif_trans_update(netdev);
f21fb3ed 2861
1f164717
RV		 2862 if (skb_shinfo(skb)->gso_size)
2863 stats->tx_done += skb_shinfo(skb)->gso_segs;
2864 else
2865 stats->tx_done++;
f21fb3ed
RV		 2866 stats->tx_tot_bytes += skb->len;
2867
2868 return NETDEV_TX_OK;
2869
2870lio_xmit_failed:
2871 stats->tx_dropped++;
2872 netif_info(lio, tx_err, lio->netdev, "IQ%d Transmit dropped:%llu\n",
2873 iq_no, stats->tx_dropped);
6a885b60
RV		 2874 if (dptr)
2875 dma_unmap_single(&oct->pci_dev->dev, dptr,
2876 ndata.datasize, DMA_TO_DEVICE);
cabeb13b 2877 tx_buffer_free(skb);
f21fb3ed
RV		 2878 return NETDEV_TX_OK;
2879}
2880
2881/** \brief Network device Tx timeout
2882 * @param netdev pointer to network device
2883 */
2884static void liquidio_tx_timeout(struct net_device *netdev)
2885{
2886 struct lio *lio;
2887
2888 lio = GET_LIO(netdev);
2889
2890 netif_info(lio, tx_err, lio->netdev,
2891 "Transmit timeout tx_dropped:%ld, waking up queues now!!\n",
2892 netdev->stats.tx_dropped);
860e9538 2893 netif_trans_update(netdev);
f21fb3ed
RV		 2894 txqs_wake(netdev);
2895}
2896
63245f25
RV		 2897static int liquidio_vlan_rx_add_vid(struct net_device *netdev,
2898 __be16 proto __attribute__((unused)),
2899 u16 vid)
2900{
2901 struct lio *lio = GET_LIO(netdev);
2902 struct octeon_device *oct = lio->oct_dev;
2903 struct octnic_ctrl_pkt nctrl;
2904 int ret = 0;
2905
2906 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2907
2908 nctrl.ncmd.u64 = 0;
2909 nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER;
2910 nctrl.ncmd.s.param1 = vid;
2911 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
2912 nctrl.wait_time = 100;
2913 nctrl.netpndev = (u64)netdev;
2914 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2915
2916 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
2917 if (ret < 0) {
2918 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
2919 ret);
2920 }
2921
2922 return ret;
2923}
2924
2925static int liquidio_vlan_rx_kill_vid(struct net_device *netdev,
2926 __be16 proto __attribute__((unused)),
2927 u16 vid)
2928{
2929 struct lio *lio = GET_LIO(netdev);
2930 struct octeon_device *oct = lio->oct_dev;
2931 struct octnic_ctrl_pkt nctrl;
2932 int ret = 0;
2933
2934 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
2935
2936 nctrl.ncmd.u64 = 0;
2937 nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER;
2938 nctrl.ncmd.s.param1 = vid;
2939 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
2940 nctrl.wait_time = 100;
2941 nctrl.netpndev = (u64)netdev;
2942 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2943
2944 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
2945 if (ret < 0) {
2946 dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
2947 ret);
2948 }
2949 return ret;
2950}
2951
01fb237a
RV		 2952/** Sending command to enable/disable RX checksum offload
2953 * @param netdev pointer to network device
2954 * @param command OCTNET_CMD_TNL_RX_CSUM_CTL
2955 * @param rx_cmd_bit OCTNET_CMD_RXCSUM_ENABLE/
2956 * OCTNET_CMD_RXCSUM_DISABLE
2957 * @returns SUCCESS or FAILURE
2958 */
c41419b0
NMG		 2959static int liquidio_set_rxcsum_command(struct net_device *netdev, int command,
2960 u8 rx_cmd)
01fb237a
RV		 2961{
2962 struct lio *lio = GET_LIO(netdev);
2963 struct octeon_device *oct = lio->oct_dev;
2964 struct octnic_ctrl_pkt nctrl;
2965 int ret = 0;
2966
2967 nctrl.ncmd.u64 = 0;
2968 nctrl.ncmd.s.cmd = command;
2969 nctrl.ncmd.s.param1 = rx_cmd;
2970 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
2971 nctrl.wait_time = 100;
2972 nctrl.netpndev = (u64)netdev;
2973 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
2974
2975 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
2976 if (ret < 0) {
2977 dev_err(&oct->pci_dev->dev,
2978 "DEVFLAGS RXCSUM change failed in core(ret:0x%x)\n",
2979 ret);
2980 }
2981 return ret;
2982}
2983
2984/** Sending command to add/delete VxLAN UDP port to firmware
2985 * @param netdev pointer to network device
2986 * @param command OCTNET_CMD_VXLAN_PORT_CONFIG
2987 * @param vxlan_port VxLAN port to be added or deleted
2988 * @param vxlan_cmd_bit OCTNET_CMD_VXLAN_PORT_ADD,
2989 * OCTNET_CMD_VXLAN_PORT_DEL
2990 * @returns SUCCESS or FAILURE
2991 */
2992static int liquidio_vxlan_port_command(struct net_device *netdev, int command,
2993 u16 vxlan_port, u8 vxlan_cmd_bit)
2994{
2995 struct lio *lio = GET_LIO(netdev);
2996 struct octeon_device *oct = lio->oct_dev;
2997 struct octnic_ctrl_pkt nctrl;
2998 int ret = 0;
2999
3000 nctrl.ncmd.u64 = 0;
3001 nctrl.ncmd.s.cmd = command;
3002 nctrl.ncmd.s.more = vxlan_cmd_bit;
3003 nctrl.ncmd.s.param1 = vxlan_port;
3004 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
3005 nctrl.wait_time = 100;
3006 nctrl.netpndev = (u64)netdev;
3007 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
3008
3009 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
3010 if (ret < 0) {
3011 dev_err(&oct->pci_dev->dev,
3012 "VxLAN port add/delete failed in core (ret:0x%x)\n",
3013 ret);
3014 }
3015 return ret;
3016}
3017
f21fb3ed
RV		 3018/** \brief Net device fix features
3019 * @param netdev pointer to network device
3020 * @param request features requested
3021 * @returns updated features list
3022 */
3023static netdev_features_t liquidio_fix_features(struct net_device *netdev,
3024 netdev_features_t request)
3025{
3026 struct lio *lio = netdev_priv(netdev);
3027
3028 if ((request & NETIF_F_RXCSUM) &&
3029 !(lio->dev_capability & NETIF_F_RXCSUM))
3030 request &= ~NETIF_F_RXCSUM;
3031
3032 if ((request & NETIF_F_HW_CSUM) &&
3033 !(lio->dev_capability & NETIF_F_HW_CSUM))
3034 request &= ~NETIF_F_HW_CSUM;
3035
3036 if ((request & NETIF_F_TSO) && !(lio->dev_capability & NETIF_F_TSO))
3037 request &= ~NETIF_F_TSO;
3038
3039 if ((request & NETIF_F_TSO6) && !(lio->dev_capability & NETIF_F_TSO6))
3040 request &= ~NETIF_F_TSO6;
3041
3042 if ((request & NETIF_F_LRO) && !(lio->dev_capability & NETIF_F_LRO))
3043 request &= ~NETIF_F_LRO;
3044
3045 /*Disable LRO if RXCSUM is off */
3046 if (!(request & NETIF_F_RXCSUM) && (netdev->features & NETIF_F_LRO) &&
3047 (lio->dev_capability & NETIF_F_LRO))
3048 request &= ~NETIF_F_LRO;
3049
3050 return request;
3051}
3052
3053/** \brief Net device set features
3054 * @param netdev pointer to network device
3055 * @param features features to enable/disable
3056 */
3057static int liquidio_set_features(struct net_device *netdev,
3058 netdev_features_t features)
3059{
3060 struct lio *lio = netdev_priv(netdev);
3061
3062 if (!((netdev->features ^ features) & NETIF_F_LRO))
3063 return 0;
3064
3065 if ((features & NETIF_F_LRO) && (lio->dev_capability & NETIF_F_LRO))
0cece6c5
RV		 3066 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
3067 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed
RV		 3068 else if (!(features & NETIF_F_LRO) &&
3069 (lio->dev_capability & NETIF_F_LRO))
0cece6c5
RV		 3070 liquidio_set_feature(netdev, OCTNET_CMD_LRO_DISABLE,
3071 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed 3072
01fb237a
RV		 3073 /* Sending command to firmware to enable/disable RX checksum
3074 * offload settings using ethtool
3075 */
3076 if (!(netdev->features & NETIF_F_RXCSUM) &&
3077 (lio->enc_dev_capability & NETIF_F_RXCSUM) &&
3078 (features & NETIF_F_RXCSUM))
3079 liquidio_set_rxcsum_command(netdev,
3080 OCTNET_CMD_TNL_RX_CSUM_CTL,
3081 OCTNET_CMD_RXCSUM_ENABLE);
3082 else if ((netdev->features & NETIF_F_RXCSUM) &&
3083 (lio->enc_dev_capability & NETIF_F_RXCSUM) &&
3084 !(features & NETIF_F_RXCSUM))
3085 liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL,
3086 OCTNET_CMD_RXCSUM_DISABLE);
3087
f21fb3ed
RV		 3088 return 0;
3089}
3090
01fb237a
RV		 3091static void liquidio_add_vxlan_port(struct net_device *netdev,
3092 struct udp_tunnel_info *ti)
3093{
3094 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3095 return;
3096
3097 liquidio_vxlan_port_command(netdev,
3098 OCTNET_CMD_VXLAN_PORT_CONFIG,
3099 htons(ti->port),
3100 OCTNET_CMD_VXLAN_PORT_ADD);
3101}
3102
3103static void liquidio_del_vxlan_port(struct net_device *netdev,
3104 struct udp_tunnel_info *ti)
3105{
3106 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3107 return;
3108
3109 liquidio_vxlan_port_command(netdev,
3110 OCTNET_CMD_VXLAN_PORT_CONFIG,
3111 htons(ti->port),
3112 OCTNET_CMD_VXLAN_PORT_DEL);
3113}
3114
f21fb3ed
RV		 3115static struct net_device_ops lionetdevops = {
3116 .ndo_open = liquidio_open,
3117 .ndo_stop = liquidio_stop,
3118 .ndo_start_xmit = liquidio_xmit,
3119 .ndo_get_stats = liquidio_get_stats,
3120 .ndo_set_mac_address = liquidio_set_mac,
3121 .ndo_set_rx_mode = liquidio_set_mcast_list,
3122 .ndo_tx_timeout = liquidio_tx_timeout,
63245f25
RV		 3123
3124 .ndo_vlan_rx_add_vid = liquidio_vlan_rx_add_vid,
3125 .ndo_vlan_rx_kill_vid = liquidio_vlan_rx_kill_vid,
f21fb3ed
RV		 3126 .ndo_change_mtu = liquidio_change_mtu,
3127 .ndo_do_ioctl = liquidio_ioctl,
3128 .ndo_fix_features = liquidio_fix_features,
3129 .ndo_set_features = liquidio_set_features,
01fb237a
RV		 3130 .ndo_udp_tunnel_add = liquidio_add_vxlan_port,
3131 .ndo_udp_tunnel_del = liquidio_del_vxlan_port,
f21fb3ed
RV		 3132};
3133
3134/** \brief Entry point for the liquidio module
3135 */
3136static int __init liquidio_init(void)
3137{
3138 int i;
3139 struct handshake *hs;
3140
3141 init_completion(&first_stage);
3142
3143 octeon_init_device_list(conf_type);
3144
3145 if (liquidio_init_pci())
3146 return -EINVAL;
3147
3148 wait_for_completion_timeout(&first_stage, msecs_to_jiffies(1000));
3149
3150 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3151 hs = &handshake[i];
3152 if (hs->pci_dev) {
3153 wait_for_completion(&hs->init);
3154 if (!hs->init_ok) {
3155 /* init handshake failed */
3156 dev_err(&hs->pci_dev->dev,
3157 "Failed to init device\n");
3158 liquidio_deinit_pci();
3159 return -EIO;
3160 }
3161 }
3162 }
3163
3164 for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
3165 hs = &handshake[i];
3166 if (hs->pci_dev) {
3167 wait_for_completion_timeout(&hs->started,
3168 msecs_to_jiffies(30000));
3169 if (!hs->started_ok) {
3170 /* starter handshake failed */
3171 dev_err(&hs->pci_dev->dev,
3172 "Firmware failed to start\n");
3173 liquidio_deinit_pci();
3174 return -EIO;
3175 }
3176 }
3177 }
3178
3179 return 0;
3180}
3181
5b173cf9 3182static int lio_nic_info(struct octeon_recv_info *recv_info, void *buf)
f21fb3ed
RV		 3183{
3184 struct octeon_device *oct = (struct octeon_device *)buf;
3185 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
0cece6c5 3186 int gmxport = 0;
f21fb3ed
RV		 3187 union oct_link_status *ls;
3188 int i;
3189
0cece6c5 3190 if (recv_pkt->buffer_size[0] != sizeof(*ls)) {
f21fb3ed
RV		 3191 dev_err(&oct->pci_dev->dev, "Malformed NIC_INFO, len=%d, ifidx=%d\n",
3192 recv_pkt->buffer_size[0],
0cece6c5 3193 recv_pkt->rh.r_nic_info.gmxport);
f21fb3ed
RV		 3194 goto nic_info_err;
3195 }
3196
0cece6c5 3197 gmxport = recv_pkt->rh.r_nic_info.gmxport;
f21fb3ed
RV		 3198 ls = (union oct_link_status *)get_rbd(recv_pkt->buffer_ptr[0]);
3199
3200 octeon_swap_8B_data((u64 *)ls, (sizeof(union oct_link_status)) >> 3);
0cece6c5
RV		 3201 for (i = 0; i < oct->ifcount; i++) {
3202 if (oct->props[i].gmxport == gmxport) {
3203 update_link_status(oct->props[i].netdev, ls);
3204 break;
3205 }
3206 }
f21fb3ed
RV		 3207
3208nic_info_err:
3209 for (i = 0; i < recv_pkt->buffer_count; i++)
3210 recv_buffer_free(recv_pkt->buffer_ptr[i]);
3211 octeon_free_recv_info(recv_info);
3212 return 0;
3213}
3214
3215/**
3216 * \brief Setup network interfaces
3217 * @param octeon_dev octeon device
3218 *
3219 * Called during init time for each device. It assumes the NIC
3220 * is already up and running. The link information for each
3221 * interface is passed in link_info.
3222 */
3223static int setup_nic_devices(struct octeon_device *octeon_dev)
3224{
3225 struct lio *lio = NULL;
3226 struct net_device *netdev;
3227 u8 mac[6], i, j;
3228 struct octeon_soft_command *sc;
3229 struct liquidio_if_cfg_context *ctx;
3230 struct liquidio_if_cfg_resp *resp;
3231 struct octdev_props *props;
26236fa9 3232 int retval, num_iqueues, num_oqueues;
f21fb3ed
RV		 3233 union oct_nic_if_cfg if_cfg;
3234 unsigned int base_queue;
3235 unsigned int gmx_port_id;
83101ce3 3236 u32 resp_size, ctx_size, data_size;
0cece6c5 3237 u32 ifidx_or_pfnum;
83101ce3 3238 struct lio_version *vdata;
f21fb3ed
RV		 3239
3240 /* This is to handle link status changes */
3241 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3242 OPCODE_NIC_INFO,
3243 lio_nic_info, octeon_dev);
3244
3245 /* REQTYPE_RESP_NET and REQTYPE_SOFT_COMMAND do not have free functions.
3246 * They are handled directly.
3247 */
3248 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET,
3249 free_netbuf);
3250
3251 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET_SG,
3252 free_netsgbuf);
3253
3254 octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_RESP_NET_SG,
3255 free_netsgbuf_with_resp);
3256
3257 for (i = 0; i < octeon_dev->ifcount; i++) {
3258 resp_size = sizeof(struct liquidio_if_cfg_resp);
3259 ctx_size = sizeof(struct liquidio_if_cfg_context);
83101ce3 3260 data_size = sizeof(struct lio_version);
f21fb3ed 3261 sc = (struct octeon_soft_command *)
83101ce3 3262 octeon_alloc_soft_command(octeon_dev, data_size,
f21fb3ed
RV		 3263 resp_size, ctx_size);
3264 resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
3265 ctx = (struct liquidio_if_cfg_context *)sc->ctxptr;
83101ce3
RV		 3266 vdata = (struct lio_version *)sc->virtdptr;
3267
3268 *((u64 *)vdata) = 0;
3269 vdata->major = cpu_to_be16(LIQUIDIO_BASE_MAJOR_VERSION);
3270 vdata->minor = cpu_to_be16(LIQUIDIO_BASE_MINOR_VERSION);
3271 vdata->micro = cpu_to_be16(LIQUIDIO_BASE_MICRO_VERSION);
f21fb3ed 3272
e86b1ab6
RV		 3273 if (OCTEON_CN23XX_PF(octeon_dev)) {
3274 num_iqueues = octeon_dev->sriov_info.num_pf_rings;
3275 num_oqueues = octeon_dev->sriov_info.num_pf_rings;
3276 base_queue = octeon_dev->sriov_info.pf_srn;
3277
3278 gmx_port_id = octeon_dev->pf_num;
3279 ifidx_or_pfnum = octeon_dev->pf_num;
3280 } else {
3281 num_iqueues = CFG_GET_NUM_TXQS_NIC_IF(
3282 octeon_get_conf(octeon_dev), i);
3283 num_oqueues = CFG_GET_NUM_RXQS_NIC_IF(
3284 octeon_get_conf(octeon_dev), i);
3285 base_queue = CFG_GET_BASE_QUE_NIC_IF(
3286 octeon_get_conf(octeon_dev), i);
3287 gmx_port_id = CFG_GET_GMXID_NIC_IF(
3288 octeon_get_conf(octeon_dev), i);
3289 ifidx_or_pfnum = i;
3290 }
3dcef2ca 3291
f21fb3ed
RV		 3292 dev_dbg(&octeon_dev->pci_dev->dev,
3293 "requesting config for interface %d, iqs %d, oqs %d\n",
0cece6c5 3294 ifidx_or_pfnum, num_iqueues, num_oqueues);
a7d5a3dc 3295 WRITE_ONCE(ctx->cond, 0);
f21fb3ed
RV		 3296 ctx->octeon_id = lio_get_device_id(octeon_dev);
3297 init_waitqueue_head(&ctx->wc);
3298
3299 if_cfg.u64 = 0;
3300 if_cfg.s.num_iqueues = num_iqueues;
3301 if_cfg.s.num_oqueues = num_oqueues;
3302 if_cfg.s.base_queue = base_queue;
3303 if_cfg.s.gmx_port_id = gmx_port_id;
0cece6c5
RV		 3304
3305 sc->iq_no = 0;
3306
f21fb3ed 3307 octeon_prepare_soft_command(octeon_dev, sc, OPCODE_NIC,
0cece6c5 3308 OPCODE_NIC_IF_CFG, 0,
f21fb3ed
RV		 3309 if_cfg.u64, 0);
3310
3311 sc->callback = if_cfg_callback;
3312 sc->callback_arg = sc;
55893a63 3313 sc->wait_time = 3000;
f21fb3ed
RV		 3314
3315 retval = octeon_send_soft_command(octeon_dev, sc);
ddc173a6 3316 if (retval == IQ_SEND_FAILED) {
f21fb3ed
RV		 3317 dev_err(&octeon_dev->pci_dev->dev,
3318 "iq/oq config failed status: %x\n",
3319 retval);
3320 /* Soft instr is freed by driver in case of failure. */
3321 goto setup_nic_dev_fail;
3322 }
3323
3324 /* Sleep on a wait queue till the cond flag indicates that the
3325 * response arrived or timed-out.
3326 */
3327 sleep_cond(&ctx->wc, &ctx->cond);
3328 retval = resp->status;
3329 if (retval) {
3330 dev_err(&octeon_dev->pci_dev->dev, "iq/oq config failed\n");
3331 goto setup_nic_dev_fail;
3332 }
3333
3334 octeon_swap_8B_data((u64 *)(&resp->cfg_info),
3335 (sizeof(struct liquidio_if_cfg_info)) >> 3);
3336
3337 num_iqueues = hweight64(resp->cfg_info.iqmask);
3338 num_oqueues = hweight64(resp->cfg_info.oqmask);
3339
3340 if (!(num_iqueues) || !(num_oqueues)) {
3341 dev_err(&octeon_dev->pci_dev->dev,
3342 "Got bad iqueues (%016llx) or oqueues (%016llx) from firmware.\n",
3343 resp->cfg_info.iqmask,
3344 resp->cfg_info.oqmask);
3345 goto setup_nic_dev_fail;
3346 }
3347 dev_dbg(&octeon_dev->pci_dev->dev,
3348 "interface %d, iqmask %016llx, oqmask %016llx, numiqueues %d, numoqueues %d\n",
3349 i, resp->cfg_info.iqmask, resp->cfg_info.oqmask,
3350 num_iqueues, num_oqueues);
3351 netdev = alloc_etherdev_mq(LIO_SIZE, num_iqueues);
3352
3353 if (!netdev) {
3354 dev_err(&octeon_dev->pci_dev->dev, "Device allocation failed\n");
3355 goto setup_nic_dev_fail;
3356 }
3357
0cece6c5 3358 SET_NETDEV_DEV(netdev, &octeon_dev->pci_dev->dev);
f21fb3ed
RV		 3359
3360 if (num_iqueues > 1)
3361 lionetdevops.ndo_select_queue = select_q;
3362
3363 /* Associate the routines that will handle different
3364 * netdev tasks.
3365 */
3366 netdev->netdev_ops = &lionetdevops;
3367
3368 lio = GET_LIO(netdev);
3369
3370 memset(lio, 0, sizeof(struct lio));
3371
0cece6c5
RV		 3372 lio->ifidx = ifidx_or_pfnum;
3373
3374 props = &octeon_dev->props[i];
3375 props->gmxport = resp->cfg_info.linfo.gmxport;
3376 props->netdev = netdev;
f21fb3ed
RV		 3377
3378 lio->linfo.num_rxpciq = num_oqueues;
3379 lio->linfo.num_txpciq = num_iqueues;
f21fb3ed 3380 for (j = 0; j < num_oqueues; j++) {
26236fa9
RV		 3381 lio->linfo.rxpciq[j].u64 =
3382 resp->cfg_info.linfo.rxpciq[j].u64;
f21fb3ed 3383 }
f21fb3ed 3384 for (j = 0; j < num_iqueues; j++) {
26236fa9
RV		 3385 lio->linfo.txpciq[j].u64 =
3386 resp->cfg_info.linfo.txpciq[j].u64;
f21fb3ed
RV		 3387 }
3388 lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr;
3389 lio->linfo.gmxport = resp->cfg_info.linfo.gmxport;
3390 lio->linfo.link.u64 = resp->cfg_info.linfo.link.u64;
3391
3392 lio->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3393
e86b1ab6
RV		 3394 if (OCTEON_CN23XX_PF(octeon_dev) ||
3395 OCTEON_CN6XXX(octeon_dev)) {
3396 lio->dev_capability = NETIF_F_HIGHDMA
3397 | NETIF_F_IP_CSUM
3398 | NETIF_F_IPV6_CSUM
3399 | NETIF_F_SG | NETIF_F_RXCSUM
3400 | NETIF_F_GRO
3401 | NETIF_F_TSO | NETIF_F_TSO6
3402 | NETIF_F_LRO;
3403 }
f21fb3ed
RV		 3404 netif_set_gso_max_size(netdev, OCTNIC_GSO_MAX_SIZE);
3405
01fb237a
RV		 3406 /* Copy of transmit encapsulation capabilities:
3407 * TSO, TSO6, Checksums for this device
3408 */
3409 lio->enc_dev_capability = NETIF_F_IP_CSUM
3410 | NETIF_F_IPV6_CSUM
3411 | NETIF_F_GSO_UDP_TUNNEL
3412 | NETIF_F_HW_CSUM | NETIF_F_SG
3413 | NETIF_F_RXCSUM
3414 | NETIF_F_TSO | NETIF_F_TSO6
3415 | NETIF_F_LRO;
3416
3417 netdev->hw_enc_features = (lio->enc_dev_capability &
3418 ~NETIF_F_LRO);
3419
3420 lio->dev_capability |= NETIF_F_GSO_UDP_TUNNEL;
3421
f21fb3ed 3422 netdev->vlan_features = lio->dev_capability;
0da0b77c 3423 /* Add any unchangeable hw features */
63245f25
RV		 3424 lio->dev_capability |= NETIF_F_HW_VLAN_CTAG_FILTER |
3425 NETIF_F_HW_VLAN_CTAG_RX |
0da0b77c
RV		 3426 NETIF_F_HW_VLAN_CTAG_TX;
3427
3428 netdev->features = (lio->dev_capability & ~NETIF_F_LRO);
f21fb3ed
RV		 3429
3430 netdev->hw_features = lio->dev_capability;
0da0b77c
RV		 3431 /*HW_VLAN_RX and HW_VLAN_FILTER is always on*/
3432 netdev->hw_features = netdev->hw_features &
3433 ~NETIF_F_HW_VLAN_CTAG_RX;
f21fb3ed
RV		 3434
3435 /* Point to the properties for octeon device to which this
3436 * interface belongs.
3437 */
3438 lio->oct_dev = octeon_dev;
3439 lio->octprops = props;
3440 lio->netdev = netdev;
f21fb3ed
RV		 3441
3442 dev_dbg(&octeon_dev->pci_dev->dev,
3443 "if%d gmx: %d hw_addr: 0x%llx\n", i,
3444 lio->linfo.gmxport, CVM_CAST64(lio->linfo.hw_addr));
3445
3446 /* 64-bit swap required on LE machines */
3447 octeon_swap_8B_data(&lio->linfo.hw_addr, 1);
3448 for (j = 0; j < 6; j++)
3449 mac[j] = *((u8 *)(((u8 *)&lio->linfo.hw_addr) + 2 + j));
3450
3451 /* Copy MAC Address to OS network device structure */
3452
3453 ether_addr_copy(netdev->dev_addr, mac);
3454
26236fa9
RV		 3455 /* By default all interfaces on a single Octeon uses the same
3456 * tx and rx queues
3457 */
3458 lio->txq = lio->linfo.txpciq[0].s.q_no;
3459 lio->rxq = lio->linfo.rxpciq[0].s.q_no;
0cece6c5 3460 if (setup_io_queues(octeon_dev, i)) {
f21fb3ed
RV		 3461 dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n");
3462 goto setup_nic_dev_fail;
3463 }
3464
3465 ifstate_set(lio, LIO_IFSTATE_DROQ_OPS);
3466
f21fb3ed
RV		 3467 lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq);
3468 lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq);
3469
fcd2b5e3 3470 if (setup_glists(octeon_dev, lio, num_iqueues)) {
f21fb3ed
RV		 3471 dev_err(&octeon_dev->pci_dev->dev,
3472 "Gather list allocation failed\n");
3473 goto setup_nic_dev_fail;
3474 }
3475
3476 /* Register ethtool support */
3477 liquidio_set_ethtool_ops(netdev);
f5a20472 3478 octeon_dev->priv_flags = 0x0;
f21fb3ed 3479
0cece6c5 3480 if (netdev->features & NETIF_F_LRO)
a2c64b67
RV		 3481 liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
3482 OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
f21fb3ed 3483
63245f25
RV		 3484 liquidio_set_feature(netdev, OCTNET_CMD_ENABLE_VLAN_FILTER, 0);
3485
f21fb3ed 3486 if ((debug != -1) && (debug & NETIF_MSG_HW))
63245f25
RV		 3487 liquidio_set_feature(netdev,
3488 OCTNET_CMD_VERBOSE_ENABLE, 0);
f21fb3ed
RV		 3489
3490 /* Register the network device with the OS */
3491 if (register_netdev(netdev)) {
3492 dev_err(&octeon_dev->pci_dev->dev, "Device registration failed\n");
3493 goto setup_nic_dev_fail;
3494 }
3495
3496 dev_dbg(&octeon_dev->pci_dev->dev,
3497 "Setup NIC ifidx:%d mac:%02x%02x%02x%02x%02x%02x\n",
3498 i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
3499 netif_carrier_off(netdev);
0cece6c5 3500 lio->link_changes++;
f21fb3ed
RV		 3501
3502 ifstate_set(lio, LIO_IFSTATE_REGISTERED);
3503
01fb237a
RV		 3504 /* Sending command to firmware to enable Rx checksum offload
3505 * by default at the time of setup of Liquidio driver for
3506 * this device
3507 */
3508 liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL,
3509 OCTNET_CMD_RXCSUM_ENABLE);
3510 liquidio_set_feature(netdev, OCTNET_CMD_TNL_TX_CSUM_CTL,
3511 OCTNET_CMD_TXCSUM_ENABLE);
3512
f21fb3ed
RV		 3513 dev_dbg(&octeon_dev->pci_dev->dev,
3514 "NIC ifidx:%d Setup successful\n", i);
3515
3516 octeon_free_soft_command(octeon_dev, sc);
3517 }
3518
3519 return 0;
3520
3521setup_nic_dev_fail:
3522
3523 octeon_free_soft_command(octeon_dev, sc);
3524
3525 while (i--) {
3526 dev_err(&octeon_dev->pci_dev->dev,
3527 "NIC ifidx:%d Setup failed\n", i);
3528 liquidio_destroy_nic_device(octeon_dev, i);
3529 }
3530 return -ENODEV;
3531}
3532
3533/**
3534 * \brief initialize the NIC
3535 * @param oct octeon device
3536 *
3537 * This initialization routine is called once the Octeon device application is
3538 * up and running
3539 */
3540static int liquidio_init_nic_module(struct octeon_device *oct)
3541{
3542 struct oct_intrmod_cfg *intrmod_cfg;
0cece6c5 3543 int i, retval = 0;
f21fb3ed
RV		 3544 int num_nic_ports = CFG_GET_NUM_NIC_PORTS(octeon_get_conf(oct));
3545
3546 dev_dbg(&oct->pci_dev->dev, "Initializing network interfaces\n");
3547
3548 /* only default iq and oq were initialized
3549 * initialize the rest as well
3550 */
3551 /* run port_config command for each port */
3552 oct->ifcount = num_nic_ports;
3553
3554 memset(oct->props, 0,
3555 sizeof(struct octdev_props) * num_nic_ports);
3556
0cece6c5
RV		 3557 for (i = 0; i < MAX_OCTEON_LINKS; i++)
3558 oct->props[i].gmxport = -1;
3559
f21fb3ed
RV		 3560 retval = setup_nic_devices(oct);
3561 if (retval) {
3562 dev_err(&oct->pci_dev->dev, "Setup NIC devices failed\n");
3563 goto octnet_init_failure;
3564 }
3565
3566 liquidio_ptp_init(oct);
3567
3568 /* Initialize interrupt moderation params */
3569 intrmod_cfg = &((struct octeon_device *)oct)->intrmod;
78e6a9b4
RV		 3570 intrmod_cfg->rx_enable = 1;
3571 intrmod_cfg->check_intrvl = LIO_INTRMOD_CHECK_INTERVAL;
3572 intrmod_cfg->maxpkt_ratethr = LIO_INTRMOD_MAXPKT_RATETHR;
3573 intrmod_cfg->minpkt_ratethr = LIO_INTRMOD_MINPKT_RATETHR;
3574 intrmod_cfg->rx_maxcnt_trigger = LIO_INTRMOD_RXMAXCNT_TRIGGER;
3575 intrmod_cfg->rx_maxtmr_trigger = LIO_INTRMOD_RXMAXTMR_TRIGGER;
3576 intrmod_cfg->rx_mintmr_trigger = LIO_INTRMOD_RXMINTMR_TRIGGER;
3577 intrmod_cfg->rx_mincnt_trigger = LIO_INTRMOD_RXMINCNT_TRIGGER;
3578 intrmod_cfg->tx_enable = 1;
3579 intrmod_cfg->tx_maxcnt_trigger = LIO_INTRMOD_TXMAXCNT_TRIGGER;
3580 intrmod_cfg->tx_mincnt_trigger = LIO_INTRMOD_TXMINCNT_TRIGGER;
3581 intrmod_cfg->rx_frames = CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct));
3582 intrmod_cfg->rx_usecs = CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct));
f21fb3ed
RV		 3583 dev_dbg(&oct->pci_dev->dev, "Network interfaces ready\n");
3584
3585 return retval;
3586
3587octnet_init_failure:
3588
3589 oct->ifcount = 0;
3590
3591 return retval;
3592}
3593
3594/**
3595 * \brief starter callback that invokes the remaining initialization work after
3596 * the NIC is up and running.
3597 * @param octptr work struct work_struct
3598 */
3599static void nic_starter(struct work_struct *work)
3600{
3601 struct octeon_device *oct;
3602 struct cavium_wk *wk = (struct cavium_wk *)work;
3603
3604 oct = (struct octeon_device *)wk->ctxptr;
3605
3606 if (atomic_read(&oct->status) == OCT_DEV_RUNNING)
3607 return;
3608
3609 /* If the status of the device is CORE_OK, the core
3610 * application has reported its application type. Call
3611 * any registered handlers now and move to the RUNNING
3612 * state.
3613 */
3614 if (atomic_read(&oct->status) != OCT_DEV_CORE_OK) {
3615 schedule_delayed_work(&oct->nic_poll_work.work,
3616 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
3617 return;
3618 }
3619
3620 atomic_set(&oct->status, OCT_DEV_RUNNING);
3621
3622 if (oct->app_mode && oct->app_mode == CVM_DRV_NIC_APP) {
3623 dev_dbg(&oct->pci_dev->dev, "Starting NIC module\n");
3624
3625 if (liquidio_init_nic_module(oct))
3626 dev_err(&oct->pci_dev->dev, "NIC initialization failed\n");
3627 else
3628 handshake[oct->octeon_id].started_ok = 1;
3629 } else {
3630 dev_err(&oct->pci_dev->dev,
3631 "Unexpected application running on NIC (%d). Check firmware.\n",
3632 oct->app_mode);
3633 }
3634
3635 complete(&handshake[oct->octeon_id].started);
3636}
3637
3638/**
3639 * \brief Device initialization for each Octeon device that is probed
3640 * @param octeon_dev octeon device
3641 */
3642static int octeon_device_init(struct octeon_device *octeon_dev)
3643{
3644 int j, ret;
d3d7e6c6 3645 char bootcmd[] = "\n";
f21fb3ed
RV		 3646 struct octeon_device_priv *oct_priv =
3647 (struct octeon_device_priv *)octeon_dev->priv;
3648 atomic_set(&octeon_dev->status, OCT_DEV_BEGIN_STATE);
3649
3650 /* Enable access to the octeon device and make its DMA capability
3651 * known to the OS.
3652 */
3653 if (octeon_pci_os_setup(octeon_dev))
3654 return 1;
3655
3656 /* Identify the Octeon type and map the BAR address space. */
3657 if (octeon_chip_specific_setup(octeon_dev)) {
3658 dev_err(&octeon_dev->pci_dev->dev, "Chip specific setup failed\n");
3659 return 1;
3660 }
3661
3662 atomic_set(&octeon_dev->status, OCT_DEV_PCI_MAP_DONE);
3663
3664 octeon_dev->app_mode = CVM_DRV_INVALID_APP;
3665
3666 /* Do a soft reset of the Octeon device. */
3667 if (octeon_dev->fn_list.soft_reset(octeon_dev))
3668 return 1;
3669
3670 /* Initialize the dispatch mechanism used to push packets arriving on
3671 * Octeon Output queues.
3672 */
3673 if (octeon_init_dispatch_list(octeon_dev))
3674 return 1;
3675
3676 octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
3677 OPCODE_NIC_CORE_DRV_ACTIVE,
3678 octeon_core_drv_init,
3679 octeon_dev);
3680
3681 INIT_DELAYED_WORK(&octeon_dev->nic_poll_work.work, nic_starter);
3682 octeon_dev->nic_poll_work.ctxptr = (void *)octeon_dev;
3683 schedule_delayed_work(&octeon_dev->nic_poll_work.work,
3684 LIQUIDIO_STARTER_POLL_INTERVAL_MS);
3685
3686 atomic_set(&octeon_dev->status, OCT_DEV_DISPATCH_INIT_DONE);
3687
3688 octeon_set_io_queues_off(octeon_dev);
3689
3690 /* Setup the data structures that manage this Octeon's Input queues. */
3691 if (octeon_setup_instr_queues(octeon_dev)) {
3692 dev_err(&octeon_dev->pci_dev->dev,
3693 "instruction queue initialization failed\n");
3694 /* On error, release any previously allocated queues */
3695 for (j = 0; j < octeon_dev->num_iqs; j++)
3696 octeon_delete_instr_queue(octeon_dev, j);
3697 return 1;
3698 }
3699 atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE);
3700
3701 /* Initialize soft command buffer pool
3702 */
3703 if (octeon_setup_sc_buffer_pool(octeon_dev)) {
3704 dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n");
3705 return 1;
3706 }
3707 atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
3708
3709 /* Initialize lists to manage the requests of different types that
3710 * arrive from user & kernel applications for this octeon device.
3711 */
3712 if (octeon_setup_response_list(octeon_dev)) {
3713 dev_err(&octeon_dev->pci_dev->dev, "Response list allocation failed\n");
3714 return 1;
3715 }
3716 atomic_set(&octeon_dev->status, OCT_DEV_RESP_LIST_INIT_DONE);
3717
3718 if (octeon_setup_output_queues(octeon_dev)) {
3719 dev_err(&octeon_dev->pci_dev->dev, "Output queue initialization failed\n");
3720 /* Release any previously allocated queues */
3721 for (j = 0; j < octeon_dev->num_oqs; j++)
3722 octeon_delete_droq(octeon_dev, j);
1e0d30fe 3723 return 1;
f21fb3ed
RV		 3724 }
3725
3726 atomic_set(&octeon_dev->status, OCT_DEV_DROQ_INIT_DONE);
3727
3728 /* The input and output queue registers were setup earlier (the queues
3729 * were not enabled). Any additional registers that need to be
3730 * programmed should be done now.
3731 */
3732 ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
3733 if (ret) {
3734 dev_err(&octeon_dev->pci_dev->dev,
3735 "Failed to configure device registers\n");
3736 return ret;
3737 }
3738
3739 /* Initialize the tasklet that handles output queue packet processing.*/
3740 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing droq tasklet\n");
3741 tasklet_init(&oct_priv->droq_tasklet, octeon_droq_bh,
3742 (unsigned long)octeon_dev);
3743
3744 /* Setup the interrupt handler and record the INT SUM register address
3745 */
1e0d30fe
RV		 3746 if (octeon_setup_interrupt(octeon_dev))
3747 return 1;
f21fb3ed
RV		 3748
3749 /* Enable Octeon device interrupts */
3750 octeon_dev->fn_list.enable_interrupt(octeon_dev->chip);
3751
3752 /* Enable the input and output queues for this Octeon device */
3753 octeon_dev->fn_list.enable_io_queues(octeon_dev);
3754
3755 atomic_set(&octeon_dev->status, OCT_DEV_IO_QUEUES_DONE);
3756
3757 dev_dbg(&octeon_dev->pci_dev->dev, "Waiting for DDR initialization...\n");
3758
4b129ae3
RV		 3759 if (ddr_timeout == 0)
3760 dev_info(&octeon_dev->pci_dev->dev, "WAITING. Set ddr_timeout to non-zero value to proceed with initialization.\n");
f21fb3ed
RV		 3761
3762 schedule_timeout_uninterruptible(HZ * LIO_RESET_SECS);
3763
3764 /* Wait for the octeon to initialize DDR after the soft-reset. */
4b129ae3
RV		 3765 while (ddr_timeout == 0) {
3766 set_current_state(TASK_INTERRUPTIBLE);
3767 if (schedule_timeout(HZ / 10)) {
3768 /* user probably pressed Control-C */
3769 return 1;
3770 }
3771 }
f21fb3ed
RV		 3772 ret = octeon_wait_for_ddr_init(octeon_dev, &ddr_timeout);
3773 if (ret) {
3774 dev_err(&octeon_dev->pci_dev->dev,
3775 "DDR not initialized. Please confirm that board is configured to boot from Flash, ret: %d\n",
3776 ret);
3777 return 1;
3778 }
3779
3780 if (octeon_wait_for_bootloader(octeon_dev, 1000) != 0) {
3781 dev_err(&octeon_dev->pci_dev->dev, "Board not responding\n");
3782 return 1;
3783 }
3784
d3d7e6c6
RV		 3785 /* Divert uboot to take commands from host instead. */
3786 ret = octeon_console_send_cmd(octeon_dev, bootcmd, 50);
3787
f21fb3ed
RV		 3788 dev_dbg(&octeon_dev->pci_dev->dev, "Initializing consoles\n");
3789 ret = octeon_init_consoles(octeon_dev);
3790 if (ret) {
3791 dev_err(&octeon_dev->pci_dev->dev, "Could not access board consoles\n");
3792 return 1;
3793 }
3794 ret = octeon_add_console(octeon_dev, 0);
3795 if (ret) {
3796 dev_err(&octeon_dev->pci_dev->dev, "Could not access board console\n");
3797 return 1;
3798 }
3799
3800 atomic_set(&octeon_dev->status, OCT_DEV_CONSOLE_INIT_DONE);
3801
3802 dev_dbg(&octeon_dev->pci_dev->dev, "Loading firmware\n");
3803 ret = load_firmware(octeon_dev);
3804 if (ret) {
3805 dev_err(&octeon_dev->pci_dev->dev, "Could not load firmware to board\n");
3806 return 1;
3807 }
3808
3809 handshake[octeon_dev->octeon_id].init_ok = 1;
3810 complete(&handshake[octeon_dev->octeon_id].init);
3811
3812 atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK);
3813
3814 /* Send Credit for Octeon Output queues. Credits are always sent after
3815 * the output queue is enabled.
3816 */
3817 for (j = 0; j < octeon_dev->num_oqs; j++)
3818 writel(octeon_dev->droq[j]->max_count,
3819 octeon_dev->droq[j]->pkts_credit_reg);
3820
3821 /* Packets can start arriving on the output queues from this point. */
3822
3823 return 0;
3824}
3825
3826/**
3827 * \brief Exits the module
3828 */
3829static void __exit liquidio_exit(void)
3830{
3831 liquidio_deinit_pci();
3832
3833 pr_info("LiquidIO network module is now unloaded\n");
3834}
3835
3836module_init(liquidio_init);
3837module_exit(liquidio_exit);
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