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f21fb3ed | 1 | /********************************************************************** |
50579d3d RV |
2 | * Author: Cavium, Inc. |
3 | * | |
4 | * Contact: support@cavium.com | |
5 | * Please include "LiquidIO" in the subject. | |
6 | * | |
7 | * Copyright (c) 2003-2016 Cavium, Inc. | |
8 | * | |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more details. | |
17 | ***********************************************************************/ | |
f21fb3ed RV |
18 | /*! \file liquidio_common.h |
19 | * \brief Common: Structures and macros used in PCI-NIC package by core and | |
20 | * host driver. | |
21 | */ | |
22 | ||
23 | #ifndef __LIQUIDIO_COMMON_H__ | |
24 | #define __LIQUIDIO_COMMON_H__ | |
25 | ||
26 | #include "octeon_config.h" | |
27 | ||
d3d7e6c6 | 28 | #define LIQUIDIO_PACKAGE "" |
83101ce3 | 29 | #define LIQUIDIO_BASE_MAJOR_VERSION 1 |
25c5f715 FM |
30 | #define LIQUIDIO_BASE_MINOR_VERSION 7 |
31 | #define LIQUIDIO_BASE_MICRO_VERSION 0 | |
83101ce3 RV |
32 | #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ |
33 | __stringify(LIQUIDIO_BASE_MINOR_VERSION) | |
34 | #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) | |
35 | #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ | |
36 | __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ | |
37 | __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ | |
38 | "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) | |
39 | ||
40 | struct lio_version { | |
41 | u16 major; | |
42 | u16 minor; | |
43 | u16 micro; | |
44 | u16 reserved; | |
45 | }; | |
a2c64b67 | 46 | |
f21fb3ed RV |
47 | #define CONTROL_IQ 0 |
48 | /** Tag types used by Octeon cores in its work. */ | |
49 | enum octeon_tag_type { | |
50 | ORDERED_TAG = 0, | |
51 | ATOMIC_TAG = 1, | |
52 | NULL_TAG = 2, | |
53 | NULL_NULL_TAG = 3 | |
54 | }; | |
55 | ||
56 | /* pre-defined host->NIC tag values */ | |
57 | #define LIO_CONTROL (0x11111110) | |
58 | #define LIO_DATA(i) (0x11111111 + (i)) | |
59 | ||
60 | /* Opcodes used by host driver/apps to perform operations on the core. | |
61 | * These are used to identify the major subsystem that the operation | |
62 | * is for. | |
63 | */ | |
64 | #define OPCODE_CORE 0 /* used for generic core operations */ | |
65 | #define OPCODE_NIC 1 /* used for NIC operations */ | |
f21fb3ed RV |
66 | /* Subcodes are used by host driver/apps to identify the sub-operation |
67 | * for the core. They only need to by unique for a given subsystem. | |
68 | */ | |
97a25326 | 69 | #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) |
f21fb3ed RV |
70 | |
71 | /** OPCODE_CORE subcodes. For future use. */ | |
72 | ||
73 | /** OPCODE_NIC subcodes */ | |
74 | ||
75 | /* This subcode is sent by core PCI driver to indicate cores are ready. */ | |
76 | #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 | |
77 | #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ | |
78 | #define OPCODE_NIC_CMD 0x03 | |
79 | #define OPCODE_NIC_INFO 0x04 | |
80 | #define OPCODE_NIC_PORT_STATS 0x05 | |
81 | #define OPCODE_NIC_MDIO45 0x06 | |
82 | #define OPCODE_NIC_TIMESTAMP 0x07 | |
83 | #define OPCODE_NIC_INTRMOD_CFG 0x08 | |
84 | #define OPCODE_NIC_IF_CFG 0x09 | |
86dea55b | 85 | #define OPCODE_NIC_VF_DRV_NOTICE 0x0A |
50c0add5 | 86 | #define OPCODE_NIC_INTRMOD_PARAMS 0x0B |
f2d254fa | 87 | #define OPCODE_NIC_SET_TRUSTED_VF 0x13 |
907aaa6b | 88 | #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14 |
86dea55b RV |
89 | #define VF_DRV_LOADED 1 |
90 | #define VF_DRV_REMOVED -1 | |
91 | #define VF_DRV_MACADDR_CHANGED 2 | |
f21fb3ed | 92 | |
1f233f32 VMG |
93 | #define OPCODE_NIC_VF_REP_PKT 0x15 |
94 | #define OPCODE_NIC_VF_REP_CMD 0x16 | |
95 | ||
f21fb3ed RV |
96 | #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 |
97 | ||
f21fb3ed RV |
98 | /* Application codes advertised by the core driver initialization packet. */ |
99 | #define CVM_DRV_APP_START 0x0 | |
100 | #define CVM_DRV_NO_APP 0 | |
101 | #define CVM_DRV_APP_COUNT 0x2 | |
102 | #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) | |
103 | #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) | |
104 | #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) | |
105 | #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) | |
106 | ||
de28c99d | 107 | #define BYTES_PER_DHLEN_UNIT 8 |
cdb478e5 | 108 | #define MAX_REG_CNT 2000000U |
0c88a761 RF |
109 | #define INTRNAMSIZ 32 |
110 | #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) | |
111 | #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2) | |
112 | #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2) | |
113 | ||
b2854772 | 114 | #define SCR2_BIT_FW_LOADED 63 |
de28c99d | 115 | |
907aaa6b VB |
116 | /* App specific capabilities from firmware to pf driver */ |
117 | #define LIQUIDIO_TIME_SYNC_CAP 0x1 | |
d4be8ebe | 118 | #define LIQUIDIO_SWITCHDEV_CAP 0x2 |
907aaa6b | 119 | |
97a25326 RV |
120 | static inline u32 incr_index(u32 index, u32 count, u32 max) |
121 | { | |
122 | if ((index + count) >= max) | |
123 | index = index + count - max; | |
124 | else | |
125 | index += count; | |
126 | ||
127 | return index; | |
128 | } | |
f21fb3ed RV |
129 | |
130 | #define OCT_BOARD_NAME 32 | |
131 | #define OCT_SERIAL_LEN 64 | |
132 | ||
133 | /* Structure used by core driver to send indication that the Octeon | |
134 | * application is ready. | |
135 | */ | |
136 | struct octeon_core_setup { | |
137 | u64 corefreq; | |
138 | ||
139 | char boardname[OCT_BOARD_NAME]; | |
140 | ||
141 | char board_serial_number[OCT_SERIAL_LEN]; | |
142 | ||
143 | u64 board_rev_major; | |
144 | ||
145 | u64 board_rev_minor; | |
146 | ||
147 | }; | |
148 | ||
149 | /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ | |
150 | ||
151 | /* The Scatter-Gather List Entry. The scatter or gather component used with | |
152 | * a Octeon input instruction has this format. | |
153 | */ | |
154 | struct octeon_sg_entry { | |
155 | /** The first 64 bit gives the size of data in each dptr.*/ | |
156 | union { | |
157 | u16 size[4]; | |
158 | u64 size64; | |
159 | } u; | |
160 | ||
161 | /** The 4 dptr pointers for this entry. */ | |
162 | u64 ptr[4]; | |
163 | ||
164 | }; | |
165 | ||
166 | #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) | |
167 | ||
168 | /* \brief Add size to gather list | |
169 | * @param sg_entry scatter/gather entry | |
170 | * @param size size to add | |
171 | * @param pos position to add it. | |
172 | */ | |
173 | static inline void add_sg_size(struct octeon_sg_entry *sg_entry, | |
174 | u16 size, | |
175 | u32 pos) | |
176 | { | |
177 | #ifdef __BIG_ENDIAN_BITFIELD | |
178 | sg_entry->u.size[pos] = size; | |
179 | #else | |
180 | sg_entry->u.size[3 - pos] = size; | |
181 | #endif | |
182 | } | |
183 | ||
184 | /*------------------------- End Scatter/Gather ---------------------------*/ | |
185 | ||
c4ee5d81 PK |
186 | #define OCTNET_FRM_LENGTH_SIZE 8 |
187 | ||
f21fb3ed | 188 | #define OCTNET_FRM_PTP_HEADER_SIZE 8 |
f21fb3ed | 189 | |
a5b37888 RV |
190 | #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ |
191 | ||
192 | #define OCTNET_MIN_FRM_SIZE 64 | |
193 | ||
f21fb3ed RV |
194 | #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) |
195 | ||
87a7c4b3 VB |
196 | #define OCTNET_DEFAULT_MTU (1500) |
197 | #define OCTNET_DEFAULT_FRM_SIZE (OCTNET_DEFAULT_MTU + OCTNET_FRM_HEADER_SIZE) | |
f21fb3ed RV |
198 | |
199 | /** NIC Commands are sent using this Octeon Input Queue */ | |
200 | #define OCTNET_CMD_Q 0 | |
201 | ||
202 | /* NIC Command types */ | |
203 | #define OCTNET_CMD_CHANGE_MTU 0x1 | |
204 | #define OCTNET_CMD_CHANGE_MACADDR 0x2 | |
205 | #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 | |
206 | #define OCTNET_CMD_RX_CTL 0x4 | |
207 | ||
208 | #define OCTNET_CMD_SET_MULTI_LIST 0x5 | |
209 | #define OCTNET_CMD_CLEAR_STATS 0x6 | |
210 | ||
211 | /* command for setting the speed, duplex & autoneg */ | |
212 | #define OCTNET_CMD_SET_SETTINGS 0x7 | |
213 | #define OCTNET_CMD_SET_FLOW_CTL 0x8 | |
214 | ||
215 | #define OCTNET_CMD_MDIO_READ_WRITE 0x9 | |
216 | #define OCTNET_CMD_GPIO_ACCESS 0xA | |
217 | #define OCTNET_CMD_LRO_ENABLE 0xB | |
218 | #define OCTNET_CMD_LRO_DISABLE 0xC | |
219 | #define OCTNET_CMD_SET_RSS 0xD | |
220 | #define OCTNET_CMD_WRITE_SA 0xE | |
221 | #define OCTNET_CMD_DELETE_SA 0xF | |
222 | #define OCTNET_CMD_UPDATE_SA 0x12 | |
223 | ||
224 | #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 | |
225 | #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 | |
226 | #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 | |
227 | #define OCTNET_CMD_VERBOSE_ENABLE 0x14 | |
228 | #define OCTNET_CMD_VERBOSE_DISABLE 0x15 | |
229 | ||
836d57e5 | 230 | #define OCTNET_CMD_VLAN_FILTER_CTL 0x16 |
63245f25 RV |
231 | #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 |
232 | #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 | |
01fb237a | 233 | #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 |
dc3abcbe RV |
234 | |
235 | #define OCTNET_CMD_ID_ACTIVE 0x1a | |
236 | ||
50f7f94b | 237 | #define OCTNET_CMD_SET_UC_LIST 0x1b |
86dea55b | 238 | #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c |
a82457f1 IB |
239 | |
240 | #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f | |
241 | ||
01fb237a RV |
242 | #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 |
243 | #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 | |
244 | #define OCTNET_CMD_RXCSUM_ENABLE 0x0 | |
245 | #define OCTNET_CMD_RXCSUM_DISABLE 0x1 | |
246 | #define OCTNET_CMD_TXCSUM_ENABLE 0x0 | |
247 | #define OCTNET_CMD_TXCSUM_DISABLE 0x1 | |
836d57e5 PK |
248 | #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1 |
249 | #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0 | |
63245f25 | 250 | |
ad530a1d VB |
251 | #define LIO_CMD_WAIT_TM 100 |
252 | ||
f21fb3ed RV |
253 | /* RX(packets coming from wire) Checksum verification flags */ |
254 | /* TCP/UDP csum */ | |
255 | #define CNNIC_L4SUM_VERIFIED 0x1 | |
256 | #define CNNIC_IPSUM_VERIFIED 0x2 | |
257 | #define CNNIC_TUN_CSUM_VERIFIED 0x4 | |
258 | #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) | |
259 | ||
260 | /*LROIPV4 and LROIPV6 Flags*/ | |
261 | #define OCTNIC_LROIPV4 0x1 | |
262 | #define OCTNIC_LROIPV6 0x2 | |
263 | ||
264 | /* Interface flags communicated between host driver and core app. */ | |
265 | enum octnet_ifflags { | |
266 | OCTNET_IFFLAG_PROMISC = 0x01, | |
267 | OCTNET_IFFLAG_ALLMULTI = 0x02, | |
268 | OCTNET_IFFLAG_MULTICAST = 0x04, | |
269 | OCTNET_IFFLAG_BROADCAST = 0x08, | |
270 | OCTNET_IFFLAG_UNICAST = 0x10 | |
271 | }; | |
272 | ||
273 | /* wqe | |
274 | * --------------- 0 | |
275 | * | wqe word0-3 | | |
276 | * --------------- 32 | |
277 | * | PCI IH | | |
278 | * --------------- 40 | |
279 | * | RPTR | | |
280 | * --------------- 48 | |
281 | * | PCI IRH | | |
282 | * --------------- 56 | |
283 | * | OCT_NET_CMD | | |
284 | * --------------- 64 | |
285 | * | Addtl 8-BData | | |
286 | * | | | |
287 | * --------------- | |
288 | */ | |
289 | ||
290 | union octnet_cmd { | |
291 | u64 u64; | |
292 | ||
293 | struct { | |
294 | #ifdef __BIG_ENDIAN_BITFIELD | |
295 | u64 cmd:5; | |
296 | ||
297 | u64 more:6; /* How many udd words follow the command */ | |
298 | ||
0cece6c5 | 299 | u64 reserved:29; |
f21fb3ed | 300 | |
0cece6c5 | 301 | u64 param1:16; |
f21fb3ed | 302 | |
0cece6c5 | 303 | u64 param2:8; |
f21fb3ed RV |
304 | |
305 | #else | |
306 | ||
0cece6c5 | 307 | u64 param2:8; |
f21fb3ed | 308 | |
0cece6c5 | 309 | u64 param1:16; |
f21fb3ed | 310 | |
0cece6c5 | 311 | u64 reserved:29; |
f21fb3ed RV |
312 | |
313 | u64 more:6; | |
314 | ||
315 | u64 cmd:5; | |
316 | ||
317 | #endif | |
318 | } s; | |
319 | ||
320 | }; | |
321 | ||
322 | #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) | |
323 | ||
5b823514 RV |
324 | /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ |
325 | #define LIO_SOFTCMDRESP_IH2 40 | |
326 | #define LIO_SOFTCMDRESP_IH3 (40 + 8) | |
327 | ||
328 | #define LIO_PCICMD_O2 24 | |
329 | #define LIO_PCICMD_O3 (24 + 8) | |
330 | ||
a2c64b67 | 331 | /* Instruction Header(DPI) - for OCTEON-III models */ |
6a885b60 RV |
332 | struct octeon_instr_ih3 { |
333 | #ifdef __BIG_ENDIAN_BITFIELD | |
334 | ||
335 | /** Reserved3 */ | |
336 | u64 reserved3:1; | |
337 | ||
338 | /** Gather indicator 1=gather*/ | |
339 | u64 gather:1; | |
340 | ||
341 | /** Data length OR no. of entries in gather list */ | |
342 | u64 dlengsz:14; | |
343 | ||
344 | /** Front Data size */ | |
345 | u64 fsz:6; | |
346 | ||
347 | /** Reserved2 */ | |
348 | u64 reserved2:4; | |
349 | ||
350 | /** PKI port kind - PKIND */ | |
351 | u64 pkind:6; | |
352 | ||
353 | /** Reserved1 */ | |
354 | u64 reserved1:32; | |
355 | ||
356 | #else | |
357 | /** Reserved1 */ | |
358 | u64 reserved1:32; | |
359 | ||
360 | /** PKI port kind - PKIND */ | |
361 | u64 pkind:6; | |
362 | ||
363 | /** Reserved2 */ | |
364 | u64 reserved2:4; | |
365 | ||
366 | /** Front Data size */ | |
367 | u64 fsz:6; | |
368 | ||
369 | /** Data length OR no. of entries in gather list */ | |
370 | u64 dlengsz:14; | |
371 | ||
372 | /** Gather indicator 1=gather*/ | |
373 | u64 gather:1; | |
374 | ||
375 | /** Reserved3 */ | |
376 | u64 reserved3:1; | |
377 | ||
378 | #endif | |
379 | }; | |
380 | ||
a2c64b67 | 381 | /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ |
6a885b60 RV |
382 | /** BIG ENDIAN format. */ |
383 | struct octeon_instr_pki_ih3 { | |
384 | #ifdef __BIG_ENDIAN_BITFIELD | |
385 | ||
386 | /** Wider bit */ | |
387 | u64 w:1; | |
388 | ||
389 | /** Raw mode indicator 1 = RAW */ | |
390 | u64 raw:1; | |
391 | ||
392 | /** Use Tag */ | |
393 | u64 utag:1; | |
394 | ||
395 | /** Use QPG */ | |
396 | u64 uqpg:1; | |
397 | ||
398 | /** Reserved2 */ | |
399 | u64 reserved2:1; | |
400 | ||
401 | /** Parse Mode */ | |
402 | u64 pm:3; | |
403 | ||
404 | /** Skip Length */ | |
405 | u64 sl:8; | |
406 | ||
407 | /** Use Tag Type */ | |
408 | u64 utt:1; | |
409 | ||
410 | /** Tag type */ | |
411 | u64 tagtype:2; | |
412 | ||
413 | /** Reserved1 */ | |
414 | u64 reserved1:2; | |
415 | ||
416 | /** QPG Value */ | |
417 | u64 qpg:11; | |
418 | ||
419 | /** Tag Value */ | |
420 | u64 tag:32; | |
421 | ||
422 | #else | |
423 | ||
424 | /** Tag Value */ | |
425 | u64 tag:32; | |
426 | ||
427 | /** QPG Value */ | |
428 | u64 qpg:11; | |
429 | ||
430 | /** Reserved1 */ | |
431 | u64 reserved1:2; | |
432 | ||
433 | /** Tag type */ | |
434 | u64 tagtype:2; | |
435 | ||
436 | /** Use Tag Type */ | |
437 | u64 utt:1; | |
438 | ||
439 | /** Skip Length */ | |
440 | u64 sl:8; | |
441 | ||
442 | /** Parse Mode */ | |
443 | u64 pm:3; | |
444 | ||
445 | /** Reserved2 */ | |
446 | u64 reserved2:1; | |
447 | ||
448 | /** Use QPG */ | |
449 | u64 uqpg:1; | |
450 | ||
451 | /** Use Tag */ | |
452 | u64 utag:1; | |
453 | ||
454 | /** Raw mode indicator 1 = RAW */ | |
455 | u64 raw:1; | |
456 | ||
457 | /** Wider bit */ | |
458 | u64 w:1; | |
459 | #endif | |
460 | ||
461 | }; | |
462 | ||
f21fb3ed | 463 | /** Instruction Header */ |
6a885b60 | 464 | struct octeon_instr_ih2 { |
f21fb3ed RV |
465 | #ifdef __BIG_ENDIAN_BITFIELD |
466 | /** Raw mode indicator 1 = RAW */ | |
467 | u64 raw:1; | |
468 | ||
469 | /** Gather indicator 1=gather*/ | |
470 | u64 gather:1; | |
471 | ||
472 | /** Data length OR no. of entries in gather list */ | |
473 | u64 dlengsz:14; | |
474 | ||
475 | /** Front Data size */ | |
476 | u64 fsz:6; | |
477 | ||
478 | /** Packet Order / Work Unit selection (1 of 8)*/ | |
479 | u64 qos:3; | |
480 | ||
481 | /** Core group selection (1 of 16) */ | |
482 | u64 grp:4; | |
483 | ||
484 | /** Short Raw Packet Indicator 1=short raw pkt */ | |
485 | u64 rs:1; | |
486 | ||
487 | /** Tag type */ | |
488 | u64 tagtype:2; | |
489 | ||
490 | /** Tag Value */ | |
491 | u64 tag:32; | |
492 | #else | |
493 | /** Tag Value */ | |
494 | u64 tag:32; | |
495 | ||
496 | /** Tag type */ | |
497 | u64 tagtype:2; | |
498 | ||
499 | /** Short Raw Packet Indicator 1=short raw pkt */ | |
500 | u64 rs:1; | |
501 | ||
502 | /** Core group selection (1 of 16) */ | |
503 | u64 grp:4; | |
504 | ||
505 | /** Packet Order / Work Unit selection (1 of 8)*/ | |
506 | u64 qos:3; | |
507 | ||
508 | /** Front Data size */ | |
509 | u64 fsz:6; | |
510 | ||
511 | /** Data length OR no. of entries in gather list */ | |
512 | u64 dlengsz:14; | |
513 | ||
514 | /** Gather indicator 1=gather*/ | |
515 | u64 gather:1; | |
516 | ||
517 | /** Raw mode indicator 1 = RAW */ | |
518 | u64 raw:1; | |
519 | #endif | |
520 | }; | |
521 | ||
522 | /** Input Request Header */ | |
523 | struct octeon_instr_irh { | |
524 | #ifdef __BIG_ENDIAN_BITFIELD | |
525 | u64 opcode:4; | |
526 | u64 rflag:1; | |
527 | u64 subcode:7; | |
0da0b77c RV |
528 | u64 vlan:12; |
529 | u64 priority:3; | |
530 | u64 reserved:5; | |
f21fb3ed RV |
531 | u64 ossp:32; /* opcode/subcode specific parameters */ |
532 | #else | |
533 | u64 ossp:32; /* opcode/subcode specific parameters */ | |
0da0b77c RV |
534 | u64 reserved:5; |
535 | u64 priority:3; | |
536 | u64 vlan:12; | |
f21fb3ed RV |
537 | u64 subcode:7; |
538 | u64 rflag:1; | |
539 | u64 opcode:4; | |
540 | #endif | |
541 | }; | |
542 | ||
543 | /** Return Data Parameters */ | |
544 | struct octeon_instr_rdp { | |
545 | #ifdef __BIG_ENDIAN_BITFIELD | |
546 | u64 reserved:49; | |
547 | u64 pcie_port:3; | |
548 | u64 rlen:12; | |
549 | #else | |
550 | u64 rlen:12; | |
551 | u64 pcie_port:3; | |
552 | u64 reserved:49; | |
553 | #endif | |
554 | }; | |
555 | ||
556 | /** Receive Header */ | |
557 | union octeon_rh { | |
558 | #ifdef __BIG_ENDIAN_BITFIELD | |
559 | u64 u64; | |
560 | struct { | |
561 | u64 opcode:4; | |
562 | u64 subcode:8; | |
0da0b77c RV |
563 | u64 len:3; /** additional 64-bit words */ |
564 | u64 reserved:17; | |
565 | u64 ossp:32; /** opcode/subcode specific parameters */ | |
f21fb3ed RV |
566 | } r; |
567 | struct { | |
568 | u64 opcode:4; | |
569 | u64 subcode:8; | |
0da0b77c RV |
570 | u64 len:3; /** additional 64-bit words */ |
571 | u64 extra:28; | |
572 | u64 vlan:12; | |
573 | u64 priority:3; | |
f21fb3ed RV |
574 | u64 csum_verified:3; /** checksum verified. */ |
575 | u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ | |
01fb237a | 576 | u64 encap_on:1; |
9fbc48f6 | 577 | u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ |
f21fb3ed RV |
578 | } r_dh; |
579 | struct { | |
580 | u64 opcode:4; | |
581 | u64 subcode:8; | |
0da0b77c RV |
582 | u64 len:3; /** additional 64-bit words */ |
583 | u64 reserved:11; | |
f21fb3ed | 584 | u64 num_gmx_ports:8; |
0da0b77c | 585 | u64 max_nic_ports:10; |
f21fb3ed | 586 | u64 app_cap_flags:4; |
9fbc48f6 RV |
587 | u64 app_mode:8; |
588 | u64 pkind:8; | |
f21fb3ed RV |
589 | } r_core_drv_init; |
590 | struct { | |
591 | u64 opcode:4; | |
592 | u64 subcode:8; | |
593 | u64 len:3; /** additional 64-bit words */ | |
0cece6c5 | 594 | u64 reserved:8; |
f21fb3ed | 595 | u64 extra:25; |
0cece6c5 | 596 | u64 gmxport:16; |
f21fb3ed RV |
597 | } r_nic_info; |
598 | #else | |
599 | u64 u64; | |
600 | struct { | |
601 | u64 ossp:32; /** opcode/subcode specific parameters */ | |
0da0b77c | 602 | u64 reserved:17; |
f21fb3ed RV |
603 | u64 len:3; /** additional 64-bit words */ |
604 | u64 subcode:8; | |
605 | u64 opcode:4; | |
606 | } r; | |
607 | struct { | |
9fbc48f6 | 608 | u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ |
01fb237a | 609 | u64 encap_on:1; |
f21fb3ed RV |
610 | u64 has_hwtstamp:1; /** 1 = has hwtstamp */ |
611 | u64 csum_verified:3; /** checksum verified. */ | |
0da0b77c RV |
612 | u64 priority:3; |
613 | u64 vlan:12; | |
614 | u64 extra:28; | |
f21fb3ed RV |
615 | u64 len:3; /** additional 64-bit words */ |
616 | u64 subcode:8; | |
617 | u64 opcode:4; | |
618 | } r_dh; | |
619 | struct { | |
9fbc48f6 RV |
620 | u64 pkind:8; |
621 | u64 app_mode:8; | |
f21fb3ed | 622 | u64 app_cap_flags:4; |
0da0b77c | 623 | u64 max_nic_ports:10; |
f21fb3ed | 624 | u64 num_gmx_ports:8; |
0da0b77c | 625 | u64 reserved:11; |
f21fb3ed RV |
626 | u64 len:3; /** additional 64-bit words */ |
627 | u64 subcode:8; | |
628 | u64 opcode:4; | |
629 | } r_core_drv_init; | |
630 | struct { | |
0cece6c5 | 631 | u64 gmxport:16; |
f21fb3ed | 632 | u64 extra:25; |
0cece6c5 | 633 | u64 reserved:8; |
f21fb3ed RV |
634 | u64 len:3; /** additional 64-bit words */ |
635 | u64 subcode:8; | |
636 | u64 opcode:4; | |
637 | } r_nic_info; | |
638 | #endif | |
639 | }; | |
640 | ||
641 | #define OCT_RH_SIZE (sizeof(union octeon_rh)) | |
642 | ||
f21fb3ed RV |
643 | union octnic_packet_params { |
644 | u32 u32; | |
645 | struct { | |
646 | #ifdef __BIG_ENDIAN_BITFIELD | |
0cece6c5 | 647 | u32 reserved:24; |
7275ebfc RV |
648 | u32 ip_csum:1; /* Perform IP header checksum(s) */ |
649 | /* Perform Outer transport header checksum */ | |
650 | u32 transport_csum:1; | |
651 | /* Find tunnel, and perform transport csum. */ | |
f21fb3ed | 652 | u32 tnl_csum:1; |
7275ebfc RV |
653 | u32 tsflag:1; /* Timestamp this packet */ |
654 | u32 ipsec_ops:4; /* IPsec operation */ | |
f21fb3ed | 655 | #else |
f21fb3ed | 656 | u32 ipsec_ops:4; |
7275ebfc | 657 | u32 tsflag:1; |
f21fb3ed | 658 | u32 tnl_csum:1; |
7275ebfc RV |
659 | u32 transport_csum:1; |
660 | u32 ip_csum:1; | |
0cece6c5 | 661 | u32 reserved:24; |
f21fb3ed RV |
662 | #endif |
663 | } s; | |
664 | }; | |
665 | ||
666 | /** Status of a RGMII Link on Octeon as seen by core driver. */ | |
667 | union oct_link_status { | |
668 | u64 u64; | |
669 | ||
670 | struct { | |
671 | #ifdef __BIG_ENDIAN_BITFIELD | |
672 | u64 duplex:8; | |
f21fb3ed RV |
673 | u64 mtu:16; |
674 | u64 speed:16; | |
0cece6c5 | 675 | u64 link_up:1; |
f21fb3ed | 676 | u64 autoneg:1; |
9eb60844 | 677 | u64 if_mode:5; |
f21fb3ed | 678 | u64 pause:1; |
9fbc48f6 | 679 | u64 flashing:1; |
5677629a VB |
680 | u64 phy_type:5; |
681 | u64 reserved:10; | |
f21fb3ed | 682 | #else |
5677629a VB |
683 | u64 reserved:10; |
684 | u64 phy_type:5; | |
9fbc48f6 | 685 | u64 flashing:1; |
f21fb3ed | 686 | u64 pause:1; |
9eb60844 | 687 | u64 if_mode:5; |
f21fb3ed | 688 | u64 autoneg:1; |
0cece6c5 | 689 | u64 link_up:1; |
f21fb3ed RV |
690 | u64 speed:16; |
691 | u64 mtu:16; | |
f21fb3ed RV |
692 | u64 duplex:8; |
693 | #endif | |
694 | } s; | |
695 | }; | |
696 | ||
5677629a VB |
697 | enum lio_phy_type { |
698 | LIO_PHY_PORT_TP = 0x0, | |
699 | LIO_PHY_PORT_FIBRE = 0x1, | |
700 | LIO_PHY_PORT_UNKNOWN, | |
701 | }; | |
702 | ||
26236fa9 RV |
703 | /** The txpciq info passed to host from the firmware */ |
704 | ||
705 | union oct_txpciq { | |
706 | u64 u64; | |
707 | ||
708 | struct { | |
709 | #ifdef __BIG_ENDIAN_BITFIELD | |
710 | u64 q_no:8; | |
711 | u64 port:8; | |
712 | u64 pkind:6; | |
713 | u64 use_qpg:1; | |
714 | u64 qpg:11; | |
697fefc7 IB |
715 | u64 reserved0:10; |
716 | u64 ctrl_qpg:11; | |
717 | u64 reserved:9; | |
26236fa9 | 718 | #else |
697fefc7 IB |
719 | u64 reserved:9; |
720 | u64 ctrl_qpg:11; | |
721 | u64 reserved0:10; | |
26236fa9 RV |
722 | u64 qpg:11; |
723 | u64 use_qpg:1; | |
724 | u64 pkind:6; | |
725 | u64 port:8; | |
726 | u64 q_no:8; | |
727 | #endif | |
728 | } s; | |
729 | }; | |
730 | ||
731 | /** The rxpciq info passed to host from the firmware */ | |
732 | ||
733 | union oct_rxpciq { | |
734 | u64 u64; | |
735 | ||
736 | struct { | |
737 | #ifdef __BIG_ENDIAN_BITFIELD | |
738 | u64 q_no:8; | |
739 | u64 reserved:56; | |
740 | #else | |
741 | u64 reserved:56; | |
742 | u64 q_no:8; | |
743 | #endif | |
744 | } s; | |
745 | }; | |
746 | ||
f21fb3ed RV |
747 | /** Information for a OCTEON ethernet interface shared between core & host. */ |
748 | struct oct_link_info { | |
749 | union oct_link_status link; | |
750 | u64 hw_addr; | |
751 | ||
752 | #ifdef __BIG_ENDIAN_BITFIELD | |
0cece6c5 | 753 | u64 gmxport:16; |
8c978d05 RV |
754 | u64 macaddr_is_admin_asgnd:1; |
755 | u64 rsvd:31; | |
0cece6c5 RV |
756 | u64 num_txpciq:8; |
757 | u64 num_rxpciq:8; | |
f21fb3ed | 758 | #else |
0cece6c5 RV |
759 | u64 num_rxpciq:8; |
760 | u64 num_txpciq:8; | |
8c978d05 RV |
761 | u64 rsvd:31; |
762 | u64 macaddr_is_admin_asgnd:1; | |
0cece6c5 | 763 | u64 gmxport:16; |
f21fb3ed RV |
764 | #endif |
765 | ||
26236fa9 RV |
766 | union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; |
767 | union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; | |
f21fb3ed RV |
768 | }; |
769 | ||
770 | #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) | |
771 | ||
772 | struct liquidio_if_cfg_info { | |
f21fb3ed RV |
773 | u64 iqmask; /** mask for IQs enabled for the port */ |
774 | u64 oqmask; /** mask for OQs enabled for the port */ | |
775 | struct oct_link_info linfo; /** initial link information */ | |
d3d7e6c6 | 776 | char liquidio_firmware_version[32]; |
f21fb3ed RV |
777 | }; |
778 | ||
779 | /** Stats for each NIC port in RX direction. */ | |
780 | struct nic_rx_stats { | |
781 | /* link-level stats */ | |
782 | u64 total_rcvd; | |
783 | u64 bytes_rcvd; | |
784 | u64 total_bcst; | |
785 | u64 total_mcst; | |
786 | u64 runts; | |
787 | u64 ctl_rcvd; | |
788 | u64 fifo_err; /* Accounts for over/under-run of buffers */ | |
789 | u64 dmac_drop; | |
790 | u64 fcs_err; | |
791 | u64 jabber_err; | |
792 | u64 l2_err; | |
793 | u64 frame_err; | |
794 | ||
795 | /* firmware stats */ | |
796 | u64 fw_total_rcvd; | |
797 | u64 fw_total_fwd; | |
a847135a | 798 | u64 fw_total_fwd_bytes; |
f21fb3ed RV |
799 | u64 fw_err_pko; |
800 | u64 fw_err_link; | |
801 | u64 fw_err_drop; | |
01fb237a RV |
802 | u64 fw_rx_vxlan; |
803 | u64 fw_rx_vxlan_err; | |
1f164717 RV |
804 | |
805 | /* LRO */ | |
f21fb3ed RV |
806 | u64 fw_lro_pkts; /* Number of packets that are LROed */ |
807 | u64 fw_lro_octs; /* Number of octets that are LROed */ | |
808 | u64 fw_total_lro; /* Number of LRO packets formed */ | |
809 | u64 fw_lro_aborts; /* Number of times lRO of packet aborted */ | |
1f164717 RV |
810 | u64 fw_lro_aborts_port; |
811 | u64 fw_lro_aborts_seq; | |
812 | u64 fw_lro_aborts_tsval; | |
813 | u64 fw_lro_aborts_timer; | |
f21fb3ed RV |
814 | /* intrmod: packet forward rate */ |
815 | u64 fwd_rate; | |
816 | }; | |
817 | ||
818 | /** Stats for each NIC port in RX direction. */ | |
819 | struct nic_tx_stats { | |
820 | /* link-level stats */ | |
821 | u64 total_pkts_sent; | |
822 | u64 total_bytes_sent; | |
823 | u64 mcast_pkts_sent; | |
824 | u64 bcast_pkts_sent; | |
825 | u64 ctl_sent; | |
826 | u64 one_collision_sent; /* Packets sent after one collision*/ | |
827 | u64 multi_collision_sent; /* Packets sent after multiple collision*/ | |
828 | u64 max_collision_fail; /* Packets not sent due to max collisions */ | |
829 | u64 max_deferral_fail; /* Packets not sent due to max deferrals */ | |
830 | u64 fifo_err; /* Accounts for over/under-run of buffers */ | |
831 | u64 runts; | |
832 | u64 total_collisions; /* Total number of collisions detected */ | |
833 | ||
834 | /* firmware stats */ | |
835 | u64 fw_total_sent; | |
836 | u64 fw_total_fwd; | |
1f164717 | 837 | u64 fw_total_fwd_bytes; |
f21fb3ed RV |
838 | u64 fw_err_pko; |
839 | u64 fw_err_link; | |
840 | u64 fw_err_drop; | |
1f164717 RV |
841 | u64 fw_err_tso; |
842 | u64 fw_tso; /* number of tso requests */ | |
843 | u64 fw_tso_fwd; /* number of packets segmented in tso */ | |
01fb237a | 844 | u64 fw_tx_vxlan; |
741912c5 | 845 | u64 fw_err_pki; |
f21fb3ed RV |
846 | }; |
847 | ||
848 | struct oct_link_stats { | |
849 | struct nic_rx_stats fromwire; | |
850 | struct nic_tx_stats fromhost; | |
851 | ||
852 | }; | |
853 | ||
97a25326 RV |
854 | static inline int opcode_slow_path(union octeon_rh *rh) |
855 | { | |
856 | u16 subcode1, subcode2; | |
857 | ||
858 | subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); | |
859 | subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); | |
860 | ||
861 | return (subcode2 != subcode1); | |
862 | } | |
863 | ||
f21fb3ed RV |
864 | #define LIO68XX_LED_CTRL_ADDR 0x3501 |
865 | #define LIO68XX_LED_CTRL_CFGON 0x1f | |
866 | #define LIO68XX_LED_CTRL_CFGOFF 0x100 | |
867 | #define LIO68XX_LED_BEACON_ADDR 0x3508 | |
868 | #define LIO68XX_LED_BEACON_CFGON 0x47fd | |
869 | #define LIO68XX_LED_BEACON_CFGOFF 0x11fc | |
870 | #define VITESSE_PHY_GPIO_DRIVEON 0x1 | |
871 | #define VITESSE_PHY_GPIO_CFG 0x8 | |
872 | #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 | |
873 | #define VITESSE_PHY_GPIO_HIGH 0x2 | |
874 | #define VITESSE_PHY_GPIO_LOW 0x3 | |
dc3abcbe RV |
875 | #define LED_IDENTIFICATION_ON 0x1 |
876 | #define LED_IDENTIFICATION_OFF 0x0 | |
f21fb3ed RV |
877 | |
878 | struct oct_mdio_cmd { | |
879 | u64 op; | |
880 | u64 mdio_addr; | |
881 | u64 value1; | |
882 | u64 value2; | |
883 | u64 value3; | |
884 | }; | |
885 | ||
886 | #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) | |
887 | ||
f21fb3ed | 888 | struct oct_intrmod_cfg { |
78e6a9b4 RV |
889 | u64 rx_enable; |
890 | u64 tx_enable; | |
891 | u64 check_intrvl; | |
892 | u64 maxpkt_ratethr; | |
893 | u64 minpkt_ratethr; | |
894 | u64 rx_maxcnt_trigger; | |
895 | u64 rx_mincnt_trigger; | |
896 | u64 rx_maxtmr_trigger; | |
897 | u64 rx_mintmr_trigger; | |
898 | u64 tx_mincnt_trigger; | |
899 | u64 tx_maxcnt_trigger; | |
900 | u64 rx_frames; | |
901 | u64 tx_frames; | |
902 | u64 rx_usecs; | |
f21fb3ed RV |
903 | }; |
904 | ||
905 | #define BASE_QUEUE_NOT_REQUESTED 65535 | |
906 | ||
907 | union oct_nic_if_cfg { | |
908 | u64 u64; | |
909 | struct { | |
910 | #ifdef __BIG_ENDIAN_BITFIELD | |
911 | u64 base_queue:16; | |
912 | u64 num_iqueues:16; | |
913 | u64 num_oqueues:16; | |
914 | u64 gmx_port_id:8; | |
9fbc48f6 | 915 | u64 vf_id:8; |
f21fb3ed | 916 | #else |
9fbc48f6 | 917 | u64 vf_id:8; |
f21fb3ed RV |
918 | u64 gmx_port_id:8; |
919 | u64 num_oqueues:16; | |
920 | u64 num_iqueues:16; | |
921 | u64 base_queue:16; | |
922 | #endif | |
923 | } s; | |
924 | }; | |
925 | ||
f2d254fa IB |
926 | struct lio_trusted_vf { |
927 | uint64_t active: 1; | |
928 | uint64_t id : 8; | |
929 | uint64_t reserved: 55; | |
930 | }; | |
931 | ||
907aaa6b VB |
932 | struct lio_time { |
933 | s64 sec; /* seconds */ | |
934 | s64 nsec; /* nanoseconds */ | |
935 | }; | |
1f233f32 VMG |
936 | |
937 | struct lio_vf_rep_stats { | |
938 | u64 tx_packets; | |
939 | u64 tx_bytes; | |
940 | u64 tx_dropped; | |
941 | ||
942 | u64 rx_packets; | |
943 | u64 rx_bytes; | |
944 | u64 rx_dropped; | |
945 | }; | |
946 | ||
947 | enum lio_vf_rep_req_type { | |
948 | LIO_VF_REP_REQ_NONE, | |
949 | LIO_VF_REP_REQ_STATE, | |
950 | LIO_VF_REP_REQ_MTU, | |
e20f4696 VMG |
951 | LIO_VF_REP_REQ_STATS, |
952 | LIO_VF_REP_REQ_DEVNAME | |
1f233f32 VMG |
953 | }; |
954 | ||
955 | enum { | |
956 | LIO_VF_REP_STATE_DOWN, | |
957 | LIO_VF_REP_STATE_UP | |
958 | }; | |
959 | ||
e20f4696 | 960 | #define LIO_IF_NAME_SIZE 16 |
1f233f32 VMG |
961 | struct lio_vf_rep_req { |
962 | u8 req_type; | |
963 | u8 ifidx; | |
964 | u8 rsvd[6]; | |
965 | ||
966 | union { | |
e20f4696 VMG |
967 | struct lio_vf_rep_name { |
968 | char name[LIO_IF_NAME_SIZE]; | |
969 | } rep_name; | |
970 | ||
1f233f32 VMG |
971 | struct lio_vf_rep_mtu { |
972 | u32 mtu; | |
973 | u32 rsvd; | |
974 | } rep_mtu; | |
975 | ||
976 | struct lio_vf_rep_state { | |
977 | u8 state; | |
978 | u8 rsvd[7]; | |
979 | } rep_state; | |
980 | }; | |
981 | }; | |
982 | ||
983 | struct lio_vf_rep_resp { | |
984 | u64 rh; | |
985 | u8 status; | |
986 | u8 rsvd[7]; | |
987 | }; | |
f21fb3ed | 988 | #endif |